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* config/tc-m68k.c (md_section_align): If a.out and BFD, force
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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a1c7c0f3 1/* tc-m68k.c -- Assemble for the m68k family
b4d51f3d
ILT		 2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
6d27d3a2 4
a39116f1 5 This file is part of GAS, the GNU Assembler.
6d27d3a2 6
a39116f1
RP		 7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
6d27d3a2 11
a39116f1
RP		 12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
6d27d3a2 16
a39116f1 17 You should have received a copy of the GNU General Public License
a1c7c0f3
ILT		 18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
fecd2382
RP		 21
22#include <ctype.h>
fecd2382 23#include "as.h"
fecd2382 24#include "obstack.h"
b4ec75e0 25#include "subsegs.h"
fecd2382 26
e0982afe 27#include "opcode/m68k.h"
a1c7c0f3 28#include "m68k-parse.h"
3ad9ec6a 29
8d20a0a8
C		 30/* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
fee3e248 34#if defined (TE_SVR4) || defined (TE_DELTA)
8d20a0a8 35const char *m68k_comment_chars = "|#";
5f8cb05e 36#else
8d20a0a8 37const char *m68k_comment_chars = "|";
5f8cb05e 38#endif
fecd2382
RP		 39
40/* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43/* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46/* Also note that comments like this one will always work. */
590c50d8 47const char line_comment_chars[] = "#*";
fecd2382 48
326b087c 49const char line_separator_chars[] = "";
587c4264 50
fecd2382 51/* Chars that can be used to separate mant from exp in floating point nums */
49864cfa 52CONST char EXP_CHARS[] = "eE";
fecd2382 53
49864cfa
KR		 54/* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
fecd2382 56
49864cfa 57CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
fecd2382
RP		 58
59/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
49864cfa 61 but nothing is ideal around here. */
fecd2382 62
49864cfa 63const int md_reloc_size = 8; /* Size of relocation record */
fecd2382 64
b80d39a0 65/* Are we trying to generate PIC code? If so, absolute references
dff60b7d 66 ought to be made into linkage table references or pc-relative
a043f579
ILT		 67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
b80d39a0
KR		 69int flag_want_pic;
70
9ad5755f
KR		 71static int flag_short_refs; /* -l option */
72static int flag_long_jumps; /* -S option */
73
82489ea0
KR		 74#ifdef REGISTER_PREFIX_OPTIONAL
75int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76#else
77int flag_reg_prefix_optional;
78#endif
79
20710f1c
ILT		 80/* Whether --register-prefix-optional was used on the command line. */
81static int reg_prefix_optional_seen;
82
27a53b88
ILT		 83/* The floating point coprocessor to use by default. */
84static enum m68k_register m68k_float_copnum = COP1;
85
6700d36e
ILT		 86/* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88static int m68k_abspcadd;
89
90/* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92static int m68k_quick = 1;
93
94/* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97static int m68k_rel32 = 1;
98
924160b0
ILT		 99/* This is non-zero if m68k_rel32 was set from the command line. */
100static int m68k_rel32_from_cmdline;
101
b4d51f3d
ILT		 102/* The default width to use for an index register when using a base
103 displacement. */
104static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
d703b5a7
ILT		 106/* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110struct label_line
111{
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117};
118
119/* The list of labels. */
120
121static struct label_line *labels;
122
123/* The current label. */
124
125static struct label_line *current_label;
126
fecd2382
RP		 127/* Its an arbitrary name: This means I don't approve of it */
128/* See flames below */
129static struct obstack robyn;
130
131#define TAB(x,y) (((x)<<2)+(y))
132#define TABTYPE(xy) ((xy) >> 2)
133#define BYTE 0
134#define SHORT 1
135#define LONG 2
136#define SZ_UNDEF 3
3ad9ec6a 137#undef BRANCH
04ef74bb 138/* Case `g' except when BCC68000 is applicable. */
3ad9ec6a 139#define ABRANCH 1
04ef74bb 140/* Coprocessor branches. */
fecd2382 141#define FBRANCH 2
04ef74bb
KR		 142/* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
fecd2382 144#define PCREL 3
04ef74bb
KR		 145/* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
fecd2382 150#define BCC68000 4
04ef74bb
KR		 151/* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
fecd2382 153#define DBCC 5
04ef74bb 154/* Not currently used? */
fecd2382 155#define PCLEA 6
04ef74bb
KR		 156/* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158#define PCINDEX 7
fecd2382 159
bcb8dff8
KR		 160struct m68k_incant
161 {
a1c7c0f3 162 const char *m_operands;
bcb8dff8
KR		 163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171#define gettwo(x) (((x)->m_opcode)&0xffff)
172
a1c7c0f3
ILT		 173static const enum m68k_register m68000_control_regs[] = { 0 };
174static const enum m68k_register m68010_control_regs[] = {
82489ea0
KR		 175 SFC, DFC, USP, VBR,
176 0
177};
a1c7c0f3 178static const enum m68k_register m68020_control_regs[] = {
82489ea0
KR		 179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181};
a1c7c0f3 182static const enum m68k_register m68040_control_regs[] = {
82489ea0
KR		 183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186};
a1c7c0f3 187static const enum m68k_register m68060_control_regs[] = {
82489ea0
KR		 188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191};
8d20a0a8
C		 192static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196};
b79de3a1 197#define cpu32_control_regs m68010_control_regs
82489ea0 198
a1c7c0f3 199static const enum m68k_register *control_regs;
fecd2382
RP		 200
201/* internal form of a 68020 instruction */
355afbcd 202struct m68k_it
a1c7c0f3
ILT		 203{
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
355afbcd 207
a1c7c0f3
ILT		 208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
355afbcd 210
a1c7c0f3 211 struct m68k_op operands[6];
355afbcd 212
a1c7c0f3
ILT		 213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
355afbcd 215
a1c7c0f3
ILT		 216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
f59fb6ca 221 offsetT foff;
a1c7c0f3
ILT		 222 int fragty;
223 }
224 fragb[4];
355afbcd 225
a1c7c0f3
ILT		 226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
a043f579
ILT		 241#ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245#endif
a1c7c0f3
ILT		 246 }
247 reloc[5]; /* Five is enough??? */
248};
fecd2382 249
8d20a0a8 250#define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
865a2edf
MT		 251#define float_of_arch(x) ((x) & mfloat)
252#define mmu_of_arch(x) ((x) & mmmu)
253
ffecfc8b
C		 254/* Macros for determining if cpu supports a specific addressing mode */
255#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
256
355afbcd 257static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 258
a1c7c0f3
ILT		 259#define op(ex) ((ex)->exp.X_op)
260#define adds(ex) ((ex)->exp.X_add_symbol)
261#define subs(ex) ((ex)->exp.X_op_symbol)
262#define offs(ex) ((ex)->exp.X_add_number)
49864cfa 263
7c15cbe8 264/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 265
266#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
267
f59fb6ca
ILT		 268/* Static functions. */
269
270static void insop PARAMS ((int, struct m68k_incant *));
271static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
272static void add_frag PARAMS ((symbolS *, offsetT, int));
273
fecd2382 274/* Like addword, but goes BEFORE general operands */
bcb8dff8
KR		 275static void
276insop (w, opcode)
277 int w;
278 struct m68k_incant *opcode;
279{
280 int z;
281 for(z=the_ins.numo;z>opcode->m_codenum;--z)
282 the_ins.opcode[z]=the_ins.opcode[z-1];
283 for(z=0;z<the_ins.nrel;z++)
284 the_ins.reloc[z].n+=2;
5f8cb05e
ILT		 285 for (z = 0; z < the_ins.nfrag; z++)
286 the_ins.fragb[z].fragoff++;
bcb8dff8
KR		 287 the_ins.opcode[opcode->m_codenum]=w;
288 the_ins.numo++;
289}
fecd2382 290
1404ef23
KR		 291/* The numo+1 kludge is so we can hit the low order byte of the prev word.
292 Blecch. */
49864cfa 293static void
5f8cb05e 294add_fix (width, exp, pc_rel, pc_fix)
f59fb6ca 295 int width;
49864cfa
KR		 296 struct m68k_exp *exp;
297 int pc_rel;
5f8cb05e 298 int pc_fix;
49864cfa 299{
0b810a6e 300 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
49864cfa
KR		 301 ? (the_ins.numo*2-1)
302 : (((width)=='b')
5f8cb05e 303 ? (the_ins.numo*2+1)
49864cfa 304 : (the_ins.numo*2)));
a1c7c0f3 305 the_ins.reloc[the_ins.nrel].exp = exp->exp;
49864cfa 306 the_ins.reloc[the_ins.nrel].wid = width;
5f8cb05e 307 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
a043f579
ILT		 308#ifdef OBJ_ELF
309 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
310#endif
49864cfa 311 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
1404ef23
KR		 312}
313
5f8cb05e
ILT		 314/* Cause an extra frag to be generated here, inserting up to 10 bytes
315 (that value is chosen in the frag_var call in md_assemble). TYPE
316 is the subtype of the frag to be generated; its primary type is
317 rs_machine_dependent.
318
319 The TYPE parameter is also used by md_convert_frag_1 and
320 md_estimate_size_before_relax. The appropriate type of fixup will
321 be emitted by md_convert_frag_1.
322
323 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
49864cfa 324static void
f59fb6ca 325add_frag (add, off, type)
49864cfa 326 symbolS *add;
f59fb6ca 327 offsetT off;
49864cfa
KR		 328 int type;
329{
330 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
331 the_ins.fragb[the_ins.nfrag].fadd=add;
332 the_ins.fragb[the_ins.nfrag].foff=off;
333 the_ins.fragb[the_ins.nfrag++].fragty=type;
1404ef23 334}
fecd2382 335
a1c7c0f3
ILT		 336#define isvar(ex) \
337 (op (ex) != O_constant && op (ex) != O_big)
fecd2382 338
49864cfa
KR		 339static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
340static int get_num PARAMS ((struct m68k_exp *exp, int ok));
f59fb6ca
ILT		 341static void m68k_ip PARAMS ((char *));
342static void insert_reg PARAMS ((const char *, int));
343static void select_control_regs PARAMS ((void));
344static void init_regtable PARAMS ((void));
49864cfa
KR		 345static int reverse_16_bits PARAMS ((int in));
346static int reverse_8_bits PARAMS ((int in));
49864cfa
KR		 347static void install_gen_operand PARAMS ((int mode, int val));
348static void install_operand PARAMS ((int mode, int val));
bcb8dff8
KR		 349static void s_bss PARAMS ((int));
350static void s_data1 PARAMS ((int));
351static void s_data2 PARAMS ((int));
352static void s_even PARAMS ((int));
353static void s_proc PARAMS ((int));
e9bb39b4
ILT		 354static void mri_chip PARAMS ((void));
355static void s_chip PARAMS ((int));
27a53b88 356static void s_fopt PARAMS ((int));
6700d36e
ILT		 357static void s_opt PARAMS ((int));
358static void s_reg PARAMS ((int));
e14994d9
ILT		 359static void s_restore PARAMS ((int));
360static void s_save PARAMS ((int));
b4ec75e0
ILT		 361static void s_mri_if PARAMS ((int));
362static void s_mri_else PARAMS ((int));
363static void s_mri_endi PARAMS ((int));
364static void s_mri_break PARAMS ((int));
365static void s_mri_next PARAMS ((int));
366static void s_mri_for PARAMS ((int));
367static void s_mri_endf PARAMS ((int));
368static void s_mri_repeat PARAMS ((int));
369static void s_mri_until PARAMS ((int));
370static void s_mri_while PARAMS ((int));
371static void s_mri_endw PARAMS ((int));
f59fb6ca
ILT		 372static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
373static void md_convert_frag_1 PARAMS ((fragS *));
49864cfa
KR		 374
375static int current_architecture;
7c15cbe8 376
b79de3a1
KR		 377struct m68k_cpu {
378 unsigned long arch;
379 const char *name;
9e64486e 380 int alias;
b79de3a1
KR		 381};
382
383static const struct m68k_cpu archs[] = {
9e64486e
ILT		 384 { m68000, "68000", 0 },
385 { m68010, "68010", 0 },
386 { m68020, "68020", 0 },
387 { m68030, "68030", 0 },
388 { m68040, "68040", 0 },
389 { m68060, "68060", 0 },
390 { cpu32, "cpu32", 0 },
391 { m68881, "68881", 0 },
392 { m68851, "68851", 0 },
8d20a0a8 393 { mcf5200, "5200", 0 },
b79de3a1
KR		 394 /* Aliases (effectively, so far as gas is concerned) for the above
395 cpus. */
9e64486e
ILT		 396 { m68020, "68k", 1 },
397 { m68000, "68302", 1 },
398 { m68000, "68008", 1 },
399 { m68000, "68ec000", 1 },
400 { m68000, "68hc000", 1 },
401 { m68000, "68hc001", 1 },
402 { m68020, "68ec020", 1 },
403 { m68030, "68ec030", 1 },
404 { m68040, "68ec040", 1 },
8d20a0a8 405 { m68060, "68ec060", 1 },
9e64486e
ILT		 406 { cpu32, "68330", 1 },
407 { cpu32, "68331", 1 },
408 { cpu32, "68332", 1 },
409 { cpu32, "68333", 1 },
410 { cpu32, "68340", 1 },
411 { cpu32, "68360", 1 },
412 { m68881, "68882", 1 },
b79de3a1
KR		 413};
414
415static const int n_archs = sizeof (archs) / sizeof (archs[0]);
416
fecd2382
RP		 417/* BCC68000 is for patching in an extra jmp instruction for long offsets
418 on the 68000. The 68000 doesn't support long branches with branchs */
419
420/* This table desribes how you change sizes for the various types of variable
421 size expressions. This version only supports two kinds. */
422
49864cfa
KR		 423/* Note that calls to frag_var need to specify the maximum expansion
424 needed; this is currently 10 bytes for DBCC. */
fecd2382
RP		 425
426/* The fields are:
a39116f1
RP		 427 How far Forward this mode will reach:
428 How far Backward this mode will reach:
429 How many bytes this mode will add to the size of the frag
430 Which mode to go to if the offset won't fit in this one
431 */
04ef74bb 432relax_typeS md_relax_table[] =
355afbcd
KR		 433{
434 {1, 1, 0, 0}, /* First entries aren't used */
435 {1, 1, 0, 0}, /* For no good reason except */
436 {1, 1, 0, 0}, /* that the VAX doesn't either */
437 {1, 1, 0, 0},
438
439 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
440 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
441 {0, 0, 4, 0},
442 {1, 1, 0, 0},
443
444 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
445 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
446 {0, 0, 4, 0},
447 {1, 1, 0, 0},
448
449 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
450 {(32767), (-32768), 2, TAB (PCREL, LONG)},
451 {0, 0, 4, 0},
452 {1, 1, 0, 0},
453
454 {(127), (-128), 0, TAB (BCC68000, SHORT)},
455 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
456 {0, 0, 6, 0}, /* jmp long space */
457 {1, 1, 0, 0},
458
459 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
460 {(32767), (-32768), 2, TAB (DBCC, LONG)},
461 {0, 0, 10, 0}, /* bra/jmp long space */
462 {1, 1, 0, 0},
463
464 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
465 {32767, -32768, 2, TAB (PCLEA, LONG)},
466 {0, 0, 6, 0},
467 {1, 1, 0, 0},
468
04ef74bb
KR		 469 /* For, e.g., jmp pcrel indexed. */
470 {125, -130, 0, TAB (PCINDEX, SHORT)},
471 {32765, -32770, 2, TAB (PCINDEX, LONG)},
472 {0, 0, 4, 0},
473 {1, 1, 0, 0},
355afbcd 474};
fecd2382
RP		 475
476/* These are the machine dependent pseudo-ops. These are included so
477 the assembler can work on the output from the SUN C compiler, which
478 generates these.
a39116f1 479 */
fecd2382
RP		 480
481/* This table describes all the machine specific pseudo-ops the assembler
482 has to support. The fields are:
a39116f1
RP		 483 pseudo-op name without dot
484 function to call to execute this pseudo-op
485 Integer arg to pass to the function
486 */
326b087c 487const pseudo_typeS md_pseudo_table[] =
355afbcd
KR		 488{
489 {"data1", s_data1, 0},
490 {"data2", s_data2, 0},
491 {"bss", s_bss, 0},
492 {"even", s_even, 0},
493 {"skip", s_space, 0},
494 {"proc", s_proc, 0},
a043f579 495#if defined (TE_SUN3) || defined (OBJ_ELF)
355afbcd 496 {"align", s_align_bytes, 0},
5f8cb05e
ILT		 497#endif
498#ifdef OBJ_ELF
499 {"swbeg", s_ignore, 0},
bec66218 500#endif
9e64486e
ILT		 501 {"extend", float_cons, 'x'},
502 {"ldouble", float_cons, 'x'},
e9bb39b4
ILT		 503
504 /* The following pseudo-ops are supported for MRI compatibility. */
505 {"chip", s_chip, 0},
506 {"comline", s_space, 1},
27a53b88
ILT		 507 {"fopt", s_fopt, 0},
508 {"mask2", s_ignore, 0},
6700d36e
ILT		 509 {"opt", s_opt, 0},
510 {"reg", s_reg, 0},
e14994d9
ILT		 511 {"restore", s_restore, 0},
512 {"save", s_save, 0},
e9bb39b4 513
b4ec75e0
ILT		 514 {"if", s_mri_if, 0},
515 {"if.b", s_mri_if, 'b'},
516 {"if.w", s_mri_if, 'w'},
517 {"if.l", s_mri_if, 'l'},
518 {"else", s_mri_else, 0},
519 {"else.s", s_mri_else, 's'},
520 {"else.l", s_mri_else, 'l'},
521 {"endi", s_mri_endi, 0},
522 {"break", s_mri_break, 0},
523 {"break.s", s_mri_break, 's'},
524 {"break.l", s_mri_break, 'l'},
525 {"next", s_mri_next, 0},
526 {"next.s", s_mri_next, 's'},
527 {"next.l", s_mri_next, 'l'},
528 {"for", s_mri_for, 0},
529 {"for.b", s_mri_for, 'b'},
530 {"for.w", s_mri_for, 'w'},
531 {"for.l", s_mri_for, 'l'},
532 {"endf", s_mri_endf, 0},
533 {"repeat", s_mri_repeat, 0},
534 {"until", s_mri_until, 0},
535 {"until.b", s_mri_until, 'b'},
536 {"until.w", s_mri_until, 'w'},
537 {"until.l", s_mri_until, 'l'},
538 {"while", s_mri_while, 0},
539 {"while.b", s_mri_while, 'b'},
540 {"while.w", s_mri_while, 'w'},
541 {"while.l", s_mri_while, 'l'},
542 {"endw", s_mri_endw, 0},
543
355afbcd 544 {0, 0, 0}
fecd2382
RP		 545};
546
547
3ad9ec6a 548/* The mote pseudo ops are put into the opcode table, since they
355afbcd 549 don't start with a . they look like opcodes to gas.
3ad9ec6a 550 */
f59fb6ca
ILT		 551
552#ifdef M68KCOFF
553extern void obj_coff_section PARAMS ((int));
554#endif
3ad9ec6a 555
49864cfa 556CONST pseudo_typeS mote_pseudo_table[] =
3ad9ec6a
ILT		 557{
558
b79de3a1 559 {"dcl", cons, 4},
355afbcd 560 {"dc", cons, 2},
b79de3a1
KR		 561 {"dcw", cons, 2},
562 {"dcb", cons, 1},
3ad9ec6a 563
b79de3a1 564 {"dsl", s_space, 4},
355afbcd 565 {"ds", s_space, 2},
b79de3a1
KR		 566 {"dsw", s_space, 2},
567 {"dsb", s_space, 1},
3ad9ec6a 568
355afbcd 569 {"xdef", s_globl, 0},
a043f579
ILT		 570#ifdef OBJ_ELF
571 {"align", s_align_bytes, 0},
572#else
355afbcd 573 {"align", s_align_ptwo, 0},
a043f579 574#endif
3ad9ec6a 575#ifdef M68KCOFF
355afbcd
KR		 576 {"sect", obj_coff_section, 0},
577 {"section", obj_coff_section, 0},
3ad9ec6a 578#endif
bcb8dff8 579 {0, 0, 0}
3ad9ec6a
ILT		 580};
581
fecd2382
RP		 582#define issbyte(x) ((x)>=-128 && (x)<=127)
583#define isubyte(x) ((x)>=0 && (x)<=255)
584#define issword(x) ((x)>=-32768 && (x)<=32767)
585#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 586
e284846a 587#define isbyte(x) ((x)>= -255 && (x)<=255)
a7512014 588#define isword(x) ((x)>=-65536 && (x)<=65535)
fecd2382 589#define islong(x) (1)
f8701a3f
SC		 590
591extern char *input_line_pointer;
fecd2382 592
fecd2382
RP		 593static char mklower_table[256];
594#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 595static char notend_table[256];
fecd2382 596static char alt_notend_table[256];
a1c7c0f3
ILT		 597#define notend(s) \
598 (! (notend_table[(unsigned char) *s] \
599 || (*s == ':' \
600 && alt_notend_table[(unsigned char) s[1]])))
7c15cbe8 601
49864cfa 602#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
3ad9ec6a 603
82489ea0
KR		 604#ifdef NO_PCREL_RELOCS
605
606int
607make_pcrel_absolute(fixP, add_number)
608 fixS *fixP;
609 long *add_number;
610{
611 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
612
613 /* rewrite the PC relative instructions to absolute address ones.
614 * these are rumoured to be faster, and the apollo linker refuses
615 * to deal with the PC relative relocations.
616 */
617 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
618 {
619 opcode[0] = 0x4e;
620 opcode[1] = 0xf9;
621 }
622 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
623 {
624 opcode[0] = 0x4e;
625 opcode[1] = 0xb9;
626 }
627 else
628 as_fatal ("Unknown PC relative instruction");
629 *add_number -= 4;
630 return 0;
631}
632
633#endif /* NO_PCREL_RELOCS */
634
355afbcd
KR		 635short
636tc_coff_fix2rtype (fixP)
637 fixS *fixP;
fecd2382 638{
3b06beb7
ILT		 639 if (fixP->fx_tcbit && fixP->fx_size == 4)
640 return R_RELLONG_NEG;
82489ea0
KR		 641#ifdef NO_PCREL_RELOCS
642 know (fixP->fx_pcrel == 0);
643 return (fixP->fx_size == 1 ? R_RELBYTE
644 : fixP->fx_size == 2 ? R_DIR16
645 : R_DIR32);
646#else
355afbcd
KR		 647 return (fixP->fx_pcrel ?
648 (fixP->fx_size == 1 ? R_PCRBYTE :
649 fixP->fx_size == 2 ? R_PCRWORD :
650 R_PCRLONG) :
651 (fixP->fx_size == 1 ? R_RELBYTE :
652 fixP->fx_size == 2 ? R_RELWORD :
653 R_RELLONG));
82489ea0 654#endif
3ad9ec6a
ILT		 655}
656
657#endif
fecd2382 658
a043f579
ILT		 659#ifdef OBJ_ELF
660
661/* Compute the relocation code for a fixup of SIZE bytes, using pc
662 relative relocation if PCREL is non-zero. PIC says whether a special
663 pic relocation was requested. */
664
665static bfd_reloc_code_real_type get_reloc_code
666 PARAMS ((int, int, enum pic_relocation));
667
668static bfd_reloc_code_real_type
669get_reloc_code (size, pcrel, pic)
670 int size;
671 int pcrel;
672 enum pic_relocation pic;
673{
674 switch (pic)
675 {
676 case pic_got_pcrel:
677 switch (size)
678 {
679 case 1:
680 return BFD_RELOC_8_GOT_PCREL;
681 case 2:
682 return BFD_RELOC_16_GOT_PCREL;
683 case 4:
684 return BFD_RELOC_32_GOT_PCREL;
685 }
686 break;
687
688 case pic_got_off:
689 switch (size)
690 {
691 case 1:
692 return BFD_RELOC_8_GOTOFF;
693 case 2:
694 return BFD_RELOC_16_GOTOFF;
695 case 4:
696 return BFD_RELOC_32_GOTOFF;
697 }
698 break;
699
700 case pic_plt_pcrel:
701 switch (size)
702 {
703 case 1:
704 return BFD_RELOC_8_PLT_PCREL;
705 case 2:
706 return BFD_RELOC_16_PLT_PCREL;
707 case 4:
708 return BFD_RELOC_32_PLT_PCREL;
709 }
710 break;
711
712 case pic_plt_off:
713 switch (size)
714 {
715 case 1:
716 return BFD_RELOC_8_PLTOFF;
717 case 2:
718 return BFD_RELOC_16_PLTOFF;
719 case 4:
720 return BFD_RELOC_32_PLTOFF;
721 }
722 break;
723
724 case pic_none:
725 if (pcrel)
726 {
727 switch (size)
728 {
729 case 1:
730 return BFD_RELOC_8_PCREL;
731 case 2:
732 return BFD_RELOC_16_PCREL;
733 case 4:
734 return BFD_RELOC_32_PCREL;
735 }
736 }
737 else
738 {
739 switch (size)
740 {
741 case 1:
742 return BFD_RELOC_8;
743 case 2:
744 return BFD_RELOC_16;
745 case 4:
746 return BFD_RELOC_32;
747 }
748 }
749 }
750
751 as_bad ("Can not do %d byte %s%srelocation", size,
752 pcrel ? "pc-relative " : "",
753 pic == pic_none ? "" : "pic ");
754 return BFD_RELOC_NONE;
755}
756
757/* Here we decide which fixups can be adjusted to make them relative
758 to the beginning of the section instead of the symbol. Basically
759 we need to make sure that the dynamic relocations are done
760 correctly, so in some cases we force the original symbol to be
761 used. */
762int
763tc_m68k_fix_adjustable (fixP)
764 fixS *fixP;
765{
766 /* Prevent all adjustments to global symbols. */
767 if (S_IS_EXTERNAL (fixP->fx_addsy))
768 return 0;
769
770 /* adjust_reloc_syms doesn't know about the GOT */
771 switch (fixP->fx_r_type)
772 {
773 case BFD_RELOC_8_GOT_PCREL:
774 case BFD_RELOC_16_GOT_PCREL:
775 case BFD_RELOC_32_GOT_PCREL:
776 case BFD_RELOC_8_GOTOFF:
777 case BFD_RELOC_16_GOTOFF:
778 case BFD_RELOC_32_GOTOFF:
779 case BFD_RELOC_8_PLT_PCREL:
780 case BFD_RELOC_16_PLT_PCREL:
781 case BFD_RELOC_32_PLT_PCREL:
782 case BFD_RELOC_8_PLTOFF:
783 case BFD_RELOC_16_PLTOFF:
784 case BFD_RELOC_32_PLTOFF:
785 return 0;
786
787 default:
788 return 1;
789 }
790}
791
792#else /* !OBJ_ELF */
793
794#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
795
796#endif /* OBJ_ELF */
797
49864cfa
KR		 798#ifdef BFD_ASSEMBLER
799
800arelent *
801tc_gen_reloc (section, fixp)
802 asection *section;
803 fixS *fixp;
804{
805 arelent *reloc;
806 bfd_reloc_code_real_type code;
807
9e64486e 808 if (fixp->fx_tcbit)
3b06beb7
ILT		 809 abort ();
810
a043f579 811 if (fixp->fx_r_type != BFD_RELOC_NONE)
7f003b7f
ILT		 812 {
813 code = fixp->fx_r_type;
814
815 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
816 that fixup_segment converted a non-PC relative reloc into a
817 PC relative reloc. In such a case, we need to convert the
818 reloc code. */
819 if (fixp->fx_pcrel)
820 {
821 switch (code)
822 {
823 case BFD_RELOC_8:
824 code = BFD_RELOC_8_PCREL;
825 break;
826 case BFD_RELOC_16:
827 code = BFD_RELOC_16_PCREL;
828 break;
829 case BFD_RELOC_32:
830 code = BFD_RELOC_32_PCREL;
831 break;
832 case BFD_RELOC_8_PCREL:
833 case BFD_RELOC_16_PCREL:
834 case BFD_RELOC_32_PCREL:
835 case BFD_RELOC_8_GOT_PCREL:
836 case BFD_RELOC_16_GOT_PCREL:
837 case BFD_RELOC_32_GOT_PCREL:
838 case BFD_RELOC_8_GOTOFF:
839 case BFD_RELOC_16_GOTOFF:
840 case BFD_RELOC_32_GOTOFF:
841 case BFD_RELOC_8_PLT_PCREL:
842 case BFD_RELOC_16_PLT_PCREL:
843 case BFD_RELOC_32_PLT_PCREL:
844 case BFD_RELOC_8_PLTOFF:
845 case BFD_RELOC_16_PLTOFF:
846 case BFD_RELOC_32_PLTOFF:
847 break;
848 default:
849 as_bad_where (fixp->fx_file, fixp->fx_line,
850 "Cannot make %s relocation PC relative",
851 bfd_get_reloc_code_name (code));
852 }
853 }
854 }
a043f579 855 else
49864cfa 856 {
a043f579
ILT		 857#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
858 switch (F (fixp->fx_size, fixp->fx_pcrel))
859 {
49864cfa 860#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
a043f579
ILT		 861 MAP (1, 0, BFD_RELOC_8);
862 MAP (2, 0, BFD_RELOC_16);
863 MAP (4, 0, BFD_RELOC_32);
864 MAP (1, 1, BFD_RELOC_8_PCREL);
865 MAP (2, 1, BFD_RELOC_16_PCREL);
866 MAP (4, 1, BFD_RELOC_32_PCREL);
867 default:
868 abort ();
869 }
49864cfa 870 }
a043f579
ILT		 871#undef F
872#undef MAP
49864cfa 873
590c50d8 874 reloc = (arelent *) xmalloc (sizeof (arelent));
49864cfa
KR		 875 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
876 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a043f579 877#ifndef OBJ_ELF
49864cfa
KR		 878 if (fixp->fx_pcrel)
879 reloc->addend = fixp->fx_addnumber;
880 else
881 reloc->addend = 0;
a043f579
ILT		 882#else
883 if (!fixp->fx_pcrel)
884 reloc->addend = fixp->fx_addnumber;
7f003b7f 885 else
a043f579
ILT		 886 reloc->addend = (section->vma
887 + (fixp->fx_pcrel_adjust == 64
888 ? -1 : fixp->fx_pcrel_adjust)
889 + fixp->fx_addnumber
890 + md_pcrel_from (fixp));
a043f579 891#endif
49864cfa
KR		 892
893 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
894 assert (reloc->howto != 0);
895
896 return reloc;
897}
898
899#endif /* BFD_ASSEMBLER */
900
49864cfa
KR		 901/* Handle of the OPCODE hash table. NULL means any use before
902 m68k_ip_begin() will crash. */
903static struct hash_control *op_hash;
fecd2382 904\f
a1c7c0f3 905/* Assemble an m68k instruction. */
355afbcd 906
355afbcd
KR		 907void
908m68k_ip (instring)
6d27d3a2 909 char *instring;
fecd2382 910{
6d27d3a2
KR		 911 register char *p;
912 register struct m68k_op *opP;
913 register struct m68k_incant *opcode;
a1c7c0f3 914 register const char *s;
6d27d3a2 915 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 916 char *pdot, *pdotmove;
a1c7c0f3 917 enum m68k_size siz1, siz2;
355afbcd
KR		 918 char c;
919 int losing;
920 int opsfound;
6d27d3a2
KR		 921 LITTLENUM_TYPE words[6];
922 LITTLENUM_TYPE *wordp;
8be74775 923 unsigned long ok_arch = 0;
6d27d3a2
KR		 924
925 if (*instring == ' ')
926 instring++; /* skip leading whitespace */
927
928 /* Scan up to end of operation-code, which MUST end in end-of-string
929 or exactly 1 space. */
3ad9ec6a 930 pdot = 0;
355afbcd
KR		 931 for (p = instring; *p != '\0'; p++)
932 {
933 if (*p == ' ')
934 break;
935 if (*p == '.')
936 pdot = p;
937 }
6d27d3a2 938
355afbcd
KR		 939 if (p == instring)
940 {
941 the_ins.error = "No operator";
355afbcd
KR		 942 return;
943 }
6d27d3a2
KR		 944
945 /* p now points to the end of the opcode name, probably whitespace.
a1c7c0f3
ILT		 946 Make sure the name is null terminated by clobbering the
947 whitespace, look it up in the hash table, then fix it back.
3ad9ec6a 948 Remove a dot, first, since the opcode tables have none. */
355afbcd
KR		 949 if (pdot != NULL)
950 {
951 for (pdotmove = pdot; pdotmove < p; pdotmove++)
952 *pdotmove = pdotmove[1];
953 p--;
954 }
3ad9ec6a 955
6d27d3a2
KR		 956 c = *p;
957 *p = '\0';
355afbcd 958 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
6d27d3a2
KR		 959 *p = c;
960
355afbcd
KR		 961 if (pdot != NULL)
962 {
963 for (pdotmove = p; pdotmove > pdot; pdotmove--)
964 *pdotmove = pdotmove[-1];
965 *pdot = '.';
966 ++p;
967 }
3ad9ec6a 968
355afbcd
KR		 969 if (opcode == NULL)
970 {
971 the_ins.error = "Unknown operator";
355afbcd
KR		 972 return;
973 }
6d27d3a2
KR		 974
975 /* found a legitimate opcode, start matching operands */
355afbcd
KR		 976 while (*p == ' ')
977 ++p;
6d27d3a2 978
355afbcd
KR		 979 if (opcode->m_operands == 0)
980 {
981 char *old = input_line_pointer;
982 *old = '\n';
983 input_line_pointer = p;
984 /* Ahh - it's a motorola style psuedo op */
985 mote_pseudo_table[opcode->m_opnum].poc_handler
986 (mote_pseudo_table[opcode->m_opnum].poc_val);
987 input_line_pointer = old;
988 *old = 0;
3ad9ec6a 989
355afbcd
KR		 990 return;
991 }
3ad9ec6a 992
92a25e12
ILT		 993 if (flag_mri && opcode->m_opnum == 0)
994 {
995 /* In MRI mode, random garbage is allowed after an instruction
996 which accepts no operands. */
997 the_ins.args = opcode->m_operands;
998 the_ins.numargs = opcode->m_opnum;
999 the_ins.numo = opcode->m_codenum;
1000 the_ins.opcode[0] = getone (opcode);
1001 the_ins.opcode[1] = gettwo (opcode);
1002 return;
1003 }
1004
355afbcd
KR		 1005 for (opP = &the_ins.operands[0]; *p; opP++)
1006 {
355afbcd 1007 p = crack_operand (p, opP);
6d27d3a2 1008
355afbcd
KR		 1009 if (opP->error)
1010 {
1011 the_ins.error = opP->error;
1012 return;
1013 }
6d27d3a2 1014 }
6d27d3a2
KR		 1015
1016 opsfound = opP - &the_ins.operands[0];
1017
a1c7c0f3
ILT		 1018 /* This ugly hack is to support the floating pt opcodes in their
1019 standard form. Essentially, we fake a first enty of type COP#1 */
355afbcd
KR		 1020 if (opcode->m_operands[0] == 'I')
1021 {
1022 int n;
6d27d3a2 1023
355afbcd
KR		 1024 for (n = opsfound; n > 0; --n)
1025 the_ins.operands[n] = the_ins.operands[n - 1];
6d27d3a2 1026
a1c7c0f3
ILT		 1027 memset ((char *) (&the_ins.operands[0]), '\0',
1028 sizeof (the_ins.operands[0]));
1029 the_ins.operands[0].mode = CONTROL;
27a53b88 1030 the_ins.operands[0].reg = m68k_float_copnum;
355afbcd
KR		 1031 opsfound++;
1032 }
6d27d3a2
KR		 1033
1034 /* We've got the operands. Find an opcode that'll accept them */
355afbcd
KR		 1035 for (losing = 0;;)
1036 {
49864cfa
KR		 1037 /* If we didn't get the right number of ops, or we have no
1038 common model with this pattern then reject this pattern. */
6d27d3a2 1039
0b810a6e 1040 ok_arch |= opcode->m_arch;
355afbcd
KR		 1041 if (opsfound != opcode->m_opnum
1042 || ((opcode->m_arch & current_architecture) == 0))
0b810a6e 1043 ++losing;
355afbcd
KR		 1044 else
1045 {
a1c7c0f3
ILT		 1046 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1047 *s && !losing;
1048 s += 2, opP++)
355afbcd
KR		 1049 {
1050 /* Warning: this switch is huge! */
49864cfa
KR		 1051 /* I've tried to organize the cases into this order:
1052 non-alpha first, then alpha by letter. Lower-case
1053 goes directly before uppercase counterpart. */
1054 /* Code with multiple case ...: gets sorted by the lowest
1055 case ... it belongs to. I hope this makes sense. */
355afbcd
KR		 1056 switch (*s)
1057 {
a1c7c0f3
ILT		 1058 case '!':
1059 switch (opP->mode)
1060 {
1061 case IMMED:
1062 case DREG:
1063 case AREG:
1064 case FPREG:
1065 case CONTROL:
1066 case AINC:
1067 case ADEC:
1068 case REGLST:
1069 losing++;
1070 break;
1071 default:
1072 break;
1073 }
355afbcd
KR		 1074 break;
1075
1076 case '`':
1077 switch (opP->mode)
1078 {
355afbcd
KR		 1079 case IMMED:
1080 case DREG:
1081 case AREG:
a1c7c0f3
ILT		 1082 case FPREG:
1083 case CONTROL:
355afbcd
KR		 1084 case AINC:
1085 case REGLST:
1086 case AINDR:
1087 losing++;
bcb8dff8
KR		 1088 break;
1089 default:
1090 break;
355afbcd
KR		 1091 }
1092 break;
8be74775 1093
b4d51f3d
ILT		 1094 case '<':
1095 switch (opP->mode)
1096 {
1097 case DREG:
1098 case AREG:
1099 case FPREG:
1100 case CONTROL:
1101 case IMMED:
1102 case ADEC:
1103 case REGLST:
1104 losing++;
1105 break;
1106 default:
1107 break;
1108 }
1109 break;
1110
1111 case '>':
1112 switch (opP->mode)
1113 {
1114 case DREG:
1115 case AREG:
1116 case FPREG:
1117 case CONTROL:
1118 case IMMED:
1119 case AINC:
1120 case REGLST:
1121 losing++;
1122 break;
1123 case ABSL:
1124 break;
1125 default:
1126 if (opP->reg == PC
1127 || opP->reg == ZPC)
1128 losing++;
1129 break;
1130 }
1131 break;
1132
1133 case 'm':
1134 switch (opP->mode)
1135 {
1136 case DREG:
1137 case AREG:
1138 case AINDR:
1139 case AINC:
1140 case ADEC:
1141 break;
1142 default:
1143 losing++;
1144 }
1145 break;
1146
1147 case 'n':
1148 switch (opP->mode)
1149 {
1150 case DISP:
1151 break;
1152 default:
1153 losing++;
1154 }
1155 break;
1156
1157 case 'o':
1158 switch (opP->mode)
1159 {
1160 case BASE:
1161 case ABSL:
1162 case IMMED:
1163 break;
1164 default:
1165 losing++;
1166 }
1167 break;
1168
1169 case 'p':
1170 switch (opP->mode)
1171 {
1172 case DREG:
1173 case AREG:
1174 case AINDR:
1175 case AINC:
1176 case ADEC:
fee3e248 1177 break;
b4d51f3d 1178 case DISP:
fee3e248
ILT		 1179 if (opP->reg == PC || opP->reg == ZPC)
1180 losing++;
b4d51f3d
ILT		 1181 break;
1182 default:
1183 losing++;
1184 }
1185 break;
1186
355afbcd
KR		 1187 case '#':
1188 if (opP->mode != IMMED)
1189 losing++;
a1c7c0f3
ILT		 1190 else if (s[1] == 'b'
1191 && ! isvar (&opP->disp)
336435bc
ILT		 1192 && (opP->disp.exp.X_op != O_constant
1193 || ! isbyte (opP->disp.exp.X_add_number)))
a1c7c0f3 1194 losing++;
a78bc551
ILT		 1195 else if (s[1] == 'B'
1196 && ! isvar (&opP->disp)
1197 && (opP->disp.exp.X_op != O_constant
1198 || ! issbyte (opP->disp.exp.X_add_number)))
1199 losing++;
a1c7c0f3
ILT		 1200 else if (s[1] == 'w'
1201 && ! isvar (&opP->disp)
336435bc
ILT		 1202 && (opP->disp.exp.X_op != O_constant
1203 || ! isword (opP->disp.exp.X_add_number)))
a1c7c0f3 1204 losing++;
9e64486e
ILT		 1205 else if (s[1] == 'W'
1206 && ! isvar (&opP->disp)
1207 && (opP->disp.exp.X_op != O_constant
1208 || ! issword (opP->disp.exp.X_add_number)))
1209 losing++;
355afbcd
KR		 1210 break;
1211
1212 case '^':
1213 case 'T':
1214 if (opP->mode != IMMED)
1215 losing++;
1216 break;
1217
1218 case '$':
a1c7c0f3
ILT		 1219 if (opP->mode == AREG
1220 || opP->mode == CONTROL
1221 || opP->mode == FPREG
1222 || opP->mode == IMMED
1223 || opP->mode == REGLST
1224 || (opP->mode != ABSL
1225 && (opP->reg == PC
1226 || opP->reg == ZPC)))
355afbcd
KR		 1227 losing++;
1228 break;
1229
1230 case '%':
a1c7c0f3
ILT		 1231 if (opP->mode == CONTROL
1232 || opP->mode == FPREG
1233 || opP->mode == REGLST
a7512014 1234 || opP->mode == IMMED
a1c7c0f3 1235 || (opP->mode != ABSL
a1c7c0f3
ILT		 1236 && (opP->reg == PC
1237 || opP->reg == ZPC)))
355afbcd
KR		 1238 losing++;
1239 break;
1240
355afbcd 1241 case '&':
a1c7c0f3
ILT		 1242 switch (opP->mode)
1243 {
1244 case DREG:
1245 case AREG:
1246 case FPREG:
1247 case CONTROL:
1248 case IMMED:
1249 case AINC:
1250 case ADEC:
1251 case REGLST:
1252 losing++;
1253 break;
1254 case ABSL:
1255 break;
1256 default:
1257 if (opP->reg == PC
1258 || opP->reg == ZPC)
1259 losing++;
1260 break;
1261 }
355afbcd
KR		 1262 break;
1263
1264 case '*':
a1c7c0f3
ILT		 1265 if (opP->mode == CONTROL
1266 || opP->mode == FPREG
1267 || opP->mode == REGLST)
355afbcd
KR		 1268 losing++;
1269 break;
1270
1271 case '+':
1272 if (opP->mode != AINC)
1273 losing++;
1274 break;
1275
1276 case '-':
1277 if (opP->mode != ADEC)
1278 losing++;
1279 break;
1280
1281 case '/':
a1c7c0f3
ILT		 1282 switch (opP->mode)
1283 {
1284 case AREG:
1285 case CONTROL:
1286 case FPREG:
1287 case AINC:
1288 case ADEC:
1289 case IMMED:
1290 case REGLST:
1291 losing++;
1292 break;
1293 default:
1294 break;
1295 }
355afbcd
KR		 1296 break;
1297
1298 case ';':
a1c7c0f3
ILT		 1299 switch (opP->mode)
1300 {
1301 case AREG:
1302 case CONTROL:
1303 case FPREG:
1304 case REGLST:
1305 losing++;
1306 break;
1307 default:
1308 break;
1309 }
355afbcd
KR		 1310 break;
1311
1312 case '?':
a1c7c0f3
ILT		 1313 switch (opP->mode)
1314 {
1315 case AREG:
1316 case CONTROL:
1317 case FPREG:
1318 case AINC:
1319 case ADEC:
1320 case IMMED:
1321 case REGLST:
1322 losing++;
1323 break;
1324 case ABSL:
1325 break;
1326 default:
1327 if (opP->reg == PC || opP->reg == ZPC)
1328 losing++;
1329 break;
1330 }
355afbcd
KR		 1331 break;
1332
1333 case '@':
a1c7c0f3
ILT		 1334 switch (opP->mode)
1335 {
1336 case AREG:
1337 case CONTROL:
1338 case FPREG:
1339 case IMMED:
1340 case REGLST:
1341 losing++;
1342 break;
1343 default:
1344 break;
1345 }
355afbcd
KR		 1346 break;
1347
1348 case '~': /* For now! (JF FOO is this right?) */
a1c7c0f3
ILT		 1349 switch (opP->mode)
1350 {
1351 case DREG:
1352 case AREG:
1353 case CONTROL:
1354 case FPREG:
1355 case IMMED:
1356 case REGLST:
1357 losing++;
1358 break;
1359 case ABSL:
1360 break;
1361 default:
1362 if (opP->reg == PC
1363 || opP->reg == ZPC)
1364 losing++;
1365 break;
1366 }
355afbcd
KR		 1367 break;
1368
1369 case '3':
a1c7c0f3
ILT		 1370 if (opP->mode != CONTROL
1371 || (opP->reg != TT0 && opP->reg != TT1))
355afbcd
KR		 1372 losing++;
1373 break;
1374
1375 case 'A':
1376 if (opP->mode != AREG)
1377 losing++;
1378 break;
a1c7c0f3 1379
355afbcd
KR		 1380 case 'a':
1381 if (opP->mode != AINDR)
a1c7c0f3 1382 ++losing;
355afbcd 1383 break;
a1c7c0f3 1384
355afbcd 1385 case 'B': /* FOO */
a1c7c0f3
ILT		 1386 if (opP->mode != ABSL
1387 || (flag_long_jumps
1388 && strncmp (instring, "jbsr", 4) == 0))
355afbcd
KR		 1389 losing++;
1390 break;
1391
1392 case 'C':
a1c7c0f3 1393 if (opP->mode != CONTROL || opP->reg != CCR)
355afbcd
KR		 1394 losing++;
1395 break;
1396
a1c7c0f3
ILT		 1397 case 'd':
1398 if (opP->mode != DISP
1399 || opP->reg < ADDR0
1400 || opP->reg > ADDR7)
355afbcd
KR		 1401 losing++;
1402 break;
1403
1404 case 'D':
1405 if (opP->mode != DREG)
1406 losing++;
1407 break;
1408
1409 case 'F':
a1c7c0f3 1410 if (opP->mode != FPREG)
355afbcd
KR		 1411 losing++;
1412 break;
1413
1414 case 'I':
a1c7c0f3 1415 if (opP->mode != CONTROL
27a53b88
ILT		 1416 || opP->reg < COP0
1417 || opP->reg > COP7)
355afbcd
KR		 1418 losing++;
1419 break;
1420
1421 case 'J':
a1c7c0f3 1422 if (opP->mode != CONTROL
355afbcd 1423 || opP->reg < USP
82489ea0
KR		 1424 || opP->reg > last_movec_reg)
1425 losing++;
1426 else
355afbcd 1427 {
a1c7c0f3 1428 const enum m68k_register *rp;
82489ea0
KR		 1429 for (rp = control_regs; *rp; rp++)
1430 if (*rp == opP->reg)
1431 break;
1432 if (*rp == 0)
1433 losing++;
1434 }
355afbcd
KR		 1435 break;
1436
1437 case 'k':
1438 if (opP->mode != IMMED)
1439 losing++;
1440 break;
8be74775 1441
355afbcd
KR		 1442 case 'l':
1443 case 'L':
a1c7c0f3
ILT		 1444 if (opP->mode == DREG
1445 || opP->mode == AREG
1446 || opP->mode == FPREG)
355afbcd
KR		 1447 {
1448 if (s[1] == '8')
1449 losing++;
1450 else
1451 {
a1c7c0f3
ILT		 1452 switch (opP->mode)
1453 {
1454 case DREG:
1455 opP->mask = 1 << (opP->reg - DATA0);
1456 break;
1457 case AREG:
1458 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1459 break;
1460 case FPREG:
1461 opP->mask = 1 << (opP->reg - FP0 + 16);
1462 break;
1463 default:
1464 abort ();
1465 }
355afbcd 1466 opP->mode = REGLST;
355afbcd
KR		 1467 }
1468 }
a1c7c0f3 1469 else if (opP->mode == CONTROL)
355afbcd 1470 {
a1c7c0f3
ILT		 1471 if (s[1] != '8')
1472 losing++;
1473 else
1474 {
1475 switch (opP->reg)
1476 {
1477 case FPI:
1478 opP->mask = 1 << 24;
1479 break;
1480 case FPS:
1481 opP->mask = 1 << 25;
1482 break;
1483 case FPC:
1484 opP->mask = 1 << 26;
1485 break;
1486 default:
1487 losing++;
1488 break;
1489 }
1490 opP->mode = REGLST;
1491 }
355afbcd 1492 }
6700d36e
ILT		 1493 else if (opP->mode == ABSL
1494 && opP->disp.size == SIZE_UNSPEC
1495 && opP->disp.exp.X_op == O_constant)
1496 {
1497 /* This is what the MRI REG pseudo-op generates. */
1498 opP->mode = REGLST;
1499 opP->mask = opP->disp.exp.X_add_number;
1500 }
a1c7c0f3 1501 else if (opP->mode != REGLST)
355afbcd 1502 losing++;
a1c7c0f3
ILT		 1503 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1504 losing++;
1505 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
355afbcd
KR		 1506 losing++;
1507 break;
1508
1509 case 'M':
1510 if (opP->mode != IMMED)
1511 losing++;
336435bc
ILT		 1512 else if (opP->disp.exp.X_op != O_constant
1513 || ! issbyte (opP->disp.exp.X_add_number))
a1c7c0f3 1514 losing++;
6700d36e
ILT		 1515 else if (! m68k_quick
1516 && instring[3] != 'q'
1517 && instring[4] != 'q')
1518 losing++;
355afbcd 1519 break;
8be74775 1520
355afbcd 1521 case 'O':
8d20a0a8
C		 1522 if (opP->mode != DREG
1523 && opP->mode != IMMED
1524 && opP->mode != ABSL)
355afbcd
KR		 1525 losing++;
1526 break;
6d27d3a2 1527
355afbcd
KR		 1528 case 'Q':
1529 if (opP->mode != IMMED)
1530 losing++;
336435bc 1531 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1532 || opP->disp.exp.X_add_number < 1
1533 || opP->disp.exp.X_add_number > 8)
1534 losing++;
6700d36e
ILT		 1535 else if (! m68k_quick
1536 && (strncmp (instring, "add", 3) == 0
1537 || strncmp (instring, "sub", 3) == 0)
1538 && instring[3] != 'q')
1539 losing++;
355afbcd 1540 break;
8be74775 1541
355afbcd
KR		 1542 case 'R':
1543 if (opP->mode != DREG && opP->mode != AREG)
1544 losing++;
1545 break;
8be74775 1546
355afbcd 1547 case 'r':
a1c7c0f3
ILT		 1548 if (opP->mode != AINDR
1549 && (opP->mode != BASE
1550 || (opP->reg != 0
1551 && opP->reg != ZADDR0)
1552 || opP->disp.exp.X_op != O_absent
1553 || ((opP->index.reg < DATA0
1554 || opP->index.reg > DATA7)
1555 && (opP->index.reg < ADDR0
1556 || opP->index.reg > ADDR7))
1557 || opP->index.size != SIZE_UNSPEC
1558 || opP->index.scale != 1))
355afbcd
KR		 1559 losing++;
1560 break;
c50140c8 1561
355afbcd 1562 case 's':
a1c7c0f3
ILT		 1563 if (opP->mode != CONTROL
1564 || ! (opP->reg == FPI
1565 || opP->reg == FPS
1566 || opP->reg == FPC))
355afbcd
KR		 1567 losing++;
1568 break;
8be74775 1569
355afbcd 1570 case 'S':
a1c7c0f3 1571 if (opP->mode != CONTROL || opP->reg != SR)
355afbcd
KR		 1572 losing++;
1573 break;
8be74775 1574
355afbcd
KR		 1575 case 't':
1576 if (opP->mode != IMMED)
1577 losing++;
336435bc 1578 else if (opP->disp.exp.X_op != O_constant
a1c7c0f3
ILT		 1579 || opP->disp.exp.X_add_number < 0
1580 || opP->disp.exp.X_add_number > 7)
1581 losing++;
355afbcd 1582 break;
4134a793 1583
355afbcd 1584 case 'U':
a1c7c0f3 1585 if (opP->mode != CONTROL || opP->reg != USP)
355afbcd
KR		 1586 losing++;
1587 break;
8be74775 1588
355afbcd 1589 /* JF these are out of order. We could put them
1404ef23
KR		 1590 in order if we were willing to put up with
1591 bunches of #ifdef m68851s in the code.
4134a793 1592
1404ef23
KR		 1593 Don't forget that you need these operands
1594 to use 68030 MMU instructions. */
f8701a3f 1595#ifndef NO_68851
355afbcd
KR		 1596 /* Memory addressing mode used by pflushr */
1597 case '|':
a1c7c0f3
ILT		 1598 if (opP->mode == CONTROL
1599 || opP->mode == FPREG
1600 || opP->mode == DREG
1601 || opP->mode == AREG
1602 || opP->mode == REGLST)
355afbcd 1603 losing++;
9adcd781
ILT		 1604 /* We should accept immediate operands, but they
1605 supposedly have to be quad word, and we don't
1606 handle that. I would like to see what a Motorola
1607 assembler does before doing something here. */
1608 if (opP->mode == IMMED)
1609 losing++;
355afbcd
KR		 1610 break;
1611
1612 case 'f':
a1c7c0f3
ILT		 1613 if (opP->mode != CONTROL
1614 || (opP->reg != SFC && opP->reg != DFC))
355afbcd
KR		 1615 losing++;
1616 break;
1617
9adcd781
ILT		 1618 case '0':
1619 if (opP->mode != CONTROL || opP->reg != TC)
1620 losing++;
1621 break;
1622
1623 case '1':
1624 if (opP->mode != CONTROL || opP->reg != AC)
1625 losing++;
1626 break;
1627
1628 case '2':
a1c7c0f3 1629 if (opP->mode != CONTROL
9adcd781 1630 || (opP->reg != CAL
a1c7c0f3 1631 && opP->reg != VAL
9adcd781 1632 && opP->reg != SCC))
355afbcd
KR		 1633 losing++;
1634 break;
1635
1636 case 'V':
a1c7c0f3
ILT		 1637 if (opP->mode != CONTROL
1638 || opP->reg != VAL)
355afbcd
KR		 1639 losing++;
1640 break;
8be74775 1641
355afbcd 1642 case 'W':
a1c7c0f3
ILT		 1643 if (opP->mode != CONTROL
1644 || (opP->reg != DRP
1645 && opP->reg != SRP
355afbcd
KR		 1646 && opP->reg != CRP))
1647 losing++;
1648 break;
1649
1650 case 'X':
a1c7c0f3
ILT		 1651 if (opP->mode != CONTROL
1652 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1653 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
355afbcd
KR		 1654 losing++;
1655 break;
1656
1657 case 'Y':
a1c7c0f3 1658 if (opP->mode != CONTROL || opP->reg != PSR)
355afbcd
KR		 1659 losing++;
1660 break;
1661
1662 case 'Z':
a1c7c0f3 1663 if (opP->mode != CONTROL || opP->reg != PCSR)
355afbcd
KR		 1664 losing++;
1665 break;
f8701a3f 1666#endif
355afbcd 1667 case 'c':
a1c7c0f3
ILT		 1668 if (opP->mode != CONTROL
1669 || (opP->reg != NC
1670 && opP->reg != IC
1671 && opP->reg != DC
1672 && opP->reg != BC))
355afbcd
KR		 1673 {
1674 losing++;
1675 } /* not a cache specifier. */
1676 break;
1677
1678 case '_':
1679 if (opP->mode != ABSL)
a1c7c0f3 1680 ++losing;
355afbcd 1681 break;
8be74775 1682
355afbcd 1683 default:
a1c7c0f3 1684 abort ();
355afbcd 1685 } /* switch on type of operand */
6d27d3a2 1686
355afbcd
KR		 1687 if (losing)
1688 break;
1689 } /* for each operand */
1690 } /* if immediately wrong */
6d27d3a2 1691
355afbcd
KR		 1692 if (!losing)
1693 {
8be74775 1694 break;
355afbcd 1695 } /* got it. */
6d27d3a2 1696
355afbcd 1697 opcode = opcode->m_next;
6d27d3a2 1698
355afbcd 1699 if (!opcode)
8be74775 1700 {
355afbcd
KR		 1701 if (ok_arch
1702 && !(ok_arch & current_architecture))
8be74775 1703 {
355afbcd 1704 char buf[200], *cp;
091221ce 1705
a1c7c0f3
ILT		 1706 strcpy (buf,
1707 "invalid instruction for this architecture; needs ");
355afbcd
KR		 1708 cp = buf + strlen (buf);
1709 switch (ok_arch)
1710 {
1711 case mfloat:
82489ea0 1712 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
355afbcd
KR		 1713 break;
1714 case mmmu:
1715 strcpy (cp, "mmu (68030 or 68851)");
1716 break;
1717 case m68020up:
1718 strcpy (cp, "68020 or higher");
1719 break;
1720 case m68000up:
1721 strcpy (cp, "68000 or higher");
1722 break;
1723 case m68010up:
1724 strcpy (cp, "68010 or higher");
1725 break;
1726 default:
8be74775 1727 {
355afbcd 1728 int got_one = 0, idx;
a1c7c0f3
ILT		 1729 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1730 idx++)
8be74775 1731 {
9e64486e
ILT		 1732 if ((archs[idx].arch & ok_arch)
1733 && ! archs[idx].alias)
8be74775 1734 {
355afbcd
KR		 1735 if (got_one)
1736 {
1737 strcpy (cp, " or ");
1738 cp += strlen (cp);
1739 }
1740 got_one = 1;
1741 strcpy (cp, archs[idx].name);
8be74775
KR		 1742 cp += strlen (cp);
1743 }
8be74775
KR		 1744 }
1745 }
355afbcd 1746 }
091221ce 1747 cp = xmalloc (strlen (buf) + 1);
355afbcd
KR		 1748 strcpy (cp, buf);
1749 the_ins.error = cp;
8be74775 1750 }
355afbcd
KR		 1751 else
1752 the_ins.error = "operands mismatch";
1753 return;
1754 } /* Fell off the end */
6d27d3a2 1755
355afbcd
KR		 1756 losing = 0;
1757 }
6d27d3a2
KR		 1758
1759 /* now assemble it */
1760
355afbcd
KR		 1761 the_ins.args = opcode->m_operands;
1762 the_ins.numargs = opcode->m_opnum;
1763 the_ins.numo = opcode->m_codenum;
1764 the_ins.opcode[0] = getone (opcode);
1765 the_ins.opcode[1] = gettwo (opcode);
6d27d3a2 1766
355afbcd
KR		 1767 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1768 {
1769 /* This switch is a doozy.
6d27d3a2 1770 Watch the first step; its a big one! */
355afbcd
KR		 1771 switch (s[0])
1772 {
6d27d3a2 1773
355afbcd
KR		 1774 case '*':
1775 case '~':
1776 case '%':
1777 case ';':
1778 case '@':
1779 case '!':
1780 case '&':
1781 case '$':
1782 case '?':
1783 case '/':
1784 case '`':
b4d51f3d
ILT		 1785 case '<':
1786 case '>':
1787 case 'm':
1788 case 'n':
1789 case 'o':
1790 case 'p':
355afbcd
KR		 1791#ifndef NO_68851
1792 case '|':
1793#endif
1794 switch (opP->mode)
1795 {
1796 case IMMED:
1797 tmpreg = 0x3c; /* 7.4 */
1798 if (strchr ("bwl", s[1]))
a1c7c0f3 1799 nextword = get_num (&opP->disp, 80);
355afbcd 1800 else
a1c7c0f3
ILT		 1801 nextword = get_num (&opP->disp, 0);
1802 if (isvar (&opP->disp))
1803 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 1804 switch (s[1])
1805 {
1806 case 'b':
1807 if (!isbyte (nextword))
1808 opP->error = "operand out of range";
1809 addword (nextword);
1810 baseo = 0;
1811 break;
1812 case 'w':
1813 if (!isword (nextword))
1814 opP->error = "operand out of range";
1815 addword (nextword);
1816 baseo = 0;
1817 break;
9e64486e
ILT		 1818 case 'W':
1819 if (!issword (nextword))
1820 opP->error = "operand out of range";
1821 addword (nextword);
1822 baseo = 0;
1823 break;
355afbcd
KR		 1824 case 'l':
1825 addword (nextword >> 16);
1826 addword (nextword);
1827 baseo = 0;
1828 break;
1829
1830 case 'f':
1831 baseo = 2;
1832 outro = 8;
1833 break;
1834 case 'F':
1835 baseo = 4;
1836 outro = 11;
1837 break;
1838 case 'x':
1839 baseo = 6;
1840 outro = 15;
1841 break;
1842 case 'p':
1843 baseo = 6;
1844 outro = -1;
1845 break;
1846 default:
a1c7c0f3 1847 abort ();
355afbcd
KR		 1848 }
1849 if (!baseo)
1850 break;
6d27d3a2 1851
355afbcd 1852 /* We gotta put out some float */
a1c7c0f3 1853 if (op (&opP->disp) != O_big)
355afbcd 1854 {
bcb8dff8
KR		 1855 valueT val;
1856 int gencnt;
1857
1858 /* Can other cases happen here? */
a1c7c0f3 1859 if (op (&opP->disp) != O_constant)
bcb8dff8 1860 abort ();
82489ea0 1861
a1c7c0f3 1862 val = (valueT) offs (&opP->disp);
bcb8dff8
KR		 1863 gencnt = 0;
1864 do
1865 {
1866 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1867 val >>= LITTLENUM_NUMBER_OF_BITS;
1868 ++gencnt;
1869 }
1870 while (val != 0);
a1c7c0f3 1871 offs (&opP->disp) = gencnt;
355afbcd 1872 }
a1c7c0f3 1873 if (offs (&opP->disp) > 0)
355afbcd 1874 {
a1c7c0f3 1875 if (offs (&opP->disp) > baseo)
355afbcd 1876 {
a1c7c0f3
ILT		 1877 as_warn ("Bignum too big for %c format; truncated",
1878 s[1]);
1879 offs (&opP->disp) = baseo;
355afbcd 1880 }
a1c7c0f3 1881 baseo -= offs (&opP->disp);
355afbcd
KR		 1882 while (baseo--)
1883 addword (0);
a1c7c0f3
ILT		 1884 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1885 offs (&opP->disp)--;
1886 --wordp)
bcb8dff8 1887 addword (*wordp);
355afbcd
KR		 1888 break;
1889 }
1890 gen_to_words (words, baseo, (long) outro);
1891 for (wordp = words; baseo--; wordp++)
1892 addword (*wordp);
1893 break;
1894 case DREG:
1895 tmpreg = opP->reg - DATA; /* 0.dreg */
1896 break;
1897 case AREG:
1898 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1899 break;
1900 case AINDR:
1901 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1902 break;
1903 case ADEC:
1904 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1905 break;
1906 case AINC:
1907 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1908 break;
a1c7c0f3 1909 case DISP:
6d27d3a2 1910
a1c7c0f3 1911 nextword = get_num (&opP->disp, 80);
6700d36e
ILT		 1912
1913 if (opP->reg == PC
1914 && ! isvar (&opP->disp)
1915 && m68k_abspcadd)
1916 {
1917 opP->disp.exp.X_op = O_symbol;
1918#ifndef BFD_ASSEMBLER
1919 opP->disp.exp.X_add_symbol = &abs_symbol;
1920#else
1921 opP->disp.exp.X_add_symbol =
1922 section_symbol (absolute_section);
1923#endif
1924 }
1925
355afbcd 1926 /* Force into index mode. Hope this works */
6d27d3a2 1927
1404ef23
KR		 1928 /* We do the first bit for 32-bit displacements, and the
1929 second bit for 16 bit ones. It is possible that we
1930 should make the default be WORD instead of LONG, but
1931 I think that'd break GCC, so we put up with a little
1932 inefficiency for the sake of working output. */
6d27d3a2 1933
355afbcd 1934 if (!issword (nextword)
a1c7c0f3
ILT		 1935 || (isvar (&opP->disp)
1936 && ((opP->disp.size == SIZE_UNSPEC
b79de3a1
KR		 1937 && flag_short_refs == 0
1938 && cpu_of_arch (current_architecture) >= m68020)
a1c7c0f3 1939 || opP->disp.size == SIZE_LONG)))
355afbcd 1940 {
912e4245
ILT		 1941 if (cpu_of_arch (current_architecture) < m68020)
1942 opP->error =
1943 "displacement too large for this architecture; needs 68020 or higher";
355afbcd
KR		 1944 if (opP->reg == PC)
1945 tmpreg = 0x3B; /* 7.3 */
1946 else
1947 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
a1c7c0f3 1948 if (isvar (&opP->disp))
355afbcd
KR		 1949 {
1950 if (opP->reg == PC)
1951 {
a043f579
ILT		 1952 if (opP->disp.size == SIZE_LONG
1953#ifdef OBJ_ELF
1954 /* If the displacement needs pic
1955 relocation it cannot be relaxed. */
1956 || opP->disp.pic_reloc != pic_none
04ef74bb 1957#endif
a043f579
ILT		 1958 )
1959 {
1960 addword (0x0170);
1961 add_fix ('l', &opP->disp, 1, 2);
1962 }
1963 else
1964 {
1965 add_frag (adds (&opP->disp),
1966 offs (&opP->disp),
1967 TAB (PCLEA, SZ_UNDEF));
1968 break;
1969 }
355afbcd
KR		 1970 }
1971 else
1972 {
1973 addword (0x0170);
a1c7c0f3 1974 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 1975 }
1976 }
1977 else
1978 addword (0x0170);
1979 addword (nextword >> 16);
1980 }
1981 else
1982 {
1983 if (opP->reg == PC)
1984 tmpreg = 0x3A; /* 7.2 */
1985 else
1986 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1987
a1c7c0f3 1988 if (isvar (&opP->disp))
355afbcd
KR		 1989 {
1990 if (opP->reg == PC)
1991 {
a1c7c0f3 1992 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 1993 }
1994 else
a1c7c0f3 1995 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 1996 }
1997 }
1998 addword (nextword);
6d27d3a2 1999 break;
6d27d3a2 2000
a1c7c0f3
ILT		 2001 case POST:
2002 case PRE:
2003 case BASE:
355afbcd 2004 nextword = 0;
a1c7c0f3
ILT		 2005 baseo = get_num (&opP->disp, 80);
2006 if (opP->mode == POST || opP->mode == PRE)
2007 outro = get_num (&opP->odisp, 80);
49864cfa
KR		 2008 /* Figure out the `addressing mode'.
2009 Also turn on the BASE_DISABLE bit, if needed. */
355afbcd
KR		 2010 if (opP->reg == PC || opP->reg == ZPC)
2011 {
a1c7c0f3 2012 tmpreg = 0x3b; /* 7.3 */
355afbcd
KR		 2013 if (opP->reg == ZPC)
2014 nextword |= 0x80;
2015 }
a1c7c0f3
ILT		 2016 else if (opP->reg == 0)
2017 {
2018 nextword |= 0x80;
2019 tmpreg = 0x30; /* 6.garbage */
2020 }
2021 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
355afbcd
KR		 2022 {
2023 nextword |= 0x80;
a1c7c0f3 2024 tmpreg = 0x30 + opP->reg - ZADDR0;
355afbcd
KR		 2025 }
2026 else
2027 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2028
a1c7c0f3
ILT		 2029 siz1 = opP->disp.size;
2030 if (opP->mode == POST || opP->mode == PRE)
2031 siz2 = opP->odisp.size;
2032 else
2033 siz2 = SIZE_UNSPEC;
355afbcd
KR		 2034
2035 /* Index register stuff */
a1c7c0f3
ILT		 2036 if (opP->index.reg != 0
2037 && opP->index.reg >= DATA
2038 && opP->index.reg <= ADDR7)
355afbcd 2039 {
a1c7c0f3 2040 nextword |= (opP->index.reg - DATA) << 12;
355afbcd 2041
b4d51f3d
ILT		 2042 if (opP->index.size == SIZE_LONG
2043 || (opP->index.size == SIZE_UNSPEC
2044 && m68k_index_width_default == SIZE_LONG))
355afbcd 2045 nextword |= 0x800;
a1c7c0f3 2046
8d20a0a8
C		 2047 if ((opP->index.scale != 1
2048 && cpu_of_arch (current_architecture) < m68020)
2049 || (opP->index.scale == 8
2050 && current_architecture == mcf5200))
a1c7c0f3 2051 {
8d20a0a8
C		 2052 opP->error =
2053 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
a1c7c0f3
ILT		 2054 }
2055
2056 switch (opP->index.scale)
355afbcd
KR		 2057 {
2058 case 1:
2059 break;
2060 case 2:
2061 nextword |= 0x200;
2062 break;
2063 case 4:
2064 nextword |= 0x400;
2065 break;
2066 case 8:
2067 nextword |= 0x600;
2068 break;
2069 default:
a1c7c0f3 2070 abort ();
355afbcd
KR		 2071 }
2072 /* IF its simple,
49864cfa 2073 GET US OUT OF HERE! */
6d27d3a2 2074
04ef74bb
KR		 2075 /* Must be INDEX, with an index register. Address
2076 register cannot be ZERO-PC, and either :b was
2077 forced, or we know it will fit. For a 68000 or
2078 68010, force this mode anyways, because the
2079 larger modes aren't supported. */
a1c7c0f3
ILT		 2080 if (opP->mode == BASE
2081 && ((opP->reg >= ADDR0
2082 && opP->reg <= ADDR7)
2083 || opP->reg == PC))
355afbcd 2084 {
a1c7c0f3
ILT		 2085 if (siz1 == SIZE_BYTE
2086 || cpu_of_arch (current_architecture) < m68020
2087 || (siz1 == SIZE_UNSPEC
2088 && ! isvar (&opP->disp)
2089 && issbyte (baseo)))
2090 {
5f8cb05e
ILT		 2091 nextword += baseo & 0xff;
2092 addword (nextword);
a1c7c0f3 2093 if (isvar (&opP->disp))
04ef74bb 2094 {
a1c7c0f3
ILT		 2095 /* Do a byte relocation. If it doesn't
2096 fit (possible on m68000) let the
2097 fixup processing complain later. */
5f8cb05e 2098 if (opP->reg == PC)
a1c7c0f3 2099 add_fix ('B', &opP->disp, 1, 1);
5f8cb05e 2100 else
a1c7c0f3 2101 add_fix ('B', &opP->disp, 0, 0);
04ef74bb 2102 }
a1c7c0f3
ILT		 2103 else if (siz1 != SIZE_BYTE)
2104 {
2105 if (siz1 != SIZE_UNSPEC)
2106 as_warn ("Forcing byte displacement");
2107 if (! issbyte (baseo))
2108 opP->error = "byte displacement out of range";
2109 }
2110
2111 break;
2112 }
2113 else if (siz1 == SIZE_UNSPEC
2114 && opP->reg == PC
2115 && isvar (&opP->disp)
a043f579
ILT		 2116 && subs (&opP->disp) == NULL
2117#ifdef OBJ_ELF
2118 /* If the displacement needs pic
2119 relocation it cannot be relaxed. */
2120 && opP->disp.pic_reloc == pic_none
2121#endif
2122 )
a1c7c0f3 2123 {
2156d0d7
ILT		 2124 /* The code in md_convert_frag_1 needs to be
2125 able to adjust nextword. Call frag_grow
2126 to ensure that we have enough space in
2127 the frag obstack to make all the bytes
2128 contiguous. */
2129 frag_grow (14);
5f8cb05e
ILT		 2130 nextword += baseo & 0xff;
2131 addword (nextword);
a1c7c0f3 2132 add_frag (adds (&opP->disp), offs (&opP->disp),
5f8cb05e 2133 TAB (PCINDEX, SZ_UNDEF));
a1c7c0f3
ILT		 2134
2135 break;
5f8cb05e 2136 }
355afbcd
KR		 2137 }
2138 }
2139 else
a1c7c0f3
ILT		 2140 {
2141 nextword |= 0x40; /* No index reg */
2142 if (opP->index.reg >= ZDATA0
2143 && opP->index.reg <= ZDATA7)
2144 nextword |= (opP->index.reg - ZDATA0) << 12;
2145 else if (opP->index.reg >= ZADDR0
2146 || opP->index.reg <= ZADDR7)
2147 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2148 }
6d27d3a2 2149
49864cfa 2150 /* It isn't simple. */
a1c7c0f3
ILT		 2151
2152 if (cpu_of_arch (current_architecture) < m68020)
2153 opP->error =
2154 "invalid operand mode for this architecture; needs 68020 or higher";
2155
355afbcd 2156 nextword |= 0x100;
49864cfa
KR		 2157 /* If the guy specified a width, we assume that it is
2158 wide enough. Maybe it isn't. If so, we lose. */
355afbcd
KR		 2159 switch (siz1)
2160 {
a1c7c0f3 2161 case SIZE_UNSPEC:
6700d36e
ILT		 2162 if (isvar (&opP->disp)
2163 ? m68k_rel32
2164 : ! issword (baseo))
355afbcd 2165 {
a1c7c0f3 2166 siz1 = SIZE_LONG;
355afbcd
KR		 2167 nextword |= 0x30;
2168 }
6700d36e 2169 else if (! isvar (&opP->disp) && baseo == 0)
355afbcd
KR		 2170 nextword |= 0x10;
2171 else
2172 {
2173 nextword |= 0x20;
a1c7c0f3 2174 siz1 = SIZE_WORD;
355afbcd
KR		 2175 }
2176 break;
a1c7c0f3
ILT		 2177 case SIZE_BYTE:
2178 as_warn (":b not permitted; defaulting to :w");
2179 /* Fall through. */
2180 case SIZE_WORD:
355afbcd
KR		 2181 nextword |= 0x20;
2182 break;
a1c7c0f3 2183 case SIZE_LONG:
355afbcd
KR		 2184 nextword |= 0x30;
2185 break;
2186 }
6d27d3a2 2187
355afbcd 2188 /* Figure out innner displacement stuff */
a1c7c0f3 2189 if (opP->mode == POST || opP->mode == PRE)
355afbcd 2190 {
8d20a0a8
C		 2191 if (cpu_of_arch (current_architecture) & cpu32)
2192 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
355afbcd
KR		 2193 switch (siz2)
2194 {
a1c7c0f3 2195 case SIZE_UNSPEC:
6700d36e
ILT		 2196 if (isvar (&opP->odisp)
2197 ? m68k_rel32
2198 : ! issword (outro))
355afbcd 2199 {
a1c7c0f3 2200 siz2 = SIZE_LONG;
355afbcd
KR		 2201 nextword |= 0x3;
2202 }
92a25e12 2203 else if (! isvar (&opP->odisp) && outro == 0)
355afbcd
KR		 2204 nextword |= 0x1;
2205 else
2206 {
2207 nextword |= 0x2;
a1c7c0f3 2208 siz2 = SIZE_WORD;
355afbcd
KR		 2209 }
2210 break;
2211 case 1:
a1c7c0f3
ILT		 2212 as_warn (":b not permitted; defaulting to :w");
2213 /* Fall through. */
355afbcd
KR		 2214 case 2:
2215 nextword |= 0x2;
2216 break;
2217 case 3:
2218 nextword |= 0x3;
2219 break;
2220 }
92a25e12
ILT		 2221 if (opP->mode == POST
2222 && (nextword & 0x40) == 0)
355afbcd 2223 nextword |= 0x04;
355afbcd
KR		 2224 }
2225 addword (nextword);
2226
a1c7c0f3 2227 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
355afbcd
KR		 2228 {
2229 if (opP->reg == PC || opP->reg == ZPC)
a1c7c0f3 2230 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
355afbcd 2231 else
a1c7c0f3 2232 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
355afbcd 2233 }
a1c7c0f3 2234 if (siz1 == SIZE_LONG)
355afbcd 2235 addword (baseo >> 16);
a1c7c0f3 2236 if (siz1 != SIZE_UNSPEC)
355afbcd
KR		 2237 addword (baseo);
2238
a1c7c0f3
ILT		 2239 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2240 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2241 if (siz2 == SIZE_LONG)
355afbcd 2242 addword (outro >> 16);
a1c7c0f3 2243 if (siz2 != SIZE_UNSPEC)
355afbcd 2244 addword (outro);
6d27d3a2 2245
355afbcd 2246 break;
6d27d3a2 2247
355afbcd 2248 case ABSL:
a1c7c0f3
ILT		 2249 nextword = get_num (&opP->disp, 80);
2250 switch (opP->disp.size)
355afbcd
KR		 2251 {
2252 default:
a1c7c0f3
ILT		 2253 abort ();
2254 case SIZE_UNSPEC:
2255 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
355afbcd
KR		 2256 {
2257 tmpreg = 0x38; /* 7.0 */
2258 addword (nextword);
2259 break;
2260 }
bcb8dff8
KR		 2261 /* Don't generate pc relative code on 68010 and
2262 68000. */
a1c7c0f3
ILT		 2263 if (isvar (&opP->disp)
2264 && !subs (&opP->disp)
2265 && adds (&opP->disp)
a043f579
ILT		 2266#ifdef OBJ_ELF
2267 /* If the displacement needs pic relocation it
2268 cannot be relaxed. */
2269 && opP->disp.pic_reloc == pic_none
2270#endif
f00f5ecd 2271 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
ffecfc8b 2272 && HAVE_LONG_BRANCH(current_architecture)
9ad5755f 2273 && !flag_long_jumps
355afbcd
KR		 2274 && !strchr ("~%&$?", s[0]))
2275 {
2276 tmpreg = 0x3A; /* 7.2 */
a1c7c0f3
ILT		 2277 add_frag (adds (&opP->disp),
2278 offs (&opP->disp),
355afbcd
KR		 2279 TAB (PCREL, SZ_UNDEF));
2280 break;
2281 }
04ef74bb 2282 /* Fall through into long */
a1c7c0f3
ILT		 2283 case SIZE_LONG:
2284 if (isvar (&opP->disp))
2285 add_fix ('l', &opP->disp, 0, 0);
355afbcd
KR		 2286
2287 tmpreg = 0x39;/* 7.1 mode */
2288 addword (nextword >> 16);
2289 addword (nextword);
2290 break;
2291
a1c7c0f3
ILT		 2292 case SIZE_WORD: /* Word */
2293 if (isvar (&opP->disp))
2294 add_fix ('w', &opP->disp, 0, 0);
355afbcd
KR		 2295
2296 tmpreg = 0x38;/* 7.0 mode */
2297 addword (nextword);
2298 break;
2299 }
2300 break;
a1c7c0f3
ILT		 2301 case CONTROL:
2302 case FPREG:
355afbcd
KR		 2303 default:
2304 as_bad ("unknown/incorrect operand");
2305 /* abort(); */
2306 }
2307 install_gen_operand (s[1], tmpreg);
6d27d3a2 2308 break;
6d27d3a2 2309
355afbcd
KR		 2310 case '#':
2311 case '^':
2312 switch (s[1])
2313 { /* JF: I hate floating point! */
2314 case 'j':
2315 tmpreg = 70;
2316 break;
2317 case '8':
2318 tmpreg = 20;
2319 break;
2320 case 'C':
2321 tmpreg = 50;
2322 break;
2323 case '3':
2324 default:
2325 tmpreg = 80;
2326 break;
2327 }
a1c7c0f3
ILT		 2328 tmpreg = get_num (&opP->disp, tmpreg);
2329 if (isvar (&opP->disp))
2330 add_fix (s[1], &opP->disp, 0, 0);
355afbcd
KR		 2331 switch (s[1])
2332 {
2333 case 'b': /* Danger: These do no check for
6d27d3a2
KR		 2334 certain types of overflow.
2335 user beware! */
355afbcd
KR		 2336 if (!isbyte (tmpreg))
2337 opP->error = "out of range";
bcb8dff8 2338 insop (tmpreg, opcode);
a1c7c0f3 2339 if (isvar (&opP->disp))
d9396c16
ILT		 2340 the_ins.reloc[the_ins.nrel - 1].n =
2341 (opcode->m_codenum) * 2 + 1;
355afbcd 2342 break;
a78bc551
ILT		 2343 case 'B':
2344 if (!issbyte (tmpreg))
2345 opP->error = "out of range";
2346 opcode->m_opcode |= tmpreg;
2347 if (isvar (&opP->disp))
2348 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2349 break;
355afbcd
KR		 2350 case 'w':
2351 if (!isword (tmpreg))
2352 opP->error = "out of range";
bcb8dff8 2353 insop (tmpreg, opcode);
a1c7c0f3 2354 if (isvar (&opP->disp))
355afbcd
KR		 2355 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2356 break;
9e64486e
ILT		 2357 case 'W':
2358 if (!issword (tmpreg))
2359 opP->error = "out of range";
2360 insop (tmpreg, opcode);
2361 if (isvar (&opP->disp))
2362 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2363 break;
355afbcd 2364 case 'l':
bcb8dff8
KR		 2365 /* Because of the way insop works, we put these two out
2366 backwards. */
2367 insop (tmpreg, opcode);
2368 insop (tmpreg >> 16, opcode);
a1c7c0f3 2369 if (isvar (&opP->disp))
355afbcd
KR		 2370 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2371 break;
2372 case '3':
2373 tmpreg &= 0xFF;
2374 case '8':
2375 case 'C':
af438bdb 2376 case 'j':
355afbcd
KR		 2377 install_operand (s[1], tmpreg);
2378 break;
2379 default:
a1c7c0f3 2380 abort ();
355afbcd
KR		 2381 }
2382 break;
6d27d3a2 2383
355afbcd
KR		 2384 case '+':
2385 case '-':
2386 case 'A':
2387 case 'a':
2388 install_operand (s[1], opP->reg - ADDR);
2389 break;
6d27d3a2 2390
355afbcd 2391 case 'B':
a1c7c0f3 2392 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2393 switch (s[1])
2394 {
2395 case 'B':
b4ec75e0
ILT		 2396 /* The pc_fix argument winds up in fx_pcrel_adjust,
2397 which is a char, and may therefore be unsigned. We
2398 want to pass -1, but we pass 64 instead, and convert
2399 back in md_pcrel_from. */
2400 add_fix ('B', &opP->disp, 1, 64);
355afbcd
KR		 2401 break;
2402 case 'W':
a1c7c0f3 2403 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 2404 addword (0);
2405 break;
2406 case 'L':
2407 long_branch:
ffecfc8b
C		 2408 if (!HAVE_LONG_BRANCH(current_architecture))
2409 as_warn ("Can't use long branches on 68000/68010/5200");
355afbcd 2410 the_ins.opcode[the_ins.numo - 1] |= 0xff;
a1c7c0f3 2411 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2412 addword (0);
2413 addword (0);
2414 break;
2415 case 'g':
a1c7c0f3 2416 if (subs (&opP->disp)) /* We can't relax it */
355afbcd 2417 goto long_branch;
6d27d3a2 2418
a043f579
ILT		 2419#ifdef OBJ_ELF
2420 /* If the displacement needs pic relocation it cannot be
2421 relaxed. */
2422 if (opP->disp.pic_reloc != pic_none)
2423 goto long_branch;
2424#endif
2425
a1c7c0f3
ILT		 2426 /* This could either be a symbol, or an absolute
2427 address. No matter, the frag hacking will finger it
2428 out. Not quite: it can't switch from BRANCH to
2429 BCC68000 for the case where opnd is absolute (it
2430 needs to use the 68000 hack since no conditional abs
2431 jumps). */
ffecfc8b 2432 if (( !HAVE_LONG_BRANCH(current_architecture)
a1c7c0f3 2433 || (0 == adds (&opP->disp)))
355afbcd
KR		 2434 && (the_ins.opcode[0] >= 0x6200)
2435 && (the_ins.opcode[0] <= 0x6f00))
a1c7c0f3
ILT		 2436 add_frag (adds (&opP->disp), offs (&opP->disp),
2437 TAB (BCC68000, SZ_UNDEF));
355afbcd 2438 else
a1c7c0f3
ILT		 2439 add_frag (adds (&opP->disp), offs (&opP->disp),
2440 TAB (ABRANCH, SZ_UNDEF));
355afbcd
KR		 2441 break;
2442 case 'w':
a1c7c0f3 2443 if (isvar (&opP->disp))
355afbcd 2444 {
49864cfa 2445#if 1
355afbcd
KR		 2446 /* check for DBcc instruction */
2447 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2448 {
2449 /* size varies if patch */
2450 /* needed for long form */
a1c7c0f3 2451 add_frag (adds (&opP->disp), offs (&opP->disp),
b79de3a1 2452 TAB (DBCC, SZ_UNDEF));
355afbcd
KR		 2453 break;
2454 }
49864cfa 2455#endif
a1c7c0f3 2456 add_fix ('w', &opP->disp, 1, 0);
355afbcd
KR		 2457 }
2458 addword (0);
2459 break;
2460 case 'C': /* Fixed size LONG coproc branches */
a1c7c0f3 2461 add_fix ('l', &opP->disp, 1, 0);
355afbcd
KR		 2462 addword (0);
2463 addword (0);
2464 break;
2465 case 'c': /* Var size Coprocesssor branches */
a1c7c0f3 2466 if (subs (&opP->disp))
355afbcd 2467 {
a1c7c0f3 2468 add_fix ('l', &opP->disp, 1, 0);
f59fb6ca 2469 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
355afbcd 2470 }
a1c7c0f3
ILT		 2471 else if (adds (&opP->disp))
2472 add_frag (adds (&opP->disp), offs (&opP->disp),
2473 TAB (FBRANCH, SZ_UNDEF));
355afbcd
KR		 2474 else
2475 {
f59fb6ca
ILT		 2476 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2477 TAB(FBRANCH,SHORT)); */
355afbcd 2478 the_ins.opcode[the_ins.numo - 1] |= 0x40;
a1c7c0f3 2479 add_fix ('l', &opP->disp, 1, 0);
5f8cb05e 2480 addword (0);
355afbcd 2481 addword (0);
355afbcd
KR		 2482 }
2483 break;
2484 default:
a1c7c0f3 2485 abort ();
355afbcd
KR		 2486 }
2487 break;
6d27d3a2 2488
355afbcd
KR		 2489 case 'C': /* Ignore it */
2490 break;
6d27d3a2 2491
355afbcd 2492 case 'd': /* JF this is a kludge */
a1c7c0f3
ILT		 2493 install_operand ('s', opP->reg - ADDR);
2494 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2495 if (!issword (tmpreg))
2496 {
2497 as_warn ("Expression out of range, using 0");
2498 tmpreg = 0;
2499 }
2500 addword (tmpreg);
2501 break;
6d27d3a2 2502
355afbcd
KR		 2503 case 'D':
2504 install_operand (s[1], opP->reg - DATA);
2505 break;
6d27d3a2 2506
355afbcd 2507 case 'F':
a1c7c0f3 2508 install_operand (s[1], opP->reg - FP0);
355afbcd 2509 break;
6d27d3a2 2510
355afbcd 2511 case 'I':
27a53b88 2512 tmpreg = opP->reg - COP0;
355afbcd
KR		 2513 install_operand (s[1], tmpreg);
2514 break;
6d27d3a2 2515
355afbcd
KR		 2516 case 'J': /* JF foo */
2517 switch (opP->reg)
2518 {
2519 case SFC:
2520 tmpreg = 0x000;
2521 break;
2522 case DFC:
2523 tmpreg = 0x001;
2524 break;
2525 case CACR:
2526 tmpreg = 0x002;
2527 break;
2528 case TC:
2529 tmpreg = 0x003;
2530 break;
2531 case ITT0:
2532 tmpreg = 0x004;
2533 break;
2534 case ITT1:
2535 tmpreg = 0x005;
2536 break;
2537 case DTT0:
2538 tmpreg = 0x006;
2539 break;
2540 case DTT1:
2541 tmpreg = 0x007;
2542 break;
9ad5755f
KR		 2543 case BUSCR:
2544 tmpreg = 0x008;
2545 break;
6d27d3a2 2546
355afbcd
KR		 2547 case USP:
2548 tmpreg = 0x800;
2549 break;
2550 case VBR:
2551 tmpreg = 0x801;
2552 break;
2553 case CAAR:
2554 tmpreg = 0x802;
2555 break;
2556 case MSP:
2557 tmpreg = 0x803;
2558 break;
2559 case ISP:
2560 tmpreg = 0x804;
2561 break;
2562 case MMUSR:
2563 tmpreg = 0x805;
2564 break;
2565 case URP:
2566 tmpreg = 0x806;
2567 break;
2568 case SRP:
2569 tmpreg = 0x807;
2570 break;
9ad5755f
KR		 2571 case PCR:
2572 tmpreg = 0x808;
2573 break;
8d20a0a8
C		 2574 case ROMBAR:
2575 tmpreg = 0xC00;
2576 break;
2577 case RAMBAR0:
2578 tmpreg = 0xC04;
2579 break;
2580 case RAMBAR1:
2581 tmpreg = 0xC05;
2582 break;
2583 case MBAR:
2584 tmpreg = 0xC0F;
2585 break;
355afbcd 2586 default:
a1c7c0f3 2587 abort ();
355afbcd
KR		 2588 }
2589 install_operand (s[1], tmpreg);
2590 break;
6d27d3a2 2591
355afbcd 2592 case 'k':
a1c7c0f3 2593 tmpreg = get_num (&opP->disp, 55);
355afbcd
KR		 2594 install_operand (s[1], tmpreg & 0x7f);
2595 break;
6d27d3a2 2596
355afbcd 2597 case 'l':
a1c7c0f3 2598 tmpreg = opP->mask;
355afbcd
KR		 2599 if (s[1] == 'w')
2600 {
2601 if (tmpreg & 0x7FF0000)
2602 as_bad ("Floating point register in register list");
bcb8dff8 2603 insop (reverse_16_bits (tmpreg), opcode);
355afbcd
KR		 2604 }
2605 else
2606 {
2607 if (tmpreg & 0x700FFFF)
2608 as_bad ("Wrong register in floating-point reglist");
2609 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2610 }
2611 break;
6d27d3a2 2612
355afbcd 2613 case 'L':
a1c7c0f3 2614 tmpreg = opP->mask;
355afbcd
KR		 2615 if (s[1] == 'w')
2616 {
2617 if (tmpreg & 0x7FF0000)
2618 as_bad ("Floating point register in register list");
bcb8dff8 2619 insop (tmpreg, opcode);
355afbcd
KR		 2620 }
2621 else if (s[1] == '8')
2622 {
2623 if (tmpreg & 0x0FFFFFF)
2624 as_bad ("incorrect register in reglist");
2625 install_operand (s[1], tmpreg >> 24);
2626 }
2627 else
2628 {
2629 if (tmpreg & 0x700FFFF)
2630 as_bad ("wrong register in floating-point reglist");
2631 else
2632 install_operand (s[1], tmpreg >> 16);
2633 }
2634 break;
6d27d3a2 2635
355afbcd 2636 case 'M':
a1c7c0f3 2637 install_operand (s[1], get_num (&opP->disp, 60));
355afbcd 2638 break;
6d27d3a2 2639
355afbcd 2640 case 'O':
a1c7c0f3
ILT		 2641 tmpreg = ((opP->mode == DREG)
2642 ? 0x20 + opP->reg - DATA
2643 : (get_num (&opP->disp, 40) & 0x1F));
355afbcd
KR		 2644 install_operand (s[1], tmpreg);
2645 break;
6d27d3a2 2646
355afbcd 2647 case 'Q':
a1c7c0f3 2648 tmpreg = get_num (&opP->disp, 10);
355afbcd
KR		 2649 if (tmpreg == 8)
2650 tmpreg = 0;
2651 install_operand (s[1], tmpreg);
2652 break;
2653
2654 case 'R':
a1c7c0f3
ILT		 2655 /* This depends on the fact that ADDR registers are eight
2656 more than their corresponding DATA regs, so the result
2657 will have the ADDR_REG bit set */
355afbcd
KR		 2658 install_operand (s[1], opP->reg - DATA);
2659 break;
6d27d3a2 2660
a1c7c0f3
ILT		 2661 case 'r':
2662 if (opP->mode == AINDR)
2663 install_operand (s[1], opP->reg - DATA);
2664 else
2665 install_operand (s[1], opP->index.reg - DATA);
2666 break;
2667
355afbcd
KR		 2668 case 's':
2669 if (opP->reg == FPI)
2670 tmpreg = 0x1;
2671 else if (opP->reg == FPS)
2672 tmpreg = 0x2;
2673 else if (opP->reg == FPC)
2674 tmpreg = 0x4;
2675 else
a1c7c0f3 2676 abort ();
355afbcd
KR		 2677 install_operand (s[1], tmpreg);
2678 break;
6d27d3a2 2679
355afbcd
KR		 2680 case 'S': /* Ignore it */
2681 break;
6d27d3a2 2682
355afbcd 2683 case 'T':
a1c7c0f3 2684 install_operand (s[1], get_num (&opP->disp, 30));
355afbcd 2685 break;
6d27d3a2 2686
355afbcd
KR		 2687 case 'U': /* Ignore it */
2688 break;
6d27d3a2 2689
355afbcd
KR		 2690 case 'c':
2691 switch (opP->reg)
2692 {
2693 case NC:
2694 tmpreg = 0;
2695 break;
2696 case DC:
2697 tmpreg = 1;
2698 break;
2699 case IC:
2700 tmpreg = 2;
2701 break;
2702 case BC:
2703 tmpreg = 3;
2704 break;
2705 default:
2706 as_fatal ("failed sanity check");
2707 } /* switch on cache token */
2708 install_operand (s[1], tmpreg);
2709 break;
a39116f1 2710#ifndef NO_68851
355afbcd
KR		 2711 /* JF: These are out of order, I fear. */
2712 case 'f':
2713 switch (opP->reg)
2714 {
2715 case SFC:
2716 tmpreg = 0;
2717 break;
2718 case DFC:
2719 tmpreg = 1;
2720 break;
2721 default:
a1c7c0f3 2722 abort ();
355afbcd
KR		 2723 }
2724 install_operand (s[1], tmpreg);
2725 break;
6d27d3a2 2726
9adcd781
ILT		 2727 case '0':
2728 case '1':
2729 case '2':
355afbcd
KR		 2730 switch (opP->reg)
2731 {
2732 case TC:
2733 tmpreg = 0;
2734 break;
2735 case CAL:
2736 tmpreg = 4;
2737 break;
2738 case VAL:
2739 tmpreg = 5;
2740 break;
2741 case SCC:
2742 tmpreg = 6;
2743 break;
2744 case AC:
2745 tmpreg = 7;
2746 break;
2747 default:
a1c7c0f3 2748 abort ();
355afbcd
KR		 2749 }
2750 install_operand (s[1], tmpreg);
2751 break;
6d27d3a2 2752
355afbcd
KR		 2753 case 'V':
2754 if (opP->reg == VAL)
2755 break;
a1c7c0f3 2756 abort ();
6d27d3a2 2757
355afbcd
KR		 2758 case 'W':
2759 switch (opP->reg)
2760 {
355afbcd
KR		 2761 case DRP:
2762 tmpreg = 1;
2763 break;
2764 case SRP:
2765 tmpreg = 2;
2766 break;
2767 case CRP:
2768 tmpreg = 3;
2769 break;
2770 default:
a1c7c0f3 2771 abort ();
355afbcd
KR		 2772 }
2773 install_operand (s[1], tmpreg);
2774 break;
6d27d3a2 2775
355afbcd
KR		 2776 case 'X':
2777 switch (opP->reg)
2778 {
2779 case BAD:
2780 case BAD + 1:
2781 case BAD + 2:
2782 case BAD + 3:
2783 case BAD + 4:
2784 case BAD + 5:
2785 case BAD + 6:
2786 case BAD + 7:
2787 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2788 break;
6d27d3a2 2789
355afbcd
KR		 2790 case BAC:
2791 case BAC + 1:
2792 case BAC + 2:
2793 case BAC + 3:
2794 case BAC + 4:
2795 case BAC + 5:
2796 case BAC + 6:
2797 case BAC + 7:
2798 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2799 break;
6d27d3a2 2800
355afbcd 2801 default:
a1c7c0f3 2802 abort ();
355afbcd
KR		 2803 }
2804 install_operand (s[1], tmpreg);
2805 break;
2806 case 'Y':
2807 know (opP->reg == PSR);
2808 break;
2809 case 'Z':
2810 know (opP->reg == PCSR);
2811 break;
f8701a3f 2812#endif /* m68851 */
355afbcd
KR		 2813 case '3':
2814 switch (opP->reg)
2815 {
2816 case TT0:
2817 tmpreg = 2;
2818 break;
2819 case TT1:
2820 tmpreg = 3;
2821 break;
2822 default:
a1c7c0f3 2823 abort ();
355afbcd
KR		 2824 }
2825 install_operand (s[1], tmpreg);
2826 break;
2827 case 't':
a1c7c0f3 2828 tmpreg = get_num (&opP->disp, 20);
355afbcd 2829 install_operand (s[1], tmpreg);
4134a793 2830 break;
a1c7c0f3
ILT		 2831 case '_': /* used only for move16 absolute 32-bit address */
2832 tmpreg = get_num (&opP->disp, 80);
355afbcd
KR		 2833 addword (tmpreg >> 16);
2834 addword (tmpreg & 0xFFFF);
4134a793
KR		 2835 break;
2836 default:
a1c7c0f3 2837 abort ();
4134a793 2838 }
6d27d3a2 2839 }
3ad9ec6a 2840
6d27d3a2
KR		 2841 /* By the time whe get here (FINALLY) the_ins contains the complete
2842 instruction, ready to be emitted. . . */
a1c7c0f3 2843}
fecd2382 2844
355afbcd
KR		 2845static int
2846reverse_16_bits (in)
2847 int in;
fecd2382 2848{
355afbcd
KR		 2849 int out = 0;
2850 int n;
6d27d3a2 2851
355afbcd
KR		 2852 static int mask[16] =
2853 {
2854 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2855 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2856 };
2857 for (n = 0; n < 16; n++)
2858 {
2859 if (in & mask[n])
2860 out |= mask[15 - n];
2861 }
2862 return out;
2863} /* reverse_16_bits() */
fecd2382 2864
355afbcd
KR		 2865static int
2866reverse_8_bits (in)
2867 int in;
fecd2382 2868{
355afbcd
KR		 2869 int out = 0;
2870 int n;
6d27d3a2 2871
355afbcd
KR		 2872 static int mask[8] =
2873 {
2874 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2875 };
6d27d3a2 2876
355afbcd
KR		 2877 for (n = 0; n < 8; n++)
2878 {
2879 if (in & mask[n])
2880 out |= mask[7 - n];
2881 }
2882 return out;
2883} /* reverse_8_bits() */
fecd2382 2884
04ef74bb
KR		 2885/* Cause an extra frag to be generated here, inserting up to 10 bytes
2886 (that value is chosen in the frag_var call in md_assemble). TYPE
2887 is the subtype of the frag to be generated; its primary type is
2888 rs_machine_dependent.
2889
2890 The TYPE parameter is also used by md_convert_frag_1 and
2891 md_estimate_size_before_relax. The appropriate type of fixup will
2892 be emitted by md_convert_frag_1.
2893
2894 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
355afbcd
KR		 2895static void
2896install_operand (mode, val)
2897 int mode;
2898 int val;
fecd2382 2899{
355afbcd
KR		 2900 switch (mode)
2901 {
2902 case 's':
2903 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2904 break;
2905 case 'd':
2906 the_ins.opcode[0] |= val << 9;
2907 break;
2908 case '1':
2909 the_ins.opcode[1] |= val << 12;
2910 break;
2911 case '2':
2912 the_ins.opcode[1] |= val << 6;
2913 break;
2914 case '3':
2915 the_ins.opcode[1] |= val;
2916 break;
2917 case '4':
2918 the_ins.opcode[2] |= val << 12;
2919 break;
2920 case '5':
2921 the_ins.opcode[2] |= val << 6;
2922 break;
2923 case '6':
bcb8dff8
KR		 2924 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2925 three words long! */
355afbcd
KR		 2926 the_ins.numo++;
2927 the_ins.opcode[2] |= val;
2928 break;
2929 case '7':
2930 the_ins.opcode[1] |= val << 7;
2931 break;
2932 case '8':
2933 the_ins.opcode[1] |= val << 10;
2934 break;
f8701a3f 2935#ifndef NO_68851
355afbcd
KR		 2936 case '9':
2937 the_ins.opcode[1] |= val << 5;
2938 break;
f8701a3f 2939#endif
6d27d3a2 2940
355afbcd
KR		 2941 case 't':
2942 the_ins.opcode[1] |= (val << 10) | (val << 7);
2943 break;
2944 case 'D':
2945 the_ins.opcode[1] |= (val << 12) | val;
2946 break;
2947 case 'g':
2948 the_ins.opcode[0] |= val = 0xff;
2949 break;
2950 case 'i':
2951 the_ins.opcode[0] |= val << 9;
2952 break;
2953 case 'C':
2954 the_ins.opcode[1] |= val;
2955 break;
2956 case 'j':
2957 the_ins.opcode[1] |= val;
2958 the_ins.numo++; /* What a hack */
2959 break;
2960 case 'k':
2961 the_ins.opcode[1] |= val << 4;
2962 break;
2963 case 'b':
2964 case 'w':
9e64486e 2965 case 'W':
355afbcd
KR		 2966 case 'l':
2967 break;
2968 case 'e':
2969 the_ins.opcode[0] |= (val << 6);
2970 break;
2971 case 'L':
2972 the_ins.opcode[1] = (val >> 16);
2973 the_ins.opcode[2] = val & 0xffff;
2974 break;
2975 case 'c':
2976 default:
2977 as_fatal ("failed sanity check.");
2978 }
2979} /* install_operand() */
fecd2382 2980
355afbcd
KR		 2981static void
2982install_gen_operand (mode, val)
2983 int mode;
2984 int val;
fecd2382 2985{
355afbcd
KR		 2986 switch (mode)
2987 {
2988 case 's':
2989 the_ins.opcode[0] |= val;
2990 break;
2991 case 'd':
2992 /* This is a kludge!!! */
2993 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2994 break;
2995 case 'b':
2996 case 'w':
2997 case 'l':
2998 case 'f':
2999 case 'F':
3000 case 'x':
3001 case 'p':
3002 the_ins.opcode[0] |= val;
3003 break;
3004 /* more stuff goes here */
3005 default:
3006 as_fatal ("failed sanity check.");
3007 }
3008} /* install_gen_operand() */
fecd2382 3009
7c15cbe8
RP		 3010/*
3011 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3012 * then deal with the bitfield hack.
3013 */
3014
355afbcd
KR		 3015static char *
3016crack_operand (str, opP)
3017 register char *str;
3018 register struct m68k_op *opP;
fecd2382 3019{
355afbcd
KR		 3020 register int parens;
3021 register int c;
3022 register char *beg_str;
4026c122 3023 int inquote = 0;
6d27d3a2 3024
355afbcd
KR		 3025 if (!str)
3026 {
3027 return str;
3028 }
3029 beg_str = str;
4026c122 3030 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
355afbcd 3031 {
4026c122 3032 if (! inquote)
355afbcd 3033 {
4026c122
ILT		 3034 if (*str == '(')
3035 parens++;
3036 else if (*str == ')')
3037 {
3038 if (!parens)
3039 { /* ERROR */
3040 opP->error = "Extra )";
3041 return str;
3042 }
3043 --parens;
355afbcd 3044 }
f8701a3f 3045 }
4026c122
ILT		 3046 if (flag_mri && *str == '\'')
3047 inquote = ! inquote;
355afbcd
KR		 3048 }
3049 if (!*str && parens)
3050 { /* ERROR */
3051 opP->error = "Missing )";
3052 return str;
3053 }
3054 c = *str;
3055 *str = '\0';
a1c7c0f3 3056 if (m68k_ip_op (beg_str, opP) != 0)
355afbcd
KR		 3057 {
3058 *str = c;
3059 return str;
3060 }
3061 *str = c;
3062 if (c == '}')
3063 c = *++str; /* JF bitfield hack */
3064 if (c)
3065 {
3066 c = *++str;
3067 if (!c)
3068 as_bad ("Missing operand");
3069 }
3070 return str;
fecd2382
RP		 3071}
3072
fecd2382 3073/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 3074 machine dependent instruction. This function is supposed to emit
fecd2382 3075 the frags/bytes it assembles to.
a39116f1 3076 */
a933d598
SC		 3077
3078void
355afbcd 3079insert_reg (regname, regnum)
f59fb6ca 3080 const char *regname;
355afbcd 3081 int regnum;
a933d598
SC		 3082{
3083 char buf[100];
3084 int i;
355afbcd
KR		 3085
3086#ifdef REGISTER_PREFIX
82489ea0
KR		 3087 if (!flag_reg_prefix_optional)
3088 {
3089 buf[0] = REGISTER_PREFIX;
3090 strcpy (buf + 1, regname);
3091 regname = buf;
3092 }
355afbcd
KR		 3093#endif
3094
82489ea0
KR		 3095 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3096 &zero_address_frag));
a933d598
SC		 3097
3098 for (i = 0; regname[i]; i++)
355afbcd 3099 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
a933d598 3100 buf[i] = '\0';
6d27d3a2 3101
82489ea0
KR		 3102 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3103 &zero_address_frag));
a933d598
SC		 3104}
3105
49864cfa 3106struct init_entry
355afbcd 3107 {
bcb8dff8 3108 const char *name;
355afbcd 3109 int number;
49864cfa 3110 };
355afbcd 3111
bcb8dff8 3112static const struct init_entry init_table[] =
355afbcd 3113{
bcb8dff8
KR		 3114 { "d0", DATA0 },
3115 { "d1", DATA1 },
3116 { "d2", DATA2 },
3117 { "d3", DATA3 },
3118 { "d4", DATA4 },
3119 { "d5", DATA5 },
3120 { "d6", DATA6 },
3121 { "d7", DATA7 },
3122 { "a0", ADDR0 },
3123 { "a1", ADDR1 },
3124 { "a2", ADDR2 },
3125 { "a3", ADDR3 },
3126 { "a4", ADDR4 },
3127 { "a5", ADDR5 },
3128 { "a6", ADDR6 },
3129 { "fp", ADDR6 },
3130 { "a7", ADDR7 },
3131 { "sp", ADDR7 },
a1c7c0f3 3132 { "ssp", ADDR7 },
bcb8dff8
KR		 3133 { "fp0", FP0 },
3134 { "fp1", FP1 },
3135 { "fp2", FP2 },
3136 { "fp3", FP3 },
3137 { "fp4", FP4 },
3138 { "fp5", FP5 },
3139 { "fp6", FP6 },
3140 { "fp7", FP7 },
3141 { "fpi", FPI },
3142 { "fpiar", FPI },
3143 { "fpc", FPI },
3144 { "fps", FPS },
3145 { "fpsr", FPS },
3146 { "fpc", FPC },
3147 { "fpcr", FPC },
064ba683
ILT		 3148 { "control", FPC },
3149 { "status", FPS },
3150 { "iaddr", FPI },
bcb8dff8
KR		 3151
3152 { "cop0", COP0 },
3153 { "cop1", COP1 },
3154 { "cop2", COP2 },
3155 { "cop3", COP3 },
3156 { "cop4", COP4 },
3157 { "cop5", COP5 },
3158 { "cop6", COP6 },
3159 { "cop7", COP7 },
3160 { "pc", PC },
3161 { "zpc", ZPC },
3162 { "sr", SR },
3163
3164 { "ccr", CCR },
3165 { "cc", CCR },
3166
8d20a0a8
C		 3167 /* control registers */
3168 { "sfc", SFC }, /* Source Function Code */
064ba683 3169 { "sfcr", SFC },
8d20a0a8 3170 { "dfc", DFC }, /* Destination Function Code */
064ba683 3171 { "dfcr", DFC },
8d20a0a8
C		 3172 { "cacr", CACR }, /* Cache Control Register */
3173 { "caar", CAAR }, /* Cache Address Register */
3174
3175 { "usp", USP }, /* User Stack Pointer */
3176 { "vbr", VBR }, /* Vector Base Register */
3177 { "msp", MSP }, /* Master Stack Pointer */
3178 { "isp", ISP }, /* Interrupt Stack Pointer */
3179
3180 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3181 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3182 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3183 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3184
3185 /* 68ec040 versions of same */
3186 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3187 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3188 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3189 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3190
0b810a6e
ILT		 3191 /* mcf5200 versions of same. The ColdFire programmer's reference
3192 manual indicated that the order is 2,3,0,1, but Ken Rose
3193 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3194 { "acr0", ITT0 }, /* Access Control Unit 0 */
3195 { "acr1", ITT1 }, /* Access Control Unit 1 */
3196 { "acr2", DTT0 }, /* Access Control Unit 2 */
3197 { "acr3", DTT1 }, /* Access Control Unit 3 */
8d20a0a8
C		 3198
3199 { "tc", TC }, /* MMU Translation Control Register */
3200 { "tcr", TC },
3201
3202 { "mmusr", MMUSR }, /* MMU Status Register */
3203 { "srp", SRP }, /* User Root Pointer */
3204 { "urp", URP }, /* Supervisor Root Pointer */
3205
9ad5755f
KR		 3206 { "buscr", BUSCR },
3207 { "pcr", PCR },
bcb8dff8 3208
8d20a0a8
C		 3209 { "rombar", ROMBAR }, /* ROM Base Address Register */
3210 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3211 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3212 { "mbar", MBAR }, /* Module Base Address Register */
3213 /* end of control registers */
3214
bcb8dff8
KR		 3215 { "ac", AC },
3216 { "bc", BC },
3217 { "cal", CAL },
3218 { "crp", CRP },
3219 { "drp", DRP },
3220 { "pcsr", PCSR },
3221 { "psr", PSR },
3222 { "scc", SCC },
3223 { "val", VAL },
3224 { "bad0", BAD0 },
3225 { "bad1", BAD1 },
3226 { "bad2", BAD2 },
3227 { "bad3", BAD3 },
3228 { "bad4", BAD4 },
3229 { "bad5", BAD5 },
3230 { "bad6", BAD6 },
3231 { "bad7", BAD7 },
3232 { "bac0", BAC0 },
3233 { "bac1", BAC1 },
3234 { "bac2", BAC2 },
3235 { "bac3", BAC3 },
3236 { "bac4", BAC4 },
3237 { "bac5", BAC5 },
3238 { "bac6", BAC6 },
3239 { "bac7", BAC7 },
3240
3241 { "ic", IC },
3242 { "dc", DC },
3243 { "nc", NC },
3244
3245 { "tt0", TT0 },
3246 { "tt1", TT1 },
4134a793 3247 /* 68ec030 versions of same */
bcb8dff8
KR		 3248 { "ac0", TT0 },
3249 { "ac1", TT1 },
4134a793 3250 /* 68ec030 access control unit, identical to 030 MMU status reg */
bcb8dff8 3251 { "acusr", PSR },
a933d598 3252
a1c7c0f3
ILT		 3253 /* Suppressed data and address registers. */
3254 { "zd0", ZDATA0 },
3255 { "zd1", ZDATA1 },
3256 { "zd2", ZDATA2 },
3257 { "zd3", ZDATA3 },
3258 { "zd4", ZDATA4 },
3259 { "zd5", ZDATA5 },
3260 { "zd6", ZDATA6 },
3261 { "zd7", ZDATA7 },
3262 { "za0", ZADDR0 },
3263 { "za1", ZADDR1 },
3264 { "za2", ZADDR2 },
3265 { "za3", ZADDR3 },
3266 { "za4", ZADDR4 },
3267 { "za5", ZADDR5 },
3268 { "za6", ZADDR6 },
3269 { "za7", ZADDR7 },
3270
bcb8dff8 3271 { 0, 0 }
a933d598
SC		 3272};
3273
a933d598 3274void
355afbcd 3275init_regtable ()
a933d598
SC		 3276{
3277 int i;
6d27d3a2 3278 for (i = 0; init_table[i].name; i++)
355afbcd 3279 insert_reg (init_table[i].name, init_table[i].number);
a933d598 3280}
6d27d3a2 3281
df3768fb 3282static int no_68851, no_68881;
a933d598 3283
dff60b7d
ILT		 3284#ifdef OBJ_AOUT
3285/* a.out machine type. Default to 68020. */
3286int m68k_aout_machtype = 2;
3287#endif
3288
fecd2382 3289void
355afbcd 3290md_assemble (str)
6d27d3a2 3291 char *str;
fecd2382 3292{
a1c7c0f3 3293 const char *er;
355afbcd
KR		 3294 short *fromP;
3295 char *toP = NULL;
3296 int m, n = 0;
3297 char *to_beg_P;
3298 int shorts_this_frag;
5f8cb05e 3299 fixS *fixP;
6d27d3a2 3300
4026c122
ILT		 3301 /* In MRI mode, the instruction and operands are separated by a
3302 space. Anything following the operands is a comment. The label
3303 has already been removed. */
3304 if (flag_mri)
3305 {
3306 char *s;
3307 int fields = 0;
3308 int infield = 0;
3309 int inquote = 0;
3310
3311 for (s = str; *s != '\0'; s++)
3312 {
3313 if ((*s == ' ' || *s == '\t') && ! inquote)
3314 {
3315 if (infield)
3316 {
3317 ++fields;
3318 if (fields >= 2)
3319 {
3320 *s = '\0';
3321 break;
3322 }
3323 infield = 0;
3324 }
3325 }
3326 else
3327 {
3328 if (! infield)
3329 infield = 1;
3330 if (*s == '\'')
3331 inquote = ! inquote;
3332 }
3333 }
3334 }
3335
e284846a 3336 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
355afbcd
KR		 3337 m68k_ip (str);
3338 er = the_ins.error;
3339 if (!er)
3340 {
a1c7c0f3 3341 for (n = 0; n < the_ins.numargs; n++)
355afbcd
KR		 3342 if (the_ins.operands[n].error)
3343 {
3344 er = the_ins.operands[n].error;
3345 break;
3346 }
3347 }
3348 if (er)
3349 {
3350 as_bad ("%s -- statement `%s' ignored", er, str);
3351 return;
3352 }
6d27d3a2 3353
d703b5a7
ILT		 3354 /* If there is a current label, record that it marks an instruction. */
3355 if (current_label != NULL)
3356 {
3357 current_label->text = 1;
3358 current_label = NULL;
3359 }
3360
355afbcd 3361 if (the_ins.nfrag == 0)
49864cfa
KR		 3362 {
3363 /* No frag hacking involved; just put it out */
355afbcd
KR		 3364 toP = frag_more (2 * the_ins.numo);
3365 fromP = &the_ins.opcode[0];
3366 for (m = the_ins.numo; m; --m)
3367 {
3368 md_number_to_chars (toP, (long) (*fromP), 2);
3369 toP += 2;
3370 fromP++;
f8701a3f 3371 }
355afbcd
KR		 3372 /* put out symbol-dependent info */
3373 for (m = 0; m < the_ins.nrel; m++)
3374 {
3375 switch (the_ins.reloc[m].wid)
3376 {
3377 case 'B':
3378 n = 1;
3379 break;
3380 case 'b':
3381 n = 1;
3382 break;
3383 case '3':
0b810a6e 3384 n = 1;
355afbcd
KR		 3385 break;
3386 case 'w':
590c50d8 3387 case 'W':
355afbcd
KR		 3388 n = 2;
3389 break;
3390 case 'l':
3391 n = 4;
3392 break;
3393 default:
49864cfa
KR		 3394 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3395 the_ins.reloc[m].wid);
355afbcd 3396 }
6d27d3a2 3397
5f8cb05e
ILT		 3398 fixP = fix_new_exp (frag_now,
3399 ((toP - frag_now->fr_literal)
3400 - the_ins.numo * 2 + the_ins.reloc[m].n),
3401 n,
3402 &the_ins.reloc[m].exp,
3403 the_ins.reloc[m].pcrel,
a043f579
ILT		 3404 get_reloc_code (n, the_ins.reloc[m].pcrel,
3405 the_ins.reloc[m].pic_reloc));
5f8cb05e 3406 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
a78bc551
ILT		 3407 if (the_ins.reloc[m].wid == 'B')
3408 fixP->fx_signed = 1;
f8701a3f 3409 }
355afbcd
KR		 3410 return;
3411 }
3412
3413 /* There's some frag hacking */
3414 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3415 {
3416 int wid;
3417
3418 if (n == 0)
3419 wid = 2 * the_ins.fragb[n].fragoff;
3420 else
3421 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3422 toP = frag_more (wid);
3423 to_beg_P = toP;
3424 shorts_this_frag = 0;
3425 for (m = wid / 2; m; --m)
3426 {
3427 md_number_to_chars (toP, (long) (*fromP), 2);
3428 toP += 2;
3429 fromP++;
3430 shorts_this_frag++;
3431 }
3432 for (m = 0; m < the_ins.nrel; m++)
3433 {
49864cfa 3434 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
355afbcd 3435 {
49864cfa 3436 the_ins.reloc[m].n -= 2 * shorts_this_frag;
355afbcd
KR		 3437 break;
3438 }
3439 wid = the_ins.reloc[m].wid;
3440 if (wid == 0)
3441 continue;
3442 the_ins.reloc[m].wid = 0;
3443 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3444
5f8cb05e
ILT		 3445 fixP = fix_new_exp (frag_now,
3446 ((toP - frag_now->fr_literal)
3447 - the_ins.numo * 2 + the_ins.reloc[m].n),
3448 wid,
3449 &the_ins.reloc[m].exp,
3450 the_ins.reloc[m].pcrel,
a043f579
ILT		 3451 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3452 the_ins.reloc[m].pic_reloc));
5f8cb05e 3453 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
fecd2382 3454 }
49864cfa
KR		 3455 (void) frag_var (rs_machine_dependent, 10, 0,
3456 (relax_substateT) (the_ins.fragb[n].fragty),
3457 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
355afbcd
KR		 3458 }
3459 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3460 shorts_this_frag = 0;
3461 if (n)
3462 {
3463 toP = frag_more (n * sizeof (short));
3464 while (n--)
3465 {
3466 md_number_to_chars (toP, (long) (*fromP), 2);
3467 toP += 2;
3468 fromP++;
3469 shorts_this_frag++;
fecd2382 3470 }
355afbcd
KR		 3471 }
3472 for (m = 0; m < the_ins.nrel; m++)
3473 {
3474 int wid;
3475
3476 wid = the_ins.reloc[m].wid;
3477 if (wid == 0)
3478 continue;
3479 the_ins.reloc[m].wid = 0;
3480 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3481
5f8cb05e
ILT		 3482 fixP = fix_new_exp (frag_now,
3483 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3484 - shorts_this_frag * 2),
3485 wid,
3486 &the_ins.reloc[m].exp,
3487 the_ins.reloc[m].pcrel,
a043f579
ILT		 3488 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3489 the_ins.reloc[m].pic_reloc));
5f8cb05e 3490 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
355afbcd 3491 }
fecd2382
RP		 3492}
3493
fecd2382 3494void
355afbcd 3495md_begin ()
fecd2382 3496{
355afbcd 3497 /*
e284846a
KR		 3498 * md_begin -- set up hash tables with 68000 instructions.
3499 * similar to what the vax assembler does. ---phr
3500 */
355afbcd 3501 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
e284846a
KR		 3502 a copy of it at runtime, adding in the information we want but isn't
3503 there. I think it'd be better to have an awk script hack the table
3504 at compile time. Or even just xstr the table and use it as-is. But
3505 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3506 names. */
6d27d3a2 3507
b79de3a1 3508 register const struct m68k_opcode *ins;
355afbcd 3509 register struct m68k_incant *hack, *slak;
bcb8dff8 3510 register const char *retval = 0; /* empty string, or error msg text */
355afbcd
KR		 3511 register unsigned int i;
3512 register char c;
3513
064ba683 3514 if (flag_mri)
6700d36e
ILT		 3515 {
3516 flag_reg_prefix_optional = 1;
3517 m68k_abspcadd = 1;
924160b0
ILT		 3518 if (! m68k_rel32_from_cmdline)
3519 m68k_rel32 = 0;
6700d36e 3520 }
064ba683 3521
82489ea0 3522 op_hash = hash_new ();
355afbcd
KR		 3523
3524 obstack_begin (&robyn, 4000);
a1c7c0f3 3525 for (i = 0; i < m68k_numopcodes; i++)
355afbcd
KR		 3526 {
3527 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3528 do
3529 {
a1c7c0f3 3530 ins = &m68k_opcodes[i];
e284846a
KR		 3531 /* We *could* ignore insns that don't match our arch here
3532 but just leaving them out of the hash. */
355afbcd
KR		 3533 slak->m_operands = ins->args;
3534 slak->m_opnum = strlen (slak->m_operands) / 2;
3535 slak->m_arch = ins->arch;
3536 slak->m_opcode = ins->opcode;
3537 /* This is kludgey */
3538 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
a1c7c0f3
ILT		 3539 if (i + 1 != m68k_numopcodes
3540 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
355afbcd
KR		 3541 {
3542 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
e284846a 3543 i++;
355afbcd
KR		 3544 }
3545 else
3546 slak->m_next = 0;
3547 slak = slak->m_next;
f8701a3f 3548 }
355afbcd
KR		 3549 while (slak);
3550
3551 retval = hash_insert (op_hash, ins->name, (char *) hack);
dff60b7d 3552 if (retval)
b79de3a1
KR		 3553 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3554 }
3555
a1c7c0f3 3556 for (i = 0; i < m68k_numaliases; i++)
b79de3a1
KR		 3557 {
3558 const char *name = m68k_opcode_aliases[i].primary;
3559 const char *alias = m68k_opcode_aliases[i].alias;
3560 PTR val = hash_find (op_hash, name);
3561 if (!val)
3562 as_fatal ("Internal Error: Can't find %s in hash table", name);
3563 retval = hash_insert (op_hash, alias, val);
3564 if (retval)
3565 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
355afbcd 3566 }
6d27d3a2 3567
6700d36e
ILT		 3568 /* In MRI mode, all unsized branches are variable sized. Normally,
3569 they are word sized. */
3570 if (flag_mri)
3571 {
3572 static struct m68k_opcode_alias mri_aliases[] =
3573 {
3574 { "bhi", "jhi", },
3575 { "bls", "jls", },
3576 { "bcc", "jcc", },
3577 { "bcs", "jcs", },
3578 { "bne", "jne", },
3579 { "beq", "jeq", },
3580 { "bvc", "jvc", },
3581 { "bvs", "jvs", },
3582 { "bpl", "jpl", },
3583 { "bmi", "jmi", },
3584 { "bge", "jge", },
3585 { "blt", "jlt", },
3586 { "bgt", "jgt", },
3587 { "ble", "jle", },
3588 { "bra", "jra", },
3589 { "bsr", "jbsr", },
3590 };
3591
3592 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3593 {
3594 const char *name = mri_aliases[i].primary;
3595 const char *alias = mri_aliases[i].alias;
3596 PTR val = hash_find (op_hash, name);
3597 if (!val)
3598 as_fatal ("Internal Error: Can't find %s in hash table", name);
3599 retval = hash_jam (op_hash, alias, val);
3600 if (retval)
3601 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3602 }
3603 }
3604
355afbcd
KR		 3605 for (i = 0; i < sizeof (mklower_table); i++)
3606 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
6d27d3a2 3607
355afbcd
KR		 3608 for (i = 0; i < sizeof (notend_table); i++)
3609 {
3610 notend_table[i] = 0;
3611 alt_notend_table[i] = 0;
3612 }
3613 notend_table[','] = 1;
3614 notend_table['{'] = 1;
3615 notend_table['}'] = 1;
3616 alt_notend_table['a'] = 1;
3617 alt_notend_table['A'] = 1;
3618 alt_notend_table['d'] = 1;
3619 alt_notend_table['D'] = 1;
3620 alt_notend_table['#'] = 1;
5f8cb05e 3621 alt_notend_table['&'] = 1;
355afbcd
KR		 3622 alt_notend_table['f'] = 1;
3623 alt_notend_table['F'] = 1;
fecd2382 3624#ifdef REGISTER_PREFIX
355afbcd 3625 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 3626#endif
f8701a3f 3627
a1c7c0f3
ILT		 3628 /* We need to put '(' in alt_notend_table to handle
3629 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3630 */
3631 alt_notend_table['('] = 1;
3632
3633 /* We need to put '@' in alt_notend_table to handle
3634 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3635 */
3636 alt_notend_table['@'] = 1;
3637
8d20a0a8
C		 3638 /* We need to put digits in alt_notend_table to handle
3639 bfextu %d0{24:1},%d0
3640 */
3641 alt_notend_table['0'] = 1;
3642 alt_notend_table['1'] = 1;
3643 alt_notend_table['2'] = 1;
3644 alt_notend_table['3'] = 1;
3645 alt_notend_table['4'] = 1;
3646 alt_notend_table['5'] = 1;
3647 alt_notend_table['6'] = 1;
3648 alt_notend_table['7'] = 1;
3649 alt_notend_table['8'] = 1;
3650 alt_notend_table['9'] = 1;
3651
3ad9ec6a 3652#ifndef MIT_SYNTAX_ONLY
355afbcd 3653 /* Insert pseudo ops, these have to go into the opcode table since
bcb8dff8 3654 gas expects pseudo ops to start with a dot */
355afbcd
KR		 3655 {
3656 int n = 0;
3657 while (mote_pseudo_table[n].poc_name)
3658 {
3659 hack = (struct m68k_incant *)
3660 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3661 hash_insert (op_hash,
3662 mote_pseudo_table[n].poc_name, (char *) hack);
3663 hack->m_operands = 0;
3664 hack->m_opnum = n;
3665 n++;
3666 }
3667 }
3ad9ec6a
ILT		 3668#endif
3669
355afbcd 3670 init_regtable ();
a043f579
ILT		 3671
3672#ifdef OBJ_ELF
3673 record_alignment (text_section, 2);
3674 record_alignment (data_section, 2);
3675 record_alignment (bss_section, 2);
3676#endif
fecd2382
RP		 3677}
3678
b4d51f3d
ILT		 3679static void
3680select_control_regs ()
3681{
3682 /* Note which set of "movec" control registers is available. */
3683 switch (cpu_of_arch (current_architecture))
3684 {
3685 case m68000:
3686 control_regs = m68000_control_regs;
3687 break;
3688 case m68010:
3689 control_regs = m68010_control_regs;
3690 break;
3691 case m68020:
3692 case m68030:
3693 control_regs = m68020_control_regs;
3694 break;
3695 case m68040:
3696 control_regs = m68040_control_regs;
3697 break;
3698 case m68060:
3699 control_regs = m68060_control_regs;
3700 break;
3701 case cpu32:
3702 control_regs = cpu32_control_regs;
3703 break;
3704 case mcf5200:
3705 control_regs = mcf5200_control_regs;
3706 break;
3707 default:
3708 abort ();
3709 }
3710}
3711
82489ea0
KR		 3712void
3713m68k_init_after_args ()
3714{
3715 if (cpu_of_arch (current_architecture) == 0)
3716 {
064ba683 3717 int i;
b79de3a1 3718 const char *default_cpu = TARGET_CPU;
82489ea0 3719
b79de3a1
KR		 3720 if (*default_cpu == 'm')
3721 default_cpu++;
3722 for (i = 0; i < n_archs; i++)
e9bb39b4 3723 if (strcasecmp (default_cpu, archs[i].name) == 0)
b79de3a1
KR		 3724 break;
3725 if (i == n_archs)
3726 {
3727 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3728 current_architecture |= m68020;
3729 }
3730 else
3731 current_architecture |= archs[i].arch;
82489ea0 3732 }
b79de3a1
KR		 3733 /* Permit m68881 specification with all cpus; those that can't work
3734 with a coprocessor could be doing emulation. */
82489ea0
KR		 3735 if (current_architecture & m68851)
3736 {
3737 if (current_architecture & m68040)
3738 {
3739 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3740 }
3741 }
3742 /* What other incompatibilities could we check for? */
3743
3744 /* Toss in some default assumptions about coprocessors. */
3745 if (!no_68881
3746 && (cpu_of_arch (current_architecture)
3747 /* Can CPU32 have a 68881 coprocessor?? */
3748 & (m68020 | m68030 | cpu32)))
3749 {
3750 current_architecture |= m68881;
3751 }
3752 if (!no_68851
3753 && (cpu_of_arch (current_architecture) & m68020up) != 0
3754 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3755 {
3756 current_architecture |= m68851;
3757 }
3758 if (no_68881 && (current_architecture & m68881))
3759 as_bad ("options for 68881 and no-68881 both given");
3760 if (no_68851 && (current_architecture & m68851))
3761 as_bad ("options for 68851 and no-68851 both given");
3762
3763#ifdef OBJ_AOUT
3764 /* Work out the magic number. This isn't very general. */
3765 if (current_architecture & m68000)
3766 m68k_aout_machtype = 0;
3767 else if (current_architecture & m68010)
3768 m68k_aout_machtype = 1;
3769 else if (current_architecture & m68020)
3770 m68k_aout_machtype = 2;
3771 else
3772 m68k_aout_machtype = 2;
3773#endif
3774
3775 /* Note which set of "movec" control registers is available. */
b4d51f3d 3776 select_control_regs ();
04ef74bb
KR		 3777
3778 if (cpu_of_arch (current_architecture) < m68020)
3779 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
82489ea0 3780}
d703b5a7
ILT		 3781\f
3782/* This is called when a label is defined. */
3783
3784void
3785m68k_frob_label (sym)
3786 symbolS *sym;
3787{
3788 struct label_line *n;
3789
3790 n = (struct label_line *) xmalloc (sizeof *n);
3791 n->next = labels;
3792 n->label = sym;
3793 as_where (&n->file, &n->line);
ffecfc8b 3794 n->text = 0;
d703b5a7
ILT		 3795 labels = n;
3796 current_label = n;
3797}
3798
3799/* This is called when a value that is not an instruction is emitted. */
3800
3801void
3802m68k_flush_pending_output ()
3803{
3804 current_label = NULL;
3805}
3806
3807/* This is called at the end of the assembly, when the final value of
3808 the label is known. We warn if this is a text symbol aligned at an
3809 odd location. */
3810
3811void
3812m68k_frob_symbol (sym)
3813 symbolS *sym;
3814{
3815 if ((S_GET_VALUE (sym) & 1) != 0)
3816 {
3817 struct label_line *l;
82489ea0 3818
d703b5a7
ILT		 3819 for (l = labels; l != NULL; l = l->next)
3820 {
3821 if (l->label == sym)
3822 {
3823 if (l->text)
3824 as_warn_where (l->file, l->line,
3825 "text label `%s' aligned to odd boundary",
3826 S_GET_NAME (sym));
3827 break;
3828 }
3829 }
3830 }
3831}
3832\f
20710f1c
ILT		 3833/* This is called if we go in or out of MRI mode because of the .mri
3834 pseudo-op. */
3835
3836void
3837m68k_mri_mode_change (on)
3838 int on;
3839{
3840 if (on)
3841 {
3842 if (! flag_reg_prefix_optional)
3843 {
3844 flag_reg_prefix_optional = 1;
3845#ifdef REGISTER_PREFIX
3846 init_regtable ();
3847#endif
3848 }
3849 m68k_abspcadd = 1;
924160b0
ILT		 3850 if (! m68k_rel32_from_cmdline)
3851 m68k_rel32 = 0;
20710f1c
ILT		 3852 }
3853 else
3854 {
3855 if (! reg_prefix_optional_seen)
3856 {
3857#ifdef REGISTER_PREFIX_OPTIONAL
3858 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3859#else
3860 flag_reg_prefix_optional = 0;
3861#endif
3862#ifdef REGISTER_PREFIX
3863 init_regtable ();
3864#endif
3865 }
3866 m68k_abspcadd = 0;
924160b0
ILT		 3867 if (! m68k_rel32_from_cmdline)
3868 m68k_rel32 = 1;
20710f1c
ILT		 3869 }
3870}
3871
fecd2382
RP		 3872/* Equal to MAX_PRECISION in atof-ieee.c */
3873#define MAX_LITTLENUMS 6
3874
a1c7c0f3
ILT		 3875/* Turn a string in input_line_pointer into a floating point constant
3876 of type type, and store the appropriate bytes in *litP. The number
3877 of LITTLENUMS emitted is stored in *sizeP . An error message is
3878 returned, or NULL on OK. */
3879
fecd2382 3880char *
355afbcd
KR		 3881md_atof (type, litP, sizeP)
3882 char type;
3883 char *litP;
3884 int *sizeP;
fecd2382 3885{
355afbcd
KR		 3886 int prec;
3887 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3888 LITTLENUM_TYPE *wordP;
3889 char *t;
6d27d3a2 3890
355afbcd
KR		 3891 switch (type)
3892 {
3893 case 'f':
3894 case 'F':
3895 case 's':
3896 case 'S':
3897 prec = 2;
3898 break;
6d27d3a2 3899
355afbcd
KR		 3900 case 'd':
3901 case 'D':
3902 case 'r':
3903 case 'R':
3904 prec = 4;
3905 break;
6d27d3a2 3906
355afbcd
KR		 3907 case 'x':
3908 case 'X':
3909 prec = 6;
3910 break;
6d27d3a2 3911
355afbcd
KR		 3912 case 'p':
3913 case 'P':
3914 prec = 6;
3915 break;
6d27d3a2 3916
355afbcd
KR		 3917 default:
3918 *sizeP = 0;
3919 return "Bad call to MD_ATOF()";
3920 }
3921 t = atof_ieee (input_line_pointer, type, words);
3922 if (t)
3923 input_line_pointer = t;
3924
3925 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3926 for (wordP = words; prec--;)
3927 {
3928 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3929 litP += sizeof (LITTLENUM_TYPE);
3930 }
49864cfa 3931 return 0;
fecd2382
RP		 3932}
3933
fecd2382 3934void
355afbcd
KR		 3935md_number_to_chars (buf, val, n)
3936 char *buf;
025b0302 3937 valueT val;
355afbcd 3938 int n;
fecd2382 3939{
82489ea0 3940 number_to_chars_bigendian (buf, val, n);
fecd2382
RP		 3941}
3942
49864cfa
KR		 3943static void
3944md_apply_fix_2 (fixP, val)
355afbcd 3945 fixS *fixP;
9ad5755f 3946 offsetT val;
fecd2382 3947{
9ad5755f
KR		 3948 addressT upper_limit;
3949 offsetT lower_limit;
49864cfa 3950
9ad5755f
KR		 3951 /* This is unnecessary but it convinces the native rs6000 compiler
3952 to generate the code we want. */
355afbcd
KR		 3953 char *buf = fixP->fx_frag->fr_literal;
3954 buf += fixP->fx_where;
9ad5755f
KR		 3955 /* end ibm compiler workaround */
3956
3957 if (val & 0x80000000)
3958 val |= ~(addressT)0x7fffffff;
3959 else
3960 val &= 0x7fffffff;
6d27d3a2 3961
a043f579
ILT		 3962#ifdef OBJ_ELF
3963 if (fixP->fx_addsy)
3964 {
3965 memset (buf, 0, fixP->fx_size);
3966 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3967 return;
3968 }
3969#endif
3970
355afbcd
KR		 3971 switch (fixP->fx_size)
3972 {
b79de3a1
KR		 3973 /* The cast to offsetT below are necessary to make code correct for
3974 machines where ints are smaller than offsetT */
355afbcd
KR		 3975 case 1:
3976 *buf++ = val;
49864cfa 3977 upper_limit = 0x7f;
b79de3a1 3978 lower_limit = - (offsetT) 0x80;
355afbcd
KR		 3979 break;
3980 case 2:
3981 *buf++ = (val >> 8);
3982 *buf++ = val;
49864cfa 3983 upper_limit = 0x7fff;
b79de3a1 3984 lower_limit = - (offsetT) 0x8000;
355afbcd
KR		 3985 break;
3986 case 4:
3987 *buf++ = (val >> 24);
3988 *buf++ = (val >> 16);
3989 *buf++ = (val >> 8);
3990 *buf++ = val;
49864cfa 3991 upper_limit = 0x7fffffff;
b79de3a1 3992 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
355afbcd
KR		 3993 break;
3994 default:
3995 BAD_CASE (fixP->fx_size);
3996 }
49864cfa 3997
3b06beb7
ILT		 3998 /* Fix up a negative reloc. */
3999 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4000 {
4001 fixP->fx_addsy = fixP->fx_subsy;
4002 fixP->fx_subsy = NULL;
4003 fixP->fx_tcbit = 1;
4004 }
4005
49864cfa
KR		 4006 /* For non-pc-relative values, it's conceivable we might get something
4007 like "0xff" for a byte field. So extend the upper part of the range
4008 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4009 so that we can do any range checking at all. */
a78bc551 4010 if (! fixP->fx_pcrel && ! fixP->fx_signed)
49864cfa
KR		 4011 upper_limit = upper_limit * 2 + 1;
4012
9ad5755f
KR		 4013 if ((addressT) val > upper_limit
4014 && (val > 0 || val < lower_limit))
f3751617
ILT		 4015 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4016
4017 /* A one byte PC-relative reloc means a short branch. We can't use
4018 a short branch with a value of 0 or -1, because those indicate
4019 different opcodes (branches with longer offsets). */
4020 if (fixP->fx_pcrel
4021 && fixP->fx_size == 1
4022 && (fixP->fx_addsy == NULL
4023 || S_IS_DEFINED (fixP->fx_addsy))
4024 && (val == 0 || val == -1))
4025 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
fecd2382
RP		 4026}
4027
49864cfa
KR		 4028#ifdef BFD_ASSEMBLER
4029int
4030md_apply_fix (fixP, valp)
4031 fixS *fixP;
5f8cb05e 4032 valueT *valp;
49864cfa 4033{
9ad5755f 4034 md_apply_fix_2 (fixP, (addressT) *valp);
49864cfa
KR		 4035 return 1;
4036}
4037#else
4038void md_apply_fix (fixP, val)
4039 fixS *fixP;
4040 long val;
4041{
9ad5755f 4042 md_apply_fix_2 (fixP, (addressT) val);
49864cfa
KR		 4043}
4044#endif
fecd2382
RP		 4045
4046/* *fragP has been relaxed to its final size, and now needs to have
4047 the bytes inside it modified to conform to the new size There is UGLY
4048 MAGIC here. ..
a39116f1 4049 */
fecd2382 4050void
49864cfa 4051md_convert_frag_1 (fragP)
355afbcd 4052 register fragS *fragP;
fecd2382 4053{
355afbcd
KR		 4054 long disp;
4055 long ext = 0;
5f8cb05e 4056 fixS *fixP;
6d27d3a2 4057
355afbcd
KR		 4058 /* Address in object code of the displacement. */
4059 register int object_address = fragP->fr_fix + fragP->fr_address;
6d27d3a2 4060
9ad5755f
KR		 4061 /* Address in gas core of the place to store the displacement. */
4062 /* This convinces the native rs6000 compiler to generate the code we
4063 want. */
355afbcd
KR		 4064 register char *buffer_address = fragP->fr_literal;
4065 buffer_address += fragP->fr_fix;
9ad5755f 4066 /* end ibm compiler workaround */
6d27d3a2 4067
355afbcd
KR		 4068 /* The displacement of the address, from current location. */
4069 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4070 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 4071
5f8cb05e
ILT		 4072#ifdef BFD_ASSEMBLER
4073 disp += fragP->fr_symbol->sy_frag->fr_address;
4074#endif
4075
355afbcd
KR		 4076 switch (fragP->fr_subtype)
4077 {
4078 case TAB (BCC68000, BYTE):
4079 case TAB (ABRANCH, BYTE):
4080 know (issbyte (disp));
4081 if (disp == 0)
4082 as_bad ("short branch with zero offset: use :w");
4083 fragP->fr_opcode[1] = disp;
4084 ext = 0;
4085 break;
4086 case TAB (DBCC, SHORT):
4087 know (issword (disp));
4088 ext = 2;
4089 break;
4090 case TAB (BCC68000, SHORT):
4091 case TAB (ABRANCH, SHORT):
4092 know (issword (disp));
4093 fragP->fr_opcode[1] = 0x00;
4094 ext = 2;
4095 break;
4096 case TAB (ABRANCH, LONG):
ffecfc8b 4097 if (!HAVE_LONG_BRANCH(current_architecture))
355afbcd
KR		 4098 {
4099 if (fragP->fr_opcode[0] == 0x61)
04ef74bb 4100 /* BSR */
355afbcd
KR		 4101 {
4102 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4103 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
355afbcd
KR		 4104
4105 fix_new (fragP,
4106 fragP->fr_fix,
4107 4,
4108 fragP->fr_symbol,
355afbcd
KR		 4109 fragP->fr_offset,
4110 0,
4111 NO_RELOC);
4112
4113 fragP->fr_fix += 4;
4114 ext = 0;
4115 }
04ef74bb 4116 /* BRA */
355afbcd
KR		 4117 else if (fragP->fr_opcode[0] == 0x60)
4118 {
4119 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4120 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
bcb8dff8
KR		 4121 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4122 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4123 fragP->fr_fix += 4;
4124 ext = 0;
4125 }
4126 else
4127 {
4128 as_bad ("Long branch offset not supported.");
4129 }
4130 }
4131 else
4132 {
bcb8dff8 4133 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 4134 ext = 4;
4135 }
4136 break;
4137 case TAB (BCC68000, LONG):
4138 /* only Bcc 68000 instructions can come here */
4139 /* change bcc into b!cc/jmp absl long */
4140 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4141 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
6d27d3a2 4142
355afbcd 4143 /* JF: these used to be fr_opcode[2,3], but they may be in a
fecd2382
RP		 4144 different frag, in which case refering to them is a no-no.
4145 Only fr_opcode[0,1] are guaranteed to work. */
355afbcd 4146 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4147 *buffer_address++ = (char) 0xf9;
355afbcd 4148 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8
KR		 4149 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4150 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4151 fragP->fr_fix += 4;
4152 ext = 0;
4153 break;
4154 case TAB (DBCC, LONG):
4155 /* only DBcc 68000 instructions can come here */
4156 /* change dbcc into dbcc/jmp absl long */
4157 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4158 *buffer_address++ = 0x00; /* branch offset = 4 */
4159 *buffer_address++ = 0x04;
4160 *buffer_address++ = 0x60; /* put in bra pc+6 */
4161 *buffer_address++ = 0x06;
4162 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4163 *buffer_address++ = (char) 0xf9;
355afbcd
KR		 4164
4165 fragP->fr_fix += 6; /* account for bra/jmp instructions */
bcb8dff8 4166 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
49864cfa 4167 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4168 fragP->fr_fix += 4;
4169 ext = 0;
4170 break;
4171 case TAB (FBRANCH, SHORT):
4172 know ((fragP->fr_opcode[1] & 0x40) == 0);
4173 ext = 2;
4174 break;
4175 case TAB (FBRANCH, LONG):
4176 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4177 ext = 4;
4178 break;
4179 case TAB (PCREL, SHORT):
4180 ext = 2;
4181 break;
4182 case TAB (PCREL, LONG):
4183 /* The thing to do here is force it to ABSOLUTE LONG, since
f8701a3f 4184 PCREL is really trying to shorten an ABSOLUTE address anyway */
355afbcd 4185 /* JF FOO This code has not been tested */
bcb8dff8 4186 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
49864cfa 4187 0, NO_RELOC);
355afbcd 4188 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
bcb8dff8
KR		 4189 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4190 (unsigned) fragP->fr_opcode[0],
4191 (unsigned long) fragP->fr_address);
355afbcd
KR		 4192 fragP->fr_opcode[1] &= ~0x3F;
4193 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4194 fragP->fr_fix += 4;
355afbcd
KR		 4195 ext = 0;
4196 break;
4197 case TAB (PCLEA, SHORT):
49864cfa 4198 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
bcb8dff8 4199 fragP->fr_offset, 1, NO_RELOC);
355afbcd 4200 fragP->fr_opcode[1] &= ~0x3F;
04ef74bb 4201 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
355afbcd
KR		 4202 ext = 2;
4203 break;
4204 case TAB (PCLEA, LONG):
5f8cb05e
ILT		 4205 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4206 fragP->fr_offset, 1, NO_RELOC);
4207 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 4208 /* Already set to mode 7.3; this indicates: PC indirect with
4209 suppressed index, 32-bit displacement. */
355afbcd
KR		 4210 *buffer_address++ = 0x01;
4211 *buffer_address++ = 0x70;
4212 fragP->fr_fix += 2;
355afbcd
KR		 4213 ext = 4;
4214 break;
04ef74bb
KR		 4215
4216 case TAB (PCINDEX, BYTE):
4217 disp += 2;
4218 if (!issbyte (disp))
4219 {
4220 as_bad ("displacement doesn't fit in one byte");
4221 disp = 0;
4222 }
5f8cb05e
ILT		 4223 assert (fragP->fr_fix >= 2);
4224 buffer_address[-2] &= ~1;
4225 buffer_address[-1] = disp;
04ef74bb
KR		 4226 ext = 0;
4227 break;
4228 case TAB (PCINDEX, SHORT):
04ef74bb
KR		 4229 disp += 2;
4230 assert (issword (disp));
5f8cb05e
ILT		 4231 assert (fragP->fr_fix >= 2);
4232 buffer_address[-2] |= 0x1;
4233 buffer_address[-1] = 0x20;
4234 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4235 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4236 NO_RELOC);
4237 fixP->fx_pcrel_adjust = 2;
04ef74bb
KR		 4238 ext = 2;
4239 break;
4240 case TAB (PCINDEX, LONG):
04ef74bb 4241 disp += 2;
5f8cb05e
ILT		 4242 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4243 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4244 NO_RELOC);
4245 fixP->fx_pcrel_adjust = 2;
4246 assert (fragP->fr_fix >= 2);
4247 buffer_address[-2] |= 0x1;
4248 buffer_address[-1] = 0x30;
04ef74bb
KR		 4249 ext = 4;
4250 break;
49864cfa 4251 }
355afbcd
KR		 4252
4253 if (ext)
4254 {
4255 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4256 fragP->fr_fix += ext;
49864cfa
KR		 4257 }
4258}
355afbcd 4259
49864cfa
KR		 4260#ifndef BFD_ASSEMBLER
4261
4262void
064ba683 4263md_convert_frag (headers, sec, fragP)
49864cfa 4264 object_headers *headers;
064ba683 4265 segT sec;
49864cfa
KR		 4266 fragS *fragP;
4267{
4268 md_convert_frag_1 (fragP);
4269}
4270
4271#else
4272
4273void
4274md_convert_frag (abfd, sec, fragP)
4275 bfd *abfd;
5f8cb05e 4276 segT sec;
49864cfa
KR		 4277 fragS *fragP;
4278{
4279 md_convert_frag_1 (fragP);
4280}
4281#endif
355afbcd
KR		 4282
4283/* Force truly undefined symbols to their maximum size, and generally set up
4284 the frag list to be relaxed
4285 */
4286int
4287md_estimate_size_before_relax (fragP, segment)
4288 register fragS *fragP;
4289 segT segment;
4290{
4291 int old_fix;
4292 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4293
4294 old_fix = fragP->fr_fix;
4295
4296 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4297 switch (fragP->fr_subtype)
4298 {
4299
4300 case TAB (ABRANCH, SZ_UNDEF):
4301 {
4302 if ((fragP->fr_symbol != NULL) /* Not absolute */
4303 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4304 {
4305 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4306 break;
4307 }
ffecfc8b 4308 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
355afbcd
KR		 4309 {
4310 /* On 68000, or for absolute value, switch to abs long */
4311 /* FIXME, we should check abs val, pick short or long */
4312 if (fragP->fr_opcode[0] == 0x61)
4313 {
4314 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4315 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
355afbcd 4316 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4317 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4318 fragP->fr_fix += 4;
4319 frag_wane (fragP);
4320 }
4321 else if (fragP->fr_opcode[0] == 0x60)
4322 {
4323 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4324 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
355afbcd 4325 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4326 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4327 fragP->fr_fix += 4;
4328 frag_wane (fragP);
4329 }
4330 else
4331 {
4332 as_warn ("Long branch offset to extern symbol not supported.");
4333 }
4334 }
4335 else
4336 { /* Symbol is still undefined. Make it simple */
4337 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5f8cb05e 4338 fragP->fr_offset, 1, NO_RELOC);
355afbcd 4339 fragP->fr_fix += 4;
bcb8dff8 4340 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 4341 frag_wane (fragP);
4342 break;
4343 }
4344
a39116f1 4345 break;
355afbcd 4346 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 4347
355afbcd
KR		 4348 case TAB (FBRANCH, SZ_UNDEF):
4349 {
9ad5755f 4350 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
355afbcd
KR		 4351 {
4352 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4353 fragP->fr_var += 2;
4354 }
4355 else
4356 {
5f8cb05e
ILT		 4357 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4358 fragP->fr_offset, 1, NO_RELOC);
4359 fragP->fr_fix += 4;
4360 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4361 frag_wane (fragP);
355afbcd
KR		 4362 }
4363 break;
4364 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 4365
355afbcd
KR		 4366 case TAB (PCREL, SZ_UNDEF):
4367 {
b79de3a1
KR		 4368 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4369 || flag_short_refs
4370 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 4371 {
4372 fragP->fr_subtype = TAB (PCREL, SHORT);
4373 fragP->fr_var += 2;
4374 }
4375 else
4376 {
4377 fragP->fr_subtype = TAB (PCREL, LONG);
4378 fragP->fr_var += 4;
4379 }
4380 break;
4381 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 4382
355afbcd
KR		 4383 case TAB (BCC68000, SZ_UNDEF):
4384 {
4385 if ((fragP->fr_symbol != NULL)
4386 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4387 {
4388 fragP->fr_subtype = TAB (BCC68000, BYTE);
4389 break;
4390 }
4391 /* only Bcc 68000 instructions can come here */
4392 /* change bcc into b!cc/jmp absl long */
4393 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
9ad5755f 4394 if (flag_short_refs)
355afbcd
KR		 4395 {
4396 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4397 /* JF: these were fr_opcode[2,3] */
4398 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4399 buffer_address[1] = (char) 0xf8;
355afbcd 4400 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8 4401 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4402 fragP->fr_offset, 0, NO_RELOC);
4403 fragP->fr_fix += 2;
4404 }
4405 else
4406 {
4407 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4408 /* JF: these were fr_opcode[2,3] */
4409 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4410 buffer_address[1] = (char) 0xf9;
355afbcd 4411 fragP->fr_fix += 2; /* account for jmp instruction */
bcb8dff8 4412 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4413 fragP->fr_offset, 0, NO_RELOC);
4414 fragP->fr_fix += 4;
4415 }
4416 frag_wane (fragP);
4417 break;
4418 } /* case TAB(BCC68000,SZ_UNDEF) */
f8701a3f 4419
355afbcd
KR		 4420 case TAB (DBCC, SZ_UNDEF):
4421 {
4422 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4423 {
4424 fragP->fr_subtype = TAB (DBCC, SHORT);
4425 fragP->fr_var += 2;
4426 break;
4427 }
4428 /* only DBcc 68000 instructions can come here */
4429 /* change dbcc into dbcc/jmp absl long */
4430 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4431 buffer_address[0] = 0x00; /* branch offset = 4 */
4432 buffer_address[1] = 0x04;
4433 buffer_address[2] = 0x60; /* put in bra pc + ... */
4434
9ad5755f 4435 if (flag_short_refs)
355afbcd
KR		 4436 {
4437 /* JF: these were fr_opcode[5-7] */
4438 buffer_address[3] = 0x04; /* plus 4 */
4439 buffer_address[4] = 0x4e; /* Put in Jump Word */
bcb8dff8 4440 buffer_address[5] = (char) 0xf8;
355afbcd 4441 fragP->fr_fix += 6; /* account for bra/jmp instruction */
bcb8dff8 4442 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4443 fragP->fr_offset, 0, NO_RELOC);
4444 fragP->fr_fix += 2;
4445 }
4446 else
4447 {
4448 /* JF: these were fr_opcode[5-7] */
4449 buffer_address[3] = 0x06; /* Plus 6 */
4450 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4451 buffer_address[5] = (char) 0xf9;
355afbcd 4452 fragP->fr_fix += 6; /* account for bra/jmp instruction */
bcb8dff8 4453 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4454 fragP->fr_offset, 0, NO_RELOC);
4455 fragP->fr_fix += 4;
4456 }
6d27d3a2 4457
355afbcd
KR		 4458 frag_wane (fragP);
4459 break;
4460 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 4461
355afbcd
KR		 4462 case TAB (PCLEA, SZ_UNDEF):
4463 {
b79de3a1
KR		 4464 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4465 || flag_short_refs
4466 || cpu_of_arch (current_architecture) < m68020)
355afbcd
KR		 4467 {
4468 fragP->fr_subtype = TAB (PCLEA, SHORT);
4469 fragP->fr_var += 2;
4470 }
4471 else
4472 {
4473 fragP->fr_subtype = TAB (PCLEA, LONG);
4474 fragP->fr_var += 6;
4475 }
4476 break;
4477 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 4478
04ef74bb
KR		 4479 case TAB (PCINDEX, SZ_UNDEF):
4480 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4481 || cpu_of_arch (current_architecture) < m68020)
4482 {
4483 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4484 }
4485 else
4486 {
4487 fragP->fr_subtype = TAB (PCINDEX, LONG);
5f8cb05e 4488 fragP->fr_var += 4;
04ef74bb 4489 }
355afbcd 4490 break;
6d27d3a2 4491
04ef74bb
KR		 4492 default:
4493 break;
4494 }
6d27d3a2 4495
355afbcd
KR		 4496 /* now that SZ_UNDEF are taken care of, check others */
4497 switch (fragP->fr_subtype)
4498 {
4499 case TAB (BCC68000, BYTE):
4500 case TAB (ABRANCH, BYTE):
024e1779
ILT		 4501 /* We can't do a short jump to the next instruction, so in that
4502 case we force word mode. At this point S_GET_VALUE should
4503 return the offset of the symbol within its frag. If the
4504 symbol is at the start of a frag, and it is the next frag
4505 with any data in it (usually this is just the next frag, but
4506 assembler listings may introduce empty frags), we must use
4507 word mode. */
65feb78d 4508 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
355afbcd 4509 {
65feb78d
ILT		 4510 fragS *l;
4511
4512 for (l = fragP->fr_next;
4513 l != fragP->fr_symbol->sy_frag;
4514 l = l->fr_next)
4515 if (l->fr_fix + l->fr_var != 0)
4516 break;
4517 if (l == fragP->fr_symbol->sy_frag)
4518 {
4519 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4520 fragP->fr_var += 2;
4521 }
fecd2382 4522 }
355afbcd
KR		 4523 break;
4524 default:
4525 break;
4526 }
4527 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 4528}
4529
4530#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 4531/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 4532 with the byte-order problems of cross-assembly. So as a hack,
4533 I added this mach. dependent ri twiddler. Ugly, but it gets
4534 you there. -KWK */
4535/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 4536 are symbolnum, most sig. byte first. Last byte is broken up with
4537 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4538 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 4539/* Translate the internal relocation information into target-specific
4540 format. */
a79c6033 4541#ifdef comment
fecd2382 4542void
355afbcd
KR		 4543md_ri_to_chars (the_bytes, ri)
4544 char *the_bytes;
4545 struct reloc_info_generic *ri;
fecd2382 4546{
355afbcd
KR		 4547 /* this is easy */
4548 md_number_to_chars (the_bytes, ri->r_address, 4);
4549 /* now the fun stuff */
4550 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4551 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4552 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4553 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4554 ((ri->r_extern << 4) & 0x10));
fecd2382 4555}
355afbcd 4556
a79c6033
RP		 4557#endif /* comment */
4558
49864cfa 4559#ifndef BFD_ASSEMBLER
355afbcd
KR		 4560void
4561tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4562 char *where;
4563 fixS *fixP;
4564 relax_addressT segment_address_in_file;
a79c6033 4565{
355afbcd 4566 /*
1404ef23
KR		 4567 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4568 * Out: GNU LD relocation length code: 0, 1, or 2.
4569 */
6d27d3a2 4570
82489ea0 4571 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
355afbcd 4572 long r_symbolnum;
6d27d3a2 4573
355afbcd 4574 know (fixP->fx_addsy != NULL);
6d27d3a2 4575
355afbcd
KR		 4576 md_number_to_chars (where,
4577 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4578 4);
6d27d3a2 4579
355afbcd
KR		 4580 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4581 ? S_GET_TYPE (fixP->fx_addsy)
4582 : fixP->fx_addsy->sy_number);
6d27d3a2 4583
355afbcd
KR		 4584 where[4] = (r_symbolnum >> 16) & 0x0ff;
4585 where[5] = (r_symbolnum >> 8) & 0x0ff;
4586 where[6] = r_symbolnum & 0x0ff;
4587 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4588 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
49864cfa
KR		 4589}
4590#endif
a79c6033 4591
fecd2382
RP		 4592#endif /* OBJ_AOUT or OBJ_BOUT */
4593
4594#ifndef WORKING_DOT_WORD
49864cfa
KR		 4595CONST int md_short_jump_size = 4;
4596CONST int md_long_jump_size = 6;
fecd2382
RP		 4597
4598void
355afbcd
KR		 4599md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4600 char *ptr;
025b0302 4601 addressT from_addr, to_addr;
355afbcd
KR		 4602 fragS *frag;
4603 symbolS *to_symbol;
fecd2382 4604{
025b0302 4605 valueT offset;
6d27d3a2 4606
355afbcd 4607 offset = to_addr - (from_addr + 2);
6d27d3a2 4608
025b0302
ME		 4609 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4610 md_number_to_chars (ptr + 2, (valueT) offset, 2);
fecd2382
RP		 4611}
4612
4613void
355afbcd
KR		 4614md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4615 char *ptr;
025b0302 4616 addressT from_addr, to_addr;
355afbcd
KR		 4617 fragS *frag;
4618 symbolS *to_symbol;
fecd2382 4619{
025b0302 4620 valueT offset;
355afbcd 4621
ffecfc8b 4622 if (!HAVE_LONG_BRANCH(current_architecture))
355afbcd
KR		 4623 {
4624 offset = to_addr - S_GET_VALUE (to_symbol);
025b0302
ME		 4625 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4626 md_number_to_chars (ptr + 2, (valueT) offset, 4);
bcb8dff8
KR		 4627 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4628 0, NO_RELOC);
355afbcd
KR		 4629 }
4630 else
4631 {
4632 offset = to_addr - (from_addr + 2);
025b0302
ME		 4633 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4634 md_number_to_chars (ptr + 2, (valueT) offset, 4);
355afbcd 4635 }
fecd2382
RP		 4636}
4637
4638#endif
a1c7c0f3
ILT		 4639
4640/* Different values of OK tell what its OK to return. Things that
4641 aren't OK are an error (what a shock, no?)
6d27d3a2 4642
a39116f1
RP		 4643 0: Everything is OK
4644 10: Absolute 1:8 only
4645 20: Absolute 0:7 only
4646 30: absolute 0:15 only
4647 40: Absolute 0:31 only
4648 50: absolute 0:127 only
4649 55: absolute -64:63 only
4650 60: absolute -128:127 only
4651 70: absolute 0:4095 only
4652 80: No bignums
6d27d3a2 4653
a39116f1 4654 */
fecd2382 4655
355afbcd
KR		 4656static int
4657get_num (exp, ok)
4658 struct m68k_exp *exp;
4659 int ok;
fecd2382 4660{
a1c7c0f3 4661 if (exp->exp.X_op == O_absent)
49864cfa 4662 {
355afbcd 4663 /* Do the same thing the VAX asm does */
bcb8dff8 4664 op (exp) = O_constant;
355afbcd
KR		 4665 adds (exp) = 0;
4666 subs (exp) = 0;
4667 offs (exp) = 0;
4668 if (ok == 10)
4669 {
4670 as_warn ("expression out of range: defaulting to 1");
4671 offs (exp) = 1;
4672 }
49864cfa 4673 }
a1c7c0f3 4674 else if (exp->exp.X_op == O_constant)
49864cfa 4675 {
355afbcd
KR		 4676 switch (ok)
4677 {
4678 case 10:
4679 if (offs (exp) < 1 || offs (exp) > 8)
4680 {
4681 as_warn ("expression out of range: defaulting to 1");
4682 offs (exp) = 1;
4683 }
4684 break;
4685 case 20:
4686 if (offs (exp) < 0 || offs (exp) > 7)
4687 goto outrange;
4688 break;
4689 case 30:
4690 if (offs (exp) < 0 || offs (exp) > 15)
4691 goto outrange;
4692 break;
4693 case 40:
4694 if (offs (exp) < 0 || offs (exp) > 32)
4695 goto outrange;
4696 break;
4697 case 50:
4698 if (offs (exp) < 0 || offs (exp) > 127)
4699 goto outrange;
4700 break;
4701 case 55:
4702 if (offs (exp) < -64 || offs (exp) > 63)
4703 goto outrange;
4704 break;
4705 case 60:
4706 if (offs (exp) < -128 || offs (exp) > 127)
4707 goto outrange;
4708 break;
4709 case 70:
4710 if (offs (exp) < 0 || offs (exp) > 4095)
4711 {
4712 outrange:
4713 as_warn ("expression out of range: defaulting to 0");
4714 offs (exp) = 0;
4715 }
4716 break;
fecd2382 4717 default:
355afbcd
KR		 4718 break;
4719 }
49864cfa 4720 }
a1c7c0f3 4721 else if (exp->exp.X_op == O_big)
49864cfa 4722 {
bcb8dff8 4723 if (offs (exp) <= 0 /* flonum */
355afbcd
KR		 4724 && (ok == 80 /* no bignums */
4725 || (ok > 10 /* small-int ranges including 0 ok */
1404ef23
KR		 4726 /* If we have a flonum zero, a zero integer should
4727 do as well (e.g., in moveq). */
355afbcd
KR		 4728 && generic_floating_point_number.exponent == 0
4729 && generic_floating_point_number.low[0] == 0)))
4730 {
4731 /* HACK! Turn it into a long */
4732 LITTLENUM_TYPE words[6];
4733
4734 gen_to_words (words, 2, 8L); /* These numbers are magic! */
bcb8dff8 4735 op (exp) = O_constant;
355afbcd
KR		 4736 adds (exp) = 0;
4737 subs (exp) = 0;
4738 offs (exp) = words[1] | (words[0] << 16);
4739 }
4740 else if (ok != 0)
4741 {
bcb8dff8 4742 op (exp) = O_constant;
355afbcd
KR		 4743 adds (exp) = 0;
4744 subs (exp) = 0;
4745 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 4746 as_warn ("Can't deal with expression; defaulting to %ld",
4747 offs (exp));
355afbcd 4748 }
49864cfa
KR		 4749 }
4750 else
4751 {
355afbcd
KR		 4752 if (ok >= 10 && ok <= 70)
4753 {
bcb8dff8 4754 op (exp) = O_constant;
355afbcd
KR		 4755 adds (exp) = 0;
4756 subs (exp) = 0;
4757 offs (exp) = (ok == 10) ? 1 : 0;
a1c7c0f3
ILT		 4758 as_warn ("Can't deal with expression; defaulting to %ld",
4759 offs (exp));
355afbcd 4760 }
355afbcd 4761 }
49864cfa 4762
a1c7c0f3 4763 if (exp->size != SIZE_UNSPEC)
355afbcd 4764 {
a1c7c0f3 4765 switch (exp->size)
355afbcd 4766 {
a1c7c0f3
ILT		 4767 case SIZE_UNSPEC:
4768 case SIZE_LONG:
4769 break;
4770 case SIZE_BYTE:
355afbcd
KR		 4771 if (!isbyte (offs (exp)))
4772 as_warn ("expression doesn't fit in BYTE");
4773 break;
a1c7c0f3 4774 case SIZE_WORD:
355afbcd
KR		 4775 if (!isword (offs (exp)))
4776 as_warn ("expression doesn't fit in WORD");
4777 break;
a39116f1 4778 }
355afbcd 4779 }
a1c7c0f3 4780
355afbcd 4781 return offs (exp);
49864cfa 4782}
fecd2382
RP		 4783
4784/* These are the back-ends for the various machine dependent pseudo-ops. */
4785
355afbcd 4786static void
bcb8dff8
KR		 4787s_data1 (ignore)
4788 int ignore;
355afbcd 4789{
bcb8dff8 4790 subseg_set (data_section, 1);
355afbcd 4791 demand_empty_rest_of_line ();
49864cfa 4792}
fecd2382 4793
355afbcd 4794static void
bcb8dff8
KR		 4795s_data2 (ignore)
4796 int ignore;
355afbcd 4797{
bcb8dff8 4798 subseg_set (data_section, 2);
355afbcd 4799 demand_empty_rest_of_line ();
49864cfa 4800}
fecd2382 4801
355afbcd 4802static void
bcb8dff8
KR		 4803s_bss (ignore)
4804 int ignore;
a1765cf0 4805{
355afbcd 4806 /* We don't support putting frags in the BSS segment, we fake it
49864cfa 4807 by marking in_bss, then looking at s_skip for clues. */
a1765cf0 4808
bcb8dff8 4809 subseg_set (bss_section, 0);
355afbcd 4810 demand_empty_rest_of_line ();
49864cfa 4811}
6d27d3a2 4812
355afbcd 4813static void
bcb8dff8
KR		 4814s_even (ignore)
4815 int ignore;
355afbcd
KR		 4816{
4817 register int temp;
4818 register long temp_fill;
4819
4820 temp = 1; /* JF should be 2? */
4821 temp_fill = get_absolute_expression ();
4822 if (!need_pass_2) /* Never make frag if expect extra pass. */
fee3e248 4823 frag_align (temp, (int) temp_fill, 0);
355afbcd 4824 demand_empty_rest_of_line ();
79811f6f 4825 record_alignment (now_seg, temp);
49864cfa 4826}
355afbcd
KR		 4827
4828static void
bcb8dff8
KR		 4829s_proc (ignore)
4830 int ignore;
355afbcd
KR		 4831{
4832 demand_empty_rest_of_line ();
49864cfa 4833}
e9bb39b4
ILT		 4834\f
4835/* Pseudo-ops handled for MRI compatibility. */
4836
a986926b
ILT		 4837/* This function returns non-zero if the argument is a conditional
4838 pseudo-op. This is called when checking whether a pending
4839 alignment is needed. */
4840
4841int
4842m68k_conditional_pseudoop (pop)
4843 pseudo_typeS *pop;
4844{
4845 return (pop->poc_handler == s_mri_if
4846 || pop->poc_handler == s_mri_else);
4847}
4848
e9bb39b4 4849/* Handle an MRI style chip specification. */
fecd2382 4850
e9bb39b4
ILT		 4851static void
4852mri_chip ()
4853{
4854 char *s;
4855 char c;
4856 int i;
4857
4858 s = input_line_pointer;
af438bdb
ILT		 4859 /* We can't use get_symbol_end since the processor names are not proper
4860 symbols. */
4861 while (is_part_of_name (c = *input_line_pointer++))
4862 ;
4863 *--input_line_pointer = 0;
e9bb39b4
ILT		 4864 for (i = 0; i < n_archs; i++)
4865 if (strcasecmp (s, archs[i].name) == 0)
4866 break;
4867 if (i >= n_archs)
4868 {
4869 as_bad ("%s: unrecognized processor name", s);
4870 *input_line_pointer = c;
4871 ignore_rest_of_line ();
4872 return;
4873 }
4874 *input_line_pointer = c;
fecd2382 4875
e9bb39b4
ILT		 4876 if (*input_line_pointer == '/')
4877 current_architecture = 0;
4878 else
4879 current_architecture &= m68881 | m68851;
4880 current_architecture |= archs[i].arch;
4881
4882 while (*input_line_pointer == '/')
4883 {
4884 ++input_line_pointer;
4885 s = input_line_pointer;
af438bdb
ILT		 4886 /* We can't use get_symbol_end since the processor names are not
4887 proper symbols. */
4888 while (is_part_of_name (c = *input_line_pointer++))
4889 ;
4890 *--input_line_pointer = 0;
e9bb39b4
ILT		 4891 if (strcmp (s, "68881") == 0)
4892 current_architecture |= m68881;
4893 else if (strcmp (s, "68851") == 0)
4894 current_architecture |= m68851;
4895 *input_line_pointer = c;
4896 }
b4d51f3d
ILT		 4897
4898 /* Update info about available control registers. */
4899 select_control_regs ();
e9bb39b4
ILT		 4900}
4901
4902/* The MRI CHIP pseudo-op. */
4903
4904static void
4905s_chip (ignore)
4906 int ignore;
4907{
f9680a05
ILT		 4908 char *stop = NULL;
4909 char stopc;
4910
4911 if (flag_mri)
4912 stop = mri_comment_field (&stopc);
e9bb39b4 4913 mri_chip ();
f9680a05
ILT		 4914 if (flag_mri)
4915 mri_comment_end (stop, stopc);
e9bb39b4
ILT		 4916 demand_empty_rest_of_line ();
4917}
27a53b88
ILT		 4918
4919/* The MRI FOPT pseudo-op. */
4920
4921static void
4922s_fopt (ignore)
4923 int ignore;
4924{
4925 SKIP_WHITESPACE ();
4926
4927 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4928 {
4929 int temp;
4930
4931 input_line_pointer += 3;
4932 temp = get_absolute_expression ();
4933 if (temp < 0 || temp > 7)
4934 as_bad ("bad coprocessor id");
4935 else
4936 m68k_float_copnum = COP0 + temp;
4937 }
4938 else
4939 {
4940 as_bad ("unrecognized fopt option");
4941 ignore_rest_of_line ();
4942 return;
4943 }
4944
4945 demand_empty_rest_of_line ();
4946}
6700d36e
ILT		 4947
4948/* The structure used to handle the MRI OPT pseudo-op. */
4949
4950struct opt_action
4951{
4952 /* The name of the option. */
4953 const char *name;
4954
4955 /* If this is not NULL, just call this function. The first argument
4956 is the ARG field of this structure, the second argument is
4957 whether the option was negated. */
4958 void (*pfn) PARAMS ((int arg, int on));
4959
4960 /* If this is not NULL, and the PFN field is NULL, set the variable
4961 this points to. Set it to the ARG field if the option was not
4962 negated, and the NOTARG field otherwise. */
4963 int *pvar;
4964
4965 /* The value to pass to PFN or to assign to *PVAR. */
4966 int arg;
4967
4968 /* The value to assign to *PVAR if the option is negated. If PFN is
4969 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4970 the option may not be negated. */
4971 int notarg;
4972};
4973
4974/* The table used to handle the MRI OPT pseudo-op. */
4975
4976static void skip_to_comma PARAMS ((int, int));
7e047ac2 4977static void opt_nest PARAMS ((int, int));
6700d36e
ILT		 4978static void opt_chip PARAMS ((int, int));
4979static void opt_list PARAMS ((int, int));
4980static void opt_list_symbols PARAMS ((int, int));
4981
4982static const struct opt_action opt_table[] =
4983{
4984 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4985
4986 /* We do relaxing, so there is little use for these options. */
4987 { "b", 0, 0, 0, 0 },
4988 { "brs", 0, 0, 0, 0 },
4989 { "brb", 0, 0, 0, 0 },
4990 { "brl", 0, 0, 0, 0 },
4991 { "brw", 0, 0, 0, 0 },
4992
4993 { "c", 0, 0, 0, 0 },
4994 { "cex", 0, 0, 0, 0 },
4995 { "case", 0, &symbols_case_sensitive, 1, 0 },
4996 { "cl", 0, 0, 0, 0 },
4997 { "cre", 0, 0, 0, 0 },
4998 { "d", 0, &flag_keep_locals, 1, 0 },
4999 { "e", 0, 0, 0, 0 },
5000 { "f", 0, &flag_short_refs, 1, 0 },
5001 { "frs", 0, &flag_short_refs, 1, 0 },
5002 { "frl", 0, &flag_short_refs, 0, 1 },
5003 { "g", 0, 0, 0, 0 },
5004 { "i", 0, 0, 0, 0 },
5005 { "m", 0, 0, 0, 0 },
5006 { "mex", 0, 0, 0, 0 },
5007 { "mc", 0, 0, 0, 0 },
5008 { "md", 0, 0, 0, 0 },
7e047ac2 5009 { "nest", opt_nest, 0, 0, 0 },
6700d36e
ILT		 5010 { "next", skip_to_comma, 0, 0, 0 },
5011 { "o", 0, 0, 0, 0 },
5012 { "old", 0, 0, 0, 0 },
5013 { "op", skip_to_comma, 0, 0, 0 },
5014 { "pco", 0, 0, 0, 0 },
5015 { "p", opt_chip, 0, 0, 0 },
5016 { "pcr", 0, 0, 0, 0 },
5017 { "pcs", 0, 0, 0, 0 },
5018 { "r", 0, 0, 0, 0 },
5019 { "quick", 0, &m68k_quick, 1, 0 },
5020 { "rel32", 0, &m68k_rel32, 1, 0 },
5021 { "s", opt_list, 0, 0, 0 },
5022 { "t", opt_list_symbols, 0, 0, 0 },
5023 { "w", 0, &flag_no_warnings, 0, 1 },
5024 { "x", 0, 0, 0, 0 }
5025};
5026
5027#define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5028
5029/* The MRI OPT pseudo-op. */
5030
5031static void
5032s_opt (ignore)
5033 int ignore;
5034{
5035 do
5036 {
5037 int t;
5038 char *s;
5039 char c;
5040 int i;
5041 const struct opt_action *o;
5042
5043 SKIP_WHITESPACE ();
5044
5045 t = 1;
5046 if (*input_line_pointer == '-')
5047 {
5048 ++input_line_pointer;
5049 t = 0;
5050 }
5051 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5052 {
5053 input_line_pointer += 2;
5054 t = 0;
5055 }
5056
5057 s = input_line_pointer;
5058 c = get_symbol_end ();
5059
5060 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5061 {
5062 if (strcasecmp (s, o->name) == 0)
5063 {
5064 if (o->pfn)
5065 {
5066 /* Restore input_line_pointer now in case the option
5067 takes arguments. */
5068 *input_line_pointer = c;
5069 (*o->pfn) (o->arg, t);
5070 }
5071 else if (o->pvar != NULL)
5072 {
5073 if (! t && o->arg == o->notarg)
5074 as_bad ("option `%s' may not be negated", s);
5075 *input_line_pointer = c;
5076 *o->pvar = t ? o->arg : o->notarg;
5077 }
9bef2324
ILT		 5078 else
5079 *input_line_pointer = c;
6700d36e
ILT		 5080 break;
5081 }
5082 }
5083 if (i >= OPTCOUNT)
5084 {
5085 as_bad ("option `%s' not recognized", s);
5086 *input_line_pointer = c;
5087 }
5088 }
5089 while (*input_line_pointer++ == ',');
5090
5091 /* Move back to terminating character. */
5092 --input_line_pointer;
5093 demand_empty_rest_of_line ();
5094}
5095
5096/* Skip ahead to a comma. This is used for OPT options which we do
5097 not suppor tand which take arguments. */
5098
5099static void
5100skip_to_comma (arg, on)
5101 int arg;
5102 int on;
5103{
5104 while (*input_line_pointer != ','
5105 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5106 ++input_line_pointer;
5107}
5108
7e047ac2
ILT		 5109/* Handle the OPT NEST=depth option. */
5110
5111static void
5112opt_nest (arg, on)
5113 int arg;
5114 int on;
5115{
5116 if (*input_line_pointer != '=')
5117 {
5118 as_bad ("bad format of OPT NEST=depth");
5119 return;
5120 }
5121
5122 ++input_line_pointer;
5123 max_macro_nest = get_absolute_expression ();
5124}
5125
6700d36e
ILT		 5126/* Handle the OPT P=chip option. */
5127
5128static void
5129opt_chip (arg, on)
5130 int arg;
5131 int on;
5132{
5133 if (*input_line_pointer != '=')
5134 {
5135 /* This is just OPT P, which we do not support. */
5136 return;
5137 }
5138
5139 ++input_line_pointer;
5140 mri_chip ();
5141}
5142
5143/* Handle the OPT S option. */
5144
5145static void
5146opt_list (arg, on)
5147 int arg;
5148 int on;
5149{
5150 listing_list (on);
5151}
5152
5153/* Handle the OPT T option. */
5154
5155static void
5156opt_list_symbols (arg, on)
5157 int arg;
5158 int on;
5159{
5160 if (on)
5161 listing |= LISTING_SYMBOLS;
5162 else
5163 listing &=~ LISTING_SYMBOLS;
5164}
5165
5166/* Handle the MRI REG pseudo-op. */
5167
5168static void
5169s_reg (ignore)
5170 int ignore;
5171{
5172 char *s;
5173 int c;
8e11ad0a 5174 struct m68k_op rop;
6700d36e 5175 unsigned long mask;
f9680a05
ILT		 5176 char *stop = NULL;
5177 char stopc;
6700d36e 5178
7e047ac2 5179 if (line_label == NULL)
6700d36e
ILT		 5180 {
5181 as_bad ("missing label");
5182 ignore_rest_of_line ();
5183 return;
5184 }
5185
f9680a05
ILT		 5186 if (flag_mri)
5187 stop = mri_comment_field (&stopc);
5188
6700d36e
ILT		 5189 SKIP_WHITESPACE ();
5190
5191 s = input_line_pointer;
5192 while (isalnum ((unsigned char) *input_line_pointer)
5193#ifdef REGISTER_PREFIX
5194 || *input_line_pointer == REGISTER_PREFIX
5195#endif
5196 || *input_line_pointer == '/'
5197 || *input_line_pointer == '-')
5198 ++input_line_pointer;
5199 c = *input_line_pointer;
5200 *input_line_pointer = '\0';
5201
8e11ad0a 5202 if (m68k_ip_op (s, &rop) != 0)
6700d36e 5203 {
8e11ad0a 5204 if (rop.error == NULL)
6700d36e
ILT		 5205 as_bad ("bad register list");
5206 else
8e11ad0a 5207 as_bad ("bad register list: %s", rop.error);
6700d36e
ILT		 5208 *input_line_pointer = c;
5209 ignore_rest_of_line ();
5210 return;
5211 }
5212
5213 *input_line_pointer = c;
5214
8e11ad0a
ILT		 5215 if (rop.mode == REGLST)
5216 mask = rop.mask;
5217 else if (rop.mode == DREG)
5218 mask = 1 << (rop.reg - DATA0);
5219 else if (rop.mode == AREG)
5220 mask = 1 << (rop.reg - ADDR0 + 8);
5221 else if (rop.mode == FPREG)
5222 mask = 1 << (rop.reg - FP0 + 16);
5223 else if (rop.mode == CONTROL
5224 && rop.reg == FPI)
6700d36e 5225 mask = 1 << 24;
8e11ad0a
ILT		 5226 else if (rop.mode == CONTROL
5227 && rop.reg == FPS)
6700d36e 5228 mask = 1 << 25;
8e11ad0a
ILT		 5229 else if (rop.mode == CONTROL
5230 && rop.reg == FPC)
6700d36e
ILT		 5231 mask = 1 << 26;
5232 else
5233 {
5234 as_bad ("bad register list");
5235 ignore_rest_of_line ();
5236 return;
5237 }
5238
7e047ac2
ILT		 5239 S_SET_SEGMENT (line_label, absolute_section);
5240 S_SET_VALUE (line_label, mask);
5241 line_label->sy_frag = &zero_address_frag;
6700d36e 5242
85f34122 5243 if (flag_mri)
f9680a05 5244 mri_comment_end (stop, stopc);
85f34122 5245
6700d36e
ILT		 5246 demand_empty_rest_of_line ();
5247}
e14994d9
ILT		 5248
5249/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5250
5251struct save_opts
5252{
5253 struct save_opts *next;
5254 int abspcadd;
5255 int symbols_case_sensitive;
5256 int keep_locals;
5257 int short_refs;
5258 int architecture;
5259 int quick;
5260 int rel32;
5261 int listing;
5262 int no_warnings;
5263 /* FIXME: We don't save OPT S. */
5264};
5265
5266/* This variable holds the stack of saved options. */
5267
5268static struct save_opts *save_stack;
5269
5270/* The MRI SAVE pseudo-op. */
5271
5272static void
5273s_save (ignore)
5274 int ignore;
5275{
5276 struct save_opts *s;
5277
5278 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5279 s->abspcadd = m68k_abspcadd;
5280 s->symbols_case_sensitive = symbols_case_sensitive;
5281 s->keep_locals = flag_keep_locals;
5282 s->short_refs = flag_short_refs;
5283 s->architecture = current_architecture;
5284 s->quick = m68k_quick;
5285 s->rel32 = m68k_rel32;
5286 s->listing = listing;
5287 s->no_warnings = flag_no_warnings;
5288
5289 s->next = save_stack;
5290 save_stack = s;
5291
5292 demand_empty_rest_of_line ();
5293}
5294
5295/* The MRI RESTORE pseudo-op. */
5296
5297static void
5298s_restore (ignore)
5299 int ignore;
5300{
5301 struct save_opts *s;
5302
5303 if (save_stack == NULL)
5304 {
5305 as_bad ("restore without save");
5306 ignore_rest_of_line ();
5307 return;
5308 }
5309
5310 s = save_stack;
5311 save_stack = s->next;
5312
5313 m68k_abspcadd = s->abspcadd;
5314 symbols_case_sensitive = s->symbols_case_sensitive;
5315 flag_keep_locals = s->keep_locals;
5316 flag_short_refs = s->short_refs;
5317 current_architecture = s->architecture;
5318 m68k_quick = s->quick;
5319 m68k_rel32 = s->rel32;
5320 listing = s->listing;
5321 flag_no_warnings = s->no_warnings;
5322
5323 free (s);
5324
5325 demand_empty_rest_of_line ();
5326}
b4ec75e0
ILT		 5327
5328/* Types of MRI structured control directives. */
5329
5330enum mri_control_type
5331{
5332 mri_for,
5333 mri_if,
5334 mri_repeat,
5335 mri_while
5336};
5337
5338/* This structure is used to stack the MRI structured control
5339 directives. */
5340
5341struct mri_control_info
5342{
5343 /* The directive within which this one is enclosed. */
5344 struct mri_control_info *outer;
5345
5346 /* The type of directive. */
5347 enum mri_control_type type;
5348
5349 /* Whether an ELSE has been in an IF. */
5350 int else_seen;
5351
5352 /* The add or sub statement at the end of a FOR. */
5353 char *incr;
5354
5355 /* The label of the top of a FOR or REPEAT loop. */
5356 char *top;
5357
5358 /* The label to jump to for the next iteration, or the else
5359 expression of a conditional. */
5360 char *next;
5361
5362 /* The label to jump to to break out of the loop, or the label past
5363 the end of a conditional. */
5364 char *bottom;
5365};
5366
5367/* The stack of MRI structured control directives. */
5368
5369static struct mri_control_info *mri_control_stack;
5370
5371/* The current MRI structured control directive index number, used to
5372 generate label names. */
5373
5374static int mri_control_index;
5375
5376/* Some function prototypes. */
5377
5378static char *mri_control_label PARAMS ((void));
5379static struct mri_control_info *push_mri_control
5380 PARAMS ((enum mri_control_type));
5381static void pop_mri_control PARAMS ((void));
5382static int parse_mri_condition PARAMS ((int *));
5383static int parse_mri_control_operand
e1c0287d 5384 PARAMS ((int *, char **, char **, char **, char **));
b4ec75e0
ILT		 5385static int swap_mri_condition PARAMS ((int));
5386static int reverse_mri_condition PARAMS ((int));
5387static void build_mri_control_operand
e1c0287d
ILT		 5388 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5389 const char *, int));
b4ec75e0
ILT		 5390static void parse_mri_control_expression
5391 PARAMS ((char *, int, const char *, const char *, int));
5392
5393/* Generate a new MRI label structured control directive label name. */
5394
5395static char *
5396mri_control_label ()
5397{
5398 char *n;
5399
5400 n = (char *) xmalloc (20);
5401 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5402 ++mri_control_index;
5403 return n;
5404}
5405
5406/* Create a new MRI structured control directive. */
5407
5408static struct mri_control_info *
5409push_mri_control (type)
5410 enum mri_control_type type;
5411{
5412 struct mri_control_info *n;
5413
5414 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5415
5416 n->type = type;
5417 n->else_seen = 0;
5418 if (type == mri_if || type == mri_while)
5419 n->top = NULL;
5420 else
5421 n->top = mri_control_label ();
5422 n->next = mri_control_label ();
5423 n->bottom = mri_control_label ();
5424
5425 n->outer = mri_control_stack;
5426 mri_control_stack = n;
5427
5428 return n;
5429}
5430
5431/* Pop off the stack of MRI structured control directives. */
5432
5433static void
5434pop_mri_control ()
5435{
5436 struct mri_control_info *n;
5437
5438 n = mri_control_stack;
5439 mri_control_stack = n->outer;
5440 if (n->top != NULL)
5441 free (n->top);
5442 free (n->next);
5443 free (n->bottom);
5444 free (n);
5445}
5446
5447/* Recognize a condition code in an MRI structured control expression. */
5448
5449static int
5450parse_mri_condition (pcc)
5451 int *pcc;
5452{
5453 char c1, c2;
5454
5455 know (*input_line_pointer == '<');
5456
5457 ++input_line_pointer;
5458 c1 = *input_line_pointer++;
5459 c2 = *input_line_pointer++;
5460
5461 if (*input_line_pointer != '>')
5462 {
5463 as_bad ("syntax error in structured control directive");
5464 return 0;
5465 }
5466
5467 ++input_line_pointer;
5468 SKIP_WHITESPACE ();
5469
5470 if (isupper (c1))
5471 c1 = tolower (c1);
5472 if (isupper (c2))
5473 c2 = tolower (c2);
5474
5475 *pcc = (c1 << 8) | c2;
5476
5477 return 1;
5478}
5479
5480/* Parse a single operand in an MRI structured control expression. */
5481
5482static int
5483parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5484 int *pcc;
b3625fe6 5485 char **leftstart;
e1c0287d 5486 char **leftstop;
b3625fe6 5487 char **rightstart;
e1c0287d 5488 char **rightstop;
b4ec75e0
ILT		 5489{
5490 char *s;
5491
5492 SKIP_WHITESPACE ();
5493
5494 *pcc = -1;
5495 *leftstart = NULL;
5496 *leftstop = NULL;
5497 *rightstart = NULL;
5498 *rightstop = NULL;
5499
5500 if (*input_line_pointer == '<')
5501 {
5502 /* It's just a condition code. */
5503 return parse_mri_condition (pcc);
5504 }
5505
5506 /* Look ahead for the condition code. */
5507 for (s = input_line_pointer; *s != '\0'; ++s)
5508 {
5509 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5510 break;
5511 }
5512 if (*s == '\0')
5513 {
5514 as_bad ("missing condition code in structured control directive");
5515 return 0;
5516 }
5517
5518 *leftstart = input_line_pointer;
5519 *leftstop = s;
4026c122
ILT		 5520 if (*leftstop > *leftstart
5521 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5522 --*leftstop;
b4ec75e0
ILT		 5523
5524 input_line_pointer = s;
5525 if (! parse_mri_condition (pcc))
5526 return 0;
5527
5528 /* Look ahead for AND or OR or end of line. */
5529 for (s = input_line_pointer; *s != '\0'; ++s)
5530 {
5531 if ((strncasecmp (s, "AND", 3) == 0
5532 && (s[3] == '.' || ! is_part_of_name (s[3])))
5533 || (strncasecmp (s, "OR", 2) == 0
5534 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5535 break;
5536 }
5537
5538 *rightstart = input_line_pointer;
5539 *rightstop = s;
4026c122
ILT		 5540 if (*rightstop > *rightstart
5541 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5542 --*rightstop;
b4ec75e0
ILT		 5543
5544 input_line_pointer = s;
5545
5546 return 1;
5547}
5548
5549#define MCC(b1, b2) (((b1) << 8) | (b2))
5550
5551/* Swap the sense of a condition. This changes the condition so that
5552 it generates the same result when the operands are swapped. */
5553
5554static int
5555swap_mri_condition (cc)
5556 int cc;
5557{
5558 switch (cc)
5559 {
5560 case MCC ('h', 'i'): return MCC ('c', 's');
5561 case MCC ('l', 's'): return MCC ('c', 'c');
5562 case MCC ('c', 'c'): return MCC ('l', 's');
5563 case MCC ('c', 's'): return MCC ('h', 'i');
5564 case MCC ('p', 'l'): return MCC ('m', 'i');
5565 case MCC ('m', 'i'): return MCC ('p', 'l');
5566 case MCC ('g', 'e'): return MCC ('l', 'e');
5567 case MCC ('l', 't'): return MCC ('g', 't');
5568 case MCC ('g', 't'): return MCC ('l', 't');
5569 case MCC ('l', 'e'): return MCC ('g', 'e');
5570 }
5571 return cc;
5572}
5573
5574/* Reverse the sense of a condition. */
5575
5576static int
5577reverse_mri_condition (cc)
5578 int cc;
5579{
5580 switch (cc)
5581 {
5582 case MCC ('h', 'i'): return MCC ('l', 's');
5583 case MCC ('l', 's'): return MCC ('h', 'i');
5584 case MCC ('c', 'c'): return MCC ('c', 's');
5585 case MCC ('c', 's'): return MCC ('c', 'c');
5586 case MCC ('n', 'e'): return MCC ('e', 'q');
5587 case MCC ('e', 'q'): return MCC ('n', 'e');
5588 case MCC ('v', 'c'): return MCC ('v', 's');
5589 case MCC ('v', 's'): return MCC ('v', 'c');
5590 case MCC ('p', 'l'): return MCC ('m', 'i');
5591 case MCC ('m', 'i'): return MCC ('p', 'l');
5592 case MCC ('g', 'e'): return MCC ('l', 't');
5593 case MCC ('l', 't'): return MCC ('g', 'e');
5594 case MCC ('g', 't'): return MCC ('l', 'e');
5595 case MCC ('l', 'e'): return MCC ('g', 't');
5596 }
5597 return cc;
5598}
5599
5600/* Build an MRI structured control expression. This generates test
5601 and branch instructions. It goes to TRUELAB if the condition is
5602 true, and to FALSELAB if the condition is false. Exactly one of
5603 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5604 is the size qualifier for the expression. EXTENT is the size to
5605 use for the branch. */
5606
5607static void
5608build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5609 rightstop, truelab, falselab, extent)
5610 int qual;
5611 int cc;
b3625fe6 5612 char *leftstart;
e1c0287d 5613 char *leftstop;
b3625fe6 5614 char *rightstart;
e1c0287d 5615 char *rightstop;
b4ec75e0
ILT		 5616 const char *truelab;
5617 const char *falselab;
5618 int extent;
5619{
5620 char *buf;
5621 char *s;
5622
e1c0287d 5623 if (leftstart != NULL)
b3625fe6 5624 {
e1c0287d
ILT		 5625 struct m68k_op leftop, rightop;
5626 char c;
b3625fe6 5627
e1c0287d
ILT		 5628 /* Swap the compare operands, if necessary, to produce a legal
5629 m68k compare instruction. Comparing a register operand with
5630 a non-register operand requires the register to be on the
5631 right (cmp, cmpa). Comparing an immediate value with
5632 anything requires the immediate value to be on the left
5633 (cmpi). */
5634
5635 c = *leftstop;
5636 *leftstop = '\0';
5637 (void) m68k_ip_op (leftstart, &leftop);
5638 *leftstop = c;
5639
5640 c = *rightstop;
5641 *rightstop = '\0';
5642 (void) m68k_ip_op (rightstart, &rightop);
5643 *rightstop = c;
5644
5645 if (rightop.mode == IMMED
5646 || ((leftop.mode == DREG || leftop.mode == AREG)
5647 && (rightop.mode != DREG && rightop.mode != AREG)))
5648 {
5649 char *temp;
5650
5651 cc = swap_mri_condition (cc);
5652 temp = leftstart;
5653 leftstart = rightstart;
5654 rightstart = temp;
5655 temp = leftstop;
5656 leftstop = rightstop;
5657 rightstop = temp;
5658 }
b4ec75e0
ILT		 5659 }
5660
5661 if (truelab == NULL)
5662 {
5663 cc = reverse_mri_condition (cc);
5664 truelab = falselab;
5665 }
5666
5667 if (leftstart != NULL)
5668 {
5669 buf = (char *) xmalloc (20
5670 + (leftstop - leftstart)
5671 + (rightstop - rightstart));
5672 s = buf;
5673 *s++ = 'c';
5674 *s++ = 'm';
5675 *s++ = 'p';
5676 if (qual != '\0')
5677 *s++ = qual;
5678 *s++ = ' ';
5679 memcpy (s, leftstart, leftstop - leftstart);
5680 s += leftstop - leftstart;
5681 *s++ = ',';
5682 memcpy (s, rightstart, rightstop - rightstart);
5683 s += rightstop - rightstart;
5684 *s = '\0';
5685 md_assemble (buf);
5686 free (buf);
5687 }
5688
5689 buf = (char *) xmalloc (20 + strlen (truelab));
5690 s = buf;
5691 *s++ = 'b';
5692 *s++ = cc >> 8;
5693 *s++ = cc & 0xff;
5694 if (extent != '\0')
5695 *s++ = extent;
5696 *s++ = ' ';
5697 strcpy (s, truelab);
5698 md_assemble (buf);
5699 free (buf);
5700}
5701
5702/* Parse an MRI structured control expression. This generates test
5703 and branch instructions. STOP is where the expression ends. It
5704 goes to TRUELAB if the condition is true, and to FALSELAB if the
5705 condition is false. Exactly one of TRUELAB and FALSELAB will be
5706 NULL, meaning to fall through. QUAL is the size qualifier for the
5707 expression. EXTENT is the size to use for the branch. */
5708
5709static void
5710parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5711 char *stop;
5712 int qual;
5713 const char *truelab;
5714 const char *falselab;
5715 int extent;
5716{
5717 int c;
5718 int cc;
b3625fe6 5719 char *leftstart;
e1c0287d 5720 char *leftstop;
b3625fe6 5721 char *rightstart;
e1c0287d 5722 char *rightstop;
b4ec75e0
ILT		 5723
5724 c = *stop;
5725 *stop = '\0';
5726
5727 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5728 &rightstart, &rightstop))
5729 {
5730 *stop = c;
5731 return;
5732 }
5733
5734 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5735 {
5736 const char *flab;
5737
5738 if (falselab != NULL)
5739 flab = falselab;
5740 else
5741 flab = mri_control_label ();
5742
5743 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5744 rightstop, (const char *) NULL, flab, extent);
5745
5746 input_line_pointer += 3;
5747 if (*input_line_pointer != '.'
5748 || input_line_pointer[1] == '\0')
5749 qual = '\0';
5750 else
5751 {
5752 qual = input_line_pointer[1];
5753 input_line_pointer += 2;
5754 }
5755
5756 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5757 &rightstart, &rightstop))
5758 {
5759 *stop = c;
5760 return;
5761 }
5762
5763 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5764 rightstop, truelab, falselab, extent);
5765
5766 if (falselab == NULL)
5767 colon (flab);
5768 }
5769 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5770 {
5771 const char *tlab;
5772
5773 if (truelab != NULL)
5774 tlab = truelab;
5775 else
5776 tlab = mri_control_label ();
5777
5778 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5779 rightstop, tlab, (const char *) NULL, extent);
5780
5781 input_line_pointer += 2;
5782 if (*input_line_pointer != '.'
5783 || input_line_pointer[1] == '\0')
5784 qual = '\0';
5785 else
5786 {
5787 qual = input_line_pointer[1];
5788 input_line_pointer += 2;
5789 }
5790
5791 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5792 &rightstart, &rightstop))
5793 {
5794 *stop = c;
5795 return;
5796 }
5797
5798 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5799 rightstop, truelab, falselab, extent);
5800
5801 if (truelab == NULL)
5802 colon (tlab);
5803 }
5804 else
5805 {
5806 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5807 rightstop, truelab, falselab, extent);
5808 }
5809
5810 *stop = c;
5811 if (input_line_pointer != stop)
5812 as_bad ("syntax error in structured control directive");
5813}
5814
5815/* Handle the MRI IF pseudo-op. This may be a structured control
5816 directive, or it may be a regular assembler conditional, depending
5817 on its operands. */
5818
5819static void
5820s_mri_if (qual)
5821 int qual;
5822{
5823 char *s;
5824 int c;
5825 struct mri_control_info *n;
5826
5827 /* A structured control directive must end with THEN with an
5828 optional qualifier. */
5829 s = input_line_pointer;
e1c0287d
ILT		 5830 while (! is_end_of_line[(unsigned char) *s]
5831 && (! flag_mri || *s != '*'))
b4ec75e0
ILT		 5832 ++s;
5833 --s;
5834 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5835 --s;
5836
5837 if (s - input_line_pointer > 1
5838 && s[-1] == '.')
5839 s -= 2;
5840
5841 if (s - input_line_pointer < 3
5842 || strncasecmp (s - 3, "THEN", 4) != 0)
5843 {
5844 if (qual != '\0')
5845 {
5846 as_bad ("missing then");
5847 ignore_rest_of_line ();
5848 return;
5849 }
5850
5851 /* It's a conditional. */
5852 s_if (O_ne);
5853 return;
5854 }
5855
5856 /* Since this might be a conditional if, this pseudo-op will be
5857 called even if we are supported to be ignoring input. Double
5858 check now. Clobber *input_line_pointer so that ignore_input
5859 thinks that this is not a special pseudo-op. */
5860 c = *input_line_pointer;
5861 *input_line_pointer = 0;
5862 if (ignore_input ())
5863 {
5864 *input_line_pointer = c;
5865 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5866 ++input_line_pointer;
5867 demand_empty_rest_of_line ();
5868 return;
5869 }
5870 *input_line_pointer = c;
5871
5872 n = push_mri_control (mri_if);
5873
5874 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5875 n->next, s[1] == '.' ? s[2] : '\0');
5876
5877 if (s[1] == '.')
5878 input_line_pointer = s + 3;
5879 else
5880 input_line_pointer = s + 1;
5881
e1c0287d
ILT		 5882 if (flag_mri)
5883 {
5884 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5885 ++input_line_pointer;
5886 }
5887
b4ec75e0
ILT		 5888 demand_empty_rest_of_line ();
5889}
5890
5891/* Handle the MRI else pseudo-op. If we are currently doing an MRI
5892 structured IF, associate the ELSE with the IF. Otherwise, assume
5893 it is a conditional else. */
5894
5895static void
5896s_mri_else (qual)
5897 int qual;
5898{
5899 int c;
5900 char *buf;
5901 char q[2];
5902
5903 if (qual == '\0'
5904 && (mri_control_stack == NULL
5905 || mri_control_stack->type != mri_if
5906 || mri_control_stack->else_seen))
5907 {
5908 s_else (0);
5909 return;
5910 }
5911
5912 c = *input_line_pointer;
5913 *input_line_pointer = 0;
5914 if (ignore_input ())
5915 {
5916 *input_line_pointer = c;
5917 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5918 ++input_line_pointer;
5919 demand_empty_rest_of_line ();
5920 return;
5921 }
5922 *input_line_pointer = c;
5923
5924 if (mri_control_stack == NULL
5925 || mri_control_stack->type != mri_if
5926 || mri_control_stack->else_seen)
5927 {
5928 as_bad ("else without matching if");
5929 ignore_rest_of_line ();
5930 return;
5931 }
5932
5933 mri_control_stack->else_seen = 1;
5934
5935 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5936 q[0] = qual;
5937 q[1] = '\0';
5938 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5939 md_assemble (buf);
5940 free (buf);
5941
5942 colon (mri_control_stack->next);
5943
e1c0287d
ILT		 5944 if (flag_mri)
5945 {
5946 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5947 ++input_line_pointer;
5948 }
5949
b4ec75e0
ILT		 5950 demand_empty_rest_of_line ();
5951}
5952
5953/* Handle the MRI ENDI pseudo-op. */
5954
5955static void
5956s_mri_endi (ignore)
5957 int ignore;
5958{
5959 if (mri_control_stack == NULL
5960 || mri_control_stack->type != mri_if)
5961 {
5962 as_bad ("endi without matching if");
5963 ignore_rest_of_line ();
5964 return;
5965 }
5966
5967 /* ignore_input will not return true for ENDI, so we don't need to
5968 worry about checking it again here. */
5969
5970 if (! mri_control_stack->else_seen)
5971 colon (mri_control_stack->next);
5972 colon (mri_control_stack->bottom);
5973
5974 pop_mri_control ();
5975
e1c0287d
ILT		 5976 if (flag_mri)
5977 {
5978 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5979 ++input_line_pointer;
5980 }
5981
b4ec75e0
ILT		 5982 demand_empty_rest_of_line ();
5983}
5984
5985/* Handle the MRI BREAK pseudo-op. */
5986
5987static void
5988s_mri_break (extent)
5989 int extent;
5990{
5991 struct mri_control_info *n;
5992 char *buf;
5993 char ex[2];
5994
5995 n = mri_control_stack;
5996 while (n != NULL
5997 && n->type != mri_for
5998 && n->type != mri_repeat
5999 && n->type != mri_while)
6000 n = n->outer;
6001 if (n == NULL)
6002 {
6003 as_bad ("break outside of structured loop");
6004 ignore_rest_of_line ();
6005 return;
6006 }
6007
6008 buf = (char *) xmalloc (20 + strlen (n->bottom));
6009 ex[0] = extent;
6010 ex[1] = '\0';
6011 sprintf (buf, "bra%s %s", ex, n->bottom);
6012 md_assemble (buf);
6013 free (buf);
6014
e1c0287d
ILT		 6015 if (flag_mri)
6016 {
6017 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6018 ++input_line_pointer;
6019 }
6020
b4ec75e0
ILT		 6021 demand_empty_rest_of_line ();
6022}
6023
6024/* Handle the MRI NEXT pseudo-op. */
6025
6026static void
6027s_mri_next (extent)
6028 int extent;
6029{
6030 struct mri_control_info *n;
6031 char *buf;
6032 char ex[2];
6033
6034 n = mri_control_stack;
6035 while (n != NULL
6036 && n->type != mri_for
6037 && n->type != mri_repeat
6038 && n->type != mri_while)
6039 n = n->outer;
6040 if (n == NULL)
6041 {
6042 as_bad ("next outside of structured loop");
6043 ignore_rest_of_line ();
6044 return;
6045 }
6046
6047 buf = (char *) xmalloc (20 + strlen (n->next));
6048 ex[0] = extent;
6049 ex[1] = '\0';
6050 sprintf (buf, "bra%s %s", ex, n->next);
6051 md_assemble (buf);
6052 free (buf);
6053
e1c0287d
ILT		 6054 if (flag_mri)
6055 {
6056 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6057 ++input_line_pointer;
6058 }
6059
b4ec75e0
ILT		 6060 demand_empty_rest_of_line ();
6061}
6062
6063/* Handle the MRI FOR pseudo-op. */
6064
6065static void
6066s_mri_for (qual)
6067 int qual;
6068{
6069 const char *varstart, *varstop;
6070 const char *initstart, *initstop;
6071 const char *endstart, *endstop;
6072 const char *bystart, *bystop;
6073 int up;
6074 int by;
6075 int extent;
6076 struct mri_control_info *n;
6077 char *buf;
6078 char *s;
6079 char ex[2];
6080
6081 /* The syntax is
6082 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6083 */
6084
4026c122 6085 SKIP_WHITESPACE ();
b4ec75e0
ILT		 6086 varstart = input_line_pointer;
6087
6088 /* Look for the '='. */
6089 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6090 && *input_line_pointer != '=')
6091 ++input_line_pointer;
6092 if (*input_line_pointer != '=')
6093 {
6094 as_bad ("missing =");
6095 ignore_rest_of_line ();
6096 return;
6097 }
6098
6099 varstop = input_line_pointer;
4026c122
ILT		 6100 if (varstop > varstart
6101 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6102 --varstop;
b4ec75e0
ILT		 6103
6104 ++input_line_pointer;
6105
6106 initstart = input_line_pointer;
6107
6108 /* Look for TO or DOWNTO. */
6109 up = 1;
6110 initstop = NULL;
6111 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6112 {
6113 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6114 && ! is_part_of_name (input_line_pointer[2]))
6115 {
6116 initstop = input_line_pointer;
6117 input_line_pointer += 2;
6118 break;
6119 }
6120 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6121 && ! is_part_of_name (input_line_pointer[6]))
6122 {
6123 initstop = input_line_pointer;
6124 up = 0;
6125 input_line_pointer += 6;
6126 break;
6127 }
6128 ++input_line_pointer;
6129 }
6130 if (initstop == NULL)
6131 {
6132 as_bad ("missing to or downto");
6133 ignore_rest_of_line ();
6134 return;
6135 }
4026c122
ILT		 6136 if (initstop > initstart
6137 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6138 --initstop;
b4ec75e0 6139
4026c122 6140 SKIP_WHITESPACE ();
b4ec75e0
ILT		 6141 endstart = input_line_pointer;
6142
6143 /* Look for BY or DO. */
6144 by = 0;
6145 endstop = NULL;
6146 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6147 {
6148 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6149 && ! is_part_of_name (input_line_pointer[2]))
6150 {
6151 endstop = input_line_pointer;
6152 by = 1;
6153 input_line_pointer += 2;
6154 break;
6155 }
6156 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6157 && (input_line_pointer[2] == '.'
6158 || ! is_part_of_name (input_line_pointer[2])))
6159 {
6160 endstop = input_line_pointer;
6161 input_line_pointer += 2;
6162 break;
6163 }
6164 ++input_line_pointer;
6165 }
6166 if (endstop == NULL)
6167 {
6168 as_bad ("missing do");
6169 ignore_rest_of_line ();
6170 return;
6171 }
4026c122
ILT		 6172 if (endstop > endstart
6173 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6174 --endstop;
b4ec75e0
ILT		 6175
6176 if (! by)
6177 {
6178 bystart = "#1";
6179 bystop = bystart + 2;
6180 }
6181 else
6182 {
4026c122 6183 SKIP_WHITESPACE ();
b4ec75e0
ILT		 6184 bystart = input_line_pointer;
6185
6186 /* Look for DO. */
6187 bystop = NULL;
6188 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6189 {
6190 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6191 && (input_line_pointer[2] == '.'
6192 || ! is_part_of_name (input_line_pointer[2])))
6193 {
6194 bystop = input_line_pointer;
6195 input_line_pointer += 2;
6196 break;
6197 }
6198 ++input_line_pointer;
6199 }
6200 if (bystop == NULL)
6201 {
6202 as_bad ("missing do");
6203 ignore_rest_of_line ();
6204 return;
6205 }
4026c122
ILT		 6206 if (bystop > bystart
6207 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6208 --bystop;
b4ec75e0
ILT		 6209 }
6210
6211 if (*input_line_pointer != '.')
6212 extent = '\0';
6213 else
6214 {
6215 extent = input_line_pointer[1];
6216 input_line_pointer += 2;
6217 }
6218
6219 /* We have fully parsed the FOR operands. Now build the loop. */
6220
6221 n = push_mri_control (mri_for);
6222
6223 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6224
6225 /* move init,var */
6226 s = buf;
6227 *s++ = 'm';
6228 *s++ = 'o';
6229 *s++ = 'v';
6230 *s++ = 'e';
6231 if (qual != '\0')
6232 *s++ = qual;
6233 *s++ = ' ';
6234 memcpy (s, initstart, initstop - initstart);
6235 s += initstop - initstart;
6236 *s++ = ',';
6237 memcpy (s, varstart, varstop - varstart);
6238 s += varstop - varstart;
6239 *s = '\0';
6240 md_assemble (buf);
6241
6242 colon (n->top);
6243
6244 /* cmp end,var */
6245 s = buf;
6246 *s++ = 'c';
6247 *s++ = 'm';
6248 *s++ = 'p';
6249 if (qual != '\0')
6250 *s++ = qual;
6251 *s++ = ' ';
6252 memcpy (s, endstart, endstop - endstart);
6253 s += endstop - endstart;
6254 *s++ = ',';
6255 memcpy (s, varstart, varstop - varstart);
6256 s += varstop - varstart;
6257 *s = '\0';
6258 md_assemble (buf);
6259
6260 /* bcc bottom */
6261 ex[0] = extent;
6262 ex[1] = '\0';
6263 if (up)
6264 sprintf (buf, "blt%s %s", ex, n->bottom);
6265 else
6266 sprintf (buf, "bgt%s %s", ex, n->bottom);
6267 md_assemble (buf);
6268
6269 /* Put together the add or sub instruction used by ENDF. */
6270 s = buf;
6271 if (up)
6272 strcpy (s, "add");
6273 else
6274 strcpy (s, "sub");
6275 s += 3;
6276 if (qual != '\0')
6277 *s++ = qual;
6278 *s++ = ' ';
6279 memcpy (s, bystart, bystop - bystart);
6280 s += bystop - bystart;
6281 *s++ = ',';
6282 memcpy (s, varstart, varstop - varstart);
6283 s += varstop - varstart;
6284 *s = '\0';
6285 n->incr = buf;
6286
e1c0287d
ILT		 6287 if (flag_mri)
6288 {
6289 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6290 ++input_line_pointer;
6291 }
6292
b4ec75e0
ILT		 6293 demand_empty_rest_of_line ();
6294}
6295
6296/* Handle the MRI ENDF pseudo-op. */
6297
6298static void
6299s_mri_endf (ignore)
6300 int ignore;
6301{
6302 if (mri_control_stack == NULL
6303 || mri_control_stack->type != mri_for)
6304 {
6305 as_bad ("endf without for");
6306 ignore_rest_of_line ();
6307 return;
6308 }
6309
6310 colon (mri_control_stack->next);
6311
6312 md_assemble (mri_control_stack->incr);
6313
6314 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6315 md_assemble (mri_control_stack->incr);
6316
6317 free (mri_control_stack->incr);
6318
6319 colon (mri_control_stack->bottom);
6320
6321 pop_mri_control ();
6322
e1c0287d
ILT		 6323 if (flag_mri)
6324 {
6325 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6326 ++input_line_pointer;
6327 }
6328
b4ec75e0
ILT		 6329 demand_empty_rest_of_line ();
6330}
6331
6332/* Handle the MRI REPEAT pseudo-op. */
6333
6334static void
6335s_mri_repeat (ignore)
6336 int ignore;
6337{
6338 struct mri_control_info *n;
6339
6340 n = push_mri_control (mri_repeat);
6341 colon (n->top);
e1c0287d
ILT		 6342 if (flag_mri)
6343 {
6344 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6345 ++input_line_pointer;
6346 }
b4ec75e0
ILT		 6347 demand_empty_rest_of_line ();
6348}
6349
6350/* Handle the MRI UNTIL pseudo-op. */
6351
6352static void
6353s_mri_until (qual)
6354 int qual;
6355{
6356 char *s;
6357
6358 if (mri_control_stack == NULL
6359 || mri_control_stack->type != mri_repeat)
6360 {
6361 as_bad ("until without repeat");
6362 ignore_rest_of_line ();
6363 return;
6364 }
6365
6366 colon (mri_control_stack->next);
6367
6368 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6369 ;
6370
6371 parse_mri_control_expression (s, qual, (const char *) NULL,
6372 mri_control_stack->top, '\0');
6373
6374 colon (mri_control_stack->bottom);
6375
6376 input_line_pointer = s;
6377
9e64486e
ILT		 6378 pop_mri_control ();
6379
e1c0287d
ILT		 6380 if (flag_mri)
6381 {
6382 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6383 ++input_line_pointer;
6384 }
6385
b4ec75e0
ILT		 6386 demand_empty_rest_of_line ();
6387}
6388
6389/* Handle the MRI WHILE pseudo-op. */
6390
6391static void
6392s_mri_while (qual)
6393 int qual;
6394{
6395 char *s;
6396
6397 struct mri_control_info *n;
6398
6399 s = input_line_pointer;
e1c0287d
ILT		 6400 while (! is_end_of_line[(unsigned char) *s]
6401 && (! flag_mri || *s != '*'))
b4ec75e0
ILT		 6402 s++;
6403 --s;
6404 while (*s == ' ' || *s == '\t')
6405 --s;
6406 if (s - input_line_pointer > 1
6407 && s[-1] == '.')
6408 s -= 2;
6409 if (s - input_line_pointer < 2
6410 || strncasecmp (s - 1, "DO", 2) != 0)
6411 {
6412 as_bad ("missing do");
6413 ignore_rest_of_line ();
6414 return;
6415 }
6416
6417 n = push_mri_control (mri_while);
6418
6419 colon (n->next);
6420
6421 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6422 s[1] == '.' ? s[2] : '\0');
6423
6424 input_line_pointer = s + 1;
6425 if (*input_line_pointer == '.')
6426 input_line_pointer += 2;
6427
e1c0287d
ILT		 6428 if (flag_mri)
6429 {
6430 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6431 ++input_line_pointer;
6432 }
6433
b4ec75e0
ILT		 6434 demand_empty_rest_of_line ();
6435}
6436
6437/* Handle the MRI ENDW pseudo-op. */
6438
6439static void
6440s_mri_endw (ignore)
6441 int ignore;
6442{
6443 char *buf;
6444
6445 if (mri_control_stack == NULL
6446 || mri_control_stack->type != mri_while)
6447 {
6448 as_bad ("endw without while");
6449 ignore_rest_of_line ();
6450 return;
6451 }
6452
6453 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6454 sprintf (buf, "bra %s", mri_control_stack->next);
6455 md_assemble (buf);
6456 free (buf);
6457
6458 colon (mri_control_stack->bottom);
6459
6460 pop_mri_control ();
6461
e1c0287d
ILT		 6462 if (flag_mri)
6463 {
6464 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6465 ++input_line_pointer;
6466 }
6467
b4ec75e0
ILT		 6468 demand_empty_rest_of_line ();
6469}
f3d817d8 6470\f
7c15cbe8
RP		 6471/*
6472 * md_parse_option
6473 * Invocation line includes a switch not recognized by the base assembler.
6474 * See if it's a processor-specific option. These are:
6475 *
6476 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6477 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6478 * Select the architecture. Instructions or features not
6479 * supported by the selected architecture cause fatal
6480 * errors. More than one may be specified. The default is
6481 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6482 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 6483 * -[A]m[c]no-68851, -[A]m[c]no-68881
6484 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6485 * so don't use or document it, but that's the way the parsing
6486 * works).
7c15cbe8 6487 *
dff60b7d
ILT		 6488 * -pic Indicates PIC.
6489 * -k Indicates PIC. (Sun 3 only.)
b80d39a0 6490 *
8d20a0a8
C		 6491 * --bitwise-or
6492 * Permit `|' to be used in expressions.
6493 *
7c15cbe8
RP		 6494 */
6495
5f8cb05e
ILT		 6496#ifdef OBJ_ELF
6497CONST char *md_shortopts = "lSA:m:kQ:V";
6498#else
f3d817d8 6499CONST char *md_shortopts = "lSA:m:k";
5f8cb05e
ILT		 6500#endif
6501
f3d817d8
DM		 6502struct option md_longopts[] = {
6503#define OPTION_PIC (OPTION_MD_BASE)
6504 {"pic", no_argument, NULL, OPTION_PIC},
6505#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6506 {"register-prefix-optional", no_argument, NULL,
6507 OPTION_REGISTER_PREFIX_OPTIONAL},
8d20a0a8
C		 6508#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6509 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
b4d51f3d
ILT		 6510#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6511 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6512#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6513 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
924160b0
ILT		 6514#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6515 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6516#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6517 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
f3d817d8
DM		 6518 {NULL, no_argument, NULL, 0}
6519};
6520size_t md_longopts_size = sizeof(md_longopts);
82489ea0 6521
355afbcd 6522int
f3d817d8
DM		 6523md_parse_option (c, arg)
6524 int c;
6525 char *arg;
fecd2382 6526{
f3d817d8 6527 switch (c)
355afbcd
KR		 6528 {
6529 case 'l': /* -l means keep external to 2 bit offset
e284846a 6530 rather than 16 bit one */
9ad5755f 6531 flag_short_refs = 1;
355afbcd 6532 break;
6d27d3a2 6533
e284846a
KR		 6534 case 'S': /* -S means that jbsr's always turn into
6535 jsr's. */
9ad5755f 6536 flag_long_jumps = 1;
355afbcd 6537 break;
6d27d3a2 6538
355afbcd 6539 case 'A':
f3d817d8
DM		 6540 if (*arg == 'm')
6541 arg++;
355afbcd
KR		 6542 /* intentional fall-through */
6543 case 'm':
355afbcd 6544
b79de3a1 6545 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
e284846a 6546 {
064ba683
ILT		 6547 int i;
6548 unsigned long arch;
b79de3a1
KR		 6549 const char *oarg = arg;
6550
6551 arg += 3;
6552 if (*arg == 'm')
6553 {
6554 arg++;
6555 if (arg[0] == 'c' && arg[1] == '6')
6556 arg++;
6557 }
6558 for (i = 0; i < n_archs; i++)
6559 if (!strcmp (arg, archs[i].name))
6560 break;
6561 if (i == n_archs)
6562 {
6563 unknown:
6564 as_bad ("unrecognized option `%s'", oarg);
6565 return 0;
6566 }
6567 arch = archs[i].arch;
6568 if (arch == m68881)
6569 no_68881 = 1;
6570 else if (arch == m68851)
6571 no_68851 = 1;
6572 else
6573 goto unknown;
355afbcd
KR		 6574 }
6575 else
6576 {
b79de3a1
KR		 6577 int i;
6578
6579 if (arg[0] == 'c' && arg[1] == '6')
6580 arg++;
6581
6582 for (i = 0; i < n_archs; i++)
6583 if (!strcmp (arg, archs[i].name))
6584 {
6585 unsigned long arch = archs[i].arch;
6586 if (cpu_of_arch (arch))
6587 /* It's a cpu spec. */
6588 {
6589 current_architecture &= ~m68000up;
6590 current_architecture |= arch;
6591 }
6592 else if (arch == m68881)
6593 {
6594 current_architecture |= m68881;
6595 no_68881 = 0;
6596 }
6597 else if (arch == m68851)
6598 {
6599 current_architecture |= m68851;
6600 no_68851 = 0;
6601 }
6602 else
6603 /* ??? */
6604 abort ();
6605 break;
6606 }
6607 if (i == n_archs)
6608 {
6609 as_bad ("unrecognized architecture specification `%s'", arg);
6610 return 0;
6611 }
f8701a3f 6612 }
f3d817d8 6613 break;
dff60b7d 6614
f3d817d8 6615 case OPTION_PIC:
dff60b7d
ILT		 6616 case 'k':
6617 flag_want_pic = 1;
f3d817d8
DM		 6618 break; /* -pic, Position Independent Code */
6619
6620 case OPTION_REGISTER_PREFIX_OPTIONAL:
6621 flag_reg_prefix_optional = 1;
20710f1c 6622 reg_prefix_optional_seen = 1;
dff60b7d 6623 break;
355afbcd 6624
a043f579 6625 /* -V: SVR4 argument to print version ID. */
5f8cb05e 6626 case 'V':
a043f579
ILT		 6627 print_version_id ();
6628 break;
6629
6630 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6631 should be emitted or not. FIXME: Not implemented. */
6632 case 'Q':
5f8cb05e
ILT		 6633 break;
6634
8d20a0a8
C		 6635 case OPTION_BITWISE_OR:
6636 {
6637 char *n, *t;
6638 const char *s;
6639
6640 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6641 t = n;
6642 for (s = m68k_comment_chars; *s != '\0'; s++)
6643 if (*s != '|')
6644 *t++ = *s;
6645 *t = '\0';
6646 m68k_comment_chars = n;
6647 }
6648 break;
6649
b4d51f3d
ILT		 6650 case OPTION_BASE_SIZE_DEFAULT_16:
6651 m68k_index_width_default = SIZE_WORD;
6652 break;
6653
6654 case OPTION_BASE_SIZE_DEFAULT_32:
6655 m68k_index_width_default = SIZE_LONG;
6656 break;
6657
924160b0
ILT		 6658 case OPTION_DISP_SIZE_DEFAULT_16:
6659 m68k_rel32 = 0;
6660 m68k_rel32_from_cmdline = 1;
6661 break;
6662
6663 case OPTION_DISP_SIZE_DEFAULT_32:
6664 m68k_rel32 = 1;
6665 m68k_rel32_from_cmdline = 1;
6666 break;
6667
355afbcd
KR		 6668 default:
6669 return 0;
6670 }
f3d817d8 6671
355afbcd 6672 return 1;
fecd2382
RP		 6673}
6674
f3d817d8
DM		 6675void
6676md_show_usage (stream)
6677 FILE *stream;
6678{
6679 fprintf(stream, "\
6680680X0 options:\n\
6681-l use 1 word for refs to undefined symbols [default 2]\n\
5f8cb05e
ILT		 6682-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6683 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
7f003b7f 6684 | -mcpu32 | -m5200\n\
f3d817d8
DM		 6685 specify variant of 680X0 architecture [default 68020]\n\
6686-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6687 target has/lacks floating-point coprocessor\n\
92a25e12
ILT		 6688 [default yes for 68020, 68030, and cpu32]\n");
6689 fprintf(stream, "\
f3d817d8
DM		 6690-m68851 | -mno-68851\n\
6691 target has/lacks memory-management unit coprocessor\n\
6692 [default yes for 68020 and up]\n\
6693-pic, -k generate position independent code\n\
6694-S turn jbsr into jsr\n\
6695--register-prefix-optional\n\
8d20a0a8
C		 6696 recognize register names without prefix character\n\
6697--bitwise-or do not treat `|' as a comment character\n");
b4d51f3d
ILT		 6698 fprintf (stream, "\
6699--base-size-default-16 base reg without size is 16 bits\n\
924160b0
ILT		 6700--base-size-default-32 base reg without size is 32 bits (default)\n\
6701--disp-size-default-16 displacement with unknown size is 16 bits\n\
6702--disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
f3d817d8
DM		 6703}
6704\f
fecd2382
RP		 6705#ifdef TEST2
6706
6707/* TEST2: Test md_assemble() */
6708/* Warning, this routine probably doesn't work anymore */
6709
355afbcd 6710main ()
fecd2382 6711{
355afbcd
KR		 6712 struct m68k_it the_ins;
6713 char buf[120];
6714 char *cp;
6715 int n;
6716
6717 m68k_ip_begin ();
6718 for (;;)
6719 {
6720 if (!gets (buf) || !*buf)
6721 break;
6722 if (buf[0] == '|' || buf[1] == '.')
6723 continue;
6724 for (cp = buf; *cp; cp++)
6725 if (*cp == '\t')
6726 *cp = ' ';
6727 if (is_label (buf))
6728 continue;
6729 memset (&the_ins, '\0', sizeof (the_ins));
6730 m68k_ip (&the_ins, buf);
6731 if (the_ins.error)
6732 {
6733 printf ("Error %s in %s\n", the_ins.error, buf);
6734 }
6735 else
6736 {
6737 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6738 for (n = 0; n < the_ins.numo; n++)
6739 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6740 printf (" ");
6741 print_the_insn (&the_ins.opcode[0], stdout);
6742 (void) putchar ('\n');
6743 }
6744 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6745 {
6746 if (the_ins.operands[n].error)
6747 {
6748 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6749 continue;
6750 }
6751 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6752 if (the_ins.operands[n].b_const)
6753 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6754 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6755 if (the_ins.operands[n].b_iadd)
6756 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6757 (void) putchar ('\n');
a39116f1 6758 }
355afbcd
KR		 6759 }
6760 m68k_ip_end ();
6761 return 0;
fecd2382
RP		 6762}
6763
355afbcd
KR		 6764is_label (str)
6765 char *str;
fecd2382 6766{
355afbcd
KR		 6767 while (*str == ' ')
6768 str++;
6769 while (*str && *str != ' ')
6770 str++;
6771 if (str[-1] == ':' || str[1] == '=')
6772 return 1;
6773 return 0;
fecd2382
RP		 6774}
6775
6776#endif
6777
6778/* Possible states for relaxation:
6d27d3a2 6779
a39116f1
RP		 6780 0 0 branch offset byte (bra, etc)
6781 0 1 word
6782 0 2 long
6d27d3a2 6783
a39116f1
RP		 6784 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6785 1 1 word
6786 1 2 long
6d27d3a2 6787
a39116f1
RP		 6788 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6789 2 1 word-long
6790 2 2 long-word
6791 2 3 long-long
6d27d3a2 6792
a39116f1 6793 */
fecd2382 6794
fecd2382
RP		 6795/* We have no need to default values of symbols. */
6796
6797/* ARGSUSED */
6798symbolS *
355afbcd
KR		 6799md_undefined_symbol (name)
6800 char *name;
fecd2382 6801{
355afbcd 6802 return 0;
fecd2382
RP		 6803}
6804
fecd2382 6805/* Round up a section size to the appropriate boundary. */
025b0302 6806valueT
355afbcd
KR		 6807md_section_align (segment, size)
6808 segT segment;
025b0302 6809 valueT size;
fecd2382 6810{
af438bdb
ILT		 6811#ifdef OBJ_AOUT
6812#ifdef BFD_ASSEMBLER
6813 /* For a.out, force the section size to be aligned. If we don't do
6814 this, BFD will align it for us, but it will not write out the
6815 final bytes of the section. This may be a bug in BFD, but it is
6816 easier to fix it here since that is how the other a.out targets
6817 work. */
6818 int align;
6819
6820 align = bfd_get_section_alignment (stdoutput, segment);
6821 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6822#endif
6823#endif
6824
6825 return size;
fecd2382
RP		 6826}
6827
6828/* Exactly what point is a PC-relative offset relative TO?
5f8cb05e
ILT		 6829 On the 68k, it is relative to the address of the first extension
6830 word. The difference between the addresses of the offset and the
6831 first extension word is stored in fx_pcrel_adjust. */
fecd2382 6832long
355afbcd
KR		 6833md_pcrel_from (fixP)
6834 fixS *fixP;
fecd2382 6835{
b4ec75e0
ILT		 6836 int adjust;
6837
6838 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6839 -1 as 64. */
6840 adjust = fixP->fx_pcrel_adjust;
6841 if (adjust == 64)
6842 adjust = -1;
6843 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
fecd2382
RP		 6844}
6845
49864cfa 6846#ifndef BFD_ASSEMBLER
af438bdb
ILT		 6847#ifdef OBJ_COFF
6848
9ad5755f 6849/*ARGSUSED*/
355afbcd 6850void
9ad5755f
KR		 6851tc_coff_symbol_emit_hook (ignore)
6852 symbolS *ignore;
3ad9ec6a
ILT		 6853{
6854}
6855
355afbcd
KR		 6856int
6857tc_coff_sizemachdep (frag)
6858 fragS *frag;
3ad9ec6a 6859{
355afbcd
KR		 6860 switch (frag->fr_subtype & 0x3)
6861 {
6862 case BYTE:
6863 return 1;
6864 case SHORT:
6865 return 2;
6866 case LONG:
6867 return 4;
6868 default:
6869 abort ();
064ba683 6870 return 0;
355afbcd 6871 }
3ad9ec6a 6872}
af438bdb
ILT		 6873
6874#endif
49864cfa 6875#endif
355afbcd 6876
fecd2382 6877/* end of tc-m68k.c */
GDB Binutils - Deliverables
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