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* elf32-arm.c (elf32_arm_modify_segment_map): New function.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
f17c130b 3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
36759679 73const int md_reloc_size = 8; /* Size of relocation record. */
252b5132
RH		 74
75/* Are we trying to generate PIC code? If so, absolute references
76 ought to be made into linkage table references or pc-relative
92774660 77 references. Not implemented. For ELF there are other means
252b5132
RH		 78 to denote pic relocations. */
79int flag_want_pic;
80
36759679
NC		 81static int flag_short_refs; /* -l option. */
82static int flag_long_jumps; /* -S option. */
28e7409f 83static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 84
85#ifdef REGISTER_PREFIX_OPTIONAL
86int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
87#else
88int flag_reg_prefix_optional;
89#endif
90
91/* Whether --register-prefix-optional was used on the command line. */
92static int reg_prefix_optional_seen;
93
94/* The floating point coprocessor to use by default. */
95static enum m68k_register m68k_float_copnum = COP1;
96
97/* If this is non-zero, then references to number(%pc) will be taken
98 to refer to number, rather than to %pc + number. */
99static int m68k_abspcadd;
100
101/* If this is non-zero, then the quick forms of the move, add, and sub
102 instructions are used when possible. */
103static int m68k_quick = 1;
104
105/* If this is non-zero, then if the size is not specified for a base
106 or outer displacement, the assembler assumes that the size should
107 be 32 bits. */
108static int m68k_rel32 = 1;
109
110/* This is non-zero if m68k_rel32 was set from the command line. */
111static int m68k_rel32_from_cmdline;
112
113/* The default width to use for an index register when using a base
114 displacement. */
115static enum m68k_size m68k_index_width_default = SIZE_LONG;
116
117/* We want to warn if any text labels are misaligned. In order to get
118 the right line number, we need to record the line number for each
119 label. */
252b5132
RH		 120struct label_line
121{
122 struct label_line *next;
123 symbolS *label;
124 char *file;
125 unsigned int line;
126 int text;
127};
128
129/* The list of labels. */
130
131static struct label_line *labels;
132
133/* The current label. */
134
135static struct label_line *current_label;
136
60fed2d3
NC		 137/* Pointer to list holding the opcodes sorted by name. */
138static struct m68k_opcode const ** m68k_sorted_opcodes;
139
36759679
NC		 140/* Its an arbitrary name: This means I don't approve of it.
141 See flames below. */
252b5132
RH		 142static struct obstack robyn;
143
252b5132
RH		 144struct m68k_incant
145 {
146 const char *m_operands;
147 unsigned long m_opcode;
148 short m_opnum;
149 short m_codenum;
150 int m_arch;
151 struct m68k_incant *m_next;
152 };
153
154#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
155#define gettwo(x) (((x)->m_opcode)&0xffff)
156
157static const enum m68k_register m68000_control_regs[] = { 0 };
158static const enum m68k_register m68010_control_regs[] = {
159 SFC, DFC, USP, VBR,
160 0
161};
162static const enum m68k_register m68020_control_regs[] = {
163 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
164 0
165};
166static const enum m68k_register m68040_control_regs[] = {
167 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
168 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
169 0
170};
171static const enum m68k_register m68060_control_regs[] = {
172 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
173 USP, VBR, URP, SRP, PCR,
174 0
175};
6da466c7 176static const enum m68k_register mcf_control_regs[] = {
3e602632 177 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 178 RAMBAR0, RAMBAR1, MBAR,
179 0
180};
e80e0390
NC		 181static const enum m68k_register mcf5249_control_regs[] = {
182 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR1, MBAR, MBAR2,
183 0
184};
3e602632
NC		 185static const enum m68k_register mcf528x_control_regs[] = {
186 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
187 0
188};
189static const enum m68k_register mcfv4e_control_regs[] = {
190 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
191 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
192 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
193 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
194 0
195};
252b5132
RH		 196#define cpu32_control_regs m68010_control_regs
197
198static const enum m68k_register *control_regs;
199
36759679 200/* Internal form of a 68020 instruction. */
252b5132
RH		 201struct m68k_it
202{
203 const char *error;
36759679 204 const char *args; /* List of opcode info. */
252b5132
RH		 205 int numargs;
206
36759679 207 int numo; /* Number of shorts in opcode. */
252b5132
RH		 208 short opcode[11];
209
210 struct m68k_op operands[6];
211
36759679 212 int nexp; /* Number of exprs in use. */
252b5132
RH		 213 struct m68k_exp exprs[4];
214
36759679 215 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 216 struct
217 {
36759679 218 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 219 symbolS *fadd;
220 offsetT foff;
221 int fragty;
222 }
223 fragb[4];
224
36759679 225 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 226 struct
227 {
228 int n;
229 expressionS exp;
230 char wid;
231 char pcrel;
232 /* In a pc relative address the difference between the address
233 of the offset and the address that the offset is relative
234 to. This depends on the addressing mode. Basically this
235 is the value to put in the offset field to address the
236 first byte of the offset, without regarding the special
237 significance of some values (in the branch instruction, for
238 example). */
239 int pcrel_fix;
240#ifdef OBJ_ELF
241 /* Whether this expression needs special pic relocation, and if
242 so, which. */
243 enum pic_relocation pic_reloc;
244#endif
245 }
36759679 246 reloc[5]; /* Five is enough??? */
252b5132
RH		 247};
248
6b6e92f4 249#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
252b5132
RH		 250#define float_of_arch(x) ((x) & mfloat)
251#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 252#define arch_coldfire_p(x) ((x) & mcfisa_a)
253#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 254
36759679 255/* Macros for determining if cpu supports a specific addressing mode. */
6b6e92f4 256#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
252b5132 257
36759679 258static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 259
260#define op(ex) ((ex)->exp.X_op)
261#define adds(ex) ((ex)->exp.X_add_symbol)
262#define subs(ex) ((ex)->exp.X_op_symbol)
263#define offs(ex) ((ex)->exp.X_add_number)
264
36759679 265/* Macros for adding things to the m68k_it struct. */
31302357 266#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 267
36759679
NC		 268/* Like addword, but goes BEFORE general operands. */
269
252b5132 270static void
31302357 271insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 272{
273 int z;
07726851 274 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 275 the_ins.opcode[z] = the_ins.opcode[z - 1];
276 for (z = 0; z < the_ins.nrel; z++)
277 the_ins.reloc[z].n += 2;
252b5132
RH		 278 for (z = 0; z < the_ins.nfrag; z++)
279 the_ins.fragb[z].fragoff++;
8a104df9 280 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 281 the_ins.numo++;
282}
283
284/* The numo+1 kludge is so we can hit the low order byte of the prev word.
285 Blecch. */
286static void
31302357 287add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 288{
31302357
AS		 289 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
290 ? the_ins.numo * 2 - 1
291 : (width == 'b'
292 ? the_ins.numo * 2 + 1
293 : the_ins.numo * 2));
252b5132
RH		 294 the_ins.reloc[the_ins.nrel].exp = exp->exp;
295 the_ins.reloc[the_ins.nrel].wid = width;
296 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
297#ifdef OBJ_ELF
298 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
299#endif
300 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
301}
302
303/* Cause an extra frag to be generated here, inserting up to 10 bytes
304 (that value is chosen in the frag_var call in md_assemble). TYPE
305 is the subtype of the frag to be generated; its primary type is
306 rs_machine_dependent.
307
308 The TYPE parameter is also used by md_convert_frag_1 and
309 md_estimate_size_before_relax. The appropriate type of fixup will
310 be emitted by md_convert_frag_1.
311
312 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
313static void
31302357 314add_frag (symbolS *add, offsetT off, int type)
252b5132 315{
8a104df9
KH		 316 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
317 the_ins.fragb[the_ins.nfrag].fadd = add;
318 the_ins.fragb[the_ins.nfrag].foff = off;
319 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 320}
321
322#define isvar(ex) \
323 (op (ex) != O_constant && op (ex) != O_big)
324
31302357
AS		 325static char *crack_operand (char *str, struct m68k_op *opP);
326static int get_num (struct m68k_exp *exp, int ok);
327static int reverse_16_bits (int in);
328static int reverse_8_bits (int in);
329static void install_gen_operand (int mode, int val);
330static void install_operand (int mode, int val);
331static void s_bss (int);
332static void s_data1 (int);
333static void s_data2 (int);
334static void s_even (int);
335static void s_proc (int);
336static void s_chip (int);
337static void s_fopt (int);
338static void s_opt (int);
339static void s_reg (int);
340static void s_restore (int);
341static void s_save (int);
342static void s_mri_if (int);
343static void s_mri_else (int);
344static void s_mri_endi (int);
345static void s_mri_break (int);
346static void s_mri_next (int);
347static void s_mri_for (int);
348static void s_mri_endf (int);
349static void s_mri_repeat (int);
350static void s_mri_until (int);
351static void s_mri_while (int);
352static void s_mri_endw (int);
252b5132
RH		 353
354static int current_architecture;
6b6e92f4 355static int current_chip;
252b5132 356
dc84e067
NC		 357struct m68k_cpu
358 {
359 unsigned long arch;
6b6e92f4 360 unsigned long chip;
dc84e067
NC		 361 const char *name;
362 int alias;
363 };
252b5132 364
dc84e067
NC		 365static const struct m68k_cpu archs[] =
366 {
6b6e92f4
NC		 367 { m68000, m68000, "68000", 0 },
368 { m68010, m68010, "68010", 0 },
369 { m68020, m68020, "68020", 0 },
370 { m68030, m68030, "68030", 0 },
371 { m68040, m68040, "68040", 0 },
372 { m68060, m68060, "68060", 0 },
373 { cpu32, cpu32, "cpu32", 0 },
374 { m68881, m68881, "68881", 0 },
375 { m68851, m68851, "68851", 0 },
376 { mcfisa_a, mcf5200, "5200", 0 },
377 { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 },
378 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 },
379 { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 },
380 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 },
381 { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 },
382 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 },
383 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 },
384 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 },
dc84e067
NC		 385 /* Aliases (effectively, so far as gas is concerned) for the above
386 cpus. */
6b6e92f4
NC		 387 { m68020, m68020, "68k", 1 },
388 { m68000, m68000, "68008", 1 },
389 { m68000, m68000, "68302", 1 },
390 { m68000, m68000, "68306", 1 },
391 { m68000, m68000, "68307", 1 },
392 { m68000, m68000, "68322", 1 },
393 { m68000, m68000, "68356", 1 },
394 { m68000, m68000, "68ec000", 1 },
395 { m68000, m68000, "68hc000", 1 },
396 { m68000, m68000, "68hc001", 1 },
397 { m68020, m68020, "68ec020", 1 },
398 { m68030, m68030, "68ec030", 1 },
399 { m68040, m68040, "68ec040", 1 },
400 { m68060, m68060, "68ec060", 1 },
401 { cpu32, cpu32, "68330", 1 },
402 { cpu32, cpu32, "68331", 1 },
403 { cpu32, cpu32, "68332", 1 },
404 { cpu32, cpu32, "68333", 1 },
405 { cpu32, cpu32, "68334", 1 },
406 { cpu32, cpu32, "68336", 1 },
407 { cpu32, cpu32, "68340", 1 },
408 { cpu32, cpu32, "68341", 1 },
409 { cpu32, cpu32, "68349", 1 },
410 { cpu32, cpu32, "68360", 1 },
411 { m68881, m68881, "68882", 1 },
412 { mcfisa_a, mcf5200, "5202", 1 },
413 { mcfisa_a, mcf5200, "5204", 1 },
414 { mcfisa_a, mcf5200, "5206", 1 },
415 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 },
416 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 },
417 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 },
418 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 },
419 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 },
420 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 },
421 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 },
422 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 },
423 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 },
424 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 },
425 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 },
426 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 },
427 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 },
428 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 },
429 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 },
430 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 },
431 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 },
432 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 },
433 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 },
dc84e067 434 };
252b5132
RH		 435
436static const int n_archs = sizeof (archs) / sizeof (archs[0]);
437
151337e8
NC		 438/* This is the assembler relaxation table for m68k. m68k is a rich CISC
439 architecture and we have a lot of relaxation modes. */
252b5132 440
151337e8
NC		 441/* Macros used in the relaxation code. */
442#define TAB(x,y) (((x) << 2) + (y))
443#define TABTYPE(x) ((x) >> 2)
444
445/* Relaxation states. */
446#define BYTE 0
447#define SHORT 1
448#define LONG 2
449#define SZ_UNDEF 3
450
451/* Here are all the relaxation modes we support. First we can relax ordinary
452 branches. On 68020 and higher and on CPU32 all branch instructions take
453 three forms, so on these CPUs all branches always remain as such. When we
454 have to expand to the LONG form on a 68000, though, we substitute an
455 absolute jump instead. This is a direct replacement for unconditional
456 branches and a branch over a jump for conditional branches. However, if the
457 user requires PIC and disables this with --pcrel, we can only relax between
458 BYTE and SHORT forms, punting if that isn't enough. This gives us four
459 different relaxation modes for branches: */
460
36759679
NC		 461#define BRANCHBWL 0 /* Branch byte, word, or long. */
462#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
463#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
464#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 465
466/* We also relax coprocessor branches and DBcc's. All CPUs that support
467 coprocessor branches support them in word and long forms, so we have only
468 one relaxation mode for them. DBcc's are word only on all CPUs. We can
469 relax them to the LONG form with a branch-around sequence. This sequence
470 can use a long branch (if available) or an absolute jump (if acceptable).
471 This gives us two relaxation modes. If long branches are not available and
472 absolute jumps are not acceptable, we don't relax DBcc's. */
473
36759679
NC		 474#define FBRANCH 4 /* Coprocessor branch. */
475#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
476#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 477
478/* That's all for instruction relaxation. However, we also relax PC-relative
479 operands. Specifically, we have three operand relaxation modes. On the
480 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
481 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
482 two. Also PC+displacement+index operands in their simple form (with a non-
483 suppressed index without memory indirection) are supported on all CPUs, but
484 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
485 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
486 form of the PC+displacement+index operand. Finally, some absolute operands
487 can be relaxed down to 16-bit PC-relative. */
488
36759679
NC		 489#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
490#define PCINDEX 8 /* PC + displacement + index. */
491#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 492
493/* Note that calls to frag_var need to specify the maximum expansion
494 needed; this is currently 10 bytes for DBCC. */
495
496/* The fields are:
497 How far Forward this mode will reach:
498 How far Backward this mode will reach:
499 How many bytes this mode will add to the size of the frag
500 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 501
502 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 503relax_typeS md_relax_table[] =
504{
ac62c346
AM		 505 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
506 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
507 { 0, 0, 4, 0 },
508 { 1, 1, 0, 0 },
509
510 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
511 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
512 { 0, 0, 4, 0 },
513 { 1, 1, 0, 0 },
514
515 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
516 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
517 { 0, 0, 6, 0 },
518 { 1, 1, 0, 0 },
519
520 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
521 { 0, 0, 2, 0 },
522 { 1, 1, 0, 0 },
523 { 1, 1, 0, 0 },
524
36759679 525 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 526 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
527 { 0, 0, 4, 0 },
528 { 1, 1, 0, 0 },
529
36759679 530 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 531 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
532 { 0, 0, 10, 0 },
533 { 1, 1, 0, 0 },
534
36759679 535 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 536 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
537 { 0, 0, 10, 0 },
538 { 1, 1, 0, 0 },
539
36759679 540 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 541 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
542 { 0, 0, 6, 0 },
543 { 1, 1, 0, 0 },
544
545 { 125, -130, 0, TAB (PCINDEX, SHORT) },
546 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
547 { 0, 0, 4, 0 },
548 { 1, 1, 0, 0 },
549
36759679 550 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 551 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
552 { 0, 0, 4, 0 },
553 { 1, 1, 0, 0 },
252b5132
RH		 554};
555
556/* These are the machine dependent pseudo-ops. These are included so
557 the assembler can work on the output from the SUN C compiler, which
36759679 558 generates these. */
252b5132
RH		 559
560/* This table describes all the machine specific pseudo-ops the assembler
561 has to support. The fields are:
562 pseudo-op name without dot
563 function to call to execute this pseudo-op
36759679 564 Integer arg to pass to the function. */
252b5132
RH		 565const pseudo_typeS md_pseudo_table[] =
566{
567 {"data1", s_data1, 0},
568 {"data2", s_data2, 0},
569 {"bss", s_bss, 0},
570 {"even", s_even, 0},
571 {"skip", s_space, 0},
572 {"proc", s_proc, 0},
573#if defined (TE_SUN3) || defined (OBJ_ELF)
574 {"align", s_align_bytes, 0},
575#endif
576#ifdef OBJ_ELF
577 {"swbeg", s_ignore, 0},
578#endif
579 {"extend", float_cons, 'x'},
580 {"ldouble", float_cons, 'x'},
581
582 /* The following pseudo-ops are supported for MRI compatibility. */
583 {"chip", s_chip, 0},
584 {"comline", s_space, 1},
585 {"fopt", s_fopt, 0},
586 {"mask2", s_ignore, 0},
587 {"opt", s_opt, 0},
588 {"reg", s_reg, 0},
589 {"restore", s_restore, 0},
590 {"save", s_save, 0},
591
592 {"if", s_mri_if, 0},
593 {"if.b", s_mri_if, 'b'},
594 {"if.w", s_mri_if, 'w'},
595 {"if.l", s_mri_if, 'l'},
596 {"else", s_mri_else, 0},
597 {"else.s", s_mri_else, 's'},
598 {"else.l", s_mri_else, 'l'},
599 {"endi", s_mri_endi, 0},
600 {"break", s_mri_break, 0},
601 {"break.s", s_mri_break, 's'},
602 {"break.l", s_mri_break, 'l'},
603 {"next", s_mri_next, 0},
604 {"next.s", s_mri_next, 's'},
605 {"next.l", s_mri_next, 'l'},
606 {"for", s_mri_for, 0},
607 {"for.b", s_mri_for, 'b'},
608 {"for.w", s_mri_for, 'w'},
609 {"for.l", s_mri_for, 'l'},
610 {"endf", s_mri_endf, 0},
611 {"repeat", s_mri_repeat, 0},
612 {"until", s_mri_until, 0},
613 {"until.b", s_mri_until, 'b'},
614 {"until.w", s_mri_until, 'w'},
615 {"until.l", s_mri_until, 'l'},
616 {"while", s_mri_while, 0},
617 {"while.b", s_mri_while, 'b'},
618 {"while.w", s_mri_while, 'w'},
619 {"while.l", s_mri_while, 'l'},
620 {"endw", s_mri_endw, 0},
621
622 {0, 0, 0}
623};
624
252b5132 625/* The mote pseudo ops are put into the opcode table, since they
31302357 626 don't start with a . they look like opcodes to gas. */
252b5132 627
5a38dc70 628const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 629{
630
631 {"dcl", cons, 4},
632 {"dc", cons, 2},
633 {"dcw", cons, 2},
634 {"dcb", cons, 1},
635
636 {"dsl", s_space, 4},
637 {"ds", s_space, 2},
638 {"dsw", s_space, 2},
639 {"dsb", s_space, 1},
640
641 {"xdef", s_globl, 0},
642#ifdef OBJ_ELF
643 {"align", s_align_bytes, 0},
644#else
645 {"align", s_align_ptwo, 0},
646#endif
647#ifdef M68KCOFF
648 {"sect", obj_coff_section, 0},
649 {"section", obj_coff_section, 0},
650#endif
651 {0, 0, 0}
652};
653
31302357
AS		 654#define issbyte(x) ((x) >= -128 && (x) <= 127)
655#define isubyte(x) ((x) >= 0 && (x) <= 255)
656#define issword(x) ((x) >= -32768 && (x) <= 32767)
657#define isuword(x) ((x) >= 0 && (x) <= 65535)
252b5132 658
31302357
AS		 659#define isbyte(x) ((x) >= -255 && (x) <= 255)
660#define isword(x) ((x) >= -65536 && (x) <= 65535)
252b5132
RH		 661#define islong(x) (1)
662
252b5132
RH		 663static char notend_table[256];
664static char alt_notend_table[256];
665#define notend(s) \
666 (! (notend_table[(unsigned char) *s] \
667 || (*s == ':' \
668 && alt_notend_table[(unsigned char) s[1]])))
669
6b6e92f4
NC		 670/* Return a human readable string holding the list of chips that are
671 valid for a particular architecture, suppressing aliases (unless
672 there is only one of them). */
673
674static char *
675find_cf_chip (int architecture)
676{
677 static char buf[1024];
678 int i, j, n_chips, n_alias;
679 char *cp;
680
681 strcpy (buf, " (");
682 cp = buf + strlen (buf);
683
684 for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i)
685 if (archs[i].arch & architecture)
686 {
687 n_chips++;
688 if (archs[i].alias)
689 n_alias++;
690 }
691
692 if (n_chips == 0)
693 as_fatal (_("no matching ColdFire architectures found"));
694
695 if (n_alias > 1)
696 n_chips -= n_alias;
697
698 for (i = 0, j = 0; i < n_archs && j < n_chips; ++i)
699 if (archs[i].arch & architecture)
700 {
701 if (j)
702 {
31302357 703 if ((j == n_chips - 1 && !(n_alias > 1)) || ! n_alias)
6b6e92f4
NC		 704 {
705 if (n_chips == 2)
706 {
707 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
708 cp += strlen (cp);
709 }
710 else
711 {
712 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
713 cp += strlen (cp);
714 }
715 }
716 else
717 {
718 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
719 cp += strlen (cp);
720 }
721 }
722 strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf)));
723 cp += strlen (cp);
724 j++;
725 }
726
727 if (n_alias > 1)
728 {
729 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
730 cp += strlen (cp);
731 }
732
733 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
734
735 return buf;
736}
737
252b5132
RH		 738#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
739
740#ifdef NO_PCREL_RELOCS
741
742int
31302357 743make_pcrel_absolute (fixS *fixP, long *add_number)
252b5132
RH		 744{
745 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
746
36759679 747 /* Rewrite the PC relative instructions to absolute address ones.
67c1ffbe 748 these are rumored to be faster, and the apollo linker refuses
36759679
NC		 749 to deal with the PC relative relocations. */
750 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
252b5132 751 {
36759679 752 if (flag_keep_pcrel)
6b6e92f4 753 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 754 opcode[0] = 0x4e;
755 opcode[1] = 0xf9;
756 }
36759679 757 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
252b5132 758 {
36759679 759 if (flag_keep_pcrel)
6b6e92f4 760 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
252b5132
RH		 761 opcode[0] = 0x4e;
762 opcode[1] = 0xb9;
763 }
764 else
765 as_fatal (_("Unknown PC relative instruction"));
766 *add_number -= 4;
767 return 0;
768}
769
770#endif /* NO_PCREL_RELOCS */
771
772short
31302357 773tc_coff_fix2rtype (fixS *fixP)
252b5132
RH		 774{
775 if (fixP->fx_tcbit && fixP->fx_size == 4)
776 return R_RELLONG_NEG;
777#ifdef NO_PCREL_RELOCS
778 know (fixP->fx_pcrel == 0);
779 return (fixP->fx_size == 1 ? R_RELBYTE
780 : fixP->fx_size == 2 ? R_DIR16
781 : R_DIR32);
782#else
31302357
AS		 783 return (fixP->fx_pcrel
784 ? (fixP->fx_size == 1 ? R_PCRBYTE
785 : fixP->fx_size == 2 ? R_PCRWORD
786 : R_PCRLONG)
787 : (fixP->fx_size == 1 ? R_RELBYTE
788 : fixP->fx_size == 2 ? R_RELWORD
789 : R_RELLONG));
252b5132
RH		 790#endif
791}
792
793#endif
794
795#ifdef OBJ_ELF
796
c801568a
AM		 797/* Return zero if the reference to SYMBOL from within the same segment may
798 be relaxed. */
799
800/* On an ELF system, we can't relax an externally visible symbol,
801 because it may be overridden by a shared library. However, if
802 TARGET_OS is "elf", then we presume that we are assembling for an
803 embedded system, in which case we don't have to worry about shared
804 libraries, and we can relax any external sym. */
805
806#define relaxable_symbol(symbol) \
6358301e 807 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 808 || S_IS_WEAK (symbol)))
809
252b5132
RH		 810/* Compute the relocation code for a fixup of SIZE bytes, using pc
811 relative relocation if PCREL is non-zero. PIC says whether a special
812 pic relocation was requested. */
813
252b5132 814static bfd_reloc_code_real_type
31302357 815get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 816{
817 switch (pic)
818 {
819 case pic_got_pcrel:
820 switch (size)
821 {
822 case 1:
823 return BFD_RELOC_8_GOT_PCREL;
824 case 2:
825 return BFD_RELOC_16_GOT_PCREL;
826 case 4:
827 return BFD_RELOC_32_GOT_PCREL;
828 }
829 break;
830
831 case pic_got_off:
832 switch (size)
833 {
834 case 1:
835 return BFD_RELOC_8_GOTOFF;
836 case 2:
837 return BFD_RELOC_16_GOTOFF;
838 case 4:
839 return BFD_RELOC_32_GOTOFF;
840 }
841 break;
842
843 case pic_plt_pcrel:
844 switch (size)
845 {
846 case 1:
847 return BFD_RELOC_8_PLT_PCREL;
848 case 2:
849 return BFD_RELOC_16_PLT_PCREL;
850 case 4:
851 return BFD_RELOC_32_PLT_PCREL;
852 }
853 break;
854
855 case pic_plt_off:
856 switch (size)
857 {
858 case 1:
859 return BFD_RELOC_8_PLTOFF;
860 case 2:
861 return BFD_RELOC_16_PLTOFF;
862 case 4:
863 return BFD_RELOC_32_PLTOFF;
864 }
865 break;
866
867 case pic_none:
868 if (pcrel)
869 {
870 switch (size)
871 {
872 case 1:
873 return BFD_RELOC_8_PCREL;
874 case 2:
875 return BFD_RELOC_16_PCREL;
876 case 4:
877 return BFD_RELOC_32_PCREL;
878 }
879 }
880 else
881 {
882 switch (size)
883 {
884 case 1:
885 return BFD_RELOC_8;
886 case 2:
887 return BFD_RELOC_16;
888 case 4:
889 return BFD_RELOC_32;
890 }
891 }
892 }
893
894 if (pcrel)
895 {
896 if (pic == pic_none)
897 as_bad (_("Can not do %d byte pc-relative relocation"), size);
898 else
899 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
900 }
901 else
902 {
903 if (pic == pic_none)
904 as_bad (_("Can not do %d byte relocation"), size);
905 else
906 as_bad (_("Can not do %d byte pic relocation"), size);
907 }
908
909 return BFD_RELOC_NONE;
910}
911
912/* Here we decide which fixups can be adjusted to make them relative
913 to the beginning of the section instead of the symbol. Basically
914 we need to make sure that the dynamic relocations are done
915 correctly, so in some cases we force the original symbol to be
916 used. */
917int
31302357 918tc_m68k_fix_adjustable (fixS *fixP)
252b5132 919{
36759679 920 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 921 switch (fixP->fx_r_type)
922 {
923 case BFD_RELOC_8_GOT_PCREL:
924 case BFD_RELOC_16_GOT_PCREL:
925 case BFD_RELOC_32_GOT_PCREL:
926 case BFD_RELOC_8_GOTOFF:
927 case BFD_RELOC_16_GOTOFF:
928 case BFD_RELOC_32_GOTOFF:
929 case BFD_RELOC_8_PLT_PCREL:
930 case BFD_RELOC_16_PLT_PCREL:
931 case BFD_RELOC_32_PLT_PCREL:
932 case BFD_RELOC_8_PLTOFF:
933 case BFD_RELOC_16_PLTOFF:
934 case BFD_RELOC_32_PLTOFF:
935 return 0;
936
937 case BFD_RELOC_VTABLE_INHERIT:
938 case BFD_RELOC_VTABLE_ENTRY:
939 return 0;
940
941 default:
942 return 1;
943 }
944}
945
946#else /* !OBJ_ELF */
947
948#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
949
c801568a
AM		 950#define relaxable_symbol(symbol) 1
951
252b5132
RH		 952#endif /* OBJ_ELF */
953
954#ifdef BFD_ASSEMBLER
955
956arelent *
31302357 957tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 958{
959 arelent *reloc;
960 bfd_reloc_code_real_type code;
961
8ec6253e
NC		 962 /* If the tcbit is set, then this was a fixup of a negative value
963 that was never resolved. We do not have a reloc to handle this,
964 so just return. We assume that other code will have detected this
965 situation and produced a helpful error message, so we just tell the
966 user that the reloc cannot be produced. */
252b5132 967 if (fixp->fx_tcbit)
8ec6253e
NC		 968 {
969 if (fixp->fx_addsy)
b091f402
AM		 970 as_bad_where (fixp->fx_file, fixp->fx_line,
971 _("Unable to produce reloc against symbol '%s'"),
972 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 973 return NULL;
974 }
252b5132
RH		 975
976 if (fixp->fx_r_type != BFD_RELOC_NONE)
977 {
978 code = fixp->fx_r_type;
979
980 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
981 that fixup_segment converted a non-PC relative reloc into a
982 PC relative reloc. In such a case, we need to convert the
983 reloc code. */
984 if (fixp->fx_pcrel)
985 {
986 switch (code)
987 {
988 case BFD_RELOC_8:
989 code = BFD_RELOC_8_PCREL;
990 break;
991 case BFD_RELOC_16:
992 code = BFD_RELOC_16_PCREL;
993 break;
994 case BFD_RELOC_32:
995 code = BFD_RELOC_32_PCREL;
996 break;
997 case BFD_RELOC_8_PCREL:
998 case BFD_RELOC_16_PCREL:
999 case BFD_RELOC_32_PCREL:
1000 case BFD_RELOC_8_GOT_PCREL:
1001 case BFD_RELOC_16_GOT_PCREL:
1002 case BFD_RELOC_32_GOT_PCREL:
1003 case BFD_RELOC_8_GOTOFF:
1004 case BFD_RELOC_16_GOTOFF:
1005 case BFD_RELOC_32_GOTOFF:
1006 case BFD_RELOC_8_PLT_PCREL:
1007 case BFD_RELOC_16_PLT_PCREL:
1008 case BFD_RELOC_32_PLT_PCREL:
1009 case BFD_RELOC_8_PLTOFF:
1010 case BFD_RELOC_16_PLTOFF:
1011 case BFD_RELOC_32_PLTOFF:
1012 break;
1013 default:
1014 as_bad_where (fixp->fx_file, fixp->fx_line,
1015 _("Cannot make %s relocation PC relative"),
1016 bfd_get_reloc_code_name (code));
1017 }
1018 }
1019 }
1020 else
1021 {
1022#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1023 switch (F (fixp->fx_size, fixp->fx_pcrel))
1024 {
1025#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1026 MAP (1, 0, BFD_RELOC_8);
1027 MAP (2, 0, BFD_RELOC_16);
1028 MAP (4, 0, BFD_RELOC_32);
1029 MAP (1, 1, BFD_RELOC_8_PCREL);
1030 MAP (2, 1, BFD_RELOC_16_PCREL);
1031 MAP (4, 1, BFD_RELOC_32_PCREL);
1032 default:
1033 abort ();
1034 }
1035 }
1036#undef F
1037#undef MAP
1038
1039 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1040 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1041 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1042 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1043#ifndef OBJ_ELF
1044 if (fixp->fx_pcrel)
1045 reloc->addend = fixp->fx_addnumber;
1046 else
1047 reloc->addend = 0;
1048#else
1049 if (!fixp->fx_pcrel)
1050 reloc->addend = fixp->fx_addnumber;
1051 else
1052 reloc->addend = (section->vma
8390138c
AS		 1053 /* Explicit sign extension in case char is
1054 unsigned. */
1055 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1056 + fixp->fx_addnumber
1057 + md_pcrel_from (fixp));
1058#endif
1059
1060 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1061 assert (reloc->howto != 0);
1062
1063 return reloc;
1064}
1065
1066#endif /* BFD_ASSEMBLER */
1067
252b5132
RH		 1068/* Handle of the OPCODE hash table. NULL means any use before
1069 m68k_ip_begin() will crash. */
1070static struct hash_control *op_hash;
1071\f
1072/* Assemble an m68k instruction. */
1073
1074static void
31302357 1075m68k_ip (char *instring)
252b5132
RH		 1076{
1077 register char *p;
1078 register struct m68k_op *opP;
1079 register const struct m68k_incant *opcode;
1080 register const char *s;
1081 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1082 char *pdot, *pdotmove;
1083 enum m68k_size siz1, siz2;
1084 char c;
1085 int losing;
1086 int opsfound;
1087 LITTLENUM_TYPE words[6];
1088 LITTLENUM_TYPE *wordp;
1089 unsigned long ok_arch = 0;
1090
1091 if (*instring == ' ')
36759679 1092 instring++; /* Skip leading whitespace. */
252b5132
RH		 1093
1094 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1095 or exactly 1 space. */
252b5132
RH		 1096 pdot = 0;
1097 for (p = instring; *p != '\0'; p++)
1098 {
1099 if (*p == ' ')
1100 break;
1101 if (*p == '.')
1102 pdot = p;
1103 }
1104
1105 if (p == instring)
1106 {
1107 the_ins.error = _("No operator");
1108 return;
1109 }
1110
1111 /* p now points to the end of the opcode name, probably whitespace.
1112 Make sure the name is null terminated by clobbering the
1113 whitespace, look it up in the hash table, then fix it back.
1114 Remove a dot, first, since the opcode tables have none. */
1115 if (pdot != NULL)
1116 {
1117 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1118 *pdotmove = pdotmove[1];
1119 p--;
1120 }
1121
1122 c = *p;
1123 *p = '\0';
1124 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1125 *p = c;
1126
1127 if (pdot != NULL)
1128 {
1129 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1130 *pdotmove = pdotmove[-1];
1131 *pdot = '.';
1132 ++p;
1133 }
1134
1135 if (opcode == NULL)
1136 {
1137 the_ins.error = _("Unknown operator");
1138 return;
1139 }
1140
36759679 1141 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1142 while (*p == ' ')
1143 ++p;
1144
1145 if (opcode->m_operands == 0)
1146 {
1147 char *old = input_line_pointer;
1148 *old = '\n';
1149 input_line_pointer = p;
36759679 1150 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1151 mote_pseudo_table[opcode->m_opnum].poc_handler
1152 (mote_pseudo_table[opcode->m_opnum].poc_val);
1153 input_line_pointer = old;
1154 *old = 0;
1155
1156 return;
1157 }
1158
1159 if (flag_mri && opcode->m_opnum == 0)
1160 {
1161 /* In MRI mode, random garbage is allowed after an instruction
1162 which accepts no operands. */
1163 the_ins.args = opcode->m_operands;
1164 the_ins.numargs = opcode->m_opnum;
1165 the_ins.numo = opcode->m_codenum;
1166 the_ins.opcode[0] = getone (opcode);
1167 the_ins.opcode[1] = gettwo (opcode);
1168 return;
1169 }
1170
1171 for (opP = &the_ins.operands[0]; *p; opP++)
1172 {
1173 p = crack_operand (p, opP);
1174
1175 if (opP->error)
1176 {
1177 the_ins.error = opP->error;
1178 return;
1179 }
1180 }
1181
1182 opsfound = opP - &the_ins.operands[0];
1183
1184 /* This ugly hack is to support the floating pt opcodes in their
1185 standard form. Essentially, we fake a first enty of type COP#1 */
1186 if (opcode->m_operands[0] == 'I')
1187 {
1188 int n;
1189
1190 for (n = opsfound; n > 0; --n)
1191 the_ins.operands[n] = the_ins.operands[n - 1];
1192
31302357 1193 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1194 the_ins.operands[0].mode = CONTROL;
1195 the_ins.operands[0].reg = m68k_float_copnum;
1196 opsfound++;
1197 }
1198
36759679 1199 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1200 for (losing = 0;;)
1201 {
1202 /* If we didn't get the right number of ops, or we have no
92774660 1203 common model with this pattern then reject this pattern. */
252b5132
RH		 1204
1205 ok_arch |= opcode->m_arch;
1206 if (opsfound != opcode->m_opnum
1207 || ((opcode->m_arch & current_architecture) == 0))
1208 ++losing;
1209 else
1210 {
1211 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1212 *s && !losing;
1213 s += 2, opP++)
1214 {
1215 /* Warning: this switch is huge! */
1216 /* I've tried to organize the cases into this order:
1217 non-alpha first, then alpha by letter. Lower-case
1218 goes directly before uppercase counterpart. */
1219 /* Code with multiple case ...: gets sorted by the lowest
1220 case ... it belongs to. I hope this makes sense. */
1221 switch (*s)
1222 {
1223 case '!':
1224 switch (opP->mode)
1225 {
1226 case IMMED:
1227 case DREG:
1228 case AREG:
1229 case FPREG:
1230 case CONTROL:
1231 case AINC:
1232 case ADEC:
1233 case REGLST:
1234 losing++;
1235 break;
1236 default:
1237 break;
1238 }
1239 break;
1240
1241 case '<':
1242 switch (opP->mode)
1243 {
1244 case DREG:
1245 case AREG:
1246 case FPREG:
1247 case CONTROL:
1248 case IMMED:
1249 case ADEC:
1250 case REGLST:
1251 losing++;
1252 break;
1253 default:
1254 break;
1255 }
1256 break;
1257
1258 case '>':
1259 switch (opP->mode)
1260 {
1261 case DREG:
1262 case AREG:
1263 case FPREG:
1264 case CONTROL:
1265 case IMMED:
1266 case AINC:
1267 case REGLST:
1268 losing++;
1269 break;
1270 case ABSL:
1271 break;
1272 default:
1273 if (opP->reg == PC
1274 || opP->reg == ZPC)
1275 losing++;
1276 break;
1277 }
1278 break;
1279
1280 case 'm':
1281 switch (opP->mode)
1282 {
1283 case DREG:
1284 case AREG:
1285 case AINDR:
1286 case AINC:
1287 case ADEC:
1288 break;
1289 default:
1290 losing++;
1291 }
8a104df9 1292 break;
252b5132
RH		 1293
1294 case 'n':
1295 switch (opP->mode)
1296 {
1297 case DISP:
1298 break;
1299 default:
1300 losing++;
1301 }
8a104df9 1302 break;
252b5132
RH		 1303
1304 case 'o':
1305 switch (opP->mode)
1306 {
1307 case BASE:
1308 case ABSL:
1309 case IMMED:
1310 break;
1311 default:
1312 losing++;
1313 }
8a104df9 1314 break;
252b5132
RH		 1315
1316 case 'p':
1317 switch (opP->mode)
1318 {
1319 case DREG:
1320 case AREG:
1321 case AINDR:
1322 case AINC:
1323 case ADEC:
1324 break;
1325 case DISP:
1326 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1327 losing++;
252b5132
RH		 1328 break;
1329 default:
1330 losing++;
1331 }
8a104df9 1332 break;
252b5132
RH		 1333
1334 case 'q':
1335 switch (opP->mode)
1336 {
1337 case DREG:
1338 case AINDR:
1339 case AINC:
1340 case ADEC:
1341 break;
1342 case DISP:
1343 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1344 losing++;
252b5132
RH		 1345 break;
1346 default:
1347 losing++;
1348 break;
1349 }
8a104df9 1350 break;
252b5132
RH		 1351
1352 case 'v':
1353 switch (opP->mode)
1354 {
1355 case DREG:
1356 case AINDR:
1357 case AINC:
1358 case ADEC:
1359 case ABSL:
1360 break;
1361 case DISP:
1362 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1363 losing++;
252b5132
RH		 1364 break;
1365 default:
1366 losing++;
1367 break;
1368 }
1369 break;
1370
1371 case '#':
1372 if (opP->mode != IMMED)
1373 losing++;
1374 else if (s[1] == 'b'
1375 && ! isvar (&opP->disp)
1376 && (opP->disp.exp.X_op != O_constant
1377 || ! isbyte (opP->disp.exp.X_add_number)))
1378 losing++;
1379 else if (s[1] == 'B'
1380 && ! isvar (&opP->disp)
1381 && (opP->disp.exp.X_op != O_constant
1382 || ! issbyte (opP->disp.exp.X_add_number)))
1383 losing++;
1384 else if (s[1] == 'w'
1385 && ! isvar (&opP->disp)
1386 && (opP->disp.exp.X_op != O_constant
1387 || ! isword (opP->disp.exp.X_add_number)))
1388 losing++;
1389 else if (s[1] == 'W'
1390 && ! isvar (&opP->disp)
1391 && (opP->disp.exp.X_op != O_constant
1392 || ! issword (opP->disp.exp.X_add_number)))
1393 losing++;
1394 break;
1395
1396 case '^':
1397 case 'T':
1398 if (opP->mode != IMMED)
1399 losing++;
1400 break;
1401
1402 case '$':
1403 if (opP->mode == AREG
1404 || opP->mode == CONTROL
1405 || opP->mode == FPREG
1406 || opP->mode == IMMED
1407 || opP->mode == REGLST
1408 || (opP->mode != ABSL
1409 && (opP->reg == PC
1410 || opP->reg == ZPC)))
1411 losing++;
1412 break;
1413
1414 case '%':
1415 if (opP->mode == CONTROL
1416 || opP->mode == FPREG
1417 || opP->mode == REGLST
1418 || opP->mode == IMMED
1419 || (opP->mode != ABSL
1420 && (opP->reg == PC
1421 || opP->reg == ZPC)))
1422 losing++;
1423 break;
1424
1425 case '&':
1426 switch (opP->mode)
1427 {
1428 case DREG:
1429 case AREG:
1430 case FPREG:
1431 case CONTROL:
1432 case IMMED:
1433 case AINC:
1434 case ADEC:
1435 case REGLST:
1436 losing++;
1437 break;
1438 case ABSL:
1439 break;
1440 default:
1441 if (opP->reg == PC
1442 || opP->reg == ZPC)
1443 losing++;
1444 break;
1445 }
1446 break;
1447
1448 case '*':
1449 if (opP->mode == CONTROL
1450 || opP->mode == FPREG
1451 || opP->mode == REGLST)
1452 losing++;
1453 break;
1454
1455 case '+':
1456 if (opP->mode != AINC)
1457 losing++;
1458 break;
1459
1460 case '-':
1461 if (opP->mode != ADEC)
1462 losing++;
1463 break;
1464
1465 case '/':
1466 switch (opP->mode)
1467 {
1468 case AREG:
1469 case CONTROL:
1470 case FPREG:
1471 case AINC:
1472 case ADEC:
1473 case IMMED:
1474 case REGLST:
1475 losing++;
1476 break;
1477 default:
1478 break;
1479 }
1480 break;
1481
1482 case ';':
1483 switch (opP->mode)
1484 {
1485 case AREG:
1486 case CONTROL:
1487 case FPREG:
1488 case REGLST:
1489 losing++;
1490 break;
1491 default:
1492 break;
1493 }
1494 break;
1495
1496 case '?':
1497 switch (opP->mode)
1498 {
1499 case AREG:
1500 case CONTROL:
1501 case FPREG:
1502 case AINC:
1503 case ADEC:
1504 case IMMED:
1505 case REGLST:
1506 losing++;
1507 break;
1508 case ABSL:
1509 break;
1510 default:
1511 if (opP->reg == PC || opP->reg == ZPC)
1512 losing++;
1513 break;
1514 }
1515 break;
1516
1517 case '@':
1518 switch (opP->mode)
1519 {
1520 case AREG:
1521 case CONTROL:
1522 case FPREG:
1523 case IMMED:
1524 case REGLST:
1525 losing++;
1526 break;
1527 default:
1528 break;
1529 }
1530 break;
1531
1532 case '~': /* For now! (JF FOO is this right?) */
1533 switch (opP->mode)
1534 {
1535 case DREG:
1536 case AREG:
1537 case CONTROL:
1538 case FPREG:
1539 case IMMED:
1540 case REGLST:
1541 losing++;
1542 break;
1543 case ABSL:
1544 break;
1545 default:
1546 if (opP->reg == PC
1547 || opP->reg == ZPC)
1548 losing++;
1549 break;
1550 }
1551 break;
1552
1553 case '3':
1554 if (opP->mode != CONTROL
1555 || (opP->reg != TT0 && opP->reg != TT1))
1556 losing++;
1557 break;
1558
1559 case 'A':
1560 if (opP->mode != AREG)
1561 losing++;
1562 break;
1563
1564 case 'a':
1565 if (opP->mode != AINDR)
1566 ++losing;
1567 break;
1568
fd99574b
NC		 1569 case '4':
1570 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1571 && (opP->mode != DISP
1572 || opP->reg < ADDR0
1573 || opP->reg > ADDR7))
1574 ++losing;
1575 break;
1576
252b5132
RH		 1577 case 'B': /* FOO */
1578 if (opP->mode != ABSL
1579 || (flag_long_jumps
1580 && strncmp (instring, "jbsr", 4) == 0))
1581 losing++;
1582 break;
1583
3e602632
NC		 1584 case 'b':
1585 switch (opP->mode)
1586 {
1587 case IMMED:
1588 case ABSL:
1589 case AREG:
1590 case FPREG:
1591 case CONTROL:
1592 case POST:
1593 case PRE:
1594 case REGLST:
1595 losing++;
1596 break;
1597 default:
1598 break;
1599 }
1600 break;
1601
252b5132
RH		 1602 case 'C':
1603 if (opP->mode != CONTROL || opP->reg != CCR)
1604 losing++;
1605 break;
1606
1607 case 'd':
1608 if (opP->mode != DISP
1609 || opP->reg < ADDR0
1610 || opP->reg > ADDR7)
1611 losing++;
1612 break;
1613
1614 case 'D':
1615 if (opP->mode != DREG)
1616 losing++;
1617 break;
1618
6da466c7
ILT		 1619 case 'E':
1620 if (opP->reg != ACC)
1621 losing++;
1622 break;
1623
fd99574b
NC		 1624 case 'e':
1625 if (opP->reg != ACC && opP->reg != ACC1
1626 && opP->reg != ACC2 && opP->reg != ACC3)
1627 losing++;
1628 break;
1629
252b5132
RH		 1630 case 'F':
1631 if (opP->mode != FPREG)
1632 losing++;
1633 break;
1634
6da466c7
ILT		 1635 case 'G':
1636 if (opP->reg != MACSR)
1637 losing++;
1638 break;
1639
fd99574b
NC		 1640 case 'g':
1641 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1642 losing++;
1643 break;
1644
6da466c7
ILT		 1645 case 'H':
1646 if (opP->reg != MASK)
1647 losing++;
1648 break;
1649
252b5132
RH		 1650 case 'I':
1651 if (opP->mode != CONTROL
1652 || opP->reg < COP0
1653 || opP->reg > COP7)
1654 losing++;
1655 break;
1656
fd99574b
NC		 1657 case 'i':
1658 if (opP->mode != LSH && opP->mode != RSH)
1659 losing++;
1660 break;
1661
252b5132
RH		 1662 case 'J':
1663 if (opP->mode != CONTROL
1664 || opP->reg < USP
1665 || opP->reg > last_movec_reg)
1666 losing++;
1667 else
1668 {
1669 const enum m68k_register *rp;
1670 for (rp = control_regs; *rp; rp++)
1671 if (*rp == opP->reg)
1672 break;
1673 if (*rp == 0)
1674 losing++;
1675 }
1676 break;
1677
1678 case 'k':
1679 if (opP->mode != IMMED)
1680 losing++;
1681 break;
1682
1683 case 'l':
1684 case 'L':
1685 if (opP->mode == DREG
1686 || opP->mode == AREG
1687 || opP->mode == FPREG)
1688 {
1689 if (s[1] == '8')
1690 losing++;
1691 else
1692 {
1693 switch (opP->mode)
1694 {
1695 case DREG:
1696 opP->mask = 1 << (opP->reg - DATA0);
1697 break;
1698 case AREG:
1699 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1700 break;
1701 case FPREG:
1702 opP->mask = 1 << (opP->reg - FP0 + 16);
1703 break;
1704 default:
1705 abort ();
1706 }
1707 opP->mode = REGLST;
1708 }
1709 }
1710 else if (opP->mode == CONTROL)
1711 {
1712 if (s[1] != '8')
1713 losing++;
1714 else
1715 {
1716 switch (opP->reg)
1717 {
1718 case FPI:
1719 opP->mask = 1 << 24;
1720 break;
1721 case FPS:
1722 opP->mask = 1 << 25;
1723 break;
1724 case FPC:
1725 opP->mask = 1 << 26;
1726 break;
1727 default:
1728 losing++;
1729 break;
1730 }
1731 opP->mode = REGLST;
1732 }
1733 }
1734 else if (opP->mode != REGLST)
1735 losing++;
1736 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1737 losing++;
1738 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1739 losing++;
1740 break;
1741
1742 case 'M':
1743 if (opP->mode != IMMED)
1744 losing++;
1745 else if (opP->disp.exp.X_op != O_constant
1746 || ! issbyte (opP->disp.exp.X_add_number))
1747 losing++;
1748 else if (! m68k_quick
1749 && instring[3] != 'q'
1750 && instring[4] != 'q')
1751 losing++;
1752 break;
1753
1754 case 'O':
1755 if (opP->mode != DREG
1756 && opP->mode != IMMED
1757 && opP->mode != ABSL)
1758 losing++;
1759 break;
1760
1761 case 'Q':
1762 if (opP->mode != IMMED)
1763 losing++;
1764 else if (opP->disp.exp.X_op != O_constant
1765 || opP->disp.exp.X_add_number < 1
1766 || opP->disp.exp.X_add_number > 8)
1767 losing++;
1768 else if (! m68k_quick
1769 && (strncmp (instring, "add", 3) == 0
1770 || strncmp (instring, "sub", 3) == 0)
1771 && instring[3] != 'q')
1772 losing++;
1773 break;
1774
1775 case 'R':
1776 if (opP->mode != DREG && opP->mode != AREG)
1777 losing++;
1778 break;
1779
1780 case 'r':
1781 if (opP->mode != AINDR
1782 && (opP->mode != BASE
1783 || (opP->reg != 0
1784 && opP->reg != ZADDR0)
1785 || opP->disp.exp.X_op != O_absent
1786 || ((opP->index.reg < DATA0
1787 || opP->index.reg > DATA7)
1788 && (opP->index.reg < ADDR0
1789 || opP->index.reg > ADDR7))
1790 || opP->index.size != SIZE_UNSPEC
1791 || opP->index.scale != 1))
1792 losing++;
1793 break;
1794
1795 case 's':
1796 if (opP->mode != CONTROL
1797 || ! (opP->reg == FPI
1798 || opP->reg == FPS
1799 || opP->reg == FPC))
1800 losing++;
1801 break;
1802
1803 case 'S':
1804 if (opP->mode != CONTROL || opP->reg != SR)
1805 losing++;
1806 break;
1807
1808 case 't':
1809 if (opP->mode != IMMED)
1810 losing++;
1811 else if (opP->disp.exp.X_op != O_constant
1812 || opP->disp.exp.X_add_number < 0
1813 || opP->disp.exp.X_add_number > 7)
1814 losing++;
1815 break;
1816
1817 case 'U':
1818 if (opP->mode != CONTROL || opP->reg != USP)
1819 losing++;
1820 break;
1821
3e602632
NC		 1822 case 'x':
1823 if (opP->mode != IMMED)
1824 losing++;
1825 else if (opP->disp.exp.X_op != O_constant
1826 || opP->disp.exp.X_add_number < -1
1827 || opP->disp.exp.X_add_number > 7
1828 || opP->disp.exp.X_add_number == 0)
1829 losing++;
1830 break;
1831
252b5132
RH		 1832 /* JF these are out of order. We could put them
1833 in order if we were willing to put up with
1834 bunches of #ifdef m68851s in the code.
1835
1836 Don't forget that you need these operands
1837 to use 68030 MMU instructions. */
1838#ifndef NO_68851
36759679 1839 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1840 case '|':
1841 if (opP->mode == CONTROL
1842 || opP->mode == FPREG
1843 || opP->mode == DREG
1844 || opP->mode == AREG
1845 || opP->mode == REGLST)
1846 losing++;
1847 /* We should accept immediate operands, but they
1848 supposedly have to be quad word, and we don't
1849 handle that. I would like to see what a Motorola
1850 assembler does before doing something here. */
1851 if (opP->mode == IMMED)
1852 losing++;
1853 break;
1854
1855 case 'f':
1856 if (opP->mode != CONTROL
1857 || (opP->reg != SFC && opP->reg != DFC))
1858 losing++;
1859 break;
1860
1861 case '0':
1862 if (opP->mode != CONTROL || opP->reg != TC)
1863 losing++;
1864 break;
1865
1866 case '1':
1867 if (opP->mode != CONTROL || opP->reg != AC)
1868 losing++;
1869 break;
1870
1871 case '2':
1872 if (opP->mode != CONTROL
1873 || (opP->reg != CAL
1874 && opP->reg != VAL
1875 && opP->reg != SCC))
1876 losing++;
1877 break;
1878
1879 case 'V':
1880 if (opP->mode != CONTROL
1881 || opP->reg != VAL)
1882 losing++;
1883 break;
1884
1885 case 'W':
1886 if (opP->mode != CONTROL
1887 || (opP->reg != DRP
1888 && opP->reg != SRP
1889 && opP->reg != CRP))
1890 losing++;
1891 break;
1892
3e602632
NC		 1893 case 'w':
1894 switch (opP->mode)
1895 {
1896 case IMMED:
1897 case ABSL:
1898 case AREG:
1899 case DREG:
1900 case FPREG:
1901 case CONTROL:
1902 case POST:
1903 case PRE:
1904 case REGLST:
1905 losing++;
1906 break;
1907 default:
1908 break;
1909 }
1910 break;
1911
252b5132
RH		 1912 case 'X':
1913 if (opP->mode != CONTROL
1914 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1915 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1916 losing++;
1917 break;
1918
1919 case 'Y':
1920 if (opP->mode != CONTROL || opP->reg != PSR)
1921 losing++;
1922 break;
1923
1924 case 'Z':
1925 if (opP->mode != CONTROL || opP->reg != PCSR)
1926 losing++;
1927 break;
1928#endif
1929 case 'c':
1930 if (opP->mode != CONTROL
1931 || (opP->reg != NC
1932 && opP->reg != IC
1933 && opP->reg != DC
1934 && opP->reg != BC))
36759679 1935 losing++;
252b5132
RH		 1936 break;
1937
1938 case '_':
1939 if (opP->mode != ABSL)
1940 ++losing;
1941 break;
1942
6da466c7
ILT		 1943 case 'u':
1944 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1945 losing++;
1946 /* FIXME: kludge instead of fixing parser:
1947 upper/lower registers are *not* CONTROL
92774660 1948 registers, but ordinary ones. */
6da466c7
ILT		 1949 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1950 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1951 opP->mode = DREG;
1952 else
1953 opP->mode = AREG;
1954 break;
1955
3e602632
NC		 1956 case 'y':
1957 if (!(opP->mode == AINDR
31302357
AS		 1958 || (opP->mode == DISP
1959 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 1960 losing++;
1961 break;
1962
1963 case 'z':
1964 if (!(opP->mode == AINDR || opP->mode == DISP))
1965 losing++;
1966 break;
1967
252b5132
RH		 1968 default:
1969 abort ();
36759679 1970 }
252b5132
RH		 1971
1972 if (losing)
1973 break;
36759679
NC		 1974 }
1975 }
252b5132
RH		 1976
1977 if (!losing)
36759679 1978 break;
252b5132
RH		 1979
1980 opcode = opcode->m_next;
1981
1982 if (!opcode)
1983 {
1984 if (ok_arch
1985 && !(ok_arch & current_architecture))
1986 {
1987 char buf[200], *cp;
1988
6b6e92f4 1989 strncpy (buf,
31302357
AS		 1990 _("invalid instruction for this architecture; needs "),
1991 sizeof (buf));
252b5132
RH		 1992 cp = buf + strlen (buf);
1993 switch (ok_arch)
1994 {
6b6e92f4 1995 case mcfisa_a:
31302357
AS		 1996 strncpy (cp, _("ColdFire ISA_A"),
1997 sizeof (buf) - (cp - buf));
6b6e92f4 1998 cp += strlen (cp);
31302357
AS		 1999 strncpy (cp, find_cf_chip (ok_arch),
2000 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2001 cp += strlen (cp);
2002 break;
2003 case mcfhwdiv:
31302357
AS		 2004 strncpy (cp, _("ColdFire hardware divide"),
2005 sizeof (buf) - (cp - buf));
6b6e92f4 2006 cp += strlen (cp);
31302357
AS		 2007 strncpy (cp, find_cf_chip (ok_arch),
2008 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2009 cp += strlen (cp);
2010 break;
2011 case mcfisa_aa:
31302357
AS		 2012 strncpy (cp, _("ColdFire ISA_A+"),
2013 sizeof (buf) - (cp - buf));
6b6e92f4 2014 cp += strlen (cp);
31302357
AS		 2015 strncpy (cp, find_cf_chip (ok_arch),
2016 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2017 cp += strlen (cp);
2018 break;
2019 case mcfisa_b:
31302357
AS		 2020 strncpy (cp, _("ColdFire ISA_B"),
2021 sizeof (buf) - (cp - buf));
6b6e92f4 2022 cp += strlen (cp);
31302357
AS		 2023 strncpy (cp, find_cf_chip (ok_arch),
2024 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2025 cp += strlen (cp);
2026 break;
3e602632 2027 case cfloat:
31302357 2028 strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf));
6b6e92f4 2029 cp += strlen (cp);
31302357
AS		 2030 strncpy (cp, find_cf_chip (ok_arch),
2031 sizeof (buf) - (cp - buf));
6b6e92f4 2032 cp += strlen (cp);
3e602632 2033 break;
252b5132
RH		 2034 case mfloat:
2035 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2036 break;
2037 case mmmu:
2038 strcpy (cp, _("mmu (68030 or 68851)"));
2039 break;
2040 case m68020up:
2041 strcpy (cp, _("68020 or higher"));
2042 break;
2043 case m68000up:
2044 strcpy (cp, _("68000 or higher"));
2045 break;
2046 case m68010up:
2047 strcpy (cp, _("68010 or higher"));
2048 break;
2049 default:
2050 {
2051 int got_one = 0, idx;
6b6e92f4
NC		 2052
2053 for (idx = 0; idx < n_archs; idx++)
252b5132
RH		 2054 {
2055 if ((archs[idx].arch & ok_arch)
2056 && ! archs[idx].alias)
2057 {
2058 if (got_one)
2059 {
2060 strcpy (cp, " or ");
2061 cp += strlen (cp);
2062 }
2063 got_one = 1;
2064 strcpy (cp, archs[idx].name);
2065 cp += strlen (cp);
2066 }
2067 }
2068 }
2069 }
2070 cp = xmalloc (strlen (buf) + 1);
2071 strcpy (cp, buf);
2072 the_ins.error = cp;
2073 }
2074 else
2075 the_ins.error = _("operands mismatch");
2076 return;
36759679 2077 }
252b5132
RH		 2078
2079 losing = 0;
2080 }
2081
36759679 2082 /* Now assemble it. */
252b5132
RH		 2083 the_ins.args = opcode->m_operands;
2084 the_ins.numargs = opcode->m_opnum;
2085 the_ins.numo = opcode->m_codenum;
2086 the_ins.opcode[0] = getone (opcode);
2087 the_ins.opcode[1] = gettwo (opcode);
2088
2089 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2090 {
2091 /* This switch is a doozy.
31302357 2092 Watch the first step; its a big one! */
252b5132
RH		 2093 switch (s[0])
2094 {
2095
2096 case '*':
2097 case '~':
2098 case '%':
2099 case ';':
2100 case '@':
2101 case '!':
2102 case '&':
2103 case '$':
2104 case '?':
2105 case '/':
2106 case '<':
2107 case '>':
3e602632 2108 case 'b':
252b5132
RH		 2109 case 'm':
2110 case 'n':
2111 case 'o':
2112 case 'p':
2113 case 'q':
2114 case 'v':
3e602632
NC		 2115 case 'w':
2116 case 'y':
2117 case 'z':
fd99574b 2118 case '4':
252b5132
RH		 2119#ifndef NO_68851
2120 case '|':
2121#endif
2122 switch (opP->mode)
2123 {
2124 case IMMED:
2125 tmpreg = 0x3c; /* 7.4 */
2126 if (strchr ("bwl", s[1]))
3e602632 2127 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2128 else
2129 nextword = get_num (&opP->disp, 0);
2130 if (isvar (&opP->disp))
2131 add_fix (s[1], &opP->disp, 0, 0);
2132 switch (s[1])
2133 {
2134 case 'b':
2135 if (!isbyte (nextword))
2136 opP->error = _("operand out of range");
2137 addword (nextword);
2138 baseo = 0;
2139 break;
2140 case 'w':
2141 if (!isword (nextword))
2142 opP->error = _("operand out of range");
2143 addword (nextword);
2144 baseo = 0;
2145 break;
2146 case 'W':
2147 if (!issword (nextword))
2148 opP->error = _("operand out of range");
2149 addword (nextword);
2150 baseo = 0;
2151 break;
2152 case 'l':
2153 addword (nextword >> 16);
2154 addword (nextword);
2155 baseo = 0;
2156 break;
2157
2158 case 'f':
2159 baseo = 2;
2160 outro = 8;
2161 break;
2162 case 'F':
2163 baseo = 4;
2164 outro = 11;
2165 break;
2166 case 'x':
2167 baseo = 6;
2168 outro = 15;
2169 break;
2170 case 'p':
2171 baseo = 6;
2172 outro = -1;
2173 break;
2174 default:
2175 abort ();
2176 }
2177 if (!baseo)
2178 break;
2179
36759679 2180 /* We gotta put out some float. */
252b5132
RH		 2181 if (op (&opP->disp) != O_big)
2182 {
2183 valueT val;
2184 int gencnt;
2185
2186 /* Can other cases happen here? */
2187 if (op (&opP->disp) != O_constant)
2188 abort ();
2189
2190 val = (valueT) offs (&opP->disp);
2191 gencnt = 0;
2192 do
2193 {
2194 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2195 val >>= LITTLENUM_NUMBER_OF_BITS;
2196 ++gencnt;
2197 }
2198 while (val != 0);
2199 offs (&opP->disp) = gencnt;
2200 }
2201 if (offs (&opP->disp) > 0)
2202 {
2203 if (offs (&opP->disp) > baseo)
2204 {
2205 as_warn (_("Bignum too big for %c format; truncated"),
2206 s[1]);
2207 offs (&opP->disp) = baseo;
2208 }
2209 baseo -= offs (&opP->disp);
2210 while (baseo--)
2211 addword (0);
2212 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2213 offs (&opP->disp)--;
2214 --wordp)
2215 addword (*wordp);
2216 break;
2217 }
2218 gen_to_words (words, baseo, (long) outro);
2219 for (wordp = words; baseo--; wordp++)
2220 addword (*wordp);
2221 break;
2222 case DREG:
2223 tmpreg = opP->reg - DATA; /* 0.dreg */
2224 break;
2225 case AREG:
2226 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2227 break;
2228 case AINDR:
2229 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2230 break;
2231 case ADEC:
2232 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2233 break;
2234 case AINC:
2235 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2236 break;
2237 case DISP:
2238
3e602632 2239 nextword = get_num (&opP->disp, 90);
252b5132 2240
580b9172
NC		 2241 /* Convert mode 5 addressing with a zero offset into
2242 mode 2 addressing to reduce the instruction size by a
2243 word. */
2244 if (! isvar (&opP->disp)
2245 && (nextword == 0)
2246 && (opP->disp.size == SIZE_UNSPEC)
2247 && (opP->reg >= ADDR0)
2248 && (opP->reg <= ADDR7))
2249 {
2250 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2251 break;
2252 }
2253
252b5132
RH		 2254 if (opP->reg == PC
2255 && ! isvar (&opP->disp)
2256 && m68k_abspcadd)
2257 {
2258 opP->disp.exp.X_op = O_symbol;
2259#ifndef BFD_ASSEMBLER
2260 opP->disp.exp.X_add_symbol = &abs_symbol;
2261#else
2262 opP->disp.exp.X_add_symbol =
2263 section_symbol (absolute_section);
2264#endif
2265 }
2266
36759679 2267 /* Force into index mode. Hope this works. */
252b5132
RH		 2268
2269 /* We do the first bit for 32-bit displacements, and the
2270 second bit for 16 bit ones. It is possible that we
2271 should make the default be WORD instead of LONG, but
2272 I think that'd break GCC, so we put up with a little
2273 inefficiency for the sake of working output. */
2274
2275 if (!issword (nextword)
2276 || (isvar (&opP->disp)
2277 && ((opP->disp.size == SIZE_UNSPEC
2278 && flag_short_refs == 0
2279 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2280 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2281 || opP->disp.size == SIZE_LONG)))
2282 {
2283 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2284 || arch_coldfire_p (current_architecture))
252b5132
RH		 2285 opP->error =
2286 _("displacement too large for this architecture; needs 68020 or higher");
2287 if (opP->reg == PC)
2288 tmpreg = 0x3B; /* 7.3 */
2289 else
2290 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2291 if (isvar (&opP->disp))
2292 {
2293 if (opP->reg == PC)
2294 {
2295 if (opP->disp.size == SIZE_LONG
2296#ifdef OBJ_ELF
2297 /* If the displacement needs pic
2298 relocation it cannot be relaxed. */
2299 || opP->disp.pic_reloc != pic_none
2300#endif
2301 )
2302 {
2303 addword (0x0170);
2304 add_fix ('l', &opP->disp, 1, 2);
2305 }
2306 else
2307 {
2308 add_frag (adds (&opP->disp),
2309 offs (&opP->disp),
151337e8 2310 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2311 break;
2312 }
2313 }
2314 else
2315 {
2316 addword (0x0170);
2317 add_fix ('l', &opP->disp, 0, 0);
2318 }
2319 }
2320 else
2321 addword (0x0170);
2322 addword (nextword >> 16);
2323 }
2324 else
2325 {
2326 if (opP->reg == PC)
2327 tmpreg = 0x3A; /* 7.2 */
2328 else
2329 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2330
2331 if (isvar (&opP->disp))
2332 {
2333 if (opP->reg == PC)
2334 {
2335 add_fix ('w', &opP->disp, 1, 0);
2336 }
2337 else
2338 add_fix ('w', &opP->disp, 0, 0);
2339 }
2340 }
2341 addword (nextword);
2342 break;
2343
2344 case POST:
2345 case PRE:
2346 case BASE:
2347 nextword = 0;
3e602632 2348 baseo = get_num (&opP->disp, 90);
252b5132 2349 if (opP->mode == POST || opP->mode == PRE)
3e602632 2350 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2351 /* Figure out the `addressing mode'.
2352 Also turn on the BASE_DISABLE bit, if needed. */
2353 if (opP->reg == PC || opP->reg == ZPC)
2354 {
2355 tmpreg = 0x3b; /* 7.3 */
2356 if (opP->reg == ZPC)
2357 nextword |= 0x80;
2358 }
2359 else if (opP->reg == 0)
2360 {
2361 nextword |= 0x80;
2362 tmpreg = 0x30; /* 6.garbage */
2363 }
2364 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2365 {
2366 nextword |= 0x80;
2367 tmpreg = 0x30 + opP->reg - ZADDR0;
2368 }
2369 else
2370 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2371
2372 siz1 = opP->disp.size;
2373 if (opP->mode == POST || opP->mode == PRE)
2374 siz2 = opP->odisp.size;
2375 else
2376 siz2 = SIZE_UNSPEC;
2377
36759679 2378 /* Index register stuff. */
252b5132
RH		 2379 if (opP->index.reg != 0
2380 && opP->index.reg >= DATA
2381 && opP->index.reg <= ADDR7)
2382 {
2383 nextword |= (opP->index.reg - DATA) << 12;
2384
2385 if (opP->index.size == SIZE_LONG
2386 || (opP->index.size == SIZE_UNSPEC
2387 && m68k_index_width_default == SIZE_LONG))
2388 nextword |= 0x800;
2389
92774660 2390 if ((opP->index.scale != 1
252b5132 2391 && cpu_of_arch (current_architecture) < m68020)
92774660 2392 || (opP->index.scale == 8
3e602632 2393 && (arch_coldfire_p (current_architecture)
6b6e92f4 2394 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2395 {
2396 opP->error =
2397 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2398 }
2399
6da466c7
ILT		 2400 if (arch_coldfire_p (current_architecture)
2401 && opP->index.size == SIZE_WORD)
2402 opP->error = _("invalid index size for coldfire");
2403
252b5132
RH		 2404 switch (opP->index.scale)
2405 {
2406 case 1:
2407 break;
2408 case 2:
2409 nextword |= 0x200;
2410 break;
2411 case 4:
2412 nextword |= 0x400;
2413 break;
2414 case 8:
2415 nextword |= 0x600;
2416 break;
2417 default:
2418 abort ();
2419 }
2420 /* IF its simple,
2421 GET US OUT OF HERE! */
2422
2423 /* Must be INDEX, with an index register. Address
2424 register cannot be ZERO-PC, and either :b was
2425 forced, or we know it will fit. For a 68000 or
2426 68010, force this mode anyways, because the
2427 larger modes aren't supported. */
2428 if (opP->mode == BASE
2429 && ((opP->reg >= ADDR0
2430 && opP->reg <= ADDR7)
2431 || opP->reg == PC))
2432 {
2433 if (siz1 == SIZE_BYTE
2434 || cpu_of_arch (current_architecture) < m68020
6da466c7 2435 || arch_coldfire_p (current_architecture)
252b5132
RH		 2436 || (siz1 == SIZE_UNSPEC
2437 && ! isvar (&opP->disp)
2438 && issbyte (baseo)))
2439 {
2440 nextword += baseo & 0xff;
2441 addword (nextword);
2442 if (isvar (&opP->disp))
2443 {
2444 /* Do a byte relocation. If it doesn't
2445 fit (possible on m68000) let the
2446 fixup processing complain later. */
2447 if (opP->reg == PC)
2448 add_fix ('B', &opP->disp, 1, 1);
2449 else
2450 add_fix ('B', &opP->disp, 0, 0);
2451 }
2452 else if (siz1 != SIZE_BYTE)
2453 {
2454 if (siz1 != SIZE_UNSPEC)
2455 as_warn (_("Forcing byte displacement"));
2456 if (! issbyte (baseo))
2457 opP->error = _("byte displacement out of range");
2458 }
2459
2460 break;
2461 }
2462 else if (siz1 == SIZE_UNSPEC
2463 && opP->reg == PC
2464 && isvar (&opP->disp)
2465 && subs (&opP->disp) == NULL
2466#ifdef OBJ_ELF
2467 /* If the displacement needs pic
2468 relocation it cannot be relaxed. */
2469 && opP->disp.pic_reloc == pic_none
2470#endif
2471 )
2472 {
2473 /* The code in md_convert_frag_1 needs to be
2474 able to adjust nextword. Call frag_grow
2475 to ensure that we have enough space in
2476 the frag obstack to make all the bytes
2477 contiguous. */
2478 frag_grow (14);
8a104df9
KH		 2479 nextword += baseo & 0xff;
2480 addword (nextword);
2481 add_frag (adds (&opP->disp), offs (&opP->disp),
2482 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2483
2484 break;
8a104df9 2485 }
252b5132
RH		 2486 }
2487 }
2488 else
2489 {
36759679 2490 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2491 if (opP->index.reg >= ZDATA0
2492 && opP->index.reg <= ZDATA7)
2493 nextword |= (opP->index.reg - ZDATA0) << 12;
2494 else if (opP->index.reg >= ZADDR0
2495 || opP->index.reg <= ZADDR7)
2496 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2497 }
2498
2499 /* It isn't simple. */
2500
2501 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2502 || arch_coldfire_p (current_architecture))
252b5132
RH		 2503 opP->error =
2504 _("invalid operand mode for this architecture; needs 68020 or higher");
2505
2506 nextword |= 0x100;
2507 /* If the guy specified a width, we assume that it is
2508 wide enough. Maybe it isn't. If so, we lose. */
2509 switch (siz1)
2510 {
2511 case SIZE_UNSPEC:
2512 if (isvar (&opP->disp)
2513 ? m68k_rel32
2514 : ! issword (baseo))
2515 {
2516 siz1 = SIZE_LONG;
2517 nextword |= 0x30;
2518 }
2519 else if (! isvar (&opP->disp) && baseo == 0)
2520 nextword |= 0x10;
2521 else
2522 {
2523 nextword |= 0x20;
2524 siz1 = SIZE_WORD;
2525 }
2526 break;
2527 case SIZE_BYTE:
2528 as_warn (_(":b not permitted; defaulting to :w"));
2529 /* Fall through. */
2530 case SIZE_WORD:
2531 nextword |= 0x20;
2532 break;
2533 case SIZE_LONG:
2534 nextword |= 0x30;
2535 break;
2536 }
2537
67c1ffbe 2538 /* Figure out inner displacement stuff. */
252b5132
RH		 2539 if (opP->mode == POST || opP->mode == PRE)
2540 {
2541 if (cpu_of_arch (current_architecture) & cpu32)
2542 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2543 switch (siz2)
2544 {
2545 case SIZE_UNSPEC:
2546 if (isvar (&opP->odisp)
2547 ? m68k_rel32
2548 : ! issword (outro))
2549 {
2550 siz2 = SIZE_LONG;
2551 nextword |= 0x3;
2552 }
2553 else if (! isvar (&opP->odisp) && outro == 0)
2554 nextword |= 0x1;
2555 else
2556 {
2557 nextword |= 0x2;
2558 siz2 = SIZE_WORD;
2559 }
2560 break;
2561 case 1:
2562 as_warn (_(":b not permitted; defaulting to :w"));
2563 /* Fall through. */
2564 case 2:
2565 nextword |= 0x2;
2566 break;
2567 case 3:
2568 nextword |= 0x3;
2569 break;
2570 }
2571 if (opP->mode == POST
2572 && (nextword & 0x40) == 0)
2573 nextword |= 0x04;
2574 }
2575 addword (nextword);
2576
2577 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2578 {
2579 if (opP->reg == PC || opP->reg == ZPC)
2580 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2581 else
2582 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2583 }
2584 if (siz1 == SIZE_LONG)
2585 addword (baseo >> 16);
2586 if (siz1 != SIZE_UNSPEC)
2587 addword (baseo);
2588
2589 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2590 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2591 if (siz2 == SIZE_LONG)
2592 addword (outro >> 16);
2593 if (siz2 != SIZE_UNSPEC)
2594 addword (outro);
2595
2596 break;
2597
2598 case ABSL:
3e602632 2599 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2600 switch (opP->disp.size)
2601 {
2602 default:
2603 abort ();
2604 case SIZE_UNSPEC:
2605 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2606 {
2607 tmpreg = 0x38; /* 7.0 */
2608 addword (nextword);
2609 break;
2610 }
252b5132
RH		 2611 if (isvar (&opP->disp)
2612 && !subs (&opP->disp)
2613 && adds (&opP->disp)
2614#ifdef OBJ_ELF
2615 /* If the displacement needs pic relocation it
2616 cannot be relaxed. */
2617 && opP->disp.pic_reloc == pic_none
2618#endif
252b5132
RH		 2619 && !flag_long_jumps
2620 && !strchr ("~%&$?", s[0]))
2621 {
2622 tmpreg = 0x3A; /* 7.2 */
2623 add_frag (adds (&opP->disp),
2624 offs (&opP->disp),
151337e8 2625 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2626 break;
2627 }
36759679 2628 /* Fall through into long. */
252b5132
RH		 2629 case SIZE_LONG:
2630 if (isvar (&opP->disp))
2631 add_fix ('l', &opP->disp, 0, 0);
2632
2633 tmpreg = 0x39;/* 7.1 mode */
2634 addword (nextword >> 16);
2635 addword (nextword);
2636 break;
2637
2638 case SIZE_BYTE:
2639 as_bad (_("unsupported byte value; use a different suffix"));
2640 /* Fall through. */
36759679
NC		 2641
2642 case SIZE_WORD:
252b5132
RH		 2643 if (isvar (&opP->disp))
2644 add_fix ('w', &opP->disp, 0, 0);
2645
2646 tmpreg = 0x38;/* 7.0 mode */
2647 addword (nextword);
2648 break;
2649 }
2650 break;
2651 case CONTROL:
2652 case FPREG:
2653 default:
2654 as_bad (_("unknown/incorrect operand"));
bc805888 2655 /* abort (); */
252b5132 2656 }
fd99574b
NC		 2657
2658 /* If s[0] is '4', then this is for the mac instructions
2659 that can have a trailing_ampersand set. If so, set 0x100
2660 bit on tmpreg so install_gen_operand can check for it and
2661 set the appropriate bit (word2, bit 5). */
2662 if (s[0] == '4')
2663 {
2664 if (opP->trailing_ampersand)
2665 tmpreg |= 0x100;
2666 }
252b5132
RH		 2667 install_gen_operand (s[1], tmpreg);
2668 break;
2669
2670 case '#':
2671 case '^':
2672 switch (s[1])
2673 { /* JF: I hate floating point! */
2674 case 'j':
2675 tmpreg = 70;
2676 break;
2677 case '8':
2678 tmpreg = 20;
2679 break;
2680 case 'C':
2681 tmpreg = 50;
2682 break;
2683 case '3':
2684 default:
3e602632 2685 tmpreg = 90;
252b5132
RH		 2686 break;
2687 }
2688 tmpreg = get_num (&opP->disp, tmpreg);
2689 if (isvar (&opP->disp))
2690 add_fix (s[1], &opP->disp, 0, 0);
2691 switch (s[1])
2692 {
2693 case 'b': /* Danger: These do no check for
2694 certain types of overflow.
2695 user beware! */
2696 if (!isbyte (tmpreg))
2697 opP->error = _("out of range");
2698 insop (tmpreg, opcode);
2699 if (isvar (&opP->disp))
2700 the_ins.reloc[the_ins.nrel - 1].n =
2701 (opcode->m_codenum) * 2 + 1;
2702 break;
2703 case 'B':
2704 if (!issbyte (tmpreg))
2705 opP->error = _("out of range");
2706 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2707 if (isvar (&opP->disp))
2708 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2709 break;
2710 case 'w':
2711 if (!isword (tmpreg))
2712 opP->error = _("out of range");
2713 insop (tmpreg, opcode);
2714 if (isvar (&opP->disp))
2715 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2716 break;
2717 case 'W':
2718 if (!issword (tmpreg))
2719 opP->error = _("out of range");
2720 insop (tmpreg, opcode);
2721 if (isvar (&opP->disp))
2722 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2723 break;
2724 case 'l':
2725 /* Because of the way insop works, we put these two out
2726 backwards. */
2727 insop (tmpreg, opcode);
2728 insop (tmpreg >> 16, opcode);
2729 if (isvar (&opP->disp))
2730 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2731 break;
2732 case '3':
2733 tmpreg &= 0xFF;
2734 case '8':
2735 case 'C':
2736 case 'j':
2737 install_operand (s[1], tmpreg);
2738 break;
2739 default:
2740 abort ();
2741 }
2742 break;
2743
2744 case '+':
2745 case '-':
2746 case 'A':
2747 case 'a':
2748 install_operand (s[1], opP->reg - ADDR);
2749 break;
2750
2751 case 'B':
3e602632 2752 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2753 switch (s[1])
2754 {
2755 case 'B':
8390138c 2756 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2757 break;
2758 case 'W':
2759 add_fix ('w', &opP->disp, 1, 0);
2760 addword (0);
2761 break;
2762 case 'L':
2763 long_branch:
151337e8 2764 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2765 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2766 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2767 add_fix ('l', &opP->disp, 1, 0);
2768 addword (0);
2769 addword (0);
2770 break;
2771 case 'g':
36759679 2772 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2773 goto long_branch;
2774
2775#ifdef OBJ_ELF
2776 /* If the displacement needs pic relocation it cannot be
2777 relaxed. */
2778 if (opP->disp.pic_reloc != pic_none)
2779 goto long_branch;
2780#endif
252b5132 2781 /* This could either be a symbol, or an absolute
151337e8
NC		 2782 address. If it's an absolute address, turn it into
2783 an absolute jump right here and keep it out of the
2784 relaxer. */
2785 if (adds (&opP->disp) == 0)
2786 {
2787 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2788 the_ins.opcode[0] = 0x4EF9;
151337e8 2789 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2790 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2791 else /* jCC */
2792 {
2793 the_ins.opcode[0] ^= 0x0100;
2794 the_ins.opcode[0] |= 0x0006;
18566f55 2795 addword (0x4EF9);
151337e8
NC		 2796 }
2797 add_fix ('l', &opP->disp, 0, 0);
2798 addword (0);
2799 addword (0);
2800 break;
2801 }
2802
2803 /* Now we know it's going into the relaxer. Now figure
2804 out which mode. We try in this order of preference:
2805 long branch, absolute jump, byte/word branches only. */
2806 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2807 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2808 TAB (BRANCHBWL, SZ_UNDEF));
2809 else if (! flag_keep_pcrel)
2810 {
2811 if ((the_ins.opcode[0] == 0x6000)
2812 || (the_ins.opcode[0] == 0x6100))
2813 add_frag (adds (&opP->disp), offs (&opP->disp),
2814 TAB (BRABSJUNC, SZ_UNDEF));
2815 else
2816 add_frag (adds (&opP->disp), offs (&opP->disp),
2817 TAB (BRABSJCOND, SZ_UNDEF));
2818 }
252b5132
RH		 2819 else
2820 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2821 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2822 break;
2823 case 'w':
2824 if (isvar (&opP->disp))
2825 {
151337e8
NC		 2826 /* Check for DBcc instructions. We can relax them,
2827 but only if we have long branches and/or absolute
2828 jumps. */
2829 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2830 && (HAVE_LONG_BRANCH (current_architecture)
2831 || (! flag_keep_pcrel)))
252b5132 2832 {
151337e8
NC		 2833 if (HAVE_LONG_BRANCH (current_architecture))
2834 add_frag (adds (&opP->disp), offs (&opP->disp),
2835 TAB (DBCCLBR, SZ_UNDEF));
2836 else
2837 add_frag (adds (&opP->disp), offs (&opP->disp),
2838 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2839 break;
2840 }
252b5132
RH		 2841 add_fix ('w', &opP->disp, 1, 0);
2842 }
2843 addword (0);
2844 break;
36759679 2845 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2846 add_fix ('l', &opP->disp, 1, 0);
2847 addword (0);
2848 addword (0);
2849 break;
36759679 2850 case 'c': /* Var size Coprocesssor branches. */
151337e8 2851 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2852 {
252b5132
RH		 2853 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2854 add_fix ('l', &opP->disp, 1, 0);
2855 addword (0);
2856 addword (0);
2857 }
151337e8
NC		 2858 else
2859 add_frag (adds (&opP->disp), offs (&opP->disp),
2860 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2861 break;
2862 default:
2863 abort ();
2864 }
2865 break;
2866
36759679 2867 case 'C': /* Ignore it. */
252b5132
RH		 2868 break;
2869
36759679 2870 case 'd': /* JF this is a kludge. */
252b5132 2871 install_operand ('s', opP->reg - ADDR);
3e602632 2872 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2873 if (!issword (tmpreg))
2874 {
2875 as_warn (_("Expression out of range, using 0"));
2876 tmpreg = 0;
2877 }
2878 addword (tmpreg);
2879 break;
2880
2881 case 'D':
2882 install_operand (s[1], opP->reg - DATA);
2883 break;
2884
fd99574b
NC		 2885 case 'e': /* EMAC ACCx, reg/reg. */
2886 install_operand (s[1], opP->reg - ACC);
2887 break;
2888
36759679 2889 case 'E': /* Ignore it. */
6da466c7
ILT		 2890 break;
2891
252b5132
RH		 2892 case 'F':
2893 install_operand (s[1], opP->reg - FP0);
2894 break;
2895
fd99574b
NC		 2896 case 'g': /* EMAC ACCEXTx. */
2897 install_operand (s[1], opP->reg - ACCEXT01);
2898 break;
2899
36759679 2900 case 'G': /* Ignore it. */
6da466c7
ILT		 2901 case 'H':
2902 break;
2903
252b5132
RH		 2904 case 'I':
2905 tmpreg = opP->reg - COP0;
2906 install_operand (s[1], tmpreg);
2907 break;
2908
fd99574b
NC		 2909 case 'i': /* MAC/EMAC scale factor. */
2910 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2911 break;
2912
36759679 2913 case 'J': /* JF foo. */
252b5132
RH		 2914 switch (opP->reg)
2915 {
2916 case SFC:
2917 tmpreg = 0x000;
2918 break;
2919 case DFC:
2920 tmpreg = 0x001;
2921 break;
2922 case CACR:
2923 tmpreg = 0x002;
2924 break;
2925 case TC:
2926 tmpreg = 0x003;
2927 break;
3e602632 2928 case ACR0:
252b5132
RH		 2929 case ITT0:
2930 tmpreg = 0x004;
2931 break;
3e602632 2932 case ACR1:
252b5132
RH		 2933 case ITT1:
2934 tmpreg = 0x005;
2935 break;
3e602632 2936 case ACR2:
252b5132
RH		 2937 case DTT0:
2938 tmpreg = 0x006;
2939 break;
3e602632 2940 case ACR3:
252b5132
RH		 2941 case DTT1:
2942 tmpreg = 0x007;
2943 break;
2944 case BUSCR:
2945 tmpreg = 0x008;
2946 break;
2947
2948 case USP:
2949 tmpreg = 0x800;
2950 break;
2951 case VBR:
2952 tmpreg = 0x801;
2953 break;
2954 case CAAR:
2955 tmpreg = 0x802;
2956 break;
2957 case MSP:
2958 tmpreg = 0x803;
2959 break;
2960 case ISP:
2961 tmpreg = 0x804;
2962 break;
2963 case MMUSR:
2964 tmpreg = 0x805;
2965 break;
2966 case URP:
2967 tmpreg = 0x806;
2968 break;
2969 case SRP:
2970 tmpreg = 0x807;
2971 break;
2972 case PCR:
2973 tmpreg = 0x808;
2974 break;
2975 case ROMBAR:
2976 tmpreg = 0xC00;
2977 break;
3e602632
NC		 2978 case ROMBAR1:
2979 tmpreg = 0xC01;
2980 break;
2981 case FLASHBAR:
252b5132
RH		 2982 case RAMBAR0:
2983 tmpreg = 0xC04;
2984 break;
3e602632 2985 case RAMBAR:
252b5132
RH		 2986 case RAMBAR1:
2987 tmpreg = 0xC05;
2988 break;
3e602632
NC		 2989 case MPCR:
2990 tmpreg = 0xC0C;
2991 break;
2992 case EDRAMBAR:
2993 tmpreg = 0xC0D;
2994 break;
2995 case MBAR0:
e80e0390 2996 case MBAR2:
3e602632
NC		 2997 case SECMBAR:
2998 tmpreg = 0xC0E;
2999 break;
3000 case MBAR1:
252b5132
RH		 3001 case MBAR:
3002 tmpreg = 0xC0F;
3003 break;
3e602632
NC		 3004 case PCR1U0:
3005 tmpreg = 0xD02;
3006 break;
3007 case PCR1L0:
3008 tmpreg = 0xD03;
3009 break;
3010 case PCR2U0:
3011 tmpreg = 0xD04;
3012 break;
3013 case PCR2L0:
3014 tmpreg = 0xD05;
3015 break;
3016 case PCR3U0:
3017 tmpreg = 0xD06;
3018 break;
3019 case PCR3L0:
3020 tmpreg = 0xD07;
3021 break;
3022 case PCR1L1:
3023 tmpreg = 0xD0A;
3024 break;
3025 case PCR1U1:
3026 tmpreg = 0xD0B;
3027 break;
3028 case PCR2L1:
3029 tmpreg = 0xD0C;
3030 break;
3031 case PCR2U1:
3032 tmpreg = 0xD0D;
3033 break;
3034 case PCR3L1:
3035 tmpreg = 0xD0E;
3036 break;
3037 case PCR3U1:
3038 tmpreg = 0xD0F;
3039 break;
252b5132
RH		 3040 default:
3041 abort ();
3042 }
3043 install_operand (s[1], tmpreg);
3044 break;
3045
3046 case 'k':
3047 tmpreg = get_num (&opP->disp, 55);
3048 install_operand (s[1], tmpreg & 0x7f);
3049 break;
3050
3051 case 'l':
3052 tmpreg = opP->mask;
3053 if (s[1] == 'w')
3054 {
3055 if (tmpreg & 0x7FF0000)
3056 as_bad (_("Floating point register in register list"));
3057 insop (reverse_16_bits (tmpreg), opcode);
3058 }
3059 else
3060 {
3061 if (tmpreg & 0x700FFFF)
3062 as_bad (_("Wrong register in floating-point reglist"));
3063 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3064 }
3065 break;
3066
3067 case 'L':
3068 tmpreg = opP->mask;
3069 if (s[1] == 'w')
3070 {
3071 if (tmpreg & 0x7FF0000)
3072 as_bad (_("Floating point register in register list"));
3073 insop (tmpreg, opcode);
3074 }
3075 else if (s[1] == '8')
3076 {
3077 if (tmpreg & 0x0FFFFFF)
3078 as_bad (_("incorrect register in reglist"));
3079 install_operand (s[1], tmpreg >> 24);
3080 }
3081 else
3082 {
3083 if (tmpreg & 0x700FFFF)
3084 as_bad (_("wrong register in floating-point reglist"));
3085 else
3086 install_operand (s[1], tmpreg >> 16);
3087 }
3088 break;
3089
3090 case 'M':
3091 install_operand (s[1], get_num (&opP->disp, 60));
3092 break;
3093
3094 case 'O':
3095 tmpreg = ((opP->mode == DREG)
8fce3f5e 3096 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3097 : (get_num (&opP->disp, 40) & 0x1F));
3098 install_operand (s[1], tmpreg);
3099 break;
3100
3101 case 'Q':
3102 tmpreg = get_num (&opP->disp, 10);
3103 if (tmpreg == 8)
3104 tmpreg = 0;
3105 install_operand (s[1], tmpreg);
3106 break;
3107
3108 case 'R':
3109 /* This depends on the fact that ADDR registers are eight
3110 more than their corresponding DATA regs, so the result
36759679 3111 will have the ADDR_REG bit set. */
252b5132
RH		 3112 install_operand (s[1], opP->reg - DATA);
3113 break;
3114
3115 case 'r':
3116 if (opP->mode == AINDR)
3117 install_operand (s[1], opP->reg - DATA);
3118 else
3119 install_operand (s[1], opP->index.reg - DATA);
3120 break;
3121
3122 case 's':
3123 if (opP->reg == FPI)
3124 tmpreg = 0x1;
3125 else if (opP->reg == FPS)
3126 tmpreg = 0x2;
3127 else if (opP->reg == FPC)
3128 tmpreg = 0x4;
3129 else
3130 abort ();
3131 install_operand (s[1], tmpreg);
3132 break;
3133
36759679 3134 case 'S': /* Ignore it. */
252b5132
RH		 3135 break;
3136
3137 case 'T':
3138 install_operand (s[1], get_num (&opP->disp, 30));
3139 break;
3140
36759679 3141 case 'U': /* Ignore it. */
252b5132
RH		 3142 break;
3143
3144 case 'c':
3145 switch (opP->reg)
3146 {
3147 case NC:
3148 tmpreg = 0;
3149 break;
3150 case DC:
3151 tmpreg = 1;
3152 break;
3153 case IC:
3154 tmpreg = 2;
3155 break;
3156 case BC:
3157 tmpreg = 3;
3158 break;
3159 default:
3160 as_fatal (_("failed sanity check"));
36759679 3161 } /* switch on cache token. */
252b5132
RH		 3162 install_operand (s[1], tmpreg);
3163 break;
3164#ifndef NO_68851
92774660 3165 /* JF: These are out of order, I fear. */
252b5132
RH		 3166 case 'f':
3167 switch (opP->reg)
3168 {
3169 case SFC:
3170 tmpreg = 0;
3171 break;
3172 case DFC:
3173 tmpreg = 1;
3174 break;
3175 default:
3176 abort ();
3177 }
3178 install_operand (s[1], tmpreg);
3179 break;
3180
3181 case '0':
3182 case '1':
3183 case '2':
3184 switch (opP->reg)
3185 {
3186 case TC:
3187 tmpreg = 0;
3188 break;
3189 case CAL:
3190 tmpreg = 4;
3191 break;
3192 case VAL:
3193 tmpreg = 5;
3194 break;
3195 case SCC:
3196 tmpreg = 6;
3197 break;
3198 case AC:
3199 tmpreg = 7;
3200 break;
3201 default:
3202 abort ();
3203 }
3204 install_operand (s[1], tmpreg);
3205 break;
3206
3207 case 'V':
3208 if (opP->reg == VAL)
3209 break;
3210 abort ();
3211
3212 case 'W':
3213 switch (opP->reg)
3214 {
3215 case DRP:
3216 tmpreg = 1;
3217 break;
3218 case SRP:
3219 tmpreg = 2;
3220 break;
3221 case CRP:
3222 tmpreg = 3;
3223 break;
3224 default:
3225 abort ();
3226 }
3227 install_operand (s[1], tmpreg);
3228 break;
3229
3230 case 'X':
3231 switch (opP->reg)
3232 {
3233 case BAD:
3234 case BAD + 1:
3235 case BAD + 2:
3236 case BAD + 3:
3237 case BAD + 4:
3238 case BAD + 5:
3239 case BAD + 6:
3240 case BAD + 7:
3241 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3242 break;
3243
3244 case BAC:
3245 case BAC + 1:
3246 case BAC + 2:
3247 case BAC + 3:
3248 case BAC + 4:
3249 case BAC + 5:
3250 case BAC + 6:
3251 case BAC + 7:
3252 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3253 break;
3254
3255 default:
3256 abort ();
3257 }
3258 install_operand (s[1], tmpreg);
3259 break;
3260 case 'Y':
3261 know (opP->reg == PSR);
3262 break;
3263 case 'Z':
3264 know (opP->reg == PCSR);
3265 break;
3266#endif /* m68851 */
3267 case '3':
3268 switch (opP->reg)
3269 {
3270 case TT0:
3271 tmpreg = 2;
3272 break;
3273 case TT1:
3274 tmpreg = 3;
3275 break;
3276 default:
3277 abort ();
3278 }
3279 install_operand (s[1], tmpreg);
3280 break;
3281 case 't':
3282 tmpreg = get_num (&opP->disp, 20);
3283 install_operand (s[1], tmpreg);
3284 break;
36759679 3285 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3286 if (isvar (&opP->disp))
3287 add_fix ('l', &opP->disp, 0, 0);
3e602632 3288 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3289 addword (tmpreg >> 16);
3290 addword (tmpreg & 0xFFFF);
3291 break;
6da466c7
ILT		 3292 case 'u':
3293 install_operand (s[1], opP->reg - DATA0L);
3294 opP->reg -= (DATA0L);
36759679 3295 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3296 break;
3e602632
NC		 3297 case 'x':
3298 tmpreg = get_num (&opP->disp, 80);
3299 if (tmpreg == -1)
3300 tmpreg = 0;
3301 install_operand (s[1], tmpreg);
3302 break;
252b5132
RH		 3303 default:
3304 abort ();
3305 }
3306 }
3307
3308 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3309 instruction, ready to be emitted. . . */
252b5132
RH		 3310}
3311
3312static int
31302357 3313reverse_16_bits (int in)
252b5132
RH		 3314{
3315 int out = 0;
3316 int n;
3317
3318 static int mask[16] =
3319 {
3320 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3321 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3322 };
3323 for (n = 0; n < 16; n++)
3324 {
3325 if (in & mask[n])
3326 out |= mask[15 - n];
3327 }
3328 return out;
3329} /* reverse_16_bits() */
3330
3331static int
31302357 3332reverse_8_bits (int in)
252b5132
RH		 3333{
3334 int out = 0;
3335 int n;
3336
3337 static int mask[8] =
3338 {
3339 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3340 };
3341
3342 for (n = 0; n < 8; n++)
3343 {
3344 if (in & mask[n])
3345 out |= mask[7 - n];
3346 }
3347 return out;
3348} /* reverse_8_bits() */
3349
3350/* Cause an extra frag to be generated here, inserting up to 10 bytes
3351 (that value is chosen in the frag_var call in md_assemble). TYPE
3352 is the subtype of the frag to be generated; its primary type is
3353 rs_machine_dependent.
3354
3355 The TYPE parameter is also used by md_convert_frag_1 and
3356 md_estimate_size_before_relax. The appropriate type of fixup will
3357 be emitted by md_convert_frag_1.
3358
3359 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3360static void
31302357 3361install_operand (int mode, int val)
252b5132
RH		 3362{
3363 switch (mode)
3364 {
3365 case 's':
36759679 3366 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3367 break;
3368 case 'd':
3369 the_ins.opcode[0] |= val << 9;
3370 break;
3371 case '1':
3372 the_ins.opcode[1] |= val << 12;
3373 break;
3374 case '2':
3375 the_ins.opcode[1] |= val << 6;
3376 break;
3377 case '3':
3378 the_ins.opcode[1] |= val;
3379 break;
3380 case '4':
3381 the_ins.opcode[2] |= val << 12;
3382 break;
3383 case '5':
3384 the_ins.opcode[2] |= val << 6;
3385 break;
3386 case '6':
3387 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3388 three words long! */
3389 the_ins.numo++;
3390 the_ins.opcode[2] |= val;
3391 break;
3392 case '7':
3393 the_ins.opcode[1] |= val << 7;
3394 break;
3395 case '8':
3396 the_ins.opcode[1] |= val << 10;
3397 break;
3398#ifndef NO_68851
3399 case '9':
3400 the_ins.opcode[1] |= val << 5;
3401 break;
3402#endif
3403
3404 case 't':
3405 the_ins.opcode[1] |= (val << 10) | (val << 7);
3406 break;
3407 case 'D':
3408 the_ins.opcode[1] |= (val << 12) | val;
3409 break;
3410 case 'g':
3411 the_ins.opcode[0] |= val = 0xff;
3412 break;
3413 case 'i':
3414 the_ins.opcode[0] |= val << 9;
3415 break;
3416 case 'C':
3417 the_ins.opcode[1] |= val;
3418 break;
3419 case 'j':
3420 the_ins.opcode[1] |= val;
36759679 3421 the_ins.numo++; /* What a hack. */
252b5132
RH		 3422 break;
3423 case 'k':
3424 the_ins.opcode[1] |= val << 4;
3425 break;
3426 case 'b':
3427 case 'w':
3428 case 'W':
3429 case 'l':
3430 break;
3431 case 'e':
3432 the_ins.opcode[0] |= (val << 6);
3433 break;
3434 case 'L':
3435 the_ins.opcode[1] = (val >> 16);
3436 the_ins.opcode[2] = val & 0xffff;
3437 break;
6da466c7
ILT		 3438 case 'm':
3439 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3440 the_ins.opcode[0] |= ((val & 0x7) << 9);
3441 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3442 break;
fd99574b 3443 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3444 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3445 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3446 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3447 break;
fd99574b 3448 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3449 the_ins.opcode[1] |= val << 12;
3450 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3451 break;
fd99574b 3452 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3453 the_ins.opcode[0] |= (val & 0xF);
3454 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3455 break;
fd99574b 3456 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3457 the_ins.opcode[1] |= (val & 0xF);
3458 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3459 break;
3460 case 'h':
3461 the_ins.opcode[1] |= ((val != 1) << 10);
3462 break;
fd99574b
NC		 3463 case 'F':
3464 the_ins.opcode[0] |= ((val & 0x3) << 9);
3465 break;
3466 case 'f':
3467 the_ins.opcode[0] |= ((val & 0x3) << 0);
3468 break;
be8c092b 3469 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3470 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3471 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3472 break;
be8c092b 3473 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3474 the_ins.opcode[0] |= ((val & 0x1) << 7);
3475 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3476 break;
3477 case 'I':
3478 the_ins.opcode[1] |= ((val & 0x3) << 9);
3479 break;
3480 case ']':
3481 the_ins.opcode[0] |= (val & 0x1) <<10;
3482 break;
252b5132
RH		 3483 case 'c':
3484 default:
3485 as_fatal (_("failed sanity check."));
3486 }
6b6e92f4 3487}
252b5132
RH		 3488
3489static void
31302357 3490install_gen_operand (int mode, int val)
252b5132
RH		 3491{
3492 switch (mode)
3493 {
fd99574b
NC		 3494 case '/': /* Special for mask loads for mac/msac insns with
3495 possible mask; trailing_ampersend set in bit 8. */
3496 the_ins.opcode[0] |= (val & 0x3f);
3497 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3498 break;
252b5132
RH		 3499 case 's':
3500 the_ins.opcode[0] |= val;
3501 break;
3502 case 'd':
3503 /* This is a kludge!!! */
3504 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3505 break;
3506 case 'b':
3507 case 'w':
3508 case 'l':
3509 case 'f':
3510 case 'F':
3511 case 'x':
3512 case 'p':
3513 the_ins.opcode[0] |= val;
3514 break;
36759679 3515 /* more stuff goes here. */
252b5132
RH		 3516 default:
3517 as_fatal (_("failed sanity check."));
3518 }
6b6e92f4 3519}
252b5132 3520
6b6e92f4
NC		 3521/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3522 then deal with the bitfield hack. */
252b5132
RH		 3523
3524static char *
31302357 3525crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3526{
3527 register int parens;
3528 register int c;
3529 register char *beg_str;
3530 int inquote = 0;
3531
3532 if (!str)
3533 {
3534 return str;
3535 }
3536 beg_str = str;
3537 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3538 {
3539 if (! inquote)
3540 {
3541 if (*str == '(')
3542 parens++;
3543 else if (*str == ')')
3544 {
3545 if (!parens)
36759679 3546 { /* ERROR. */
252b5132
RH		 3547 opP->error = _("Extra )");
3548 return str;
3549 }
3550 --parens;
3551 }
3552 }
3553 if (flag_mri && *str == '\'')
3554 inquote = ! inquote;
3555 }
3556 if (!*str && parens)
36759679 3557 { /* ERROR. */
252b5132
RH		 3558 opP->error = _("Missing )");
3559 return str;
3560 }
3561 c = *str;
3562 *str = '\0';
3563 if (m68k_ip_op (beg_str, opP) != 0)
3564 {
3565 *str = c;
3566 return str;
3567 }
3568 *str = c;
3569 if (c == '}')
36759679 3570 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3571 if (c)
3572 {
3573 c = *++str;
3574 if (!c)
3575 as_bad (_("Missing operand"));
3576 }
3577
3578 /* Detect MRI REG symbols and convert them to REGLSTs. */
3579 if (opP->mode == CONTROL && (int)opP->reg < 0)
3580 {
3581 opP->mode = REGLST;
3582 opP->mask = ~(int)opP->reg;
3583 opP->reg = 0;
3584 }
3585
3586 return str;
3587}
3588
3589/* This is the guts of the machine-dependent assembler. STR points to a
3590 machine dependent instruction. This function is supposed to emit
3591 the frags/bytes it assembles to.
3592 */
3593
3594static void
31302357 3595insert_reg (const char *regname, int regnum)
252b5132
RH		 3596{
3597 char buf[100];
3598 int i;
3599
3600#ifdef REGISTER_PREFIX
3601 if (!flag_reg_prefix_optional)
3602 {
3603 buf[0] = REGISTER_PREFIX;
3604 strcpy (buf + 1, regname);
3605 regname = buf;
3606 }
3607#endif
3608
3609 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3610 &zero_address_frag));
3611
3612 for (i = 0; regname[i]; i++)
3882b010 3613 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3614 buf[i] = '\0';
3615
3616 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3617 &zero_address_frag));
3618}
3619
3620struct init_entry
3621 {
3622 const char *name;
3623 int number;
3624 };
3625
3626static const struct init_entry init_table[] =
3627{
3628 { "d0", DATA0 },
3629 { "d1", DATA1 },
3630 { "d2", DATA2 },
3631 { "d3", DATA3 },
3632 { "d4", DATA4 },
3633 { "d5", DATA5 },
3634 { "d6", DATA6 },
3635 { "d7", DATA7 },
3636 { "a0", ADDR0 },
3637 { "a1", ADDR1 },
3638 { "a2", ADDR2 },
3639 { "a3", ADDR3 },
3640 { "a4", ADDR4 },
3641 { "a5", ADDR5 },
3642 { "a6", ADDR6 },
3643 { "fp", ADDR6 },
3644 { "a7", ADDR7 },
3645 { "sp", ADDR7 },
3646 { "ssp", ADDR7 },
3647 { "fp0", FP0 },
3648 { "fp1", FP1 },
3649 { "fp2", FP2 },
3650 { "fp3", FP3 },
3651 { "fp4", FP4 },
3652 { "fp5", FP5 },
3653 { "fp6", FP6 },
3654 { "fp7", FP7 },
3655 { "fpi", FPI },
3656 { "fpiar", FPI },
3657 { "fpc", FPI },
3658 { "fps", FPS },
3659 { "fpsr", FPS },
3660 { "fpc", FPC },
3661 { "fpcr", FPC },
3662 { "control", FPC },
3663 { "status", FPS },
3664 { "iaddr", FPI },
3665
3666 { "cop0", COP0 },
3667 { "cop1", COP1 },
3668 { "cop2", COP2 },
3669 { "cop3", COP3 },
3670 { "cop4", COP4 },
3671 { "cop5", COP5 },
3672 { "cop6", COP6 },
3673 { "cop7", COP7 },
3674 { "pc", PC },
3675 { "zpc", ZPC },
3676 { "sr", SR },
3677
3678 { "ccr", CCR },
3679 { "cc", CCR },
3680
6da466c7 3681 { "acc", ACC },
fd99574b
NC		 3682 { "acc0", ACC },
3683 { "acc1", ACC1 },
3684 { "acc2", ACC2 },
3685 { "acc3", ACC3 },
3686 { "accext01", ACCEXT01 },
3687 { "accext23", ACCEXT23 },
6da466c7
ILT		 3688 { "macsr", MACSR },
3689 { "mask", MASK },
3690
36759679
NC		 3691 /* Control registers. */
3692 { "sfc", SFC }, /* Source Function Code. */
252b5132 3693 { "sfcr", SFC },
36759679 3694 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3695 { "dfcr", DFC },
36759679
NC		 3696 { "cacr", CACR }, /* Cache Control Register. */
3697 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3698
36759679
NC		 3699 { "usp", USP }, /* User Stack Pointer. */
3700 { "vbr", VBR }, /* Vector Base Register. */
3701 { "msp", MSP }, /* Master Stack Pointer. */
3702 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3703
36759679
NC		 3704 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3705 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3706 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3707 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3708
3709 /* 68ec040 versions of same */
36759679
NC		 3710 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3711 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3712 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3713 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3714
3715 /* mcf5200 versions of same. The ColdFire programmer's reference
3716 manual indicated that the order is 2,3,0,1, but Ken Rose
3717 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3718 { "acr0", ACR0 }, /* Access Control Unit 0. */
3719 { "acr1", ACR1 }, /* Access Control Unit 1. */
3720 { "acr2", ACR2 }, /* Access Control Unit 2. */
3721 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3722
36759679 3723 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3724 { "tcr", TC },
3725
36759679
NC		 3726 { "mmusr", MMUSR }, /* MMU Status Register. */
3727 { "srp", SRP }, /* User Root Pointer. */
3728 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3729
3730 { "buscr", BUSCR },
3731 { "pcr", PCR },
3732
36759679
NC		 3733 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3734 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3735 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3736 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3737
3738 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3739 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3740 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3741 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3742 { "mpcr", MPCR }, /* mcfv4e registers. */
3743 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3744 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3745 { "asid", TC }, /* mcfv4e registers. */
3746 { "mmubar", BUSCR }, /* mcfv4e registers. */
3747 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3748 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3749 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3750 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3751 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3752 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3753 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3754 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3755 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3756 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3757 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3758 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3759
3760 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3761 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3762
3763 { "mbar2", MBAR2 }, /* mcf5249 registers. */
36759679 3764 /* End of control registers. */
252b5132
RH		 3765
3766 { "ac", AC },
3767 { "bc", BC },
3768 { "cal", CAL },
3769 { "crp", CRP },
3770 { "drp", DRP },
3771 { "pcsr", PCSR },
3772 { "psr", PSR },
3773 { "scc", SCC },
3774 { "val", VAL },
3775 { "bad0", BAD0 },
3776 { "bad1", BAD1 },
3777 { "bad2", BAD2 },
3778 { "bad3", BAD3 },
3779 { "bad4", BAD4 },
3780 { "bad5", BAD5 },
3781 { "bad6", BAD6 },
3782 { "bad7", BAD7 },
3783 { "bac0", BAC0 },
3784 { "bac1", BAC1 },
3785 { "bac2", BAC2 },
3786 { "bac3", BAC3 },
3787 { "bac4", BAC4 },
3788 { "bac5", BAC5 },
3789 { "bac6", BAC6 },
3790 { "bac7", BAC7 },
3791
3792 { "ic", IC },
3793 { "dc", DC },
3794 { "nc", NC },
3795
3796 { "tt0", TT0 },
3797 { "tt1", TT1 },
36759679 3798 /* 68ec030 versions of same. */
252b5132
RH		 3799 { "ac0", TT0 },
3800 { "ac1", TT1 },
36759679 3801 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3802 { "acusr", PSR },
3803
3804 /* Suppressed data and address registers. */
3805 { "zd0", ZDATA0 },
3806 { "zd1", ZDATA1 },
3807 { "zd2", ZDATA2 },
3808 { "zd3", ZDATA3 },
3809 { "zd4", ZDATA4 },
3810 { "zd5", ZDATA5 },
3811 { "zd6", ZDATA6 },
3812 { "zd7", ZDATA7 },
3813 { "za0", ZADDR0 },
3814 { "za1", ZADDR1 },
3815 { "za2", ZADDR2 },
3816 { "za3", ZADDR3 },
3817 { "za4", ZADDR4 },
3818 { "za5", ZADDR5 },
3819 { "za6", ZADDR6 },
3820 { "za7", ZADDR7 },
3821
92774660 3822 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3823 { "d0l", DATA0L },
3824 { "d1l", DATA1L },
3825 { "d2l", DATA2L },
3826 { "d3l", DATA3L },
3827 { "d4l", DATA4L },
3828 { "d5l", DATA5L },
3829 { "d6l", DATA6L },
3830 { "d7l", DATA7L },
3831
3832 { "a0l", ADDR0L },
3833 { "a1l", ADDR1L },
3834 { "a2l", ADDR2L },
3835 { "a3l", ADDR3L },
3836 { "a4l", ADDR4L },
3837 { "a5l", ADDR5L },
3838 { "a6l", ADDR6L },
3839 { "a7l", ADDR7L },
3840
3841 { "d0u", DATA0U },
3842 { "d1u", DATA1U },
3843 { "d2u", DATA2U },
3844 { "d3u", DATA3U },
3845 { "d4u", DATA4U },
3846 { "d5u", DATA5U },
3847 { "d6u", DATA6U },
3848 { "d7u", DATA7U },
3849
3850 { "a0u", ADDR0U },
3851 { "a1u", ADDR1U },
3852 { "a2u", ADDR2U },
3853 { "a3u", ADDR3U },
3854 { "a4u", ADDR4U },
3855 { "a5u", ADDR5U },
3856 { "a6u", ADDR6U },
3857 { "a7u", ADDR7U },
3858
252b5132
RH		 3859 { 0, 0 }
3860};
3861
3862static void
31302357 3863init_regtable (void)
252b5132
RH		 3864{
3865 int i;
3866 for (i = 0; init_table[i].name; i++)
3867 insert_reg (init_table[i].name, init_table[i].number);
3868}
3869
3870static int no_68851, no_68881;
3871
3872#ifdef OBJ_AOUT
3873/* a.out machine type. Default to 68020. */
3874int m68k_aout_machtype = 2;
3875#endif
3876
3877void
31302357 3878md_assemble (char *str)
252b5132
RH		 3879{
3880 const char *er;
3881 short *fromP;
3882 char *toP = NULL;
3883 int m, n = 0;
3884 char *to_beg_P;
3885 int shorts_this_frag;
3886 fixS *fixP;
3887
3888 /* In MRI mode, the instruction and operands are separated by a
3889 space. Anything following the operands is a comment. The label
3890 has already been removed. */
3891 if (flag_mri)
3892 {
3893 char *s;
3894 int fields = 0;
3895 int infield = 0;
3896 int inquote = 0;
3897
3898 for (s = str; *s != '\0'; s++)
3899 {
3900 if ((*s == ' ' || *s == '\t') && ! inquote)
3901 {
3902 if (infield)
3903 {
3904 ++fields;
3905 if (fields >= 2)
3906 {
3907 *s = '\0';
3908 break;
3909 }
3910 infield = 0;
3911 }
3912 }
3913 else
3914 {
3915 if (! infield)
3916 infield = 1;
3917 if (*s == '\'')
3918 inquote = ! inquote;
3919 }
3920 }
3921 }
3922
31302357 3923 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 3924 m68k_ip (str);
3925 er = the_ins.error;
3926 if (!er)
3927 {
3928 for (n = 0; n < the_ins.numargs; n++)
3929 if (the_ins.operands[n].error)
3930 {
3931 er = the_ins.operands[n].error;
3932 break;
3933 }
3934 }
3935 if (er)
3936 {
3937 as_bad (_("%s -- statement `%s' ignored"), er, str);
3938 return;
3939 }
3940
3941 /* If there is a current label, record that it marks an instruction. */
3942 if (current_label != NULL)
3943 {
3944 current_label->text = 1;
3945 current_label = NULL;
3946 }
3947
f27a3839
AS		 3948#ifdef OBJ_ELF
3949 /* Tie dwarf2 debug info to the address at the start of the insn. */
3950 dwarf2_emit_insn (0);
3951#endif
3952
252b5132
RH		 3953 if (the_ins.nfrag == 0)
3954 {
36759679 3955 /* No frag hacking involved; just put it out. */
252b5132
RH		 3956 toP = frag_more (2 * the_ins.numo);
3957 fromP = &the_ins.opcode[0];
3958 for (m = the_ins.numo; m; --m)
3959 {
3960 md_number_to_chars (toP, (long) (*fromP), 2);
3961 toP += 2;
3962 fromP++;
3963 }
36759679 3964 /* Put out symbol-dependent info. */
252b5132
RH		 3965 for (m = 0; m < the_ins.nrel; m++)
3966 {
3967 switch (the_ins.reloc[m].wid)
3968 {
3969 case 'B':
3970 n = 1;
3971 break;
3972 case 'b':
3973 n = 1;
3974 break;
3975 case '3':
3976 n = 1;
3977 break;
3978 case 'w':
3979 case 'W':
3980 n = 2;
3981 break;
3982 case 'l':
3983 n = 4;
3984 break;
3985 default:
3986 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3987 the_ins.reloc[m].wid);
3988 }
3989
3990 fixP = fix_new_exp (frag_now,
3991 ((toP - frag_now->fr_literal)
3992 - the_ins.numo * 2 + the_ins.reloc[m].n),
3993 n,
3994 &the_ins.reloc[m].exp,
3995 the_ins.reloc[m].pcrel,
3996 get_reloc_code (n, the_ins.reloc[m].pcrel,
3997 the_ins.reloc[m].pic_reloc));
3998 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3999 if (the_ins.reloc[m].wid == 'B')
4000 fixP->fx_signed = 1;
4001 }
4002 return;
4003 }
4004
36759679 4005 /* There's some frag hacking. */
fbe572f9
AM		 4006 {
4007 /* Calculate the max frag size. */
4008 int wid;
4009
4010 wid = 2 * the_ins.fragb[0].fragoff;
4011 for (n = 1; n < the_ins.nfrag; n++)
4012 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4013 /* frag_var part. */
4014 wid += 10;
4015 /* Make sure the whole insn fits in one chunk, in particular that
4016 the var part is attached, as we access one byte before the
4017 variable frag for byte branches. */
4018 frag_grow (wid);
4019 }
4020
252b5132
RH		 4021 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4022 {
4023 int wid;
4024
4025 if (n == 0)
4026 wid = 2 * the_ins.fragb[n].fragoff;
4027 else
4028 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4029 toP = frag_more (wid);
4030 to_beg_P = toP;
4031 shorts_this_frag = 0;
4032 for (m = wid / 2; m; --m)
4033 {
4034 md_number_to_chars (toP, (long) (*fromP), 2);
4035 toP += 2;
4036 fromP++;
4037 shorts_this_frag++;
4038 }
4039 for (m = 0; m < the_ins.nrel; m++)
4040 {
4041 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4042 {
4043 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4044 break;
4045 }
4046 wid = the_ins.reloc[m].wid;
4047 if (wid == 0)
4048 continue;
4049 the_ins.reloc[m].wid = 0;
4050 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4051
4052 fixP = fix_new_exp (frag_now,
4053 ((toP - frag_now->fr_literal)
4054 - the_ins.numo * 2 + the_ins.reloc[m].n),
4055 wid,
4056 &the_ins.reloc[m].exp,
4057 the_ins.reloc[m].pcrel,
4058 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4059 the_ins.reloc[m].pic_reloc));
4060 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4061 }
4062 (void) frag_var (rs_machine_dependent, 10, 0,
4063 (relax_substateT) (the_ins.fragb[n].fragty),
4064 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4065 }
4066 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4067 shorts_this_frag = 0;
4068 if (n)
4069 {
055d1eb0 4070 toP = frag_more (n * 2);
252b5132
RH		 4071 while (n--)
4072 {
4073 md_number_to_chars (toP, (long) (*fromP), 2);
4074 toP += 2;
4075 fromP++;
4076 shorts_this_frag++;
4077 }
4078 }
4079 for (m = 0; m < the_ins.nrel; m++)
4080 {
4081 int wid;
4082
4083 wid = the_ins.reloc[m].wid;
4084 if (wid == 0)
4085 continue;
4086 the_ins.reloc[m].wid = 0;
4087 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4088
4089 fixP = fix_new_exp (frag_now,
4090 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4091 - shorts_this_frag * 2),
4092 wid,
4093 &the_ins.reloc[m].exp,
4094 the_ins.reloc[m].pcrel,
4095 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4096 the_ins.reloc[m].pic_reloc));
4097 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4098 }
4099}
4100
60fed2d3
NC		 4101/* Comparison function used by qsort to rank the opcode entries by name. */
4102
4103static int
4104m68k_compare_opcode (const void * v1, const void * v2)
4105{
4106 struct m68k_opcode * op1, * op2;
4107 int ret;
4108
4109 op1 = *(struct m68k_opcode **) v1;
4110 op2 = *(struct m68k_opcode **) v2;
4111
4112 /* Compare the two names. If different, return the comparison.
4113 If the same, return the order they are in the opcode table. */
4114 ret = strcmp (op1->name, op2->name);
4115 if (ret)
4116 return ret;
4117 if (op1 < op2)
4118 return -1;
4119 return 0;
4120}
4121
252b5132 4122void
60fed2d3 4123md_begin (void)
252b5132 4124{
60fed2d3
NC		 4125 const struct m68k_opcode *ins;
4126 struct m68k_incant *hack, *slak;
4127 const char *retval = 0; /* Empty string, or error msg text. */
4128 int i;
4129
4130 /* Set up hash tables with 68000 instructions.
4131 similar to what the vax assembler does. */
252b5132
RH		 4132 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4133 a copy of it at runtime, adding in the information we want but isn't
4134 there. I think it'd be better to have an awk script hack the table
4135 at compile time. Or even just xstr the table and use it as-is. But
4136 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4137 names. */
4138
252b5132
RH		 4139 if (flag_mri)
4140 {
4141 flag_reg_prefix_optional = 1;
4142 m68k_abspcadd = 1;
4143 if (! m68k_rel32_from_cmdline)
4144 m68k_rel32 = 0;
4145 }
4146
60fed2d3
NC		 4147 /* First sort the opcode table into alphabetical order to seperate
4148 the order that the assembler wants to see the opcodes from the
4149 order that the disassembler wants to see them. */
4150 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4151 if (!m68k_sorted_opcodes)
4152 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4153 m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4154
4155 for (i = m68k_numopcodes; i--;)
4156 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4157
4158 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4159 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4160
252b5132
RH		 4161 op_hash = hash_new ();
4162
4163 obstack_begin (&robyn, 4000);
4164 for (i = 0; i < m68k_numopcodes; i++)
4165 {
4166 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4167 do
4168 {
60fed2d3
NC		 4169 ins = m68k_sorted_opcodes[i];
4170
4171 /* We *could* ignore insns that don't match our
4172 arch here by just leaving them out of the hash. */
252b5132
RH		 4173 slak->m_operands = ins->args;
4174 slak->m_opnum = strlen (slak->m_operands) / 2;
4175 slak->m_arch = ins->arch;
4176 slak->m_opcode = ins->opcode;
36759679 4177 /* This is kludgey. */
252b5132
RH		 4178 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4179 if (i + 1 != m68k_numopcodes
60fed2d3 4180 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4181 {
60fed2d3 4182 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4183 i++;
4184 }
4185 else
4186 slak->m_next = 0;
4187 slak = slak->m_next;
4188 }
4189 while (slak);
4190
4191 retval = hash_insert (op_hash, ins->name, (char *) hack);
4192 if (retval)
4193 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4194 }
4195
4196 for (i = 0; i < m68k_numaliases; i++)
4197 {
4198 const char *name = m68k_opcode_aliases[i].primary;
4199 const char *alias = m68k_opcode_aliases[i].alias;
4200 PTR val = hash_find (op_hash, name);
60fed2d3 4201
252b5132
RH		 4202 if (!val)
4203 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4204 retval = hash_insert (op_hash, alias, val);
4205 if (retval)
4206 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4207 }
4208
4209 /* In MRI mode, all unsized branches are variable sized. Normally,
4210 they are word sized. */
4211 if (flag_mri)
4212 {
4213 static struct m68k_opcode_alias mri_aliases[] =
4214 {
4215 { "bhi", "jhi", },
4216 { "bls", "jls", },
4217 { "bcc", "jcc", },
4218 { "bcs", "jcs", },
4219 { "bne", "jne", },
4220 { "beq", "jeq", },
4221 { "bvc", "jvc", },
4222 { "bvs", "jvs", },
4223 { "bpl", "jpl", },
4224 { "bmi", "jmi", },
4225 { "bge", "jge", },
4226 { "blt", "jlt", },
4227 { "bgt", "jgt", },
4228 { "ble", "jle", },
4229 { "bra", "jra", },
4230 { "bsr", "jbsr", },
4231 };
4232
8fce3f5e
AM		 4233 for (i = 0;
4234 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4235 i++)
252b5132
RH		 4236 {
4237 const char *name = mri_aliases[i].primary;
4238 const char *alias = mri_aliases[i].alias;
4239 PTR val = hash_find (op_hash, name);
60fed2d3 4240
252b5132
RH		 4241 if (!val)
4242 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4243 retval = hash_jam (op_hash, alias, val);
4244 if (retval)
4245 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4246 }
4247 }
4248
8fce3f5e 4249 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4250 {
4251 notend_table[i] = 0;
4252 alt_notend_table[i] = 0;
4253 }
60fed2d3 4254
252b5132
RH		 4255 notend_table[','] = 1;
4256 notend_table['{'] = 1;
4257 notend_table['}'] = 1;
4258 alt_notend_table['a'] = 1;
4259 alt_notend_table['A'] = 1;
4260 alt_notend_table['d'] = 1;
4261 alt_notend_table['D'] = 1;
4262 alt_notend_table['#'] = 1;
4263 alt_notend_table['&'] = 1;
4264 alt_notend_table['f'] = 1;
4265 alt_notend_table['F'] = 1;
4266#ifdef REGISTER_PREFIX
4267 alt_notend_table[REGISTER_PREFIX] = 1;
4268#endif
4269
4270 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4271 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4272 alt_notend_table['('] = 1;
4273
4274 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4275 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4276 alt_notend_table['@'] = 1;
4277
4278 /* We need to put digits in alt_notend_table to handle
60fed2d3 4279 bfextu %d0{24:1},%d0 */
252b5132
RH		 4280 alt_notend_table['0'] = 1;
4281 alt_notend_table['1'] = 1;
4282 alt_notend_table['2'] = 1;
4283 alt_notend_table['3'] = 1;
4284 alt_notend_table['4'] = 1;
4285 alt_notend_table['5'] = 1;
4286 alt_notend_table['6'] = 1;
4287 alt_notend_table['7'] = 1;
4288 alt_notend_table['8'] = 1;
4289 alt_notend_table['9'] = 1;
4290
4291#ifndef MIT_SYNTAX_ONLY
4292 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4293 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4294 {
4295 int n = 0;
60fed2d3 4296
252b5132
RH		 4297 while (mote_pseudo_table[n].poc_name)
4298 {
60fed2d3 4299 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4300 hash_insert (op_hash,
4301 mote_pseudo_table[n].poc_name, (char *) hack);
4302 hack->m_operands = 0;
4303 hack->m_opnum = n;
4304 n++;
4305 }
4306 }
4307#endif
4308
4309 init_regtable ();
4310
4311#ifdef OBJ_ELF
4312 record_alignment (text_section, 2);
4313 record_alignment (data_section, 2);
4314 record_alignment (bss_section, 2);
4315#endif
4316}
4317
4318static void
31302357 4319select_control_regs (void)
252b5132
RH		 4320{
4321 /* Note which set of "movec" control registers is available. */
6b6e92f4 4322 switch (current_chip)
252b5132 4323 {
4f2a7c9e 4324 case 0:
6b6e92f4
NC		 4325 if (verbose)
4326 as_warn (_("architecture not yet selected: defaulting to 68020"));
4f2a7c9e
NC		 4327 control_regs = m68020_control_regs;
4328 break;
4329
252b5132
RH		 4330 case m68000:
4331 control_regs = m68000_control_regs;
4332 break;
4333 case m68010:
4334 control_regs = m68010_control_regs;
4335 break;
4336 case m68020:
4337 case m68030:
4338 control_regs = m68020_control_regs;
4339 break;
4340 case m68040:
4341 control_regs = m68040_control_regs;
4342 break;
4343 case m68060:
4344 control_regs = m68060_control_regs;
4345 break;
4346 case cpu32:
4347 control_regs = cpu32_control_regs;
4348 break;
4349 case mcf5200:
6da466c7
ILT		 4350 case mcf5206e:
4351 case mcf5307:
dc84e067 4352 case mcf5407:
6da466c7 4353 control_regs = mcf_control_regs;
252b5132 4354 break;
e80e0390
NC		 4355 case mcf5249:
4356 control_regs = mcf5249_control_regs;
4357 break;
3e602632 4358 case mcf528x:
6b6e92f4 4359 case mcf521x:
3e602632
NC		 4360 control_regs = mcf528x_control_regs;
4361 break;
6b6e92f4
NC		 4362 case mcf5470:
4363 case mcf5480:
3e602632
NC		 4364 control_regs = mcfv4e_control_regs;
4365 break;
252b5132
RH		 4366 default:
4367 abort ();
4368 }
4369}
4370
4371void
31302357 4372m68k_init_after_args (void)
252b5132
RH		 4373{
4374 if (cpu_of_arch (current_architecture) == 0)
4375 {
4376 int i;
4377 const char *default_cpu = TARGET_CPU;
4378
4379 if (*default_cpu == 'm')
4380 default_cpu++;
4381 for (i = 0; i < n_archs; i++)
4382 if (strcasecmp (default_cpu, archs[i].name) == 0)
4383 break;
4384 if (i == n_archs)
4385 {
4386 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4387 current_architecture |= m68020;
4388 }
4389 else
4390 current_architecture |= archs[i].arch;
4391 }
4392 /* Permit m68881 specification with all cpus; those that can't work
4393 with a coprocessor could be doing emulation. */
4394 if (current_architecture & m68851)
4395 {
4396 if (current_architecture & m68040)
60fed2d3 4397 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
252b5132
RH		 4398 }
4399 /* What other incompatibilities could we check for? */
4400
4401 /* Toss in some default assumptions about coprocessors. */
4402 if (!no_68881
4403 && (cpu_of_arch (current_architecture)
4404 /* Can CPU32 have a 68881 coprocessor?? */
4405 & (m68020 | m68030 | cpu32)))
60fed2d3
NC		 4406 current_architecture |= m68881;
4407
252b5132
RH		 4408 if (!no_68851
4409 && (cpu_of_arch (current_architecture) & m68020up) != 0
4410 && (cpu_of_arch (current_architecture) & m68040up) == 0)
60fed2d3
NC		 4411 current_architecture |= m68851;
4412
252b5132
RH		 4413 if (no_68881 && (current_architecture & m68881))
4414 as_bad (_("options for 68881 and no-68881 both given"));
60fed2d3 4415
252b5132
RH		 4416 if (no_68851 && (current_architecture & m68851))
4417 as_bad (_("options for 68851 and no-68851 both given"));
4418
4419#ifdef OBJ_AOUT
4420 /* Work out the magic number. This isn't very general. */
4421 if (current_architecture & m68000)
4422 m68k_aout_machtype = 0;
4423 else if (current_architecture & m68010)
4424 m68k_aout_machtype = 1;
4425 else if (current_architecture & m68020)
4426 m68k_aout_machtype = 2;
4427 else
4428 m68k_aout_machtype = 2;
4429#endif
4430
4431 /* Note which set of "movec" control registers is available. */
4432 select_control_regs ();
4433
4434 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4435 || arch_coldfire_p (current_architecture))
252b5132
RH		 4436 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4437}
4438\f
4439/* This is called when a label is defined. */
4440
4441void
31302357 4442m68k_frob_label (symbolS *sym)
252b5132
RH		 4443{
4444 struct label_line *n;
4445
4446 n = (struct label_line *) xmalloc (sizeof *n);
4447 n->next = labels;
4448 n->label = sym;
4449 as_where (&n->file, &n->line);
4450 n->text = 0;
4451 labels = n;
4452 current_label = n;
4453}
4454
4455/* This is called when a value that is not an instruction is emitted. */
4456
4457void
31302357 4458m68k_flush_pending_output (void)
252b5132
RH		 4459{
4460 current_label = NULL;
4461}
4462
4463/* This is called at the end of the assembly, when the final value of
4464 the label is known. We warn if this is a text symbol aligned at an
4465 odd location. */
4466
4467void
31302357 4468m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4469{
4470 if (S_GET_SEGMENT (sym) == reg_section
4471 && (int) S_GET_VALUE (sym) < 0)
4472 {
4473 S_SET_SEGMENT (sym, absolute_section);
4474 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4475 }
4476 else if ((S_GET_VALUE (sym) & 1) != 0)
4477 {
4478 struct label_line *l;
4479
4480 for (l = labels; l != NULL; l = l->next)
4481 {
4482 if (l->label == sym)
4483 {
4484 if (l->text)
4485 as_warn_where (l->file, l->line,
4486 _("text label `%s' aligned to odd boundary"),
4487 S_GET_NAME (sym));
4488 break;
4489 }
4490 }
4491 }
4492}
4493\f
4494/* This is called if we go in or out of MRI mode because of the .mri
4495 pseudo-op. */
4496
4497void
31302357 4498m68k_mri_mode_change (int on)
252b5132
RH		 4499{
4500 if (on)
4501 {
4502 if (! flag_reg_prefix_optional)
4503 {
4504 flag_reg_prefix_optional = 1;
4505#ifdef REGISTER_PREFIX
4506 init_regtable ();
4507#endif
4508 }
4509 m68k_abspcadd = 1;
4510 if (! m68k_rel32_from_cmdline)
4511 m68k_rel32 = 0;
4512 }
4513 else
4514 {
4515 if (! reg_prefix_optional_seen)
4516 {
4517#ifdef REGISTER_PREFIX_OPTIONAL
4518 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4519#else
4520 flag_reg_prefix_optional = 0;
4521#endif
4522#ifdef REGISTER_PREFIX
4523 init_regtable ();
4524#endif
4525 }
4526 m68k_abspcadd = 0;
4527 if (! m68k_rel32_from_cmdline)
4528 m68k_rel32 = 1;
4529 }
4530}
4531
36759679 4532/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4533#define MAX_LITTLENUMS 6
4534
4535/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4536 of type TYPE, and store the appropriate bytes in *LITP. The number
4537 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4538 returned, or NULL on OK. */
4539
4540char *
31302357 4541md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4542{
4543 int prec;
4544 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4545 LITTLENUM_TYPE *wordP;
4546 char *t;
4547
4548 switch (type)
4549 {
4550 case 'f':
4551 case 'F':
4552 case 's':
4553 case 'S':
4554 prec = 2;
4555 break;
4556
4557 case 'd':
4558 case 'D':
4559 case 'r':
4560 case 'R':
4561 prec = 4;
4562 break;
4563
4564 case 'x':
4565 case 'X':
4566 prec = 6;
4567 break;
4568
4569 case 'p':
4570 case 'P':
4571 prec = 6;
4572 break;
4573
4574 default:
4575 *sizeP = 0;
4576 return _("Bad call to MD_ATOF()");
4577 }
4578 t = atof_ieee (input_line_pointer, type, words);
4579 if (t)
4580 input_line_pointer = t;
4581
4582 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4583 for (wordP = words; prec--;)
4584 {
4585 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4586 litP += sizeof (LITTLENUM_TYPE);
4587 }
4588 return 0;
4589}
4590
4591void
31302357 4592md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4593{
4594 number_to_chars_bigendian (buf, val, n);
4595}
4596
94f592af 4597void
31302357 4598md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4599{
bbe8ef22 4600 offsetT val = *valP;
252b5132
RH		 4601 addressT upper_limit;
4602 offsetT lower_limit;
4603
4604 /* This is unnecessary but it convinces the native rs6000 compiler
4605 to generate the code we want. */
4606 char *buf = fixP->fx_frag->fr_literal;
4607 buf += fixP->fx_where;
36759679 4608 /* End ibm compiler workaround. */
252b5132 4609
c801568a 4610 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132 4611
94f592af
NC		 4612 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4613 fixP->fx_done = 1;
4614
252b5132
RH		 4615#ifdef OBJ_ELF
4616 if (fixP->fx_addsy)
4617 {
4618 memset (buf, 0, fixP->fx_size);
36759679 4619 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4620
4621 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4622 && !S_IS_DEFINED (fixP->fx_addsy)
4623 && !S_IS_WEAK (fixP->fx_addsy))
4624 S_SET_WEAK (fixP->fx_addsy);
4625 return;
4626 }
4627#endif
4628
4629#ifdef BFD_ASSEMBLER
4630 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4631 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4632 return;
4633#endif
4634
4635 switch (fixP->fx_size)
4636 {
94f592af
NC		 4637 /* The cast to offsetT below are necessary to make code
4638 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4639 case 1:
4640 *buf++ = val;
4641 upper_limit = 0x7f;
4642 lower_limit = - (offsetT) 0x80;
4643 break;
4644 case 2:
4645 *buf++ = (val >> 8);
4646 *buf++ = val;
4647 upper_limit = 0x7fff;
4648 lower_limit = - (offsetT) 0x8000;
4649 break;
4650 case 4:
4651 *buf++ = (val >> 24);
4652 *buf++ = (val >> 16);
4653 *buf++ = (val >> 8);
4654 *buf++ = val;
4655 upper_limit = 0x7fffffff;
36759679 4656 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4657 break;
4658 default:
4659 BAD_CASE (fixP->fx_size);
4660 }
4661
4662 /* Fix up a negative reloc. */
4663 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4664 {
4665 fixP->fx_addsy = fixP->fx_subsy;
4666 fixP->fx_subsy = NULL;
4667 fixP->fx_tcbit = 1;
4668 }
4669
4670 /* For non-pc-relative values, it's conceivable we might get something
4671 like "0xff" for a byte field. So extend the upper part of the range
4672 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4673 so that we can do any range checking at all. */
4674 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4675 upper_limit = upper_limit * 2 + 1;
4676
4677 if ((addressT) val > upper_limit
4678 && (val > 0 || val < lower_limit))
4679 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4680
4681 /* A one byte PC-relative reloc means a short branch. We can't use
4682 a short branch with a value of 0 or -1, because those indicate
4683 different opcodes (branches with longer offsets). fixup_segment
4684 in write.c may have clobbered fx_pcrel, so we need to examine the
4685 reloc type. */
4686 if ((fixP->fx_pcrel
4687#ifdef BFD_ASSEMBLER
4688 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4689#endif
4690 )
4691 && fixP->fx_size == 1
4692 && (fixP->fx_addsy == NULL
4693 || S_IS_DEFINED (fixP->fx_addsy))
4694 && (val == 0 || val == -1))
4695 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4696}
4697
252b5132
RH		 4698/* *fragP has been relaxed to its final size, and now needs to have
4699 the bytes inside it modified to conform to the new size There is UGLY
4700 MAGIC here. ..
4701 */
4702static void
31302357 4703md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4704{
4705 long disp;
252b5132
RH		 4706 fixS *fixP;
4707
4708 /* Address in object code of the displacement. */
4709 register int object_address = fragP->fr_fix + fragP->fr_address;
4710
4711 /* Address in gas core of the place to store the displacement. */
4712 /* This convinces the native rs6000 compiler to generate the code we
92774660 4713 want. */
252b5132
RH		 4714 register char *buffer_address = fragP->fr_literal;
4715 buffer_address += fragP->fr_fix;
36759679 4716 /* End ibm compiler workaround. */
252b5132
RH		 4717
4718 /* The displacement of the address, from current location. */
4719 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4720 disp = (disp + fragP->fr_offset) - object_address;
4721
252b5132
RH		 4722 switch (fragP->fr_subtype)
4723 {
151337e8
NC		 4724 case TAB (BRANCHBWL, BYTE):
4725 case TAB (BRABSJUNC, BYTE):
4726 case TAB (BRABSJCOND, BYTE):
4727 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4728 know (issbyte (disp));
4729 if (disp == 0)
b091f402
AM		 4730 as_bad_where (fragP->fr_file, fragP->fr_line,
4731 _("short branch with zero offset: use :w"));
151337e8 4732 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4733 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4734 fixP->fx_pcrel_adjust = -1;
252b5132 4735 break;
151337e8
NC		 4736 case TAB (BRANCHBWL, SHORT):
4737 case TAB (BRABSJUNC, SHORT):
4738 case TAB (BRABSJCOND, SHORT):
4739 case TAB (BRANCHBW, SHORT):
252b5132 4740 fragP->fr_opcode[1] = 0x00;
151337e8 4741 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4742 1, RELAX_RELOC_PC16);
151337e8
NC		 4743 fragP->fr_fix += 2;
4744 break;
4745 case TAB (BRANCHBWL, LONG):
4746 fragP->fr_opcode[1] = (char) 0xFF;
4747 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4748 1, RELAX_RELOC_PC32);
151337e8 4749 fragP->fr_fix += 4;
252b5132 4750 break;
151337e8
NC		 4751 case TAB (BRABSJUNC, LONG):
4752 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4753 {
36759679 4754 if (flag_keep_pcrel)
6b6e92f4 4755 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4756 fragP->fr_opcode[0] = 0x4E;
36759679 4757 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4758 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4759 0, RELAX_RELOC_ABS32);
151337e8
NC		 4760 fragP->fr_fix += 4;
4761 }
4762 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4763 {
36759679 4764 if (flag_keep_pcrel)
6b6e92f4 4765 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4766 fragP->fr_opcode[0] = 0x4E;
36759679 4767 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4768 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4769 0, RELAX_RELOC_ABS32);
151337e8 4770 fragP->fr_fix += 4;
252b5132
RH		 4771 }
4772 else
4773 {
151337e8
NC		 4774 /* This cannot happen, because jbsr and jbra are the only two
4775 unconditional branches. */
4776 abort ();
252b5132
RH		 4777 }
4778 break;
151337e8 4779 case TAB (BRABSJCOND, LONG):
36759679 4780 if (flag_keep_pcrel)
6b6e92f4 4781 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4782
36759679
NC		 4783 /* Only Bcc 68000 instructions can come here
4784 Change bcc into b!cc/jmp absl long. */
4785 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4786 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4787
4788 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4789 different frag, in which case referring to them is a no-no.
92774660 4790 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4791 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4792 *buffer_address++ = (char) 0xf9;
36759679 4793 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4794 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4795 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4796 fragP->fr_fix += 4;
4797 break;
4798 case TAB (FBRANCH, SHORT):
4799 know ((fragP->fr_opcode[1] & 0x40) == 0);
4800 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4801 1, RELAX_RELOC_PC16);
151337e8
NC		 4802 fragP->fr_fix += 2;
4803 break;
4804 case TAB (FBRANCH, LONG):
36759679 4805 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4806 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4807 1, RELAX_RELOC_PC32);
252b5132 4808 fragP->fr_fix += 4;
252b5132 4809 break;
151337e8
NC		 4810 case TAB (DBCCLBR, SHORT):
4811 case TAB (DBCCABSJ, SHORT):
4812 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4813 1, RELAX_RELOC_PC16);
151337e8
NC		 4814 fragP->fr_fix += 2;
4815 break;
4816 case TAB (DBCCLBR, LONG):
36759679
NC		 4817 /* Only DBcc instructions can come here.
4818 Change dbcc into dbcc/bral.
4819 JF: these used to be fr_opcode[2-7], but that's wrong. */
4820 if (flag_keep_pcrel)
6b6e92f4 4821 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4822
36759679 4823 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4824 *buffer_address++ = 0x04;
36759679 4825 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4826 *buffer_address++ = 0x06;
151337e8
NC		 4827 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4828 *buffer_address++ = (char) 0xff;
252b5132 4829
36759679 4830 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4831 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4832 RELAX_RELOC_PC32);
252b5132 4833 fragP->fr_fix += 4;
252b5132 4834 break;
151337e8 4835 case TAB (DBCCABSJ, LONG):
36759679
NC		 4836 /* Only DBcc instructions can come here.
4837 Change dbcc into dbcc/jmp.
4838 JF: these used to be fr_opcode[2-7], but that's wrong. */
4839 if (flag_keep_pcrel)
6b6e92f4 4840 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4841
36759679 4842 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4843 *buffer_address++ = 0x04;
36759679 4844 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4845 *buffer_address++ = 0x06;
36759679 4846 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4847 *buffer_address++ = (char) 0xf9;
4848
36759679 4849 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4850 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4851 RELAX_RELOC_ABS32);
252b5132 4852 fragP->fr_fix += 4;
252b5132 4853 break;
151337e8 4854 case TAB (PCREL1632, SHORT):
252b5132
RH		 4855 fragP->fr_opcode[1] &= ~0x3F;
4856 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4857 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4858 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4859 fragP->fr_fix += 2;
252b5132 4860 break;
151337e8 4861 case TAB (PCREL1632, LONG):
252b5132
RH		 4862 /* Already set to mode 7.3; this indicates: PC indirect with
4863 suppressed index, 32-bit displacement. */
4864 *buffer_address++ = 0x01;
4865 *buffer_address++ = 0x70;
4866 fragP->fr_fix += 2;
151337e8 4867 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4868 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4869 fixP->fx_pcrel_adjust = 2;
4870 fragP->fr_fix += 4;
252b5132 4871 break;
252b5132 4872 case TAB (PCINDEX, BYTE):
252b5132
RH		 4873 assert (fragP->fr_fix >= 2);
4874 buffer_address[-2] &= ~1;
151337e8 4875 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4876 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4877 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4878 break;
4879 case TAB (PCINDEX, SHORT):
252b5132
RH		 4880 assert (fragP->fr_fix >= 2);
4881 buffer_address[-2] |= 0x1;
4882 buffer_address[-1] = 0x20;
4883 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4884 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4885 fixP->fx_pcrel_adjust = 2;
151337e8 4886 fragP->fr_fix += 2;
252b5132
RH		 4887 break;
4888 case TAB (PCINDEX, LONG):
252b5132
RH		 4889 assert (fragP->fr_fix >= 2);
4890 buffer_address[-2] |= 0x1;
4891 buffer_address[-1] = 0x30;
151337e8 4892 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4893 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4894 fixP->fx_pcrel_adjust = 2;
4895 fragP->fr_fix += 4;
4896 break;
4897 case TAB (ABSTOPCREL, SHORT):
4898 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4899 1, RELAX_RELOC_PC16);
151337e8
NC		 4900 fragP->fr_fix += 2;
4901 break;
4902 case TAB (ABSTOPCREL, LONG):
36759679 4903 if (flag_keep_pcrel)
6b6e92f4 4904 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4905 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4906 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4907 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4908 abort ();
4909 fragP->fr_opcode[1] &= ~0x3F;
4910 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4911 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4912 0, RELAX_RELOC_ABS32);
151337e8 4913 fragP->fr_fix += 4;
252b5132 4914 break;
252b5132
RH		 4915 }
4916}
4917
4918#ifndef BFD_ASSEMBLER
4919
4920void
31302357
AS		 4921md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED,
4922 segT sec ATTRIBUTE_UNUSED,
4923 fragS *fragP)
252b5132
RH		 4924{
4925 md_convert_frag_1 (fragP);
4926}
4927
4928#else
4929
4930void
31302357
AS		 4931md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4932 segT sec ATTRIBUTE_UNUSED,
4933 fragS *fragP)
252b5132
RH		 4934{
4935 md_convert_frag_1 (fragP);
4936}
4937#endif
4938
4939/* Force truly undefined symbols to their maximum size, and generally set up
4940 the frag list to be relaxed
4941 */
4942int
31302357 4943md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 4944{
151337e8 4945 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4946 switch (fragP->fr_subtype)
4947 {
151337e8
NC		 4948 case TAB (BRANCHBWL, SZ_UNDEF):
4949 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4950 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4951 {
151337e8
NC		 4952 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4953 && relaxable_symbol (fragP->fr_symbol))
252b5132 4954 {
151337e8
NC		 4955 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4956 }
4957 else if (flag_short_refs)
4958 {
4959 /* Symbol is undefined and we want short ref. */
4960 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4961 }
4962 else
4963 {
151337e8
NC		 4964 /* Symbol is still undefined. Make it LONG. */
4965 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4966 }
4967 break;
151337e8 4968 }
252b5132 4969
151337e8 4970 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4971 {
151337e8
NC		 4972 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4973 && relaxable_symbol (fragP->fr_symbol))
252b5132 4974 {
151337e8 4975 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4976 }
4977 else
4978 {
151337e8
NC		 4979 /* Symbol is undefined and we don't have long branches. */
4980 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4981 }
4982 break;
151337e8 4983 }
252b5132 4984
151337e8 4985 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4986 case TAB (DBCCLBR, SZ_UNDEF):
4987 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4988 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4989 {
8ec6253e
NC		 4990 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4991 && relaxable_symbol (fragP->fr_symbol))
151337e8 4992 || flag_short_refs)
252b5132 4993 {
151337e8 4994 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4995 }
4996 else
4997 {
151337e8 4998 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4999 }
5000 break;
151337e8 5001 }
81d4177b 5002
252b5132
RH		 5003 case TAB (PCINDEX, SZ_UNDEF):
5004 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5005 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5006 {
5007 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5008 }
5009 else
5010 {
5011 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5012 }
5013 break;
5014
151337e8
NC		 5015 case TAB (ABSTOPCREL, SZ_UNDEF):
5016 {
5017 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5018 && relaxable_symbol (fragP->fr_symbol)))
5019 {
5020 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5021 }
5022 else
5023 {
5024 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5025 }
5026 break;
5027 }
5028
252b5132
RH		 5029 default:
5030 break;
5031 }
5032
151337e8 5033 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5034 switch (fragP->fr_subtype)
5035 {
151337e8
NC		 5036 case TAB (BRANCHBWL, BYTE):
5037 case TAB (BRABSJUNC, BYTE):
5038 case TAB (BRABSJCOND, BYTE):
5039 case TAB (BRANCHBW, BYTE):
252b5132 5040 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5041 case we force word mode. If the symbol is at the start of a
5042 frag, and it is the next frag with any data in it (usually
5043 this is just the next frag, but assembler listings may
5044 introduce empty frags), we must use word mode. */
5045 if (fragP->fr_symbol)
252b5132 5046 {
ac62c346 5047 fragS *sym_frag;
252b5132 5048
ac62c346
AM		 5049 sym_frag = symbol_get_frag (fragP->fr_symbol);
5050 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5051 {
ac62c346
AM		 5052 fragS *l;
5053
23b7f870 5054 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5055 if (l->fr_fix != 0)
5056 break;
5057 if (l == sym_frag)
5058 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5059 }
5060 }
5061 break;
5062 default:
5063 break;
5064 }
ac62c346 5065 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5066}
5067
5068#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5069/* the bit-field entries in the relocation_info struct plays hell
5070 with the byte-order problems of cross-assembly. So as a hack,
5071 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5072 you there. -KWK */
252b5132
RH		 5073/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5074 are symbolnum, most sig. byte first. Last byte is broken up with
5075 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5076 nibble as nuthin. (on Sun 3 at least) */
5077/* Translate the internal relocation information into target-specific
92774660 5078 format. */
252b5132
RH		 5079#ifdef comment
5080void
31302357 5081md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5082{
36759679 5083 /* This is easy. */
252b5132 5084 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5085 /* Now the fun stuff. */
252b5132 5086 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5087 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5088 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5089 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5090 | ((ri->r_length << 5) & 0x60)
5091 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5092}
5093
36759679 5094#endif
252b5132
RH		 5095
5096#ifndef BFD_ASSEMBLER
5097void
31302357
AS		 5098tc_aout_fix_to_chars (char *where, fixS *fixP,
5099 relax_addressT segment_address_in_file)
252b5132
RH		 5100{
5101 /*
5102 * In: length of relocation (or of address) in chars: 1, 2 or 4.
5103 * Out: GNU LD relocation length code: 0, 1, or 2.
5104 */
5105
5a38dc70 5106 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
252b5132
RH		 5107 long r_symbolnum;
5108
5109 know (fixP->fx_addsy != NULL);
5110
5111 md_number_to_chars (where,
31302357
AS		 5112 (fixP->fx_frag->fr_address
5113 + fixP->fx_where - segment_address_in_file), 4);
252b5132
RH		 5114
5115 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5116 ? S_GET_TYPE (fixP->fx_addsy)
5117 : fixP->fx_addsy->sy_number);
5118
5119 where[4] = (r_symbolnum >> 16) & 0x0ff;
5120 where[5] = (r_symbolnum >> 8) & 0x0ff;
5121 where[6] = r_symbolnum & 0x0ff;
31302357
AS		 5122 where[7] = (((fixP->fx_pcrel << 7) & 0x80)
5123 | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60)
5124 | ((!S_IS_DEFINED (fixP->fx_addsy) << 4) & 0x10));
252b5132
RH		 5125}
5126#endif
5127
5128#endif /* OBJ_AOUT or OBJ_BOUT */
5129
5130#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5131int md_short_jump_size = 4;
5132int md_long_jump_size = 6;
252b5132
RH		 5133
5134void
31302357
AS		 5135md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5136 fragS *frag ATTRIBUTE_UNUSED,
5137 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5138{
5139 valueT offset;
5140
5141 offset = to_addr - (from_addr + 2);
5142
5143 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5144 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5145}
5146
5147void
31302357
AS		 5148md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5149 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5150{
5151 valueT offset;
5152
6b6e92f4 5153 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5154 {
36759679 5155 if (flag_keep_pcrel)
6b6e92f4 5156 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5157 offset = to_addr - S_GET_VALUE (to_symbol);
5158 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5159 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5160 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5161 0, NO_RELOC);
5162 }
5163 else
5164 {
5165 offset = to_addr - (from_addr + 2);
5166 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5167 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5168 }
5169}
5170
5171#endif
5172
5173/* Different values of OK tell what its OK to return. Things that
5174 aren't OK are an error (what a shock, no?)
5175
5176 0: Everything is OK
3e602632
NC		 5177 10: Absolute 1:8 only
5178 20: Absolute 0:7 only
5179 30: absolute 0:15 only
5180 40: Absolute 0:31 only
5181 50: absolute 0:127 only
252b5132 5182 55: absolute -64:63 only
3e602632
NC		 5183 60: absolute -128:127 only
5184 70: absolute 0:4095 only
5185 80: absolute -1, 1:7 only
5186 90: No bignums. */
252b5132
RH		 5187
5188static int
31302357 5189get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5190{
5191 if (exp->exp.X_op == O_absent)
5192 {
36759679 5193 /* Do the same thing the VAX asm does. */
252b5132
RH		 5194 op (exp) = O_constant;
5195 adds (exp) = 0;
5196 subs (exp) = 0;
5197 offs (exp) = 0;
5198 if (ok == 10)
5199 {
5200 as_warn (_("expression out of range: defaulting to 1"));
5201 offs (exp) = 1;
5202 }
5203 }
5204 else if (exp->exp.X_op == O_constant)
5205 {
5206 switch (ok)
5207 {
5208 case 10:
5209 if (offs (exp) < 1 || offs (exp) > 8)
5210 {
5211 as_warn (_("expression out of range: defaulting to 1"));
5212 offs (exp) = 1;
5213 }
5214 break;
5215 case 20:
5216 if (offs (exp) < 0 || offs (exp) > 7)
5217 goto outrange;
5218 break;
5219 case 30:
5220 if (offs (exp) < 0 || offs (exp) > 15)
5221 goto outrange;
5222 break;
5223 case 40:
5224 if (offs (exp) < 0 || offs (exp) > 32)
5225 goto outrange;
5226 break;
5227 case 50:
5228 if (offs (exp) < 0 || offs (exp) > 127)
5229 goto outrange;
5230 break;
5231 case 55:
5232 if (offs (exp) < -64 || offs (exp) > 63)
5233 goto outrange;
5234 break;
5235 case 60:
5236 if (offs (exp) < -128 || offs (exp) > 127)
5237 goto outrange;
5238 break;
5239 case 70:
5240 if (offs (exp) < 0 || offs (exp) > 4095)
5241 {
5242 outrange:
5243 as_warn (_("expression out of range: defaulting to 0"));
5244 offs (exp) = 0;
5245 }
5246 break;
3e602632
NC		 5247 case 80:
5248 if (offs (exp) < -1
5249 || offs (exp) > 7
5250 || offs (exp) == 0)
5251 {
5252 as_warn (_("expression out of range: defaulting to 1"));
5253 offs (exp) = 1;
5254 }
5255 break;
252b5132
RH		 5256 default:
5257 break;
5258 }
5259 }
5260 else if (exp->exp.X_op == O_big)
5261 {
36759679 5262 if (offs (exp) <= 0 /* flonum. */
3e602632 5263 && (ok == 90 /* no bignums */
36759679 5264 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5265 /* If we have a flonum zero, a zero integer should
5266 do as well (e.g., in moveq). */
5267 && generic_floating_point_number.exponent == 0
5268 && generic_floating_point_number.low[0] == 0)))
5269 {
36759679 5270 /* HACK! Turn it into a long. */
252b5132
RH		 5271 LITTLENUM_TYPE words[6];
5272
36759679 5273 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5274 op (exp) = O_constant;
5275 adds (exp) = 0;
5276 subs (exp) = 0;
5277 offs (exp) = words[1] | (words[0] << 16);
5278 }
5279 else if (ok != 0)
5280 {
5281 op (exp) = O_constant;
5282 adds (exp) = 0;
5283 subs (exp) = 0;
5284 offs (exp) = (ok == 10) ? 1 : 0;
5285 as_warn (_("Can't deal with expression; defaulting to %ld"),
5286 offs (exp));
5287 }
5288 }
5289 else
5290 {
3e602632 5291 if (ok >= 10 && ok <= 80)
252b5132
RH		 5292 {
5293 op (exp) = O_constant;
5294 adds (exp) = 0;
5295 subs (exp) = 0;
5296 offs (exp) = (ok == 10) ? 1 : 0;
5297 as_warn (_("Can't deal with expression; defaulting to %ld"),
5298 offs (exp));
5299 }
5300 }
5301
5302 if (exp->size != SIZE_UNSPEC)
5303 {
5304 switch (exp->size)
5305 {
5306 case SIZE_UNSPEC:
5307 case SIZE_LONG:
5308 break;
5309 case SIZE_BYTE:
5310 if (!isbyte (offs (exp)))
5311 as_warn (_("expression doesn't fit in BYTE"));
5312 break;
5313 case SIZE_WORD:
5314 if (!isword (offs (exp)))
5315 as_warn (_("expression doesn't fit in WORD"));
5316 break;
5317 }
5318 }
5319
5320 return offs (exp);
5321}
5322
5323/* These are the back-ends for the various machine dependent pseudo-ops. */
5324
5325static void
31302357 5326s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5327{
5328 subseg_set (data_section, 1);
5329 demand_empty_rest_of_line ();
5330}
5331
5332static void
31302357 5333s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5334{
5335 subseg_set (data_section, 2);
5336 demand_empty_rest_of_line ();
5337}
5338
5339static void
31302357 5340s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5341{
5342 /* We don't support putting frags in the BSS segment, we fake it
5343 by marking in_bss, then looking at s_skip for clues. */
5344
5345 subseg_set (bss_section, 0);
5346 demand_empty_rest_of_line ();
5347}
5348
5349static void
31302357 5350s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5351{
5352 register int temp;
5353 register long temp_fill;
5354
5355 temp = 1; /* JF should be 2? */
5356 temp_fill = get_absolute_expression ();
92774660 5357 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5358 frag_align (temp, (int) temp_fill, 0);
5359 demand_empty_rest_of_line ();
5360 record_alignment (now_seg, temp);
5361}
5362
5363static void
31302357 5364s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5365{
5366 demand_empty_rest_of_line ();
5367}
5368\f
5369/* Pseudo-ops handled for MRI compatibility. */
5370
5371/* This function returns non-zero if the argument is a conditional
5372 pseudo-op. This is called when checking whether a pending
5373 alignment is needed. */
5374
5375int
31302357 5376m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5377{
5378 return (pop->poc_handler == s_mri_if
5379 || pop->poc_handler == s_mri_else);
5380}
5381
5382/* Handle an MRI style chip specification. */
5383
5384static void
31302357 5385mri_chip (void)
252b5132
RH		 5386{
5387 char *s;
5388 char c;
5389 int i;
5390
5391 s = input_line_pointer;
5392 /* We can't use get_symbol_end since the processor names are not proper
5393 symbols. */
5394 while (is_part_of_name (c = *input_line_pointer++))
5395 ;
5396 *--input_line_pointer = 0;
5397 for (i = 0; i < n_archs; i++)
5398 if (strcasecmp (s, archs[i].name) == 0)
5399 break;
5400 if (i >= n_archs)
5401 {
5402 as_bad (_("%s: unrecognized processor name"), s);
5403 *input_line_pointer = c;
5404 ignore_rest_of_line ();
5405 return;
5406 }
5407 *input_line_pointer = c;
5408
5409 if (*input_line_pointer == '/')
5410 current_architecture = 0;
5411 else
5412 current_architecture &= m68881 | m68851;
5413 current_architecture |= archs[i].arch;
990ae22a 5414 current_chip = archs[i].chip;
252b5132
RH		 5415
5416 while (*input_line_pointer == '/')
5417 {
5418 ++input_line_pointer;
5419 s = input_line_pointer;
5420 /* We can't use get_symbol_end since the processor names are not
5421 proper symbols. */
5422 while (is_part_of_name (c = *input_line_pointer++))
5423 ;
5424 *--input_line_pointer = 0;
5425 if (strcmp (s, "68881") == 0)
5426 current_architecture |= m68881;
5427 else if (strcmp (s, "68851") == 0)
5428 current_architecture |= m68851;
5429 *input_line_pointer = c;
5430 }
5431
5432 /* Update info about available control registers. */
5433 select_control_regs ();
5434}
5435
5436/* The MRI CHIP pseudo-op. */
5437
5438static void
31302357 5439s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5440{
5441 char *stop = NULL;
5442 char stopc;
5443
5444 if (flag_mri)
5445 stop = mri_comment_field (&stopc);
5446 mri_chip ();
5447 if (flag_mri)
5448 mri_comment_end (stop, stopc);
5449 demand_empty_rest_of_line ();
5450}
5451
5452/* The MRI FOPT pseudo-op. */
5453
5454static void
31302357 5455s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5456{
5457 SKIP_WHITESPACE ();
5458
5459 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5460 {
5461 int temp;
5462
5463 input_line_pointer += 3;
5464 temp = get_absolute_expression ();
5465 if (temp < 0 || temp > 7)
5466 as_bad (_("bad coprocessor id"));
5467 else
5468 m68k_float_copnum = COP0 + temp;
5469 }
5470 else
5471 {
5472 as_bad (_("unrecognized fopt option"));
5473 ignore_rest_of_line ();
5474 return;
5475 }
5476
5477 demand_empty_rest_of_line ();
5478}
5479
5480/* The structure used to handle the MRI OPT pseudo-op. */
5481
5482struct opt_action
5483{
5484 /* The name of the option. */
5485 const char *name;
5486
5487 /* If this is not NULL, just call this function. The first argument
5488 is the ARG field of this structure, the second argument is
5489 whether the option was negated. */
31302357 5490 void (*pfn) (int arg, int on);
252b5132
RH		 5491
5492 /* If this is not NULL, and the PFN field is NULL, set the variable
5493 this points to. Set it to the ARG field if the option was not
5494 negated, and the NOTARG field otherwise. */
5495 int *pvar;
5496
5497 /* The value to pass to PFN or to assign to *PVAR. */
5498 int arg;
5499
5500 /* The value to assign to *PVAR if the option is negated. If PFN is
5501 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5502 the option may not be negated. */
5503 int notarg;
5504};
5505
5506/* The table used to handle the MRI OPT pseudo-op. */
5507
31302357
AS		 5508static void skip_to_comma (int, int);
5509static void opt_nest (int, int);
5510static void opt_chip (int, int);
5511static void opt_list (int, int);
5512static void opt_list_symbols (int, int);
252b5132
RH		 5513
5514static const struct opt_action opt_table[] =
5515{
5516 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5517
5518 /* We do relaxing, so there is little use for these options. */
5519 { "b", 0, 0, 0, 0 },
5520 { "brs", 0, 0, 0, 0 },
5521 { "brb", 0, 0, 0, 0 },
5522 { "brl", 0, 0, 0, 0 },
5523 { "brw", 0, 0, 0, 0 },
5524
5525 { "c", 0, 0, 0, 0 },
5526 { "cex", 0, 0, 0, 0 },
5527 { "case", 0, &symbols_case_sensitive, 1, 0 },
5528 { "cl", 0, 0, 0, 0 },
5529 { "cre", 0, 0, 0, 0 },
5530 { "d", 0, &flag_keep_locals, 1, 0 },
5531 { "e", 0, 0, 0, 0 },
5532 { "f", 0, &flag_short_refs, 1, 0 },
5533 { "frs", 0, &flag_short_refs, 1, 0 },
5534 { "frl", 0, &flag_short_refs, 0, 1 },
5535 { "g", 0, 0, 0, 0 },
5536 { "i", 0, 0, 0, 0 },
5537 { "m", 0, 0, 0, 0 },
5538 { "mex", 0, 0, 0, 0 },
5539 { "mc", 0, 0, 0, 0 },
5540 { "md", 0, 0, 0, 0 },
5541 { "nest", opt_nest, 0, 0, 0 },
5542 { "next", skip_to_comma, 0, 0, 0 },
5543 { "o", 0, 0, 0, 0 },
5544 { "old", 0, 0, 0, 0 },
5545 { "op", skip_to_comma, 0, 0, 0 },
5546 { "pco", 0, 0, 0, 0 },
5547 { "p", opt_chip, 0, 0, 0 },
5548 { "pcr", 0, 0, 0, 0 },
5549 { "pcs", 0, 0, 0, 0 },
5550 { "r", 0, 0, 0, 0 },
5551 { "quick", 0, &m68k_quick, 1, 0 },
5552 { "rel32", 0, &m68k_rel32, 1, 0 },
5553 { "s", opt_list, 0, 0, 0 },
5554 { "t", opt_list_symbols, 0, 0, 0 },
5555 { "w", 0, &flag_no_warnings, 0, 1 },
5556 { "x", 0, 0, 0, 0 }
5557};
5558
8fce3f5e 5559#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5560
5561/* The MRI OPT pseudo-op. */
5562
5563static void
31302357 5564s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5565{
5566 do
5567 {
5568 int t;
5569 char *s;
5570 char c;
5571 int i;
5572 const struct opt_action *o;
5573
5574 SKIP_WHITESPACE ();
5575
5576 t = 1;
5577 if (*input_line_pointer == '-')
5578 {
5579 ++input_line_pointer;
5580 t = 0;
5581 }
5582 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5583 {
5584 input_line_pointer += 2;
5585 t = 0;
5586 }
5587
5588 s = input_line_pointer;
5589 c = get_symbol_end ();
5590
5591 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5592 {
5593 if (strcasecmp (s, o->name) == 0)
5594 {
5595 if (o->pfn)
5596 {
5597 /* Restore input_line_pointer now in case the option
5598 takes arguments. */
5599 *input_line_pointer = c;
5600 (*o->pfn) (o->arg, t);
5601 }
5602 else if (o->pvar != NULL)
5603 {
5604 if (! t && o->arg == o->notarg)
5605 as_bad (_("option `%s' may not be negated"), s);
5606 *input_line_pointer = c;
5607 *o->pvar = t ? o->arg : o->notarg;
5608 }
5609 else
5610 *input_line_pointer = c;
5611 break;
5612 }
5613 }
5614 if (i >= OPTCOUNT)
5615 {
5616 as_bad (_("option `%s' not recognized"), s);
5617 *input_line_pointer = c;
5618 }
5619 }
5620 while (*input_line_pointer++ == ',');
5621
5622 /* Move back to terminating character. */
5623 --input_line_pointer;
5624 demand_empty_rest_of_line ();
5625}
5626
5627/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5628 not support and which take arguments. */
252b5132
RH		 5629
5630static void
31302357 5631skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5632{
5633 while (*input_line_pointer != ','
5634 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5635 ++input_line_pointer;
5636}
5637
5638/* Handle the OPT NEST=depth option. */
5639
5640static void
31302357 5641opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5642{
5643 if (*input_line_pointer != '=')
5644 {
5645 as_bad (_("bad format of OPT NEST=depth"));
5646 return;
5647 }
5648
5649 ++input_line_pointer;
5650 max_macro_nest = get_absolute_expression ();
5651}
5652
5653/* Handle the OPT P=chip option. */
5654
5655static void
31302357 5656opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5657{
5658 if (*input_line_pointer != '=')
5659 {
5660 /* This is just OPT P, which we do not support. */
5661 return;
5662 }
5663
5664 ++input_line_pointer;
5665 mri_chip ();
5666}
5667
5668/* Handle the OPT S option. */
5669
5670static void
31302357 5671opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5672{
5673 listing_list (on);
5674}
5675
5676/* Handle the OPT T option. */
5677
5678static void
31302357 5679opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5680{
5681 if (on)
5682 listing |= LISTING_SYMBOLS;
5683 else
8a104df9 5684 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5685}
5686
5687/* Handle the MRI REG pseudo-op. */
5688
5689static void
31302357 5690s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5691{
5692 char *s;
5693 int c;
5694 struct m68k_op rop;
5695 int mask;
5696 char *stop = NULL;
5697 char stopc;
5698
5699 if (line_label == NULL)
5700 {
5701 as_bad (_("missing label"));
5702 ignore_rest_of_line ();
5703 return;
5704 }
5705
5706 if (flag_mri)
5707 stop = mri_comment_field (&stopc);
5708
5709 SKIP_WHITESPACE ();
5710
5711 s = input_line_pointer;
3882b010 5712 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5713#ifdef REGISTER_PREFIX
5714 || *input_line_pointer == REGISTER_PREFIX
5715#endif
5716 || *input_line_pointer == '/'
5717 || *input_line_pointer == '-')
5718 ++input_line_pointer;
5719 c = *input_line_pointer;
5720 *input_line_pointer = '\0';
5721
5722 if (m68k_ip_op (s, &rop) != 0)
5723 {
5724 if (rop.error == NULL)
5725 as_bad (_("bad register list"));
5726 else
5727 as_bad (_("bad register list: %s"), rop.error);
5728 *input_line_pointer = c;
5729 ignore_rest_of_line ();
5730 return;
5731 }
5732
5733 *input_line_pointer = c;
5734
5735 if (rop.mode == REGLST)
5736 mask = rop.mask;
5737 else if (rop.mode == DREG)
5738 mask = 1 << (rop.reg - DATA0);
5739 else if (rop.mode == AREG)
5740 mask = 1 << (rop.reg - ADDR0 + 8);
5741 else if (rop.mode == FPREG)
5742 mask = 1 << (rop.reg - FP0 + 16);
5743 else if (rop.mode == CONTROL
5744 && rop.reg == FPI)
5745 mask = 1 << 24;
5746 else if (rop.mode == CONTROL
5747 && rop.reg == FPS)
5748 mask = 1 << 25;
5749 else if (rop.mode == CONTROL
5750 && rop.reg == FPC)
5751 mask = 1 << 26;
5752 else
5753 {
5754 as_bad (_("bad register list"));
5755 ignore_rest_of_line ();
5756 return;
5757 }
5758
5759 S_SET_SEGMENT (line_label, reg_section);
5760 S_SET_VALUE (line_label, ~mask);
49309057 5761 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5762
5763 if (flag_mri)
5764 mri_comment_end (stop, stopc);
5765
5766 demand_empty_rest_of_line ();
5767}
5768
5769/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5770
5771struct save_opts
5772{
5773 struct save_opts *next;
5774 int abspcadd;
5775 int symbols_case_sensitive;
5776 int keep_locals;
5777 int short_refs;
5778 int architecture;
6b6e92f4 5779 int chip;
252b5132
RH		 5780 int quick;
5781 int rel32;
5782 int listing;
5783 int no_warnings;
5784 /* FIXME: We don't save OPT S. */
5785};
5786
5787/* This variable holds the stack of saved options. */
5788
5789static struct save_opts *save_stack;
5790
5791/* The MRI SAVE pseudo-op. */
5792
5793static void
31302357 5794s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5795{
5796 struct save_opts *s;
5797
5798 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5799 s->abspcadd = m68k_abspcadd;
5800 s->symbols_case_sensitive = symbols_case_sensitive;
5801 s->keep_locals = flag_keep_locals;
5802 s->short_refs = flag_short_refs;
5803 s->architecture = current_architecture;
6b6e92f4 5804 s->chip = current_chip;
252b5132
RH		 5805 s->quick = m68k_quick;
5806 s->rel32 = m68k_rel32;
5807 s->listing = listing;
5808 s->no_warnings = flag_no_warnings;
5809
5810 s->next = save_stack;
5811 save_stack = s;
5812
5813 demand_empty_rest_of_line ();
5814}
5815
5816/* The MRI RESTORE pseudo-op. */
5817
5818static void
31302357 5819s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5820{
5821 struct save_opts *s;
5822
5823 if (save_stack == NULL)
5824 {
5825 as_bad (_("restore without save"));
5826 ignore_rest_of_line ();
5827 return;
5828 }
5829
5830 s = save_stack;
5831 save_stack = s->next;
5832
5833 m68k_abspcadd = s->abspcadd;
5834 symbols_case_sensitive = s->symbols_case_sensitive;
5835 flag_keep_locals = s->keep_locals;
5836 flag_short_refs = s->short_refs;
5837 current_architecture = s->architecture;
6b6e92f4 5838 current_chip = s->chip;
252b5132
RH		 5839 m68k_quick = s->quick;
5840 m68k_rel32 = s->rel32;
5841 listing = s->listing;
5842 flag_no_warnings = s->no_warnings;
5843
5844 free (s);
5845
5846 demand_empty_rest_of_line ();
5847}
5848
5849/* Types of MRI structured control directives. */
5850
5851enum mri_control_type
5852{
5853 mri_for,
5854 mri_if,
5855 mri_repeat,
5856 mri_while
5857};
5858
5859/* This structure is used to stack the MRI structured control
5860 directives. */
5861
5862struct mri_control_info
5863{
5864 /* The directive within which this one is enclosed. */
5865 struct mri_control_info *outer;
5866
5867 /* The type of directive. */
5868 enum mri_control_type type;
5869
5870 /* Whether an ELSE has been in an IF. */
5871 int else_seen;
5872
5873 /* The add or sub statement at the end of a FOR. */
5874 char *incr;
5875
5876 /* The label of the top of a FOR or REPEAT loop. */
5877 char *top;
5878
5879 /* The label to jump to for the next iteration, or the else
5880 expression of a conditional. */
5881 char *next;
5882
5883 /* The label to jump to to break out of the loop, or the label past
5884 the end of a conditional. */
5885 char *bottom;
5886};
5887
5888/* The stack of MRI structured control directives. */
5889
5890static struct mri_control_info *mri_control_stack;
5891
5892/* The current MRI structured control directive index number, used to
5893 generate label names. */
5894
5895static int mri_control_index;
5896
252b5132
RH		 5897/* Assemble an instruction for an MRI structured control directive. */
5898
5899static void
31302357 5900mri_assemble (char *str)
252b5132
RH		 5901{
5902 char *s;
5903
5904 /* md_assemble expects the opcode to be in lower case. */
5905 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5906 *s = TOLOWER (*s);
252b5132
RH		 5907
5908 md_assemble (str);
5909}
5910
5911/* Generate a new MRI label structured control directive label name. */
5912
5913static char *
31302357 5914mri_control_label (void)
252b5132
RH		 5915{
5916 char *n;
5917
5918 n = (char *) xmalloc (20);
5919 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5920 ++mri_control_index;
5921 return n;
5922}
5923
5924/* Create a new MRI structured control directive. */
5925
5926static struct mri_control_info *
31302357 5927push_mri_control (enum mri_control_type type)
252b5132
RH		 5928{
5929 struct mri_control_info *n;
5930
5931 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5932
5933 n->type = type;
5934 n->else_seen = 0;
5935 if (type == mri_if || type == mri_while)
5936 n->top = NULL;
5937 else
5938 n->top = mri_control_label ();
5939 n->next = mri_control_label ();
5940 n->bottom = mri_control_label ();
5941
5942 n->outer = mri_control_stack;
5943 mri_control_stack = n;
5944
5945 return n;
5946}
5947
5948/* Pop off the stack of MRI structured control directives. */
5949
5950static void
31302357 5951pop_mri_control (void)
252b5132
RH		 5952{
5953 struct mri_control_info *n;
5954
5955 n = mri_control_stack;
5956 mri_control_stack = n->outer;
5957 if (n->top != NULL)
5958 free (n->top);
5959 free (n->next);
5960 free (n->bottom);
5961 free (n);
5962}
5963
5964/* Recognize a condition code in an MRI structured control expression. */
5965
5966static int
31302357 5967parse_mri_condition (int *pcc)
252b5132
RH		 5968{
5969 char c1, c2;
5970
5971 know (*input_line_pointer == '<');
5972
5973 ++input_line_pointer;
5974 c1 = *input_line_pointer++;
5975 c2 = *input_line_pointer++;
5976
5977 if (*input_line_pointer != '>')
5978 {
5979 as_bad (_("syntax error in structured control directive"));
5980 return 0;
5981 }
5982
5983 ++input_line_pointer;
5984 SKIP_WHITESPACE ();
5985
3882b010
L		 5986 c1 = TOLOWER (c1);
5987 c2 = TOLOWER (c2);
252b5132
RH		 5988
5989 *pcc = (c1 << 8) | c2;
5990
5991 return 1;
5992}
5993
5994/* Parse a single operand in an MRI structured control expression. */
5995
5996static int
31302357
AS		 5997parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5998 char **rightstart, char **rightstop)
252b5132
RH		 5999{
6000 char *s;
6001
6002 SKIP_WHITESPACE ();
6003
6004 *pcc = -1;
6005 *leftstart = NULL;
6006 *leftstop = NULL;
6007 *rightstart = NULL;
6008 *rightstop = NULL;
6009
6010 if (*input_line_pointer == '<')
6011 {
6012 /* It's just a condition code. */
6013 return parse_mri_condition (pcc);
6014 }
6015
6016 /* Look ahead for the condition code. */
6017 for (s = input_line_pointer; *s != '\0'; ++s)
6018 {
6019 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6020 break;
6021 }
6022 if (*s == '\0')
6023 {
6024 as_bad (_("missing condition code in structured control directive"));
6025 return 0;
6026 }
6027
6028 *leftstart = input_line_pointer;
6029 *leftstop = s;
6030 if (*leftstop > *leftstart
6031 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6032 --*leftstop;
6033
6034 input_line_pointer = s;
6035 if (! parse_mri_condition (pcc))
6036 return 0;
6037
6038 /* Look ahead for AND or OR or end of line. */
6039 for (s = input_line_pointer; *s != '\0'; ++s)
6040 {
e1f44d10
NC		 6041 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6042 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6043 ^^^ ^^ */
8a104df9
KH		 6044 if ((s == input_line_pointer
6045 || *(s-1) == ' '
6046 || *(s-1) == '\t')
6047 && ((strncasecmp (s, "AND", 3) == 0
6048 && (s[3] == '.' || ! is_part_of_name (s[3])))
6049 || (strncasecmp (s, "OR", 2) == 0
6050 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6051 break;
252b5132
RH		 6052 }
6053
6054 *rightstart = input_line_pointer;
6055 *rightstop = s;
6056 if (*rightstop > *rightstart
6057 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6058 --*rightstop;
6059
6060 input_line_pointer = s;
6061
6062 return 1;
6063}
6064
6065#define MCC(b1, b2) (((b1) << 8) | (b2))
6066
6067/* Swap the sense of a condition. This changes the condition so that
6068 it generates the same result when the operands are swapped. */
6069
6070static int
31302357 6071swap_mri_condition (int cc)
252b5132
RH		 6072{
6073 switch (cc)
6074 {
6075 case MCC ('h', 'i'): return MCC ('c', 's');
6076 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6077 /* <HS> is an alias for <CC>. */
e1f44d10 6078 case MCC ('h', 's'):
252b5132 6079 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6080 /* <LO> is an alias for <CS>. */
e1f44d10 6081 case MCC ('l', 'o'):
252b5132
RH		 6082 case MCC ('c', 's'): return MCC ('h', 'i');
6083 case MCC ('p', 'l'): return MCC ('m', 'i');
6084 case MCC ('m', 'i'): return MCC ('p', 'l');
6085 case MCC ('g', 'e'): return MCC ('l', 'e');
6086 case MCC ('l', 't'): return MCC ('g', 't');
6087 case MCC ('g', 't'): return MCC ('l', 't');
6088 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6089 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 6090 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6091 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6092 case MCC ('v', 'c'):
6093 case MCC ('v', 's'):
6094 default :
6095 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6096 (char) (cc >> 8), (char) (cc));
6097 break;
252b5132
RH		 6098 }
6099 return cc;
6100}
6101
6102/* Reverse the sense of a condition. */
6103
6104static int
31302357 6105reverse_mri_condition (int cc)
252b5132
RH		 6106{
6107 switch (cc)
6108 {
6109 case MCC ('h', 'i'): return MCC ('l', 's');
6110 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6111 /* <HS> is an alias for <CC> */
6112 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6113 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6114 /* <LO> is an alias for <CS> */
6115 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6116 case MCC ('c', 's'): return MCC ('c', 'c');
6117 case MCC ('n', 'e'): return MCC ('e', 'q');
6118 case MCC ('e', 'q'): return MCC ('n', 'e');
6119 case MCC ('v', 'c'): return MCC ('v', 's');
6120 case MCC ('v', 's'): return MCC ('v', 'c');
6121 case MCC ('p', 'l'): return MCC ('m', 'i');
6122 case MCC ('m', 'i'): return MCC ('p', 'l');
6123 case MCC ('g', 'e'): return MCC ('l', 't');
6124 case MCC ('l', 't'): return MCC ('g', 'e');
6125 case MCC ('g', 't'): return MCC ('l', 'e');
6126 case MCC ('l', 'e'): return MCC ('g', 't');
6127 }
6128 return cc;
6129}
6130
6131/* Build an MRI structured control expression. This generates test
6132 and branch instructions. It goes to TRUELAB if the condition is
6133 true, and to FALSELAB if the condition is false. Exactly one of
6134 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6135 is the size qualifier for the expression. EXTENT is the size to
6136 use for the branch. */
6137
6138static void
31302357
AS		 6139build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6140 char *rightstart, char *rightstop,
6141 const char *truelab, const char *falselab,
6142 int extent)
252b5132
RH		 6143{
6144 char *buf;
6145 char *s;
6146
6147 if (leftstart != NULL)
6148 {
6149 struct m68k_op leftop, rightop;
6150 char c;
6151
6152 /* Swap the compare operands, if necessary, to produce a legal
6153 m68k compare instruction. Comparing a register operand with
6154 a non-register operand requires the register to be on the
6155 right (cmp, cmpa). Comparing an immediate value with
6156 anything requires the immediate value to be on the left
6157 (cmpi). */
6158
6159 c = *leftstop;
6160 *leftstop = '\0';
6161 (void) m68k_ip_op (leftstart, &leftop);
6162 *leftstop = c;
6163
6164 c = *rightstop;
6165 *rightstop = '\0';
6166 (void) m68k_ip_op (rightstart, &rightop);
6167 *rightstop = c;
6168
6169 if (rightop.mode == IMMED
6170 || ((leftop.mode == DREG || leftop.mode == AREG)
6171 && (rightop.mode != DREG && rightop.mode != AREG)))
6172 {
6173 char *temp;
6174
31302357
AS		 6175 /* Correct conditional handling:
6176 if #1 <lt> d0 then ;means if (1 < d0)
6177 ...
6178 endi
e1f44d10 6179
31302357 6180 should assemble to:
e1f44d10 6181
31302357
AS		 6182 cmp #1,d0 if we do *not* swap the operands
6183 bgt true we need the swapped condition!
6184 ble false
6185 true:
6186 ...
6187 false:
6188 */
252b5132
RH		 6189 temp = leftstart;
6190 leftstart = rightstart;
6191 rightstart = temp;
6192 temp = leftstop;
6193 leftstop = rightstop;
6194 rightstop = temp;
8a104df9
KH		 6195 }
6196 else
6197 {
e1f44d10 6198 cc = swap_mri_condition (cc);
252b5132
RH		 6199 }
6200 }
6201
6202 if (truelab == NULL)
6203 {
6204 cc = reverse_mri_condition (cc);
6205 truelab = falselab;
6206 }
92774660 6207
252b5132
RH		 6208 if (leftstart != NULL)
6209 {
6210 buf = (char *) xmalloc (20
6211 + (leftstop - leftstart)
6212 + (rightstop - rightstart));
6213 s = buf;
6214 *s++ = 'c';
6215 *s++ = 'm';
6216 *s++ = 'p';
6217 if (qual != '\0')
3882b010 6218 *s++ = TOLOWER (qual);
252b5132
RH		 6219 *s++ = ' ';
6220 memcpy (s, leftstart, leftstop - leftstart);
6221 s += leftstop - leftstart;
6222 *s++ = ',';
6223 memcpy (s, rightstart, rightstop - rightstart);
6224 s += rightstop - rightstart;
6225 *s = '\0';
6226 mri_assemble (buf);
6227 free (buf);
6228 }
92774660 6229
252b5132
RH		 6230 buf = (char *) xmalloc (20 + strlen (truelab));
6231 s = buf;
6232 *s++ = 'b';
6233 *s++ = cc >> 8;
6234 *s++ = cc & 0xff;
6235 if (extent != '\0')
3882b010 6236 *s++ = TOLOWER (extent);
252b5132
RH		 6237 *s++ = ' ';
6238 strcpy (s, truelab);
6239 mri_assemble (buf);
6240 free (buf);
6241}
6242
6243/* Parse an MRI structured control expression. This generates test
6244 and branch instructions. STOP is where the expression ends. It
6245 goes to TRUELAB if the condition is true, and to FALSELAB if the
6246 condition is false. Exactly one of TRUELAB and FALSELAB will be
6247 NULL, meaning to fall through. QUAL is the size qualifier for the
6248 expression. EXTENT is the size to use for the branch. */
6249
6250static void
31302357
AS		 6251parse_mri_control_expression (char *stop, int qual, const char *truelab,
6252 const char *falselab, int extent)
252b5132
RH		 6253{
6254 int c;
6255 int cc;
6256 char *leftstart;
6257 char *leftstop;
6258 char *rightstart;
6259 char *rightstop;
6260
6261 c = *stop;
6262 *stop = '\0';
6263
6264 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6265 &rightstart, &rightstop))
6266 {
6267 *stop = c;
6268 return;
6269 }
6270
6271 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6272 {
6273 const char *flab;
6274
6275 if (falselab != NULL)
6276 flab = falselab;
6277 else
6278 flab = mri_control_label ();
6279
6280 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6281 rightstop, (const char *) NULL, flab, extent);
6282
6283 input_line_pointer += 3;
6284 if (*input_line_pointer != '.'
6285 || input_line_pointer[1] == '\0')
6286 qual = '\0';
6287 else
6288 {
6289 qual = input_line_pointer[1];
6290 input_line_pointer += 2;
6291 }
6292
6293 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6294 &rightstart, &rightstop))
6295 {
6296 *stop = c;
6297 return;
6298 }
6299
6300 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6301 rightstop, truelab, falselab, extent);
6302
6303 if (falselab == NULL)
6304 colon (flab);
6305 }
6306 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6307 {
6308 const char *tlab;
6309
6310 if (truelab != NULL)
6311 tlab = truelab;
6312 else
6313 tlab = mri_control_label ();
6314
6315 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6316 rightstop, tlab, (const char *) NULL, extent);
6317
6318 input_line_pointer += 2;
6319 if (*input_line_pointer != '.'
6320 || input_line_pointer[1] == '\0')
6321 qual = '\0';
6322 else
6323 {
6324 qual = input_line_pointer[1];
6325 input_line_pointer += 2;
6326 }
6327
6328 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6329 &rightstart, &rightstop))
6330 {
6331 *stop = c;
6332 return;
6333 }
6334
6335 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6336 rightstop, truelab, falselab, extent);
6337
6338 if (truelab == NULL)
6339 colon (tlab);
6340 }
6341 else
6342 {
6343 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6344 rightstop, truelab, falselab, extent);
6345 }
6346
6347 *stop = c;
6348 if (input_line_pointer != stop)
6349 as_bad (_("syntax error in structured control directive"));
6350}
6351
6352/* Handle the MRI IF pseudo-op. This may be a structured control
6353 directive, or it may be a regular assembler conditional, depending
6354 on its operands. */
6355
6356static void
31302357 6357s_mri_if (int qual)
252b5132
RH		 6358{
6359 char *s;
6360 int c;
6361 struct mri_control_info *n;
6362
6363 /* A structured control directive must end with THEN with an
6364 optional qualifier. */
6365 s = input_line_pointer;
e1f44d10
NC		 6366 /* We only accept '*' as introduction of comments if preceded by white space
6367 or at first column of a line (I think this can't actually happen here?)
6368 This is important when assembling:
6369 if d0 <ne> 12(a0,d0*2) then
36759679 6370 if d0 <ne> #CONST*20 then. */
31302357
AS		 6371 while (! (is_end_of_line[(unsigned char) *s]
6372 || (flag_mri
6373 && *s == '*'
6374 && (s == input_line_pointer
6375 || *(s-1) == ' '
6376 || *(s-1) == '\t'))))
252b5132
RH		 6377 ++s;
6378 --s;
6379 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6380 --s;
6381
6382 if (s - input_line_pointer > 1
6383 && s[-1] == '.')
6384 s -= 2;
6385
6386 if (s - input_line_pointer < 3
6387 || strncasecmp (s - 3, "THEN", 4) != 0)
6388 {
6389 if (qual != '\0')
6390 {
6391 as_bad (_("missing then"));
6392 ignore_rest_of_line ();
6393 return;
6394 }
6395
6396 /* It's a conditional. */
6397 s_if (O_ne);
6398 return;
6399 }
6400
6401 /* Since this might be a conditional if, this pseudo-op will be
6402 called even if we are supported to be ignoring input. Double
6403 check now. Clobber *input_line_pointer so that ignore_input
6404 thinks that this is not a special pseudo-op. */
6405 c = *input_line_pointer;
6406 *input_line_pointer = 0;
6407 if (ignore_input ())
6408 {
6409 *input_line_pointer = c;
6410 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6411 ++input_line_pointer;
6412 demand_empty_rest_of_line ();
6413 return;
6414 }
6415 *input_line_pointer = c;
6416
6417 n = push_mri_control (mri_if);
6418
6419 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6420 n->next, s[1] == '.' ? s[2] : '\0');
6421
6422 if (s[1] == '.')
6423 input_line_pointer = s + 3;
6424 else
6425 input_line_pointer = s + 1;
6426
6427 if (flag_mri)
6428 {
6429 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6430 ++input_line_pointer;
6431 }
6432
6433 demand_empty_rest_of_line ();
6434}
6435
6436/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6437 structured IF, associate the ELSE with the IF. Otherwise, assume
6438 it is a conditional else. */
6439
6440static void
31302357 6441s_mri_else (int qual)
252b5132
RH		 6442{
6443 int c;
6444 char *buf;
6445 char q[2];
6446
6447 if (qual == '\0'
6448 && (mri_control_stack == NULL
6449 || mri_control_stack->type != mri_if
6450 || mri_control_stack->else_seen))
6451 {
6452 s_else (0);
6453 return;
6454 }
6455
6456 c = *input_line_pointer;
6457 *input_line_pointer = 0;
6458 if (ignore_input ())
6459 {
6460 *input_line_pointer = c;
6461 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6462 ++input_line_pointer;
6463 demand_empty_rest_of_line ();
6464 return;
6465 }
6466 *input_line_pointer = c;
6467
6468 if (mri_control_stack == NULL
6469 || mri_control_stack->type != mri_if
6470 || mri_control_stack->else_seen)
6471 {
6472 as_bad (_("else without matching if"));
6473 ignore_rest_of_line ();
6474 return;
6475 }
6476
6477 mri_control_stack->else_seen = 1;
6478
6479 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6480 q[0] = TOLOWER (qual);
252b5132
RH		 6481 q[1] = '\0';
6482 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6483 mri_assemble (buf);
6484 free (buf);
6485
6486 colon (mri_control_stack->next);
6487
6488 if (flag_mri)
6489 {
6490 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6491 ++input_line_pointer;
6492 }
6493
6494 demand_empty_rest_of_line ();
6495}
6496
6497/* Handle the MRI ENDI pseudo-op. */
6498
6499static void
31302357 6500s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6501{
6502 if (mri_control_stack == NULL
6503 || mri_control_stack->type != mri_if)
6504 {
6505 as_bad (_("endi without matching if"));
6506 ignore_rest_of_line ();
6507 return;
6508 }
6509
6510 /* ignore_input will not return true for ENDI, so we don't need to
6511 worry about checking it again here. */
6512
6513 if (! mri_control_stack->else_seen)
6514 colon (mri_control_stack->next);
6515 colon (mri_control_stack->bottom);
6516
6517 pop_mri_control ();
6518
6519 if (flag_mri)
6520 {
6521 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6522 ++input_line_pointer;
6523 }
6524
6525 demand_empty_rest_of_line ();
6526}
6527
6528/* Handle the MRI BREAK pseudo-op. */
6529
6530static void
31302357 6531s_mri_break (int extent)
252b5132
RH		 6532{
6533 struct mri_control_info *n;
6534 char *buf;
6535 char ex[2];
6536
6537 n = mri_control_stack;
6538 while (n != NULL
6539 && n->type != mri_for
6540 && n->type != mri_repeat
6541 && n->type != mri_while)
6542 n = n->outer;
6543 if (n == NULL)
6544 {
6545 as_bad (_("break outside of structured loop"));
6546 ignore_rest_of_line ();
6547 return;
6548 }
6549
6550 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6551 ex[0] = TOLOWER (extent);
252b5132
RH		 6552 ex[1] = '\0';
6553 sprintf (buf, "bra%s %s", ex, n->bottom);
6554 mri_assemble (buf);
6555 free (buf);
6556
6557 if (flag_mri)
6558 {
6559 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6560 ++input_line_pointer;
6561 }
6562
6563 demand_empty_rest_of_line ();
6564}
6565
6566/* Handle the MRI NEXT pseudo-op. */
6567
6568static void
31302357 6569s_mri_next (int extent)
252b5132
RH		 6570{
6571 struct mri_control_info *n;
6572 char *buf;
6573 char ex[2];
6574
6575 n = mri_control_stack;
6576 while (n != NULL
6577 && n->type != mri_for
6578 && n->type != mri_repeat
6579 && n->type != mri_while)
6580 n = n->outer;
6581 if (n == NULL)
6582 {
6583 as_bad (_("next outside of structured loop"));
6584 ignore_rest_of_line ();
6585 return;
6586 }
6587
6588 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6589 ex[0] = TOLOWER (extent);
252b5132
RH		 6590 ex[1] = '\0';
6591 sprintf (buf, "bra%s %s", ex, n->next);
6592 mri_assemble (buf);
6593 free (buf);
6594
6595 if (flag_mri)
6596 {
6597 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6598 ++input_line_pointer;
6599 }
6600
6601 demand_empty_rest_of_line ();
6602}
6603
6604/* Handle the MRI FOR pseudo-op. */
6605
6606static void
31302357 6607s_mri_for (int qual)
252b5132
RH		 6608{
6609 const char *varstart, *varstop;
6610 const char *initstart, *initstop;
6611 const char *endstart, *endstop;
6612 const char *bystart, *bystop;
6613 int up;
6614 int by;
6615 int extent;
6616 struct mri_control_info *n;
6617 char *buf;
6618 char *s;
6619 char ex[2];
6620
6621 /* The syntax is
6622 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6623 */
6624
6625 SKIP_WHITESPACE ();
6626 varstart = input_line_pointer;
6627
6628 /* Look for the '='. */
6629 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6630 && *input_line_pointer != '=')
6631 ++input_line_pointer;
6632 if (*input_line_pointer != '=')
6633 {
6634 as_bad (_("missing ="));
6635 ignore_rest_of_line ();
6636 return;
6637 }
6638
6639 varstop = input_line_pointer;
6640 if (varstop > varstart
6641 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6642 --varstop;
6643
6644 ++input_line_pointer;
6645
6646 initstart = input_line_pointer;
6647
6648 /* Look for TO or DOWNTO. */
6649 up = 1;
6650 initstop = NULL;
6651 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6652 {
6653 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6654 && ! is_part_of_name (input_line_pointer[2]))
6655 {
6656 initstop = input_line_pointer;
6657 input_line_pointer += 2;
6658 break;
6659 }
6660 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6661 && ! is_part_of_name (input_line_pointer[6]))
6662 {
6663 initstop = input_line_pointer;
6664 up = 0;
6665 input_line_pointer += 6;
6666 break;
6667 }
6668 ++input_line_pointer;
6669 }
6670 if (initstop == NULL)
6671 {
6672 as_bad (_("missing to or downto"));
6673 ignore_rest_of_line ();
6674 return;
6675 }
6676 if (initstop > initstart
6677 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6678 --initstop;
6679
6680 SKIP_WHITESPACE ();
6681 endstart = input_line_pointer;
6682
6683 /* Look for BY or DO. */
6684 by = 0;
6685 endstop = NULL;
6686 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6687 {
6688 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6689 && ! is_part_of_name (input_line_pointer[2]))
6690 {
6691 endstop = input_line_pointer;
6692 by = 1;
6693 input_line_pointer += 2;
6694 break;
6695 }
6696 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6697 && (input_line_pointer[2] == '.'
6698 || ! is_part_of_name (input_line_pointer[2])))
6699 {
6700 endstop = input_line_pointer;
6701 input_line_pointer += 2;
6702 break;
6703 }
6704 ++input_line_pointer;
6705 }
6706 if (endstop == NULL)
6707 {
6708 as_bad (_("missing do"));
6709 ignore_rest_of_line ();
6710 return;
6711 }
6712 if (endstop > endstart
6713 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6714 --endstop;
6715
6716 if (! by)
6717 {
6718 bystart = "#1";
6719 bystop = bystart + 2;
6720 }
6721 else
6722 {
6723 SKIP_WHITESPACE ();
6724 bystart = input_line_pointer;
6725
6726 /* Look for DO. */
6727 bystop = NULL;
6728 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6729 {
6730 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6731 && (input_line_pointer[2] == '.'
6732 || ! is_part_of_name (input_line_pointer[2])))
6733 {
6734 bystop = input_line_pointer;
6735 input_line_pointer += 2;
6736 break;
6737 }
6738 ++input_line_pointer;
6739 }
6740 if (bystop == NULL)
6741 {
6742 as_bad (_("missing do"));
6743 ignore_rest_of_line ();
6744 return;
6745 }
6746 if (bystop > bystart
6747 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6748 --bystop;
6749 }
6750
6751 if (*input_line_pointer != '.')
6752 extent = '\0';
6753 else
6754 {
6755 extent = input_line_pointer[1];
6756 input_line_pointer += 2;
6757 }
6758
6759 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6760 n = push_mri_control (mri_for);
6761
6762 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6763
36759679 6764 /* Move init,var. */
252b5132
RH		 6765 s = buf;
6766 *s++ = 'm';
6767 *s++ = 'o';
6768 *s++ = 'v';
6769 *s++ = 'e';
6770 if (qual != '\0')
3882b010 6771 *s++ = TOLOWER (qual);
252b5132
RH		 6772 *s++ = ' ';
6773 memcpy (s, initstart, initstop - initstart);
6774 s += initstop - initstart;
6775 *s++ = ',';
6776 memcpy (s, varstart, varstop - varstart);
6777 s += varstop - varstart;
6778 *s = '\0';
6779 mri_assemble (buf);
6780
6781 colon (n->top);
6782
36759679 6783 /* cmp end,var. */
252b5132
RH		 6784 s = buf;
6785 *s++ = 'c';
6786 *s++ = 'm';
6787 *s++ = 'p';
6788 if (qual != '\0')
3882b010 6789 *s++ = TOLOWER (qual);
252b5132
RH		 6790 *s++ = ' ';
6791 memcpy (s, endstart, endstop - endstart);
6792 s += endstop - endstart;
6793 *s++ = ',';
6794 memcpy (s, varstart, varstop - varstart);
6795 s += varstop - varstart;
6796 *s = '\0';
6797 mri_assemble (buf);
6798
36759679 6799 /* bcc bottom. */
3882b010 6800 ex[0] = TOLOWER (extent);
252b5132
RH		 6801 ex[1] = '\0';
6802 if (up)
6803 sprintf (buf, "blt%s %s", ex, n->bottom);
6804 else
6805 sprintf (buf, "bgt%s %s", ex, n->bottom);
6806 mri_assemble (buf);
6807
6808 /* Put together the add or sub instruction used by ENDF. */
6809 s = buf;
6810 if (up)
6811 strcpy (s, "add");
6812 else
6813 strcpy (s, "sub");
6814 s += 3;
6815 if (qual != '\0')
3882b010 6816 *s++ = TOLOWER (qual);
252b5132
RH		 6817 *s++ = ' ';
6818 memcpy (s, bystart, bystop - bystart);
6819 s += bystop - bystart;
6820 *s++ = ',';
6821 memcpy (s, varstart, varstop - varstart);
6822 s += varstop - varstart;
6823 *s = '\0';
6824 n->incr = buf;
6825
6826 if (flag_mri)
6827 {
6828 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6829 ++input_line_pointer;
6830 }
6831
6832 demand_empty_rest_of_line ();
6833}
6834
6835/* Handle the MRI ENDF pseudo-op. */
6836
6837static void
31302357 6838s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6839{
6840 if (mri_control_stack == NULL
6841 || mri_control_stack->type != mri_for)
6842 {
6843 as_bad (_("endf without for"));
6844 ignore_rest_of_line ();
6845 return;
6846 }
6847
6848 colon (mri_control_stack->next);
6849
6850 mri_assemble (mri_control_stack->incr);
6851
6852 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6853 mri_assemble (mri_control_stack->incr);
6854
6855 free (mri_control_stack->incr);
6856
6857 colon (mri_control_stack->bottom);
6858
6859 pop_mri_control ();
6860
6861 if (flag_mri)
6862 {
6863 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6864 ++input_line_pointer;
6865 }
6866
6867 demand_empty_rest_of_line ();
6868}
6869
6870/* Handle the MRI REPEAT pseudo-op. */
6871
6872static void
31302357 6873s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6874{
6875 struct mri_control_info *n;
6876
6877 n = push_mri_control (mri_repeat);
6878 colon (n->top);
6879 if (flag_mri)
6880 {
6881 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6882 ++input_line_pointer;
6883 }
6884 demand_empty_rest_of_line ();
6885}
6886
6887/* Handle the MRI UNTIL pseudo-op. */
6888
6889static void
31302357 6890s_mri_until (int qual)
252b5132
RH		 6891{
6892 char *s;
6893
6894 if (mri_control_stack == NULL
6895 || mri_control_stack->type != mri_repeat)
6896 {
6897 as_bad (_("until without repeat"));
6898 ignore_rest_of_line ();
6899 return;
6900 }
6901
6902 colon (mri_control_stack->next);
6903
6904 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6905 ;
6906
6907 parse_mri_control_expression (s, qual, (const char *) NULL,
6908 mri_control_stack->top, '\0');
6909
6910 colon (mri_control_stack->bottom);
6911
6912 input_line_pointer = s;
6913
6914 pop_mri_control ();
6915
6916 if (flag_mri)
6917 {
6918 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6919 ++input_line_pointer;
6920 }
6921
6922 demand_empty_rest_of_line ();
6923}
6924
6925/* Handle the MRI WHILE pseudo-op. */
6926
6927static void
31302357 6928s_mri_while (int qual)
252b5132
RH		 6929{
6930 char *s;
6931
6932 struct mri_control_info *n;
6933
6934 s = input_line_pointer;
e1f44d10
NC		 6935 /* We only accept '*' as introduction of comments if preceded by white space
6936 or at first column of a line (I think this can't actually happen here?)
6937 This is important when assembling:
6938 while d0 <ne> 12(a0,d0*2) do
36759679 6939 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6940 while (! (is_end_of_line[(unsigned char) *s]
6941 || (flag_mri
6942 && *s == '*'
6943 && (s == input_line_pointer
6944 || *(s-1) == ' '
6945 || *(s-1) == '\t'))))
252b5132
RH		 6946 s++;
6947 --s;
6948 while (*s == ' ' || *s == '\t')
6949 --s;
6950 if (s - input_line_pointer > 1
6951 && s[-1] == '.')
6952 s -= 2;
6953 if (s - input_line_pointer < 2
6954 || strncasecmp (s - 1, "DO", 2) != 0)
6955 {
6956 as_bad (_("missing do"));
6957 ignore_rest_of_line ();
6958 return;
6959 }
6960
6961 n = push_mri_control (mri_while);
6962
6963 colon (n->next);
6964
6965 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6966 s[1] == '.' ? s[2] : '\0');
6967
6968 input_line_pointer = s + 1;
6969 if (*input_line_pointer == '.')
6970 input_line_pointer += 2;
6971
6972 if (flag_mri)
6973 {
6974 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6975 ++input_line_pointer;
6976 }
6977
6978 demand_empty_rest_of_line ();
6979}
6980
6981/* Handle the MRI ENDW pseudo-op. */
6982
6983static void
31302357 6984s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6985{
6986 char *buf;
6987
6988 if (mri_control_stack == NULL
6989 || mri_control_stack->type != mri_while)
6990 {
6991 as_bad (_("endw without while"));
6992 ignore_rest_of_line ();
6993 return;
6994 }
6995
6996 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6997 sprintf (buf, "bra %s", mri_control_stack->next);
6998 mri_assemble (buf);
6999 free (buf);
7000
7001 colon (mri_control_stack->bottom);
7002
7003 pop_mri_control ();
7004
7005 if (flag_mri)
7006 {
7007 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7008 ++input_line_pointer;
7009 }
7010
7011 demand_empty_rest_of_line ();
7012}
7013\f
31302357
AS		 7014/* md_parse_option
7015 Invocation line includes a switch not recognized by the base assembler.
7016 See if it's a processor-specific option. These are:
7017
7018 -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
7019 -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
7020 Select the architecture. Instructions or features not
7021 supported by the selected architecture cause fatal
7022 errors. More than one may be specified. The default is
7023 -m68020 -m68851 -m68881. Note that -m68008 is a synonym
7024 for -m68000, and -m68882 is a synonym for -m68881.
7025 -[A]m[c]no-68851, -[A]m[c]no-68881
7026 Don't accept 688?1 instructions. (The "c" is kind of silly,
7027 so don't use or document it, but that's the way the parsing
7028 works).
7029
7030 -pic Indicates PIC.
7031 -k Indicates PIC. (Sun 3 only.)
7032 --pcrel
7033 Never turn PC-relative branches into absolute jumps.
7034 --bitwise-or
7035 Permit `|' to be used in expressions. */
252b5132
RH		 7036
7037#ifdef OBJ_ELF
5a38dc70 7038const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7039#else
5a38dc70 7040const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7041#endif
7042
7043struct option md_longopts[] = {
7044#define OPTION_PIC (OPTION_MD_BASE)
7045 {"pic", no_argument, NULL, OPTION_PIC},
7046#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7047 {"register-prefix-optional", no_argument, NULL,
7048 OPTION_REGISTER_PREFIX_OPTIONAL},
7049#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7050 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7051#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7052 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7053#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7054 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7055#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7056 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7057#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7058 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7059#define OPTION_PCREL (OPTION_MD_BASE + 7)
7060 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7061 {NULL, no_argument, NULL, 0}
7062};
bc805888 7063size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7064
7065int
31302357 7066md_parse_option (int c, char *arg)
252b5132
RH		 7067{
7068 switch (c)
7069 {
7070 case 'l': /* -l means keep external to 2 bit offset
36759679 7071 rather than 16 bit one. */
252b5132
RH		 7072 flag_short_refs = 1;
7073 break;
7074
7075 case 'S': /* -S means that jbsr's always turn into
7076 jsr's. */
7077 flag_long_jumps = 1;
7078 break;
7079
28e7409f
NC		 7080 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7081 branches into absolute jumps. */
7082 flag_keep_pcrel = 1;
7083 break;
7084
252b5132
RH		 7085 case 'A':
7086 if (*arg == 'm')
8a104df9 7087 arg++;
36759679 7088 /* Intentional fall-through. */
252b5132
RH		 7089 case 'm':
7090
7091 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7092 {
7093 int i;
7094 unsigned long arch;
252b5132
RH		 7095
7096 arg += 3;
7097 if (*arg == 'm')
7098 {
7099 arg++;
7100 if (arg[0] == 'c' && arg[1] == '6')
7101 arg++;
7102 }
7103 for (i = 0; i < n_archs; i++)
7104 if (!strcmp (arg, archs[i].name))
7105 break;
7106 if (i == n_archs)
329e276d
NC		 7107 return 0;
7108
252b5132
RH		 7109 arch = archs[i].arch;
7110 if (arch == m68881)
7111 no_68881 = 1;
7112 else if (arch == m68851)
7113 no_68851 = 1;
7114 else
329e276d 7115 return 0;
252b5132
RH		 7116 }
7117 else
7118 {
7119 int i;
7120
7121 if (arg[0] == 'c' && arg[1] == '6')
7122 arg++;
7123
7124 for (i = 0; i < n_archs; i++)
7125 if (!strcmp (arg, archs[i].name))
7126 {
7127 unsigned long arch = archs[i].arch;
329e276d 7128
252b5132
RH		 7129 if (cpu_of_arch (arch))
7130 /* It's a cpu spec. */
7131 {
7132 current_architecture &= ~m68000up;
7133 current_architecture |= arch;
990ae22a 7134 current_chip = archs[i].chip;
252b5132
RH		 7135 }
7136 else if (arch == m68881)
7137 {
7138 current_architecture |= m68881;
7139 no_68881 = 0;
7140 }
7141 else if (arch == m68851)
7142 {
7143 current_architecture |= m68851;
7144 no_68851 = 0;
7145 }
7146 else
7147 /* ??? */
7148 abort ();
7149 break;
7150 }
7151 if (i == n_archs)
7152 {
7153 as_bad (_("unrecognized architecture specification `%s'"), arg);
7154 return 0;
7155 }
7156 }
7157 break;
7158
7159 case OPTION_PIC:
7160 case 'k':
7161 flag_want_pic = 1;
36759679 7162 break; /* -pic, Position Independent Code. */
252b5132
RH		 7163
7164 case OPTION_REGISTER_PREFIX_OPTIONAL:
7165 flag_reg_prefix_optional = 1;
7166 reg_prefix_optional_seen = 1;
7167 break;
7168
7169 /* -V: SVR4 argument to print version ID. */
7170 case 'V':
7171 print_version_id ();
7172 break;
7173
7174 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7175 should be emitted or not. FIXME: Not implemented. */
7176 case 'Q':
7177 break;
7178
7179 case OPTION_BITWISE_OR:
7180 {
7181 char *n, *t;
7182 const char *s;
7183
7184 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7185 t = n;
7186 for (s = m68k_comment_chars; *s != '\0'; s++)
7187 if (*s != '|')
7188 *t++ = *s;
7189 *t = '\0';
7190 m68k_comment_chars = n;
7191 }
7192 break;
7193
7194 case OPTION_BASE_SIZE_DEFAULT_16:
7195 m68k_index_width_default = SIZE_WORD;
7196 break;
7197
7198 case OPTION_BASE_SIZE_DEFAULT_32:
7199 m68k_index_width_default = SIZE_LONG;
7200 break;
7201
7202 case OPTION_DISP_SIZE_DEFAULT_16:
7203 m68k_rel32 = 0;
7204 m68k_rel32_from_cmdline = 1;
7205 break;
7206
7207 case OPTION_DISP_SIZE_DEFAULT_32:
7208 m68k_rel32 = 1;
7209 m68k_rel32_from_cmdline = 1;
7210 break;
7211
7212 default:
7213 return 0;
7214 }
7215
7216 return 1;
7217}
7218
7219void
31302357 7220md_show_usage (FILE *stream)
252b5132 7221{
76f57f3a 7222 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7223 int i;
7224 unsigned int default_arch;
76f57f3a 7225
8a104df9 7226 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7227 if (*default_cpu == 'm')
7228 default_cpu++;
7229 for (i = 0; i < n_archs; i++)
7230 {
7231 if (strcasecmp (default_cpu, archs[i].name) == 0)
7232 {
7233 default_arch = archs[i].arch;
7234 for (i = 0; i < n_archs; i++)
7235 {
7236 if (archs[i].arch == default_arch
7237 && !archs[i].alias)
7238 {
7239 default_cpu = archs[i].name;
7240 break;
7241 }
7242 }
7243 }
7244 }
7245
bc805888 7246 fprintf (stream, _("\
252b5132
RH		 7247680X0 options:\n\
7248-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 7249-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7250-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6b6e92f4
NC		 7251-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7252-m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
76f57f3a 7253 specify variant of 680X0 architecture [default %s]\n\
252b5132
RH		 7254-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7255 target has/lacks floating-point coprocessor\n\
76f57f3a
JT		 7256 [default yes for 68020, 68030, and cpu32]\n"),
7257 default_cpu);
bc805888 7258 fprintf (stream, _("\
252b5132
RH		 7259-m68851 | -mno-68851\n\
7260 target has/lacks memory-management unit coprocessor\n\
7261 [default yes for 68020 and up]\n\
7262-pic, -k generate position independent code\n\
7263-S turn jbsr into jsr\n\
28e7409f 7264--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7265--register-prefix-optional\n\
7266 recognize register names without prefix character\n\
7267--bitwise-or do not treat `|' as a comment character\n"));
7268 fprintf (stream, _("\
7269--base-size-default-16 base reg without size is 16 bits\n\
7270--base-size-default-32 base reg without size is 32 bits (default)\n\
7271--disp-size-default-16 displacement with unknown size is 16 bits\n\
7272--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7273}
7274\f
7275#ifdef TEST2
7276
7277/* TEST2: Test md_assemble() */
36759679
NC		 7278/* Warning, this routine probably doesn't work anymore. */
7279int
31302357 7280main (void)
252b5132
RH		 7281{
7282 struct m68k_it the_ins;
7283 char buf[120];
7284 char *cp;
7285 int n;
7286
7287 m68k_ip_begin ();
7288 for (;;)
7289 {
7290 if (!gets (buf) || !*buf)
7291 break;
7292 if (buf[0] == '|' || buf[1] == '.')
7293 continue;
7294 for (cp = buf; *cp; cp++)
7295 if (*cp == '\t')
7296 *cp = ' ';
7297 if (is_label (buf))
7298 continue;
7299 memset (&the_ins, '\0', sizeof (the_ins));
7300 m68k_ip (&the_ins, buf);
7301 if (the_ins.error)
7302 {
7303 printf (_("Error %s in %s\n"), the_ins.error, buf);
7304 }
7305 else
7306 {
7307 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7308 for (n = 0; n < the_ins.numo; n++)
7309 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7310 printf (" ");
7311 print_the_insn (&the_ins.opcode[0], stdout);
7312 (void) putchar ('\n');
7313 }
7314 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7315 {
7316 if (the_ins.operands[n].error)
7317 {
7318 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7319 continue;
7320 }
31302357
AS		 7321 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7322 the_ins.operands[n].reg);
252b5132 7323 if (the_ins.operands[n].b_const)
31302357
AS		 7324 printf ("Constant: '%.*s', ",
7325 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7326 the_ins.operands[n].b_const);
7327 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7328 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7329 if (the_ins.operands[n].b_iadd)
31302357
AS		 7330 printf ("Iadd: '%.*s',",
7331 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7332 the_ins.operands[n].b_iadd);
7333 putchar ('\n');
252b5132
RH		 7334 }
7335 }
7336 m68k_ip_end ();
7337 return 0;
7338}
7339
31302357
AS		 7340int
7341is_label (char *str)
252b5132
RH		 7342{
7343 while (*str == ' ')
7344 str++;
7345 while (*str && *str != ' ')
7346 str++;
7347 if (str[-1] == ':' || str[1] == '=')
7348 return 1;
7349 return 0;
7350}
7351
7352#endif
7353
7354/* Possible states for relaxation:
7355
7356 0 0 branch offset byte (bra, etc)
7357 0 1 word
7358 0 2 long
7359
7360 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7361 1 1 word
7362 1 2 long
7363
7364 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7365 2 1 word-long
7366 2 2 long-word
7367 2 3 long-long
7368
7369 */
7370
7371/* We have no need to default values of symbols. */
7372
252b5132 7373symbolS *
31302357 7374md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7375{
7376 return 0;
7377}
7378
7379/* Round up a section size to the appropriate boundary. */
7380valueT
31302357 7381md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7382{
7383#ifdef OBJ_AOUT
7384#ifdef BFD_ASSEMBLER
7385 /* For a.out, force the section size to be aligned. If we don't do
7386 this, BFD will align it for us, but it will not write out the
7387 final bytes of the section. This may be a bug in BFD, but it is
7388 easier to fix it here since that is how the other a.out targets
7389 work. */
7390 int align;
7391
7392 align = bfd_get_section_alignment (stdoutput, segment);
7393 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7394#endif
7395#endif
7396
7397 return size;
7398}
7399
7400/* Exactly what point is a PC-relative offset relative TO?
7401 On the 68k, it is relative to the address of the first extension
7402 word. The difference between the addresses of the offset and the
92774660 7403 first extension word is stored in fx_pcrel_adjust. */
252b5132 7404long
31302357 7405md_pcrel_from (fixS *fixP)
252b5132
RH		 7406{
7407 int adjust;
7408
8390138c
AS		 7409 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7410 sign extend the value here. */
7411 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7412 if (adjust == 64)
7413 adjust = -1;
7414 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7415}
7416
7417#ifndef BFD_ASSEMBLER
7418#ifdef OBJ_COFF
7419
252b5132 7420void
31302357 7421tc_coff_symbol_emit_hook (symbolS *ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7422{
7423}
7424
7425int
31302357 7426tc_coff_sizemachdep (fragS *frag)
252b5132
RH		 7427{
7428 switch (frag->fr_subtype & 0x3)
7429 {
7430 case BYTE:
7431 return 1;
7432 case SHORT:
7433 return 2;
7434 case LONG:
7435 return 4;
7436 default:
7437 abort ();
7438 return 0;
7439 }
7440}
7441
7442#endif
7443#endif
31302357 7444
0d96863f 7445#ifdef OBJ_ELF
8a104df9 7446void
31302357 7447m68k_elf_final_processing (void)
0d96863f 7448{
36759679 7449 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9
KH		 7450 if (cpu_of_arch (current_architecture) & cpu32)
7451 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7452 else if ((cpu_of_arch (current_architecture) & m68000up)
7453 && !(cpu_of_arch (current_architecture) & m68020up))
7454 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
0d96863f
CM		 7455}
7456#endif
c04898f8
AS		 7457
7458int
7459tc_m68k_regname_to_dw2regnum (const char *regname)
7460{
7461 unsigned int regnum;
7462 static const char *const regnames[] =
7463 {
7464 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7465 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7466 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7467 "pc"
7468 };
7469
7470 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7471 if (strcmp (regname, regnames[regnum]) == 0)
7472 return regnum;
7473
7474 return -1;
7475}
7476
7477void
7478tc_m68k_frame_initial_instructions (void)
7479{
7480 static int sp_regno = -1;
7481
7482 if (sp_regno < 0)
7483 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7484
7485 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7486 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7487}
GDB Binutils - Deliverables
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