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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4
NC		 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
252b5132
RH		 4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23#include <ctype.h>
24#include "as.h"
25#include "obstack.h"
26#include "subsegs.h"
27
28#include "opcode/m68k.h"
29#include "m68k-parse.h"
30
0d96863f
CM		 31#if defined (OBJ_ELF)
32#include "elf/m68k.h"
33#endif
34
252b5132
RH		 35/* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39#if defined (TE_SVR4) || defined (TE_DELTA)
40const char *m68k_comment_chars = "|#";
41#else
42const char *m68k_comment_chars = "|";
43#endif
44
45/* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48/* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
92774660
KH		 50 #NO_APP at the beginning of its output. */
51/* Also note that comments like this one will always work. */
252b5132
RH		 52const char line_comment_chars[] = "#*";
53
63a0b638 54const char line_separator_chars[] = ";";
252b5132
RH		 55
56/* Chars that can be used to separate mant from exp in floating point nums */
57CONST char EXP_CHARS[] = "eE";
58
59/* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
61
62CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63
64/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
67
68const int md_reloc_size = 8; /* Size of relocation record */
69
70/* Are we trying to generate PIC code? If so, absolute references
71 ought to be made into linkage table references or pc-relative
92774660 72 references. Not implemented. For ELF there are other means
252b5132
RH		 73 to denote pic relocations. */
74int flag_want_pic;
75
76static int flag_short_refs; /* -l option */
77static int flag_long_jumps; /* -S option */
28e7409f 78static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 79
80#ifdef REGISTER_PREFIX_OPTIONAL
81int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
82#else
83int flag_reg_prefix_optional;
84#endif
85
86/* Whether --register-prefix-optional was used on the command line. */
87static int reg_prefix_optional_seen;
88
89/* The floating point coprocessor to use by default. */
90static enum m68k_register m68k_float_copnum = COP1;
91
92/* If this is non-zero, then references to number(%pc) will be taken
93 to refer to number, rather than to %pc + number. */
94static int m68k_abspcadd;
95
96/* If this is non-zero, then the quick forms of the move, add, and sub
97 instructions are used when possible. */
98static int m68k_quick = 1;
99
100/* If this is non-zero, then if the size is not specified for a base
101 or outer displacement, the assembler assumes that the size should
102 be 32 bits. */
103static int m68k_rel32 = 1;
104
105/* This is non-zero if m68k_rel32 was set from the command line. */
106static int m68k_rel32_from_cmdline;
107
108/* The default width to use for an index register when using a base
109 displacement. */
110static enum m68k_size m68k_index_width_default = SIZE_LONG;
111
112/* We want to warn if any text labels are misaligned. In order to get
113 the right line number, we need to record the line number for each
114 label. */
115
116struct label_line
117{
118 struct label_line *next;
119 symbolS *label;
120 char *file;
121 unsigned int line;
122 int text;
123};
124
125/* The list of labels. */
126
127static struct label_line *labels;
128
129/* The current label. */
130
131static struct label_line *current_label;
132
133/* Its an arbitrary name: This means I don't approve of it */
134/* See flames below */
135static struct obstack robyn;
136
252b5132
RH		 137struct m68k_incant
138 {
139 const char *m_operands;
140 unsigned long m_opcode;
141 short m_opnum;
142 short m_codenum;
143 int m_arch;
144 struct m68k_incant *m_next;
145 };
146
147#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148#define gettwo(x) (((x)->m_opcode)&0xffff)
149
150static const enum m68k_register m68000_control_regs[] = { 0 };
151static const enum m68k_register m68010_control_regs[] = {
152 SFC, DFC, USP, VBR,
153 0
154};
155static const enum m68k_register m68020_control_regs[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
157 0
158};
159static const enum m68k_register m68040_control_regs[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
162 0
163};
164static const enum m68k_register m68060_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
167 0
168};
6da466c7 169static const enum m68k_register mcf_control_regs[] = {
92774660 170 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
252b5132
RH		 171 RAMBAR0, RAMBAR1, MBAR,
172 0
173};
174#define cpu32_control_regs m68010_control_regs
175
176static const enum m68k_register *control_regs;
177
178/* internal form of a 68020 instruction */
179struct m68k_it
180{
181 const char *error;
182 const char *args; /* list of opcode info */
183 int numargs;
184
185 int numo; /* Number of shorts in opcode */
186 short opcode[11];
187
188 struct m68k_op operands[6];
189
190 int nexp; /* number of exprs in use */
191 struct m68k_exp exprs[4];
192
193 int nfrag; /* Number of frags we have to produce */
194 struct
195 {
196 int fragoff; /* Where in the current opcode the frag ends */
197 symbolS *fadd;
198 offsetT foff;
199 int fragty;
200 }
201 fragb[4];
202
203 int nrel; /* Num of reloc strucs in use */
204 struct
205 {
206 int n;
207 expressionS exp;
208 char wid;
209 char pcrel;
210 /* In a pc relative address the difference between the address
211 of the offset and the address that the offset is relative
212 to. This depends on the addressing mode. Basically this
213 is the value to put in the offset field to address the
214 first byte of the offset, without regarding the special
215 significance of some values (in the branch instruction, for
216 example). */
217 int pcrel_fix;
218#ifdef OBJ_ELF
219 /* Whether this expression needs special pic relocation, and if
220 so, which. */
221 enum pic_relocation pic_reloc;
222#endif
223 }
224 reloc[5]; /* Five is enough??? */
225};
226
6da466c7 227#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 228#define float_of_arch(x) ((x) & mfloat)
229#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 230#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 231
232/* Macros for determining if cpu supports a specific addressing mode */
dc84e067 233#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
252b5132
RH		 234
235static struct m68k_it the_ins; /* the instruction being assembled */
236
237#define op(ex) ((ex)->exp.X_op)
238#define adds(ex) ((ex)->exp.X_add_symbol)
239#define subs(ex) ((ex)->exp.X_op_symbol)
240#define offs(ex) ((ex)->exp.X_add_number)
241
242/* Macros for adding things to the m68k_it struct */
243
244#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
245
246/* Static functions. */
247
248static void insop PARAMS ((int, const struct m68k_incant *));
249static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
250static void add_frag PARAMS ((symbolS *, offsetT, int));
251
252/* Like addword, but goes BEFORE general operands */
253static void
254insop (w, opcode)
255 int w;
256 const struct m68k_incant *opcode;
257{
258 int z;
259 for(z=the_ins.numo;z>opcode->m_codenum;--z)
260 the_ins.opcode[z]=the_ins.opcode[z-1];
261 for(z=0;z<the_ins.nrel;z++)
262 the_ins.reloc[z].n+=2;
263 for (z = 0; z < the_ins.nfrag; z++)
264 the_ins.fragb[z].fragoff++;
265 the_ins.opcode[opcode->m_codenum]=w;
266 the_ins.numo++;
267}
268
269/* The numo+1 kludge is so we can hit the low order byte of the prev word.
270 Blecch. */
271static void
272add_fix (width, exp, pc_rel, pc_fix)
273 int width;
274 struct m68k_exp *exp;
275 int pc_rel;
276 int pc_fix;
277{
278 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
279 ? (the_ins.numo*2-1)
280 : (((width)=='b')
281 ? (the_ins.numo*2+1)
282 : (the_ins.numo*2)));
283 the_ins.reloc[the_ins.nrel].exp = exp->exp;
284 the_ins.reloc[the_ins.nrel].wid = width;
285 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
286#ifdef OBJ_ELF
287 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
288#endif
289 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
290}
291
292/* Cause an extra frag to be generated here, inserting up to 10 bytes
293 (that value is chosen in the frag_var call in md_assemble). TYPE
294 is the subtype of the frag to be generated; its primary type is
295 rs_machine_dependent.
296
297 The TYPE parameter is also used by md_convert_frag_1 and
298 md_estimate_size_before_relax. The appropriate type of fixup will
299 be emitted by md_convert_frag_1.
300
301 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
302static void
303add_frag (add, off, type)
304 symbolS *add;
305 offsetT off;
306 int type;
307{
308 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
309 the_ins.fragb[the_ins.nfrag].fadd=add;
310 the_ins.fragb[the_ins.nfrag].foff=off;
311 the_ins.fragb[the_ins.nfrag++].fragty=type;
312}
313
314#define isvar(ex) \
315 (op (ex) != O_constant && op (ex) != O_big)
316
317static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
318static int get_num PARAMS ((struct m68k_exp *exp, int ok));
319static void m68k_ip PARAMS ((char *));
320static void insert_reg PARAMS ((const char *, int));
321static void select_control_regs PARAMS ((void));
322static void init_regtable PARAMS ((void));
323static int reverse_16_bits PARAMS ((int in));
324static int reverse_8_bits PARAMS ((int in));
325static void install_gen_operand PARAMS ((int mode, int val));
326static void install_operand PARAMS ((int mode, int val));
327static void s_bss PARAMS ((int));
328static void s_data1 PARAMS ((int));
329static void s_data2 PARAMS ((int));
330static void s_even PARAMS ((int));
331static void s_proc PARAMS ((int));
332static void mri_chip PARAMS ((void));
333static void s_chip PARAMS ((int));
334static void s_fopt PARAMS ((int));
335static void s_opt PARAMS ((int));
336static void s_reg PARAMS ((int));
337static void s_restore PARAMS ((int));
338static void s_save PARAMS ((int));
339static void s_mri_if PARAMS ((int));
340static void s_mri_else PARAMS ((int));
341static void s_mri_endi PARAMS ((int));
342static void s_mri_break PARAMS ((int));
343static void s_mri_next PARAMS ((int));
344static void s_mri_for PARAMS ((int));
345static void s_mri_endf PARAMS ((int));
346static void s_mri_repeat PARAMS ((int));
347static void s_mri_until PARAMS ((int));
348static void s_mri_while PARAMS ((int));
349static void s_mri_endw PARAMS ((int));
350static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
351static void md_convert_frag_1 PARAMS ((fragS *));
352
353static int current_architecture;
354
dc84e067
NC		 355struct m68k_cpu
356 {
357 unsigned long arch;
358 const char *name;
359 int alias;
360 };
252b5132 361
dc84e067
NC		 362static const struct m68k_cpu archs[] =
363 {
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
378 cpus. */
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
407 };
252b5132
RH		 408
409static const int n_archs = sizeof (archs) / sizeof (archs[0]);
410
151337e8
NC		 411/* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
252b5132 413
151337e8
NC		 414/* Macros used in the relaxation code. */
415#define TAB(x,y) (((x) << 2) + (y))
416#define TABTYPE(x) ((x) >> 2)
417
418/* Relaxation states. */
419#define BYTE 0
420#define SHORT 1
421#define LONG 2
422#define SZ_UNDEF 3
423
424/* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
433
434#define BRANCHBWL 1 /* branch byte, word, or long */
435#define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
436#define BRABSJCOND 3 /* absolute jump for LONG, conditional */
437#define BRANCHBW 4 /* branch byte or word */
438
439/* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
446
447#define FBRANCH 5 /* coprocessor branch */
448#define DBCCLBR 6 /* DBcc relaxable with a long branch */
449#define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
450
451/* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
461
462#define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
463#define PCINDEX 9 /* PC+displacement+index */
464#define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
252b5132
RH		 465
466/* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
468
469/* The fields are:
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
474 */
475relax_typeS md_relax_table[] =
476{
477 {1, 1, 0, 0}, /* First entries aren't used */
478 {1, 1, 0, 0}, /* For no good reason except */
479 {1, 1, 0, 0}, /* that the VAX doesn't either */
480 {1, 1, 0, 0},
481
151337e8
NC		 482 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
483 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
252b5132
RH		 484 {0, 0, 4, 0},
485 {1, 1, 0, 0},
486
151337e8
NC		 487 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
488 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
252b5132
RH		 489 {0, 0, 4, 0},
490 {1, 1, 0, 0},
491
151337e8
NC		 492 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
493 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
494 {0, 0, 6, 0},
495 {1, 1, 0, 0},
496
497 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
498 {0, 0, 2, 0},
499 {1, 1, 0, 0},
500 {1, 1, 0, 0},
501
502 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
503 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
252b5132
RH		 504 {0, 0, 4, 0},
505 {1, 1, 0, 0},
506
151337e8
NC		 507 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
508 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
509 {0, 0, 10, 0},
252b5132
RH		 510 {1, 1, 0, 0},
511
512 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
151337e8
NC		 513 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
514 {0, 0, 10, 0},
252b5132
RH		 515 {1, 1, 0, 0},
516
151337e8
NC		 517 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
518 {32767, -32768, 2, TAB (PCREL1632, LONG)},
252b5132
RH		 519 {0, 0, 6, 0},
520 {1, 1, 0, 0},
521
252b5132
RH		 522 {125, -130, 0, TAB (PCINDEX, SHORT)},
523 {32765, -32770, 2, TAB (PCINDEX, LONG)},
524 {0, 0, 4, 0},
525 {1, 1, 0, 0},
151337e8
NC		 526
527 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
528 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
529 {0, 0, 4, 0},
530 {1, 1, 0, 0},
252b5132
RH		 531};
532
533/* These are the machine dependent pseudo-ops. These are included so
534 the assembler can work on the output from the SUN C compiler, which
535 generates these.
536 */
537
538/* This table describes all the machine specific pseudo-ops the assembler
539 has to support. The fields are:
540 pseudo-op name without dot
541 function to call to execute this pseudo-op
542 Integer arg to pass to the function
543 */
544const pseudo_typeS md_pseudo_table[] =
545{
546 {"data1", s_data1, 0},
547 {"data2", s_data2, 0},
548 {"bss", s_bss, 0},
549 {"even", s_even, 0},
550 {"skip", s_space, 0},
551 {"proc", s_proc, 0},
552#if defined (TE_SUN3) || defined (OBJ_ELF)
553 {"align", s_align_bytes, 0},
554#endif
555#ifdef OBJ_ELF
556 {"swbeg", s_ignore, 0},
557#endif
558 {"extend", float_cons, 'x'},
559 {"ldouble", float_cons, 'x'},
560
561 /* The following pseudo-ops are supported for MRI compatibility. */
562 {"chip", s_chip, 0},
563 {"comline", s_space, 1},
564 {"fopt", s_fopt, 0},
565 {"mask2", s_ignore, 0},
566 {"opt", s_opt, 0},
567 {"reg", s_reg, 0},
568 {"restore", s_restore, 0},
569 {"save", s_save, 0},
570
571 {"if", s_mri_if, 0},
572 {"if.b", s_mri_if, 'b'},
573 {"if.w", s_mri_if, 'w'},
574 {"if.l", s_mri_if, 'l'},
575 {"else", s_mri_else, 0},
576 {"else.s", s_mri_else, 's'},
577 {"else.l", s_mri_else, 'l'},
578 {"endi", s_mri_endi, 0},
579 {"break", s_mri_break, 0},
580 {"break.s", s_mri_break, 's'},
581 {"break.l", s_mri_break, 'l'},
582 {"next", s_mri_next, 0},
583 {"next.s", s_mri_next, 's'},
584 {"next.l", s_mri_next, 'l'},
585 {"for", s_mri_for, 0},
586 {"for.b", s_mri_for, 'b'},
587 {"for.w", s_mri_for, 'w'},
588 {"for.l", s_mri_for, 'l'},
589 {"endf", s_mri_endf, 0},
590 {"repeat", s_mri_repeat, 0},
591 {"until", s_mri_until, 0},
592 {"until.b", s_mri_until, 'b'},
593 {"until.w", s_mri_until, 'w'},
594 {"until.l", s_mri_until, 'l'},
595 {"while", s_mri_while, 0},
596 {"while.b", s_mri_while, 'b'},
597 {"while.w", s_mri_while, 'w'},
598 {"while.l", s_mri_while, 'l'},
599 {"endw", s_mri_endw, 0},
600
601 {0, 0, 0}
602};
603
252b5132
RH		 604/* The mote pseudo ops are put into the opcode table, since they
605 don't start with a . they look like opcodes to gas.
606 */
607
608#ifdef M68KCOFF
609extern void obj_coff_section PARAMS ((int));
610#endif
611
612CONST pseudo_typeS mote_pseudo_table[] =
613{
614
615 {"dcl", cons, 4},
616 {"dc", cons, 2},
617 {"dcw", cons, 2},
618 {"dcb", cons, 1},
619
620 {"dsl", s_space, 4},
621 {"ds", s_space, 2},
622 {"dsw", s_space, 2},
623 {"dsb", s_space, 1},
624
625 {"xdef", s_globl, 0},
626#ifdef OBJ_ELF
627 {"align", s_align_bytes, 0},
628#else
629 {"align", s_align_ptwo, 0},
630#endif
631#ifdef M68KCOFF
632 {"sect", obj_coff_section, 0},
633 {"section", obj_coff_section, 0},
634#endif
635 {0, 0, 0}
636};
637
638#define issbyte(x) ((x)>=-128 && (x)<=127)
639#define isubyte(x) ((x)>=0 && (x)<=255)
640#define issword(x) ((x)>=-32768 && (x)<=32767)
641#define isuword(x) ((x)>=0 && (x)<=65535)
642
643#define isbyte(x) ((x)>= -255 && (x)<=255)
644#define isword(x) ((x)>=-65536 && (x)<=65535)
645#define islong(x) (1)
646
647extern char *input_line_pointer;
648
649static char mklower_table[256];
bc805888 650#define mklower(c) (mklower_table[(unsigned char) (c)])
252b5132
RH		 651static char notend_table[256];
652static char alt_notend_table[256];
653#define notend(s) \
654 (! (notend_table[(unsigned char) *s] \
655 || (*s == ':' \
656 && alt_notend_table[(unsigned char) s[1]])))
657
658#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
659
660#ifdef NO_PCREL_RELOCS
661
662int
663make_pcrel_absolute(fixP, add_number)
664 fixS *fixP;
665 long *add_number;
666{
667 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
668
669 /* rewrite the PC relative instructions to absolute address ones.
670 * these are rumoured to be faster, and the apollo linker refuses
671 * to deal with the PC relative relocations.
672 */
673 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
674 {
675 opcode[0] = 0x4e;
676 opcode[1] = 0xf9;
677 }
678 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
679 {
680 opcode[0] = 0x4e;
681 opcode[1] = 0xb9;
682 }
683 else
684 as_fatal (_("Unknown PC relative instruction"));
685 *add_number -= 4;
686 return 0;
687}
688
689#endif /* NO_PCREL_RELOCS */
690
691short
692tc_coff_fix2rtype (fixP)
693 fixS *fixP;
694{
695 if (fixP->fx_tcbit && fixP->fx_size == 4)
696 return R_RELLONG_NEG;
697#ifdef NO_PCREL_RELOCS
698 know (fixP->fx_pcrel == 0);
699 return (fixP->fx_size == 1 ? R_RELBYTE
700 : fixP->fx_size == 2 ? R_DIR16
701 : R_DIR32);
702#else
703 return (fixP->fx_pcrel ?
704 (fixP->fx_size == 1 ? R_PCRBYTE :
705 fixP->fx_size == 2 ? R_PCRWORD :
706 R_PCRLONG) :
707 (fixP->fx_size == 1 ? R_RELBYTE :
708 fixP->fx_size == 2 ? R_RELWORD :
709 R_RELLONG));
710#endif
711}
712
713#endif
714
715#ifdef OBJ_ELF
716
c801568a
AM		 717/* Return zero if the reference to SYMBOL from within the same segment may
718 be relaxed. */
719
720/* On an ELF system, we can't relax an externally visible symbol,
721 because it may be overridden by a shared library. However, if
722 TARGET_OS is "elf", then we presume that we are assembling for an
723 embedded system, in which case we don't have to worry about shared
724 libraries, and we can relax any external sym. */
725
726#define relaxable_symbol(symbol) \
727 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
728 || S_IS_WEAK (symbol)))
729
252b5132
RH		 730/* Compute the relocation code for a fixup of SIZE bytes, using pc
731 relative relocation if PCREL is non-zero. PIC says whether a special
732 pic relocation was requested. */
733
734static bfd_reloc_code_real_type get_reloc_code
735 PARAMS ((int, int, enum pic_relocation));
736
737static bfd_reloc_code_real_type
738get_reloc_code (size, pcrel, pic)
739 int size;
740 int pcrel;
741 enum pic_relocation pic;
742{
743 switch (pic)
744 {
745 case pic_got_pcrel:
746 switch (size)
747 {
748 case 1:
749 return BFD_RELOC_8_GOT_PCREL;
750 case 2:
751 return BFD_RELOC_16_GOT_PCREL;
752 case 4:
753 return BFD_RELOC_32_GOT_PCREL;
754 }
755 break;
756
757 case pic_got_off:
758 switch (size)
759 {
760 case 1:
761 return BFD_RELOC_8_GOTOFF;
762 case 2:
763 return BFD_RELOC_16_GOTOFF;
764 case 4:
765 return BFD_RELOC_32_GOTOFF;
766 }
767 break;
768
769 case pic_plt_pcrel:
770 switch (size)
771 {
772 case 1:
773 return BFD_RELOC_8_PLT_PCREL;
774 case 2:
775 return BFD_RELOC_16_PLT_PCREL;
776 case 4:
777 return BFD_RELOC_32_PLT_PCREL;
778 }
779 break;
780
781 case pic_plt_off:
782 switch (size)
783 {
784 case 1:
785 return BFD_RELOC_8_PLTOFF;
786 case 2:
787 return BFD_RELOC_16_PLTOFF;
788 case 4:
789 return BFD_RELOC_32_PLTOFF;
790 }
791 break;
792
793 case pic_none:
794 if (pcrel)
795 {
796 switch (size)
797 {
798 case 1:
799 return BFD_RELOC_8_PCREL;
800 case 2:
801 return BFD_RELOC_16_PCREL;
802 case 4:
803 return BFD_RELOC_32_PCREL;
804 }
805 }
806 else
807 {
808 switch (size)
809 {
810 case 1:
811 return BFD_RELOC_8;
812 case 2:
813 return BFD_RELOC_16;
814 case 4:
815 return BFD_RELOC_32;
816 }
817 }
818 }
819
820 if (pcrel)
821 {
822 if (pic == pic_none)
823 as_bad (_("Can not do %d byte pc-relative relocation"), size);
824 else
825 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
826 }
827 else
828 {
829 if (pic == pic_none)
830 as_bad (_("Can not do %d byte relocation"), size);
831 else
832 as_bad (_("Can not do %d byte pic relocation"), size);
833 }
834
835 return BFD_RELOC_NONE;
836}
837
838/* Here we decide which fixups can be adjusted to make them relative
839 to the beginning of the section instead of the symbol. Basically
840 we need to make sure that the dynamic relocations are done
841 correctly, so in some cases we force the original symbol to be
842 used. */
843int
844tc_m68k_fix_adjustable (fixP)
845 fixS *fixP;
846{
92774660 847 /* Prevent all adjustments to global symbols. */
c801568a 848 if (! relaxable_symbol (fixP->fx_addsy))
252b5132
RH		 849 return 0;
850
851 /* adjust_reloc_syms doesn't know about the GOT */
852 switch (fixP->fx_r_type)
853 {
854 case BFD_RELOC_8_GOT_PCREL:
855 case BFD_RELOC_16_GOT_PCREL:
856 case BFD_RELOC_32_GOT_PCREL:
857 case BFD_RELOC_8_GOTOFF:
858 case BFD_RELOC_16_GOTOFF:
859 case BFD_RELOC_32_GOTOFF:
860 case BFD_RELOC_8_PLT_PCREL:
861 case BFD_RELOC_16_PLT_PCREL:
862 case BFD_RELOC_32_PLT_PCREL:
863 case BFD_RELOC_8_PLTOFF:
864 case BFD_RELOC_16_PLTOFF:
865 case BFD_RELOC_32_PLTOFF:
866 return 0;
867
868 case BFD_RELOC_VTABLE_INHERIT:
869 case BFD_RELOC_VTABLE_ENTRY:
870 return 0;
871
872 default:
873 return 1;
874 }
875}
876
877#else /* !OBJ_ELF */
878
879#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
880
c801568a
AM		 881#define relaxable_symbol(symbol) 1
882
252b5132
RH		 883#endif /* OBJ_ELF */
884
885#ifdef BFD_ASSEMBLER
886
887arelent *
888tc_gen_reloc (section, fixp)
889 asection *section;
890 fixS *fixp;
891{
892 arelent *reloc;
893 bfd_reloc_code_real_type code;
894
8ec6253e
NC		 895 /* If the tcbit is set, then this was a fixup of a negative value
896 that was never resolved. We do not have a reloc to handle this,
897 so just return. We assume that other code will have detected this
898 situation and produced a helpful error message, so we just tell the
899 user that the reloc cannot be produced. */
252b5132 900 if (fixp->fx_tcbit)
8ec6253e
NC		 901 {
902 if (fixp->fx_addsy)
b091f402
AM		 903 as_bad_where (fixp->fx_file, fixp->fx_line,
904 _("Unable to produce reloc against symbol '%s'"),
905 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 906 return NULL;
907 }
252b5132
RH		 908
909 if (fixp->fx_r_type != BFD_RELOC_NONE)
910 {
911 code = fixp->fx_r_type;
912
913 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
914 that fixup_segment converted a non-PC relative reloc into a
915 PC relative reloc. In such a case, we need to convert the
916 reloc code. */
917 if (fixp->fx_pcrel)
918 {
919 switch (code)
920 {
921 case BFD_RELOC_8:
922 code = BFD_RELOC_8_PCREL;
923 break;
924 case BFD_RELOC_16:
925 code = BFD_RELOC_16_PCREL;
926 break;
927 case BFD_RELOC_32:
928 code = BFD_RELOC_32_PCREL;
929 break;
930 case BFD_RELOC_8_PCREL:
931 case BFD_RELOC_16_PCREL:
932 case BFD_RELOC_32_PCREL:
933 case BFD_RELOC_8_GOT_PCREL:
934 case BFD_RELOC_16_GOT_PCREL:
935 case BFD_RELOC_32_GOT_PCREL:
936 case BFD_RELOC_8_GOTOFF:
937 case BFD_RELOC_16_GOTOFF:
938 case BFD_RELOC_32_GOTOFF:
939 case BFD_RELOC_8_PLT_PCREL:
940 case BFD_RELOC_16_PLT_PCREL:
941 case BFD_RELOC_32_PLT_PCREL:
942 case BFD_RELOC_8_PLTOFF:
943 case BFD_RELOC_16_PLTOFF:
944 case BFD_RELOC_32_PLTOFF:
945 break;
946 default:
947 as_bad_where (fixp->fx_file, fixp->fx_line,
948 _("Cannot make %s relocation PC relative"),
949 bfd_get_reloc_code_name (code));
950 }
951 }
952 }
953 else
954 {
955#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
956 switch (F (fixp->fx_size, fixp->fx_pcrel))
957 {
958#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
959 MAP (1, 0, BFD_RELOC_8);
960 MAP (2, 0, BFD_RELOC_16);
961 MAP (4, 0, BFD_RELOC_32);
962 MAP (1, 1, BFD_RELOC_8_PCREL);
963 MAP (2, 1, BFD_RELOC_16_PCREL);
964 MAP (4, 1, BFD_RELOC_32_PCREL);
965 default:
966 abort ();
967 }
968 }
969#undef F
970#undef MAP
971
972 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 973 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
974 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 975 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
976#ifndef OBJ_ELF
977 if (fixp->fx_pcrel)
978 reloc->addend = fixp->fx_addnumber;
979 else
980 reloc->addend = 0;
981#else
982 if (!fixp->fx_pcrel)
983 reloc->addend = fixp->fx_addnumber;
984 else
985 reloc->addend = (section->vma
8390138c
AS		 986 /* Explicit sign extension in case char is
987 unsigned. */
988 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 989 + fixp->fx_addnumber
990 + md_pcrel_from (fixp));
991#endif
992
993 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
994 assert (reloc->howto != 0);
995
996 return reloc;
997}
998
999#endif /* BFD_ASSEMBLER */
1000
252b5132
RH		 1001/* Handle of the OPCODE hash table. NULL means any use before
1002 m68k_ip_begin() will crash. */
1003static struct hash_control *op_hash;
1004\f
1005/* Assemble an m68k instruction. */
1006
1007static void
1008m68k_ip (instring)
1009 char *instring;
1010{
1011 register char *p;
1012 register struct m68k_op *opP;
1013 register const struct m68k_incant *opcode;
1014 register const char *s;
1015 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1016 char *pdot, *pdotmove;
1017 enum m68k_size siz1, siz2;
1018 char c;
1019 int losing;
1020 int opsfound;
1021 LITTLENUM_TYPE words[6];
1022 LITTLENUM_TYPE *wordp;
1023 unsigned long ok_arch = 0;
1024
1025 if (*instring == ' ')
1026 instring++; /* skip leading whitespace */
1027
1028 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1029 or exactly 1 space. */
252b5132
RH		 1030 pdot = 0;
1031 for (p = instring; *p != '\0'; p++)
1032 {
1033 if (*p == ' ')
1034 break;
1035 if (*p == '.')
1036 pdot = p;
1037 }
1038
1039 if (p == instring)
1040 {
1041 the_ins.error = _("No operator");
1042 return;
1043 }
1044
1045 /* p now points to the end of the opcode name, probably whitespace.
1046 Make sure the name is null terminated by clobbering the
1047 whitespace, look it up in the hash table, then fix it back.
1048 Remove a dot, first, since the opcode tables have none. */
1049 if (pdot != NULL)
1050 {
1051 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1052 *pdotmove = pdotmove[1];
1053 p--;
1054 }
1055
1056 c = *p;
1057 *p = '\0';
1058 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1059 *p = c;
1060
1061 if (pdot != NULL)
1062 {
1063 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1064 *pdotmove = pdotmove[-1];
1065 *pdot = '.';
1066 ++p;
1067 }
1068
1069 if (opcode == NULL)
1070 {
1071 the_ins.error = _("Unknown operator");
1072 return;
1073 }
1074
1075 /* found a legitimate opcode, start matching operands */
1076 while (*p == ' ')
1077 ++p;
1078
1079 if (opcode->m_operands == 0)
1080 {
1081 char *old = input_line_pointer;
1082 *old = '\n';
1083 input_line_pointer = p;
1084 /* Ahh - it's a motorola style psuedo op */
1085 mote_pseudo_table[opcode->m_opnum].poc_handler
1086 (mote_pseudo_table[opcode->m_opnum].poc_val);
1087 input_line_pointer = old;
1088 *old = 0;
1089
1090 return;
1091 }
1092
1093 if (flag_mri && opcode->m_opnum == 0)
1094 {
1095 /* In MRI mode, random garbage is allowed after an instruction
1096 which accepts no operands. */
1097 the_ins.args = opcode->m_operands;
1098 the_ins.numargs = opcode->m_opnum;
1099 the_ins.numo = opcode->m_codenum;
1100 the_ins.opcode[0] = getone (opcode);
1101 the_ins.opcode[1] = gettwo (opcode);
1102 return;
1103 }
1104
1105 for (opP = &the_ins.operands[0]; *p; opP++)
1106 {
1107 p = crack_operand (p, opP);
1108
1109 if (opP->error)
1110 {
1111 the_ins.error = opP->error;
1112 return;
1113 }
1114 }
1115
1116 opsfound = opP - &the_ins.operands[0];
1117
1118 /* This ugly hack is to support the floating pt opcodes in their
1119 standard form. Essentially, we fake a first enty of type COP#1 */
1120 if (opcode->m_operands[0] == 'I')
1121 {
1122 int n;
1123
1124 for (n = opsfound; n > 0; --n)
1125 the_ins.operands[n] = the_ins.operands[n - 1];
1126
1127 memset ((char *) (&the_ins.operands[0]), '\0',
1128 sizeof (the_ins.operands[0]));
1129 the_ins.operands[0].mode = CONTROL;
1130 the_ins.operands[0].reg = m68k_float_copnum;
1131 opsfound++;
1132 }
1133
1134 /* We've got the operands. Find an opcode that'll accept them */
1135 for (losing = 0;;)
1136 {
1137 /* If we didn't get the right number of ops, or we have no
92774660 1138 common model with this pattern then reject this pattern. */
252b5132
RH		 1139
1140 ok_arch |= opcode->m_arch;
1141 if (opsfound != opcode->m_opnum
1142 || ((opcode->m_arch & current_architecture) == 0))
1143 ++losing;
1144 else
1145 {
1146 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1147 *s && !losing;
1148 s += 2, opP++)
1149 {
1150 /* Warning: this switch is huge! */
1151 /* I've tried to organize the cases into this order:
1152 non-alpha first, then alpha by letter. Lower-case
1153 goes directly before uppercase counterpart. */
1154 /* Code with multiple case ...: gets sorted by the lowest
1155 case ... it belongs to. I hope this makes sense. */
1156 switch (*s)
1157 {
1158 case '!':
1159 switch (opP->mode)
1160 {
1161 case IMMED:
1162 case DREG:
1163 case AREG:
1164 case FPREG:
1165 case CONTROL:
1166 case AINC:
1167 case ADEC:
1168 case REGLST:
1169 losing++;
1170 break;
1171 default:
1172 break;
1173 }
1174 break;
1175
1176 case '<':
1177 switch (opP->mode)
1178 {
1179 case DREG:
1180 case AREG:
1181 case FPREG:
1182 case CONTROL:
1183 case IMMED:
1184 case ADEC:
1185 case REGLST:
1186 losing++;
1187 break;
1188 default:
1189 break;
1190 }
1191 break;
1192
1193 case '>':
1194 switch (opP->mode)
1195 {
1196 case DREG:
1197 case AREG:
1198 case FPREG:
1199 case CONTROL:
1200 case IMMED:
1201 case AINC:
1202 case REGLST:
1203 losing++;
1204 break;
1205 case ABSL:
1206 break;
1207 default:
1208 if (opP->reg == PC
1209 || opP->reg == ZPC)
1210 losing++;
1211 break;
1212 }
1213 break;
1214
1215 case 'm':
1216 switch (opP->mode)
1217 {
1218 case DREG:
1219 case AREG:
1220 case AINDR:
1221 case AINC:
1222 case ADEC:
1223 break;
1224 default:
1225 losing++;
1226 }
1227 break;
1228
1229 case 'n':
1230 switch (opP->mode)
1231 {
1232 case DISP:
1233 break;
1234 default:
1235 losing++;
1236 }
1237 break;
1238
1239 case 'o':
1240 switch (opP->mode)
1241 {
1242 case BASE:
1243 case ABSL:
1244 case IMMED:
1245 break;
1246 default:
1247 losing++;
1248 }
1249 break;
1250
1251 case 'p':
1252 switch (opP->mode)
1253 {
1254 case DREG:
1255 case AREG:
1256 case AINDR:
1257 case AINC:
1258 case ADEC:
1259 break;
1260 case DISP:
1261 if (opP->reg == PC || opP->reg == ZPC)
1262 losing++;
1263 break;
1264 default:
1265 losing++;
1266 }
1267 break;
1268
1269 case 'q':
1270 switch (opP->mode)
1271 {
1272 case DREG:
1273 case AINDR:
1274 case AINC:
1275 case ADEC:
1276 break;
1277 case DISP:
1278 if (opP->reg == PC || opP->reg == ZPC)
1279 losing++;
1280 break;
1281 default:
1282 losing++;
1283 break;
1284 }
1285 break;
1286
1287 case 'v':
1288 switch (opP->mode)
1289 {
1290 case DREG:
1291 case AINDR:
1292 case AINC:
1293 case ADEC:
1294 case ABSL:
1295 break;
1296 case DISP:
1297 if (opP->reg == PC || opP->reg == ZPC)
1298 losing++;
1299 break;
1300 default:
1301 losing++;
1302 break;
1303 }
1304 break;
1305
1306 case '#':
1307 if (opP->mode != IMMED)
1308 losing++;
1309 else if (s[1] == 'b'
1310 && ! isvar (&opP->disp)
1311 && (opP->disp.exp.X_op != O_constant
1312 || ! isbyte (opP->disp.exp.X_add_number)))
1313 losing++;
1314 else if (s[1] == 'B'
1315 && ! isvar (&opP->disp)
1316 && (opP->disp.exp.X_op != O_constant
1317 || ! issbyte (opP->disp.exp.X_add_number)))
1318 losing++;
1319 else if (s[1] == 'w'
1320 && ! isvar (&opP->disp)
1321 && (opP->disp.exp.X_op != O_constant
1322 || ! isword (opP->disp.exp.X_add_number)))
1323 losing++;
1324 else if (s[1] == 'W'
1325 && ! isvar (&opP->disp)
1326 && (opP->disp.exp.X_op != O_constant
1327 || ! issword (opP->disp.exp.X_add_number)))
1328 losing++;
1329 break;
1330
1331 case '^':
1332 case 'T':
1333 if (opP->mode != IMMED)
1334 losing++;
1335 break;
1336
1337 case '$':
1338 if (opP->mode == AREG
1339 || opP->mode == CONTROL
1340 || opP->mode == FPREG
1341 || opP->mode == IMMED
1342 || opP->mode == REGLST
1343 || (opP->mode != ABSL
1344 && (opP->reg == PC
1345 || opP->reg == ZPC)))
1346 losing++;
1347 break;
1348
1349 case '%':
1350 if (opP->mode == CONTROL
1351 || opP->mode == FPREG
1352 || opP->mode == REGLST
1353 || opP->mode == IMMED
1354 || (opP->mode != ABSL
1355 && (opP->reg == PC
1356 || opP->reg == ZPC)))
1357 losing++;
1358 break;
1359
1360 case '&':
1361 switch (opP->mode)
1362 {
1363 case DREG:
1364 case AREG:
1365 case FPREG:
1366 case CONTROL:
1367 case IMMED:
1368 case AINC:
1369 case ADEC:
1370 case REGLST:
1371 losing++;
1372 break;
1373 case ABSL:
1374 break;
1375 default:
1376 if (opP->reg == PC
1377 || opP->reg == ZPC)
1378 losing++;
1379 break;
1380 }
1381 break;
1382
1383 case '*':
1384 if (opP->mode == CONTROL
1385 || opP->mode == FPREG
1386 || opP->mode == REGLST)
1387 losing++;
1388 break;
1389
1390 case '+':
1391 if (opP->mode != AINC)
1392 losing++;
1393 break;
1394
1395 case '-':
1396 if (opP->mode != ADEC)
1397 losing++;
1398 break;
1399
1400 case '/':
1401 switch (opP->mode)
1402 {
1403 case AREG:
1404 case CONTROL:
1405 case FPREG:
1406 case AINC:
1407 case ADEC:
1408 case IMMED:
1409 case REGLST:
1410 losing++;
1411 break;
1412 default:
1413 break;
1414 }
1415 break;
1416
1417 case ';':
1418 switch (opP->mode)
1419 {
1420 case AREG:
1421 case CONTROL:
1422 case FPREG:
1423 case REGLST:
1424 losing++;
1425 break;
1426 default:
1427 break;
1428 }
1429 break;
1430
1431 case '?':
1432 switch (opP->mode)
1433 {
1434 case AREG:
1435 case CONTROL:
1436 case FPREG:
1437 case AINC:
1438 case ADEC:
1439 case IMMED:
1440 case REGLST:
1441 losing++;
1442 break;
1443 case ABSL:
1444 break;
1445 default:
1446 if (opP->reg == PC || opP->reg == ZPC)
1447 losing++;
1448 break;
1449 }
1450 break;
1451
1452 case '@':
1453 switch (opP->mode)
1454 {
1455 case AREG:
1456 case CONTROL:
1457 case FPREG:
1458 case IMMED:
1459 case REGLST:
1460 losing++;
1461 break;
1462 default:
1463 break;
1464 }
1465 break;
1466
1467 case '~': /* For now! (JF FOO is this right?) */
1468 switch (opP->mode)
1469 {
1470 case DREG:
1471 case AREG:
1472 case CONTROL:
1473 case FPREG:
1474 case IMMED:
1475 case REGLST:
1476 losing++;
1477 break;
1478 case ABSL:
1479 break;
1480 default:
1481 if (opP->reg == PC
1482 || opP->reg == ZPC)
1483 losing++;
1484 break;
1485 }
1486 break;
1487
1488 case '3':
1489 if (opP->mode != CONTROL
1490 || (opP->reg != TT0 && opP->reg != TT1))
1491 losing++;
1492 break;
1493
1494 case 'A':
1495 if (opP->mode != AREG)
1496 losing++;
1497 break;
1498
1499 case 'a':
1500 if (opP->mode != AINDR)
1501 ++losing;
1502 break;
1503
1504 case 'B': /* FOO */
1505 if (opP->mode != ABSL
1506 || (flag_long_jumps
1507 && strncmp (instring, "jbsr", 4) == 0))
1508 losing++;
1509 break;
1510
1511 case 'C':
1512 if (opP->mode != CONTROL || opP->reg != CCR)
1513 losing++;
1514 break;
1515
1516 case 'd':
1517 if (opP->mode != DISP
1518 || opP->reg < ADDR0
1519 || opP->reg > ADDR7)
1520 losing++;
1521 break;
1522
1523 case 'D':
1524 if (opP->mode != DREG)
1525 losing++;
1526 break;
1527
6da466c7
ILT		 1528 case 'E':
1529 if (opP->reg != ACC)
1530 losing++;
1531 break;
1532
252b5132
RH		 1533 case 'F':
1534 if (opP->mode != FPREG)
1535 losing++;
1536 break;
1537
6da466c7
ILT		 1538 case 'G':
1539 if (opP->reg != MACSR)
1540 losing++;
1541 break;
1542
1543 case 'H':
1544 if (opP->reg != MASK)
1545 losing++;
1546 break;
1547
252b5132
RH		 1548 case 'I':
1549 if (opP->mode != CONTROL
1550 || opP->reg < COP0
1551 || opP->reg > COP7)
1552 losing++;
1553 break;
1554
1555 case 'J':
1556 if (opP->mode != CONTROL
1557 || opP->reg < USP
1558 || opP->reg > last_movec_reg)
1559 losing++;
1560 else
1561 {
1562 const enum m68k_register *rp;
1563 for (rp = control_regs; *rp; rp++)
1564 if (*rp == opP->reg)
1565 break;
1566 if (*rp == 0)
1567 losing++;
1568 }
1569 break;
1570
1571 case 'k':
1572 if (opP->mode != IMMED)
1573 losing++;
1574 break;
1575
1576 case 'l':
1577 case 'L':
1578 if (opP->mode == DREG
1579 || opP->mode == AREG
1580 || opP->mode == FPREG)
1581 {
1582 if (s[1] == '8')
1583 losing++;
1584 else
1585 {
1586 switch (opP->mode)
1587 {
1588 case DREG:
1589 opP->mask = 1 << (opP->reg - DATA0);
1590 break;
1591 case AREG:
1592 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1593 break;
1594 case FPREG:
1595 opP->mask = 1 << (opP->reg - FP0 + 16);
1596 break;
1597 default:
1598 abort ();
1599 }
1600 opP->mode = REGLST;
1601 }
1602 }
1603 else if (opP->mode == CONTROL)
1604 {
1605 if (s[1] != '8')
1606 losing++;
1607 else
1608 {
1609 switch (opP->reg)
1610 {
1611 case FPI:
1612 opP->mask = 1 << 24;
1613 break;
1614 case FPS:
1615 opP->mask = 1 << 25;
1616 break;
1617 case FPC:
1618 opP->mask = 1 << 26;
1619 break;
1620 default:
1621 losing++;
1622 break;
1623 }
1624 opP->mode = REGLST;
1625 }
1626 }
1627 else if (opP->mode != REGLST)
1628 losing++;
1629 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1630 losing++;
1631 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1632 losing++;
1633 break;
1634
1635 case 'M':
1636 if (opP->mode != IMMED)
1637 losing++;
1638 else if (opP->disp.exp.X_op != O_constant
1639 || ! issbyte (opP->disp.exp.X_add_number))
1640 losing++;
1641 else if (! m68k_quick
1642 && instring[3] != 'q'
1643 && instring[4] != 'q')
1644 losing++;
1645 break;
1646
1647 case 'O':
1648 if (opP->mode != DREG
1649 && opP->mode != IMMED
1650 && opP->mode != ABSL)
1651 losing++;
1652 break;
1653
1654 case 'Q':
1655 if (opP->mode != IMMED)
1656 losing++;
1657 else if (opP->disp.exp.X_op != O_constant
1658 || opP->disp.exp.X_add_number < 1
1659 || opP->disp.exp.X_add_number > 8)
1660 losing++;
1661 else if (! m68k_quick
1662 && (strncmp (instring, "add", 3) == 0
1663 || strncmp (instring, "sub", 3) == 0)
1664 && instring[3] != 'q')
1665 losing++;
1666 break;
1667
1668 case 'R':
1669 if (opP->mode != DREG && opP->mode != AREG)
1670 losing++;
1671 break;
1672
1673 case 'r':
1674 if (opP->mode != AINDR
1675 && (opP->mode != BASE
1676 || (opP->reg != 0
1677 && opP->reg != ZADDR0)
1678 || opP->disp.exp.X_op != O_absent
1679 || ((opP->index.reg < DATA0
1680 || opP->index.reg > DATA7)
1681 && (opP->index.reg < ADDR0
1682 || opP->index.reg > ADDR7))
1683 || opP->index.size != SIZE_UNSPEC
1684 || opP->index.scale != 1))
1685 losing++;
1686 break;
1687
1688 case 's':
1689 if (opP->mode != CONTROL
1690 || ! (opP->reg == FPI
1691 || opP->reg == FPS
1692 || opP->reg == FPC))
1693 losing++;
1694 break;
1695
1696 case 'S':
1697 if (opP->mode != CONTROL || opP->reg != SR)
1698 losing++;
1699 break;
1700
1701 case 't':
1702 if (opP->mode != IMMED)
1703 losing++;
1704 else if (opP->disp.exp.X_op != O_constant
1705 || opP->disp.exp.X_add_number < 0
1706 || opP->disp.exp.X_add_number > 7)
1707 losing++;
1708 break;
1709
1710 case 'U':
1711 if (opP->mode != CONTROL || opP->reg != USP)
1712 losing++;
1713 break;
1714
1715 /* JF these are out of order. We could put them
1716 in order if we were willing to put up with
1717 bunches of #ifdef m68851s in the code.
1718
1719 Don't forget that you need these operands
1720 to use 68030 MMU instructions. */
1721#ifndef NO_68851
1722 /* Memory addressing mode used by pflushr */
1723 case '|':
1724 if (opP->mode == CONTROL
1725 || opP->mode == FPREG
1726 || opP->mode == DREG
1727 || opP->mode == AREG
1728 || opP->mode == REGLST)
1729 losing++;
1730 /* We should accept immediate operands, but they
1731 supposedly have to be quad word, and we don't
1732 handle that. I would like to see what a Motorola
1733 assembler does before doing something here. */
1734 if (opP->mode == IMMED)
1735 losing++;
1736 break;
1737
1738 case 'f':
1739 if (opP->mode != CONTROL
1740 || (opP->reg != SFC && opP->reg != DFC))
1741 losing++;
1742 break;
1743
1744 case '0':
1745 if (opP->mode != CONTROL || opP->reg != TC)
1746 losing++;
1747 break;
1748
1749 case '1':
1750 if (opP->mode != CONTROL || opP->reg != AC)
1751 losing++;
1752 break;
1753
1754 case '2':
1755 if (opP->mode != CONTROL
1756 || (opP->reg != CAL
1757 && opP->reg != VAL
1758 && opP->reg != SCC))
1759 losing++;
1760 break;
1761
1762 case 'V':
1763 if (opP->mode != CONTROL
1764 || opP->reg != VAL)
1765 losing++;
1766 break;
1767
1768 case 'W':
1769 if (opP->mode != CONTROL
1770 || (opP->reg != DRP
1771 && opP->reg != SRP
1772 && opP->reg != CRP))
1773 losing++;
1774 break;
1775
1776 case 'X':
1777 if (opP->mode != CONTROL
1778 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1779 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1780 losing++;
1781 break;
1782
1783 case 'Y':
1784 if (opP->mode != CONTROL || opP->reg != PSR)
1785 losing++;
1786 break;
1787
1788 case 'Z':
1789 if (opP->mode != CONTROL || opP->reg != PCSR)
1790 losing++;
1791 break;
1792#endif
1793 case 'c':
1794 if (opP->mode != CONTROL
1795 || (opP->reg != NC
1796 && opP->reg != IC
1797 && opP->reg != DC
1798 && opP->reg != BC))
1799 {
1800 losing++;
92774660 1801 } /* not a cache specifier. */
252b5132
RH		 1802 break;
1803
1804 case '_':
1805 if (opP->mode != ABSL)
1806 ++losing;
1807 break;
1808
6da466c7
ILT		 1809 case 'u':
1810 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1811 losing++;
1812 /* FIXME: kludge instead of fixing parser:
1813 upper/lower registers are *not* CONTROL
92774660 1814 registers, but ordinary ones. */
6da466c7
ILT		 1815 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1816 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1817 opP->mode = DREG;
1818 else
1819 opP->mode = AREG;
1820 break;
1821
252b5132
RH		 1822 default:
1823 abort ();
1824 } /* switch on type of operand */
1825
1826 if (losing)
1827 break;
1828 } /* for each operand */
1829 } /* if immediately wrong */
1830
1831 if (!losing)
1832 {
1833 break;
92774660 1834 } /* got it. */
252b5132
RH		 1835
1836 opcode = opcode->m_next;
1837
1838 if (!opcode)
1839 {
1840 if (ok_arch
1841 && !(ok_arch & current_architecture))
1842 {
1843 char buf[200], *cp;
1844
1845 strcpy (buf,
1846 _("invalid instruction for this architecture; needs "));
1847 cp = buf + strlen (buf);
1848 switch (ok_arch)
1849 {
1850 case mfloat:
1851 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1852 break;
1853 case mmmu:
1854 strcpy (cp, _("mmu (68030 or 68851)"));
1855 break;
1856 case m68020up:
1857 strcpy (cp, _("68020 or higher"));
1858 break;
1859 case m68000up:
1860 strcpy (cp, _("68000 or higher"));
1861 break;
1862 case m68010up:
1863 strcpy (cp, _("68010 or higher"));
1864 break;
1865 default:
1866 {
1867 int got_one = 0, idx;
8fce3f5e
AM		 1868 for (idx = 0;
1869 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1870 idx++)
1871 {
1872 if ((archs[idx].arch & ok_arch)
1873 && ! archs[idx].alias)
1874 {
1875 if (got_one)
1876 {
1877 strcpy (cp, " or ");
1878 cp += strlen (cp);
1879 }
1880 got_one = 1;
1881 strcpy (cp, archs[idx].name);
1882 cp += strlen (cp);
1883 }
1884 }
1885 }
1886 }
1887 cp = xmalloc (strlen (buf) + 1);
1888 strcpy (cp, buf);
1889 the_ins.error = cp;
1890 }
1891 else
1892 the_ins.error = _("operands mismatch");
1893 return;
1894 } /* Fell off the end */
1895
1896 losing = 0;
1897 }
1898
1899 /* now assemble it */
1900
1901 the_ins.args = opcode->m_operands;
1902 the_ins.numargs = opcode->m_opnum;
1903 the_ins.numo = opcode->m_codenum;
1904 the_ins.opcode[0] = getone (opcode);
1905 the_ins.opcode[1] = gettwo (opcode);
1906
1907 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1908 {
1909 /* This switch is a doozy.
1910 Watch the first step; its a big one! */
1911 switch (s[0])
1912 {
1913
1914 case '*':
1915 case '~':
1916 case '%':
1917 case ';':
1918 case '@':
1919 case '!':
1920 case '&':
1921 case '$':
1922 case '?':
1923 case '/':
1924 case '<':
1925 case '>':
1926 case 'm':
1927 case 'n':
1928 case 'o':
1929 case 'p':
1930 case 'q':
1931 case 'v':
1932#ifndef NO_68851
1933 case '|':
1934#endif
1935 switch (opP->mode)
1936 {
1937 case IMMED:
1938 tmpreg = 0x3c; /* 7.4 */
1939 if (strchr ("bwl", s[1]))
1940 nextword = get_num (&opP->disp, 80);
1941 else
1942 nextword = get_num (&opP->disp, 0);
1943 if (isvar (&opP->disp))
1944 add_fix (s[1], &opP->disp, 0, 0);
1945 switch (s[1])
1946 {
1947 case 'b':
1948 if (!isbyte (nextword))
1949 opP->error = _("operand out of range");
1950 addword (nextword);
1951 baseo = 0;
1952 break;
1953 case 'w':
1954 if (!isword (nextword))
1955 opP->error = _("operand out of range");
1956 addword (nextword);
1957 baseo = 0;
1958 break;
1959 case 'W':
1960 if (!issword (nextword))
1961 opP->error = _("operand out of range");
1962 addword (nextword);
1963 baseo = 0;
1964 break;
1965 case 'l':
1966 addword (nextword >> 16);
1967 addword (nextword);
1968 baseo = 0;
1969 break;
1970
1971 case 'f':
1972 baseo = 2;
1973 outro = 8;
1974 break;
1975 case 'F':
1976 baseo = 4;
1977 outro = 11;
1978 break;
1979 case 'x':
1980 baseo = 6;
1981 outro = 15;
1982 break;
1983 case 'p':
1984 baseo = 6;
1985 outro = -1;
1986 break;
1987 default:
1988 abort ();
1989 }
1990 if (!baseo)
1991 break;
1992
1993 /* We gotta put out some float */
1994 if (op (&opP->disp) != O_big)
1995 {
1996 valueT val;
1997 int gencnt;
1998
1999 /* Can other cases happen here? */
2000 if (op (&opP->disp) != O_constant)
2001 abort ();
2002
2003 val = (valueT) offs (&opP->disp);
2004 gencnt = 0;
2005 do
2006 {
2007 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2008 val >>= LITTLENUM_NUMBER_OF_BITS;
2009 ++gencnt;
2010 }
2011 while (val != 0);
2012 offs (&opP->disp) = gencnt;
2013 }
2014 if (offs (&opP->disp) > 0)
2015 {
2016 if (offs (&opP->disp) > baseo)
2017 {
2018 as_warn (_("Bignum too big for %c format; truncated"),
2019 s[1]);
2020 offs (&opP->disp) = baseo;
2021 }
2022 baseo -= offs (&opP->disp);
2023 while (baseo--)
2024 addword (0);
2025 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2026 offs (&opP->disp)--;
2027 --wordp)
2028 addword (*wordp);
2029 break;
2030 }
2031 gen_to_words (words, baseo, (long) outro);
2032 for (wordp = words; baseo--; wordp++)
2033 addword (*wordp);
2034 break;
2035 case DREG:
2036 tmpreg = opP->reg - DATA; /* 0.dreg */
2037 break;
2038 case AREG:
2039 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2040 break;
2041 case AINDR:
2042 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2043 break;
2044 case ADEC:
2045 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2046 break;
2047 case AINC:
2048 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2049 break;
2050 case DISP:
2051
2052 nextword = get_num (&opP->disp, 80);
2053
2054 if (opP->reg == PC
2055 && ! isvar (&opP->disp)
2056 && m68k_abspcadd)
2057 {
2058 opP->disp.exp.X_op = O_symbol;
2059#ifndef BFD_ASSEMBLER
2060 opP->disp.exp.X_add_symbol = &abs_symbol;
2061#else
2062 opP->disp.exp.X_add_symbol =
2063 section_symbol (absolute_section);
2064#endif
2065 }
2066
2067 /* Force into index mode. Hope this works */
2068
2069 /* We do the first bit for 32-bit displacements, and the
2070 second bit for 16 bit ones. It is possible that we
2071 should make the default be WORD instead of LONG, but
2072 I think that'd break GCC, so we put up with a little
2073 inefficiency for the sake of working output. */
2074
2075 if (!issword (nextword)
2076 || (isvar (&opP->disp)
2077 && ((opP->disp.size == SIZE_UNSPEC
2078 && flag_short_refs == 0
2079 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2080 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2081 || opP->disp.size == SIZE_LONG)))
2082 {
2083 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2084 || arch_coldfire_p (current_architecture))
252b5132
RH		 2085 opP->error =
2086 _("displacement too large for this architecture; needs 68020 or higher");
2087 if (opP->reg == PC)
2088 tmpreg = 0x3B; /* 7.3 */
2089 else
2090 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2091 if (isvar (&opP->disp))
2092 {
2093 if (opP->reg == PC)
2094 {
2095 if (opP->disp.size == SIZE_LONG
2096#ifdef OBJ_ELF
2097 /* If the displacement needs pic
2098 relocation it cannot be relaxed. */
2099 || opP->disp.pic_reloc != pic_none
2100#endif
2101 )
2102 {
2103 addword (0x0170);
2104 add_fix ('l', &opP->disp, 1, 2);
2105 }
2106 else
2107 {
2108 add_frag (adds (&opP->disp),
2109 offs (&opP->disp),
151337e8 2110 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2111 break;
2112 }
2113 }
2114 else
2115 {
2116 addword (0x0170);
2117 add_fix ('l', &opP->disp, 0, 0);
2118 }
2119 }
2120 else
2121 addword (0x0170);
2122 addword (nextword >> 16);
2123 }
2124 else
2125 {
2126 if (opP->reg == PC)
2127 tmpreg = 0x3A; /* 7.2 */
2128 else
2129 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2130
2131 if (isvar (&opP->disp))
2132 {
2133 if (opP->reg == PC)
2134 {
2135 add_fix ('w', &opP->disp, 1, 0);
2136 }
2137 else
2138 add_fix ('w', &opP->disp, 0, 0);
2139 }
2140 }
2141 addword (nextword);
2142 break;
2143
2144 case POST:
2145 case PRE:
2146 case BASE:
2147 nextword = 0;
2148 baseo = get_num (&opP->disp, 80);
2149 if (opP->mode == POST || opP->mode == PRE)
2150 outro = get_num (&opP->odisp, 80);
2151 /* Figure out the `addressing mode'.
2152 Also turn on the BASE_DISABLE bit, if needed. */
2153 if (opP->reg == PC || opP->reg == ZPC)
2154 {
2155 tmpreg = 0x3b; /* 7.3 */
2156 if (opP->reg == ZPC)
2157 nextword |= 0x80;
2158 }
2159 else if (opP->reg == 0)
2160 {
2161 nextword |= 0x80;
2162 tmpreg = 0x30; /* 6.garbage */
2163 }
2164 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2165 {
2166 nextword |= 0x80;
2167 tmpreg = 0x30 + opP->reg - ZADDR0;
2168 }
2169 else
2170 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2171
2172 siz1 = opP->disp.size;
2173 if (opP->mode == POST || opP->mode == PRE)
2174 siz2 = opP->odisp.size;
2175 else
2176 siz2 = SIZE_UNSPEC;
2177
2178 /* Index register stuff */
2179 if (opP->index.reg != 0
2180 && opP->index.reg >= DATA
2181 && opP->index.reg <= ADDR7)
2182 {
2183 nextword |= (opP->index.reg - DATA) << 12;
2184
2185 if (opP->index.size == SIZE_LONG
2186 || (opP->index.size == SIZE_UNSPEC
2187 && m68k_index_width_default == SIZE_LONG))
2188 nextword |= 0x800;
2189
92774660 2190 if ((opP->index.scale != 1
252b5132 2191 && cpu_of_arch (current_architecture) < m68020)
92774660 2192 || (opP->index.scale == 8
6da466c7 2193 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2194 {
2195 opP->error =
2196 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2197 }
2198
6da466c7
ILT		 2199 if (arch_coldfire_p (current_architecture)
2200 && opP->index.size == SIZE_WORD)
2201 opP->error = _("invalid index size for coldfire");
2202
252b5132
RH		 2203 switch (opP->index.scale)
2204 {
2205 case 1:
2206 break;
2207 case 2:
2208 nextword |= 0x200;
2209 break;
2210 case 4:
2211 nextword |= 0x400;
2212 break;
2213 case 8:
2214 nextword |= 0x600;
2215 break;
2216 default:
2217 abort ();
2218 }
2219 /* IF its simple,
2220 GET US OUT OF HERE! */
2221
2222 /* Must be INDEX, with an index register. Address
2223 register cannot be ZERO-PC, and either :b was
2224 forced, or we know it will fit. For a 68000 or
2225 68010, force this mode anyways, because the
2226 larger modes aren't supported. */
2227 if (opP->mode == BASE
2228 && ((opP->reg >= ADDR0
2229 && opP->reg <= ADDR7)
2230 || opP->reg == PC))
2231 {
2232 if (siz1 == SIZE_BYTE
2233 || cpu_of_arch (current_architecture) < m68020
6da466c7 2234 || arch_coldfire_p (current_architecture)
252b5132
RH		 2235 || (siz1 == SIZE_UNSPEC
2236 && ! isvar (&opP->disp)
2237 && issbyte (baseo)))
2238 {
2239 nextword += baseo & 0xff;
2240 addword (nextword);
2241 if (isvar (&opP->disp))
2242 {
2243 /* Do a byte relocation. If it doesn't
2244 fit (possible on m68000) let the
2245 fixup processing complain later. */
2246 if (opP->reg == PC)
2247 add_fix ('B', &opP->disp, 1, 1);
2248 else
2249 add_fix ('B', &opP->disp, 0, 0);
2250 }
2251 else if (siz1 != SIZE_BYTE)
2252 {
2253 if (siz1 != SIZE_UNSPEC)
2254 as_warn (_("Forcing byte displacement"));
2255 if (! issbyte (baseo))
2256 opP->error = _("byte displacement out of range");
2257 }
2258
2259 break;
2260 }
2261 else if (siz1 == SIZE_UNSPEC
2262 && opP->reg == PC
2263 && isvar (&opP->disp)
2264 && subs (&opP->disp) == NULL
2265#ifdef OBJ_ELF
2266 /* If the displacement needs pic
2267 relocation it cannot be relaxed. */
2268 && opP->disp.pic_reloc == pic_none
2269#endif
2270 )
2271 {
2272 /* The code in md_convert_frag_1 needs to be
2273 able to adjust nextword. Call frag_grow
2274 to ensure that we have enough space in
2275 the frag obstack to make all the bytes
2276 contiguous. */
2277 frag_grow (14);
2278 nextword += baseo & 0xff;
2279 addword (nextword);
2280 add_frag (adds (&opP->disp), offs (&opP->disp),
2281 TAB (PCINDEX, SZ_UNDEF));
2282
2283 break;
2284 }
2285 }
2286 }
2287 else
2288 {
2289 nextword |= 0x40; /* No index reg */
2290 if (opP->index.reg >= ZDATA0
2291 && opP->index.reg <= ZDATA7)
2292 nextword |= (opP->index.reg - ZDATA0) << 12;
2293 else if (opP->index.reg >= ZADDR0
2294 || opP->index.reg <= ZADDR7)
2295 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2296 }
2297
2298 /* It isn't simple. */
2299
2300 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2301 || arch_coldfire_p (current_architecture))
252b5132
RH		 2302 opP->error =
2303 _("invalid operand mode for this architecture; needs 68020 or higher");
2304
2305 nextword |= 0x100;
2306 /* If the guy specified a width, we assume that it is
2307 wide enough. Maybe it isn't. If so, we lose. */
2308 switch (siz1)
2309 {
2310 case SIZE_UNSPEC:
2311 if (isvar (&opP->disp)
2312 ? m68k_rel32
2313 : ! issword (baseo))
2314 {
2315 siz1 = SIZE_LONG;
2316 nextword |= 0x30;
2317 }
2318 else if (! isvar (&opP->disp) && baseo == 0)
2319 nextword |= 0x10;
2320 else
2321 {
2322 nextword |= 0x20;
2323 siz1 = SIZE_WORD;
2324 }
2325 break;
2326 case SIZE_BYTE:
2327 as_warn (_(":b not permitted; defaulting to :w"));
2328 /* Fall through. */
2329 case SIZE_WORD:
2330 nextword |= 0x20;
2331 break;
2332 case SIZE_LONG:
2333 nextword |= 0x30;
2334 break;
2335 }
2336
2337 /* Figure out innner displacement stuff */
2338 if (opP->mode == POST || opP->mode == PRE)
2339 {
2340 if (cpu_of_arch (current_architecture) & cpu32)
2341 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2342 switch (siz2)
2343 {
2344 case SIZE_UNSPEC:
2345 if (isvar (&opP->odisp)
2346 ? m68k_rel32
2347 : ! issword (outro))
2348 {
2349 siz2 = SIZE_LONG;
2350 nextword |= 0x3;
2351 }
2352 else if (! isvar (&opP->odisp) && outro == 0)
2353 nextword |= 0x1;
2354 else
2355 {
2356 nextword |= 0x2;
2357 siz2 = SIZE_WORD;
2358 }
2359 break;
2360 case 1:
2361 as_warn (_(":b not permitted; defaulting to :w"));
2362 /* Fall through. */
2363 case 2:
2364 nextword |= 0x2;
2365 break;
2366 case 3:
2367 nextword |= 0x3;
2368 break;
2369 }
2370 if (opP->mode == POST
2371 && (nextword & 0x40) == 0)
2372 nextword |= 0x04;
2373 }
2374 addword (nextword);
2375
2376 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2377 {
2378 if (opP->reg == PC || opP->reg == ZPC)
2379 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2380 else
2381 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2382 }
2383 if (siz1 == SIZE_LONG)
2384 addword (baseo >> 16);
2385 if (siz1 != SIZE_UNSPEC)
2386 addword (baseo);
2387
2388 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2389 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2390 if (siz2 == SIZE_LONG)
2391 addword (outro >> 16);
2392 if (siz2 != SIZE_UNSPEC)
2393 addword (outro);
2394
2395 break;
2396
2397 case ABSL:
2398 nextword = get_num (&opP->disp, 80);
2399 switch (opP->disp.size)
2400 {
2401 default:
2402 abort ();
2403 case SIZE_UNSPEC:
2404 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2405 {
2406 tmpreg = 0x38; /* 7.0 */
2407 addword (nextword);
2408 break;
2409 }
252b5132
RH		 2410 if (isvar (&opP->disp)
2411 && !subs (&opP->disp)
2412 && adds (&opP->disp)
2413#ifdef OBJ_ELF
2414 /* If the displacement needs pic relocation it
2415 cannot be relaxed. */
2416 && opP->disp.pic_reloc == pic_none
2417#endif
252b5132
RH		 2418 && !flag_long_jumps
2419 && !strchr ("~%&$?", s[0]))
2420 {
2421 tmpreg = 0x3A; /* 7.2 */
2422 add_frag (adds (&opP->disp),
2423 offs (&opP->disp),
151337e8 2424 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2425 break;
2426 }
2427 /* Fall through into long */
2428 case SIZE_LONG:
2429 if (isvar (&opP->disp))
2430 add_fix ('l', &opP->disp, 0, 0);
2431
2432 tmpreg = 0x39;/* 7.1 mode */
2433 addword (nextword >> 16);
2434 addword (nextword);
2435 break;
2436
2437 case SIZE_BYTE:
2438 as_bad (_("unsupported byte value; use a different suffix"));
2439 /* Fall through. */
2440 case SIZE_WORD: /* Word */
2441 if (isvar (&opP->disp))
2442 add_fix ('w', &opP->disp, 0, 0);
2443
2444 tmpreg = 0x38;/* 7.0 mode */
2445 addword (nextword);
2446 break;
2447 }
2448 break;
2449 case CONTROL:
2450 case FPREG:
2451 default:
2452 as_bad (_("unknown/incorrect operand"));
bc805888 2453 /* abort (); */
252b5132
RH		 2454 }
2455 install_gen_operand (s[1], tmpreg);
2456 break;
2457
2458 case '#':
2459 case '^':
2460 switch (s[1])
2461 { /* JF: I hate floating point! */
2462 case 'j':
2463 tmpreg = 70;
2464 break;
2465 case '8':
2466 tmpreg = 20;
2467 break;
2468 case 'C':
2469 tmpreg = 50;
2470 break;
2471 case '3':
2472 default:
2473 tmpreg = 80;
2474 break;
2475 }
2476 tmpreg = get_num (&opP->disp, tmpreg);
2477 if (isvar (&opP->disp))
2478 add_fix (s[1], &opP->disp, 0, 0);
2479 switch (s[1])
2480 {
2481 case 'b': /* Danger: These do no check for
2482 certain types of overflow.
2483 user beware! */
2484 if (!isbyte (tmpreg))
2485 opP->error = _("out of range");
2486 insop (tmpreg, opcode);
2487 if (isvar (&opP->disp))
2488 the_ins.reloc[the_ins.nrel - 1].n =
2489 (opcode->m_codenum) * 2 + 1;
2490 break;
2491 case 'B':
2492 if (!issbyte (tmpreg))
2493 opP->error = _("out of range");
2494 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2495 if (isvar (&opP->disp))
2496 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2497 break;
2498 case 'w':
2499 if (!isword (tmpreg))
2500 opP->error = _("out of range");
2501 insop (tmpreg, opcode);
2502 if (isvar (&opP->disp))
2503 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2504 break;
2505 case 'W':
2506 if (!issword (tmpreg))
2507 opP->error = _("out of range");
2508 insop (tmpreg, opcode);
2509 if (isvar (&opP->disp))
2510 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2511 break;
2512 case 'l':
2513 /* Because of the way insop works, we put these two out
2514 backwards. */
2515 insop (tmpreg, opcode);
2516 insop (tmpreg >> 16, opcode);
2517 if (isvar (&opP->disp))
2518 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2519 break;
2520 case '3':
2521 tmpreg &= 0xFF;
2522 case '8':
2523 case 'C':
2524 case 'j':
2525 install_operand (s[1], tmpreg);
2526 break;
2527 default:
2528 abort ();
2529 }
2530 break;
2531
2532 case '+':
2533 case '-':
2534 case 'A':
2535 case 'a':
2536 install_operand (s[1], opP->reg - ADDR);
2537 break;
2538
2539 case 'B':
2540 tmpreg = get_num (&opP->disp, 80);
2541 switch (s[1])
2542 {
2543 case 'B':
8390138c 2544 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2545 break;
2546 case 'W':
2547 add_fix ('w', &opP->disp, 1, 0);
2548 addword (0);
2549 break;
2550 case 'L':
2551 long_branch:
151337e8 2552 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2553 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2554 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2555 add_fix ('l', &opP->disp, 1, 0);
2556 addword (0);
2557 addword (0);
2558 break;
2559 case 'g':
2560 if (subs (&opP->disp)) /* We can't relax it */
2561 goto long_branch;
2562
2563#ifdef OBJ_ELF
2564 /* If the displacement needs pic relocation it cannot be
2565 relaxed. */
2566 if (opP->disp.pic_reloc != pic_none)
2567 goto long_branch;
2568#endif
252b5132 2569 /* This could either be a symbol, or an absolute
151337e8
NC		 2570 address. If it's an absolute address, turn it into
2571 an absolute jump right here and keep it out of the
2572 relaxer. */
2573 if (adds (&opP->disp) == 0)
2574 {
2575 if (the_ins.opcode[0] == 0x6000) /* jbra */
2576 the_ins.opcode[0] = 0x4EF1;
2577 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2578 the_ins.opcode[0] = 0x4EB1;
2579 else /* jCC */
2580 {
2581 the_ins.opcode[0] ^= 0x0100;
2582 the_ins.opcode[0] |= 0x0006;
2583 addword (0x4EF1);
2584 }
2585 add_fix ('l', &opP->disp, 0, 0);
2586 addword (0);
2587 addword (0);
2588 break;
2589 }
2590
2591 /* Now we know it's going into the relaxer. Now figure
2592 out which mode. We try in this order of preference:
2593 long branch, absolute jump, byte/word branches only. */
2594 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2595 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2596 TAB (BRANCHBWL, SZ_UNDEF));
2597 else if (! flag_keep_pcrel)
2598 {
2599 if ((the_ins.opcode[0] == 0x6000)
2600 || (the_ins.opcode[0] == 0x6100))
2601 add_frag (adds (&opP->disp), offs (&opP->disp),
2602 TAB (BRABSJUNC, SZ_UNDEF));
2603 else
2604 add_frag (adds (&opP->disp), offs (&opP->disp),
2605 TAB (BRABSJCOND, SZ_UNDEF));
2606 }
252b5132
RH		 2607 else
2608 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2609 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2610 break;
2611 case 'w':
2612 if (isvar (&opP->disp))
2613 {
151337e8
NC		 2614 /* Check for DBcc instructions. We can relax them,
2615 but only if we have long branches and/or absolute
2616 jumps. */
2617 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2618 && (HAVE_LONG_BRANCH (current_architecture)
2619 || (! flag_keep_pcrel)))
252b5132 2620 {
151337e8
NC		 2621 if (HAVE_LONG_BRANCH (current_architecture))
2622 add_frag (adds (&opP->disp), offs (&opP->disp),
2623 TAB (DBCCLBR, SZ_UNDEF));
2624 else
2625 add_frag (adds (&opP->disp), offs (&opP->disp),
2626 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2627 break;
2628 }
252b5132
RH		 2629 add_fix ('w', &opP->disp, 1, 0);
2630 }
2631 addword (0);
2632 break;
2633 case 'C': /* Fixed size LONG coproc branches */
2634 add_fix ('l', &opP->disp, 1, 0);
2635 addword (0);
2636 addword (0);
2637 break;
2638 case 'c': /* Var size Coprocesssor branches */
151337e8 2639 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2640 {
252b5132
RH		 2641 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2642 add_fix ('l', &opP->disp, 1, 0);
2643 addword (0);
2644 addword (0);
2645 }
151337e8
NC		 2646 else
2647 add_frag (adds (&opP->disp), offs (&opP->disp),
2648 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2649 break;
2650 default:
2651 abort ();
2652 }
2653 break;
2654
2655 case 'C': /* Ignore it */
2656 break;
2657
2658 case 'd': /* JF this is a kludge */
2659 install_operand ('s', opP->reg - ADDR);
2660 tmpreg = get_num (&opP->disp, 80);
2661 if (!issword (tmpreg))
2662 {
2663 as_warn (_("Expression out of range, using 0"));
2664 tmpreg = 0;
2665 }
2666 addword (tmpreg);
2667 break;
2668
2669 case 'D':
2670 install_operand (s[1], opP->reg - DATA);
2671 break;
2672
6da466c7
ILT		 2673 case 'E': /* Ignore it */
2674 break;
2675
252b5132
RH		 2676 case 'F':
2677 install_operand (s[1], opP->reg - FP0);
2678 break;
2679
6da466c7
ILT		 2680 case 'G': /* Ignore it */
2681 case 'H':
2682 break;
2683
252b5132
RH		 2684 case 'I':
2685 tmpreg = opP->reg - COP0;
2686 install_operand (s[1], tmpreg);
2687 break;
2688
2689 case 'J': /* JF foo */
2690 switch (opP->reg)
2691 {
2692 case SFC:
2693 tmpreg = 0x000;
2694 break;
2695 case DFC:
2696 tmpreg = 0x001;
2697 break;
2698 case CACR:
2699 tmpreg = 0x002;
2700 break;
2701 case TC:
2702 tmpreg = 0x003;
2703 break;
2704 case ITT0:
2705 tmpreg = 0x004;
2706 break;
2707 case ITT1:
2708 tmpreg = 0x005;
2709 break;
2710 case DTT0:
2711 tmpreg = 0x006;
2712 break;
2713 case DTT1:
2714 tmpreg = 0x007;
2715 break;
2716 case BUSCR:
2717 tmpreg = 0x008;
2718 break;
2719
2720 case USP:
2721 tmpreg = 0x800;
2722 break;
2723 case VBR:
2724 tmpreg = 0x801;
2725 break;
2726 case CAAR:
2727 tmpreg = 0x802;
2728 break;
2729 case MSP:
2730 tmpreg = 0x803;
2731 break;
2732 case ISP:
2733 tmpreg = 0x804;
2734 break;
2735 case MMUSR:
2736 tmpreg = 0x805;
2737 break;
2738 case URP:
2739 tmpreg = 0x806;
2740 break;
2741 case SRP:
2742 tmpreg = 0x807;
2743 break;
2744 case PCR:
2745 tmpreg = 0x808;
2746 break;
2747 case ROMBAR:
2748 tmpreg = 0xC00;
2749 break;
2750 case RAMBAR0:
2751 tmpreg = 0xC04;
2752 break;
2753 case RAMBAR1:
2754 tmpreg = 0xC05;
2755 break;
2756 case MBAR:
2757 tmpreg = 0xC0F;
2758 break;
2759 default:
2760 abort ();
2761 }
2762 install_operand (s[1], tmpreg);
2763 break;
2764
2765 case 'k':
2766 tmpreg = get_num (&opP->disp, 55);
2767 install_operand (s[1], tmpreg & 0x7f);
2768 break;
2769
2770 case 'l':
2771 tmpreg = opP->mask;
2772 if (s[1] == 'w')
2773 {
2774 if (tmpreg & 0x7FF0000)
2775 as_bad (_("Floating point register in register list"));
2776 insop (reverse_16_bits (tmpreg), opcode);
2777 }
2778 else
2779 {
2780 if (tmpreg & 0x700FFFF)
2781 as_bad (_("Wrong register in floating-point reglist"));
2782 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2783 }
2784 break;
2785
2786 case 'L':
2787 tmpreg = opP->mask;
2788 if (s[1] == 'w')
2789 {
2790 if (tmpreg & 0x7FF0000)
2791 as_bad (_("Floating point register in register list"));
2792 insop (tmpreg, opcode);
2793 }
2794 else if (s[1] == '8')
2795 {
2796 if (tmpreg & 0x0FFFFFF)
2797 as_bad (_("incorrect register in reglist"));
2798 install_operand (s[1], tmpreg >> 24);
2799 }
2800 else
2801 {
2802 if (tmpreg & 0x700FFFF)
2803 as_bad (_("wrong register in floating-point reglist"));
2804 else
2805 install_operand (s[1], tmpreg >> 16);
2806 }
2807 break;
2808
2809 case 'M':
2810 install_operand (s[1], get_num (&opP->disp, 60));
2811 break;
2812
2813 case 'O':
2814 tmpreg = ((opP->mode == DREG)
8fce3f5e 2815 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2816 : (get_num (&opP->disp, 40) & 0x1F));
2817 install_operand (s[1], tmpreg);
2818 break;
2819
2820 case 'Q':
2821 tmpreg = get_num (&opP->disp, 10);
2822 if (tmpreg == 8)
2823 tmpreg = 0;
2824 install_operand (s[1], tmpreg);
2825 break;
2826
2827 case 'R':
2828 /* This depends on the fact that ADDR registers are eight
2829 more than their corresponding DATA regs, so the result
2830 will have the ADDR_REG bit set */
2831 install_operand (s[1], opP->reg - DATA);
2832 break;
2833
2834 case 'r':
2835 if (opP->mode == AINDR)
2836 install_operand (s[1], opP->reg - DATA);
2837 else
2838 install_operand (s[1], opP->index.reg - DATA);
2839 break;
2840
2841 case 's':
2842 if (opP->reg == FPI)
2843 tmpreg = 0x1;
2844 else if (opP->reg == FPS)
2845 tmpreg = 0x2;
2846 else if (opP->reg == FPC)
2847 tmpreg = 0x4;
2848 else
2849 abort ();
2850 install_operand (s[1], tmpreg);
2851 break;
2852
2853 case 'S': /* Ignore it */
2854 break;
2855
2856 case 'T':
2857 install_operand (s[1], get_num (&opP->disp, 30));
2858 break;
2859
2860 case 'U': /* Ignore it */
2861 break;
2862
2863 case 'c':
2864 switch (opP->reg)
2865 {
2866 case NC:
2867 tmpreg = 0;
2868 break;
2869 case DC:
2870 tmpreg = 1;
2871 break;
2872 case IC:
2873 tmpreg = 2;
2874 break;
2875 case BC:
2876 tmpreg = 3;
2877 break;
2878 default:
2879 as_fatal (_("failed sanity check"));
2880 } /* switch on cache token */
2881 install_operand (s[1], tmpreg);
2882 break;
2883#ifndef NO_68851
92774660 2884 /* JF: These are out of order, I fear. */
252b5132
RH		 2885 case 'f':
2886 switch (opP->reg)
2887 {
2888 case SFC:
2889 tmpreg = 0;
2890 break;
2891 case DFC:
2892 tmpreg = 1;
2893 break;
2894 default:
2895 abort ();
2896 }
2897 install_operand (s[1], tmpreg);
2898 break;
2899
2900 case '0':
2901 case '1':
2902 case '2':
2903 switch (opP->reg)
2904 {
2905 case TC:
2906 tmpreg = 0;
2907 break;
2908 case CAL:
2909 tmpreg = 4;
2910 break;
2911 case VAL:
2912 tmpreg = 5;
2913 break;
2914 case SCC:
2915 tmpreg = 6;
2916 break;
2917 case AC:
2918 tmpreg = 7;
2919 break;
2920 default:
2921 abort ();
2922 }
2923 install_operand (s[1], tmpreg);
2924 break;
2925
2926 case 'V':
2927 if (opP->reg == VAL)
2928 break;
2929 abort ();
2930
2931 case 'W':
2932 switch (opP->reg)
2933 {
2934 case DRP:
2935 tmpreg = 1;
2936 break;
2937 case SRP:
2938 tmpreg = 2;
2939 break;
2940 case CRP:
2941 tmpreg = 3;
2942 break;
2943 default:
2944 abort ();
2945 }
2946 install_operand (s[1], tmpreg);
2947 break;
2948
2949 case 'X':
2950 switch (opP->reg)
2951 {
2952 case BAD:
2953 case BAD + 1:
2954 case BAD + 2:
2955 case BAD + 3:
2956 case BAD + 4:
2957 case BAD + 5:
2958 case BAD + 6:
2959 case BAD + 7:
2960 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2961 break;
2962
2963 case BAC:
2964 case BAC + 1:
2965 case BAC + 2:
2966 case BAC + 3:
2967 case BAC + 4:
2968 case BAC + 5:
2969 case BAC + 6:
2970 case BAC + 7:
2971 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2972 break;
2973
2974 default:
2975 abort ();
2976 }
2977 install_operand (s[1], tmpreg);
2978 break;
2979 case 'Y':
2980 know (opP->reg == PSR);
2981 break;
2982 case 'Z':
2983 know (opP->reg == PCSR);
2984 break;
2985#endif /* m68851 */
2986 case '3':
2987 switch (opP->reg)
2988 {
2989 case TT0:
2990 tmpreg = 2;
2991 break;
2992 case TT1:
2993 tmpreg = 3;
2994 break;
2995 default:
2996 abort ();
2997 }
2998 install_operand (s[1], tmpreg);
2999 break;
3000 case 't':
3001 tmpreg = get_num (&opP->disp, 20);
3002 install_operand (s[1], tmpreg);
3003 break;
3004 case '_': /* used only for move16 absolute 32-bit address */
3005 if (isvar (&opP->disp))
3006 add_fix ('l', &opP->disp, 0, 0);
3007 tmpreg = get_num (&opP->disp, 80);
3008 addword (tmpreg >> 16);
3009 addword (tmpreg & 0xFFFF);
3010 break;
6da466c7
ILT		 3011 case 'u':
3012 install_operand (s[1], opP->reg - DATA0L);
3013 opP->reg -= (DATA0L);
3014 opP->reg &= 0x0F; /* remove upper/lower bit */
3015 break;
252b5132
RH		 3016 default:
3017 abort ();
3018 }
3019 }
3020
3021 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3022 instruction, ready to be emitted. . . */
252b5132
RH		 3023}
3024
3025static int
3026reverse_16_bits (in)
3027 int in;
3028{
3029 int out = 0;
3030 int n;
3031
3032 static int mask[16] =
3033 {
3034 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3035 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3036 };
3037 for (n = 0; n < 16; n++)
3038 {
3039 if (in & mask[n])
3040 out |= mask[15 - n];
3041 }
3042 return out;
3043} /* reverse_16_bits() */
3044
3045static int
3046reverse_8_bits (in)
3047 int in;
3048{
3049 int out = 0;
3050 int n;
3051
3052 static int mask[8] =
3053 {
3054 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3055 };
3056
3057 for (n = 0; n < 8; n++)
3058 {
3059 if (in & mask[n])
3060 out |= mask[7 - n];
3061 }
3062 return out;
3063} /* reverse_8_bits() */
3064
3065/* Cause an extra frag to be generated here, inserting up to 10 bytes
3066 (that value is chosen in the frag_var call in md_assemble). TYPE
3067 is the subtype of the frag to be generated; its primary type is
3068 rs_machine_dependent.
3069
3070 The TYPE parameter is also used by md_convert_frag_1 and
3071 md_estimate_size_before_relax. The appropriate type of fixup will
3072 be emitted by md_convert_frag_1.
3073
3074 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3075static void
3076install_operand (mode, val)
3077 int mode;
3078 int val;
3079{
3080 switch (mode)
3081 {
3082 case 's':
3083 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3084 break;
3085 case 'd':
3086 the_ins.opcode[0] |= val << 9;
3087 break;
3088 case '1':
3089 the_ins.opcode[1] |= val << 12;
3090 break;
3091 case '2':
3092 the_ins.opcode[1] |= val << 6;
3093 break;
3094 case '3':
3095 the_ins.opcode[1] |= val;
3096 break;
3097 case '4':
3098 the_ins.opcode[2] |= val << 12;
3099 break;
3100 case '5':
3101 the_ins.opcode[2] |= val << 6;
3102 break;
3103 case '6':
3104 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3105 three words long! */
3106 the_ins.numo++;
3107 the_ins.opcode[2] |= val;
3108 break;
3109 case '7':
3110 the_ins.opcode[1] |= val << 7;
3111 break;
3112 case '8':
3113 the_ins.opcode[1] |= val << 10;
3114 break;
3115#ifndef NO_68851
3116 case '9':
3117 the_ins.opcode[1] |= val << 5;
3118 break;
3119#endif
3120
3121 case 't':
3122 the_ins.opcode[1] |= (val << 10) | (val << 7);
3123 break;
3124 case 'D':
3125 the_ins.opcode[1] |= (val << 12) | val;
3126 break;
3127 case 'g':
3128 the_ins.opcode[0] |= val = 0xff;
3129 break;
3130 case 'i':
3131 the_ins.opcode[0] |= val << 9;
3132 break;
3133 case 'C':
3134 the_ins.opcode[1] |= val;
3135 break;
3136 case 'j':
3137 the_ins.opcode[1] |= val;
3138 the_ins.numo++; /* What a hack */
3139 break;
3140 case 'k':
3141 the_ins.opcode[1] |= val << 4;
3142 break;
3143 case 'b':
3144 case 'w':
3145 case 'W':
3146 case 'l':
3147 break;
3148 case 'e':
3149 the_ins.opcode[0] |= (val << 6);
3150 break;
3151 case 'L':
3152 the_ins.opcode[1] = (val >> 16);
3153 the_ins.opcode[2] = val & 0xffff;
3154 break;
6da466c7
ILT		 3155 case 'm':
3156 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3157 the_ins.opcode[0] |= ((val & 0x7) << 9);
3158 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3159 break;
3160 case 'n':
3161 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3162 the_ins.opcode[0] |= ((val & 0x7) << 9);
3163 break;
3164 case 'o':
3165 the_ins.opcode[1] |= val << 12;
3166 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3167 break;
3168 case 'M':
3169 the_ins.opcode[0] |= (val & 0xF);
3170 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3171 break;
3172 case 'N':
3173 the_ins.opcode[1] |= (val & 0xF);
3174 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3175 break;
3176 case 'h':
3177 the_ins.opcode[1] |= ((val != 1) << 10);
3178 break;
252b5132
RH		 3179 case 'c':
3180 default:
3181 as_fatal (_("failed sanity check."));
3182 }
3183} /* install_operand() */
3184
3185static void
3186install_gen_operand (mode, val)
3187 int mode;
3188 int val;
3189{
3190 switch (mode)
3191 {
3192 case 's':
3193 the_ins.opcode[0] |= val;
3194 break;
3195 case 'd':
3196 /* This is a kludge!!! */
3197 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3198 break;
3199 case 'b':
3200 case 'w':
3201 case 'l':
3202 case 'f':
3203 case 'F':
3204 case 'x':
3205 case 'p':
3206 the_ins.opcode[0] |= val;
3207 break;
3208 /* more stuff goes here */
3209 default:
3210 as_fatal (_("failed sanity check."));
3211 }
3212} /* install_gen_operand() */
3213
3214/*
3215 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3216 * then deal with the bitfield hack.
3217 */
3218
3219static char *
3220crack_operand (str, opP)
3221 register char *str;
3222 register struct m68k_op *opP;
3223{
3224 register int parens;
3225 register int c;
3226 register char *beg_str;
3227 int inquote = 0;
3228
3229 if (!str)
3230 {
3231 return str;
3232 }
3233 beg_str = str;
3234 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3235 {
3236 if (! inquote)
3237 {
3238 if (*str == '(')
3239 parens++;
3240 else if (*str == ')')
3241 {
3242 if (!parens)
3243 { /* ERROR */
3244 opP->error = _("Extra )");
3245 return str;
3246 }
3247 --parens;
3248 }
3249 }
3250 if (flag_mri && *str == '\'')
3251 inquote = ! inquote;
3252 }
3253 if (!*str && parens)
3254 { /* ERROR */
3255 opP->error = _("Missing )");
3256 return str;
3257 }
3258 c = *str;
3259 *str = '\0';
3260 if (m68k_ip_op (beg_str, opP) != 0)
3261 {
3262 *str = c;
3263 return str;
3264 }
3265 *str = c;
3266 if (c == '}')
3267 c = *++str; /* JF bitfield hack */
3268 if (c)
3269 {
3270 c = *++str;
3271 if (!c)
3272 as_bad (_("Missing operand"));
3273 }
3274
3275 /* Detect MRI REG symbols and convert them to REGLSTs. */
3276 if (opP->mode == CONTROL && (int)opP->reg < 0)
3277 {
3278 opP->mode = REGLST;
3279 opP->mask = ~(int)opP->reg;
3280 opP->reg = 0;
3281 }
3282
3283 return str;
3284}
3285
3286/* This is the guts of the machine-dependent assembler. STR points to a
3287 machine dependent instruction. This function is supposed to emit
3288 the frags/bytes it assembles to.
3289 */
3290
3291static void
3292insert_reg (regname, regnum)
3293 const char *regname;
3294 int regnum;
3295{
3296 char buf[100];
3297 int i;
3298
3299#ifdef REGISTER_PREFIX
3300 if (!flag_reg_prefix_optional)
3301 {
3302 buf[0] = REGISTER_PREFIX;
3303 strcpy (buf + 1, regname);
3304 regname = buf;
3305 }
3306#endif
3307
3308 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3309 &zero_address_frag));
3310
3311 for (i = 0; regname[i]; i++)
3312 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3313 buf[i] = '\0';
3314
3315 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3316 &zero_address_frag));
3317}
3318
3319struct init_entry
3320 {
3321 const char *name;
3322 int number;
3323 };
3324
3325static const struct init_entry init_table[] =
3326{
3327 { "d0", DATA0 },
3328 { "d1", DATA1 },
3329 { "d2", DATA2 },
3330 { "d3", DATA3 },
3331 { "d4", DATA4 },
3332 { "d5", DATA5 },
3333 { "d6", DATA6 },
3334 { "d7", DATA7 },
3335 { "a0", ADDR0 },
3336 { "a1", ADDR1 },
3337 { "a2", ADDR2 },
3338 { "a3", ADDR3 },
3339 { "a4", ADDR4 },
3340 { "a5", ADDR5 },
3341 { "a6", ADDR6 },
3342 { "fp", ADDR6 },
3343 { "a7", ADDR7 },
3344 { "sp", ADDR7 },
3345 { "ssp", ADDR7 },
3346 { "fp0", FP0 },
3347 { "fp1", FP1 },
3348 { "fp2", FP2 },
3349 { "fp3", FP3 },
3350 { "fp4", FP4 },
3351 { "fp5", FP5 },
3352 { "fp6", FP6 },
3353 { "fp7", FP7 },
3354 { "fpi", FPI },
3355 { "fpiar", FPI },
3356 { "fpc", FPI },
3357 { "fps", FPS },
3358 { "fpsr", FPS },
3359 { "fpc", FPC },
3360 { "fpcr", FPC },
3361 { "control", FPC },
3362 { "status", FPS },
3363 { "iaddr", FPI },
3364
3365 { "cop0", COP0 },
3366 { "cop1", COP1 },
3367 { "cop2", COP2 },
3368 { "cop3", COP3 },
3369 { "cop4", COP4 },
3370 { "cop5", COP5 },
3371 { "cop6", COP6 },
3372 { "cop7", COP7 },
3373 { "pc", PC },
3374 { "zpc", ZPC },
3375 { "sr", SR },
3376
3377 { "ccr", CCR },
3378 { "cc", CCR },
3379
6da466c7
ILT		 3380 { "acc", ACC },
3381 { "macsr", MACSR },
3382 { "mask", MASK },
3383
252b5132
RH		 3384 /* control registers */
3385 { "sfc", SFC }, /* Source Function Code */
3386 { "sfcr", SFC },
3387 { "dfc", DFC }, /* Destination Function Code */
3388 { "dfcr", DFC },
3389 { "cacr", CACR }, /* Cache Control Register */
3390 { "caar", CAAR }, /* Cache Address Register */
3391
3392 { "usp", USP }, /* User Stack Pointer */
3393 { "vbr", VBR }, /* Vector Base Register */
3394 { "msp", MSP }, /* Master Stack Pointer */
3395 { "isp", ISP }, /* Interrupt Stack Pointer */
3396
3397 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3398 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3399 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3400 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3401
3402 /* 68ec040 versions of same */
3403 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3404 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3405 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3406 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3407
3408 /* mcf5200 versions of same. The ColdFire programmer's reference
3409 manual indicated that the order is 2,3,0,1, but Ken Rose
3410 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3411 { "acr0", ITT0 }, /* Access Control Unit 0 */
3412 { "acr1", ITT1 }, /* Access Control Unit 1 */
3413 { "acr2", DTT0 }, /* Access Control Unit 2 */
3414 { "acr3", DTT1 }, /* Access Control Unit 3 */
3415
3416 { "tc", TC }, /* MMU Translation Control Register */
3417 { "tcr", TC },
3418
3419 { "mmusr", MMUSR }, /* MMU Status Register */
3420 { "srp", SRP }, /* User Root Pointer */
3421 { "urp", URP }, /* Supervisor Root Pointer */
3422
3423 { "buscr", BUSCR },
3424 { "pcr", PCR },
3425
3426 { "rombar", ROMBAR }, /* ROM Base Address Register */
3427 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3428 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3429 { "mbar", MBAR }, /* Module Base Address Register */
3430 /* end of control registers */
3431
3432 { "ac", AC },
3433 { "bc", BC },
3434 { "cal", CAL },
3435 { "crp", CRP },
3436 { "drp", DRP },
3437 { "pcsr", PCSR },
3438 { "psr", PSR },
3439 { "scc", SCC },
3440 { "val", VAL },
3441 { "bad0", BAD0 },
3442 { "bad1", BAD1 },
3443 { "bad2", BAD2 },
3444 { "bad3", BAD3 },
3445 { "bad4", BAD4 },
3446 { "bad5", BAD5 },
3447 { "bad6", BAD6 },
3448 { "bad7", BAD7 },
3449 { "bac0", BAC0 },
3450 { "bac1", BAC1 },
3451 { "bac2", BAC2 },
3452 { "bac3", BAC3 },
3453 { "bac4", BAC4 },
3454 { "bac5", BAC5 },
3455 { "bac6", BAC6 },
3456 { "bac7", BAC7 },
3457
3458 { "ic", IC },
3459 { "dc", DC },
3460 { "nc", NC },
3461
3462 { "tt0", TT0 },
3463 { "tt1", TT1 },
3464 /* 68ec030 versions of same */
3465 { "ac0", TT0 },
3466 { "ac1", TT1 },
3467 /* 68ec030 access control unit, identical to 030 MMU status reg */
3468 { "acusr", PSR },
3469
3470 /* Suppressed data and address registers. */
3471 { "zd0", ZDATA0 },
3472 { "zd1", ZDATA1 },
3473 { "zd2", ZDATA2 },
3474 { "zd3", ZDATA3 },
3475 { "zd4", ZDATA4 },
3476 { "zd5", ZDATA5 },
3477 { "zd6", ZDATA6 },
3478 { "zd7", ZDATA7 },
3479 { "za0", ZADDR0 },
3480 { "za1", ZADDR1 },
3481 { "za2", ZADDR2 },
3482 { "za3", ZADDR3 },
3483 { "za4", ZADDR4 },
3484 { "za5", ZADDR5 },
3485 { "za6", ZADDR6 },
3486 { "za7", ZADDR7 },
3487
92774660 3488 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3489 { "d0l", DATA0L },
3490 { "d1l", DATA1L },
3491 { "d2l", DATA2L },
3492 { "d3l", DATA3L },
3493 { "d4l", DATA4L },
3494 { "d5l", DATA5L },
3495 { "d6l", DATA6L },
3496 { "d7l", DATA7L },
3497
3498 { "a0l", ADDR0L },
3499 { "a1l", ADDR1L },
3500 { "a2l", ADDR2L },
3501 { "a3l", ADDR3L },
3502 { "a4l", ADDR4L },
3503 { "a5l", ADDR5L },
3504 { "a6l", ADDR6L },
3505 { "a7l", ADDR7L },
3506
3507 { "d0u", DATA0U },
3508 { "d1u", DATA1U },
3509 { "d2u", DATA2U },
3510 { "d3u", DATA3U },
3511 { "d4u", DATA4U },
3512 { "d5u", DATA5U },
3513 { "d6u", DATA6U },
3514 { "d7u", DATA7U },
3515
3516 { "a0u", ADDR0U },
3517 { "a1u", ADDR1U },
3518 { "a2u", ADDR2U },
3519 { "a3u", ADDR3U },
3520 { "a4u", ADDR4U },
3521 { "a5u", ADDR5U },
3522 { "a6u", ADDR6U },
3523 { "a7u", ADDR7U },
3524
252b5132
RH		 3525 { 0, 0 }
3526};
3527
3528static void
3529init_regtable ()
3530{
3531 int i;
3532 for (i = 0; init_table[i].name; i++)
3533 insert_reg (init_table[i].name, init_table[i].number);
3534}
3535
3536static int no_68851, no_68881;
3537
3538#ifdef OBJ_AOUT
3539/* a.out machine type. Default to 68020. */
3540int m68k_aout_machtype = 2;
3541#endif
3542
3543void
3544md_assemble (str)
3545 char *str;
3546{
3547 const char *er;
3548 short *fromP;
3549 char *toP = NULL;
3550 int m, n = 0;
3551 char *to_beg_P;
3552 int shorts_this_frag;
3553 fixS *fixP;
3554
3555 /* In MRI mode, the instruction and operands are separated by a
3556 space. Anything following the operands is a comment. The label
3557 has already been removed. */
3558 if (flag_mri)
3559 {
3560 char *s;
3561 int fields = 0;
3562 int infield = 0;
3563 int inquote = 0;
3564
3565 for (s = str; *s != '\0'; s++)
3566 {
3567 if ((*s == ' ' || *s == '\t') && ! inquote)
3568 {
3569 if (infield)
3570 {
3571 ++fields;
3572 if (fields >= 2)
3573 {
3574 *s = '\0';
3575 break;
3576 }
3577 infield = 0;
3578 }
3579 }
3580 else
3581 {
3582 if (! infield)
3583 infield = 1;
3584 if (*s == '\'')
3585 inquote = ! inquote;
3586 }
3587 }
3588 }
3589
3590 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3591 m68k_ip (str);
3592 er = the_ins.error;
3593 if (!er)
3594 {
3595 for (n = 0; n < the_ins.numargs; n++)
3596 if (the_ins.operands[n].error)
3597 {
3598 er = the_ins.operands[n].error;
3599 break;
3600 }
3601 }
3602 if (er)
3603 {
3604 as_bad (_("%s -- statement `%s' ignored"), er, str);
3605 return;
3606 }
3607
3608 /* If there is a current label, record that it marks an instruction. */
3609 if (current_label != NULL)
3610 {
3611 current_label->text = 1;
3612 current_label = NULL;
3613 }
3614
3615 if (the_ins.nfrag == 0)
3616 {
3617 /* No frag hacking involved; just put it out */
3618 toP = frag_more (2 * the_ins.numo);
3619 fromP = &the_ins.opcode[0];
3620 for (m = the_ins.numo; m; --m)
3621 {
3622 md_number_to_chars (toP, (long) (*fromP), 2);
3623 toP += 2;
3624 fromP++;
3625 }
3626 /* put out symbol-dependent info */
3627 for (m = 0; m < the_ins.nrel; m++)
3628 {
3629 switch (the_ins.reloc[m].wid)
3630 {
3631 case 'B':
3632 n = 1;
3633 break;
3634 case 'b':
3635 n = 1;
3636 break;
3637 case '3':
3638 n = 1;
3639 break;
3640 case 'w':
3641 case 'W':
3642 n = 2;
3643 break;
3644 case 'l':
3645 n = 4;
3646 break;
3647 default:
3648 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3649 the_ins.reloc[m].wid);
3650 }
3651
3652 fixP = fix_new_exp (frag_now,
3653 ((toP - frag_now->fr_literal)
3654 - the_ins.numo * 2 + the_ins.reloc[m].n),
3655 n,
3656 &the_ins.reloc[m].exp,
3657 the_ins.reloc[m].pcrel,
3658 get_reloc_code (n, the_ins.reloc[m].pcrel,
3659 the_ins.reloc[m].pic_reloc));
3660 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3661 if (the_ins.reloc[m].wid == 'B')
3662 fixP->fx_signed = 1;
3663 }
3664 return;
3665 }
3666
3667 /* There's some frag hacking */
fbe572f9
AM		 3668 {
3669 /* Calculate the max frag size. */
3670 int wid;
3671
3672 wid = 2 * the_ins.fragb[0].fragoff;
3673 for (n = 1; n < the_ins.nfrag; n++)
3674 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3675 /* frag_var part. */
3676 wid += 10;
3677 /* Make sure the whole insn fits in one chunk, in particular that
3678 the var part is attached, as we access one byte before the
3679 variable frag for byte branches. */
3680 frag_grow (wid);
3681 }
3682
252b5132
RH		 3683 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3684 {
3685 int wid;
3686
3687 if (n == 0)
3688 wid = 2 * the_ins.fragb[n].fragoff;
3689 else
3690 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3691 toP = frag_more (wid);
3692 to_beg_P = toP;
3693 shorts_this_frag = 0;
3694 for (m = wid / 2; m; --m)
3695 {
3696 md_number_to_chars (toP, (long) (*fromP), 2);
3697 toP += 2;
3698 fromP++;
3699 shorts_this_frag++;
3700 }
3701 for (m = 0; m < the_ins.nrel; m++)
3702 {
3703 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3704 {
3705 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3706 break;
3707 }
3708 wid = the_ins.reloc[m].wid;
3709 if (wid == 0)
3710 continue;
3711 the_ins.reloc[m].wid = 0;
3712 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3713
3714 fixP = fix_new_exp (frag_now,
3715 ((toP - frag_now->fr_literal)
3716 - the_ins.numo * 2 + the_ins.reloc[m].n),
3717 wid,
3718 &the_ins.reloc[m].exp,
3719 the_ins.reloc[m].pcrel,
3720 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3721 the_ins.reloc[m].pic_reloc));
3722 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3723 }
3724 (void) frag_var (rs_machine_dependent, 10, 0,
3725 (relax_substateT) (the_ins.fragb[n].fragty),
3726 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3727 }
3728 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3729 shorts_this_frag = 0;
3730 if (n)
3731 {
3732 toP = frag_more (n * sizeof (short));
3733 while (n--)
3734 {
3735 md_number_to_chars (toP, (long) (*fromP), 2);
3736 toP += 2;
3737 fromP++;
3738 shorts_this_frag++;
3739 }
3740 }
3741 for (m = 0; m < the_ins.nrel; m++)
3742 {
3743 int wid;
3744
3745 wid = the_ins.reloc[m].wid;
3746 if (wid == 0)
3747 continue;
3748 the_ins.reloc[m].wid = 0;
3749 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3750
3751 fixP = fix_new_exp (frag_now,
3752 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3753 - shorts_this_frag * 2),
3754 wid,
3755 &the_ins.reloc[m].exp,
3756 the_ins.reloc[m].pcrel,
3757 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3758 the_ins.reloc[m].pic_reloc));
3759 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3760 }
3761}
3762
3763void
3764md_begin ()
3765{
3766 /*
3767 * md_begin -- set up hash tables with 68000 instructions.
3768 * similar to what the vax assembler does. ---phr
3769 */
3770 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3771 a copy of it at runtime, adding in the information we want but isn't
3772 there. I think it'd be better to have an awk script hack the table
3773 at compile time. Or even just xstr the table and use it as-is. But
3774 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3775 names. */
3776
3777 register const struct m68k_opcode *ins;
3778 register struct m68k_incant *hack, *slak;
3779 register const char *retval = 0; /* empty string, or error msg text */
8fce3f5e 3780 register int i;
252b5132
RH		 3781 register char c;
3782
3783 if (flag_mri)
3784 {
3785 flag_reg_prefix_optional = 1;
3786 m68k_abspcadd = 1;
3787 if (! m68k_rel32_from_cmdline)
3788 m68k_rel32 = 0;
3789 }
3790
3791 op_hash = hash_new ();
3792
3793 obstack_begin (&robyn, 4000);
3794 for (i = 0; i < m68k_numopcodes; i++)
3795 {
3796 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3797 do
3798 {
3799 ins = &m68k_opcodes[i];
3800 /* We *could* ignore insns that don't match our arch here
92774660 3801 but just leaving them out of the hash. */
252b5132
RH		 3802 slak->m_operands = ins->args;
3803 slak->m_opnum = strlen (slak->m_operands) / 2;
3804 slak->m_arch = ins->arch;
3805 slak->m_opcode = ins->opcode;
3806 /* This is kludgey */
3807 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3808 if (i + 1 != m68k_numopcodes
3809 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3810 {
3811 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3812 i++;
3813 }
3814 else
3815 slak->m_next = 0;
3816 slak = slak->m_next;
3817 }
3818 while (slak);
3819
3820 retval = hash_insert (op_hash, ins->name, (char *) hack);
3821 if (retval)
3822 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3823 }
3824
3825 for (i = 0; i < m68k_numaliases; i++)
3826 {
3827 const char *name = m68k_opcode_aliases[i].primary;
3828 const char *alias = m68k_opcode_aliases[i].alias;
3829 PTR val = hash_find (op_hash, name);
3830 if (!val)
3831 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3832 retval = hash_insert (op_hash, alias, val);
3833 if (retval)
3834 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3835 }
3836
3837 /* In MRI mode, all unsized branches are variable sized. Normally,
3838 they are word sized. */
3839 if (flag_mri)
3840 {
3841 static struct m68k_opcode_alias mri_aliases[] =
3842 {
3843 { "bhi", "jhi", },
3844 { "bls", "jls", },
3845 { "bcc", "jcc", },
3846 { "bcs", "jcs", },
3847 { "bne", "jne", },
3848 { "beq", "jeq", },
3849 { "bvc", "jvc", },
3850 { "bvs", "jvs", },
3851 { "bpl", "jpl", },
3852 { "bmi", "jmi", },
3853 { "bge", "jge", },
3854 { "blt", "jlt", },
3855 { "bgt", "jgt", },
3856 { "ble", "jle", },
3857 { "bra", "jra", },
3858 { "bsr", "jbsr", },
3859 };
3860
8fce3f5e
AM		 3861 for (i = 0;
3862 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3863 i++)
252b5132
RH		 3864 {
3865 const char *name = mri_aliases[i].primary;
3866 const char *alias = mri_aliases[i].alias;
3867 PTR val = hash_find (op_hash, name);
3868 if (!val)
3869 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3870 retval = hash_jam (op_hash, alias, val);
3871 if (retval)
3872 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3873 }
3874 }
3875
8fce3f5e 3876 for (i = 0; i < (int) sizeof (mklower_table); i++)
252b5132
RH		 3877 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3878
8fce3f5e 3879 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 3880 {
3881 notend_table[i] = 0;
3882 alt_notend_table[i] = 0;
3883 }
3884 notend_table[','] = 1;
3885 notend_table['{'] = 1;
3886 notend_table['}'] = 1;
3887 alt_notend_table['a'] = 1;
3888 alt_notend_table['A'] = 1;
3889 alt_notend_table['d'] = 1;
3890 alt_notend_table['D'] = 1;
3891 alt_notend_table['#'] = 1;
3892 alt_notend_table['&'] = 1;
3893 alt_notend_table['f'] = 1;
3894 alt_notend_table['F'] = 1;
3895#ifdef REGISTER_PREFIX
3896 alt_notend_table[REGISTER_PREFIX] = 1;
3897#endif
3898
3899 /* We need to put '(' in alt_notend_table to handle
3900 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3901 */
3902 alt_notend_table['('] = 1;
3903
3904 /* We need to put '@' in alt_notend_table to handle
3905 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3906 */
3907 alt_notend_table['@'] = 1;
3908
3909 /* We need to put digits in alt_notend_table to handle
3910 bfextu %d0{24:1},%d0
3911 */
3912 alt_notend_table['0'] = 1;
3913 alt_notend_table['1'] = 1;
3914 alt_notend_table['2'] = 1;
3915 alt_notend_table['3'] = 1;
3916 alt_notend_table['4'] = 1;
3917 alt_notend_table['5'] = 1;
3918 alt_notend_table['6'] = 1;
3919 alt_notend_table['7'] = 1;
3920 alt_notend_table['8'] = 1;
3921 alt_notend_table['9'] = 1;
3922
3923#ifndef MIT_SYNTAX_ONLY
3924 /* Insert pseudo ops, these have to go into the opcode table since
3925 gas expects pseudo ops to start with a dot */
3926 {
3927 int n = 0;
3928 while (mote_pseudo_table[n].poc_name)
3929 {
3930 hack = (struct m68k_incant *)
3931 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3932 hash_insert (op_hash,
3933 mote_pseudo_table[n].poc_name, (char *) hack);
3934 hack->m_operands = 0;
3935 hack->m_opnum = n;
3936 n++;
3937 }
3938 }
3939#endif
3940
3941 init_regtable ();
3942
3943#ifdef OBJ_ELF
3944 record_alignment (text_section, 2);
3945 record_alignment (data_section, 2);
3946 record_alignment (bss_section, 2);
3947#endif
3948}
3949
3950static void
3951select_control_regs ()
3952{
3953 /* Note which set of "movec" control registers is available. */
3954 switch (cpu_of_arch (current_architecture))
3955 {
3956 case m68000:
3957 control_regs = m68000_control_regs;
3958 break;
3959 case m68010:
3960 control_regs = m68010_control_regs;
3961 break;
3962 case m68020:
3963 case m68030:
3964 control_regs = m68020_control_regs;
3965 break;
3966 case m68040:
3967 control_regs = m68040_control_regs;
3968 break;
3969 case m68060:
3970 control_regs = m68060_control_regs;
3971 break;
3972 case cpu32:
3973 control_regs = cpu32_control_regs;
3974 break;
3975 case mcf5200:
6da466c7
ILT		 3976 case mcf5206e:
3977 case mcf5307:
dc84e067 3978 case mcf5407:
6da466c7 3979 control_regs = mcf_control_regs;
252b5132
RH		 3980 break;
3981 default:
3982 abort ();
3983 }
3984}
3985
3986void
3987m68k_init_after_args ()
3988{
3989 if (cpu_of_arch (current_architecture) == 0)
3990 {
3991 int i;
3992 const char *default_cpu = TARGET_CPU;
3993
3994 if (*default_cpu == 'm')
3995 default_cpu++;
3996 for (i = 0; i < n_archs; i++)
3997 if (strcasecmp (default_cpu, archs[i].name) == 0)
3998 break;
3999 if (i == n_archs)
4000 {
4001 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4002 current_architecture |= m68020;
4003 }
4004 else
4005 current_architecture |= archs[i].arch;
4006 }
4007 /* Permit m68881 specification with all cpus; those that can't work
4008 with a coprocessor could be doing emulation. */
4009 if (current_architecture & m68851)
4010 {
4011 if (current_architecture & m68040)
4012 {
4013 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4014 }
4015 }
4016 /* What other incompatibilities could we check for? */
4017
4018 /* Toss in some default assumptions about coprocessors. */
4019 if (!no_68881
4020 && (cpu_of_arch (current_architecture)
4021 /* Can CPU32 have a 68881 coprocessor?? */
4022 & (m68020 | m68030 | cpu32)))
4023 {
4024 current_architecture |= m68881;
4025 }
4026 if (!no_68851
4027 && (cpu_of_arch (current_architecture) & m68020up) != 0
4028 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4029 {
4030 current_architecture |= m68851;
4031 }
4032 if (no_68881 && (current_architecture & m68881))
4033 as_bad (_("options for 68881 and no-68881 both given"));
4034 if (no_68851 && (current_architecture & m68851))
4035 as_bad (_("options for 68851 and no-68851 both given"));
4036
4037#ifdef OBJ_AOUT
4038 /* Work out the magic number. This isn't very general. */
4039 if (current_architecture & m68000)
4040 m68k_aout_machtype = 0;
4041 else if (current_architecture & m68010)
4042 m68k_aout_machtype = 1;
4043 else if (current_architecture & m68020)
4044 m68k_aout_machtype = 2;
4045 else
4046 m68k_aout_machtype = 2;
4047#endif
4048
4049 /* Note which set of "movec" control registers is available. */
4050 select_control_regs ();
4051
4052 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4053 || arch_coldfire_p (current_architecture))
252b5132
RH		 4054 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4055}
4056\f
4057/* This is called when a label is defined. */
4058
4059void
4060m68k_frob_label (sym)
4061 symbolS *sym;
4062{
4063 struct label_line *n;
4064
4065 n = (struct label_line *) xmalloc (sizeof *n);
4066 n->next = labels;
4067 n->label = sym;
4068 as_where (&n->file, &n->line);
4069 n->text = 0;
4070 labels = n;
4071 current_label = n;
4072}
4073
4074/* This is called when a value that is not an instruction is emitted. */
4075
4076void
4077m68k_flush_pending_output ()
4078{
4079 current_label = NULL;
4080}
4081
4082/* This is called at the end of the assembly, when the final value of
4083 the label is known. We warn if this is a text symbol aligned at an
4084 odd location. */
4085
4086void
4087m68k_frob_symbol (sym)
4088 symbolS *sym;
4089{
4090 if (S_GET_SEGMENT (sym) == reg_section
4091 && (int) S_GET_VALUE (sym) < 0)
4092 {
4093 S_SET_SEGMENT (sym, absolute_section);
4094 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4095 }
4096 else if ((S_GET_VALUE (sym) & 1) != 0)
4097 {
4098 struct label_line *l;
4099
4100 for (l = labels; l != NULL; l = l->next)
4101 {
4102 if (l->label == sym)
4103 {
4104 if (l->text)
4105 as_warn_where (l->file, l->line,
4106 _("text label `%s' aligned to odd boundary"),
4107 S_GET_NAME (sym));
4108 break;
4109 }
4110 }
4111 }
4112}
4113\f
4114/* This is called if we go in or out of MRI mode because of the .mri
4115 pseudo-op. */
4116
4117void
4118m68k_mri_mode_change (on)
4119 int on;
4120{
4121 if (on)
4122 {
4123 if (! flag_reg_prefix_optional)
4124 {
4125 flag_reg_prefix_optional = 1;
4126#ifdef REGISTER_PREFIX
4127 init_regtable ();
4128#endif
4129 }
4130 m68k_abspcadd = 1;
4131 if (! m68k_rel32_from_cmdline)
4132 m68k_rel32 = 0;
4133 }
4134 else
4135 {
4136 if (! reg_prefix_optional_seen)
4137 {
4138#ifdef REGISTER_PREFIX_OPTIONAL
4139 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4140#else
4141 flag_reg_prefix_optional = 0;
4142#endif
4143#ifdef REGISTER_PREFIX
4144 init_regtable ();
4145#endif
4146 }
4147 m68k_abspcadd = 0;
4148 if (! m68k_rel32_from_cmdline)
4149 m68k_rel32 = 1;
4150 }
4151}
4152
4153/* Equal to MAX_PRECISION in atof-ieee.c */
4154#define MAX_LITTLENUMS 6
4155
4156/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4157 of type TYPE, and store the appropriate bytes in *LITP. The number
4158 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4159 returned, or NULL on OK. */
4160
4161char *
4162md_atof (type, litP, sizeP)
4163 char type;
4164 char *litP;
4165 int *sizeP;
4166{
4167 int prec;
4168 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4169 LITTLENUM_TYPE *wordP;
4170 char *t;
4171
4172 switch (type)
4173 {
4174 case 'f':
4175 case 'F':
4176 case 's':
4177 case 'S':
4178 prec = 2;
4179 break;
4180
4181 case 'd':
4182 case 'D':
4183 case 'r':
4184 case 'R':
4185 prec = 4;
4186 break;
4187
4188 case 'x':
4189 case 'X':
4190 prec = 6;
4191 break;
4192
4193 case 'p':
4194 case 'P':
4195 prec = 6;
4196 break;
4197
4198 default:
4199 *sizeP = 0;
4200 return _("Bad call to MD_ATOF()");
4201 }
4202 t = atof_ieee (input_line_pointer, type, words);
4203 if (t)
4204 input_line_pointer = t;
4205
4206 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4207 for (wordP = words; prec--;)
4208 {
4209 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4210 litP += sizeof (LITTLENUM_TYPE);
4211 }
4212 return 0;
4213}
4214
4215void
4216md_number_to_chars (buf, val, n)
4217 char *buf;
4218 valueT val;
4219 int n;
4220{
4221 number_to_chars_bigendian (buf, val, n);
4222}
4223
4224static void
4225md_apply_fix_2 (fixP, val)
4226 fixS *fixP;
4227 offsetT val;
4228{
4229 addressT upper_limit;
4230 offsetT lower_limit;
4231
4232 /* This is unnecessary but it convinces the native rs6000 compiler
4233 to generate the code we want. */
4234 char *buf = fixP->fx_frag->fr_literal;
4235 buf += fixP->fx_where;
4236 /* end ibm compiler workaround */
4237
c801568a 4238 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132
RH		 4239
4240#ifdef OBJ_ELF
4241 if (fixP->fx_addsy)
4242 {
4243 memset (buf, 0, fixP->fx_size);
4244 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4245
4246 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4247 && !S_IS_DEFINED (fixP->fx_addsy)
4248 && !S_IS_WEAK (fixP->fx_addsy))
4249 S_SET_WEAK (fixP->fx_addsy);
4250 return;
4251 }
4252#endif
4253
4254#ifdef BFD_ASSEMBLER
4255 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4256 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4257 return;
4258#endif
4259
4260 switch (fixP->fx_size)
4261 {
4262 /* The cast to offsetT below are necessary to make code correct for
4263 machines where ints are smaller than offsetT */
4264 case 1:
4265 *buf++ = val;
4266 upper_limit = 0x7f;
4267 lower_limit = - (offsetT) 0x80;
4268 break;
4269 case 2:
4270 *buf++ = (val >> 8);
4271 *buf++ = val;
4272 upper_limit = 0x7fff;
4273 lower_limit = - (offsetT) 0x8000;
4274 break;
4275 case 4:
4276 *buf++ = (val >> 24);
4277 *buf++ = (val >> 16);
4278 *buf++ = (val >> 8);
4279 *buf++ = val;
4280 upper_limit = 0x7fffffff;
4281 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4282 break;
4283 default:
4284 BAD_CASE (fixP->fx_size);
4285 }
4286
4287 /* Fix up a negative reloc. */
4288 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4289 {
4290 fixP->fx_addsy = fixP->fx_subsy;
4291 fixP->fx_subsy = NULL;
4292 fixP->fx_tcbit = 1;
4293 }
4294
4295 /* For non-pc-relative values, it's conceivable we might get something
4296 like "0xff" for a byte field. So extend the upper part of the range
4297 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4298 so that we can do any range checking at all. */
4299 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4300 upper_limit = upper_limit * 2 + 1;
4301
4302 if ((addressT) val > upper_limit
4303 && (val > 0 || val < lower_limit))
4304 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4305
4306 /* A one byte PC-relative reloc means a short branch. We can't use
4307 a short branch with a value of 0 or -1, because those indicate
4308 different opcodes (branches with longer offsets). fixup_segment
4309 in write.c may have clobbered fx_pcrel, so we need to examine the
4310 reloc type. */
4311 if ((fixP->fx_pcrel
4312#ifdef BFD_ASSEMBLER
4313 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4314#endif
4315 )
4316 && fixP->fx_size == 1
4317 && (fixP->fx_addsy == NULL
4318 || S_IS_DEFINED (fixP->fx_addsy))
4319 && (val == 0 || val == -1))
4320 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4321}
4322
4323#ifdef BFD_ASSEMBLER
4324int
4325md_apply_fix (fixP, valp)
4326 fixS *fixP;
4327 valueT *valp;
4328{
4329 md_apply_fix_2 (fixP, (addressT) *valp);
4330 return 1;
4331}
4332#else
4333void md_apply_fix (fixP, val)
4334 fixS *fixP;
4335 long val;
4336{
4337 md_apply_fix_2 (fixP, (addressT) val);
4338}
4339#endif
4340
4341/* *fragP has been relaxed to its final size, and now needs to have
4342 the bytes inside it modified to conform to the new size There is UGLY
4343 MAGIC here. ..
4344 */
4345static void
4346md_convert_frag_1 (fragP)
4347 register fragS *fragP;
4348{
4349 long disp;
252b5132
RH		 4350 fixS *fixP;
4351
4352 /* Address in object code of the displacement. */
4353 register int object_address = fragP->fr_fix + fragP->fr_address;
4354
4355 /* Address in gas core of the place to store the displacement. */
4356 /* This convinces the native rs6000 compiler to generate the code we
92774660 4357 want. */
252b5132
RH		 4358 register char *buffer_address = fragP->fr_literal;
4359 buffer_address += fragP->fr_fix;
4360 /* end ibm compiler workaround */
4361
4362 /* The displacement of the address, from current location. */
4363 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4364 disp = (disp + fragP->fr_offset) - object_address;
4365
4366#ifdef BFD_ASSEMBLER
49309057 4367 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
252b5132
RH		 4368#endif
4369
4370 switch (fragP->fr_subtype)
4371 {
151337e8
NC		 4372 case TAB (BRANCHBWL, BYTE):
4373 case TAB (BRABSJUNC, BYTE):
4374 case TAB (BRABSJCOND, BYTE):
4375 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4376 know (issbyte (disp));
4377 if (disp == 0)
b091f402
AM		 4378 as_bad_where (fragP->fr_file, fragP->fr_line,
4379 _("short branch with zero offset: use :w"));
151337e8 4380 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4381 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4382 fixP->fx_pcrel_adjust = -1;
252b5132 4383 break;
151337e8
NC		 4384 case TAB (BRANCHBWL, SHORT):
4385 case TAB (BRABSJUNC, SHORT):
4386 case TAB (BRABSJCOND, SHORT):
4387 case TAB (BRANCHBW, SHORT):
252b5132 4388 fragP->fr_opcode[1] = 0x00;
151337e8 4389 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4390 1, RELAX_RELOC_PC16);
151337e8
NC		 4391 fragP->fr_fix += 2;
4392 break;
4393 case TAB (BRANCHBWL, LONG):
4394 fragP->fr_opcode[1] = (char) 0xFF;
4395 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4396 1, RELAX_RELOC_PC32);
151337e8 4397 fragP->fr_fix += 4;
252b5132 4398 break;
151337e8
NC		 4399 case TAB (BRABSJUNC, LONG):
4400 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4401 {
151337e8
NC		 4402 fragP->fr_opcode[0] = 0x4E;
4403 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4404 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4405 0, RELAX_RELOC_ABS32);
151337e8
NC		 4406 fragP->fr_fix += 4;
4407 }
4408 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4409 {
4410 fragP->fr_opcode[0] = 0x4E;
4411 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4412 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4413 0, RELAX_RELOC_ABS32);
151337e8 4414 fragP->fr_fix += 4;
252b5132
RH		 4415 }
4416 else
4417 {
151337e8
NC		 4418 /* This cannot happen, because jbsr and jbra are the only two
4419 unconditional branches. */
4420 abort ();
252b5132
RH		 4421 }
4422 break;
151337e8
NC		 4423 case TAB (BRABSJCOND, LONG):
4424 /* Only Bcc 68000 instructions can come here. */
4425 /* Change bcc into b!cc/jmp absl long. */
92774660 4426
252b5132
RH		 4427 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4428 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4429
4430 /* JF: these used to be fr_opcode[2,3], but they may be in a
4431 different frag, in which case refering to them is a no-no.
92774660 4432 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4433 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4434 *buffer_address++ = (char) 0xf9;
4435 fragP->fr_fix += 2; /* account for jmp instruction */
4436 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4437 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4438 fragP->fr_fix += 4;
4439 break;
4440 case TAB (FBRANCH, SHORT):
4441 know ((fragP->fr_opcode[1] & 0x40) == 0);
4442 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4443 1, RELAX_RELOC_PC16);
151337e8
NC		 4444 fragP->fr_fix += 2;
4445 break;
4446 case TAB (FBRANCH, LONG):
4447 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4448 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4449 1, RELAX_RELOC_PC32);
252b5132 4450 fragP->fr_fix += 4;
252b5132 4451 break;
151337e8
NC		 4452 case TAB (DBCCLBR, SHORT):
4453 case TAB (DBCCABSJ, SHORT):
4454 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4455 1, RELAX_RELOC_PC16);
151337e8
NC		 4456 fragP->fr_fix += 2;
4457 break;
4458 case TAB (DBCCLBR, LONG):
4459 /* only DBcc instructions can come here */
28e7409f 4460 /* Change dbcc into dbcc/bral. */
28e7409f 4461
252b5132
RH		 4462 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4463 *buffer_address++ = 0x00; /* branch offset = 4 */
4464 *buffer_address++ = 0x04;
4465 *buffer_address++ = 0x60; /* put in bra pc+6 */
4466 *buffer_address++ = 0x06;
151337e8
NC		 4467 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4468 *buffer_address++ = (char) 0xff;
252b5132
RH		 4469
4470 fragP->fr_fix += 6; /* account for bra/jmp instructions */
151337e8 4471 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4472 RELAX_RELOC_PC32);
252b5132 4473 fragP->fr_fix += 4;
252b5132 4474 break;
151337e8
NC		 4475 case TAB (DBCCABSJ, LONG):
4476 /* only DBcc instructions can come here */
4477 /* Change dbcc into dbcc/jmp. */
4478
4479 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4480 *buffer_address++ = 0x00; /* branch offset = 4 */
4481 *buffer_address++ = 0x04;
4482 *buffer_address++ = 0x60; /* put in bra pc+6 */
4483 *buffer_address++ = 0x06;
4484 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4485 *buffer_address++ = (char) 0xf9;
4486
4487 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4488 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4489 RELAX_RELOC_ABS32);
252b5132 4490 fragP->fr_fix += 4;
252b5132 4491 break;
151337e8 4492 case TAB (PCREL1632, SHORT):
252b5132
RH		 4493 fragP->fr_opcode[1] &= ~0x3F;
4494 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4495 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4496 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4497 fragP->fr_fix += 2;
252b5132 4498 break;
151337e8 4499 case TAB (PCREL1632, LONG):
252b5132
RH		 4500 /* Already set to mode 7.3; this indicates: PC indirect with
4501 suppressed index, 32-bit displacement. */
4502 *buffer_address++ = 0x01;
4503 *buffer_address++ = 0x70;
4504 fragP->fr_fix += 2;
151337e8 4505 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4506 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4507 fixP->fx_pcrel_adjust = 2;
4508 fragP->fr_fix += 4;
252b5132 4509 break;
252b5132 4510 case TAB (PCINDEX, BYTE):
252b5132
RH		 4511 assert (fragP->fr_fix >= 2);
4512 buffer_address[-2] &= ~1;
151337e8 4513 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4514 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4515 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4516 break;
4517 case TAB (PCINDEX, SHORT):
252b5132
RH		 4518 assert (fragP->fr_fix >= 2);
4519 buffer_address[-2] |= 0x1;
4520 buffer_address[-1] = 0x20;
4521 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4522 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4523 fixP->fx_pcrel_adjust = 2;
151337e8 4524 fragP->fr_fix += 2;
252b5132
RH		 4525 break;
4526 case TAB (PCINDEX, LONG):
252b5132
RH		 4527 assert (fragP->fr_fix >= 2);
4528 buffer_address[-2] |= 0x1;
4529 buffer_address[-1] = 0x30;
151337e8 4530 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4531 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4532 fixP->fx_pcrel_adjust = 2;
4533 fragP->fr_fix += 4;
4534 break;
4535 case TAB (ABSTOPCREL, SHORT):
4536 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4537 1, RELAX_RELOC_PC16);
151337e8
NC		 4538 fragP->fr_fix += 2;
4539 break;
4540 case TAB (ABSTOPCREL, LONG):
4541 /* The thing to do here is force it to ABSOLUTE LONG, since
4542 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4543 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4544 abort ();
4545 fragP->fr_opcode[1] &= ~0x3F;
4546 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4547 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4548 0, RELAX_RELOC_ABS32);
151337e8 4549 fragP->fr_fix += 4;
252b5132 4550 break;
252b5132
RH		 4551 }
4552}
4553
4554#ifndef BFD_ASSEMBLER
4555
4556void
4557md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4558 object_headers *headers ATTRIBUTE_UNUSED;
4559 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4560 fragS *fragP;
4561{
4562 md_convert_frag_1 (fragP);
4563}
4564
4565#else
4566
4567void
4568md_convert_frag (abfd, sec, fragP)
36823076
AS		 4569 bfd *abfd ATTRIBUTE_UNUSED;
4570 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4571 fragS *fragP;
4572{
4573 md_convert_frag_1 (fragP);
4574}
4575#endif
4576
4577/* Force truly undefined symbols to their maximum size, and generally set up
4578 the frag list to be relaxed
4579 */
4580int
4581md_estimate_size_before_relax (fragP, segment)
4582 register fragS *fragP;
4583 segT segment;
4584{
4585 int old_fix;
252b5132
RH		 4586
4587 old_fix = fragP->fr_fix;
4588
151337e8 4589 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4590 switch (fragP->fr_subtype)
4591 {
151337e8
NC		 4592 case TAB (BRANCHBWL, SZ_UNDEF):
4593 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4594 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4595 {
151337e8
NC		 4596 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4597 && relaxable_symbol (fragP->fr_symbol))
252b5132 4598 {
151337e8
NC		 4599 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4600 }
4601 else if (flag_short_refs)
4602 {
4603 /* Symbol is undefined and we want short ref. */
4604 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4605 }
4606 else
4607 {
151337e8
NC		 4608 /* Symbol is still undefined. Make it LONG. */
4609 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4610 }
4611 break;
151337e8 4612 }
252b5132 4613
151337e8 4614 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4615 {
151337e8
NC		 4616 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4617 && relaxable_symbol (fragP->fr_symbol))
252b5132 4618 {
151337e8 4619 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4620 }
4621 else
4622 {
151337e8
NC		 4623 /* Symbol is undefined and we don't have long branches. */
4624 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4625 }
4626 break;
151337e8 4627 }
252b5132 4628
151337e8 4629 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4630 case TAB (DBCCLBR, SZ_UNDEF):
4631 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4632 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4633 {
8ec6253e
NC		 4634 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4635 && relaxable_symbol (fragP->fr_symbol))
151337e8 4636 || flag_short_refs)
252b5132 4637 {
151337e8 4638 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4639 }
4640 else
4641 {
151337e8 4642 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4643 }
4644 break;
151337e8 4645 }
81d4177b 4646
252b5132
RH		 4647 case TAB (PCINDEX, SZ_UNDEF):
4648 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4649 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4650 {
4651 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4652 }
4653 else
4654 {
4655 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4656 }
4657 break;
4658
151337e8
NC		 4659 case TAB (ABSTOPCREL, SZ_UNDEF):
4660 {
4661 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4662 && relaxable_symbol (fragP->fr_symbol)))
4663 {
4664 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4665 }
4666 else
4667 {
4668 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4669 }
4670 break;
4671 }
4672
252b5132
RH		 4673 default:
4674 break;
4675 }
4676
151337e8 4677 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4678 switch (fragP->fr_subtype)
4679 {
151337e8
NC		 4680 case TAB (BRANCHBWL, BYTE):
4681 case TAB (BRABSJUNC, BYTE):
4682 case TAB (BRABSJCOND, BYTE):
4683 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4684 /* We can't do a short jump to the next instruction, so in that
4685 case we force word mode. At this point S_GET_VALUE should
4686 return the offset of the symbol within its frag. If the
4687 symbol is at the start of a frag, and it is the next frag
4688 with any data in it (usually this is just the next frag, but
4689 assembler listings may introduce empty frags), we must use
4690 word mode. */
4691 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4692 {
49309057 4693 fragS *stop;
252b5132
RH		 4694 fragS *l;
4695
49309057 4696 stop = symbol_get_frag (fragP->fr_symbol);
7099f9f9 4697
49309057 4698 for (l = fragP->fr_next; l != stop; l = l->fr_next)
252b5132 4699 {
7099f9f9
NC		 4700 /* Catch empty alignment frags whoes fr_offset field
4701 is an alignment requirement of 2 bytes. The check
4702 below will misinterpret this as evidence that real
4703 code exists between the symbol and the instruction
4704 and so will not convert the short jump into a word
4705 jump. */
4706 if (l->fr_fix == 0
4707 && l->fr_var == 1
4708 && (l->fr_type == rs_align || l->fr_type == rs_align_code))
4709 continue;
4710
4711 if (l->fr_fix + l->fr_var != 0)
4712 break;
252b5132 4713 }
7099f9f9
NC		 4714 if (l == stop)
4715 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4716 }
4717 break;
4718 default:
4719 break;
4720 }
5c65dbc1 4721 fragP->fr_var = md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4722 return fragP->fr_var + fragP->fr_fix - old_fix;
4723}
4724
4725#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4726/* the bit-field entries in the relocation_info struct plays hell
4727 with the byte-order problems of cross-assembly. So as a hack,
4728 I added this mach. dependent ri twiddler. Ugly, but it gets
4729 you there. -KWK */
4730/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4731 are symbolnum, most sig. byte first. Last byte is broken up with
4732 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4733 nibble as nuthin. (on Sun 3 at least) */
4734/* Translate the internal relocation information into target-specific
92774660 4735 format. */
252b5132
RH		 4736#ifdef comment
4737void
4738md_ri_to_chars (the_bytes, ri)
4739 char *the_bytes;
4740 struct reloc_info_generic *ri;
4741{
4742 /* this is easy */
4743 md_number_to_chars (the_bytes, ri->r_address, 4);
4744 /* now the fun stuff */
4745 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4746 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4747 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4748 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4749 ((ri->r_extern << 4) & 0x10));
4750}
4751
4752#endif /* comment */
4753
4754#ifndef BFD_ASSEMBLER
4755void
4756tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4757 char *where;
4758 fixS *fixP;
4759 relax_addressT segment_address_in_file;
4760{
4761 /*
4762 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4763 * Out: GNU LD relocation length code: 0, 1, or 2.
4764 */
4765
4766 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4767 long r_symbolnum;
4768
4769 know (fixP->fx_addsy != NULL);
4770
4771 md_number_to_chars (where,
4772 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4773 4);
4774
4775 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4776 ? S_GET_TYPE (fixP->fx_addsy)
4777 : fixP->fx_addsy->sy_number);
4778
4779 where[4] = (r_symbolnum >> 16) & 0x0ff;
4780 where[5] = (r_symbolnum >> 8) & 0x0ff;
4781 where[6] = r_symbolnum & 0x0ff;
4782 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4783 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4784}
4785#endif
4786
4787#endif /* OBJ_AOUT or OBJ_BOUT */
4788
4789#ifndef WORKING_DOT_WORD
4790CONST int md_short_jump_size = 4;
4791CONST int md_long_jump_size = 6;
4792
4793void
4794md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4795 char *ptr;
4796 addressT from_addr, to_addr;
36823076
AS		 4797 fragS *frag ATTRIBUTE_UNUSED;
4798 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4799{
4800 valueT offset;
4801
4802 offset = to_addr - (from_addr + 2);
4803
4804 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4805 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4806}
4807
4808void
4809md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4810 char *ptr;
4811 addressT from_addr, to_addr;
4812 fragS *frag;
4813 symbolS *to_symbol;
4814{
4815 valueT offset;
4816
4817 if (!HAVE_LONG_BRANCH(current_architecture))
4818 {
4819 offset = to_addr - S_GET_VALUE (to_symbol);
4820 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4821 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4822 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4823 0, NO_RELOC);
4824 }
4825 else
4826 {
4827 offset = to_addr - (from_addr + 2);
4828 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4829 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4830 }
4831}
4832
4833#endif
4834
4835/* Different values of OK tell what its OK to return. Things that
4836 aren't OK are an error (what a shock, no?)
4837
4838 0: Everything is OK
4839 10: Absolute 1:8 only
4840 20: Absolute 0:7 only
4841 30: absolute 0:15 only
4842 40: Absolute 0:31 only
4843 50: absolute 0:127 only
4844 55: absolute -64:63 only
4845 60: absolute -128:127 only
4846 70: absolute 0:4095 only
4847 80: No bignums
4848
4849 */
4850
4851static int
4852get_num (exp, ok)
4853 struct m68k_exp *exp;
4854 int ok;
4855{
4856 if (exp->exp.X_op == O_absent)
4857 {
4858 /* Do the same thing the VAX asm does */
4859 op (exp) = O_constant;
4860 adds (exp) = 0;
4861 subs (exp) = 0;
4862 offs (exp) = 0;
4863 if (ok == 10)
4864 {
4865 as_warn (_("expression out of range: defaulting to 1"));
4866 offs (exp) = 1;
4867 }
4868 }
4869 else if (exp->exp.X_op == O_constant)
4870 {
4871 switch (ok)
4872 {
4873 case 10:
4874 if (offs (exp) < 1 || offs (exp) > 8)
4875 {
4876 as_warn (_("expression out of range: defaulting to 1"));
4877 offs (exp) = 1;
4878 }
4879 break;
4880 case 20:
4881 if (offs (exp) < 0 || offs (exp) > 7)
4882 goto outrange;
4883 break;
4884 case 30:
4885 if (offs (exp) < 0 || offs (exp) > 15)
4886 goto outrange;
4887 break;
4888 case 40:
4889 if (offs (exp) < 0 || offs (exp) > 32)
4890 goto outrange;
4891 break;
4892 case 50:
4893 if (offs (exp) < 0 || offs (exp) > 127)
4894 goto outrange;
4895 break;
4896 case 55:
4897 if (offs (exp) < -64 || offs (exp) > 63)
4898 goto outrange;
4899 break;
4900 case 60:
4901 if (offs (exp) < -128 || offs (exp) > 127)
4902 goto outrange;
4903 break;
4904 case 70:
4905 if (offs (exp) < 0 || offs (exp) > 4095)
4906 {
4907 outrange:
4908 as_warn (_("expression out of range: defaulting to 0"));
4909 offs (exp) = 0;
4910 }
4911 break;
4912 default:
4913 break;
4914 }
4915 }
4916 else if (exp->exp.X_op == O_big)
4917 {
4918 if (offs (exp) <= 0 /* flonum */
4919 && (ok == 80 /* no bignums */
4920 || (ok > 10 /* small-int ranges including 0 ok */
4921 /* If we have a flonum zero, a zero integer should
4922 do as well (e.g., in moveq). */
4923 && generic_floating_point_number.exponent == 0
4924 && generic_floating_point_number.low[0] == 0)))
4925 {
4926 /* HACK! Turn it into a long */
4927 LITTLENUM_TYPE words[6];
4928
4929 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4930 op (exp) = O_constant;
4931 adds (exp) = 0;
4932 subs (exp) = 0;
4933 offs (exp) = words[1] | (words[0] << 16);
4934 }
4935 else if (ok != 0)
4936 {
4937 op (exp) = O_constant;
4938 adds (exp) = 0;
4939 subs (exp) = 0;
4940 offs (exp) = (ok == 10) ? 1 : 0;
4941 as_warn (_("Can't deal with expression; defaulting to %ld"),
4942 offs (exp));
4943 }
4944 }
4945 else
4946 {
4947 if (ok >= 10 && ok <= 70)
4948 {
4949 op (exp) = O_constant;
4950 adds (exp) = 0;
4951 subs (exp) = 0;
4952 offs (exp) = (ok == 10) ? 1 : 0;
4953 as_warn (_("Can't deal with expression; defaulting to %ld"),
4954 offs (exp));
4955 }
4956 }
4957
4958 if (exp->size != SIZE_UNSPEC)
4959 {
4960 switch (exp->size)
4961 {
4962 case SIZE_UNSPEC:
4963 case SIZE_LONG:
4964 break;
4965 case SIZE_BYTE:
4966 if (!isbyte (offs (exp)))
4967 as_warn (_("expression doesn't fit in BYTE"));
4968 break;
4969 case SIZE_WORD:
4970 if (!isword (offs (exp)))
4971 as_warn (_("expression doesn't fit in WORD"));
4972 break;
4973 }
4974 }
4975
4976 return offs (exp);
4977}
4978
4979/* These are the back-ends for the various machine dependent pseudo-ops. */
4980
4981static void
4982s_data1 (ignore)
36823076 4983 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4984{
4985 subseg_set (data_section, 1);
4986 demand_empty_rest_of_line ();
4987}
4988
4989static void
4990s_data2 (ignore)
36823076 4991 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4992{
4993 subseg_set (data_section, 2);
4994 demand_empty_rest_of_line ();
4995}
4996
4997static void
4998s_bss (ignore)
36823076 4999 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5000{
5001 /* We don't support putting frags in the BSS segment, we fake it
5002 by marking in_bss, then looking at s_skip for clues. */
5003
5004 subseg_set (bss_section, 0);
5005 demand_empty_rest_of_line ();
5006}
5007
5008static void
5009s_even (ignore)
36823076 5010 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5011{
5012 register int temp;
5013 register long temp_fill;
5014
5015 temp = 1; /* JF should be 2? */
5016 temp_fill = get_absolute_expression ();
92774660 5017 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5018 frag_align (temp, (int) temp_fill, 0);
5019 demand_empty_rest_of_line ();
5020 record_alignment (now_seg, temp);
5021}
5022
5023static void
5024s_proc (ignore)
36823076 5025 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5026{
5027 demand_empty_rest_of_line ();
5028}
5029\f
5030/* Pseudo-ops handled for MRI compatibility. */
5031
5032/* This function returns non-zero if the argument is a conditional
5033 pseudo-op. This is called when checking whether a pending
5034 alignment is needed. */
5035
5036int
5037m68k_conditional_pseudoop (pop)
5038 pseudo_typeS *pop;
5039{
5040 return (pop->poc_handler == s_mri_if
5041 || pop->poc_handler == s_mri_else);
5042}
5043
5044/* Handle an MRI style chip specification. */
5045
5046static void
5047mri_chip ()
5048{
5049 char *s;
5050 char c;
5051 int i;
5052
5053 s = input_line_pointer;
5054 /* We can't use get_symbol_end since the processor names are not proper
5055 symbols. */
5056 while (is_part_of_name (c = *input_line_pointer++))
5057 ;
5058 *--input_line_pointer = 0;
5059 for (i = 0; i < n_archs; i++)
5060 if (strcasecmp (s, archs[i].name) == 0)
5061 break;
5062 if (i >= n_archs)
5063 {
5064 as_bad (_("%s: unrecognized processor name"), s);
5065 *input_line_pointer = c;
5066 ignore_rest_of_line ();
5067 return;
5068 }
5069 *input_line_pointer = c;
5070
5071 if (*input_line_pointer == '/')
5072 current_architecture = 0;
5073 else
5074 current_architecture &= m68881 | m68851;
5075 current_architecture |= archs[i].arch;
5076
5077 while (*input_line_pointer == '/')
5078 {
5079 ++input_line_pointer;
5080 s = input_line_pointer;
5081 /* We can't use get_symbol_end since the processor names are not
5082 proper symbols. */
5083 while (is_part_of_name (c = *input_line_pointer++))
5084 ;
5085 *--input_line_pointer = 0;
5086 if (strcmp (s, "68881") == 0)
5087 current_architecture |= m68881;
5088 else if (strcmp (s, "68851") == 0)
5089 current_architecture |= m68851;
5090 *input_line_pointer = c;
5091 }
5092
5093 /* Update info about available control registers. */
5094 select_control_regs ();
5095}
5096
5097/* The MRI CHIP pseudo-op. */
5098
5099static void
5100s_chip (ignore)
36823076 5101 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5102{
5103 char *stop = NULL;
5104 char stopc;
5105
5106 if (flag_mri)
5107 stop = mri_comment_field (&stopc);
5108 mri_chip ();
5109 if (flag_mri)
5110 mri_comment_end (stop, stopc);
5111 demand_empty_rest_of_line ();
5112}
5113
5114/* The MRI FOPT pseudo-op. */
5115
5116static void
5117s_fopt (ignore)
36823076 5118 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5119{
5120 SKIP_WHITESPACE ();
5121
5122 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5123 {
5124 int temp;
5125
5126 input_line_pointer += 3;
5127 temp = get_absolute_expression ();
5128 if (temp < 0 || temp > 7)
5129 as_bad (_("bad coprocessor id"));
5130 else
5131 m68k_float_copnum = COP0 + temp;
5132 }
5133 else
5134 {
5135 as_bad (_("unrecognized fopt option"));
5136 ignore_rest_of_line ();
5137 return;
5138 }
5139
5140 demand_empty_rest_of_line ();
5141}
5142
5143/* The structure used to handle the MRI OPT pseudo-op. */
5144
5145struct opt_action
5146{
5147 /* The name of the option. */
5148 const char *name;
5149
5150 /* If this is not NULL, just call this function. The first argument
5151 is the ARG field of this structure, the second argument is
5152 whether the option was negated. */
5153 void (*pfn) PARAMS ((int arg, int on));
5154
5155 /* If this is not NULL, and the PFN field is NULL, set the variable
5156 this points to. Set it to the ARG field if the option was not
5157 negated, and the NOTARG field otherwise. */
5158 int *pvar;
5159
5160 /* The value to pass to PFN or to assign to *PVAR. */
5161 int arg;
5162
5163 /* The value to assign to *PVAR if the option is negated. If PFN is
5164 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5165 the option may not be negated. */
5166 int notarg;
5167};
5168
5169/* The table used to handle the MRI OPT pseudo-op. */
5170
5171static void skip_to_comma PARAMS ((int, int));
5172static void opt_nest PARAMS ((int, int));
5173static void opt_chip PARAMS ((int, int));
5174static void opt_list PARAMS ((int, int));
5175static void opt_list_symbols PARAMS ((int, int));
5176
5177static const struct opt_action opt_table[] =
5178{
5179 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5180
5181 /* We do relaxing, so there is little use for these options. */
5182 { "b", 0, 0, 0, 0 },
5183 { "brs", 0, 0, 0, 0 },
5184 { "brb", 0, 0, 0, 0 },
5185 { "brl", 0, 0, 0, 0 },
5186 { "brw", 0, 0, 0, 0 },
5187
5188 { "c", 0, 0, 0, 0 },
5189 { "cex", 0, 0, 0, 0 },
5190 { "case", 0, &symbols_case_sensitive, 1, 0 },
5191 { "cl", 0, 0, 0, 0 },
5192 { "cre", 0, 0, 0, 0 },
5193 { "d", 0, &flag_keep_locals, 1, 0 },
5194 { "e", 0, 0, 0, 0 },
5195 { "f", 0, &flag_short_refs, 1, 0 },
5196 { "frs", 0, &flag_short_refs, 1, 0 },
5197 { "frl", 0, &flag_short_refs, 0, 1 },
5198 { "g", 0, 0, 0, 0 },
5199 { "i", 0, 0, 0, 0 },
5200 { "m", 0, 0, 0, 0 },
5201 { "mex", 0, 0, 0, 0 },
5202 { "mc", 0, 0, 0, 0 },
5203 { "md", 0, 0, 0, 0 },
5204 { "nest", opt_nest, 0, 0, 0 },
5205 { "next", skip_to_comma, 0, 0, 0 },
5206 { "o", 0, 0, 0, 0 },
5207 { "old", 0, 0, 0, 0 },
5208 { "op", skip_to_comma, 0, 0, 0 },
5209 { "pco", 0, 0, 0, 0 },
5210 { "p", opt_chip, 0, 0, 0 },
5211 { "pcr", 0, 0, 0, 0 },
5212 { "pcs", 0, 0, 0, 0 },
5213 { "r", 0, 0, 0, 0 },
5214 { "quick", 0, &m68k_quick, 1, 0 },
5215 { "rel32", 0, &m68k_rel32, 1, 0 },
5216 { "s", opt_list, 0, 0, 0 },
5217 { "t", opt_list_symbols, 0, 0, 0 },
5218 { "w", 0, &flag_no_warnings, 0, 1 },
5219 { "x", 0, 0, 0, 0 }
5220};
5221
8fce3f5e 5222#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5223
5224/* The MRI OPT pseudo-op. */
5225
5226static void
5227s_opt (ignore)
36823076 5228 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5229{
5230 do
5231 {
5232 int t;
5233 char *s;
5234 char c;
5235 int i;
5236 const struct opt_action *o;
5237
5238 SKIP_WHITESPACE ();
5239
5240 t = 1;
5241 if (*input_line_pointer == '-')
5242 {
5243 ++input_line_pointer;
5244 t = 0;
5245 }
5246 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5247 {
5248 input_line_pointer += 2;
5249 t = 0;
5250 }
5251
5252 s = input_line_pointer;
5253 c = get_symbol_end ();
5254
5255 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5256 {
5257 if (strcasecmp (s, o->name) == 0)
5258 {
5259 if (o->pfn)
5260 {
5261 /* Restore input_line_pointer now in case the option
5262 takes arguments. */
5263 *input_line_pointer = c;
5264 (*o->pfn) (o->arg, t);
5265 }
5266 else if (o->pvar != NULL)
5267 {
5268 if (! t && o->arg == o->notarg)
5269 as_bad (_("option `%s' may not be negated"), s);
5270 *input_line_pointer = c;
5271 *o->pvar = t ? o->arg : o->notarg;
5272 }
5273 else
5274 *input_line_pointer = c;
5275 break;
5276 }
5277 }
5278 if (i >= OPTCOUNT)
5279 {
5280 as_bad (_("option `%s' not recognized"), s);
5281 *input_line_pointer = c;
5282 }
5283 }
5284 while (*input_line_pointer++ == ',');
5285
5286 /* Move back to terminating character. */
5287 --input_line_pointer;
5288 demand_empty_rest_of_line ();
5289}
5290
5291/* Skip ahead to a comma. This is used for OPT options which we do
5292 not suppor tand which take arguments. */
5293
5294static void
5295skip_to_comma (arg, on)
36823076
AS		 5296 int arg ATTRIBUTE_UNUSED;
5297 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5298{
5299 while (*input_line_pointer != ','
5300 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5301 ++input_line_pointer;
5302}
5303
5304/* Handle the OPT NEST=depth option. */
5305
5306static void
5307opt_nest (arg, on)
36823076
AS		 5308 int arg ATTRIBUTE_UNUSED;
5309 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5310{
5311 if (*input_line_pointer != '=')
5312 {
5313 as_bad (_("bad format of OPT NEST=depth"));
5314 return;
5315 }
5316
5317 ++input_line_pointer;
5318 max_macro_nest = get_absolute_expression ();
5319}
5320
5321/* Handle the OPT P=chip option. */
5322
5323static void
5324opt_chip (arg, on)
36823076
AS		 5325 int arg ATTRIBUTE_UNUSED;
5326 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5327{
5328 if (*input_line_pointer != '=')
5329 {
5330 /* This is just OPT P, which we do not support. */
5331 return;
5332 }
5333
5334 ++input_line_pointer;
5335 mri_chip ();
5336}
5337
5338/* Handle the OPT S option. */
5339
5340static void
5341opt_list (arg, on)
36823076 5342 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5343 int on;
5344{
5345 listing_list (on);
5346}
5347
5348/* Handle the OPT T option. */
5349
5350static void
5351opt_list_symbols (arg, on)
36823076 5352 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5353 int on;
5354{
5355 if (on)
5356 listing |= LISTING_SYMBOLS;
5357 else
5358 listing &=~ LISTING_SYMBOLS;
5359}
5360
5361/* Handle the MRI REG pseudo-op. */
5362
5363static void
5364s_reg (ignore)
36823076 5365 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5366{
5367 char *s;
5368 int c;
5369 struct m68k_op rop;
5370 int mask;
5371 char *stop = NULL;
5372 char stopc;
5373
5374 if (line_label == NULL)
5375 {
5376 as_bad (_("missing label"));
5377 ignore_rest_of_line ();
5378 return;
5379 }
5380
5381 if (flag_mri)
5382 stop = mri_comment_field (&stopc);
5383
5384 SKIP_WHITESPACE ();
5385
5386 s = input_line_pointer;
5387 while (isalnum ((unsigned char) *input_line_pointer)
5388#ifdef REGISTER_PREFIX
5389 || *input_line_pointer == REGISTER_PREFIX
5390#endif
5391 || *input_line_pointer == '/'
5392 || *input_line_pointer == '-')
5393 ++input_line_pointer;
5394 c = *input_line_pointer;
5395 *input_line_pointer = '\0';
5396
5397 if (m68k_ip_op (s, &rop) != 0)
5398 {
5399 if (rop.error == NULL)
5400 as_bad (_("bad register list"));
5401 else
5402 as_bad (_("bad register list: %s"), rop.error);
5403 *input_line_pointer = c;
5404 ignore_rest_of_line ();
5405 return;
5406 }
5407
5408 *input_line_pointer = c;
5409
5410 if (rop.mode == REGLST)
5411 mask = rop.mask;
5412 else if (rop.mode == DREG)
5413 mask = 1 << (rop.reg - DATA0);
5414 else if (rop.mode == AREG)
5415 mask = 1 << (rop.reg - ADDR0 + 8);
5416 else if (rop.mode == FPREG)
5417 mask = 1 << (rop.reg - FP0 + 16);
5418 else if (rop.mode == CONTROL
5419 && rop.reg == FPI)
5420 mask = 1 << 24;
5421 else if (rop.mode == CONTROL
5422 && rop.reg == FPS)
5423 mask = 1 << 25;
5424 else if (rop.mode == CONTROL
5425 && rop.reg == FPC)
5426 mask = 1 << 26;
5427 else
5428 {
5429 as_bad (_("bad register list"));
5430 ignore_rest_of_line ();
5431 return;
5432 }
5433
5434 S_SET_SEGMENT (line_label, reg_section);
5435 S_SET_VALUE (line_label, ~mask);
49309057 5436 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5437
5438 if (flag_mri)
5439 mri_comment_end (stop, stopc);
5440
5441 demand_empty_rest_of_line ();
5442}
5443
5444/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5445
5446struct save_opts
5447{
5448 struct save_opts *next;
5449 int abspcadd;
5450 int symbols_case_sensitive;
5451 int keep_locals;
5452 int short_refs;
5453 int architecture;
5454 int quick;
5455 int rel32;
5456 int listing;
5457 int no_warnings;
5458 /* FIXME: We don't save OPT S. */
5459};
5460
5461/* This variable holds the stack of saved options. */
5462
5463static struct save_opts *save_stack;
5464
5465/* The MRI SAVE pseudo-op. */
5466
5467static void
5468s_save (ignore)
36823076 5469 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5470{
5471 struct save_opts *s;
5472
5473 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5474 s->abspcadd = m68k_abspcadd;
5475 s->symbols_case_sensitive = symbols_case_sensitive;
5476 s->keep_locals = flag_keep_locals;
5477 s->short_refs = flag_short_refs;
5478 s->architecture = current_architecture;
5479 s->quick = m68k_quick;
5480 s->rel32 = m68k_rel32;
5481 s->listing = listing;
5482 s->no_warnings = flag_no_warnings;
5483
5484 s->next = save_stack;
5485 save_stack = s;
5486
5487 demand_empty_rest_of_line ();
5488}
5489
5490/* The MRI RESTORE pseudo-op. */
5491
5492static void
5493s_restore (ignore)
36823076 5494 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5495{
5496 struct save_opts *s;
5497
5498 if (save_stack == NULL)
5499 {
5500 as_bad (_("restore without save"));
5501 ignore_rest_of_line ();
5502 return;
5503 }
5504
5505 s = save_stack;
5506 save_stack = s->next;
5507
5508 m68k_abspcadd = s->abspcadd;
5509 symbols_case_sensitive = s->symbols_case_sensitive;
5510 flag_keep_locals = s->keep_locals;
5511 flag_short_refs = s->short_refs;
5512 current_architecture = s->architecture;
5513 m68k_quick = s->quick;
5514 m68k_rel32 = s->rel32;
5515 listing = s->listing;
5516 flag_no_warnings = s->no_warnings;
5517
5518 free (s);
5519
5520 demand_empty_rest_of_line ();
5521}
5522
5523/* Types of MRI structured control directives. */
5524
5525enum mri_control_type
5526{
5527 mri_for,
5528 mri_if,
5529 mri_repeat,
5530 mri_while
5531};
5532
5533/* This structure is used to stack the MRI structured control
5534 directives. */
5535
5536struct mri_control_info
5537{
5538 /* The directive within which this one is enclosed. */
5539 struct mri_control_info *outer;
5540
5541 /* The type of directive. */
5542 enum mri_control_type type;
5543
5544 /* Whether an ELSE has been in an IF. */
5545 int else_seen;
5546
5547 /* The add or sub statement at the end of a FOR. */
5548 char *incr;
5549
5550 /* The label of the top of a FOR or REPEAT loop. */
5551 char *top;
5552
5553 /* The label to jump to for the next iteration, or the else
5554 expression of a conditional. */
5555 char *next;
5556
5557 /* The label to jump to to break out of the loop, or the label past
5558 the end of a conditional. */
5559 char *bottom;
5560};
5561
5562/* The stack of MRI structured control directives. */
5563
5564static struct mri_control_info *mri_control_stack;
5565
5566/* The current MRI structured control directive index number, used to
5567 generate label names. */
5568
5569static int mri_control_index;
5570
5571/* Some function prototypes. */
5572
5573static void mri_assemble PARAMS ((char *));
5574static char *mri_control_label PARAMS ((void));
5575static struct mri_control_info *push_mri_control
5576 PARAMS ((enum mri_control_type));
5577static void pop_mri_control PARAMS ((void));
5578static int parse_mri_condition PARAMS ((int *));
5579static int parse_mri_control_operand
5580 PARAMS ((int *, char **, char **, char **, char **));
5581static int swap_mri_condition PARAMS ((int));
5582static int reverse_mri_condition PARAMS ((int));
5583static void build_mri_control_operand
5584 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5585 const char *, int));
5586static void parse_mri_control_expression
5587 PARAMS ((char *, int, const char *, const char *, int));
5588
5589/* Assemble an instruction for an MRI structured control directive. */
5590
5591static void
5592mri_assemble (str)
5593 char *str;
5594{
5595 char *s;
5596
5597 /* md_assemble expects the opcode to be in lower case. */
5598 for (s = str; *s != ' ' && *s != '\0'; s++)
5599 {
5600 if (isupper ((unsigned char) *s))
5601 *s = tolower ((unsigned char) *s);
5602 }
5603
5604 md_assemble (str);
5605}
5606
5607/* Generate a new MRI label structured control directive label name. */
5608
5609static char *
5610mri_control_label ()
5611{
5612 char *n;
5613
5614 n = (char *) xmalloc (20);
5615 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5616 ++mri_control_index;
5617 return n;
5618}
5619
5620/* Create a new MRI structured control directive. */
5621
5622static struct mri_control_info *
5623push_mri_control (type)
5624 enum mri_control_type type;
5625{
5626 struct mri_control_info *n;
5627
5628 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5629
5630 n->type = type;
5631 n->else_seen = 0;
5632 if (type == mri_if || type == mri_while)
5633 n->top = NULL;
5634 else
5635 n->top = mri_control_label ();
5636 n->next = mri_control_label ();
5637 n->bottom = mri_control_label ();
5638
5639 n->outer = mri_control_stack;
5640 mri_control_stack = n;
5641
5642 return n;
5643}
5644
5645/* Pop off the stack of MRI structured control directives. */
5646
5647static void
5648pop_mri_control ()
5649{
5650 struct mri_control_info *n;
5651
5652 n = mri_control_stack;
5653 mri_control_stack = n->outer;
5654 if (n->top != NULL)
5655 free (n->top);
5656 free (n->next);
5657 free (n->bottom);
5658 free (n);
5659}
5660
5661/* Recognize a condition code in an MRI structured control expression. */
5662
5663static int
5664parse_mri_condition (pcc)
5665 int *pcc;
5666{
5667 char c1, c2;
5668
5669 know (*input_line_pointer == '<');
5670
5671 ++input_line_pointer;
5672 c1 = *input_line_pointer++;
5673 c2 = *input_line_pointer++;
5674
5675 if (*input_line_pointer != '>')
5676 {
5677 as_bad (_("syntax error in structured control directive"));
5678 return 0;
5679 }
5680
5681 ++input_line_pointer;
5682 SKIP_WHITESPACE ();
5683
5684 if (isupper (c1))
5685 c1 = tolower (c1);
5686 if (isupper (c2))
5687 c2 = tolower (c2);
5688
5689 *pcc = (c1 << 8) | c2;
5690
5691 return 1;
5692}
5693
5694/* Parse a single operand in an MRI structured control expression. */
5695
5696static int
5697parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5698 int *pcc;
5699 char **leftstart;
5700 char **leftstop;
5701 char **rightstart;
5702 char **rightstop;
5703{
5704 char *s;
5705
5706 SKIP_WHITESPACE ();
5707
5708 *pcc = -1;
5709 *leftstart = NULL;
5710 *leftstop = NULL;
5711 *rightstart = NULL;
5712 *rightstop = NULL;
5713
5714 if (*input_line_pointer == '<')
5715 {
5716 /* It's just a condition code. */
5717 return parse_mri_condition (pcc);
5718 }
5719
5720 /* Look ahead for the condition code. */
5721 for (s = input_line_pointer; *s != '\0'; ++s)
5722 {
5723 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5724 break;
5725 }
5726 if (*s == '\0')
5727 {
5728 as_bad (_("missing condition code in structured control directive"));
5729 return 0;
5730 }
5731
5732 *leftstart = input_line_pointer;
5733 *leftstop = s;
5734 if (*leftstop > *leftstart
5735 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5736 --*leftstop;
5737
5738 input_line_pointer = s;
5739 if (! parse_mri_condition (pcc))
5740 return 0;
5741
5742 /* Look ahead for AND or OR or end of line. */
5743 for (s = input_line_pointer; *s != '\0'; ++s)
5744 {
e1f44d10
NC		 5745 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5746 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5747 ^^^ ^^ */
5748 if ( ( s == input_line_pointer
5749 || *(s-1) == ' '
5750 || *(s-1) == '\t')
5751 && ( ( strncasecmp (s, "AND", 3) == 0
5752 && (s[3] == '.' || ! is_part_of_name (s[3])))
5753 || ( strncasecmp (s, "OR", 2) == 0
5754 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5755 break;
252b5132
RH		 5756 }
5757
5758 *rightstart = input_line_pointer;
5759 *rightstop = s;
5760 if (*rightstop > *rightstart
5761 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5762 --*rightstop;
5763
5764 input_line_pointer = s;
5765
5766 return 1;
5767}
5768
5769#define MCC(b1, b2) (((b1) << 8) | (b2))
5770
5771/* Swap the sense of a condition. This changes the condition so that
5772 it generates the same result when the operands are swapped. */
5773
5774static int
5775swap_mri_condition (cc)
5776 int cc;
5777{
5778 switch (cc)
5779 {
5780 case MCC ('h', 'i'): return MCC ('c', 's');
5781 case MCC ('l', 's'): return MCC ('c', 'c');
e1f44d10
NC		 5782 /* <HS> is an alias for <CC> */
5783 case MCC ('h', 's'):
252b5132 5784 case MCC ('c', 'c'): return MCC ('l', 's');
e1f44d10
NC		 5785 /* <LO> is an alias for <CS> */
5786 case MCC ('l', 'o'):
252b5132
RH		 5787 case MCC ('c', 's'): return MCC ('h', 'i');
5788 case MCC ('p', 'l'): return MCC ('m', 'i');
5789 case MCC ('m', 'i'): return MCC ('p', 'l');
5790 case MCC ('g', 'e'): return MCC ('l', 'e');
5791 case MCC ('l', 't'): return MCC ('g', 't');
5792 case MCC ('g', 't'): return MCC ('l', 't');
5793 case MCC ('l', 'e'): return MCC ('g', 'e');
e1f44d10
NC		 5794 /* issue a warning for conditions we can not swap */
5795 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5796 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5797 case MCC ('v', 'c'):
5798 case MCC ('v', 's'):
5799 default :
5800 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5801 (char) (cc >> 8), (char) (cc));
5802 break;
252b5132
RH		 5803 }
5804 return cc;
5805}
5806
5807/* Reverse the sense of a condition. */
5808
5809static int
5810reverse_mri_condition (cc)
5811 int cc;
5812{
5813 switch (cc)
5814 {
5815 case MCC ('h', 'i'): return MCC ('l', 's');
5816 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5817 /* <HS> is an alias for <CC> */
5818 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 5819 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 5820 /* <LO> is an alias for <CS> */
5821 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 5822 case MCC ('c', 's'): return MCC ('c', 'c');
5823 case MCC ('n', 'e'): return MCC ('e', 'q');
5824 case MCC ('e', 'q'): return MCC ('n', 'e');
5825 case MCC ('v', 'c'): return MCC ('v', 's');
5826 case MCC ('v', 's'): return MCC ('v', 'c');
5827 case MCC ('p', 'l'): return MCC ('m', 'i');
5828 case MCC ('m', 'i'): return MCC ('p', 'l');
5829 case MCC ('g', 'e'): return MCC ('l', 't');
5830 case MCC ('l', 't'): return MCC ('g', 'e');
5831 case MCC ('g', 't'): return MCC ('l', 'e');
5832 case MCC ('l', 'e'): return MCC ('g', 't');
5833 }
5834 return cc;
5835}
5836
5837/* Build an MRI structured control expression. This generates test
5838 and branch instructions. It goes to TRUELAB if the condition is
5839 true, and to FALSELAB if the condition is false. Exactly one of
5840 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5841 is the size qualifier for the expression. EXTENT is the size to
5842 use for the branch. */
5843
5844static void
5845build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5846 rightstop, truelab, falselab, extent)
5847 int qual;
5848 int cc;
5849 char *leftstart;
5850 char *leftstop;
5851 char *rightstart;
5852 char *rightstop;
5853 const char *truelab;
5854 const char *falselab;
5855 int extent;
5856{
5857 char *buf;
5858 char *s;
5859
5860 if (leftstart != NULL)
5861 {
5862 struct m68k_op leftop, rightop;
5863 char c;
5864
5865 /* Swap the compare operands, if necessary, to produce a legal
5866 m68k compare instruction. Comparing a register operand with
5867 a non-register operand requires the register to be on the
5868 right (cmp, cmpa). Comparing an immediate value with
5869 anything requires the immediate value to be on the left
5870 (cmpi). */
5871
5872 c = *leftstop;
5873 *leftstop = '\0';
5874 (void) m68k_ip_op (leftstart, &leftop);
5875 *leftstop = c;
5876
5877 c = *rightstop;
5878 *rightstop = '\0';
5879 (void) m68k_ip_op (rightstart, &rightop);
5880 *rightstop = c;
5881
5882 if (rightop.mode == IMMED
5883 || ((leftop.mode == DREG || leftop.mode == AREG)
5884 && (rightop.mode != DREG && rightop.mode != AREG)))
5885 {
5886 char *temp;
5887
e1f44d10
NC		 5888 /* Correct conditional handling:
5889 if #1 <lt> d0 then ;means if (1 < d0)
5890 ...
5891 endi
5892
5893 should assemble to:
5894
5895 cmp #1,d0 if we do *not* swap the operands
5896 bgt true we need the swapped condition!
5897 ble false
5898 true:
5899 ...
5900 false:
5901 */
252b5132
RH		 5902 temp = leftstart;
5903 leftstart = rightstart;
5904 rightstart = temp;
5905 temp = leftstop;
5906 leftstop = rightstop;
5907 rightstop = temp;
e1f44d10
NC		 5908 } else {
5909 cc = swap_mri_condition (cc);
252b5132
RH		 5910 }
5911 }
5912
5913 if (truelab == NULL)
5914 {
5915 cc = reverse_mri_condition (cc);
5916 truelab = falselab;
5917 }
92774660 5918
252b5132
RH		 5919 if (leftstart != NULL)
5920 {
5921 buf = (char *) xmalloc (20
5922 + (leftstop - leftstart)
5923 + (rightstop - rightstart));
5924 s = buf;
5925 *s++ = 'c';
5926 *s++ = 'm';
5927 *s++ = 'p';
5928 if (qual != '\0')
e1f44d10 5929 *s++ = tolower(qual);
252b5132
RH		 5930 *s++ = ' ';
5931 memcpy (s, leftstart, leftstop - leftstart);
5932 s += leftstop - leftstart;
5933 *s++ = ',';
5934 memcpy (s, rightstart, rightstop - rightstart);
5935 s += rightstop - rightstart;
5936 *s = '\0';
5937 mri_assemble (buf);
5938 free (buf);
5939 }
92774660 5940
252b5132
RH		 5941 buf = (char *) xmalloc (20 + strlen (truelab));
5942 s = buf;
5943 *s++ = 'b';
5944 *s++ = cc >> 8;
5945 *s++ = cc & 0xff;
5946 if (extent != '\0')
e1f44d10 5947 *s++ = tolower(extent);
252b5132
RH		 5948 *s++ = ' ';
5949 strcpy (s, truelab);
5950 mri_assemble (buf);
5951 free (buf);
5952}
5953
5954/* Parse an MRI structured control expression. This generates test
5955 and branch instructions. STOP is where the expression ends. It
5956 goes to TRUELAB if the condition is true, and to FALSELAB if the
5957 condition is false. Exactly one of TRUELAB and FALSELAB will be
5958 NULL, meaning to fall through. QUAL is the size qualifier for the
5959 expression. EXTENT is the size to use for the branch. */
5960
5961static void
5962parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5963 char *stop;
5964 int qual;
5965 const char *truelab;
5966 const char *falselab;
5967 int extent;
5968{
5969 int c;
5970 int cc;
5971 char *leftstart;
5972 char *leftstop;
5973 char *rightstart;
5974 char *rightstop;
5975
5976 c = *stop;
5977 *stop = '\0';
5978
5979 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5980 &rightstart, &rightstop))
5981 {
5982 *stop = c;
5983 return;
5984 }
5985
5986 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5987 {
5988 const char *flab;
5989
5990 if (falselab != NULL)
5991 flab = falselab;
5992 else
5993 flab = mri_control_label ();
5994
5995 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5996 rightstop, (const char *) NULL, flab, extent);
5997
5998 input_line_pointer += 3;
5999 if (*input_line_pointer != '.'
6000 || input_line_pointer[1] == '\0')
6001 qual = '\0';
6002 else
6003 {
6004 qual = input_line_pointer[1];
6005 input_line_pointer += 2;
6006 }
6007
6008 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6009 &rightstart, &rightstop))
6010 {
6011 *stop = c;
6012 return;
6013 }
6014
6015 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6016 rightstop, truelab, falselab, extent);
6017
6018 if (falselab == NULL)
6019 colon (flab);
6020 }
6021 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6022 {
6023 const char *tlab;
6024
6025 if (truelab != NULL)
6026 tlab = truelab;
6027 else
6028 tlab = mri_control_label ();
6029
6030 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6031 rightstop, tlab, (const char *) NULL, extent);
6032
6033 input_line_pointer += 2;
6034 if (*input_line_pointer != '.'
6035 || input_line_pointer[1] == '\0')
6036 qual = '\0';
6037 else
6038 {
6039 qual = input_line_pointer[1];
6040 input_line_pointer += 2;
6041 }
6042
6043 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6044 &rightstart, &rightstop))
6045 {
6046 *stop = c;
6047 return;
6048 }
6049
6050 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6051 rightstop, truelab, falselab, extent);
6052
6053 if (truelab == NULL)
6054 colon (tlab);
6055 }
6056 else
6057 {
6058 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6059 rightstop, truelab, falselab, extent);
6060 }
6061
6062 *stop = c;
6063 if (input_line_pointer != stop)
6064 as_bad (_("syntax error in structured control directive"));
6065}
6066
6067/* Handle the MRI IF pseudo-op. This may be a structured control
6068 directive, or it may be a regular assembler conditional, depending
6069 on its operands. */
6070
6071static void
6072s_mri_if (qual)
6073 int qual;
6074{
6075 char *s;
6076 int c;
6077 struct mri_control_info *n;
6078
6079 /* A structured control directive must end with THEN with an
6080 optional qualifier. */
6081 s = input_line_pointer;
e1f44d10
NC		 6082 /* We only accept '*' as introduction of comments if preceded by white space
6083 or at first column of a line (I think this can't actually happen here?)
6084 This is important when assembling:
6085 if d0 <ne> 12(a0,d0*2) then
6086 if d0 <ne> #CONST*20 then */
6087 while ( ! ( is_end_of_line[(unsigned char) *s]
6088 || ( flag_mri
6089 && *s == '*'
6090 && ( s == input_line_pointer
6091 || *(s-1) == ' '
6092 || *(s-1) == '\t'))))
252b5132
RH		 6093 ++s;
6094 --s;
6095 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6096 --s;
6097
6098 if (s - input_line_pointer > 1
6099 && s[-1] == '.')
6100 s -= 2;
6101
6102 if (s - input_line_pointer < 3
6103 || strncasecmp (s - 3, "THEN", 4) != 0)
6104 {
6105 if (qual != '\0')
6106 {
6107 as_bad (_("missing then"));
6108 ignore_rest_of_line ();
6109 return;
6110 }
6111
6112 /* It's a conditional. */
6113 s_if (O_ne);
6114 return;
6115 }
6116
6117 /* Since this might be a conditional if, this pseudo-op will be
6118 called even if we are supported to be ignoring input. Double
6119 check now. Clobber *input_line_pointer so that ignore_input
6120 thinks that this is not a special pseudo-op. */
6121 c = *input_line_pointer;
6122 *input_line_pointer = 0;
6123 if (ignore_input ())
6124 {
6125 *input_line_pointer = c;
6126 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6127 ++input_line_pointer;
6128 demand_empty_rest_of_line ();
6129 return;
6130 }
6131 *input_line_pointer = c;
6132
6133 n = push_mri_control (mri_if);
6134
6135 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6136 n->next, s[1] == '.' ? s[2] : '\0');
6137
6138 if (s[1] == '.')
6139 input_line_pointer = s + 3;
6140 else
6141 input_line_pointer = s + 1;
6142
6143 if (flag_mri)
6144 {
6145 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6146 ++input_line_pointer;
6147 }
6148
6149 demand_empty_rest_of_line ();
6150}
6151
6152/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6153 structured IF, associate the ELSE with the IF. Otherwise, assume
6154 it is a conditional else. */
6155
6156static void
6157s_mri_else (qual)
6158 int qual;
6159{
6160 int c;
6161 char *buf;
6162 char q[2];
6163
6164 if (qual == '\0'
6165 && (mri_control_stack == NULL
6166 || mri_control_stack->type != mri_if
6167 || mri_control_stack->else_seen))
6168 {
6169 s_else (0);
6170 return;
6171 }
6172
6173 c = *input_line_pointer;
6174 *input_line_pointer = 0;
6175 if (ignore_input ())
6176 {
6177 *input_line_pointer = c;
6178 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6179 ++input_line_pointer;
6180 demand_empty_rest_of_line ();
6181 return;
6182 }
6183 *input_line_pointer = c;
6184
6185 if (mri_control_stack == NULL
6186 || mri_control_stack->type != mri_if
6187 || mri_control_stack->else_seen)
6188 {
6189 as_bad (_("else without matching if"));
6190 ignore_rest_of_line ();
6191 return;
6192 }
6193
6194 mri_control_stack->else_seen = 1;
6195
6196 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
e1f44d10 6197 q[0] = tolower(qual);
252b5132
RH		 6198 q[1] = '\0';
6199 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6200 mri_assemble (buf);
6201 free (buf);
6202
6203 colon (mri_control_stack->next);
6204
6205 if (flag_mri)
6206 {
6207 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6208 ++input_line_pointer;
6209 }
6210
6211 demand_empty_rest_of_line ();
6212}
6213
6214/* Handle the MRI ENDI pseudo-op. */
6215
6216static void
6217s_mri_endi (ignore)
36823076 6218 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6219{
6220 if (mri_control_stack == NULL
6221 || mri_control_stack->type != mri_if)
6222 {
6223 as_bad (_("endi without matching if"));
6224 ignore_rest_of_line ();
6225 return;
6226 }
6227
6228 /* ignore_input will not return true for ENDI, so we don't need to
6229 worry about checking it again here. */
6230
6231 if (! mri_control_stack->else_seen)
6232 colon (mri_control_stack->next);
6233 colon (mri_control_stack->bottom);
6234
6235 pop_mri_control ();
6236
6237 if (flag_mri)
6238 {
6239 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6240 ++input_line_pointer;
6241 }
6242
6243 demand_empty_rest_of_line ();
6244}
6245
6246/* Handle the MRI BREAK pseudo-op. */
6247
6248static void
6249s_mri_break (extent)
6250 int extent;
6251{
6252 struct mri_control_info *n;
6253 char *buf;
6254 char ex[2];
6255
6256 n = mri_control_stack;
6257 while (n != NULL
6258 && n->type != mri_for
6259 && n->type != mri_repeat
6260 && n->type != mri_while)
6261 n = n->outer;
6262 if (n == NULL)
6263 {
6264 as_bad (_("break outside of structured loop"));
6265 ignore_rest_of_line ();
6266 return;
6267 }
6268
6269 buf = (char *) xmalloc (20 + strlen (n->bottom));
e1f44d10 6270 ex[0] = tolower(extent);
252b5132
RH		 6271 ex[1] = '\0';
6272 sprintf (buf, "bra%s %s", ex, n->bottom);
6273 mri_assemble (buf);
6274 free (buf);
6275
6276 if (flag_mri)
6277 {
6278 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6279 ++input_line_pointer;
6280 }
6281
6282 demand_empty_rest_of_line ();
6283}
6284
6285/* Handle the MRI NEXT pseudo-op. */
6286
6287static void
6288s_mri_next (extent)
6289 int extent;
6290{
6291 struct mri_control_info *n;
6292 char *buf;
6293 char ex[2];
6294
6295 n = mri_control_stack;
6296 while (n != NULL
6297 && n->type != mri_for
6298 && n->type != mri_repeat
6299 && n->type != mri_while)
6300 n = n->outer;
6301 if (n == NULL)
6302 {
6303 as_bad (_("next outside of structured loop"));
6304 ignore_rest_of_line ();
6305 return;
6306 }
6307
6308 buf = (char *) xmalloc (20 + strlen (n->next));
e1f44d10 6309 ex[0] = tolower(extent);
252b5132
RH		 6310 ex[1] = '\0';
6311 sprintf (buf, "bra%s %s", ex, n->next);
6312 mri_assemble (buf);
6313 free (buf);
6314
6315 if (flag_mri)
6316 {
6317 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6318 ++input_line_pointer;
6319 }
6320
6321 demand_empty_rest_of_line ();
6322}
6323
6324/* Handle the MRI FOR pseudo-op. */
6325
6326static void
6327s_mri_for (qual)
6328 int qual;
6329{
6330 const char *varstart, *varstop;
6331 const char *initstart, *initstop;
6332 const char *endstart, *endstop;
6333 const char *bystart, *bystop;
6334 int up;
6335 int by;
6336 int extent;
6337 struct mri_control_info *n;
6338 char *buf;
6339 char *s;
6340 char ex[2];
6341
6342 /* The syntax is
6343 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6344 */
6345
6346 SKIP_WHITESPACE ();
6347 varstart = input_line_pointer;
6348
6349 /* Look for the '='. */
6350 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6351 && *input_line_pointer != '=')
6352 ++input_line_pointer;
6353 if (*input_line_pointer != '=')
6354 {
6355 as_bad (_("missing ="));
6356 ignore_rest_of_line ();
6357 return;
6358 }
6359
6360 varstop = input_line_pointer;
6361 if (varstop > varstart
6362 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6363 --varstop;
6364
6365 ++input_line_pointer;
6366
6367 initstart = input_line_pointer;
6368
6369 /* Look for TO or DOWNTO. */
6370 up = 1;
6371 initstop = NULL;
6372 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6373 {
6374 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6375 && ! is_part_of_name (input_line_pointer[2]))
6376 {
6377 initstop = input_line_pointer;
6378 input_line_pointer += 2;
6379 break;
6380 }
6381 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6382 && ! is_part_of_name (input_line_pointer[6]))
6383 {
6384 initstop = input_line_pointer;
6385 up = 0;
6386 input_line_pointer += 6;
6387 break;
6388 }
6389 ++input_line_pointer;
6390 }
6391 if (initstop == NULL)
6392 {
6393 as_bad (_("missing to or downto"));
6394 ignore_rest_of_line ();
6395 return;
6396 }
6397 if (initstop > initstart
6398 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6399 --initstop;
6400
6401 SKIP_WHITESPACE ();
6402 endstart = input_line_pointer;
6403
6404 /* Look for BY or DO. */
6405 by = 0;
6406 endstop = NULL;
6407 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6408 {
6409 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6410 && ! is_part_of_name (input_line_pointer[2]))
6411 {
6412 endstop = input_line_pointer;
6413 by = 1;
6414 input_line_pointer += 2;
6415 break;
6416 }
6417 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6418 && (input_line_pointer[2] == '.'
6419 || ! is_part_of_name (input_line_pointer[2])))
6420 {
6421 endstop = input_line_pointer;
6422 input_line_pointer += 2;
6423 break;
6424 }
6425 ++input_line_pointer;
6426 }
6427 if (endstop == NULL)
6428 {
6429 as_bad (_("missing do"));
6430 ignore_rest_of_line ();
6431 return;
6432 }
6433 if (endstop > endstart
6434 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6435 --endstop;
6436
6437 if (! by)
6438 {
6439 bystart = "#1";
6440 bystop = bystart + 2;
6441 }
6442 else
6443 {
6444 SKIP_WHITESPACE ();
6445 bystart = input_line_pointer;
6446
6447 /* Look for DO. */
6448 bystop = NULL;
6449 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6450 {
6451 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6452 && (input_line_pointer[2] == '.'
6453 || ! is_part_of_name (input_line_pointer[2])))
6454 {
6455 bystop = input_line_pointer;
6456 input_line_pointer += 2;
6457 break;
6458 }
6459 ++input_line_pointer;
6460 }
6461 if (bystop == NULL)
6462 {
6463 as_bad (_("missing do"));
6464 ignore_rest_of_line ();
6465 return;
6466 }
6467 if (bystop > bystart
6468 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6469 --bystop;
6470 }
6471
6472 if (*input_line_pointer != '.')
6473 extent = '\0';
6474 else
6475 {
6476 extent = input_line_pointer[1];
6477 input_line_pointer += 2;
6478 }
6479
6480 /* We have fully parsed the FOR operands. Now build the loop. */
6481
6482 n = push_mri_control (mri_for);
6483
6484 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6485
6486 /* move init,var */
6487 s = buf;
6488 *s++ = 'm';
6489 *s++ = 'o';
6490 *s++ = 'v';
6491 *s++ = 'e';
6492 if (qual != '\0')
e1f44d10 6493 *s++ = tolower(qual);
252b5132
RH		 6494 *s++ = ' ';
6495 memcpy (s, initstart, initstop - initstart);
6496 s += initstop - initstart;
6497 *s++ = ',';
6498 memcpy (s, varstart, varstop - varstart);
6499 s += varstop - varstart;
6500 *s = '\0';
6501 mri_assemble (buf);
6502
6503 colon (n->top);
6504
6505 /* cmp end,var */
6506 s = buf;
6507 *s++ = 'c';
6508 *s++ = 'm';
6509 *s++ = 'p';
6510 if (qual != '\0')
e1f44d10 6511 *s++ = tolower(qual);
252b5132
RH		 6512 *s++ = ' ';
6513 memcpy (s, endstart, endstop - endstart);
6514 s += endstop - endstart;
6515 *s++ = ',';
6516 memcpy (s, varstart, varstop - varstart);
6517 s += varstop - varstart;
6518 *s = '\0';
6519 mri_assemble (buf);
6520
6521 /* bcc bottom */
e1f44d10 6522 ex[0] = tolower(extent);
252b5132
RH		 6523 ex[1] = '\0';
6524 if (up)
6525 sprintf (buf, "blt%s %s", ex, n->bottom);
6526 else
6527 sprintf (buf, "bgt%s %s", ex, n->bottom);
6528 mri_assemble (buf);
6529
6530 /* Put together the add or sub instruction used by ENDF. */
6531 s = buf;
6532 if (up)
6533 strcpy (s, "add");
6534 else
6535 strcpy (s, "sub");
6536 s += 3;
6537 if (qual != '\0')
e1f44d10 6538 *s++ = tolower(qual);
252b5132
RH		 6539 *s++ = ' ';
6540 memcpy (s, bystart, bystop - bystart);
6541 s += bystop - bystart;
6542 *s++ = ',';
6543 memcpy (s, varstart, varstop - varstart);
6544 s += varstop - varstart;
6545 *s = '\0';
6546 n->incr = buf;
6547
6548 if (flag_mri)
6549 {
6550 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6551 ++input_line_pointer;
6552 }
6553
6554 demand_empty_rest_of_line ();
6555}
6556
6557/* Handle the MRI ENDF pseudo-op. */
6558
6559static void
6560s_mri_endf (ignore)
36823076 6561 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6562{
6563 if (mri_control_stack == NULL
6564 || mri_control_stack->type != mri_for)
6565 {
6566 as_bad (_("endf without for"));
6567 ignore_rest_of_line ();
6568 return;
6569 }
6570
6571 colon (mri_control_stack->next);
6572
6573 mri_assemble (mri_control_stack->incr);
6574
6575 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6576 mri_assemble (mri_control_stack->incr);
6577
6578 free (mri_control_stack->incr);
6579
6580 colon (mri_control_stack->bottom);
6581
6582 pop_mri_control ();
6583
6584 if (flag_mri)
6585 {
6586 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6587 ++input_line_pointer;
6588 }
6589
6590 demand_empty_rest_of_line ();
6591}
6592
6593/* Handle the MRI REPEAT pseudo-op. */
6594
6595static void
6596s_mri_repeat (ignore)
36823076 6597 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6598{
6599 struct mri_control_info *n;
6600
6601 n = push_mri_control (mri_repeat);
6602 colon (n->top);
6603 if (flag_mri)
6604 {
6605 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6606 ++input_line_pointer;
6607 }
6608 demand_empty_rest_of_line ();
6609}
6610
6611/* Handle the MRI UNTIL pseudo-op. */
6612
6613static void
6614s_mri_until (qual)
6615 int qual;
6616{
6617 char *s;
6618
6619 if (mri_control_stack == NULL
6620 || mri_control_stack->type != mri_repeat)
6621 {
6622 as_bad (_("until without repeat"));
6623 ignore_rest_of_line ();
6624 return;
6625 }
6626
6627 colon (mri_control_stack->next);
6628
6629 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6630 ;
6631
6632 parse_mri_control_expression (s, qual, (const char *) NULL,
6633 mri_control_stack->top, '\0');
6634
6635 colon (mri_control_stack->bottom);
6636
6637 input_line_pointer = s;
6638
6639 pop_mri_control ();
6640
6641 if (flag_mri)
6642 {
6643 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6644 ++input_line_pointer;
6645 }
6646
6647 demand_empty_rest_of_line ();
6648}
6649
6650/* Handle the MRI WHILE pseudo-op. */
6651
6652static void
6653s_mri_while (qual)
6654 int qual;
6655{
6656 char *s;
6657
6658 struct mri_control_info *n;
6659
6660 s = input_line_pointer;
e1f44d10
NC		 6661 /* We only accept '*' as introduction of comments if preceded by white space
6662 or at first column of a line (I think this can't actually happen here?)
6663 This is important when assembling:
6664 while d0 <ne> 12(a0,d0*2) do
6665 while d0 <ne> #CONST*20 do */
6666 while ( ! ( is_end_of_line[(unsigned char) *s]
6667 || ( flag_mri
6668 && *s == '*'
6669 && ( s == input_line_pointer
6670 || *(s-1) == ' '
6671 || *(s-1) == '\t'))))
252b5132
RH		 6672 s++;
6673 --s;
6674 while (*s == ' ' || *s == '\t')
6675 --s;
6676 if (s - input_line_pointer > 1
6677 && s[-1] == '.')
6678 s -= 2;
6679 if (s - input_line_pointer < 2
6680 || strncasecmp (s - 1, "DO", 2) != 0)
6681 {
6682 as_bad (_("missing do"));
6683 ignore_rest_of_line ();
6684 return;
6685 }
6686
6687 n = push_mri_control (mri_while);
6688
6689 colon (n->next);
6690
6691 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6692 s[1] == '.' ? s[2] : '\0');
6693
6694 input_line_pointer = s + 1;
6695 if (*input_line_pointer == '.')
6696 input_line_pointer += 2;
6697
6698 if (flag_mri)
6699 {
6700 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6701 ++input_line_pointer;
6702 }
6703
6704 demand_empty_rest_of_line ();
6705}
6706
6707/* Handle the MRI ENDW pseudo-op. */
6708
6709static void
6710s_mri_endw (ignore)
36823076 6711 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6712{
6713 char *buf;
6714
6715 if (mri_control_stack == NULL
6716 || mri_control_stack->type != mri_while)
6717 {
6718 as_bad (_("endw without while"));
6719 ignore_rest_of_line ();
6720 return;
6721 }
6722
6723 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6724 sprintf (buf, "bra %s", mri_control_stack->next);
6725 mri_assemble (buf);
6726 free (buf);
6727
6728 colon (mri_control_stack->bottom);
6729
6730 pop_mri_control ();
6731
6732 if (flag_mri)
6733 {
6734 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6735 ++input_line_pointer;
6736 }
6737
6738 demand_empty_rest_of_line ();
6739}
6740\f
6741/*
6742 * md_parse_option
6743 * Invocation line includes a switch not recognized by the base assembler.
6744 * See if it's a processor-specific option. These are:
6745 *
6746 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6747 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6748 * Select the architecture. Instructions or features not
6749 * supported by the selected architecture cause fatal
6750 * errors. More than one may be specified. The default is
6751 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6752 * for -m68000, and -m68882 is a synonym for -m68881.
6753 * -[A]m[c]no-68851, -[A]m[c]no-68881
6754 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6755 * so don't use or document it, but that's the way the parsing
6756 * works).
6757 *
6758 * -pic Indicates PIC.
6759 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6760 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6761 *
6762 * --bitwise-or
6763 * Permit `|' to be used in expressions.
6764 *
6765 */
6766
6767#ifdef OBJ_ELF
6768CONST char *md_shortopts = "lSA:m:kQ:V";
6769#else
6770CONST char *md_shortopts = "lSA:m:k";
6771#endif
6772
6773struct option md_longopts[] = {
6774#define OPTION_PIC (OPTION_MD_BASE)
6775 {"pic", no_argument, NULL, OPTION_PIC},
6776#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6777 {"register-prefix-optional", no_argument, NULL,
6778 OPTION_REGISTER_PREFIX_OPTIONAL},
6779#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6780 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6781#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6782 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6783#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6784 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6785#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6786 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6787#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6788 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6789#define OPTION_PCREL (OPTION_MD_BASE + 7)
6790 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6791 {NULL, no_argument, NULL, 0}
6792};
bc805888 6793size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6794
6795int
6796md_parse_option (c, arg)
6797 int c;
6798 char *arg;
6799{
6800 switch (c)
6801 {
6802 case 'l': /* -l means keep external to 2 bit offset
6803 rather than 16 bit one */
6804 flag_short_refs = 1;
6805 break;
6806
6807 case 'S': /* -S means that jbsr's always turn into
6808 jsr's. */
6809 flag_long_jumps = 1;
6810 break;
6811
28e7409f
NC		 6812 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6813 branches into absolute jumps. */
6814 flag_keep_pcrel = 1;
6815 break;
6816
252b5132
RH		 6817 case 'A':
6818 if (*arg == 'm')
6819 arg++;
6820 /* intentional fall-through */
6821 case 'm':
6822
6823 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6824 {
6825 int i;
6826 unsigned long arch;
6827 const char *oarg = arg;
6828
6829 arg += 3;
6830 if (*arg == 'm')
6831 {
6832 arg++;
6833 if (arg[0] == 'c' && arg[1] == '6')
6834 arg++;
6835 }
6836 for (i = 0; i < n_archs; i++)
6837 if (!strcmp (arg, archs[i].name))
6838 break;
6839 if (i == n_archs)
6840 {
6841 unknown:
6842 as_bad (_("unrecognized option `%s'"), oarg);
6843 return 0;
6844 }
6845 arch = archs[i].arch;
6846 if (arch == m68881)
6847 no_68881 = 1;
6848 else if (arch == m68851)
6849 no_68851 = 1;
6850 else
6851 goto unknown;
6852 }
6853 else
6854 {
6855 int i;
6856
6857 if (arg[0] == 'c' && arg[1] == '6')
6858 arg++;
6859
6860 for (i = 0; i < n_archs; i++)
6861 if (!strcmp (arg, archs[i].name))
6862 {
6863 unsigned long arch = archs[i].arch;
6864 if (cpu_of_arch (arch))
6865 /* It's a cpu spec. */
6866 {
6867 current_architecture &= ~m68000up;
6868 current_architecture |= arch;
6869 }
6870 else if (arch == m68881)
6871 {
6872 current_architecture |= m68881;
6873 no_68881 = 0;
6874 }
6875 else if (arch == m68851)
6876 {
6877 current_architecture |= m68851;
6878 no_68851 = 0;
6879 }
6880 else
6881 /* ??? */
6882 abort ();
6883 break;
6884 }
6885 if (i == n_archs)
6886 {
6887 as_bad (_("unrecognized architecture specification `%s'"), arg);
6888 return 0;
6889 }
6890 }
6891 break;
6892
6893 case OPTION_PIC:
6894 case 'k':
6895 flag_want_pic = 1;
6896 break; /* -pic, Position Independent Code */
6897
6898 case OPTION_REGISTER_PREFIX_OPTIONAL:
6899 flag_reg_prefix_optional = 1;
6900 reg_prefix_optional_seen = 1;
6901 break;
6902
6903 /* -V: SVR4 argument to print version ID. */
6904 case 'V':
6905 print_version_id ();
6906 break;
6907
6908 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6909 should be emitted or not. FIXME: Not implemented. */
6910 case 'Q':
6911 break;
6912
6913 case OPTION_BITWISE_OR:
6914 {
6915 char *n, *t;
6916 const char *s;
6917
6918 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6919 t = n;
6920 for (s = m68k_comment_chars; *s != '\0'; s++)
6921 if (*s != '|')
6922 *t++ = *s;
6923 *t = '\0';
6924 m68k_comment_chars = n;
6925 }
6926 break;
6927
6928 case OPTION_BASE_SIZE_DEFAULT_16:
6929 m68k_index_width_default = SIZE_WORD;
6930 break;
6931
6932 case OPTION_BASE_SIZE_DEFAULT_32:
6933 m68k_index_width_default = SIZE_LONG;
6934 break;
6935
6936 case OPTION_DISP_SIZE_DEFAULT_16:
6937 m68k_rel32 = 0;
6938 m68k_rel32_from_cmdline = 1;
6939 break;
6940
6941 case OPTION_DISP_SIZE_DEFAULT_32:
6942 m68k_rel32 = 1;
6943 m68k_rel32_from_cmdline = 1;
6944 break;
6945
6946 default:
6947 return 0;
6948 }
6949
6950 return 1;
6951}
6952
6953void
6954md_show_usage (stream)
6955 FILE *stream;
6956{
bc805888 6957 fprintf (stream, _("\
252b5132
RH		 6958680X0 options:\n\
6959-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 6960-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6961-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6962-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
252b5132
RH		 6963 specify variant of 680X0 architecture [default 68020]\n\
6964-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6965 target has/lacks floating-point coprocessor\n\
6966 [default yes for 68020, 68030, and cpu32]\n"));
bc805888 6967 fprintf (stream, _("\
252b5132
RH		 6968-m68851 | -mno-68851\n\
6969 target has/lacks memory-management unit coprocessor\n\
6970 [default yes for 68020 and up]\n\
6971-pic, -k generate position independent code\n\
6972-S turn jbsr into jsr\n\
28e7409f 6973--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 6974--register-prefix-optional\n\
6975 recognize register names without prefix character\n\
6976--bitwise-or do not treat `|' as a comment character\n"));
6977 fprintf (stream, _("\
6978--base-size-default-16 base reg without size is 16 bits\n\
6979--base-size-default-32 base reg without size is 32 bits (default)\n\
6980--disp-size-default-16 displacement with unknown size is 16 bits\n\
6981--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6982}
6983\f
6984#ifdef TEST2
6985
6986/* TEST2: Test md_assemble() */
6987/* Warning, this routine probably doesn't work anymore */
6988
6989main ()
6990{
6991 struct m68k_it the_ins;
6992 char buf[120];
6993 char *cp;
6994 int n;
6995
6996 m68k_ip_begin ();
6997 for (;;)
6998 {
6999 if (!gets (buf) || !*buf)
7000 break;
7001 if (buf[0] == '|' || buf[1] == '.')
7002 continue;
7003 for (cp = buf; *cp; cp++)
7004 if (*cp == '\t')
7005 *cp = ' ';
7006 if (is_label (buf))
7007 continue;
7008 memset (&the_ins, '\0', sizeof (the_ins));
7009 m68k_ip (&the_ins, buf);
7010 if (the_ins.error)
7011 {
7012 printf (_("Error %s in %s\n"), the_ins.error, buf);
7013 }
7014 else
7015 {
7016 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7017 for (n = 0; n < the_ins.numo; n++)
7018 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7019 printf (" ");
7020 print_the_insn (&the_ins.opcode[0], stdout);
7021 (void) putchar ('\n');
7022 }
7023 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7024 {
7025 if (the_ins.operands[n].error)
7026 {
7027 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7028 continue;
7029 }
7030 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7031 if (the_ins.operands[n].b_const)
7032 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7033 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7034 if (the_ins.operands[n].b_iadd)
7035 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7036 (void) putchar ('\n');
7037 }
7038 }
7039 m68k_ip_end ();
7040 return 0;
7041}
7042
7043is_label (str)
7044 char *str;
7045{
7046 while (*str == ' ')
7047 str++;
7048 while (*str && *str != ' ')
7049 str++;
7050 if (str[-1] == ':' || str[1] == '=')
7051 return 1;
7052 return 0;
7053}
7054
7055#endif
7056
7057/* Possible states for relaxation:
7058
7059 0 0 branch offset byte (bra, etc)
7060 0 1 word
7061 0 2 long
7062
7063 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7064 1 1 word
7065 1 2 long
7066
7067 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7068 2 1 word-long
7069 2 2 long-word
7070 2 3 long-long
7071
7072 */
7073
7074/* We have no need to default values of symbols. */
7075
252b5132
RH		 7076symbolS *
7077md_undefined_symbol (name)
36823076 7078 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7079{
7080 return 0;
7081}
7082
7083/* Round up a section size to the appropriate boundary. */
7084valueT
7085md_section_align (segment, size)
36823076 7086 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7087 valueT size;
7088{
7089#ifdef OBJ_AOUT
7090#ifdef BFD_ASSEMBLER
7091 /* For a.out, force the section size to be aligned. If we don't do
7092 this, BFD will align it for us, but it will not write out the
7093 final bytes of the section. This may be a bug in BFD, but it is
7094 easier to fix it here since that is how the other a.out targets
7095 work. */
7096 int align;
7097
7098 align = bfd_get_section_alignment (stdoutput, segment);
7099 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7100#endif
7101#endif
7102
7103 return size;
7104}
7105
7106/* Exactly what point is a PC-relative offset relative TO?
7107 On the 68k, it is relative to the address of the first extension
7108 word. The difference between the addresses of the offset and the
92774660 7109 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7110long
7111md_pcrel_from (fixP)
7112 fixS *fixP;
7113{
7114 int adjust;
7115
8390138c
AS		 7116 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7117 sign extend the value here. */
7118 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7119 if (adjust == 64)
7120 adjust = -1;
7121 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7122}
7123
7124#ifndef BFD_ASSEMBLER
7125#ifdef OBJ_COFF
7126
252b5132
RH		 7127void
7128tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7129 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7130{
7131}
7132
7133int
7134tc_coff_sizemachdep (frag)
7135 fragS *frag;
7136{
7137 switch (frag->fr_subtype & 0x3)
7138 {
7139 case BYTE:
7140 return 1;
7141 case SHORT:
7142 return 2;
7143 case LONG:
7144 return 4;
7145 default:
7146 abort ();
7147 return 0;
7148 }
7149}
7150
7151#endif
7152#endif
0d96863f
CM		 7153#ifdef OBJ_ELF
7154void m68k_elf_final_processing()
7155{
7156 /* Set file-specific flags if this is a cpu32 processor */
7157 if (cpu_of_arch (current_architecture) & cpu32)
7158 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7159}
7160#endif
GDB Binutils - Deliverables
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