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M68K TLS support.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
cf869cce 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5a49b8ac 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
3882b010 24#include "safe-ctype.h"
252b5132
RH		 25#include "obstack.h"
26#include "subsegs.h"
f27a3839 27#include "dwarf2dbg.h"
c04898f8 28#include "dw2gencfi.h"
252b5132
RH		 29
30#include "opcode/m68k.h"
31#include "m68k-parse.h"
32
0d96863f
CM		 33#if defined (OBJ_ELF)
34#include "elf/m68k.h"
35#endif
36
31302357
AS		 37#ifdef M68KCOFF
38#include "obj-coff.h"
39#endif
40
cf869cce
NC		 41#ifdef OBJ_ELF
42static void m68k_elf_cons (int);
43#endif
44
252b5132
RH		 45/* This string holds the chars that always start a comment. If the
46 pre-processor is disabled, these aren't very useful. The macro
47 tc_comment_chars points to this. We use this, rather than the
48 usual comment_chars, so that the --bitwise-or option will work. */
49#if defined (TE_SVR4) || defined (TE_DELTA)
50const char *m68k_comment_chars = "|#";
51#else
52const char *m68k_comment_chars = "|";
53#endif
54
55/* This array holds the chars that only start a comment at the beginning of
56 a line. If the line seems to have the form '# 123 filename'
57 .line and .file directives will appear in the pre-processed output */
58/* Note that input_file.c hand checks for '#' at the beginning of the
59 first line of the input file. This is because the compiler outputs
92774660
KH		 60 #NO_APP at the beginning of its output. */
61/* Also note that comments like this one will always work. */
252b5132
RH		 62const char line_comment_chars[] = "#*";
63
63a0b638 64const char line_separator_chars[] = ";";
252b5132 65
36759679 66/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 67const char EXP_CHARS[] = "eE";
252b5132
RH		 68
69/* Chars that mean this number is a floating point constant, as
70 in "0f12.456" or "0d1.2345e12". */
71
5a38dc70 72const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 73
74/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
75 changed in read.c . Ideally it shouldn't have to know about it at all,
76 but nothing is ideal around here. */
77
252b5132
RH		 78/* Are we trying to generate PIC code? If so, absolute references
79 ought to be made into linkage table references or pc-relative
92774660 80 references. Not implemented. For ELF there are other means
252b5132
RH		 81 to denote pic relocations. */
82int flag_want_pic;
83
36759679
NC		 84static int flag_short_refs; /* -l option. */
85static int flag_long_jumps; /* -S option. */
28e7409f 86static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 87
88#ifdef REGISTER_PREFIX_OPTIONAL
89int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
90#else
91int flag_reg_prefix_optional;
92#endif
93
94/* Whether --register-prefix-optional was used on the command line. */
95static int reg_prefix_optional_seen;
96
97/* The floating point coprocessor to use by default. */
98static enum m68k_register m68k_float_copnum = COP1;
99
100/* If this is non-zero, then references to number(%pc) will be taken
101 to refer to number, rather than to %pc + number. */
102static int m68k_abspcadd;
103
104/* If this is non-zero, then the quick forms of the move, add, and sub
105 instructions are used when possible. */
106static int m68k_quick = 1;
107
108/* If this is non-zero, then if the size is not specified for a base
109 or outer displacement, the assembler assumes that the size should
110 be 32 bits. */
111static int m68k_rel32 = 1;
112
113/* This is non-zero if m68k_rel32 was set from the command line. */
114static int m68k_rel32_from_cmdline;
115
116/* The default width to use for an index register when using a base
117 displacement. */
118static enum m68k_size m68k_index_width_default = SIZE_LONG;
119
120/* We want to warn if any text labels are misaligned. In order to get
121 the right line number, we need to record the line number for each
122 label. */
252b5132
RH		 123struct label_line
124{
125 struct label_line *next;
126 symbolS *label;
127 char *file;
128 unsigned int line;
129 int text;
130};
131
132/* The list of labels. */
133
134static struct label_line *labels;
135
136/* The current label. */
137
138static struct label_line *current_label;
139
60fed2d3
NC		 140/* Pointer to list holding the opcodes sorted by name. */
141static struct m68k_opcode const ** m68k_sorted_opcodes;
142
36759679
NC		 143/* Its an arbitrary name: This means I don't approve of it.
144 See flames below. */
252b5132
RH		 145static struct obstack robyn;
146
252b5132
RH		 147struct m68k_incant
148 {
149 const char *m_operands;
150 unsigned long m_opcode;
151 short m_opnum;
152 short m_codenum;
153 int m_arch;
154 struct m68k_incant *m_next;
155 };
156
157#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
158#define gettwo(x) (((x)->m_opcode)&0xffff)
159
2da12c60
NS		 160static const enum m68k_register m68000_ctrl[] = { 0 };
161static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 162 SFC, DFC, USP, VBR,
163 0
164};
2da12c60 165static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 166 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
167 0
168};
2da12c60 169static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
171 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
172 0
173};
2da12c60 174static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 175 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
176 USP, VBR, URP, SRP, PCR,
177 0
178};
2da12c60 179static const enum m68k_register mcf_ctrl[] = {
3e602632 180 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 181 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
182 0
183};
f75192f2
KH		 184static const enum m68k_register mcf51qe_ctrl[] = {
185 VBR,
186 0
187};
78336706
NS		 188static const enum m68k_register mcf5206_ctrl[] = {
189 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 190 0
191};
2da12c60 192static const enum m68k_register mcf5208_ctrl[] = {
78336706 193 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 194 0
195};
96e0bbcc 196static const enum m68k_register mcf5210a_ctrl[] = {
78336706 197 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 198 0
199};
2da12c60 200static const enum m68k_register mcf5213_ctrl[] = {
78336706 201 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 202 0
203};
2da12c60 204static const enum m68k_register mcf5216_ctrl[] = {
78336706 205 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 206 0
207};
d5be9593
NS		 208static const enum m68k_register mcf52223_ctrl[] = {
209 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
210 0
211};
96e0bbcc 212static const enum m68k_register mcf52235_ctrl[] = {
def8fc92 213 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 214 0
215};
216static const enum m68k_register mcf5225_ctrl[] = {
78336706 217 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 218 0
219};
2da12c60 220static const enum m68k_register mcf5235_ctrl[] = {
78336706 221 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 222 0
223};
2da12c60 224static const enum m68k_register mcf5249_ctrl[] = {
78336706 225 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 226 0
227};
2da12c60
NS		 228static const enum m68k_register mcf5250_ctrl[] = {
229 VBR,
230 0
231};
d5be9593 232static const enum m68k_register mcf5253_ctrl[] = {
def8fc92 233 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
d5be9593
NS		 234 0
235};
2da12c60 236static const enum m68k_register mcf5271_ctrl[] = {
78336706 237 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 238 0
239};
240static const enum m68k_register mcf5272_ctrl[] = {
78336706 241 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 242 0
243};
244static const enum m68k_register mcf5275_ctrl[] = {
78336706 245 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 246 0
247};
248static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 249 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
250 0
251};
252static const enum m68k_register mcf5307_ctrl[] = {
253 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 254 0
255};
256static const enum m68k_register mcf5329_ctrl[] = {
78336706 257 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 258 0
259};
260static const enum m68k_register mcf5373_ctrl[] = {
78336706 261 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 262 0
263};
264static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 265 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
266 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
267 MBAR, SECMBAR,
268 MPCR /* Multiprocessor Control register */,
269 EDRAMBAR /* Embedded DRAM Base Address Register */,
270 /* Permutation control registers. */
3e602632
NC		 271 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
272 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 273 /* Legacy names */
274 TC /* ASID */, BUSCR /* MMUBAR */,
275 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
276 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 277 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 278 0
279};
def8fc92
KH		 280static const enum m68k_register mcf5407_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
282 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
283 /* Legacy names */
284 TC /* ASID */,
285 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
286 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
287 0
288};
9a2e615a
NS		 289static const enum m68k_register mcf54455_ctrl[] = {
290 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
291 VBR, PC, RAMBAR1, MBAR,
292 /* Legacy names */
293 TC /* ASID */, BUSCR /* MMUBAR */,
294 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
295 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
296 0
297};
a8e24a56
NS		 298static const enum m68k_register mcf5475_ctrl[] = {
299 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
300 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
301 /* Legacy names */
302 TC /* ASID */, BUSCR /* MMUBAR */,
303 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 304 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 305 0
306};
307static const enum m68k_register mcf5485_ctrl[] = {
308 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
309 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
310 /* Legacy names */
311 TC /* ASID */, BUSCR /* MMUBAR */,
312 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 313 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 314 0
315};
f7ec513b 316static const enum m68k_register fido_ctrl[] = {
d0fa1372 317 SFC, DFC, USP, VBR, CAC, MBO,
f7ec513b
KH		 318 0
319};
2da12c60 320#define cpu32_ctrl m68010_ctrl
252b5132
RH		 321
322static const enum m68k_register *control_regs;
323
36759679 324/* Internal form of a 68020 instruction. */
252b5132
RH		 325struct m68k_it
326{
327 const char *error;
36759679 328 const char *args; /* List of opcode info. */
252b5132
RH		 329 int numargs;
330
36759679 331 int numo; /* Number of shorts in opcode. */
252b5132
RH		 332 short opcode[11];
333
334 struct m68k_op operands[6];
335
36759679 336 int nexp; /* Number of exprs in use. */
252b5132
RH		 337 struct m68k_exp exprs[4];
338
36759679 339 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 340 struct
341 {
36759679 342 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 343 symbolS *fadd;
344 offsetT foff;
345 int fragty;
346 }
347 fragb[4];
348
36759679 349 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 350 struct
351 {
352 int n;
353 expressionS exp;
354 char wid;
355 char pcrel;
356 /* In a pc relative address the difference between the address
357 of the offset and the address that the offset is relative
358 to. This depends on the addressing mode. Basically this
359 is the value to put in the offset field to address the
360 first byte of the offset, without regarding the special
361 significance of some values (in the branch instruction, for
362 example). */
363 int pcrel_fix;
364#ifdef OBJ_ELF
365 /* Whether this expression needs special pic relocation, and if
366 so, which. */
367 enum pic_relocation pic_reloc;
368#endif
369 }
36759679 370 reloc[5]; /* Five is enough??? */
252b5132
RH		 371};
372
9840d27e 373#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 374#define float_of_arch(x) ((x) & mfloat)
375#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 376#define arch_coldfire_p(x) ((x) & mcfisa_a)
377#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 378
36759679 379/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 380#define HAVE_LONG_DISP(x) \
381 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
382#define HAVE_LONG_CALL(x) \
383 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
384#define HAVE_LONG_COND(x) \
385 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
386#define HAVE_LONG_BRANCH(x) \
387 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
cac27205 388#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
252b5132 389
36759679 390static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 391
392#define op(ex) ((ex)->exp.X_op)
393#define adds(ex) ((ex)->exp.X_add_symbol)
394#define subs(ex) ((ex)->exp.X_op_symbol)
395#define offs(ex) ((ex)->exp.X_add_number)
396
36759679 397/* Macros for adding things to the m68k_it struct. */
31302357 398#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 399
36759679
NC		 400/* Like addword, but goes BEFORE general operands. */
401
252b5132 402static void
31302357 403insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 404{
405 int z;
07726851 406 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 407 the_ins.opcode[z] = the_ins.opcode[z - 1];
408 for (z = 0; z < the_ins.nrel; z++)
409 the_ins.reloc[z].n += 2;
252b5132
RH		 410 for (z = 0; z < the_ins.nfrag; z++)
411 the_ins.fragb[z].fragoff++;
8a104df9 412 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 413 the_ins.numo++;
414}
415
416/* The numo+1 kludge is so we can hit the low order byte of the prev word.
417 Blecch. */
418static void
31302357 419add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 420{
31302357
AS		 421 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
422 ? the_ins.numo * 2 - 1
423 : (width == 'b'
424 ? the_ins.numo * 2 + 1
425 : the_ins.numo * 2));
252b5132
RH		 426 the_ins.reloc[the_ins.nrel].exp = exp->exp;
427 the_ins.reloc[the_ins.nrel].wid = width;
428 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
429#ifdef OBJ_ELF
430 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
431#endif
432 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
433}
434
435/* Cause an extra frag to be generated here, inserting up to 10 bytes
436 (that value is chosen in the frag_var call in md_assemble). TYPE
437 is the subtype of the frag to be generated; its primary type is
438 rs_machine_dependent.
439
440 The TYPE parameter is also used by md_convert_frag_1 and
441 md_estimate_size_before_relax. The appropriate type of fixup will
442 be emitted by md_convert_frag_1.
443
444 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
445static void
31302357 446add_frag (symbolS *add, offsetT off, int type)
252b5132 447{
8a104df9
KH		 448 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
449 the_ins.fragb[the_ins.nfrag].fadd = add;
450 the_ins.fragb[the_ins.nfrag].foff = off;
451 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 452}
453
454#define isvar(ex) \
455 (op (ex) != O_constant && op (ex) != O_big)
456
31302357
AS		 457static char *crack_operand (char *str, struct m68k_op *opP);
458static int get_num (struct m68k_exp *exp, int ok);
459static int reverse_16_bits (int in);
460static int reverse_8_bits (int in);
461static void install_gen_operand (int mode, int val);
462static void install_operand (int mode, int val);
463static void s_bss (int);
464static void s_data1 (int);
465static void s_data2 (int);
466static void s_even (int);
467static void s_proc (int);
468static void s_chip (int);
469static void s_fopt (int);
470static void s_opt (int);
471static void s_reg (int);
472static void s_restore (int);
473static void s_save (int);
474static void s_mri_if (int);
475static void s_mri_else (int);
476static void s_mri_endi (int);
477static void s_mri_break (int);
478static void s_mri_next (int);
479static void s_mri_for (int);
480static void s_mri_endf (int);
481static void s_mri_repeat (int);
482static void s_mri_until (int);
483static void s_mri_while (int);
484static void s_mri_endw (int);
266abb8f
NS		 485static void s_m68k_cpu (int);
486static void s_m68k_arch (int);
487
488struct m68k_cpu
489{
490 unsigned long arch; /* Architecture features. */
2da12c60 491 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 492 const char *name; /* Name */
0b2e31dc
NS		 493 int alias; /* Alias for a cannonical name. If 1, then
494 succeeds canonical name, if -1 then
495 succeeds canonical name, if <-1 ||>1 this is a
496 deprecated name, and the next/previous name
497 should be used. */
266abb8f 498};
252b5132 499
266abb8f
NS		 500/* We hold flags for features explicitly enabled and explicitly
501 disabled. */
252b5132 502static int current_architecture;
266abb8f 503static int not_current_architecture;
266abb8f
NS		 504static const struct m68k_cpu *selected_arch;
505static const struct m68k_cpu *selected_cpu;
506static int initialized;
252b5132 507
266abb8f
NS		 508/* Architecture models. */
509static const struct m68k_cpu m68k_archs[] =
510{
2da12c60
NS		 511 {m68000, m68000_ctrl, "68000", 0},
512 {m68010, m68010_ctrl, "68010", 0},
513 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
514 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
515 {m68040, m68040_ctrl, "68040", 0},
516 {m68060, m68060_ctrl, "68060", 0},
517 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 518 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 519 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
520 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
521 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 522 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 523 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
524 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 525 {0,0,NULL, 0}
526};
252b5132 527
0b2e31dc
NS		 528/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
529 for either. */
266abb8f
NS		 530static const struct m68k_cpu m68k_extensions[] =
531{
2da12c60
NS		 532 {m68851, NULL, "68851", -1},
533 {m68881, NULL, "68881", -1},
534 {m68881, NULL, "68882", -1},
cf869cce 535
2da12c60 536 {cfloat|m68881, NULL, "float", 0},
cf869cce 537
2da12c60
NS		 538 {mcfhwdiv, NULL, "div", 1},
539 {mcfusp, NULL, "usp", 1},
540 {mcfmac, NULL, "mac", 1},
541 {mcfemac, NULL, "emac", 1},
cf869cce 542
2da12c60 543 {0,NULL,NULL, 0}
266abb8f
NS		 544};
545
546/* Processor list */
547static const struct m68k_cpu m68k_cpus[] =
548{
2da12c60
NS		 549 {m68000, m68000_ctrl, "68000", 0},
550 {m68000, m68000_ctrl, "68ec000", 1},
551 {m68000, m68000_ctrl, "68hc000", 1},
552 {m68000, m68000_ctrl, "68hc001", 1},
553 {m68000, m68000_ctrl, "68008", 1},
554 {m68000, m68000_ctrl, "68302", 1},
555 {m68000, m68000_ctrl, "68306", 1},
556 {m68000, m68000_ctrl, "68307", 1},
557 {m68000, m68000_ctrl, "68322", 1},
558 {m68000, m68000_ctrl, "68356", 1},
559 {m68010, m68010_ctrl, "68010", 0},
560 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
561 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
562 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
563 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
564 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
565 {m68040, m68040_ctrl, "68040", 0},
566 {m68040, m68040_ctrl, "68ec040", 1},
567 {m68060, m68060_ctrl, "68060", 0},
568 {m68060, m68060_ctrl, "68ec060", 1},
cf869cce 569
2da12c60
NS		 570 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
571 {cpu32|m68881, cpu32_ctrl, "68330", 1},
572 {cpu32|m68881, cpu32_ctrl, "68331", 1},
573 {cpu32|m68881, cpu32_ctrl, "68332", 1},
574 {cpu32|m68881, cpu32_ctrl, "68333", 1},
575 {cpu32|m68881, cpu32_ctrl, "68334", 1},
576 {cpu32|m68881, cpu32_ctrl, "68336", 1},
577 {cpu32|m68881, cpu32_ctrl, "68340", 1},
578 {cpu32|m68881, cpu32_ctrl, "68341", 1},
579 {cpu32|m68881, cpu32_ctrl, "68349", 1},
580 {cpu32|m68881, cpu32_ctrl, "68360", 1},
f75192f2
KH		 581
582 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
cf869cce 583
2da12c60
NS		 584 {mcfisa_a, mcf_ctrl, "5200", 0},
585 {mcfisa_a, mcf_ctrl, "5202", 1},
586 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 587 {mcfisa_a, mcf5206_ctrl, "5206", 1},
cf869cce 588
78336706 589 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
cf869cce 590
2da12c60
NS		 591 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
cf869cce 593
96e0bbcc
NS		 594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
cf869cce 596
2da12c60
NS		 597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
cf869cce 600
2da12c60
NS		 601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
602 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
604
d5be9593
NS		 605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
607
96e0bbcc
NS		 608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
609 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
cf869cce 612
96e0bbcc
NS		 613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
cf869cce 615
2da12c60
NS		 616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
617 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
618 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
621
622 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
623 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 624 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
2da12c60
NS		 625
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
628
629 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
630
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
633
634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
638
78336706 639 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
2da12c60
NS		 640
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
645
646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
649
def8fc92 650 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
9a2e615a
NS		 651
652 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
653 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
654 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
655 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
656 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
657 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
2da12c60 658
a8e24a56
NS		 659 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
660 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
661 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
662 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
663 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
664 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
665 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
2da12c60 666
a8e24a56
NS		 667 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
668 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
669 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
670 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
671 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
672 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
673 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
2da12c60 674
b3768379 675 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 676 {fido_a, fido_ctrl, "fido", 1},
9840d27e 677
2da12c60 678 {0,NULL,NULL, 0}
dc84e067 679 };
252b5132 680
266abb8f
NS		 681static const struct m68k_cpu *m68k_lookup_cpu
682(const char *, const struct m68k_cpu *, int, int *);
683static int m68k_set_arch (const char *, int, int);
684static int m68k_set_cpu (const char *, int, int);
685static int m68k_set_extension (const char *, int, int);
686static void m68k_init_arch (void);
252b5132 687
151337e8
NC		 688/* This is the assembler relaxation table for m68k. m68k is a rich CISC
689 architecture and we have a lot of relaxation modes. */
252b5132 690
151337e8
NC		 691/* Macros used in the relaxation code. */
692#define TAB(x,y) (((x) << 2) + (y))
693#define TABTYPE(x) ((x) >> 2)
694
695/* Relaxation states. */
696#define BYTE 0
697#define SHORT 1
698#define LONG 2
699#define SZ_UNDEF 3
700
701/* Here are all the relaxation modes we support. First we can relax ordinary
702 branches. On 68020 and higher and on CPU32 all branch instructions take
703 three forms, so on these CPUs all branches always remain as such. When we
704 have to expand to the LONG form on a 68000, though, we substitute an
705 absolute jump instead. This is a direct replacement for unconditional
706 branches and a branch over a jump for conditional branches. However, if the
707 user requires PIC and disables this with --pcrel, we can only relax between
708 BYTE and SHORT forms, punting if that isn't enough. This gives us four
709 different relaxation modes for branches: */
710
36759679
NC		 711#define BRANCHBWL 0 /* Branch byte, word, or long. */
712#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
713#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
714#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 715
716/* We also relax coprocessor branches and DBcc's. All CPUs that support
717 coprocessor branches support them in word and long forms, so we have only
718 one relaxation mode for them. DBcc's are word only on all CPUs. We can
719 relax them to the LONG form with a branch-around sequence. This sequence
720 can use a long branch (if available) or an absolute jump (if acceptable).
721 This gives us two relaxation modes. If long branches are not available and
722 absolute jumps are not acceptable, we don't relax DBcc's. */
723
36759679
NC		 724#define FBRANCH 4 /* Coprocessor branch. */
725#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
726#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 727
728/* That's all for instruction relaxation. However, we also relax PC-relative
729 operands. Specifically, we have three operand relaxation modes. On the
730 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
731 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
732 two. Also PC+displacement+index operands in their simple form (with a non-
733 suppressed index without memory indirection) are supported on all CPUs, but
734 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
735 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
736 form of the PC+displacement+index operand. Finally, some absolute operands
737 can be relaxed down to 16-bit PC-relative. */
738
36759679
NC		 739#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
740#define PCINDEX 8 /* PC + displacement + index. */
741#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132 742
cac27205
NC		 743/* This relaxation is required for branches where there is no long
744 branch and we are in pcrel mode. We generate a bne/beq pair. */
745#define BRANCHBWPL 10 /* Branch byte, word or pair of longs
746 */
747
252b5132 748/* Note that calls to frag_var need to specify the maximum expansion
cac27205
NC		 749 needed; this is currently 12 bytes for bne/beq pair. */
750#define FRAG_VAR_SIZE 12
252b5132
RH		 751
752/* The fields are:
753 How far Forward this mode will reach:
754 How far Backward this mode will reach:
755 How many bytes this mode will add to the size of the frag
756 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 757
758 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 759relax_typeS md_relax_table[] =
760{
ac62c346
AM		 761 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
762 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
763 { 0, 0, 4, 0 },
764 { 1, 1, 0, 0 },
765
766 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
767 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
768 { 0, 0, 4, 0 },
769 { 1, 1, 0, 0 },
770
771 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
772 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
773 { 0, 0, 6, 0 },
774 { 1, 1, 0, 0 },
775
776 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
777 { 0, 0, 2, 0 },
778 { 1, 1, 0, 0 },
779 { 1, 1, 0, 0 },
780
36759679 781 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 782 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
783 { 0, 0, 4, 0 },
784 { 1, 1, 0, 0 },
785
36759679 786 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 787 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
788 { 0, 0, 10, 0 },
789 { 1, 1, 0, 0 },
790
36759679 791 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 792 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
793 { 0, 0, 10, 0 },
794 { 1, 1, 0, 0 },
795
36759679 796 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 797 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
798 { 0, 0, 6, 0 },
799 { 1, 1, 0, 0 },
800
801 { 125, -130, 0, TAB (PCINDEX, SHORT) },
802 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
803 { 0, 0, 4, 0 },
804 { 1, 1, 0, 0 },
805
36759679 806 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 807 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
808 { 0, 0, 4, 0 },
809 { 1, 1, 0, 0 },
cac27205
NC		 810
811 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
812 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
813 { 0, 0, 10, 0 },
814 { 1, 1, 0, 0 },
252b5132
RH		 815};
816
817/* These are the machine dependent pseudo-ops. These are included so
818 the assembler can work on the output from the SUN C compiler, which
36759679 819 generates these. */
252b5132
RH		 820
821/* This table describes all the machine specific pseudo-ops the assembler
822 has to support. The fields are:
823 pseudo-op name without dot
824 function to call to execute this pseudo-op
36759679 825 Integer arg to pass to the function. */
252b5132
RH		 826const pseudo_typeS md_pseudo_table[] =
827{
828 {"data1", s_data1, 0},
829 {"data2", s_data2, 0},
830 {"bss", s_bss, 0},
831 {"even", s_even, 0},
832 {"skip", s_space, 0},
833 {"proc", s_proc, 0},
834#if defined (TE_SUN3) || defined (OBJ_ELF)
835 {"align", s_align_bytes, 0},
836#endif
837#ifdef OBJ_ELF
838 {"swbeg", s_ignore, 0},
cf869cce 839 {"long", m68k_elf_cons, 4},
252b5132
RH		 840#endif
841 {"extend", float_cons, 'x'},
842 {"ldouble", float_cons, 'x'},
843
266abb8f
NS		 844 {"arch", s_m68k_arch, 0},
845 {"cpu", s_m68k_cpu, 0},
846
252b5132
RH		 847 /* The following pseudo-ops are supported for MRI compatibility. */
848 {"chip", s_chip, 0},
849 {"comline", s_space, 1},
850 {"fopt", s_fopt, 0},
851 {"mask2", s_ignore, 0},
852 {"opt", s_opt, 0},
853 {"reg", s_reg, 0},
854 {"restore", s_restore, 0},
855 {"save", s_save, 0},
856
857 {"if", s_mri_if, 0},
858 {"if.b", s_mri_if, 'b'},
859 {"if.w", s_mri_if, 'w'},
860 {"if.l", s_mri_if, 'l'},
861 {"else", s_mri_else, 0},
862 {"else.s", s_mri_else, 's'},
863 {"else.l", s_mri_else, 'l'},
864 {"endi", s_mri_endi, 0},
865 {"break", s_mri_break, 0},
866 {"break.s", s_mri_break, 's'},
867 {"break.l", s_mri_break, 'l'},
868 {"next", s_mri_next, 0},
869 {"next.s", s_mri_next, 's'},
870 {"next.l", s_mri_next, 'l'},
871 {"for", s_mri_for, 0},
872 {"for.b", s_mri_for, 'b'},
873 {"for.w", s_mri_for, 'w'},
874 {"for.l", s_mri_for, 'l'},
875 {"endf", s_mri_endf, 0},
876 {"repeat", s_mri_repeat, 0},
877 {"until", s_mri_until, 0},
878 {"until.b", s_mri_until, 'b'},
879 {"until.w", s_mri_until, 'w'},
880 {"until.l", s_mri_until, 'l'},
881 {"while", s_mri_while, 0},
882 {"while.b", s_mri_while, 'b'},
883 {"while.w", s_mri_while, 'w'},
884 {"while.l", s_mri_while, 'l'},
885 {"endw", s_mri_endw, 0},
886
887 {0, 0, 0}
888};
889
252b5132 890/* The mote pseudo ops are put into the opcode table, since they
31302357 891 don't start with a . they look like opcodes to gas. */
252b5132 892
5a38dc70 893const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 894{
895
896 {"dcl", cons, 4},
897 {"dc", cons, 2},
898 {"dcw", cons, 2},
899 {"dcb", cons, 1},
900
901 {"dsl", s_space, 4},
902 {"ds", s_space, 2},
903 {"dsw", s_space, 2},
904 {"dsb", s_space, 1},
905
906 {"xdef", s_globl, 0},
907#ifdef OBJ_ELF
908 {"align", s_align_bytes, 0},
909#else
910 {"align", s_align_ptwo, 0},
911#endif
912#ifdef M68KCOFF
913 {"sect", obj_coff_section, 0},
914 {"section", obj_coff_section, 0},
915#endif
916 {0, 0, 0}
917};
918
bd17c2c3
AM		 919/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
920 gives identical results to a 32-bit host. */
921#define TRUNC(X) ((valueT) (X) & 0xffffffff)
922#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
923
924#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
925#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
926#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
927#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
928
929#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
930#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 931#define islong(x) (1)
932
252b5132
RH		 933static char notend_table[256];
934static char alt_notend_table[256];
935#define notend(s) \
936 (! (notend_table[(unsigned char) *s] \
937 || (*s == ':' \
938 && alt_notend_table[(unsigned char) s[1]])))
939
252b5132
RH		 940#ifdef OBJ_ELF
941
c801568a
AM		 942/* Return zero if the reference to SYMBOL from within the same segment may
943 be relaxed. */
944
945/* On an ELF system, we can't relax an externally visible symbol,
946 because it may be overridden by a shared library. However, if
947 TARGET_OS is "elf", then we presume that we are assembling for an
948 embedded system, in which case we don't have to worry about shared
949 libraries, and we can relax any external sym. */
950
951#define relaxable_symbol(symbol) \
6358301e 952 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 953 || S_IS_WEAK (symbol)))
954
252b5132
RH		 955/* Compute the relocation code for a fixup of SIZE bytes, using pc
956 relative relocation if PCREL is non-zero. PIC says whether a special
957 pic relocation was requested. */
958
252b5132 959static bfd_reloc_code_real_type
31302357 960get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 961{
962 switch (pic)
963 {
964 case pic_got_pcrel:
965 switch (size)
966 {
967 case 1:
968 return BFD_RELOC_8_GOT_PCREL;
969 case 2:
970 return BFD_RELOC_16_GOT_PCREL;
971 case 4:
972 return BFD_RELOC_32_GOT_PCREL;
973 }
974 break;
975
976 case pic_got_off:
977 switch (size)
978 {
979 case 1:
980 return BFD_RELOC_8_GOTOFF;
981 case 2:
982 return BFD_RELOC_16_GOTOFF;
983 case 4:
984 return BFD_RELOC_32_GOTOFF;
985 }
986 break;
987
988 case pic_plt_pcrel:
989 switch (size)
990 {
991 case 1:
992 return BFD_RELOC_8_PLT_PCREL;
993 case 2:
994 return BFD_RELOC_16_PLT_PCREL;
995 case 4:
996 return BFD_RELOC_32_PLT_PCREL;
997 }
998 break;
999
1000 case pic_plt_off:
1001 switch (size)
1002 {
1003 case 1:
1004 return BFD_RELOC_8_PLTOFF;
1005 case 2:
1006 return BFD_RELOC_16_PLTOFF;
1007 case 4:
1008 return BFD_RELOC_32_PLTOFF;
1009 }
1010 break;
1011
cf869cce
NC		 1012 case pic_tls_gd:
1013 switch (size)
1014 {
1015 case 1:
1016 return BFD_RELOC_68K_TLS_GD8;
1017 case 2:
1018 return BFD_RELOC_68K_TLS_GD16;
1019 case 4:
1020 return BFD_RELOC_68K_TLS_GD32;
1021 }
1022 break;
1023
1024 case pic_tls_ldm:
1025 switch (size)
1026 {
1027 case 1:
1028 return BFD_RELOC_68K_TLS_LDM8;
1029 case 2:
1030 return BFD_RELOC_68K_TLS_LDM16;
1031 case 4:
1032 return BFD_RELOC_68K_TLS_LDM32;
1033 }
1034 break;
1035
1036 case pic_tls_ldo:
1037 switch (size)
1038 {
1039 case 1:
1040 return BFD_RELOC_68K_TLS_LDO8;
1041 case 2:
1042 return BFD_RELOC_68K_TLS_LDO16;
1043 case 4:
1044 return BFD_RELOC_68K_TLS_LDO32;
1045 }
1046 break;
1047
1048 case pic_tls_ie:
1049 switch (size)
1050 {
1051 case 1:
1052 return BFD_RELOC_68K_TLS_IE8;
1053 case 2:
1054 return BFD_RELOC_68K_TLS_IE16;
1055 case 4:
1056 return BFD_RELOC_68K_TLS_IE32;
1057 }
1058 break;
1059
1060 case pic_tls_le:
1061 switch (size)
1062 {
1063 case 1:
1064 return BFD_RELOC_68K_TLS_LE8;
1065 case 2:
1066 return BFD_RELOC_68K_TLS_LE16;
1067 case 4:
1068 return BFD_RELOC_68K_TLS_LE32;
1069 }
1070 break;
1071
252b5132
RH		 1072 case pic_none:
1073 if (pcrel)
1074 {
1075 switch (size)
1076 {
1077 case 1:
1078 return BFD_RELOC_8_PCREL;
1079 case 2:
1080 return BFD_RELOC_16_PCREL;
1081 case 4:
1082 return BFD_RELOC_32_PCREL;
1083 }
1084 }
1085 else
1086 {
1087 switch (size)
1088 {
1089 case 1:
1090 return BFD_RELOC_8;
1091 case 2:
1092 return BFD_RELOC_16;
1093 case 4:
1094 return BFD_RELOC_32;
1095 }
1096 }
1097 }
1098
1099 if (pcrel)
1100 {
1101 if (pic == pic_none)
1102 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1103 else
1104 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1105 }
1106 else
1107 {
1108 if (pic == pic_none)
1109 as_bad (_("Can not do %d byte relocation"), size);
1110 else
1111 as_bad (_("Can not do %d byte pic relocation"), size);
1112 }
1113
1114 return BFD_RELOC_NONE;
1115}
1116
1117/* Here we decide which fixups can be adjusted to make them relative
1118 to the beginning of the section instead of the symbol. Basically
1119 we need to make sure that the dynamic relocations are done
1120 correctly, so in some cases we force the original symbol to be
1121 used. */
1122int
31302357 1123tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1124{
36759679 1125 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1126 switch (fixP->fx_r_type)
1127 {
1128 case BFD_RELOC_8_GOT_PCREL:
1129 case BFD_RELOC_16_GOT_PCREL:
1130 case BFD_RELOC_32_GOT_PCREL:
1131 case BFD_RELOC_8_GOTOFF:
1132 case BFD_RELOC_16_GOTOFF:
1133 case BFD_RELOC_32_GOTOFF:
1134 case BFD_RELOC_8_PLT_PCREL:
1135 case BFD_RELOC_16_PLT_PCREL:
1136 case BFD_RELOC_32_PLT_PCREL:
1137 case BFD_RELOC_8_PLTOFF:
1138 case BFD_RELOC_16_PLTOFF:
1139 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1140 case BFD_RELOC_68K_TLS_GD32:
1141 case BFD_RELOC_68K_TLS_GD16:
1142 case BFD_RELOC_68K_TLS_GD8:
1143 case BFD_RELOC_68K_TLS_LDM32:
1144 case BFD_RELOC_68K_TLS_LDM16:
1145 case BFD_RELOC_68K_TLS_LDM8:
1146 case BFD_RELOC_68K_TLS_LDO32:
1147 case BFD_RELOC_68K_TLS_LDO16:
1148 case BFD_RELOC_68K_TLS_LDO8:
1149 case BFD_RELOC_68K_TLS_IE32:
1150 case BFD_RELOC_68K_TLS_IE16:
1151 case BFD_RELOC_68K_TLS_IE8:
1152 case BFD_RELOC_68K_TLS_LE32:
1153 case BFD_RELOC_68K_TLS_LE16:
1154 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1155 return 0;
1156
1157 case BFD_RELOC_VTABLE_INHERIT:
1158 case BFD_RELOC_VTABLE_ENTRY:
1159 return 0;
1160
1161 default:
1162 return 1;
1163 }
1164}
1165
1166#else /* !OBJ_ELF */
1167
1168#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1169
22184a77
NC		 1170/* PR gas/3041 Weak symbols are not relaxable
1171 because they must be treated as extern. */
1172#define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
c801568a 1173
252b5132
RH		 1174#endif /* OBJ_ELF */
1175
252b5132 1176arelent *
31302357 1177tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1178{
1179 arelent *reloc;
1180 bfd_reloc_code_real_type code;
1181
8ec6253e
NC		 1182 /* If the tcbit is set, then this was a fixup of a negative value
1183 that was never resolved. We do not have a reloc to handle this,
1184 so just return. We assume that other code will have detected this
1185 situation and produced a helpful error message, so we just tell the
1186 user that the reloc cannot be produced. */
252b5132 1187 if (fixp->fx_tcbit)
8ec6253e
NC		 1188 {
1189 if (fixp->fx_addsy)
b091f402
AM		 1190 as_bad_where (fixp->fx_file, fixp->fx_line,
1191 _("Unable to produce reloc against symbol '%s'"),
1192 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1193 return NULL;
1194 }
252b5132
RH		 1195
1196 if (fixp->fx_r_type != BFD_RELOC_NONE)
1197 {
1198 code = fixp->fx_r_type;
1199
1200 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1201 that fixup_segment converted a non-PC relative reloc into a
1202 PC relative reloc. In such a case, we need to convert the
1203 reloc code. */
1204 if (fixp->fx_pcrel)
1205 {
1206 switch (code)
1207 {
1208 case BFD_RELOC_8:
1209 code = BFD_RELOC_8_PCREL;
1210 break;
1211 case BFD_RELOC_16:
1212 code = BFD_RELOC_16_PCREL;
1213 break;
1214 case BFD_RELOC_32:
1215 code = BFD_RELOC_32_PCREL;
1216 break;
1217 case BFD_RELOC_8_PCREL:
1218 case BFD_RELOC_16_PCREL:
1219 case BFD_RELOC_32_PCREL:
1220 case BFD_RELOC_8_GOT_PCREL:
1221 case BFD_RELOC_16_GOT_PCREL:
1222 case BFD_RELOC_32_GOT_PCREL:
1223 case BFD_RELOC_8_GOTOFF:
1224 case BFD_RELOC_16_GOTOFF:
1225 case BFD_RELOC_32_GOTOFF:
1226 case BFD_RELOC_8_PLT_PCREL:
1227 case BFD_RELOC_16_PLT_PCREL:
1228 case BFD_RELOC_32_PLT_PCREL:
1229 case BFD_RELOC_8_PLTOFF:
1230 case BFD_RELOC_16_PLTOFF:
1231 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1232 case BFD_RELOC_68K_TLS_GD32:
1233 case BFD_RELOC_68K_TLS_GD16:
1234 case BFD_RELOC_68K_TLS_GD8:
1235 case BFD_RELOC_68K_TLS_LDM32:
1236 case BFD_RELOC_68K_TLS_LDM16:
1237 case BFD_RELOC_68K_TLS_LDM8:
1238 case BFD_RELOC_68K_TLS_LDO32:
1239 case BFD_RELOC_68K_TLS_LDO16:
1240 case BFD_RELOC_68K_TLS_LDO8:
1241 case BFD_RELOC_68K_TLS_IE32:
1242 case BFD_RELOC_68K_TLS_IE16:
1243 case BFD_RELOC_68K_TLS_IE8:
1244 case BFD_RELOC_68K_TLS_LE32:
1245 case BFD_RELOC_68K_TLS_LE16:
1246 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1247 break;
1248 default:
1249 as_bad_where (fixp->fx_file, fixp->fx_line,
1250 _("Cannot make %s relocation PC relative"),
1251 bfd_get_reloc_code_name (code));
1252 }
1253 }
1254 }
1255 else
1256 {
1257#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1258 switch (F (fixp->fx_size, fixp->fx_pcrel))
1259 {
1260#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1261 MAP (1, 0, BFD_RELOC_8);
1262 MAP (2, 0, BFD_RELOC_16);
1263 MAP (4, 0, BFD_RELOC_32);
1264 MAP (1, 1, BFD_RELOC_8_PCREL);
1265 MAP (2, 1, BFD_RELOC_16_PCREL);
1266 MAP (4, 1, BFD_RELOC_32_PCREL);
1267 default:
1268 abort ();
1269 }
1270 }
1271#undef F
1272#undef MAP
1273
1274 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1275 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1276 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1277 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1278#ifndef OBJ_ELF
1279 if (fixp->fx_pcrel)
1280 reloc->addend = fixp->fx_addnumber;
22184a77
NC		 1281 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1282 && fixp->fx_addsy
1283 && S_IS_WEAK (fixp->fx_addsy)
1284 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1285 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1c3f20b4
NC		 1286 to put the symbol offset into frags referencing a weak symbol. */
1287 reloc->addend = fixp->fx_addnumber
1288 - (S_GET_VALUE (fixp->fx_addsy) * 2);
252b5132
RH		 1289 else
1290 reloc->addend = 0;
1291#else
1292 if (!fixp->fx_pcrel)
1293 reloc->addend = fixp->fx_addnumber;
1294 else
1295 reloc->addend = (section->vma
8390138c
AS		 1296 /* Explicit sign extension in case char is
1297 unsigned. */
1298 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1299 + fixp->fx_addnumber
1300 + md_pcrel_from (fixp));
1301#endif
1302
1303 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1304 assert (reloc->howto != 0);
1305
1306 return reloc;
1307}
1308
252b5132
RH		 1309/* Handle of the OPCODE hash table. NULL means any use before
1310 m68k_ip_begin() will crash. */
1311static struct hash_control *op_hash;
1312\f
1313/* Assemble an m68k instruction. */
1314
1315static void
31302357 1316m68k_ip (char *instring)
252b5132
RH		 1317{
1318 register char *p;
1319 register struct m68k_op *opP;
1320 register const struct m68k_incant *opcode;
1321 register const char *s;
1322 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1323 char *pdot, *pdotmove;
1324 enum m68k_size siz1, siz2;
1325 char c;
1326 int losing;
1327 int opsfound;
03b13e59 1328 struct m68k_op operands_backup[6];
252b5132
RH		 1329 LITTLENUM_TYPE words[6];
1330 LITTLENUM_TYPE *wordp;
1331 unsigned long ok_arch = 0;
1332
1333 if (*instring == ' ')
36759679 1334 instring++; /* Skip leading whitespace. */
252b5132
RH		 1335
1336 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1337 or exactly 1 space. */
252b5132
RH		 1338 pdot = 0;
1339 for (p = instring; *p != '\0'; p++)
1340 {
1341 if (*p == ' ')
1342 break;
1343 if (*p == '.')
1344 pdot = p;
1345 }
1346
1347 if (p == instring)
1348 {
1349 the_ins.error = _("No operator");
1350 return;
1351 }
1352
1353 /* p now points to the end of the opcode name, probably whitespace.
1354 Make sure the name is null terminated by clobbering the
1355 whitespace, look it up in the hash table, then fix it back.
1356 Remove a dot, first, since the opcode tables have none. */
1357 if (pdot != NULL)
1358 {
1359 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1360 *pdotmove = pdotmove[1];
1361 p--;
1362 }
1363
1364 c = *p;
1365 *p = '\0';
1366 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1367 *p = c;
1368
1369 if (pdot != NULL)
1370 {
1371 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1372 *pdotmove = pdotmove[-1];
1373 *pdot = '.';
1374 ++p;
1375 }
1376
1377 if (opcode == NULL)
1378 {
1379 the_ins.error = _("Unknown operator");
1380 return;
1381 }
1382
36759679 1383 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1384 while (*p == ' ')
1385 ++p;
1386
1387 if (opcode->m_operands == 0)
1388 {
1389 char *old = input_line_pointer;
1390 *old = '\n';
1391 input_line_pointer = p;
36759679 1392 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1393 mote_pseudo_table[opcode->m_opnum].poc_handler
1394 (mote_pseudo_table[opcode->m_opnum].poc_val);
1395 input_line_pointer = old;
1396 *old = 0;
1397
1398 return;
1399 }
1400
1401 if (flag_mri && opcode->m_opnum == 0)
1402 {
1403 /* In MRI mode, random garbage is allowed after an instruction
1404 which accepts no operands. */
1405 the_ins.args = opcode->m_operands;
1406 the_ins.numargs = opcode->m_opnum;
1407 the_ins.numo = opcode->m_codenum;
1408 the_ins.opcode[0] = getone (opcode);
1409 the_ins.opcode[1] = gettwo (opcode);
1410 return;
1411 }
1412
1413 for (opP = &the_ins.operands[0]; *p; opP++)
1414 {
1415 p = crack_operand (p, opP);
1416
1417 if (opP->error)
1418 {
1419 the_ins.error = opP->error;
1420 return;
1421 }
1422 }
1423
1424 opsfound = opP - &the_ins.operands[0];
1425
1426 /* This ugly hack is to support the floating pt opcodes in their
1427 standard form. Essentially, we fake a first enty of type COP#1 */
1428 if (opcode->m_operands[0] == 'I')
1429 {
1430 int n;
1431
1432 for (n = opsfound; n > 0; --n)
1433 the_ins.operands[n] = the_ins.operands[n - 1];
1434
31302357 1435 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1436 the_ins.operands[0].mode = CONTROL;
1437 the_ins.operands[0].reg = m68k_float_copnum;
1438 opsfound++;
1439 }
1440
36759679 1441 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1442 for (losing = 0;;)
1443 {
1444 /* If we didn't get the right number of ops, or we have no
92774660 1445 common model with this pattern then reject this pattern. */
252b5132
RH		 1446
1447 ok_arch |= opcode->m_arch;
1448 if (opsfound != opcode->m_opnum
1449 || ((opcode->m_arch & current_architecture) == 0))
1450 ++losing;
1451 else
1452 {
03b13e59
NC		 1453 int i;
1454
1455 /* Make a copy of the operands of this insn so that
1456 we can modify them safely, should we want to. */
1457 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1458 for (i = 0; i < opsfound; i++)
1459 operands_backup[i] = the_ins.operands[i];
1460
1461 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1462 *s && !losing;
1463 s += 2, opP++)
1464 {
1465 /* Warning: this switch is huge! */
1466 /* I've tried to organize the cases into this order:
1467 non-alpha first, then alpha by letter. Lower-case
1468 goes directly before uppercase counterpart. */
1469 /* Code with multiple case ...: gets sorted by the lowest
1470 case ... it belongs to. I hope this makes sense. */
1471 switch (*s)
1472 {
1473 case '!':
1474 switch (opP->mode)
1475 {
1476 case IMMED:
1477 case DREG:
1478 case AREG:
1479 case FPREG:
1480 case CONTROL:
1481 case AINC:
1482 case ADEC:
1483 case REGLST:
1484 losing++;
1485 break;
1486 default:
1487 break;
1488 }
1489 break;
1490
1491 case '<':
1492 switch (opP->mode)
1493 {
1494 case DREG:
1495 case AREG:
1496 case FPREG:
1497 case CONTROL:
1498 case IMMED:
1499 case ADEC:
1500 case REGLST:
1501 losing++;
1502 break;
1503 default:
1504 break;
1505 }
1506 break;
1507
1508 case '>':
1509 switch (opP->mode)
1510 {
1511 case DREG:
1512 case AREG:
1513 case FPREG:
1514 case CONTROL:
1515 case IMMED:
1516 case AINC:
1517 case REGLST:
1518 losing++;
1519 break;
1520 case ABSL:
1521 break;
1522 default:
1523 if (opP->reg == PC
1524 || opP->reg == ZPC)
1525 losing++;
1526 break;
1527 }
1528 break;
1529
1530 case 'm':
1531 switch (opP->mode)
1532 {
1533 case DREG:
1534 case AREG:
1535 case AINDR:
1536 case AINC:
1537 case ADEC:
1538 break;
1539 default:
1540 losing++;
1541 }
8a104df9 1542 break;
252b5132
RH		 1543
1544 case 'n':
1545 switch (opP->mode)
1546 {
1547 case DISP:
1548 break;
1549 default:
1550 losing++;
1551 }
8a104df9 1552 break;
252b5132
RH		 1553
1554 case 'o':
1555 switch (opP->mode)
1556 {
1557 case BASE:
1558 case ABSL:
1559 case IMMED:
1560 break;
1561 default:
1562 losing++;
1563 }
8a104df9 1564 break;
252b5132
RH		 1565
1566 case 'p':
1567 switch (opP->mode)
1568 {
1569 case DREG:
1570 case AREG:
1571 case AINDR:
1572 case AINC:
1573 case ADEC:
1574 break;
1575 case DISP:
1576 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1577 losing++;
252b5132
RH		 1578 break;
1579 default:
1580 losing++;
1581 }
8a104df9 1582 break;
252b5132
RH		 1583
1584 case 'q':
1585 switch (opP->mode)
1586 {
1587 case DREG:
1588 case AINDR:
1589 case AINC:
1590 case ADEC:
1591 break;
1592 case DISP:
1593 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1594 losing++;
252b5132
RH		 1595 break;
1596 default:
1597 losing++;
1598 break;
1599 }
8a104df9 1600 break;
252b5132
RH		 1601
1602 case 'v':
1603 switch (opP->mode)
1604 {
1605 case DREG:
1606 case AINDR:
1607 case AINC:
1608 case ADEC:
1609 case ABSL:
1610 break;
1611 case DISP:
1612 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1613 losing++;
252b5132
RH		 1614 break;
1615 default:
1616 losing++;
1617 break;
1618 }
1619 break;
1620
1621 case '#':
1622 if (opP->mode != IMMED)
1623 losing++;
1624 else if (s[1] == 'b'
1625 && ! isvar (&opP->disp)
1626 && (opP->disp.exp.X_op != O_constant
1627 || ! isbyte (opP->disp.exp.X_add_number)))
1628 losing++;
1629 else if (s[1] == 'B'
1630 && ! isvar (&opP->disp)
1631 && (opP->disp.exp.X_op != O_constant
1632 || ! issbyte (opP->disp.exp.X_add_number)))
1633 losing++;
1634 else if (s[1] == 'w'
1635 && ! isvar (&opP->disp)
1636 && (opP->disp.exp.X_op != O_constant
1637 || ! isword (opP->disp.exp.X_add_number)))
1638 losing++;
1639 else if (s[1] == 'W'
1640 && ! isvar (&opP->disp)
1641 && (opP->disp.exp.X_op != O_constant
1642 || ! issword (opP->disp.exp.X_add_number)))
1643 losing++;
1644 break;
1645
1646 case '^':
1647 case 'T':
1648 if (opP->mode != IMMED)
1649 losing++;
1650 break;
1651
1652 case '$':
1653 if (opP->mode == AREG
1654 || opP->mode == CONTROL
1655 || opP->mode == FPREG
1656 || opP->mode == IMMED
1657 || opP->mode == REGLST
1658 || (opP->mode != ABSL
1659 && (opP->reg == PC
1660 || opP->reg == ZPC)))
1661 losing++;
1662 break;
1663
1664 case '%':
1665 if (opP->mode == CONTROL
1666 || opP->mode == FPREG
1667 || opP->mode == REGLST
1668 || opP->mode == IMMED
1669 || (opP->mode != ABSL
1670 && (opP->reg == PC
1671 || opP->reg == ZPC)))
1672 losing++;
1673 break;
1674
1675 case '&':
1676 switch (opP->mode)
1677 {
1678 case DREG:
1679 case AREG:
1680 case FPREG:
1681 case CONTROL:
1682 case IMMED:
1683 case AINC:
1684 case ADEC:
1685 case REGLST:
1686 losing++;
1687 break;
1688 case ABSL:
1689 break;
1690 default:
1691 if (opP->reg == PC
1692 || opP->reg == ZPC)
1693 losing++;
1694 break;
1695 }
1696 break;
1697
1698 case '*':
1699 if (opP->mode == CONTROL
1700 || opP->mode == FPREG
1701 || opP->mode == REGLST)
1702 losing++;
1703 break;
1704
1705 case '+':
1706 if (opP->mode != AINC)
1707 losing++;
1708 break;
1709
1710 case '-':
1711 if (opP->mode != ADEC)
1712 losing++;
1713 break;
1714
1715 case '/':
1716 switch (opP->mode)
1717 {
1718 case AREG:
1719 case CONTROL:
1720 case FPREG:
1721 case AINC:
1722 case ADEC:
1723 case IMMED:
1724 case REGLST:
1725 losing++;
1726 break;
1727 default:
1728 break;
1729 }
1730 break;
1731
1732 case ';':
1733 switch (opP->mode)
1734 {
1735 case AREG:
1736 case CONTROL:
1737 case FPREG:
1738 case REGLST:
1739 losing++;
1740 break;
1741 default:
1742 break;
1743 }
1744 break;
1745
1746 case '?':
1747 switch (opP->mode)
1748 {
1749 case AREG:
1750 case CONTROL:
1751 case FPREG:
1752 case AINC:
1753 case ADEC:
1754 case IMMED:
1755 case REGLST:
1756 losing++;
1757 break;
1758 case ABSL:
1759 break;
1760 default:
1761 if (opP->reg == PC || opP->reg == ZPC)
1762 losing++;
1763 break;
1764 }
1765 break;
1766
1767 case '@':
1768 switch (opP->mode)
1769 {
1770 case AREG:
1771 case CONTROL:
1772 case FPREG:
1773 case IMMED:
1774 case REGLST:
1775 losing++;
1776 break;
1777 default:
1778 break;
1779 }
1780 break;
1781
1782 case '~': /* For now! (JF FOO is this right?) */
1783 switch (opP->mode)
1784 {
1785 case DREG:
1786 case AREG:
1787 case CONTROL:
1788 case FPREG:
1789 case IMMED:
1790 case REGLST:
1791 losing++;
1792 break;
1793 case ABSL:
1794 break;
1795 default:
1796 if (opP->reg == PC
1797 || opP->reg == ZPC)
1798 losing++;
1799 break;
1800 }
1801 break;
1802
1803 case '3':
1804 if (opP->mode != CONTROL
1805 || (opP->reg != TT0 && opP->reg != TT1))
1806 losing++;
1807 break;
1808
1809 case 'A':
1810 if (opP->mode != AREG)
1811 losing++;
1812 break;
1813
1814 case 'a':
1815 if (opP->mode != AINDR)
1816 ++losing;
1817 break;
1818
fd99574b
NC		 1819 case '4':
1820 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1821 && (opP->mode != DISP
1822 || opP->reg < ADDR0
1823 || opP->reg > ADDR7))
1824 ++losing;
1825 break;
1826
252b5132
RH		 1827 case 'B': /* FOO */
1828 if (opP->mode != ABSL
1829 || (flag_long_jumps
1830 && strncmp (instring, "jbsr", 4) == 0))
1831 losing++;
1832 break;
1833
3e602632
NC		 1834 case 'b':
1835 switch (opP->mode)
1836 {
1837 case IMMED:
1838 case ABSL:
1839 case AREG:
1840 case FPREG:
1841 case CONTROL:
1842 case POST:
1843 case PRE:
1844 case REGLST:
1845 losing++;
1846 break;
1847 default:
1848 break;
1849 }
1850 break;
1851
252b5132
RH		 1852 case 'C':
1853 if (opP->mode != CONTROL || opP->reg != CCR)
1854 losing++;
1855 break;
1856
1857 case 'd':
1858 if (opP->mode != DISP
1859 || opP->reg < ADDR0
1860 || opP->reg > ADDR7)
1861 losing++;
1862 break;
1863
1864 case 'D':
1865 if (opP->mode != DREG)
1866 losing++;
1867 break;
1868
6da466c7
ILT		 1869 case 'E':
1870 if (opP->reg != ACC)
1871 losing++;
1872 break;
1873
fd99574b
NC		 1874 case 'e':
1875 if (opP->reg != ACC && opP->reg != ACC1
1876 && opP->reg != ACC2 && opP->reg != ACC3)
1877 losing++;
1878 break;
1879
252b5132
RH		 1880 case 'F':
1881 if (opP->mode != FPREG)
1882 losing++;
1883 break;
1884
6da466c7
ILT		 1885 case 'G':
1886 if (opP->reg != MACSR)
1887 losing++;
1888 break;
1889
fd99574b
NC		 1890 case 'g':
1891 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1892 losing++;
1893 break;
1894
6da466c7
ILT		 1895 case 'H':
1896 if (opP->reg != MASK)
1897 losing++;
1898 break;
1899
252b5132
RH		 1900 case 'I':
1901 if (opP->mode != CONTROL
1902 || opP->reg < COP0
1903 || opP->reg > COP7)
1904 losing++;
1905 break;
1906
fd99574b
NC		 1907 case 'i':
1908 if (opP->mode != LSH && opP->mode != RSH)
1909 losing++;
1910 break;
1911
252b5132
RH		 1912 case 'J':
1913 if (opP->mode != CONTROL
1914 || opP->reg < USP
0b2e31dc
NS		 1915 || opP->reg > last_movec_reg
1916 || !control_regs)
252b5132
RH		 1917 losing++;
1918 else
1919 {
1920 const enum m68k_register *rp;
0b2e31dc 1921
252b5132 1922 for (rp = control_regs; *rp; rp++)
78336706
NS		 1923 {
1924 if (*rp == opP->reg)
1925 break;
1926 /* In most CPUs RAMBAR refers to control reg
1927 c05 (RAMBAR1), but a few CPUs have it
1928 refer to c04 (RAMBAR0). */
1929 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1930 {
1931 opP->reg = RAMBAR_ALT;
1932 break;
1933 }
1934 }
252b5132
RH		 1935 if (*rp == 0)
1936 losing++;
1937 }
1938 break;
1939
1940 case 'k':
1941 if (opP->mode != IMMED)
1942 losing++;
1943 break;
1944
1945 case 'l':
1946 case 'L':
1947 if (opP->mode == DREG
1948 || opP->mode == AREG
1949 || opP->mode == FPREG)
1950 {
1951 if (s[1] == '8')
1952 losing++;
1953 else
1954 {
1955 switch (opP->mode)
1956 {
1957 case DREG:
1958 opP->mask = 1 << (opP->reg - DATA0);
1959 break;
1960 case AREG:
1961 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1962 break;
1963 case FPREG:
1964 opP->mask = 1 << (opP->reg - FP0 + 16);
1965 break;
1966 default:
1967 abort ();
1968 }
1969 opP->mode = REGLST;
1970 }
1971 }
1972 else if (opP->mode == CONTROL)
1973 {
1974 if (s[1] != '8')
1975 losing++;
1976 else
1977 {
1978 switch (opP->reg)
1979 {
1980 case FPI:
1981 opP->mask = 1 << 24;
1982 break;
1983 case FPS:
1984 opP->mask = 1 << 25;
1985 break;
1986 case FPC:
1987 opP->mask = 1 << 26;
1988 break;
1989 default:
1990 losing++;
1991 break;
1992 }
1993 opP->mode = REGLST;
1994 }
1995 }
1996 else if (opP->mode != REGLST)
1997 losing++;
1998 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1999 losing++;
2000 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2001 losing++;
2002 break;
2003
2004 case 'M':
2005 if (opP->mode != IMMED)
2006 losing++;
2007 else if (opP->disp.exp.X_op != O_constant
2008 || ! issbyte (opP->disp.exp.X_add_number))
2009 losing++;
2010 else if (! m68k_quick
2011 && instring[3] != 'q'
2012 && instring[4] != 'q')
2013 losing++;
2014 break;
2015
2016 case 'O':
2017 if (opP->mode != DREG
2018 && opP->mode != IMMED
2019 && opP->mode != ABSL)
2020 losing++;
2021 break;
2022
2023 case 'Q':
2024 if (opP->mode != IMMED)
2025 losing++;
2026 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2027 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 2028 losing++;
2029 else if (! m68k_quick
2030 && (strncmp (instring, "add", 3) == 0
2031 || strncmp (instring, "sub", 3) == 0)
2032 && instring[3] != 'q')
2033 losing++;
2034 break;
2035
2036 case 'R':
2037 if (opP->mode != DREG && opP->mode != AREG)
2038 losing++;
2039 break;
2040
2041 case 'r':
2042 if (opP->mode != AINDR
2043 && (opP->mode != BASE
2044 || (opP->reg != 0
2045 && opP->reg != ZADDR0)
2046 || opP->disp.exp.X_op != O_absent
2047 || ((opP->index.reg < DATA0
2048 || opP->index.reg > DATA7)
2049 && (opP->index.reg < ADDR0
2050 || opP->index.reg > ADDR7))
2051 || opP->index.size != SIZE_UNSPEC
2052 || opP->index.scale != 1))
2053 losing++;
2054 break;
2055
2056 case 's':
2057 if (opP->mode != CONTROL
2058 || ! (opP->reg == FPI
2059 || opP->reg == FPS
2060 || opP->reg == FPC))
2061 losing++;
2062 break;
2063
2064 case 'S':
2065 if (opP->mode != CONTROL || opP->reg != SR)
2066 losing++;
2067 break;
2068
2069 case 't':
2070 if (opP->mode != IMMED)
2071 losing++;
2072 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2073 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 2074 losing++;
2075 break;
2076
2077 case 'U':
2078 if (opP->mode != CONTROL || opP->reg != USP)
2079 losing++;
2080 break;
2081
3e602632
NC		 2082 case 'x':
2083 if (opP->mode != IMMED)
2084 losing++;
2085 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 2086 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2087 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 2088 losing++;
2089 break;
2090
afa2158f
NS		 2091 case 'j':
2092 if (opP->mode != IMMED)
2093 losing++;
2094 else if (opP->disp.exp.X_op != O_constant
2095 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2096 losing++;
2097 break;
2098
2099 case 'K':
2100 if (opP->mode != IMMED)
2101 losing++;
2102 else if (opP->disp.exp.X_op != O_constant
2103 || TRUNC (opP->disp.exp.X_add_number) > 511)
2104 losing++;
2105 break;
2106
252b5132
RH		 2107 /* JF these are out of order. We could put them
2108 in order if we were willing to put up with
2109 bunches of #ifdef m68851s in the code.
2110
2111 Don't forget that you need these operands
2112 to use 68030 MMU instructions. */
2113#ifndef NO_68851
36759679 2114 /* Memory addressing mode used by pflushr. */
252b5132
RH		 2115 case '|':
2116 if (opP->mode == CONTROL
2117 || opP->mode == FPREG
2118 || opP->mode == DREG
2119 || opP->mode == AREG
2120 || opP->mode == REGLST)
2121 losing++;
2122 /* We should accept immediate operands, but they
2123 supposedly have to be quad word, and we don't
2124 handle that. I would like to see what a Motorola
2125 assembler does before doing something here. */
2126 if (opP->mode == IMMED)
2127 losing++;
2128 break;
2129
2130 case 'f':
2131 if (opP->mode != CONTROL
2132 || (opP->reg != SFC && opP->reg != DFC))
2133 losing++;
2134 break;
2135
2136 case '0':
2137 if (opP->mode != CONTROL || opP->reg != TC)
2138 losing++;
2139 break;
2140
2141 case '1':
2142 if (opP->mode != CONTROL || opP->reg != AC)
2143 losing++;
2144 break;
2145
2146 case '2':
2147 if (opP->mode != CONTROL
2148 || (opP->reg != CAL
2149 && opP->reg != VAL
2150 && opP->reg != SCC))
2151 losing++;
2152 break;
2153
2154 case 'V':
2155 if (opP->mode != CONTROL
2156 || opP->reg != VAL)
2157 losing++;
2158 break;
2159
2160 case 'W':
2161 if (opP->mode != CONTROL
2162 || (opP->reg != DRP
2163 && opP->reg != SRP
2164 && opP->reg != CRP))
2165 losing++;
2166 break;
2167
3e602632
NC		 2168 case 'w':
2169 switch (opP->mode)
2170 {
2171 case IMMED:
2172 case ABSL:
2173 case AREG:
2174 case DREG:
2175 case FPREG:
2176 case CONTROL:
2177 case POST:
2178 case PRE:
2179 case REGLST:
2180 losing++;
2181 break;
2182 default:
2183 break;
2184 }
2185 break;
2186
252b5132
RH		 2187 case 'X':
2188 if (opP->mode != CONTROL
2189 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2190 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2191 losing++;
2192 break;
2193
2194 case 'Y':
2195 if (opP->mode != CONTROL || opP->reg != PSR)
2196 losing++;
2197 break;
2198
2199 case 'Z':
2200 if (opP->mode != CONTROL || opP->reg != PCSR)
2201 losing++;
2202 break;
2203#endif
2204 case 'c':
2205 if (opP->mode != CONTROL
2206 || (opP->reg != NC
2207 && opP->reg != IC
2208 && opP->reg != DC
2209 && opP->reg != BC))
36759679 2210 losing++;
252b5132
RH		 2211 break;
2212
2213 case '_':
2214 if (opP->mode != ABSL)
2215 ++losing;
2216 break;
2217
6da466c7
ILT		 2218 case 'u':
2219 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2220 losing++;
2221 /* FIXME: kludge instead of fixing parser:
2222 upper/lower registers are *not* CONTROL
92774660 2223 registers, but ordinary ones. */
6da466c7
ILT		 2224 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2225 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2226 opP->mode = DREG;
2227 else
2228 opP->mode = AREG;
2229 break;
2230
3e602632
NC		 2231 case 'y':
2232 if (!(opP->mode == AINDR
31302357
AS		 2233 || (opP->mode == DISP
2234 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2235 losing++;
2236 break;
2237
2238 case 'z':
2239 if (!(opP->mode == AINDR || opP->mode == DISP))
2240 losing++;
2241 break;
2242
252b5132
RH		 2243 default:
2244 abort ();
36759679 2245 }
252b5132
RH		 2246
2247 if (losing)
2248 break;
36759679 2249 }
03b13e59
NC		 2250
2251 /* Since we have found the correct instruction, copy
2252 in the modifications that we may have made. */
2253 if (!losing)
2254 for (i = 0; i < opsfound; i++)
2255 the_ins.operands[i] = operands_backup[i];
36759679 2256 }
252b5132
RH		 2257
2258 if (!losing)
36759679 2259 break;
252b5132
RH		 2260
2261 opcode = opcode->m_next;
2262
2263 if (!opcode)
2264 {
2265 if (ok_arch
2266 && !(ok_arch & current_architecture))
2267 {
6d89cc8f
NS		 2268 const struct m68k_cpu *cpu;
2269 int any = 0;
2270 size_t space = 400;
2271 char *buf = xmalloc (space + 1);
2272 size_t len;
2273 int paren = 1;
2274
2275 the_ins.error = buf;
2276 /* Make sure there's a NUL at the end of the buffer -- strncpy
b2f58c0c 2277 won't write one when it runs out of buffer. */
6d89cc8f
NS		 2278 buf[space] = 0;
2279#define APPEND(STRING) \
2280 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2281
2282 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2283 switch (ok_arch)
2284 {
6b6e92f4 2285 case mcfisa_a:
b2f58c0c 2286 APPEND ("ColdFire ISA_A");
6b6e92f4
NC		 2287 break;
2288 case mcfhwdiv:
b2f58c0c
NC		 2289 APPEND ("ColdFire ");
2290 APPEND (_("hardware divide"));
6b6e92f4
NC		 2291 break;
2292 case mcfisa_aa:
b2f58c0c 2293 APPEND ("ColdFire ISA_A+");
6b6e92f4
NC		 2294 break;
2295 case mcfisa_b:
b2f58c0c 2296 APPEND ("ColdFire ISA_B");
6b6e92f4 2297 break;
8d100c32 2298 case mcfisa_c:
b2f58c0c 2299 APPEND ("ColdFire ISA_C");
8d100c32 2300 break;
3e602632 2301 case cfloat:
b2f58c0c 2302 APPEND ("ColdFire fpu");
3e602632 2303 break;
252b5132 2304 case mfloat:
b2f58c0c 2305 APPEND ("M68K fpu");
252b5132
RH		 2306 break;
2307 case mmmu:
b2f58c0c 2308 APPEND ("M68K mmu");
252b5132
RH		 2309 break;
2310 case m68020up:
b2f58c0c
NC		 2311 APPEND ("68020 ");
2312 APPEND (_("or higher"));
252b5132
RH		 2313 break;
2314 case m68000up:
b2f58c0c
NC		 2315 APPEND ("68000 ");
2316 APPEND (_("or higher"));
252b5132
RH		 2317 break;
2318 case m68010up:
b2f58c0c
NC		 2319 APPEND ("68010 ");
2320 APPEND (_("or higher"));
252b5132
RH		 2321 break;
2322 default:
6d89cc8f
NS		 2323 paren = 0;
2324 }
2325 if (paren)
2326 APPEND (" (");
6b6e92f4 2327
6d89cc8f
NS		 2328 for (cpu = m68k_cpus; cpu->name; cpu++)
2329 if (!cpu->alias && (cpu->arch & ok_arch))
2330 {
2331 const struct m68k_cpu *alias;
869ddf2a
NS		 2332 int seen_master = 0;
2333
6d89cc8f
NS		 2334 if (any)
2335 APPEND (", ");
2336 any = 0;
2337 APPEND (cpu->name);
869ddf2a
NS		 2338 for (alias = cpu; alias != m68k_cpus; alias--)
2339 if (alias[-1].alias >= 0)
2340 break;
2341 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2342 {
869ddf2a
NS		 2343 if (!alias->alias)
2344 seen_master = 1;
2345 else
2346 {
2347 if (any)
2348 APPEND (", ");
2349 else
2350 APPEND (" [");
2351 APPEND (alias->name);
2352 any = 1;
2353 }
6d89cc8f 2354 }
869ddf2a
NS		 2355 if (any)
2356 APPEND ("]");
6d89cc8f 2357 any = 1;
252b5132 2358 }
6d89cc8f
NS		 2359 if (paren)
2360 APPEND (")");
2361#undef APPEND
2362 if (!space)
2363 {
b2f58c0c 2364 /* We ran out of space, so replace the end of the list
6d89cc8f
NS		 2365 with ellipsis. */
2366 buf -= 4;
2367 while (*buf != ' ')
2368 buf--;
2369 strcpy (buf, " ...");
252b5132 2370 }
252b5132
RH		 2371 }
2372 else
2373 the_ins.error = _("operands mismatch");
2374 return;
36759679 2375 }
252b5132
RH		 2376
2377 losing = 0;
2378 }
2379
36759679 2380 /* Now assemble it. */
252b5132
RH		 2381 the_ins.args = opcode->m_operands;
2382 the_ins.numargs = opcode->m_opnum;
2383 the_ins.numo = opcode->m_codenum;
2384 the_ins.opcode[0] = getone (opcode);
2385 the_ins.opcode[1] = gettwo (opcode);
2386
2387 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2388 {
9a2e615a 2389 int have_disp = 0;
cac27205 2390 int use_pl = 0;
9a2e615a 2391
252b5132 2392 /* This switch is a doozy.
31302357 2393 Watch the first step; its a big one! */
252b5132
RH		 2394 switch (s[0])
2395 {
2396
2397 case '*':
2398 case '~':
2399 case '%':
2400 case ';':
2401 case '@':
2402 case '!':
2403 case '&':
2404 case '$':
2405 case '?':
2406 case '/':
2407 case '<':
2408 case '>':
3e602632 2409 case 'b':
252b5132
RH		 2410 case 'm':
2411 case 'n':
2412 case 'o':
2413 case 'p':
2414 case 'q':
2415 case 'v':
3e602632
NC		 2416 case 'w':
2417 case 'y':
2418 case 'z':
fd99574b 2419 case '4':
252b5132
RH		 2420#ifndef NO_68851
2421 case '|':
2422#endif
2423 switch (opP->mode)
2424 {
2425 case IMMED:
2426 tmpreg = 0x3c; /* 7.4 */
2427 if (strchr ("bwl", s[1]))
3e602632 2428 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2429 else
2430 nextword = get_num (&opP->disp, 0);
2431 if (isvar (&opP->disp))
2432 add_fix (s[1], &opP->disp, 0, 0);
2433 switch (s[1])
2434 {
2435 case 'b':
2436 if (!isbyte (nextword))
2437 opP->error = _("operand out of range");
2438 addword (nextword);
2439 baseo = 0;
2440 break;
2441 case 'w':
2442 if (!isword (nextword))
2443 opP->error = _("operand out of range");
2444 addword (nextword);
2445 baseo = 0;
2446 break;
2447 case 'W':
2448 if (!issword (nextword))
2449 opP->error = _("operand out of range");
2450 addword (nextword);
2451 baseo = 0;
2452 break;
2453 case 'l':
2454 addword (nextword >> 16);
2455 addword (nextword);
2456 baseo = 0;
2457 break;
2458
2459 case 'f':
2460 baseo = 2;
2461 outro = 8;
2462 break;
2463 case 'F':
2464 baseo = 4;
2465 outro = 11;
2466 break;
2467 case 'x':
2468 baseo = 6;
2469 outro = 15;
2470 break;
2471 case 'p':
2472 baseo = 6;
2473 outro = -1;
2474 break;
2475 default:
2476 abort ();
2477 }
2478 if (!baseo)
2479 break;
2480
36759679 2481 /* We gotta put out some float. */
252b5132
RH		 2482 if (op (&opP->disp) != O_big)
2483 {
2484 valueT val;
2485 int gencnt;
2486
2487 /* Can other cases happen here? */
2488 if (op (&opP->disp) != O_constant)
2489 abort ();
2490
2491 val = (valueT) offs (&opP->disp);
2492 gencnt = 0;
2493 do
2494 {
2495 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2496 val >>= LITTLENUM_NUMBER_OF_BITS;
2497 ++gencnt;
2498 }
2499 while (val != 0);
2500 offs (&opP->disp) = gencnt;
2501 }
2502 if (offs (&opP->disp) > 0)
2503 {
2504 if (offs (&opP->disp) > baseo)
2505 {
2506 as_warn (_("Bignum too big for %c format; truncated"),
2507 s[1]);
2508 offs (&opP->disp) = baseo;
2509 }
2510 baseo -= offs (&opP->disp);
2511 while (baseo--)
2512 addword (0);
2513 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2514 offs (&opP->disp)--;
2515 --wordp)
2516 addword (*wordp);
2517 break;
2518 }
2519 gen_to_words (words, baseo, (long) outro);
2520 for (wordp = words; baseo--; wordp++)
2521 addword (*wordp);
2522 break;
2523 case DREG:
2524 tmpreg = opP->reg - DATA; /* 0.dreg */
2525 break;
2526 case AREG:
2527 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2528 break;
2529 case AINDR:
2530 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2531 break;
2532 case ADEC:
2533 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2534 break;
2535 case AINC:
2536 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2537 break;
2538 case DISP:
2539
3e602632 2540 nextword = get_num (&opP->disp, 90);
252b5132 2541
580b9172
NC		 2542 /* Convert mode 5 addressing with a zero offset into
2543 mode 2 addressing to reduce the instruction size by a
2544 word. */
2545 if (! isvar (&opP->disp)
2546 && (nextword == 0)
2547 && (opP->disp.size == SIZE_UNSPEC)
2548 && (opP->reg >= ADDR0)
2549 && (opP->reg <= ADDR7))
2550 {
2551 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2552 break;
2553 }
2554
252b5132
RH		 2555 if (opP->reg == PC
2556 && ! isvar (&opP->disp)
2557 && m68k_abspcadd)
2558 {
2559 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2560 opP->disp.exp.X_add_symbol =
2561 section_symbol (absolute_section);
252b5132
RH		 2562 }
2563
36759679 2564 /* Force into index mode. Hope this works. */
252b5132
RH		 2565
2566 /* We do the first bit for 32-bit displacements, and the
2567 second bit for 16 bit ones. It is possible that we
2568 should make the default be WORD instead of LONG, but
2569 I think that'd break GCC, so we put up with a little
2570 inefficiency for the sake of working output. */
2571
2572 if (!issword (nextword)
2573 || (isvar (&opP->disp)
2574 && ((opP->disp.size == SIZE_UNSPEC
2575 && flag_short_refs == 0
2576 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2577 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2578 || opP->disp.size == SIZE_LONG)))
2579 {
2580 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2581 || arch_coldfire_p (current_architecture))
252b5132
RH		 2582 opP->error =
2583 _("displacement too large for this architecture; needs 68020 or higher");
2584 if (opP->reg == PC)
2585 tmpreg = 0x3B; /* 7.3 */
2586 else
2587 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2588 if (isvar (&opP->disp))
2589 {
2590 if (opP->reg == PC)
2591 {
2592 if (opP->disp.size == SIZE_LONG
2593#ifdef OBJ_ELF
2594 /* If the displacement needs pic
2595 relocation it cannot be relaxed. */
2596 || opP->disp.pic_reloc != pic_none
2597#endif
2598 )
2599 {
2600 addword (0x0170);
2601 add_fix ('l', &opP->disp, 1, 2);
2602 }
2603 else
2604 {
2605 add_frag (adds (&opP->disp),
bd17c2c3 2606 SEXT (offs (&opP->disp)),
151337e8 2607 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2608 break;
2609 }
2610 }
2611 else
2612 {
2613 addword (0x0170);
2614 add_fix ('l', &opP->disp, 0, 0);
2615 }
2616 }
2617 else
2618 addword (0x0170);
2619 addword (nextword >> 16);
2620 }
2621 else
2622 {
2623 if (opP->reg == PC)
2624 tmpreg = 0x3A; /* 7.2 */
2625 else
2626 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2627
2628 if (isvar (&opP->disp))
2629 {
2630 if (opP->reg == PC)
2631 {
2632 add_fix ('w', &opP->disp, 1, 0);
2633 }
2634 else
2635 add_fix ('w', &opP->disp, 0, 0);
2636 }
2637 }
2638 addword (nextword);
2639 break;
2640
2641 case POST:
2642 case PRE:
2643 case BASE:
2644 nextword = 0;
3e602632 2645 baseo = get_num (&opP->disp, 90);
252b5132 2646 if (opP->mode == POST || opP->mode == PRE)
3e602632 2647 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2648 /* Figure out the `addressing mode'.
2649 Also turn on the BASE_DISABLE bit, if needed. */
2650 if (opP->reg == PC || opP->reg == ZPC)
2651 {
2652 tmpreg = 0x3b; /* 7.3 */
2653 if (opP->reg == ZPC)
2654 nextword |= 0x80;
2655 }
2656 else if (opP->reg == 0)
2657 {
2658 nextword |= 0x80;
2659 tmpreg = 0x30; /* 6.garbage */
2660 }
2661 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2662 {
2663 nextword |= 0x80;
2664 tmpreg = 0x30 + opP->reg - ZADDR0;
2665 }
2666 else
2667 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2668
2669 siz1 = opP->disp.size;
2670 if (opP->mode == POST || opP->mode == PRE)
2671 siz2 = opP->odisp.size;
2672 else
2673 siz2 = SIZE_UNSPEC;
2674
36759679 2675 /* Index register stuff. */
252b5132
RH		 2676 if (opP->index.reg != 0
2677 && opP->index.reg >= DATA
2678 && opP->index.reg <= ADDR7)
2679 {
2680 nextword |= (opP->index.reg - DATA) << 12;
2681
2682 if (opP->index.size == SIZE_LONG
2683 || (opP->index.size == SIZE_UNSPEC
2684 && m68k_index_width_default == SIZE_LONG))
2685 nextword |= 0x800;
2686
92774660 2687 if ((opP->index.scale != 1
252b5132 2688 && cpu_of_arch (current_architecture) < m68020)
92774660 2689 || (opP->index.scale == 8
3e602632 2690 && (arch_coldfire_p (current_architecture)
6b6e92f4 2691 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2692 {
2693 opP->error =
2694 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2695 }
2696
6da466c7
ILT		 2697 if (arch_coldfire_p (current_architecture)
2698 && opP->index.size == SIZE_WORD)
2699 opP->error = _("invalid index size for coldfire");
2700
252b5132
RH		 2701 switch (opP->index.scale)
2702 {
2703 case 1:
2704 break;
2705 case 2:
2706 nextword |= 0x200;
2707 break;
2708 case 4:
2709 nextword |= 0x400;
2710 break;
2711 case 8:
2712 nextword |= 0x600;
2713 break;
2714 default:
2715 abort ();
2716 }
2717 /* IF its simple,
2718 GET US OUT OF HERE! */
2719
2720 /* Must be INDEX, with an index register. Address
2721 register cannot be ZERO-PC, and either :b was
2722 forced, or we know it will fit. For a 68000 or
2723 68010, force this mode anyways, because the
2724 larger modes aren't supported. */
2725 if (opP->mode == BASE
2726 && ((opP->reg >= ADDR0
2727 && opP->reg <= ADDR7)
2728 || opP->reg == PC))
2729 {
2730 if (siz1 == SIZE_BYTE
2731 || cpu_of_arch (current_architecture) < m68020
6da466c7 2732 || arch_coldfire_p (current_architecture)
252b5132
RH		 2733 || (siz1 == SIZE_UNSPEC
2734 && ! isvar (&opP->disp)
2735 && issbyte (baseo)))
2736 {
2737 nextword += baseo & 0xff;
2738 addword (nextword);
2739 if (isvar (&opP->disp))
2740 {
2741 /* Do a byte relocation. If it doesn't
2742 fit (possible on m68000) let the
2743 fixup processing complain later. */
2744 if (opP->reg == PC)
2745 add_fix ('B', &opP->disp, 1, 1);
2746 else
2747 add_fix ('B', &opP->disp, 0, 0);
2748 }
2749 else if (siz1 != SIZE_BYTE)
2750 {
2751 if (siz1 != SIZE_UNSPEC)
2752 as_warn (_("Forcing byte displacement"));
2753 if (! issbyte (baseo))
2754 opP->error = _("byte displacement out of range");
2755 }
2756
2757 break;
2758 }
2759 else if (siz1 == SIZE_UNSPEC
2760 && opP->reg == PC
2761 && isvar (&opP->disp)
2762 && subs (&opP->disp) == NULL
2763#ifdef OBJ_ELF
2764 /* If the displacement needs pic
2765 relocation it cannot be relaxed. */
2766 && opP->disp.pic_reloc == pic_none
2767#endif
2768 )
2769 {
2770 /* The code in md_convert_frag_1 needs to be
2771 able to adjust nextword. Call frag_grow
2772 to ensure that we have enough space in
2773 the frag obstack to make all the bytes
2774 contiguous. */
2775 frag_grow (14);
8a104df9
KH		 2776 nextword += baseo & 0xff;
2777 addword (nextword);
bd17c2c3
AM		 2778 add_frag (adds (&opP->disp),
2779 SEXT (offs (&opP->disp)),
8a104df9 2780 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2781
2782 break;
8a104df9 2783 }
252b5132
RH		 2784 }
2785 }
2786 else
2787 {
36759679 2788 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2789 if (opP->index.reg >= ZDATA0
2790 && opP->index.reg <= ZDATA7)
2791 nextword |= (opP->index.reg - ZDATA0) << 12;
2792 else if (opP->index.reg >= ZADDR0
2793 || opP->index.reg <= ZADDR7)
2794 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2795 }
2796
2797 /* It isn't simple. */
2798
2799 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2800 || arch_coldfire_p (current_architecture))
252b5132
RH		 2801 opP->error =
2802 _("invalid operand mode for this architecture; needs 68020 or higher");
2803
2804 nextword |= 0x100;
2805 /* If the guy specified a width, we assume that it is
2806 wide enough. Maybe it isn't. If so, we lose. */
2807 switch (siz1)
2808 {
2809 case SIZE_UNSPEC:
2810 if (isvar (&opP->disp)
2811 ? m68k_rel32
2812 : ! issword (baseo))
2813 {
2814 siz1 = SIZE_LONG;
2815 nextword |= 0x30;
2816 }
2817 else if (! isvar (&opP->disp) && baseo == 0)
2818 nextword |= 0x10;
2819 else
2820 {
2821 nextword |= 0x20;
2822 siz1 = SIZE_WORD;
2823 }
2824 break;
2825 case SIZE_BYTE:
2826 as_warn (_(":b not permitted; defaulting to :w"));
2827 /* Fall through. */
2828 case SIZE_WORD:
2829 nextword |= 0x20;
2830 break;
2831 case SIZE_LONG:
2832 nextword |= 0x30;
2833 break;
2834 }
2835
67c1ffbe 2836 /* Figure out inner displacement stuff. */
252b5132
RH		 2837 if (opP->mode == POST || opP->mode == PRE)
2838 {
2839 if (cpu_of_arch (current_architecture) & cpu32)
2840 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2841 switch (siz2)
2842 {
2843 case SIZE_UNSPEC:
2844 if (isvar (&opP->odisp)
2845 ? m68k_rel32
2846 : ! issword (outro))
2847 {
2848 siz2 = SIZE_LONG;
2849 nextword |= 0x3;
2850 }
2851 else if (! isvar (&opP->odisp) && outro == 0)
2852 nextword |= 0x1;
2853 else
2854 {
2855 nextword |= 0x2;
2856 siz2 = SIZE_WORD;
2857 }
2858 break;
2859 case 1:
2860 as_warn (_(":b not permitted; defaulting to :w"));
2861 /* Fall through. */
2862 case 2:
2863 nextword |= 0x2;
2864 break;
2865 case 3:
2866 nextword |= 0x3;
2867 break;
2868 }
2869 if (opP->mode == POST
2870 && (nextword & 0x40) == 0)
2871 nextword |= 0x04;
2872 }
2873 addword (nextword);
2874
2875 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2876 {
2877 if (opP->reg == PC || opP->reg == ZPC)
2878 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2879 else
2880 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2881 }
2882 if (siz1 == SIZE_LONG)
2883 addword (baseo >> 16);
2884 if (siz1 != SIZE_UNSPEC)
2885 addword (baseo);
2886
2887 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2888 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2889 if (siz2 == SIZE_LONG)
2890 addword (outro >> 16);
2891 if (siz2 != SIZE_UNSPEC)
2892 addword (outro);
2893
2894 break;
2895
2896 case ABSL:
3e602632 2897 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2898 switch (opP->disp.size)
2899 {
2900 default:
2901 abort ();
2902 case SIZE_UNSPEC:
2903 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2904 {
2905 tmpreg = 0x38; /* 7.0 */
2906 addword (nextword);
2907 break;
2908 }
252b5132
RH		 2909 if (isvar (&opP->disp)
2910 && !subs (&opP->disp)
2911 && adds (&opP->disp)
2912#ifdef OBJ_ELF
2913 /* If the displacement needs pic relocation it
2914 cannot be relaxed. */
2915 && opP->disp.pic_reloc == pic_none
2916#endif
252b5132
RH		 2917 && !flag_long_jumps
2918 && !strchr ("~%&$?", s[0]))
2919 {
2920 tmpreg = 0x3A; /* 7.2 */
2921 add_frag (adds (&opP->disp),
bd17c2c3 2922 SEXT (offs (&opP->disp)),
151337e8 2923 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2924 break;
2925 }
36759679 2926 /* Fall through into long. */
252b5132
RH		 2927 case SIZE_LONG:
2928 if (isvar (&opP->disp))
2929 add_fix ('l', &opP->disp, 0, 0);
2930
2931 tmpreg = 0x39;/* 7.1 mode */
2932 addword (nextword >> 16);
2933 addword (nextword);
2934 break;
2935
2936 case SIZE_BYTE:
2937 as_bad (_("unsupported byte value; use a different suffix"));
2938 /* Fall through. */
36759679
NC		 2939
2940 case SIZE_WORD:
252b5132
RH		 2941 if (isvar (&opP->disp))
2942 add_fix ('w', &opP->disp, 0, 0);
2943
2944 tmpreg = 0x38;/* 7.0 mode */
2945 addword (nextword);
2946 break;
2947 }
2948 break;
2949 case CONTROL:
2950 case FPREG:
2951 default:
2952 as_bad (_("unknown/incorrect operand"));
bc805888 2953 /* abort (); */
252b5132 2954 }
fd99574b
NC		 2955
2956 /* If s[0] is '4', then this is for the mac instructions
2957 that can have a trailing_ampersand set. If so, set 0x100
2958 bit on tmpreg so install_gen_operand can check for it and
2959 set the appropriate bit (word2, bit 5). */
2960 if (s[0] == '4')
2961 {
2962 if (opP->trailing_ampersand)
2963 tmpreg |= 0x100;
2964 }
252b5132
RH		 2965 install_gen_operand (s[1], tmpreg);
2966 break;
2967
2968 case '#':
2969 case '^':
2970 switch (s[1])
2971 { /* JF: I hate floating point! */
2972 case 'j':
2973 tmpreg = 70;
2974 break;
2975 case '8':
2976 tmpreg = 20;
2977 break;
2978 case 'C':
2979 tmpreg = 50;
2980 break;
2981 case '3':
2982 default:
3e602632 2983 tmpreg = 90;
252b5132
RH		 2984 break;
2985 }
2986 tmpreg = get_num (&opP->disp, tmpreg);
2987 if (isvar (&opP->disp))
2988 add_fix (s[1], &opP->disp, 0, 0);
2989 switch (s[1])
2990 {
2991 case 'b': /* Danger: These do no check for
2992 certain types of overflow.
2993 user beware! */
2994 if (!isbyte (tmpreg))
2995 opP->error = _("out of range");
2996 insop (tmpreg, opcode);
2997 if (isvar (&opP->disp))
2998 the_ins.reloc[the_ins.nrel - 1].n =
2999 (opcode->m_codenum) * 2 + 1;
3000 break;
3001 case 'B':
3002 if (!issbyte (tmpreg))
3003 opP->error = _("out of range");
3004 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3005 if (isvar (&opP->disp))
3006 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3007 break;
3008 case 'w':
3009 if (!isword (tmpreg))
3010 opP->error = _("out of range");
3011 insop (tmpreg, opcode);
3012 if (isvar (&opP->disp))
3013 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3014 break;
3015 case 'W':
3016 if (!issword (tmpreg))
3017 opP->error = _("out of range");
3018 insop (tmpreg, opcode);
3019 if (isvar (&opP->disp))
3020 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3021 break;
3022 case 'l':
3023 /* Because of the way insop works, we put these two out
3024 backwards. */
3025 insop (tmpreg, opcode);
3026 insop (tmpreg >> 16, opcode);
3027 if (isvar (&opP->disp))
3028 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3029 break;
3030 case '3':
3031 tmpreg &= 0xFF;
3032 case '8':
3033 case 'C':
3034 case 'j':
3035 install_operand (s[1], tmpreg);
3036 break;
3037 default:
3038 abort ();
3039 }
3040 break;
3041
3042 case '+':
3043 case '-':
3044 case 'A':
3045 case 'a':
3046 install_operand (s[1], opP->reg - ADDR);
3047 break;
3048
3049 case 'B':
3e602632 3050 tmpreg = get_num (&opP->disp, 90);
9a2e615a 3051
252b5132
RH		 3052 switch (s[1])
3053 {
3054 case 'B':
8390138c 3055 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 3056 break;
3057 case 'W':
3058 add_fix ('w', &opP->disp, 1, 0);
3059 addword (0);
3060 break;
3061 case 'L':
3062 long_branch:
151337e8 3063 the_ins.opcode[0] |= 0xff;
252b5132
RH		 3064 add_fix ('l', &opP->disp, 1, 0);
3065 addword (0);
3066 addword (0);
3067 break;
9a2e615a
NS		 3068 case 'g': /* Conditional branch */
3069 have_disp = HAVE_LONG_CALL (current_architecture);
3070 goto var_branch;
3071
3072 case 'b': /* Unconditional branch */
3073 have_disp = HAVE_LONG_BRANCH (current_architecture);
cac27205 3074 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
9a2e615a
NS		 3075 goto var_branch;
3076
3077 case 's': /* Unconditional subroutine */
3078 have_disp = HAVE_LONG_CALL (current_architecture);
3079
3080 var_branch:
3081 if (subs (&opP->disp) /* We can't relax it. */
252b5132 3082#ifdef OBJ_ELF
9a2e615a
NS		 3083 /* If the displacement needs pic relocation it cannot be
3084 relaxed. */
3085 || opP->disp.pic_reloc != pic_none
252b5132 3086#endif
9a2e615a
NS		 3087 || 0)
3088 {
3089 if (!have_disp)
3090 as_warn (_("Can't use long branches on this architecture"));
3091 goto long_branch;
3092 }
3093
252b5132 3094 /* This could either be a symbol, or an absolute
151337e8
NC		 3095 address. If it's an absolute address, turn it into
3096 an absolute jump right here and keep it out of the
3097 relaxer. */
3098 if (adds (&opP->disp) == 0)
3099 {
3100 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 3101 the_ins.opcode[0] = 0x4EF9;
151337e8 3102 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 3103 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 3104 else /* jCC */
3105 {
3106 the_ins.opcode[0] ^= 0x0100;
3107 the_ins.opcode[0] |= 0x0006;
18566f55 3108 addword (0x4EF9);
151337e8
NC		 3109 }
3110 add_fix ('l', &opP->disp, 0, 0);
3111 addword (0);
3112 addword (0);
3113 break;
3114 }
3115
3116 /* Now we know it's going into the relaxer. Now figure
3117 out which mode. We try in this order of preference:
3118 long branch, absolute jump, byte/word branches only. */
9a2e615a 3119 if (have_disp)
bd17c2c3
AM		 3120 add_frag (adds (&opP->disp),
3121 SEXT (offs (&opP->disp)),
151337e8
NC		 3122 TAB (BRANCHBWL, SZ_UNDEF));
3123 else if (! flag_keep_pcrel)
3124 {
3125 if ((the_ins.opcode[0] == 0x6000)
3126 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 3127 add_frag (adds (&opP->disp),
3128 SEXT (offs (&opP->disp)),
151337e8
NC		 3129 TAB (BRABSJUNC, SZ_UNDEF));
3130 else
bd17c2c3
AM		 3131 add_frag (adds (&opP->disp),
3132 SEXT (offs (&opP->disp)),
151337e8
NC		 3133 TAB (BRABSJCOND, SZ_UNDEF));
3134 }
252b5132 3135 else
bd17c2c3
AM		 3136 add_frag (adds (&opP->disp),
3137 SEXT (offs (&opP->disp)),
cac27205
NC		 3138 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3139 : TAB (BRANCHBW, SZ_UNDEF)));
252b5132
RH		 3140 break;
3141 case 'w':
3142 if (isvar (&opP->disp))
3143 {
151337e8
NC		 3144 /* Check for DBcc instructions. We can relax them,
3145 but only if we have long branches and/or absolute
3146 jumps. */
3147 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3148 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3149 || ! flag_keep_pcrel))
252b5132 3150 {
151337e8 3151 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3152 add_frag (adds (&opP->disp),
3153 SEXT (offs (&opP->disp)),
151337e8
NC		 3154 TAB (DBCCLBR, SZ_UNDEF));
3155 else
bd17c2c3
AM		 3156 add_frag (adds (&opP->disp),
3157 SEXT (offs (&opP->disp)),
151337e8 3158 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3159 break;
3160 }
252b5132
RH		 3161 add_fix ('w', &opP->disp, 1, 0);
3162 }
3163 addword (0);
3164 break;
36759679 3165 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3166 add_fix ('l', &opP->disp, 1, 0);
3167 addword (0);
3168 addword (0);
3169 break;
36759679 3170 case 'c': /* Var size Coprocesssor branches. */
151337e8 3171 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3172 {
252b5132
RH		 3173 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3174 add_fix ('l', &opP->disp, 1, 0);
3175 addword (0);
3176 addword (0);
3177 }
151337e8 3178 else
bd17c2c3
AM		 3179 add_frag (adds (&opP->disp),
3180 SEXT (offs (&opP->disp)),
151337e8 3181 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3182 break;
3183 default:
3184 abort ();
3185 }
3186 break;
3187
36759679 3188 case 'C': /* Ignore it. */
252b5132
RH		 3189 break;
3190
36759679 3191 case 'd': /* JF this is a kludge. */
252b5132 3192 install_operand ('s', opP->reg - ADDR);
3e602632 3193 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3194 if (!issword (tmpreg))
3195 {
3196 as_warn (_("Expression out of range, using 0"));
3197 tmpreg = 0;
3198 }
3199 addword (tmpreg);
3200 break;
3201
3202 case 'D':
3203 install_operand (s[1], opP->reg - DATA);
3204 break;
3205
fd99574b
NC		 3206 case 'e': /* EMAC ACCx, reg/reg. */
3207 install_operand (s[1], opP->reg - ACC);
3208 break;
3209
36759679 3210 case 'E': /* Ignore it. */
6da466c7
ILT		 3211 break;
3212
252b5132
RH		 3213 case 'F':
3214 install_operand (s[1], opP->reg - FP0);
3215 break;
3216
fd99574b
NC		 3217 case 'g': /* EMAC ACCEXTx. */
3218 install_operand (s[1], opP->reg - ACCEXT01);
3219 break;
3220
36759679 3221 case 'G': /* Ignore it. */
6da466c7
ILT		 3222 case 'H':
3223 break;
3224
252b5132
RH		 3225 case 'I':
3226 tmpreg = opP->reg - COP0;
3227 install_operand (s[1], tmpreg);
3228 break;
3229
fd99574b
NC		 3230 case 'i': /* MAC/EMAC scale factor. */
3231 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3232 break;
3233
36759679 3234 case 'J': /* JF foo. */
252b5132
RH		 3235 switch (opP->reg)
3236 {
3237 case SFC:
3238 tmpreg = 0x000;
3239 break;
3240 case DFC:
3241 tmpreg = 0x001;
3242 break;
3243 case CACR:
3244 tmpreg = 0x002;
3245 break;
3246 case TC:
a8e24a56 3247 case ASID:
252b5132
RH		 3248 tmpreg = 0x003;
3249 break;
3e602632 3250 case ACR0:
252b5132
RH		 3251 case ITT0:
3252 tmpreg = 0x004;
3253 break;
3e602632 3254 case ACR1:
252b5132
RH		 3255 case ITT1:
3256 tmpreg = 0x005;
3257 break;
3e602632 3258 case ACR2:
252b5132
RH		 3259 case DTT0:
3260 tmpreg = 0x006;
3261 break;
3e602632 3262 case ACR3:
252b5132
RH		 3263 case DTT1:
3264 tmpreg = 0x007;
3265 break;
3266 case BUSCR:
a8e24a56 3267 case MMUBAR:
252b5132
RH		 3268 tmpreg = 0x008;
3269 break;
3270
3271 case USP:
3272 tmpreg = 0x800;
3273 break;
3274 case VBR:
3275 tmpreg = 0x801;
3276 break;
3277 case CAAR:
3278 tmpreg = 0x802;
3279 break;
3280 case MSP:
3281 tmpreg = 0x803;
3282 break;
3283 case ISP:
3284 tmpreg = 0x804;
3285 break;
3286 case MMUSR:
3287 tmpreg = 0x805;
3288 break;
3289 case URP:
3290 tmpreg = 0x806;
3291 break;
3292 case SRP:
3293 tmpreg = 0x807;
3294 break;
3295 case PCR:
3296 tmpreg = 0x808;
3297 break;
3298 case ROMBAR:
a8e24a56 3299 case ROMBAR0:
252b5132
RH		 3300 tmpreg = 0xC00;
3301 break;
3e602632
NC		 3302 case ROMBAR1:
3303 tmpreg = 0xC01;
3304 break;
3305 case FLASHBAR:
252b5132 3306 case RAMBAR0:
78336706 3307 case RAMBAR_ALT:
252b5132
RH		 3308 tmpreg = 0xC04;
3309 break;
3e602632 3310 case RAMBAR:
252b5132
RH		 3311 case RAMBAR1:
3312 tmpreg = 0xC05;
3313 break;
3e602632
NC		 3314 case MPCR:
3315 tmpreg = 0xC0C;
3316 break;
3317 case EDRAMBAR:
3318 tmpreg = 0xC0D;
3319 break;
3320 case MBAR0:
e80e0390 3321 case MBAR2:
3e602632
NC		 3322 case SECMBAR:
3323 tmpreg = 0xC0E;
3324 break;
3325 case MBAR1:
252b5132
RH		 3326 case MBAR:
3327 tmpreg = 0xC0F;
3328 break;
3e602632
NC		 3329 case PCR1U0:
3330 tmpreg = 0xD02;
3331 break;
3332 case PCR1L0:
3333 tmpreg = 0xD03;
3334 break;
3335 case PCR2U0:
3336 tmpreg = 0xD04;
3337 break;
3338 case PCR2L0:
3339 tmpreg = 0xD05;
3340 break;
3341 case PCR3U0:
3342 tmpreg = 0xD06;
3343 break;
3344 case PCR3L0:
3345 tmpreg = 0xD07;
3346 break;
3347 case PCR1L1:
3348 tmpreg = 0xD0A;
3349 break;
3350 case PCR1U1:
3351 tmpreg = 0xD0B;
3352 break;
3353 case PCR2L1:
3354 tmpreg = 0xD0C;
3355 break;
3356 case PCR2U1:
3357 tmpreg = 0xD0D;
3358 break;
3359 case PCR3L1:
3360 tmpreg = 0xD0E;
3361 break;
3362 case PCR3U1:
3363 tmpreg = 0xD0F;
3364 break;
f7ec513b
KH		 3365 case CAC:
3366 tmpreg = 0xFFE;
3367 break;
d0fa1372 3368 case MBO:
f7ec513b
KH		 3369 tmpreg = 0xFFF;
3370 break;
252b5132
RH		 3371 default:
3372 abort ();
3373 }
3374 install_operand (s[1], tmpreg);
3375 break;
3376
3377 case 'k':
3378 tmpreg = get_num (&opP->disp, 55);
3379 install_operand (s[1], tmpreg & 0x7f);
3380 break;
3381
3382 case 'l':
3383 tmpreg = opP->mask;
3384 if (s[1] == 'w')
3385 {
3386 if (tmpreg & 0x7FF0000)
3387 as_bad (_("Floating point register in register list"));
3388 insop (reverse_16_bits (tmpreg), opcode);
3389 }
3390 else
3391 {
3392 if (tmpreg & 0x700FFFF)
3393 as_bad (_("Wrong register in floating-point reglist"));
3394 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3395 }
3396 break;
3397
3398 case 'L':
3399 tmpreg = opP->mask;
3400 if (s[1] == 'w')
3401 {
3402 if (tmpreg & 0x7FF0000)
3403 as_bad (_("Floating point register in register list"));
3404 insop (tmpreg, opcode);
3405 }
3406 else if (s[1] == '8')
3407 {
3408 if (tmpreg & 0x0FFFFFF)
3409 as_bad (_("incorrect register in reglist"));
3410 install_operand (s[1], tmpreg >> 24);
3411 }
3412 else
3413 {
3414 if (tmpreg & 0x700FFFF)
3415 as_bad (_("wrong register in floating-point reglist"));
3416 else
3417 install_operand (s[1], tmpreg >> 16);
3418 }
3419 break;
3420
3421 case 'M':
3422 install_operand (s[1], get_num (&opP->disp, 60));
3423 break;
3424
3425 case 'O':
3426 tmpreg = ((opP->mode == DREG)
8fce3f5e 3427 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3428 : (get_num (&opP->disp, 40) & 0x1F));
3429 install_operand (s[1], tmpreg);
3430 break;
3431
3432 case 'Q':
3433 tmpreg = get_num (&opP->disp, 10);
3434 if (tmpreg == 8)
3435 tmpreg = 0;
3436 install_operand (s[1], tmpreg);
3437 break;
3438
3439 case 'R':
3440 /* This depends on the fact that ADDR registers are eight
3441 more than their corresponding DATA regs, so the result
36759679 3442 will have the ADDR_REG bit set. */
252b5132
RH		 3443 install_operand (s[1], opP->reg - DATA);
3444 break;
3445
3446 case 'r':
3447 if (opP->mode == AINDR)
3448 install_operand (s[1], opP->reg - DATA);
3449 else
3450 install_operand (s[1], opP->index.reg - DATA);
3451 break;
3452
3453 case 's':
3454 if (opP->reg == FPI)
3455 tmpreg = 0x1;
3456 else if (opP->reg == FPS)
3457 tmpreg = 0x2;
3458 else if (opP->reg == FPC)
3459 tmpreg = 0x4;
3460 else
3461 abort ();
3462 install_operand (s[1], tmpreg);
3463 break;
3464
36759679 3465 case 'S': /* Ignore it. */
252b5132
RH		 3466 break;
3467
3468 case 'T':
3469 install_operand (s[1], get_num (&opP->disp, 30));
3470 break;
3471
36759679 3472 case 'U': /* Ignore it. */
252b5132
RH		 3473 break;
3474
3475 case 'c':
3476 switch (opP->reg)
3477 {
3478 case NC:
3479 tmpreg = 0;
3480 break;
3481 case DC:
3482 tmpreg = 1;
3483 break;
3484 case IC:
3485 tmpreg = 2;
3486 break;
3487 case BC:
3488 tmpreg = 3;
3489 break;
3490 default:
3491 as_fatal (_("failed sanity check"));
36759679 3492 } /* switch on cache token. */
252b5132
RH		 3493 install_operand (s[1], tmpreg);
3494 break;
3495#ifndef NO_68851
92774660 3496 /* JF: These are out of order, I fear. */
252b5132
RH		 3497 case 'f':
3498 switch (opP->reg)
3499 {
3500 case SFC:
3501 tmpreg = 0;
3502 break;
3503 case DFC:
3504 tmpreg = 1;
3505 break;
3506 default:
3507 abort ();
3508 }
3509 install_operand (s[1], tmpreg);
3510 break;
3511
3512 case '0':
3513 case '1':
3514 case '2':
3515 switch (opP->reg)
3516 {
3517 case TC:
3518 tmpreg = 0;
3519 break;
3520 case CAL:
3521 tmpreg = 4;
3522 break;
3523 case VAL:
3524 tmpreg = 5;
3525 break;
3526 case SCC:
3527 tmpreg = 6;
3528 break;
3529 case AC:
3530 tmpreg = 7;
3531 break;
3532 default:
3533 abort ();
3534 }
3535 install_operand (s[1], tmpreg);
3536 break;
3537
3538 case 'V':
3539 if (opP->reg == VAL)
3540 break;
3541 abort ();
3542
3543 case 'W':
3544 switch (opP->reg)
3545 {
3546 case DRP:
3547 tmpreg = 1;
3548 break;
3549 case SRP:
3550 tmpreg = 2;
3551 break;
3552 case CRP:
3553 tmpreg = 3;
3554 break;
3555 default:
3556 abort ();
3557 }
3558 install_operand (s[1], tmpreg);
3559 break;
3560
3561 case 'X':
3562 switch (opP->reg)
3563 {
3564 case BAD:
3565 case BAD + 1:
3566 case BAD + 2:
3567 case BAD + 3:
3568 case BAD + 4:
3569 case BAD + 5:
3570 case BAD + 6:
3571 case BAD + 7:
3572 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3573 break;
3574
3575 case BAC:
3576 case BAC + 1:
3577 case BAC + 2:
3578 case BAC + 3:
3579 case BAC + 4:
3580 case BAC + 5:
3581 case BAC + 6:
3582 case BAC + 7:
3583 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3584 break;
3585
3586 default:
3587 abort ();
3588 }
3589 install_operand (s[1], tmpreg);
3590 break;
3591 case 'Y':
3592 know (opP->reg == PSR);
3593 break;
3594 case 'Z':
3595 know (opP->reg == PCSR);
3596 break;
3597#endif /* m68851 */
3598 case '3':
3599 switch (opP->reg)
3600 {
3601 case TT0:
3602 tmpreg = 2;
3603 break;
3604 case TT1:
3605 tmpreg = 3;
3606 break;
3607 default:
3608 abort ();
3609 }
3610 install_operand (s[1], tmpreg);
3611 break;
3612 case 't':
3613 tmpreg = get_num (&opP->disp, 20);
3614 install_operand (s[1], tmpreg);
3615 break;
36759679 3616 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3617 if (isvar (&opP->disp))
3618 add_fix ('l', &opP->disp, 0, 0);
3e602632 3619 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3620 addword (tmpreg >> 16);
3621 addword (tmpreg & 0xFFFF);
3622 break;
6da466c7
ILT		 3623 case 'u':
3624 install_operand (s[1], opP->reg - DATA0L);
3625 opP->reg -= (DATA0L);
36759679 3626 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3627 break;
3e602632
NC		 3628 case 'x':
3629 tmpreg = get_num (&opP->disp, 80);
3630 if (tmpreg == -1)
3631 tmpreg = 0;
3632 install_operand (s[1], tmpreg);
3633 break;
afa2158f
NS		 3634 case 'j':
3635 tmpreg = get_num (&opP->disp, 10);
3636 install_operand (s[1], tmpreg - 1);
3637 break;
3638 case 'K':
3639 tmpreg = get_num (&opP->disp, 65);
3640 install_operand (s[1], tmpreg);
3641 break;
252b5132
RH		 3642 default:
3643 abort ();
3644 }
3645 }
3646
3647 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3648 instruction, ready to be emitted. . . */
252b5132
RH		 3649}
3650
3651static int
31302357 3652reverse_16_bits (int in)
252b5132
RH		 3653{
3654 int out = 0;
3655 int n;
3656
3657 static int mask[16] =
3658 {
3659 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3660 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3661 };
3662 for (n = 0; n < 16; n++)
3663 {
3664 if (in & mask[n])
3665 out |= mask[15 - n];
3666 }
3667 return out;
3668} /* reverse_16_bits() */
3669
3670static int
31302357 3671reverse_8_bits (int in)
252b5132
RH		 3672{
3673 int out = 0;
3674 int n;
3675
3676 static int mask[8] =
3677 {
3678 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3679 };
3680
3681 for (n = 0; n < 8; n++)
3682 {
3683 if (in & mask[n])
3684 out |= mask[7 - n];
3685 }
3686 return out;
3687} /* reverse_8_bits() */
3688
cac27205
NC		 3689/* Cause an extra frag to be generated here, inserting up to
3690 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3691 generated; its primary type is rs_machine_dependent.
252b5132
RH		 3692
3693 The TYPE parameter is also used by md_convert_frag_1 and
3694 md_estimate_size_before_relax. The appropriate type of fixup will
3695 be emitted by md_convert_frag_1.
3696
3697 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3698static void
31302357 3699install_operand (int mode, int val)
252b5132
RH		 3700{
3701 switch (mode)
3702 {
3703 case 's':
36759679 3704 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3705 break;
3706 case 'd':
3707 the_ins.opcode[0] |= val << 9;
3708 break;
afa2158f
NS		 3709 case 'E':
3710 the_ins.opcode[1] |= val << 9;
3711 break;
252b5132
RH		 3712 case '1':
3713 the_ins.opcode[1] |= val << 12;
3714 break;
3715 case '2':
3716 the_ins.opcode[1] |= val << 6;
3717 break;
3718 case '3':
3719 the_ins.opcode[1] |= val;
3720 break;
3721 case '4':
3722 the_ins.opcode[2] |= val << 12;
3723 break;
3724 case '5':
3725 the_ins.opcode[2] |= val << 6;
3726 break;
3727 case '6':
3728 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3729 three words long! */
3730 the_ins.numo++;
3731 the_ins.opcode[2] |= val;
3732 break;
3733 case '7':
3734 the_ins.opcode[1] |= val << 7;
3735 break;
3736 case '8':
3737 the_ins.opcode[1] |= val << 10;
3738 break;
3739#ifndef NO_68851
3740 case '9':
3741 the_ins.opcode[1] |= val << 5;
3742 break;
3743#endif
3744
3745 case 't':
3746 the_ins.opcode[1] |= (val << 10) | (val << 7);
3747 break;
3748 case 'D':
3749 the_ins.opcode[1] |= (val << 12) | val;
3750 break;
3751 case 'g':
3752 the_ins.opcode[0] |= val = 0xff;
3753 break;
3754 case 'i':
3755 the_ins.opcode[0] |= val << 9;
3756 break;
3757 case 'C':
3758 the_ins.opcode[1] |= val;
3759 break;
3760 case 'j':
3761 the_ins.opcode[1] |= val;
36759679 3762 the_ins.numo++; /* What a hack. */
252b5132
RH		 3763 break;
3764 case 'k':
3765 the_ins.opcode[1] |= val << 4;
3766 break;
3767 case 'b':
3768 case 'w':
3769 case 'W':
3770 case 'l':
3771 break;
3772 case 'e':
3773 the_ins.opcode[0] |= (val << 6);
3774 break;
3775 case 'L':
3776 the_ins.opcode[1] = (val >> 16);
3777 the_ins.opcode[2] = val & 0xffff;
3778 break;
6da466c7
ILT		 3779 case 'm':
3780 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3781 the_ins.opcode[0] |= ((val & 0x7) << 9);
3782 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3783 break;
fd99574b 3784 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3785 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3786 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3787 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3788 break;
fd99574b 3789 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3790 the_ins.opcode[1] |= val << 12;
3791 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3792 break;
fd99574b 3793 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3794 the_ins.opcode[0] |= (val & 0xF);
3795 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3796 break;
fd99574b 3797 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3798 the_ins.opcode[1] |= (val & 0xF);
3799 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3800 break;
3801 case 'h':
3802 the_ins.opcode[1] |= ((val != 1) << 10);
3803 break;
fd99574b
NC		 3804 case 'F':
3805 the_ins.opcode[0] |= ((val & 0x3) << 9);
3806 break;
3807 case 'f':
3808 the_ins.opcode[0] |= ((val & 0x3) << 0);
3809 break;
be8c092b 3810 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3811 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3812 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3813 break;
be8c092b 3814 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3815 the_ins.opcode[0] |= ((val & 0x1) << 7);
3816 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3817 break;
3818 case 'I':
3819 the_ins.opcode[1] |= ((val & 0x3) << 9);
3820 break;
3821 case ']':
3822 the_ins.opcode[0] |= (val & 0x1) <<10;
3823 break;
252b5132
RH		 3824 case 'c':
3825 default:
3826 as_fatal (_("failed sanity check."));
3827 }
6b6e92f4 3828}
252b5132
RH		 3829
3830static void
31302357 3831install_gen_operand (int mode, int val)
252b5132
RH		 3832{
3833 switch (mode)
3834 {
fd99574b
NC		 3835 case '/': /* Special for mask loads for mac/msac insns with
3836 possible mask; trailing_ampersend set in bit 8. */
3837 the_ins.opcode[0] |= (val & 0x3f);
3838 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3839 break;
252b5132
RH		 3840 case 's':
3841 the_ins.opcode[0] |= val;
3842 break;
3843 case 'd':
3844 /* This is a kludge!!! */
3845 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3846 break;
3847 case 'b':
3848 case 'w':
3849 case 'l':
3850 case 'f':
3851 case 'F':
3852 case 'x':
3853 case 'p':
3854 the_ins.opcode[0] |= val;
3855 break;
36759679 3856 /* more stuff goes here. */
252b5132
RH		 3857 default:
3858 as_fatal (_("failed sanity check."));
3859 }
6b6e92f4 3860}
252b5132 3861
6b6e92f4
NC		 3862/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3863 then deal with the bitfield hack. */
252b5132
RH		 3864
3865static char *
31302357 3866crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3867{
3868 register int parens;
3869 register int c;
3870 register char *beg_str;
3871 int inquote = 0;
3872
3873 if (!str)
3874 {
3875 return str;
3876 }
3877 beg_str = str;
3878 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3879 {
3880 if (! inquote)
3881 {
3882 if (*str == '(')
3883 parens++;
3884 else if (*str == ')')
3885 {
3886 if (!parens)
36759679 3887 { /* ERROR. */
252b5132
RH		 3888 opP->error = _("Extra )");
3889 return str;
3890 }
3891 --parens;
3892 }
3893 }
3894 if (flag_mri && *str == '\'')
3895 inquote = ! inquote;
3896 }
3897 if (!*str && parens)
36759679 3898 { /* ERROR. */
252b5132
RH		 3899 opP->error = _("Missing )");
3900 return str;
3901 }
3902 c = *str;
3903 *str = '\0';
3904 if (m68k_ip_op (beg_str, opP) != 0)
3905 {
3906 *str = c;
3907 return str;
3908 }
3909 *str = c;
3910 if (c == '}')
36759679 3911 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3912 if (c)
3913 {
3914 c = *++str;
3915 if (!c)
3916 as_bad (_("Missing operand"));
3917 }
3918
3919 /* Detect MRI REG symbols and convert them to REGLSTs. */
3920 if (opP->mode == CONTROL && (int)opP->reg < 0)
3921 {
3922 opP->mode = REGLST;
3923 opP->mask = ~(int)opP->reg;
3924 opP->reg = 0;
3925 }
3926
3927 return str;
3928}
3929
3930/* This is the guts of the machine-dependent assembler. STR points to a
3931 machine dependent instruction. This function is supposed to emit
3932 the frags/bytes it assembles to.
3933 */
3934
3935static void
31302357 3936insert_reg (const char *regname, int regnum)
252b5132
RH		 3937{
3938 char buf[100];
3939 int i;
3940
3941#ifdef REGISTER_PREFIX
3942 if (!flag_reg_prefix_optional)
3943 {
3944 buf[0] = REGISTER_PREFIX;
3945 strcpy (buf + 1, regname);
3946 regname = buf;
3947 }
3948#endif
3949
3950 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3951 &zero_address_frag));
3952
3953 for (i = 0; regname[i]; i++)
3882b010 3954 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3955 buf[i] = '\0';
3956
3957 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3958 &zero_address_frag));
3959}
3960
3961struct init_entry
3962 {
3963 const char *name;
3964 int number;
3965 };
3966
3967static const struct init_entry init_table[] =
3968{
3969 { "d0", DATA0 },
3970 { "d1", DATA1 },
3971 { "d2", DATA2 },
3972 { "d3", DATA3 },
3973 { "d4", DATA4 },
3974 { "d5", DATA5 },
3975 { "d6", DATA6 },
3976 { "d7", DATA7 },
3977 { "a0", ADDR0 },
3978 { "a1", ADDR1 },
3979 { "a2", ADDR2 },
3980 { "a3", ADDR3 },
3981 { "a4", ADDR4 },
3982 { "a5", ADDR5 },
3983 { "a6", ADDR6 },
3984 { "fp", ADDR6 },
3985 { "a7", ADDR7 },
3986 { "sp", ADDR7 },
3987 { "ssp", ADDR7 },
3988 { "fp0", FP0 },
3989 { "fp1", FP1 },
3990 { "fp2", FP2 },
3991 { "fp3", FP3 },
3992 { "fp4", FP4 },
3993 { "fp5", FP5 },
3994 { "fp6", FP6 },
3995 { "fp7", FP7 },
3996 { "fpi", FPI },
3997 { "fpiar", FPI },
3998 { "fpc", FPI },
3999 { "fps", FPS },
4000 { "fpsr", FPS },
4001 { "fpc", FPC },
4002 { "fpcr", FPC },
4003 { "control", FPC },
4004 { "status", FPS },
4005 { "iaddr", FPI },
4006
4007 { "cop0", COP0 },
4008 { "cop1", COP1 },
4009 { "cop2", COP2 },
4010 { "cop3", COP3 },
4011 { "cop4", COP4 },
4012 { "cop5", COP5 },
4013 { "cop6", COP6 },
4014 { "cop7", COP7 },
4015 { "pc", PC },
4016 { "zpc", ZPC },
4017 { "sr", SR },
4018
4019 { "ccr", CCR },
4020 { "cc", CCR },
4021
6da466c7 4022 { "acc", ACC },
fd99574b
NC		 4023 { "acc0", ACC },
4024 { "acc1", ACC1 },
4025 { "acc2", ACC2 },
4026 { "acc3", ACC3 },
4027 { "accext01", ACCEXT01 },
4028 { "accext23", ACCEXT23 },
6da466c7
ILT		 4029 { "macsr", MACSR },
4030 { "mask", MASK },
4031
36759679
NC		 4032 /* Control registers. */
4033 { "sfc", SFC }, /* Source Function Code. */
252b5132 4034 { "sfcr", SFC },
36759679 4035 { "dfc", DFC }, /* Destination Function Code. */
252b5132 4036 { "dfcr", DFC },
36759679
NC		 4037 { "cacr", CACR }, /* Cache Control Register. */
4038 { "caar", CAAR }, /* Cache Address Register. */
252b5132 4039
36759679
NC		 4040 { "usp", USP }, /* User Stack Pointer. */
4041 { "vbr", VBR }, /* Vector Base Register. */
4042 { "msp", MSP }, /* Master Stack Pointer. */
4043 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 4044
36759679
NC		 4045 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4046 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4047 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4048 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 4049
4050 /* 68ec040 versions of same */
36759679
NC		 4051 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4052 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4053 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4054 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 4055
a8e24a56 4056 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 4057 manual indicated that the order is 2,3,0,1, but Ken Rose
4058 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 4059 { "acr0", ACR0 }, /* Access Control Unit 0. */
4060 { "acr1", ACR1 }, /* Access Control Unit 1. */
4061 { "acr2", ACR2 }, /* Access Control Unit 2. */
4062 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 4063
36759679 4064 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 4065 { "tcr", TC },
a8e24a56 4066 { "asid", ASID },
252b5132 4067
36759679
NC		 4068 { "mmusr", MMUSR }, /* MMU Status Register. */
4069 { "srp", SRP }, /* User Root Pointer. */
4070 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 4071
4072 { "buscr", BUSCR },
a8e24a56 4073 { "mmubar", MMUBAR },
252b5132
RH		 4074 { "pcr", PCR },
4075
36759679
NC		 4076 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4077 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4078 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4079 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 4080
4081 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4082 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 4083 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 4084 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4085 { "mpcr", MPCR }, /* mcfv4e registers. */
4086 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4087 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4088 { "asid", TC }, /* mcfv4e registers. */
4089 { "mmubar", BUSCR }, /* mcfv4e registers. */
4090 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4091 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4092 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4093 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4094 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4095 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4096 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4097 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4098 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4099 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4100 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4101 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4102
4103 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4104 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 4105
4106 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b
KH		 4107
4108 { "cac", CAC }, /* fido registers. */
d0fa1372
KH		 4109 { "mbb", MBO }, /* fido registers (obsolete). */
4110 { "mbo", MBO }, /* fido registers. */
36759679 4111 /* End of control registers. */
252b5132
RH		 4112
4113 { "ac", AC },
4114 { "bc", BC },
4115 { "cal", CAL },
4116 { "crp", CRP },
4117 { "drp", DRP },
4118 { "pcsr", PCSR },
4119 { "psr", PSR },
4120 { "scc", SCC },
4121 { "val", VAL },
4122 { "bad0", BAD0 },
4123 { "bad1", BAD1 },
4124 { "bad2", BAD2 },
4125 { "bad3", BAD3 },
4126 { "bad4", BAD4 },
4127 { "bad5", BAD5 },
4128 { "bad6", BAD6 },
4129 { "bad7", BAD7 },
4130 { "bac0", BAC0 },
4131 { "bac1", BAC1 },
4132 { "bac2", BAC2 },
4133 { "bac3", BAC3 },
4134 { "bac4", BAC4 },
4135 { "bac5", BAC5 },
4136 { "bac6", BAC6 },
4137 { "bac7", BAC7 },
4138
4139 { "ic", IC },
4140 { "dc", DC },
4141 { "nc", NC },
4142
4143 { "tt0", TT0 },
4144 { "tt1", TT1 },
36759679 4145 /* 68ec030 versions of same. */
252b5132
RH		 4146 { "ac0", TT0 },
4147 { "ac1", TT1 },
36759679 4148 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 4149 { "acusr", PSR },
4150
4151 /* Suppressed data and address registers. */
4152 { "zd0", ZDATA0 },
4153 { "zd1", ZDATA1 },
4154 { "zd2", ZDATA2 },
4155 { "zd3", ZDATA3 },
4156 { "zd4", ZDATA4 },
4157 { "zd5", ZDATA5 },
4158 { "zd6", ZDATA6 },
4159 { "zd7", ZDATA7 },
4160 { "za0", ZADDR0 },
4161 { "za1", ZADDR1 },
4162 { "za2", ZADDR2 },
4163 { "za3", ZADDR3 },
4164 { "za4", ZADDR4 },
4165 { "za5", ZADDR5 },
4166 { "za6", ZADDR6 },
4167 { "za7", ZADDR7 },
4168
92774660 4169 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4170 { "d0l", DATA0L },
4171 { "d1l", DATA1L },
4172 { "d2l", DATA2L },
4173 { "d3l", DATA3L },
4174 { "d4l", DATA4L },
4175 { "d5l", DATA5L },
4176 { "d6l", DATA6L },
4177 { "d7l", DATA7L },
4178
4179 { "a0l", ADDR0L },
4180 { "a1l", ADDR1L },
4181 { "a2l", ADDR2L },
4182 { "a3l", ADDR3L },
4183 { "a4l", ADDR4L },
4184 { "a5l", ADDR5L },
4185 { "a6l", ADDR6L },
4186 { "a7l", ADDR7L },
4187
4188 { "d0u", DATA0U },
4189 { "d1u", DATA1U },
4190 { "d2u", DATA2U },
4191 { "d3u", DATA3U },
4192 { "d4u", DATA4U },
4193 { "d5u", DATA5U },
4194 { "d6u", DATA6U },
4195 { "d7u", DATA7U },
4196
4197 { "a0u", ADDR0U },
4198 { "a1u", ADDR1U },
4199 { "a2u", ADDR2U },
4200 { "a3u", ADDR3U },
4201 { "a4u", ADDR4U },
4202 { "a5u", ADDR5U },
4203 { "a6u", ADDR6U },
4204 { "a7u", ADDR7U },
4205
252b5132
RH		 4206 { 0, 0 }
4207};
4208
4209static void
31302357 4210init_regtable (void)
252b5132
RH		 4211{
4212 int i;
4213 for (i = 0; init_table[i].name; i++)
4214 insert_reg (init_table[i].name, init_table[i].number);
4215}
4216
252b5132 4217void
31302357 4218md_assemble (char *str)
252b5132
RH		 4219{
4220 const char *er;
4221 short *fromP;
4222 char *toP = NULL;
4223 int m, n = 0;
4224 char *to_beg_P;
4225 int shorts_this_frag;
4226 fixS *fixP;
4227
266abb8f
NS		 4228 if (!selected_cpu && !selected_arch)
4229 {
4230 /* We've not selected an architecture yet. Set the default
4231 now. We do this lazily so that an initial .cpu or .arch directive
4232 can specify. */
4233 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4234 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4235 }
4236 if (!initialized)
4237 m68k_init_arch ();
4238
252b5132
RH		 4239 /* In MRI mode, the instruction and operands are separated by a
4240 space. Anything following the operands is a comment. The label
4241 has already been removed. */
4242 if (flag_mri)
4243 {
4244 char *s;
4245 int fields = 0;
4246 int infield = 0;
4247 int inquote = 0;
4248
4249 for (s = str; *s != '\0'; s++)
4250 {
4251 if ((*s == ' ' || *s == '\t') && ! inquote)
4252 {
4253 if (infield)
4254 {
4255 ++fields;
4256 if (fields >= 2)
4257 {
4258 *s = '\0';
4259 break;
4260 }
4261 infield = 0;
4262 }
4263 }
4264 else
4265 {
4266 if (! infield)
4267 infield = 1;
4268 if (*s == '\'')
4269 inquote = ! inquote;
4270 }
4271 }
4272 }
4273
31302357 4274 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4275 m68k_ip (str);
4276 er = the_ins.error;
4277 if (!er)
4278 {
4279 for (n = 0; n < the_ins.numargs; n++)
4280 if (the_ins.operands[n].error)
4281 {
4282 er = the_ins.operands[n].error;
4283 break;
4284 }
4285 }
4286 if (er)
4287 {
4288 as_bad (_("%s -- statement `%s' ignored"), er, str);
4289 return;
4290 }
4291
4292 /* If there is a current label, record that it marks an instruction. */
4293 if (current_label != NULL)
4294 {
4295 current_label->text = 1;
4296 current_label = NULL;
4297 }
4298
f27a3839
AS		 4299#ifdef OBJ_ELF
4300 /* Tie dwarf2 debug info to the address at the start of the insn. */
4301 dwarf2_emit_insn (0);
4302#endif
4303
252b5132
RH		 4304 if (the_ins.nfrag == 0)
4305 {
36759679 4306 /* No frag hacking involved; just put it out. */
252b5132
RH		 4307 toP = frag_more (2 * the_ins.numo);
4308 fromP = &the_ins.opcode[0];
4309 for (m = the_ins.numo; m; --m)
4310 {
4311 md_number_to_chars (toP, (long) (*fromP), 2);
4312 toP += 2;
4313 fromP++;
4314 }
36759679 4315 /* Put out symbol-dependent info. */
252b5132
RH		 4316 for (m = 0; m < the_ins.nrel; m++)
4317 {
4318 switch (the_ins.reloc[m].wid)
4319 {
4320 case 'B':
4321 n = 1;
4322 break;
4323 case 'b':
4324 n = 1;
4325 break;
4326 case '3':
4327 n = 1;
4328 break;
4329 case 'w':
4330 case 'W':
4331 n = 2;
4332 break;
4333 case 'l':
4334 n = 4;
4335 break;
4336 default:
4337 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4338 the_ins.reloc[m].wid);
4339 }
4340
4341 fixP = fix_new_exp (frag_now,
4342 ((toP - frag_now->fr_literal)
4343 - the_ins.numo * 2 + the_ins.reloc[m].n),
4344 n,
4345 &the_ins.reloc[m].exp,
4346 the_ins.reloc[m].pcrel,
4347 get_reloc_code (n, the_ins.reloc[m].pcrel,
4348 the_ins.reloc[m].pic_reloc));
4349 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4350 if (the_ins.reloc[m].wid == 'B')
4351 fixP->fx_signed = 1;
4352 }
4353 return;
4354 }
4355
36759679 4356 /* There's some frag hacking. */
fbe572f9
AM		 4357 {
4358 /* Calculate the max frag size. */
4359 int wid;
4360
4361 wid = 2 * the_ins.fragb[0].fragoff;
4362 for (n = 1; n < the_ins.nfrag; n++)
4363 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4364 /* frag_var part. */
cac27205 4365 wid += FRAG_VAR_SIZE;
fbe572f9
AM		 4366 /* Make sure the whole insn fits in one chunk, in particular that
4367 the var part is attached, as we access one byte before the
4368 variable frag for byte branches. */
4369 frag_grow (wid);
4370 }
4371
252b5132
RH		 4372 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4373 {
4374 int wid;
4375
4376 if (n == 0)
4377 wid = 2 * the_ins.fragb[n].fragoff;
4378 else
4379 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4380 toP = frag_more (wid);
4381 to_beg_P = toP;
4382 shorts_this_frag = 0;
4383 for (m = wid / 2; m; --m)
4384 {
4385 md_number_to_chars (toP, (long) (*fromP), 2);
4386 toP += 2;
4387 fromP++;
4388 shorts_this_frag++;
4389 }
4390 for (m = 0; m < the_ins.nrel; m++)
4391 {
4392 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4393 {
4394 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4395 break;
4396 }
4397 wid = the_ins.reloc[m].wid;
4398 if (wid == 0)
4399 continue;
4400 the_ins.reloc[m].wid = 0;
4401 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4402
4403 fixP = fix_new_exp (frag_now,
4404 ((toP - frag_now->fr_literal)
4405 - the_ins.numo * 2 + the_ins.reloc[m].n),
4406 wid,
4407 &the_ins.reloc[m].exp,
4408 the_ins.reloc[m].pcrel,
4409 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4410 the_ins.reloc[m].pic_reloc));
4411 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4412 }
cac27205 4413 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
252b5132
RH		 4414 (relax_substateT) (the_ins.fragb[n].fragty),
4415 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4416 }
4417 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4418 shorts_this_frag = 0;
4419 if (n)
4420 {
055d1eb0 4421 toP = frag_more (n * 2);
252b5132
RH		 4422 while (n--)
4423 {
4424 md_number_to_chars (toP, (long) (*fromP), 2);
4425 toP += 2;
4426 fromP++;
4427 shorts_this_frag++;
4428 }
4429 }
4430 for (m = 0; m < the_ins.nrel; m++)
4431 {
4432 int wid;
4433
4434 wid = the_ins.reloc[m].wid;
4435 if (wid == 0)
4436 continue;
4437 the_ins.reloc[m].wid = 0;
4438 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4439
4440 fixP = fix_new_exp (frag_now,
4441 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4442 - shorts_this_frag * 2),
4443 wid,
4444 &the_ins.reloc[m].exp,
4445 the_ins.reloc[m].pcrel,
4446 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4447 the_ins.reloc[m].pic_reloc));
4448 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4449 }
4450}
4451
60fed2d3
NC		 4452/* Comparison function used by qsort to rank the opcode entries by name. */
4453
4454static int
4455m68k_compare_opcode (const void * v1, const void * v2)
4456{
4457 struct m68k_opcode * op1, * op2;
4458 int ret;
4459
03b13e59
NC		 4460 if (v1 == v2)
4461 return 0;
4462
60fed2d3
NC		 4463 op1 = *(struct m68k_opcode **) v1;
4464 op2 = *(struct m68k_opcode **) v2;
4465
4466 /* Compare the two names. If different, return the comparison.
4467 If the same, return the order they are in the opcode table. */
4468 ret = strcmp (op1->name, op2->name);
4469 if (ret)
4470 return ret;
4471 if (op1 < op2)
4472 return -1;
03b13e59 4473 return 1;
60fed2d3
NC		 4474}
4475
252b5132 4476void
60fed2d3 4477md_begin (void)
252b5132 4478{
60fed2d3
NC		 4479 const struct m68k_opcode *ins;
4480 struct m68k_incant *hack, *slak;
4481 const char *retval = 0; /* Empty string, or error msg text. */
4482 int i;
4483
4484 /* Set up hash tables with 68000 instructions.
4485 similar to what the vax assembler does. */
252b5132
RH		 4486 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4487 a copy of it at runtime, adding in the information we want but isn't
4488 there. I think it'd be better to have an awk script hack the table
4489 at compile time. Or even just xstr the table and use it as-is. But
4490 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4491 names. */
4492
252b5132
RH		 4493 if (flag_mri)
4494 {
4495 flag_reg_prefix_optional = 1;
4496 m68k_abspcadd = 1;
4497 if (! m68k_rel32_from_cmdline)
4498 m68k_rel32 = 0;
4499 }
4500
60fed2d3
NC		 4501 /* First sort the opcode table into alphabetical order to seperate
4502 the order that the assembler wants to see the opcodes from the
4503 order that the disassembler wants to see them. */
4504 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4505 if (!m68k_sorted_opcodes)
4506 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4507 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4508
4509 for (i = m68k_numopcodes; i--;)
4510 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4511
4512 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4513 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4514
252b5132
RH		 4515 op_hash = hash_new ();
4516
4517 obstack_begin (&robyn, 4000);
4518 for (i = 0; i < m68k_numopcodes; i++)
4519 {
78aff5a5 4520 hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4521 do
4522 {
60fed2d3
NC		 4523 ins = m68k_sorted_opcodes[i];
4524
afa2158f
NS		 4525 /* We must enter all insns into the table, because .arch and
4526 .cpu directives can change things. */
252b5132 4527 slak->m_operands = ins->args;
252b5132
RH		 4528 slak->m_arch = ins->arch;
4529 slak->m_opcode = ins->opcode;
afa2158f
NS		 4530
4531 /* In most cases we can determine the number of opcode words
4532 by checking the second word of the mask. Unfortunately
4533 some instructions have 2 opcode words, but no fixed bits
4534 in the second word. A leading dot in the operands
4535 string also indicates 2 opcodes. */
4536 if (*slak->m_operands == '.')
4537 {
4538 slak->m_operands++;
4539 slak->m_codenum = 2;
4540 }
4541 else if (ins->match & 0xffffL)
4542 slak->m_codenum = 2;
4543 else
4544 slak->m_codenum = 1;
4545 slak->m_opnum = strlen (slak->m_operands) / 2;
4546
252b5132 4547 if (i + 1 != m68k_numopcodes
60fed2d3 4548 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4549 {
60fed2d3 4550 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4551 i++;
4552 }
4553 else
4554 slak->m_next = 0;
4555 slak = slak->m_next;
4556 }
4557 while (slak);
4558
4559 retval = hash_insert (op_hash, ins->name, (char *) hack);
4560 if (retval)
4561 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4562 }
4563
4564 for (i = 0; i < m68k_numaliases; i++)
4565 {
4566 const char *name = m68k_opcode_aliases[i].primary;
4567 const char *alias = m68k_opcode_aliases[i].alias;
5a49b8ac 4568 void *val = hash_find (op_hash, name);
60fed2d3 4569
252b5132
RH		 4570 if (!val)
4571 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4572 retval = hash_insert (op_hash, alias, val);
4573 if (retval)
4574 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4575 }
4576
4577 /* In MRI mode, all unsized branches are variable sized. Normally,
4578 they are word sized. */
4579 if (flag_mri)
4580 {
4581 static struct m68k_opcode_alias mri_aliases[] =
4582 {
4583 { "bhi", "jhi", },
4584 { "bls", "jls", },
4585 { "bcc", "jcc", },
4586 { "bcs", "jcs", },
4587 { "bne", "jne", },
4588 { "beq", "jeq", },
4589 { "bvc", "jvc", },
4590 { "bvs", "jvs", },
4591 { "bpl", "jpl", },
4592 { "bmi", "jmi", },
4593 { "bge", "jge", },
4594 { "blt", "jlt", },
4595 { "bgt", "jgt", },
4596 { "ble", "jle", },
4597 { "bra", "jra", },
4598 { "bsr", "jbsr", },
4599 };
4600
8fce3f5e
AM		 4601 for (i = 0;
4602 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4603 i++)
252b5132
RH		 4604 {
4605 const char *name = mri_aliases[i].primary;
4606 const char *alias = mri_aliases[i].alias;
5a49b8ac 4607 void *val = hash_find (op_hash, name);
60fed2d3 4608
252b5132
RH		 4609 if (!val)
4610 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4611 retval = hash_jam (op_hash, alias, val);
4612 if (retval)
4613 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4614 }
4615 }
4616
8fce3f5e 4617 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4618 {
4619 notend_table[i] = 0;
4620 alt_notend_table[i] = 0;
4621 }
60fed2d3 4622
252b5132
RH		 4623 notend_table[','] = 1;
4624 notend_table['{'] = 1;
4625 notend_table['}'] = 1;
4626 alt_notend_table['a'] = 1;
4627 alt_notend_table['A'] = 1;
4628 alt_notend_table['d'] = 1;
4629 alt_notend_table['D'] = 1;
4630 alt_notend_table['#'] = 1;
4631 alt_notend_table['&'] = 1;
4632 alt_notend_table['f'] = 1;
4633 alt_notend_table['F'] = 1;
4634#ifdef REGISTER_PREFIX
4635 alt_notend_table[REGISTER_PREFIX] = 1;
4636#endif
4637
4638 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4639 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4640 alt_notend_table['('] = 1;
4641
4642 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4643 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4644 alt_notend_table['@'] = 1;
4645
4646 /* We need to put digits in alt_notend_table to handle
60fed2d3 4647 bfextu %d0{24:1},%d0 */
252b5132
RH		 4648 alt_notend_table['0'] = 1;
4649 alt_notend_table['1'] = 1;
4650 alt_notend_table['2'] = 1;
4651 alt_notend_table['3'] = 1;
4652 alt_notend_table['4'] = 1;
4653 alt_notend_table['5'] = 1;
4654 alt_notend_table['6'] = 1;
4655 alt_notend_table['7'] = 1;
4656 alt_notend_table['8'] = 1;
4657 alt_notend_table['9'] = 1;
4658
4659#ifndef MIT_SYNTAX_ONLY
4660 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4661 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4662 {
4663 int n = 0;
60fed2d3 4664
252b5132
RH		 4665 while (mote_pseudo_table[n].poc_name)
4666 {
60fed2d3 4667 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4668 hash_insert (op_hash,
4669 mote_pseudo_table[n].poc_name, (char *) hack);
4670 hack->m_operands = 0;
4671 hack->m_opnum = n;
4672 n++;
4673 }
4674 }
4675#endif
4676
4677 init_regtable ();
4678
4679#ifdef OBJ_ELF
4680 record_alignment (text_section, 2);
4681 record_alignment (data_section, 2);
4682 record_alignment (bss_section, 2);
4683#endif
4684}
4685
252b5132
RH		 4686\f
4687/* This is called when a label is defined. */
4688
4689void
31302357 4690m68k_frob_label (symbolS *sym)
252b5132
RH		 4691{
4692 struct label_line *n;
4693
4694 n = (struct label_line *) xmalloc (sizeof *n);
4695 n->next = labels;
4696 n->label = sym;
4697 as_where (&n->file, &n->line);
4698 n->text = 0;
4699 labels = n;
4700 current_label = n;
07a53e5c
RH		 4701
4702#ifdef OBJ_ELF
4703 dwarf2_emit_label (sym);
4704#endif
252b5132
RH		 4705}
4706
4707/* This is called when a value that is not an instruction is emitted. */
4708
4709void
31302357 4710m68k_flush_pending_output (void)
252b5132
RH		 4711{
4712 current_label = NULL;
4713}
4714
4715/* This is called at the end of the assembly, when the final value of
4716 the label is known. We warn if this is a text symbol aligned at an
4717 odd location. */
4718
4719void
31302357 4720m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4721{
4722 if (S_GET_SEGMENT (sym) == reg_section
4723 && (int) S_GET_VALUE (sym) < 0)
4724 {
4725 S_SET_SEGMENT (sym, absolute_section);
4726 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4727 }
4728 else if ((S_GET_VALUE (sym) & 1) != 0)
4729 {
4730 struct label_line *l;
4731
4732 for (l = labels; l != NULL; l = l->next)
4733 {
4734 if (l->label == sym)
4735 {
4736 if (l->text)
4737 as_warn_where (l->file, l->line,
4738 _("text label `%s' aligned to odd boundary"),
4739 S_GET_NAME (sym));
4740 break;
4741 }
4742 }
4743 }
4744}
4745\f
4746/* This is called if we go in or out of MRI mode because of the .mri
4747 pseudo-op. */
4748
4749void
31302357 4750m68k_mri_mode_change (int on)
252b5132
RH		 4751{
4752 if (on)
4753 {
4754 if (! flag_reg_prefix_optional)
4755 {
4756 flag_reg_prefix_optional = 1;
4757#ifdef REGISTER_PREFIX
4758 init_regtable ();
4759#endif
4760 }
4761 m68k_abspcadd = 1;
4762 if (! m68k_rel32_from_cmdline)
4763 m68k_rel32 = 0;
4764 }
4765 else
4766 {
4767 if (! reg_prefix_optional_seen)
4768 {
4769#ifdef REGISTER_PREFIX_OPTIONAL
4770 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4771#else
4772 flag_reg_prefix_optional = 0;
4773#endif
4774#ifdef REGISTER_PREFIX
4775 init_regtable ();
4776#endif
4777 }
4778 m68k_abspcadd = 0;
4779 if (! m68k_rel32_from_cmdline)
4780 m68k_rel32 = 1;
4781 }
4782}
4783
252b5132 4784char *
31302357 4785md_atof (int type, char *litP, int *sizeP)
252b5132 4786{
499ac353 4787 return ieee_md_atof (type, litP, sizeP, TRUE);
252b5132
RH		 4788}
4789
4790void
31302357 4791md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4792{
4793 number_to_chars_bigendian (buf, val, n);
4794}
4795
94f592af 4796void
55cf6793 4797md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4798{
bbe8ef22 4799 offsetT val = *valP;
252b5132
RH		 4800 addressT upper_limit;
4801 offsetT lower_limit;
4802
4803 /* This is unnecessary but it convinces the native rs6000 compiler
4804 to generate the code we want. */
4805 char *buf = fixP->fx_frag->fr_literal;
4806 buf += fixP->fx_where;
36759679 4807 /* End ibm compiler workaround. */
252b5132 4808
bd17c2c3 4809 val = SEXT (val);
252b5132 4810
94f592af
NC		 4811 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4812 fixP->fx_done = 1;
4813
252b5132
RH		 4814#ifdef OBJ_ELF
4815 if (fixP->fx_addsy)
4816 {
4817 memset (buf, 0, fixP->fx_size);
36759679 4818 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4819
4820 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4821 && !S_IS_DEFINED (fixP->fx_addsy)
4822 && !S_IS_WEAK (fixP->fx_addsy))
4823 S_SET_WEAK (fixP->fx_addsy);
cf869cce
NC		 4824
4825 switch (fixP->fx_r_type)
4826 {
4827 case BFD_RELOC_68K_TLS_GD32:
4828 case BFD_RELOC_68K_TLS_GD16:
4829 case BFD_RELOC_68K_TLS_GD8:
4830 case BFD_RELOC_68K_TLS_LDM32:
4831 case BFD_RELOC_68K_TLS_LDM16:
4832 case BFD_RELOC_68K_TLS_LDM8:
4833 case BFD_RELOC_68K_TLS_LDO32:
4834 case BFD_RELOC_68K_TLS_LDO16:
4835 case BFD_RELOC_68K_TLS_LDO8:
4836 case BFD_RELOC_68K_TLS_IE32:
4837 case BFD_RELOC_68K_TLS_IE16:
4838 case BFD_RELOC_68K_TLS_IE8:
4839 case BFD_RELOC_68K_TLS_LE32:
4840 case BFD_RELOC_68K_TLS_LE16:
4841 case BFD_RELOC_68K_TLS_LE8:
4842 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4843 break;
4844
4845 default:
4846 break;
4847 }
4848
252b5132
RH		 4849 return;
4850 }
22184a77 4851#elif defined(OBJ_AOUT)
1c3f20b4 4852 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
22184a77
NC		 4853 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4854 {
4855 memset (buf, 0, fixP->fx_size);
1c3f20b4 4856 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
22184a77
NC		 4857 return;
4858 }
252b5132
RH		 4859#endif
4860
252b5132
RH		 4861 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4862 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4863 return;
252b5132
RH		 4864
4865 switch (fixP->fx_size)
4866 {
94f592af
NC		 4867 /* The cast to offsetT below are necessary to make code
4868 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4869 case 1:
4870 *buf++ = val;
4871 upper_limit = 0x7f;
4872 lower_limit = - (offsetT) 0x80;
4873 break;
4874 case 2:
4875 *buf++ = (val >> 8);
4876 *buf++ = val;
4877 upper_limit = 0x7fff;
4878 lower_limit = - (offsetT) 0x8000;
4879 break;
4880 case 4:
4881 *buf++ = (val >> 24);
4882 *buf++ = (val >> 16);
4883 *buf++ = (val >> 8);
4884 *buf++ = val;
4885 upper_limit = 0x7fffffff;
36759679 4886 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4887 break;
4888 default:
4889 BAD_CASE (fixP->fx_size);
4890 }
4891
4892 /* Fix up a negative reloc. */
4893 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4894 {
4895 fixP->fx_addsy = fixP->fx_subsy;
4896 fixP->fx_subsy = NULL;
4897 fixP->fx_tcbit = 1;
4898 }
4899
4900 /* For non-pc-relative values, it's conceivable we might get something
4901 like "0xff" for a byte field. So extend the upper part of the range
4902 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4903 so that we can do any range checking at all. */
4904 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4905 upper_limit = upper_limit * 2 + 1;
4906
4907 if ((addressT) val > upper_limit
4908 && (val > 0 || val < lower_limit))
2b878742
NS		 4909 as_bad_where (fixP->fx_file, fixP->fx_line,
4910 _("value %ld out of range"), (long)val);
252b5132
RH		 4911
4912 /* A one byte PC-relative reloc means a short branch. We can't use
4913 a short branch with a value of 0 or -1, because those indicate
4914 different opcodes (branches with longer offsets). fixup_segment
4915 in write.c may have clobbered fx_pcrel, so we need to examine the
4916 reloc type. */
4917 if ((fixP->fx_pcrel
7be1c489 4918 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4919 && fixP->fx_size == 1
4920 && (fixP->fx_addsy == NULL
4921 || S_IS_DEFINED (fixP->fx_addsy))
4922 && (val == 0 || val == -1))
2b878742
NS		 4923 as_bad_where (fixP->fx_file, fixP->fx_line,
4924 _("invalid byte branch offset"));
252b5132
RH		 4925}
4926
252b5132
RH		 4927/* *fragP has been relaxed to its final size, and now needs to have
4928 the bytes inside it modified to conform to the new size There is UGLY
4929 MAGIC here. ..
4930 */
4931static void
31302357 4932md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4933{
4934 long disp;
2b878742 4935 fixS *fixP = NULL;
252b5132
RH		 4936
4937 /* Address in object code of the displacement. */
4938 register int object_address = fragP->fr_fix + fragP->fr_address;
4939
4940 /* Address in gas core of the place to store the displacement. */
4941 /* This convinces the native rs6000 compiler to generate the code we
92774660 4942 want. */
252b5132
RH		 4943 register char *buffer_address = fragP->fr_literal;
4944 buffer_address += fragP->fr_fix;
36759679 4945 /* End ibm compiler workaround. */
252b5132
RH		 4946
4947 /* The displacement of the address, from current location. */
4948 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4949 disp = (disp + fragP->fr_offset) - object_address;
4950
252b5132
RH		 4951 switch (fragP->fr_subtype)
4952 {
151337e8
NC		 4953 case TAB (BRANCHBWL, BYTE):
4954 case TAB (BRABSJUNC, BYTE):
4955 case TAB (BRABSJCOND, BYTE):
4956 case TAB (BRANCHBW, BYTE):
cac27205 4957 case TAB (BRANCHBWPL, BYTE):
252b5132
RH		 4958 know (issbyte (disp));
4959 if (disp == 0)
b091f402
AM		 4960 as_bad_where (fragP->fr_file, fragP->fr_line,
4961 _("short branch with zero offset: use :w"));
151337e8 4962 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4963 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4964 fixP->fx_pcrel_adjust = -1;
252b5132 4965 break;
151337e8
NC		 4966 case TAB (BRANCHBWL, SHORT):
4967 case TAB (BRABSJUNC, SHORT):
4968 case TAB (BRABSJCOND, SHORT):
4969 case TAB (BRANCHBW, SHORT):
cac27205 4970 case TAB (BRANCHBWPL, SHORT):
252b5132 4971 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 4972 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4973 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4974 fragP->fr_fix += 2;
4975 break;
4976 case TAB (BRANCHBWL, LONG):
4977 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 4978 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4979 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 4980 fragP->fr_fix += 4;
252b5132 4981 break;
cac27205
NC		 4982 case TAB (BRANCHBWPL, LONG):
4983 /* Here we are converting an unconditional branch into a pair of
4984 conditional branches, in order to get the range. */
4985 fragP->fr_opcode[0] = 0x66; /* bne */
4986 fragP->fr_opcode[1] = 0xFF;
4987 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4988 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4989 fixP->fx_file = fragP->fr_file;
4990 fixP->fx_line = fragP->fr_line;
4991 fragP->fr_fix += 4; /* Skip first offset */
4992 buffer_address += 4;
4993 *buffer_address++ = 0x67; /* beq */
4994 *buffer_address++ = 0xff;
4995 fragP->fr_fix += 2; /* Skip second branch opcode */
4996 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4997 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4998 fragP->fr_fix += 4;
4999 break;
151337e8
NC		 5000 case TAB (BRABSJUNC, LONG):
5001 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 5002 {
36759679 5003 if (flag_keep_pcrel)
2b878742
NS		 5004 as_bad_where (fragP->fr_file, fragP->fr_line,
5005 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 5006 fragP->fr_opcode[0] = 0x4E;
36759679 5007 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 5008 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5009 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5010 fragP->fr_fix += 4;
5011 }
5012 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5013 {
36759679 5014 if (flag_keep_pcrel)
2b878742
NS		 5015 as_bad_where (fragP->fr_file, fragP->fr_line,
5016 _("Conversion of PC relative branch to absolute jump"));
151337e8 5017 fragP->fr_opcode[0] = 0x4E;
36759679 5018 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 5019 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5020 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5021 fragP->fr_fix += 4;
252b5132
RH		 5022 }
5023 else
5024 {
151337e8
NC		 5025 /* This cannot happen, because jbsr and jbra are the only two
5026 unconditional branches. */
5027 abort ();
252b5132
RH		 5028 }
5029 break;
151337e8 5030 case TAB (BRABSJCOND, LONG):
36759679 5031 if (flag_keep_pcrel)
2b878742
NS		 5032 as_bad_where (fragP->fr_file, fragP->fr_line,
5033 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 5034
36759679
NC		 5035 /* Only Bcc 68000 instructions can come here
5036 Change bcc into b!cc/jmp absl long. */
5037 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5038 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 5039
5040 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 5041 different frag, in which case referring to them is a no-no.
92774660 5042 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 5043 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5044 *buffer_address++ = (char) 0xf9;
36759679 5045 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 5046 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5047 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5048 fragP->fr_fix += 4;
5049 break;
5050 case TAB (FBRANCH, SHORT):
5051 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 5052 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5053 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5054 fragP->fr_fix += 2;
5055 break;
5056 case TAB (FBRANCH, LONG):
36759679 5057 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 5058 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5059 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5060 fragP->fr_fix += 4;
252b5132 5061 break;
151337e8
NC		 5062 case TAB (DBCCLBR, SHORT):
5063 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 5064 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5065 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5066 fragP->fr_fix += 2;
5067 break;
5068 case TAB (DBCCLBR, LONG):
36759679
NC		 5069 /* Only DBcc instructions can come here.
5070 Change dbcc into dbcc/bral.
5071 JF: these used to be fr_opcode[2-7], but that's wrong. */
5072 if (flag_keep_pcrel)
2b878742
NS		 5073 as_bad_where (fragP->fr_file, fragP->fr_line,
5074 _("Conversion of DBcc to absolute jump"));
28e7409f 5075
36759679 5076 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 5077 *buffer_address++ = 0x04;
36759679 5078 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 5079 *buffer_address++ = 0x06;
151337e8
NC		 5080 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5081 *buffer_address++ = (char) 0xff;
252b5132 5082
36759679 5083 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5084 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5085 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5086 fragP->fr_fix += 4;
252b5132 5087 break;
151337e8 5088 case TAB (DBCCABSJ, LONG):
36759679
NC		 5089 /* Only DBcc instructions can come here.
5090 Change dbcc into dbcc/jmp.
5091 JF: these used to be fr_opcode[2-7], but that's wrong. */
5092 if (flag_keep_pcrel)
2b878742
NS		 5093 as_bad_where (fragP->fr_file, fragP->fr_line,
5094 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 5095
36759679 5096 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 5097 *buffer_address++ = 0x04;
36759679 5098 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 5099 *buffer_address++ = 0x06;
36759679 5100 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 5101 *buffer_address++ = (char) 0xf9;
5102
36759679 5103 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5104 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5105 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 5106 fragP->fr_fix += 4;
252b5132 5107 break;
151337e8 5108 case TAB (PCREL1632, SHORT):
252b5132
RH		 5109 fragP->fr_opcode[1] &= ~0x3F;
5110 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 5111 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5112 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 5113 fragP->fr_fix += 2;
252b5132 5114 break;
151337e8 5115 case TAB (PCREL1632, LONG):
252b5132
RH		 5116 /* Already set to mode 7.3; this indicates: PC indirect with
5117 suppressed index, 32-bit displacement. */
5118 *buffer_address++ = 0x01;
5119 *buffer_address++ = 0x70;
5120 fragP->fr_fix += 2;
151337e8 5121 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5122 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5123 fixP->fx_pcrel_adjust = 2;
5124 fragP->fr_fix += 4;
252b5132 5125 break;
252b5132 5126 case TAB (PCINDEX, BYTE):
252b5132
RH		 5127 assert (fragP->fr_fix >= 2);
5128 buffer_address[-2] &= ~1;
151337e8 5129 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5130 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5131 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 5132 break;
5133 case TAB (PCINDEX, SHORT):
252b5132
RH		 5134 assert (fragP->fr_fix >= 2);
5135 buffer_address[-2] |= 0x1;
5136 buffer_address[-1] = 0x20;
5137 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 5138 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 5139 fixP->fx_pcrel_adjust = 2;
151337e8 5140 fragP->fr_fix += 2;
252b5132
RH		 5141 break;
5142 case TAB (PCINDEX, LONG):
252b5132
RH		 5143 assert (fragP->fr_fix >= 2);
5144 buffer_address[-2] |= 0x1;
5145 buffer_address[-1] = 0x30;
151337e8 5146 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5147 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5148 fixP->fx_pcrel_adjust = 2;
5149 fragP->fr_fix += 4;
5150 break;
5151 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 5152 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5153 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5154 fragP->fr_fix += 2;
5155 break;
5156 case TAB (ABSTOPCREL, LONG):
36759679 5157 if (flag_keep_pcrel)
025987ea
NS		 5158 as_bad_where (fragP->fr_file, fragP->fr_line,
5159 _("Conversion of PC relative displacement to absolute"));
151337e8 5160 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 5161 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 5162 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5163 abort ();
5164 fragP->fr_opcode[1] &= ~0x3F;
5165 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 5166 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5167 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5168 fragP->fr_fix += 4;
252b5132 5169 break;
252b5132 5170 }
2b878742
NS		 5171 if (fixP)
5172 {
5173 fixP->fx_file = fragP->fr_file;
5174 fixP->fx_line = fragP->fr_line;
5175 }
252b5132
RH		 5176}
5177
252b5132 5178void
31302357
AS		 5179md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5180 segT sec ATTRIBUTE_UNUSED,
5181 fragS *fragP)
252b5132
RH		 5182{
5183 md_convert_frag_1 (fragP);
5184}
252b5132
RH		 5185
5186/* Force truly undefined symbols to their maximum size, and generally set up
5187 the frag list to be relaxed
5188 */
5189int
31302357 5190md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5191{
151337e8 5192 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5193 switch (fragP->fr_subtype)
5194 {
151337e8 5195 case TAB (BRANCHBWL, SZ_UNDEF):
cac27205 5196 case TAB (BRANCHBWPL, SZ_UNDEF):
151337e8 5197 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5198 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5199 {
151337e8
NC		 5200 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5201 && relaxable_symbol (fragP->fr_symbol))
252b5132 5202 {
151337e8
NC		 5203 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5204 }
5205 else if (flag_short_refs)
5206 {
5207 /* Symbol is undefined and we want short ref. */
5208 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5209 }
5210 else
5211 {
151337e8
NC		 5212 /* Symbol is still undefined. Make it LONG. */
5213 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5214 }
5215 break;
151337e8 5216 }
252b5132 5217
151337e8 5218 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5219 {
151337e8
NC		 5220 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5221 && relaxable_symbol (fragP->fr_symbol))
252b5132 5222 {
151337e8 5223 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5224 }
5225 else
5226 {
151337e8
NC		 5227 /* Symbol is undefined and we don't have long branches. */
5228 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5229 }
5230 break;
151337e8 5231 }
252b5132 5232
151337e8 5233 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5234 case TAB (DBCCLBR, SZ_UNDEF):
5235 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5236 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5237 {
8ec6253e
NC		 5238 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5239 && relaxable_symbol (fragP->fr_symbol))
151337e8 5240 || flag_short_refs)
252b5132 5241 {
151337e8 5242 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5243 }
5244 else
5245 {
151337e8 5246 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5247 }
5248 break;
151337e8 5249 }
81d4177b 5250
252b5132
RH		 5251 case TAB (PCINDEX, SZ_UNDEF):
5252 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5253 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5254 {
5255 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5256 }
5257 else
5258 {
5259 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5260 }
5261 break;
5262
151337e8
NC		 5263 case TAB (ABSTOPCREL, SZ_UNDEF):
5264 {
5265 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5266 && relaxable_symbol (fragP->fr_symbol)))
5267 {
5268 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5269 }
5270 else
5271 {
5272 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5273 }
5274 break;
5275 }
5276
252b5132
RH		 5277 default:
5278 break;
5279 }
5280
151337e8 5281 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5282 switch (fragP->fr_subtype)
5283 {
151337e8
NC		 5284 case TAB (BRANCHBWL, BYTE):
5285 case TAB (BRABSJUNC, BYTE):
5286 case TAB (BRABSJCOND, BYTE):
5287 case TAB (BRANCHBW, BYTE):
252b5132 5288 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5289 case we force word mode. If the symbol is at the start of a
5290 frag, and it is the next frag with any data in it (usually
5291 this is just the next frag, but assembler listings may
5292 introduce empty frags), we must use word mode. */
5293 if (fragP->fr_symbol)
252b5132 5294 {
ac62c346 5295 fragS *sym_frag;
252b5132 5296
ac62c346
AM		 5297 sym_frag = symbol_get_frag (fragP->fr_symbol);
5298 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5299 {
ac62c346
AM		 5300 fragS *l;
5301
23b7f870 5302 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5303 if (l->fr_fix != 0)
5304 break;
5305 if (l == sym_frag)
5306 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5307 }
5308 }
5309 break;
5310 default:
5311 break;
5312 }
ac62c346 5313 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5314}
5315
5316#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5317/* the bit-field entries in the relocation_info struct plays hell
5318 with the byte-order problems of cross-assembly. So as a hack,
5319 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5320 you there. -KWK */
252b5132
RH		 5321/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5322 are symbolnum, most sig. byte first. Last byte is broken up with
5323 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5324 nibble as nuthin. (on Sun 3 at least) */
5325/* Translate the internal relocation information into target-specific
92774660 5326 format. */
252b5132
RH		 5327#ifdef comment
5328void
31302357 5329md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5330{
36759679 5331 /* This is easy. */
252b5132 5332 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5333 /* Now the fun stuff. */
252b5132 5334 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5335 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5336 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5337 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5338 | ((ri->r_length << 5) & 0x60)
5339 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5340}
5341
36759679 5342#endif
252b5132 5343
252b5132
RH		 5344#endif /* OBJ_AOUT or OBJ_BOUT */
5345
5346#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5347int md_short_jump_size = 4;
5348int md_long_jump_size = 6;
252b5132
RH		 5349
5350void
31302357
AS		 5351md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5352 fragS *frag ATTRIBUTE_UNUSED,
5353 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5354{
5355 valueT offset;
5356
5357 offset = to_addr - (from_addr + 2);
5358
5359 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5360 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5361}
5362
5363void
31302357
AS		 5364md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5365 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5366{
5367 valueT offset;
5368
6b6e92f4 5369 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5370 {
36759679 5371 if (flag_keep_pcrel)
6b6e92f4 5372 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5373 offset = to_addr - S_GET_VALUE (to_symbol);
5374 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5375 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5376 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5377 0, NO_RELOC);
5378 }
5379 else
5380 {
5381 offset = to_addr - (from_addr + 2);
5382 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5383 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5384 }
5385}
5386
5387#endif
5388
5389/* Different values of OK tell what its OK to return. Things that
5390 aren't OK are an error (what a shock, no?)
5391
5392 0: Everything is OK
3e602632
NC		 5393 10: Absolute 1:8 only
5394 20: Absolute 0:7 only
5395 30: absolute 0:15 only
5396 40: Absolute 0:31 only
5397 50: absolute 0:127 only
252b5132 5398 55: absolute -64:63 only
3e602632 5399 60: absolute -128:127 only
afa2158f 5400 65: absolute 0:511 only
3e602632
NC		 5401 70: absolute 0:4095 only
5402 80: absolute -1, 1:7 only
5403 90: No bignums. */
252b5132
RH		 5404
5405static int
31302357 5406get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5407{
5408 if (exp->exp.X_op == O_absent)
5409 {
36759679 5410 /* Do the same thing the VAX asm does. */
252b5132
RH		 5411 op (exp) = O_constant;
5412 adds (exp) = 0;
5413 subs (exp) = 0;
5414 offs (exp) = 0;
5415 if (ok == 10)
5416 {
5417 as_warn (_("expression out of range: defaulting to 1"));
5418 offs (exp) = 1;
5419 }
5420 }
5421 else if (exp->exp.X_op == O_constant)
5422 {
5423 switch (ok)
5424 {
5425 case 10:
bd17c2c3 5426 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5427 {
5428 as_warn (_("expression out of range: defaulting to 1"));
5429 offs (exp) = 1;
5430 }
5431 break;
5432 case 20:
bd17c2c3 5433 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5434 goto outrange;
5435 break;
5436 case 30:
bd17c2c3 5437 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5438 goto outrange;
5439 break;
5440 case 40:
bd17c2c3 5441 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5442 goto outrange;
5443 break;
5444 case 50:
bd17c2c3 5445 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5446 goto outrange;
5447 break;
5448 case 55:
bd17c2c3 5449 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5450 goto outrange;
5451 break;
5452 case 60:
bd17c2c3 5453 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132 5454 goto outrange;
afa2158f
NS		 5455 break;
5456 case 65:
5457 if ((valueT) TRUNC (offs (exp)) > 511)
5458 goto outrange;
252b5132
RH		 5459 break;
5460 case 70:
bd17c2c3 5461 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5462 {
5463 outrange:
5464 as_warn (_("expression out of range: defaulting to 0"));
5465 offs (exp) = 0;
5466 }
5467 break;
3e602632 5468 case 80:
bd17c2c3
AM		 5469 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5470 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5471 {
5472 as_warn (_("expression out of range: defaulting to 1"));
5473 offs (exp) = 1;
5474 }
5475 break;
252b5132
RH		 5476 default:
5477 break;
5478 }
5479 }
5480 else if (exp->exp.X_op == O_big)
5481 {
36759679 5482 if (offs (exp) <= 0 /* flonum. */
3e602632 5483 && (ok == 90 /* no bignums */
36759679 5484 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5485 /* If we have a flonum zero, a zero integer should
5486 do as well (e.g., in moveq). */
5487 && generic_floating_point_number.exponent == 0
5488 && generic_floating_point_number.low[0] == 0)))
5489 {
36759679 5490 /* HACK! Turn it into a long. */
252b5132
RH		 5491 LITTLENUM_TYPE words[6];
5492
36759679 5493 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5494 op (exp) = O_constant;
5495 adds (exp) = 0;
5496 subs (exp) = 0;
5497 offs (exp) = words[1] | (words[0] << 16);
5498 }
5499 else if (ok != 0)
5500 {
5501 op (exp) = O_constant;
5502 adds (exp) = 0;
5503 subs (exp) = 0;
5504 offs (exp) = (ok == 10) ? 1 : 0;
5505 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5506 (long) offs (exp));
252b5132
RH		 5507 }
5508 }
5509 else
5510 {
3e602632 5511 if (ok >= 10 && ok <= 80)
252b5132
RH		 5512 {
5513 op (exp) = O_constant;
5514 adds (exp) = 0;
5515 subs (exp) = 0;
5516 offs (exp) = (ok == 10) ? 1 : 0;
5517 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5518 (long) offs (exp));
252b5132
RH		 5519 }
5520 }
5521
5522 if (exp->size != SIZE_UNSPEC)
5523 {
5524 switch (exp->size)
5525 {
5526 case SIZE_UNSPEC:
5527 case SIZE_LONG:
5528 break;
5529 case SIZE_BYTE:
5530 if (!isbyte (offs (exp)))
5531 as_warn (_("expression doesn't fit in BYTE"));
5532 break;
5533 case SIZE_WORD:
5534 if (!isword (offs (exp)))
5535 as_warn (_("expression doesn't fit in WORD"));
5536 break;
5537 }
5538 }
5539
5540 return offs (exp);
5541}
5542
5543/* These are the back-ends for the various machine dependent pseudo-ops. */
5544
5545static void
31302357 5546s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5547{
5548 subseg_set (data_section, 1);
5549 demand_empty_rest_of_line ();
5550}
5551
5552static void
31302357 5553s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5554{
5555 subseg_set (data_section, 2);
5556 demand_empty_rest_of_line ();
5557}
5558
5559static void
31302357 5560s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5561{
5562 /* We don't support putting frags in the BSS segment, we fake it
5563 by marking in_bss, then looking at s_skip for clues. */
5564
5565 subseg_set (bss_section, 0);
5566 demand_empty_rest_of_line ();
5567}
5568
5569static void
31302357 5570s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5571{
5572 register int temp;
5573 register long temp_fill;
5574
5575 temp = 1; /* JF should be 2? */
5576 temp_fill = get_absolute_expression ();
92774660 5577 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5578 frag_align (temp, (int) temp_fill, 0);
5579 demand_empty_rest_of_line ();
5580 record_alignment (now_seg, temp);
5581}
5582
5583static void
31302357 5584s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5585{
5586 demand_empty_rest_of_line ();
5587}
5588\f
5589/* Pseudo-ops handled for MRI compatibility. */
5590
5591/* This function returns non-zero if the argument is a conditional
5592 pseudo-op. This is called when checking whether a pending
5593 alignment is needed. */
5594
5595int
31302357 5596m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5597{
5598 return (pop->poc_handler == s_mri_if
5599 || pop->poc_handler == s_mri_else);
5600}
5601
5602/* Handle an MRI style chip specification. */
5603
5604static void
31302357 5605mri_chip (void)
252b5132
RH		 5606{
5607 char *s;
5608 char c;
5609 int i;
5610
5611 s = input_line_pointer;
5612 /* We can't use get_symbol_end since the processor names are not proper
5613 symbols. */
5614 while (is_part_of_name (c = *input_line_pointer++))
5615 ;
5616 *--input_line_pointer = 0;
266abb8f
NS		 5617 for (i = 0; m68k_cpus[i].name; i++)
5618 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5619 break;
266abb8f 5620 if (!m68k_cpus[i].name)
252b5132
RH		 5621 {
5622 as_bad (_("%s: unrecognized processor name"), s);
5623 *input_line_pointer = c;
5624 ignore_rest_of_line ();
5625 return;
5626 }
5627 *input_line_pointer = c;
5628
5629 if (*input_line_pointer == '/')
5630 current_architecture = 0;
5631 else
5632 current_architecture &= m68881 | m68851;
266abb8f 5633 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5634 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5635
5636 while (*input_line_pointer == '/')
5637 {
5638 ++input_line_pointer;
5639 s = input_line_pointer;
5640 /* We can't use get_symbol_end since the processor names are not
5641 proper symbols. */
5642 while (is_part_of_name (c = *input_line_pointer++))
5643 ;
5644 *--input_line_pointer = 0;
5645 if (strcmp (s, "68881") == 0)
5646 current_architecture |= m68881;
5647 else if (strcmp (s, "68851") == 0)
5648 current_architecture |= m68851;
5649 *input_line_pointer = c;
5650 }
252b5132
RH		 5651}
5652
5653/* The MRI CHIP pseudo-op. */
5654
5655static void
31302357 5656s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5657{
5658 char *stop = NULL;
5659 char stopc;
5660
5661 if (flag_mri)
5662 stop = mri_comment_field (&stopc);
5663 mri_chip ();
5664 if (flag_mri)
5665 mri_comment_end (stop, stopc);
5666 demand_empty_rest_of_line ();
5667}
5668
5669/* The MRI FOPT pseudo-op. */
5670
5671static void
31302357 5672s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5673{
5674 SKIP_WHITESPACE ();
5675
5676 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5677 {
5678 int temp;
5679
5680 input_line_pointer += 3;
5681 temp = get_absolute_expression ();
5682 if (temp < 0 || temp > 7)
5683 as_bad (_("bad coprocessor id"));
5684 else
5685 m68k_float_copnum = COP0 + temp;
5686 }
5687 else
5688 {
5689 as_bad (_("unrecognized fopt option"));
5690 ignore_rest_of_line ();
5691 return;
5692 }
5693
5694 demand_empty_rest_of_line ();
5695}
5696
5697/* The structure used to handle the MRI OPT pseudo-op. */
5698
5699struct opt_action
5700{
5701 /* The name of the option. */
5702 const char *name;
5703
5704 /* If this is not NULL, just call this function. The first argument
5705 is the ARG field of this structure, the second argument is
5706 whether the option was negated. */
31302357 5707 void (*pfn) (int arg, int on);
252b5132
RH		 5708
5709 /* If this is not NULL, and the PFN field is NULL, set the variable
5710 this points to. Set it to the ARG field if the option was not
5711 negated, and the NOTARG field otherwise. */
5712 int *pvar;
5713
5714 /* The value to pass to PFN or to assign to *PVAR. */
5715 int arg;
5716
5717 /* The value to assign to *PVAR if the option is negated. If PFN is
5718 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5719 the option may not be negated. */
5720 int notarg;
5721};
5722
5723/* The table used to handle the MRI OPT pseudo-op. */
5724
31302357
AS		 5725static void skip_to_comma (int, int);
5726static void opt_nest (int, int);
5727static void opt_chip (int, int);
5728static void opt_list (int, int);
5729static void opt_list_symbols (int, int);
252b5132
RH		 5730
5731static const struct opt_action opt_table[] =
5732{
5733 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5734
5735 /* We do relaxing, so there is little use for these options. */
5736 { "b", 0, 0, 0, 0 },
5737 { "brs", 0, 0, 0, 0 },
5738 { "brb", 0, 0, 0, 0 },
5739 { "brl", 0, 0, 0, 0 },
5740 { "brw", 0, 0, 0, 0 },
5741
5742 { "c", 0, 0, 0, 0 },
5743 { "cex", 0, 0, 0, 0 },
5744 { "case", 0, &symbols_case_sensitive, 1, 0 },
5745 { "cl", 0, 0, 0, 0 },
5746 { "cre", 0, 0, 0, 0 },
5747 { "d", 0, &flag_keep_locals, 1, 0 },
5748 { "e", 0, 0, 0, 0 },
5749 { "f", 0, &flag_short_refs, 1, 0 },
5750 { "frs", 0, &flag_short_refs, 1, 0 },
5751 { "frl", 0, &flag_short_refs, 0, 1 },
5752 { "g", 0, 0, 0, 0 },
5753 { "i", 0, 0, 0, 0 },
5754 { "m", 0, 0, 0, 0 },
5755 { "mex", 0, 0, 0, 0 },
5756 { "mc", 0, 0, 0, 0 },
5757 { "md", 0, 0, 0, 0 },
5758 { "nest", opt_nest, 0, 0, 0 },
5759 { "next", skip_to_comma, 0, 0, 0 },
5760 { "o", 0, 0, 0, 0 },
5761 { "old", 0, 0, 0, 0 },
5762 { "op", skip_to_comma, 0, 0, 0 },
5763 { "pco", 0, 0, 0, 0 },
5764 { "p", opt_chip, 0, 0, 0 },
5765 { "pcr", 0, 0, 0, 0 },
5766 { "pcs", 0, 0, 0, 0 },
5767 { "r", 0, 0, 0, 0 },
5768 { "quick", 0, &m68k_quick, 1, 0 },
5769 { "rel32", 0, &m68k_rel32, 1, 0 },
5770 { "s", opt_list, 0, 0, 0 },
5771 { "t", opt_list_symbols, 0, 0, 0 },
5772 { "w", 0, &flag_no_warnings, 0, 1 },
5773 { "x", 0, 0, 0, 0 }
5774};
5775
8fce3f5e 5776#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5777
5778/* The MRI OPT pseudo-op. */
5779
5780static void
31302357 5781s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5782{
5783 do
5784 {
5785 int t;
5786 char *s;
5787 char c;
5788 int i;
5789 const struct opt_action *o;
5790
5791 SKIP_WHITESPACE ();
5792
5793 t = 1;
5794 if (*input_line_pointer == '-')
5795 {
5796 ++input_line_pointer;
5797 t = 0;
5798 }
5799 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5800 {
5801 input_line_pointer += 2;
5802 t = 0;
5803 }
5804
5805 s = input_line_pointer;
5806 c = get_symbol_end ();
5807
5808 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5809 {
5810 if (strcasecmp (s, o->name) == 0)
5811 {
5812 if (o->pfn)
5813 {
5814 /* Restore input_line_pointer now in case the option
5815 takes arguments. */
5816 *input_line_pointer = c;
5817 (*o->pfn) (o->arg, t);
5818 }
5819 else if (o->pvar != NULL)
5820 {
5821 if (! t && o->arg == o->notarg)
5822 as_bad (_("option `%s' may not be negated"), s);
5823 *input_line_pointer = c;
5824 *o->pvar = t ? o->arg : o->notarg;
5825 }
5826 else
5827 *input_line_pointer = c;
5828 break;
5829 }
5830 }
5831 if (i >= OPTCOUNT)
5832 {
5833 as_bad (_("option `%s' not recognized"), s);
5834 *input_line_pointer = c;
5835 }
5836 }
5837 while (*input_line_pointer++ == ',');
5838
5839 /* Move back to terminating character. */
5840 --input_line_pointer;
5841 demand_empty_rest_of_line ();
5842}
5843
5844/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5845 not support and which take arguments. */
252b5132
RH		 5846
5847static void
31302357 5848skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5849{
5850 while (*input_line_pointer != ','
5851 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5852 ++input_line_pointer;
5853}
5854
5855/* Handle the OPT NEST=depth option. */
5856
5857static void
31302357 5858opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5859{
5860 if (*input_line_pointer != '=')
5861 {
5862 as_bad (_("bad format of OPT NEST=depth"));
5863 return;
5864 }
5865
5866 ++input_line_pointer;
5867 max_macro_nest = get_absolute_expression ();
5868}
5869
5870/* Handle the OPT P=chip option. */
5871
5872static void
31302357 5873opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5874{
5875 if (*input_line_pointer != '=')
5876 {
5877 /* This is just OPT P, which we do not support. */
5878 return;
5879 }
5880
5881 ++input_line_pointer;
5882 mri_chip ();
5883}
5884
5885/* Handle the OPT S option. */
5886
5887static void
31302357 5888opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5889{
5890 listing_list (on);
5891}
5892
5893/* Handle the OPT T option. */
5894
5895static void
31302357 5896opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5897{
5898 if (on)
5899 listing |= LISTING_SYMBOLS;
5900 else
8a104df9 5901 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5902}
5903
5904/* Handle the MRI REG pseudo-op. */
5905
5906static void
31302357 5907s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5908{
5909 char *s;
5910 int c;
5911 struct m68k_op rop;
5912 int mask;
5913 char *stop = NULL;
5914 char stopc;
5915
5916 if (line_label == NULL)
5917 {
5918 as_bad (_("missing label"));
5919 ignore_rest_of_line ();
5920 return;
5921 }
5922
5923 if (flag_mri)
5924 stop = mri_comment_field (&stopc);
5925
5926 SKIP_WHITESPACE ();
5927
5928 s = input_line_pointer;
3882b010 5929 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5930#ifdef REGISTER_PREFIX
5931 || *input_line_pointer == REGISTER_PREFIX
5932#endif
5933 || *input_line_pointer == '/'
5934 || *input_line_pointer == '-')
5935 ++input_line_pointer;
5936 c = *input_line_pointer;
5937 *input_line_pointer = '\0';
5938
5939 if (m68k_ip_op (s, &rop) != 0)
5940 {
5941 if (rop.error == NULL)
5942 as_bad (_("bad register list"));
5943 else
5944 as_bad (_("bad register list: %s"), rop.error);
5945 *input_line_pointer = c;
5946 ignore_rest_of_line ();
5947 return;
5948 }
5949
5950 *input_line_pointer = c;
5951
5952 if (rop.mode == REGLST)
5953 mask = rop.mask;
5954 else if (rop.mode == DREG)
5955 mask = 1 << (rop.reg - DATA0);
5956 else if (rop.mode == AREG)
5957 mask = 1 << (rop.reg - ADDR0 + 8);
5958 else if (rop.mode == FPREG)
5959 mask = 1 << (rop.reg - FP0 + 16);
5960 else if (rop.mode == CONTROL
5961 && rop.reg == FPI)
5962 mask = 1 << 24;
5963 else if (rop.mode == CONTROL
5964 && rop.reg == FPS)
5965 mask = 1 << 25;
5966 else if (rop.mode == CONTROL
5967 && rop.reg == FPC)
5968 mask = 1 << 26;
5969 else
5970 {
5971 as_bad (_("bad register list"));
5972 ignore_rest_of_line ();
5973 return;
5974 }
5975
5976 S_SET_SEGMENT (line_label, reg_section);
5977 S_SET_VALUE (line_label, ~mask);
49309057 5978 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5979
5980 if (flag_mri)
5981 mri_comment_end (stop, stopc);
5982
5983 demand_empty_rest_of_line ();
5984}
5985
5986/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5987
5988struct save_opts
5989{
5990 struct save_opts *next;
5991 int abspcadd;
5992 int symbols_case_sensitive;
5993 int keep_locals;
5994 int short_refs;
5995 int architecture;
2da12c60 5996 const enum m68k_register *control_regs;
252b5132
RH		 5997 int quick;
5998 int rel32;
5999 int listing;
6000 int no_warnings;
6001 /* FIXME: We don't save OPT S. */
6002};
6003
6004/* This variable holds the stack of saved options. */
6005
6006static struct save_opts *save_stack;
6007
6008/* The MRI SAVE pseudo-op. */
6009
6010static void
31302357 6011s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6012{
6013 struct save_opts *s;
6014
6015 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
6016 s->abspcadd = m68k_abspcadd;
6017 s->symbols_case_sensitive = symbols_case_sensitive;
6018 s->keep_locals = flag_keep_locals;
6019 s->short_refs = flag_short_refs;
6020 s->architecture = current_architecture;
2da12c60 6021 s->control_regs = control_regs;
252b5132
RH		 6022 s->quick = m68k_quick;
6023 s->rel32 = m68k_rel32;
6024 s->listing = listing;
6025 s->no_warnings = flag_no_warnings;
6026
6027 s->next = save_stack;
6028 save_stack = s;
6029
6030 demand_empty_rest_of_line ();
6031}
6032
6033/* The MRI RESTORE pseudo-op. */
6034
6035static void
31302357 6036s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6037{
6038 struct save_opts *s;
6039
6040 if (save_stack == NULL)
6041 {
6042 as_bad (_("restore without save"));
6043 ignore_rest_of_line ();
6044 return;
6045 }
6046
6047 s = save_stack;
6048 save_stack = s->next;
6049
6050 m68k_abspcadd = s->abspcadd;
6051 symbols_case_sensitive = s->symbols_case_sensitive;
6052 flag_keep_locals = s->keep_locals;
6053 flag_short_refs = s->short_refs;
6054 current_architecture = s->architecture;
2da12c60 6055 control_regs = s->control_regs;
252b5132
RH		 6056 m68k_quick = s->quick;
6057 m68k_rel32 = s->rel32;
6058 listing = s->listing;
6059 flag_no_warnings = s->no_warnings;
6060
6061 free (s);
6062
6063 demand_empty_rest_of_line ();
6064}
6065
6066/* Types of MRI structured control directives. */
6067
6068enum mri_control_type
6069{
6070 mri_for,
6071 mri_if,
6072 mri_repeat,
6073 mri_while
6074};
6075
6076/* This structure is used to stack the MRI structured control
6077 directives. */
6078
6079struct mri_control_info
6080{
6081 /* The directive within which this one is enclosed. */
6082 struct mri_control_info *outer;
6083
6084 /* The type of directive. */
6085 enum mri_control_type type;
6086
6087 /* Whether an ELSE has been in an IF. */
6088 int else_seen;
6089
6090 /* The add or sub statement at the end of a FOR. */
6091 char *incr;
6092
6093 /* The label of the top of a FOR or REPEAT loop. */
6094 char *top;
6095
6096 /* The label to jump to for the next iteration, or the else
6097 expression of a conditional. */
6098 char *next;
6099
6100 /* The label to jump to to break out of the loop, or the label past
6101 the end of a conditional. */
6102 char *bottom;
6103};
6104
6105/* The stack of MRI structured control directives. */
6106
6107static struct mri_control_info *mri_control_stack;
6108
6109/* The current MRI structured control directive index number, used to
6110 generate label names. */
6111
6112static int mri_control_index;
6113
252b5132
RH		 6114/* Assemble an instruction for an MRI structured control directive. */
6115
6116static void
31302357 6117mri_assemble (char *str)
252b5132
RH		 6118{
6119 char *s;
6120
6121 /* md_assemble expects the opcode to be in lower case. */
6122 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 6123 *s = TOLOWER (*s);
252b5132
RH		 6124
6125 md_assemble (str);
6126}
6127
6128/* Generate a new MRI label structured control directive label name. */
6129
6130static char *
31302357 6131mri_control_label (void)
252b5132
RH		 6132{
6133 char *n;
6134
6135 n = (char *) xmalloc (20);
6136 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6137 ++mri_control_index;
6138 return n;
6139}
6140
6141/* Create a new MRI structured control directive. */
6142
6143static struct mri_control_info *
31302357 6144push_mri_control (enum mri_control_type type)
252b5132
RH		 6145{
6146 struct mri_control_info *n;
6147
6148 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6149
6150 n->type = type;
6151 n->else_seen = 0;
6152 if (type == mri_if || type == mri_while)
6153 n->top = NULL;
6154 else
6155 n->top = mri_control_label ();
6156 n->next = mri_control_label ();
6157 n->bottom = mri_control_label ();
6158
6159 n->outer = mri_control_stack;
6160 mri_control_stack = n;
6161
6162 return n;
6163}
6164
6165/* Pop off the stack of MRI structured control directives. */
6166
6167static void
31302357 6168pop_mri_control (void)
252b5132
RH		 6169{
6170 struct mri_control_info *n;
6171
6172 n = mri_control_stack;
6173 mri_control_stack = n->outer;
6174 if (n->top != NULL)
6175 free (n->top);
6176 free (n->next);
6177 free (n->bottom);
6178 free (n);
6179}
6180
6181/* Recognize a condition code in an MRI structured control expression. */
6182
6183static int
31302357 6184parse_mri_condition (int *pcc)
252b5132
RH		 6185{
6186 char c1, c2;
6187
6188 know (*input_line_pointer == '<');
6189
6190 ++input_line_pointer;
6191 c1 = *input_line_pointer++;
6192 c2 = *input_line_pointer++;
6193
6194 if (*input_line_pointer != '>')
6195 {
6196 as_bad (_("syntax error in structured control directive"));
6197 return 0;
6198 }
6199
6200 ++input_line_pointer;
6201 SKIP_WHITESPACE ();
6202
3882b010
L		 6203 c1 = TOLOWER (c1);
6204 c2 = TOLOWER (c2);
252b5132
RH		 6205
6206 *pcc = (c1 << 8) | c2;
6207
6208 return 1;
6209}
6210
6211/* Parse a single operand in an MRI structured control expression. */
6212
6213static int
31302357
AS		 6214parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6215 char **rightstart, char **rightstop)
252b5132
RH		 6216{
6217 char *s;
6218
6219 SKIP_WHITESPACE ();
6220
6221 *pcc = -1;
6222 *leftstart = NULL;
6223 *leftstop = NULL;
6224 *rightstart = NULL;
6225 *rightstop = NULL;
6226
6227 if (*input_line_pointer == '<')
6228 {
6229 /* It's just a condition code. */
6230 return parse_mri_condition (pcc);
6231 }
6232
6233 /* Look ahead for the condition code. */
6234 for (s = input_line_pointer; *s != '\0'; ++s)
6235 {
6236 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6237 break;
6238 }
6239 if (*s == '\0')
6240 {
6241 as_bad (_("missing condition code in structured control directive"));
6242 return 0;
6243 }
6244
6245 *leftstart = input_line_pointer;
6246 *leftstop = s;
6247 if (*leftstop > *leftstart
6248 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6249 --*leftstop;
6250
6251 input_line_pointer = s;
6252 if (! parse_mri_condition (pcc))
6253 return 0;
6254
6255 /* Look ahead for AND or OR or end of line. */
6256 for (s = input_line_pointer; *s != '\0'; ++s)
6257 {
e1f44d10
NC		 6258 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6259 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6260 ^^^ ^^ */
8a104df9
KH		 6261 if ((s == input_line_pointer
6262 || *(s-1) == ' '
6263 || *(s-1) == '\t')
6264 && ((strncasecmp (s, "AND", 3) == 0
6265 && (s[3] == '.' || ! is_part_of_name (s[3])))
6266 || (strncasecmp (s, "OR", 2) == 0
6267 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6268 break;
252b5132
RH		 6269 }
6270
6271 *rightstart = input_line_pointer;
6272 *rightstop = s;
6273 if (*rightstop > *rightstart
6274 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6275 --*rightstop;
6276
6277 input_line_pointer = s;
6278
6279 return 1;
6280}
6281
6282#define MCC(b1, b2) (((b1) << 8) | (b2))
6283
6284/* Swap the sense of a condition. This changes the condition so that
6285 it generates the same result when the operands are swapped. */
6286
6287static int
31302357 6288swap_mri_condition (int cc)
252b5132
RH		 6289{
6290 switch (cc)
6291 {
6292 case MCC ('h', 'i'): return MCC ('c', 's');
6293 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6294 /* <HS> is an alias for <CC>. */
e1f44d10 6295 case MCC ('h', 's'):
252b5132 6296 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6297 /* <LO> is an alias for <CS>. */
e1f44d10 6298 case MCC ('l', 'o'):
252b5132
RH		 6299 case MCC ('c', 's'): return MCC ('h', 'i');
6300 case MCC ('p', 'l'): return MCC ('m', 'i');
6301 case MCC ('m', 'i'): return MCC ('p', 'l');
6302 case MCC ('g', 'e'): return MCC ('l', 'e');
6303 case MCC ('l', 't'): return MCC ('g', 't');
6304 case MCC ('g', 't'): return MCC ('l', 't');
6305 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6306 /* Issue a warning for conditions we can not swap. */
8fc4ee9b
AM		 6307 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6308 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
e1f44d10
NC		 6309 case MCC ('v', 'c'):
6310 case MCC ('v', 's'):
6311 default :
6312 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6313 (char) (cc >> 8), (char) (cc));
6314 break;
252b5132
RH		 6315 }
6316 return cc;
6317}
6318
6319/* Reverse the sense of a condition. */
6320
6321static int
31302357 6322reverse_mri_condition (int cc)
252b5132
RH		 6323{
6324 switch (cc)
6325 {
6326 case MCC ('h', 'i'): return MCC ('l', 's');
6327 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6328 /* <HS> is an alias for <CC> */
6329 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6330 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6331 /* <LO> is an alias for <CS> */
6332 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6333 case MCC ('c', 's'): return MCC ('c', 'c');
6334 case MCC ('n', 'e'): return MCC ('e', 'q');
6335 case MCC ('e', 'q'): return MCC ('n', 'e');
6336 case MCC ('v', 'c'): return MCC ('v', 's');
6337 case MCC ('v', 's'): return MCC ('v', 'c');
6338 case MCC ('p', 'l'): return MCC ('m', 'i');
6339 case MCC ('m', 'i'): return MCC ('p', 'l');
6340 case MCC ('g', 'e'): return MCC ('l', 't');
6341 case MCC ('l', 't'): return MCC ('g', 'e');
6342 case MCC ('g', 't'): return MCC ('l', 'e');
6343 case MCC ('l', 'e'): return MCC ('g', 't');
6344 }
6345 return cc;
6346}
6347
6348/* Build an MRI structured control expression. This generates test
6349 and branch instructions. It goes to TRUELAB if the condition is
6350 true, and to FALSELAB if the condition is false. Exactly one of
6351 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6352 is the size qualifier for the expression. EXTENT is the size to
6353 use for the branch. */
6354
6355static void
31302357
AS		 6356build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6357 char *rightstart, char *rightstop,
6358 const char *truelab, const char *falselab,
6359 int extent)
252b5132
RH		 6360{
6361 char *buf;
6362 char *s;
6363
6364 if (leftstart != NULL)
6365 {
6366 struct m68k_op leftop, rightop;
6367 char c;
6368
6369 /* Swap the compare operands, if necessary, to produce a legal
6370 m68k compare instruction. Comparing a register operand with
6371 a non-register operand requires the register to be on the
6372 right (cmp, cmpa). Comparing an immediate value with
6373 anything requires the immediate value to be on the left
6374 (cmpi). */
6375
6376 c = *leftstop;
6377 *leftstop = '\0';
6378 (void) m68k_ip_op (leftstart, &leftop);
6379 *leftstop = c;
6380
6381 c = *rightstop;
6382 *rightstop = '\0';
6383 (void) m68k_ip_op (rightstart, &rightop);
6384 *rightstop = c;
6385
6386 if (rightop.mode == IMMED
6387 || ((leftop.mode == DREG || leftop.mode == AREG)
6388 && (rightop.mode != DREG && rightop.mode != AREG)))
6389 {
6390 char *temp;
6391
31302357
AS		 6392 /* Correct conditional handling:
6393 if #1 <lt> d0 then ;means if (1 < d0)
6394 ...
6395 endi
e1f44d10 6396
31302357 6397 should assemble to:
e1f44d10 6398
31302357
AS		 6399 cmp #1,d0 if we do *not* swap the operands
6400 bgt true we need the swapped condition!
6401 ble false
6402 true:
6403 ...
6404 false:
6405 */
252b5132
RH		 6406 temp = leftstart;
6407 leftstart = rightstart;
6408 rightstart = temp;
6409 temp = leftstop;
6410 leftstop = rightstop;
6411 rightstop = temp;
8a104df9
KH		 6412 }
6413 else
6414 {
e1f44d10 6415 cc = swap_mri_condition (cc);
252b5132
RH		 6416 }
6417 }
6418
6419 if (truelab == NULL)
6420 {
6421 cc = reverse_mri_condition (cc);
6422 truelab = falselab;
6423 }
92774660 6424
252b5132
RH		 6425 if (leftstart != NULL)
6426 {
6427 buf = (char *) xmalloc (20
6428 + (leftstop - leftstart)
6429 + (rightstop - rightstart));
6430 s = buf;
6431 *s++ = 'c';
6432 *s++ = 'm';
6433 *s++ = 'p';
6434 if (qual != '\0')
3882b010 6435 *s++ = TOLOWER (qual);
252b5132
RH		 6436 *s++ = ' ';
6437 memcpy (s, leftstart, leftstop - leftstart);
6438 s += leftstop - leftstart;
6439 *s++ = ',';
6440 memcpy (s, rightstart, rightstop - rightstart);
6441 s += rightstop - rightstart;
6442 *s = '\0';
6443 mri_assemble (buf);
6444 free (buf);
6445 }
92774660 6446
252b5132
RH		 6447 buf = (char *) xmalloc (20 + strlen (truelab));
6448 s = buf;
6449 *s++ = 'b';
6450 *s++ = cc >> 8;
6451 *s++ = cc & 0xff;
6452 if (extent != '\0')
3882b010 6453 *s++ = TOLOWER (extent);
252b5132
RH		 6454 *s++ = ' ';
6455 strcpy (s, truelab);
6456 mri_assemble (buf);
6457 free (buf);
6458}
6459
6460/* Parse an MRI structured control expression. This generates test
6461 and branch instructions. STOP is where the expression ends. It
6462 goes to TRUELAB if the condition is true, and to FALSELAB if the
6463 condition is false. Exactly one of TRUELAB and FALSELAB will be
6464 NULL, meaning to fall through. QUAL is the size qualifier for the
6465 expression. EXTENT is the size to use for the branch. */
6466
6467static void
31302357
AS		 6468parse_mri_control_expression (char *stop, int qual, const char *truelab,
6469 const char *falselab, int extent)
252b5132
RH		 6470{
6471 int c;
6472 int cc;
6473 char *leftstart;
6474 char *leftstop;
6475 char *rightstart;
6476 char *rightstop;
6477
6478 c = *stop;
6479 *stop = '\0';
6480
6481 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6482 &rightstart, &rightstop))
6483 {
6484 *stop = c;
6485 return;
6486 }
6487
6488 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6489 {
6490 const char *flab;
6491
6492 if (falselab != NULL)
6493 flab = falselab;
6494 else
6495 flab = mri_control_label ();
6496
6497 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6498 rightstop, (const char *) NULL, flab, extent);
6499
6500 input_line_pointer += 3;
6501 if (*input_line_pointer != '.'
6502 || input_line_pointer[1] == '\0')
6503 qual = '\0';
6504 else
6505 {
6506 qual = input_line_pointer[1];
6507 input_line_pointer += 2;
6508 }
6509
6510 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6511 &rightstart, &rightstop))
6512 {
6513 *stop = c;
6514 return;
6515 }
6516
6517 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6518 rightstop, truelab, falselab, extent);
6519
6520 if (falselab == NULL)
6521 colon (flab);
6522 }
6523 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6524 {
6525 const char *tlab;
6526
6527 if (truelab != NULL)
6528 tlab = truelab;
6529 else
6530 tlab = mri_control_label ();
6531
6532 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6533 rightstop, tlab, (const char *) NULL, extent);
6534
6535 input_line_pointer += 2;
6536 if (*input_line_pointer != '.'
6537 || input_line_pointer[1] == '\0')
6538 qual = '\0';
6539 else
6540 {
6541 qual = input_line_pointer[1];
6542 input_line_pointer += 2;
6543 }
6544
6545 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6546 &rightstart, &rightstop))
6547 {
6548 *stop = c;
6549 return;
6550 }
6551
6552 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6553 rightstop, truelab, falselab, extent);
6554
6555 if (truelab == NULL)
6556 colon (tlab);
6557 }
6558 else
6559 {
6560 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6561 rightstop, truelab, falselab, extent);
6562 }
6563
6564 *stop = c;
6565 if (input_line_pointer != stop)
6566 as_bad (_("syntax error in structured control directive"));
6567}
6568
6569/* Handle the MRI IF pseudo-op. This may be a structured control
6570 directive, or it may be a regular assembler conditional, depending
6571 on its operands. */
6572
6573static void
31302357 6574s_mri_if (int qual)
252b5132
RH		 6575{
6576 char *s;
6577 int c;
6578 struct mri_control_info *n;
6579
6580 /* A structured control directive must end with THEN with an
6581 optional qualifier. */
6582 s = input_line_pointer;
e1f44d10
NC		 6583 /* We only accept '*' as introduction of comments if preceded by white space
6584 or at first column of a line (I think this can't actually happen here?)
6585 This is important when assembling:
6586 if d0 <ne> 12(a0,d0*2) then
36759679 6587 if d0 <ne> #CONST*20 then. */
31302357
AS		 6588 while (! (is_end_of_line[(unsigned char) *s]
6589 || (flag_mri
6590 && *s == '*'
6591 && (s == input_line_pointer
6592 || *(s-1) == ' '
6593 || *(s-1) == '\t'))))
252b5132
RH		 6594 ++s;
6595 --s;
6596 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6597 --s;
6598
6599 if (s - input_line_pointer > 1
6600 && s[-1] == '.')
6601 s -= 2;
6602
6603 if (s - input_line_pointer < 3
6604 || strncasecmp (s - 3, "THEN", 4) != 0)
6605 {
6606 if (qual != '\0')
6607 {
6608 as_bad (_("missing then"));
6609 ignore_rest_of_line ();
6610 return;
6611 }
6612
6613 /* It's a conditional. */
6614 s_if (O_ne);
6615 return;
6616 }
6617
6618 /* Since this might be a conditional if, this pseudo-op will be
6619 called even if we are supported to be ignoring input. Double
6620 check now. Clobber *input_line_pointer so that ignore_input
6621 thinks that this is not a special pseudo-op. */
6622 c = *input_line_pointer;
6623 *input_line_pointer = 0;
6624 if (ignore_input ())
6625 {
6626 *input_line_pointer = c;
6627 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6628 ++input_line_pointer;
6629 demand_empty_rest_of_line ();
6630 return;
6631 }
6632 *input_line_pointer = c;
6633
6634 n = push_mri_control (mri_if);
6635
6636 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6637 n->next, s[1] == '.' ? s[2] : '\0');
6638
6639 if (s[1] == '.')
6640 input_line_pointer = s + 3;
6641 else
6642 input_line_pointer = s + 1;
6643
6644 if (flag_mri)
6645 {
6646 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6647 ++input_line_pointer;
6648 }
6649
6650 demand_empty_rest_of_line ();
6651}
6652
6653/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6654 structured IF, associate the ELSE with the IF. Otherwise, assume
6655 it is a conditional else. */
6656
6657static void
31302357 6658s_mri_else (int qual)
252b5132
RH		 6659{
6660 int c;
6661 char *buf;
6662 char q[2];
6663
6664 if (qual == '\0'
6665 && (mri_control_stack == NULL
6666 || mri_control_stack->type != mri_if
6667 || mri_control_stack->else_seen))
6668 {
6669 s_else (0);
6670 return;
6671 }
6672
6673 c = *input_line_pointer;
6674 *input_line_pointer = 0;
6675 if (ignore_input ())
6676 {
6677 *input_line_pointer = c;
6678 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6679 ++input_line_pointer;
6680 demand_empty_rest_of_line ();
6681 return;
6682 }
6683 *input_line_pointer = c;
6684
6685 if (mri_control_stack == NULL
6686 || mri_control_stack->type != mri_if
6687 || mri_control_stack->else_seen)
6688 {
6689 as_bad (_("else without matching if"));
6690 ignore_rest_of_line ();
6691 return;
6692 }
6693
6694 mri_control_stack->else_seen = 1;
6695
6696 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6697 q[0] = TOLOWER (qual);
252b5132
RH		 6698 q[1] = '\0';
6699 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6700 mri_assemble (buf);
6701 free (buf);
6702
6703 colon (mri_control_stack->next);
6704
6705 if (flag_mri)
6706 {
6707 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6708 ++input_line_pointer;
6709 }
6710
6711 demand_empty_rest_of_line ();
6712}
6713
6714/* Handle the MRI ENDI pseudo-op. */
6715
6716static void
31302357 6717s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6718{
6719 if (mri_control_stack == NULL
6720 || mri_control_stack->type != mri_if)
6721 {
6722 as_bad (_("endi without matching if"));
6723 ignore_rest_of_line ();
6724 return;
6725 }
6726
6727 /* ignore_input will not return true for ENDI, so we don't need to
6728 worry about checking it again here. */
6729
6730 if (! mri_control_stack->else_seen)
6731 colon (mri_control_stack->next);
6732 colon (mri_control_stack->bottom);
6733
6734 pop_mri_control ();
6735
6736 if (flag_mri)
6737 {
6738 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6739 ++input_line_pointer;
6740 }
6741
6742 demand_empty_rest_of_line ();
6743}
6744
6745/* Handle the MRI BREAK pseudo-op. */
6746
6747static void
31302357 6748s_mri_break (int extent)
252b5132
RH		 6749{
6750 struct mri_control_info *n;
6751 char *buf;
6752 char ex[2];
6753
6754 n = mri_control_stack;
6755 while (n != NULL
6756 && n->type != mri_for
6757 && n->type != mri_repeat
6758 && n->type != mri_while)
6759 n = n->outer;
6760 if (n == NULL)
6761 {
6762 as_bad (_("break outside of structured loop"));
6763 ignore_rest_of_line ();
6764 return;
6765 }
6766
6767 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6768 ex[0] = TOLOWER (extent);
252b5132
RH		 6769 ex[1] = '\0';
6770 sprintf (buf, "bra%s %s", ex, n->bottom);
6771 mri_assemble (buf);
6772 free (buf);
6773
6774 if (flag_mri)
6775 {
6776 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6777 ++input_line_pointer;
6778 }
6779
6780 demand_empty_rest_of_line ();
6781}
6782
6783/* Handle the MRI NEXT pseudo-op. */
6784
6785static void
31302357 6786s_mri_next (int extent)
252b5132
RH		 6787{
6788 struct mri_control_info *n;
6789 char *buf;
6790 char ex[2];
6791
6792 n = mri_control_stack;
6793 while (n != NULL
6794 && n->type != mri_for
6795 && n->type != mri_repeat
6796 && n->type != mri_while)
6797 n = n->outer;
6798 if (n == NULL)
6799 {
6800 as_bad (_("next outside of structured loop"));
6801 ignore_rest_of_line ();
6802 return;
6803 }
6804
6805 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6806 ex[0] = TOLOWER (extent);
252b5132
RH		 6807 ex[1] = '\0';
6808 sprintf (buf, "bra%s %s", ex, n->next);
6809 mri_assemble (buf);
6810 free (buf);
6811
6812 if (flag_mri)
6813 {
6814 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6815 ++input_line_pointer;
6816 }
6817
6818 demand_empty_rest_of_line ();
6819}
6820
6821/* Handle the MRI FOR pseudo-op. */
6822
6823static void
31302357 6824s_mri_for (int qual)
252b5132
RH		 6825{
6826 const char *varstart, *varstop;
6827 const char *initstart, *initstop;
6828 const char *endstart, *endstop;
6829 const char *bystart, *bystop;
6830 int up;
6831 int by;
6832 int extent;
6833 struct mri_control_info *n;
6834 char *buf;
6835 char *s;
6836 char ex[2];
6837
6838 /* The syntax is
6839 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6840 */
6841
6842 SKIP_WHITESPACE ();
6843 varstart = input_line_pointer;
6844
6845 /* Look for the '='. */
6846 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6847 && *input_line_pointer != '=')
6848 ++input_line_pointer;
6849 if (*input_line_pointer != '=')
6850 {
6851 as_bad (_("missing ="));
6852 ignore_rest_of_line ();
6853 return;
6854 }
6855
6856 varstop = input_line_pointer;
6857 if (varstop > varstart
6858 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6859 --varstop;
6860
6861 ++input_line_pointer;
6862
6863 initstart = input_line_pointer;
6864
6865 /* Look for TO or DOWNTO. */
6866 up = 1;
6867 initstop = NULL;
6868 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6869 {
6870 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6871 && ! is_part_of_name (input_line_pointer[2]))
6872 {
6873 initstop = input_line_pointer;
6874 input_line_pointer += 2;
6875 break;
6876 }
6877 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6878 && ! is_part_of_name (input_line_pointer[6]))
6879 {
6880 initstop = input_line_pointer;
6881 up = 0;
6882 input_line_pointer += 6;
6883 break;
6884 }
6885 ++input_line_pointer;
6886 }
6887 if (initstop == NULL)
6888 {
6889 as_bad (_("missing to or downto"));
6890 ignore_rest_of_line ();
6891 return;
6892 }
6893 if (initstop > initstart
6894 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6895 --initstop;
6896
6897 SKIP_WHITESPACE ();
6898 endstart = input_line_pointer;
6899
6900 /* Look for BY or DO. */
6901 by = 0;
6902 endstop = NULL;
6903 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6904 {
6905 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6906 && ! is_part_of_name (input_line_pointer[2]))
6907 {
6908 endstop = input_line_pointer;
6909 by = 1;
6910 input_line_pointer += 2;
6911 break;
6912 }
6913 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6914 && (input_line_pointer[2] == '.'
6915 || ! is_part_of_name (input_line_pointer[2])))
6916 {
6917 endstop = input_line_pointer;
6918 input_line_pointer += 2;
6919 break;
6920 }
6921 ++input_line_pointer;
6922 }
6923 if (endstop == NULL)
6924 {
6925 as_bad (_("missing do"));
6926 ignore_rest_of_line ();
6927 return;
6928 }
6929 if (endstop > endstart
6930 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6931 --endstop;
6932
6933 if (! by)
6934 {
6935 bystart = "#1";
6936 bystop = bystart + 2;
6937 }
6938 else
6939 {
6940 SKIP_WHITESPACE ();
6941 bystart = input_line_pointer;
6942
6943 /* Look for DO. */
6944 bystop = NULL;
6945 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6946 {
6947 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6948 && (input_line_pointer[2] == '.'
6949 || ! is_part_of_name (input_line_pointer[2])))
6950 {
6951 bystop = input_line_pointer;
6952 input_line_pointer += 2;
6953 break;
6954 }
6955 ++input_line_pointer;
6956 }
6957 if (bystop == NULL)
6958 {
6959 as_bad (_("missing do"));
6960 ignore_rest_of_line ();
6961 return;
6962 }
6963 if (bystop > bystart
6964 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6965 --bystop;
6966 }
6967
6968 if (*input_line_pointer != '.')
6969 extent = '\0';
6970 else
6971 {
6972 extent = input_line_pointer[1];
6973 input_line_pointer += 2;
6974 }
6975
6976 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6977 n = push_mri_control (mri_for);
6978
6979 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6980
36759679 6981 /* Move init,var. */
252b5132
RH		 6982 s = buf;
6983 *s++ = 'm';
6984 *s++ = 'o';
6985 *s++ = 'v';
6986 *s++ = 'e';
6987 if (qual != '\0')
3882b010 6988 *s++ = TOLOWER (qual);
252b5132
RH		 6989 *s++ = ' ';
6990 memcpy (s, initstart, initstop - initstart);
6991 s += initstop - initstart;
6992 *s++ = ',';
6993 memcpy (s, varstart, varstop - varstart);
6994 s += varstop - varstart;
6995 *s = '\0';
6996 mri_assemble (buf);
6997
6998 colon (n->top);
6999
36759679 7000 /* cmp end,var. */
252b5132
RH		 7001 s = buf;
7002 *s++ = 'c';
7003 *s++ = 'm';
7004 *s++ = 'p';
7005 if (qual != '\0')
3882b010 7006 *s++ = TOLOWER (qual);
252b5132
RH		 7007 *s++ = ' ';
7008 memcpy (s, endstart, endstop - endstart);
7009 s += endstop - endstart;
7010 *s++ = ',';
7011 memcpy (s, varstart, varstop - varstart);
7012 s += varstop - varstart;
7013 *s = '\0';
7014 mri_assemble (buf);
7015
36759679 7016 /* bcc bottom. */
3882b010 7017 ex[0] = TOLOWER (extent);
252b5132
RH		 7018 ex[1] = '\0';
7019 if (up)
7020 sprintf (buf, "blt%s %s", ex, n->bottom);
7021 else
7022 sprintf (buf, "bgt%s %s", ex, n->bottom);
7023 mri_assemble (buf);
7024
7025 /* Put together the add or sub instruction used by ENDF. */
7026 s = buf;
7027 if (up)
7028 strcpy (s, "add");
7029 else
7030 strcpy (s, "sub");
7031 s += 3;
7032 if (qual != '\0')
3882b010 7033 *s++ = TOLOWER (qual);
252b5132
RH		 7034 *s++ = ' ';
7035 memcpy (s, bystart, bystop - bystart);
7036 s += bystop - bystart;
7037 *s++ = ',';
7038 memcpy (s, varstart, varstop - varstart);
7039 s += varstop - varstart;
7040 *s = '\0';
7041 n->incr = buf;
7042
7043 if (flag_mri)
7044 {
7045 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7046 ++input_line_pointer;
7047 }
7048
7049 demand_empty_rest_of_line ();
7050}
7051
7052/* Handle the MRI ENDF pseudo-op. */
7053
7054static void
31302357 7055s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7056{
7057 if (mri_control_stack == NULL
7058 || mri_control_stack->type != mri_for)
7059 {
7060 as_bad (_("endf without for"));
7061 ignore_rest_of_line ();
7062 return;
7063 }
7064
7065 colon (mri_control_stack->next);
7066
7067 mri_assemble (mri_control_stack->incr);
7068
7069 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7070 mri_assemble (mri_control_stack->incr);
7071
7072 free (mri_control_stack->incr);
7073
7074 colon (mri_control_stack->bottom);
7075
7076 pop_mri_control ();
7077
7078 if (flag_mri)
7079 {
7080 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7081 ++input_line_pointer;
7082 }
7083
7084 demand_empty_rest_of_line ();
7085}
7086
7087/* Handle the MRI REPEAT pseudo-op. */
7088
7089static void
31302357 7090s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7091{
7092 struct mri_control_info *n;
7093
7094 n = push_mri_control (mri_repeat);
7095 colon (n->top);
7096 if (flag_mri)
7097 {
7098 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7099 ++input_line_pointer;
7100 }
7101 demand_empty_rest_of_line ();
7102}
7103
7104/* Handle the MRI UNTIL pseudo-op. */
7105
7106static void
31302357 7107s_mri_until (int qual)
252b5132
RH		 7108{
7109 char *s;
7110
7111 if (mri_control_stack == NULL
7112 || mri_control_stack->type != mri_repeat)
7113 {
7114 as_bad (_("until without repeat"));
7115 ignore_rest_of_line ();
7116 return;
7117 }
7118
7119 colon (mri_control_stack->next);
7120
7121 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7122 ;
7123
7124 parse_mri_control_expression (s, qual, (const char *) NULL,
7125 mri_control_stack->top, '\0');
7126
7127 colon (mri_control_stack->bottom);
7128
7129 input_line_pointer = s;
7130
7131 pop_mri_control ();
7132
7133 if (flag_mri)
7134 {
7135 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7136 ++input_line_pointer;
7137 }
7138
7139 demand_empty_rest_of_line ();
7140}
7141
7142/* Handle the MRI WHILE pseudo-op. */
7143
7144static void
31302357 7145s_mri_while (int qual)
252b5132
RH		 7146{
7147 char *s;
7148
7149 struct mri_control_info *n;
7150
7151 s = input_line_pointer;
e1f44d10
NC		 7152 /* We only accept '*' as introduction of comments if preceded by white space
7153 or at first column of a line (I think this can't actually happen here?)
7154 This is important when assembling:
7155 while d0 <ne> 12(a0,d0*2) do
36759679 7156 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7157 while (! (is_end_of_line[(unsigned char) *s]
7158 || (flag_mri
7159 && *s == '*'
7160 && (s == input_line_pointer
7161 || *(s-1) == ' '
7162 || *(s-1) == '\t'))))
252b5132
RH		 7163 s++;
7164 --s;
7165 while (*s == ' ' || *s == '\t')
7166 --s;
7167 if (s - input_line_pointer > 1
7168 && s[-1] == '.')
7169 s -= 2;
7170 if (s - input_line_pointer < 2
7171 || strncasecmp (s - 1, "DO", 2) != 0)
7172 {
7173 as_bad (_("missing do"));
7174 ignore_rest_of_line ();
7175 return;
7176 }
7177
7178 n = push_mri_control (mri_while);
7179
7180 colon (n->next);
7181
7182 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7183 s[1] == '.' ? s[2] : '\0');
7184
7185 input_line_pointer = s + 1;
7186 if (*input_line_pointer == '.')
7187 input_line_pointer += 2;
7188
7189 if (flag_mri)
7190 {
7191 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7192 ++input_line_pointer;
7193 }
7194
7195 demand_empty_rest_of_line ();
7196}
7197
7198/* Handle the MRI ENDW pseudo-op. */
7199
7200static void
31302357 7201s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7202{
7203 char *buf;
7204
7205 if (mri_control_stack == NULL
7206 || mri_control_stack->type != mri_while)
7207 {
7208 as_bad (_("endw without while"));
7209 ignore_rest_of_line ();
7210 return;
7211 }
7212
7213 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7214 sprintf (buf, "bra %s", mri_control_stack->next);
7215 mri_assemble (buf);
7216 free (buf);
7217
7218 colon (mri_control_stack->bottom);
7219
7220 pop_mri_control ();
7221
7222 if (flag_mri)
7223 {
7224 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7225 ++input_line_pointer;
7226 }
7227
7228 demand_empty_rest_of_line ();
7229}
7230\f
266abb8f
NS		 7231/* Parse a .cpu directive. */
7232
7233static void
7234s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7235{
7236 char saved_char;
7237 char *name;
7238
7239 if (initialized)
7240 {
7241 as_bad (_("already assembled instructions"));
7242 ignore_rest_of_line ();
7243 return;
7244 }
7245
7246 name = input_line_pointer;
7247 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7248 input_line_pointer++;
7249 saved_char = *input_line_pointer;
7250 *input_line_pointer = 0;
7251
7252 m68k_set_cpu (name, 1, 0);
7253
7254 *input_line_pointer = saved_char;
7255 demand_empty_rest_of_line ();
7256 return;
7257}
7258
7259/* Parse a .arch directive. */
7260
7261static void
7262s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7263{
7264 char saved_char;
7265 char *name;
7266
7267 if (initialized)
7268 {
7269 as_bad (_("already assembled instructions"));
7270 ignore_rest_of_line ();
7271 return;
7272 }
7273
7274 name = input_line_pointer;
7275 while (*input_line_pointer && *input_line_pointer != ','
7276 && !ISSPACE (*input_line_pointer))
7277 input_line_pointer++;
7278 saved_char = *input_line_pointer;
7279 *input_line_pointer = 0;
7280
7281 if (m68k_set_arch (name, 1, 0))
7282 {
7283 /* Scan extensions. */
7284 do
7285 {
7286 *input_line_pointer++ = saved_char;
7287 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7288 break;
7289 name = input_line_pointer;
7290 while (*input_line_pointer && *input_line_pointer != ','
7291 && !ISSPACE (*input_line_pointer))
7292 input_line_pointer++;
7293 saved_char = *input_line_pointer;
7294 *input_line_pointer = 0;
7295 }
7296 while (m68k_set_extension (name, 1, 0));
7297 }
7298
7299 *input_line_pointer = saved_char;
7300 demand_empty_rest_of_line ();
7301 return;
7302}
7303\f
7304/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7305 if none is found, the caller is responsible for emitting an error
7306 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7307 cpu name, if it begins with a '6' (possibly skipping an intervening
7308 'c'. We also allow a 'c' in the same place. if NEGATED is
7309 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7310 the option is indeed negated. */
7311
7312static const struct m68k_cpu *
7313m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7314 int allow_m, int *negated)
7315{
7316 /* allow negated value? */
7317 if (negated)
7318 {
7319 *negated = 0;
7320
7321 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7322 {
7323 arg += 3;
7324 *negated = 1;
7325 }
7326 }
7327
7328 /* Remove 'm' or 'mc' prefix from 68k variants. */
7329 if (allow_m)
7330 {
7331 if (arg[0] == 'm')
7332 {
7333 if (arg[1] == '6')
7334 arg += 1;
7335 else if (arg[1] == 'c' && arg[2] == '6')
7336 arg += 2;
7337 }
7338 }
7339 else if (arg[0] == 'c' && arg[1] == '6')
7340 arg += 1;
7341
7342 for (; table->name; table++)
7343 if (!strcmp (arg, table->name))
2da12c60
NS		 7344 {
7345 if (table->alias < -1 || table->alias > 1)
7346 as_bad (_("`%s' is deprecated, use `%s'"),
7347 table->name, table[table->alias < 0 ? 1 : -1].name);
7348 return table;
7349 }
266abb8f
NS		 7350 return 0;
7351}
7352
bfbba8e4 7353/* Set the cpu, issuing errors if it is unrecognized. */
266abb8f
NS		 7354
7355static int
7356m68k_set_cpu (char const *name, int allow_m, int silent)
7357{
7358 const struct m68k_cpu *cpu;
7359
7360 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7361
7362 if (!cpu)
7363 {
7364 if (!silent)
7365 as_bad (_("cpu `%s' unrecognized"), name);
7366 return 0;
7367 }
266abb8f
NS		 7368 selected_cpu = cpu;
7369 return 1;
7370}
7371
bfbba8e4 7372/* Set the architecture, issuing errors if it is unrecognized. */
266abb8f
NS		 7373
7374static int
7375m68k_set_arch (char const *name, int allow_m, int silent)
7376{
7377 const struct m68k_cpu *arch;
7378
7379 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7380
7381 if (!arch)
7382 {
7383 if (!silent)
7384 as_bad (_("architecture `%s' unrecognized"), name);
7385 return 0;
7386 }
266abb8f
NS		 7387 selected_arch = arch;
7388 return 1;
7389}
7390
7391/* Set the architecture extension, issuing errors if it is
7392 unrecognized, or invalid */
7393
7394static int
7395m68k_set_extension (char const *name, int allow_m, int silent)
7396{
7397 int negated;
7398 const struct m68k_cpu *ext;
7399
7400 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7401
7402 if (!ext)
7403 {
7404 if (!silent)
7405 as_bad (_("extension `%s' unrecognized"), name);
7406 return 0;
7407 }
7408
7409 if (negated)
7410 not_current_architecture |= ext->arch;
7411 else
7412 current_architecture |= ext->arch;
7413 return 1;
7414}
7415
31302357
AS		 7416/* md_parse_option
7417 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7418 */
252b5132
RH		 7419
7420#ifdef OBJ_ELF
5a38dc70 7421const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7422#else
5a38dc70 7423const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7424#endif
7425
7426struct option md_longopts[] = {
7427#define OPTION_PIC (OPTION_MD_BASE)
7428 {"pic", no_argument, NULL, OPTION_PIC},
7429#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7430 {"register-prefix-optional", no_argument, NULL,
7431 OPTION_REGISTER_PREFIX_OPTIONAL},
7432#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7433 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7434#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7435 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7436#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7437 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7438#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7439 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7440#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7441 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7442#define OPTION_PCREL (OPTION_MD_BASE + 7)
7443 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7444 {NULL, no_argument, NULL, 0}
7445};
bc805888 7446size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7447
7448int
31302357 7449md_parse_option (int c, char *arg)
252b5132
RH		 7450{
7451 switch (c)
7452 {
7453 case 'l': /* -l means keep external to 2 bit offset
36759679 7454 rather than 16 bit one. */
252b5132
RH		 7455 flag_short_refs = 1;
7456 break;
7457
7458 case 'S': /* -S means that jbsr's always turn into
7459 jsr's. */
7460 flag_long_jumps = 1;
7461 break;
7462
28e7409f
NC		 7463 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7464 branches into absolute jumps. */
7465 flag_keep_pcrel = 1;
7466 break;
7467
252b5132
RH		 7468 case OPTION_PIC:
7469 case 'k':
7470 flag_want_pic = 1;
36759679 7471 break; /* -pic, Position Independent Code. */
252b5132
RH		 7472
7473 case OPTION_REGISTER_PREFIX_OPTIONAL:
7474 flag_reg_prefix_optional = 1;
7475 reg_prefix_optional_seen = 1;
7476 break;
7477
7478 /* -V: SVR4 argument to print version ID. */
7479 case 'V':
7480 print_version_id ();
7481 break;
7482
7483 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7484 should be emitted or not. FIXME: Not implemented. */
7485 case 'Q':
7486 break;
7487
7488 case OPTION_BITWISE_OR:
7489 {
7490 char *n, *t;
7491 const char *s;
7492
7493 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7494 t = n;
7495 for (s = m68k_comment_chars; *s != '\0'; s++)
7496 if (*s != '|')
7497 *t++ = *s;
7498 *t = '\0';
7499 m68k_comment_chars = n;
7500 }
7501 break;
7502
7503 case OPTION_BASE_SIZE_DEFAULT_16:
7504 m68k_index_width_default = SIZE_WORD;
7505 break;
7506
7507 case OPTION_BASE_SIZE_DEFAULT_32:
7508 m68k_index_width_default = SIZE_LONG;
7509 break;
7510
7511 case OPTION_DISP_SIZE_DEFAULT_16:
7512 m68k_rel32 = 0;
7513 m68k_rel32_from_cmdline = 1;
7514 break;
7515
7516 case OPTION_DISP_SIZE_DEFAULT_32:
7517 m68k_rel32 = 1;
7518 m68k_rel32_from_cmdline = 1;
7519 break;
7520
266abb8f
NS		 7521 case 'A':
7522#if WARN_DEPRECATED
7523 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7524 arg, arg));
7525#endif
7526 /* Intentional fall-through. */
7527 case 'm':
7528 if (!strncmp (arg, "arch=", 5))
7529 m68k_set_arch (arg + 5, 1, 0);
7530 else if (!strncmp (arg, "cpu=", 4))
7531 m68k_set_cpu (arg + 4, 1, 0);
7532 else if (m68k_set_extension (arg, 0, 1))
7533 ;
0b2e31dc
NS		 7534 else if (m68k_set_arch (arg, 0, 1))
7535 ;
266abb8f
NS		 7536 else if (m68k_set_cpu (arg, 0, 1))
7537 ;
7538 else
7539 return 0;
7540 break;
7541
252b5132
RH		 7542 default:
7543 return 0;
7544 }
7545
7546 return 1;
7547}
7548
266abb8f
NS		 7549/* Setup tables from the selected arch and/or cpu */
7550
7551static void
7552m68k_init_arch (void)
7553{
266abb8f
NS		 7554 if (not_current_architecture & current_architecture)
7555 {
7556 as_bad (_("architecture features both enabled and disabled"));
7557 not_current_architecture &= ~current_architecture;
7558 }
7559 if (selected_arch)
2da12c60
NS		 7560 {
7561 current_architecture |= selected_arch->arch;
7562 control_regs = selected_arch->control_regs;
7563 }
0b2e31dc
NS		 7564 else
7565 current_architecture |= selected_cpu->arch;
0b2e31dc 7566
2da12c60
NS		 7567 current_architecture &= ~not_current_architecture;
7568
377260ba
NS		 7569 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7570 {
7571 /* Determine which float is really meant. */
7572 if (current_architecture & (m68k_mask & ~m68881))
7573 current_architecture ^= cfloat;
7574 else
7575 current_architecture ^= m68881;
7576 }
7577
0b2e31dc 7578 if (selected_cpu)
266abb8f 7579 {
2da12c60 7580 control_regs = selected_cpu->control_regs;
0b2e31dc 7581 if (current_architecture & ~selected_cpu->arch)
266abb8f 7582 {
0b2e31dc
NS		 7583 as_bad (_("selected processor does not have all features of selected architecture"));
7584 current_architecture
7585 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7586 }
7587 }
266abb8f 7588
266abb8f
NS		 7589 if ((current_architecture & m68k_mask)
7590 && (current_architecture & ~m68k_mask))
7591 {
7592 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7593 if (current_architecture & m68k_mask)
266abb8f
NS		 7594 current_architecture &= m68k_mask;
7595 else
7596 current_architecture &= ~m68k_mask;
7597 }
7598
7599 /* Permit m68881 specification with all cpus; those that can't work
7600 with a coprocessor could be doing emulation. */
7601 if (current_architecture & m68851)
7602 {
7603 if (current_architecture & m68040)
7604 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7605 }
7606 /* What other incompatibilities could we check for? */
7607
266abb8f
NS		 7608 if (cpu_of_arch (current_architecture) < m68020
7609 || arch_coldfire_p (current_architecture))
7610 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7611
7612 initialized = 1;
7613}
7614
252b5132 7615void
31302357 7616md_show_usage (FILE *stream)
252b5132 7617{
76f57f3a 7618 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7619 int i;
7620 unsigned int default_arch;
76f57f3a 7621
8a104df9 7622 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7623 if (*default_cpu == 'm')
7624 default_cpu++;
266abb8f 7625 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7626 {
266abb8f 7627 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7628 {
266abb8f 7629 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7630 while (m68k_cpus[i].alias > 0)
7631 i--;
7632 while (m68k_cpus[i].alias < 0)
7633 i++;
7634 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7635 }
7636 }
7637
bc805888 7638 fprintf (stream, _("\
266abb8f
NS		 7639-march=<arch> set architecture\n\
7640-mcpu=<cpu> set cpu [default %s]\n\
7641"), default_cpu);
7642 for (i = 0; m68k_extensions[i].name; i++)
7643 fprintf (stream, _("\
0b2e31dc
NS		 7644-m[no-]%-16s enable/disable%s architecture extension\n\
7645"), m68k_extensions[i].name,
7646 m68k_extensions[i].alias > 0 ? " ColdFire"
7647 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7648
bc805888 7649 fprintf (stream, _("\
266abb8f 7650-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7651-pic, -k generate position independent code\n\
7652-S turn jbsr into jsr\n\
28e7409f 7653--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7654--register-prefix-optional\n\
7655 recognize register names without prefix character\n\
266abb8f 7656--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7657--base-size-default-16 base reg without size is 16 bits\n\
7658--base-size-default-32 base reg without size is 32 bits (default)\n\
7659--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7660--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7661"));
7662
7663 fprintf (stream, _("Architecture variants are: "));
7664 for (i = 0; m68k_archs[i].name; i++)
7665 {
7666 if (i)
7667 fprintf (stream, " | ");
7668 fprintf (stream, m68k_archs[i].name);
7669 }
7670 fprintf (stream, "\n");
7671
7672 fprintf (stream, _("Processor variants are: "));
7673 for (i = 0; m68k_cpus[i].name; i++)
7674 {
7675 if (i)
7676 fprintf (stream, " | ");
7677 fprintf (stream, m68k_cpus[i].name);
7678 }
7679 fprintf (stream, _("\n"));
252b5132
RH		 7680}
7681\f
7682#ifdef TEST2
7683
7684/* TEST2: Test md_assemble() */
36759679
NC		 7685/* Warning, this routine probably doesn't work anymore. */
7686int
31302357 7687main (void)
252b5132
RH		 7688{
7689 struct m68k_it the_ins;
7690 char buf[120];
7691 char *cp;
7692 int n;
7693
7694 m68k_ip_begin ();
7695 for (;;)
7696 {
7697 if (!gets (buf) || !*buf)
7698 break;
7699 if (buf[0] == '|' || buf[1] == '.')
7700 continue;
7701 for (cp = buf; *cp; cp++)
7702 if (*cp == '\t')
7703 *cp = ' ';
7704 if (is_label (buf))
7705 continue;
7706 memset (&the_ins, '\0', sizeof (the_ins));
7707 m68k_ip (&the_ins, buf);
7708 if (the_ins.error)
7709 {
7710 printf (_("Error %s in %s\n"), the_ins.error, buf);
7711 }
7712 else
7713 {
7714 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7715 for (n = 0; n < the_ins.numo; n++)
7716 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7717 printf (" ");
7718 print_the_insn (&the_ins.opcode[0], stdout);
7719 (void) putchar ('\n');
7720 }
7721 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7722 {
7723 if (the_ins.operands[n].error)
7724 {
7725 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7726 continue;
7727 }
31302357
AS		 7728 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7729 the_ins.operands[n].reg);
252b5132 7730 if (the_ins.operands[n].b_const)
31302357
AS		 7731 printf ("Constant: '%.*s', ",
7732 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7733 the_ins.operands[n].b_const);
7734 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7735 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7736 if (the_ins.operands[n].b_iadd)
31302357
AS		 7737 printf ("Iadd: '%.*s',",
7738 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7739 the_ins.operands[n].b_iadd);
7740 putchar ('\n');
252b5132
RH		 7741 }
7742 }
7743 m68k_ip_end ();
7744 return 0;
7745}
7746
31302357
AS		 7747int
7748is_label (char *str)
252b5132
RH		 7749{
7750 while (*str == ' ')
7751 str++;
7752 while (*str && *str != ' ')
7753 str++;
7754 if (str[-1] == ':' || str[1] == '=')
7755 return 1;
7756 return 0;
7757}
7758
7759#endif
7760
7761/* Possible states for relaxation:
7762
7763 0 0 branch offset byte (bra, etc)
7764 0 1 word
7765 0 2 long
7766
7767 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7768 1 1 word
7769 1 2 long
7770
7771 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7772 2 1 word-long
7773 2 2 long-word
7774 2 3 long-long
7775
7776 */
7777
7778/* We have no need to default values of symbols. */
7779
252b5132 7780symbolS *
31302357 7781md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7782{
7783 return 0;
7784}
7785
7786/* Round up a section size to the appropriate boundary. */
7787valueT
31302357 7788md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7789{
7790#ifdef OBJ_AOUT
252b5132
RH		 7791 /* For a.out, force the section size to be aligned. If we don't do
7792 this, BFD will align it for us, but it will not write out the
7793 final bytes of the section. This may be a bug in BFD, but it is
7794 easier to fix it here since that is how the other a.out targets
7795 work. */
7796 int align;
7797
7798 align = bfd_get_section_alignment (stdoutput, segment);
7799 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7800#endif
7801
7802 return size;
7803}
7804
7805/* Exactly what point is a PC-relative offset relative TO?
7806 On the 68k, it is relative to the address of the first extension
7807 word. The difference between the addresses of the offset and the
92774660 7808 first extension word is stored in fx_pcrel_adjust. */
252b5132 7809long
31302357 7810md_pcrel_from (fixS *fixP)
252b5132
RH		 7811{
7812 int adjust;
7813
8390138c
AS		 7814 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7815 sign extend the value here. */
7816 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7817 if (adjust == 64)
7818 adjust = -1;
7819 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7820}
7821
0d96863f 7822#ifdef OBJ_ELF
8a104df9 7823void
31302357 7824m68k_elf_final_processing (void)
0d96863f 7825{
266abb8f
NS		 7826 unsigned flags = 0;
7827
238d258f 7828 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7829 flags |= EF_M68K_CFV4E;
7830 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7831 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7832 flags |= EF_M68K_CPU32;
7833 else if (cpu_of_arch (current_architecture) & fido_a)
7834 flags |= EF_M68K_FIDO;
8a104df9
KH		 7835 else if ((cpu_of_arch (current_architecture) & m68000up)
7836 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7837 flags |= EF_M68K_M68000;
7838
7839 if (current_architecture & mcfisa_a)
7840 {
0b2e31dc
NS		 7841 static const unsigned isa_features[][2] =
7842 {
9a2e615a 7843 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7844 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7845 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7846 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7847 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7848 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
8d100c32 7849 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
0b2e31dc
NS		 7850 {0,0},
7851 };
7852 static const unsigned mac_features[][2] =
7853 {
c694fd50
KH		 7854 {EF_M68K_CF_MAC, mcfmac},
7855 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7856 {0,0},
7857 };
7858 unsigned ix;
7859 unsigned pattern;
266abb8f 7860
0b2e31dc 7861 pattern = (current_architecture
9a2e615a 7862 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7863 for (ix = 0; isa_features[ix][1]; ix++)
7864 {
7865 if (pattern == isa_features[ix][1])
7866 {
7867 flags |= isa_features[ix][0];
7868 break;
7869 }
7870 }
7871 if (!isa_features[ix][1])
7872 {
7873 cf_bad:
7874 as_warn (_("Not a defined coldfire architecture"));
7875 }
7876 else
7877 {
7878 if (current_architecture & cfloat)
c694fd50 7879 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7880
0b2e31dc
NS		 7881 pattern = current_architecture & (mcfmac|mcfemac);
7882 if (pattern)
7883 {
7884 for (ix = 0; mac_features[ix][1]; ix++)
7885 {
7886 if (pattern == mac_features[ix][1])
7887 {
7888 flags |= mac_features[ix][0];
7889 break;
7890 }
7891 }
7892 if (!mac_features[ix][1])
7893 goto cf_bad;
7894 }
7895 }
266abb8f
NS		 7896 }
7897 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f 7898}
cf869cce
NC		 7899
7900/* Parse @TLSLDO and return the desired relocation. */
7901static bfd_reloc_code_real_type
7902m68k_elf_suffix (char **str_p, expressionS *exp_p)
7903{
7904 char ident[20];
7905 char *str = *str_p;
7906 char *str2;
7907 int ch;
7908 int len;
7909
7910 if (*str++ != '@')
7911 return BFD_RELOC_UNUSED;
7912
7913 for (ch = *str, str2 = ident;
7914 (str2 < ident + sizeof (ident) - 1
7915 && (ISALNUM (ch) || ch == '@'));
7916 ch = *++str)
7917 {
7918 *str2++ = ch;
7919 }
7920
7921 *str2 = '\0';
7922 len = str2 - ident;
7923
7924 if (strncmp (ident, "TLSLDO", 6) == 0
7925 && len == 6)
7926 {
7927 /* Now check for identifier@suffix+constant. */
7928 if (*str == '-' || *str == '+')
7929 {
7930 char *orig_line = input_line_pointer;
7931 expressionS new_exp;
7932
7933 input_line_pointer = str;
7934 expression (&new_exp);
7935 if (new_exp.X_op == O_constant)
7936 {
7937 exp_p->X_add_number += new_exp.X_add_number;
7938 str = input_line_pointer;
7939 }
7940
7941 if (&input_line_pointer != str_p)
7942 input_line_pointer = orig_line;
7943 }
7944 *str_p = str;
7945
7946 return BFD_RELOC_68K_TLS_LDO32;
7947 }
7948
7949 return BFD_RELOC_UNUSED;
7950}
7951
7952/* Handles .long <tls_symbol>+0x8000 debug info.
7953 Clobbers input_line_pointer, checks end-of-line.
7954 Adapted from tc-ppc.c:ppc_elf_cons. */
7955static void
7956m68k_elf_cons (int nbytes /* 4=.long */)
7957{
7958 if (is_it_end_of_statement ())
7959 {
7960 demand_empty_rest_of_line ();
7961 return;
7962 }
7963
7964 do
7965 {
7966 expressionS exp;
7967 bfd_reloc_code_real_type reloc;
7968
7969 expression (&exp);
7970 if (exp.X_op == O_symbol
7971 && *input_line_pointer == '@'
7972 && (reloc = m68k_elf_suffix (&input_line_pointer,
7973 &exp)) != BFD_RELOC_UNUSED)
7974 {
7975 reloc_howto_type *reloc_howto;
7976 int size;
7977
7978 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
7979 size = bfd_get_reloc_size (reloc_howto);
7980
7981 if (size > nbytes)
7982 {
7983 as_bad (_("%s relocations do not fit in %d bytes\n"),
7984 reloc_howto->name, nbytes);
7985 }
7986 else
7987 {
7988 char *p;
7989 int offset;
7990
7991 p = frag_more (nbytes);
7992 offset = 0;
7993 if (target_big_endian)
7994 offset = nbytes - size;
7995 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7996 &exp, 0, reloc);
7997 }
7998 }
7999 else
8000 emit_expr (&exp, (unsigned int) nbytes);
8001 }
8002 while (*input_line_pointer++ == ',');
8003
8004 /* Put terminator back into stream. */
8005 input_line_pointer--;
8006 demand_empty_rest_of_line ();
8007}
0d96863f 8008#endif
c04898f8
AS		 8009
8010int
1df69f4f 8011tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 8012{
8013 unsigned int regnum;
8014 static const char *const regnames[] =
8015 {
8016 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8017 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8018 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8019 "pc"
8020 };
8021
8022 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
8023 if (strcmp (regname, regnames[regnum]) == 0)
8024 return regnum;
8025
8026 return -1;
8027}
8028
8029void
8030tc_m68k_frame_initial_instructions (void)
8031{
8032 static int sp_regno = -1;
8033
8034 if (sp_regno < 0)
8035 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8036
8037 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8038 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
8039}
GDB Binutils - Deliverables
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