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* config/tc-m68k.c (mcf51qe_ctrl): Define 51QE control registers.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
22184a77 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
ec2655a6 9 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
252b5132
RH		 73/* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
92774660 75 references. Not implemented. For ELF there are other means
252b5132
RH		 76 to denote pic relocations. */
77int flag_want_pic;
78
36759679
NC		 79static int flag_short_refs; /* -l option. */
80static int flag_long_jumps; /* -S option. */
28e7409f 81static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 82
83#ifdef REGISTER_PREFIX_OPTIONAL
84int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85#else
86int flag_reg_prefix_optional;
87#endif
88
89/* Whether --register-prefix-optional was used on the command line. */
90static int reg_prefix_optional_seen;
91
92/* The floating point coprocessor to use by default. */
93static enum m68k_register m68k_float_copnum = COP1;
94
95/* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97static int m68k_abspcadd;
98
99/* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101static int m68k_quick = 1;
102
103/* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106static int m68k_rel32 = 1;
107
108/* This is non-zero if m68k_rel32 was set from the command line. */
109static int m68k_rel32_from_cmdline;
110
111/* The default width to use for an index register when using a base
112 displacement. */
113static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115/* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
252b5132
RH		 118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
60fed2d3
NC		 135/* Pointer to list holding the opcodes sorted by name. */
136static struct m68k_opcode const ** m68k_sorted_opcodes;
137
36759679
NC		 138/* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
252b5132
RH		 140static struct obstack robyn;
141
252b5132
RH		 142struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153#define gettwo(x) (((x)->m_opcode)&0xffff)
154
2da12c60
NS		 155static const enum m68k_register m68000_ctrl[] = { 0 };
156static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 157 SFC, DFC, USP, VBR,
158 0
159};
2da12c60 160static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163};
2da12c60 164static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168};
2da12c60 169static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173};
2da12c60 174static const enum m68k_register mcf_ctrl[] = {
3e602632 175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178};
f75192f2
KH		 179static const enum m68k_register mcf51qe_ctrl[] = {
180 VBR,
181 0
182};
78336706
NS		 183static const enum m68k_register mcf5206_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 185 0
186};
2da12c60 187static const enum m68k_register mcf5208_ctrl[] = {
78336706 188 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 189 0
190};
96e0bbcc 191static const enum m68k_register mcf5210a_ctrl[] = {
78336706 192 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 193 0
194};
2da12c60 195static const enum m68k_register mcf5213_ctrl[] = {
78336706 196 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 197 0
198};
2da12c60 199static const enum m68k_register mcf5216_ctrl[] = {
78336706 200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 201 0
202};
d5be9593
NS		 203static const enum m68k_register mcf52223_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206};
96e0bbcc 207static const enum m68k_register mcf52235_ctrl[] = {
78336706 208 VBR, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 209 0
210};
211static const enum m68k_register mcf5225_ctrl[] = {
78336706 212 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 213 0
214};
2da12c60 215static const enum m68k_register mcf5235_ctrl[] = {
78336706 216 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 217 0
218};
2da12c60 219static const enum m68k_register mcf5249_ctrl[] = {
78336706 220 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 221 0
222};
2da12c60
NS		 223static const enum m68k_register mcf5250_ctrl[] = {
224 VBR,
225 0
226};
d5be9593
NS		 227static const enum m68k_register mcf5253_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
229 0
230};
2da12c60 231static const enum m68k_register mcf5271_ctrl[] = {
78336706 232 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 233 0
234};
235static const enum m68k_register mcf5272_ctrl[] = {
78336706 236 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 237 0
238};
239static const enum m68k_register mcf5275_ctrl[] = {
78336706 240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 241 0
242};
243static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 244 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
245 0
246};
247static const enum m68k_register mcf5307_ctrl[] = {
248 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 249 0
250};
251static const enum m68k_register mcf5329_ctrl[] = {
78336706 252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 253 0
254};
255static const enum m68k_register mcf5373_ctrl[] = {
78336706 256 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 257 0
258};
259static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 260 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
261 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
262 MBAR, SECMBAR,
263 MPCR /* Multiprocessor Control register */,
264 EDRAMBAR /* Embedded DRAM Base Address Register */,
265 /* Permutation control registers. */
3e602632
NC		 266 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
267 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 268 /* Legacy names */
269 TC /* ASID */, BUSCR /* MMUBAR */,
270 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
271 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 272 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 273 0
274};
9a2e615a
NS		 275static const enum m68k_register mcf54455_ctrl[] = {
276 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
277 VBR, PC, RAMBAR1, MBAR,
278 /* Legacy names */
279 TC /* ASID */, BUSCR /* MMUBAR */,
280 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
282 0
283};
a8e24a56
NS		 284static const enum m68k_register mcf5475_ctrl[] = {
285 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
286 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
287 /* Legacy names */
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 290 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 291 0
292};
293static const enum m68k_register mcf5485_ctrl[] = {
294 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
295 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
296 /* Legacy names */
297 TC /* ASID */, BUSCR /* MMUBAR */,
298 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 299 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 300 0
301};
f7ec513b
KH		 302static const enum m68k_register fido_ctrl[] = {
303 SFC, DFC, USP, VBR, CAC, MBB,
304 0
305};
2da12c60 306#define cpu32_ctrl m68010_ctrl
252b5132
RH		 307
308static const enum m68k_register *control_regs;
309
36759679 310/* Internal form of a 68020 instruction. */
252b5132
RH		 311struct m68k_it
312{
313 const char *error;
36759679 314 const char *args; /* List of opcode info. */
252b5132
RH		 315 int numargs;
316
36759679 317 int numo; /* Number of shorts in opcode. */
252b5132
RH		 318 short opcode[11];
319
320 struct m68k_op operands[6];
321
36759679 322 int nexp; /* Number of exprs in use. */
252b5132
RH		 323 struct m68k_exp exprs[4];
324
36759679 325 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 326 struct
327 {
36759679 328 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 329 symbolS *fadd;
330 offsetT foff;
331 int fragty;
332 }
333 fragb[4];
334
36759679 335 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 336 struct
337 {
338 int n;
339 expressionS exp;
340 char wid;
341 char pcrel;
342 /* In a pc relative address the difference between the address
343 of the offset and the address that the offset is relative
344 to. This depends on the addressing mode. Basically this
345 is the value to put in the offset field to address the
346 first byte of the offset, without regarding the special
347 significance of some values (in the branch instruction, for
348 example). */
349 int pcrel_fix;
350#ifdef OBJ_ELF
351 /* Whether this expression needs special pic relocation, and if
352 so, which. */
353 enum pic_relocation pic_reloc;
354#endif
355 }
36759679 356 reloc[5]; /* Five is enough??? */
252b5132
RH		 357};
358
9840d27e 359#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 360#define float_of_arch(x) ((x) & mfloat)
361#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 362#define arch_coldfire_p(x) ((x) & mcfisa_a)
363#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 364
36759679 365/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 366#define HAVE_LONG_DISP(x) \
367 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
368#define HAVE_LONG_CALL(x) \
369 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
370#define HAVE_LONG_COND(x) \
371 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
372#define HAVE_LONG_BRANCH(x) \
373 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
252b5132 374
36759679 375static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 376
377#define op(ex) ((ex)->exp.X_op)
378#define adds(ex) ((ex)->exp.X_add_symbol)
379#define subs(ex) ((ex)->exp.X_op_symbol)
380#define offs(ex) ((ex)->exp.X_add_number)
381
36759679 382/* Macros for adding things to the m68k_it struct. */
31302357 383#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 384
36759679
NC		 385/* Like addword, but goes BEFORE general operands. */
386
252b5132 387static void
31302357 388insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 389{
390 int z;
07726851 391 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 392 the_ins.opcode[z] = the_ins.opcode[z - 1];
393 for (z = 0; z < the_ins.nrel; z++)
394 the_ins.reloc[z].n += 2;
252b5132
RH		 395 for (z = 0; z < the_ins.nfrag; z++)
396 the_ins.fragb[z].fragoff++;
8a104df9 397 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 398 the_ins.numo++;
399}
400
401/* The numo+1 kludge is so we can hit the low order byte of the prev word.
402 Blecch. */
403static void
31302357 404add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 405{
31302357
AS		 406 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
407 ? the_ins.numo * 2 - 1
408 : (width == 'b'
409 ? the_ins.numo * 2 + 1
410 : the_ins.numo * 2));
252b5132
RH		 411 the_ins.reloc[the_ins.nrel].exp = exp->exp;
412 the_ins.reloc[the_ins.nrel].wid = width;
413 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
414#ifdef OBJ_ELF
415 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
416#endif
417 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
418}
419
420/* Cause an extra frag to be generated here, inserting up to 10 bytes
421 (that value is chosen in the frag_var call in md_assemble). TYPE
422 is the subtype of the frag to be generated; its primary type is
423 rs_machine_dependent.
424
425 The TYPE parameter is also used by md_convert_frag_1 and
426 md_estimate_size_before_relax. The appropriate type of fixup will
427 be emitted by md_convert_frag_1.
428
429 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
430static void
31302357 431add_frag (symbolS *add, offsetT off, int type)
252b5132 432{
8a104df9
KH		 433 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
434 the_ins.fragb[the_ins.nfrag].fadd = add;
435 the_ins.fragb[the_ins.nfrag].foff = off;
436 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 437}
438
439#define isvar(ex) \
440 (op (ex) != O_constant && op (ex) != O_big)
441
31302357
AS		 442static char *crack_operand (char *str, struct m68k_op *opP);
443static int get_num (struct m68k_exp *exp, int ok);
444static int reverse_16_bits (int in);
445static int reverse_8_bits (int in);
446static void install_gen_operand (int mode, int val);
447static void install_operand (int mode, int val);
448static void s_bss (int);
449static void s_data1 (int);
450static void s_data2 (int);
451static void s_even (int);
452static void s_proc (int);
453static void s_chip (int);
454static void s_fopt (int);
455static void s_opt (int);
456static void s_reg (int);
457static void s_restore (int);
458static void s_save (int);
459static void s_mri_if (int);
460static void s_mri_else (int);
461static void s_mri_endi (int);
462static void s_mri_break (int);
463static void s_mri_next (int);
464static void s_mri_for (int);
465static void s_mri_endf (int);
466static void s_mri_repeat (int);
467static void s_mri_until (int);
468static void s_mri_while (int);
469static void s_mri_endw (int);
266abb8f
NS		 470static void s_m68k_cpu (int);
471static void s_m68k_arch (int);
472
473struct m68k_cpu
474{
475 unsigned long arch; /* Architecture features. */
2da12c60 476 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 477 const char *name; /* Name */
0b2e31dc
NS		 478 int alias; /* Alias for a cannonical name. If 1, then
479 succeeds canonical name, if -1 then
480 succeeds canonical name, if <-1 ||>1 this is a
481 deprecated name, and the next/previous name
482 should be used. */
266abb8f 483};
252b5132 484
266abb8f
NS		 485/* We hold flags for features explicitly enabled and explicitly
486 disabled. */
252b5132 487static int current_architecture;
266abb8f 488static int not_current_architecture;
266abb8f
NS		 489static const struct m68k_cpu *selected_arch;
490static const struct m68k_cpu *selected_cpu;
491static int initialized;
252b5132 492
266abb8f
NS		 493/* Architecture models. */
494static const struct m68k_cpu m68k_archs[] =
495{
2da12c60
NS		 496 {m68000, m68000_ctrl, "68000", 0},
497 {m68010, m68010_ctrl, "68010", 0},
498 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
499 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
500 {m68040, m68040_ctrl, "68040", 0},
501 {m68060, m68060_ctrl, "68060", 0},
502 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 503 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 504 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
505 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
506 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 507 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 508 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
509 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 510 {0,0,NULL, 0}
511};
252b5132 512
0b2e31dc
NS		 513/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
514 for either. */
266abb8f
NS		 515static const struct m68k_cpu m68k_extensions[] =
516{
2da12c60
NS		 517 {m68851, NULL, "68851", -1},
518 {m68881, NULL, "68881", -1},
519 {m68881, NULL, "68882", -1},
0b2e31dc 520
2da12c60 521 {cfloat|m68881, NULL, "float", 0},
266abb8f 522
2da12c60
NS		 523 {mcfhwdiv, NULL, "div", 1},
524 {mcfusp, NULL, "usp", 1},
525 {mcfmac, NULL, "mac", 1},
526 {mcfemac, NULL, "emac", 1},
266abb8f 527
2da12c60 528 {0,NULL,NULL, 0}
266abb8f
NS		 529};
530
531/* Processor list */
532static const struct m68k_cpu m68k_cpus[] =
533{
2da12c60
NS		 534 {m68000, m68000_ctrl, "68000", 0},
535 {m68000, m68000_ctrl, "68ec000", 1},
536 {m68000, m68000_ctrl, "68hc000", 1},
537 {m68000, m68000_ctrl, "68hc001", 1},
538 {m68000, m68000_ctrl, "68008", 1},
539 {m68000, m68000_ctrl, "68302", 1},
540 {m68000, m68000_ctrl, "68306", 1},
541 {m68000, m68000_ctrl, "68307", 1},
542 {m68000, m68000_ctrl, "68322", 1},
543 {m68000, m68000_ctrl, "68356", 1},
544 {m68010, m68010_ctrl, "68010", 0},
545 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
546 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
547 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
548 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
549 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
550 {m68040, m68040_ctrl, "68040", 0},
551 {m68040, m68040_ctrl, "68ec040", 1},
552 {m68060, m68060_ctrl, "68060", 0},
553 {m68060, m68060_ctrl, "68ec060", 1},
554
555 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
556 {cpu32|m68881, cpu32_ctrl, "68330", 1},
557 {cpu32|m68881, cpu32_ctrl, "68331", 1},
558 {cpu32|m68881, cpu32_ctrl, "68332", 1},
559 {cpu32|m68881, cpu32_ctrl, "68333", 1},
560 {cpu32|m68881, cpu32_ctrl, "68334", 1},
561 {cpu32|m68881, cpu32_ctrl, "68336", 1},
562 {cpu32|m68881, cpu32_ctrl, "68340", 1},
563 {cpu32|m68881, cpu32_ctrl, "68341", 1},
564 {cpu32|m68881, cpu32_ctrl, "68349", 1},
565 {cpu32|m68881, cpu32_ctrl, "68360", 1},
f75192f2
KH		 566
567 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
2da12c60
NS		 568
569 {mcfisa_a, mcf_ctrl, "5200", 0},
570 {mcfisa_a, mcf_ctrl, "5202", 1},
571 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 572 {mcfisa_a, mcf5206_ctrl, "5206", 1},
2da12c60 573
78336706 574 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
2da12c60
NS		 575
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
578
96e0bbcc
NS		 579 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
580 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
581
2da12c60
NS		 582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
583 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
585
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
589
d5be9593
NS		 590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
591 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
592
96e0bbcc
NS		 593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
597
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
600
2da12c60
NS		 601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
602 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
606
607 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
608 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 609 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
2da12c60
NS		 610
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
613
614 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
615
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
617 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
618
619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
623
78336706 624 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
2da12c60
NS		 625
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
630
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
634
635 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
9a2e615a
NS		 636
637 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
638 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
639 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
640 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
641 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
642 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
2da12c60 643
a8e24a56
NS		 644 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
645 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
646 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
647 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
648 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
649 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
650 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
2da12c60 651
a8e24a56
NS		 652 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
653 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
654 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
655 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
656 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
657 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
658 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
2da12c60 659
b3768379 660 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 661 {fido_a, fido_ctrl, "fido", 1},
9840d27e 662
2da12c60 663 {0,NULL,NULL, 0}
dc84e067 664 };
252b5132 665
266abb8f
NS		 666static const struct m68k_cpu *m68k_lookup_cpu
667(const char *, const struct m68k_cpu *, int, int *);
668static int m68k_set_arch (const char *, int, int);
669static int m68k_set_cpu (const char *, int, int);
670static int m68k_set_extension (const char *, int, int);
671static void m68k_init_arch (void);
252b5132 672
151337e8
NC		 673/* This is the assembler relaxation table for m68k. m68k is a rich CISC
674 architecture and we have a lot of relaxation modes. */
252b5132 675
151337e8
NC		 676/* Macros used in the relaxation code. */
677#define TAB(x,y) (((x) << 2) + (y))
678#define TABTYPE(x) ((x) >> 2)
679
680/* Relaxation states. */
681#define BYTE 0
682#define SHORT 1
683#define LONG 2
684#define SZ_UNDEF 3
685
686/* Here are all the relaxation modes we support. First we can relax ordinary
687 branches. On 68020 and higher and on CPU32 all branch instructions take
688 three forms, so on these CPUs all branches always remain as such. When we
689 have to expand to the LONG form on a 68000, though, we substitute an
690 absolute jump instead. This is a direct replacement for unconditional
691 branches and a branch over a jump for conditional branches. However, if the
692 user requires PIC and disables this with --pcrel, we can only relax between
693 BYTE and SHORT forms, punting if that isn't enough. This gives us four
694 different relaxation modes for branches: */
695
36759679
NC		 696#define BRANCHBWL 0 /* Branch byte, word, or long. */
697#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
698#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
699#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 700
701/* We also relax coprocessor branches and DBcc's. All CPUs that support
702 coprocessor branches support them in word and long forms, so we have only
703 one relaxation mode for them. DBcc's are word only on all CPUs. We can
704 relax them to the LONG form with a branch-around sequence. This sequence
705 can use a long branch (if available) or an absolute jump (if acceptable).
706 This gives us two relaxation modes. If long branches are not available and
707 absolute jumps are not acceptable, we don't relax DBcc's. */
708
36759679
NC		 709#define FBRANCH 4 /* Coprocessor branch. */
710#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
711#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 712
713/* That's all for instruction relaxation. However, we also relax PC-relative
714 operands. Specifically, we have three operand relaxation modes. On the
715 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
716 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
717 two. Also PC+displacement+index operands in their simple form (with a non-
718 suppressed index without memory indirection) are supported on all CPUs, but
719 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
720 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
721 form of the PC+displacement+index operand. Finally, some absolute operands
722 can be relaxed down to 16-bit PC-relative. */
723
36759679
NC		 724#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
725#define PCINDEX 8 /* PC + displacement + index. */
726#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 727
728/* Note that calls to frag_var need to specify the maximum expansion
729 needed; this is currently 10 bytes for DBCC. */
730
731/* The fields are:
732 How far Forward this mode will reach:
733 How far Backward this mode will reach:
734 How many bytes this mode will add to the size of the frag
735 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 736
737 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 738relax_typeS md_relax_table[] =
739{
ac62c346
AM		 740 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
741 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
742 { 0, 0, 4, 0 },
743 { 1, 1, 0, 0 },
744
745 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
746 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
747 { 0, 0, 4, 0 },
748 { 1, 1, 0, 0 },
749
750 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
751 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
752 { 0, 0, 6, 0 },
753 { 1, 1, 0, 0 },
754
755 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
756 { 0, 0, 2, 0 },
757 { 1, 1, 0, 0 },
758 { 1, 1, 0, 0 },
759
36759679 760 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 761 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
762 { 0, 0, 4, 0 },
763 { 1, 1, 0, 0 },
764
36759679 765 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 766 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
767 { 0, 0, 10, 0 },
768 { 1, 1, 0, 0 },
769
36759679 770 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 771 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
772 { 0, 0, 10, 0 },
773 { 1, 1, 0, 0 },
774
36759679 775 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 776 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
777 { 0, 0, 6, 0 },
778 { 1, 1, 0, 0 },
779
780 { 125, -130, 0, TAB (PCINDEX, SHORT) },
781 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
782 { 0, 0, 4, 0 },
783 { 1, 1, 0, 0 },
784
36759679 785 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 786 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
787 { 0, 0, 4, 0 },
788 { 1, 1, 0, 0 },
252b5132
RH		 789};
790
791/* These are the machine dependent pseudo-ops. These are included so
792 the assembler can work on the output from the SUN C compiler, which
36759679 793 generates these. */
252b5132
RH		 794
795/* This table describes all the machine specific pseudo-ops the assembler
796 has to support. The fields are:
797 pseudo-op name without dot
798 function to call to execute this pseudo-op
36759679 799 Integer arg to pass to the function. */
252b5132
RH		 800const pseudo_typeS md_pseudo_table[] =
801{
802 {"data1", s_data1, 0},
803 {"data2", s_data2, 0},
804 {"bss", s_bss, 0},
805 {"even", s_even, 0},
806 {"skip", s_space, 0},
807 {"proc", s_proc, 0},
808#if defined (TE_SUN3) || defined (OBJ_ELF)
809 {"align", s_align_bytes, 0},
810#endif
811#ifdef OBJ_ELF
812 {"swbeg", s_ignore, 0},
813#endif
814 {"extend", float_cons, 'x'},
815 {"ldouble", float_cons, 'x'},
816
266abb8f
NS		 817 {"arch", s_m68k_arch, 0},
818 {"cpu", s_m68k_cpu, 0},
819
252b5132
RH		 820 /* The following pseudo-ops are supported for MRI compatibility. */
821 {"chip", s_chip, 0},
822 {"comline", s_space, 1},
823 {"fopt", s_fopt, 0},
824 {"mask2", s_ignore, 0},
825 {"opt", s_opt, 0},
826 {"reg", s_reg, 0},
827 {"restore", s_restore, 0},
828 {"save", s_save, 0},
829
830 {"if", s_mri_if, 0},
831 {"if.b", s_mri_if, 'b'},
832 {"if.w", s_mri_if, 'w'},
833 {"if.l", s_mri_if, 'l'},
834 {"else", s_mri_else, 0},
835 {"else.s", s_mri_else, 's'},
836 {"else.l", s_mri_else, 'l'},
837 {"endi", s_mri_endi, 0},
838 {"break", s_mri_break, 0},
839 {"break.s", s_mri_break, 's'},
840 {"break.l", s_mri_break, 'l'},
841 {"next", s_mri_next, 0},
842 {"next.s", s_mri_next, 's'},
843 {"next.l", s_mri_next, 'l'},
844 {"for", s_mri_for, 0},
845 {"for.b", s_mri_for, 'b'},
846 {"for.w", s_mri_for, 'w'},
847 {"for.l", s_mri_for, 'l'},
848 {"endf", s_mri_endf, 0},
849 {"repeat", s_mri_repeat, 0},
850 {"until", s_mri_until, 0},
851 {"until.b", s_mri_until, 'b'},
852 {"until.w", s_mri_until, 'w'},
853 {"until.l", s_mri_until, 'l'},
854 {"while", s_mri_while, 0},
855 {"while.b", s_mri_while, 'b'},
856 {"while.w", s_mri_while, 'w'},
857 {"while.l", s_mri_while, 'l'},
858 {"endw", s_mri_endw, 0},
859
860 {0, 0, 0}
861};
862
252b5132 863/* The mote pseudo ops are put into the opcode table, since they
31302357 864 don't start with a . they look like opcodes to gas. */
252b5132 865
5a38dc70 866const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 867{
868
869 {"dcl", cons, 4},
870 {"dc", cons, 2},
871 {"dcw", cons, 2},
872 {"dcb", cons, 1},
873
874 {"dsl", s_space, 4},
875 {"ds", s_space, 2},
876 {"dsw", s_space, 2},
877 {"dsb", s_space, 1},
878
879 {"xdef", s_globl, 0},
880#ifdef OBJ_ELF
881 {"align", s_align_bytes, 0},
882#else
883 {"align", s_align_ptwo, 0},
884#endif
885#ifdef M68KCOFF
886 {"sect", obj_coff_section, 0},
887 {"section", obj_coff_section, 0},
888#endif
889 {0, 0, 0}
890};
891
bd17c2c3
AM		 892/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
893 gives identical results to a 32-bit host. */
894#define TRUNC(X) ((valueT) (X) & 0xffffffff)
895#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
896
897#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
898#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
899#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
900#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
901
902#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
903#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 904#define islong(x) (1)
905
252b5132
RH		 906static char notend_table[256];
907static char alt_notend_table[256];
908#define notend(s) \
909 (! (notend_table[(unsigned char) *s] \
910 || (*s == ':' \
911 && alt_notend_table[(unsigned char) s[1]])))
912
252b5132
RH		 913#ifdef OBJ_ELF
914
c801568a
AM		 915/* Return zero if the reference to SYMBOL from within the same segment may
916 be relaxed. */
917
918/* On an ELF system, we can't relax an externally visible symbol,
919 because it may be overridden by a shared library. However, if
920 TARGET_OS is "elf", then we presume that we are assembling for an
921 embedded system, in which case we don't have to worry about shared
922 libraries, and we can relax any external sym. */
923
924#define relaxable_symbol(symbol) \
6358301e 925 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 926 || S_IS_WEAK (symbol)))
927
252b5132
RH		 928/* Compute the relocation code for a fixup of SIZE bytes, using pc
929 relative relocation if PCREL is non-zero. PIC says whether a special
930 pic relocation was requested. */
931
252b5132 932static bfd_reloc_code_real_type
31302357 933get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 934{
935 switch (pic)
936 {
937 case pic_got_pcrel:
938 switch (size)
939 {
940 case 1:
941 return BFD_RELOC_8_GOT_PCREL;
942 case 2:
943 return BFD_RELOC_16_GOT_PCREL;
944 case 4:
945 return BFD_RELOC_32_GOT_PCREL;
946 }
947 break;
948
949 case pic_got_off:
950 switch (size)
951 {
952 case 1:
953 return BFD_RELOC_8_GOTOFF;
954 case 2:
955 return BFD_RELOC_16_GOTOFF;
956 case 4:
957 return BFD_RELOC_32_GOTOFF;
958 }
959 break;
960
961 case pic_plt_pcrel:
962 switch (size)
963 {
964 case 1:
965 return BFD_RELOC_8_PLT_PCREL;
966 case 2:
967 return BFD_RELOC_16_PLT_PCREL;
968 case 4:
969 return BFD_RELOC_32_PLT_PCREL;
970 }
971 break;
972
973 case pic_plt_off:
974 switch (size)
975 {
976 case 1:
977 return BFD_RELOC_8_PLTOFF;
978 case 2:
979 return BFD_RELOC_16_PLTOFF;
980 case 4:
981 return BFD_RELOC_32_PLTOFF;
982 }
983 break;
984
985 case pic_none:
986 if (pcrel)
987 {
988 switch (size)
989 {
990 case 1:
991 return BFD_RELOC_8_PCREL;
992 case 2:
993 return BFD_RELOC_16_PCREL;
994 case 4:
995 return BFD_RELOC_32_PCREL;
996 }
997 }
998 else
999 {
1000 switch (size)
1001 {
1002 case 1:
1003 return BFD_RELOC_8;
1004 case 2:
1005 return BFD_RELOC_16;
1006 case 4:
1007 return BFD_RELOC_32;
1008 }
1009 }
1010 }
1011
1012 if (pcrel)
1013 {
1014 if (pic == pic_none)
1015 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1016 else
1017 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1018 }
1019 else
1020 {
1021 if (pic == pic_none)
1022 as_bad (_("Can not do %d byte relocation"), size);
1023 else
1024 as_bad (_("Can not do %d byte pic relocation"), size);
1025 }
1026
1027 return BFD_RELOC_NONE;
1028}
1029
1030/* Here we decide which fixups can be adjusted to make them relative
1031 to the beginning of the section instead of the symbol. Basically
1032 we need to make sure that the dynamic relocations are done
1033 correctly, so in some cases we force the original symbol to be
1034 used. */
1035int
31302357 1036tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1037{
36759679 1038 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1039 switch (fixP->fx_r_type)
1040 {
1041 case BFD_RELOC_8_GOT_PCREL:
1042 case BFD_RELOC_16_GOT_PCREL:
1043 case BFD_RELOC_32_GOT_PCREL:
1044 case BFD_RELOC_8_GOTOFF:
1045 case BFD_RELOC_16_GOTOFF:
1046 case BFD_RELOC_32_GOTOFF:
1047 case BFD_RELOC_8_PLT_PCREL:
1048 case BFD_RELOC_16_PLT_PCREL:
1049 case BFD_RELOC_32_PLT_PCREL:
1050 case BFD_RELOC_8_PLTOFF:
1051 case BFD_RELOC_16_PLTOFF:
1052 case BFD_RELOC_32_PLTOFF:
1053 return 0;
1054
1055 case BFD_RELOC_VTABLE_INHERIT:
1056 case BFD_RELOC_VTABLE_ENTRY:
1057 return 0;
1058
1059 default:
1060 return 1;
1061 }
1062}
1063
1064#else /* !OBJ_ELF */
1065
1066#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1067
22184a77
NC		 1068/* PR gas/3041 Weak symbols are not relaxable
1069 because they must be treated as extern. */
1070#define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
c801568a 1071
252b5132
RH		 1072#endif /* OBJ_ELF */
1073
252b5132 1074arelent *
31302357 1075tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1076{
1077 arelent *reloc;
1078 bfd_reloc_code_real_type code;
1079
8ec6253e
NC		 1080 /* If the tcbit is set, then this was a fixup of a negative value
1081 that was never resolved. We do not have a reloc to handle this,
1082 so just return. We assume that other code will have detected this
1083 situation and produced a helpful error message, so we just tell the
1084 user that the reloc cannot be produced. */
252b5132 1085 if (fixp->fx_tcbit)
8ec6253e
NC		 1086 {
1087 if (fixp->fx_addsy)
b091f402
AM		 1088 as_bad_where (fixp->fx_file, fixp->fx_line,
1089 _("Unable to produce reloc against symbol '%s'"),
1090 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1091 return NULL;
1092 }
252b5132
RH		 1093
1094 if (fixp->fx_r_type != BFD_RELOC_NONE)
1095 {
1096 code = fixp->fx_r_type;
1097
1098 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1099 that fixup_segment converted a non-PC relative reloc into a
1100 PC relative reloc. In such a case, we need to convert the
1101 reloc code. */
1102 if (fixp->fx_pcrel)
1103 {
1104 switch (code)
1105 {
1106 case BFD_RELOC_8:
1107 code = BFD_RELOC_8_PCREL;
1108 break;
1109 case BFD_RELOC_16:
1110 code = BFD_RELOC_16_PCREL;
1111 break;
1112 case BFD_RELOC_32:
1113 code = BFD_RELOC_32_PCREL;
1114 break;
1115 case BFD_RELOC_8_PCREL:
1116 case BFD_RELOC_16_PCREL:
1117 case BFD_RELOC_32_PCREL:
1118 case BFD_RELOC_8_GOT_PCREL:
1119 case BFD_RELOC_16_GOT_PCREL:
1120 case BFD_RELOC_32_GOT_PCREL:
1121 case BFD_RELOC_8_GOTOFF:
1122 case BFD_RELOC_16_GOTOFF:
1123 case BFD_RELOC_32_GOTOFF:
1124 case BFD_RELOC_8_PLT_PCREL:
1125 case BFD_RELOC_16_PLT_PCREL:
1126 case BFD_RELOC_32_PLT_PCREL:
1127 case BFD_RELOC_8_PLTOFF:
1128 case BFD_RELOC_16_PLTOFF:
1129 case BFD_RELOC_32_PLTOFF:
1130 break;
1131 default:
1132 as_bad_where (fixp->fx_file, fixp->fx_line,
1133 _("Cannot make %s relocation PC relative"),
1134 bfd_get_reloc_code_name (code));
1135 }
1136 }
1137 }
1138 else
1139 {
1140#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1141 switch (F (fixp->fx_size, fixp->fx_pcrel))
1142 {
1143#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1144 MAP (1, 0, BFD_RELOC_8);
1145 MAP (2, 0, BFD_RELOC_16);
1146 MAP (4, 0, BFD_RELOC_32);
1147 MAP (1, 1, BFD_RELOC_8_PCREL);
1148 MAP (2, 1, BFD_RELOC_16_PCREL);
1149 MAP (4, 1, BFD_RELOC_32_PCREL);
1150 default:
1151 abort ();
1152 }
1153 }
1154#undef F
1155#undef MAP
1156
1157 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1158 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1159 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1160 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1161#ifndef OBJ_ELF
1162 if (fixp->fx_pcrel)
1163 reloc->addend = fixp->fx_addnumber;
22184a77
NC		 1164 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1165 && fixp->fx_addsy
1166 && S_IS_WEAK (fixp->fx_addsy)
1167 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1168 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1c3f20b4
NC		 1169 to put the symbol offset into frags referencing a weak symbol. */
1170 reloc->addend = fixp->fx_addnumber
1171 - (S_GET_VALUE (fixp->fx_addsy) * 2);
252b5132
RH		 1172 else
1173 reloc->addend = 0;
1174#else
1175 if (!fixp->fx_pcrel)
1176 reloc->addend = fixp->fx_addnumber;
1177 else
1178 reloc->addend = (section->vma
8390138c
AS		 1179 /* Explicit sign extension in case char is
1180 unsigned. */
1181 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1182 + fixp->fx_addnumber
1183 + md_pcrel_from (fixp));
1184#endif
1185
1186 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1187 assert (reloc->howto != 0);
1188
1189 return reloc;
1190}
1191
252b5132
RH		 1192/* Handle of the OPCODE hash table. NULL means any use before
1193 m68k_ip_begin() will crash. */
1194static struct hash_control *op_hash;
1195\f
1196/* Assemble an m68k instruction. */
1197
1198static void
31302357 1199m68k_ip (char *instring)
252b5132
RH		 1200{
1201 register char *p;
1202 register struct m68k_op *opP;
1203 register const struct m68k_incant *opcode;
1204 register const char *s;
1205 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1206 char *pdot, *pdotmove;
1207 enum m68k_size siz1, siz2;
1208 char c;
1209 int losing;
1210 int opsfound;
03b13e59 1211 struct m68k_op operands_backup[6];
252b5132
RH		 1212 LITTLENUM_TYPE words[6];
1213 LITTLENUM_TYPE *wordp;
1214 unsigned long ok_arch = 0;
1215
1216 if (*instring == ' ')
36759679 1217 instring++; /* Skip leading whitespace. */
252b5132
RH		 1218
1219 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1220 or exactly 1 space. */
252b5132
RH		 1221 pdot = 0;
1222 for (p = instring; *p != '\0'; p++)
1223 {
1224 if (*p == ' ')
1225 break;
1226 if (*p == '.')
1227 pdot = p;
1228 }
1229
1230 if (p == instring)
1231 {
1232 the_ins.error = _("No operator");
1233 return;
1234 }
1235
1236 /* p now points to the end of the opcode name, probably whitespace.
1237 Make sure the name is null terminated by clobbering the
1238 whitespace, look it up in the hash table, then fix it back.
1239 Remove a dot, first, since the opcode tables have none. */
1240 if (pdot != NULL)
1241 {
1242 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1243 *pdotmove = pdotmove[1];
1244 p--;
1245 }
1246
1247 c = *p;
1248 *p = '\0';
1249 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1250 *p = c;
1251
1252 if (pdot != NULL)
1253 {
1254 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1255 *pdotmove = pdotmove[-1];
1256 *pdot = '.';
1257 ++p;
1258 }
1259
1260 if (opcode == NULL)
1261 {
1262 the_ins.error = _("Unknown operator");
1263 return;
1264 }
1265
36759679 1266 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1267 while (*p == ' ')
1268 ++p;
1269
1270 if (opcode->m_operands == 0)
1271 {
1272 char *old = input_line_pointer;
1273 *old = '\n';
1274 input_line_pointer = p;
36759679 1275 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1276 mote_pseudo_table[opcode->m_opnum].poc_handler
1277 (mote_pseudo_table[opcode->m_opnum].poc_val);
1278 input_line_pointer = old;
1279 *old = 0;
1280
1281 return;
1282 }
1283
1284 if (flag_mri && opcode->m_opnum == 0)
1285 {
1286 /* In MRI mode, random garbage is allowed after an instruction
1287 which accepts no operands. */
1288 the_ins.args = opcode->m_operands;
1289 the_ins.numargs = opcode->m_opnum;
1290 the_ins.numo = opcode->m_codenum;
1291 the_ins.opcode[0] = getone (opcode);
1292 the_ins.opcode[1] = gettwo (opcode);
1293 return;
1294 }
1295
1296 for (opP = &the_ins.operands[0]; *p; opP++)
1297 {
1298 p = crack_operand (p, opP);
1299
1300 if (opP->error)
1301 {
1302 the_ins.error = opP->error;
1303 return;
1304 }
1305 }
1306
1307 opsfound = opP - &the_ins.operands[0];
1308
1309 /* This ugly hack is to support the floating pt opcodes in their
1310 standard form. Essentially, we fake a first enty of type COP#1 */
1311 if (opcode->m_operands[0] == 'I')
1312 {
1313 int n;
1314
1315 for (n = opsfound; n > 0; --n)
1316 the_ins.operands[n] = the_ins.operands[n - 1];
1317
31302357 1318 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1319 the_ins.operands[0].mode = CONTROL;
1320 the_ins.operands[0].reg = m68k_float_copnum;
1321 opsfound++;
1322 }
1323
36759679 1324 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1325 for (losing = 0;;)
1326 {
1327 /* If we didn't get the right number of ops, or we have no
92774660 1328 common model with this pattern then reject this pattern. */
252b5132
RH		 1329
1330 ok_arch |= opcode->m_arch;
1331 if (opsfound != opcode->m_opnum
1332 || ((opcode->m_arch & current_architecture) == 0))
1333 ++losing;
1334 else
1335 {
03b13e59
NC		 1336 int i;
1337
1338 /* Make a copy of the operands of this insn so that
1339 we can modify them safely, should we want to. */
1340 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1341 for (i = 0; i < opsfound; i++)
1342 operands_backup[i] = the_ins.operands[i];
1343
1344 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1345 *s && !losing;
1346 s += 2, opP++)
1347 {
1348 /* Warning: this switch is huge! */
1349 /* I've tried to organize the cases into this order:
1350 non-alpha first, then alpha by letter. Lower-case
1351 goes directly before uppercase counterpart. */
1352 /* Code with multiple case ...: gets sorted by the lowest
1353 case ... it belongs to. I hope this makes sense. */
1354 switch (*s)
1355 {
1356 case '!':
1357 switch (opP->mode)
1358 {
1359 case IMMED:
1360 case DREG:
1361 case AREG:
1362 case FPREG:
1363 case CONTROL:
1364 case AINC:
1365 case ADEC:
1366 case REGLST:
1367 losing++;
1368 break;
1369 default:
1370 break;
1371 }
1372 break;
1373
1374 case '<':
1375 switch (opP->mode)
1376 {
1377 case DREG:
1378 case AREG:
1379 case FPREG:
1380 case CONTROL:
1381 case IMMED:
1382 case ADEC:
1383 case REGLST:
1384 losing++;
1385 break;
1386 default:
1387 break;
1388 }
1389 break;
1390
1391 case '>':
1392 switch (opP->mode)
1393 {
1394 case DREG:
1395 case AREG:
1396 case FPREG:
1397 case CONTROL:
1398 case IMMED:
1399 case AINC:
1400 case REGLST:
1401 losing++;
1402 break;
1403 case ABSL:
1404 break;
1405 default:
1406 if (opP->reg == PC
1407 || opP->reg == ZPC)
1408 losing++;
1409 break;
1410 }
1411 break;
1412
1413 case 'm':
1414 switch (opP->mode)
1415 {
1416 case DREG:
1417 case AREG:
1418 case AINDR:
1419 case AINC:
1420 case ADEC:
1421 break;
1422 default:
1423 losing++;
1424 }
8a104df9 1425 break;
252b5132
RH		 1426
1427 case 'n':
1428 switch (opP->mode)
1429 {
1430 case DISP:
1431 break;
1432 default:
1433 losing++;
1434 }
8a104df9 1435 break;
252b5132
RH		 1436
1437 case 'o':
1438 switch (opP->mode)
1439 {
1440 case BASE:
1441 case ABSL:
1442 case IMMED:
1443 break;
1444 default:
1445 losing++;
1446 }
8a104df9 1447 break;
252b5132
RH		 1448
1449 case 'p':
1450 switch (opP->mode)
1451 {
1452 case DREG:
1453 case AREG:
1454 case AINDR:
1455 case AINC:
1456 case ADEC:
1457 break;
1458 case DISP:
1459 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1460 losing++;
252b5132
RH		 1461 break;
1462 default:
1463 losing++;
1464 }
8a104df9 1465 break;
252b5132
RH		 1466
1467 case 'q':
1468 switch (opP->mode)
1469 {
1470 case DREG:
1471 case AINDR:
1472 case AINC:
1473 case ADEC:
1474 break;
1475 case DISP:
1476 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1477 losing++;
252b5132
RH		 1478 break;
1479 default:
1480 losing++;
1481 break;
1482 }
8a104df9 1483 break;
252b5132
RH		 1484
1485 case 'v':
1486 switch (opP->mode)
1487 {
1488 case DREG:
1489 case AINDR:
1490 case AINC:
1491 case ADEC:
1492 case ABSL:
1493 break;
1494 case DISP:
1495 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1496 losing++;
252b5132
RH		 1497 break;
1498 default:
1499 losing++;
1500 break;
1501 }
1502 break;
1503
1504 case '#':
1505 if (opP->mode != IMMED)
1506 losing++;
1507 else if (s[1] == 'b'
1508 && ! isvar (&opP->disp)
1509 && (opP->disp.exp.X_op != O_constant
1510 || ! isbyte (opP->disp.exp.X_add_number)))
1511 losing++;
1512 else if (s[1] == 'B'
1513 && ! isvar (&opP->disp)
1514 && (opP->disp.exp.X_op != O_constant
1515 || ! issbyte (opP->disp.exp.X_add_number)))
1516 losing++;
1517 else if (s[1] == 'w'
1518 && ! isvar (&opP->disp)
1519 && (opP->disp.exp.X_op != O_constant
1520 || ! isword (opP->disp.exp.X_add_number)))
1521 losing++;
1522 else if (s[1] == 'W'
1523 && ! isvar (&opP->disp)
1524 && (opP->disp.exp.X_op != O_constant
1525 || ! issword (opP->disp.exp.X_add_number)))
1526 losing++;
1527 break;
1528
1529 case '^':
1530 case 'T':
1531 if (opP->mode != IMMED)
1532 losing++;
1533 break;
1534
1535 case '$':
1536 if (opP->mode == AREG
1537 || opP->mode == CONTROL
1538 || opP->mode == FPREG
1539 || opP->mode == IMMED
1540 || opP->mode == REGLST
1541 || (opP->mode != ABSL
1542 && (opP->reg == PC
1543 || opP->reg == ZPC)))
1544 losing++;
1545 break;
1546
1547 case '%':
1548 if (opP->mode == CONTROL
1549 || opP->mode == FPREG
1550 || opP->mode == REGLST
1551 || opP->mode == IMMED
1552 || (opP->mode != ABSL
1553 && (opP->reg == PC
1554 || opP->reg == ZPC)))
1555 losing++;
1556 break;
1557
1558 case '&':
1559 switch (opP->mode)
1560 {
1561 case DREG:
1562 case AREG:
1563 case FPREG:
1564 case CONTROL:
1565 case IMMED:
1566 case AINC:
1567 case ADEC:
1568 case REGLST:
1569 losing++;
1570 break;
1571 case ABSL:
1572 break;
1573 default:
1574 if (opP->reg == PC
1575 || opP->reg == ZPC)
1576 losing++;
1577 break;
1578 }
1579 break;
1580
1581 case '*':
1582 if (opP->mode == CONTROL
1583 || opP->mode == FPREG
1584 || opP->mode == REGLST)
1585 losing++;
1586 break;
1587
1588 case '+':
1589 if (opP->mode != AINC)
1590 losing++;
1591 break;
1592
1593 case '-':
1594 if (opP->mode != ADEC)
1595 losing++;
1596 break;
1597
1598 case '/':
1599 switch (opP->mode)
1600 {
1601 case AREG:
1602 case CONTROL:
1603 case FPREG:
1604 case AINC:
1605 case ADEC:
1606 case IMMED:
1607 case REGLST:
1608 losing++;
1609 break;
1610 default:
1611 break;
1612 }
1613 break;
1614
1615 case ';':
1616 switch (opP->mode)
1617 {
1618 case AREG:
1619 case CONTROL:
1620 case FPREG:
1621 case REGLST:
1622 losing++;
1623 break;
1624 default:
1625 break;
1626 }
1627 break;
1628
1629 case '?':
1630 switch (opP->mode)
1631 {
1632 case AREG:
1633 case CONTROL:
1634 case FPREG:
1635 case AINC:
1636 case ADEC:
1637 case IMMED:
1638 case REGLST:
1639 losing++;
1640 break;
1641 case ABSL:
1642 break;
1643 default:
1644 if (opP->reg == PC || opP->reg == ZPC)
1645 losing++;
1646 break;
1647 }
1648 break;
1649
1650 case '@':
1651 switch (opP->mode)
1652 {
1653 case AREG:
1654 case CONTROL:
1655 case FPREG:
1656 case IMMED:
1657 case REGLST:
1658 losing++;
1659 break;
1660 default:
1661 break;
1662 }
1663 break;
1664
1665 case '~': /* For now! (JF FOO is this right?) */
1666 switch (opP->mode)
1667 {
1668 case DREG:
1669 case AREG:
1670 case CONTROL:
1671 case FPREG:
1672 case IMMED:
1673 case REGLST:
1674 losing++;
1675 break;
1676 case ABSL:
1677 break;
1678 default:
1679 if (opP->reg == PC
1680 || opP->reg == ZPC)
1681 losing++;
1682 break;
1683 }
1684 break;
1685
1686 case '3':
1687 if (opP->mode != CONTROL
1688 || (opP->reg != TT0 && opP->reg != TT1))
1689 losing++;
1690 break;
1691
1692 case 'A':
1693 if (opP->mode != AREG)
1694 losing++;
1695 break;
1696
1697 case 'a':
1698 if (opP->mode != AINDR)
1699 ++losing;
1700 break;
1701
fd99574b
NC		 1702 case '4':
1703 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1704 && (opP->mode != DISP
1705 || opP->reg < ADDR0
1706 || opP->reg > ADDR7))
1707 ++losing;
1708 break;
1709
252b5132
RH		 1710 case 'B': /* FOO */
1711 if (opP->mode != ABSL
1712 || (flag_long_jumps
1713 && strncmp (instring, "jbsr", 4) == 0))
1714 losing++;
1715 break;
1716
3e602632
NC		 1717 case 'b':
1718 switch (opP->mode)
1719 {
1720 case IMMED:
1721 case ABSL:
1722 case AREG:
1723 case FPREG:
1724 case CONTROL:
1725 case POST:
1726 case PRE:
1727 case REGLST:
1728 losing++;
1729 break;
1730 default:
1731 break;
1732 }
1733 break;
1734
252b5132
RH		 1735 case 'C':
1736 if (opP->mode != CONTROL || opP->reg != CCR)
1737 losing++;
1738 break;
1739
1740 case 'd':
1741 if (opP->mode != DISP
1742 || opP->reg < ADDR0
1743 || opP->reg > ADDR7)
1744 losing++;
1745 break;
1746
1747 case 'D':
1748 if (opP->mode != DREG)
1749 losing++;
1750 break;
1751
6da466c7
ILT		 1752 case 'E':
1753 if (opP->reg != ACC)
1754 losing++;
1755 break;
1756
fd99574b
NC		 1757 case 'e':
1758 if (opP->reg != ACC && opP->reg != ACC1
1759 && opP->reg != ACC2 && opP->reg != ACC3)
1760 losing++;
1761 break;
1762
252b5132
RH		 1763 case 'F':
1764 if (opP->mode != FPREG)
1765 losing++;
1766 break;
1767
6da466c7
ILT		 1768 case 'G':
1769 if (opP->reg != MACSR)
1770 losing++;
1771 break;
1772
fd99574b
NC		 1773 case 'g':
1774 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1775 losing++;
1776 break;
1777
6da466c7
ILT		 1778 case 'H':
1779 if (opP->reg != MASK)
1780 losing++;
1781 break;
1782
252b5132
RH		 1783 case 'I':
1784 if (opP->mode != CONTROL
1785 || opP->reg < COP0
1786 || opP->reg > COP7)
1787 losing++;
1788 break;
1789
fd99574b
NC		 1790 case 'i':
1791 if (opP->mode != LSH && opP->mode != RSH)
1792 losing++;
1793 break;
1794
252b5132
RH		 1795 case 'J':
1796 if (opP->mode != CONTROL
1797 || opP->reg < USP
0b2e31dc
NS		 1798 || opP->reg > last_movec_reg
1799 || !control_regs)
252b5132
RH		 1800 losing++;
1801 else
1802 {
1803 const enum m68k_register *rp;
0b2e31dc 1804
252b5132 1805 for (rp = control_regs; *rp; rp++)
78336706
NS		 1806 {
1807 if (*rp == opP->reg)
1808 break;
1809 /* In most CPUs RAMBAR refers to control reg
1810 c05 (RAMBAR1), but a few CPUs have it
1811 refer to c04 (RAMBAR0). */
1812 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1813 {
1814 opP->reg = RAMBAR_ALT;
1815 break;
1816 }
1817 }
252b5132
RH		 1818 if (*rp == 0)
1819 losing++;
1820 }
1821 break;
1822
1823 case 'k':
1824 if (opP->mode != IMMED)
1825 losing++;
1826 break;
1827
1828 case 'l':
1829 case 'L':
1830 if (opP->mode == DREG
1831 || opP->mode == AREG
1832 || opP->mode == FPREG)
1833 {
1834 if (s[1] == '8')
1835 losing++;
1836 else
1837 {
1838 switch (opP->mode)
1839 {
1840 case DREG:
1841 opP->mask = 1 << (opP->reg - DATA0);
1842 break;
1843 case AREG:
1844 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1845 break;
1846 case FPREG:
1847 opP->mask = 1 << (opP->reg - FP0 + 16);
1848 break;
1849 default:
1850 abort ();
1851 }
1852 opP->mode = REGLST;
1853 }
1854 }
1855 else if (opP->mode == CONTROL)
1856 {
1857 if (s[1] != '8')
1858 losing++;
1859 else
1860 {
1861 switch (opP->reg)
1862 {
1863 case FPI:
1864 opP->mask = 1 << 24;
1865 break;
1866 case FPS:
1867 opP->mask = 1 << 25;
1868 break;
1869 case FPC:
1870 opP->mask = 1 << 26;
1871 break;
1872 default:
1873 losing++;
1874 break;
1875 }
1876 opP->mode = REGLST;
1877 }
1878 }
1879 else if (opP->mode != REGLST)
1880 losing++;
1881 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1882 losing++;
1883 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1884 losing++;
1885 break;
1886
1887 case 'M':
1888 if (opP->mode != IMMED)
1889 losing++;
1890 else if (opP->disp.exp.X_op != O_constant
1891 || ! issbyte (opP->disp.exp.X_add_number))
1892 losing++;
1893 else if (! m68k_quick
1894 && instring[3] != 'q'
1895 && instring[4] != 'q')
1896 losing++;
1897 break;
1898
1899 case 'O':
1900 if (opP->mode != DREG
1901 && opP->mode != IMMED
1902 && opP->mode != ABSL)
1903 losing++;
1904 break;
1905
1906 case 'Q':
1907 if (opP->mode != IMMED)
1908 losing++;
1909 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1910 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1911 losing++;
1912 else if (! m68k_quick
1913 && (strncmp (instring, "add", 3) == 0
1914 || strncmp (instring, "sub", 3) == 0)
1915 && instring[3] != 'q')
1916 losing++;
1917 break;
1918
1919 case 'R':
1920 if (opP->mode != DREG && opP->mode != AREG)
1921 losing++;
1922 break;
1923
1924 case 'r':
1925 if (opP->mode != AINDR
1926 && (opP->mode != BASE
1927 || (opP->reg != 0
1928 && opP->reg != ZADDR0)
1929 || opP->disp.exp.X_op != O_absent
1930 || ((opP->index.reg < DATA0
1931 || opP->index.reg > DATA7)
1932 && (opP->index.reg < ADDR0
1933 || opP->index.reg > ADDR7))
1934 || opP->index.size != SIZE_UNSPEC
1935 || opP->index.scale != 1))
1936 losing++;
1937 break;
1938
1939 case 's':
1940 if (opP->mode != CONTROL
1941 || ! (opP->reg == FPI
1942 || opP->reg == FPS
1943 || opP->reg == FPC))
1944 losing++;
1945 break;
1946
1947 case 'S':
1948 if (opP->mode != CONTROL || opP->reg != SR)
1949 losing++;
1950 break;
1951
1952 case 't':
1953 if (opP->mode != IMMED)
1954 losing++;
1955 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1956 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1957 losing++;
1958 break;
1959
1960 case 'U':
1961 if (opP->mode != CONTROL || opP->reg != USP)
1962 losing++;
1963 break;
1964
3e602632
NC		 1965 case 'x':
1966 if (opP->mode != IMMED)
1967 losing++;
1968 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1969 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1970 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1971 losing++;
1972 break;
1973
afa2158f
NS		 1974 case 'j':
1975 if (opP->mode != IMMED)
1976 losing++;
1977 else if (opP->disp.exp.X_op != O_constant
1978 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1979 losing++;
1980 break;
1981
1982 case 'K':
1983 if (opP->mode != IMMED)
1984 losing++;
1985 else if (opP->disp.exp.X_op != O_constant
1986 || TRUNC (opP->disp.exp.X_add_number) > 511)
1987 losing++;
1988 break;
1989
252b5132
RH		 1990 /* JF these are out of order. We could put them
1991 in order if we were willing to put up with
1992 bunches of #ifdef m68851s in the code.
1993
1994 Don't forget that you need these operands
1995 to use 68030 MMU instructions. */
1996#ifndef NO_68851
36759679 1997 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1998 case '|':
1999 if (opP->mode == CONTROL
2000 || opP->mode == FPREG
2001 || opP->mode == DREG
2002 || opP->mode == AREG
2003 || opP->mode == REGLST)
2004 losing++;
2005 /* We should accept immediate operands, but they
2006 supposedly have to be quad word, and we don't
2007 handle that. I would like to see what a Motorola
2008 assembler does before doing something here. */
2009 if (opP->mode == IMMED)
2010 losing++;
2011 break;
2012
2013 case 'f':
2014 if (opP->mode != CONTROL
2015 || (opP->reg != SFC && opP->reg != DFC))
2016 losing++;
2017 break;
2018
2019 case '0':
2020 if (opP->mode != CONTROL || opP->reg != TC)
2021 losing++;
2022 break;
2023
2024 case '1':
2025 if (opP->mode != CONTROL || opP->reg != AC)
2026 losing++;
2027 break;
2028
2029 case '2':
2030 if (opP->mode != CONTROL
2031 || (opP->reg != CAL
2032 && opP->reg != VAL
2033 && opP->reg != SCC))
2034 losing++;
2035 break;
2036
2037 case 'V':
2038 if (opP->mode != CONTROL
2039 || opP->reg != VAL)
2040 losing++;
2041 break;
2042
2043 case 'W':
2044 if (opP->mode != CONTROL
2045 || (opP->reg != DRP
2046 && opP->reg != SRP
2047 && opP->reg != CRP))
2048 losing++;
2049 break;
2050
3e602632
NC		 2051 case 'w':
2052 switch (opP->mode)
2053 {
2054 case IMMED:
2055 case ABSL:
2056 case AREG:
2057 case DREG:
2058 case FPREG:
2059 case CONTROL:
2060 case POST:
2061 case PRE:
2062 case REGLST:
2063 losing++;
2064 break;
2065 default:
2066 break;
2067 }
2068 break;
2069
252b5132
RH		 2070 case 'X':
2071 if (opP->mode != CONTROL
2072 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2073 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2074 losing++;
2075 break;
2076
2077 case 'Y':
2078 if (opP->mode != CONTROL || opP->reg != PSR)
2079 losing++;
2080 break;
2081
2082 case 'Z':
2083 if (opP->mode != CONTROL || opP->reg != PCSR)
2084 losing++;
2085 break;
2086#endif
2087 case 'c':
2088 if (opP->mode != CONTROL
2089 || (opP->reg != NC
2090 && opP->reg != IC
2091 && opP->reg != DC
2092 && opP->reg != BC))
36759679 2093 losing++;
252b5132
RH		 2094 break;
2095
2096 case '_':
2097 if (opP->mode != ABSL)
2098 ++losing;
2099 break;
2100
6da466c7
ILT		 2101 case 'u':
2102 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2103 losing++;
2104 /* FIXME: kludge instead of fixing parser:
2105 upper/lower registers are *not* CONTROL
92774660 2106 registers, but ordinary ones. */
6da466c7
ILT		 2107 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2108 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2109 opP->mode = DREG;
2110 else
2111 opP->mode = AREG;
2112 break;
2113
3e602632
NC		 2114 case 'y':
2115 if (!(opP->mode == AINDR
31302357
AS		 2116 || (opP->mode == DISP
2117 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2118 losing++;
2119 break;
2120
2121 case 'z':
2122 if (!(opP->mode == AINDR || opP->mode == DISP))
2123 losing++;
2124 break;
2125
252b5132
RH		 2126 default:
2127 abort ();
36759679 2128 }
252b5132
RH		 2129
2130 if (losing)
2131 break;
36759679 2132 }
03b13e59
NC		 2133
2134 /* Since we have found the correct instruction, copy
2135 in the modifications that we may have made. */
2136 if (!losing)
2137 for (i = 0; i < opsfound; i++)
2138 the_ins.operands[i] = operands_backup[i];
36759679 2139 }
252b5132
RH		 2140
2141 if (!losing)
36759679 2142 break;
252b5132
RH		 2143
2144 opcode = opcode->m_next;
2145
2146 if (!opcode)
2147 {
2148 if (ok_arch
2149 && !(ok_arch & current_architecture))
2150 {
6d89cc8f
NS		 2151 const struct m68k_cpu *cpu;
2152 int any = 0;
2153 size_t space = 400;
2154 char *buf = xmalloc (space + 1);
2155 size_t len;
2156 int paren = 1;
2157
2158 the_ins.error = buf;
2159 /* Make sure there's a NUL at the end of the buffer -- strncpy
2160 won't write one when it runs out of buffer */
2161 buf[space] = 0;
2162#define APPEND(STRING) \
2163 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2164
2165 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2166 switch (ok_arch)
2167 {
6b6e92f4 2168 case mcfisa_a:
6d89cc8f 2169 APPEND (_("ColdFire ISA_A"));
6b6e92f4
NC		 2170 break;
2171 case mcfhwdiv:
6d89cc8f 2172 APPEND (_("ColdFire hardware divide"));
6b6e92f4
NC		 2173 break;
2174 case mcfisa_aa:
6d89cc8f 2175 APPEND (_("ColdFire ISA_A+"));
6b6e92f4
NC		 2176 break;
2177 case mcfisa_b:
6d89cc8f 2178 APPEND (_("ColdFire ISA_B"));
6b6e92f4 2179 break;
3e602632 2180 case cfloat:
6d89cc8f 2181 APPEND (_("ColdFire fpu"));
3e602632 2182 break;
252b5132 2183 case mfloat:
6d89cc8f 2184 APPEND (_("M68K fpu"));
252b5132
RH		 2185 break;
2186 case mmmu:
6d89cc8f 2187 APPEND (_("M68K mmu"));
252b5132
RH		 2188 break;
2189 case m68020up:
6d89cc8f 2190 APPEND (_("68020 or higher"));
252b5132
RH		 2191 break;
2192 case m68000up:
6d89cc8f 2193 APPEND (_("68000 or higher"));
252b5132
RH		 2194 break;
2195 case m68010up:
6d89cc8f 2196 APPEND (_("68010 or higher"));
252b5132
RH		 2197 break;
2198 default:
6d89cc8f
NS		 2199 paren = 0;
2200 }
2201 if (paren)
2202 APPEND (" (");
6b6e92f4 2203
6d89cc8f
NS		 2204 for (cpu = m68k_cpus; cpu->name; cpu++)
2205 if (!cpu->alias && (cpu->arch & ok_arch))
2206 {
2207 const struct m68k_cpu *alias;
869ddf2a
NS		 2208 int seen_master = 0;
2209
6d89cc8f
NS		 2210 if (any)
2211 APPEND (", ");
2212 any = 0;
2213 APPEND (cpu->name);
869ddf2a
NS		 2214 for (alias = cpu; alias != m68k_cpus; alias--)
2215 if (alias[-1].alias >= 0)
2216 break;
2217 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2218 {
869ddf2a
NS		 2219 if (!alias->alias)
2220 seen_master = 1;
2221 else
2222 {
2223 if (any)
2224 APPEND (", ");
2225 else
2226 APPEND (" [");
2227 APPEND (alias->name);
2228 any = 1;
2229 }
6d89cc8f 2230 }
869ddf2a
NS		 2231 if (any)
2232 APPEND ("]");
6d89cc8f 2233 any = 1;
252b5132 2234 }
6d89cc8f
NS		 2235 if (paren)
2236 APPEND (")");
2237#undef APPEND
2238 if (!space)
2239 {
2240 /* we ran out of space, so replace the end of the list
2241 with ellipsis. */
2242 buf -= 4;
2243 while (*buf != ' ')
2244 buf--;
2245 strcpy (buf, " ...");
252b5132 2246 }
252b5132
RH		 2247 }
2248 else
2249 the_ins.error = _("operands mismatch");
2250 return;
36759679 2251 }
252b5132
RH		 2252
2253 losing = 0;
2254 }
2255
36759679 2256 /* Now assemble it. */
252b5132
RH		 2257 the_ins.args = opcode->m_operands;
2258 the_ins.numargs = opcode->m_opnum;
2259 the_ins.numo = opcode->m_codenum;
2260 the_ins.opcode[0] = getone (opcode);
2261 the_ins.opcode[1] = gettwo (opcode);
2262
2263 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2264 {
9a2e615a
NS		 2265 int have_disp = 0;
2266
252b5132 2267 /* This switch is a doozy.
31302357 2268 Watch the first step; its a big one! */
252b5132
RH		 2269 switch (s[0])
2270 {
2271
2272 case '*':
2273 case '~':
2274 case '%':
2275 case ';':
2276 case '@':
2277 case '!':
2278 case '&':
2279 case '$':
2280 case '?':
2281 case '/':
2282 case '<':
2283 case '>':
3e602632 2284 case 'b':
252b5132
RH		 2285 case 'm':
2286 case 'n':
2287 case 'o':
2288 case 'p':
2289 case 'q':
2290 case 'v':
3e602632
NC		 2291 case 'w':
2292 case 'y':
2293 case 'z':
fd99574b 2294 case '4':
252b5132
RH		 2295#ifndef NO_68851
2296 case '|':
2297#endif
2298 switch (opP->mode)
2299 {
2300 case IMMED:
2301 tmpreg = 0x3c; /* 7.4 */
2302 if (strchr ("bwl", s[1]))
3e602632 2303 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2304 else
2305 nextword = get_num (&opP->disp, 0);
2306 if (isvar (&opP->disp))
2307 add_fix (s[1], &opP->disp, 0, 0);
2308 switch (s[1])
2309 {
2310 case 'b':
2311 if (!isbyte (nextword))
2312 opP->error = _("operand out of range");
2313 addword (nextword);
2314 baseo = 0;
2315 break;
2316 case 'w':
2317 if (!isword (nextword))
2318 opP->error = _("operand out of range");
2319 addword (nextword);
2320 baseo = 0;
2321 break;
2322 case 'W':
2323 if (!issword (nextword))
2324 opP->error = _("operand out of range");
2325 addword (nextword);
2326 baseo = 0;
2327 break;
2328 case 'l':
2329 addword (nextword >> 16);
2330 addword (nextword);
2331 baseo = 0;
2332 break;
2333
2334 case 'f':
2335 baseo = 2;
2336 outro = 8;
2337 break;
2338 case 'F':
2339 baseo = 4;
2340 outro = 11;
2341 break;
2342 case 'x':
2343 baseo = 6;
2344 outro = 15;
2345 break;
2346 case 'p':
2347 baseo = 6;
2348 outro = -1;
2349 break;
2350 default:
2351 abort ();
2352 }
2353 if (!baseo)
2354 break;
2355
36759679 2356 /* We gotta put out some float. */
252b5132
RH		 2357 if (op (&opP->disp) != O_big)
2358 {
2359 valueT val;
2360 int gencnt;
2361
2362 /* Can other cases happen here? */
2363 if (op (&opP->disp) != O_constant)
2364 abort ();
2365
2366 val = (valueT) offs (&opP->disp);
2367 gencnt = 0;
2368 do
2369 {
2370 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2371 val >>= LITTLENUM_NUMBER_OF_BITS;
2372 ++gencnt;
2373 }
2374 while (val != 0);
2375 offs (&opP->disp) = gencnt;
2376 }
2377 if (offs (&opP->disp) > 0)
2378 {
2379 if (offs (&opP->disp) > baseo)
2380 {
2381 as_warn (_("Bignum too big for %c format; truncated"),
2382 s[1]);
2383 offs (&opP->disp) = baseo;
2384 }
2385 baseo -= offs (&opP->disp);
2386 while (baseo--)
2387 addword (0);
2388 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2389 offs (&opP->disp)--;
2390 --wordp)
2391 addword (*wordp);
2392 break;
2393 }
2394 gen_to_words (words, baseo, (long) outro);
2395 for (wordp = words; baseo--; wordp++)
2396 addword (*wordp);
2397 break;
2398 case DREG:
2399 tmpreg = opP->reg - DATA; /* 0.dreg */
2400 break;
2401 case AREG:
2402 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2403 break;
2404 case AINDR:
2405 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2406 break;
2407 case ADEC:
2408 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2409 break;
2410 case AINC:
2411 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2412 break;
2413 case DISP:
2414
3e602632 2415 nextword = get_num (&opP->disp, 90);
252b5132 2416
580b9172
NC		 2417 /* Convert mode 5 addressing with a zero offset into
2418 mode 2 addressing to reduce the instruction size by a
2419 word. */
2420 if (! isvar (&opP->disp)
2421 && (nextword == 0)
2422 && (opP->disp.size == SIZE_UNSPEC)
2423 && (opP->reg >= ADDR0)
2424 && (opP->reg <= ADDR7))
2425 {
2426 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2427 break;
2428 }
2429
252b5132
RH		 2430 if (opP->reg == PC
2431 && ! isvar (&opP->disp)
2432 && m68k_abspcadd)
2433 {
2434 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2435 opP->disp.exp.X_add_symbol =
2436 section_symbol (absolute_section);
252b5132
RH		 2437 }
2438
36759679 2439 /* Force into index mode. Hope this works. */
252b5132
RH		 2440
2441 /* We do the first bit for 32-bit displacements, and the
2442 second bit for 16 bit ones. It is possible that we
2443 should make the default be WORD instead of LONG, but
2444 I think that'd break GCC, so we put up with a little
2445 inefficiency for the sake of working output. */
2446
2447 if (!issword (nextword)
2448 || (isvar (&opP->disp)
2449 && ((opP->disp.size == SIZE_UNSPEC
2450 && flag_short_refs == 0
2451 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2452 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2453 || opP->disp.size == SIZE_LONG)))
2454 {
2455 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2456 || arch_coldfire_p (current_architecture))
252b5132
RH		 2457 opP->error =
2458 _("displacement too large for this architecture; needs 68020 or higher");
2459 if (opP->reg == PC)
2460 tmpreg = 0x3B; /* 7.3 */
2461 else
2462 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2463 if (isvar (&opP->disp))
2464 {
2465 if (opP->reg == PC)
2466 {
2467 if (opP->disp.size == SIZE_LONG
2468#ifdef OBJ_ELF
2469 /* If the displacement needs pic
2470 relocation it cannot be relaxed. */
2471 || opP->disp.pic_reloc != pic_none
2472#endif
2473 )
2474 {
2475 addword (0x0170);
2476 add_fix ('l', &opP->disp, 1, 2);
2477 }
2478 else
2479 {
2480 add_frag (adds (&opP->disp),
bd17c2c3 2481 SEXT (offs (&opP->disp)),
151337e8 2482 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2483 break;
2484 }
2485 }
2486 else
2487 {
2488 addword (0x0170);
2489 add_fix ('l', &opP->disp, 0, 0);
2490 }
2491 }
2492 else
2493 addword (0x0170);
2494 addword (nextword >> 16);
2495 }
2496 else
2497 {
2498 if (opP->reg == PC)
2499 tmpreg = 0x3A; /* 7.2 */
2500 else
2501 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2502
2503 if (isvar (&opP->disp))
2504 {
2505 if (opP->reg == PC)
2506 {
2507 add_fix ('w', &opP->disp, 1, 0);
2508 }
2509 else
2510 add_fix ('w', &opP->disp, 0, 0);
2511 }
2512 }
2513 addword (nextword);
2514 break;
2515
2516 case POST:
2517 case PRE:
2518 case BASE:
2519 nextword = 0;
3e602632 2520 baseo = get_num (&opP->disp, 90);
252b5132 2521 if (opP->mode == POST || opP->mode == PRE)
3e602632 2522 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2523 /* Figure out the `addressing mode'.
2524 Also turn on the BASE_DISABLE bit, if needed. */
2525 if (opP->reg == PC || opP->reg == ZPC)
2526 {
2527 tmpreg = 0x3b; /* 7.3 */
2528 if (opP->reg == ZPC)
2529 nextword |= 0x80;
2530 }
2531 else if (opP->reg == 0)
2532 {
2533 nextword |= 0x80;
2534 tmpreg = 0x30; /* 6.garbage */
2535 }
2536 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2537 {
2538 nextword |= 0x80;
2539 tmpreg = 0x30 + opP->reg - ZADDR0;
2540 }
2541 else
2542 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2543
2544 siz1 = opP->disp.size;
2545 if (opP->mode == POST || opP->mode == PRE)
2546 siz2 = opP->odisp.size;
2547 else
2548 siz2 = SIZE_UNSPEC;
2549
36759679 2550 /* Index register stuff. */
252b5132
RH		 2551 if (opP->index.reg != 0
2552 && opP->index.reg >= DATA
2553 && opP->index.reg <= ADDR7)
2554 {
2555 nextword |= (opP->index.reg - DATA) << 12;
2556
2557 if (opP->index.size == SIZE_LONG
2558 || (opP->index.size == SIZE_UNSPEC
2559 && m68k_index_width_default == SIZE_LONG))
2560 nextword |= 0x800;
2561
92774660 2562 if ((opP->index.scale != 1
252b5132 2563 && cpu_of_arch (current_architecture) < m68020)
92774660 2564 || (opP->index.scale == 8
3e602632 2565 && (arch_coldfire_p (current_architecture)
6b6e92f4 2566 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2567 {
2568 opP->error =
2569 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2570 }
2571
6da466c7
ILT		 2572 if (arch_coldfire_p (current_architecture)
2573 && opP->index.size == SIZE_WORD)
2574 opP->error = _("invalid index size for coldfire");
2575
252b5132
RH		 2576 switch (opP->index.scale)
2577 {
2578 case 1:
2579 break;
2580 case 2:
2581 nextword |= 0x200;
2582 break;
2583 case 4:
2584 nextword |= 0x400;
2585 break;
2586 case 8:
2587 nextword |= 0x600;
2588 break;
2589 default:
2590 abort ();
2591 }
2592 /* IF its simple,
2593 GET US OUT OF HERE! */
2594
2595 /* Must be INDEX, with an index register. Address
2596 register cannot be ZERO-PC, and either :b was
2597 forced, or we know it will fit. For a 68000 or
2598 68010, force this mode anyways, because the
2599 larger modes aren't supported. */
2600 if (opP->mode == BASE
2601 && ((opP->reg >= ADDR0
2602 && opP->reg <= ADDR7)
2603 || opP->reg == PC))
2604 {
2605 if (siz1 == SIZE_BYTE
2606 || cpu_of_arch (current_architecture) < m68020
6da466c7 2607 || arch_coldfire_p (current_architecture)
252b5132
RH		 2608 || (siz1 == SIZE_UNSPEC
2609 && ! isvar (&opP->disp)
2610 && issbyte (baseo)))
2611 {
2612 nextword += baseo & 0xff;
2613 addword (nextword);
2614 if (isvar (&opP->disp))
2615 {
2616 /* Do a byte relocation. If it doesn't
2617 fit (possible on m68000) let the
2618 fixup processing complain later. */
2619 if (opP->reg == PC)
2620 add_fix ('B', &opP->disp, 1, 1);
2621 else
2622 add_fix ('B', &opP->disp, 0, 0);
2623 }
2624 else if (siz1 != SIZE_BYTE)
2625 {
2626 if (siz1 != SIZE_UNSPEC)
2627 as_warn (_("Forcing byte displacement"));
2628 if (! issbyte (baseo))
2629 opP->error = _("byte displacement out of range");
2630 }
2631
2632 break;
2633 }
2634 else if (siz1 == SIZE_UNSPEC
2635 && opP->reg == PC
2636 && isvar (&opP->disp)
2637 && subs (&opP->disp) == NULL
2638#ifdef OBJ_ELF
2639 /* If the displacement needs pic
2640 relocation it cannot be relaxed. */
2641 && opP->disp.pic_reloc == pic_none
2642#endif
2643 )
2644 {
2645 /* The code in md_convert_frag_1 needs to be
2646 able to adjust nextword. Call frag_grow
2647 to ensure that we have enough space in
2648 the frag obstack to make all the bytes
2649 contiguous. */
2650 frag_grow (14);
8a104df9
KH		 2651 nextword += baseo & 0xff;
2652 addword (nextword);
bd17c2c3
AM		 2653 add_frag (adds (&opP->disp),
2654 SEXT (offs (&opP->disp)),
8a104df9 2655 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2656
2657 break;
8a104df9 2658 }
252b5132
RH		 2659 }
2660 }
2661 else
2662 {
36759679 2663 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2664 if (opP->index.reg >= ZDATA0
2665 && opP->index.reg <= ZDATA7)
2666 nextword |= (opP->index.reg - ZDATA0) << 12;
2667 else if (opP->index.reg >= ZADDR0
2668 || opP->index.reg <= ZADDR7)
2669 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2670 }
2671
2672 /* It isn't simple. */
2673
2674 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2675 || arch_coldfire_p (current_architecture))
252b5132
RH		 2676 opP->error =
2677 _("invalid operand mode for this architecture; needs 68020 or higher");
2678
2679 nextword |= 0x100;
2680 /* If the guy specified a width, we assume that it is
2681 wide enough. Maybe it isn't. If so, we lose. */
2682 switch (siz1)
2683 {
2684 case SIZE_UNSPEC:
2685 if (isvar (&opP->disp)
2686 ? m68k_rel32
2687 : ! issword (baseo))
2688 {
2689 siz1 = SIZE_LONG;
2690 nextword |= 0x30;
2691 }
2692 else if (! isvar (&opP->disp) && baseo == 0)
2693 nextword |= 0x10;
2694 else
2695 {
2696 nextword |= 0x20;
2697 siz1 = SIZE_WORD;
2698 }
2699 break;
2700 case SIZE_BYTE:
2701 as_warn (_(":b not permitted; defaulting to :w"));
2702 /* Fall through. */
2703 case SIZE_WORD:
2704 nextword |= 0x20;
2705 break;
2706 case SIZE_LONG:
2707 nextword |= 0x30;
2708 break;
2709 }
2710
67c1ffbe 2711 /* Figure out inner displacement stuff. */
252b5132
RH		 2712 if (opP->mode == POST || opP->mode == PRE)
2713 {
2714 if (cpu_of_arch (current_architecture) & cpu32)
2715 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2716 switch (siz2)
2717 {
2718 case SIZE_UNSPEC:
2719 if (isvar (&opP->odisp)
2720 ? m68k_rel32
2721 : ! issword (outro))
2722 {
2723 siz2 = SIZE_LONG;
2724 nextword |= 0x3;
2725 }
2726 else if (! isvar (&opP->odisp) && outro == 0)
2727 nextword |= 0x1;
2728 else
2729 {
2730 nextword |= 0x2;
2731 siz2 = SIZE_WORD;
2732 }
2733 break;
2734 case 1:
2735 as_warn (_(":b not permitted; defaulting to :w"));
2736 /* Fall through. */
2737 case 2:
2738 nextword |= 0x2;
2739 break;
2740 case 3:
2741 nextword |= 0x3;
2742 break;
2743 }
2744 if (opP->mode == POST
2745 && (nextword & 0x40) == 0)
2746 nextword |= 0x04;
2747 }
2748 addword (nextword);
2749
2750 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2751 {
2752 if (opP->reg == PC || opP->reg == ZPC)
2753 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2754 else
2755 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2756 }
2757 if (siz1 == SIZE_LONG)
2758 addword (baseo >> 16);
2759 if (siz1 != SIZE_UNSPEC)
2760 addword (baseo);
2761
2762 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2763 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2764 if (siz2 == SIZE_LONG)
2765 addword (outro >> 16);
2766 if (siz2 != SIZE_UNSPEC)
2767 addword (outro);
2768
2769 break;
2770
2771 case ABSL:
3e602632 2772 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2773 switch (opP->disp.size)
2774 {
2775 default:
2776 abort ();
2777 case SIZE_UNSPEC:
2778 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2779 {
2780 tmpreg = 0x38; /* 7.0 */
2781 addword (nextword);
2782 break;
2783 }
252b5132
RH		 2784 if (isvar (&opP->disp)
2785 && !subs (&opP->disp)
2786 && adds (&opP->disp)
2787#ifdef OBJ_ELF
2788 /* If the displacement needs pic relocation it
2789 cannot be relaxed. */
2790 && opP->disp.pic_reloc == pic_none
2791#endif
252b5132
RH		 2792 && !flag_long_jumps
2793 && !strchr ("~%&$?", s[0]))
2794 {
2795 tmpreg = 0x3A; /* 7.2 */
2796 add_frag (adds (&opP->disp),
bd17c2c3 2797 SEXT (offs (&opP->disp)),
151337e8 2798 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2799 break;
2800 }
36759679 2801 /* Fall through into long. */
252b5132
RH		 2802 case SIZE_LONG:
2803 if (isvar (&opP->disp))
2804 add_fix ('l', &opP->disp, 0, 0);
2805
2806 tmpreg = 0x39;/* 7.1 mode */
2807 addword (nextword >> 16);
2808 addword (nextword);
2809 break;
2810
2811 case SIZE_BYTE:
2812 as_bad (_("unsupported byte value; use a different suffix"));
2813 /* Fall through. */
36759679
NC		 2814
2815 case SIZE_WORD:
252b5132
RH		 2816 if (isvar (&opP->disp))
2817 add_fix ('w', &opP->disp, 0, 0);
2818
2819 tmpreg = 0x38;/* 7.0 mode */
2820 addword (nextword);
2821 break;
2822 }
2823 break;
2824 case CONTROL:
2825 case FPREG:
2826 default:
2827 as_bad (_("unknown/incorrect operand"));
bc805888 2828 /* abort (); */
252b5132 2829 }
fd99574b
NC		 2830
2831 /* If s[0] is '4', then this is for the mac instructions
2832 that can have a trailing_ampersand set. If so, set 0x100
2833 bit on tmpreg so install_gen_operand can check for it and
2834 set the appropriate bit (word2, bit 5). */
2835 if (s[0] == '4')
2836 {
2837 if (opP->trailing_ampersand)
2838 tmpreg |= 0x100;
2839 }
252b5132
RH		 2840 install_gen_operand (s[1], tmpreg);
2841 break;
2842
2843 case '#':
2844 case '^':
2845 switch (s[1])
2846 { /* JF: I hate floating point! */
2847 case 'j':
2848 tmpreg = 70;
2849 break;
2850 case '8':
2851 tmpreg = 20;
2852 break;
2853 case 'C':
2854 tmpreg = 50;
2855 break;
2856 case '3':
2857 default:
3e602632 2858 tmpreg = 90;
252b5132
RH		 2859 break;
2860 }
2861 tmpreg = get_num (&opP->disp, tmpreg);
2862 if (isvar (&opP->disp))
2863 add_fix (s[1], &opP->disp, 0, 0);
2864 switch (s[1])
2865 {
2866 case 'b': /* Danger: These do no check for
2867 certain types of overflow.
2868 user beware! */
2869 if (!isbyte (tmpreg))
2870 opP->error = _("out of range");
2871 insop (tmpreg, opcode);
2872 if (isvar (&opP->disp))
2873 the_ins.reloc[the_ins.nrel - 1].n =
2874 (opcode->m_codenum) * 2 + 1;
2875 break;
2876 case 'B':
2877 if (!issbyte (tmpreg))
2878 opP->error = _("out of range");
2879 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2880 if (isvar (&opP->disp))
2881 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2882 break;
2883 case 'w':
2884 if (!isword (tmpreg))
2885 opP->error = _("out of range");
2886 insop (tmpreg, opcode);
2887 if (isvar (&opP->disp))
2888 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2889 break;
2890 case 'W':
2891 if (!issword (tmpreg))
2892 opP->error = _("out of range");
2893 insop (tmpreg, opcode);
2894 if (isvar (&opP->disp))
2895 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2896 break;
2897 case 'l':
2898 /* Because of the way insop works, we put these two out
2899 backwards. */
2900 insop (tmpreg, opcode);
2901 insop (tmpreg >> 16, opcode);
2902 if (isvar (&opP->disp))
2903 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2904 break;
2905 case '3':
2906 tmpreg &= 0xFF;
2907 case '8':
2908 case 'C':
2909 case 'j':
2910 install_operand (s[1], tmpreg);
2911 break;
2912 default:
2913 abort ();
2914 }
2915 break;
2916
2917 case '+':
2918 case '-':
2919 case 'A':
2920 case 'a':
2921 install_operand (s[1], opP->reg - ADDR);
2922 break;
2923
2924 case 'B':
3e602632 2925 tmpreg = get_num (&opP->disp, 90);
9a2e615a 2926
252b5132
RH		 2927 switch (s[1])
2928 {
2929 case 'B':
8390138c 2930 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2931 break;
2932 case 'W':
2933 add_fix ('w', &opP->disp, 1, 0);
2934 addword (0);
2935 break;
2936 case 'L':
2937 long_branch:
151337e8 2938 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2939 add_fix ('l', &opP->disp, 1, 0);
2940 addword (0);
2941 addword (0);
2942 break;
9a2e615a
NS		 2943 case 'g': /* Conditional branch */
2944 have_disp = HAVE_LONG_CALL (current_architecture);
2945 goto var_branch;
2946
2947 case 'b': /* Unconditional branch */
2948 have_disp = HAVE_LONG_BRANCH (current_architecture);
2949 goto var_branch;
2950
2951 case 's': /* Unconditional subroutine */
2952 have_disp = HAVE_LONG_CALL (current_architecture);
2953
2954 var_branch:
2955 if (subs (&opP->disp) /* We can't relax it. */
252b5132 2956#ifdef OBJ_ELF
9a2e615a
NS		 2957 /* If the displacement needs pic relocation it cannot be
2958 relaxed. */
2959 || opP->disp.pic_reloc != pic_none
252b5132 2960#endif
9a2e615a
NS		 2961 || 0)
2962 {
2963 if (!have_disp)
2964 as_warn (_("Can't use long branches on this architecture"));
2965 goto long_branch;
2966 }
2967
252b5132 2968 /* This could either be a symbol, or an absolute
151337e8
NC		 2969 address. If it's an absolute address, turn it into
2970 an absolute jump right here and keep it out of the
2971 relaxer. */
2972 if (adds (&opP->disp) == 0)
2973 {
2974 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2975 the_ins.opcode[0] = 0x4EF9;
151337e8 2976 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2977 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2978 else /* jCC */
2979 {
2980 the_ins.opcode[0] ^= 0x0100;
2981 the_ins.opcode[0] |= 0x0006;
18566f55 2982 addword (0x4EF9);
151337e8
NC		 2983 }
2984 add_fix ('l', &opP->disp, 0, 0);
2985 addword (0);
2986 addword (0);
2987 break;
2988 }
2989
2990 /* Now we know it's going into the relaxer. Now figure
2991 out which mode. We try in this order of preference:
2992 long branch, absolute jump, byte/word branches only. */
9a2e615a 2993 if (have_disp)
bd17c2c3
AM		 2994 add_frag (adds (&opP->disp),
2995 SEXT (offs (&opP->disp)),
151337e8
NC		 2996 TAB (BRANCHBWL, SZ_UNDEF));
2997 else if (! flag_keep_pcrel)
2998 {
2999 if ((the_ins.opcode[0] == 0x6000)
3000 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 3001 add_frag (adds (&opP->disp),
3002 SEXT (offs (&opP->disp)),
151337e8
NC		 3003 TAB (BRABSJUNC, SZ_UNDEF));
3004 else
bd17c2c3
AM		 3005 add_frag (adds (&opP->disp),
3006 SEXT (offs (&opP->disp)),
151337e8
NC		 3007 TAB (BRABSJCOND, SZ_UNDEF));
3008 }
252b5132 3009 else
bd17c2c3
AM		 3010 add_frag (adds (&opP->disp),
3011 SEXT (offs (&opP->disp)),
151337e8 3012 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 3013 break;
3014 case 'w':
3015 if (isvar (&opP->disp))
3016 {
151337e8
NC		 3017 /* Check for DBcc instructions. We can relax them,
3018 but only if we have long branches and/or absolute
3019 jumps. */
3020 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3021 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3022 || ! flag_keep_pcrel))
252b5132 3023 {
151337e8 3024 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3025 add_frag (adds (&opP->disp),
3026 SEXT (offs (&opP->disp)),
151337e8
NC		 3027 TAB (DBCCLBR, SZ_UNDEF));
3028 else
bd17c2c3
AM		 3029 add_frag (adds (&opP->disp),
3030 SEXT (offs (&opP->disp)),
151337e8 3031 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3032 break;
3033 }
252b5132
RH		 3034 add_fix ('w', &opP->disp, 1, 0);
3035 }
3036 addword (0);
3037 break;
36759679 3038 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3039 add_fix ('l', &opP->disp, 1, 0);
3040 addword (0);
3041 addword (0);
3042 break;
36759679 3043 case 'c': /* Var size Coprocesssor branches. */
151337e8 3044 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3045 {
252b5132
RH		 3046 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3047 add_fix ('l', &opP->disp, 1, 0);
3048 addword (0);
3049 addword (0);
3050 }
151337e8 3051 else
bd17c2c3
AM		 3052 add_frag (adds (&opP->disp),
3053 SEXT (offs (&opP->disp)),
151337e8 3054 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3055 break;
3056 default:
3057 abort ();
3058 }
3059 break;
3060
36759679 3061 case 'C': /* Ignore it. */
252b5132
RH		 3062 break;
3063
36759679 3064 case 'd': /* JF this is a kludge. */
252b5132 3065 install_operand ('s', opP->reg - ADDR);
3e602632 3066 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3067 if (!issword (tmpreg))
3068 {
3069 as_warn (_("Expression out of range, using 0"));
3070 tmpreg = 0;
3071 }
3072 addword (tmpreg);
3073 break;
3074
3075 case 'D':
3076 install_operand (s[1], opP->reg - DATA);
3077 break;
3078
fd99574b
NC		 3079 case 'e': /* EMAC ACCx, reg/reg. */
3080 install_operand (s[1], opP->reg - ACC);
3081 break;
3082
36759679 3083 case 'E': /* Ignore it. */
6da466c7
ILT		 3084 break;
3085
252b5132
RH		 3086 case 'F':
3087 install_operand (s[1], opP->reg - FP0);
3088 break;
3089
fd99574b
NC		 3090 case 'g': /* EMAC ACCEXTx. */
3091 install_operand (s[1], opP->reg - ACCEXT01);
3092 break;
3093
36759679 3094 case 'G': /* Ignore it. */
6da466c7
ILT		 3095 case 'H':
3096 break;
3097
252b5132
RH		 3098 case 'I':
3099 tmpreg = opP->reg - COP0;
3100 install_operand (s[1], tmpreg);
3101 break;
3102
fd99574b
NC		 3103 case 'i': /* MAC/EMAC scale factor. */
3104 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3105 break;
3106
36759679 3107 case 'J': /* JF foo. */
252b5132
RH		 3108 switch (opP->reg)
3109 {
3110 case SFC:
3111 tmpreg = 0x000;
3112 break;
3113 case DFC:
3114 tmpreg = 0x001;
3115 break;
3116 case CACR:
3117 tmpreg = 0x002;
3118 break;
3119 case TC:
a8e24a56 3120 case ASID:
252b5132
RH		 3121 tmpreg = 0x003;
3122 break;
3e602632 3123 case ACR0:
252b5132
RH		 3124 case ITT0:
3125 tmpreg = 0x004;
3126 break;
3e602632 3127 case ACR1:
252b5132
RH		 3128 case ITT1:
3129 tmpreg = 0x005;
3130 break;
3e602632 3131 case ACR2:
252b5132
RH		 3132 case DTT0:
3133 tmpreg = 0x006;
3134 break;
3e602632 3135 case ACR3:
252b5132
RH		 3136 case DTT1:
3137 tmpreg = 0x007;
3138 break;
3139 case BUSCR:
a8e24a56 3140 case MMUBAR:
252b5132
RH		 3141 tmpreg = 0x008;
3142 break;
3143
3144 case USP:
3145 tmpreg = 0x800;
3146 break;
3147 case VBR:
3148 tmpreg = 0x801;
3149 break;
3150 case CAAR:
3151 tmpreg = 0x802;
3152 break;
3153 case MSP:
3154 tmpreg = 0x803;
3155 break;
3156 case ISP:
3157 tmpreg = 0x804;
3158 break;
3159 case MMUSR:
3160 tmpreg = 0x805;
3161 break;
3162 case URP:
3163 tmpreg = 0x806;
3164 break;
3165 case SRP:
3166 tmpreg = 0x807;
3167 break;
3168 case PCR:
3169 tmpreg = 0x808;
3170 break;
3171 case ROMBAR:
a8e24a56 3172 case ROMBAR0:
252b5132
RH		 3173 tmpreg = 0xC00;
3174 break;
3e602632
NC		 3175 case ROMBAR1:
3176 tmpreg = 0xC01;
3177 break;
3178 case FLASHBAR:
252b5132 3179 case RAMBAR0:
78336706 3180 case RAMBAR_ALT:
252b5132
RH		 3181 tmpreg = 0xC04;
3182 break;
3e602632 3183 case RAMBAR:
252b5132
RH		 3184 case RAMBAR1:
3185 tmpreg = 0xC05;
3186 break;
3e602632
NC		 3187 case MPCR:
3188 tmpreg = 0xC0C;
3189 break;
3190 case EDRAMBAR:
3191 tmpreg = 0xC0D;
3192 break;
3193 case MBAR0:
e80e0390 3194 case MBAR2:
3e602632
NC		 3195 case SECMBAR:
3196 tmpreg = 0xC0E;
3197 break;
3198 case MBAR1:
252b5132
RH		 3199 case MBAR:
3200 tmpreg = 0xC0F;
3201 break;
3e602632
NC		 3202 case PCR1U0:
3203 tmpreg = 0xD02;
3204 break;
3205 case PCR1L0:
3206 tmpreg = 0xD03;
3207 break;
3208 case PCR2U0:
3209 tmpreg = 0xD04;
3210 break;
3211 case PCR2L0:
3212 tmpreg = 0xD05;
3213 break;
3214 case PCR3U0:
3215 tmpreg = 0xD06;
3216 break;
3217 case PCR3L0:
3218 tmpreg = 0xD07;
3219 break;
3220 case PCR1L1:
3221 tmpreg = 0xD0A;
3222 break;
3223 case PCR1U1:
3224 tmpreg = 0xD0B;
3225 break;
3226 case PCR2L1:
3227 tmpreg = 0xD0C;
3228 break;
3229 case PCR2U1:
3230 tmpreg = 0xD0D;
3231 break;
3232 case PCR3L1:
3233 tmpreg = 0xD0E;
3234 break;
3235 case PCR3U1:
3236 tmpreg = 0xD0F;
3237 break;
f7ec513b
KH		 3238 case CAC:
3239 tmpreg = 0xFFE;
3240 break;
3241 case MBB:
3242 tmpreg = 0xFFF;
3243 break;
252b5132
RH		 3244 default:
3245 abort ();
3246 }
3247 install_operand (s[1], tmpreg);
3248 break;
3249
3250 case 'k':
3251 tmpreg = get_num (&opP->disp, 55);
3252 install_operand (s[1], tmpreg & 0x7f);
3253 break;
3254
3255 case 'l':
3256 tmpreg = opP->mask;
3257 if (s[1] == 'w')
3258 {
3259 if (tmpreg & 0x7FF0000)
3260 as_bad (_("Floating point register in register list"));
3261 insop (reverse_16_bits (tmpreg), opcode);
3262 }
3263 else
3264 {
3265 if (tmpreg & 0x700FFFF)
3266 as_bad (_("Wrong register in floating-point reglist"));
3267 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3268 }
3269 break;
3270
3271 case 'L':
3272 tmpreg = opP->mask;
3273 if (s[1] == 'w')
3274 {
3275 if (tmpreg & 0x7FF0000)
3276 as_bad (_("Floating point register in register list"));
3277 insop (tmpreg, opcode);
3278 }
3279 else if (s[1] == '8')
3280 {
3281 if (tmpreg & 0x0FFFFFF)
3282 as_bad (_("incorrect register in reglist"));
3283 install_operand (s[1], tmpreg >> 24);
3284 }
3285 else
3286 {
3287 if (tmpreg & 0x700FFFF)
3288 as_bad (_("wrong register in floating-point reglist"));
3289 else
3290 install_operand (s[1], tmpreg >> 16);
3291 }
3292 break;
3293
3294 case 'M':
3295 install_operand (s[1], get_num (&opP->disp, 60));
3296 break;
3297
3298 case 'O':
3299 tmpreg = ((opP->mode == DREG)
8fce3f5e 3300 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3301 : (get_num (&opP->disp, 40) & 0x1F));
3302 install_operand (s[1], tmpreg);
3303 break;
3304
3305 case 'Q':
3306 tmpreg = get_num (&opP->disp, 10);
3307 if (tmpreg == 8)
3308 tmpreg = 0;
3309 install_operand (s[1], tmpreg);
3310 break;
3311
3312 case 'R':
3313 /* This depends on the fact that ADDR registers are eight
3314 more than their corresponding DATA regs, so the result
36759679 3315 will have the ADDR_REG bit set. */
252b5132
RH		 3316 install_operand (s[1], opP->reg - DATA);
3317 break;
3318
3319 case 'r':
3320 if (opP->mode == AINDR)
3321 install_operand (s[1], opP->reg - DATA);
3322 else
3323 install_operand (s[1], opP->index.reg - DATA);
3324 break;
3325
3326 case 's':
3327 if (opP->reg == FPI)
3328 tmpreg = 0x1;
3329 else if (opP->reg == FPS)
3330 tmpreg = 0x2;
3331 else if (opP->reg == FPC)
3332 tmpreg = 0x4;
3333 else
3334 abort ();
3335 install_operand (s[1], tmpreg);
3336 break;
3337
36759679 3338 case 'S': /* Ignore it. */
252b5132
RH		 3339 break;
3340
3341 case 'T':
3342 install_operand (s[1], get_num (&opP->disp, 30));
3343 break;
3344
36759679 3345 case 'U': /* Ignore it. */
252b5132
RH		 3346 break;
3347
3348 case 'c':
3349 switch (opP->reg)
3350 {
3351 case NC:
3352 tmpreg = 0;
3353 break;
3354 case DC:
3355 tmpreg = 1;
3356 break;
3357 case IC:
3358 tmpreg = 2;
3359 break;
3360 case BC:
3361 tmpreg = 3;
3362 break;
3363 default:
3364 as_fatal (_("failed sanity check"));
36759679 3365 } /* switch on cache token. */
252b5132
RH		 3366 install_operand (s[1], tmpreg);
3367 break;
3368#ifndef NO_68851
92774660 3369 /* JF: These are out of order, I fear. */
252b5132
RH		 3370 case 'f':
3371 switch (opP->reg)
3372 {
3373 case SFC:
3374 tmpreg = 0;
3375 break;
3376 case DFC:
3377 tmpreg = 1;
3378 break;
3379 default:
3380 abort ();
3381 }
3382 install_operand (s[1], tmpreg);
3383 break;
3384
3385 case '0':
3386 case '1':
3387 case '2':
3388 switch (opP->reg)
3389 {
3390 case TC:
3391 tmpreg = 0;
3392 break;
3393 case CAL:
3394 tmpreg = 4;
3395 break;
3396 case VAL:
3397 tmpreg = 5;
3398 break;
3399 case SCC:
3400 tmpreg = 6;
3401 break;
3402 case AC:
3403 tmpreg = 7;
3404 break;
3405 default:
3406 abort ();
3407 }
3408 install_operand (s[1], tmpreg);
3409 break;
3410
3411 case 'V':
3412 if (opP->reg == VAL)
3413 break;
3414 abort ();
3415
3416 case 'W':
3417 switch (opP->reg)
3418 {
3419 case DRP:
3420 tmpreg = 1;
3421 break;
3422 case SRP:
3423 tmpreg = 2;
3424 break;
3425 case CRP:
3426 tmpreg = 3;
3427 break;
3428 default:
3429 abort ();
3430 }
3431 install_operand (s[1], tmpreg);
3432 break;
3433
3434 case 'X':
3435 switch (opP->reg)
3436 {
3437 case BAD:
3438 case BAD + 1:
3439 case BAD + 2:
3440 case BAD + 3:
3441 case BAD + 4:
3442 case BAD + 5:
3443 case BAD + 6:
3444 case BAD + 7:
3445 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3446 break;
3447
3448 case BAC:
3449 case BAC + 1:
3450 case BAC + 2:
3451 case BAC + 3:
3452 case BAC + 4:
3453 case BAC + 5:
3454 case BAC + 6:
3455 case BAC + 7:
3456 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3457 break;
3458
3459 default:
3460 abort ();
3461 }
3462 install_operand (s[1], tmpreg);
3463 break;
3464 case 'Y':
3465 know (opP->reg == PSR);
3466 break;
3467 case 'Z':
3468 know (opP->reg == PCSR);
3469 break;
3470#endif /* m68851 */
3471 case '3':
3472 switch (opP->reg)
3473 {
3474 case TT0:
3475 tmpreg = 2;
3476 break;
3477 case TT1:
3478 tmpreg = 3;
3479 break;
3480 default:
3481 abort ();
3482 }
3483 install_operand (s[1], tmpreg);
3484 break;
3485 case 't':
3486 tmpreg = get_num (&opP->disp, 20);
3487 install_operand (s[1], tmpreg);
3488 break;
36759679 3489 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3490 if (isvar (&opP->disp))
3491 add_fix ('l', &opP->disp, 0, 0);
3e602632 3492 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3493 addword (tmpreg >> 16);
3494 addword (tmpreg & 0xFFFF);
3495 break;
6da466c7
ILT		 3496 case 'u':
3497 install_operand (s[1], opP->reg - DATA0L);
3498 opP->reg -= (DATA0L);
36759679 3499 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3500 break;
3e602632
NC		 3501 case 'x':
3502 tmpreg = get_num (&opP->disp, 80);
3503 if (tmpreg == -1)
3504 tmpreg = 0;
3505 install_operand (s[1], tmpreg);
3506 break;
afa2158f
NS		 3507 case 'j':
3508 tmpreg = get_num (&opP->disp, 10);
3509 install_operand (s[1], tmpreg - 1);
3510 break;
3511 case 'K':
3512 tmpreg = get_num (&opP->disp, 65);
3513 install_operand (s[1], tmpreg);
3514 break;
252b5132
RH		 3515 default:
3516 abort ();
3517 }
3518 }
3519
3520 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3521 instruction, ready to be emitted. . . */
252b5132
RH		 3522}
3523
3524static int
31302357 3525reverse_16_bits (int in)
252b5132
RH		 3526{
3527 int out = 0;
3528 int n;
3529
3530 static int mask[16] =
3531 {
3532 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3533 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3534 };
3535 for (n = 0; n < 16; n++)
3536 {
3537 if (in & mask[n])
3538 out |= mask[15 - n];
3539 }
3540 return out;
3541} /* reverse_16_bits() */
3542
3543static int
31302357 3544reverse_8_bits (int in)
252b5132
RH		 3545{
3546 int out = 0;
3547 int n;
3548
3549 static int mask[8] =
3550 {
3551 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3552 };
3553
3554 for (n = 0; n < 8; n++)
3555 {
3556 if (in & mask[n])
3557 out |= mask[7 - n];
3558 }
3559 return out;
3560} /* reverse_8_bits() */
3561
3562/* Cause an extra frag to be generated here, inserting up to 10 bytes
3563 (that value is chosen in the frag_var call in md_assemble). TYPE
3564 is the subtype of the frag to be generated; its primary type is
3565 rs_machine_dependent.
3566
3567 The TYPE parameter is also used by md_convert_frag_1 and
3568 md_estimate_size_before_relax. The appropriate type of fixup will
3569 be emitted by md_convert_frag_1.
3570
3571 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3572static void
31302357 3573install_operand (int mode, int val)
252b5132
RH		 3574{
3575 switch (mode)
3576 {
3577 case 's':
36759679 3578 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3579 break;
3580 case 'd':
3581 the_ins.opcode[0] |= val << 9;
3582 break;
afa2158f
NS		 3583 case 'E':
3584 the_ins.opcode[1] |= val << 9;
3585 break;
252b5132
RH		 3586 case '1':
3587 the_ins.opcode[1] |= val << 12;
3588 break;
3589 case '2':
3590 the_ins.opcode[1] |= val << 6;
3591 break;
3592 case '3':
3593 the_ins.opcode[1] |= val;
3594 break;
3595 case '4':
3596 the_ins.opcode[2] |= val << 12;
3597 break;
3598 case '5':
3599 the_ins.opcode[2] |= val << 6;
3600 break;
3601 case '6':
3602 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3603 three words long! */
3604 the_ins.numo++;
3605 the_ins.opcode[2] |= val;
3606 break;
3607 case '7':
3608 the_ins.opcode[1] |= val << 7;
3609 break;
3610 case '8':
3611 the_ins.opcode[1] |= val << 10;
3612 break;
3613#ifndef NO_68851
3614 case '9':
3615 the_ins.opcode[1] |= val << 5;
3616 break;
3617#endif
3618
3619 case 't':
3620 the_ins.opcode[1] |= (val << 10) | (val << 7);
3621 break;
3622 case 'D':
3623 the_ins.opcode[1] |= (val << 12) | val;
3624 break;
3625 case 'g':
3626 the_ins.opcode[0] |= val = 0xff;
3627 break;
3628 case 'i':
3629 the_ins.opcode[0] |= val << 9;
3630 break;
3631 case 'C':
3632 the_ins.opcode[1] |= val;
3633 break;
3634 case 'j':
3635 the_ins.opcode[1] |= val;
36759679 3636 the_ins.numo++; /* What a hack. */
252b5132
RH		 3637 break;
3638 case 'k':
3639 the_ins.opcode[1] |= val << 4;
3640 break;
3641 case 'b':
3642 case 'w':
3643 case 'W':
3644 case 'l':
3645 break;
3646 case 'e':
3647 the_ins.opcode[0] |= (val << 6);
3648 break;
3649 case 'L':
3650 the_ins.opcode[1] = (val >> 16);
3651 the_ins.opcode[2] = val & 0xffff;
3652 break;
6da466c7
ILT		 3653 case 'm':
3654 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3655 the_ins.opcode[0] |= ((val & 0x7) << 9);
3656 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3657 break;
fd99574b 3658 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3659 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3660 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3661 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3662 break;
fd99574b 3663 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3664 the_ins.opcode[1] |= val << 12;
3665 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3666 break;
fd99574b 3667 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3668 the_ins.opcode[0] |= (val & 0xF);
3669 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3670 break;
fd99574b 3671 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3672 the_ins.opcode[1] |= (val & 0xF);
3673 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3674 break;
3675 case 'h':
3676 the_ins.opcode[1] |= ((val != 1) << 10);
3677 break;
fd99574b
NC		 3678 case 'F':
3679 the_ins.opcode[0] |= ((val & 0x3) << 9);
3680 break;
3681 case 'f':
3682 the_ins.opcode[0] |= ((val & 0x3) << 0);
3683 break;
be8c092b 3684 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3685 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3686 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3687 break;
be8c092b 3688 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3689 the_ins.opcode[0] |= ((val & 0x1) << 7);
3690 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3691 break;
3692 case 'I':
3693 the_ins.opcode[1] |= ((val & 0x3) << 9);
3694 break;
3695 case ']':
3696 the_ins.opcode[0] |= (val & 0x1) <<10;
3697 break;
252b5132
RH		 3698 case 'c':
3699 default:
3700 as_fatal (_("failed sanity check."));
3701 }
6b6e92f4 3702}
252b5132
RH		 3703
3704static void
31302357 3705install_gen_operand (int mode, int val)
252b5132
RH		 3706{
3707 switch (mode)
3708 {
fd99574b
NC		 3709 case '/': /* Special for mask loads for mac/msac insns with
3710 possible mask; trailing_ampersend set in bit 8. */
3711 the_ins.opcode[0] |= (val & 0x3f);
3712 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3713 break;
252b5132
RH		 3714 case 's':
3715 the_ins.opcode[0] |= val;
3716 break;
3717 case 'd':
3718 /* This is a kludge!!! */
3719 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3720 break;
3721 case 'b':
3722 case 'w':
3723 case 'l':
3724 case 'f':
3725 case 'F':
3726 case 'x':
3727 case 'p':
3728 the_ins.opcode[0] |= val;
3729 break;
36759679 3730 /* more stuff goes here. */
252b5132
RH		 3731 default:
3732 as_fatal (_("failed sanity check."));
3733 }
6b6e92f4 3734}
252b5132 3735
6b6e92f4
NC		 3736/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3737 then deal with the bitfield hack. */
252b5132
RH		 3738
3739static char *
31302357 3740crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3741{
3742 register int parens;
3743 register int c;
3744 register char *beg_str;
3745 int inquote = 0;
3746
3747 if (!str)
3748 {
3749 return str;
3750 }
3751 beg_str = str;
3752 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3753 {
3754 if (! inquote)
3755 {
3756 if (*str == '(')
3757 parens++;
3758 else if (*str == ')')
3759 {
3760 if (!parens)
36759679 3761 { /* ERROR. */
252b5132
RH		 3762 opP->error = _("Extra )");
3763 return str;
3764 }
3765 --parens;
3766 }
3767 }
3768 if (flag_mri && *str == '\'')
3769 inquote = ! inquote;
3770 }
3771 if (!*str && parens)
36759679 3772 { /* ERROR. */
252b5132
RH		 3773 opP->error = _("Missing )");
3774 return str;
3775 }
3776 c = *str;
3777 *str = '\0';
3778 if (m68k_ip_op (beg_str, opP) != 0)
3779 {
3780 *str = c;
3781 return str;
3782 }
3783 *str = c;
3784 if (c == '}')
36759679 3785 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3786 if (c)
3787 {
3788 c = *++str;
3789 if (!c)
3790 as_bad (_("Missing operand"));
3791 }
3792
3793 /* Detect MRI REG symbols and convert them to REGLSTs. */
3794 if (opP->mode == CONTROL && (int)opP->reg < 0)
3795 {
3796 opP->mode = REGLST;
3797 opP->mask = ~(int)opP->reg;
3798 opP->reg = 0;
3799 }
3800
3801 return str;
3802}
3803
3804/* This is the guts of the machine-dependent assembler. STR points to a
3805 machine dependent instruction. This function is supposed to emit
3806 the frags/bytes it assembles to.
3807 */
3808
3809static void
31302357 3810insert_reg (const char *regname, int regnum)
252b5132
RH		 3811{
3812 char buf[100];
3813 int i;
3814
3815#ifdef REGISTER_PREFIX
3816 if (!flag_reg_prefix_optional)
3817 {
3818 buf[0] = REGISTER_PREFIX;
3819 strcpy (buf + 1, regname);
3820 regname = buf;
3821 }
3822#endif
3823
3824 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3825 &zero_address_frag));
3826
3827 for (i = 0; regname[i]; i++)
3882b010 3828 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3829 buf[i] = '\0';
3830
3831 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3832 &zero_address_frag));
3833}
3834
3835struct init_entry
3836 {
3837 const char *name;
3838 int number;
3839 };
3840
3841static const struct init_entry init_table[] =
3842{
3843 { "d0", DATA0 },
3844 { "d1", DATA1 },
3845 { "d2", DATA2 },
3846 { "d3", DATA3 },
3847 { "d4", DATA4 },
3848 { "d5", DATA5 },
3849 { "d6", DATA6 },
3850 { "d7", DATA7 },
3851 { "a0", ADDR0 },
3852 { "a1", ADDR1 },
3853 { "a2", ADDR2 },
3854 { "a3", ADDR3 },
3855 { "a4", ADDR4 },
3856 { "a5", ADDR5 },
3857 { "a6", ADDR6 },
3858 { "fp", ADDR6 },
3859 { "a7", ADDR7 },
3860 { "sp", ADDR7 },
3861 { "ssp", ADDR7 },
3862 { "fp0", FP0 },
3863 { "fp1", FP1 },
3864 { "fp2", FP2 },
3865 { "fp3", FP3 },
3866 { "fp4", FP4 },
3867 { "fp5", FP5 },
3868 { "fp6", FP6 },
3869 { "fp7", FP7 },
3870 { "fpi", FPI },
3871 { "fpiar", FPI },
3872 { "fpc", FPI },
3873 { "fps", FPS },
3874 { "fpsr", FPS },
3875 { "fpc", FPC },
3876 { "fpcr", FPC },
3877 { "control", FPC },
3878 { "status", FPS },
3879 { "iaddr", FPI },
3880
3881 { "cop0", COP0 },
3882 { "cop1", COP1 },
3883 { "cop2", COP2 },
3884 { "cop3", COP3 },
3885 { "cop4", COP4 },
3886 { "cop5", COP5 },
3887 { "cop6", COP6 },
3888 { "cop7", COP7 },
3889 { "pc", PC },
3890 { "zpc", ZPC },
3891 { "sr", SR },
3892
3893 { "ccr", CCR },
3894 { "cc", CCR },
3895
6da466c7 3896 { "acc", ACC },
fd99574b
NC		 3897 { "acc0", ACC },
3898 { "acc1", ACC1 },
3899 { "acc2", ACC2 },
3900 { "acc3", ACC3 },
3901 { "accext01", ACCEXT01 },
3902 { "accext23", ACCEXT23 },
6da466c7
ILT		 3903 { "macsr", MACSR },
3904 { "mask", MASK },
3905
36759679
NC		 3906 /* Control registers. */
3907 { "sfc", SFC }, /* Source Function Code. */
252b5132 3908 { "sfcr", SFC },
36759679 3909 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3910 { "dfcr", DFC },
36759679
NC		 3911 { "cacr", CACR }, /* Cache Control Register. */
3912 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3913
36759679
NC		 3914 { "usp", USP }, /* User Stack Pointer. */
3915 { "vbr", VBR }, /* Vector Base Register. */
3916 { "msp", MSP }, /* Master Stack Pointer. */
3917 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3918
36759679
NC		 3919 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3920 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3921 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3922 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3923
3924 /* 68ec040 versions of same */
36759679
NC		 3925 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3926 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3927 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3928 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 3929
a8e24a56 3930 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 3931 manual indicated that the order is 2,3,0,1, but Ken Rose
3932 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3933 { "acr0", ACR0 }, /* Access Control Unit 0. */
3934 { "acr1", ACR1 }, /* Access Control Unit 1. */
3935 { "acr2", ACR2 }, /* Access Control Unit 2. */
3936 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3937
36759679 3938 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 3939 { "tcr", TC },
a8e24a56 3940 { "asid", ASID },
252b5132 3941
36759679
NC		 3942 { "mmusr", MMUSR }, /* MMU Status Register. */
3943 { "srp", SRP }, /* User Root Pointer. */
3944 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3945
3946 { "buscr", BUSCR },
a8e24a56 3947 { "mmubar", MMUBAR },
252b5132
RH		 3948 { "pcr", PCR },
3949
36759679
NC		 3950 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3951 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3952 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3953 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3954
3955 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3956 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 3957 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 3958 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3959 { "mpcr", MPCR }, /* mcfv4e registers. */
3960 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3961 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3962 { "asid", TC }, /* mcfv4e registers. */
3963 { "mmubar", BUSCR }, /* mcfv4e registers. */
3964 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3965 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3966 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3967 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3968 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3969 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3970 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3971 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3972 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3973 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3974 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3975 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3976
3977 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3978 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3979
3980 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b
KH		 3981
3982 { "cac", CAC }, /* fido registers. */
3983 { "mbb", MBB }, /* fido registers. */
36759679 3984 /* End of control registers. */
252b5132
RH		 3985
3986 { "ac", AC },
3987 { "bc", BC },
3988 { "cal", CAL },
3989 { "crp", CRP },
3990 { "drp", DRP },
3991 { "pcsr", PCSR },
3992 { "psr", PSR },
3993 { "scc", SCC },
3994 { "val", VAL },
3995 { "bad0", BAD0 },
3996 { "bad1", BAD1 },
3997 { "bad2", BAD2 },
3998 { "bad3", BAD3 },
3999 { "bad4", BAD4 },
4000 { "bad5", BAD5 },
4001 { "bad6", BAD6 },
4002 { "bad7", BAD7 },
4003 { "bac0", BAC0 },
4004 { "bac1", BAC1 },
4005 { "bac2", BAC2 },
4006 { "bac3", BAC3 },
4007 { "bac4", BAC4 },
4008 { "bac5", BAC5 },
4009 { "bac6", BAC6 },
4010 { "bac7", BAC7 },
4011
4012 { "ic", IC },
4013 { "dc", DC },
4014 { "nc", NC },
4015
4016 { "tt0", TT0 },
4017 { "tt1", TT1 },
36759679 4018 /* 68ec030 versions of same. */
252b5132
RH		 4019 { "ac0", TT0 },
4020 { "ac1", TT1 },
36759679 4021 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 4022 { "acusr", PSR },
4023
4024 /* Suppressed data and address registers. */
4025 { "zd0", ZDATA0 },
4026 { "zd1", ZDATA1 },
4027 { "zd2", ZDATA2 },
4028 { "zd3", ZDATA3 },
4029 { "zd4", ZDATA4 },
4030 { "zd5", ZDATA5 },
4031 { "zd6", ZDATA6 },
4032 { "zd7", ZDATA7 },
4033 { "za0", ZADDR0 },
4034 { "za1", ZADDR1 },
4035 { "za2", ZADDR2 },
4036 { "za3", ZADDR3 },
4037 { "za4", ZADDR4 },
4038 { "za5", ZADDR5 },
4039 { "za6", ZADDR6 },
4040 { "za7", ZADDR7 },
4041
92774660 4042 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4043 { "d0l", DATA0L },
4044 { "d1l", DATA1L },
4045 { "d2l", DATA2L },
4046 { "d3l", DATA3L },
4047 { "d4l", DATA4L },
4048 { "d5l", DATA5L },
4049 { "d6l", DATA6L },
4050 { "d7l", DATA7L },
4051
4052 { "a0l", ADDR0L },
4053 { "a1l", ADDR1L },
4054 { "a2l", ADDR2L },
4055 { "a3l", ADDR3L },
4056 { "a4l", ADDR4L },
4057 { "a5l", ADDR5L },
4058 { "a6l", ADDR6L },
4059 { "a7l", ADDR7L },
4060
4061 { "d0u", DATA0U },
4062 { "d1u", DATA1U },
4063 { "d2u", DATA2U },
4064 { "d3u", DATA3U },
4065 { "d4u", DATA4U },
4066 { "d5u", DATA5U },
4067 { "d6u", DATA6U },
4068 { "d7u", DATA7U },
4069
4070 { "a0u", ADDR0U },
4071 { "a1u", ADDR1U },
4072 { "a2u", ADDR2U },
4073 { "a3u", ADDR3U },
4074 { "a4u", ADDR4U },
4075 { "a5u", ADDR5U },
4076 { "a6u", ADDR6U },
4077 { "a7u", ADDR7U },
4078
252b5132
RH		 4079 { 0, 0 }
4080};
4081
4082static void
31302357 4083init_regtable (void)
252b5132
RH		 4084{
4085 int i;
4086 for (i = 0; init_table[i].name; i++)
4087 insert_reg (init_table[i].name, init_table[i].number);
4088}
4089
252b5132 4090void
31302357 4091md_assemble (char *str)
252b5132
RH		 4092{
4093 const char *er;
4094 short *fromP;
4095 char *toP = NULL;
4096 int m, n = 0;
4097 char *to_beg_P;
4098 int shorts_this_frag;
4099 fixS *fixP;
4100
266abb8f
NS		 4101 if (!selected_cpu && !selected_arch)
4102 {
4103 /* We've not selected an architecture yet. Set the default
4104 now. We do this lazily so that an initial .cpu or .arch directive
4105 can specify. */
4106 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4107 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4108 }
4109 if (!initialized)
4110 m68k_init_arch ();
4111
252b5132
RH		 4112 /* In MRI mode, the instruction and operands are separated by a
4113 space. Anything following the operands is a comment. The label
4114 has already been removed. */
4115 if (flag_mri)
4116 {
4117 char *s;
4118 int fields = 0;
4119 int infield = 0;
4120 int inquote = 0;
4121
4122 for (s = str; *s != '\0'; s++)
4123 {
4124 if ((*s == ' ' || *s == '\t') && ! inquote)
4125 {
4126 if (infield)
4127 {
4128 ++fields;
4129 if (fields >= 2)
4130 {
4131 *s = '\0';
4132 break;
4133 }
4134 infield = 0;
4135 }
4136 }
4137 else
4138 {
4139 if (! infield)
4140 infield = 1;
4141 if (*s == '\'')
4142 inquote = ! inquote;
4143 }
4144 }
4145 }
4146
31302357 4147 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4148 m68k_ip (str);
4149 er = the_ins.error;
4150 if (!er)
4151 {
4152 for (n = 0; n < the_ins.numargs; n++)
4153 if (the_ins.operands[n].error)
4154 {
4155 er = the_ins.operands[n].error;
4156 break;
4157 }
4158 }
4159 if (er)
4160 {
4161 as_bad (_("%s -- statement `%s' ignored"), er, str);
4162 return;
4163 }
4164
4165 /* If there is a current label, record that it marks an instruction. */
4166 if (current_label != NULL)
4167 {
4168 current_label->text = 1;
4169 current_label = NULL;
4170 }
4171
f27a3839
AS		 4172#ifdef OBJ_ELF
4173 /* Tie dwarf2 debug info to the address at the start of the insn. */
4174 dwarf2_emit_insn (0);
4175#endif
4176
252b5132
RH		 4177 if (the_ins.nfrag == 0)
4178 {
36759679 4179 /* No frag hacking involved; just put it out. */
252b5132
RH		 4180 toP = frag_more (2 * the_ins.numo);
4181 fromP = &the_ins.opcode[0];
4182 for (m = the_ins.numo; m; --m)
4183 {
4184 md_number_to_chars (toP, (long) (*fromP), 2);
4185 toP += 2;
4186 fromP++;
4187 }
36759679 4188 /* Put out symbol-dependent info. */
252b5132
RH		 4189 for (m = 0; m < the_ins.nrel; m++)
4190 {
4191 switch (the_ins.reloc[m].wid)
4192 {
4193 case 'B':
4194 n = 1;
4195 break;
4196 case 'b':
4197 n = 1;
4198 break;
4199 case '3':
4200 n = 1;
4201 break;
4202 case 'w':
4203 case 'W':
4204 n = 2;
4205 break;
4206 case 'l':
4207 n = 4;
4208 break;
4209 default:
4210 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4211 the_ins.reloc[m].wid);
4212 }
4213
4214 fixP = fix_new_exp (frag_now,
4215 ((toP - frag_now->fr_literal)
4216 - the_ins.numo * 2 + the_ins.reloc[m].n),
4217 n,
4218 &the_ins.reloc[m].exp,
4219 the_ins.reloc[m].pcrel,
4220 get_reloc_code (n, the_ins.reloc[m].pcrel,
4221 the_ins.reloc[m].pic_reloc));
4222 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4223 if (the_ins.reloc[m].wid == 'B')
4224 fixP->fx_signed = 1;
4225 }
4226 return;
4227 }
4228
36759679 4229 /* There's some frag hacking. */
fbe572f9
AM		 4230 {
4231 /* Calculate the max frag size. */
4232 int wid;
4233
4234 wid = 2 * the_ins.fragb[0].fragoff;
4235 for (n = 1; n < the_ins.nfrag; n++)
4236 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4237 /* frag_var part. */
4238 wid += 10;
4239 /* Make sure the whole insn fits in one chunk, in particular that
4240 the var part is attached, as we access one byte before the
4241 variable frag for byte branches. */
4242 frag_grow (wid);
4243 }
4244
252b5132
RH		 4245 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4246 {
4247 int wid;
4248
4249 if (n == 0)
4250 wid = 2 * the_ins.fragb[n].fragoff;
4251 else
4252 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4253 toP = frag_more (wid);
4254 to_beg_P = toP;
4255 shorts_this_frag = 0;
4256 for (m = wid / 2; m; --m)
4257 {
4258 md_number_to_chars (toP, (long) (*fromP), 2);
4259 toP += 2;
4260 fromP++;
4261 shorts_this_frag++;
4262 }
4263 for (m = 0; m < the_ins.nrel; m++)
4264 {
4265 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4266 {
4267 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4268 break;
4269 }
4270 wid = the_ins.reloc[m].wid;
4271 if (wid == 0)
4272 continue;
4273 the_ins.reloc[m].wid = 0;
4274 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4275
4276 fixP = fix_new_exp (frag_now,
4277 ((toP - frag_now->fr_literal)
4278 - the_ins.numo * 2 + the_ins.reloc[m].n),
4279 wid,
4280 &the_ins.reloc[m].exp,
4281 the_ins.reloc[m].pcrel,
4282 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4283 the_ins.reloc[m].pic_reloc));
4284 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4285 }
4286 (void) frag_var (rs_machine_dependent, 10, 0,
4287 (relax_substateT) (the_ins.fragb[n].fragty),
4288 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4289 }
4290 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4291 shorts_this_frag = 0;
4292 if (n)
4293 {
055d1eb0 4294 toP = frag_more (n * 2);
252b5132
RH		 4295 while (n--)
4296 {
4297 md_number_to_chars (toP, (long) (*fromP), 2);
4298 toP += 2;
4299 fromP++;
4300 shorts_this_frag++;
4301 }
4302 }
4303 for (m = 0; m < the_ins.nrel; m++)
4304 {
4305 int wid;
4306
4307 wid = the_ins.reloc[m].wid;
4308 if (wid == 0)
4309 continue;
4310 the_ins.reloc[m].wid = 0;
4311 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4312
4313 fixP = fix_new_exp (frag_now,
4314 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4315 - shorts_this_frag * 2),
4316 wid,
4317 &the_ins.reloc[m].exp,
4318 the_ins.reloc[m].pcrel,
4319 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4320 the_ins.reloc[m].pic_reloc));
4321 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4322 }
4323}
4324
60fed2d3
NC		 4325/* Comparison function used by qsort to rank the opcode entries by name. */
4326
4327static int
4328m68k_compare_opcode (const void * v1, const void * v2)
4329{
4330 struct m68k_opcode * op1, * op2;
4331 int ret;
4332
03b13e59
NC		 4333 if (v1 == v2)
4334 return 0;
4335
60fed2d3
NC		 4336 op1 = *(struct m68k_opcode **) v1;
4337 op2 = *(struct m68k_opcode **) v2;
4338
4339 /* Compare the two names. If different, return the comparison.
4340 If the same, return the order they are in the opcode table. */
4341 ret = strcmp (op1->name, op2->name);
4342 if (ret)
4343 return ret;
4344 if (op1 < op2)
4345 return -1;
03b13e59 4346 return 1;
60fed2d3
NC		 4347}
4348
252b5132 4349void
60fed2d3 4350md_begin (void)
252b5132 4351{
60fed2d3
NC		 4352 const struct m68k_opcode *ins;
4353 struct m68k_incant *hack, *slak;
4354 const char *retval = 0; /* Empty string, or error msg text. */
4355 int i;
4356
4357 /* Set up hash tables with 68000 instructions.
4358 similar to what the vax assembler does. */
252b5132
RH		 4359 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4360 a copy of it at runtime, adding in the information we want but isn't
4361 there. I think it'd be better to have an awk script hack the table
4362 at compile time. Or even just xstr the table and use it as-is. But
4363 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4364 names. */
4365
252b5132
RH		 4366 if (flag_mri)
4367 {
4368 flag_reg_prefix_optional = 1;
4369 m68k_abspcadd = 1;
4370 if (! m68k_rel32_from_cmdline)
4371 m68k_rel32 = 0;
4372 }
4373
60fed2d3
NC		 4374 /* First sort the opcode table into alphabetical order to seperate
4375 the order that the assembler wants to see the opcodes from the
4376 order that the disassembler wants to see them. */
4377 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4378 if (!m68k_sorted_opcodes)
4379 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4380 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4381
4382 for (i = m68k_numopcodes; i--;)
4383 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4384
4385 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4386 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4387
252b5132
RH		 4388 op_hash = hash_new ();
4389
4390 obstack_begin (&robyn, 4000);
4391 for (i = 0; i < m68k_numopcodes; i++)
4392 {
4393 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4394 do
4395 {
60fed2d3
NC		 4396 ins = m68k_sorted_opcodes[i];
4397
afa2158f
NS		 4398 /* We must enter all insns into the table, because .arch and
4399 .cpu directives can change things. */
252b5132 4400 slak->m_operands = ins->args;
252b5132
RH		 4401 slak->m_arch = ins->arch;
4402 slak->m_opcode = ins->opcode;
afa2158f
NS		 4403
4404 /* In most cases we can determine the number of opcode words
4405 by checking the second word of the mask. Unfortunately
4406 some instructions have 2 opcode words, but no fixed bits
4407 in the second word. A leading dot in the operands
4408 string also indicates 2 opcodes. */
4409 if (*slak->m_operands == '.')
4410 {
4411 slak->m_operands++;
4412 slak->m_codenum = 2;
4413 }
4414 else if (ins->match & 0xffffL)
4415 slak->m_codenum = 2;
4416 else
4417 slak->m_codenum = 1;
4418 slak->m_opnum = strlen (slak->m_operands) / 2;
4419
252b5132 4420 if (i + 1 != m68k_numopcodes
60fed2d3 4421 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4422 {
60fed2d3 4423 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4424 i++;
4425 }
4426 else
4427 slak->m_next = 0;
4428 slak = slak->m_next;
4429 }
4430 while (slak);
4431
4432 retval = hash_insert (op_hash, ins->name, (char *) hack);
4433 if (retval)
4434 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4435 }
4436
4437 for (i = 0; i < m68k_numaliases; i++)
4438 {
4439 const char *name = m68k_opcode_aliases[i].primary;
4440 const char *alias = m68k_opcode_aliases[i].alias;
4441 PTR val = hash_find (op_hash, name);
60fed2d3 4442
252b5132
RH		 4443 if (!val)
4444 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4445 retval = hash_insert (op_hash, alias, val);
4446 if (retval)
4447 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4448 }
4449
4450 /* In MRI mode, all unsized branches are variable sized. Normally,
4451 they are word sized. */
4452 if (flag_mri)
4453 {
4454 static struct m68k_opcode_alias mri_aliases[] =
4455 {
4456 { "bhi", "jhi", },
4457 { "bls", "jls", },
4458 { "bcc", "jcc", },
4459 { "bcs", "jcs", },
4460 { "bne", "jne", },
4461 { "beq", "jeq", },
4462 { "bvc", "jvc", },
4463 { "bvs", "jvs", },
4464 { "bpl", "jpl", },
4465 { "bmi", "jmi", },
4466 { "bge", "jge", },
4467 { "blt", "jlt", },
4468 { "bgt", "jgt", },
4469 { "ble", "jle", },
4470 { "bra", "jra", },
4471 { "bsr", "jbsr", },
4472 };
4473
8fce3f5e
AM		 4474 for (i = 0;
4475 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4476 i++)
252b5132
RH		 4477 {
4478 const char *name = mri_aliases[i].primary;
4479 const char *alias = mri_aliases[i].alias;
4480 PTR val = hash_find (op_hash, name);
60fed2d3 4481
252b5132
RH		 4482 if (!val)
4483 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4484 retval = hash_jam (op_hash, alias, val);
4485 if (retval)
4486 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4487 }
4488 }
4489
8fce3f5e 4490 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4491 {
4492 notend_table[i] = 0;
4493 alt_notend_table[i] = 0;
4494 }
60fed2d3 4495
252b5132
RH		 4496 notend_table[','] = 1;
4497 notend_table['{'] = 1;
4498 notend_table['}'] = 1;
4499 alt_notend_table['a'] = 1;
4500 alt_notend_table['A'] = 1;
4501 alt_notend_table['d'] = 1;
4502 alt_notend_table['D'] = 1;
4503 alt_notend_table['#'] = 1;
4504 alt_notend_table['&'] = 1;
4505 alt_notend_table['f'] = 1;
4506 alt_notend_table['F'] = 1;
4507#ifdef REGISTER_PREFIX
4508 alt_notend_table[REGISTER_PREFIX] = 1;
4509#endif
4510
4511 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4512 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4513 alt_notend_table['('] = 1;
4514
4515 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4516 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4517 alt_notend_table['@'] = 1;
4518
4519 /* We need to put digits in alt_notend_table to handle
60fed2d3 4520 bfextu %d0{24:1},%d0 */
252b5132
RH		 4521 alt_notend_table['0'] = 1;
4522 alt_notend_table['1'] = 1;
4523 alt_notend_table['2'] = 1;
4524 alt_notend_table['3'] = 1;
4525 alt_notend_table['4'] = 1;
4526 alt_notend_table['5'] = 1;
4527 alt_notend_table['6'] = 1;
4528 alt_notend_table['7'] = 1;
4529 alt_notend_table['8'] = 1;
4530 alt_notend_table['9'] = 1;
4531
4532#ifndef MIT_SYNTAX_ONLY
4533 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4534 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4535 {
4536 int n = 0;
60fed2d3 4537
252b5132
RH		 4538 while (mote_pseudo_table[n].poc_name)
4539 {
60fed2d3 4540 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4541 hash_insert (op_hash,
4542 mote_pseudo_table[n].poc_name, (char *) hack);
4543 hack->m_operands = 0;
4544 hack->m_opnum = n;
4545 n++;
4546 }
4547 }
4548#endif
4549
4550 init_regtable ();
4551
4552#ifdef OBJ_ELF
4553 record_alignment (text_section, 2);
4554 record_alignment (data_section, 2);
4555 record_alignment (bss_section, 2);
4556#endif
4557}
4558
252b5132
RH		 4559\f
4560/* This is called when a label is defined. */
4561
4562void
31302357 4563m68k_frob_label (symbolS *sym)
252b5132
RH		 4564{
4565 struct label_line *n;
4566
4567 n = (struct label_line *) xmalloc (sizeof *n);
4568 n->next = labels;
4569 n->label = sym;
4570 as_where (&n->file, &n->line);
4571 n->text = 0;
4572 labels = n;
4573 current_label = n;
07a53e5c
RH		 4574
4575#ifdef OBJ_ELF
4576 dwarf2_emit_label (sym);
4577#endif
252b5132
RH		 4578}
4579
4580/* This is called when a value that is not an instruction is emitted. */
4581
4582void
31302357 4583m68k_flush_pending_output (void)
252b5132
RH		 4584{
4585 current_label = NULL;
4586}
4587
4588/* This is called at the end of the assembly, when the final value of
4589 the label is known. We warn if this is a text symbol aligned at an
4590 odd location. */
4591
4592void
31302357 4593m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4594{
4595 if (S_GET_SEGMENT (sym) == reg_section
4596 && (int) S_GET_VALUE (sym) < 0)
4597 {
4598 S_SET_SEGMENT (sym, absolute_section);
4599 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4600 }
4601 else if ((S_GET_VALUE (sym) & 1) != 0)
4602 {
4603 struct label_line *l;
4604
4605 for (l = labels; l != NULL; l = l->next)
4606 {
4607 if (l->label == sym)
4608 {
4609 if (l->text)
4610 as_warn_where (l->file, l->line,
4611 _("text label `%s' aligned to odd boundary"),
4612 S_GET_NAME (sym));
4613 break;
4614 }
4615 }
4616 }
4617}
4618\f
4619/* This is called if we go in or out of MRI mode because of the .mri
4620 pseudo-op. */
4621
4622void
31302357 4623m68k_mri_mode_change (int on)
252b5132
RH		 4624{
4625 if (on)
4626 {
4627 if (! flag_reg_prefix_optional)
4628 {
4629 flag_reg_prefix_optional = 1;
4630#ifdef REGISTER_PREFIX
4631 init_regtable ();
4632#endif
4633 }
4634 m68k_abspcadd = 1;
4635 if (! m68k_rel32_from_cmdline)
4636 m68k_rel32 = 0;
4637 }
4638 else
4639 {
4640 if (! reg_prefix_optional_seen)
4641 {
4642#ifdef REGISTER_PREFIX_OPTIONAL
4643 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4644#else
4645 flag_reg_prefix_optional = 0;
4646#endif
4647#ifdef REGISTER_PREFIX
4648 init_regtable ();
4649#endif
4650 }
4651 m68k_abspcadd = 0;
4652 if (! m68k_rel32_from_cmdline)
4653 m68k_rel32 = 1;
4654 }
4655}
4656
36759679 4657/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4658#define MAX_LITTLENUMS 6
4659
4660/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4661 of type TYPE, and store the appropriate bytes in *LITP. The number
4662 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4663 returned, or NULL on OK. */
4664
4665char *
31302357 4666md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4667{
4668 int prec;
4669 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4670 LITTLENUM_TYPE *wordP;
4671 char *t;
4672
4673 switch (type)
4674 {
4675 case 'f':
4676 case 'F':
4677 case 's':
4678 case 'S':
4679 prec = 2;
4680 break;
4681
4682 case 'd':
4683 case 'D':
4684 case 'r':
4685 case 'R':
4686 prec = 4;
4687 break;
4688
4689 case 'x':
4690 case 'X':
4691 prec = 6;
4692 break;
4693
4694 case 'p':
4695 case 'P':
4696 prec = 6;
4697 break;
4698
4699 default:
4700 *sizeP = 0;
4701 return _("Bad call to MD_ATOF()");
4702 }
4703 t = atof_ieee (input_line_pointer, type, words);
4704 if (t)
4705 input_line_pointer = t;
4706
4707 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4708 for (wordP = words; prec--;)
4709 {
4710 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4711 litP += sizeof (LITTLENUM_TYPE);
4712 }
4713 return 0;
4714}
4715
4716void
31302357 4717md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4718{
4719 number_to_chars_bigendian (buf, val, n);
4720}
4721
94f592af 4722void
55cf6793 4723md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4724{
bbe8ef22 4725 offsetT val = *valP;
252b5132
RH		 4726 addressT upper_limit;
4727 offsetT lower_limit;
4728
4729 /* This is unnecessary but it convinces the native rs6000 compiler
4730 to generate the code we want. */
4731 char *buf = fixP->fx_frag->fr_literal;
4732 buf += fixP->fx_where;
36759679 4733 /* End ibm compiler workaround. */
252b5132 4734
bd17c2c3 4735 val = SEXT (val);
252b5132 4736
94f592af
NC		 4737 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4738 fixP->fx_done = 1;
4739
252b5132
RH		 4740#ifdef OBJ_ELF
4741 if (fixP->fx_addsy)
4742 {
4743 memset (buf, 0, fixP->fx_size);
36759679 4744 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4745
4746 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4747 && !S_IS_DEFINED (fixP->fx_addsy)
4748 && !S_IS_WEAK (fixP->fx_addsy))
4749 S_SET_WEAK (fixP->fx_addsy);
4750 return;
4751 }
22184a77 4752#elif defined(OBJ_AOUT)
1c3f20b4 4753 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
22184a77
NC		 4754 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4755 {
4756 memset (buf, 0, fixP->fx_size);
1c3f20b4 4757 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
22184a77
NC		 4758 return;
4759 }
252b5132
RH		 4760#endif
4761
252b5132
RH		 4762 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4763 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4764 return;
252b5132
RH		 4765
4766 switch (fixP->fx_size)
4767 {
94f592af
NC		 4768 /* The cast to offsetT below are necessary to make code
4769 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4770 case 1:
4771 *buf++ = val;
4772 upper_limit = 0x7f;
4773 lower_limit = - (offsetT) 0x80;
4774 break;
4775 case 2:
4776 *buf++ = (val >> 8);
4777 *buf++ = val;
4778 upper_limit = 0x7fff;
4779 lower_limit = - (offsetT) 0x8000;
4780 break;
4781 case 4:
4782 *buf++ = (val >> 24);
4783 *buf++ = (val >> 16);
4784 *buf++ = (val >> 8);
4785 *buf++ = val;
4786 upper_limit = 0x7fffffff;
36759679 4787 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4788 break;
4789 default:
4790 BAD_CASE (fixP->fx_size);
4791 }
4792
4793 /* Fix up a negative reloc. */
4794 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4795 {
4796 fixP->fx_addsy = fixP->fx_subsy;
4797 fixP->fx_subsy = NULL;
4798 fixP->fx_tcbit = 1;
4799 }
4800
4801 /* For non-pc-relative values, it's conceivable we might get something
4802 like "0xff" for a byte field. So extend the upper part of the range
4803 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4804 so that we can do any range checking at all. */
4805 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4806 upper_limit = upper_limit * 2 + 1;
4807
4808 if ((addressT) val > upper_limit
4809 && (val > 0 || val < lower_limit))
2b878742
NS		 4810 as_bad_where (fixP->fx_file, fixP->fx_line,
4811 _("value %ld out of range"), (long)val);
252b5132
RH		 4812
4813 /* A one byte PC-relative reloc means a short branch. We can't use
4814 a short branch with a value of 0 or -1, because those indicate
4815 different opcodes (branches with longer offsets). fixup_segment
4816 in write.c may have clobbered fx_pcrel, so we need to examine the
4817 reloc type. */
4818 if ((fixP->fx_pcrel
7be1c489 4819 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4820 && fixP->fx_size == 1
4821 && (fixP->fx_addsy == NULL
4822 || S_IS_DEFINED (fixP->fx_addsy))
4823 && (val == 0 || val == -1))
2b878742
NS		 4824 as_bad_where (fixP->fx_file, fixP->fx_line,
4825 _("invalid byte branch offset"));
252b5132
RH		 4826}
4827
252b5132
RH		 4828/* *fragP has been relaxed to its final size, and now needs to have
4829 the bytes inside it modified to conform to the new size There is UGLY
4830 MAGIC here. ..
4831 */
4832static void
31302357 4833md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4834{
4835 long disp;
2b878742 4836 fixS *fixP = NULL;
252b5132
RH		 4837
4838 /* Address in object code of the displacement. */
4839 register int object_address = fragP->fr_fix + fragP->fr_address;
4840
4841 /* Address in gas core of the place to store the displacement. */
4842 /* This convinces the native rs6000 compiler to generate the code we
92774660 4843 want. */
252b5132
RH		 4844 register char *buffer_address = fragP->fr_literal;
4845 buffer_address += fragP->fr_fix;
36759679 4846 /* End ibm compiler workaround. */
252b5132
RH		 4847
4848 /* The displacement of the address, from current location. */
4849 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4850 disp = (disp + fragP->fr_offset) - object_address;
4851
252b5132
RH		 4852 switch (fragP->fr_subtype)
4853 {
151337e8
NC		 4854 case TAB (BRANCHBWL, BYTE):
4855 case TAB (BRABSJUNC, BYTE):
4856 case TAB (BRABSJCOND, BYTE):
4857 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4858 know (issbyte (disp));
4859 if (disp == 0)
b091f402
AM		 4860 as_bad_where (fragP->fr_file, fragP->fr_line,
4861 _("short branch with zero offset: use :w"));
151337e8 4862 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4863 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4864 fixP->fx_pcrel_adjust = -1;
252b5132 4865 break;
151337e8
NC		 4866 case TAB (BRANCHBWL, SHORT):
4867 case TAB (BRABSJUNC, SHORT):
4868 case TAB (BRABSJCOND, SHORT):
4869 case TAB (BRANCHBW, SHORT):
252b5132 4870 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 4871 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4872 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4873 fragP->fr_fix += 2;
4874 break;
4875 case TAB (BRANCHBWL, LONG):
4876 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 4877 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4878 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 4879 fragP->fr_fix += 4;
252b5132 4880 break;
151337e8
NC		 4881 case TAB (BRABSJUNC, LONG):
4882 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4883 {
36759679 4884 if (flag_keep_pcrel)
2b878742
NS		 4885 as_bad_where (fragP->fr_file, fragP->fr_line,
4886 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 4887 fragP->fr_opcode[0] = 0x4E;
36759679 4888 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 4889 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4890 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4891 fragP->fr_fix += 4;
4892 }
4893 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4894 {
36759679 4895 if (flag_keep_pcrel)
2b878742
NS		 4896 as_bad_where (fragP->fr_file, fragP->fr_line,
4897 _("Conversion of PC relative branch to absolute jump"));
151337e8 4898 fragP->fr_opcode[0] = 0x4E;
36759679 4899 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 4900 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4901 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 4902 fragP->fr_fix += 4;
252b5132
RH		 4903 }
4904 else
4905 {
151337e8
NC		 4906 /* This cannot happen, because jbsr and jbra are the only two
4907 unconditional branches. */
4908 abort ();
252b5132
RH		 4909 }
4910 break;
151337e8 4911 case TAB (BRABSJCOND, LONG):
36759679 4912 if (flag_keep_pcrel)
2b878742
NS		 4913 as_bad_where (fragP->fr_file, fragP->fr_line,
4914 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 4915
36759679
NC		 4916 /* Only Bcc 68000 instructions can come here
4917 Change bcc into b!cc/jmp absl long. */
4918 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4919 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4920
4921 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4922 different frag, in which case referring to them is a no-no.
92774660 4923 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4924 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4925 *buffer_address++ = (char) 0xf9;
36759679 4926 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 4927 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4928 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4929 fragP->fr_fix += 4;
4930 break;
4931 case TAB (FBRANCH, SHORT):
4932 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 4933 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4934 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4935 fragP->fr_fix += 2;
4936 break;
4937 case TAB (FBRANCH, LONG):
36759679 4938 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 4939 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4940 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 4941 fragP->fr_fix += 4;
252b5132 4942 break;
151337e8
NC		 4943 case TAB (DBCCLBR, SHORT):
4944 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 4945 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4946 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4947 fragP->fr_fix += 2;
4948 break;
4949 case TAB (DBCCLBR, LONG):
36759679
NC		 4950 /* Only DBcc instructions can come here.
4951 Change dbcc into dbcc/bral.
4952 JF: these used to be fr_opcode[2-7], but that's wrong. */
4953 if (flag_keep_pcrel)
2b878742
NS		 4954 as_bad_where (fragP->fr_file, fragP->fr_line,
4955 _("Conversion of DBcc to absolute jump"));
28e7409f 4956
36759679 4957 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4958 *buffer_address++ = 0x04;
36759679 4959 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4960 *buffer_address++ = 0x06;
151337e8
NC		 4961 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4962 *buffer_address++ = (char) 0xff;
252b5132 4963
36759679 4964 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 4965 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4966 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 4967 fragP->fr_fix += 4;
252b5132 4968 break;
151337e8 4969 case TAB (DBCCABSJ, LONG):
36759679
NC		 4970 /* Only DBcc instructions can come here.
4971 Change dbcc into dbcc/jmp.
4972 JF: these used to be fr_opcode[2-7], but that's wrong. */
4973 if (flag_keep_pcrel)
2b878742
NS		 4974 as_bad_where (fragP->fr_file, fragP->fr_line,
4975 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 4976
36759679 4977 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4978 *buffer_address++ = 0x04;
36759679 4979 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4980 *buffer_address++ = 0x06;
36759679 4981 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4982 *buffer_address++ = (char) 0xf9;
4983
36759679 4984 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 4985 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4986 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 4987 fragP->fr_fix += 4;
252b5132 4988 break;
151337e8 4989 case TAB (PCREL1632, SHORT):
252b5132
RH		 4990 fragP->fr_opcode[1] &= ~0x3F;
4991 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 4992 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4993 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4994 fragP->fr_fix += 2;
252b5132 4995 break;
151337e8 4996 case TAB (PCREL1632, LONG):
252b5132
RH		 4997 /* Already set to mode 7.3; this indicates: PC indirect with
4998 suppressed index, 32-bit displacement. */
4999 *buffer_address++ = 0x01;
5000 *buffer_address++ = 0x70;
5001 fragP->fr_fix += 2;
151337e8 5002 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5003 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5004 fixP->fx_pcrel_adjust = 2;
5005 fragP->fr_fix += 4;
252b5132 5006 break;
252b5132 5007 case TAB (PCINDEX, BYTE):
252b5132
RH		 5008 assert (fragP->fr_fix >= 2);
5009 buffer_address[-2] &= ~1;
151337e8 5010 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5011 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5012 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 5013 break;
5014 case TAB (PCINDEX, SHORT):
252b5132
RH		 5015 assert (fragP->fr_fix >= 2);
5016 buffer_address[-2] |= 0x1;
5017 buffer_address[-1] = 0x20;
5018 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 5019 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 5020 fixP->fx_pcrel_adjust = 2;
151337e8 5021 fragP->fr_fix += 2;
252b5132
RH		 5022 break;
5023 case TAB (PCINDEX, LONG):
252b5132
RH		 5024 assert (fragP->fr_fix >= 2);
5025 buffer_address[-2] |= 0x1;
5026 buffer_address[-1] = 0x30;
151337e8 5027 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5028 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5029 fixP->fx_pcrel_adjust = 2;
5030 fragP->fr_fix += 4;
5031 break;
5032 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 5033 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5034 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5035 fragP->fr_fix += 2;
5036 break;
5037 case TAB (ABSTOPCREL, LONG):
36759679 5038 if (flag_keep_pcrel)
2b878742 5039 as_fatal (_("Conversion of PC relative displacement to absolute"));
151337e8 5040 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 5041 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 5042 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5043 abort ();
5044 fragP->fr_opcode[1] &= ~0x3F;
5045 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 5046 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5047 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5048 fragP->fr_fix += 4;
252b5132 5049 break;
252b5132 5050 }
2b878742
NS		 5051 if (fixP)
5052 {
5053 fixP->fx_file = fragP->fr_file;
5054 fixP->fx_line = fragP->fr_line;
5055 }
252b5132
RH		 5056}
5057
252b5132 5058void
31302357
AS		 5059md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5060 segT sec ATTRIBUTE_UNUSED,
5061 fragS *fragP)
252b5132
RH		 5062{
5063 md_convert_frag_1 (fragP);
5064}
252b5132
RH		 5065
5066/* Force truly undefined symbols to their maximum size, and generally set up
5067 the frag list to be relaxed
5068 */
5069int
31302357 5070md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5071{
151337e8 5072 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5073 switch (fragP->fr_subtype)
5074 {
151337e8
NC		 5075 case TAB (BRANCHBWL, SZ_UNDEF):
5076 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5077 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5078 {
151337e8
NC		 5079 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5080 && relaxable_symbol (fragP->fr_symbol))
252b5132 5081 {
151337e8
NC		 5082 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5083 }
5084 else if (flag_short_refs)
5085 {
5086 /* Symbol is undefined and we want short ref. */
5087 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5088 }
5089 else
5090 {
151337e8
NC		 5091 /* Symbol is still undefined. Make it LONG. */
5092 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5093 }
5094 break;
151337e8 5095 }
252b5132 5096
151337e8 5097 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5098 {
151337e8
NC		 5099 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5100 && relaxable_symbol (fragP->fr_symbol))
252b5132 5101 {
151337e8 5102 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5103 }
5104 else
5105 {
151337e8
NC		 5106 /* Symbol is undefined and we don't have long branches. */
5107 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5108 }
5109 break;
151337e8 5110 }
252b5132 5111
151337e8 5112 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5113 case TAB (DBCCLBR, SZ_UNDEF):
5114 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5115 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5116 {
8ec6253e
NC		 5117 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5118 && relaxable_symbol (fragP->fr_symbol))
151337e8 5119 || flag_short_refs)
252b5132 5120 {
151337e8 5121 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5122 }
5123 else
5124 {
151337e8 5125 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5126 }
5127 break;
151337e8 5128 }
81d4177b 5129
252b5132
RH		 5130 case TAB (PCINDEX, SZ_UNDEF):
5131 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5132 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5133 {
5134 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5135 }
5136 else
5137 {
5138 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5139 }
5140 break;
5141
151337e8
NC		 5142 case TAB (ABSTOPCREL, SZ_UNDEF):
5143 {
5144 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5145 && relaxable_symbol (fragP->fr_symbol)))
5146 {
5147 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5148 }
5149 else
5150 {
5151 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5152 }
5153 break;
5154 }
5155
252b5132
RH		 5156 default:
5157 break;
5158 }
5159
151337e8 5160 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5161 switch (fragP->fr_subtype)
5162 {
151337e8
NC		 5163 case TAB (BRANCHBWL, BYTE):
5164 case TAB (BRABSJUNC, BYTE):
5165 case TAB (BRABSJCOND, BYTE):
5166 case TAB (BRANCHBW, BYTE):
252b5132 5167 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5168 case we force word mode. If the symbol is at the start of a
5169 frag, and it is the next frag with any data in it (usually
5170 this is just the next frag, but assembler listings may
5171 introduce empty frags), we must use word mode. */
5172 if (fragP->fr_symbol)
252b5132 5173 {
ac62c346 5174 fragS *sym_frag;
252b5132 5175
ac62c346
AM		 5176 sym_frag = symbol_get_frag (fragP->fr_symbol);
5177 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5178 {
ac62c346
AM		 5179 fragS *l;
5180
23b7f870 5181 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5182 if (l->fr_fix != 0)
5183 break;
5184 if (l == sym_frag)
5185 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5186 }
5187 }
5188 break;
5189 default:
5190 break;
5191 }
ac62c346 5192 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5193}
5194
5195#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5196/* the bit-field entries in the relocation_info struct plays hell
5197 with the byte-order problems of cross-assembly. So as a hack,
5198 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5199 you there. -KWK */
252b5132
RH		 5200/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5201 are symbolnum, most sig. byte first. Last byte is broken up with
5202 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5203 nibble as nuthin. (on Sun 3 at least) */
5204/* Translate the internal relocation information into target-specific
92774660 5205 format. */
252b5132
RH		 5206#ifdef comment
5207void
31302357 5208md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5209{
36759679 5210 /* This is easy. */
252b5132 5211 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5212 /* Now the fun stuff. */
252b5132 5213 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5214 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5215 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5216 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5217 | ((ri->r_length << 5) & 0x60)
5218 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5219}
5220
36759679 5221#endif
252b5132 5222
252b5132
RH		 5223#endif /* OBJ_AOUT or OBJ_BOUT */
5224
5225#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5226int md_short_jump_size = 4;
5227int md_long_jump_size = 6;
252b5132
RH		 5228
5229void
31302357
AS		 5230md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5231 fragS *frag ATTRIBUTE_UNUSED,
5232 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5233{
5234 valueT offset;
5235
5236 offset = to_addr - (from_addr + 2);
5237
5238 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5239 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5240}
5241
5242void
31302357
AS		 5243md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5244 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5245{
5246 valueT offset;
5247
6b6e92f4 5248 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5249 {
36759679 5250 if (flag_keep_pcrel)
6b6e92f4 5251 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5252 offset = to_addr - S_GET_VALUE (to_symbol);
5253 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5254 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5255 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5256 0, NO_RELOC);
5257 }
5258 else
5259 {
5260 offset = to_addr - (from_addr + 2);
5261 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5262 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5263 }
5264}
5265
5266#endif
5267
5268/* Different values of OK tell what its OK to return. Things that
5269 aren't OK are an error (what a shock, no?)
5270
5271 0: Everything is OK
3e602632
NC		 5272 10: Absolute 1:8 only
5273 20: Absolute 0:7 only
5274 30: absolute 0:15 only
5275 40: Absolute 0:31 only
5276 50: absolute 0:127 only
252b5132 5277 55: absolute -64:63 only
3e602632 5278 60: absolute -128:127 only
afa2158f 5279 65: absolute 0:511 only
3e602632
NC		 5280 70: absolute 0:4095 only
5281 80: absolute -1, 1:7 only
5282 90: No bignums. */
252b5132
RH		 5283
5284static int
31302357 5285get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5286{
5287 if (exp->exp.X_op == O_absent)
5288 {
36759679 5289 /* Do the same thing the VAX asm does. */
252b5132
RH		 5290 op (exp) = O_constant;
5291 adds (exp) = 0;
5292 subs (exp) = 0;
5293 offs (exp) = 0;
5294 if (ok == 10)
5295 {
5296 as_warn (_("expression out of range: defaulting to 1"));
5297 offs (exp) = 1;
5298 }
5299 }
5300 else if (exp->exp.X_op == O_constant)
5301 {
5302 switch (ok)
5303 {
5304 case 10:
bd17c2c3 5305 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5306 {
5307 as_warn (_("expression out of range: defaulting to 1"));
5308 offs (exp) = 1;
5309 }
5310 break;
5311 case 20:
bd17c2c3 5312 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5313 goto outrange;
5314 break;
5315 case 30:
bd17c2c3 5316 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5317 goto outrange;
5318 break;
5319 case 40:
bd17c2c3 5320 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5321 goto outrange;
5322 break;
5323 case 50:
bd17c2c3 5324 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5325 goto outrange;
5326 break;
5327 case 55:
bd17c2c3 5328 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5329 goto outrange;
5330 break;
5331 case 60:
bd17c2c3 5332 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132 5333 goto outrange;
afa2158f
NS		 5334 break;
5335 case 65:
5336 if ((valueT) TRUNC (offs (exp)) > 511)
5337 goto outrange;
252b5132
RH		 5338 break;
5339 case 70:
bd17c2c3 5340 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5341 {
5342 outrange:
5343 as_warn (_("expression out of range: defaulting to 0"));
5344 offs (exp) = 0;
5345 }
5346 break;
3e602632 5347 case 80:
bd17c2c3
AM		 5348 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5349 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5350 {
5351 as_warn (_("expression out of range: defaulting to 1"));
5352 offs (exp) = 1;
5353 }
5354 break;
252b5132
RH		 5355 default:
5356 break;
5357 }
5358 }
5359 else if (exp->exp.X_op == O_big)
5360 {
36759679 5361 if (offs (exp) <= 0 /* flonum. */
3e602632 5362 && (ok == 90 /* no bignums */
36759679 5363 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5364 /* If we have a flonum zero, a zero integer should
5365 do as well (e.g., in moveq). */
5366 && generic_floating_point_number.exponent == 0
5367 && generic_floating_point_number.low[0] == 0)))
5368 {
36759679 5369 /* HACK! Turn it into a long. */
252b5132
RH		 5370 LITTLENUM_TYPE words[6];
5371
36759679 5372 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5373 op (exp) = O_constant;
5374 adds (exp) = 0;
5375 subs (exp) = 0;
5376 offs (exp) = words[1] | (words[0] << 16);
5377 }
5378 else if (ok != 0)
5379 {
5380 op (exp) = O_constant;
5381 adds (exp) = 0;
5382 subs (exp) = 0;
5383 offs (exp) = (ok == 10) ? 1 : 0;
5384 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5385 (long) offs (exp));
252b5132
RH		 5386 }
5387 }
5388 else
5389 {
3e602632 5390 if (ok >= 10 && ok <= 80)
252b5132
RH		 5391 {
5392 op (exp) = O_constant;
5393 adds (exp) = 0;
5394 subs (exp) = 0;
5395 offs (exp) = (ok == 10) ? 1 : 0;
5396 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5397 (long) offs (exp));
252b5132
RH		 5398 }
5399 }
5400
5401 if (exp->size != SIZE_UNSPEC)
5402 {
5403 switch (exp->size)
5404 {
5405 case SIZE_UNSPEC:
5406 case SIZE_LONG:
5407 break;
5408 case SIZE_BYTE:
5409 if (!isbyte (offs (exp)))
5410 as_warn (_("expression doesn't fit in BYTE"));
5411 break;
5412 case SIZE_WORD:
5413 if (!isword (offs (exp)))
5414 as_warn (_("expression doesn't fit in WORD"));
5415 break;
5416 }
5417 }
5418
5419 return offs (exp);
5420}
5421
5422/* These are the back-ends for the various machine dependent pseudo-ops. */
5423
5424static void
31302357 5425s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5426{
5427 subseg_set (data_section, 1);
5428 demand_empty_rest_of_line ();
5429}
5430
5431static void
31302357 5432s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5433{
5434 subseg_set (data_section, 2);
5435 demand_empty_rest_of_line ();
5436}
5437
5438static void
31302357 5439s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5440{
5441 /* We don't support putting frags in the BSS segment, we fake it
5442 by marking in_bss, then looking at s_skip for clues. */
5443
5444 subseg_set (bss_section, 0);
5445 demand_empty_rest_of_line ();
5446}
5447
5448static void
31302357 5449s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5450{
5451 register int temp;
5452 register long temp_fill;
5453
5454 temp = 1; /* JF should be 2? */
5455 temp_fill = get_absolute_expression ();
92774660 5456 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5457 frag_align (temp, (int) temp_fill, 0);
5458 demand_empty_rest_of_line ();
5459 record_alignment (now_seg, temp);
5460}
5461
5462static void
31302357 5463s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5464{
5465 demand_empty_rest_of_line ();
5466}
5467\f
5468/* Pseudo-ops handled for MRI compatibility. */
5469
5470/* This function returns non-zero if the argument is a conditional
5471 pseudo-op. This is called when checking whether a pending
5472 alignment is needed. */
5473
5474int
31302357 5475m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5476{
5477 return (pop->poc_handler == s_mri_if
5478 || pop->poc_handler == s_mri_else);
5479}
5480
5481/* Handle an MRI style chip specification. */
5482
5483static void
31302357 5484mri_chip (void)
252b5132
RH		 5485{
5486 char *s;
5487 char c;
5488 int i;
5489
5490 s = input_line_pointer;
5491 /* We can't use get_symbol_end since the processor names are not proper
5492 symbols. */
5493 while (is_part_of_name (c = *input_line_pointer++))
5494 ;
5495 *--input_line_pointer = 0;
266abb8f
NS		 5496 for (i = 0; m68k_cpus[i].name; i++)
5497 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5498 break;
266abb8f 5499 if (!m68k_cpus[i].name)
252b5132
RH		 5500 {
5501 as_bad (_("%s: unrecognized processor name"), s);
5502 *input_line_pointer = c;
5503 ignore_rest_of_line ();
5504 return;
5505 }
5506 *input_line_pointer = c;
5507
5508 if (*input_line_pointer == '/')
5509 current_architecture = 0;
5510 else
5511 current_architecture &= m68881 | m68851;
266abb8f 5512 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5513 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5514
5515 while (*input_line_pointer == '/')
5516 {
5517 ++input_line_pointer;
5518 s = input_line_pointer;
5519 /* We can't use get_symbol_end since the processor names are not
5520 proper symbols. */
5521 while (is_part_of_name (c = *input_line_pointer++))
5522 ;
5523 *--input_line_pointer = 0;
5524 if (strcmp (s, "68881") == 0)
5525 current_architecture |= m68881;
5526 else if (strcmp (s, "68851") == 0)
5527 current_architecture |= m68851;
5528 *input_line_pointer = c;
5529 }
252b5132
RH		 5530}
5531
5532/* The MRI CHIP pseudo-op. */
5533
5534static void
31302357 5535s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5536{
5537 char *stop = NULL;
5538 char stopc;
5539
5540 if (flag_mri)
5541 stop = mri_comment_field (&stopc);
5542 mri_chip ();
5543 if (flag_mri)
5544 mri_comment_end (stop, stopc);
5545 demand_empty_rest_of_line ();
5546}
5547
5548/* The MRI FOPT pseudo-op. */
5549
5550static void
31302357 5551s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5552{
5553 SKIP_WHITESPACE ();
5554
5555 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5556 {
5557 int temp;
5558
5559 input_line_pointer += 3;
5560 temp = get_absolute_expression ();
5561 if (temp < 0 || temp > 7)
5562 as_bad (_("bad coprocessor id"));
5563 else
5564 m68k_float_copnum = COP0 + temp;
5565 }
5566 else
5567 {
5568 as_bad (_("unrecognized fopt option"));
5569 ignore_rest_of_line ();
5570 return;
5571 }
5572
5573 demand_empty_rest_of_line ();
5574}
5575
5576/* The structure used to handle the MRI OPT pseudo-op. */
5577
5578struct opt_action
5579{
5580 /* The name of the option. */
5581 const char *name;
5582
5583 /* If this is not NULL, just call this function. The first argument
5584 is the ARG field of this structure, the second argument is
5585 whether the option was negated. */
31302357 5586 void (*pfn) (int arg, int on);
252b5132
RH		 5587
5588 /* If this is not NULL, and the PFN field is NULL, set the variable
5589 this points to. Set it to the ARG field if the option was not
5590 negated, and the NOTARG field otherwise. */
5591 int *pvar;
5592
5593 /* The value to pass to PFN or to assign to *PVAR. */
5594 int arg;
5595
5596 /* The value to assign to *PVAR if the option is negated. If PFN is
5597 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5598 the option may not be negated. */
5599 int notarg;
5600};
5601
5602/* The table used to handle the MRI OPT pseudo-op. */
5603
31302357
AS		 5604static void skip_to_comma (int, int);
5605static void opt_nest (int, int);
5606static void opt_chip (int, int);
5607static void opt_list (int, int);
5608static void opt_list_symbols (int, int);
252b5132
RH		 5609
5610static const struct opt_action opt_table[] =
5611{
5612 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5613
5614 /* We do relaxing, so there is little use for these options. */
5615 { "b", 0, 0, 0, 0 },
5616 { "brs", 0, 0, 0, 0 },
5617 { "brb", 0, 0, 0, 0 },
5618 { "brl", 0, 0, 0, 0 },
5619 { "brw", 0, 0, 0, 0 },
5620
5621 { "c", 0, 0, 0, 0 },
5622 { "cex", 0, 0, 0, 0 },
5623 { "case", 0, &symbols_case_sensitive, 1, 0 },
5624 { "cl", 0, 0, 0, 0 },
5625 { "cre", 0, 0, 0, 0 },
5626 { "d", 0, &flag_keep_locals, 1, 0 },
5627 { "e", 0, 0, 0, 0 },
5628 { "f", 0, &flag_short_refs, 1, 0 },
5629 { "frs", 0, &flag_short_refs, 1, 0 },
5630 { "frl", 0, &flag_short_refs, 0, 1 },
5631 { "g", 0, 0, 0, 0 },
5632 { "i", 0, 0, 0, 0 },
5633 { "m", 0, 0, 0, 0 },
5634 { "mex", 0, 0, 0, 0 },
5635 { "mc", 0, 0, 0, 0 },
5636 { "md", 0, 0, 0, 0 },
5637 { "nest", opt_nest, 0, 0, 0 },
5638 { "next", skip_to_comma, 0, 0, 0 },
5639 { "o", 0, 0, 0, 0 },
5640 { "old", 0, 0, 0, 0 },
5641 { "op", skip_to_comma, 0, 0, 0 },
5642 { "pco", 0, 0, 0, 0 },
5643 { "p", opt_chip, 0, 0, 0 },
5644 { "pcr", 0, 0, 0, 0 },
5645 { "pcs", 0, 0, 0, 0 },
5646 { "r", 0, 0, 0, 0 },
5647 { "quick", 0, &m68k_quick, 1, 0 },
5648 { "rel32", 0, &m68k_rel32, 1, 0 },
5649 { "s", opt_list, 0, 0, 0 },
5650 { "t", opt_list_symbols, 0, 0, 0 },
5651 { "w", 0, &flag_no_warnings, 0, 1 },
5652 { "x", 0, 0, 0, 0 }
5653};
5654
8fce3f5e 5655#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5656
5657/* The MRI OPT pseudo-op. */
5658
5659static void
31302357 5660s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5661{
5662 do
5663 {
5664 int t;
5665 char *s;
5666 char c;
5667 int i;
5668 const struct opt_action *o;
5669
5670 SKIP_WHITESPACE ();
5671
5672 t = 1;
5673 if (*input_line_pointer == '-')
5674 {
5675 ++input_line_pointer;
5676 t = 0;
5677 }
5678 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5679 {
5680 input_line_pointer += 2;
5681 t = 0;
5682 }
5683
5684 s = input_line_pointer;
5685 c = get_symbol_end ();
5686
5687 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5688 {
5689 if (strcasecmp (s, o->name) == 0)
5690 {
5691 if (o->pfn)
5692 {
5693 /* Restore input_line_pointer now in case the option
5694 takes arguments. */
5695 *input_line_pointer = c;
5696 (*o->pfn) (o->arg, t);
5697 }
5698 else if (o->pvar != NULL)
5699 {
5700 if (! t && o->arg == o->notarg)
5701 as_bad (_("option `%s' may not be negated"), s);
5702 *input_line_pointer = c;
5703 *o->pvar = t ? o->arg : o->notarg;
5704 }
5705 else
5706 *input_line_pointer = c;
5707 break;
5708 }
5709 }
5710 if (i >= OPTCOUNT)
5711 {
5712 as_bad (_("option `%s' not recognized"), s);
5713 *input_line_pointer = c;
5714 }
5715 }
5716 while (*input_line_pointer++ == ',');
5717
5718 /* Move back to terminating character. */
5719 --input_line_pointer;
5720 demand_empty_rest_of_line ();
5721}
5722
5723/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5724 not support and which take arguments. */
252b5132
RH		 5725
5726static void
31302357 5727skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5728{
5729 while (*input_line_pointer != ','
5730 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5731 ++input_line_pointer;
5732}
5733
5734/* Handle the OPT NEST=depth option. */
5735
5736static void
31302357 5737opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5738{
5739 if (*input_line_pointer != '=')
5740 {
5741 as_bad (_("bad format of OPT NEST=depth"));
5742 return;
5743 }
5744
5745 ++input_line_pointer;
5746 max_macro_nest = get_absolute_expression ();
5747}
5748
5749/* Handle the OPT P=chip option. */
5750
5751static void
31302357 5752opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5753{
5754 if (*input_line_pointer != '=')
5755 {
5756 /* This is just OPT P, which we do not support. */
5757 return;
5758 }
5759
5760 ++input_line_pointer;
5761 mri_chip ();
5762}
5763
5764/* Handle the OPT S option. */
5765
5766static void
31302357 5767opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5768{
5769 listing_list (on);
5770}
5771
5772/* Handle the OPT T option. */
5773
5774static void
31302357 5775opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5776{
5777 if (on)
5778 listing |= LISTING_SYMBOLS;
5779 else
8a104df9 5780 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5781}
5782
5783/* Handle the MRI REG pseudo-op. */
5784
5785static void
31302357 5786s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5787{
5788 char *s;
5789 int c;
5790 struct m68k_op rop;
5791 int mask;
5792 char *stop = NULL;
5793 char stopc;
5794
5795 if (line_label == NULL)
5796 {
5797 as_bad (_("missing label"));
5798 ignore_rest_of_line ();
5799 return;
5800 }
5801
5802 if (flag_mri)
5803 stop = mri_comment_field (&stopc);
5804
5805 SKIP_WHITESPACE ();
5806
5807 s = input_line_pointer;
3882b010 5808 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5809#ifdef REGISTER_PREFIX
5810 || *input_line_pointer == REGISTER_PREFIX
5811#endif
5812 || *input_line_pointer == '/'
5813 || *input_line_pointer == '-')
5814 ++input_line_pointer;
5815 c = *input_line_pointer;
5816 *input_line_pointer = '\0';
5817
5818 if (m68k_ip_op (s, &rop) != 0)
5819 {
5820 if (rop.error == NULL)
5821 as_bad (_("bad register list"));
5822 else
5823 as_bad (_("bad register list: %s"), rop.error);
5824 *input_line_pointer = c;
5825 ignore_rest_of_line ();
5826 return;
5827 }
5828
5829 *input_line_pointer = c;
5830
5831 if (rop.mode == REGLST)
5832 mask = rop.mask;
5833 else if (rop.mode == DREG)
5834 mask = 1 << (rop.reg - DATA0);
5835 else if (rop.mode == AREG)
5836 mask = 1 << (rop.reg - ADDR0 + 8);
5837 else if (rop.mode == FPREG)
5838 mask = 1 << (rop.reg - FP0 + 16);
5839 else if (rop.mode == CONTROL
5840 && rop.reg == FPI)
5841 mask = 1 << 24;
5842 else if (rop.mode == CONTROL
5843 && rop.reg == FPS)
5844 mask = 1 << 25;
5845 else if (rop.mode == CONTROL
5846 && rop.reg == FPC)
5847 mask = 1 << 26;
5848 else
5849 {
5850 as_bad (_("bad register list"));
5851 ignore_rest_of_line ();
5852 return;
5853 }
5854
5855 S_SET_SEGMENT (line_label, reg_section);
5856 S_SET_VALUE (line_label, ~mask);
49309057 5857 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5858
5859 if (flag_mri)
5860 mri_comment_end (stop, stopc);
5861
5862 demand_empty_rest_of_line ();
5863}
5864
5865/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5866
5867struct save_opts
5868{
5869 struct save_opts *next;
5870 int abspcadd;
5871 int symbols_case_sensitive;
5872 int keep_locals;
5873 int short_refs;
5874 int architecture;
2da12c60 5875 const enum m68k_register *control_regs;
252b5132
RH		 5876 int quick;
5877 int rel32;
5878 int listing;
5879 int no_warnings;
5880 /* FIXME: We don't save OPT S. */
5881};
5882
5883/* This variable holds the stack of saved options. */
5884
5885static struct save_opts *save_stack;
5886
5887/* The MRI SAVE pseudo-op. */
5888
5889static void
31302357 5890s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5891{
5892 struct save_opts *s;
5893
5894 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5895 s->abspcadd = m68k_abspcadd;
5896 s->symbols_case_sensitive = symbols_case_sensitive;
5897 s->keep_locals = flag_keep_locals;
5898 s->short_refs = flag_short_refs;
5899 s->architecture = current_architecture;
2da12c60 5900 s->control_regs = control_regs;
252b5132
RH		 5901 s->quick = m68k_quick;
5902 s->rel32 = m68k_rel32;
5903 s->listing = listing;
5904 s->no_warnings = flag_no_warnings;
5905
5906 s->next = save_stack;
5907 save_stack = s;
5908
5909 demand_empty_rest_of_line ();
5910}
5911
5912/* The MRI RESTORE pseudo-op. */
5913
5914static void
31302357 5915s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5916{
5917 struct save_opts *s;
5918
5919 if (save_stack == NULL)
5920 {
5921 as_bad (_("restore without save"));
5922 ignore_rest_of_line ();
5923 return;
5924 }
5925
5926 s = save_stack;
5927 save_stack = s->next;
5928
5929 m68k_abspcadd = s->abspcadd;
5930 symbols_case_sensitive = s->symbols_case_sensitive;
5931 flag_keep_locals = s->keep_locals;
5932 flag_short_refs = s->short_refs;
5933 current_architecture = s->architecture;
2da12c60 5934 control_regs = s->control_regs;
252b5132
RH		 5935 m68k_quick = s->quick;
5936 m68k_rel32 = s->rel32;
5937 listing = s->listing;
5938 flag_no_warnings = s->no_warnings;
5939
5940 free (s);
5941
5942 demand_empty_rest_of_line ();
5943}
5944
5945/* Types of MRI structured control directives. */
5946
5947enum mri_control_type
5948{
5949 mri_for,
5950 mri_if,
5951 mri_repeat,
5952 mri_while
5953};
5954
5955/* This structure is used to stack the MRI structured control
5956 directives. */
5957
5958struct mri_control_info
5959{
5960 /* The directive within which this one is enclosed. */
5961 struct mri_control_info *outer;
5962
5963 /* The type of directive. */
5964 enum mri_control_type type;
5965
5966 /* Whether an ELSE has been in an IF. */
5967 int else_seen;
5968
5969 /* The add or sub statement at the end of a FOR. */
5970 char *incr;
5971
5972 /* The label of the top of a FOR or REPEAT loop. */
5973 char *top;
5974
5975 /* The label to jump to for the next iteration, or the else
5976 expression of a conditional. */
5977 char *next;
5978
5979 /* The label to jump to to break out of the loop, or the label past
5980 the end of a conditional. */
5981 char *bottom;
5982};
5983
5984/* The stack of MRI structured control directives. */
5985
5986static struct mri_control_info *mri_control_stack;
5987
5988/* The current MRI structured control directive index number, used to
5989 generate label names. */
5990
5991static int mri_control_index;
5992
252b5132
RH		 5993/* Assemble an instruction for an MRI structured control directive. */
5994
5995static void
31302357 5996mri_assemble (char *str)
252b5132
RH		 5997{
5998 char *s;
5999
6000 /* md_assemble expects the opcode to be in lower case. */
6001 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 6002 *s = TOLOWER (*s);
252b5132
RH		 6003
6004 md_assemble (str);
6005}
6006
6007/* Generate a new MRI label structured control directive label name. */
6008
6009static char *
31302357 6010mri_control_label (void)
252b5132
RH		 6011{
6012 char *n;
6013
6014 n = (char *) xmalloc (20);
6015 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6016 ++mri_control_index;
6017 return n;
6018}
6019
6020/* Create a new MRI structured control directive. */
6021
6022static struct mri_control_info *
31302357 6023push_mri_control (enum mri_control_type type)
252b5132
RH		 6024{
6025 struct mri_control_info *n;
6026
6027 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6028
6029 n->type = type;
6030 n->else_seen = 0;
6031 if (type == mri_if || type == mri_while)
6032 n->top = NULL;
6033 else
6034 n->top = mri_control_label ();
6035 n->next = mri_control_label ();
6036 n->bottom = mri_control_label ();
6037
6038 n->outer = mri_control_stack;
6039 mri_control_stack = n;
6040
6041 return n;
6042}
6043
6044/* Pop off the stack of MRI structured control directives. */
6045
6046static void
31302357 6047pop_mri_control (void)
252b5132
RH		 6048{
6049 struct mri_control_info *n;
6050
6051 n = mri_control_stack;
6052 mri_control_stack = n->outer;
6053 if (n->top != NULL)
6054 free (n->top);
6055 free (n->next);
6056 free (n->bottom);
6057 free (n);
6058}
6059
6060/* Recognize a condition code in an MRI structured control expression. */
6061
6062static int
31302357 6063parse_mri_condition (int *pcc)
252b5132
RH		 6064{
6065 char c1, c2;
6066
6067 know (*input_line_pointer == '<');
6068
6069 ++input_line_pointer;
6070 c1 = *input_line_pointer++;
6071 c2 = *input_line_pointer++;
6072
6073 if (*input_line_pointer != '>')
6074 {
6075 as_bad (_("syntax error in structured control directive"));
6076 return 0;
6077 }
6078
6079 ++input_line_pointer;
6080 SKIP_WHITESPACE ();
6081
3882b010
L		 6082 c1 = TOLOWER (c1);
6083 c2 = TOLOWER (c2);
252b5132
RH		 6084
6085 *pcc = (c1 << 8) | c2;
6086
6087 return 1;
6088}
6089
6090/* Parse a single operand in an MRI structured control expression. */
6091
6092static int
31302357
AS		 6093parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6094 char **rightstart, char **rightstop)
252b5132
RH		 6095{
6096 char *s;
6097
6098 SKIP_WHITESPACE ();
6099
6100 *pcc = -1;
6101 *leftstart = NULL;
6102 *leftstop = NULL;
6103 *rightstart = NULL;
6104 *rightstop = NULL;
6105
6106 if (*input_line_pointer == '<')
6107 {
6108 /* It's just a condition code. */
6109 return parse_mri_condition (pcc);
6110 }
6111
6112 /* Look ahead for the condition code. */
6113 for (s = input_line_pointer; *s != '\0'; ++s)
6114 {
6115 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6116 break;
6117 }
6118 if (*s == '\0')
6119 {
6120 as_bad (_("missing condition code in structured control directive"));
6121 return 0;
6122 }
6123
6124 *leftstart = input_line_pointer;
6125 *leftstop = s;
6126 if (*leftstop > *leftstart
6127 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6128 --*leftstop;
6129
6130 input_line_pointer = s;
6131 if (! parse_mri_condition (pcc))
6132 return 0;
6133
6134 /* Look ahead for AND or OR or end of line. */
6135 for (s = input_line_pointer; *s != '\0'; ++s)
6136 {
e1f44d10
NC		 6137 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6138 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6139 ^^^ ^^ */
8a104df9
KH		 6140 if ((s == input_line_pointer
6141 || *(s-1) == ' '
6142 || *(s-1) == '\t')
6143 && ((strncasecmp (s, "AND", 3) == 0
6144 && (s[3] == '.' || ! is_part_of_name (s[3])))
6145 || (strncasecmp (s, "OR", 2) == 0
6146 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6147 break;
252b5132
RH		 6148 }
6149
6150 *rightstart = input_line_pointer;
6151 *rightstop = s;
6152 if (*rightstop > *rightstart
6153 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6154 --*rightstop;
6155
6156 input_line_pointer = s;
6157
6158 return 1;
6159}
6160
6161#define MCC(b1, b2) (((b1) << 8) | (b2))
6162
6163/* Swap the sense of a condition. This changes the condition so that
6164 it generates the same result when the operands are swapped. */
6165
6166static int
31302357 6167swap_mri_condition (int cc)
252b5132
RH		 6168{
6169 switch (cc)
6170 {
6171 case MCC ('h', 'i'): return MCC ('c', 's');
6172 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6173 /* <HS> is an alias for <CC>. */
e1f44d10 6174 case MCC ('h', 's'):
252b5132 6175 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6176 /* <LO> is an alias for <CS>. */
e1f44d10 6177 case MCC ('l', 'o'):
252b5132
RH		 6178 case MCC ('c', 's'): return MCC ('h', 'i');
6179 case MCC ('p', 'l'): return MCC ('m', 'i');
6180 case MCC ('m', 'i'): return MCC ('p', 'l');
6181 case MCC ('g', 'e'): return MCC ('l', 'e');
6182 case MCC ('l', 't'): return MCC ('g', 't');
6183 case MCC ('g', 't'): return MCC ('l', 't');
6184 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6185 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 6186 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6187 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6188 case MCC ('v', 'c'):
6189 case MCC ('v', 's'):
6190 default :
6191 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6192 (char) (cc >> 8), (char) (cc));
6193 break;
252b5132
RH		 6194 }
6195 return cc;
6196}
6197
6198/* Reverse the sense of a condition. */
6199
6200static int
31302357 6201reverse_mri_condition (int cc)
252b5132
RH		 6202{
6203 switch (cc)
6204 {
6205 case MCC ('h', 'i'): return MCC ('l', 's');
6206 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6207 /* <HS> is an alias for <CC> */
6208 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6209 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6210 /* <LO> is an alias for <CS> */
6211 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6212 case MCC ('c', 's'): return MCC ('c', 'c');
6213 case MCC ('n', 'e'): return MCC ('e', 'q');
6214 case MCC ('e', 'q'): return MCC ('n', 'e');
6215 case MCC ('v', 'c'): return MCC ('v', 's');
6216 case MCC ('v', 's'): return MCC ('v', 'c');
6217 case MCC ('p', 'l'): return MCC ('m', 'i');
6218 case MCC ('m', 'i'): return MCC ('p', 'l');
6219 case MCC ('g', 'e'): return MCC ('l', 't');
6220 case MCC ('l', 't'): return MCC ('g', 'e');
6221 case MCC ('g', 't'): return MCC ('l', 'e');
6222 case MCC ('l', 'e'): return MCC ('g', 't');
6223 }
6224 return cc;
6225}
6226
6227/* Build an MRI structured control expression. This generates test
6228 and branch instructions. It goes to TRUELAB if the condition is
6229 true, and to FALSELAB if the condition is false. Exactly one of
6230 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6231 is the size qualifier for the expression. EXTENT is the size to
6232 use for the branch. */
6233
6234static void
31302357
AS		 6235build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6236 char *rightstart, char *rightstop,
6237 const char *truelab, const char *falselab,
6238 int extent)
252b5132
RH		 6239{
6240 char *buf;
6241 char *s;
6242
6243 if (leftstart != NULL)
6244 {
6245 struct m68k_op leftop, rightop;
6246 char c;
6247
6248 /* Swap the compare operands, if necessary, to produce a legal
6249 m68k compare instruction. Comparing a register operand with
6250 a non-register operand requires the register to be on the
6251 right (cmp, cmpa). Comparing an immediate value with
6252 anything requires the immediate value to be on the left
6253 (cmpi). */
6254
6255 c = *leftstop;
6256 *leftstop = '\0';
6257 (void) m68k_ip_op (leftstart, &leftop);
6258 *leftstop = c;
6259
6260 c = *rightstop;
6261 *rightstop = '\0';
6262 (void) m68k_ip_op (rightstart, &rightop);
6263 *rightstop = c;
6264
6265 if (rightop.mode == IMMED
6266 || ((leftop.mode == DREG || leftop.mode == AREG)
6267 && (rightop.mode != DREG && rightop.mode != AREG)))
6268 {
6269 char *temp;
6270
31302357
AS		 6271 /* Correct conditional handling:
6272 if #1 <lt> d0 then ;means if (1 < d0)
6273 ...
6274 endi
e1f44d10 6275
31302357 6276 should assemble to:
e1f44d10 6277
31302357
AS		 6278 cmp #1,d0 if we do *not* swap the operands
6279 bgt true we need the swapped condition!
6280 ble false
6281 true:
6282 ...
6283 false:
6284 */
252b5132
RH		 6285 temp = leftstart;
6286 leftstart = rightstart;
6287 rightstart = temp;
6288 temp = leftstop;
6289 leftstop = rightstop;
6290 rightstop = temp;
8a104df9
KH		 6291 }
6292 else
6293 {
e1f44d10 6294 cc = swap_mri_condition (cc);
252b5132
RH		 6295 }
6296 }
6297
6298 if (truelab == NULL)
6299 {
6300 cc = reverse_mri_condition (cc);
6301 truelab = falselab;
6302 }
92774660 6303
252b5132
RH		 6304 if (leftstart != NULL)
6305 {
6306 buf = (char *) xmalloc (20
6307 + (leftstop - leftstart)
6308 + (rightstop - rightstart));
6309 s = buf;
6310 *s++ = 'c';
6311 *s++ = 'm';
6312 *s++ = 'p';
6313 if (qual != '\0')
3882b010 6314 *s++ = TOLOWER (qual);
252b5132
RH		 6315 *s++ = ' ';
6316 memcpy (s, leftstart, leftstop - leftstart);
6317 s += leftstop - leftstart;
6318 *s++ = ',';
6319 memcpy (s, rightstart, rightstop - rightstart);
6320 s += rightstop - rightstart;
6321 *s = '\0';
6322 mri_assemble (buf);
6323 free (buf);
6324 }
92774660 6325
252b5132
RH		 6326 buf = (char *) xmalloc (20 + strlen (truelab));
6327 s = buf;
6328 *s++ = 'b';
6329 *s++ = cc >> 8;
6330 *s++ = cc & 0xff;
6331 if (extent != '\0')
3882b010 6332 *s++ = TOLOWER (extent);
252b5132
RH		 6333 *s++ = ' ';
6334 strcpy (s, truelab);
6335 mri_assemble (buf);
6336 free (buf);
6337}
6338
6339/* Parse an MRI structured control expression. This generates test
6340 and branch instructions. STOP is where the expression ends. It
6341 goes to TRUELAB if the condition is true, and to FALSELAB if the
6342 condition is false. Exactly one of TRUELAB and FALSELAB will be
6343 NULL, meaning to fall through. QUAL is the size qualifier for the
6344 expression. EXTENT is the size to use for the branch. */
6345
6346static void
31302357
AS		 6347parse_mri_control_expression (char *stop, int qual, const char *truelab,
6348 const char *falselab, int extent)
252b5132
RH		 6349{
6350 int c;
6351 int cc;
6352 char *leftstart;
6353 char *leftstop;
6354 char *rightstart;
6355 char *rightstop;
6356
6357 c = *stop;
6358 *stop = '\0';
6359
6360 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6361 &rightstart, &rightstop))
6362 {
6363 *stop = c;
6364 return;
6365 }
6366
6367 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6368 {
6369 const char *flab;
6370
6371 if (falselab != NULL)
6372 flab = falselab;
6373 else
6374 flab = mri_control_label ();
6375
6376 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6377 rightstop, (const char *) NULL, flab, extent);
6378
6379 input_line_pointer += 3;
6380 if (*input_line_pointer != '.'
6381 || input_line_pointer[1] == '\0')
6382 qual = '\0';
6383 else
6384 {
6385 qual = input_line_pointer[1];
6386 input_line_pointer += 2;
6387 }
6388
6389 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6390 &rightstart, &rightstop))
6391 {
6392 *stop = c;
6393 return;
6394 }
6395
6396 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6397 rightstop, truelab, falselab, extent);
6398
6399 if (falselab == NULL)
6400 colon (flab);
6401 }
6402 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6403 {
6404 const char *tlab;
6405
6406 if (truelab != NULL)
6407 tlab = truelab;
6408 else
6409 tlab = mri_control_label ();
6410
6411 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6412 rightstop, tlab, (const char *) NULL, extent);
6413
6414 input_line_pointer += 2;
6415 if (*input_line_pointer != '.'
6416 || input_line_pointer[1] == '\0')
6417 qual = '\0';
6418 else
6419 {
6420 qual = input_line_pointer[1];
6421 input_line_pointer += 2;
6422 }
6423
6424 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6425 &rightstart, &rightstop))
6426 {
6427 *stop = c;
6428 return;
6429 }
6430
6431 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6432 rightstop, truelab, falselab, extent);
6433
6434 if (truelab == NULL)
6435 colon (tlab);
6436 }
6437 else
6438 {
6439 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6440 rightstop, truelab, falselab, extent);
6441 }
6442
6443 *stop = c;
6444 if (input_line_pointer != stop)
6445 as_bad (_("syntax error in structured control directive"));
6446}
6447
6448/* Handle the MRI IF pseudo-op. This may be a structured control
6449 directive, or it may be a regular assembler conditional, depending
6450 on its operands. */
6451
6452static void
31302357 6453s_mri_if (int qual)
252b5132
RH		 6454{
6455 char *s;
6456 int c;
6457 struct mri_control_info *n;
6458
6459 /* A structured control directive must end with THEN with an
6460 optional qualifier. */
6461 s = input_line_pointer;
e1f44d10
NC		 6462 /* We only accept '*' as introduction of comments if preceded by white space
6463 or at first column of a line (I think this can't actually happen here?)
6464 This is important when assembling:
6465 if d0 <ne> 12(a0,d0*2) then
36759679 6466 if d0 <ne> #CONST*20 then. */
31302357
AS		 6467 while (! (is_end_of_line[(unsigned char) *s]
6468 || (flag_mri
6469 && *s == '*'
6470 && (s == input_line_pointer
6471 || *(s-1) == ' '
6472 || *(s-1) == '\t'))))
252b5132
RH		 6473 ++s;
6474 --s;
6475 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6476 --s;
6477
6478 if (s - input_line_pointer > 1
6479 && s[-1] == '.')
6480 s -= 2;
6481
6482 if (s - input_line_pointer < 3
6483 || strncasecmp (s - 3, "THEN", 4) != 0)
6484 {
6485 if (qual != '\0')
6486 {
6487 as_bad (_("missing then"));
6488 ignore_rest_of_line ();
6489 return;
6490 }
6491
6492 /* It's a conditional. */
6493 s_if (O_ne);
6494 return;
6495 }
6496
6497 /* Since this might be a conditional if, this pseudo-op will be
6498 called even if we are supported to be ignoring input. Double
6499 check now. Clobber *input_line_pointer so that ignore_input
6500 thinks that this is not a special pseudo-op. */
6501 c = *input_line_pointer;
6502 *input_line_pointer = 0;
6503 if (ignore_input ())
6504 {
6505 *input_line_pointer = c;
6506 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6507 ++input_line_pointer;
6508 demand_empty_rest_of_line ();
6509 return;
6510 }
6511 *input_line_pointer = c;
6512
6513 n = push_mri_control (mri_if);
6514
6515 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6516 n->next, s[1] == '.' ? s[2] : '\0');
6517
6518 if (s[1] == '.')
6519 input_line_pointer = s + 3;
6520 else
6521 input_line_pointer = s + 1;
6522
6523 if (flag_mri)
6524 {
6525 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6526 ++input_line_pointer;
6527 }
6528
6529 demand_empty_rest_of_line ();
6530}
6531
6532/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6533 structured IF, associate the ELSE with the IF. Otherwise, assume
6534 it is a conditional else. */
6535
6536static void
31302357 6537s_mri_else (int qual)
252b5132
RH		 6538{
6539 int c;
6540 char *buf;
6541 char q[2];
6542
6543 if (qual == '\0'
6544 && (mri_control_stack == NULL
6545 || mri_control_stack->type != mri_if
6546 || mri_control_stack->else_seen))
6547 {
6548 s_else (0);
6549 return;
6550 }
6551
6552 c = *input_line_pointer;
6553 *input_line_pointer = 0;
6554 if (ignore_input ())
6555 {
6556 *input_line_pointer = c;
6557 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6558 ++input_line_pointer;
6559 demand_empty_rest_of_line ();
6560 return;
6561 }
6562 *input_line_pointer = c;
6563
6564 if (mri_control_stack == NULL
6565 || mri_control_stack->type != mri_if
6566 || mri_control_stack->else_seen)
6567 {
6568 as_bad (_("else without matching if"));
6569 ignore_rest_of_line ();
6570 return;
6571 }
6572
6573 mri_control_stack->else_seen = 1;
6574
6575 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6576 q[0] = TOLOWER (qual);
252b5132
RH		 6577 q[1] = '\0';
6578 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6579 mri_assemble (buf);
6580 free (buf);
6581
6582 colon (mri_control_stack->next);
6583
6584 if (flag_mri)
6585 {
6586 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6587 ++input_line_pointer;
6588 }
6589
6590 demand_empty_rest_of_line ();
6591}
6592
6593/* Handle the MRI ENDI pseudo-op. */
6594
6595static void
31302357 6596s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6597{
6598 if (mri_control_stack == NULL
6599 || mri_control_stack->type != mri_if)
6600 {
6601 as_bad (_("endi without matching if"));
6602 ignore_rest_of_line ();
6603 return;
6604 }
6605
6606 /* ignore_input will not return true for ENDI, so we don't need to
6607 worry about checking it again here. */
6608
6609 if (! mri_control_stack->else_seen)
6610 colon (mri_control_stack->next);
6611 colon (mri_control_stack->bottom);
6612
6613 pop_mri_control ();
6614
6615 if (flag_mri)
6616 {
6617 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6618 ++input_line_pointer;
6619 }
6620
6621 demand_empty_rest_of_line ();
6622}
6623
6624/* Handle the MRI BREAK pseudo-op. */
6625
6626static void
31302357 6627s_mri_break (int extent)
252b5132
RH		 6628{
6629 struct mri_control_info *n;
6630 char *buf;
6631 char ex[2];
6632
6633 n = mri_control_stack;
6634 while (n != NULL
6635 && n->type != mri_for
6636 && n->type != mri_repeat
6637 && n->type != mri_while)
6638 n = n->outer;
6639 if (n == NULL)
6640 {
6641 as_bad (_("break outside of structured loop"));
6642 ignore_rest_of_line ();
6643 return;
6644 }
6645
6646 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6647 ex[0] = TOLOWER (extent);
252b5132
RH		 6648 ex[1] = '\0';
6649 sprintf (buf, "bra%s %s", ex, n->bottom);
6650 mri_assemble (buf);
6651 free (buf);
6652
6653 if (flag_mri)
6654 {
6655 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6656 ++input_line_pointer;
6657 }
6658
6659 demand_empty_rest_of_line ();
6660}
6661
6662/* Handle the MRI NEXT pseudo-op. */
6663
6664static void
31302357 6665s_mri_next (int extent)
252b5132
RH		 6666{
6667 struct mri_control_info *n;
6668 char *buf;
6669 char ex[2];
6670
6671 n = mri_control_stack;
6672 while (n != NULL
6673 && n->type != mri_for
6674 && n->type != mri_repeat
6675 && n->type != mri_while)
6676 n = n->outer;
6677 if (n == NULL)
6678 {
6679 as_bad (_("next outside of structured loop"));
6680 ignore_rest_of_line ();
6681 return;
6682 }
6683
6684 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6685 ex[0] = TOLOWER (extent);
252b5132
RH		 6686 ex[1] = '\0';
6687 sprintf (buf, "bra%s %s", ex, n->next);
6688 mri_assemble (buf);
6689 free (buf);
6690
6691 if (flag_mri)
6692 {
6693 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6694 ++input_line_pointer;
6695 }
6696
6697 demand_empty_rest_of_line ();
6698}
6699
6700/* Handle the MRI FOR pseudo-op. */
6701
6702static void
31302357 6703s_mri_for (int qual)
252b5132
RH		 6704{
6705 const char *varstart, *varstop;
6706 const char *initstart, *initstop;
6707 const char *endstart, *endstop;
6708 const char *bystart, *bystop;
6709 int up;
6710 int by;
6711 int extent;
6712 struct mri_control_info *n;
6713 char *buf;
6714 char *s;
6715 char ex[2];
6716
6717 /* The syntax is
6718 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6719 */
6720
6721 SKIP_WHITESPACE ();
6722 varstart = input_line_pointer;
6723
6724 /* Look for the '='. */
6725 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6726 && *input_line_pointer != '=')
6727 ++input_line_pointer;
6728 if (*input_line_pointer != '=')
6729 {
6730 as_bad (_("missing ="));
6731 ignore_rest_of_line ();
6732 return;
6733 }
6734
6735 varstop = input_line_pointer;
6736 if (varstop > varstart
6737 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6738 --varstop;
6739
6740 ++input_line_pointer;
6741
6742 initstart = input_line_pointer;
6743
6744 /* Look for TO or DOWNTO. */
6745 up = 1;
6746 initstop = NULL;
6747 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6748 {
6749 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6750 && ! is_part_of_name (input_line_pointer[2]))
6751 {
6752 initstop = input_line_pointer;
6753 input_line_pointer += 2;
6754 break;
6755 }
6756 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6757 && ! is_part_of_name (input_line_pointer[6]))
6758 {
6759 initstop = input_line_pointer;
6760 up = 0;
6761 input_line_pointer += 6;
6762 break;
6763 }
6764 ++input_line_pointer;
6765 }
6766 if (initstop == NULL)
6767 {
6768 as_bad (_("missing to or downto"));
6769 ignore_rest_of_line ();
6770 return;
6771 }
6772 if (initstop > initstart
6773 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6774 --initstop;
6775
6776 SKIP_WHITESPACE ();
6777 endstart = input_line_pointer;
6778
6779 /* Look for BY or DO. */
6780 by = 0;
6781 endstop = NULL;
6782 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6783 {
6784 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6785 && ! is_part_of_name (input_line_pointer[2]))
6786 {
6787 endstop = input_line_pointer;
6788 by = 1;
6789 input_line_pointer += 2;
6790 break;
6791 }
6792 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6793 && (input_line_pointer[2] == '.'
6794 || ! is_part_of_name (input_line_pointer[2])))
6795 {
6796 endstop = input_line_pointer;
6797 input_line_pointer += 2;
6798 break;
6799 }
6800 ++input_line_pointer;
6801 }
6802 if (endstop == NULL)
6803 {
6804 as_bad (_("missing do"));
6805 ignore_rest_of_line ();
6806 return;
6807 }
6808 if (endstop > endstart
6809 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6810 --endstop;
6811
6812 if (! by)
6813 {
6814 bystart = "#1";
6815 bystop = bystart + 2;
6816 }
6817 else
6818 {
6819 SKIP_WHITESPACE ();
6820 bystart = input_line_pointer;
6821
6822 /* Look for DO. */
6823 bystop = NULL;
6824 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6825 {
6826 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6827 && (input_line_pointer[2] == '.'
6828 || ! is_part_of_name (input_line_pointer[2])))
6829 {
6830 bystop = input_line_pointer;
6831 input_line_pointer += 2;
6832 break;
6833 }
6834 ++input_line_pointer;
6835 }
6836 if (bystop == NULL)
6837 {
6838 as_bad (_("missing do"));
6839 ignore_rest_of_line ();
6840 return;
6841 }
6842 if (bystop > bystart
6843 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6844 --bystop;
6845 }
6846
6847 if (*input_line_pointer != '.')
6848 extent = '\0';
6849 else
6850 {
6851 extent = input_line_pointer[1];
6852 input_line_pointer += 2;
6853 }
6854
6855 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6856 n = push_mri_control (mri_for);
6857
6858 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6859
36759679 6860 /* Move init,var. */
252b5132
RH		 6861 s = buf;
6862 *s++ = 'm';
6863 *s++ = 'o';
6864 *s++ = 'v';
6865 *s++ = 'e';
6866 if (qual != '\0')
3882b010 6867 *s++ = TOLOWER (qual);
252b5132
RH		 6868 *s++ = ' ';
6869 memcpy (s, initstart, initstop - initstart);
6870 s += initstop - initstart;
6871 *s++ = ',';
6872 memcpy (s, varstart, varstop - varstart);
6873 s += varstop - varstart;
6874 *s = '\0';
6875 mri_assemble (buf);
6876
6877 colon (n->top);
6878
36759679 6879 /* cmp end,var. */
252b5132
RH		 6880 s = buf;
6881 *s++ = 'c';
6882 *s++ = 'm';
6883 *s++ = 'p';
6884 if (qual != '\0')
3882b010 6885 *s++ = TOLOWER (qual);
252b5132
RH		 6886 *s++ = ' ';
6887 memcpy (s, endstart, endstop - endstart);
6888 s += endstop - endstart;
6889 *s++ = ',';
6890 memcpy (s, varstart, varstop - varstart);
6891 s += varstop - varstart;
6892 *s = '\0';
6893 mri_assemble (buf);
6894
36759679 6895 /* bcc bottom. */
3882b010 6896 ex[0] = TOLOWER (extent);
252b5132
RH		 6897 ex[1] = '\0';
6898 if (up)
6899 sprintf (buf, "blt%s %s", ex, n->bottom);
6900 else
6901 sprintf (buf, "bgt%s %s", ex, n->bottom);
6902 mri_assemble (buf);
6903
6904 /* Put together the add or sub instruction used by ENDF. */
6905 s = buf;
6906 if (up)
6907 strcpy (s, "add");
6908 else
6909 strcpy (s, "sub");
6910 s += 3;
6911 if (qual != '\0')
3882b010 6912 *s++ = TOLOWER (qual);
252b5132
RH		 6913 *s++ = ' ';
6914 memcpy (s, bystart, bystop - bystart);
6915 s += bystop - bystart;
6916 *s++ = ',';
6917 memcpy (s, varstart, varstop - varstart);
6918 s += varstop - varstart;
6919 *s = '\0';
6920 n->incr = buf;
6921
6922 if (flag_mri)
6923 {
6924 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6925 ++input_line_pointer;
6926 }
6927
6928 demand_empty_rest_of_line ();
6929}
6930
6931/* Handle the MRI ENDF pseudo-op. */
6932
6933static void
31302357 6934s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6935{
6936 if (mri_control_stack == NULL
6937 || mri_control_stack->type != mri_for)
6938 {
6939 as_bad (_("endf without for"));
6940 ignore_rest_of_line ();
6941 return;
6942 }
6943
6944 colon (mri_control_stack->next);
6945
6946 mri_assemble (mri_control_stack->incr);
6947
6948 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6949 mri_assemble (mri_control_stack->incr);
6950
6951 free (mri_control_stack->incr);
6952
6953 colon (mri_control_stack->bottom);
6954
6955 pop_mri_control ();
6956
6957 if (flag_mri)
6958 {
6959 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6960 ++input_line_pointer;
6961 }
6962
6963 demand_empty_rest_of_line ();
6964}
6965
6966/* Handle the MRI REPEAT pseudo-op. */
6967
6968static void
31302357 6969s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6970{
6971 struct mri_control_info *n;
6972
6973 n = push_mri_control (mri_repeat);
6974 colon (n->top);
6975 if (flag_mri)
6976 {
6977 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6978 ++input_line_pointer;
6979 }
6980 demand_empty_rest_of_line ();
6981}
6982
6983/* Handle the MRI UNTIL pseudo-op. */
6984
6985static void
31302357 6986s_mri_until (int qual)
252b5132
RH		 6987{
6988 char *s;
6989
6990 if (mri_control_stack == NULL
6991 || mri_control_stack->type != mri_repeat)
6992 {
6993 as_bad (_("until without repeat"));
6994 ignore_rest_of_line ();
6995 return;
6996 }
6997
6998 colon (mri_control_stack->next);
6999
7000 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7001 ;
7002
7003 parse_mri_control_expression (s, qual, (const char *) NULL,
7004 mri_control_stack->top, '\0');
7005
7006 colon (mri_control_stack->bottom);
7007
7008 input_line_pointer = s;
7009
7010 pop_mri_control ();
7011
7012 if (flag_mri)
7013 {
7014 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7015 ++input_line_pointer;
7016 }
7017
7018 demand_empty_rest_of_line ();
7019}
7020
7021/* Handle the MRI WHILE pseudo-op. */
7022
7023static void
31302357 7024s_mri_while (int qual)
252b5132
RH		 7025{
7026 char *s;
7027
7028 struct mri_control_info *n;
7029
7030 s = input_line_pointer;
e1f44d10
NC		 7031 /* We only accept '*' as introduction of comments if preceded by white space
7032 or at first column of a line (I think this can't actually happen here?)
7033 This is important when assembling:
7034 while d0 <ne> 12(a0,d0*2) do
36759679 7035 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7036 while (! (is_end_of_line[(unsigned char) *s]
7037 || (flag_mri
7038 && *s == '*'
7039 && (s == input_line_pointer
7040 || *(s-1) == ' '
7041 || *(s-1) == '\t'))))
252b5132
RH		 7042 s++;
7043 --s;
7044 while (*s == ' ' || *s == '\t')
7045 --s;
7046 if (s - input_line_pointer > 1
7047 && s[-1] == '.')
7048 s -= 2;
7049 if (s - input_line_pointer < 2
7050 || strncasecmp (s - 1, "DO", 2) != 0)
7051 {
7052 as_bad (_("missing do"));
7053 ignore_rest_of_line ();
7054 return;
7055 }
7056
7057 n = push_mri_control (mri_while);
7058
7059 colon (n->next);
7060
7061 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7062 s[1] == '.' ? s[2] : '\0');
7063
7064 input_line_pointer = s + 1;
7065 if (*input_line_pointer == '.')
7066 input_line_pointer += 2;
7067
7068 if (flag_mri)
7069 {
7070 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7071 ++input_line_pointer;
7072 }
7073
7074 demand_empty_rest_of_line ();
7075}
7076
7077/* Handle the MRI ENDW pseudo-op. */
7078
7079static void
31302357 7080s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7081{
7082 char *buf;
7083
7084 if (mri_control_stack == NULL
7085 || mri_control_stack->type != mri_while)
7086 {
7087 as_bad (_("endw without while"));
7088 ignore_rest_of_line ();
7089 return;
7090 }
7091
7092 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7093 sprintf (buf, "bra %s", mri_control_stack->next);
7094 mri_assemble (buf);
7095 free (buf);
7096
7097 colon (mri_control_stack->bottom);
7098
7099 pop_mri_control ();
7100
7101 if (flag_mri)
7102 {
7103 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7104 ++input_line_pointer;
7105 }
7106
7107 demand_empty_rest_of_line ();
7108}
7109\f
266abb8f
NS		 7110/* Parse a .cpu directive. */
7111
7112static void
7113s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7114{
7115 char saved_char;
7116 char *name;
7117
7118 if (initialized)
7119 {
7120 as_bad (_("already assembled instructions"));
7121 ignore_rest_of_line ();
7122 return;
7123 }
7124
7125 name = input_line_pointer;
7126 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7127 input_line_pointer++;
7128 saved_char = *input_line_pointer;
7129 *input_line_pointer = 0;
7130
7131 m68k_set_cpu (name, 1, 0);
7132
7133 *input_line_pointer = saved_char;
7134 demand_empty_rest_of_line ();
7135 return;
7136}
7137
7138/* Parse a .arch directive. */
7139
7140static void
7141s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7142{
7143 char saved_char;
7144 char *name;
7145
7146 if (initialized)
7147 {
7148 as_bad (_("already assembled instructions"));
7149 ignore_rest_of_line ();
7150 return;
7151 }
7152
7153 name = input_line_pointer;
7154 while (*input_line_pointer && *input_line_pointer != ','
7155 && !ISSPACE (*input_line_pointer))
7156 input_line_pointer++;
7157 saved_char = *input_line_pointer;
7158 *input_line_pointer = 0;
7159
7160 if (m68k_set_arch (name, 1, 0))
7161 {
7162 /* Scan extensions. */
7163 do
7164 {
7165 *input_line_pointer++ = saved_char;
7166 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7167 break;
7168 name = input_line_pointer;
7169 while (*input_line_pointer && *input_line_pointer != ','
7170 && !ISSPACE (*input_line_pointer))
7171 input_line_pointer++;
7172 saved_char = *input_line_pointer;
7173 *input_line_pointer = 0;
7174 }
7175 while (m68k_set_extension (name, 1, 0));
7176 }
7177
7178 *input_line_pointer = saved_char;
7179 demand_empty_rest_of_line ();
7180 return;
7181}
7182\f
7183/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7184 if none is found, the caller is responsible for emitting an error
7185 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7186 cpu name, if it begins with a '6' (possibly skipping an intervening
7187 'c'. We also allow a 'c' in the same place. if NEGATED is
7188 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7189 the option is indeed negated. */
7190
7191static const struct m68k_cpu *
7192m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7193 int allow_m, int *negated)
7194{
7195 /* allow negated value? */
7196 if (negated)
7197 {
7198 *negated = 0;
7199
7200 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7201 {
7202 arg += 3;
7203 *negated = 1;
7204 }
7205 }
7206
7207 /* Remove 'm' or 'mc' prefix from 68k variants. */
7208 if (allow_m)
7209 {
7210 if (arg[0] == 'm')
7211 {
7212 if (arg[1] == '6')
7213 arg += 1;
7214 else if (arg[1] == 'c' && arg[2] == '6')
7215 arg += 2;
7216 }
7217 }
7218 else if (arg[0] == 'c' && arg[1] == '6')
7219 arg += 1;
7220
7221 for (; table->name; table++)
7222 if (!strcmp (arg, table->name))
2da12c60
NS		 7223 {
7224 if (table->alias < -1 || table->alias > 1)
7225 as_bad (_("`%s' is deprecated, use `%s'"),
7226 table->name, table[table->alias < 0 ? 1 : -1].name);
7227 return table;
7228 }
266abb8f
NS		 7229 return 0;
7230}
7231
7232/* Set the cpu, issuing errors if it is unrecognized, or invalid */
7233
7234static int
7235m68k_set_cpu (char const *name, int allow_m, int silent)
7236{
7237 const struct m68k_cpu *cpu;
7238
7239 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7240
7241 if (!cpu)
7242 {
7243 if (!silent)
7244 as_bad (_("cpu `%s' unrecognized"), name);
7245 return 0;
7246 }
7247
7248 if (selected_cpu && selected_cpu != cpu)
7249 {
7250 as_bad (_("already selected `%s' processor"),
7251 selected_cpu->name);
7252 return 0;
7253 }
7254 selected_cpu = cpu;
7255 return 1;
7256}
7257
7258/* Set the architecture, issuing errors if it is unrecognized, or invalid */
7259
7260static int
7261m68k_set_arch (char const *name, int allow_m, int silent)
7262{
7263 const struct m68k_cpu *arch;
7264
7265 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7266
7267 if (!arch)
7268 {
7269 if (!silent)
7270 as_bad (_("architecture `%s' unrecognized"), name);
7271 return 0;
7272 }
7273
7274 if (selected_arch && selected_arch != arch)
7275 {
7276 as_bad (_("already selected `%s' architecture"),
7277 selected_arch->name);
7278 return 0;
7279 }
7280
7281 selected_arch = arch;
7282 return 1;
7283}
7284
7285/* Set the architecture extension, issuing errors if it is
7286 unrecognized, or invalid */
7287
7288static int
7289m68k_set_extension (char const *name, int allow_m, int silent)
7290{
7291 int negated;
7292 const struct m68k_cpu *ext;
7293
7294 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7295
7296 if (!ext)
7297 {
7298 if (!silent)
7299 as_bad (_("extension `%s' unrecognized"), name);
7300 return 0;
7301 }
7302
7303 if (negated)
7304 not_current_architecture |= ext->arch;
7305 else
7306 current_architecture |= ext->arch;
7307 return 1;
7308}
7309
31302357
AS		 7310/* md_parse_option
7311 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7312 */
252b5132
RH		 7313
7314#ifdef OBJ_ELF
5a38dc70 7315const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7316#else
5a38dc70 7317const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7318#endif
7319
7320struct option md_longopts[] = {
7321#define OPTION_PIC (OPTION_MD_BASE)
7322 {"pic", no_argument, NULL, OPTION_PIC},
7323#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7324 {"register-prefix-optional", no_argument, NULL,
7325 OPTION_REGISTER_PREFIX_OPTIONAL},
7326#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7327 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7328#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7329 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7330#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7331 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7332#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7333 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7334#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7335 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7336#define OPTION_PCREL (OPTION_MD_BASE + 7)
7337 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7338 {NULL, no_argument, NULL, 0}
7339};
bc805888 7340size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7341
7342int
31302357 7343md_parse_option (int c, char *arg)
252b5132
RH		 7344{
7345 switch (c)
7346 {
7347 case 'l': /* -l means keep external to 2 bit offset
36759679 7348 rather than 16 bit one. */
252b5132
RH		 7349 flag_short_refs = 1;
7350 break;
7351
7352 case 'S': /* -S means that jbsr's always turn into
7353 jsr's. */
7354 flag_long_jumps = 1;
7355 break;
7356
28e7409f
NC		 7357 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7358 branches into absolute jumps. */
7359 flag_keep_pcrel = 1;
7360 break;
7361
252b5132
RH		 7362 case OPTION_PIC:
7363 case 'k':
7364 flag_want_pic = 1;
36759679 7365 break; /* -pic, Position Independent Code. */
252b5132
RH		 7366
7367 case OPTION_REGISTER_PREFIX_OPTIONAL:
7368 flag_reg_prefix_optional = 1;
7369 reg_prefix_optional_seen = 1;
7370 break;
7371
7372 /* -V: SVR4 argument to print version ID. */
7373 case 'V':
7374 print_version_id ();
7375 break;
7376
7377 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7378 should be emitted or not. FIXME: Not implemented. */
7379 case 'Q':
7380 break;
7381
7382 case OPTION_BITWISE_OR:
7383 {
7384 char *n, *t;
7385 const char *s;
7386
7387 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7388 t = n;
7389 for (s = m68k_comment_chars; *s != '\0'; s++)
7390 if (*s != '|')
7391 *t++ = *s;
7392 *t = '\0';
7393 m68k_comment_chars = n;
7394 }
7395 break;
7396
7397 case OPTION_BASE_SIZE_DEFAULT_16:
7398 m68k_index_width_default = SIZE_WORD;
7399 break;
7400
7401 case OPTION_BASE_SIZE_DEFAULT_32:
7402 m68k_index_width_default = SIZE_LONG;
7403 break;
7404
7405 case OPTION_DISP_SIZE_DEFAULT_16:
7406 m68k_rel32 = 0;
7407 m68k_rel32_from_cmdline = 1;
7408 break;
7409
7410 case OPTION_DISP_SIZE_DEFAULT_32:
7411 m68k_rel32 = 1;
7412 m68k_rel32_from_cmdline = 1;
7413 break;
7414
266abb8f
NS		 7415 case 'A':
7416#if WARN_DEPRECATED
7417 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7418 arg, arg));
7419#endif
7420 /* Intentional fall-through. */
7421 case 'm':
7422 if (!strncmp (arg, "arch=", 5))
7423 m68k_set_arch (arg + 5, 1, 0);
7424 else if (!strncmp (arg, "cpu=", 4))
7425 m68k_set_cpu (arg + 4, 1, 0);
7426 else if (m68k_set_extension (arg, 0, 1))
7427 ;
0b2e31dc
NS		 7428 else if (m68k_set_arch (arg, 0, 1))
7429 ;
266abb8f
NS		 7430 else if (m68k_set_cpu (arg, 0, 1))
7431 ;
7432 else
7433 return 0;
7434 break;
7435
252b5132
RH		 7436 default:
7437 return 0;
7438 }
7439
7440 return 1;
7441}
7442
266abb8f
NS		 7443/* Setup tables from the selected arch and/or cpu */
7444
7445static void
7446m68k_init_arch (void)
7447{
266abb8f
NS		 7448 if (not_current_architecture & current_architecture)
7449 {
7450 as_bad (_("architecture features both enabled and disabled"));
7451 not_current_architecture &= ~current_architecture;
7452 }
7453 if (selected_arch)
2da12c60
NS		 7454 {
7455 current_architecture |= selected_arch->arch;
7456 control_regs = selected_arch->control_regs;
7457 }
0b2e31dc
NS		 7458 else
7459 current_architecture |= selected_cpu->arch;
0b2e31dc 7460
2da12c60
NS		 7461 current_architecture &= ~not_current_architecture;
7462
377260ba
NS		 7463 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7464 {
7465 /* Determine which float is really meant. */
7466 if (current_architecture & (m68k_mask & ~m68881))
7467 current_architecture ^= cfloat;
7468 else
7469 current_architecture ^= m68881;
7470 }
7471
0b2e31dc 7472 if (selected_cpu)
266abb8f 7473 {
2da12c60 7474 control_regs = selected_cpu->control_regs;
0b2e31dc 7475 if (current_architecture & ~selected_cpu->arch)
266abb8f 7476 {
0b2e31dc
NS		 7477 as_bad (_("selected processor does not have all features of selected architecture"));
7478 current_architecture
7479 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7480 }
7481 }
266abb8f 7482
266abb8f
NS		 7483 if ((current_architecture & m68k_mask)
7484 && (current_architecture & ~m68k_mask))
7485 {
7486 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7487 if (current_architecture & m68k_mask)
266abb8f
NS		 7488 current_architecture &= m68k_mask;
7489 else
7490 current_architecture &= ~m68k_mask;
7491 }
7492
7493 /* Permit m68881 specification with all cpus; those that can't work
7494 with a coprocessor could be doing emulation. */
7495 if (current_architecture & m68851)
7496 {
7497 if (current_architecture & m68040)
7498 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7499 }
7500 /* What other incompatibilities could we check for? */
7501
266abb8f
NS		 7502 if (cpu_of_arch (current_architecture) < m68020
7503 || arch_coldfire_p (current_architecture))
7504 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7505
7506 initialized = 1;
7507}
7508
252b5132 7509void
31302357 7510md_show_usage (FILE *stream)
252b5132 7511{
76f57f3a 7512 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7513 int i;
7514 unsigned int default_arch;
76f57f3a 7515
8a104df9 7516 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7517 if (*default_cpu == 'm')
7518 default_cpu++;
266abb8f 7519 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7520 {
266abb8f 7521 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7522 {
266abb8f 7523 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7524 while (m68k_cpus[i].alias > 0)
7525 i--;
7526 while (m68k_cpus[i].alias < 0)
7527 i++;
7528 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7529 }
7530 }
7531
bc805888 7532 fprintf (stream, _("\
266abb8f
NS		 7533-march=<arch> set architecture\n\
7534-mcpu=<cpu> set cpu [default %s]\n\
7535"), default_cpu);
7536 for (i = 0; m68k_extensions[i].name; i++)
7537 fprintf (stream, _("\
0b2e31dc
NS		 7538-m[no-]%-16s enable/disable%s architecture extension\n\
7539"), m68k_extensions[i].name,
7540 m68k_extensions[i].alias > 0 ? " ColdFire"
7541 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7542
bc805888 7543 fprintf (stream, _("\
266abb8f 7544-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7545-pic, -k generate position independent code\n\
7546-S turn jbsr into jsr\n\
28e7409f 7547--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7548--register-prefix-optional\n\
7549 recognize register names without prefix character\n\
266abb8f 7550--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7551--base-size-default-16 base reg without size is 16 bits\n\
7552--base-size-default-32 base reg without size is 32 bits (default)\n\
7553--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7554--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7555"));
7556
7557 fprintf (stream, _("Architecture variants are: "));
7558 for (i = 0; m68k_archs[i].name; i++)
7559 {
7560 if (i)
7561 fprintf (stream, " | ");
7562 fprintf (stream, m68k_archs[i].name);
7563 }
7564 fprintf (stream, "\n");
7565
7566 fprintf (stream, _("Processor variants are: "));
7567 for (i = 0; m68k_cpus[i].name; i++)
7568 {
7569 if (i)
7570 fprintf (stream, " | ");
7571 fprintf (stream, m68k_cpus[i].name);
7572 }
7573 fprintf (stream, _("\n"));
252b5132
RH		 7574}
7575\f
7576#ifdef TEST2
7577
7578/* TEST2: Test md_assemble() */
36759679
NC		 7579/* Warning, this routine probably doesn't work anymore. */
7580int
31302357 7581main (void)
252b5132
RH		 7582{
7583 struct m68k_it the_ins;
7584 char buf[120];
7585 char *cp;
7586 int n;
7587
7588 m68k_ip_begin ();
7589 for (;;)
7590 {
7591 if (!gets (buf) || !*buf)
7592 break;
7593 if (buf[0] == '|' || buf[1] == '.')
7594 continue;
7595 for (cp = buf; *cp; cp++)
7596 if (*cp == '\t')
7597 *cp = ' ';
7598 if (is_label (buf))
7599 continue;
7600 memset (&the_ins, '\0', sizeof (the_ins));
7601 m68k_ip (&the_ins, buf);
7602 if (the_ins.error)
7603 {
7604 printf (_("Error %s in %s\n"), the_ins.error, buf);
7605 }
7606 else
7607 {
7608 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7609 for (n = 0; n < the_ins.numo; n++)
7610 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7611 printf (" ");
7612 print_the_insn (&the_ins.opcode[0], stdout);
7613 (void) putchar ('\n');
7614 }
7615 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7616 {
7617 if (the_ins.operands[n].error)
7618 {
7619 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7620 continue;
7621 }
31302357
AS		 7622 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7623 the_ins.operands[n].reg);
252b5132 7624 if (the_ins.operands[n].b_const)
31302357
AS		 7625 printf ("Constant: '%.*s', ",
7626 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7627 the_ins.operands[n].b_const);
7628 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7629 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7630 if (the_ins.operands[n].b_iadd)
31302357
AS		 7631 printf ("Iadd: '%.*s',",
7632 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7633 the_ins.operands[n].b_iadd);
7634 putchar ('\n');
252b5132
RH		 7635 }
7636 }
7637 m68k_ip_end ();
7638 return 0;
7639}
7640
31302357
AS		 7641int
7642is_label (char *str)
252b5132
RH		 7643{
7644 while (*str == ' ')
7645 str++;
7646 while (*str && *str != ' ')
7647 str++;
7648 if (str[-1] == ':' || str[1] == '=')
7649 return 1;
7650 return 0;
7651}
7652
7653#endif
7654
7655/* Possible states for relaxation:
7656
7657 0 0 branch offset byte (bra, etc)
7658 0 1 word
7659 0 2 long
7660
7661 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7662 1 1 word
7663 1 2 long
7664
7665 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7666 2 1 word-long
7667 2 2 long-word
7668 2 3 long-long
7669
7670 */
7671
7672/* We have no need to default values of symbols. */
7673
252b5132 7674symbolS *
31302357 7675md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7676{
7677 return 0;
7678}
7679
7680/* Round up a section size to the appropriate boundary. */
7681valueT
31302357 7682md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7683{
7684#ifdef OBJ_AOUT
252b5132
RH		 7685 /* For a.out, force the section size to be aligned. If we don't do
7686 this, BFD will align it for us, but it will not write out the
7687 final bytes of the section. This may be a bug in BFD, but it is
7688 easier to fix it here since that is how the other a.out targets
7689 work. */
7690 int align;
7691
7692 align = bfd_get_section_alignment (stdoutput, segment);
7693 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7694#endif
7695
7696 return size;
7697}
7698
7699/* Exactly what point is a PC-relative offset relative TO?
7700 On the 68k, it is relative to the address of the first extension
7701 word. The difference between the addresses of the offset and the
92774660 7702 first extension word is stored in fx_pcrel_adjust. */
252b5132 7703long
31302357 7704md_pcrel_from (fixS *fixP)
252b5132
RH		 7705{
7706 int adjust;
7707
8390138c
AS		 7708 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7709 sign extend the value here. */
7710 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7711 if (adjust == 64)
7712 adjust = -1;
7713 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7714}
7715
0d96863f 7716#ifdef OBJ_ELF
8a104df9 7717void
31302357 7718m68k_elf_final_processing (void)
0d96863f 7719{
266abb8f
NS		 7720 unsigned flags = 0;
7721
238d258f 7722 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7723 flags |= EF_M68K_CFV4E;
7724 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7725 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7726 flags |= EF_M68K_CPU32;
7727 else if (cpu_of_arch (current_architecture) & fido_a)
7728 flags |= EF_M68K_FIDO;
8a104df9
KH		 7729 else if ((cpu_of_arch (current_architecture) & m68000up)
7730 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7731 flags |= EF_M68K_M68000;
7732
7733 if (current_architecture & mcfisa_a)
7734 {
0b2e31dc
NS		 7735 static const unsigned isa_features[][2] =
7736 {
9a2e615a 7737 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7738 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7739 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7740 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7741 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7742 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
0b2e31dc
NS		 7743 {0,0},
7744 };
7745 static const unsigned mac_features[][2] =
7746 {
c694fd50
KH		 7747 {EF_M68K_CF_MAC, mcfmac},
7748 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7749 {0,0},
7750 };
7751 unsigned ix;
7752 unsigned pattern;
266abb8f 7753
0b2e31dc 7754 pattern = (current_architecture
9a2e615a 7755 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7756 for (ix = 0; isa_features[ix][1]; ix++)
7757 {
7758 if (pattern == isa_features[ix][1])
7759 {
7760 flags |= isa_features[ix][0];
7761 break;
7762 }
7763 }
7764 if (!isa_features[ix][1])
7765 {
7766 cf_bad:
7767 as_warn (_("Not a defined coldfire architecture"));
7768 }
7769 else
7770 {
7771 if (current_architecture & cfloat)
c694fd50 7772 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7773
0b2e31dc
NS		 7774 pattern = current_architecture & (mcfmac|mcfemac);
7775 if (pattern)
7776 {
7777 for (ix = 0; mac_features[ix][1]; ix++)
7778 {
7779 if (pattern == mac_features[ix][1])
7780 {
7781 flags |= mac_features[ix][0];
7782 break;
7783 }
7784 }
7785 if (!mac_features[ix][1])
7786 goto cf_bad;
7787 }
7788 }
266abb8f
NS		 7789 }
7790 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f
CM		 7791}
7792#endif
c04898f8
AS		 7793
7794int
1df69f4f 7795tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 7796{
7797 unsigned int regnum;
7798 static const char *const regnames[] =
7799 {
7800 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7801 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7802 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7803 "pc"
7804 };
7805
7806 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7807 if (strcmp (regname, regnames[regnum]) == 0)
7808 return regnum;
7809
7810 return -1;
7811}
7812
7813void
7814tc_m68k_frame_initial_instructions (void)
7815{
7816 static int sp_regno = -1;
7817
7818 if (sp_regno < 0)
7819 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7820
7821 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7822 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7823}
GDB Binutils - Deliverables
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