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Added h8300xray target
[deliverable/binutils-gdb.git] / gas / config / tc-m68kmote.c
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01170860 1/* tc-m68kmote.c All the m68020 specific stuff in one convenient, huge,
20ec2f6c 2 slow to compile, easy to find file.
01170860 3 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
a39116f1
RP		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20ec2f6c 20
01170860 21#define MRI
20ec2f6c
SC		 22#include <ctype.h>
23
24#include "as.h"
25#include "bfd.h"
26#include "obstack.h"
27
a39116f1 28/* note that this file includes real declarations and thus can only be included by one source file per executable. */
20ec2f6c
SC		 29#include "opcode/m68k.h"
30#ifdef TE_SUN
31/* This variable contains the value to write out at the beginning of
32 the a.out file. The 2<<16 means that this is a 68020 file instead
33 of an old-style 68000 file */
34
35long omagic = 2<<16|OMAGIC; /* Magic byte for header file */
36#else
37long omagic = OMAGIC;
38#endif
39
40/* This array holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful */
42const char comment_chars[] = "|";
43
44/* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47/* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50/* Also note that comments like this one will always work. */
51#ifdef MRI
52const char line_comment_chars[] = "*";
53#else
54const char line_comment_chars[] = "#";
55#endif
56
ed90b995
SC		 57#define NO_RELOC 0
58
20ec2f6c
SC		 59/* Chars that can be used to separate mant from exp in floating point nums */
60const char EXP_CHARS[] = "eE";
61
62/* Chars that mean this number is a floating point constant */
63/* As in 0f12.456 */
64/* or 0d1.2345e12 */
65
66const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
67
68/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
69 changed in read.c . Ideally it shouldn't have to know about it at all,
70 but nothing is ideal around here.
a39116f1 71 */
20ec2f6c
SC		 72
73int md_reloc_size = 8; /* Size of relocation record */
74
75/* Its an arbitrary name: This means I don't approve of it */
76/* See flames below */
77static struct obstack robyn;
78
79#define TAB(x,y) (((x)<<2)+(y))
80#define TABTYPE(xy) ((xy) >> 2)
81#define BYTE 0
82#define SHORT 1
83#define LONG 2
84#define SZ_UNDEF 3
85
86#define BRANCH 1
87#define FBRANCH 2
88#define PCREL 3
89#define BCC68000 4
90#define DBCC 5
91#define PCLEA 6
92
93/* Operands we can parse: (And associated modes)
a39116f1
RP		 94
95 numb: 8 bit num
96 numw: 16 bit num
97 numl: 32 bit num
98 dreg: data reg 0-7
99 reg: address or data register
100 areg: address register
101 apc: address register, PC, ZPC or empty string
102 num: 16 or 32 bit num
103 num2: like num
104 sz: w or l if omitted, l assumed
105 scale: 1 2 4 or 8 if omitted, 1 assumed
106
107 7.4 IMMED #num --> NUM
108 0.? DREG dreg --> dreg
109 1.? AREG areg --> areg
110 2.? AINDR areg@ --> *(areg)
111 3.? AINC areg@+ --> *(areg++)
112 4.? ADEC areg@- --> *(--areg)
113 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
114 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
115 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
116 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
117 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
118 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
119 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
120 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
121 7.0 ABSL num:sz --> *(num)
122 num --> *(num) (sz L assumed)
123 *** MSCR otherreg --> Magic
124 With -l option
125 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
126
127 examples:
128 #foo #0x35 #12
129 d2
130 a4
131 a3@
132 a5@+
133 a6@-
134 a2@(12) pc@(14)
135 a1@(5,d2:w:1) @(45,d6:l:4)
136 pc@(a2) @(d4)
137 etc . . .
138
139
140 #name@(numw) -->turn into PC rel mode
141 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
142
143 */
20ec2f6c
SC		 144
145enum operand_type {
542e1629
RP		 146 IMMED = 1,
147 DREG,
148 AREG,
149 AINDR,
150 ADEC,
151 AINC,
152 AOFF,
153 AINDX,
154 APODX,
155 AMIND,
156 APRDX,
157 ABSL,
158 MSCR,
159 REGLST,
20ec2f6c
SC		 160};
161
162
163struct m68k_exp {
542e1629
RP		 164 char *e_beg;
165 char *e_end;
166 expressionS e_exp;
167 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
20ec2f6c
SC		 168};
169
170/* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
171 8-15==addr reg for operands that take both types */
172
173enum _register {
542e1629
RP		 174 DATA = 1, /* 1- 8 == data registers 0-7 */
175 DATA0 = DATA,
176 DATA1,
177 DATA2,
178 DATA3,
179 DATA4,
180 DATA5,
181 DATA6,
182 DATA7,
183
184 ADDR,
185 ADDR0 = ADDR,
186 ADDR1,
187 ADDR2,
188 ADDR3,
189 ADDR4,
190 ADDR5,
191 ADDR6,
192 ADDR7,
193
194 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
195 /* I think. . . */
196
197 SP = ADDR7,
198
199 FPREG, /* Eight FP registers */
200 FP0 = FPREG,
201 FP1,
202 FP2,
203 FP3,
204 FP4,
205 FP5,
206 FP6,
207 FP7,
208 COPNUM = (FPREG+8), /* Co-processor #1-#8 */
209 COP0 = COPNUM,
210 COP1,
211 COP2,
212 COP3,
213 COP4,
214 COP5,
215 COP6,
216 COP7,
217 PC, /* Program counter */
218 ZPC, /* Hack for Program space, but 0 addressing */
219 SR, /* Status Reg */
220 CCR, /* Condition code Reg */
221
222 /* These have to be in order for the movec instruction to work. */
223 USP, /* User Stack Pointer */
224 ISP, /* Interrupt stack pointer */
225 SFC,
226 DFC,
227 CACR,
228 VBR,
229 CAAR,
230 MSP,
231 ITT0,
232 ITT1,
233 DTT0,
234 DTT1,
235 MMUSR,
236 TC,
237 SRP,
238 URP,
239 /* end of movec ordering constraints */
240
241 FPI,
242 FPS,
243 FPC,
244
245 DRP,
246 CRP,
247 CAL,
248 VAL,
249 SCC,
250 AC,
251 BAD,
252 BAD0 = BAD,
253 BAD1,
254 BAD2,
255 BAD3,
256 BAD4,
257 BAD5,
258 BAD6,
259 BAD7,
260 BAC,
261 BAC0 = BAC,
262 BAC1,
263 BAC2,
264 BAC3,
265 BAC4,
266 BAC5,
267 BAC6,
268 BAC7,
269 PSR,
270 PCSR,
271
272 IC, /* instruction cache token */
273 DC, /* data cache token */
274 NC, /* no cache token */
275 BC, /* both caches token */
276
20ec2f6c
SC		 277};
278
279/* Internal form of an operand. */
280struct m68k_op {
542e1629
RP		 281 char *error; /* Couldn't parse it */
282 enum operand_type mode; /* What mode this instruction is in. */
283 enum _register reg; /* Base register */
284 struct m68k_exp *con1;
285 int ireg; /* Index register */
286 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
287 int imul; /* Multipy ireg by this (1,2,4,or 8) */
288 struct m68k_exp *con2;
20ec2f6c
SC		 289};
290
291/* internal form of a 68020 instruction */
292struct m68k_it {
542e1629
RP		 293 char *error;
294 char *args; /* list of opcode info */
295 int numargs;
296
297 int numo; /* Number of shorts in opcode */
298 short opcode[11];
299
300 struct m68k_op operands[6];
301
302 int nexp; /* number of exprs in use */
303 struct m68k_exp exprs[4];
304
305 int nfrag; /* Number of frags we have to produce */
306 struct {
307 int fragoff; /* Where in the current opcode[] the frag ends */
308 symbolS *fadd;
309 long foff;
310 int fragty;
311 } fragb[4];
312
313 int nrel; /* Num of reloc strucs in use */
314 struct {
315 int n;
316 symbolS *add,
317 *sub;
318 long off;
319 char wid;
320 char pcrel;
321 } reloc[5]; /* Five is enough??? */
20ec2f6c
SC		 322};
323
324#define cpu_of_arch(x) ((x) & m68000up)
325#define float_of_arch(x) ((x) & mfloat)
326#define mmu_of_arch(x) ((x) & mmmu)
327
328static struct m68k_it the_ins; /* the instruction being assembled */
329
330/* Macros for adding things to the m68k_it struct */
331
332#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
333
334/* Like addword, but goes BEFORE general operands */
335#define insop(w) {int z;\
a39116f1
RP		 336 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
337 the_ins.opcode[z]=the_ins.opcode[z-1];\
338 for(z=0;z<the_ins.nrel;z++)\
339 the_ins.reloc[z].n+=2;\
340 the_ins.opcode[opcode->m_codenum]=w;\
341 the_ins.numo++;\
542e1629 342 }
20ec2f6c
SC		 343
344
345#define add_exp(beg,end) (\
a39116f1
RP		 346 the_ins.exprs[the_ins.nexp].e_beg=beg,\
347 the_ins.exprs[the_ins.nexp].e_end=end,\
348 &the_ins.exprs[the_ins.nexp++]\
349 )
20ec2f6c
SC		 350
351
352/* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
353#define add_fix(width,exp,pc_rel) {\
a39116f1
RP		 354 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
355 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
356 the_ins.reloc[the_ins.nrel].add=adds((exp));\
357 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
358 the_ins.reloc[the_ins.nrel].off=offs((exp));\
359 the_ins.reloc[the_ins.nrel].wid=width;\
360 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
542e1629 361 }
20ec2f6c
SC		 362
363#define add_frag(add,off,type) {\
a39116f1
RP		 364 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
365 the_ins.fragb[the_ins.nfrag].fadd=add;\
366 the_ins.fragb[the_ins.nfrag].foff=off;\
367 the_ins.fragb[the_ins.nfrag++].fragty=type;\
542e1629 368 }
20ec2f6c
SC		 369
370#define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
371
372#define seg(exp) ((exp)->e_exp.X_seg)
373#define adds(exp) ((exp)->e_exp.X_add_symbol)
374#define subs(exp) ((exp)->e_exp.X_subtract_symbol)
375#define offs(exp) ((exp)->e_exp.X_add_number)
376
377
378struct m68k_incant {
542e1629
RP		 379 char *m_operands;
380 unsigned long m_opcode;
381 short m_opnum;
382 short m_codenum;
383 enum m68k_architecture m_arch;
384 struct m68k_incant *m_next;
20ec2f6c
SC		 385};
386
387#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
388#define gettwo(x) (((x)->m_opcode)&0xffff)
389
390
a87b3269 391#if __STDC__ == 1
20ec2f6c
SC		 392
393static char *crack_operand(char *str, struct m68k_op *opP);
394static int get_num(struct m68k_exp *exp, int ok);
395static int get_regs(int i, char *str, struct m68k_op *opP);
396static int reverse_16_bits(int in);
397static int reverse_8_bits(int in);
398static int try_index(char **s, struct m68k_op *opP);
399static void install_gen_operand(int mode, int val);
400static void install_operand(int mode, int val);
401static void s_bss(void);
402static void s_data1(void);
403static void s_data2(void);
404static void s_even(void);
405static void s_proc(void);
406
a87b3269 407#else /* not __STDC__ */
20ec2f6c
SC		 408
409static char *crack_operand();
410static int get_num();
411static int get_regs();
412static int reverse_16_bits();
413static int reverse_8_bits();
414static int try_index();
415static void install_gen_operand();
416static void install_operand();
417static void s_bss();
418static void s_data1();
419static void s_data2();
420static void s_even();
421static void s_proc();
422
a87b3269 423#endif /* not __STDC__ */
20ec2f6c 424
86582e8d 425static enum m68k_architecture current_architecture = _m68k_undef;
20ec2f6c
SC		 426
427/* BCC68000 is for patching in an extra jmp instruction for long offsets
428 on the 68000. The 68000 doesn't support long branches with branchs */
429
430/* This table desribes how you change sizes for the various types of variable
431 size expressions. This version only supports two kinds. */
432
433/* Note that calls to frag_var need to specify the maximum expansion needed */
434/* This is currently 10 bytes for DBCC */
435
436/* The fields are:
a39116f1
RP		 437 How far Forward this mode will reach:
438 How far Backward this mode will reach:
439 How many bytes this mode will add to the size of the frag
440 Which mode to go to if the offset won't fit in this one
441 */
20ec2f6c 442const relax_typeS
a39116f1 443 md_relax_table[] = {
542e1629
RP		 444 { 1, 1, 0, 0 }, /* First entries aren't used */
445 { 1, 1, 0, 0 }, /* For no good reason except */
446 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
447 { 1, 1, 0, 0 },
448
449 { (127), (-128), 0, TAB(BRANCH,SHORT)},
450 { (32767), (-32768), 2, TAB(BRANCH,LONG) },
451 { 0, 0, 4, 0 },
452 { 1, 1, 0, 0 },
453
454 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
455 { (32767), (-32768), 2, TAB(FBRANCH,LONG)},
456 { 0, 0, 4, 0 },
457 { 1, 1, 0, 0 },
458
459 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
460 { (32767), (-32768), 2, TAB(PCREL,LONG)},
461 { 0, 0, 4, 0 },
462 { 1, 1, 0, 0 },
463
464 { (127), (-128), 0, TAB(BCC68000,SHORT)},
465 { (32767), (-32768), 2, TAB(BCC68000,LONG) },
466 { 0, 0, 6, 0 }, /* jmp long space */
467 { 1, 1, 0, 0 },
468
469 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
470 { (32767), (-32768), 2, TAB(DBCC,LONG) },
471 { 0, 0, 10, 0 }, /* bra/jmp long space */
472 { 1, 1, 0, 0 },
473
474 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
475 { 32767, -32768, 2, TAB(PCLEA,LONG) },
476 { 0, 0, 6, 0 },
477 { 1, 1, 0, 0 },
478
479 };
20ec2f6c
SC		 480
481/* These are the machine dependent pseudo-ops. These are included so
482 the assembler can work on the output from the SUN C compiler, which
483 generates these.
a39116f1 484 */
20ec2f6c
SC		 485
486/* This table describes all the machine specific pseudo-ops the assembler
487 has to support. The fields are:
a39116f1
RP		 488 pseudo-op name without dot
489 function to call to execute this pseudo-op
490 Integer arg to pass to the function
491 */
20ec2f6c
SC		 492#ifdef MRI
493
494void cons();
495void s_sect();
496void float_cons();
497void s_align_bytes();
498void s_chip();
499void s_ds();
500void s_dcb();
501void s_dc();
502const pseudo_typeS md_pseudo_table[] = {
542e1629
RP		 503 { "xdef", s_globl, 0 },
504 { "sect", s_sect, 0 },
505 { "dc", s_dc, 2 },
506 { "dc.d", float_cons, 'd' },
507 { "dc.s", float_cons, 'f' },
508 { "dc.l", s_dc, 4 },
509 { "dc.w", s_dc, 2 },
510 { "dc.b", s_dc, 1 },
511 { "comline", s_ds, 1 },
512 { "ds.b", s_ds, 1 },
513 { "ds.w", s_ds, 2 },
514 { "ds", s_ds, 2 },
515 { "ds.l", s_ds, 4 },
516 { "ds.d", s_ds, 8 },
517 { "ds.s", s_ds, 4 },
518 { "dcb", s_dcb, 2 },
519 { "dcb.b", s_dcb, 1 },
520 { "dcb.w", s_dcb, 2 },
521 { "dcb.l", s_dcb, 4 },
522 { "xcom", s_comm, 0 },
523 { "align", s_align_bytes, 0 },
524 { "chip", s_chip, 0 },
525 { 0, 0, 0 }
20ec2f6c
SC		 526};
527#else
528
529const pseudo_typeS md_pseudo_table[] = {
542e1629
RP		 530 { "data1", s_data1, 0 },
531 { "data2", s_data2, 0 },
532 { "bss", s_bss, 0 },
533 { "even", s_even, 0 },
534 { "skip", s_space, 0 },
535 { "proc", s_proc, 0 },
536 { 0, 0, 0 }
20ec2f6c
SC		 537}
538
539
540
541
542#endif
543
544/* #define isbyte(x) ((x)>=-128 && (x)<=127) */
545/* #define isword(x) ((x)>=-32768 && (x)<=32767) */
546
547#define issbyte(x) ((x)>=-128 && (x)<=127)
548#define isubyte(x) ((x)>=0 && (x)<=255)
549#define issword(x) ((x)>=-32768 && (x)<=32767)
550#define isuword(x) ((x)>=0 && (x)<=65535)
542e1629 551
20ec2f6c
SC		 552#define isbyte(x) ((x)>=-128 && (x)<=255)
553#define isword(x) ((x)>=-32768 && (x)<=65535)
554#define islong(x) (1)
542e1629
RP		 555
556extern char *input_line_pointer;
20ec2f6c
SC		 557
558enum {
542e1629
RP		 559 FAIL = 0,
560 OK = 1,
20ec2f6c
SC		 561};
562
563/* JF these tables here are for speed at the expense of size */
564/* You can replace them with the #if 0 versions if you really
565 need space and don't mind it running a bit slower */
566
567static char mklower_table[256];
568#define mklower(c) (mklower_table[(unsigned char)(c)])
542e1629 569static char notend_table[256];
20ec2f6c
SC		 570static char alt_notend_table[256];
571#define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
a39116f1 572 alt_notend_table[(unsigned char)(s[1])])))
20ec2f6c
SC		 573
574#if 0
575#define mklower(c) (isupper(c) ? tolower(c) : c)
576#endif
542e1629 577
20ec2f6c
SC		 578#define ISSPACE(x) ((x) == ' ' || (x) == '\t')
579#ifdef MRI
580#define MULTIPLIER '*'
581#define SIZER '.'
582#else
583#define MULTIPLIER ':'
584#define SIZER ':'
585#endif
542e1629
RP		 586
587
588/* JF modified this to handle cases where the first part of a symbol name
589 looks like a register */
590
591/*
592 * m68k_reg_parse() := if it looks like a register, return it's token &
593 * advance the pointer.
594 */
595
596enum _register m68k_reg_parse(ccp)
20ec2f6c
SC		 597register char **ccp;
598{
599#ifndef MAX_REG_NAME_LEN
600#define MAX_REG_NAME_LEN (6)
601#endif /* MAX_REG_NAME_LEN */
542e1629
RP		 602 register char c[MAX_REG_NAME_LEN];
603 char *p, *q;
604 register int n = 0,
605 ret = FAIL;
606
607 c[0] = mklower(ccp[0][0]);
20ec2f6c 608#ifdef REGISTER_PREFIX
542e1629
RP		 609 if (c[0] != REGISTER_PREFIX) {
610 return(FAIL);
611 } /* need prefix */
20ec2f6c 612#endif
542e1629
RP		 613
614 for (p = c, q = ccp[0]; p < c + MAX_REG_NAME_LEN; ++p, ++q)
615 {
616 if (*q == 0)
617 {
618 *p = 0;
619 break;
620 }
621 else
622 *p = mklower(*q);
623 } /* downcase */
624
625 switch(c[0]) {
626 case 'a':
627 if(c[1]>='0' && c[1]<='7') {
628 n=2;
629 ret=ADDR+c[1]-'0';
630 }
20ec2f6c 631#ifndef NO_68851
542e1629
RP		 632 else if (c[1] == 'c') {
633 n = 2;
634 ret = AC;
635 }
20ec2f6c 636#endif
542e1629 637 break;
20ec2f6c 638#ifndef NO_68851
542e1629
RP		 639 case 'b':
640 if (c[1] == 'a') {
641 if (c[2] == 'd') {
642 if (c[3] >= '0' && c[3] <= '7') {
643 n = 4;
644 ret = BAD + c[3] - '0';
645 }
646 } /* BAD */
647 if (c[2] == 'c') {
648 if (c[3] >= '0' && c[3] <= '7') {
649 n = 4;
650 ret = BAC + c[3] - '0';
651 }
652 } /* BAC */
653 } else if (c[1] == 'c') {
654 n = 2;
655 ret = BC;
656 } /* BC */
657 break;
20ec2f6c 658#endif
542e1629 659 case 'c':
20ec2f6c 660#ifndef NO_68851
542e1629
RP		 661 if (c[1] == 'a' && c[2] == 'l') {
662 n = 3;
663 ret = CAL;
664 } else
20ec2f6c 665#endif
542e1629
RP		 666 /* This supports both CCR and CC as the ccr reg. */
667 if(c[1]=='c' && c[2]=='r') {
668 n=3;
669 ret = CCR;
670 } else if(c[1]=='c') {
671 n=2;
672 ret = CCR;
673 } else if(c[1]=='a' && (c[2]=='a' || c[2]=='c') && c[3]=='r') {
674 n=4;
675 ret = c[2]=='a' ? CAAR : CACR;
676 }
20ec2f6c 677#ifndef NO_68851
542e1629
RP		 678 else if (c[1] == 'r' && c[2] == 'p') {
679 n = 3;
680 ret = (CRP);
681 }
20ec2f6c 682#endif
542e1629
RP		 683 break;
684 case 'd':
685 if (c[1] >= '0' && c[1] <= '7') {
686 n = 2;
687 ret = DATA + c[1] - '0';
688 } else if (c[1] == 'f' && c[2] == 'c') {
689 n = 3;
690 ret = DFC;
691 } else if (c[1] == 'c') {
692 n = 2;
693 ret = DC;
694 } else if (c[1] == 't' && c[2] == 't') {
695 if ('0' <= c[3] && c[3] <= '1') {
696 n = 4;
697 ret = DTT0 + (c[3] - '0');
698 } /* DTT[01] */
699 }
20ec2f6c 700#ifndef NO_68851
542e1629
RP		 701 else if (c[1] == 'r' && c[2] == 'p') {
702 n = 3;
703 ret = (DRP);
704 }
20ec2f6c 705#endif
542e1629
RP		 706 break;
707 case 'f':
708 if(c[1]=='p') {
709 if(c[2]>='0' && c[2]<='7') {
710 n=3;
711 ret = FPREG+c[2]-'0';
712 if(c[3]==':')
713 ccp[0][3]=',';
714 } else if(c[2]=='i') {
715 n=3;
716 ret = FPI;
717 } else if(c[2]=='s') {
718 n= (c[3] == 'r' ? 4 : 3);
719 ret = FPS;
720 } else if(c[2]=='c') {
721 n= (c[3] == 'r' ? 4 : 3);
722 ret = FPC;
723 } else if (!isalpha(c[2]) && !isdigit(c[2])) {
724 n = 2;
725 ret = ADDR + 6;
726 }
727
728
729 }
730 break;
731 case 'i':
732 if (c[1] == 's' && c[2] == 'p') {
733 n = 3;
734 ret = ISP;
735 } else if (c[1] == 'c') {
736 n = 2;
737 ret = IC;
738 } else if (c[1] == 't' && c[2] == 't') {
739 if ('0' <= c[3] && c[3] <= '1') {
740 n = 4;
741 ret = ITT0 + (c[3] - '0');
742 } /* ITT[01] */
743 }
744 break;
745 case 'm':
746 if (c[1] == 's' && c[2] == 'p') {
747 n = 3;
748 ret = MSP;
749 } else if (c[1] == 'm' && c[2] == 'u' && c[3] == 's' && c[4] == 'r') {
750 n = 5;
751 ret = MMUSR;
752 }
753 break;
754 case 'n':
755 if (c[1] == 'c') {
756 n = 2;
757 ret = NC;
758 }
759 break;
760 case 'p':
761 if(c[1]=='c') {
20ec2f6c 762#ifndef NO_68851
542e1629
RP		 763 if(c[2] == 's' && c[3]=='r') {
764 n=4;
765 ret = (PCSR);
766 } else
20ec2f6c 767#endif
542e1629
RP		 768 {
769 n=2;
770 ret = PC;
771 }
772 }
20ec2f6c 773#ifndef NO_68851
542e1629
RP		 774 else if (c[1] == 's' && c[2] == 'r') {
775 n = 3;
776 ret = (PSR);
777 }
20ec2f6c 778#endif
542e1629
RP		 779 break;
780 case 's':
20ec2f6c 781#ifndef NO_68851
542e1629
RP		 782 if (c[1] == 'c' && c[2] == 'c') {
783 n = 3;
784 ret = (SCC);
785 } else
20ec2f6c 786#endif
542e1629
RP		 787 if (c[1] == 'r') {
788 if (c[2] == 'p') {
789 n = 3;
790 ret = SRP;
791 } else {
792 n = 2;
793 ret = SR;
794 } /* srp else sr */
795 } else if (c[1] == 'p') {
796 n = 2;
797 ret = SP;
798 } else if (c[1] == 'f' && c[2] == 'c') {
799 n = 3;
800 ret = SFC;
801 }
802 break;
803 case 't':
804 if (c[1] == 'c') {
805 n = 2;
806 ret = TC;
807 }
808 break;
809 case 'u':
810 if (c[1] == 's' && c[2] == 'p') {
811 n=3;
812 ret = USP;
813 } else if (c[1] == 'r' && c[2] == 'p') {
814 n = 3;
815 ret = URP;
816 }
817 break;
818 case 'v':
20ec2f6c 819#ifndef NO_68851
542e1629
RP		 820 if (c[1] == 'a' && c[2] == 'l') {
821 n = 3;
822 ret = (VAL);
823 } else
20ec2f6c 824#endif
542e1629
RP		 825 if(c[1]=='b' && c[2]=='r') {
826 n=3;
827 ret = VBR;
828 }
829 break;
830 case 'z':
831 if(c[1]=='p' && c[2]=='c') {
832 n=3;
833 ret = ZPC;
834 }
835 break;
836 default:
837 break;
20ec2f6c 838 }
542e1629 839 if(n) {
20ec2f6c 840#ifdef REGISTER_PREFIX
542e1629 841 n++;
20ec2f6c 842#endif
542e1629
RP		 843 if(isalnum(ccp[0][n]) || ccp[0][n]=='_')
844 ret=FAIL;
845 else
846 ccp[0]+=n;
847 } else
848 ret = FAIL;
849 return ret;
20ec2f6c
SC		 850}
851
852#define SKIP_WHITE() { str++; if(ISSPACE(*str)) str++;}
853
854#ifdef MRI
855
856
857/* Parse an operand from the text *str into the operand struct *opP. */
858int
a39116f1 859 m68k_ip_op(str,opP)
20ec2f6c
SC		 860char *str;
861register struct m68k_op *opP;
862{
542e1629
RP		 863 char *strend;
864 long i;
865 char *parse_index();
866
867 /* Skip leading blank */
868 if(ISSPACE(*str))
869 str++;
870 if(!*str) {
871 opP->error="Missing operand";
872 return FAIL;
a39116f1 873 }
542e1629
RP		 874 /* *strend = last character of string */
875 for(strend=str;*strend;strend++)
876 ;
877 --strend;
878
879 /* Logic of the parsing switch(*str):
880 case opP->mode =
881 ---- -----------
882 #anything IMMED 1
883 REG AREG or DREG or MSCR 3 or 2 or 13
884 REG- or REG/ REGLST 14
885 (REG) AINDR 4
886 (REG)+ AINC 6
887 (REG,INDX) AINDX 8
888 (EXPR,REG) AOFF 7
889 (EXPR,REG,INDX) AINDX 8
890 -(REG) ADEC 5
891 EXP2(REG) AOFF 7
892 EXP2(REG,INDX) AINDX 8
893 EXP2 ABSL 12
894
895 REG means truth(m68k_reg_parse(&str))
896 INDX means truth(try_index(&str,opP))
897 EXPR means not REG
898 EXP2 means not REG and not '(' and not '-('
899 */
900
901 if(*str=='#') {
902 /* "#<expression>" Immediate mode */
903 str++;
904 opP->con1=add_exp(str,strend);
905 opP->mode=IMMED;
906 return OK;
a39116f1 907 }
542e1629 908
a39116f1 909 i=m68k_reg_parse(&str);
542e1629 910 if (i!=FAIL) {
a39116f1 911 if(*str=='\0') {
542e1629
RP		 912 /* "Rn" Register Direct mode */
913 opP->reg=i;
914 if(i>=DATA+0 && i<=DATA+7)
915 opP->mode=DREG;
916 else if(i>=ADDR+0 && i<=ADDR+7)
917 opP->mode=AREG;
918 else
919 opP->mode=MSCR;
a39116f1 920 return OK;
a39116f1 921 }
542e1629
RP		 922 else if(*str=='/' || *str=='-') {
923 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
924 opP->mode=REGLST;
925 return get_regs(i,str,opP);
926 }
927 else {
928 opP->error="Junk after register name";
929 return FAIL;
930 }
a39116f1 931 }
542e1629
RP		 932
933 if(*str=='(') {
934 str++;
a39116f1 935 i=m68k_reg_parse(&str);
542e1629
RP		 936 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) {
937 /* Can't indirect off non address regs */
938 opP->error="Invalid indirect register";
939 return FAIL;
a39116f1
RP		 940 }
941 if(i!=FAIL) {
542e1629
RP		 942 opP->reg=i;
943 if(*str==')') {
944 str++;
945 if(*str=='\0') {
946 /* "(An)" Address Register Indirect mode */
947 opP->mode=AINDR;
948 return OK;
949 }
950 if(*str=='+') {
951 if(str[1]=='\0') {
952 /* "(An)+" Register Indirect w Postincrement */
953 opP->mode=AINC;
954 return OK;
955 }
956 }
957 opP->error="Junk after indirect";
958 return FAIL;
959 }
960 if(*str==',') {
961 str++;
962 i=try_index(&str,opP);
963 if(i==FAIL) return FAIL;
964 /* "(An,Rn)" Register Indirect with Index mode*/
965 opP->mode=AINDX;
966 return OK;
967 }
968 else {
969 opP->error="Bad indirect syntax";
970 return FAIL;
971 }
a39116f1
RP		 972 }
973 else {
542e1629
RP		 974 /* "(EXPR,..." , a displacement */
975 char *stmp;
976 char *index();
977
978 if(stmp=index(str,',')) {
979 opP->con1=add_exp(str,stmp-1);
980 str=stmp;
981 SKIP_WHITE();
982 i=m68k_reg_parse(&str);
983 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC) {
984 /* Can't indirect off non address regs */
985 opP->error="Invalid indirect register";
986 return FAIL;
987 }
988 if(i!=FAIL) {
989 opP->reg=i;
990 if(*str==')') {
991 /* "(d,An)" Register Indirect w Displacement */
992 opP->mode=AOFF;
993 return OK;
994 }
995 if(*str==',') {
996 str++;
997 i=try_index(&str,opP);
998 if(i==FAIL) return FAIL;
999 /* "(d,An,Rn)" Register Indirect with Index */
1000 opP->mode=AINDX;
1001 return OK;
1002 }
1003 else {
1004 opP->error="Bad indirect syntax";
1005 return FAIL;
1006 }
1007 }
1008 else {
1009 opP->error="Invalid register";
1010 return FAIL;
1011 }
1012 }
1013 else {
1014 opP->error="Missing register for indirect";
1015 return FAIL;
1016 }
a39116f1 1017 }
a39116f1 1018 }
542e1629
RP		 1019
1020 if(*str=='-') {
1021 if(str[1]=='(') {
1022 str = str+2;
1023 i=m68k_reg_parse(&str);
1024 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) {
1025 /* Can't indirect off non address regs */
1026 opP->error="Invalid indirect register";
1027 return FAIL;
1028 }
1029 if(i!=FAIL) {
1030 opP->reg=i;
1031 if(*str==')') {
1032 str++;
1033 if(*str=='\0') {
1034 /* "-(An)" Register Indirect with Predecrement */
1035 opP->mode=ADEC;
1036 return OK;
1037 }
1038 opP->error="Junk after indirect";
1039 return FAIL;
1040 }
1041 opP->error="Bad indirect syntax";
1042 return FAIL;
1043 }
1044 opP->error="Invalid register";
1045 return FAIL;
a39116f1 1046 }
542e1629 1047 /* if '-' but not "-(', do nothing */
a39116f1 1048 }
a39116f1 1049
542e1629
RP		 1050 /* whether *str=='-' or not */
1051 {
1052 /* "EXP2" or "EXP2(REG..." */
1053 char *stmp;
1054 char *index();
1055 if(stmp=index(str,'(')) {
1056 opP->con1=add_exp(str,stmp-1);
1057 str=stmp+1;
1058 i=m68k_reg_parse(&str);
1059 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC) {
1060 /* Can't indirect off non address regs */
1061 opP->error="Invalid indirect register";
1062 return FAIL;
1063 }
1064 if(i!=FAIL) {
1065 opP->reg=i;
1066 if(*str==')') {
1067 /* "d(An)" Register Indirect w Displacement */
1068 opP->mode=AOFF;
1069 return OK;
1070 }
1071 if(*str==',') {
1072 str++;
1073 i=try_index(&str,opP);
1074 if(i==FAIL) return FAIL;
1075 /* "d(An,Rn)" Register Indirect with Index */
1076 opP->mode=AINDX;
1077 return OK;
1078 }
1079 else {
1080 opP->error="Bad indirect syntax";
1081 return FAIL;
1082 }
1083 }
1084 else {
1085 opP->error="Invalid register";
1086 return FAIL;
1087 }
1088 }
1089 else {
1090 /* "EXP2" Absolute */
1091 opP->mode=ABSL;
1092 if(strend[-1]=='.') { /* mode ==foo.[wl] */
1093 switch(*strend) {
1094 case 'w':
1095 case 'W':
1096 opP->isiz=2;
1097 break;
1098 case 'l':
1099 case 'L':
1100 opP->isiz=3;
1101 break;
1102 default:
1103 opP->error="Size spec not .W or .L";
1104 return FAIL;
1105 }
1106 strend-=2;
1107 }
1108 else opP->isiz=0;
1109
1110
1111 opP->con1=add_exp(str,strend);
1112 return OK;
1113 }
1114 }
20ec2f6c
SC		 1115}
1116/* end of m68k_ip_op () */
1117#else
1118/*
1119 * m68k_ip_op := '#' + <anything>
1120 * | <register> + range_sep + get_regs
1121 * ;
1122 *
1123 * range_sep := '/' | '-' ;
1124 *
1125 * SKIP_WHITE := <empty> | ' ' ;
1126 *
1127 */
1128
1129int
a39116f1 1130 m68k_ip_op(str,opP)
20ec2f6c
SC		 1131char *str;
1132register struct m68k_op *opP;
1133{
542e1629
RP		 1134 char *strend;
1135 long i;
1136 char *parse_index();
a39116f1 1137
542e1629
RP		 1138 if (ISSPACE(*str)) {
1139 str++;
1140 } /* Find the beginning of the string */
1141
1142 if(!*str) {
1143 opP->error="Missing operand";
20ec2f6c 1144 return FAIL;
542e1629
RP		 1145 } /* Out of gas */
1146
1147 for(strend = str; *strend; strend++) ;;
1148
1149 --strend;
1150
1151 if(*str=='#') {
1152 str++;
1153 opP->con1=add_exp(str,strend);
1154 opP->mode=IMMED;
1155 return OK;
1156 } /* Guess what: A constant. Shar and enjoy */
1157
1158 i = m68k_reg_parse(&str);
1159
1160 /* is a register, is exactly a register, and is followed by '@' */
1161
1162 if((i==FAIL || *str!='\0') && *str!='@') {
1163 char *stmp;
1164
1165 if(i!=FAIL && (*str=='/' || *str=='-')) {
1166 opP->mode=REGLST;
1167 return(get_regs(i,str,opP));
1168 }
1169 if ((stmp=strchr(str,'@')) != '\0') {
1170 opP->con1=add_exp(str,stmp-1);
1171 if(stmp==strend) {
1172 opP->mode=AINDX;
1173 return(OK);
1174 }
1175
1176 if ((current_architecture & m68020up) == 0) {
1177 return(FAIL);
1178 } /* if target is not a '20 or better */
1179
1180 stmp++;
1181 if(*stmp++!='(' || *strend--!=')') {
1182 opP->error="Malformed operand";
1183 return(FAIL);
1184 }
1185 i=try_index(&stmp,opP);
1186 opP->con2=add_exp(stmp,strend);
1187
1188 if (i == FAIL) {
1189 opP->mode=AMIND;
1190 } else {
1191 opP->mode=APODX;
1192 }
1193 return(OK);
1194 } /* if there's an '@' */
1195 opP->mode = ABSL;
1196 opP->con1 = add_exp(str,strend);
1197 return(OK);
1198 } /* not a register, not exactly a register, or no '@' */
1199
1200 opP->reg=i;
1201
1202 if (*str=='\0') {
1203 if(i>=DATA+0 && i<=DATA+7)
1204 opP->mode=DREG;
1205 else if(i>=ADDR+0 && i<=ADDR+7)
1206 opP->mode=AREG;
1207 else
1208 opP->mode=MSCR;
1209 return OK;
20ec2f6c 1210 }
542e1629
RP		 1211
1212 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) { /* Can't indirect off non address regs */
1213 opP->error="Invalid indirect register";
a39116f1 1214 return FAIL;
20ec2f6c 1215 }
542e1629
RP		 1216 know(*str == '@');
1217
1218 str++;
1219 switch(*str) {
1220 case '\0':
1221 opP->mode=AINDR;
1222 return OK;
1223 case '-':
1224 opP->mode=ADEC;
1225 return OK;
1226 case '+':
1227 opP->mode=AINC;
1228 return OK;
1229 case '(':
1230 str++;
1231 break;
1232 default:
1233 opP->error="Junk after indirect";
1234 return FAIL;
20ec2f6c 1235 }
542e1629
RP		 1236 /* Some kind of indexing involved. Lets find out how bad it is */
1237 i=try_index(&str,opP);
1238 /* Didn't start with an index reg, maybe its offset or offset,reg */
1239 if(i==FAIL) {
1240 char *beg_str;
1241
1242 beg_str=str;
1243 for(i=1;i;) {
1244 switch(*str++) {
1245 case '\0':
1246 opP->error="Missing )";
1247 return FAIL;
1248 case ',': i=0; break;
1249 case '(': i++; break;
1250 case ')': --i; break;
1251 }
1252 }
1253 /* if(str[-3]==':') {
1254 int siz;
1255
1256 switch(str[-2]) {
1257 case 'b':
1258 case 'B':
1259 siz=1;
1260 break;
1261 case 'w':
1262 case 'W':
1263 siz=2;
1264 break;
1265 case 'l':
1266 case 'L':
1267 siz=3;
1268 break;
1269 default:
1270 opP->error="Specified size isn't :w or :l";
1271 return FAIL;
1272 }
1273 opP->con1=add_exp(beg_str,str-4);
1274 opP->con1->e_siz=siz;
1275 } else */
1276 opP->con1=add_exp(beg_str,str-2);
1277 /* Should be offset,reg */
1278 if(str[-1]==',') {
1279 i=try_index(&str,opP);
1280 if(i==FAIL) {
1281 opP->error="Malformed index reg";
1282 return FAIL;
1283 }
1284 }
20ec2f6c 1285 }
542e1629 1286 /* We've now got offset) offset,reg) or reg) */
20ec2f6c 1287
542e1629
RP		 1288 if (*str == '\0') {
1289 /* Th-the-thats all folks */
1290 if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */
1291 else if(opP->ireg == FAIL) opP->mode = AOFF;
1292 else opP->mode = AINDX;
1293 return(OK);
1294 }
1295 /* Next thing had better be another @ */
1296 if(*str!='@' || str[1]!='(') {
1297 opP->error = "junk after indirect";
20ec2f6c 1298 return(FAIL);
542e1629
RP		 1299 }
1300
1301 if ((current_architecture & m68020up) == 0) {
a39116f1 1302 return(FAIL);
542e1629
RP		 1303 } /* if target is not a '20 or better */
1304
1305 str+=2;
1306
1307 if(opP->ireg != FAIL) {
1308 opP->mode = APRDX;
1309
1310 i = try_index(&str, opP);
1311 if (i != FAIL) {
1312 opP->error = "Two index registers! not allowed!";
1313 return(FAIL);
1314 }
1315 } else {
1316 i = try_index(&str, opP);
1317 }
1318
1319 if (i == FAIL) {
1320 char *beg_str;
1321
1322 beg_str = str;
1323
1324 for (i = 1; i; ) {
1325 switch(*str++) {
1326 case '\0':
1327 opP->error="Missing )";
1328 return(FAIL);
1329 case ',': i=0; break;
1330 case '(': i++; break;
1331 case ')': --i; break;
1332 }
1333 }
1334
1335 opP->con2=add_exp(beg_str,str-2);
1336
1337 if (str[-1] == ',') {
1338 if (opP->ireg != FAIL) {
1339 opP->error = "Can't have two index regs";
1340 return(FAIL);
1341 }
1342
1343 i = try_index(&str, opP);
1344
1345 if (i == FAIL) {
1346 opP->error = "malformed index reg";
1347 return(FAIL);
1348 }
1349
1350 opP->mode = APODX;
1351 } else if (opP->ireg != FAIL) {
1352 opP->mode = APRDX;
1353 } else {
1354 opP->mode = AMIND;
1355 }
20ec2f6c 1356 } else {
542e1629
RP		 1357 opP->mode = APODX;
1358 }
1359
1360 if(*str!='\0') {
1361 opP->error="Junk after indirect";
1362 return FAIL;
20ec2f6c 1363 }
542e1629 1364 return(OK);
20ec2f6c
SC		 1365} /* m68k_ip_op() */
1366#endif
1367/*
1368 *
1369 * try_index := data_or_address_register + ')' + SKIP_W
1370 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
1371 *
1372 * multiplier := <empty>
1373 * | ':' + multiplier_number
1374 * ;
1375 *
1376 * multiplier_number := '1' | '2' | '4' | '8' ;
1377 *
1378 * size_spec := 'l' | 'L' | 'w' | 'W' ;
1379 *
1380 * SKIP_W := <empty> | ' ' ;
1381 *
1382 */
1383
1384static int try_index(s,opP)
542e1629
RP		 1385char **s;
1386struct m68k_op *opP;
20ec2f6c 1387{
542e1629
RP		 1388 register int i;
1389 char *ss;
20ec2f6c 1390#define SKIP_W() { ss++; if (ISSPACE(*ss)) ss++;}
542e1629
RP		 1391
1392 ss= *s;
1393 /* SKIP_W(); */
1394 i=m68k_reg_parse(&ss);
1395 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
1396 *s=ss;
1397 return FAIL;
1398 }
1399 opP->ireg=i;
1400 /* SKIP_W(); */
1401 if(*ss==')') {
1402 opP->isiz=0;
1403 opP->imul=1;
1404 SKIP_W();
1405 *s=ss;
1406 return OK;
1407 }
1408 if(*ss!=SIZER)
1409 {
1410 opP->error="Missing : in index register";
1411 *s=ss;
1412 return FAIL;
1413 }
20ec2f6c
SC		 1414 SKIP_W();
1415 switch(*ss) {
542e1629
RP		 1416 case 'w':
1417 case 'W':
1418 opP->isiz=2;
1419 break;
1420 case 'l':
1421 case 'L':
1422 opP->isiz=3;
1423 break;
20ec2f6c 1424 default:
542e1629
RP		 1425 opP->error="Index register size spec not :w or :l";
1426 *s=ss;
1427 return FAIL;
1428 }
1429 SKIP_W();
1430 if(*ss==MULTIPLIER)
1431 {
1432 SKIP_W();
1433 switch(*ss) {
1434 case '1':
1435 case '2':
1436 case '4':
1437 case '8':
1438 opP->imul= *ss-'0';
1439 break;
1440 default:
1441 opP->error="index multiplier not 1, 2, 4 or 8";
1442 *s=ss;
1443 return FAIL;
1444 }
1445 SKIP_W();
1446 } else opP->imul=1;
1447 if(*ss!=')') {
1448 opP->error="Missing )";
1449 *s=ss;
1450 return FAIL;
20ec2f6c
SC		 1451 }
1452 SKIP_W();
1453 *s=ss;
542e1629 1454 return OK;
20ec2f6c
SC		 1455} /* try_index() */
1456
1457#ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1458main()
1459{
542e1629
RP		 1460 char buf[128];
1461 struct m68k_op thark;
1462
1463 for(;;) {
1464 if(!gets(buf))
1465 break;
1466 memset(&thark, '\0', sizeof(thark));
1467 if(!m68k_ip_op(buf,&thark)) printf("FAIL:");
1468 if(thark.error)
1469 printf("op1 error %s in %s\n",thark.error,buf);
1470 printf("mode %d, reg %d, ",thark.mode,thark.reg);
1471 if(thark.b_const)
1472 printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const);
1473 printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul);
1474 if(thark.b_iadd)
1475 printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd);
1476 printf("\n");
1477 }
1478 exit(0);
20ec2f6c
SC		 1479}
1480
1481#endif
1482
1483
1484static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table
a39116f1
RP		 1485 NULL means any use before m68k_ip_begin()
1486 will crash */
20ec2f6c
SC		 1487
1488\f
1489/*
1490 * m 6 8 k _ i p ( )
1491 *
1492 * This converts a string into a 68k instruction.
1493 * The string must be a bare single instruction in sun format
1494 * with RMS-style 68020 indirects
1495 * (example: )
1496 *
1497 * It provides some error messages: at most one fatal error message (which
1498 * stops the scan) and at most one warning message for each operand.
1499 * The 68k instruction is returned in exploded form, since we have no
1500 * knowledge of how you parse (or evaluate) your expressions.
1501 * We do however strip off and decode addressing modes and operation
1502 * mnemonic.
1503 *
1504 * This function's value is a string. If it is not "" then an internal
1505 * logic error was found: read this code to assign meaning to the string.
1506 * No argument string should generate such an error string:
1507 * it means a bug in our code, not in the user's text.
1508 *
1509 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1510 * this function.
1511 */
1512
1513/* JF this function no longer returns a useful value. Sorry */
1514void m68k_ip (instring)
542e1629 1515char *instring;
20ec2f6c 1516{
542e1629
RP		 1517 register char *p;
1518 register struct m68k_op *opP;
1519 register struct m68k_incant *opcode, prev_opcode;
1520 register char *s;
1521 register int tmpreg = 0,
1522 baseo = 0,
1523 outro = 0,
1524 nextword;
1525 int siz1,
1526 siz2;
1527 char c;
1528 int losing;
1529 int opsfound;
1530 char *crack_operand();
1531
1532 LITTLENUM_TYPE words[6];
1533 LITTLENUM_TYPE *wordp;
1534
1535 if (ISSPACE(*instring))
1536 instring++; /* skip leading whitespace */
1537
1538 /* Scan up to end of operation-code, which MUST end in end-of-string
1539 or exactly 1 space. */
1540 for (p = instring; *p != '\0'; p++)
1541 if (ISSPACE(*p))
1542 break;
1543
1544
1545 if (p == instring) {
1546 the_ins.error = "No operator";
1547 the_ins.opcode[0] = NULL;
1548 /* the_ins.numo=1; */
1549 return;
1550 }
1551
1552 /* p now points to the end of the opcode name, probably whitespace.
1553 make sure the name is null terminated by clobbering the whitespace,
1554 look it up in the hash table, then fix it back. */
1555 c = *p;
1556 *p = '\0';
20ec2f6c 1557#ifdef MRI
542e1629
RP		 1558 /* Copy from input line to our private buffer, and drop any dots */
1559 {
1560 char our_copy[100];
1561 char *dst = our_copy;
1562 char *src = instring;
1563 while (*src)
1564 {
1565 if (*src != '.')
1566 *dst++ = *src;
1567 src++;
1568 }
1569 *dst = 0;
1570
1571
1572 opcode = (struct m68k_incant *)hash_find (op_hash, our_copy);
1573
1574 /* If no match, try again with a w suffix */
1575 if (!opcode)
1576 {
1577 *dst++ = 'w';
1578 *dst = 0;
1579 opcode = (struct m68k_incant *)hash_find (op_hash, our_copy);
1580 }
1581
1582
1583
1584 }
1585
20ec2f6c 1586#else
542e1629 1587 opcode = (struct m68k_incant *)hash_find (op_hash, instring);
20ec2f6c 1588#endif
542e1629
RP		 1589 *p = c;
1590
1591 if (opcode == NULL) {
1592 the_ins.error = "Unknown opcode";
1593 the_ins.opcode[0] = NULL;
1594 /* the_ins.numo=1; */
1595 return;
1596 }
20ec2f6c 1597
542e1629
RP		 1598 /* found a legitimate opcode, start matching operands */
1599 while (ISSPACE(*p)) ++p;
20ec2f6c 1600
542e1629
RP		 1601 for(opP = &the_ins.operands[0]; *p; opP++) {
1602
1603 p = crack_operand(p, opP);
1604
1605 if (opP->error) {
1606 the_ins.error=opP->error;
1607 return;
1608 }
20ec2f6c 1609 }
20ec2f6c 1610
542e1629
RP		 1611 opsfound = opP - &the_ins.operands[0];
1612
1613 /* This ugly hack is to support the floating pt opcodes in their standard form */
1614 /* Essentially, we fake a first enty of type COP#1 */
1615 if (opcode->m_operands[0]=='I') {
1616 int n;
1617
1618 for(n=opsfound;n>0;--n)
1619 the_ins.operands[n]=the_ins.operands[n-1];
1620
1621 /* memcpy((char *)(&the_ins.operands[1]), (char *)(&the_ins.operands[0]), opsfound*sizeof(the_ins.operands[0])); */
1622 memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
1623 the_ins.operands[0].mode=MSCR;
1624 the_ins.operands[0].reg=COPNUM; /* COP #1 */
1625 opsfound++;
1626 }
1627
1628 /* We've got the operands. Find an opcode that'll accept them */
1629 for (losing = 0; ; ) {
1630 /* if we didn't get the right number of ops,
1631 or we have no common model with this pattern
1632 then reject this pattern. */
1633
1634 if (opsfound != opcode->m_opnum
1635 || ((opcode->m_arch & current_architecture) == 0)) {
a39116f1 1636
542e1629
RP		 1637 ++losing;
1638
1639 } else {
1640 for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
1641 /* Warning: this switch is huge! */
1642 /* I've tried to organize the cases into this order:
1643 non-alpha first, then alpha by letter. lower-case goes directly
1644 before uppercase counterpart. */
1645 /* Code with multiple case ...: gets sorted by the lowest case ...
1646 it belongs to. I hope this makes sense. */
1647 switch(*s) {
1648 case '!':
1649 if (opP->mode == MSCR || opP->mode == IMMED
1650 || opP->mode == DREG || opP->mode == AREG
1651 || opP->mode == AINC || opP->mode == ADEC
1652 || opP->mode == REGLST)
1653 losing++;
1654 break;
1655
1656 case '#':
1657 if(opP->mode!=IMMED)
1658 losing++;
1659 else {
1660 long t;
1661
1662 t=get_num(opP->con1,80);
1663 if(s[1]=='b' && !isbyte(t))
1664 losing++;
1665 else if(s[1]=='w' && !isword(t))
1666 losing++;
1667 }
1668 break;
1669
1670 case '^':
1671 case 'T':
1672 if(opP->mode!=IMMED)
1673 losing++;
1674 break;
1675
1676 case '$':
1677 if(opP->mode==MSCR || opP->mode==AREG ||
1678 opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1679 losing++;
1680 break;
1681
1682 case '%':
1683 if(opP->mode==MSCR || opP->reg==PC ||
1684 opP->reg==ZPC || opP->mode==REGLST)
1685 losing++;
1686 break;
1687
1688
1689 case '&':
1690 if(opP->mode==MSCR || opP->mode==DREG ||
1691 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
1692 opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
1693 losing++;
1694 break;
1695
1696 case '*':
1697 if(opP->mode==MSCR || opP->mode==REGLST)
1698 losing++;
1699 break;
1700
1701 case '+':
1702 if(opP->mode!=AINC)
1703 losing++;
1704 break;
1705
1706 case '-':
1707 if(opP->mode!=ADEC)
1708 losing++;
1709 break;
1710
1711 case '/':
1712 if(opP->mode==MSCR || opP->mode==AREG ||
1713 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
1714 losing++;
1715 break;
1716
1717 case ';':
1718 if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
1719 losing++;
1720 break;
1721
1722 case '?':
1723 if(opP->mode==MSCR || opP->mode==AREG ||
1724 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
1725 opP->reg==ZPC || opP->mode==REGLST)
1726 losing++;
1727 break;
1728
1729 case '@':
1730 if(opP->mode==MSCR || opP->mode==AREG ||
1731 opP->mode==IMMED || opP->mode==REGLST)
1732 losing++;
1733 break;
1734
1735 case '~': /* For now! (JF FOO is this right?) */
1736 if(opP->mode==MSCR || opP->mode==DREG ||
1737 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1738 losing++;
1739 break;
1740
1741 case 'A':
1742 if(opP->mode!=AREG)
1743 losing++;
1744 break;
1745 case 'a':
1746 if (opP->mode != AINDR) {
1747 ++losing;
1748 } /* if not address register indirect */
1749 break;
1750 case 'B': /* FOO */
1751 if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
1752 && instring[1] == 'b'
1753 && instring[2] == 's'
1754 && instring[3] == 'r'))
1755 losing++;
1756 break;
1757
1758 case 'C':
1759 if(opP->mode!=MSCR || opP->reg!=CCR)
1760 losing++;
1761 break;
1762
1763 case 'd': /* FOO This mode is a KLUDGE!! */
1764 if(opP->mode!=AOFF && (opP->mode!=ABSL ||
1765 opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
1766 losing++;
1767 break;
1768
1769 case 'D':
1770 if(opP->mode!=DREG)
1771 losing++;
1772 break;
1773
1774 case 'F':
1775 if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
1776 losing++;
1777 break;
1778
1779 case 'I':
1780 if(opP->mode!=MSCR || opP->reg<COPNUM ||
1781 opP->reg>=COPNUM+7)
1782 losing++;
1783 break;
1784
1785 case 'J':
1786 if (opP->mode != MSCR
1787 || opP->reg < USP
1788 || opP->reg > URP
1789 || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
1790 || (cpu_of_arch(current_architecture) < m68020
1791 && opP->reg != SFC
1792 && opP->reg != DFC
1793 && opP->reg != USP
1794 && opP->reg != VBR) /* 68010's had only these */
1795 || (cpu_of_arch(current_architecture) < m68040
1796 && opP->reg != SFC
1797 && opP->reg != DFC
1798 && opP->reg != USP
1799 && opP->reg != VBR
1800 && opP->reg != CACR
1801 && opP->reg != CAAR
1802 && opP->reg != MSP
1803 && opP->reg != ISP) /* 680[23]0's have only these */
1804 || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
1805 && opP->reg == CAAR)) {
1806 losing++;
1807 } /* doesn't cut it */
1808 break;
1809
1810 case 'k':
1811 if(opP->mode!=IMMED)
1812 losing++;
1813 break;
1814
1815 case 'l':
1816 case 'L':
1817 if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
1818 if(s[1]=='8')
1819 losing++;
1820 else {
1821 opP->mode=REGLST;
1822 opP->reg=1<<(opP->reg-DATA);
1823 }
1824 } else if(opP->mode!=REGLST) {
1825 losing++;
1826 } else if(s[1]=='8' && opP->reg&0x0FFffFF)
1827 losing++;
1828 else if(s[1]=='3' && opP->reg&0x7000000)
1829 losing++;
1830 break;
1831
1832 case 'M':
1833 if(opP->mode!=IMMED)
1834 losing++;
1835 else {
1836 long t;
1837
1838 t=get_num(opP->con1,80);
1839 if(!issbyte(t) || isvar(opP->con1))
1840 losing++;
1841 }
1842 break;
1843
1844 case 'O':
1845 if(opP->mode!=DREG && opP->mode!=IMMED)
1846 losing++;
1847 break;
1848
1849 case 'Q':
1850 if(opP->mode!=IMMED)
1851 losing++;
1852 else {
1853 long t;
1854
1855 t=get_num(opP->con1,80);
1856 if(t<1 || t>8 || isvar(opP->con1))
1857 losing++;
1858 }
1859 break;
1860
1861 case 'R':
1862 if(opP->mode!=DREG && opP->mode!=AREG)
1863 losing++;
1864 break;
1865
1866 case 's':
1867 if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
1868 losing++;
1869 break;
1870
1871 case 'S':
1872 if(opP->mode!=MSCR || opP->reg!=SR)
1873 losing++;
1874 break;
1875
1876 case 'U':
1877 if(opP->mode!=MSCR || opP->reg!=USP)
1878 losing++;
1879 break;
1880
1881 /* JF these are out of order. We could put them
1882 in order if we were willing to put up with
1883 bunches of #ifdef m68851s in the code */
1884#ifndef NO_68851
1885 /* Memory addressing mode used by pflushr */
1886 case '|':
1887 if(opP->mode==MSCR || opP->mode==DREG ||
1888 opP->mode==AREG || opP->mode==REGLST)
1889 losing++;
1890 break;
1891
1892 case 'f':
1893 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1894 losing++;
1895 break;
1896
1897 case 'P':
1898 if (opP->mode != MSCR || (opP->reg != TC && opP->reg != CAL &&
1899 opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1900 losing++;
1901 break;
1902
1903 case 'V':
1904 if (opP->reg != VAL)
1905 losing++;
1906 break;
1907
1908 case 'W':
1909 if (opP->mode != MSCR || (opP->reg != DRP && opP->reg != SRP &&
1910 opP->reg != CRP))
1911 losing++;
1912 break;
1913
1914 case 'X':
1915 if (opP->mode != MSCR ||
1916 (!(opP->reg >= BAD && opP->reg <= BAD+7) &&
1917 !(opP->reg >= BAC && opP->reg <= BAC+7)))
1918 losing++;
1919 break;
1920
1921 case 'Y':
1922 if (opP->reg != PSR)
1923 losing++;
1924 break;
1925
1926 case 'Z':
1927 if (opP->reg != PCSR)
1928 losing++;
1929 break;
1930#endif
1931 case 'c':
1932 if (opP->reg != NC
1933 && opP->reg != IC
1934 && opP->reg != DC
1935 && opP->reg != BC) {
1936 losing++;
1937 } /* not a cache specifier. */
1938 break;
1939
1940 case '_':
1941 if (opP->mode != ABSL) {
1942 ++losing;
1943 } /* not absolute */
1944 break;
1945
1946 default:
1947 as_fatal("Internal error: Operand mode %c unknown in line %s of file \"%s\"",
1948 *s, __LINE__, __FILE__);
1949 } /* switch on type of operand */
1950
1951 if (losing) break;
1952 } /* for each operand */
1953 } /* if immediately wrong */
1954
1955 if (!losing) {
1956 break;
1957 } /* got it. */
1958
1959
1960 if (!opcode->m_next)
1961 {
1962 if ((opcode->m_arch & current_architecture) == 0)
1963 {
1964 the_ins.error = "Opcode not available on architecture specified";
1965 addword(0);
1966
1967 }
1968 else
1969 {
1970 the_ins.error = "instruction/operands mismatch";
1971 }
1972
1973 return;
1974 } /* Fell off the end */
1975 opcode = opcode->m_next;
1976 losing = 0;
1977 }
1978
1979 /* now assemble it */
1980
1981 the_ins.args=opcode->m_operands;
1982 the_ins.numargs=opcode->m_opnum;
1983 the_ins.numo=opcode->m_codenum;
1984 the_ins.opcode[0]=getone(opcode);
1985 the_ins.opcode[1]=gettwo(opcode);
1986
1987 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) {
1988 /* This switch is a doozy.
1989 Watch the first step; its a big one! */
1990 switch(s[0]) {
1991
1992 case '*':
1993 case '~':
a39116f1 1994 case '%':
542e1629
RP		 1995 case ';':
1996 case '@':
1997 case '!':
a39116f1 1998 case '&':
542e1629
RP		 1999 case '$':
2000 case '?':
2001 case '/':
2002#ifndef NO_68851
2003 case '|':
2004#endif
2005 switch(opP->mode) {
2006 case IMMED:
2007 tmpreg=0x3c; /* 7.4 */
2008 if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80);
2009 else nextword=nextword=get_num(opP->con1,0);
2010 if(isvar(opP->con1))
2011 add_fix(s[1],opP->con1,0);
2012 switch(s[1]) {
2013 case 'b':
2014 if(!isbyte(nextword))
2015 opP->error="operand out of range";
2016 addword(nextword);
2017 baseo=0;
2018 break;
2019 case 'w':
2020 if(!isword(nextword))
2021 opP->error="operand out of range";
2022 addword(nextword);
2023 baseo=0;
2024 break;
2025 case 'l':
2026 addword(nextword>>16);
2027 addword(nextword);
2028 baseo=0;
2029 break;
2030
2031 case 'f':
2032 baseo=2;
2033 outro=8;
2034 break;
2035 case 'F':
2036 baseo=4;
2037 outro=11;
2038 break;
2039 case 'x':
2040 baseo=6;
2041 outro=15;
2042 break;
2043 case 'p':
2044 baseo=6;
2045 outro= -1;
2046 break;
2047 default:
2048 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
2049 *s, s[1], __LINE__, __FILE__);
2050 }
2051 if(!baseo)
2052 break;
2053
2054 /* We gotta put out some float */
2055 if(seg(opP->con1)!=SEG_BIG) {
2056 int_to_gen(nextword);
2057 gen_to_words(words,baseo,(long int)outro);
2058 for(wordp=words;baseo--;wordp++)
2059 addword(*wordp);
2060 break;
2061 } /* Its BIG */
2062 if(offs(opP->con1)>0) {
2063 as_warn("Bignum assumed to be binary bit-pattern");
2064 if(offs(opP->con1)>baseo) {
2065 as_warn("Bignum too big for %c format; truncated",s[1]);
2066 offs(opP->con1)=baseo;
2067 }
2068 baseo-=offs(opP->con1);
2069 for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp)
2070 addword(*wordp);
2071 while(baseo--)
2072 addword(0);
2073 break;
2074 }
2075 gen_to_words(words,baseo,(long)outro);
2076 for (wordp=words;baseo--;wordp++)
2077 addword(*wordp);
2078 break;
2079 case DREG:
2080 tmpreg=opP->reg-DATA; /* 0.dreg */
2081 break;
2082 case AREG:
2083 tmpreg=0x08+opP->reg-ADDR; /* 1.areg */
2084 break;
2085 case AINDR:
2086 tmpreg=0x10+opP->reg-ADDR; /* 2.areg */
2087 break;
2088 case ADEC:
2089 tmpreg=0x20+opP->reg-ADDR; /* 4.areg */
2090 break;
2091 case AINC:
2092 tmpreg=0x18+opP->reg-ADDR; /* 3.areg */
2093 break;
2094 case AOFF:
2095
2096 nextword=get_num(opP->con1,80);
2097 /* Force into index mode. Hope this works */
2098
2099 /* We do the first bit for 32-bit displacements,
2100 and the second bit for 16 bit ones. It is
2101 possible that we should make the default be
2102 WORD instead of LONG, but I think that'd
2103 break GCC, so we put up with a little
2104 inefficiency for the sake of working output.
2105 */
2106
2107 if( !issword(nextword)
2108 || ( isvar(opP->con1)
2109 && ( ( opP->con1->e_siz==0
2110 && flagseen['l']==0)
2111 || opP->con1->e_siz==3))) {
2112
2113 if(opP->reg==PC)
2114 tmpreg=0x3B; /* 7.3 */
2115 else
2116 tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2117 if(isvar(opP->con1)) {
2118 if(opP->reg==PC) {
2119 add_frag(adds(opP->con1),
2120 offs(opP->con1),
2121 TAB(PCLEA,SZ_UNDEF));
2122 break;
2123 } else {
2124 addword(0x0170);
2125 add_fix('l',opP->con1,1);
2126 }
2127 } else
2128 addword(0x0170);
2129 addword(nextword>>16);
2130 } else {
2131 if(opP->reg==PC)
2132 tmpreg=0x3A; /* 7.2 */
2133 else
2134 tmpreg=0x28+opP->reg-ADDR; /* 5.areg */
2135
2136 if(isvar(opP->con1)) {
2137 if(opP->reg==PC) {
2138 add_fix('w',opP->con1,1);
2139 } else
2140 add_fix('w',opP->con1,0);
2141 }
2142 }
2143 addword(nextword);
2144 break;
2145
2146 case APODX:
2147 case AMIND:
2148 case APRDX:
2149 know(current_architecture & m68020up);
2150 /* intentional fall-through */
2151 case AINDX:
2152 nextword=0;
2153 baseo=get_num(opP->con1,80);
2154 outro=get_num(opP->con2,80);
2155 /* Figure out the 'addressing mode' */
2156 /* Also turn on the BASE_DISABLE bit, if needed */
2157 if(opP->reg==PC || opP->reg==ZPC) {
2158 tmpreg=0x3b; /* 7.3 */
2159 if(opP->reg==ZPC)
2160 nextword|=0x80;
2161 } else if(opP->reg==FAIL) {
2162 nextword|=0x80;
2163 tmpreg=0x30; /* 6.garbage */
2164 } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2165
2166 siz1= (opP->con1) ? opP->con1->e_siz : 0;
2167 siz2= (opP->con2) ? opP->con2->e_siz : 0;
2168
2169 /* Index register stuff */
2170 if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) {
2171 nextword|=(opP->ireg-DATA)<<12;
2172
2173 if(opP->isiz==0 || opP->isiz==3)
2174 nextword|=0x800;
2175 switch(opP->imul) {
2176 case 1: break;
2177 case 2: nextword|=0x200; break;
2178 case 4: nextword|=0x400; break;
2179 case 8: nextword|=0x600; break;
2180 default: as_fatal("failed sanity check.");
2181 }
2182 /* IF its simple,
2183 GET US OUT OF HERE! */
2184
2185 /* Must be INDEX, with an index
2186 register. Address register
2187 cannot be ZERO-PC, and either
2188 :b was forced, or we know
2189 it will fit */
2190 if( opP->mode==AINDX
2191 && opP->reg!=FAIL
2192 && opP->reg!=ZPC
2193 && ( siz1==1
2194 || ( issbyte(baseo)
2195 && !isvar(opP->con1)))) {
2196 nextword +=baseo&0xff;
2197 addword(nextword);
2198 if(isvar(opP->con1))
2199 add_fix('B',opP->con1,0);
2200 break;
2201 }
2202 } else
2203 nextword|=0x40; /* No index reg */
2204
2205 /* It aint simple */
2206 nextword|=0x100;
2207 /* If the guy specified a width, we assume that
2208 it is wide enough. Maybe it isn't. If so, we lose
2209 */
2210 switch(siz1) {
2211 case 0:
2212 if(isvar(opP->con1) || !issword(baseo)) {
2213 siz1=3;
2214 nextword|=0x30;
2215 } else if(baseo==0)
2216 nextword|=0x10;
2217 else {
2218 nextword|=0x20;
2219 siz1=2;
2220 }
2221 break;
2222 case 1:
2223 as_warn("Byte dispacement won't work. Defaulting to :w");
2224 case 2:
2225 nextword|=0x20;
2226 break;
2227 case 3:
2228 nextword|=0x30;
2229 break;
2230 }
2231
2232 /* Figure out innner displacement stuff */
2233 if(opP->mode!=AINDX) {
2234 switch(siz2) {
2235 case 0:
2236 if(isvar(opP->con2) || !issword(outro)) {
2237 siz2=3;
2238 nextword|=0x3;
2239 } else if(outro==0)
2240 nextword|=0x1;
2241 else {
2242 nextword|=0x2;
2243 siz2=2;
2244 }
2245 break;
2246 case 1:
2247 as_warn("Byte dispacement won't work. Defaulting to :w");
2248 case 2:
2249 nextword|=0x2;
2250 break;
2251 case 3:
2252 nextword|=0x3;
2253 break;
2254 }
2255 if(opP->mode==APODX) nextword|=0x04;
2256 else if(opP->mode==AMIND) nextword|=0x40;
2257 }
2258 addword(nextword);
2259
2260 if(isvar(opP->con1)) {
2261 if(opP->reg==PC || opP->reg==ZPC) {
2262 add_fix(siz1==3 ? 'l' : 'w',opP->con1,1);
2263 opP->con1->e_exp.X_add_number+=6;
2264 } else
2265 add_fix(siz1==3 ? 'l' : 'w',opP->con1,0);
2266 }
2267 if(siz1==3)
2268 addword(baseo>>16);
2269 if(siz1)
2270 addword(baseo);
2271
2272 if(isvar(opP->con2)) {
2273 if(opP->reg==PC || opP->reg==ZPC) {
2274 add_fix(siz2==3 ? 'l' : 'w',opP->con2,1);
2275 opP->con1->e_exp.X_add_number+=6;
2276 } else
2277 add_fix(siz2==3 ? 'l' : 'w',opP->con2,0);
2278 }
2279 if(siz2==3)
2280 addword(outro>>16);
2281 if(siz2)
2282 addword(outro);
2283
2284 break;
2285
2286 case ABSL:
2287 nextword=get_num(opP->con1,80);
2288 switch(opP->con1->e_siz) {
2289 default:
2290 as_warn("Unknown size for absolute reference");
2291 case 0:
2292 if(!isvar(opP->con1) && issword(offs(opP->con1))) {
2293 tmpreg=0x38; /* 7.0 */
2294 addword(nextword);
2295 break;
2296 }
2297 /* Don't generate pc relative code
2298 on 68010 and 68000 */
2299 if(isvar(opP->con1)
2300 && !subs(opP->con1)
2301 && seg(opP->con1) == SEG_TEXT
2302 && now_seg == SEG_TEXT
2303 && cpu_of_arch(current_architecture) < m68020
2304 && !flagseen['S']
2305 && !strchr("~%&$?", s[0])) {
2306 tmpreg=0x3A; /* 7.2 */
2307 add_frag(adds(opP->con1),
2308 offs(opP->con1),
2309 TAB(PCREL,SZ_UNDEF));
2310 break;
2311 }
2312 case 3: /* Fall through into long */
2313 if(isvar(opP->con1))
2314 add_fix('l',opP->con1,0);
2315
2316 tmpreg=0x39; /* 7.1 mode */
2317 addword(nextword>>16);
2318 addword(nextword);
2319 break;
2320
2321 case 2: /* Word */
2322 if(isvar(opP->con1))
2323 add_fix('w',opP->con1,0);
2324
2325 tmpreg=0x38; /* 7.0 mode */
2326 addword(nextword);
2327 break;
2328 }
2329 break;
2330 case MSCR:
2331 default:
2332 as_bad("unknown/incorrect operand");
2333 /* abort(); */
2334 }
2335 install_gen_operand(s[1],tmpreg);
2336 break;
2337
2338 case '#':
2339 case '^':
2340 switch(s[1]) { /* JF: I hate floating point! */
2341 case 'j':
2342 tmpreg=70;
2343 break;
2344 case '8':
2345 tmpreg=20;
2346 break;
2347 case 'C':
2348 tmpreg=50;
2349 break;
2350 case '3':
2351 default:
2352 tmpreg=80;
2353 break;
2354 }
2355 tmpreg=get_num(opP->con1,tmpreg);
2356 if(isvar(opP->con1))
2357 add_fix(s[1],opP->con1,0);
2358 switch(s[1]) {
2359 case 'b': /* Danger: These do no check for
2360 certain types of overflow.
2361 user beware! */
2362 if(!isbyte(tmpreg))
2363 opP->error="out of range";
2364 insop(tmpreg);
2365 if(isvar(opP->con1))
2366 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2367 break;
2368 case 'w':
2369 if(!isword(tmpreg))
2370 opP->error="out of range";
2371 insop(tmpreg);
2372 if(isvar(opP->con1))
2373 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2374 break;
2375 case 'l':
2376 insop(tmpreg); /* Because of the way insop works, we put these two out backwards */
2377 insop(tmpreg>>16);
2378 if(isvar(opP->con1))
2379 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2380 break;
2381 case '3':
2382 tmpreg&=0xFF;
2383 case '8':
2384 case 'C':
2385 install_operand(s[1],tmpreg);
2386 break;
2387 default:
2388 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
2389 }
2390 break;
2391
a39116f1 2392 case '+':
a39116f1 2393 case '-':
a39116f1 2394 case 'A':
a39116f1 2395 case 'a':
542e1629
RP		 2396 install_operand(s[1],opP->reg-ADDR);
2397 break;
2398
2399 case 'B':
2400 tmpreg=get_num(opP->con1,80);
2401 switch(s[1]) {
2402 case 'B':
2403 /* Needs no offsetting */
2404 add_fix('B',opP->con1,1);
2405 break;
2406 case 'W':
2407 /* Offset the displacement to be relative to byte disp location */
2408 opP->con1->e_exp.X_add_number+=2;
2409 add_fix('w',opP->con1,1);
2410 addword(0);
2411 break;
2412 case 'L':
2413 long_branch:
2414 if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */
2415 as_warn("Can't use long branches on 68000/68010");
2416 the_ins.opcode[the_ins.numo-1]|=0xff;
2417 /* Offset the displacement to be relative to byte disp location */
2418 opP->con1->e_exp.X_add_number+=4;
2419 add_fix('l',opP->con1,1);
2420 addword(0);
2421 addword(0);
2422 break;
2423 case 'g':
2424 if(subs(opP->con1)) /* We can't relax it */
2425 goto long_branch;
2426
2427 /* This could either be a symbol, or an
2428 absolute address. No matter, the
2429 frag hacking will finger it out.
2430 Not quite: it can't switch from
2431 BRANCH to BCC68000 for the case
2432 where opnd is absolute (it needs
2433 to use the 68000 hack since no
2434 conditional abs jumps). */
2435 if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1)))
2436 && (the_ins.opcode[0] >= 0x6200)
2437 && (the_ins.opcode[0] <= 0x6f00)) {
2438 add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF));
2439 } else {
2440 add_frag(adds(opP->con1),offs(opP->con1),TAB(BRANCH,SZ_UNDEF));
2441 }
2442 break;
2443 case 'w':
2444 if(isvar(opP->con1)) {
2445 /* check for DBcc instruction */
2446 if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) {
2447 /* size varies if patch */
2448 /* needed for long form */
2449 add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF));
2450 break;
2451 }
2452
2453 /* Don't ask! */
2454 opP->con1->e_exp.X_add_number+=2;
2455 add_fix('w',opP->con1,1);
2456 }
2457 addword(0);
2458 break;
2459 case 'C': /* Fixed size LONG coproc branches */
2460 the_ins.opcode[the_ins.numo-1]|=0x40;
2461 /* Offset the displacement to be relative to byte disp location */
2462 /* Coproc branches don't have a byte disp option, but they are
2463 compatible with the ordinary branches, which do... */
2464 opP->con1->e_exp.X_add_number+=4;
2465 add_fix('l',opP->con1,1);
2466 addword(0);
2467 addword(0);
2468 break;
2469 case 'c': /* Var size Coprocesssor branches */
2470 if(subs(opP->con1)) {
2471 add_fix('l',opP->con1,1);
2472 add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG));
2473 } else if(adds(opP->con1)) {
2474 add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF));
2475 } else {
2476 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2477 the_ins.opcode[the_ins.numo-1]|=0x40;
2478 add_fix('l',opP->con1,1);
2479 addword(0);
2480 addword(4);
2481 }
2482 break;
2483 default:
2484 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2485 s[1], __LINE__, __FILE__);
2486 }
2487 break;
2488
2489 case 'C': /* Ignore it */
2490 break;
2491
2492 case 'd': /* JF this is a kludge */
2493 if(opP->mode==AOFF) {
2494 install_operand('s',opP->reg-ADDR);
2495 } else {
2496 char *tmpP;
2497
2498 tmpP=opP->con1->e_end-2;
2499 opP->con1->e_beg++;
2500 opP->con1->e_end-=4; /* point to the , */
2501 baseo=m68k_reg_parse(&tmpP);
2502 if(baseo<ADDR+0 || baseo>ADDR+7) {
2503 as_bad("Unknown address reg, using A0");
2504 baseo=0;
2505 } else baseo-=ADDR;
2506 install_operand('s',baseo);
2507 }
2508 tmpreg=get_num(opP->con1,80);
2509 if(!issword(tmpreg)) {
2510 as_warn("Expression out of range, using 0");
2511 tmpreg=0;
2512 }
2513 addword(tmpreg);
2514 break;
2515
2516 case 'D':
2517 install_operand(s[1],opP->reg-DATA);
2518 break;
2519
2520 case 'F':
2521 install_operand(s[1],opP->reg-FPREG);
2522 break;
2523
2524 case 'I':
2525 tmpreg=1+opP->reg-COPNUM;
2526 if(tmpreg==8)
2527 tmpreg=0;
2528 install_operand(s[1],tmpreg);
2529 break;
2530
2531 case 'J': /* JF foo */
2532 switch(opP->reg) {
2533 case SFC: tmpreg=0x000; break;
2534 case DFC: tmpreg=0x001; break;
2535 case CACR: tmpreg=0x002; break;
2536 case TC: tmpreg=0x003; break;
2537 case ITT0: tmpreg=0x004; break;
2538 case ITT1: tmpreg=0x005; break;
2539 case DTT0: tmpreg=0x006; break;
2540 case DTT1: tmpreg=0x007; break;
2541
2542 case USP: tmpreg=0x800; break;
2543 case VBR: tmpreg=0x801; break;
2544 case CAAR: tmpreg=0x802; break;
2545 case MSP: tmpreg=0x803; break;
2546 case ISP: tmpreg=0x804; break;
2547 case MMUSR: tmpreg=0x805; break;
2548 case URP: tmpreg=0x806; break;
2549 case SRP: tmpreg=0x807; break;
2550 default:
2551 as_fatal("failed sanity check.");
2552 }
2553 install_operand(s[1],tmpreg);
2554 break;
2555
a39116f1 2556 case 'k':
542e1629
RP		 2557 tmpreg=get_num(opP->con1,55);
2558 install_operand(s[1],tmpreg&0x7f);
2559 break;
2560
a39116f1 2561 case 'l':
542e1629
RP		 2562 tmpreg=opP->reg;
2563 if(s[1]=='w') {
2564 if(tmpreg&0x7FF0000)
2565 as_bad("Floating point register in register list");
2566 insop(reverse_16_bits(tmpreg));
2567 } else {
2568 if(tmpreg&0x700FFFF)
2569 as_bad("Wrong register in floating-point reglist");
2570 install_operand(s[1],reverse_8_bits(tmpreg>>16));
2571 }
2572 break;
2573
a39116f1 2574 case 'L':
542e1629
RP		 2575 tmpreg=opP->reg;
2576 if(s[1]=='w') {
2577 if(tmpreg&0x7FF0000)
2578 as_bad("Floating point register in register list");
2579 insop(tmpreg);
2580 } else if(s[1]=='8') {
2581 if(tmpreg&0x0FFFFFF)
2582 as_bad("incorrect register in reglist");
2583 install_operand(s[1],tmpreg>>24);
2584 } else {
2585 if(tmpreg&0x700FFFF)
2586 as_bad("wrong register in floating-point reglist");
2587 else
2588 install_operand(s[1],tmpreg>>16);
a39116f1 2589 }
542e1629
RP		 2590 break;
2591
a39116f1 2592 case 'M':
542e1629
RP		 2593 install_operand(s[1],get_num(opP->con1,60));
2594 break;
a39116f1 2595
a39116f1 2596 case 'O':
542e1629
RP		 2597 tmpreg= (opP->mode==DREG)
2598 ? 0x20+opP->reg-DATA
2599 : (get_num(opP->con1,40)&0x1F);
2600 install_operand(s[1],tmpreg);
2601 break;
2602
a39116f1 2603 case 'Q':
542e1629
RP		 2604 tmpreg=get_num(opP->con1,10);
2605 if(tmpreg==8)
2606 tmpreg=0;
2607 install_operand(s[1],tmpreg);
2608 break;
a39116f1 2609
a39116f1 2610 case 'R':
542e1629
RP		 2611 /* This depends on the fact that ADDR registers are
2612 eight more than their corresponding DATA regs, so
2613 the result will have the ADDR_REG bit set */
2614 install_operand(s[1],opP->reg-DATA);
2615 break;
2616
a39116f1 2617 case 's':
542e1629
RP		 2618 if(opP->reg==FPI) tmpreg=0x1;
2619 else if(opP->reg==FPS) tmpreg=0x2;
2620 else if(opP->reg==FPC) tmpreg=0x4;
2621 else as_fatal("failed sanity check.");
2622 install_operand(s[1],tmpreg);
2623 break;
2624
2625 case 'S': /* Ignore it */
2626 break;
2627
2628 case 'T':
2629 install_operand(s[1],get_num(opP->con1,30));
2630 break;
2631
2632 case 'U': /* Ignore it */
2633 break;
2634
a39116f1 2635 case 'c':
542e1629
RP		 2636 switch (opP->reg) {
2637 case NC: tmpreg = 0; break;
2638 case DC: tmpreg = 1; break;
2639 case IC: tmpreg = 2; break;
2640 case BC: tmpreg = 3; break;
2641 default:
2642 as_fatal("failed sanity check");
2643 } /* switch on cache token */
2644 install_operand(s[1], tmpreg);
2645 break;
20ec2f6c 2646#ifndef NO_68851
542e1629 2647 /* JF: These are out of order, I fear. */
20ec2f6c 2648 case 'f':
542e1629
RP		 2649 switch (opP->reg) {
2650 case SFC:
2651 tmpreg=0;
2652 break;
2653 case DFC:
2654 tmpreg=1;
2655 break;
2656 default:
2657 as_fatal("failed sanity check.");
a39116f1 2658 }
542e1629 2659 install_operand(s[1],tmpreg);
a39116f1 2660 break;
542e1629
RP		 2661
2662 case 'P':
2663 switch(opP->reg) {
2664 case TC:
2665 tmpreg=0;
2666 break;
2667 case CAL:
2668 tmpreg=4;
2669 break;
2670 case VAL:
2671 tmpreg=5;
2672 break;
2673 case SCC:
2674 tmpreg=6;
2675 break;
2676 case AC:
2677 tmpreg=7;
2678 break;
2679 default:
2680 as_fatal("failed sanity check.");
20ec2f6c 2681 }
542e1629 2682 install_operand(s[1],tmpreg);
20ec2f6c 2683 break;
542e1629
RP		 2684
2685 case 'V':
2686 if (opP->reg == VAL)
2687 break;
2688 as_fatal("failed sanity check.");
2689
2690 case 'W':
2691 switch(opP->reg) {
2692
2693 case DRP:
2694 tmpreg=1;
2695 break;
2696 case SRP:
2697 tmpreg=2;
2698 break;
2699 case CRP:
2700 tmpreg=3;
2701 break;
2702 default:
2703 as_fatal("failed sanity check.");
2704 }
2705 install_operand(s[1],tmpreg);
20ec2f6c 2706 break;
542e1629
RP		 2707
2708 case 'X':
2709 switch (opP->reg) {
2710 case BAD: case BAD+1: case BAD+2: case BAD+3:
2711 case BAD+4: case BAD+5: case BAD+6: case BAD+7:
2712 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2713 break;
2714
2715 case BAC: case BAC+1: case BAC+2: case BAC+3:
2716 case BAC+4: case BAC+5: case BAC+6: case BAC+7:
2717 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2718 break;
2719
2720 default:
2721 as_fatal("failed sanity check.");
2722 }
2723 install_operand(s[1], tmpreg);
20ec2f6c 2724 break;
542e1629
RP		 2725 case 'Y':
2726 know(opP->reg == PSR);
20ec2f6c 2727 break;
542e1629
RP		 2728 case 'Z':
2729 know(opP->reg == PCSR);
20ec2f6c 2730 break;
542e1629
RP		 2731#endif /* m68851 */
2732 case '_':
2733 tmpreg=get_num(opP->con1,80);
2734 install_operand(s[1], tmpreg);
20ec2f6c 2735 break;
542e1629
RP		 2736 default:
2737 as_fatal("Internal error: Operand type %c unknown in line %s of file \"%s\"", s[0], __LINE__, __FILE__);
a39116f1 2738 }
20ec2f6c 2739 }
542e1629
RP		 2740 /* By the time whe get here (FINALLY) the_ins contains the complete
2741 instruction, ready to be emitted. . . */
20ec2f6c
SC		 2742} /* m68k_ip() */
2743
2744/*
2745 * get_regs := '/' + ?
2746 * | '-' + <register>
2747 * | '-' + <register> + ?
2748 * | <empty>
2749 * ;
2750 *
a39116f1 2751
20ec2f6c
SC		 2752 * The idea here must be to scan in a set of registers but I don't
2753 * understand it. Looks awfully sloppy to me but I don't have any doc on
2754 * this format so...
a39116f1 2755
20ec2f6c
SC		 2756 *
2757 *
2758 */
2759
2760static int get_regs(i,str,opP)
542e1629
RP		 2761int i;
2762struct m68k_op *opP;
2763char *str;
20ec2f6c 2764{
542e1629
RP		 2765 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2766 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2767 unsigned long cur_regs = 0;
2768 int reg1,
2769 reg2;
2770
20ec2f6c 2771#define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
a39116f1
RP		 2772else if(x==FPS) cur_regs|=(1<<25);\
2773else if(x==FPC) cur_regs|=(1<<26);\
2774else cur_regs|=(1<<(x-1)); }
542e1629
RP		 2775
2776 reg1=i;
2777 for(;;) {
2778 if(*str=='/') {
2779 ADD_REG(reg1);
2780 str++;
2781 } else if(*str=='-') {
2782 str++;
2783 reg2=m68k_reg_parse(&str);
2784 if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) {
2785 opP->error="unknown register in register list";
2786 return FAIL;
2787 }
2788 while(reg1<=reg2) {
2789 ADD_REG(reg1);
2790 reg1++;
2791 }
2792 if(*str=='\0')
2793 break;
2794 } else if(*str=='\0') {
2795 ADD_REG(reg1);
2796 break;
2797 } else {
2798 opP->error="unknow character in register list";
2799 return FAIL;
2800 }
2801 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2802 if (*str=='/')
2803 str ++;
2804 reg1=m68k_reg_parse(&str);
2805 if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) {
2806 opP->error="unknown register in register list";
2807 return FAIL;
2808 }
a39116f1 2809 }
542e1629
RP		 2810 opP->reg=cur_regs;
2811 return OK;
20ec2f6c
SC		 2812} /* get_regs() */
2813
2814static int reverse_16_bits(in)
542e1629 2815int in;
20ec2f6c 2816{
542e1629
RP		 2817 int out=0;
2818 int n;
2819
2820 static int mask[16] = {
2821 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2822 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2823 };
2824 for(n=0;n<16;n++) {
2825 if(in&mask[n])
2826 out|=mask[15-n];
2827 }
2828 return out;
20ec2f6c
SC		 2829} /* reverse_16_bits() */
2830
2831static int reverse_8_bits(in)
542e1629 2832int in;
20ec2f6c 2833{
542e1629
RP		 2834 int out=0;
2835 int n;
2836
2837 static int mask[8] = {
2838 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2839 };
2840
2841 for(n=0;n<8;n++) {
2842 if(in&mask[n])
2843 out|=mask[7-n];
2844 }
2845 return out;
20ec2f6c
SC		 2846} /* reverse_8_bits() */
2847
2848static void install_operand(mode,val)
542e1629
RP		 2849int mode;
2850int val;
20ec2f6c 2851{
542e1629
RP		 2852 switch(mode) {
2853 case 's':
2854 the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */
2855 break;
2856 case 'd':
2857 the_ins.opcode[0]|=val<<9;
2858 break;
2859 case '1':
2860 the_ins.opcode[1]|=val<<12;
2861 break;
2862 case '2':
2863 the_ins.opcode[1]|=val<<6;
2864 break;
2865 case '3':
2866 the_ins.opcode[1]|=val;
2867 break;
2868 case '4':
2869 the_ins.opcode[2]|=val<<12;
2870 break;
2871 case '5':
2872 the_ins.opcode[2]|=val<<6;
2873 break;
2874 case '6':
2875 /* DANGER! This is a hack to force cas2l and cas2w cmds
2876 to be three words long! */
2877 the_ins.numo++;
2878 the_ins.opcode[2]|=val;
2879 break;
2880 case '7':
2881 the_ins.opcode[1]|=val<<7;
2882 break;
2883 case '8':
2884 the_ins.opcode[1]|=val<<10;
2885 break;
20ec2f6c 2886#ifndef NO_68851
542e1629
RP		 2887 case '9':
2888 the_ins.opcode[1]|=val<<5;
2889 break;
20ec2f6c 2890#endif
542e1629
RP		 2891
2892 case 't':
2893 the_ins.opcode[1]|=(val<<10)|(val<<7);
2894 break;
2895 case 'D':
2896 the_ins.opcode[1]|=(val<<12)|val;
2897 break;
2898 case 'g':
2899 the_ins.opcode[0]|=val=0xff;
2900 break;
2901 case 'i':
2902 the_ins.opcode[0]|=val<<9;
2903 break;
2904 case 'C':
2905 the_ins.opcode[1]|=val;
2906 break;
2907 case 'j':
2908 the_ins.opcode[1]|=val;
2909 the_ins.numo++; /* What a hack */
2910 break;
2911 case 'k':
2912 the_ins.opcode[1]|=val<<4;
2913 break;
2914 case 'b':
2915 case 'w':
2916 case 'l':
2917 break;
2918 case 'e':
2919 the_ins.opcode[0] |= (val << 6);
2920 break;
2921 case 'L':
2922 the_ins.opcode[1] = (val >> 16);
2923 the_ins.opcode[2] = val & 0xffff;
2924 break;
2925 case 'c':
2926 default:
2927 as_fatal("failed sanity check.");
2928 }
20ec2f6c
SC		 2929} /* install_operand() */
2930
2931static void install_gen_operand(mode,val)
542e1629
RP		 2932int mode;
2933int val;
20ec2f6c 2934{
542e1629
RP		 2935 switch(mode) {
2936 case 's':
2937 the_ins.opcode[0]|=val;
2938 break;
2939 case 'd':
2940 /* This is a kludge!!! */
2941 the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3;
2942 break;
2943 case 'b':
2944 case 'w':
2945 case 'l':
2946 case 'f':
2947 case 'F':
2948 case 'x':
2949 case 'p':
2950 the_ins.opcode[0]|=val;
2951 break;
2952 /* more stuff goes here */
2953 default:
2954 as_fatal("failed sanity check.");
2955 }
a39116f1 2956} /* install_gen_operand() */
20ec2f6c 2957
a39116f1
RP		 2958/*
2959 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2960 * then deal with the bitfield hack.
2961 */
20ec2f6c 2962
a39116f1 2963static char *crack_operand(str,opP)
542e1629
RP		 2964register char *str;
2965register struct m68k_op *opP;
a39116f1 2966{
542e1629
RP		 2967 register int parens;
2968 register int c;
2969 register char *beg_str;
2970
2971 if(!str) {
2972 return str;
2973 }
2974 beg_str=str;
2975 for(parens=0;*str && (parens>0 || notend(str));str++) {
2976 if(*str=='(') parens++;
2977 else if(*str==')') {
2978 if(!parens) { /* ERROR */
2979 opP->error="Extra )";
2980 return str;
2981 }
2982 --parens;
2983 }
2984 }
2985 if(!*str && parens) { /* ERROR */
2986 opP->error="Missing )";
2987 return str;
2988 }
2989 c= *str;
2990 *str='\0';
2991 if(m68k_ip_op(beg_str,opP)==FAIL) {
2992 *str=c;
a39116f1 2993 return str;
20ec2f6c 2994 }
a39116f1 2995 *str=c;
542e1629
RP		 2996
2997 if(c=='}')
2998 c= *++str; /* JF bitfield hack */
2999
3000 if(c) {
3001 c= *++str;
3002 if(!c)
3003 as_bad("Missing operand");
3004 }
20ec2f6c
SC		 3005 return str;
3006}
3007
3008/* See the comment up above where the #define notend(... is */
3009#if 0
3010notend(s)
542e1629 3011char *s;
20ec2f6c 3012{
542e1629
RP		 3013 if(*s==',') return 0;
3014 if(*s=='{' || *s=='}')
3015 return 0;
3016 if(*s!=':') return 1;
3017 /* This kludge here is for the division cmd, which is a kludge */
3018 if(index("aAdD#",s[1])) return 0;
3019 return 1;
20ec2f6c
SC		 3020}
3021#endif
3022
3023
3024int done_pseudo(str)
542e1629 3025char *str;
20ec2f6c 3026{
542e1629
RP		 3027 extern struct hash_control * po_hash;
3028 char *ptr = str;
3029 char *null_ptr;
3030 pseudo_typeS * pop;
a39116f1 3031
542e1629
RP		 3032 char c;
3033
3034 is_end_of_line[0] = 1;
3035 /* Skip over name of pseudo, change to lower case */
3036 while (isalpha(*ptr) || *ptr == '.')
3037 {
3038 if (isupper(*ptr)) {
3039 *ptr = tolower(*ptr);
3040 }
3041 ptr++;
3042 }
3043 null_ptr = ptr;
3044 c = *null_ptr;
3045 *null_ptr = 0;
3046
3047
3048 pop = (pseudo_typeS *)hash_find(po_hash, str);
3049
3050 *null_ptr = c;
3051 if (pop != (pseudo_typeS *)NULL)
3052 {
3053 input_line_pointer = null_ptr+1;
3054 SKIP_WHITESPACE();
3055 /* Now we point to first non-blank char after pseudo op */
3056 (*pop->poc_handler)(pop->poc_val);
3057 input_line_pointer--;
3058
3059 return 1;
3060
3061 }
3062 /* Just put back the char where the null was put and return as if nothing had happened */
3063
3064 *null_ptr = c;
3065 return 0;
a39116f1 3066
20ec2f6c
SC		 3067}
3068
3069
3070/* This is the guts of the machine-dependent assembler. STR points to a
3071 machine dependent instruction. This function is supposed to emit
3072 the frags/bytes it assembles to.
a39116f1 3073 */
20ec2f6c 3074void
a39116f1 3075 md_assemble(str)
20ec2f6c
SC		 3076char *str;
3077{
542e1629
RP		 3078 char *er;
3079 short *fromP;
3080 char *toP = NULL;
3081 int m,n = 0;
3082 char *to_beg_P;
3083 int shorts_this_frag;
3084
3085 /* if (done_pseudo(str)) return ;*/
3086
3087
3088
3089 if (current_architecture == 0) {
3090 current_architecture = (m68020
20ec2f6c 3091#ifndef NO_68881
542e1629 3092 | m68881
20ec2f6c
SC		 3093#endif
3094#ifndef NO_68851
542e1629 3095 | m68851
20ec2f6c 3096#endif
542e1629
RP		 3097 );
3098 } /* default current_architecture */
3099
3100 memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */
3101
3102 m68k_ip(str);
3103 er=the_ins.error;
3104 if(!er) {
3105 for(n=the_ins.numargs;n;--n)
3106 if(the_ins.operands[n].error) {
3107 er=the_ins.operands[n].error;
3108 break;
3109 }
20ec2f6c 3110 }
542e1629
RP		 3111 if(er) {
3112 as_bad("\"%s\" -- Statement '%s' ignored",er,str);
3113 return;
20ec2f6c 3114 }
542e1629
RP		 3115
3116 if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */
3117 toP=frag_more(2*the_ins.numo);
3118 fromP= &the_ins.opcode[0];
3119 for(m=the_ins.numo;m;--m) {
3120 md_number_to_chars(toP,(long)(*fromP),2);
3121 toP+=2;
3122 fromP++;
3123 }
3124 /* put out symbol-dependent info */
3125 for(m=0;m<the_ins.nrel;m++) {
3126 switch(the_ins.reloc[m].wid) {
3127 case 'B':
3128 n=1;
3129 break;
3130 case 'b':
3131 n=1;
3132 break;
3133 case '3':
3134 n=2;
3135 break;
3136 case 'w':
3137 n=2;
3138 break;
3139 case 'l':
3140 n=4;
3141 break;
3142 default:
3143 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid);
3144 }
3145
3146 fix_new(frag_now,
3147 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3148 n,
3149 the_ins.reloc[m].add,
3150 the_ins.reloc[m].sub,
3151 the_ins.reloc[m].off,
3152 the_ins.reloc[m].pcrel,
3153 NO_RELOC);
3154 }
3155 return;
3156 }
3157
3158 /* There's some frag hacking */
3159 for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) {
3160 int wid;
3161
3162 if(n==0) wid=2*the_ins.fragb[n].fragoff;
3163 else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff);
3164 toP=frag_more(wid);
3165 to_beg_P=toP;
3166 shorts_this_frag=0;
3167 for(m=wid/2;m;--m) {
3168 md_number_to_chars(toP,(long)(*fromP),2);
3169 toP+=2;
3170 fromP++;
3171 shorts_this_frag++;
3172 }
3173 for(m=0;m<the_ins.nrel;m++) {
3174 if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) {
3175 the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */;
3176 break;
3177 }
3178 wid=the_ins.reloc[m].wid;
3179 if(wid==0)
3180 continue;
3181 the_ins.reloc[m].wid=0;
3182 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
3183
3184 fix_new(frag_now,
3185 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3186 wid,
3187 the_ins.reloc[m].add,
3188 the_ins.reloc[m].sub,
3189 the_ins.reloc[m].off,
3190 the_ins.reloc[m].pcrel,
3191 NO_RELOC);
3192 }
3193 /* know(the_ins.fragb[n].fadd); */
3194 (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty),
3195 the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P);
3196 }
3197 n=(the_ins.numo-the_ins.fragb[n-1].fragoff);
a39116f1 3198 shorts_this_frag=0;
542e1629
RP		 3199 if(n) {
3200 toP=frag_more(n*sizeof(short));
3201 while(n--) {
3202 md_number_to_chars(toP,(long)(*fromP),2);
3203 toP+=2;
3204 fromP++;
3205 shorts_this_frag++;
3206 }
20ec2f6c 3207 }
a39116f1 3208 for(m=0;m<the_ins.nrel;m++) {
542e1629
RP		 3209 int wid;
3210
3211 wid=the_ins.reloc[m].wid;
3212 if(wid==0)
3213 continue;
3214 the_ins.reloc[m].wid=0;
3215 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
3216
3217 fix_new(frag_now,
3218 (the_ins.reloc[m].n + toP-frag_now->fr_literal)- /* the_ins.numo */ shorts_this_frag*2,
3219 wid,
3220 the_ins.reloc[m].add,
3221 the_ins.reloc[m].sub,
3222 the_ins.reloc[m].off,
3223 the_ins.reloc[m].pcrel,
3224 NO_RELOC);
20ec2f6c 3225 }
20ec2f6c
SC		 3226}
3227
3228/* This function is called once, at assembler startup time. This should
3229 set up all the tables, etc that the MD part of the assembler needs
a39116f1 3230 */
20ec2f6c 3231void
a39116f1 3232 md_begin()
20ec2f6c 3233{
542e1629
RP		 3234 /*
3235 * md_begin -- set up hash tables with 68000 instructions.
3236 * similar to what the vax assembler does. ---phr
3237 */
3238 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3239 a copy of it at runtime, adding in the information we want but isn't
3240 there. I think it'd be better to have an awk script hack the table
3241 at compile time. Or even just xstr the table and use it as-is. But
3242 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3243 names. */
3244
3245 register const struct m68k_opcode *ins;
3246 register struct m68k_incant *hack,
3247 *slak;
3248 register char *retval = 0; /* empty string, or error msg text */
3249 register unsigned int i;
3250 register char c;
3251
3252 if ((op_hash = hash_new()) == NULL)
3253 as_fatal("Virtual memory exhausted");
3254
3255 obstack_begin(&robyn,4000);
3256 for (ins = m68k_opcodes; ins < endop; ins++) {
3257 hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant));
3258 do {
3259 /* we *could* ignore insns that don't match our
3260 arch here but just leaving them out of the
3261 hash. */
3262 slak->m_operands=ins->args;
3263 slak->m_opnum=strlen(slak->m_operands)/2;
3264 slak->m_arch = ins->arch;
3265 slak->m_opcode=ins->opcode;
3266 /* This is kludgey */
3267 slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1;
3268 if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) {
3269 slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant));
3270 ins++;
3271 } else
3272 slak->m_next=0;
3273 slak=slak->m_next;
3274 } while(slak);
3275
3276 retval = hash_insert (op_hash, ins->name,(char *)hack);
3277 /* Didn't his mommy tell him about null pointers? */
3278 if(retval && *retval)
3279 as_fatal("Internal Error: Can't hash %s: %s",ins->name,retval);
3280 }
3281
3282 for (i = 0; i < sizeof(mklower_table) ; i++)
3283 mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c;
3284
3285 for (i = 0 ; i < sizeof(notend_table) ; i++) {
3286 notend_table[i] = 0;
3287 alt_notend_table[i] = 0;
3288 }
3289 notend_table[','] = 1;
3290 notend_table['{'] = 1;
3291 notend_table['}'] = 1;
3292 alt_notend_table['a'] = 1;
3293 alt_notend_table['A'] = 1;
3294 alt_notend_table['d'] = 1;
3295 alt_notend_table['D'] = 1;
3296 alt_notend_table['#'] = 1;
3297 alt_notend_table['f'] = 1;
3298 alt_notend_table['F'] = 1;
3299
20ec2f6c 3300#ifdef REGISTER_PREFIX
542e1629 3301 alt_notend_table[REGISTER_PREFIX] = 1;
20ec2f6c 3302#endif
542e1629
RP		 3303
3304
20ec2f6c
SC		 3305}
3306
3307#if 0
3308#define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
a39116f1
RP		 3309 || (*s == ':' && strchr("aAdD#", s[1]))) \
3310 ? 0 : 1)
20ec2f6c
SC		 3311#endif
3312
3313/* This funciton is called once, before the assembler exits. It is
3314 supposed to do any final cleanup for this part of the assembler.
a39116f1 3315 */
20ec2f6c 3316void
a39116f1 3317 md_end()
20ec2f6c
SC		 3318{
3319}
3320
3321/* Equal to MAX_PRECISION in atof-ieee.c */
3322#define MAX_LITTLENUMS 6
3323
3324/* Turn a string in str into a floating point constant of type
3325 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3326 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
a39116f1 3327 */
20ec2f6c 3328char *
a39116f1 3329 md_atof(type,litP,sizeP)
20ec2f6c
SC		 3330char type;
3331char *litP;
3332int *sizeP;
3333{
542e1629
RP		 3334 int prec;
3335 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3336 LITTLENUM_TYPE *wordP;
3337 char *t;
3338 char *atof_ieee();
a39116f1 3339
542e1629
RP		 3340 switch(type) {
3341 case 'f':
3342 case 'F':
3343 case 's':
3344 case 'S':
3345 prec = 2;
3346 break;
3347
3348 case 'd':
3349 case 'D':
3350 case 'r':
3351 case 'R':
3352 prec = 4;
3353 break;
3354
3355 case 'x':
3356 case 'X':
3357 prec = 6;
3358 break;
3359
3360 case 'p':
3361 case 'P':
3362 prec = 6;
3363 break;
3364
3365 default:
3366 *sizeP=0;
3367 return "Bad call to MD_ATOF()";
3368 }
3369 t=atof_ieee(input_line_pointer,type,words);
3370 if(t)
3371 input_line_pointer=t;
a39116f1 3372
542e1629
RP		 3373 *sizeP=prec * sizeof(LITTLENUM_TYPE);
3374 for(wordP=words;prec--;) {
3375 md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE));
3376 litP+=sizeof(LITTLENUM_TYPE);
3377 }
3378 return ""; /* Someone should teach Dean about null pointers */
20ec2f6c
SC		 3379}
3380
3381/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3382 for use in the a.out file, and stores them in the array pointed to by buf.
3383 This knows about the endian-ness of the target machine and does
3384 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3385 2 (short) and 4 (long) Floating numbers are put out as a series of
3386 LITTLENUMS (shorts, here at least)
a39116f1 3387 */
20ec2f6c 3388void
a39116f1 3389 md_number_to_chars(buf,val,n)
20ec2f6c
SC		 3390char *buf;
3391long val;
3392int n;
3393{
542e1629
RP		 3394 switch(n) {
3395 case 1:
3396 *buf++=val;
3397 break;
3398 case 2:
3399 *buf++=(val>>8);
3400 *buf++=val;
3401 break;
3402 case 4:
3403 *buf++=(val>>24);
3404 *buf++=(val>>16);
3405 *buf++=(val>>8);
3406 *buf++=val;
3407 break;
3408 default:
3409 as_fatal("failed sanity check.");
3410 }
20ec2f6c
SC		 3411}
3412
3413void
a39116f1
RP		 3414 md_apply_fix(fixP, val)
3415fixS *fixP;
3416long val;
20ec2f6c 3417{
542e1629
RP		 3418 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3419
3420 switch(fixP->fx_size) {
3421 case 1:
3422 *buf++=val;
3423 break;
3424 case 2:
3425 *buf++=(val>>8);
3426 *buf++=val;
3427 break;
3428 case 4:
3429 *buf++=(val>>24);
3430 *buf++=(val>>16);
3431 *buf++=(val>>8);
3432 *buf++=val;
3433 break;
3434 default:
3435 BAD_CASE (fixP->fx_size);
3436 }
20ec2f6c
SC		 3437}
3438
3439
3440/* *fragP has been relaxed to its final size, and now needs to have
3441 the bytes inside it modified to conform to the new size There is UGLY
3442 MAGIC here. ..
a39116f1 3443 */
20ec2f6c 3444void
a39116f1 3445 md_convert_frag(headers, fragP)
20ec2f6c
SC		 3446object_headers *headers;
3447register fragS *fragP;
3448{
542e1629
RP		 3449 long disp;
3450 long ext = 0;
3451
3452 /* Address in object code of the displacement. */
3453 register int object_address = fragP -> fr_fix + fragP -> fr_address;
3454
20ec2f6c 3455#ifdef IBM_COMPILER_SUX
542e1629
RP		 3456 /* This is wrong but it convinces the native rs6000 compiler to
3457 generate the code we want. */
3458 register char *buffer_address = fragP -> fr_literal;
3459 buffer_address += fragP -> fr_fix;
20ec2f6c 3460#else /* IBM_COMPILER_SUX */
542e1629
RP		 3461 /* Address in gas core of the place to store the displacement. */
3462 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
20ec2f6c 3463#endif /* IBM_COMPILER_SUX */
542e1629
RP		 3464
3465 /* No longer true: know(fragP->fr_symbol); */
3466
3467 /* The displacement of the address, from current location. */
3468 disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0;
3469 disp = (disp + fragP->fr_offset) - object_address;
3470
3471 switch(fragP->fr_subtype) {
3472 case TAB(BCC68000,BYTE):
a39116f1
RP		 3473 case TAB(BRANCH,BYTE):
3474 know(issbyte(disp));
3475 if(disp==0)
3476 as_bad("short branch with zero offset: use :w");
3477 fragP->fr_opcode[1]=disp;
20ec2f6c 3478 ext=0;
a39116f1 3479 break;
542e1629
RP		 3480 case TAB(DBCC,SHORT):
3481 know(issword(disp));
a39116f1
RP		 3482 ext=2;
3483 break;
542e1629
RP		 3484 case TAB(BCC68000,SHORT):
3485 case TAB(BRANCH,SHORT):
3486 know(issword(disp));
a39116f1
RP		 3487 fragP->fr_opcode[1]=0x00;
3488 ext=2;
3489 break;
542e1629
RP		 3490 case TAB(BRANCH,LONG):
3491 if (cpu_of_arch(current_architecture) < m68020) {
3492 if (fragP->fr_opcode[0]==0x61) {
3493 fragP->fr_opcode[0]= 0x4E;
3494 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3495 subseg_change(SEG_TEXT, 0);
3496
3497 fix_new(fragP,
3498 fragP->fr_fix,
3499 4,
3500 fragP->fr_symbol,
3501 0,
3502 fragP->fr_offset,
3503 0,
3504 NO_RELOC);
3505
3506 fragP->fr_fix+=4;
3507 ext=0;
3508 } else if (fragP->fr_opcode[0]==0x60) {
3509 fragP->fr_opcode[0]= 0x4E;
3510 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3511 subseg_change(SEG_TEXT, 0);
3512 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0,
3513 NO_RELOC);
3514 fragP->fr_fix+=4;
3515 ext=0;
3516 } else {
3517 as_bad("Long branch offset not supported.");
3518 }
3519 } else {
3520 fragP->fr_opcode[1]=0xff;
3521 ext=4;
3522 }
a39116f1 3523 break;
542e1629
RP		 3524 case TAB(BCC68000,LONG):
3525 /* only Bcc 68000 instructions can come here */
3526 /* change bcc into b!cc/jmp absl long */
3527 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
20ec2f6c 3528 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */
a39116f1 3529
20ec2f6c
SC		 3530 /* JF: these used to be fr_opcode[2,3], but they may be in a
3531 different frag, in which case refering to them is a no-no.
3532 Only fr_opcode[0,1] are guaranteed to work. */
3533 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3534 *buffer_address++ = 0xf9;
3535 fragP->fr_fix += 2; /* account for jmp instruction */
3536 subseg_change(SEG_TEXT,0);
3537 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
a39116f1
RP		 3538 fragP->fr_offset,0,
3539 NO_RELOC);
20ec2f6c
SC		 3540 fragP->fr_fix += 4;
3541 ext=0;
3542 break;
542e1629
RP		 3543 case TAB(DBCC,LONG):
3544 /* only DBcc 68000 instructions can come here */
3545 /* change dbcc into dbcc/jmp absl long */
3546 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3547 *buffer_address++ = 0x00; /* branch offset = 4 */
20ec2f6c
SC		 3548 *buffer_address++ = 0x04;
3549 *buffer_address++ = 0x60; /* put in bra pc+6 */
3550 *buffer_address++ = 0x06;
3551 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3552 *buffer_address++ = 0xf9;
a39116f1 3553
20ec2f6c
SC		 3554 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3555 subseg_change(SEG_TEXT,0);
3556 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
a39116f1
RP		 3557 fragP->fr_offset,0,
3558 NO_RELOC);
20ec2f6c
SC		 3559 fragP->fr_fix += 4;
3560 ext=0;
a39116f1 3561 break;
542e1629
RP		 3562 case TAB(FBRANCH,SHORT):
3563 know((fragP->fr_opcode[1]&0x40)==0);
a39116f1
RP		 3564 ext=2;
3565 break;
542e1629
RP		 3566 case TAB(FBRANCH,LONG):
3567 fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */
a39116f1
RP		 3568 ext=4;
3569 break;
542e1629
RP		 3570 case TAB(PCREL,SHORT):
3571 ext=2;
a39116f1 3572 break;
542e1629
RP		 3573 case TAB(PCREL,LONG):
3574 /* The thing to do here is force it to ABSOLUTE LONG, since
3575 PCREL is really trying to shorten an ABSOLUTE address anyway */
3576 /* JF FOO This code has not been tested */
3577 subseg_change(SEG_TEXT,0);
a39116f1
RP		 3578 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3579 if((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3580 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3581 fragP->fr_opcode[0],fragP->fr_address);
3582 fragP->fr_opcode[1]&= ~0x3F;
3583 fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */
3584 fragP->fr_fix+=4;
3585 /* md_number_to_chars(buffer_address,
3586 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3587 4); */
3588 ext=0;
3589 break;
542e1629
RP		 3590 case TAB(PCLEA,SHORT):
3591 subseg_change(SEG_TEXT,0);
a39116f1
RP		 3592 fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1,
3593 NO_RELOC);
3594 fragP->fr_opcode[1] &= ~0x3F;
3595 fragP->fr_opcode[1] |= 0x3A;
3596 ext=2;
3597 break;
542e1629
RP		 3598 case TAB(PCLEA,LONG):
3599 subseg_change(SEG_TEXT,0);
a39116f1
RP		 3600 fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1,
3601 NO_RELOC);
3602 *buffer_address++ = 0x01;
3603 *buffer_address++ = 0x70;
3604 fragP->fr_fix+=2;
542e1629
RP		 3605 /* buffer_address+=2; */
3606 ext=4;
a39116f1 3607 break;
a39116f1 3608
542e1629 3609} /* switch on subtype */
a39116f1 3610
542e1629
RP		 3611 if (ext) {
3612 md_number_to_chars(buffer_address, (long) disp, (int) ext);
3613 fragP->fr_fix += ext;
3614 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3615 } /* if extending */
a39116f1 3616
542e1629
RP		 3617 return;
3618} /* md_convert_frag() */
3619
3620/* Force truly undefined symbols to their maximum size, and generally set up
3621 the frag list to be relaxed
3622 */
3623int md_estimate_size_before_relax(fragP, segment)
3624register fragS *fragP;
3625segT segment;
3626{
3627 int old_fix;
3628 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
a39116f1 3629
542e1629
RP		 3630 old_fix = fragP->fr_fix;
3631
3632 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3633 switch(fragP->fr_subtype) {
3634
3635 case TAB(BRANCH,SZ_UNDEF): {
3636 if((fragP->fr_symbol != NULL) /* Not absolute */
3637 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3638 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE);
3639 break;
3640 } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) {
3641 /* On 68000, or for absolute value, switch to abs long */
3642 /* FIXME, we should check abs val, pick short or long */
3643 if(fragP->fr_opcode[0]==0x61) {
3644 fragP->fr_opcode[0]= 0x4E;
3645 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3646 subseg_change(SEG_TEXT, 0);
3647 fix_new(fragP, fragP->fr_fix, 4,
3648 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3649 fragP->fr_fix+=4;
3650 frag_wane(fragP);
3651 } else if(fragP->fr_opcode[0]==0x60) {
3652 fragP->fr_opcode[0]= 0x4E;
3653 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3654 subseg_change(SEG_TEXT, 0);
3655 fix_new(fragP, fragP->fr_fix, 4,
3656 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3657 fragP->fr_fix+=4;
3658 frag_wane(fragP);
3659 } else {
3660 as_warn("Long branch offset to extern symbol not supported.");
3661 }
3662 } else { /* Symbol is still undefined. Make it simple */
3663 fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol,
3664 (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC);
3665 fragP->fr_fix+=4;
3666 fragP->fr_opcode[1]=0xff;
3667 frag_wane(fragP);
3668 break;
3669 }
3670
3671 break;
3672 } /* case TAB(BRANCH,SZ_UNDEF) */
3673
3674 case TAB(FBRANCH,SZ_UNDEF): {
3675 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3676 fragP->fr_subtype = TAB(FBRANCH,SHORT);
3677 fragP->fr_var += 2;
3678 } else {
3679 fragP->fr_subtype = TAB(FBRANCH,LONG);
3680 fragP->fr_var += 4;
3681 }
3682 break;
3683 } /* TAB(FBRANCH,SZ_UNDEF) */
3684
3685 case TAB(PCREL,SZ_UNDEF): {
3686 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3687 fragP->fr_subtype = TAB(PCREL,SHORT);
3688 fragP->fr_var += 2;
3689 } else {
3690 fragP->fr_subtype = TAB(PCREL,LONG);
3691 fragP->fr_var += 4;
3692 }
3693 break;
3694 } /* TAB(PCREL,SZ_UNDEF) */
3695
3696 case TAB(BCC68000,SZ_UNDEF): {
3697 if((fragP->fr_symbol != NULL)
3698 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3699 fragP->fr_subtype=TAB(BCC68000,BYTE);
3700 break;
3701 }
3702 /* only Bcc 68000 instructions can come here */
3703 /* change bcc into b!cc/jmp absl long */
3704 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3705 if(flagseen['l']) {
3706 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3707 /* JF: these were fr_opcode[2,3] */
3708 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3709 buffer_address[1] = 0xf8;
3710 fragP->fr_fix += 2; /* account for jmp instruction */
3711 subseg_change(SEG_TEXT,0);
3712 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3713 fragP->fr_offset, 0, NO_RELOC);
3714 fragP->fr_fix += 2;
3715 } else {
3716 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3717 /* JF: these were fr_opcode[2,3] */
3718 buffer_address[2] = 0x4e; /* put in jmp long (0x4ef9) */
3719 buffer_address[3] = 0xf9;
3720 fragP->fr_fix += 2; /* account for jmp instruction */
3721 subseg_change(SEG_TEXT,0);
3722 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3723 fragP->fr_offset, 0, NO_RELOC);
3724 fragP->fr_fix += 4;
3725 }
3726 frag_wane(fragP);
3727 break;
3728 } /* case TAB(BCC68000,SZ_UNDEF) */
3729
3730 case TAB(DBCC,SZ_UNDEF): {
3731 if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3732 fragP->fr_subtype=TAB(DBCC,SHORT);
3733 fragP->fr_var+=2;
3734 break;
3735 }
3736 /* only DBcc 68000 instructions can come here */
3737 /* change dbcc into dbcc/jmp absl long */
3738 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3739 buffer_address[0] = 0x00; /* branch offset = 4 */
3740 buffer_address[1] = 0x04;
3741 buffer_address[2] = 0x60; /* put in bra pc + ... */
3742
3743 if(flagseen['l']) {
3744 /* JF: these were fr_opcode[5-7] */
3745 buffer_address[3] = 0x04; /* plus 4 */
3746 buffer_address[4] = 0x4e;/* Put in Jump Word */
3747 buffer_address[5] = 0xf8;
3748 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3749 subseg_change(SEG_TEXT,0);
3750 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
3751 fragP->fr_offset, 0, NO_RELOC);
3752 fragP->fr_fix += 2;
3753 } else {
3754 /* JF: these were fr_opcode[5-7] */
3755 buffer_address[3] = 0x06; /* Plus 6 */
3756 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3757 buffer_address[5] = 0xf9;
3758 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3759 subseg_change(SEG_TEXT,0);
3760 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
3761 fragP->fr_offset, 0, NO_RELOC);
3762 fragP->fr_fix += 4;
3763 }
3764
3765 frag_wane(fragP);
3766 break;
3767 } /* case TAB(DBCC,SZ_UNDEF) */
3768
3769 case TAB(PCLEA,SZ_UNDEF): {
3770 if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) {
3771 fragP->fr_subtype=TAB(PCLEA,SHORT);
3772 fragP->fr_var+=2;
3773 } else {
3774 fragP->fr_subtype=TAB(PCLEA,LONG);
3775 fragP->fr_var+=6;
3776 }
3777 break;
3778 } /* TAB(PCLEA,SZ_UNDEF) */
3779
3780 default:
3781 break;
3782
3783 } /* switch on subtype looking for SZ_UNDEF's. */
a39116f1 3784
542e1629
RP		 3785 /* now that SZ_UNDEF are taken care of, check others */
3786 switch(fragP->fr_subtype) {
3787 case TAB(BCC68000,BYTE):
a39116f1
RP		 3788 case TAB(BRANCH,BYTE):
3789 /* We can't do a short jump to the next instruction,
3790 so we force word mode. */
3791 if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 &&
3792 fragP->fr_symbol->sy_frag==fragP->fr_next) {
542e1629
RP		 3793 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT);
3794 fragP->fr_var+=2;
20ec2f6c 3795 }
a39116f1 3796 break;
542e1629 3797 default:
a39116f1 3798 break;
542e1629
RP		 3799}
3800 return fragP->fr_var + fragP->fr_fix - old_fix;
20ec2f6c
SC		 3801}
3802
3803#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3804/* the bit-field entries in the relocation_info struct plays hell
3805 with the byte-order problems of cross-assembly. So as a hack,
3806 I added this mach. dependent ri twiddler. Ugly, but it gets
3807 you there. -KWK */
3808/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 3809 are symbolnum, most sig. byte first. Last byte is broken up with
3810 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3811 nibble as nuthin. (on Sun 3 at least) */
20ec2f6c
SC		 3812/* Translate the internal relocation information into target-specific
3813 format. */
3814#ifdef comment
3815void
a39116f1
RP		 3816 md_ri_to_chars(the_bytes, ri)
3817char *the_bytes;
3818struct reloc_info_generic *ri;
20ec2f6c 3819{
542e1629
RP		 3820 /* this is easy */
3821 md_number_to_chars(the_bytes, ri->r_address, 4);
3822 /* now the fun stuff */
3823 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3824 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3825 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3826 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3827 ((ri->r_extern << 4) & 0x10));
20ec2f6c
SC		 3828}
3829#endif /* comment */
3830
3831void tc_aout_fix_to_chars(where, fixP, segment_address_in_file)
542e1629
RP		 3832char *where;
3833fixS *fixP;
3834relax_addressT segment_address_in_file;
20ec2f6c 3835{
542e1629
RP		 3836 /*
3837 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3838 * Out: GNU LD relocation length code: 0, 1, or 2.
3839 */
3840
3841 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
3842
3843 long r_extern;
3844 long r_symbolnum;
3845
3846 /* this is easy */
3847 md_number_to_chars(where,
3848 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3849 4);
3850
3851 /* now the fun stuff */
3852 if (S_GET_TYPE(fixP->fx_addsy) == N_UNDF) {
3853 r_extern = 1;
3854 r_symbolnum = fixP->fx_addsy->sy_number;
3855 } else {
3856 r_extern = 0;
3857 r_symbolnum = S_GET_TYPE(fixP->fx_addsy);
3858 }
3859
3860 where[4] = (r_symbolnum >> 16) & 0x0ff;
3861 where[5] = (r_symbolnum >> 8) & 0x0ff;
3862 where[6] = r_symbolnum & 0x0ff;
3863 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3864 ((r_extern << 4) & 0x10));
3865
3866 return;
20ec2f6c
SC		 3867} /* tc_aout_fix_to_chars() */
3868
3869#endif /* OBJ_AOUT or OBJ_BOUT */
3870
3871#ifndef WORKING_DOT_WORD
3872const int md_short_jump_size = 4;
3873const int md_long_jump_size = 6;
3874
3875void
a39116f1 3876 md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol)
20ec2f6c
SC		 3877char *ptr;
3878long from_addr,
a39116f1 3879 to_addr;
20ec2f6c
SC		 3880fragS *frag;
3881symbolS *to_symbol;
3882{
542e1629
RP		 3883 long offset;
3884
3885 offset = to_addr - (from_addr+2);
3886
3887 md_number_to_chars(ptr ,(long)0x6000,2);
3888 md_number_to_chars(ptr+2,(long)offset,2);
20ec2f6c
SC		 3889}
3890
3891void
a39116f1 3892 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
20ec2f6c
SC		 3893char *ptr;
3894long from_addr,
a39116f1 3895 to_addr;
20ec2f6c
SC		 3896fragS *frag;
3897symbolS *to_symbol;
3898{
542e1629
RP		 3899 long offset;
3900
3901 if (cpu_of_arch(current_architecture) < m68020) {
3902 offset=to_addr-S_GET_VALUE(to_symbol);
3903 md_number_to_chars(ptr ,(long)0x4EF9,2);
3904 md_number_to_chars(ptr+2,(long)offset,4);
3905 fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0,
3906 NO_RELOC);
3907 } else {
3908 offset=to_addr - (from_addr+2);
3909 md_number_to_chars(ptr ,(long)0x60ff,2);
3910 md_number_to_chars(ptr+2,(long)offset,4);
3911 }
20ec2f6c
SC		 3912}
3913
3914#endif
3915/* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
a39116f1
RP		 3916
3917 0: Everything is OK
3918 10: Absolute 1:8 only
3919 20: Absolute 0:7 only
3920 30: absolute 0:15 only
3921 40: Absolute 0:31 only
3922 50: absolute 0:127 only
3923 55: absolute -64:63 only
3924 60: absolute -128:127 only
3925 70: absolute 0:4095 only
3926 80: No bignums
3927
3928 */
20ec2f6c
SC		 3929
3930static int get_num(exp,ok)
542e1629
RP		 3931struct m68k_exp *exp;
3932int ok;
20ec2f6c
SC		 3933{
3934#ifdef TEST2
542e1629
RP		 3935 long l = 0;
3936
3937 if(!exp->e_beg)
3938 return 0;
3939 if(*exp->e_beg=='0') {
3940 if(exp->e_beg[1]=='x')
3941 sscanf(exp->e_beg+2,"%x",&l);
3942 else
3943 sscanf(exp->e_beg+1,"%O",&l);
3944 return l;
3945 }
3946 return atol(exp->e_beg);
20ec2f6c 3947#else
542e1629
RP		 3948 char *save_in;
3949 char c_save;
3950
3951 if(!exp) {
3952 /* Can't do anything */
3953 return 0;
3954 }
3955 if(!exp->e_beg || !exp->e_end) {
3956 seg(exp)=SEG_ABSOLUTE;
3957 adds(exp)=0;
3958 subs(exp)=0;
3959 offs(exp)= (ok==10) ? 1 : 0;
3960 as_warn("Null expression defaults to %ld",offs(exp));
3961 return 0;
20ec2f6c 3962 }
a39116f1 3963
542e1629
RP		 3964 exp->e_siz=0;
3965 if(/* ok!=80 && */exp->e_end[-1]==SIZER && (exp->e_end-exp->e_beg)>=2) {
3966 switch(exp->e_end[0]) {
3967 case 's':
3968 case 'S':
3969 case 'b':
3970 case 'B':
3971 exp->e_siz=1;
3972 break;
3973 case 'w':
3974 case 'W':
3975 exp->e_siz=2;
3976 break;
3977 case 'l':
3978 case 'L':
3979 exp->e_siz=3;
3980 break;
3981 default:
3982 as_bad("Unknown size for expression \"%c\"",exp->e_end[0]);
3983 }
3984 exp->e_end-=2;
20ec2f6c 3985 }
542e1629
RP		 3986 c_save=exp->e_end[1];
3987 exp->e_end[1]='\0';
3988 save_in=input_line_pointer;
3989 input_line_pointer=exp->e_beg;
3990 switch(expression(&(exp->e_exp))) {
3991 case SEG_PASS1:
3992 seg(exp)=SEG_ABSOLUTE;
3993 adds(exp)=0;
3994 subs(exp)=0;
3995 offs(exp)= (ok==10) ? 1 : 0;
3996 as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp));
3997 break;
3998
3999 case SEG_ABSENT:
4000 /* Do the same thing the VAX asm does */
4001 seg(exp)=SEG_ABSOLUTE;
4002 adds(exp)=0;
4003 subs(exp)=0;
20ec2f6c 4004 offs(exp)=0;
542e1629
RP		 4005 if(ok==10) {
4006 as_warn("expression out of range: defaulting to 1");
4007 offs(exp)=1;
4008 }
4009 break;
4010 case SEG_ABSOLUTE:
4011 switch(ok) {
4012 case 10:
4013 if(offs(exp)<1 || offs(exp)>8) {
4014 as_warn("expression out of range: defaulting to 1");
4015 offs(exp)=1;
4016 }
4017 break;
4018 case 20:
4019 if(offs(exp)<0 || offs(exp)>7)
4020 goto outrange;
4021 break;
4022 case 30:
4023 if(offs(exp)<0 || offs(exp)>15)
4024 goto outrange;
4025 break;
4026 case 40:
4027 if(offs(exp)<0 || offs(exp)>32)
4028 goto outrange;
4029 break;
4030 case 50:
4031 if(offs(exp)<0 || offs(exp)>127)
4032 goto outrange;
4033 break;
4034 case 55:
4035 if(offs(exp)<-64 || offs(exp)>63)
4036 goto outrange;
4037 break;
4038 case 60:
4039 if(offs(exp)<-128 || offs(exp)>127)
4040 goto outrange;
4041 break;
4042 case 70:
4043 if(offs(exp)<0 || offs(exp)>4095) {
4044 outrange:
4045 as_warn("expression out of range: defaulting to 0");
4046 offs(exp)=0;
4047 }
4048 break;
4049 default:
4050 break;
4051 }
4052 break;
4053 case SEG_TEXT:
4054 case SEG_DATA:
4055 case SEG_BSS:
4056 case SEG_UNKNOWN:
4057 case SEG_DIFFERENCE:
4058 if(ok>=10 && ok<=70) {
4059 seg(exp)=SEG_ABSOLUTE;
4060 adds(exp)=0;
4061 subs(exp)=0;
4062 offs(exp)= (ok==10) ? 1 : 0;
4063 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4064 }
4065 break;
4066 case SEG_BIG:
4067 if(ok==80 && offs(exp)<0) { /* HACK! Turn it into a long */
4068 LITTLENUM_TYPE words[6];
4069
4070 gen_to_words(words,2,8L);/* These numbers are magic! */
4071 seg(exp)=SEG_ABSOLUTE;
4072 adds(exp)=0;
4073 subs(exp)=0;
4074 offs(exp)=words[1]|(words[0]<<16);
4075 } else if(ok!=0) {
4076 seg(exp)=SEG_ABSOLUTE;
4077 adds(exp)=0;
4078 subs(exp)=0;
4079 offs(exp)= (ok==10) ? 1 : 0;
4080 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4081 }
4082 break;
20ec2f6c 4083 default:
542e1629 4084 as_fatal("failed sanity check.");
a39116f1 4085 }
542e1629
RP		 4086 if(input_line_pointer!=exp->e_end+1)
4087 as_bad("Ignoring junk after expression");
4088 exp->e_end[1]=c_save;
4089 input_line_pointer=save_in;
4090 if(exp->e_siz) {
4091 switch(exp->e_siz) {
4092 case 1:
4093 if(!isbyte(offs(exp)))
4094 as_warn("expression doesn't fit in BYTE");
4095 break;
4096 case 2:
4097 if(!isword(offs(exp)))
4098 as_warn("expression doesn't fit in WORD");
4099 break;
4100 }
20ec2f6c 4101 }
542e1629 4102 return offs(exp);
20ec2f6c
SC		 4103#endif
4104} /* get_num() */
4105
4106/* These are the back-ends for the various machine dependent pseudo-ops. */
4107void demand_empty_rest_of_line(); /* Hate those extra verbose names */
4108
4109static void s_data1() {
542e1629
RP		 4110 subseg_new(SEG_DATA,1);
4111 demand_empty_rest_of_line();
20ec2f6c
SC		 4112} /* s_data1() */
4113
4114static void s_data2() {
542e1629
RP		 4115 subseg_new(SEG_DATA,2);
4116 demand_empty_rest_of_line();
20ec2f6c
SC		 4117} /* s_data2() */
4118
4119static void s_bss() {
542e1629
RP		 4120 /* We don't support putting frags in the BSS segment, but we
4121 can put them into initialized data for now... */
4122 subseg_new(SEG_DATA,255); /* FIXME-SOON */
4123 demand_empty_rest_of_line();
20ec2f6c
SC		 4124} /* s_bss() */
4125
4126static void s_even() {
542e1629
RP		 4127 register int temp;
4128 register long temp_fill;
4129
4130 temp = 1; /* JF should be 2? */
4131 temp_fill = get_absolute_expression ();
4132 if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */
4133 frag_align (temp, (int)temp_fill);
4134 demand_empty_rest_of_line();
20ec2f6c
SC		 4135} /* s_even() */
4136
4137static void s_proc() {
542e1629 4138 demand_empty_rest_of_line();
20ec2f6c
SC		 4139} /* s_proc() */
4140
4141/* s_space is defined in read.c .skip is simply an alias to it. */
4142
4143/*
4144 * md_parse_option
4145 * Invocation line includes a switch not recognized by the base assembler.
4146 * See if it's a processor-specific option. These are:
4147 *
4148 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4149 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4150 * Select the architecture. Instructions or features not
4151 * supported by the selected architecture cause fatal
4152 * errors. More than one may be specified. The default is
4153 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4154 * for -m68000, and -m68882 is a synonym for -m68881.
4155 *
4156 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4157 * (e.g. m68020) also requests that float instructions be included. This
4158 * is the default setup, mostly to avoid hassling users. A better
4159 * rearrangement of this structure would be to add an option to DENY
4160 * floating point opcodes, for people who want to really know there's none
4161 * of that funny floaty stuff going on. FIXME-later.
4162 */
4163#ifndef MAYBE_FLOAT_TOO
4164#define MAYBE_FLOAT_TOO m68881
4165#endif
4166
4167int md_parse_option(argP,cntP,vecP)
542e1629
RP		 4168char **argP;
4169int *cntP;
4170char ***vecP;
20ec2f6c 4171{
542e1629
RP		 4172 switch(**argP) {
4173 case 'l': /* -l means keep external to 2 bit offset
4174 rather than 16 bit one */
4175 break;
4176
4177 case 'S': /* -S means that jbsr's always turn into jsr's. */
4178 break;
4179
4180 case 'A':
4181 (*argP)++;
4182 /* intentional fall-through */
4183 case 'm':
4184 (*argP)++;
4185
4186 if (**argP=='c') {
4187 (*argP)++;
4188 } /* allow an optional "c" */
4189
4190 if (!strcmp(*argP, "68000")
4191 || !strcmp(*argP, "68008")) {
4192 current_architecture |= m68000;
4193 } else if (!strcmp(*argP, "68010")) {
20ec2f6c 4194#ifdef TE_SUN
542e1629 4195 omagic= 1<<16|OMAGIC;
20ec2f6c 4196#endif
542e1629
RP		 4197 current_architecture |= m68010;
4198
4199 } else if (!strcmp(*argP, "68020")) {
4200 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
4201
4202 } else if (!strcmp(*argP, "68030")) {
4203 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
4204
4205 } else if (!strcmp(*argP, "68040")) {
4206 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
4207
20ec2f6c 4208#ifndef NO_68881
542e1629
RP		 4209 } else if (!strcmp(*argP, "68881")) {
4210 current_architecture |= m68881;
4211
4212 } else if (!strcmp(*argP, "68882")) {
4213 current_architecture |= m68882;
4214
20ec2f6c
SC		 4215#endif /* NO_68881 */
4216#ifndef NO_68851
542e1629
RP		 4217 } else if (!strcmp(*argP,"68851")) {
4218 current_architecture |= m68851;
4219
20ec2f6c 4220#endif /* NO_68851 */
542e1629
RP		 4221 } else {
4222 as_warn("Unknown architecture, \"%s\". option ignored", *argP);
4223 } /* switch on architecture */
4224
4225 while(**argP) (*argP)++;
4226
4227 break;
4228
4229 case 'p':
4230 if (!strcmp(*argP,"pic")) {
4231 (*argP) += 3;
4232 break; /* -pic, Position Independent Code */
4233 } else {
4234 return(0);
4235 } /* pic or not */
4236
4237 default:
4238 return 0;
4239 }
4240 return 1;
20ec2f6c
SC		 4241}
4242
4243
4244#ifdef TEST2
4245
4246/* TEST2: Test md_assemble() */
4247/* Warning, this routine probably doesn't work anymore */
4248
4249main()
4250{
542e1629
RP		 4251 struct m68k_it the_ins;
4252 char buf[120];
4253 char *cp;
4254 int n;
4255
4256 m68k_ip_begin();
4257 for(;;) {
4258 if(!gets(buf) || !*buf)
4259 break;
4260 if(buf[0]=='|' || buf[1]=='.')
4261 continue;
4262 for(cp=buf;*cp;cp++)
4263 if(*cp=='\t')
4264 *cp=' ';
4265 if(is_label(buf))
4266 continue;
4267 memset(&the_ins, '\0', sizeof(the_ins));
4268 m68k_ip(&the_ins,buf);
4269 if(the_ins.error) {
4270 printf("Error %s in %s\n",the_ins.error,buf);
4271 } else {
4272 printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args);
4273 for(n=0;n<the_ins.numo;n++)
4274 printf(" 0x%x",the_ins.opcode[n]&0xffff);
4275 printf(" ");
4276 print_the_insn(&the_ins.opcode[0],stdout);
4277 (void)putchar('\n');
4278 }
4279 for(n=0;n<strlen(the_ins.args)/2;n++) {
4280 if(the_ins.operands[n].error) {
4281 printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf);
4282 continue;
4283 }
4284 printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg);
4285 if(the_ins.operands[n].b_const)
4286 printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const);
4287 printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul);
4288 if(the_ins.operands[n].b_iadd)
4289 printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd);
4290 (void)putchar('\n');
4291 }
a39116f1 4292 }
542e1629
RP		 4293 m68k_ip_end();
4294 return 0;
20ec2f6c
SC		 4295}
4296
4297is_label(str)
542e1629 4298char *str;
20ec2f6c 4299{
542e1629
RP		 4300 while(ISSPACE(*str))
4301 str++;
4302 while(*str && !ISSPACE(*str))
4303 str++;
4304 if(str[-1]==':' || str[1]=='=')
4305 return 1;
4306 return 0;
20ec2f6c
SC		 4307}
4308
4309#endif
4310
4311/* Possible states for relaxation:
a39116f1
RP		 4312
4313 0 0 branch offset byte (bra, etc)
4314 0 1 word
4315 0 2 long
4316
4317 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4318 1 1 word
4319 1 2 long
4320
4321 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4322 2 1 word-long
4323 2 2 long-word
4324 2 3 long-long
4325
4326 */
20ec2f6c
SC		 4327
4328
4329
4330#ifdef DONTDEF
4331abort()
4332{
542e1629
RP		 4333 printf("ABORT!\n");
4334 exit(12);
20ec2f6c
SC		 4335}
4336
4337print_frags()
4338{
542e1629
RP		 4339 fragS *fragP;
4340 extern fragS *text_frag_root;
4341
4342 for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) {
4343 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
4344 fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset);
4345 printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype);
4346 }
4347 fflush(stdout);
4348 return 0;
20ec2f6c
SC		 4349}
4350#endif
4351
4352#ifdef DONTDEF
4353/*VARARGS1*/
4354panic(format,args)
542e1629 4355char *format;
20ec2f6c 4356{
542e1629
RP		 4357 fputs("Internal error:",stderr);
4358 _doprnt(format,&args,stderr);
4359 (void)putc('\n',stderr);
4360 as_where();
4361 abort();
20ec2f6c
SC		 4362}
4363#endif
4364
4365/* We have no need to default values of symbols. */
4366
4367/* ARGSUSED */
4368symbolS *
a39116f1
RP		 4369 md_undefined_symbol (name)
4370char *name;
20ec2f6c 4371{
542e1629 4372 return 0;
20ec2f6c
SC		 4373}
4374
4375/* Parse an operand that is machine-specific.
4376 We just return without modifying the expression if we have nothing
4377 to do. */
4378
4379/* ARGSUSED */
4380void
a39116f1
RP		 4381 md_operand (expressionP)
4382expressionS *expressionP;
20ec2f6c
SC		 4383{
4384}
4385
4386/* Round up a section size to the appropriate boundary. */
4387long
a39116f1
RP		 4388 md_section_align (segment, size)
4389segT segment;
4390long size;
20ec2f6c 4391{
542e1629 4392 return size; /* Byte alignment is fine */
20ec2f6c
SC		 4393}
4394
4395/* Exactly what point is a PC-relative offset relative TO?
4396 On the 68k, they're relative to the address of the offset, plus
4397 its size. (??? Is this right? FIXME-SOON!) */
4398long
a39116f1
RP		 4399 md_pcrel_from (fixP)
4400fixS *fixP;
20ec2f6c 4401{
542e1629 4402 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
20ec2f6c
SC		 4403}
4404
4405#ifdef MRI
4406void s_ds(size)
4407{
542e1629
RP		 4408 unsigned int fill = get_absolute_expression() * size;
4409 char *p = frag_var (rs_fill, fill, fill, (relax_substateT)0, (symbolS *)0,
4410 1, (char *)0);
4411 * p = 0;
4412 demand_empty_rest_of_line();
20ec2f6c
SC		 4413}
4414
4415void s_dc(size)
4416{
542e1629
RP		 4417
4418 cons(size);
4419
4420
20ec2f6c
SC		 4421}
4422
4423void s_dcb(size)
4424{
542e1629
RP		 4425 int repeat = get_absolute_expression();
4426 int fill;
4427
4428 if (*input_line_pointer == ',')
4429 {
4430 char *p;
4431 input_line_pointer++;
4432
4433 fill = get_absolute_expression();
4434 p = frag_var(rs_fill,
4435 size,
4436 size,
4437 (relax_substateT)0,
4438 (symbolS *)0,
4439 repeat,
4440 0);
4441 md_number_to_chars(p, fill, size);
4442 }
4443 demand_empty_rest_of_line();
4444
4445
20ec2f6c
SC		 4446}
4447
4448void s_chip()
4449{
542e1629 4450 unsigned int target = get_absolute_expression();
20ec2f6c 4451#define MACHINE_MASK (m68000 | m68008 | m68010 | m68020 | m68040)
542e1629
RP		 4452 switch (target)
4453 {
4454 case 68000:
4455 case 68008:
4456 current_architecture = (current_architecture & ~ MACHINE_MASK) | m68000;
4457 break;
4458 case 68010:
4459 current_architecture = (current_architecture & ~ MACHINE_MASK) | m68010;
4460 break;
4461 case 68020:
4462 current_architecture = (current_architecture & ~ MACHINE_MASK) | m68020;
4463 break;
4464 case 68030:
4465 current_architecture = (current_architecture & ~ MACHINE_MASK) | m68030;
4466 break;
4467 case 68040:
4468 current_architecture = (current_architecture & ~ MACHINE_MASK) | m68040;
4469 break;
4470 case 68881:
4471 current_architecture |= m68881;
4472 break;
4473 case 68882:
4474 current_architecture |= m68882;
4475 break;
4476 case 68851:
4477 current_architecture |= m68851;
4478 break;
4479
4480 default:
4481 as_bad("Unrecognised CHIP %d\n", target);
4482
4483 }
4484 demand_empty_rest_of_line();
20ec2f6c
SC		 4485}
4486
4487#endif
a39116f1 4488
20ec2f6c
SC		 4489/*
4490 * Local Variables:
4491 * comment-column: 0
4492 * fill-column: 131
4493 * End:
4494 */
4495
8b228fe9 4496/* end of tc-m68kmote.c */
GDB Binutils - Deliverables
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