Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
071742cf | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
c5dd6aab | 40 | #include "dwarf2dbg.h" |
252b5132 RH |
41 | |
42 | #ifdef DEBUG | |
43 | #define DBG(x) printf x | |
44 | #else | |
45 | #define DBG(x) | |
46 | #endif | |
47 | ||
48 | #ifdef OBJ_MAYBE_ELF | |
49 | /* Clean up namespace so we can include obj-elf.h too. */ | |
50 | static int mips_output_flavor PARAMS ((void)); | |
51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
52 | #undef OBJ_PROCESS_STAB | |
53 | #undef OUTPUT_FLAVOR | |
54 | #undef S_GET_ALIGN | |
55 | #undef S_GET_SIZE | |
56 | #undef S_SET_ALIGN | |
57 | #undef S_SET_SIZE | |
252b5132 RH |
58 | #undef obj_frob_file |
59 | #undef obj_frob_file_after_relocs | |
60 | #undef obj_frob_symbol | |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
64 | ||
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
72 | #include "elf/mips.h" | |
73 | #endif | |
74 | ||
75 | #ifndef ECOFF_DEBUGGING | |
76 | #define NO_ECOFF_DEBUGGING | |
77 | #define ECOFF_DEBUGGING 0 | |
78 | #endif | |
79 | ||
ecb4347a DJ |
80 | int mips_flag_mdebug = -1; |
81 | ||
252b5132 RH |
82 | #include "ecoff.h" |
83 | ||
84 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
85 | static char *mips_regmask_frag; | |
86 | #endif | |
87 | ||
85b51719 | 88 | #define ZERO 0 |
252b5132 RH |
89 | #define AT 1 |
90 | #define TREG 24 | |
91 | #define PIC_CALL_REG 25 | |
92 | #define KT0 26 | |
93 | #define KT1 27 | |
94 | #define GP 28 | |
95 | #define SP 29 | |
96 | #define FP 30 | |
97 | #define RA 31 | |
98 | ||
99 | #define ILLEGAL_REG (32) | |
100 | ||
101 | /* Allow override of standard little-endian ECOFF format. */ | |
102 | ||
103 | #ifndef ECOFF_LITTLE_FORMAT | |
104 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
105 | #endif | |
106 | ||
107 | extern int target_big_endian; | |
108 | ||
252b5132 RH |
109 | /* The name of the readonly data section. */ |
110 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
111 | ? ".data" \ | |
112 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
113 | ? ".rdata" \ | |
056350c6 NC |
114 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
115 | ? ".rdata" \ | |
252b5132 RH |
116 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
117 | ? ".rodata" \ | |
118 | : (abort (), "")) | |
119 | ||
a325df1d TS |
120 | /* The ABI to use. */ |
121 | enum mips_abi_level | |
122 | { | |
123 | NO_ABI = 0, | |
124 | O32_ABI, | |
125 | O64_ABI, | |
126 | N32_ABI, | |
127 | N64_ABI, | |
128 | EABI_ABI | |
129 | }; | |
130 | ||
131 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 132 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 133 | |
143d77c5 EC |
134 | /* Whether or not we have code that can call pic code. */ |
135 | int mips_abicalls = FALSE; | |
136 | ||
252b5132 RH |
137 | /* This is the set of options which may be modified by the .set |
138 | pseudo-op. We use a struct so that .set push and .set pop are more | |
139 | reliable. */ | |
140 | ||
e972090a NC |
141 | struct mips_set_options |
142 | { | |
252b5132 RH |
143 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
144 | if it has not been initialized. Changed by `.set mipsN', and the | |
145 | -mipsN command line option, and the default CPU. */ | |
146 | int isa; | |
1f25f5d3 CD |
147 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
148 | if they have not been initialized. Changed by `.set <asename>', by | |
149 | command line options, and based on the default architecture. */ | |
150 | int ase_mips3d; | |
deec1734 | 151 | int ase_mdmx; |
252b5132 RH |
152 | /* Whether we are assembling for the mips16 processor. 0 if we are |
153 | not, 1 if we are, and -1 if the value has not been initialized. | |
154 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
155 | -nomips16 command line options, and the default CPU. */ | |
156 | int mips16; | |
157 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
158 | reorder' and `.set noreorder'. */ | |
159 | int noreorder; | |
160 | /* Non-zero if we should not permit the $at ($1) register to be used | |
161 | in instructions. Changed by `.set at' and `.set noat'. */ | |
162 | int noat; | |
163 | /* Non-zero if we should warn when a macro instruction expands into | |
164 | more than one machine instruction. Changed by `.set nomacro' and | |
165 | `.set macro'. */ | |
166 | int warn_about_macros; | |
167 | /* Non-zero if we should not move instructions. Changed by `.set | |
168 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
169 | int nomove; | |
170 | /* Non-zero if we should not optimize branches by moving the target | |
171 | of the branch into the delay slot. Actually, we don't perform | |
172 | this optimization anyhow. Changed by `.set bopt' and `.set | |
173 | nobopt'. */ | |
174 | int nobopt; | |
175 | /* Non-zero if we should not autoextend mips16 instructions. | |
176 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
177 | int noautoextend; | |
a325df1d TS |
178 | /* Restrict general purpose registers and floating point registers |
179 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
180 | is passed but can changed if the assembler code uses .set mipsN. */ | |
181 | int gp32; | |
182 | int fp32; | |
252b5132 RH |
183 | }; |
184 | ||
a325df1d | 185 | /* True if -mgp32 was passed. */ |
a8e8e863 | 186 | static int file_mips_gp32 = -1; |
a325df1d TS |
187 | |
188 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 189 | static int file_mips_fp32 = -1; |
a325df1d | 190 | |
252b5132 | 191 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 192 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 193 | -1 to indicate that they have not been initialized. */ |
252b5132 | 194 | |
e972090a NC |
195 | static struct mips_set_options mips_opts = |
196 | { | |
316f5878 | 197 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 |
e7af610e | 198 | }; |
252b5132 RH |
199 | |
200 | /* These variables are filled in with the masks of registers used. | |
201 | The object format code reads them and puts them in the appropriate | |
202 | place. */ | |
203 | unsigned long mips_gprmask; | |
204 | unsigned long mips_cprmask[4]; | |
205 | ||
206 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 207 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 208 | |
a4672219 TS |
209 | /* True if -mips16 was passed or implied by arguments passed on the |
210 | command line (e.g., by -march). */ | |
211 | static int file_ase_mips16; | |
212 | ||
1f25f5d3 CD |
213 | /* True if -mips3d was passed or implied by arguments passed on the |
214 | command line (e.g., by -march). */ | |
215 | static int file_ase_mips3d; | |
216 | ||
deec1734 CD |
217 | /* True if -mdmx was passed or implied by arguments passed on the |
218 | command line (e.g., by -march). */ | |
219 | static int file_ase_mdmx; | |
220 | ||
ec68c924 EC |
221 | /* The argument of the -march= flag. The architecture we are assembling. */ |
222 | static int mips_arch = CPU_UNKNOWN; | |
316f5878 RS |
223 | static const char *mips_arch_string; |
224 | static const struct mips_cpu_info *mips_arch_info; | |
ec68c924 EC |
225 | |
226 | /* The argument of the -mtune= flag. The architecture for which we | |
227 | are optimizing. */ | |
228 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 RS |
229 | static const char *mips_tune_string; |
230 | static const struct mips_cpu_info *mips_tune_info; | |
ec68c924 | 231 | |
316f5878 | 232 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
233 | static int mips_32bitmode = 0; |
234 | ||
9ce8a5dd GRK |
235 | /* Some ISA's have delay slots for instructions which read or write |
236 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 237 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
238 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
239 | delay slot in this ISA. The uses of this macro assume that any | |
240 | ISA that has delay slots for one of these, has them for all. They | |
241 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 242 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 243 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
244 | (ISA) == ISA_MIPS1 \ |
245 | || (ISA) == ISA_MIPS2 \ | |
246 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
247 | ) |
248 | ||
316f5878 RS |
249 | /* True if the given ABI requires 32-bit registers. */ |
250 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
251 | ||
252 | /* Likewise 64-bit registers. */ | |
253 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
254 | ((ABI) == N32_ABI \ | |
255 | || (ABI) == N64_ABI \ | |
256 | || (ABI) == O64_ABI) | |
257 | ||
bdaaa2e1 | 258 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 259 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
260 | (ISA) == ISA_MIPS3 \ |
261 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 262 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 263 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
264 | ) |
265 | ||
af7ee8bf CD |
266 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
267 | instructions. */ | |
268 | #define ISA_HAS_DROR(ISA) ( \ | |
269 | 0 \ | |
270 | ) | |
271 | ||
272 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
273 | instructions. */ | |
274 | #define ISA_HAS_ROR(ISA) ( \ | |
275 | (ISA) == ISA_MIPS32R2 \ | |
276 | ) | |
277 | ||
e013f690 | 278 | #define HAVE_32BIT_GPRS \ |
316f5878 | 279 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 280 | |
e013f690 | 281 | #define HAVE_32BIT_FPRS \ |
316f5878 | 282 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
283 | |
284 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
285 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
286 | ||
316f5878 | 287 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 288 | |
316f5878 | 289 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
290 | |
291 | /* We can only have 64bit addresses if the object file format | |
292 | supports it. */ | |
afdbd6d0 CD |
293 | #define HAVE_32BIT_ADDRESSES \ |
294 | (HAVE_32BIT_GPRS \ | |
295 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
296 | || ! HAVE_64BIT_OBJECTS) \ | |
297 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
298 | |
299 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
5a7a0b7b AO |
300 | #define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \ |
301 | || HAVE_64BIT_GPRS) | |
ca4e0257 | 302 | |
f899b4b8 TS |
303 | /* Addresses are loaded in different ways, depending on the address |
304 | size in use and the ABI. N32_ABI uses additions with overflow | |
305 | checking, this allows to catch code generation errors which would | |
306 | distort the proper sign extension of the 64-bit wide registers. */ | |
307 | #define ADDRESS_ADD_INSN \ | |
308 | (HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "add" : "addu") : "daddu") | |
309 | ||
310 | #define ADDRESS_ADDI_INSN \ | |
311 | (HAVE_32BIT_ADDRESSES ? (HAVE_NEWABI ? "addi" : "addiu") : "daddiu") | |
312 | ||
313 | #define ADDRESS_LOAD_INSN \ | |
314 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
315 | ||
316 | #define ADDRESS_STORE_INSN \ | |
317 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
318 | ||
a4672219 | 319 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
320 | #define CPU_HAS_MIPS16(cpu) \ |
321 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
322 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 323 | |
1f25f5d3 CD |
324 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
325 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
326 | ) | |
327 | ||
deec1734 | 328 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 329 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
330 | ) |
331 | ||
60b63b72 RS |
332 | /* True if CPU has a dror instruction. */ |
333 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
334 | ||
335 | /* True if CPU has a ror instruction. */ | |
336 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
337 | ||
bdaaa2e1 | 338 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 339 | reads from the HI and LO registers, and thus does not |
ec68c924 | 340 | require nops to be inserted. */ |
252b5132 | 341 | |
ec68c924 | 342 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
60b63b72 | 343 | || mips_arch == CPU_VR5500 \ |
0a758a12 | 344 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
345 | ) |
346 | ||
347 | /* Whether the processor uses hardware interlocks to protect reads | |
348 | from the GPRs, and thus does not require nops to be inserted. */ | |
349 | #define gpr_interlocks \ | |
e7af610e | 350 | (mips_opts.isa != ISA_MIPS1 \ |
60b63b72 RS |
351 | || mips_arch == CPU_VR5400 \ |
352 | || mips_arch == CPU_VR5500 \ | |
ec68c924 | 353 | || mips_arch == CPU_R3900) |
252b5132 RH |
354 | |
355 | /* As with other "interlocks" this is used by hardware that has FP | |
356 | (co-processor) interlocks. */ | |
bdaaa2e1 | 357 | /* Itbl support may require additional care here. */ |
ec68c924 | 358 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
60b63b72 RS |
359 | || mips_arch == CPU_VR5400 \ |
360 | || mips_arch == CPU_VR5500 \ | |
0a758a12 | 361 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
362 | ) |
363 | ||
6b76fefe CM |
364 | /* Is this a mfhi or mflo instruction? */ |
365 | #define MF_HILO_INSN(PINFO) \ | |
366 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
367 | ||
252b5132 RH |
368 | /* MIPS PIC level. */ |
369 | ||
a161fe53 | 370 | enum mips_pic_level mips_pic; |
252b5132 | 371 | |
39c0a331 L |
372 | /* Warn about all NOPS that the assembler generates. */ |
373 | static int warn_nops = 0; | |
374 | ||
c9914766 | 375 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 376 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 377 | static int mips_big_got = 0; |
252b5132 RH |
378 | |
379 | /* 1 if trap instructions should used for overflow rather than break | |
380 | instructions. */ | |
c9914766 | 381 | static int mips_trap = 0; |
252b5132 | 382 | |
119d663a | 383 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 384 | by assembling two single width halves into two single width floating |
119d663a NC |
385 | point registers which just happen to alias the double width destination |
386 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 387 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
388 | automatically at assemble time. */ |
389 | static int mips_disable_float_construction; | |
390 | ||
252b5132 RH |
391 | /* Non-zero if any .set noreorder directives were used. */ |
392 | ||
393 | static int mips_any_noreorder; | |
394 | ||
6b76fefe CM |
395 | /* Non-zero if nops should be inserted when the register referenced in |
396 | an mfhi/mflo instruction is read in the next two instructions. */ | |
397 | static int mips_7000_hilo_fix; | |
398 | ||
252b5132 | 399 | /* The size of the small data section. */ |
156c2f8b | 400 | static unsigned int g_switch_value = 8; |
252b5132 RH |
401 | /* Whether the -G option was used. */ |
402 | static int g_switch_seen = 0; | |
403 | ||
404 | #define N_RMASK 0xc4 | |
405 | #define N_VFP 0xd4 | |
406 | ||
407 | /* If we can determine in advance that GP optimization won't be | |
408 | possible, we can skip the relaxation stuff that tries to produce | |
409 | GP-relative references. This makes delay slot optimization work | |
410 | better. | |
411 | ||
412 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
413 | gcc output. It needs to guess right for gcc, otherwise gcc |
414 | will put what it thinks is a GP-relative instruction in a branch | |
415 | delay slot. | |
252b5132 RH |
416 | |
417 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
418 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
419 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
420 | ||
421 | /* handle of the OPCODE hash table */ | |
422 | static struct hash_control *op_hash = NULL; | |
423 | ||
424 | /* The opcode hash table we use for the mips16. */ | |
425 | static struct hash_control *mips16_op_hash = NULL; | |
426 | ||
427 | /* This array holds the chars that always start a comment. If the | |
428 | pre-processor is disabled, these aren't very useful */ | |
429 | const char comment_chars[] = "#"; | |
430 | ||
431 | /* This array holds the chars that only start a comment at the beginning of | |
432 | a line. If the line seems to have the form '# 123 filename' | |
433 | .line and .file directives will appear in the pre-processed output */ | |
434 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
435 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 436 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
437 | /* Also note that C style comments are always supported. */ |
438 | const char line_comment_chars[] = "#"; | |
439 | ||
bdaaa2e1 | 440 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 441 | const char line_separator_chars[] = ";"; |
252b5132 RH |
442 | |
443 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
444 | const char EXP_CHARS[] = "eE"; | |
445 | ||
446 | /* Chars that mean this number is a floating point constant */ | |
447 | /* As in 0f12.456 */ | |
448 | /* or 0d1.2345e12 */ | |
449 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
450 | ||
451 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
452 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
453 | but nothing is ideal around here. | |
454 | */ | |
455 | ||
456 | static char *insn_error; | |
457 | ||
458 | static int auto_align = 1; | |
459 | ||
460 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
461 | offset in the stack frame from which to restore the $gp register. | |
462 | This is set by the .cprestore pseudo-op, and saved in this | |
463 | variable. */ | |
464 | static offsetT mips_cprestore_offset = -1; | |
465 | ||
6478892d TS |
466 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
467 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 468 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
469 | static offsetT mips_cpreturn_offset = -1; |
470 | static int mips_cpreturn_register = -1; | |
471 | static int mips_gp_register = GP; | |
def2e0dd | 472 | static int mips_gprel_offset = 0; |
6478892d | 473 | |
7a621144 DJ |
474 | /* Whether mips_cprestore_offset has been set in the current function |
475 | (or whether it has already been warned about, if not). */ | |
476 | static int mips_cprestore_valid = 0; | |
477 | ||
252b5132 RH |
478 | /* This is the register which holds the stack frame, as set by the |
479 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
480 | static int mips_frame_reg = SP; | |
481 | ||
7a621144 DJ |
482 | /* Whether mips_frame_reg has been set in the current function |
483 | (or whether it has already been warned about, if not). */ | |
484 | static int mips_frame_reg_valid = 0; | |
485 | ||
252b5132 RH |
486 | /* To output NOP instructions correctly, we need to keep information |
487 | about the previous two instructions. */ | |
488 | ||
489 | /* Whether we are optimizing. The default value of 2 means to remove | |
490 | unneeded NOPs and swap branch instructions when possible. A value | |
491 | of 1 means to not swap branches. A value of 0 means to always | |
492 | insert NOPs. */ | |
493 | static int mips_optimize = 2; | |
494 | ||
495 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
496 | equivalent to seeing no -g option at all. */ | |
497 | static int mips_debug = 0; | |
498 | ||
499 | /* The previous instruction. */ | |
500 | static struct mips_cl_insn prev_insn; | |
501 | ||
502 | /* The instruction before prev_insn. */ | |
503 | static struct mips_cl_insn prev_prev_insn; | |
504 | ||
505 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
506 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 507 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
508 | |
509 | /* Non-zero if prev_insn is valid. */ | |
510 | static int prev_insn_valid; | |
511 | ||
512 | /* The frag for the previous instruction. */ | |
513 | static struct frag *prev_insn_frag; | |
514 | ||
515 | /* The offset into prev_insn_frag for the previous instruction. */ | |
516 | static long prev_insn_where; | |
517 | ||
518 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 519 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
520 | |
521 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 522 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
523 | |
524 | /* Non-zero if the previous instruction was in a delay slot. */ | |
525 | static int prev_insn_is_delay_slot; | |
526 | ||
527 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
528 | static int prev_insn_unreordered; | |
529 | ||
530 | /* Non-zero if the previous instruction uses an extend opcode (if | |
531 | mips16). */ | |
532 | static int prev_insn_extended; | |
533 | ||
534 | /* Non-zero if the previous previous instruction was in a .set | |
535 | noreorder. */ | |
536 | static int prev_prev_insn_unreordered; | |
537 | ||
538 | /* If this is set, it points to a frag holding nop instructions which | |
539 | were inserted before the start of a noreorder section. If those | |
540 | nops turn out to be unnecessary, the size of the frag can be | |
541 | decreased. */ | |
542 | static fragS *prev_nop_frag; | |
543 | ||
544 | /* The number of nop instructions we created in prev_nop_frag. */ | |
545 | static int prev_nop_frag_holds; | |
546 | ||
547 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 548 | prev_nop_frag. */ |
252b5132 RH |
549 | static int prev_nop_frag_required; |
550 | ||
551 | /* The number of instructions we've seen since prev_nop_frag. */ | |
552 | static int prev_nop_frag_since; | |
553 | ||
554 | /* For ECOFF and ELF, relocations against symbols are done in two | |
555 | parts, with a HI relocation and a LO relocation. Each relocation | |
556 | has only 16 bits of space to store an addend. This means that in | |
557 | order for the linker to handle carries correctly, it must be able | |
558 | to locate both the HI and the LO relocation. This means that the | |
559 | relocations must appear in order in the relocation table. | |
560 | ||
561 | In order to implement this, we keep track of each unmatched HI | |
562 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 563 | corresponding LO relocation. */ |
252b5132 | 564 | |
e972090a NC |
565 | struct mips_hi_fixup |
566 | { | |
252b5132 RH |
567 | /* Next HI fixup. */ |
568 | struct mips_hi_fixup *next; | |
569 | /* This fixup. */ | |
570 | fixS *fixp; | |
571 | /* The section this fixup is in. */ | |
572 | segT seg; | |
573 | }; | |
574 | ||
575 | /* The list of unmatched HI relocs. */ | |
576 | ||
577 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
578 | ||
64bdfcaf RS |
579 | /* The frag containing the last explicit relocation operator. |
580 | Null if explicit relocations have not been used. */ | |
581 | ||
582 | static fragS *prev_reloc_op_frag; | |
583 | ||
252b5132 RH |
584 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
585 | ||
586 | #define X ILLEGAL_REG | |
e972090a NC |
587 | static const int mips32_to_16_reg_map[] = |
588 | { | |
252b5132 RH |
589 | X, X, 2, 3, 4, 5, 6, 7, |
590 | X, X, X, X, X, X, X, X, | |
591 | 0, 1, X, X, X, X, X, X, | |
592 | X, X, X, X, X, X, X, X | |
593 | }; | |
594 | #undef X | |
595 | ||
596 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
597 | ||
e972090a NC |
598 | static const unsigned int mips16_to_32_reg_map[] = |
599 | { | |
252b5132 RH |
600 | 16, 17, 2, 3, 4, 5, 6, 7 |
601 | }; | |
60b63b72 RS |
602 | |
603 | static int mips_fix_4122_bugs; | |
4a6a3df4 AO |
604 | |
605 | /* We don't relax branches by default, since this causes us to expand | |
606 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
607 | fail to compute the offset before expanding the macro to the most | |
608 | efficient expansion. */ | |
609 | ||
610 | static int mips_relax_branch; | |
252b5132 RH |
611 | \f |
612 | /* Since the MIPS does not have multiple forms of PC relative | |
613 | instructions, we do not have to do relaxing as is done on other | |
614 | platforms. However, we do have to handle GP relative addressing | |
615 | correctly, which turns out to be a similar problem. | |
616 | ||
617 | Every macro that refers to a symbol can occur in (at least) two | |
618 | forms, one with GP relative addressing and one without. For | |
619 | example, loading a global variable into a register generally uses | |
620 | a macro instruction like this: | |
621 | lw $4,i | |
622 | If i can be addressed off the GP register (this is true if it is in | |
623 | the .sbss or .sdata section, or if it is known to be smaller than | |
624 | the -G argument) this will generate the following instruction: | |
625 | lw $4,i($gp) | |
626 | This instruction will use a GPREL reloc. If i can not be addressed | |
627 | off the GP register, the following instruction sequence will be used: | |
628 | lui $at,i | |
629 | lw $4,i($at) | |
630 | In this case the first instruction will have a HI16 reloc, and the | |
631 | second reloc will have a LO16 reloc. Both relocs will be against | |
632 | the symbol i. | |
633 | ||
634 | The issue here is that we may not know whether i is GP addressable | |
635 | until after we see the instruction that uses it. Therefore, we | |
636 | want to be able to choose the final instruction sequence only at | |
637 | the end of the assembly. This is similar to the way other | |
638 | platforms choose the size of a PC relative instruction only at the | |
639 | end of assembly. | |
640 | ||
641 | When generating position independent code we do not use GP | |
642 | addressing in quite the same way, but the issue still arises as | |
643 | external symbols and local symbols must be handled differently. | |
644 | ||
645 | We handle these issues by actually generating both possible | |
646 | instruction sequences. The longer one is put in a frag_var with | |
647 | type rs_machine_dependent. We encode what to do with the frag in | |
648 | the subtype field. We encode (1) the number of existing bytes to | |
649 | replace, (2) the number of new bytes to use, (3) the offset from | |
650 | the start of the existing bytes to the first reloc we must generate | |
651 | (that is, the offset is applied from the start of the existing | |
652 | bytes after they are replaced by the new bytes, if any), (4) the | |
653 | offset from the start of the existing bytes to the second reloc, | |
654 | (5) whether a third reloc is needed (the third reloc is always four | |
655 | bytes after the second reloc), and (6) whether to warn if this | |
656 | variant is used (this is sometimes needed if .set nomacro or .set | |
657 | noat is in effect). All these numbers are reasonably small. | |
658 | ||
659 | Generating two instruction sequences must be handled carefully to | |
660 | ensure that delay slots are handled correctly. Fortunately, there | |
661 | are a limited number of cases. When the second instruction | |
662 | sequence is generated, append_insn is directed to maintain the | |
663 | existing delay slot information, so it continues to apply to any | |
664 | code after the second instruction sequence. This means that the | |
665 | second instruction sequence must not impose any requirements not | |
666 | required by the first instruction sequence. | |
667 | ||
668 | These variant frags are then handled in functions called by the | |
669 | machine independent code. md_estimate_size_before_relax returns | |
670 | the final size of the frag. md_convert_frag sets up the final form | |
671 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
672 | one if needed. */ | |
673 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
674 | ((relax_substateT) \ | |
675 | (((old) << 23) \ | |
676 | | ((new) << 16) \ | |
677 | | (((reloc1) + 64) << 9) \ | |
678 | | (((reloc2) + 64) << 2) \ | |
679 | | ((reloc3) ? (1 << 1) : 0) \ | |
680 | | ((warn) ? 1 : 0))) | |
681 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
682 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
683 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
684 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
685 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
686 | #define RELAX_WARN(i) ((i) & 1) | |
687 | ||
4a6a3df4 AO |
688 | /* Branch without likely bit. If label is out of range, we turn: |
689 | ||
690 | beq reg1, reg2, label | |
691 | delay slot | |
692 | ||
693 | into | |
694 | ||
695 | bne reg1, reg2, 0f | |
696 | nop | |
697 | j label | |
698 | 0: delay slot | |
699 | ||
700 | with the following opcode replacements: | |
701 | ||
702 | beq <-> bne | |
703 | blez <-> bgtz | |
704 | bltz <-> bgez | |
705 | bc1f <-> bc1t | |
706 | ||
707 | bltzal <-> bgezal (with jal label instead of j label) | |
708 | ||
709 | Even though keeping the delay slot instruction in the delay slot of | |
710 | the branch would be more efficient, it would be very tricky to do | |
711 | correctly, because we'd have to introduce a variable frag *after* | |
712 | the delay slot instruction, and expand that instead. Let's do it | |
713 | the easy way for now, even if the branch-not-taken case now costs | |
714 | one additional instruction. Out-of-range branches are not supposed | |
715 | to be common, anyway. | |
716 | ||
717 | Branch likely. If label is out of range, we turn: | |
718 | ||
719 | beql reg1, reg2, label | |
720 | delay slot (annulled if branch not taken) | |
721 | ||
722 | into | |
723 | ||
724 | beql reg1, reg2, 1f | |
725 | nop | |
726 | beql $0, $0, 2f | |
727 | nop | |
728 | 1: j[al] label | |
729 | delay slot (executed only if branch taken) | |
730 | 2: | |
731 | ||
732 | It would be possible to generate a shorter sequence by losing the | |
733 | likely bit, generating something like: | |
b34976b6 | 734 | |
4a6a3df4 AO |
735 | bne reg1, reg2, 0f |
736 | nop | |
737 | j[al] label | |
738 | delay slot (executed only if branch taken) | |
739 | 0: | |
740 | ||
741 | beql -> bne | |
742 | bnel -> beq | |
743 | blezl -> bgtz | |
744 | bgtzl -> blez | |
745 | bltzl -> bgez | |
746 | bgezl -> bltz | |
747 | bc1fl -> bc1t | |
748 | bc1tl -> bc1f | |
749 | ||
750 | bltzall -> bgezal (with jal label instead of j label) | |
751 | bgezall -> bltzal (ditto) | |
752 | ||
753 | ||
754 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 755 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
756 | ((relax_substateT) \ |
757 | (0xc0000000 \ | |
758 | | ((toofar) ? 1 : 0) \ | |
759 | | ((link) ? 2 : 0) \ | |
760 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 761 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 762 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
763 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
764 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
765 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 766 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 767 | |
252b5132 RH |
768 | /* For mips16 code, we use an entirely different form of relaxation. |
769 | mips16 supports two versions of most instructions which take | |
770 | immediate values: a small one which takes some small value, and a | |
771 | larger one which takes a 16 bit value. Since branches also follow | |
772 | this pattern, relaxing these values is required. | |
773 | ||
774 | We can assemble both mips16 and normal MIPS code in a single | |
775 | object. Therefore, we need to support this type of relaxation at | |
776 | the same time that we support the relaxation described above. We | |
777 | use the high bit of the subtype field to distinguish these cases. | |
778 | ||
779 | The information we store for this type of relaxation is the | |
780 | argument code found in the opcode file for this relocation, whether | |
781 | the user explicitly requested a small or extended form, and whether | |
782 | the relocation is in a jump or jal delay slot. That tells us the | |
783 | size of the value, and how it should be stored. We also store | |
784 | whether the fragment is considered to be extended or not. We also | |
785 | store whether this is known to be a branch to a different section, | |
786 | whether we have tried to relax this frag yet, and whether we have | |
787 | ever extended a PC relative fragment because of a shift count. */ | |
788 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
789 | (0x80000000 \ | |
790 | | ((type) & 0xff) \ | |
791 | | ((small) ? 0x100 : 0) \ | |
792 | | ((ext) ? 0x200 : 0) \ | |
793 | | ((dslot) ? 0x400 : 0) \ | |
794 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 795 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
796 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
797 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
798 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
799 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
800 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
801 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
802 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
803 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
804 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
805 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
806 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
807 | |
808 | /* Is the given value a sign-extended 32-bit value? */ | |
809 | #define IS_SEXT_32BIT_NUM(x) \ | |
810 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
811 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
812 | ||
813 | /* Is the given value a sign-extended 16-bit value? */ | |
814 | #define IS_SEXT_16BIT_NUM(x) \ | |
815 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
816 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
817 | ||
252b5132 RH |
818 | \f |
819 | /* Prototypes for static functions. */ | |
820 | ||
821 | #ifdef __STDC__ | |
822 | #define internalError() \ | |
823 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
824 | #else | |
825 | #define internalError() as_fatal (_("MIPS internal Error")); | |
826 | #endif | |
827 | ||
828 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
829 | ||
5919d012 RS |
830 | static inline bfd_boolean reloc_needs_lo_p |
831 | PARAMS ((bfd_reloc_code_real_type)); | |
832 | static inline bfd_boolean fixup_has_matching_lo_p | |
833 | PARAMS ((fixS *)); | |
b34976b6 AM |
834 | static int insn_uses_reg |
835 | PARAMS ((struct mips_cl_insn *ip, unsigned int reg, | |
836 | enum mips_regclass class)); | |
837 | static int reg_needs_delay | |
838 | PARAMS ((unsigned int)); | |
839 | static void mips16_mark_labels | |
840 | PARAMS ((void)); | |
841 | static void append_insn | |
842 | PARAMS ((char *place, struct mips_cl_insn * ip, expressionS * p, | |
5e0116d5 | 843 | bfd_reloc_code_real_type *r)); |
b34976b6 AM |
844 | static void mips_no_prev_insn |
845 | PARAMS ((int)); | |
846 | static void mips_emit_delays | |
847 | PARAMS ((bfd_boolean)); | |
252b5132 | 848 | #ifdef USE_STDARG |
b34976b6 AM |
849 | static void macro_build |
850 | PARAMS ((char *place, int *counter, expressionS * ep, const char *name, | |
851 | const char *fmt, ...)); | |
252b5132 RH |
852 | #else |
853 | static void macro_build (); | |
854 | #endif | |
b34976b6 AM |
855 | static void mips16_macro_build |
856 | PARAMS ((char *, int *, expressionS *, const char *, const char *, va_list)); | |
857 | static void macro_build_jalr | |
858 | PARAMS ((int, expressionS *)); | |
859 | static void macro_build_lui | |
860 | PARAMS ((char *place, int *counter, expressionS * ep, int regnum)); | |
861 | static void macro_build_ldst_constoffset | |
862 | PARAMS ((char *place, int *counter, expressionS * ep, const char *op, | |
863 | int valreg, int breg)); | |
864 | static void set_at | |
865 | PARAMS ((int *counter, int reg, int unsignedp)); | |
866 | static void check_absolute_expr | |
867 | PARAMS ((struct mips_cl_insn * ip, expressionS *)); | |
868 | static void load_register | |
869 | PARAMS ((int *, int, expressionS *, int)); | |
870 | static void load_address | |
871 | PARAMS ((int *, int, expressionS *, int *)); | |
872 | static void move_register | |
873 | PARAMS ((int *, int, int)); | |
874 | static void macro | |
875 | PARAMS ((struct mips_cl_insn * ip)); | |
876 | static void mips16_macro | |
877 | PARAMS ((struct mips_cl_insn * ip)); | |
252b5132 | 878 | #ifdef LOSING_COMPILER |
b34976b6 AM |
879 | static void macro2 |
880 | PARAMS ((struct mips_cl_insn * ip)); | |
252b5132 | 881 | #endif |
b34976b6 AM |
882 | static void mips_ip |
883 | PARAMS ((char *str, struct mips_cl_insn * ip)); | |
884 | static void mips16_ip | |
885 | PARAMS ((char *str, struct mips_cl_insn * ip)); | |
886 | static void mips16_immed | |
887 | PARAMS ((char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, | |
888 | bfd_boolean, unsigned long *, bfd_boolean *, unsigned short *)); | |
5e0116d5 RS |
889 | static bfd_boolean parse_relocation |
890 | PARAMS ((char **, bfd_reloc_code_real_type *)); | |
891 | static size_t my_getSmallExpression | |
892 | PARAMS ((expressionS *, bfd_reloc_code_real_type *, char *)); | |
b34976b6 AM |
893 | static void my_getExpression |
894 | PARAMS ((expressionS *, char *)); | |
ae948b86 | 895 | #ifdef OBJ_ELF |
b34976b6 AM |
896 | static int support_64bit_objects |
897 | PARAMS((void)); | |
ae948b86 | 898 | #endif |
b34976b6 AM |
899 | static void mips_set_option_string |
900 | PARAMS ((const char **, const char *)); | |
901 | static symbolS *get_symbol | |
902 | PARAMS ((void)); | |
903 | static void mips_align | |
904 | PARAMS ((int to, int fill, symbolS *label)); | |
905 | static void s_align | |
906 | PARAMS ((int)); | |
907 | static void s_change_sec | |
908 | PARAMS ((int)); | |
909 | static void s_change_section | |
910 | PARAMS ((int)); | |
911 | static void s_cons | |
912 | PARAMS ((int)); | |
913 | static void s_float_cons | |
914 | PARAMS ((int)); | |
915 | static void s_mips_globl | |
916 | PARAMS ((int)); | |
917 | static void s_option | |
918 | PARAMS ((int)); | |
919 | static void s_mipsset | |
920 | PARAMS ((int)); | |
921 | static void s_abicalls | |
922 | PARAMS ((int)); | |
923 | static void s_cpload | |
924 | PARAMS ((int)); | |
925 | static void s_cpsetup | |
926 | PARAMS ((int)); | |
927 | static void s_cplocal | |
928 | PARAMS ((int)); | |
929 | static void s_cprestore | |
930 | PARAMS ((int)); | |
931 | static void s_cpreturn | |
932 | PARAMS ((int)); | |
933 | static void s_gpvalue | |
934 | PARAMS ((int)); | |
935 | static void s_gpword | |
936 | PARAMS ((int)); | |
937 | static void s_gpdword | |
938 | PARAMS ((int)); | |
939 | static void s_cpadd | |
940 | PARAMS ((int)); | |
941 | static void s_insn | |
942 | PARAMS ((int)); | |
943 | static void md_obj_begin | |
944 | PARAMS ((void)); | |
945 | static void md_obj_end | |
946 | PARAMS ((void)); | |
947 | static long get_number | |
948 | PARAMS ((void)); | |
949 | static void s_mips_ent | |
950 | PARAMS ((int)); | |
951 | static void s_mips_end | |
952 | PARAMS ((int)); | |
953 | static void s_mips_frame | |
954 | PARAMS ((int)); | |
955 | static void s_mips_mask | |
956 | PARAMS ((int)); | |
957 | static void s_mips_stab | |
958 | PARAMS ((int)); | |
959 | static void s_mips_weakext | |
960 | PARAMS ((int)); | |
961 | static void s_mips_file | |
962 | PARAMS ((int)); | |
963 | static void s_mips_loc | |
964 | PARAMS ((int)); | |
5919d012 RS |
965 | static bfd_boolean pic_need_relax |
966 | PARAMS ((symbolS *, asection *)); | |
b34976b6 AM |
967 | static int mips16_extended_frag |
968 | PARAMS ((fragS *, asection *, long)); | |
4a6a3df4 | 969 | static int relaxed_branch_length (fragS *, asection *, int); |
b34976b6 AM |
970 | static int validate_mips_insn |
971 | PARAMS ((const struct mips_opcode *)); | |
972 | static void show | |
973 | PARAMS ((FILE *, const char *, int *, int *)); | |
add55e1f | 974 | #ifdef OBJ_ELF |
b34976b6 AM |
975 | static int mips_need_elf_addend_fixup |
976 | PARAMS ((fixS *)); | |
add55e1f | 977 | #endif |
e7af610e NC |
978 | |
979 | /* Table and functions used to map between CPU/ISA names, and | |
980 | ISA levels, and CPU numbers. */ | |
981 | ||
e972090a NC |
982 | struct mips_cpu_info |
983 | { | |
e7af610e NC |
984 | const char *name; /* CPU or ISA name. */ |
985 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
986 | int isa; /* ISA level. */ | |
987 | int cpu; /* CPU number (default CPU if ISA). */ | |
988 | }; | |
989 | ||
b34976b6 AM |
990 | static void mips_set_architecture |
991 | PARAMS ((const struct mips_cpu_info *)); | |
992 | static void mips_set_tune | |
993 | PARAMS ((const struct mips_cpu_info *)); | |
994 | static bfd_boolean mips_strict_matching_cpu_name_p | |
995 | PARAMS ((const char *, const char *)); | |
996 | static bfd_boolean mips_matching_cpu_name_p | |
997 | PARAMS ((const char *, const char *)); | |
998 | static const struct mips_cpu_info *mips_parse_cpu | |
999 | PARAMS ((const char *, const char *)); | |
1000 | static const struct mips_cpu_info *mips_cpu_info_from_isa | |
1001 | PARAMS ((int)); | |
252b5132 RH |
1002 | \f |
1003 | /* Pseudo-op table. | |
1004 | ||
1005 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1006 | should be defined here, but are currently unsupported: .alias, | |
1007 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1008 | ||
1009 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1010 | specific to the type of debugging information being generated, and | |
1011 | should be defined by the object format: .aent, .begin, .bend, | |
1012 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1013 | .vreg. | |
1014 | ||
1015 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1016 | not MIPS CPU specific, but are also not specific to the object file | |
1017 | format. This file is probably the best place to define them, but | |
1018 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1019 | .struct. */ | |
1020 | ||
e972090a NC |
1021 | static const pseudo_typeS mips_pseudo_table[] = |
1022 | { | |
beae10d5 | 1023 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1024 | {"option", s_option, 0}, |
1025 | {"set", s_mipsset, 0}, | |
1026 | {"rdata", s_change_sec, 'r'}, | |
1027 | {"sdata", s_change_sec, 's'}, | |
1028 | {"livereg", s_ignore, 0}, | |
1029 | {"abicalls", s_abicalls, 0}, | |
1030 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1031 | {"cpsetup", s_cpsetup, 0}, |
1032 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1033 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1034 | {"cpreturn", s_cpreturn, 0}, |
1035 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1036 | {"gpword", s_gpword, 0}, |
10181a0d | 1037 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1038 | {"cpadd", s_cpadd, 0}, |
1039 | {"insn", s_insn, 0}, | |
1040 | ||
beae10d5 | 1041 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1042 | chips. */ |
1043 | {"asciiz", stringer, 1}, | |
1044 | {"bss", s_change_sec, 'b'}, | |
1045 | {"err", s_err, 0}, | |
1046 | {"half", s_cons, 1}, | |
1047 | {"dword", s_cons, 3}, | |
1048 | {"weakext", s_mips_weakext, 0}, | |
1049 | ||
beae10d5 | 1050 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1051 | here for one reason or another. */ |
1052 | {"align", s_align, 0}, | |
1053 | {"byte", s_cons, 0}, | |
1054 | {"data", s_change_sec, 'd'}, | |
1055 | {"double", s_float_cons, 'd'}, | |
1056 | {"float", s_float_cons, 'f'}, | |
1057 | {"globl", s_mips_globl, 0}, | |
1058 | {"global", s_mips_globl, 0}, | |
1059 | {"hword", s_cons, 1}, | |
1060 | {"int", s_cons, 2}, | |
1061 | {"long", s_cons, 2}, | |
1062 | {"octa", s_cons, 4}, | |
1063 | {"quad", s_cons, 3}, | |
cca86cc8 | 1064 | {"section", s_change_section, 0}, |
252b5132 RH |
1065 | {"short", s_cons, 1}, |
1066 | {"single", s_float_cons, 'f'}, | |
1067 | {"stabn", s_mips_stab, 'n'}, | |
1068 | {"text", s_change_sec, 't'}, | |
1069 | {"word", s_cons, 2}, | |
add56521 | 1070 | |
add56521 | 1071 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1072 | |
43841e91 | 1073 | { NULL, NULL, 0 }, |
252b5132 RH |
1074 | }; |
1075 | ||
e972090a NC |
1076 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1077 | { | |
beae10d5 KH |
1078 | /* These pseudo-ops should be defined by the object file format. |
1079 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1080 | {"aent", s_mips_ent, 1}, |
1081 | {"bgnb", s_ignore, 0}, | |
1082 | {"end", s_mips_end, 0}, | |
1083 | {"endb", s_ignore, 0}, | |
1084 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1085 | {"file", s_mips_file, 0}, |
252b5132 RH |
1086 | {"fmask", s_mips_mask, 'F'}, |
1087 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1088 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1089 | {"mask", s_mips_mask, 'R'}, |
1090 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1091 | { NULL, NULL, 0 }, |
252b5132 RH |
1092 | }; |
1093 | ||
1094 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
1095 | ||
1096 | void | |
1097 | mips_pop_insert () | |
1098 | { | |
1099 | pop_insert (mips_pseudo_table); | |
1100 | if (! ECOFF_DEBUGGING) | |
1101 | pop_insert (mips_nonecoff_pseudo_table); | |
1102 | } | |
1103 | \f | |
1104 | /* Symbols labelling the current insn. */ | |
1105 | ||
e972090a NC |
1106 | struct insn_label_list |
1107 | { | |
252b5132 RH |
1108 | struct insn_label_list *next; |
1109 | symbolS *label; | |
1110 | }; | |
1111 | ||
1112 | static struct insn_label_list *insn_labels; | |
1113 | static struct insn_label_list *free_insn_labels; | |
1114 | ||
1115 | static void mips_clear_insn_labels PARAMS ((void)); | |
1116 | ||
1117 | static inline void | |
1118 | mips_clear_insn_labels () | |
1119 | { | |
1120 | register struct insn_label_list **pl; | |
1121 | ||
1122 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1123 | ; | |
1124 | *pl = insn_labels; | |
1125 | insn_labels = NULL; | |
1126 | } | |
1127 | \f | |
1128 | static char *expr_end; | |
1129 | ||
1130 | /* Expressions which appear in instructions. These are set by | |
1131 | mips_ip. */ | |
1132 | ||
1133 | static expressionS imm_expr; | |
1134 | static expressionS offset_expr; | |
1135 | ||
1136 | /* Relocs associated with imm_expr and offset_expr. */ | |
1137 | ||
f6688943 TS |
1138 | static bfd_reloc_code_real_type imm_reloc[3] |
1139 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1140 | static bfd_reloc_code_real_type offset_reloc[3] | |
1141 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1142 | |
252b5132 RH |
1143 | /* These are set by mips16_ip if an explicit extension is used. */ |
1144 | ||
b34976b6 | 1145 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1146 | |
7ed4a06a | 1147 | #ifdef OBJ_ELF |
ecb4347a DJ |
1148 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1149 | ECOFF debugging. */ | |
252b5132 RH |
1150 | |
1151 | static segT pdr_seg; | |
7ed4a06a | 1152 | #endif |
252b5132 | 1153 | |
e013f690 TS |
1154 | /* The default target format to use. */ |
1155 | ||
1156 | const char * | |
1157 | mips_target_format () | |
1158 | { | |
1159 | switch (OUTPUT_FLAVOR) | |
1160 | { | |
1161 | case bfd_target_aout_flavour: | |
1162 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1163 | case bfd_target_ecoff_flavour: | |
1164 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1165 | case bfd_target_coff_flavour: | |
1166 | return "pe-mips"; | |
1167 | case bfd_target_elf_flavour: | |
1168 | #ifdef TE_TMIPS | |
cfe86eaa | 1169 | /* This is traditional mips. */ |
e013f690 | 1170 | return (target_big_endian |
cfe86eaa TS |
1171 | ? (HAVE_64BIT_OBJECTS |
1172 | ? "elf64-tradbigmips" | |
1173 | : (HAVE_NEWABI | |
1174 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1175 | : (HAVE_64BIT_OBJECTS | |
1176 | ? "elf64-tradlittlemips" | |
1177 | : (HAVE_NEWABI | |
1178 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1179 | #else |
1180 | return (target_big_endian | |
cfe86eaa TS |
1181 | ? (HAVE_64BIT_OBJECTS |
1182 | ? "elf64-bigmips" | |
1183 | : (HAVE_NEWABI | |
1184 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1185 | : (HAVE_64BIT_OBJECTS | |
1186 | ? "elf64-littlemips" | |
1187 | : (HAVE_NEWABI | |
1188 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1189 | #endif |
1190 | default: | |
1191 | abort (); | |
1192 | return NULL; | |
1193 | } | |
1194 | } | |
1195 | ||
156c2f8b NC |
1196 | /* This function is called once, at assembler startup time. It should |
1197 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1198 | ||
252b5132 RH |
1199 | void |
1200 | md_begin () | |
1201 | { | |
252b5132 | 1202 | register const char *retval = NULL; |
156c2f8b | 1203 | int i = 0; |
252b5132 | 1204 | int broken = 0; |
1f25f5d3 | 1205 | |
ec68c924 | 1206 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1207 | as_warn (_("Could not set architecture and machine")); |
1208 | ||
252b5132 RH |
1209 | op_hash = hash_new (); |
1210 | ||
1211 | for (i = 0; i < NUMOPCODES;) | |
1212 | { | |
1213 | const char *name = mips_opcodes[i].name; | |
1214 | ||
1215 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1216 | if (retval != NULL) | |
1217 | { | |
1218 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1219 | mips_opcodes[i].name, retval); | |
1220 | /* Probably a memory allocation problem? Give up now. */ | |
1221 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1222 | } | |
1223 | do | |
1224 | { | |
1225 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1226 | { | |
1227 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1228 | broken = 1; | |
1229 | } | |
1230 | ++i; | |
1231 | } | |
1232 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1233 | } | |
1234 | ||
1235 | mips16_op_hash = hash_new (); | |
1236 | ||
1237 | i = 0; | |
1238 | while (i < bfd_mips16_num_opcodes) | |
1239 | { | |
1240 | const char *name = mips16_opcodes[i].name; | |
1241 | ||
1242 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1243 | if (retval != NULL) | |
1244 | as_fatal (_("internal: can't hash `%s': %s"), | |
1245 | mips16_opcodes[i].name, retval); | |
1246 | do | |
1247 | { | |
1248 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1249 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1250 | != mips16_opcodes[i].match)) | |
1251 | { | |
1252 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1253 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1254 | broken = 1; | |
1255 | } | |
1256 | ++i; | |
1257 | } | |
1258 | while (i < bfd_mips16_num_opcodes | |
1259 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1260 | } | |
1261 | ||
1262 | if (broken) | |
1263 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1264 | ||
1265 | /* We add all the general register names to the symbol table. This | |
1266 | helps us detect invalid uses of them. */ | |
1267 | for (i = 0; i < 32; i++) | |
1268 | { | |
1269 | char buf[5]; | |
1270 | ||
1271 | sprintf (buf, "$%d", i); | |
1272 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1273 | &zero_address_frag)); | |
1274 | } | |
76db943d TS |
1275 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1276 | &zero_address_frag)); | |
252b5132 RH |
1277 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1278 | &zero_address_frag)); | |
1279 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1280 | &zero_address_frag)); | |
1281 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1282 | &zero_address_frag)); | |
1283 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1284 | &zero_address_frag)); | |
1285 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1286 | &zero_address_frag)); | |
1287 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1288 | &zero_address_frag)); | |
85b51719 TS |
1289 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1290 | &zero_address_frag)); | |
252b5132 RH |
1291 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1292 | &zero_address_frag)); | |
1293 | ||
6047c971 AO |
1294 | /* If we don't add these register names to the symbol table, they |
1295 | may end up being added as regular symbols by operand(), and then | |
1296 | make it to the object file as undefined in case they're not | |
1297 | regarded as local symbols. They're local in o32, since `$' is a | |
1298 | local symbol prefix, but not in n32 or n64. */ | |
1299 | for (i = 0; i < 8; i++) | |
1300 | { | |
1301 | char buf[6]; | |
1302 | ||
1303 | sprintf (buf, "$fcc%i", i); | |
1304 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1305 | &zero_address_frag)); | |
1306 | } | |
1307 | ||
b34976b6 | 1308 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1309 | |
1310 | mips_gprmask = 0; | |
1311 | mips_cprmask[0] = 0; | |
1312 | mips_cprmask[1] = 0; | |
1313 | mips_cprmask[2] = 0; | |
1314 | mips_cprmask[3] = 0; | |
1315 | ||
1316 | /* set the default alignment for the text section (2**2) */ | |
1317 | record_alignment (text_section, 2); | |
1318 | ||
1319 | if (USE_GLOBAL_POINTER_OPT) | |
1320 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1321 | ||
1322 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1323 | { | |
1324 | /* On a native system, sections must be aligned to 16 byte | |
1325 | boundaries. When configured for an embedded ELF target, we | |
1326 | don't bother. */ | |
1327 | if (strcmp (TARGET_OS, "elf") != 0) | |
1328 | { | |
1329 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1330 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1331 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1332 | } | |
1333 | ||
1334 | /* Create a .reginfo section for register masks and a .mdebug | |
1335 | section for debugging information. */ | |
1336 | { | |
1337 | segT seg; | |
1338 | subsegT subseg; | |
1339 | flagword flags; | |
1340 | segT sec; | |
1341 | ||
1342 | seg = now_seg; | |
1343 | subseg = now_subseg; | |
1344 | ||
1345 | /* The ABI says this section should be loaded so that the | |
1346 | running program can access it. However, we don't load it | |
1347 | if we are configured for an embedded target */ | |
1348 | flags = SEC_READONLY | SEC_DATA; | |
1349 | if (strcmp (TARGET_OS, "elf") != 0) | |
1350 | flags |= SEC_ALLOC | SEC_LOAD; | |
1351 | ||
316f5878 | 1352 | if (mips_abi != N64_ABI) |
252b5132 RH |
1353 | { |
1354 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1355 | ||
195325d2 TS |
1356 | bfd_set_section_flags (stdoutput, sec, flags); |
1357 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1358 | |
252b5132 RH |
1359 | #ifdef OBJ_ELF |
1360 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1361 | #endif | |
1362 | } | |
1363 | else | |
1364 | { | |
1365 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1366 | .reginfo section. */ | |
1367 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1368 | bfd_set_section_flags (stdoutput, sec, flags); |
1369 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1370 | |
1371 | #ifdef OBJ_ELF | |
1372 | /* Set up the option header. */ | |
1373 | { | |
1374 | Elf_Internal_Options opthdr; | |
1375 | char *f; | |
1376 | ||
1377 | opthdr.kind = ODK_REGINFO; | |
1378 | opthdr.size = (sizeof (Elf_External_Options) | |
1379 | + sizeof (Elf64_External_RegInfo)); | |
1380 | opthdr.section = 0; | |
1381 | opthdr.info = 0; | |
1382 | f = frag_more (sizeof (Elf_External_Options)); | |
1383 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1384 | (Elf_External_Options *) f); | |
1385 | ||
1386 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1387 | } | |
1388 | #endif | |
1389 | } | |
1390 | ||
1391 | if (ECOFF_DEBUGGING) | |
1392 | { | |
1393 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1394 | (void) bfd_set_section_flags (stdoutput, sec, | |
1395 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1396 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1397 | } | |
ecb4347a DJ |
1398 | #ifdef OBJ_ELF |
1399 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1400 | { | |
1401 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1402 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1403 | SEC_READONLY | SEC_RELOC | |
1404 | | SEC_DEBUGGING); | |
1405 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1406 | } | |
252b5132 RH |
1407 | #endif |
1408 | ||
1409 | subseg_set (seg, subseg); | |
1410 | } | |
1411 | } | |
1412 | ||
1413 | if (! ECOFF_DEBUGGING) | |
1414 | md_obj_begin (); | |
1415 | } | |
1416 | ||
1417 | void | |
1418 | md_mips_end () | |
1419 | { | |
1420 | if (! ECOFF_DEBUGGING) | |
1421 | md_obj_end (); | |
1422 | } | |
1423 | ||
1424 | void | |
1425 | md_assemble (str) | |
1426 | char *str; | |
1427 | { | |
1428 | struct mips_cl_insn insn; | |
f6688943 TS |
1429 | bfd_reloc_code_real_type unused_reloc[3] |
1430 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1431 | |
1432 | imm_expr.X_op = O_absent; | |
252b5132 | 1433 | offset_expr.X_op = O_absent; |
f6688943 TS |
1434 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1435 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1436 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1437 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1438 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1439 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1440 | |
1441 | if (mips_opts.mips16) | |
1442 | mips16_ip (str, &insn); | |
1443 | else | |
1444 | { | |
1445 | mips_ip (str, &insn); | |
beae10d5 KH |
1446 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1447 | str, insn.insn_opcode)); | |
252b5132 RH |
1448 | } |
1449 | ||
1450 | if (insn_error) | |
1451 | { | |
1452 | as_bad ("%s `%s'", insn_error, str); | |
1453 | return; | |
1454 | } | |
1455 | ||
1456 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1457 | { | |
1458 | if (mips_opts.mips16) | |
1459 | mips16_macro (&insn); | |
1460 | else | |
1461 | macro (&insn); | |
1462 | } | |
1463 | else | |
1464 | { | |
1465 | if (imm_expr.X_op != O_absent) | |
5e0116d5 | 1466 | append_insn (NULL, &insn, &imm_expr, imm_reloc); |
252b5132 | 1467 | else if (offset_expr.X_op != O_absent) |
5e0116d5 | 1468 | append_insn (NULL, &insn, &offset_expr, offset_reloc); |
252b5132 | 1469 | else |
5e0116d5 | 1470 | append_insn (NULL, &insn, NULL, unused_reloc); |
252b5132 RH |
1471 | } |
1472 | } | |
1473 | ||
5919d012 RS |
1474 | /* Return true if the given relocation might need a matching %lo(). |
1475 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1476 | applied to local symbols. */ | |
1477 | ||
1478 | static inline bfd_boolean | |
1479 | reloc_needs_lo_p (reloc) | |
1480 | bfd_reloc_code_real_type reloc; | |
1481 | { | |
1482 | return (reloc == BFD_RELOC_HI16_S | |
1483 | || reloc == BFD_RELOC_MIPS_GOT16); | |
1484 | } | |
1485 | ||
1486 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1487 | relocation. */ | |
1488 | ||
1489 | static inline bfd_boolean | |
1490 | fixup_has_matching_lo_p (fixp) | |
1491 | fixS *fixp; | |
1492 | { | |
1493 | return (fixp->fx_next != NULL | |
1494 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1495 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1496 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1497 | } | |
1498 | ||
252b5132 RH |
1499 | /* See whether instruction IP reads register REG. CLASS is the type |
1500 | of register. */ | |
1501 | ||
1502 | static int | |
1503 | insn_uses_reg (ip, reg, class) | |
1504 | struct mips_cl_insn *ip; | |
1505 | unsigned int reg; | |
1506 | enum mips_regclass class; | |
1507 | { | |
1508 | if (class == MIPS16_REG) | |
1509 | { | |
1510 | assert (mips_opts.mips16); | |
1511 | reg = mips16_to_32_reg_map[reg]; | |
1512 | class = MIPS_GR_REG; | |
1513 | } | |
1514 | ||
85b51719 TS |
1515 | /* Don't report on general register ZERO, since it never changes. */ |
1516 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1517 | return 0; |
1518 | ||
1519 | if (class == MIPS_FP_REG) | |
1520 | { | |
1521 | assert (! mips_opts.mips16); | |
1522 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1523 | This is not optimal, because it will introduce an unnecessary | |
1524 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1525 | need to distinguish reading both $f0 and $f1 or just one of | |
1526 | them. Note that we don't have to check the other way, | |
1527 | because there is no instruction that sets both $f0 and $f1 | |
1528 | and requires a delay. */ | |
1529 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1530 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1531 | == (reg &~ (unsigned) 1))) | |
1532 | return 1; | |
1533 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1534 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1535 | == (reg &~ (unsigned) 1))) | |
1536 | return 1; | |
1537 | } | |
1538 | else if (! mips_opts.mips16) | |
1539 | { | |
1540 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1541 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1542 | return 1; | |
1543 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1544 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1545 | return 1; | |
1546 | } | |
1547 | else | |
1548 | { | |
1549 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1550 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1551 | & MIPS16OP_MASK_RX)] | |
1552 | == reg)) | |
1553 | return 1; | |
1554 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1555 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1556 | & MIPS16OP_MASK_RY)] | |
1557 | == reg)) | |
1558 | return 1; | |
1559 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1560 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1561 | & MIPS16OP_MASK_MOVE32Z)] | |
1562 | == reg)) | |
1563 | return 1; | |
1564 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1565 | return 1; | |
1566 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1567 | return 1; | |
1568 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1569 | return 1; | |
1570 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1571 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1572 | & MIPS16OP_MASK_REGR32) == reg) | |
1573 | return 1; | |
1574 | } | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
1579 | /* This function returns true if modifying a register requires a | |
1580 | delay. */ | |
1581 | ||
1582 | static int | |
1583 | reg_needs_delay (reg) | |
156c2f8b | 1584 | unsigned int reg; |
252b5132 RH |
1585 | { |
1586 | unsigned long prev_pinfo; | |
1587 | ||
1588 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1589 | if (! mips_opts.noreorder | |
9ce8a5dd | 1590 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1591 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1592 | || (! gpr_interlocks | |
1593 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1594 | { | |
1595 | /* A load from a coprocessor or from memory. All load | |
1596 | delays delay the use of general register rt for one | |
1597 | instruction on the r3000. The r6000 and r4000 use | |
1598 | interlocks. */ | |
bdaaa2e1 | 1599 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1600 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1601 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1602 | return 1; | |
1603 | } | |
1604 | ||
1605 | return 0; | |
1606 | } | |
1607 | ||
1608 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1609 | handle them specially, such as generating jalx instructions when | |
1610 | needed. We also make them odd for the duration of the assembly, in | |
1611 | order to generate the right sort of code. We will make them even | |
1612 | in the adjust_symtab routine, while leaving them marked. This is | |
1613 | convenient for the debugger and the disassembler. The linker knows | |
1614 | to make them odd again. */ | |
1615 | ||
1616 | static void | |
1617 | mips16_mark_labels () | |
1618 | { | |
1619 | if (mips_opts.mips16) | |
1620 | { | |
1621 | struct insn_label_list *l; | |
98aa84af | 1622 | valueT val; |
252b5132 RH |
1623 | |
1624 | for (l = insn_labels; l != NULL; l = l->next) | |
1625 | { | |
1626 | #ifdef OBJ_ELF | |
1627 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1628 | S_SET_OTHER (l->label, STO_MIPS16); | |
1629 | #endif | |
98aa84af AM |
1630 | val = S_GET_VALUE (l->label); |
1631 | if ((val & 1) == 0) | |
1632 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1633 | } |
1634 | } | |
1635 | } | |
1636 | ||
1637 | /* Output an instruction. PLACE is where to put the instruction; if | |
1638 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1639 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1640 | used with RELOC_TYPE. */ | |
1641 | ||
1642 | static void | |
5e0116d5 | 1643 | append_insn (place, ip, address_expr, reloc_type) |
252b5132 RH |
1644 | char *place; |
1645 | struct mips_cl_insn *ip; | |
1646 | expressionS *address_expr; | |
f6688943 | 1647 | bfd_reloc_code_real_type *reloc_type; |
252b5132 RH |
1648 | { |
1649 | register unsigned long prev_pinfo, pinfo; | |
1650 | char *f; | |
f6688943 | 1651 | fixS *fixp[3]; |
252b5132 | 1652 | int nops = 0; |
f5040a92 | 1653 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1654 | |
1655 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1656 | mips16_mark_labels (); |
252b5132 RH |
1657 | |
1658 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1659 | pinfo = ip->insn_mo->pinfo; | |
1660 | ||
1661 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1662 | { | |
1663 | int prev_prev_nop; | |
1664 | ||
1665 | /* If the previous insn required any delay slots, see if we need | |
1666 | to insert a NOP or two. There are eight kinds of possible | |
1667 | hazards, of which an instruction can have at most one type. | |
1668 | (1) a load from memory delay | |
1669 | (2) a load from a coprocessor delay | |
1670 | (3) an unconditional branch delay | |
1671 | (4) a conditional branch delay | |
1672 | (5) a move to coprocessor register delay | |
1673 | (6) a load coprocessor register from memory delay | |
1674 | (7) a coprocessor condition code delay | |
1675 | (8) a HI/LO special register delay | |
1676 | ||
1677 | There are a lot of optimizations we could do that we don't. | |
1678 | In particular, we do not, in general, reorder instructions. | |
1679 | If you use gcc with optimization, it will reorder | |
1680 | instructions and generally do much more optimization then we | |
1681 | do here; repeating all that work in the assembler would only | |
1682 | benefit hand written assembly code, and does not seem worth | |
1683 | it. */ | |
1684 | ||
1685 | /* This is how a NOP is emitted. */ | |
1686 | #define emit_nop() \ | |
1687 | (mips_opts.mips16 \ | |
1688 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1689 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1690 | ||
1691 | /* The previous insn might require a delay slot, depending upon | |
1692 | the contents of the current insn. */ | |
1693 | if (! mips_opts.mips16 | |
9ce8a5dd | 1694 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1695 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1696 | && ! cop_interlocks) | |
1697 | || (! gpr_interlocks | |
1698 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1699 | { | |
1700 | /* A load from a coprocessor or from memory. All load | |
1701 | delays delay the use of general register rt for one | |
1702 | instruction on the r3000. The r6000 and r4000 use | |
1703 | interlocks. */ | |
beae10d5 | 1704 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1705 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1706 | if (mips_optimize == 0 | |
1707 | || insn_uses_reg (ip, | |
1708 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1709 | & OP_MASK_RT), | |
1710 | MIPS_GR_REG)) | |
1711 | ++nops; | |
1712 | } | |
1713 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1714 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1715 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1716 | && ! cop_interlocks) |
e7af610e | 1717 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1718 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1719 | { | |
1720 | /* A generic coprocessor delay. The previous instruction | |
1721 | modified a coprocessor general or control register. If | |
1722 | it modified a control register, we need to avoid any | |
1723 | coprocessor instruction (this is probably not always | |
1724 | required, but it sometimes is). If it modified a general | |
1725 | register, we avoid using that register. | |
1726 | ||
1727 | On the r6000 and r4000 loading a coprocessor register | |
1728 | from memory is interlocked, and does not require a delay. | |
1729 | ||
1730 | This case is not handled very well. There is no special | |
1731 | knowledge of CP0 handling, and the coprocessors other | |
1732 | than the floating point unit are not distinguished at | |
1733 | all. */ | |
1734 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1735 | Need to modify this to include knowledge about |
252b5132 RH |
1736 | user specified delays! */ |
1737 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1738 | { | |
1739 | if (mips_optimize == 0 | |
1740 | || insn_uses_reg (ip, | |
1741 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1742 | & OP_MASK_FT), | |
1743 | MIPS_FP_REG)) | |
1744 | ++nops; | |
1745 | } | |
1746 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1747 | { | |
1748 | if (mips_optimize == 0 | |
1749 | || insn_uses_reg (ip, | |
1750 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1751 | & OP_MASK_FS), | |
1752 | MIPS_FP_REG)) | |
1753 | ++nops; | |
1754 | } | |
1755 | else | |
1756 | { | |
1757 | /* We don't know exactly what the previous instruction | |
1758 | does. If the current instruction uses a coprocessor | |
1759 | register, we must insert a NOP. If previous | |
1760 | instruction may set the condition codes, and the | |
1761 | current instruction uses them, we must insert two | |
1762 | NOPS. */ | |
bdaaa2e1 | 1763 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1764 | if (mips_optimize == 0 |
1765 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1766 | && (pinfo & INSN_READ_COND_CODE))) | |
1767 | nops += 2; | |
1768 | else if (pinfo & INSN_COP) | |
1769 | ++nops; | |
1770 | } | |
1771 | } | |
1772 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1773 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1774 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1775 | && ! cop_interlocks) | |
1776 | { | |
1777 | /* The previous instruction sets the coprocessor condition | |
1778 | codes, but does not require a general coprocessor delay | |
1779 | (this means it is a floating point comparison | |
1780 | instruction). If this instruction uses the condition | |
1781 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1782 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1783 | if (mips_optimize == 0 |
1784 | || (pinfo & INSN_READ_COND_CODE)) | |
1785 | ++nops; | |
1786 | } | |
6b76fefe CM |
1787 | |
1788 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1789 | previous insn was an mfhi/mflo and the current insn | |
1790 | reads the register that the mfhi/mflo wrote to, then | |
1791 | insert two nops. */ | |
1792 | ||
1793 | else if (mips_7000_hilo_fix | |
1794 | && MF_HILO_INSN (prev_pinfo) | |
1795 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1796 | & OP_MASK_RD), |
1797 | MIPS_GR_REG)) | |
6b76fefe CM |
1798 | { |
1799 | nops += 2; | |
1800 | } | |
1801 | ||
1802 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1803 | 2nd previous insn was an mfhi/mflo and the current insn | |
1804 | reads the register that the mfhi/mflo wrote to, then | |
1805 | insert one nop. */ | |
1806 | ||
1807 | else if (mips_7000_hilo_fix | |
1808 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1809 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1810 | & OP_MASK_RD), | |
1811 | MIPS_GR_REG)) | |
bdaaa2e1 | 1812 | |
6b76fefe | 1813 | { |
f9419b05 | 1814 | ++nops; |
6b76fefe | 1815 | } |
bdaaa2e1 | 1816 | |
252b5132 RH |
1817 | else if (prev_pinfo & INSN_READ_LO) |
1818 | { | |
1819 | /* The previous instruction reads the LO register; if the | |
1820 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1821 | insert two NOPS. Some newer processors have interlocks. |
1822 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1823 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1824 | though the tx39's divide insns still do require the |
1825 | delay. */ | |
252b5132 | 1826 | if (! (hilo_interlocks |
ec68c924 | 1827 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1828 | && (mips_optimize == 0 |
1829 | || (pinfo & INSN_WRITE_LO))) | |
1830 | nops += 2; | |
1831 | /* Most mips16 branch insns don't have a delay slot. | |
1832 | If a read from LO is immediately followed by a branch | |
1833 | to a write to LO we have a read followed by a write | |
1834 | less than 2 insns away. We assume the target of | |
1835 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1836 | between a read and an immediately following branch. */ |
252b5132 RH |
1837 | else if (mips_opts.mips16 |
1838 | && (mips_optimize == 0 | |
1839 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1840 | ++nops; |
252b5132 RH |
1841 | } |
1842 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1843 | { | |
1844 | /* The previous instruction reads the HI register; if the | |
1845 | current instruction writes to the HI register, we must | |
1846 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1847 | Also the note tx39's multiply above. */ |
252b5132 | 1848 | if (! (hilo_interlocks |
ec68c924 | 1849 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1850 | && (mips_optimize == 0 |
1851 | || (pinfo & INSN_WRITE_HI))) | |
1852 | nops += 2; | |
1853 | /* Most mips16 branch insns don't have a delay slot. | |
1854 | If a read from HI is immediately followed by a branch | |
1855 | to a write to HI we have a read followed by a write | |
1856 | less than 2 insns away. We assume the target of | |
1857 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1858 | between a read and an immediately following branch. */ |
252b5132 RH |
1859 | else if (mips_opts.mips16 |
1860 | && (mips_optimize == 0 | |
1861 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1862 | ++nops; |
252b5132 RH |
1863 | } |
1864 | ||
1865 | /* If the previous instruction was in a noreorder section, then | |
1866 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1867 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1868 | if (prev_insn_unreordered) |
1869 | nops = 0; | |
1870 | ||
1871 | /* There are two cases which require two intervening | |
1872 | instructions: 1) setting the condition codes using a move to | |
1873 | coprocessor instruction which requires a general coprocessor | |
1874 | delay and then reading the condition codes 2) reading the HI | |
1875 | or LO register and then writing to it (except on processors | |
1876 | which have interlocks). If we are not already emitting a NOP | |
1877 | instruction, we must check for these cases compared to the | |
1878 | instruction previous to the previous instruction. */ | |
1879 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1880 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1881 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1882 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1883 | && (pinfo & INSN_READ_COND_CODE) | |
1884 | && ! cop_interlocks) | |
1885 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1886 | && (pinfo & INSN_WRITE_LO) | |
1887 | && ! (hilo_interlocks | |
ec68c924 | 1888 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1889 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1890 | && (pinfo & INSN_WRITE_HI) | |
1891 | && ! (hilo_interlocks | |
ec68c924 | 1892 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1893 | prev_prev_nop = 1; |
1894 | else | |
1895 | prev_prev_nop = 0; | |
1896 | ||
1897 | if (prev_prev_insn_unreordered) | |
1898 | prev_prev_nop = 0; | |
1899 | ||
1900 | if (prev_prev_nop && nops == 0) | |
1901 | ++nops; | |
1902 | ||
60b63b72 RS |
1903 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
1904 | { | |
1905 | /* We're out of bits in pinfo, so we must resort to string | |
1906 | ops here. Shortcuts are selected based on opcodes being | |
1907 | limited to the VR4122 instruction set. */ | |
1908 | int min_nops = 0; | |
1909 | const char *pn = prev_insn.insn_mo->name; | |
1910 | const char *tn = ip->insn_mo->name; | |
1911 | if (strncmp(pn, "macc", 4) == 0 | |
1912 | || strncmp(pn, "dmacc", 5) == 0) | |
1913 | { | |
1914 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1915 | if (strstr (tn, "div")) | |
1916 | { | |
1917 | min_nops = 1; | |
1918 | } | |
1919 | ||
1920 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ | |
1921 | if (pn[0] == 'd' /* dmacc */ | |
1922 | && (strncmp(tn, "dmult", 5) == 0 | |
1923 | || strncmp(tn, "dmacc", 5) == 0)) | |
1924 | { | |
1925 | min_nops = 1; | |
1926 | } | |
1927 | ||
1928 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1929 | if (strcmp (tn, "mtlo") == 0 | |
1930 | || strcmp (tn, "mthi") == 0) | |
1931 | { | |
1932 | min_nops = 1; | |
1933 | } | |
1934 | ||
1935 | } | |
1936 | else if (strncmp(pn, "dmult", 5) == 0 | |
1937 | && (strncmp(tn, "dmult", 5) == 0 | |
1938 | || strncmp(tn, "dmacc", 5) == 0)) | |
1939 | { | |
1940 | /* Here is the rest of errata 23. */ | |
1941 | min_nops = 1; | |
1942 | } | |
1943 | if (nops < min_nops) | |
1944 | nops = min_nops; | |
1945 | } | |
1946 | ||
252b5132 RH |
1947 | /* If we are being given a nop instruction, don't bother with |
1948 | one of the nops we would otherwise output. This will only | |
1949 | happen when a nop instruction is used with mips_optimize set | |
1950 | to 0. */ | |
1951 | if (nops > 0 | |
1952 | && ! mips_opts.noreorder | |
156c2f8b | 1953 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1954 | --nops; |
1955 | ||
1956 | /* Now emit the right number of NOP instructions. */ | |
1957 | if (nops > 0 && ! mips_opts.noreorder) | |
1958 | { | |
1959 | fragS *old_frag; | |
1960 | unsigned long old_frag_offset; | |
1961 | int i; | |
1962 | struct insn_label_list *l; | |
1963 | ||
1964 | old_frag = frag_now; | |
1965 | old_frag_offset = frag_now_fix (); | |
1966 | ||
1967 | for (i = 0; i < nops; i++) | |
1968 | emit_nop (); | |
1969 | ||
1970 | if (listing) | |
1971 | { | |
1972 | listing_prev_line (); | |
1973 | /* We may be at the start of a variant frag. In case we | |
1974 | are, make sure there is enough space for the frag | |
1975 | after the frags created by listing_prev_line. The | |
1976 | argument to frag_grow here must be at least as large | |
1977 | as the argument to all other calls to frag_grow in | |
1978 | this file. We don't have to worry about being in the | |
1979 | middle of a variant frag, because the variants insert | |
1980 | all needed nop instructions themselves. */ | |
1981 | frag_grow (40); | |
1982 | } | |
1983 | ||
1984 | for (l = insn_labels; l != NULL; l = l->next) | |
1985 | { | |
98aa84af AM |
1986 | valueT val; |
1987 | ||
252b5132 | 1988 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1989 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1990 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1991 | /* mips16 text labels are stored as odd. */ |
1992 | if (mips_opts.mips16) | |
f9419b05 | 1993 | ++val; |
98aa84af | 1994 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1995 | } |
1996 | ||
1997 | #ifndef NO_ECOFF_DEBUGGING | |
1998 | if (ECOFF_DEBUGGING) | |
1999 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2000 | #endif | |
2001 | } | |
2002 | else if (prev_nop_frag != NULL) | |
2003 | { | |
2004 | /* We have a frag holding nops we may be able to remove. If | |
2005 | we don't need any nops, we can decrease the size of | |
2006 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 2007 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
2008 | if (prev_nop_frag_since == 0) |
2009 | { | |
2010 | if (nops == 0) | |
2011 | { | |
2012 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2013 | --prev_nop_frag_holds; | |
2014 | } | |
2015 | else | |
2016 | prev_nop_frag_required += nops; | |
2017 | } | |
2018 | else | |
2019 | { | |
2020 | if (prev_prev_nop == 0) | |
2021 | { | |
2022 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2023 | --prev_nop_frag_holds; | |
2024 | } | |
2025 | else | |
2026 | ++prev_nop_frag_required; | |
2027 | } | |
2028 | ||
2029 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
2030 | prev_nop_frag = NULL; | |
2031 | ||
2032 | ++prev_nop_frag_since; | |
2033 | ||
2034 | /* Sanity check: by the time we reach the second instruction | |
2035 | after prev_nop_frag, we should have used up all the nops | |
2036 | one way or another. */ | |
2037 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2038 | } | |
2039 | } | |
2040 | ||
4a6a3df4 AO |
2041 | if (place == NULL |
2042 | && address_expr | |
0b25d3e6 | 2043 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2044 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2045 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2046 | && mips_relax_branch | |
2047 | /* Don't try branch relaxation within .set nomacro, or within | |
2048 | .set noat if we use $at for PIC computations. If it turns | |
2049 | out that the branch was out-of-range, we'll get an error. */ | |
2050 | && !mips_opts.warn_about_macros | |
2051 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2052 | && !mips_opts.mips16) | |
2053 | { | |
2054 | f = frag_var (rs_machine_dependent, | |
2055 | relaxed_branch_length | |
2056 | (NULL, NULL, | |
2057 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2058 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2059 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2060 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2061 | pinfo & INSN_COND_BRANCH_LIKELY, |
2062 | pinfo & INSN_WRITE_GPR_31, | |
2063 | 0), | |
2064 | address_expr->X_add_symbol, | |
2065 | address_expr->X_add_number, | |
2066 | 0); | |
2067 | *reloc_type = BFD_RELOC_UNUSED; | |
2068 | } | |
2069 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2070 | { |
2071 | /* We need to set up a variant frag. */ | |
2072 | assert (mips_opts.mips16 && address_expr != NULL); | |
2073 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2074 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2075 | mips16_small, mips16_ext, |
2076 | (prev_pinfo | |
2077 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2078 | (*prev_insn_reloc_type |
252b5132 | 2079 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2080 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
2081 | } |
2082 | else if (place != NULL) | |
2083 | f = place; | |
2084 | else if (mips_opts.mips16 | |
2085 | && ! ip->use_extend | |
f6688943 | 2086 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2087 | { |
2088 | /* Make sure there is enough room to swap this instruction with | |
2089 | a following jump instruction. */ | |
2090 | frag_grow (6); | |
2091 | f = frag_more (2); | |
2092 | } | |
2093 | else | |
2094 | { | |
2095 | if (mips_opts.mips16 | |
2096 | && mips_opts.noreorder | |
2097 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2098 | as_warn (_("extended instruction in delay slot")); | |
2099 | ||
2100 | f = frag_more (4); | |
2101 | } | |
2102 | ||
f6688943 TS |
2103 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2104 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2105 | { |
2106 | if (address_expr->X_op == O_constant) | |
2107 | { | |
4db1a35d | 2108 | valueT tmp; |
f6688943 TS |
2109 | |
2110 | switch (*reloc_type) | |
252b5132 RH |
2111 | { |
2112 | case BFD_RELOC_32: | |
2113 | ip->insn_opcode |= address_expr->X_add_number; | |
2114 | break; | |
2115 | ||
f6688943 TS |
2116 | case BFD_RELOC_MIPS_HIGHEST: |
2117 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
2118 | tmp >>= 16; | |
2119 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2120 | break; | |
2121 | ||
2122 | case BFD_RELOC_MIPS_HIGHER: | |
2123 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2124 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2125 | break; | |
2126 | ||
2127 | case BFD_RELOC_HI16_S: | |
2128 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2129 | >> 16) & 0xffff; | |
2130 | break; | |
2131 | ||
2132 | case BFD_RELOC_HI16: | |
2133 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2134 | break; | |
2135 | ||
252b5132 | 2136 | case BFD_RELOC_LO16: |
ed6fb7bd | 2137 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2138 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2139 | break; | |
2140 | ||
2141 | case BFD_RELOC_MIPS_JMP: | |
2142 | if ((address_expr->X_add_number & 3) != 0) | |
2143 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2144 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2145 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2146 | as_bad (_("jump address range overflow (0x%lx)"), |
2147 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2148 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2149 | break; | |
2150 | ||
2151 | case BFD_RELOC_MIPS16_JMP: | |
2152 | if ((address_expr->X_add_number & 3) != 0) | |
2153 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2154 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2155 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2156 | as_bad (_("jump address range overflow (0x%lx)"), |
2157 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2158 | ip->insn_opcode |= |
2159 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2160 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2161 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2162 | break; | |
2163 | ||
252b5132 RH |
2164 | case BFD_RELOC_16_PCREL_S2: |
2165 | goto need_reloc; | |
2166 | ||
2167 | default: | |
2168 | internalError (); | |
2169 | } | |
2170 | } | |
2171 | else | |
2172 | { | |
2173 | need_reloc: | |
f6688943 | 2174 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2175 | if (place == NULL) |
2176 | { | |
34ce925e RS |
2177 | reloc_howto_type *howto; |
2178 | int i; | |
2179 | ||
2180 | /* In a compound relocation, it is the final (outermost) | |
2181 | operator that determines the relocated field. */ | |
2182 | for (i = 1; i < 3; i++) | |
2183 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2184 | break; | |
2185 | ||
2186 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); | |
a105a300 TS |
2187 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, |
2188 | bfd_get_reloc_size(howto), | |
f6688943 | 2189 | address_expr, |
a105a300 | 2190 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, |
f6688943 TS |
2191 | reloc_type[0]); |
2192 | ||
b6ff326e | 2193 | /* These relocations can have an addend that won't fit in |
f6688943 | 2194 | 4 octets for 64bit assembly. */ |
a105a300 TS |
2195 | if (HAVE_64BIT_GPRS |
2196 | && ! howto->partial_inplace | |
2197 | && (reloc_type[0] == BFD_RELOC_16 | |
2198 | || reloc_type[0] == BFD_RELOC_32 | |
2199 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2200 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2201 | || reloc_type[0] == BFD_RELOC_LO16 | |
2202 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2203 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2204 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2205 | || reloc_type[0] == BFD_RELOC_64 | |
2206 | || reloc_type[0] == BFD_RELOC_CTOR | |
2207 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2208 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2209 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2210 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2211 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2212 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2213 | fixp[0]->fx_no_overflow = 1; |
2214 | ||
5919d012 | 2215 | if (reloc_needs_lo_p (*reloc_type)) |
252b5132 RH |
2216 | { |
2217 | struct mips_hi_fixup *hi_fixup; | |
2218 | ||
5919d012 RS |
2219 | /* Reuse the last entry if it already has a matching %lo. */ |
2220 | hi_fixup = mips_hi_fixup_list; | |
2221 | if (hi_fixup == 0 | |
2222 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2223 | { | |
2224 | hi_fixup = ((struct mips_hi_fixup *) | |
2225 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2226 | hi_fixup->next = mips_hi_fixup_list; | |
2227 | mips_hi_fixup_list = hi_fixup; | |
2228 | } | |
f6688943 | 2229 | hi_fixup->fixp = fixp[0]; |
252b5132 | 2230 | hi_fixup->seg = now_seg; |
252b5132 | 2231 | } |
f6688943 | 2232 | |
34ce925e RS |
2233 | /* Add fixups for the second and third relocations, if given. |
2234 | Note that the ABI allows the second relocation to be | |
2235 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2236 | moment we only use RSS_UNDEF, but we could add support | |
2237 | for the others if it ever becomes necessary. */ | |
2238 | for (i = 1; i < 3; i++) | |
2239 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2240 | { | |
2241 | address_expr->X_op = O_absent; | |
2242 | address_expr->X_add_symbol = 0; | |
2243 | address_expr->X_add_number = 0; | |
2244 | ||
2245 | fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, | |
2246 | fixp[0]->fx_size, address_expr, | |
2247 | FALSE, reloc_type[i]); | |
2248 | } | |
252b5132 RH |
2249 | } |
2250 | } | |
2251 | } | |
2252 | ||
2253 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2254 | { |
2255 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2256 | #ifdef OBJ_ELF | |
2257 | dwarf2_emit_insn (4); | |
2258 | #endif | |
2259 | } | |
f6688943 | 2260 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2261 | { |
2262 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2263 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2264 | #ifdef OBJ_ELF |
2265 | dwarf2_emit_insn (4); | |
2266 | #endif | |
252b5132 RH |
2267 | } |
2268 | else | |
2269 | { | |
2270 | if (ip->use_extend) | |
2271 | { | |
2272 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2273 | f += 2; | |
2274 | } | |
2275 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2276 | #ifdef OBJ_ELF |
2277 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2278 | #endif | |
252b5132 RH |
2279 | } |
2280 | ||
2281 | /* Update the register mask information. */ | |
2282 | if (! mips_opts.mips16) | |
2283 | { | |
2284 | if (pinfo & INSN_WRITE_GPR_D) | |
2285 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2286 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2287 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2288 | if (pinfo & INSN_READ_GPR_S) | |
2289 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2290 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2291 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2292 | if (pinfo & INSN_WRITE_FPR_D) |
2293 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2294 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2295 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2296 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2297 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2298 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2299 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2300 | if (pinfo & INSN_COP) | |
2301 | { | |
bdaaa2e1 KH |
2302 | /* We don't keep enough information to sort these cases out. |
2303 | The itbl support does keep this information however, although | |
2304 | we currently don't support itbl fprmats as part of the cop | |
2305 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2306 | } |
2307 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2308 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2309 | } |
2310 | else | |
2311 | { | |
2312 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2313 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2314 | & MIPS16OP_MASK_RX); | |
2315 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2316 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2317 | & MIPS16OP_MASK_RY); | |
2318 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2319 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2320 | & MIPS16OP_MASK_RZ); | |
2321 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2322 | mips_gprmask |= 1 << TREG; | |
2323 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2324 | mips_gprmask |= 1 << SP; | |
2325 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2326 | mips_gprmask |= 1 << RA; | |
2327 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2328 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2329 | if (pinfo & MIPS16_INSN_READ_Z) | |
2330 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2331 | & MIPS16OP_MASK_MOVE32Z); | |
2332 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2333 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2334 | & MIPS16OP_MASK_REGR32); | |
2335 | } | |
2336 | ||
2337 | if (place == NULL && ! mips_opts.noreorder) | |
2338 | { | |
2339 | /* Filling the branch delay slot is more complex. We try to | |
2340 | switch the branch with the previous instruction, which we can | |
2341 | do if the previous instruction does not set up a condition | |
2342 | that the branch tests and if the branch is not itself the | |
2343 | target of any branch. */ | |
2344 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2345 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2346 | { | |
2347 | if (mips_optimize < 2 | |
2348 | /* If we have seen .set volatile or .set nomove, don't | |
2349 | optimize. */ | |
2350 | || mips_opts.nomove != 0 | |
2351 | /* If we had to emit any NOP instructions, then we | |
2352 | already know we can not swap. */ | |
2353 | || nops != 0 | |
2354 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2355 | swap. */ |
252b5132 RH |
2356 | || ! prev_insn_valid |
2357 | /* If the previous insn is already in a branch delay | |
2358 | slot, then we can not swap. */ | |
2359 | || prev_insn_is_delay_slot | |
2360 | /* If the previous previous insn was in a .set | |
2361 | noreorder, we can't swap. Actually, the MIPS | |
2362 | assembler will swap in this situation. However, gcc | |
2363 | configured -with-gnu-as will generate code like | |
2364 | .set noreorder | |
2365 | lw $4,XXX | |
2366 | .set reorder | |
2367 | INSN | |
2368 | bne $4,$0,foo | |
2369 | in which we can not swap the bne and INSN. If gcc is | |
2370 | not configured -with-gnu-as, it does not output the | |
2371 | .set pseudo-ops. We don't have to check | |
2372 | prev_insn_unreordered, because prev_insn_valid will | |
2373 | be 0 in that case. We don't want to use | |
2374 | prev_prev_insn_valid, because we do want to be able | |
2375 | to swap at the start of a function. */ | |
2376 | || prev_prev_insn_unreordered | |
2377 | /* If the branch is itself the target of a branch, we | |
2378 | can not swap. We cheat on this; all we check for is | |
2379 | whether there is a label on this instruction. If | |
2380 | there are any branches to anything other than a | |
2381 | label, users must use .set noreorder. */ | |
2382 | || insn_labels != NULL | |
2383 | /* If the previous instruction is in a variant frag, we | |
2384 | can not do the swap. This does not apply to the | |
2385 | mips16, which uses variant frags for different | |
2386 | purposes. */ | |
2387 | || (! mips_opts.mips16 | |
2388 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2389 | /* If the branch reads the condition codes, we don't | |
2390 | even try to swap, because in the sequence | |
2391 | ctc1 $X,$31 | |
2392 | INSN | |
2393 | INSN | |
2394 | bc1t LABEL | |
2395 | we can not swap, and I don't feel like handling that | |
2396 | case. */ | |
2397 | || (! mips_opts.mips16 | |
9ce8a5dd | 2398 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2399 | && (pinfo & INSN_READ_COND_CODE)) |
2400 | /* We can not swap with an instruction that requires a | |
2401 | delay slot, becase the target of the branch might | |
2402 | interfere with that instruction. */ | |
2403 | || (! mips_opts.mips16 | |
9ce8a5dd | 2404 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2405 | && (prev_pinfo |
bdaaa2e1 | 2406 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2407 | & (INSN_LOAD_COPROC_DELAY |
2408 | | INSN_COPROC_MOVE_DELAY | |
2409 | | INSN_WRITE_COND_CODE))) | |
2410 | || (! (hilo_interlocks | |
ec68c924 | 2411 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2412 | && (prev_pinfo |
2413 | & (INSN_READ_LO | |
2414 | | INSN_READ_HI))) | |
2415 | || (! mips_opts.mips16 | |
2416 | && ! gpr_interlocks | |
2417 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2418 | || (! mips_opts.mips16 | |
e7af610e | 2419 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2420 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2421 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2422 | /* We can not swap with a branch instruction. */ | |
2423 | || (prev_pinfo | |
2424 | & (INSN_UNCOND_BRANCH_DELAY | |
2425 | | INSN_COND_BRANCH_DELAY | |
2426 | | INSN_COND_BRANCH_LIKELY)) | |
2427 | /* We do not swap with a trap instruction, since it | |
2428 | complicates trap handlers to have the trap | |
2429 | instruction be in a delay slot. */ | |
2430 | || (prev_pinfo & INSN_TRAP) | |
2431 | /* If the branch reads a register that the previous | |
2432 | instruction sets, we can not swap. */ | |
2433 | || (! mips_opts.mips16 | |
2434 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2435 | && insn_uses_reg (ip, | |
2436 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2437 | & OP_MASK_RT), | |
2438 | MIPS_GR_REG)) | |
2439 | || (! mips_opts.mips16 | |
2440 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2441 | && insn_uses_reg (ip, | |
2442 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2443 | & OP_MASK_RD), | |
2444 | MIPS_GR_REG)) | |
2445 | || (mips_opts.mips16 | |
2446 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2447 | && insn_uses_reg (ip, | |
2448 | ((prev_insn.insn_opcode | |
2449 | >> MIPS16OP_SH_RX) | |
2450 | & MIPS16OP_MASK_RX), | |
2451 | MIPS16_REG)) | |
2452 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2453 | && insn_uses_reg (ip, | |
2454 | ((prev_insn.insn_opcode | |
2455 | >> MIPS16OP_SH_RY) | |
2456 | & MIPS16OP_MASK_RY), | |
2457 | MIPS16_REG)) | |
2458 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2459 | && insn_uses_reg (ip, | |
2460 | ((prev_insn.insn_opcode | |
2461 | >> MIPS16OP_SH_RZ) | |
2462 | & MIPS16OP_MASK_RZ), | |
2463 | MIPS16_REG)) | |
2464 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2465 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2466 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2467 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2468 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2469 | && insn_uses_reg (ip, | |
2470 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2471 | insn_opcode), | |
2472 | MIPS_GR_REG)))) | |
2473 | /* If the branch writes a register that the previous | |
2474 | instruction sets, we can not swap (we know that | |
2475 | branches write only to RD or to $31). */ | |
2476 | || (! mips_opts.mips16 | |
2477 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2478 | && (((pinfo & INSN_WRITE_GPR_D) | |
2479 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2480 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2481 | || ((pinfo & INSN_WRITE_GPR_31) | |
2482 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2483 | & OP_MASK_RT) | |
f9419b05 | 2484 | == RA)))) |
252b5132 RH |
2485 | || (! mips_opts.mips16 |
2486 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2487 | && (((pinfo & INSN_WRITE_GPR_D) | |
2488 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2489 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2490 | || ((pinfo & INSN_WRITE_GPR_31) | |
2491 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2492 | & OP_MASK_RD) | |
f9419b05 | 2493 | == RA)))) |
252b5132 RH |
2494 | || (mips_opts.mips16 |
2495 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2496 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2497 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2498 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2499 | == RA)))) | |
2500 | /* If the branch writes a register that the previous | |
2501 | instruction reads, we can not swap (we know that | |
2502 | branches only write to RD or to $31). */ | |
2503 | || (! mips_opts.mips16 | |
2504 | && (pinfo & INSN_WRITE_GPR_D) | |
2505 | && insn_uses_reg (&prev_insn, | |
2506 | ((ip->insn_opcode >> OP_SH_RD) | |
2507 | & OP_MASK_RD), | |
2508 | MIPS_GR_REG)) | |
2509 | || (! mips_opts.mips16 | |
2510 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2511 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2512 | || (mips_opts.mips16 |
2513 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2514 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2515 | /* If we are generating embedded PIC code, the branch | |
2516 | might be expanded into a sequence which uses $at, so | |
2517 | we can't swap with an instruction which reads it. */ | |
2518 | || (mips_pic == EMBEDDED_PIC | |
2519 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2520 | /* If the previous previous instruction has a load | |
2521 | delay, and sets a register that the branch reads, we | |
2522 | can not swap. */ | |
2523 | || (! mips_opts.mips16 | |
9ce8a5dd | 2524 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2525 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2526 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2527 | || (! gpr_interlocks | |
2528 | && (prev_prev_insn.insn_mo->pinfo | |
2529 | & INSN_LOAD_MEMORY_DELAY))) | |
2530 | && insn_uses_reg (ip, | |
2531 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2532 | & OP_MASK_RT), | |
2533 | MIPS_GR_REG)) | |
2534 | /* If one instruction sets a condition code and the | |
2535 | other one uses a condition code, we can not swap. */ | |
2536 | || ((pinfo & INSN_READ_COND_CODE) | |
2537 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2538 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2539 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2540 | /* If the previous instruction uses the PC, we can not | |
2541 | swap. */ | |
2542 | || (mips_opts.mips16 | |
2543 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2544 | /* If the previous instruction was extended, we can not | |
2545 | swap. */ | |
2546 | || (mips_opts.mips16 && prev_insn_extended) | |
2547 | /* If the previous instruction had a fixup in mips16 | |
2548 | mode, we can not swap. This normally means that the | |
2549 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2550 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2551 | /* If the previous instruction is a sync, sync.l, or |
2552 | sync.p, we can not swap. */ | |
f173e82e | 2553 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2554 | { |
2555 | /* We could do even better for unconditional branches to | |
2556 | portions of this object file; we could pick up the | |
2557 | instruction at the destination, put it in the delay | |
2558 | slot, and bump the destination address. */ | |
2559 | emit_nop (); | |
2560 | /* Update the previous insn information. */ | |
2561 | prev_prev_insn = *ip; | |
2562 | prev_insn.insn_mo = &dummy_opcode; | |
2563 | } | |
2564 | else | |
2565 | { | |
2566 | /* It looks like we can actually do the swap. */ | |
2567 | if (! mips_opts.mips16) | |
2568 | { | |
2569 | char *prev_f; | |
2570 | char temp[4]; | |
2571 | ||
2572 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2573 | memcpy (temp, prev_f, 4); | |
2574 | memcpy (prev_f, f, 4); | |
2575 | memcpy (f, temp, 4); | |
f6688943 TS |
2576 | if (prev_insn_fixp[0]) |
2577 | { | |
2578 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2579 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2580 | } | |
2581 | if (prev_insn_fixp[1]) | |
2582 | { | |
2583 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2584 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2585 | } | |
2586 | if (prev_insn_fixp[2]) | |
252b5132 | 2587 | { |
f6688943 TS |
2588 | prev_insn_fixp[2]->fx_frag = frag_now; |
2589 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2590 | } |
f5040a92 AO |
2591 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2592 | && prev_insn_frag != frag_now | |
2593 | && (prev_insn_fixp[0]->fx_r_type | |
2594 | == BFD_RELOC_MIPS_GOT_DISP | |
2595 | || (prev_insn_fixp[0]->fx_r_type | |
2596 | == BFD_RELOC_MIPS_CALL16))) | |
2597 | { | |
2598 | /* To avoid confusion in tc_gen_reloc, we must | |
2599 | ensure that this does not become a variant | |
2600 | frag. */ | |
2601 | force_new_frag = TRUE; | |
2602 | } | |
f6688943 | 2603 | if (fixp[0]) |
252b5132 | 2604 | { |
f6688943 TS |
2605 | fixp[0]->fx_frag = prev_insn_frag; |
2606 | fixp[0]->fx_where = prev_insn_where; | |
2607 | } | |
2608 | if (fixp[1]) | |
2609 | { | |
2610 | fixp[1]->fx_frag = prev_insn_frag; | |
2611 | fixp[1]->fx_where = prev_insn_where; | |
2612 | } | |
2613 | if (fixp[2]) | |
2614 | { | |
2615 | fixp[2]->fx_frag = prev_insn_frag; | |
2616 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2617 | } |
2618 | } | |
2619 | else | |
2620 | { | |
2621 | char *prev_f; | |
2622 | char temp[2]; | |
2623 | ||
f6688943 TS |
2624 | assert (prev_insn_fixp[0] == NULL); |
2625 | assert (prev_insn_fixp[1] == NULL); | |
2626 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2627 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2628 | memcpy (temp, prev_f, 2); | |
2629 | memcpy (prev_f, f, 2); | |
f6688943 | 2630 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2631 | { |
f6688943 | 2632 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2633 | memcpy (f, temp, 2); |
2634 | } | |
2635 | else | |
2636 | { | |
2637 | memcpy (f, f + 2, 2); | |
2638 | memcpy (f + 2, temp, 2); | |
2639 | } | |
f6688943 TS |
2640 | if (fixp[0]) |
2641 | { | |
2642 | fixp[0]->fx_frag = prev_insn_frag; | |
2643 | fixp[0]->fx_where = prev_insn_where; | |
2644 | } | |
2645 | if (fixp[1]) | |
2646 | { | |
2647 | fixp[1]->fx_frag = prev_insn_frag; | |
2648 | fixp[1]->fx_where = prev_insn_where; | |
2649 | } | |
2650 | if (fixp[2]) | |
252b5132 | 2651 | { |
f6688943 TS |
2652 | fixp[2]->fx_frag = prev_insn_frag; |
2653 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2654 | } |
2655 | } | |
2656 | ||
2657 | /* Update the previous insn information; leave prev_insn | |
2658 | unchanged. */ | |
2659 | prev_prev_insn = *ip; | |
2660 | } | |
2661 | prev_insn_is_delay_slot = 1; | |
2662 | ||
2663 | /* If that was an unconditional branch, forget the previous | |
2664 | insn information. */ | |
2665 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2666 | { | |
2667 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2668 | prev_insn.insn_mo = &dummy_opcode; | |
2669 | } | |
2670 | ||
f6688943 TS |
2671 | prev_insn_fixp[0] = NULL; |
2672 | prev_insn_fixp[1] = NULL; | |
2673 | prev_insn_fixp[2] = NULL; | |
2674 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2675 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2676 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2677 | prev_insn_extended = 0; |
2678 | } | |
2679 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2680 | { | |
2681 | /* We don't yet optimize a branch likely. What we should do | |
2682 | is look at the target, copy the instruction found there | |
2683 | into the delay slot, and increment the branch to jump to | |
2684 | the next instruction. */ | |
2685 | emit_nop (); | |
2686 | /* Update the previous insn information. */ | |
2687 | prev_prev_insn = *ip; | |
2688 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2689 | prev_insn_fixp[0] = NULL; |
2690 | prev_insn_fixp[1] = NULL; | |
2691 | prev_insn_fixp[2] = NULL; | |
2692 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2693 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2694 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2695 | prev_insn_extended = 0; |
2696 | } | |
2697 | else | |
2698 | { | |
2699 | /* Update the previous insn information. */ | |
2700 | if (nops > 0) | |
2701 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2702 | else | |
2703 | prev_prev_insn = prev_insn; | |
2704 | prev_insn = *ip; | |
2705 | ||
2706 | /* Any time we see a branch, we always fill the delay slot | |
2707 | immediately; since this insn is not a branch, we know it | |
2708 | is not in a delay slot. */ | |
2709 | prev_insn_is_delay_slot = 0; | |
2710 | ||
f6688943 TS |
2711 | prev_insn_fixp[0] = fixp[0]; |
2712 | prev_insn_fixp[1] = fixp[1]; | |
2713 | prev_insn_fixp[2] = fixp[2]; | |
2714 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2715 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2716 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2717 | if (mips_opts.mips16) |
2718 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2719 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2720 | } |
2721 | ||
2722 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2723 | prev_insn_unreordered = 0; | |
2724 | prev_insn_frag = frag_now; | |
2725 | prev_insn_where = f - frag_now->fr_literal; | |
2726 | prev_insn_valid = 1; | |
2727 | } | |
2728 | else if (place == NULL) | |
2729 | { | |
2730 | /* We need to record a bit of information even when we are not | |
2731 | reordering, in order to determine the base address for mips16 | |
2732 | PC relative relocs. */ | |
2733 | prev_prev_insn = prev_insn; | |
2734 | prev_insn = *ip; | |
f6688943 TS |
2735 | prev_insn_reloc_type[0] = reloc_type[0]; |
2736 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2737 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2738 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2739 | prev_insn_unreordered = 1; | |
2740 | } | |
2741 | ||
2742 | /* We just output an insn, so the next one doesn't have a label. */ | |
2743 | mips_clear_insn_labels (); | |
f5040a92 AO |
2744 | |
2745 | /* We must ensure that the frag to which an instruction that was | |
2746 | moved from a non-variant frag doesn't become a variant frag, | |
2747 | otherwise tc_gen_reloc may get confused. */ | |
2748 | if (force_new_frag) | |
2749 | { | |
2750 | frag_wane (frag_now); | |
2751 | frag_new (0); | |
2752 | } | |
252b5132 RH |
2753 | } |
2754 | ||
2755 | /* This function forgets that there was any previous instruction or | |
2756 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2757 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2758 | |
2759 | static void | |
2760 | mips_no_prev_insn (preserve) | |
2761 | int preserve; | |
2762 | { | |
2763 | if (! preserve) | |
2764 | { | |
2765 | prev_insn.insn_mo = &dummy_opcode; | |
2766 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2767 | prev_nop_frag = NULL; | |
2768 | prev_nop_frag_holds = 0; | |
2769 | prev_nop_frag_required = 0; | |
2770 | prev_nop_frag_since = 0; | |
2771 | } | |
2772 | prev_insn_valid = 0; | |
2773 | prev_insn_is_delay_slot = 0; | |
2774 | prev_insn_unreordered = 0; | |
2775 | prev_insn_extended = 0; | |
f6688943 TS |
2776 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2777 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2778 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2779 | prev_prev_insn_unreordered = 0; |
2780 | mips_clear_insn_labels (); | |
2781 | } | |
2782 | ||
2783 | /* This function must be called whenever we turn on noreorder or emit | |
2784 | something other than instructions. It inserts any NOPS which might | |
2785 | be needed by the previous instruction, and clears the information | |
2786 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2787 | instructions are to follow. */ |
252b5132 RH |
2788 | |
2789 | static void | |
2790 | mips_emit_delays (insns) | |
b34976b6 | 2791 | bfd_boolean insns; |
252b5132 RH |
2792 | { |
2793 | if (! mips_opts.noreorder) | |
2794 | { | |
2795 | int nops; | |
2796 | ||
2797 | nops = 0; | |
2798 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2799 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2800 | && (! cop_interlocks |
2801 | && (prev_insn.insn_mo->pinfo | |
2802 | & (INSN_LOAD_COPROC_DELAY | |
2803 | | INSN_COPROC_MOVE_DELAY | |
2804 | | INSN_WRITE_COND_CODE)))) | |
2805 | || (! hilo_interlocks | |
2806 | && (prev_insn.insn_mo->pinfo | |
2807 | & (INSN_READ_LO | |
2808 | | INSN_READ_HI))) | |
2809 | || (! mips_opts.mips16 | |
2810 | && ! gpr_interlocks | |
bdaaa2e1 | 2811 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2812 | & INSN_LOAD_MEMORY_DELAY)) |
2813 | || (! mips_opts.mips16 | |
e7af610e | 2814 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2815 | && (prev_insn.insn_mo->pinfo |
2816 | & INSN_COPROC_MEMORY_DELAY))) | |
2817 | { | |
beae10d5 | 2818 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2819 | ++nops; |
2820 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2821 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2822 | && (! cop_interlocks |
2823 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2824 | || (! hilo_interlocks | |
2825 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2826 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2827 | ++nops; | |
2828 | ||
2829 | if (prev_insn_unreordered) | |
2830 | nops = 0; | |
2831 | } | |
2832 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2833 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2834 | && (! cop_interlocks |
2835 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2836 | || (! hilo_interlocks | |
2837 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2838 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2839 | { | |
beae10d5 | 2840 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2841 | if (! prev_prev_insn_unreordered) |
2842 | ++nops; | |
2843 | } | |
2844 | ||
60b63b72 RS |
2845 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
2846 | { | |
2847 | int min_nops = 0; | |
2848 | const char *pn = prev_insn.insn_mo->name; | |
2849 | if (strncmp(pn, "macc", 4) == 0 | |
2850 | || strncmp(pn, "dmacc", 5) == 0 | |
2851 | || strncmp(pn, "dmult", 5) == 0) | |
2852 | { | |
2853 | min_nops = 1; | |
2854 | } | |
2855 | if (nops < min_nops) | |
2856 | nops = min_nops; | |
2857 | } | |
2858 | ||
252b5132 RH |
2859 | if (nops > 0) |
2860 | { | |
2861 | struct insn_label_list *l; | |
2862 | ||
2863 | if (insns) | |
2864 | { | |
2865 | /* Record the frag which holds the nop instructions, so | |
2866 | that we can remove them if we don't need them. */ | |
2867 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2868 | prev_nop_frag = frag_now; | |
2869 | prev_nop_frag_holds = nops; | |
2870 | prev_nop_frag_required = 0; | |
2871 | prev_nop_frag_since = 0; | |
2872 | } | |
2873 | ||
2874 | for (; nops > 0; --nops) | |
2875 | emit_nop (); | |
2876 | ||
2877 | if (insns) | |
2878 | { | |
2879 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2880 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2881 | frag_wane (frag_now); |
2882 | frag_new (0); | |
2883 | } | |
2884 | ||
2885 | for (l = insn_labels; l != NULL; l = l->next) | |
2886 | { | |
98aa84af AM |
2887 | valueT val; |
2888 | ||
252b5132 | 2889 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2890 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2891 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2892 | /* mips16 text labels are stored as odd. */ |
2893 | if (mips_opts.mips16) | |
f9419b05 | 2894 | ++val; |
98aa84af | 2895 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2896 | } |
2897 | } | |
2898 | } | |
2899 | ||
2900 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2901 | if (insns) |
252b5132 RH |
2902 | mips16_mark_labels (); |
2903 | ||
2904 | mips_no_prev_insn (insns); | |
2905 | } | |
2906 | ||
2907 | /* Build an instruction created by a macro expansion. This is passed | |
2908 | a pointer to the count of instructions created so far, an | |
2909 | expression, the name of the instruction to build, an operand format | |
2910 | string, and corresponding arguments. */ | |
2911 | ||
2912 | #ifdef USE_STDARG | |
2913 | static void | |
2914 | macro_build (char *place, | |
2915 | int *counter, | |
2916 | expressionS * ep, | |
2917 | const char *name, | |
2918 | const char *fmt, | |
2919 | ...) | |
2920 | #else | |
2921 | static void | |
2922 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2923 | char *place; | |
2924 | int *counter; | |
2925 | expressionS *ep; | |
2926 | const char *name; | |
2927 | const char *fmt; | |
2928 | va_dcl | |
2929 | #endif | |
2930 | { | |
2931 | struct mips_cl_insn insn; | |
f6688943 | 2932 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2933 | va_list args; |
252b5132 RH |
2934 | |
2935 | #ifdef USE_STDARG | |
2936 | va_start (args, fmt); | |
2937 | #else | |
2938 | va_start (args); | |
2939 | #endif | |
2940 | ||
2941 | /* | |
2942 | * If the macro is about to expand into a second instruction, | |
2943 | * print a warning if needed. We need to pass ip as a parameter | |
2944 | * to generate a better warning message here... | |
2945 | */ | |
2946 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2947 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2948 | ||
80cc45a5 EC |
2949 | /* |
2950 | * If the macro is about to expand into a second instruction, | |
2951 | * and it is in a delay slot, print a warning. | |
2952 | */ | |
2953 | if (place == NULL | |
2954 | && *counter == 1 | |
2955 | && mips_opts.noreorder | |
2956 | && (prev_prev_insn.insn_mo->pinfo | |
2957 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2958 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2959 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2960 | ||
252b5132 | 2961 | if (place == NULL) |
f9419b05 | 2962 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2963 | |
2964 | if (mips_opts.mips16) | |
2965 | { | |
2966 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2967 | va_end (args); | |
2968 | return; | |
2969 | } | |
2970 | ||
f6688943 TS |
2971 | r[0] = BFD_RELOC_UNUSED; |
2972 | r[1] = BFD_RELOC_UNUSED; | |
2973 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2974 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2975 | assert (insn.insn_mo); | |
2976 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2977 | ||
2978 | /* Search until we get a match for NAME. */ | |
2979 | while (1) | |
2980 | { | |
b34976b6 | 2981 | /* It is assumed here that macros will never generate |
deec1734 | 2982 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
2983 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2984 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
2985 | && OPCODE_IS_MEMBER (insn.insn_mo, |
2986 | (mips_opts.isa | |
3396de36 | 2987 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
aec421e0 | 2988 | mips_arch) |
ec68c924 | 2989 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2990 | break; |
2991 | ||
2992 | ++insn.insn_mo; | |
2993 | assert (insn.insn_mo->name); | |
2994 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2995 | } | |
2996 | ||
2997 | insn.insn_opcode = insn.insn_mo->match; | |
2998 | for (;;) | |
2999 | { | |
3000 | switch (*fmt++) | |
3001 | { | |
3002 | case '\0': | |
3003 | break; | |
3004 | ||
3005 | case ',': | |
3006 | case '(': | |
3007 | case ')': | |
3008 | continue; | |
3009 | ||
3010 | case 't': | |
3011 | case 'w': | |
3012 | case 'E': | |
38487616 | 3013 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3014 | continue; |
3015 | ||
3016 | case 'c': | |
38487616 TS |
3017 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3018 | continue; | |
3019 | ||
252b5132 RH |
3020 | case 'T': |
3021 | case 'W': | |
38487616 | 3022 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3023 | continue; |
3024 | ||
3025 | case 'd': | |
3026 | case 'G': | |
af7ee8bf | 3027 | case 'K': |
38487616 | 3028 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3029 | continue; |
3030 | ||
4372b673 NC |
3031 | case 'U': |
3032 | { | |
3033 | int tmp = va_arg (args, int); | |
3034 | ||
38487616 TS |
3035 | insn.insn_opcode |= tmp << OP_SH_RT; |
3036 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3037 | continue; |
4372b673 NC |
3038 | } |
3039 | ||
252b5132 RH |
3040 | case 'V': |
3041 | case 'S': | |
38487616 | 3042 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3043 | continue; |
3044 | ||
3045 | case 'z': | |
3046 | continue; | |
3047 | ||
3048 | case '<': | |
38487616 | 3049 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3050 | continue; |
3051 | ||
3052 | case 'D': | |
38487616 | 3053 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3054 | continue; |
3055 | ||
3056 | case 'B': | |
38487616 | 3057 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3058 | continue; |
3059 | ||
4372b673 | 3060 | case 'J': |
38487616 | 3061 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3062 | continue; |
3063 | ||
252b5132 | 3064 | case 'q': |
38487616 | 3065 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3066 | continue; |
3067 | ||
3068 | case 'b': | |
3069 | case 's': | |
3070 | case 'r': | |
3071 | case 'v': | |
38487616 | 3072 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3073 | continue; |
3074 | ||
3075 | case 'i': | |
3076 | case 'j': | |
3077 | case 'o': | |
f6688943 | 3078 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3079 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3080 | || *r == BFD_RELOC_MIPS_LITERAL |
3081 | || *r == BFD_RELOC_MIPS_HIGHER | |
3082 | || *r == BFD_RELOC_HI16_S | |
3083 | || *r == BFD_RELOC_LO16 | |
3084 | || *r == BFD_RELOC_MIPS_GOT16 | |
3085 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3086 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3087 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3088 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
3089 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3090 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 3091 | || (ep->X_op == O_subtract |
f6688943 | 3092 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
3093 | continue; |
3094 | ||
3095 | case 'u': | |
f6688943 | 3096 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3097 | assert (ep != NULL |
3098 | && (ep->X_op == O_constant | |
3099 | || (ep->X_op == O_symbol | |
f6688943 TS |
3100 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3101 | || *r == BFD_RELOC_HI16_S | |
3102 | || *r == BFD_RELOC_HI16 | |
3103 | || *r == BFD_RELOC_GPREL16 | |
3104 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3105 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 3106 | || (ep->X_op == O_subtract |
f6688943 | 3107 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
3108 | continue; |
3109 | ||
3110 | case 'p': | |
3111 | assert (ep != NULL); | |
3112 | /* | |
3113 | * This allows macro() to pass an immediate expression for | |
3114 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3115 | * Note that the expression still might come from the assembly |
3116 | * input, in which case the value is not checked for range nor | |
3117 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3118 | */ |
3119 | if (ep->X_op == O_constant) | |
3120 | { | |
3121 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3122 | ep = NULL; | |
3123 | } | |
3124 | else | |
0b25d3e6 | 3125 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3126 | continue; |
3127 | ||
3128 | case 'a': | |
3129 | assert (ep != NULL); | |
f6688943 | 3130 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3131 | continue; |
3132 | ||
3133 | case 'C': | |
3134 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3135 | continue; | |
3136 | ||
3137 | default: | |
3138 | internalError (); | |
3139 | } | |
3140 | break; | |
3141 | } | |
3142 | va_end (args); | |
f6688943 | 3143 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3144 | |
5e0116d5 | 3145 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3146 | } |
3147 | ||
3148 | static void | |
3149 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
3150 | char *place; | |
43841e91 | 3151 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
3152 | expressionS *ep; |
3153 | const char *name; | |
3154 | const char *fmt; | |
3155 | va_list args; | |
3156 | { | |
3157 | struct mips_cl_insn insn; | |
f6688943 TS |
3158 | bfd_reloc_code_real_type r[3] |
3159 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3160 | |
252b5132 RH |
3161 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3162 | assert (insn.insn_mo); | |
3163 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3164 | ||
3165 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3166 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3167 | { | |
3168 | ++insn.insn_mo; | |
3169 | assert (insn.insn_mo->name); | |
3170 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3171 | } | |
3172 | ||
3173 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3174 | insn.use_extend = FALSE; |
252b5132 RH |
3175 | |
3176 | for (;;) | |
3177 | { | |
3178 | int c; | |
3179 | ||
3180 | c = *fmt++; | |
3181 | switch (c) | |
3182 | { | |
3183 | case '\0': | |
3184 | break; | |
3185 | ||
3186 | case ',': | |
3187 | case '(': | |
3188 | case ')': | |
3189 | continue; | |
3190 | ||
3191 | case 'y': | |
3192 | case 'w': | |
3193 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3194 | continue; | |
3195 | ||
3196 | case 'x': | |
3197 | case 'v': | |
3198 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3199 | continue; | |
3200 | ||
3201 | case 'z': | |
3202 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3203 | continue; | |
3204 | ||
3205 | case 'Z': | |
3206 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3207 | continue; | |
3208 | ||
3209 | case '0': | |
3210 | case 'S': | |
3211 | case 'P': | |
3212 | case 'R': | |
3213 | continue; | |
3214 | ||
3215 | case 'X': | |
3216 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3217 | continue; | |
3218 | ||
3219 | case 'Y': | |
3220 | { | |
3221 | int regno; | |
3222 | ||
3223 | regno = va_arg (args, int); | |
3224 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3225 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3226 | } | |
3227 | continue; | |
3228 | ||
3229 | case '<': | |
3230 | case '>': | |
3231 | case '4': | |
3232 | case '5': | |
3233 | case 'H': | |
3234 | case 'W': | |
3235 | case 'D': | |
3236 | case 'j': | |
3237 | case '8': | |
3238 | case 'V': | |
3239 | case 'C': | |
3240 | case 'U': | |
3241 | case 'k': | |
3242 | case 'K': | |
3243 | case 'p': | |
3244 | case 'q': | |
3245 | { | |
3246 | assert (ep != NULL); | |
3247 | ||
3248 | if (ep->X_op != O_constant) | |
874e8986 | 3249 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3250 | else |
3251 | { | |
b34976b6 AM |
3252 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3253 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3254 | &insn.extend); |
252b5132 | 3255 | ep = NULL; |
f6688943 | 3256 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3257 | } |
3258 | } | |
3259 | continue; | |
3260 | ||
3261 | case '6': | |
3262 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3263 | continue; | |
3264 | } | |
3265 | ||
3266 | break; | |
3267 | } | |
3268 | ||
f6688943 | 3269 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3270 | |
5e0116d5 | 3271 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3272 | } |
3273 | ||
438c16b8 TS |
3274 | /* |
3275 | * Generate a "jalr" instruction with a relocation hint to the called | |
3276 | * function. This occurs in NewABI PIC code. | |
3277 | */ | |
3278 | static void | |
3279 | macro_build_jalr (icnt, ep) | |
3280 | int icnt; | |
3281 | expressionS *ep; | |
3282 | { | |
36ede617 | 3283 | char *f = NULL;; |
b34976b6 | 3284 | |
438c16b8 | 3285 | if (HAVE_NEWABI) |
f21f8242 AO |
3286 | { |
3287 | frag_grow (4); | |
3288 | f = frag_more (0); | |
3289 | } | |
438c16b8 TS |
3290 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s", |
3291 | RA, PIC_CALL_REG); | |
3292 | if (HAVE_NEWABI) | |
f21f8242 | 3293 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3294 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3295 | } |
3296 | ||
252b5132 RH |
3297 | /* |
3298 | * Generate a "lui" instruction. | |
3299 | */ | |
3300 | static void | |
3301 | macro_build_lui (place, counter, ep, regnum) | |
3302 | char *place; | |
3303 | int *counter; | |
3304 | expressionS *ep; | |
3305 | int regnum; | |
3306 | { | |
3307 | expressionS high_expr; | |
3308 | struct mips_cl_insn insn; | |
f6688943 TS |
3309 | bfd_reloc_code_real_type r[3] |
3310 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3311 | const char *name = "lui"; |
3312 | const char *fmt = "t,u"; | |
252b5132 RH |
3313 | |
3314 | assert (! mips_opts.mips16); | |
3315 | ||
3316 | if (place == NULL) | |
3317 | high_expr = *ep; | |
3318 | else | |
3319 | { | |
3320 | high_expr.X_op = O_constant; | |
3321 | high_expr.X_add_number = ep->X_add_number; | |
3322 | } | |
3323 | ||
3324 | if (high_expr.X_op == O_constant) | |
3325 | { | |
3326 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3327 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3328 | >> 16) & 0xffff; | |
f6688943 | 3329 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3330 | } |
78e1bb40 | 3331 | else |
252b5132 RH |
3332 | { |
3333 | assert (ep->X_op == O_symbol); | |
3334 | /* _gp_disp is a special case, used from s_cpload. */ | |
3335 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3336 | || (! HAVE_NEWABI |
3337 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3338 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3339 | } |
3340 | ||
3341 | /* | |
3342 | * If the macro is about to expand into a second instruction, | |
3343 | * print a warning if needed. We need to pass ip as a parameter | |
3344 | * to generate a better warning message here... | |
3345 | */ | |
3346 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3347 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3348 | ||
3349 | if (place == NULL) | |
f9419b05 | 3350 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3351 | |
3352 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3353 | assert (insn.insn_mo); | |
3354 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3355 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3356 | ||
3357 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3358 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3359 | { |
3360 | insn.insn_opcode |= high_expr.X_add_number; | |
5e0116d5 | 3361 | append_insn (place, &insn, NULL, r); |
252b5132 RH |
3362 | } |
3363 | else | |
5e0116d5 | 3364 | append_insn (place, &insn, &high_expr, r); |
252b5132 RH |
3365 | } |
3366 | ||
885add95 CD |
3367 | /* Generate a sequence of instructions to do a load or store from a constant |
3368 | offset off of a base register (breg) into/from a target register (treg), | |
3369 | using AT if necessary. */ | |
3370 | static void | |
3371 | macro_build_ldst_constoffset (place, counter, ep, op, treg, breg) | |
3372 | char *place; | |
3373 | int *counter; | |
3374 | expressionS *ep; | |
3375 | const char *op; | |
3376 | int treg, breg; | |
3377 | { | |
3378 | assert (ep->X_op == O_constant); | |
3379 | ||
3380 | /* Right now, this routine can only handle signed 32-bit contants. */ | |
3381 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number)) | |
3382 | as_warn (_("operand overflow")); | |
3383 | ||
3384 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3385 | { | |
3386 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
3387 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3388 | (int) BFD_RELOC_LO16, breg); | |
3389 | } | |
3390 | else | |
3391 | { | |
3392 | /* 32-bit offset, need multiple instructions and AT, like: | |
3393 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3394 | addu $tempreg,$tempreg,$breg | |
3395 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3396 | to handle the complete offset. */ | |
3397 | macro_build_lui (place, counter, ep, AT); | |
3398 | if (place != NULL) | |
3399 | place += 4; | |
f899b4b8 | 3400 | macro_build (place, counter, (expressionS *) NULL, ADDRESS_ADD_INSN, |
885add95 CD |
3401 | "d,v,t", AT, AT, breg); |
3402 | if (place != NULL) | |
3403 | place += 4; | |
3404 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3405 | (int) BFD_RELOC_LO16, AT); | |
3406 | ||
3407 | if (mips_opts.noat) | |
3408 | as_warn (_("Macro used $at after \".set noat\"")); | |
3409 | } | |
3410 | } | |
3411 | ||
252b5132 RH |
3412 | /* set_at() |
3413 | * Generates code to set the $at register to true (one) | |
3414 | * if reg is less than the immediate expression. | |
3415 | */ | |
3416 | static void | |
3417 | set_at (counter, reg, unsignedp) | |
3418 | int *counter; | |
3419 | int reg; | |
3420 | int unsignedp; | |
3421 | { | |
3422 | if (imm_expr.X_op == O_constant | |
3423 | && imm_expr.X_add_number >= -0x8000 | |
3424 | && imm_expr.X_add_number < 0x8000) | |
3425 | macro_build ((char *) NULL, counter, &imm_expr, | |
3426 | unsignedp ? "sltiu" : "slti", | |
3427 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3428 | else | |
3429 | { | |
4d34fb5f | 3430 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 | 3431 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 RH |
3432 | unsignedp ? "sltu" : "slt", |
3433 | "d,v,t", AT, reg, AT); | |
3434 | } | |
3435 | } | |
3436 | ||
3437 | /* Warn if an expression is not a constant. */ | |
3438 | ||
3439 | static void | |
3440 | check_absolute_expr (ip, ex) | |
3441 | struct mips_cl_insn *ip; | |
3442 | expressionS *ex; | |
3443 | { | |
3444 | if (ex->X_op == O_big) | |
3445 | as_bad (_("unsupported large constant")); | |
3446 | else if (ex->X_op != O_constant) | |
3447 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3448 | } | |
3449 | ||
3450 | /* Count the leading zeroes by performing a binary chop. This is a | |
3451 | bulky bit of source, but performance is a LOT better for the | |
3452 | majority of values than a simple loop to count the bits: | |
3453 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3454 | if ((v) & (1 << (31 - lcnt))) | |
3455 | break; | |
3456 | However it is not code size friendly, and the gain will drop a bit | |
3457 | on certain cached systems. | |
3458 | */ | |
3459 | #define COUNT_TOP_ZEROES(v) \ | |
3460 | (((v) & ~0xffff) == 0 \ | |
3461 | ? ((v) & ~0xff) == 0 \ | |
3462 | ? ((v) & ~0xf) == 0 \ | |
3463 | ? ((v) & ~0x3) == 0 \ | |
3464 | ? ((v) & ~0x1) == 0 \ | |
3465 | ? !(v) \ | |
3466 | ? 32 \ | |
3467 | : 31 \ | |
3468 | : 30 \ | |
3469 | : ((v) & ~0x7) == 0 \ | |
3470 | ? 29 \ | |
3471 | : 28 \ | |
3472 | : ((v) & ~0x3f) == 0 \ | |
3473 | ? ((v) & ~0x1f) == 0 \ | |
3474 | ? 27 \ | |
3475 | : 26 \ | |
3476 | : ((v) & ~0x7f) == 0 \ | |
3477 | ? 25 \ | |
3478 | : 24 \ | |
3479 | : ((v) & ~0xfff) == 0 \ | |
3480 | ? ((v) & ~0x3ff) == 0 \ | |
3481 | ? ((v) & ~0x1ff) == 0 \ | |
3482 | ? 23 \ | |
3483 | : 22 \ | |
3484 | : ((v) & ~0x7ff) == 0 \ | |
3485 | ? 21 \ | |
3486 | : 20 \ | |
3487 | : ((v) & ~0x3fff) == 0 \ | |
3488 | ? ((v) & ~0x1fff) == 0 \ | |
3489 | ? 19 \ | |
3490 | : 18 \ | |
3491 | : ((v) & ~0x7fff) == 0 \ | |
3492 | ? 17 \ | |
3493 | : 16 \ | |
3494 | : ((v) & ~0xffffff) == 0 \ | |
3495 | ? ((v) & ~0xfffff) == 0 \ | |
3496 | ? ((v) & ~0x3ffff) == 0 \ | |
3497 | ? ((v) & ~0x1ffff) == 0 \ | |
3498 | ? 15 \ | |
3499 | : 14 \ | |
3500 | : ((v) & ~0x7ffff) == 0 \ | |
3501 | ? 13 \ | |
3502 | : 12 \ | |
3503 | : ((v) & ~0x3fffff) == 0 \ | |
3504 | ? ((v) & ~0x1fffff) == 0 \ | |
3505 | ? 11 \ | |
3506 | : 10 \ | |
3507 | : ((v) & ~0x7fffff) == 0 \ | |
3508 | ? 9 \ | |
3509 | : 8 \ | |
3510 | : ((v) & ~0xfffffff) == 0 \ | |
3511 | ? ((v) & ~0x3ffffff) == 0 \ | |
3512 | ? ((v) & ~0x1ffffff) == 0 \ | |
3513 | ? 7 \ | |
3514 | : 6 \ | |
3515 | : ((v) & ~0x7ffffff) == 0 \ | |
3516 | ? 5 \ | |
3517 | : 4 \ | |
3518 | : ((v) & ~0x3fffffff) == 0 \ | |
3519 | ? ((v) & ~0x1fffffff) == 0 \ | |
3520 | ? 3 \ | |
3521 | : 2 \ | |
3522 | : ((v) & ~0x7fffffff) == 0 \ | |
3523 | ? 1 \ | |
3524 | : 0) | |
3525 | ||
3526 | /* load_register() | |
3527 | * This routine generates the least number of instructions neccessary to load | |
3528 | * an absolute expression value into a register. | |
3529 | */ | |
3530 | static void | |
3531 | load_register (counter, reg, ep, dbl) | |
3532 | int *counter; | |
3533 | int reg; | |
3534 | expressionS *ep; | |
3535 | int dbl; | |
3536 | { | |
3537 | int freg; | |
3538 | expressionS hi32, lo32; | |
3539 | ||
3540 | if (ep->X_op != O_big) | |
3541 | { | |
3542 | assert (ep->X_op == O_constant); | |
3543 | if (ep->X_add_number < 0x8000 | |
3544 | && (ep->X_add_number >= 0 | |
3545 | || (ep->X_add_number >= -0x8000 | |
3546 | && (! dbl | |
3547 | || ! ep->X_unsigned | |
3548 | || sizeof (ep->X_add_number) > 4)))) | |
3549 | { | |
3550 | /* We can handle 16 bit signed values with an addiu to | |
3551 | $zero. No need to ever use daddiu here, since $zero and | |
3552 | the result are always correct in 32 bit mode. */ | |
3553 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3554 | (int) BFD_RELOC_LO16); | |
3555 | return; | |
3556 | } | |
3557 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3558 | { | |
3559 | /* We can handle 16 bit unsigned values with an ori to | |
3560 | $zero. */ | |
3561 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3562 | (int) BFD_RELOC_LO16); | |
3563 | return; | |
3564 | } | |
6373ee54 | 3565 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
252b5132 RH |
3566 | && (! dbl |
3567 | || ! ep->X_unsigned | |
3568 | || sizeof (ep->X_add_number) > 4 | |
3569 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3570 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3571 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3572 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3573 | && ! dbl |
3574 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3575 | == ~ (offsetT) 0xffffffff))) | |
3576 | { | |
3577 | /* 32 bit values require an lui. */ | |
3578 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3579 | (int) BFD_RELOC_HI16); | |
3580 | if ((ep->X_add_number & 0xffff) != 0) | |
3581 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3582 | (int) BFD_RELOC_LO16); | |
3583 | return; | |
3584 | } | |
3585 | } | |
3586 | ||
3587 | /* The value is larger than 32 bits. */ | |
3588 | ||
ca4e0257 | 3589 | if (HAVE_32BIT_GPRS) |
252b5132 | 3590 | { |
956cd1d6 TS |
3591 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3592 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3593 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3594 | (int) BFD_RELOC_LO16); | |
3595 | return; | |
3596 | } | |
3597 | ||
3598 | if (ep->X_op != O_big) | |
3599 | { | |
3600 | hi32 = *ep; | |
3601 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3602 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3603 | hi32.X_add_number &= 0xffffffff; | |
3604 | lo32 = *ep; | |
3605 | lo32.X_add_number &= 0xffffffff; | |
3606 | } | |
3607 | else | |
3608 | { | |
3609 | assert (ep->X_add_number > 2); | |
3610 | if (ep->X_add_number == 3) | |
3611 | generic_bignum[3] = 0; | |
3612 | else if (ep->X_add_number > 4) | |
3613 | as_bad (_("Number larger than 64 bits")); | |
3614 | lo32.X_op = O_constant; | |
3615 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3616 | hi32.X_op = O_constant; | |
3617 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3618 | } | |
3619 | ||
3620 | if (hi32.X_add_number == 0) | |
3621 | freg = 0; | |
3622 | else | |
3623 | { | |
3624 | int shift, bit; | |
3625 | unsigned long hi, lo; | |
3626 | ||
956cd1d6 | 3627 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3628 | { |
3629 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3630 | { | |
3631 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3632 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3633 | return; |
3634 | } | |
3635 | if (lo32.X_add_number & 0x80000000) | |
3636 | { | |
3637 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3638 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3639 | if (lo32.X_add_number & 0xffff) |
3640 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3641 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3642 | return; |
3643 | } | |
3644 | } | |
252b5132 RH |
3645 | |
3646 | /* Check for 16bit shifted constant. We know that hi32 is | |
3647 | non-zero, so start the mask on the first bit of the hi32 | |
3648 | value. */ | |
3649 | shift = 17; | |
3650 | do | |
beae10d5 KH |
3651 | { |
3652 | unsigned long himask, lomask; | |
3653 | ||
3654 | if (shift < 32) | |
3655 | { | |
3656 | himask = 0xffff >> (32 - shift); | |
3657 | lomask = (0xffff << shift) & 0xffffffff; | |
3658 | } | |
3659 | else | |
3660 | { | |
3661 | himask = 0xffff << (shift - 32); | |
3662 | lomask = 0; | |
3663 | } | |
3664 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3665 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3666 | { | |
3667 | expressionS tmp; | |
3668 | ||
3669 | tmp.X_op = O_constant; | |
3670 | if (shift < 32) | |
3671 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3672 | | (lo32.X_add_number >> shift)); | |
3673 | else | |
3674 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3675 | macro_build ((char *) NULL, counter, &tmp, | |
3676 | "ori", "t,r,i", reg, 0, | |
3677 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 3678 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3679 | (shift >= 32) ? "dsll32" : "dsll", |
3680 | "d,w,<", reg, reg, | |
3681 | (shift >= 32) ? shift - 32 : shift); | |
3682 | return; | |
3683 | } | |
f9419b05 | 3684 | ++shift; |
beae10d5 KH |
3685 | } |
3686 | while (shift <= (64 - 16)); | |
252b5132 RH |
3687 | |
3688 | /* Find the bit number of the lowest one bit, and store the | |
3689 | shifted value in hi/lo. */ | |
3690 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3691 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3692 | if (lo != 0) | |
3693 | { | |
3694 | bit = 0; | |
3695 | while ((lo & 1) == 0) | |
3696 | { | |
3697 | lo >>= 1; | |
3698 | ++bit; | |
3699 | } | |
3700 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3701 | hi >>= bit; | |
3702 | } | |
3703 | else | |
3704 | { | |
3705 | bit = 32; | |
3706 | while ((hi & 1) == 0) | |
3707 | { | |
3708 | hi >>= 1; | |
3709 | ++bit; | |
3710 | } | |
3711 | lo = hi; | |
3712 | hi = 0; | |
3713 | } | |
3714 | ||
3715 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3716 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3717 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3718 | { |
3719 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3720 | if (shift != 0) |
beae10d5 | 3721 | { |
252b5132 RH |
3722 | expressionS tmp; |
3723 | ||
3724 | /* This instruction will set the register to be all | |
3725 | ones. */ | |
beae10d5 KH |
3726 | tmp.X_op = O_constant; |
3727 | tmp.X_add_number = (offsetT) -1; | |
3728 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3729 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3730 | if (bit != 0) |
3731 | { | |
3732 | bit += shift; | |
2396cfb9 | 3733 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3734 | (bit >= 32) ? "dsll32" : "dsll", |
3735 | "d,w,<", reg, reg, | |
3736 | (bit >= 32) ? bit - 32 : bit); | |
3737 | } | |
2396cfb9 | 3738 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 | 3739 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3740 | "d,w,<", reg, reg, |
252b5132 | 3741 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3742 | return; |
3743 | } | |
3744 | } | |
252b5132 RH |
3745 | |
3746 | /* Sign extend hi32 before calling load_register, because we can | |
3747 | generally get better code when we load a sign extended value. */ | |
3748 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3749 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3750 | load_register (counter, reg, &hi32, 0); |
3751 | freg = reg; | |
3752 | } | |
3753 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3754 | { | |
3755 | if (freg != 0) | |
3756 | { | |
2396cfb9 TS |
3757 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3758 | "dsll32", "d,w,<", reg, freg, 0); | |
252b5132 RH |
3759 | freg = reg; |
3760 | } | |
3761 | } | |
3762 | else | |
3763 | { | |
3764 | expressionS mid16; | |
3765 | ||
956cd1d6 | 3766 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3767 | { |
252b5132 RH |
3768 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3769 | (int) BFD_RELOC_HI16); | |
956cd1d6 TS |
3770 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3771 | "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3772 | return; |
3773 | } | |
252b5132 RH |
3774 | |
3775 | if (freg != 0) | |
3776 | { | |
956cd1d6 TS |
3777 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3778 | "d,w,<", reg, freg, 16); | |
252b5132 RH |
3779 | freg = reg; |
3780 | } | |
3781 | mid16 = lo32; | |
3782 | mid16.X_add_number >>= 16; | |
3783 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3784 | freg, (int) BFD_RELOC_LO16); | |
956cd1d6 TS |
3785 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3786 | "d,w,<", reg, reg, 16); | |
252b5132 RH |
3787 | freg = reg; |
3788 | } | |
3789 | if ((lo32.X_add_number & 0xffff) != 0) | |
3790 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3791 | (int) BFD_RELOC_LO16); | |
3792 | } | |
3793 | ||
3794 | /* Load an address into a register. */ | |
3795 | ||
3796 | static void | |
c9914766 | 3797 | load_address (counter, reg, ep, used_at) |
252b5132 RH |
3798 | int *counter; |
3799 | int reg; | |
3800 | expressionS *ep; | |
d6bc6245 | 3801 | int *used_at; |
252b5132 | 3802 | { |
f9419b05 | 3803 | char *p = NULL; |
252b5132 RH |
3804 | |
3805 | if (ep->X_op != O_constant | |
3806 | && ep->X_op != O_symbol) | |
3807 | { | |
3808 | as_bad (_("expression too complex")); | |
3809 | ep->X_op = O_constant; | |
3810 | } | |
3811 | ||
3812 | if (ep->X_op == O_constant) | |
3813 | { | |
c9914766 | 3814 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3815 | return; |
3816 | } | |
3817 | ||
3818 | if (mips_pic == NO_PIC) | |
3819 | { | |
3820 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3821 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3822 | Otherwise we want |
3823 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3824 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3825 | If we have an addend, we always use the latter form. |
76b3015f | 3826 | |
d6bc6245 TS |
3827 | With 64bit address space and a usable $at we want |
3828 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3829 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3830 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3831 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3832 | dsll32 $reg,0 | |
3a482fd5 | 3833 | daddu $reg,$reg,$at |
76b3015f | 3834 | |
c03099e6 | 3835 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3836 | on superscalar processors. |
3837 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3838 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3839 | dsll $reg,16 | |
3840 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3841 | dsll $reg,16 | |
3842 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3843 | */ | |
c9914766 | 3844 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3845 | { |
d6bc6245 TS |
3846 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3847 | hold the data for such large chunks. */ | |
3848 | ||
460597ba | 3849 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
3850 | { |
3851 | macro_build (p, counter, ep, "lui", "t,u", | |
3852 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3853 | macro_build (p, counter, ep, "lui", "t,u", | |
3854 | AT, (int) BFD_RELOC_HI16_S); | |
3855 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3856 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3857 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3858 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3859 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
3860 | "d,w,<", reg, reg, 0); | |
3a482fd5 | 3861 | macro_build (p, counter, (expressionS *) NULL, "daddu", |
2396cfb9 | 3862 | "d,v,t", reg, reg, AT); |
d6bc6245 TS |
3863 | *used_at = 1; |
3864 | } | |
3865 | else | |
3866 | { | |
3867 | macro_build (p, counter, ep, "lui", "t,u", | |
3868 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3869 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3870 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
3871 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3872 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3873 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3874 | reg, reg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
3875 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3876 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3877 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3878 | reg, reg, (int) BFD_RELOC_LO16); | |
3879 | } | |
3880 | } | |
252b5132 RH |
3881 | else |
3882 | { | |
d6bc6245 TS |
3883 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3884 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3885 | { | |
3886 | frag_grow (20); | |
f899b4b8 TS |
3887 | macro_build ((char *) NULL, counter, ep, ADDRESS_ADDI_INSN, |
3888 | "t,r,j", reg, mips_gp_register, | |
3889 | (int) BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3890 | p = frag_var (rs_machine_dependent, 8, 0, |
3891 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3892 | mips_opts.warn_about_macros), | |
956cd1d6 | 3893 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3894 | } |
3895 | macro_build_lui (p, counter, ep, reg); | |
3896 | if (p != NULL) | |
3897 | p += 4; | |
f899b4b8 | 3898 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, |
d6bc6245 TS |
3899 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3900 | } | |
252b5132 RH |
3901 | } |
3902 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3903 | { | |
3904 | expressionS ex; | |
3905 | ||
3906 | /* If this is a reference to an external symbol, we want | |
3907 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3908 | Otherwise we want | |
3909 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3910 | nop | |
3911 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3912 | If there is a constant, it must be added in after. |
3913 | ||
ed6fb7bd | 3914 | If we have NewABI, we want |
f5040a92 AO |
3915 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3916 | unless we're referencing a global symbol with a non-zero | |
3917 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3918 | if (HAVE_NEWABI) |
3919 | { | |
f5040a92 | 3920 | frag_grow (12); |
684022ea | 3921 | |
f5040a92 AO |
3922 | if (ep->X_add_number) |
3923 | { | |
3924 | frag_now->tc_frag_data.tc_fr_offset = | |
3925 | ex.X_add_number = ep->X_add_number; | |
3926 | ep->X_add_number = 0; | |
f899b4b8 TS |
3927 | macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN, |
3928 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_DISP, | |
3929 | mips_gp_register); | |
f5040a92 AO |
3930 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3931 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3932 | ex.X_op = O_constant; | |
f899b4b8 | 3933 | macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN, |
f5040a92 AO |
3934 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3935 | p = frag_var (rs_machine_dependent, 8, 0, | |
3936 | RELAX_ENCODE (8, 4, 0, 0, 0, | |
3937 | mips_opts.warn_about_macros), | |
3938 | ep->X_add_symbol, 0, (char *) NULL); | |
3939 | ep->X_add_number = ex.X_add_number; | |
3940 | } | |
3941 | ||
f899b4b8 | 3942 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
ed6fb7bd | 3943 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
f5040a92 AO |
3944 | |
3945 | if (! p) | |
3946 | { | |
3947 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
3948 | that this does not become a variant frag. */ | |
3949 | frag_wane (frag_now); | |
3950 | frag_new (0); | |
3951 | } | |
ed6fb7bd SC |
3952 | } |
3953 | else | |
3954 | { | |
f5040a92 AO |
3955 | ex.X_add_number = ep->X_add_number; |
3956 | ep->X_add_number = 0; | |
3957 | frag_grow (20); | |
f899b4b8 TS |
3958 | macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN, |
3959 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, | |
3960 | mips_gp_register); | |
ed6fb7bd SC |
3961 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); |
3962 | p = frag_var (rs_machine_dependent, 4, 0, | |
3963 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3964 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
f899b4b8 | 3965 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, |
ed6fb7bd | 3966 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
ed6fb7bd | 3967 | |
f5040a92 AO |
3968 | if (ex.X_add_number != 0) |
3969 | { | |
3970 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3971 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3972 | ex.X_op = O_constant; | |
f899b4b8 | 3973 | macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN, |
f5040a92 AO |
3974 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3975 | } | |
252b5132 RH |
3976 | } |
3977 | } | |
3978 | else if (mips_pic == SVR4_PIC) | |
3979 | { | |
3980 | expressionS ex; | |
3981 | int off; | |
3982 | ||
3983 | /* This is the large GOT case. If this is a reference to an | |
3984 | external symbol, we want | |
3985 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3986 | addu $reg,$reg,$gp | |
3987 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3988 | |
3989 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3990 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3991 | nop | |
3992 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3993 | If there is a constant, it must be added in after. |
f5040a92 AO |
3994 | |
3995 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3996 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3997 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3998 | */ |
438c16b8 TS |
3999 | if (HAVE_NEWABI) |
4000 | { | |
f5040a92 AO |
4001 | frag_grow (24); |
4002 | ||
4003 | frag_now->tc_frag_data.tc_fr_offset = | |
4004 | ex.X_add_number = ep->X_add_number; | |
4005 | ep->X_add_number = 0; | |
4006 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
4007 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
4008 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
f899b4b8 TS |
4009 | ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
4010 | macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN, | |
f5040a92 AO |
4011 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
4012 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4013 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4014 | else if (ex.X_add_number) | |
4015 | { | |
4016 | ex.X_op = O_constant; | |
f899b4b8 | 4017 | macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN, |
f5040a92 AO |
4018 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
4019 | } | |
4020 | ||
4021 | ep->X_add_number = ex.X_add_number; | |
4022 | p = frag_var (rs_machine_dependent, 8, 0, | |
4023 | RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0, | |
4024 | mips_opts.warn_about_macros), | |
4025 | ep->X_add_symbol, 0, (char *) NULL); | |
f899b4b8 | 4026 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
438c16b8 | 4027 | (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f899b4b8 | 4028 | macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", |
438c16b8 TS |
4029 | reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST); |
4030 | } | |
252b5132 | 4031 | else |
438c16b8 | 4032 | { |
f5040a92 AO |
4033 | ex.X_add_number = ep->X_add_number; |
4034 | ep->X_add_number = 0; | |
438c16b8 TS |
4035 | if (reg_needs_delay (mips_gp_register)) |
4036 | off = 4; | |
4037 | else | |
4038 | off = 0; | |
4039 | frag_grow (32); | |
4040 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
4041 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
4042 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
f899b4b8 TS |
4043 | ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
4044 | macro_build ((char *) NULL, counter, ep, ADDRESS_LOAD_INSN, | |
438c16b8 TS |
4045 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
4046 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
4047 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
4048 | mips_opts.warn_about_macros), | |
4049 | ep->X_add_symbol, 0, NULL); | |
4050 | if (off > 0) | |
4051 | { | |
4052 | /* We need a nop before loading from $gp. This special | |
4053 | check is required because the lui which starts the main | |
4054 | instruction stream does not refer to $gp, and so will not | |
4055 | insert the nop which may be required. */ | |
4056 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
4057 | p += 4; | |
4058 | } | |
f899b4b8 | 4059 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
438c16b8 TS |
4060 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); |
4061 | p += 4; | |
252b5132 RH |
4062 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
4063 | p += 4; | |
f899b4b8 | 4064 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, |
438c16b8 | 4065 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
438c16b8 | 4066 | |
f5040a92 AO |
4067 | if (ex.X_add_number != 0) |
4068 | { | |
4069 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4070 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4071 | ex.X_op = O_constant; | |
f899b4b8 | 4072 | macro_build ((char *) NULL, counter, &ex, ADDRESS_ADDI_INSN, |
f5040a92 AO |
4073 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
4074 | } | |
252b5132 RH |
4075 | } |
4076 | } | |
4077 | else if (mips_pic == EMBEDDED_PIC) | |
4078 | { | |
4079 | /* We always do | |
cdf6fd85 | 4080 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 | 4081 | */ |
f899b4b8 | 4082 | macro_build ((char *) NULL, counter, ep, ADDRESS_ADDI_INSN, |
c9914766 | 4083 | "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16); |
252b5132 RH |
4084 | } |
4085 | else | |
4086 | abort (); | |
4087 | } | |
4088 | ||
ea1fb5dc RS |
4089 | /* Move the contents of register SOURCE into register DEST. */ |
4090 | ||
4091 | static void | |
4092 | move_register (counter, dest, source) | |
4093 | int *counter; | |
4094 | int dest; | |
4095 | int source; | |
4096 | { | |
4097 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
4098 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
4099 | "d,v,t", dest, source, 0); | |
4100 | } | |
4101 | ||
252b5132 RH |
4102 | /* |
4103 | * Build macros | |
4104 | * This routine implements the seemingly endless macro or synthesized | |
4105 | * instructions and addressing modes in the mips assembly language. Many | |
4106 | * of these macros are simple and are similar to each other. These could | |
4107 | * probably be handled by some kind of table or grammer aproach instead of | |
4108 | * this verbose method. Others are not simple macros but are more like | |
4109 | * optimizing code generation. | |
4110 | * One interesting optimization is when several store macros appear | |
4111 | * consecutivly that would load AT with the upper half of the same address. | |
4112 | * The ensuing load upper instructions are ommited. This implies some kind | |
4113 | * of global optimization. We currently only optimize within a single macro. | |
4114 | * For many of the load and store macros if the address is specified as a | |
4115 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4116 | * first load register 'at' with zero and use it as the base register. The | |
4117 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4118 | * we're missing. | |
4119 | */ | |
4120 | static void | |
4121 | macro (ip) | |
4122 | struct mips_cl_insn *ip; | |
4123 | { | |
4124 | register int treg, sreg, dreg, breg; | |
4125 | int tempreg; | |
4126 | int mask; | |
4127 | int icnt = 0; | |
43841e91 | 4128 | int used_at = 0; |
252b5132 RH |
4129 | expressionS expr1; |
4130 | const char *s; | |
4131 | const char *s2; | |
4132 | const char *fmt; | |
4133 | int likely = 0; | |
4134 | int dbl = 0; | |
4135 | int coproc = 0; | |
4136 | int lr = 0; | |
4137 | int imm = 0; | |
4138 | offsetT maxnum; | |
4139 | int off; | |
4140 | bfd_reloc_code_real_type r; | |
252b5132 RH |
4141 | int hold_mips_optimize; |
4142 | ||
4143 | assert (! mips_opts.mips16); | |
4144 | ||
4145 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4146 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4147 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4148 | mask = ip->insn_mo->mask; | |
4149 | ||
4150 | expr1.X_op = O_constant; | |
4151 | expr1.X_op_symbol = NULL; | |
4152 | expr1.X_add_symbol = NULL; | |
4153 | expr1.X_add_number = 1; | |
4154 | ||
5919d012 RS |
4155 | /* Umatched fixups should not be put in the same frag as a relaxable |
4156 | macro. For example, suppose we have: | |
4157 | ||
4158 | lui $4,%hi(l1) # 1 | |
4159 | la $5,l2 # 2 | |
4160 | addiu $4,$4,%lo(l1) # 3 | |
4161 | ||
4162 | If instructions 1 and 2 were put in the same frag, md_frob_file would | |
4163 | move the fixup for #1 after the fixups for the "unrelaxed" version of | |
4164 | #2. This would confuse tc_gen_reloc, which expects the relocations | |
4165 | for #2 to be the last for that frag. | |
4166 | ||
64bdfcaf RS |
4167 | Also, if tc_gen_reloc sees certain relocations in a variant frag, |
4168 | it assumes that they belong to a relaxable macro. We mustn't put | |
4169 | other uses of such relocations into a variant frag. | |
4170 | ||
4171 | To avoid both problems, finish the current frag it contains a | |
4172 | %reloc() operator. The macro then goes into a new frag. */ | |
4173 | if (prev_reloc_op_frag == frag_now) | |
5919d012 RS |
4174 | { |
4175 | frag_wane (frag_now); | |
4176 | frag_new (0); | |
4177 | } | |
4178 | ||
252b5132 RH |
4179 | switch (mask) |
4180 | { | |
4181 | case M_DABS: | |
4182 | dbl = 1; | |
4183 | case M_ABS: | |
4184 | /* bgez $a0,.+12 | |
4185 | move v0,$a0 | |
4186 | sub v0,$zero,$a0 | |
4187 | */ | |
4188 | ||
b34976b6 | 4189 | mips_emit_delays (TRUE); |
252b5132 RH |
4190 | ++mips_opts.noreorder; |
4191 | mips_any_noreorder = 1; | |
4192 | ||
4193 | expr1.X_add_number = 8; | |
4194 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
4195 | if (dreg == sreg) | |
2396cfb9 TS |
4196 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4197 | 0); | |
252b5132 | 4198 | else |
ea1fb5dc | 4199 | move_register (&icnt, dreg, sreg); |
2396cfb9 | 4200 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4201 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
4202 | |
4203 | --mips_opts.noreorder; | |
4204 | return; | |
4205 | ||
4206 | case M_ADD_I: | |
4207 | s = "addi"; | |
4208 | s2 = "add"; | |
4209 | goto do_addi; | |
4210 | case M_ADDU_I: | |
4211 | s = "addiu"; | |
4212 | s2 = "addu"; | |
4213 | goto do_addi; | |
4214 | case M_DADD_I: | |
4215 | dbl = 1; | |
4216 | s = "daddi"; | |
4217 | s2 = "dadd"; | |
4218 | goto do_addi; | |
4219 | case M_DADDU_I: | |
4220 | dbl = 1; | |
4221 | s = "daddiu"; | |
4222 | s2 = "daddu"; | |
4223 | do_addi: | |
4224 | if (imm_expr.X_op == O_constant | |
4225 | && imm_expr.X_add_number >= -0x8000 | |
4226 | && imm_expr.X_add_number < 0x8000) | |
4227 | { | |
4228 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
4229 | (int) BFD_RELOC_LO16); | |
4230 | return; | |
4231 | } | |
4232 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4233 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4234 | treg, sreg, AT); | |
252b5132 RH |
4235 | break; |
4236 | ||
4237 | case M_AND_I: | |
4238 | s = "andi"; | |
4239 | s2 = "and"; | |
4240 | goto do_bit; | |
4241 | case M_OR_I: | |
4242 | s = "ori"; | |
4243 | s2 = "or"; | |
4244 | goto do_bit; | |
4245 | case M_NOR_I: | |
4246 | s = ""; | |
4247 | s2 = "nor"; | |
4248 | goto do_bit; | |
4249 | case M_XOR_I: | |
4250 | s = "xori"; | |
4251 | s2 = "xor"; | |
4252 | do_bit: | |
4253 | if (imm_expr.X_op == O_constant | |
4254 | && imm_expr.X_add_number >= 0 | |
4255 | && imm_expr.X_add_number < 0x10000) | |
4256 | { | |
4257 | if (mask != M_NOR_I) | |
4258 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
4259 | sreg, (int) BFD_RELOC_LO16); | |
4260 | else | |
4261 | { | |
4262 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
4263 | treg, sreg, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4264 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
4265 | "d,v,t", treg, treg, 0); | |
252b5132 RH |
4266 | } |
4267 | return; | |
4268 | } | |
4269 | ||
d6bc6245 | 4270 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
4271 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4272 | treg, sreg, AT); | |
252b5132 RH |
4273 | break; |
4274 | ||
4275 | case M_BEQ_I: | |
4276 | s = "beq"; | |
4277 | goto beq_i; | |
4278 | case M_BEQL_I: | |
4279 | s = "beql"; | |
4280 | likely = 1; | |
4281 | goto beq_i; | |
4282 | case M_BNE_I: | |
4283 | s = "bne"; | |
4284 | goto beq_i; | |
4285 | case M_BNEL_I: | |
4286 | s = "bnel"; | |
4287 | likely = 1; | |
4288 | beq_i: | |
4289 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4290 | { | |
4291 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
4292 | 0); | |
4293 | return; | |
4294 | } | |
4d34fb5f | 4295 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
252b5132 RH |
4296 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
4297 | break; | |
4298 | ||
4299 | case M_BGEL: | |
4300 | likely = 1; | |
4301 | case M_BGE: | |
4302 | if (treg == 0) | |
4303 | { | |
4304 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4305 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4306 | return; |
4307 | } | |
4308 | if (sreg == 0) | |
4309 | { | |
4310 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4311 | likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4312 | return; |
4313 | } | |
2396cfb9 TS |
4314 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4315 | AT, sreg, treg); | |
252b5132 | 4316 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4317 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4318 | break; |
4319 | ||
4320 | case M_BGTL_I: | |
4321 | likely = 1; | |
4322 | case M_BGT_I: | |
4323 | /* check for > max integer */ | |
4324 | maxnum = 0x7fffffff; | |
ca4e0257 | 4325 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4326 | { |
4327 | maxnum <<= 16; | |
4328 | maxnum |= 0xffff; | |
4329 | maxnum <<= 16; | |
4330 | maxnum |= 0xffff; | |
4331 | } | |
4332 | if (imm_expr.X_op == O_constant | |
4333 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4334 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4335 | { |
4336 | do_false: | |
4337 | /* result is always false */ | |
4338 | if (! likely) | |
4339 | { | |
39c0a331 L |
4340 | if (warn_nops) |
4341 | as_warn (_("Branch %s is always false (nop)"), | |
4342 | ip->insn_mo->name); | |
2396cfb9 TS |
4343 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
4344 | "", 0); | |
252b5132 RH |
4345 | } |
4346 | else | |
4347 | { | |
39c0a331 L |
4348 | if (warn_nops) |
4349 | as_warn (_("Branch likely %s is always false"), | |
4350 | ip->insn_mo->name); | |
252b5132 RH |
4351 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
4352 | "s,t,p", 0, 0); | |
4353 | } | |
4354 | return; | |
4355 | } | |
4356 | if (imm_expr.X_op != O_constant) | |
4357 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4358 | ++imm_expr.X_add_number; |
252b5132 RH |
4359 | /* FALLTHROUGH */ |
4360 | case M_BGE_I: | |
4361 | case M_BGEL_I: | |
4362 | if (mask == M_BGEL_I) | |
4363 | likely = 1; | |
4364 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4365 | { | |
4366 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4367 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4368 | return; |
4369 | } | |
4370 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4371 | { | |
4372 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4373 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4374 | return; |
4375 | } | |
4376 | maxnum = 0x7fffffff; | |
ca4e0257 | 4377 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4378 | { |
4379 | maxnum <<= 16; | |
4380 | maxnum |= 0xffff; | |
4381 | maxnum <<= 16; | |
4382 | maxnum |= 0xffff; | |
4383 | } | |
4384 | maxnum = - maxnum - 1; | |
4385 | if (imm_expr.X_op == O_constant | |
4386 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4387 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4388 | { |
4389 | do_true: | |
4390 | /* result is always true */ | |
4391 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4392 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4393 | return; | |
4394 | } | |
4395 | set_at (&icnt, sreg, 0); | |
4396 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4397 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4398 | break; |
4399 | ||
4400 | case M_BGEUL: | |
4401 | likely = 1; | |
4402 | case M_BGEU: | |
4403 | if (treg == 0) | |
4404 | goto do_true; | |
4405 | if (sreg == 0) | |
4406 | { | |
4407 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4408 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4409 | return; |
4410 | } | |
2396cfb9 TS |
4411 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4412 | "d,v,t", AT, sreg, treg); | |
252b5132 | 4413 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4414 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4415 | break; |
4416 | ||
4417 | case M_BGTUL_I: | |
4418 | likely = 1; | |
4419 | case M_BGTU_I: | |
4420 | if (sreg == 0 | |
ca4e0257 | 4421 | || (HAVE_32BIT_GPRS |
252b5132 | 4422 | && imm_expr.X_op == O_constant |
956cd1d6 | 4423 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4424 | goto do_false; |
4425 | if (imm_expr.X_op != O_constant) | |
4426 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4427 | ++imm_expr.X_add_number; |
252b5132 RH |
4428 | /* FALLTHROUGH */ |
4429 | case M_BGEU_I: | |
4430 | case M_BGEUL_I: | |
4431 | if (mask == M_BGEUL_I) | |
4432 | likely = 1; | |
4433 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4434 | goto do_true; | |
4435 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4436 | { | |
4437 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4438 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4439 | return; |
4440 | } | |
4441 | set_at (&icnt, sreg, 1); | |
4442 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4443 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4444 | break; |
4445 | ||
4446 | case M_BGTL: | |
4447 | likely = 1; | |
4448 | case M_BGT: | |
4449 | if (treg == 0) | |
4450 | { | |
4451 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4452 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4453 | return; |
4454 | } | |
4455 | if (sreg == 0) | |
4456 | { | |
4457 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4458 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4459 | return; |
4460 | } | |
2396cfb9 TS |
4461 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4462 | AT, treg, sreg); | |
252b5132 | 4463 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4464 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4465 | break; |
4466 | ||
4467 | case M_BGTUL: | |
4468 | likely = 1; | |
4469 | case M_BGTU: | |
4470 | if (treg == 0) | |
4471 | { | |
4472 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4473 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4474 | return; |
4475 | } | |
4476 | if (sreg == 0) | |
4477 | goto do_false; | |
2396cfb9 TS |
4478 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4479 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4480 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4481 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4482 | break; |
4483 | ||
4484 | case M_BLEL: | |
4485 | likely = 1; | |
4486 | case M_BLE: | |
4487 | if (treg == 0) | |
4488 | { | |
4489 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4490 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4491 | return; |
4492 | } | |
4493 | if (sreg == 0) | |
4494 | { | |
4495 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4496 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4497 | return; |
4498 | } | |
2396cfb9 TS |
4499 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4500 | AT, treg, sreg); | |
252b5132 | 4501 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4502 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4503 | break; |
4504 | ||
4505 | case M_BLEL_I: | |
4506 | likely = 1; | |
4507 | case M_BLE_I: | |
4508 | maxnum = 0x7fffffff; | |
ca4e0257 | 4509 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4510 | { |
4511 | maxnum <<= 16; | |
4512 | maxnum |= 0xffff; | |
4513 | maxnum <<= 16; | |
4514 | maxnum |= 0xffff; | |
4515 | } | |
4516 | if (imm_expr.X_op == O_constant | |
4517 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4518 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4519 | goto do_true; |
4520 | if (imm_expr.X_op != O_constant) | |
4521 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4522 | ++imm_expr.X_add_number; |
252b5132 RH |
4523 | /* FALLTHROUGH */ |
4524 | case M_BLT_I: | |
4525 | case M_BLTL_I: | |
4526 | if (mask == M_BLTL_I) | |
4527 | likely = 1; | |
4528 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4529 | { | |
4530 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4531 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4532 | return; |
4533 | } | |
4534 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4535 | { | |
4536 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4537 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4538 | return; |
4539 | } | |
4540 | set_at (&icnt, sreg, 0); | |
4541 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4542 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4543 | break; |
4544 | ||
4545 | case M_BLEUL: | |
4546 | likely = 1; | |
4547 | case M_BLEU: | |
4548 | if (treg == 0) | |
4549 | { | |
4550 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4551 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4552 | return; |
4553 | } | |
4554 | if (sreg == 0) | |
4555 | goto do_true; | |
2396cfb9 TS |
4556 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4557 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4558 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4559 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4560 | break; |
4561 | ||
4562 | case M_BLEUL_I: | |
4563 | likely = 1; | |
4564 | case M_BLEU_I: | |
4565 | if (sreg == 0 | |
ca4e0257 | 4566 | || (HAVE_32BIT_GPRS |
252b5132 | 4567 | && imm_expr.X_op == O_constant |
956cd1d6 | 4568 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4569 | goto do_true; |
4570 | if (imm_expr.X_op != O_constant) | |
4571 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4572 | ++imm_expr.X_add_number; |
252b5132 RH |
4573 | /* FALLTHROUGH */ |
4574 | case M_BLTU_I: | |
4575 | case M_BLTUL_I: | |
4576 | if (mask == M_BLTUL_I) | |
4577 | likely = 1; | |
4578 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4579 | goto do_false; | |
4580 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4581 | { | |
4582 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4583 | likely ? "beql" : "beq", | |
4584 | "s,t,p", sreg, 0); | |
4585 | return; | |
4586 | } | |
4587 | set_at (&icnt, sreg, 1); | |
4588 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4589 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4590 | break; |
4591 | ||
4592 | case M_BLTL: | |
4593 | likely = 1; | |
4594 | case M_BLT: | |
4595 | if (treg == 0) | |
4596 | { | |
4597 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4598 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4599 | return; |
4600 | } | |
4601 | if (sreg == 0) | |
4602 | { | |
4603 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4604 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4605 | return; |
4606 | } | |
2396cfb9 TS |
4607 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4608 | AT, sreg, treg); | |
252b5132 | 4609 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4610 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4611 | break; |
4612 | ||
4613 | case M_BLTUL: | |
4614 | likely = 1; | |
4615 | case M_BLTU: | |
4616 | if (treg == 0) | |
4617 | goto do_false; | |
4618 | if (sreg == 0) | |
4619 | { | |
4620 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4621 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4622 | return; |
4623 | } | |
2396cfb9 TS |
4624 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4625 | "d,v,t", AT, sreg, | |
252b5132 RH |
4626 | treg); |
4627 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4628 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4629 | break; |
4630 | ||
4631 | case M_DDIV_3: | |
4632 | dbl = 1; | |
4633 | case M_DIV_3: | |
4634 | s = "mflo"; | |
4635 | goto do_div3; | |
4636 | case M_DREM_3: | |
4637 | dbl = 1; | |
4638 | case M_REM_3: | |
4639 | s = "mfhi"; | |
4640 | do_div3: | |
4641 | if (treg == 0) | |
4642 | { | |
4643 | as_warn (_("Divide by zero.")); | |
4644 | if (mips_trap) | |
2396cfb9 | 4645 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4646 | "s,t,q", 0, 0, 7); |
252b5132 | 4647 | else |
2396cfb9 TS |
4648 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4649 | "c", 7); | |
252b5132 RH |
4650 | return; |
4651 | } | |
4652 | ||
b34976b6 | 4653 | mips_emit_delays (TRUE); |
252b5132 RH |
4654 | ++mips_opts.noreorder; |
4655 | mips_any_noreorder = 1; | |
4656 | if (mips_trap) | |
4657 | { | |
2396cfb9 | 4658 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4659 | "s,t,q", treg, 0, 7); |
2396cfb9 | 4660 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4661 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4662 | } |
4663 | else | |
4664 | { | |
4665 | expr1.X_add_number = 8; | |
4666 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 | 4667 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4668 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
2396cfb9 TS |
4669 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4670 | "c", 7); | |
252b5132 RH |
4671 | } |
4672 | expr1.X_add_number = -1; | |
4673 | macro_build ((char *) NULL, &icnt, &expr1, | |
4674 | dbl ? "daddiu" : "addiu", | |
4675 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4676 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4677 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4678 | if (dbl) | |
4679 | { | |
4680 | expr1.X_add_number = 1; | |
4681 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4682 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4683 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
4684 | "d,w,<", AT, AT, 31); | |
252b5132 RH |
4685 | } |
4686 | else | |
4687 | { | |
4688 | expr1.X_add_number = 0x80000000; | |
4689 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4690 | (int) BFD_RELOC_HI16); | |
4691 | } | |
4692 | if (mips_trap) | |
4693 | { | |
2396cfb9 | 4694 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4695 | "s,t,q", sreg, AT, 6); |
252b5132 RH |
4696 | /* We want to close the noreorder block as soon as possible, so |
4697 | that later insns are available for delay slot filling. */ | |
4698 | --mips_opts.noreorder; | |
4699 | } | |
4700 | else | |
4701 | { | |
4702 | expr1.X_add_number = 8; | |
4703 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2396cfb9 TS |
4704 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4705 | 0); | |
252b5132 RH |
4706 | |
4707 | /* We want to close the noreorder block as soon as possible, so | |
4708 | that later insns are available for delay slot filling. */ | |
4709 | --mips_opts.noreorder; | |
4710 | ||
2396cfb9 TS |
4711 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4712 | "c", 6); | |
252b5132 | 4713 | } |
2396cfb9 | 4714 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
252b5132 RH |
4715 | break; |
4716 | ||
4717 | case M_DIV_3I: | |
4718 | s = "div"; | |
4719 | s2 = "mflo"; | |
4720 | goto do_divi; | |
4721 | case M_DIVU_3I: | |
4722 | s = "divu"; | |
4723 | s2 = "mflo"; | |
4724 | goto do_divi; | |
4725 | case M_REM_3I: | |
4726 | s = "div"; | |
4727 | s2 = "mfhi"; | |
4728 | goto do_divi; | |
4729 | case M_REMU_3I: | |
4730 | s = "divu"; | |
4731 | s2 = "mfhi"; | |
4732 | goto do_divi; | |
4733 | case M_DDIV_3I: | |
4734 | dbl = 1; | |
4735 | s = "ddiv"; | |
4736 | s2 = "mflo"; | |
4737 | goto do_divi; | |
4738 | case M_DDIVU_3I: | |
4739 | dbl = 1; | |
4740 | s = "ddivu"; | |
4741 | s2 = "mflo"; | |
4742 | goto do_divi; | |
4743 | case M_DREM_3I: | |
4744 | dbl = 1; | |
4745 | s = "ddiv"; | |
4746 | s2 = "mfhi"; | |
4747 | goto do_divi; | |
4748 | case M_DREMU_3I: | |
4749 | dbl = 1; | |
4750 | s = "ddivu"; | |
4751 | s2 = "mfhi"; | |
4752 | do_divi: | |
4753 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4754 | { | |
4755 | as_warn (_("Divide by zero.")); | |
4756 | if (mips_trap) | |
2396cfb9 | 4757 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4758 | "s,t,q", 0, 0, 7); |
252b5132 | 4759 | else |
2396cfb9 TS |
4760 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4761 | "c", 7); | |
252b5132 RH |
4762 | return; |
4763 | } | |
4764 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4765 | { | |
4766 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4767 | move_register (&icnt, dreg, sreg); |
252b5132 | 4768 | else |
ea1fb5dc | 4769 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4770 | return; |
4771 | } | |
4772 | if (imm_expr.X_op == O_constant | |
4773 | && imm_expr.X_add_number == -1 | |
4774 | && s[strlen (s) - 1] != 'u') | |
4775 | { | |
4776 | if (strcmp (s2, "mflo") == 0) | |
4777 | { | |
2396cfb9 TS |
4778 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4779 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); | |
252b5132 RH |
4780 | } |
4781 | else | |
ea1fb5dc | 4782 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4783 | return; |
4784 | } | |
4785 | ||
4786 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4787 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4788 | sreg, AT); | |
4789 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); | |
252b5132 RH |
4790 | break; |
4791 | ||
4792 | case M_DIVU_3: | |
4793 | s = "divu"; | |
4794 | s2 = "mflo"; | |
4795 | goto do_divu3; | |
4796 | case M_REMU_3: | |
4797 | s = "divu"; | |
4798 | s2 = "mfhi"; | |
4799 | goto do_divu3; | |
4800 | case M_DDIVU_3: | |
4801 | s = "ddivu"; | |
4802 | s2 = "mflo"; | |
4803 | goto do_divu3; | |
4804 | case M_DREMU_3: | |
4805 | s = "ddivu"; | |
4806 | s2 = "mfhi"; | |
4807 | do_divu3: | |
b34976b6 | 4808 | mips_emit_delays (TRUE); |
252b5132 RH |
4809 | ++mips_opts.noreorder; |
4810 | mips_any_noreorder = 1; | |
4811 | if (mips_trap) | |
4812 | { | |
2396cfb9 | 4813 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4814 | "s,t,q", treg, 0, 7); |
2396cfb9 TS |
4815 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4816 | sreg, treg); | |
252b5132 RH |
4817 | /* We want to close the noreorder block as soon as possible, so |
4818 | that later insns are available for delay slot filling. */ | |
4819 | --mips_opts.noreorder; | |
4820 | } | |
4821 | else | |
4822 | { | |
4823 | expr1.X_add_number = 8; | |
4824 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 TS |
4825 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4826 | sreg, treg); | |
252b5132 RH |
4827 | |
4828 | /* We want to close the noreorder block as soon as possible, so | |
4829 | that later insns are available for delay slot filling. */ | |
4830 | --mips_opts.noreorder; | |
2396cfb9 TS |
4831 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4832 | "c", 7); | |
252b5132 | 4833 | } |
2396cfb9 | 4834 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
252b5132 RH |
4835 | return; |
4836 | ||
4837 | case M_DLA_AB: | |
4838 | dbl = 1; | |
4839 | case M_LA_AB: | |
4840 | /* Load the address of a symbol into a register. If breg is not | |
4841 | zero, we then add a base register to it. */ | |
4842 | ||
3bec30a8 TS |
4843 | if (dbl && HAVE_32BIT_GPRS) |
4844 | as_warn (_("dla used to load 32-bit register")); | |
4845 | ||
c90bbe5b | 4846 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4847 | as_warn (_("la used to load 64-bit address")); |
4848 | ||
0c11417f MR |
4849 | if (offset_expr.X_op == O_constant |
4850 | && offset_expr.X_add_number >= -0x8000 | |
4851 | && offset_expr.X_add_number < 0x8000) | |
4852 | { | |
4853 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f5040a92 AO |
4854 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : |
4855 | HAVE_NEWABI ? "addi" : "addiu", | |
0c11417f MR |
4856 | "t,r,j", treg, sreg, (int) BFD_RELOC_LO16); |
4857 | return; | |
4858 | } | |
4859 | ||
afdbd6d0 CD |
4860 | if (treg == breg) |
4861 | { | |
4862 | tempreg = AT; | |
4863 | used_at = 1; | |
4864 | } | |
4865 | else | |
4866 | { | |
4867 | tempreg = treg; | |
4868 | used_at = 0; | |
4869 | } | |
4870 | ||
252b5132 RH |
4871 | /* When generating embedded PIC code, we permit expressions of |
4872 | the form | |
afdbd6d0 CD |
4873 | la $treg,foo-bar |
4874 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4875 | where bar is an address in the current section. These are used |
252b5132 RH |
4876 | when getting the addresses of functions. We don't permit |
4877 | X_add_number to be non-zero, because if the symbol is | |
4878 | external the relaxing code needs to know that any addend is | |
4879 | purely the offset to X_op_symbol. */ | |
4880 | if (mips_pic == EMBEDDED_PIC | |
4881 | && offset_expr.X_op == O_subtract | |
49309057 | 4882 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4883 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4884 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4885 | && (S_GET_SEGMENT | |
4886 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4887 | ->X_add_symbol) | |
bb2d6cd7 | 4888 | == now_seg))) |
bb2d6cd7 GK |
4889 | && (offset_expr.X_add_number == 0 |
4890 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4891 | { |
afdbd6d0 CD |
4892 | if (breg == 0) |
4893 | { | |
4894 | tempreg = treg; | |
4895 | used_at = 0; | |
4896 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4897 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4898 | } | |
4899 | else | |
4900 | { | |
4901 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4902 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4903 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4d34fb5f | 4904 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4905 | "d,v,t", tempreg, tempreg, breg); |
4906 | } | |
252b5132 | 4907 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 4908 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
afdbd6d0 CD |
4909 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
4910 | if (! used_at) | |
4911 | return; | |
4912 | break; | |
252b5132 RH |
4913 | } |
4914 | ||
4915 | if (offset_expr.X_op != O_symbol | |
4916 | && offset_expr.X_op != O_constant) | |
4917 | { | |
4918 | as_bad (_("expression too complex")); | |
4919 | offset_expr.X_op = O_constant; | |
4920 | } | |
4921 | ||
252b5132 | 4922 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4923 | load_register (&icnt, tempreg, &offset_expr, |
4924 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4925 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4926 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4927 | else if (mips_pic == NO_PIC) |
4928 | { | |
d6bc6245 | 4929 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4930 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4931 | Otherwise we want |
4932 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4933 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4934 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4935 | so we may as well always use the latter form. |
76b3015f | 4936 | |
d6bc6245 TS |
4937 | With 64bit address space and a usable $at we want |
4938 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4939 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4940 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4941 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4942 | dsll32 $tempreg,0 | |
3a482fd5 | 4943 | daddu $tempreg,$tempreg,$at |
76b3015f | 4944 | |
c03099e6 | 4945 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4946 | on superscalar processors. |
4947 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4948 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4949 | dsll $tempreg,16 | |
4950 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4951 | dsll $tempreg,16 | |
4952 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4953 | */ | |
f9419b05 | 4954 | char *p = NULL; |
d6bc6245 | 4955 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4956 | { |
d6bc6245 TS |
4957 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4958 | hold the data for such large chunks. */ | |
4959 | ||
460597ba | 4960 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f KH |
4961 | { |
4962 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4963 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4964 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4965 | AT, (int) BFD_RELOC_HI16_S); | |
4966 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4967 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4968 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4969 | AT, AT, (int) BFD_RELOC_LO16); | |
4970 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
4971 | "d,w,<", tempreg, tempreg, 0); | |
3a482fd5 MR |
4972 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
4973 | "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4974 | used_at = 1; |
4975 | } | |
4976 | else | |
4977 | { | |
4978 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4979 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4980 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4981 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4982 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4983 | tempreg, tempreg, 16); | |
4984 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4985 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
4986 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4987 | tempreg, tempreg, 16); | |
4988 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4989 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4990 | } | |
4991 | } | |
4992 | else | |
4993 | { | |
4994 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4995 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4996 | { | |
4997 | frag_grow (20); | |
f5040a92 | 4998 | macro_build ((char *) NULL, &icnt, &offset_expr, |
f899b4b8 TS |
4999 | ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
5000 | mips_gp_register, (int) BFD_RELOC_GPREL16); | |
98d3f06f KH |
5001 | p = frag_var (rs_machine_dependent, 8, 0, |
5002 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5003 | mips_opts.warn_about_macros), | |
5004 | offset_expr.X_add_symbol, 0, NULL); | |
5005 | } | |
5006 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5007 | if (p != NULL) | |
5008 | p += 4; | |
f899b4b8 | 5009 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
98d3f06f KH |
5010 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5011 | } | |
252b5132 | 5012 | } |
f5040a92 | 5013 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 5014 | { |
9117d219 NC |
5015 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5016 | ||
252b5132 RH |
5017 | /* If this is a reference to an external symbol, and there |
5018 | is no constant, we want | |
5019 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
5020 | or if tempreg is PIC_CALL_REG |
5021 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
5022 | For a local symbol, we want |
5023 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5024 | nop | |
5025 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5026 | ||
5027 | If we have a small constant, and this is a reference to | |
5028 | an external symbol, we want | |
5029 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5030 | nop | |
5031 | addiu $tempreg,$tempreg,<constant> | |
5032 | For a local symbol, we want the same instruction | |
5033 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5034 | addiu instruction. | |
5035 | ||
5036 | If we have a large constant, and this is a reference to | |
5037 | an external symbol, we want | |
5038 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5039 | lui $at,<hiconstant> | |
5040 | addiu $at,$at,<loconstant> | |
5041 | addu $tempreg,$tempreg,$at | |
5042 | For a local symbol, we want the same instruction | |
5043 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5044 | addiu instruction. |
ed6fb7bd SC |
5045 | */ |
5046 | ||
252b5132 RH |
5047 | expr1.X_add_number = offset_expr.X_add_number; |
5048 | offset_expr.X_add_number = 0; | |
5049 | frag_grow (32); | |
9117d219 NC |
5050 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5051 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
f899b4b8 | 5052 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
c9914766 | 5053 | "t,o(b)", tempreg, lw_reloc_type, mips_gp_register); |
252b5132 RH |
5054 | if (expr1.X_add_number == 0) |
5055 | { | |
5056 | int off; | |
f9419b05 | 5057 | char *p; |
252b5132 RH |
5058 | |
5059 | if (breg == 0) | |
5060 | off = 0; | |
5061 | else | |
5062 | { | |
5063 | /* We're going to put in an addu instruction using | |
5064 | tempreg, so we may as well insert the nop right | |
5065 | now. */ | |
5066 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5067 | "nop", ""); | |
5068 | off = 4; | |
5069 | } | |
5070 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
5071 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
5072 | (breg == 0 | |
5073 | ? mips_opts.warn_about_macros | |
5074 | : 0)), | |
c4e7957c | 5075 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5076 | if (breg == 0) |
5077 | { | |
5078 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5079 | p += 4; | |
5080 | } | |
f899b4b8 | 5081 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5082 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5083 | /* FIXME: If breg == 0, and the next instruction uses | |
5084 | $tempreg, then if this variant case is used an extra | |
5085 | nop will be generated. */ | |
5086 | } | |
5087 | else if (expr1.X_add_number >= -0x8000 | |
5088 | && expr1.X_add_number < 0x8000) | |
5089 | { | |
5090 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5091 | "nop", ""); | |
f899b4b8 | 5092 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 | 5093 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
c4e7957c TS |
5094 | frag_var (rs_machine_dependent, 0, 0, |
5095 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
5096 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5097 | } |
5098 | else | |
5099 | { | |
5100 | int off1; | |
5101 | ||
5102 | /* If we are going to add in a base register, and the | |
5103 | target register and the base register are the same, | |
5104 | then we are using AT as a temporary register. Since | |
5105 | we want to load the constant into AT, we add our | |
5106 | current AT (from the global offset table) and the | |
5107 | register into the register now, and pretend we were | |
5108 | not using a base register. */ | |
5109 | if (breg != treg) | |
5110 | off1 = 0; | |
5111 | else | |
5112 | { | |
5113 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5114 | "nop", ""); | |
5115 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5116 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
252b5132 RH |
5117 | breg = 0; |
5118 | tempreg = treg; | |
5119 | off1 = -8; | |
5120 | } | |
5121 | ||
5122 | /* Set mips_optimize around the lui instruction to avoid | |
5123 | inserting an unnecessary nop after the lw. */ | |
5124 | hold_mips_optimize = mips_optimize; | |
5125 | mips_optimize = 2; | |
c4e7957c | 5126 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5127 | mips_optimize = hold_mips_optimize; |
5128 | ||
f899b4b8 | 5129 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5130 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5131 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5132 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, AT); |
c4e7957c TS |
5133 | frag_var (rs_machine_dependent, 0, 0, |
5134 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
5135 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
5136 | used_at = 1; |
5137 | } | |
5138 | } | |
f5040a92 AO |
5139 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5140 | { | |
5141 | char *p = NULL; | |
5142 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
5143 | int adj = 0; | |
5144 | ||
5145 | /* If this is a reference to an external, and there is no | |
5146 | constant, or local symbol (*), with or without a | |
5147 | constant, we want | |
5148 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5149 | or if tempreg is PIC_CALL_REG | |
5150 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5151 | ||
5152 | If we have a small constant, and this is a reference to | |
5153 | an external symbol, we want | |
5154 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5155 | addiu $tempreg,$tempreg,<constant> | |
5156 | ||
5157 | If we have a large constant, and this is a reference to | |
5158 | an external symbol, we want | |
5159 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5160 | lui $at,<hiconstant> | |
5161 | addiu $at,$at,<loconstant> | |
5162 | addu $tempreg,$tempreg,$at | |
5163 | ||
5164 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5165 | local symbols, even though it introduces an additional | |
5166 | instruction. */ | |
5167 | ||
5168 | frag_grow (28); | |
5169 | if (offset_expr.X_add_number == 0 && tempreg == PIC_CALL_REG) | |
5170 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5171 | if (offset_expr.X_add_number) | |
5172 | { | |
5173 | frag_now->tc_frag_data.tc_fr_offset = | |
5174 | expr1.X_add_number = offset_expr.X_add_number; | |
5175 | offset_expr.X_add_number = 0; | |
5176 | ||
5177 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 TS |
5178 | ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5179 | lw_reloc_type, mips_gp_register); | |
f5040a92 AO |
5180 | |
5181 | if (expr1.X_add_number >= -0x8000 | |
5182 | && expr1.X_add_number < 0x8000) | |
5183 | { | |
5184 | macro_build ((char *) NULL, &icnt, &expr1, | |
f899b4b8 | 5185 | ADDRESS_ADDI_INSN, "t,r,j", tempreg, tempreg, |
f5040a92 AO |
5186 | (int) BFD_RELOC_LO16); |
5187 | p = frag_var (rs_machine_dependent, 4, 0, | |
5188 | RELAX_ENCODE (8, 4, 0, 0, 0, 0), | |
5189 | offset_expr.X_add_symbol, 0, NULL); | |
5190 | } | |
5191 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number)) | |
5192 | { | |
5193 | int dreg; | |
5194 | ||
5195 | /* If we are going to add in a base register, and the | |
5196 | target register and the base register are the same, | |
5197 | then we are using AT as a temporary register. Since | |
5198 | we want to load the constant into AT, we add our | |
5199 | current AT (from the global offset table) and the | |
5200 | register into the register now, and pretend we were | |
5201 | not using a base register. */ | |
5202 | if (breg != treg) | |
5203 | dreg = tempreg; | |
5204 | else | |
5205 | { | |
5206 | assert (tempreg == AT); | |
5207 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5208 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
f5040a92 AO |
5209 | dreg = treg; |
5210 | adj = 4; | |
5211 | } | |
5212 | ||
5213 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
5214 | macro_build ((char *) NULL, &icnt, &expr1, | |
f899b4b8 TS |
5215 | ADDRESS_ADDI_INSN, "t,r,j", AT, AT, |
5216 | (int) BFD_RELOC_LO16); | |
f5040a92 | 5217 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
f899b4b8 | 5218 | ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 AO |
5219 | |
5220 | p = frag_var (rs_machine_dependent, 4 + adj, 0, | |
5221 | RELAX_ENCODE (16 + adj, 4 + adj, | |
5222 | 0, 0, 0, 0), | |
5223 | offset_expr.X_add_symbol, 0, NULL); | |
5224 | ||
5225 | used_at = 1; | |
5226 | } | |
5227 | else | |
5228 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5229 | ||
5230 | offset_expr.X_add_number = expr1.X_add_number; | |
5231 | ||
f899b4b8 | 5232 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
f5040a92 AO |
5233 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_DISP, |
5234 | mips_gp_register); | |
5235 | if (adj) | |
5236 | { | |
5237 | macro_build (p + 4, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
5238 | ADDRESS_ADD_INSN, "d,v,t", |
5239 | treg, tempreg, breg); | |
f5040a92 AO |
5240 | breg = 0; |
5241 | tempreg = treg; | |
5242 | } | |
5243 | } | |
5244 | else | |
5245 | { | |
5246 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 TS |
5247 | ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5248 | lw_reloc_type, mips_gp_register); | |
f5040a92 AO |
5249 | if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP) |
5250 | p = frag_var (rs_machine_dependent, 0, 0, | |
5251 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5252 | offset_expr.X_add_symbol, 0, NULL); | |
5253 | } | |
5254 | ||
5255 | if (! p) | |
5256 | { | |
5257 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5258 | that this does not become a variant frag. */ | |
5259 | frag_wane (frag_now); | |
5260 | frag_new (0); | |
5261 | } | |
5262 | } | |
5263 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 RH |
5264 | { |
5265 | int gpdel; | |
f9419b05 | 5266 | char *p; |
9117d219 NC |
5267 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5268 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5269 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5270 | |
5271 | /* This is the large GOT case. If this is a reference to an | |
5272 | external symbol, and there is no constant, we want | |
5273 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5274 | addu $tempreg,$tempreg,$gp | |
5275 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
5276 | or if tempreg is PIC_CALL_REG |
5277 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5278 | addu $tempreg,$tempreg,$gp | |
5279 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5280 | For a local symbol, we want |
5281 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5282 | nop | |
5283 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5284 | ||
5285 | If we have a small constant, and this is a reference to | |
5286 | an external symbol, we want | |
5287 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5288 | addu $tempreg,$tempreg,$gp | |
5289 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5290 | nop | |
5291 | addiu $tempreg,$tempreg,<constant> | |
5292 | For a local symbol, we want | |
5293 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5294 | nop | |
5295 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5296 | ||
5297 | If we have a large constant, and this is a reference to | |
5298 | an external symbol, we want | |
5299 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5300 | addu $tempreg,$tempreg,$gp | |
5301 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5302 | lui $at,<hiconstant> | |
5303 | addiu $at,$at,<loconstant> | |
5304 | addu $tempreg,$tempreg,$at | |
5305 | For a local symbol, we want | |
5306 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5307 | lui $at,<hiconstant> | |
5308 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5309 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5310 | */ |
438c16b8 | 5311 | |
252b5132 RH |
5312 | expr1.X_add_number = offset_expr.X_add_number; |
5313 | offset_expr.X_add_number = 0; | |
5314 | frag_grow (52); | |
f7ea7ef2 | 5315 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5316 | gpdel = 4; |
5317 | else | |
5318 | gpdel = 0; | |
9117d219 NC |
5319 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5320 | { | |
5321 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5322 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5323 | } | |
252b5132 | 5324 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 5325 | tempreg, lui_reloc_type); |
252b5132 | 5326 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
f899b4b8 TS |
5327 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
5328 | mips_gp_register); | |
5329 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
9117d219 | 5330 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5331 | if (expr1.X_add_number == 0) |
5332 | { | |
5333 | int off; | |
5334 | ||
5335 | if (breg == 0) | |
5336 | off = 0; | |
5337 | else | |
5338 | { | |
5339 | /* We're going to put in an addu instruction using | |
5340 | tempreg, so we may as well insert the nop right | |
5341 | now. */ | |
5342 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5343 | "nop", ""); | |
5344 | off = 4; | |
5345 | } | |
5346 | ||
5347 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5348 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
5349 | 8 + gpdel, 0, | |
5350 | (breg == 0 | |
5351 | ? mips_opts.warn_about_macros | |
5352 | : 0)), | |
c4e7957c | 5353 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5354 | } |
5355 | else if (expr1.X_add_number >= -0x8000 | |
5356 | && expr1.X_add_number < 0x8000) | |
5357 | { | |
5358 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5359 | "nop", ""); | |
f899b4b8 | 5360 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5361 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5362 | ||
5363 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5364 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
5365 | (breg == 0 | |
5366 | ? mips_opts.warn_about_macros | |
5367 | : 0)), | |
c4e7957c | 5368 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5369 | } |
5370 | else | |
5371 | { | |
5372 | int adj, dreg; | |
5373 | ||
5374 | /* If we are going to add in a base register, and the | |
5375 | target register and the base register are the same, | |
5376 | then we are using AT as a temporary register. Since | |
5377 | we want to load the constant into AT, we add our | |
5378 | current AT (from the global offset table) and the | |
5379 | register into the register now, and pretend we were | |
5380 | not using a base register. */ | |
5381 | if (breg != treg) | |
5382 | { | |
5383 | adj = 0; | |
5384 | dreg = tempreg; | |
5385 | } | |
5386 | else | |
5387 | { | |
5388 | assert (tempreg == AT); | |
5389 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5390 | "nop", ""); | |
5391 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5392 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
252b5132 RH |
5393 | dreg = treg; |
5394 | adj = 8; | |
5395 | } | |
5396 | ||
5397 | /* Set mips_optimize around the lui instruction to avoid | |
5398 | inserting an unnecessary nop after the lw. */ | |
5399 | hold_mips_optimize = mips_optimize; | |
5400 | mips_optimize = 2; | |
c4e7957c | 5401 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5402 | mips_optimize = hold_mips_optimize; |
5403 | ||
f899b4b8 | 5404 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5405 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5406 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5407 | ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 RH |
5408 | |
5409 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5410 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5411 | 8 + gpdel, 0, | |
5412 | (breg == 0 | |
5413 | ? mips_opts.warn_about_macros | |
5414 | : 0)), | |
c4e7957c | 5415 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5416 | |
5417 | used_at = 1; | |
5418 | } | |
5419 | ||
5420 | if (gpdel > 0) | |
5421 | { | |
5422 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5423 | the first instruction on the main stream does not. */ |
252b5132 RH |
5424 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
5425 | p += 4; | |
5426 | } | |
ed6fb7bd | 5427 | |
f899b4b8 TS |
5428 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5429 | tempreg, local_reloc_type, mips_gp_register); | |
252b5132 | 5430 | p += 4; |
f5040a92 | 5431 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5432 | && expr1.X_add_number < 0x8000) |
5433 | { | |
5434 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5435 | p += 4; | |
f899b4b8 | 5436 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5437 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5438 | /* FIXME: If add_number is 0, and there was no base | |
f5040a92 AO |
5439 | register, the external symbol case ended with a load, |
5440 | so if the symbol turns out to not be external, and | |
5441 | the next instruction uses tempreg, an unnecessary nop | |
5442 | will be inserted. */ | |
252b5132 RH |
5443 | } |
5444 | else | |
5445 | { | |
5446 | if (breg == treg) | |
5447 | { | |
5448 | /* We must add in the base register now, as in the | |
f5040a92 | 5449 | external symbol case. */ |
252b5132 RH |
5450 | assert (tempreg == AT); |
5451 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5452 | p += 4; | |
5453 | macro_build (p, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5454 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
252b5132 RH |
5455 | p += 4; |
5456 | tempreg = treg; | |
5457 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5458 | it in in both cases. */ |
252b5132 RH |
5459 | breg = 0; |
5460 | } | |
5461 | ||
5462 | macro_build_lui (p, &icnt, &expr1, AT); | |
5463 | p += 4; | |
f899b4b8 | 5464 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
252b5132 RH |
5465 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5466 | p += 4; | |
f899b4b8 | 5467 | macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
252b5132 RH |
5468 | "d,v,t", tempreg, tempreg, AT); |
5469 | p += 4; | |
5470 | } | |
5471 | } | |
f5040a92 AO |
5472 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5473 | { | |
5474 | char *p = NULL; | |
5475 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; | |
5476 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
5477 | int adj = 0; | |
5478 | ||
5479 | /* This is the large GOT case. If this is a reference to an | |
5480 | external symbol, and there is no constant, we want | |
5481 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5482 | add $tempreg,$tempreg,$gp | |
5483 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5484 | or if tempreg is PIC_CALL_REG | |
5485 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5486 | add $tempreg,$tempreg,$gp | |
5487 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5488 | ||
5489 | If we have a small constant, and this is a reference to | |
5490 | an external symbol, we want | |
5491 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5492 | add $tempreg,$tempreg,$gp | |
5493 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5494 | addi $tempreg,$tempreg,<constant> | |
5495 | ||
5496 | If we have a large constant, and this is a reference to | |
5497 | an external symbol, we want | |
5498 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5499 | addu $tempreg,$tempreg,$gp | |
5500 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5501 | lui $at,<hiconstant> | |
5502 | addi $at,$at,<loconstant> | |
5503 | add $tempreg,$tempreg,$at | |
5504 | ||
5505 | If we have NewABI, and we know it's a local symbol, we want | |
5506 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5507 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5508 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5509 | ||
5510 | frag_grow (40); | |
5511 | ||
5512 | frag_now->tc_frag_data.tc_fr_offset = | |
5513 | expr1.X_add_number = offset_expr.X_add_number; | |
5514 | offset_expr.X_add_number = 0; | |
5515 | ||
5516 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) | |
5517 | { | |
5518 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5519 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5520 | } | |
5521 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5522 | tempreg, lui_reloc_type); | |
5523 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
5524 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
5525 | mips_gp_register); | |
5526 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
f5040a92 AO |
5527 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
5528 | ||
5529 | if (expr1.X_add_number == 0) | |
5530 | { | |
5531 | p = frag_var (rs_machine_dependent, 8, 0, | |
5532 | RELAX_ENCODE (12, 8, 0, 4, 0, | |
5533 | mips_opts.warn_about_macros), | |
5534 | offset_expr.X_add_symbol, 0, NULL); | |
684022ea | 5535 | } |
f5040a92 AO |
5536 | else if (expr1.X_add_number >= -0x8000 |
5537 | && expr1.X_add_number < 0x8000) | |
5538 | { | |
f899b4b8 | 5539 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
f5040a92 AO |
5540 | "t,r,j", tempreg, tempreg, |
5541 | (int) BFD_RELOC_LO16); | |
5542 | p = frag_var (rs_machine_dependent, 8, 0, | |
5543 | RELAX_ENCODE (16, 8, 0, 4, 0, | |
5544 | mips_opts.warn_about_macros), | |
5545 | offset_expr.X_add_symbol, 0, NULL); | |
5546 | } | |
5547 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number)) | |
5548 | { | |
5549 | int dreg; | |
5550 | ||
5551 | /* If we are going to add in a base register, and the | |
5552 | target register and the base register are the same, | |
5553 | then we are using AT as a temporary register. Since | |
5554 | we want to load the constant into AT, we add our | |
5555 | current AT (from the global offset table) and the | |
5556 | register into the register now, and pretend we were | |
5557 | not using a base register. */ | |
5558 | if (breg != treg) | |
5559 | dreg = tempreg; | |
5560 | else | |
5561 | { | |
5562 | assert (tempreg == AT); | |
5563 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5564 | ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); |
f5040a92 AO |
5565 | dreg = treg; |
5566 | adj = 4; | |
5567 | } | |
5568 | ||
5569 | /* Set mips_optimize around the lui instruction to avoid | |
5570 | inserting an unnecessary nop after the lw. */ | |
5571 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
f899b4b8 | 5572 | macro_build ((char *) NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
f5040a92 AO |
5573 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5574 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5575 | ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 AO |
5576 | |
5577 | p = frag_var (rs_machine_dependent, 8 + adj, 0, | |
5578 | RELAX_ENCODE (24 + adj, 8 + adj, | |
5579 | 0, 4, 0, | |
5580 | (breg == 0 | |
5581 | ? mips_opts.warn_about_macros | |
5582 | : 0)), | |
5583 | offset_expr.X_add_symbol, 0, NULL); | |
5584 | ||
5585 | used_at = 1; | |
5586 | } | |
5587 | else | |
5588 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5589 | ||
5590 | offset_expr.X_add_number = expr1.X_add_number; | |
f899b4b8 TS |
5591 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5592 | tempreg, (int) BFD_RELOC_MIPS_GOT_PAGE, | |
5593 | mips_gp_register); | |
5594 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
f5040a92 AO |
5595 | tempreg, tempreg, (int) BFD_RELOC_MIPS_GOT_OFST); |
5596 | if (adj) | |
5597 | { | |
5598 | macro_build (p + 8, &icnt, (expressionS *) NULL, | |
f899b4b8 | 5599 | ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
f5040a92 AO |
5600 | breg = 0; |
5601 | tempreg = treg; | |
5602 | } | |
5603 | } | |
252b5132 RH |
5604 | else if (mips_pic == EMBEDDED_PIC) |
5605 | { | |
5606 | /* We use | |
cdf6fd85 | 5607 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 | 5608 | */ |
f899b4b8 TS |
5609 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
5610 | "t,r,j", tempreg, mips_gp_register, | |
5611 | (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
5612 | } |
5613 | else | |
5614 | abort (); | |
5615 | ||
5616 | if (breg != 0) | |
4d34fb5f TS |
5617 | { |
5618 | char *s; | |
5619 | ||
5620 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
f5040a92 AO |
5621 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : |
5622 | HAVE_NEWABI ? "add" : "addu"; | |
4d34fb5f | 5623 | else |
f899b4b8 | 5624 | s = ADDRESS_ADD_INSN; |
4d34fb5f TS |
5625 | |
5626 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
5627 | "d,v,t", treg, tempreg, breg); | |
5628 | } | |
252b5132 RH |
5629 | |
5630 | if (! used_at) | |
5631 | return; | |
5632 | ||
5633 | break; | |
5634 | ||
5635 | case M_J_A: | |
5636 | /* The j instruction may not be used in PIC code, since it | |
5637 | requires an absolute address. We convert it to a b | |
5638 | instruction. */ | |
5639 | if (mips_pic == NO_PIC) | |
5640 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
5641 | else | |
5642 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
5643 | return; | |
5644 | ||
5645 | /* The jal instructions must be handled as macros because when | |
5646 | generating PIC code they expand to multi-instruction | |
5647 | sequences. Normally they are simple instructions. */ | |
5648 | case M_JAL_1: | |
5649 | dreg = RA; | |
5650 | /* Fall through. */ | |
5651 | case M_JAL_2: | |
5652 | if (mips_pic == NO_PIC | |
5653 | || mips_pic == EMBEDDED_PIC) | |
5654 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
5655 | "d,s", dreg, sreg); | |
5656 | else if (mips_pic == SVR4_PIC) | |
5657 | { | |
5658 | if (sreg != PIC_CALL_REG) | |
5659 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5660 | |
252b5132 RH |
5661 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
5662 | "d,s", dreg, sreg); | |
6478892d | 5663 | if (! HAVE_NEWABI) |
252b5132 | 5664 | { |
6478892d TS |
5665 | if (mips_cprestore_offset < 0) |
5666 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5667 | else | |
5668 | { | |
7a621144 DJ |
5669 | if (! mips_frame_reg_valid) |
5670 | { | |
5671 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5672 | /* Quiet this warning. */ | |
5673 | mips_frame_reg_valid = 1; | |
5674 | } | |
5675 | if (! mips_cprestore_valid) | |
5676 | { | |
5677 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5678 | /* Quiet this warning. */ | |
5679 | mips_cprestore_valid = 1; | |
5680 | } | |
6478892d | 5681 | expr1.X_add_number = mips_cprestore_offset; |
885add95 | 5682 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
f899b4b8 TS |
5683 | ADDRESS_LOAD_INSN, |
5684 | mips_gp_register, | |
5685 | mips_frame_reg); | |
6478892d | 5686 | } |
252b5132 RH |
5687 | } |
5688 | } | |
5689 | else | |
5690 | abort (); | |
5691 | ||
5692 | return; | |
5693 | ||
5694 | case M_JAL_A: | |
5695 | if (mips_pic == NO_PIC) | |
5696 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5697 | else if (mips_pic == SVR4_PIC) | |
5698 | { | |
f9419b05 TS |
5699 | char *p; |
5700 | ||
252b5132 RH |
5701 | /* If this is a reference to an external symbol, and we are |
5702 | using a small GOT, we want | |
5703 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5704 | nop | |
f9419b05 | 5705 | jalr $ra,$25 |
252b5132 RH |
5706 | nop |
5707 | lw $gp,cprestore($sp) | |
5708 | The cprestore value is set using the .cprestore | |
5709 | pseudo-op. If we are using a big GOT, we want | |
5710 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5711 | addu $25,$25,$gp | |
5712 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5713 | nop | |
f9419b05 | 5714 | jalr $ra,$25 |
252b5132 RH |
5715 | nop |
5716 | lw $gp,cprestore($sp) | |
5717 | If the symbol is not external, we want | |
5718 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5719 | nop | |
5720 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5721 | jalr $ra,$25 |
252b5132 | 5722 | nop |
438c16b8 | 5723 | lw $gp,cprestore($sp) |
f5040a92 AO |
5724 | |
5725 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5726 | sequences above, minus nops, unless the symbol is local, | |
5727 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5728 | GOT_DISP. */ | |
438c16b8 | 5729 | if (HAVE_NEWABI) |
252b5132 | 5730 | { |
f5040a92 AO |
5731 | if (! mips_big_got) |
5732 | { | |
5733 | frag_grow (4); | |
5734 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 | 5735 | ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, |
f5040a92 AO |
5736 | (int) BFD_RELOC_MIPS_CALL16, |
5737 | mips_gp_register); | |
5738 | frag_var (rs_machine_dependent, 0, 0, | |
5739 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5740 | offset_expr.X_add_symbol, 0, NULL); | |
5741 | } | |
5742 | else | |
5743 | { | |
5744 | frag_grow (20); | |
5745 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", | |
5746 | "t,u", PIC_CALL_REG, | |
5747 | (int) BFD_RELOC_MIPS_CALL_HI16); | |
5748 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
5749 | ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, |
5750 | PIC_CALL_REG, mips_gp_register); | |
f5040a92 | 5751 | macro_build ((char *) NULL, &icnt, &offset_expr, |
f899b4b8 | 5752 | ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, |
f5040a92 AO |
5753 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); |
5754 | p = frag_var (rs_machine_dependent, 8, 0, | |
5755 | RELAX_ENCODE (12, 8, 0, 4, 0, 0), | |
5756 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 TS |
5757 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5758 | "t,o(b)", PIC_CALL_REG, | |
5759 | (int) BFD_RELOC_MIPS_GOT_PAGE, | |
f5040a92 | 5760 | mips_gp_register); |
f899b4b8 | 5761 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
dc9461f6 | 5762 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
f5040a92 AO |
5763 | (int) BFD_RELOC_MIPS_GOT_OFST); |
5764 | } | |
684022ea | 5765 | |
438c16b8 | 5766 | macro_build_jalr (icnt, &offset_expr); |
252b5132 RH |
5767 | } |
5768 | else | |
5769 | { | |
438c16b8 TS |
5770 | frag_grow (40); |
5771 | if (! mips_big_got) | |
5772 | { | |
5773 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 | 5774 | ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, |
438c16b8 TS |
5775 | (int) BFD_RELOC_MIPS_CALL16, mips_gp_register); |
5776 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5777 | "nop", ""); | |
5778 | p = frag_var (rs_machine_dependent, 4, 0, | |
5779 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5780 | offset_expr.X_add_symbol, 0, NULL); | |
5781 | } | |
252b5132 | 5782 | else |
252b5132 | 5783 | { |
438c16b8 TS |
5784 | int gpdel; |
5785 | ||
5786 | if (reg_needs_delay (mips_gp_register)) | |
5787 | gpdel = 4; | |
5788 | else | |
5789 | gpdel = 0; | |
5790 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", | |
5791 | "t,u", PIC_CALL_REG, | |
5792 | (int) BFD_RELOC_MIPS_CALL_HI16); | |
5793 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
5794 | ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, |
5795 | PIC_CALL_REG, mips_gp_register); | |
438c16b8 | 5796 | macro_build ((char *) NULL, &icnt, &offset_expr, |
f899b4b8 | 5797 | ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, |
438c16b8 TS |
5798 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); |
5799 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5800 | "nop", ""); | |
5801 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5802 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5803 | 8 + gpdel, 0, 0), | |
5804 | offset_expr.X_add_symbol, 0, NULL); | |
5805 | if (gpdel > 0) | |
5806 | { | |
5807 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5808 | p += 4; | |
5809 | } | |
f899b4b8 | 5810 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
438c16b8 TS |
5811 | "t,o(b)", PIC_CALL_REG, |
5812 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
5813 | p += 4; | |
252b5132 RH |
5814 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
5815 | p += 4; | |
5816 | } | |
f899b4b8 | 5817 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
438c16b8 TS |
5818 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
5819 | (int) BFD_RELOC_LO16); | |
5820 | macro_build_jalr (icnt, &offset_expr); | |
5821 | ||
6478892d TS |
5822 | if (mips_cprestore_offset < 0) |
5823 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5824 | else | |
5825 | { | |
7a621144 DJ |
5826 | if (! mips_frame_reg_valid) |
5827 | { | |
5828 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5829 | /* Quiet this warning. */ | |
5830 | mips_frame_reg_valid = 1; | |
5831 | } | |
5832 | if (! mips_cprestore_valid) | |
5833 | { | |
5834 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5835 | /* Quiet this warning. */ | |
5836 | mips_cprestore_valid = 1; | |
5837 | } | |
6478892d TS |
5838 | if (mips_opts.noreorder) |
5839 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
98d3f06f | 5840 | "nop", ""); |
6478892d | 5841 | expr1.X_add_number = mips_cprestore_offset; |
885add95 | 5842 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
f899b4b8 TS |
5843 | ADDRESS_LOAD_INSN, |
5844 | mips_gp_register, | |
5845 | mips_frame_reg); | |
6478892d | 5846 | } |
252b5132 RH |
5847 | } |
5848 | } | |
5849 | else if (mips_pic == EMBEDDED_PIC) | |
5850 | { | |
5851 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5852 | /* The linker may expand the call to a longer sequence which | |
5853 | uses $at, so we must break rather than return. */ | |
5854 | break; | |
5855 | } | |
5856 | else | |
5857 | abort (); | |
5858 | ||
5859 | return; | |
5860 | ||
5861 | case M_LB_AB: | |
5862 | s = "lb"; | |
5863 | goto ld; | |
5864 | case M_LBU_AB: | |
5865 | s = "lbu"; | |
5866 | goto ld; | |
5867 | case M_LH_AB: | |
5868 | s = "lh"; | |
5869 | goto ld; | |
5870 | case M_LHU_AB: | |
5871 | s = "lhu"; | |
5872 | goto ld; | |
5873 | case M_LW_AB: | |
5874 | s = "lw"; | |
5875 | goto ld; | |
5876 | case M_LWC0_AB: | |
5877 | s = "lwc0"; | |
bdaaa2e1 | 5878 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5879 | coproc = 1; |
5880 | goto ld; | |
5881 | case M_LWC1_AB: | |
5882 | s = "lwc1"; | |
bdaaa2e1 | 5883 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5884 | coproc = 1; |
5885 | goto ld; | |
5886 | case M_LWC2_AB: | |
5887 | s = "lwc2"; | |
bdaaa2e1 | 5888 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5889 | coproc = 1; |
5890 | goto ld; | |
5891 | case M_LWC3_AB: | |
5892 | s = "lwc3"; | |
bdaaa2e1 | 5893 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5894 | coproc = 1; |
5895 | goto ld; | |
5896 | case M_LWL_AB: | |
5897 | s = "lwl"; | |
5898 | lr = 1; | |
5899 | goto ld; | |
5900 | case M_LWR_AB: | |
5901 | s = "lwr"; | |
5902 | lr = 1; | |
5903 | goto ld; | |
5904 | case M_LDC1_AB: | |
ec68c924 | 5905 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5906 | { |
5907 | as_bad (_("opcode not supported on this processor")); | |
5908 | return; | |
5909 | } | |
5910 | s = "ldc1"; | |
bdaaa2e1 | 5911 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5912 | coproc = 1; |
5913 | goto ld; | |
5914 | case M_LDC2_AB: | |
5915 | s = "ldc2"; | |
bdaaa2e1 | 5916 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5917 | coproc = 1; |
5918 | goto ld; | |
5919 | case M_LDC3_AB: | |
5920 | s = "ldc3"; | |
bdaaa2e1 | 5921 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5922 | coproc = 1; |
5923 | goto ld; | |
5924 | case M_LDL_AB: | |
5925 | s = "ldl"; | |
5926 | lr = 1; | |
5927 | goto ld; | |
5928 | case M_LDR_AB: | |
5929 | s = "ldr"; | |
5930 | lr = 1; | |
5931 | goto ld; | |
5932 | case M_LL_AB: | |
5933 | s = "ll"; | |
5934 | goto ld; | |
5935 | case M_LLD_AB: | |
5936 | s = "lld"; | |
5937 | goto ld; | |
5938 | case M_LWU_AB: | |
5939 | s = "lwu"; | |
5940 | ld: | |
5941 | if (breg == treg || coproc || lr) | |
5942 | { | |
5943 | tempreg = AT; | |
5944 | used_at = 1; | |
5945 | } | |
5946 | else | |
5947 | { | |
5948 | tempreg = treg; | |
5949 | used_at = 0; | |
5950 | } | |
5951 | goto ld_st; | |
5952 | case M_SB_AB: | |
5953 | s = "sb"; | |
5954 | goto st; | |
5955 | case M_SH_AB: | |
5956 | s = "sh"; | |
5957 | goto st; | |
5958 | case M_SW_AB: | |
5959 | s = "sw"; | |
5960 | goto st; | |
5961 | case M_SWC0_AB: | |
5962 | s = "swc0"; | |
bdaaa2e1 | 5963 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5964 | coproc = 1; |
5965 | goto st; | |
5966 | case M_SWC1_AB: | |
5967 | s = "swc1"; | |
bdaaa2e1 | 5968 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5969 | coproc = 1; |
5970 | goto st; | |
5971 | case M_SWC2_AB: | |
5972 | s = "swc2"; | |
bdaaa2e1 | 5973 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5974 | coproc = 1; |
5975 | goto st; | |
5976 | case M_SWC3_AB: | |
5977 | s = "swc3"; | |
bdaaa2e1 | 5978 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5979 | coproc = 1; |
5980 | goto st; | |
5981 | case M_SWL_AB: | |
5982 | s = "swl"; | |
5983 | goto st; | |
5984 | case M_SWR_AB: | |
5985 | s = "swr"; | |
5986 | goto st; | |
5987 | case M_SC_AB: | |
5988 | s = "sc"; | |
5989 | goto st; | |
5990 | case M_SCD_AB: | |
5991 | s = "scd"; | |
5992 | goto st; | |
5993 | case M_SDC1_AB: | |
ec68c924 | 5994 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5995 | { |
5996 | as_bad (_("opcode not supported on this processor")); | |
5997 | return; | |
5998 | } | |
5999 | s = "sdc1"; | |
6000 | coproc = 1; | |
bdaaa2e1 | 6001 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6002 | goto st; |
6003 | case M_SDC2_AB: | |
6004 | s = "sdc2"; | |
bdaaa2e1 | 6005 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6006 | coproc = 1; |
6007 | goto st; | |
6008 | case M_SDC3_AB: | |
6009 | s = "sdc3"; | |
bdaaa2e1 | 6010 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6011 | coproc = 1; |
6012 | goto st; | |
6013 | case M_SDL_AB: | |
6014 | s = "sdl"; | |
6015 | goto st; | |
6016 | case M_SDR_AB: | |
6017 | s = "sdr"; | |
6018 | st: | |
6019 | tempreg = AT; | |
6020 | used_at = 1; | |
6021 | ld_st: | |
bdaaa2e1 | 6022 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6023 | if (mask == M_LWC1_AB |
6024 | || mask == M_SWC1_AB | |
6025 | || mask == M_LDC1_AB | |
6026 | || mask == M_SDC1_AB | |
6027 | || mask == M_L_DAB | |
6028 | || mask == M_S_DAB) | |
6029 | fmt = "T,o(b)"; | |
6030 | else if (coproc) | |
6031 | fmt = "E,o(b)"; | |
6032 | else | |
6033 | fmt = "t,o(b)"; | |
6034 | ||
afdbd6d0 CD |
6035 | /* For embedded PIC, we allow loads where the offset is calculated |
6036 | by subtracting a symbol in the current segment from an unknown | |
6037 | symbol, relative to a base register, e.g.: | |
6038 | <op> $treg, <sym>-<localsym>($breg) | |
6039 | This is used by the compiler for switch statements. */ | |
76b3015f | 6040 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
6041 | && offset_expr.X_op == O_subtract |
6042 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
6043 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
6044 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
6045 | && (S_GET_SEGMENT | |
6046 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
6047 | ->X_add_symbol) | |
6048 | == now_seg))) | |
6049 | && breg != 0 | |
6050 | && (offset_expr.X_add_number == 0 | |
6051 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
6052 | { | |
6053 | /* For this case, we output the instructions: | |
6054 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
6055 | addiu $tempreg,$tempreg,$breg | |
6056 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
6057 | If the relocation would fit entirely in 16 bits, it would be | |
6058 | nice to emit: | |
6059 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
6060 | instead, but that seems quite difficult. */ | |
6061 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6062 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
6063 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6064 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
6065 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
f5040a92 | 6066 | ? HAVE_NEWABI ? "add" : "addu" : "daddu"), |
afdbd6d0 CD |
6067 | "d,v,t", tempreg, tempreg, breg); |
6068 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, | |
6069 | (int) BFD_RELOC_PCREL_LO16, tempreg); | |
6070 | if (! used_at) | |
6071 | return; | |
6072 | break; | |
6073 | } | |
6074 | ||
252b5132 RH |
6075 | if (offset_expr.X_op != O_constant |
6076 | && offset_expr.X_op != O_symbol) | |
6077 | { | |
6078 | as_bad (_("expression too complex")); | |
6079 | offset_expr.X_op = O_constant; | |
6080 | } | |
6081 | ||
6082 | /* A constant expression in PIC code can be handled just as it | |
6083 | is in non PIC code. */ | |
6084 | if (mips_pic == NO_PIC | |
6085 | || offset_expr.X_op == O_constant) | |
6086 | { | |
f9419b05 TS |
6087 | char *p; |
6088 | ||
252b5132 RH |
6089 | /* If this is a reference to a GP relative symbol, and there |
6090 | is no base register, we want | |
cdf6fd85 | 6091 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6092 | Otherwise, if there is no base register, we want |
6093 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6094 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6095 | If we have a constant, we need two instructions anyhow, | |
6096 | so we always use the latter form. | |
6097 | ||
6098 | If we have a base register, and this is a reference to a | |
6099 | GP relative symbol, we want | |
6100 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6101 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6102 | Otherwise we want |
6103 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6104 | addu $tempreg,$tempreg,$breg | |
6105 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6106 | With a constant we always use the latter case. |
76b3015f | 6107 | |
d6bc6245 TS |
6108 | With 64bit address space and no base register and $at usable, |
6109 | we want | |
6110 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6111 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6112 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6113 | dsll32 $tempreg,0 | |
6114 | daddu $tempreg,$at | |
6115 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6116 | If we have a base register, we want | |
6117 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6118 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6119 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6120 | daddu $at,$breg | |
6121 | dsll32 $tempreg,0 | |
6122 | daddu $tempreg,$at | |
6123 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6124 | ||
6125 | Without $at we can't generate the optimal path for superscalar | |
6126 | processors here since this would require two temporary registers. | |
6127 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6128 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6129 | dsll $tempreg,16 | |
6130 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6131 | dsll $tempreg,16 | |
6132 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6133 | If we have a base register, we want | |
6134 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6135 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6136 | dsll $tempreg,16 | |
6137 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6138 | dsll $tempreg,16 | |
6139 | daddu $tempreg,$tempreg,$breg | |
6140 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
6141 | |
6142 | If we have 64-bit addresses, as an optimization, for | |
6143 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
6144 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
6145 | mechanism since it is more efficient. Note that due to |
6146 | the signed offset used by memory operations, the 32-bit | |
6147 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
6148 | probably attempt to generate 64-bit constants more |
6149 | efficiently in general. | |
9214dd3b AO |
6150 | |
6151 | As an extension for architectures with 64-bit registers, | |
6152 | we don't truncate 64-bit addresses given as literal | |
6153 | constants down to 32 bits, to support existing practice | |
6154 | in the mips64 Linux (the kernel), that compiles source | |
6155 | files with -mabi=64, assembling them as o32 or n32 (with | |
6156 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
6157 | the whole kernel is loaded into a memory region that is | |
6158 | addressible with sign-extended 32-bit addresses, it is | |
6159 | wasteful to compute the upper 32 bits of every | |
6160 | non-literal address, that takes more space and time. | |
6161 | Some day this should probably be implemented as an | |
6162 | assembler option, such that the kernel doesn't have to | |
6163 | use such ugly hacks, even though it will still have to | |
6164 | end up converting the binary to ELF32 for a number of | |
6165 | platforms whose boot loaders don't support ELF64 | |
6166 | binaries. */ | |
5a7a0b7b AO |
6167 | if ((offset_expr.X_op != O_constant && HAVE_64BIT_ADDRESSES) |
6168 | || (offset_expr.X_op == O_constant | |
eb0a7d52 | 6169 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000) |
5a7a0b7b | 6170 | && HAVE_64BIT_ADDRESS_CONSTANTS)) |
d6bc6245 TS |
6171 | { |
6172 | p = NULL; | |
6173 | ||
6174 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
6175 | hold the data for such large chunks. */ | |
6176 | ||
460597ba | 6177 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
6178 | { |
6179 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
6180 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
6181 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
6182 | AT, (int) BFD_RELOC_HI16_S); | |
6183 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
6184 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
6185 | if (breg != 0) | |
2396cfb9 TS |
6186 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
6187 | "d,v,t", AT, AT, breg); | |
6188 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
6189 | "d,w,<", tempreg, tempreg, 0); | |
6190 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", | |
6191 | "d,v,t", tempreg, tempreg, AT); | |
d6bc6245 TS |
6192 | macro_build (p, &icnt, &offset_expr, s, |
6193 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
6194 | used_at = 1; | |
6195 | } | |
6196 | else | |
6197 | { | |
6198 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
6199 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
6200 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
6201 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
6202 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
6203 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 TS |
6204 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
6205 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
6206 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
6207 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6208 | if (breg != 0) |
2396cfb9 TS |
6209 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
6210 | "d,v,t", tempreg, tempreg, breg); | |
d6bc6245 TS |
6211 | macro_build (p, &icnt, &offset_expr, s, |
6212 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
6213 | } | |
6214 | ||
6215 | return; | |
6216 | } | |
5a7a0b7b | 6217 | else if (offset_expr.X_op == O_constant |
eb0a7d52 | 6218 | && !HAVE_64BIT_ADDRESS_CONSTANTS |
5a7a0b7b AO |
6219 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
6220 | as_bad (_("load/store address overflow (max 32 bits)")); | |
76b3015f | 6221 | |
252b5132 RH |
6222 | if (breg == 0) |
6223 | { | |
e7d556df | 6224 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6225 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6226 | p = NULL; | |
6227 | else | |
6228 | { | |
6229 | frag_grow (20); | |
6230 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 TS |
6231 | treg, (int) BFD_RELOC_GPREL16, |
6232 | mips_gp_register); | |
252b5132 RH |
6233 | p = frag_var (rs_machine_dependent, 8, 0, |
6234 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
6235 | (mips_opts.warn_about_macros | |
6236 | || (used_at | |
6237 | && mips_opts.noat))), | |
956cd1d6 | 6238 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6239 | used_at = 0; |
6240 | } | |
6241 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6242 | if (p != NULL) | |
6243 | p += 4; | |
6244 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
6245 | (int) BFD_RELOC_LO16, tempreg); | |
6246 | } | |
6247 | else | |
6248 | { | |
e7d556df | 6249 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6250 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6251 | p = NULL; | |
6252 | else | |
6253 | { | |
6254 | frag_grow (28); | |
6255 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6256 | ADDRESS_ADD_INSN, "d,v,t", tempreg, breg, |
6257 | mips_gp_register); | |
252b5132 | 6258 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 6259 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6260 | p = frag_var (rs_machine_dependent, 12, 0, |
6261 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 6262 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6263 | } |
6264 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6265 | if (p != NULL) | |
6266 | p += 4; | |
f899b4b8 | 6267 | macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
252b5132 RH |
6268 | "d,v,t", tempreg, tempreg, breg); |
6269 | if (p != NULL) | |
6270 | p += 4; | |
6271 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
6272 | (int) BFD_RELOC_LO16, tempreg); | |
6273 | } | |
6274 | } | |
6275 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6276 | { | |
f9419b05 | 6277 | char *p; |
ed6fb7bd | 6278 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6279 | |
252b5132 RH |
6280 | /* If this is a reference to an external symbol, we want |
6281 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6282 | nop | |
6283 | <op> $treg,0($tempreg) | |
6284 | Otherwise we want | |
6285 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6286 | nop | |
6287 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6288 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6289 | |
6290 | For NewABI, we want | |
6291 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6292 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6293 | ||
252b5132 RH |
6294 | If there is a base register, we add it to $tempreg before |
6295 | the <op>. If there is a constant, we stick it in the | |
6296 | <op> instruction. We don't handle constants larger than | |
6297 | 16 bits, because we have no way to load the upper 16 bits | |
6298 | (actually, we could handle them for the subset of cases | |
6299 | in which we are not using $at). */ | |
6300 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6301 | if (HAVE_NEWABI) |
6302 | { | |
6303 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 TS |
6304 | ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6305 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 AO |
6306 | if (breg != 0) |
6307 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6308 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6309 | breg); | |
f5040a92 AO |
6310 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, |
6311 | (int) BFD_RELOC_MIPS_GOT_OFST, tempreg); | |
6312 | ||
6313 | if (! used_at) | |
6314 | return; | |
6315 | ||
6316 | break; | |
6317 | } | |
252b5132 RH |
6318 | expr1.X_add_number = offset_expr.X_add_number; |
6319 | offset_expr.X_add_number = 0; | |
6320 | if (expr1.X_add_number < -0x8000 | |
6321 | || expr1.X_add_number >= 0x8000) | |
6322 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6323 | frag_grow (20); | |
f899b4b8 TS |
6324 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6325 | "t,o(b)", tempreg, (int) lw_reloc_type, | |
6326 | mips_gp_register); | |
252b5132 | 6327 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
bdaaa2e1 | 6328 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 6329 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 6330 | offset_expr.X_add_symbol, 0, NULL); |
f899b4b8 | 6331 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
252b5132 RH |
6332 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
6333 | if (breg != 0) | |
6334 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6335 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); |
252b5132 RH |
6336 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
6337 | (int) BFD_RELOC_LO16, tempreg); | |
6338 | } | |
f5040a92 | 6339 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 RH |
6340 | { |
6341 | int gpdel; | |
f9419b05 | 6342 | char *p; |
252b5132 RH |
6343 | |
6344 | /* If this is a reference to an external symbol, we want | |
6345 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6346 | addu $tempreg,$tempreg,$gp | |
6347 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6348 | <op> $treg,0($tempreg) | |
6349 | Otherwise we want | |
6350 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6351 | nop | |
6352 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6353 | <op> $treg,0($tempreg) | |
6354 | If there is a base register, we add it to $tempreg before | |
6355 | the <op>. If there is a constant, we stick it in the | |
6356 | <op> instruction. We don't handle constants larger than | |
6357 | 16 bits, because we have no way to load the upper 16 bits | |
6358 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6359 | in which we are not using $at). */ |
252b5132 RH |
6360 | assert (offset_expr.X_op == O_symbol); |
6361 | expr1.X_add_number = offset_expr.X_add_number; | |
6362 | offset_expr.X_add_number = 0; | |
6363 | if (expr1.X_add_number < -0x8000 | |
6364 | || expr1.X_add_number >= 0x8000) | |
6365 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
f7ea7ef2 | 6366 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6367 | gpdel = 4; |
6368 | else | |
6369 | gpdel = 0; | |
6370 | frag_grow (36); | |
6371 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6372 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6373 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6374 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6375 | mips_gp_register); | |
6376 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
252b5132 RH |
6377 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
6378 | tempreg); | |
6379 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
6380 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 6381 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6382 | if (gpdel > 0) |
6383 | { | |
6384 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6385 | p += 4; | |
6386 | } | |
f899b4b8 | 6387 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
c9914766 TS |
6388 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
6389 | mips_gp_register); | |
252b5132 RH |
6390 | p += 4; |
6391 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6392 | p += 4; | |
f899b4b8 | 6393 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
252b5132 RH |
6394 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
6395 | if (breg != 0) | |
6396 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6397 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); |
252b5132 RH |
6398 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
6399 | (int) BFD_RELOC_LO16, tempreg); | |
6400 | } | |
f5040a92 AO |
6401 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6402 | { | |
6403 | char *p; | |
6404 | int bregsz = breg != 0 ? 4 : 0; | |
6405 | ||
6406 | /* If this is a reference to an external symbol, we want | |
6407 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6408 | add $tempreg,$tempreg,$gp | |
6409 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6410 | <op> $treg,<ofst>($tempreg) | |
6411 | Otherwise, for local symbols, we want: | |
6412 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6413 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6414 | assert (offset_expr.X_op == O_symbol); | |
6415 | frag_now->tc_frag_data.tc_fr_offset = | |
6416 | expr1.X_add_number = offset_expr.X_add_number; | |
6417 | offset_expr.X_add_number = 0; | |
6418 | if (expr1.X_add_number < -0x8000 | |
6419 | || expr1.X_add_number >= 0x8000) | |
6420 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6421 | frag_grow (36); | |
6422 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6423 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6424 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6425 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6426 | mips_gp_register); | |
6427 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
f5040a92 AO |
6428 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
6429 | tempreg); | |
6430 | if (breg != 0) | |
6431 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6432 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); |
f5040a92 AO |
6433 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
6434 | (int) BFD_RELOC_LO16, tempreg); | |
684022ea | 6435 | |
f5040a92 AO |
6436 | offset_expr.X_add_number = expr1.X_add_number; |
6437 | p = frag_var (rs_machine_dependent, 12 + bregsz, 0, | |
6438 | RELAX_ENCODE (16 + bregsz, 8 + bregsz, | |
6439 | 0, 4 + bregsz, 0, 0), | |
6440 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 TS |
6441 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6442 | tempreg, (int) BFD_RELOC_MIPS_GOT_PAGE, | |
f5040a92 AO |
6443 | mips_gp_register); |
6444 | if (breg != 0) | |
6445 | macro_build (p + 4, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6446 | ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); |
f5040a92 AO |
6447 | macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg, |
6448 | (int) BFD_RELOC_MIPS_GOT_OFST, tempreg); | |
6449 | } | |
252b5132 RH |
6450 | else if (mips_pic == EMBEDDED_PIC) |
6451 | { | |
6452 | /* If there is no base register, we want | |
cdf6fd85 | 6453 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6454 | If there is a base register, we want |
6455 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6456 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6457 | */ |
6458 | assert (offset_expr.X_op == O_symbol); | |
6459 | if (breg == 0) | |
6460 | { | |
6461 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 | 6462 | treg, (int) BFD_RELOC_GPREL16, mips_gp_register); |
252b5132 RH |
6463 | used_at = 0; |
6464 | } | |
6465 | else | |
6466 | { | |
6467 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6468 | ADDRESS_ADD_INSN, "d,v,t", tempreg, breg, |
6469 | mips_gp_register); | |
252b5132 | 6470 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 6471 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6472 | } |
6473 | } | |
6474 | else | |
6475 | abort (); | |
6476 | ||
6477 | if (! used_at) | |
6478 | return; | |
6479 | ||
6480 | break; | |
6481 | ||
6482 | case M_LI: | |
6483 | case M_LI_S: | |
6484 | load_register (&icnt, treg, &imm_expr, 0); | |
6485 | return; | |
6486 | ||
6487 | case M_DLI: | |
6488 | load_register (&icnt, treg, &imm_expr, 1); | |
6489 | return; | |
6490 | ||
6491 | case M_LI_SS: | |
6492 | if (imm_expr.X_op == O_constant) | |
6493 | { | |
6494 | load_register (&icnt, AT, &imm_expr, 0); | |
6495 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6496 | "mtc1", "t,G", AT, treg); | |
6497 | break; | |
6498 | } | |
6499 | else | |
6500 | { | |
6501 | assert (offset_expr.X_op == O_symbol | |
6502 | && strcmp (segment_name (S_GET_SEGMENT | |
6503 | (offset_expr.X_add_symbol)), | |
6504 | ".lit4") == 0 | |
6505 | && offset_expr.X_add_number == 0); | |
6506 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
c9914766 | 6507 | treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6508 | return; |
6509 | } | |
6510 | ||
6511 | case M_LI_D: | |
ca4e0257 RS |
6512 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6513 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6514 | order 32 bits of the value and the low order 32 bits are either | |
6515 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6516 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6517 | { | |
ca4e0257 | 6518 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6519 | load_register (&icnt, treg, &imm_expr, 1); |
6520 | else | |
6521 | { | |
6522 | int hreg, lreg; | |
6523 | ||
6524 | if (target_big_endian) | |
6525 | { | |
6526 | hreg = treg; | |
6527 | lreg = treg + 1; | |
6528 | } | |
6529 | else | |
6530 | { | |
6531 | hreg = treg + 1; | |
6532 | lreg = treg; | |
6533 | } | |
6534 | ||
6535 | if (hreg <= 31) | |
6536 | load_register (&icnt, hreg, &imm_expr, 0); | |
6537 | if (lreg <= 31) | |
6538 | { | |
6539 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 6540 | move_register (&icnt, lreg, 0); |
252b5132 RH |
6541 | else |
6542 | { | |
6543 | assert (offset_expr.X_op == O_constant); | |
6544 | load_register (&icnt, lreg, &offset_expr, 0); | |
6545 | } | |
6546 | } | |
6547 | } | |
6548 | return; | |
6549 | } | |
6550 | ||
6551 | /* We know that sym is in the .rdata section. First we get the | |
6552 | upper 16 bits of the address. */ | |
6553 | if (mips_pic == NO_PIC) | |
6554 | { | |
956cd1d6 | 6555 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
6556 | } |
6557 | else if (mips_pic == SVR4_PIC) | |
6558 | { | |
f899b4b8 | 6559 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
c9914766 TS |
6560 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6561 | mips_gp_register); | |
252b5132 RH |
6562 | } |
6563 | else if (mips_pic == EMBEDDED_PIC) | |
6564 | { | |
6565 | /* For embedded PIC we pick up the entire address off $gp in | |
6566 | a single instruction. */ | |
f899b4b8 TS |
6567 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
6568 | "t,r,j", AT, mips_gp_register, | |
6569 | (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
6570 | offset_expr.X_op = O_constant; |
6571 | offset_expr.X_add_number = 0; | |
6572 | } | |
6573 | else | |
6574 | abort (); | |
bdaaa2e1 | 6575 | |
252b5132 | 6576 | /* Now we load the register(s). */ |
ca4e0257 | 6577 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6578 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
6579 | treg, (int) BFD_RELOC_LO16, AT); | |
6580 | else | |
6581 | { | |
6582 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6583 | treg, (int) BFD_RELOC_LO16, AT); | |
f9419b05 | 6584 | if (treg != RA) |
252b5132 RH |
6585 | { |
6586 | /* FIXME: How in the world do we deal with the possible | |
6587 | overflow here? */ | |
6588 | offset_expr.X_add_number += 4; | |
6589 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6590 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
6591 | } | |
6592 | } | |
6593 | ||
6594 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6595 | does not become a variant frag. */ | |
6596 | frag_wane (frag_now); | |
6597 | frag_new (0); | |
6598 | ||
6599 | break; | |
6600 | ||
6601 | case M_LI_DD: | |
ca4e0257 RS |
6602 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6603 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6604 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6605 | the value and the low order 32 bits are either zero or in | |
6606 | OFFSET_EXPR. */ | |
252b5132 RH |
6607 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6608 | { | |
ca4e0257 RS |
6609 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
6610 | if (HAVE_64BIT_FPRS) | |
6611 | { | |
6612 | assert (HAVE_64BIT_GPRS); | |
6613 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6614 | "dmtc1", "t,S", AT, treg); | |
6615 | } | |
252b5132 RH |
6616 | else |
6617 | { | |
6618 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6619 | "mtc1", "t,G", AT, treg + 1); | |
6620 | if (offset_expr.X_op == O_absent) | |
6621 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6622 | "mtc1", "t,G", 0, treg); | |
6623 | else | |
6624 | { | |
6625 | assert (offset_expr.X_op == O_constant); | |
6626 | load_register (&icnt, AT, &offset_expr, 0); | |
6627 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6628 | "mtc1", "t,G", AT, treg); | |
6629 | } | |
6630 | } | |
6631 | break; | |
6632 | } | |
6633 | ||
6634 | assert (offset_expr.X_op == O_symbol | |
6635 | && offset_expr.X_add_number == 0); | |
6636 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6637 | if (strcmp (s, ".lit8") == 0) | |
6638 | { | |
e7af610e | 6639 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6640 | { |
6641 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
c9914766 TS |
6642 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, |
6643 | mips_gp_register); | |
252b5132 RH |
6644 | return; |
6645 | } | |
c9914766 | 6646 | breg = mips_gp_register; |
252b5132 RH |
6647 | r = BFD_RELOC_MIPS_LITERAL; |
6648 | goto dob; | |
6649 | } | |
6650 | else | |
6651 | { | |
6652 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6653 | if (mips_pic == SVR4_PIC) | |
6654 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
f899b4b8 TS |
6655 | ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6656 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6657 | else |
6658 | { | |
6659 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6660 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6661 | } |
bdaaa2e1 | 6662 | |
e7af610e | 6663 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6664 | { |
6665 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
6666 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
6667 | ||
6668 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6669 | that this does not become a variant frag. */ | |
6670 | frag_wane (frag_now); | |
6671 | frag_new (0); | |
6672 | ||
6673 | break; | |
6674 | } | |
6675 | breg = AT; | |
6676 | r = BFD_RELOC_LO16; | |
6677 | goto dob; | |
6678 | } | |
6679 | ||
6680 | case M_L_DOB: | |
ec68c924 | 6681 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6682 | { |
6683 | as_bad (_("opcode not supported on this processor")); | |
6684 | return; | |
6685 | } | |
6686 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6687 | to adjust when loading from memory. */ | |
6688 | r = BFD_RELOC_LO16; | |
6689 | dob: | |
e7af610e | 6690 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6691 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6692 | target_big_endian ? treg + 1 : treg, | |
6693 | (int) r, breg); | |
6694 | /* FIXME: A possible overflow which I don't know how to deal | |
6695 | with. */ | |
6696 | offset_expr.X_add_number += 4; | |
6697 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
6698 | target_big_endian ? treg : treg + 1, | |
6699 | (int) r, breg); | |
6700 | ||
6701 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6702 | does not become a variant frag. */ | |
6703 | frag_wane (frag_now); | |
6704 | frag_new (0); | |
6705 | ||
6706 | if (breg != AT) | |
6707 | return; | |
6708 | break; | |
6709 | ||
6710 | case M_L_DAB: | |
6711 | /* | |
6712 | * The MIPS assembler seems to check for X_add_number not | |
6713 | * being double aligned and generating: | |
6714 | * lui at,%hi(foo+1) | |
6715 | * addu at,at,v1 | |
6716 | * addiu at,at,%lo(foo+1) | |
6717 | * lwc1 f2,0(at) | |
6718 | * lwc1 f3,4(at) | |
6719 | * But, the resulting address is the same after relocation so why | |
6720 | * generate the extra instruction? | |
6721 | */ | |
ec68c924 | 6722 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6723 | { |
6724 | as_bad (_("opcode not supported on this processor")); | |
6725 | return; | |
6726 | } | |
bdaaa2e1 | 6727 | /* Itbl support may require additional care here. */ |
252b5132 | 6728 | coproc = 1; |
e7af610e | 6729 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6730 | { |
6731 | s = "ldc1"; | |
6732 | goto ld; | |
6733 | } | |
6734 | ||
6735 | s = "lwc1"; | |
6736 | fmt = "T,o(b)"; | |
6737 | goto ldd_std; | |
6738 | ||
6739 | case M_S_DAB: | |
ec68c924 | 6740 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6741 | { |
6742 | as_bad (_("opcode not supported on this processor")); | |
6743 | return; | |
6744 | } | |
6745 | ||
e7af610e | 6746 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6747 | { |
6748 | s = "sdc1"; | |
6749 | goto st; | |
6750 | } | |
6751 | ||
6752 | s = "swc1"; | |
6753 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6754 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6755 | coproc = 1; |
6756 | goto ldd_std; | |
6757 | ||
6758 | case M_LD_AB: | |
ca4e0257 | 6759 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6760 | { |
6761 | s = "ld"; | |
6762 | goto ld; | |
6763 | } | |
6764 | ||
6765 | s = "lw"; | |
6766 | fmt = "t,o(b)"; | |
6767 | goto ldd_std; | |
6768 | ||
6769 | case M_SD_AB: | |
ca4e0257 | 6770 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6771 | { |
6772 | s = "sd"; | |
6773 | goto st; | |
6774 | } | |
6775 | ||
6776 | s = "sw"; | |
6777 | fmt = "t,o(b)"; | |
6778 | ||
6779 | ldd_std: | |
afdbd6d0 CD |
6780 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6781 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6782 | This is not currently done by the compiler, and assembly coders | |
6783 | writing embedded-pic code can cope. */ | |
6784 | ||
252b5132 RH |
6785 | if (offset_expr.X_op != O_symbol |
6786 | && offset_expr.X_op != O_constant) | |
6787 | { | |
6788 | as_bad (_("expression too complex")); | |
6789 | offset_expr.X_op = O_constant; | |
6790 | } | |
6791 | ||
6792 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6793 | to adjust when loading from memory. We set coproc if we must | |
6794 | load $fn+1 first. */ | |
bdaaa2e1 | 6795 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6796 | if (! target_big_endian) |
6797 | coproc = 0; | |
6798 | ||
6799 | if (mips_pic == NO_PIC | |
6800 | || offset_expr.X_op == O_constant) | |
6801 | { | |
f9419b05 TS |
6802 | char *p; |
6803 | ||
252b5132 | 6804 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6805 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6806 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6807 | If we have a base register, we use this |
6808 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6809 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6810 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6811 | If this is not a GP relative symbol, we want |
6812 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6813 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6814 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6815 | If there is a base register, we add it to $at after the | |
6816 | lui instruction. If there is a constant, we always use | |
6817 | the last case. */ | |
e7d556df | 6818 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6819 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6820 | { | |
6821 | p = NULL; | |
6822 | used_at = 1; | |
6823 | } | |
6824 | else | |
6825 | { | |
6826 | int off; | |
6827 | ||
6828 | if (breg == 0) | |
6829 | { | |
6830 | frag_grow (28); | |
c9914766 | 6831 | tempreg = mips_gp_register; |
252b5132 RH |
6832 | off = 0; |
6833 | used_at = 0; | |
6834 | } | |
6835 | else | |
6836 | { | |
6837 | frag_grow (36); | |
6838 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
6839 | ADDRESS_ADD_INSN, "d,v,t", AT, breg, |
6840 | mips_gp_register); | |
252b5132 RH |
6841 | tempreg = AT; |
6842 | off = 4; | |
6843 | used_at = 1; | |
6844 | } | |
6845 | ||
beae10d5 | 6846 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6847 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6848 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6849 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6850 | offset_expr.X_add_number += 4; |
6851 | ||
6852 | /* Set mips_optimize to 2 to avoid inserting an | |
6853 | undesired nop. */ | |
6854 | hold_mips_optimize = mips_optimize; | |
6855 | mips_optimize = 2; | |
beae10d5 | 6856 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6857 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6858 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6859 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6860 | mips_optimize = hold_mips_optimize; |
6861 | ||
6862 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6863 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6864 | used_at && mips_opts.noat), | |
956cd1d6 | 6865 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6866 | |
6867 | /* We just generated two relocs. When tc_gen_reloc | |
6868 | handles this case, it will skip the first reloc and | |
6869 | handle the second. The second reloc already has an | |
6870 | extra addend of 4, which we added above. We must | |
6871 | subtract it out, and then subtract another 4 to make | |
6872 | the first reloc come out right. The second reloc | |
6873 | will come out right because we are going to add 4 to | |
6874 | offset_expr when we build its instruction below. | |
6875 | ||
6876 | If we have a symbol, then we don't want to include | |
6877 | the offset, because it will wind up being included | |
6878 | when we generate the reloc. */ | |
6879 | ||
6880 | if (offset_expr.X_op == O_constant) | |
6881 | offset_expr.X_add_number -= 8; | |
6882 | else | |
6883 | { | |
6884 | offset_expr.X_add_number = -4; | |
6885 | offset_expr.X_op = O_constant; | |
6886 | } | |
6887 | } | |
6888 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6889 | if (p != NULL) | |
6890 | p += 4; | |
6891 | if (breg != 0) | |
6892 | { | |
f899b4b8 | 6893 | macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
252b5132 RH |
6894 | "d,v,t", AT, breg, AT); |
6895 | if (p != NULL) | |
6896 | p += 4; | |
6897 | } | |
beae10d5 | 6898 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6899 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6900 | coproc ? treg + 1 : treg, | |
6901 | (int) BFD_RELOC_LO16, AT); | |
6902 | if (p != NULL) | |
6903 | p += 4; | |
6904 | /* FIXME: How do we handle overflow here? */ | |
6905 | offset_expr.X_add_number += 4; | |
beae10d5 | 6906 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6907 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6908 | coproc ? treg : treg + 1, | |
6909 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6910 | } |
252b5132 RH |
6911 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6912 | { | |
6913 | int off; | |
6914 | ||
6915 | /* If this is a reference to an external symbol, we want | |
6916 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6917 | nop | |
6918 | <op> $treg,0($at) | |
6919 | <op> $treg+1,4($at) | |
6920 | Otherwise we want | |
6921 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6922 | nop | |
6923 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6924 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6925 | If there is a base register we add it to $at before the | |
6926 | lwc1 instructions. If there is a constant we include it | |
6927 | in the lwc1 instructions. */ | |
6928 | used_at = 1; | |
6929 | expr1.X_add_number = offset_expr.X_add_number; | |
6930 | offset_expr.X_add_number = 0; | |
6931 | if (expr1.X_add_number < -0x8000 | |
6932 | || expr1.X_add_number >= 0x8000 - 4) | |
6933 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6934 | if (breg == 0) | |
6935 | off = 0; | |
6936 | else | |
6937 | off = 4; | |
6938 | frag_grow (24 + off); | |
f899b4b8 TS |
6939 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6940 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, | |
6941 | mips_gp_register); | |
252b5132 RH |
6942 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
6943 | if (breg != 0) | |
6944 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 6945 | ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6946 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6947 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6948 | coproc ? treg + 1 : treg, | |
6949 | (int) BFD_RELOC_LO16, AT); | |
6950 | expr1.X_add_number += 4; | |
6951 | ||
6952 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6953 | nop. */ | |
6954 | hold_mips_optimize = mips_optimize; | |
6955 | mips_optimize = 2; | |
beae10d5 | 6956 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6957 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6958 | coproc ? treg : treg + 1, | |
6959 | (int) BFD_RELOC_LO16, AT); | |
6960 | mips_optimize = hold_mips_optimize; | |
6961 | ||
6962 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6963 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6964 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6965 | } |
6966 | else if (mips_pic == SVR4_PIC) | |
6967 | { | |
6968 | int gpdel, off; | |
f9419b05 | 6969 | char *p; |
252b5132 RH |
6970 | |
6971 | /* If this is a reference to an external symbol, we want | |
6972 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6973 | addu $at,$at,$gp | |
6974 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6975 | nop | |
6976 | <op> $treg,0($at) | |
6977 | <op> $treg+1,4($at) | |
6978 | Otherwise we want | |
6979 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6980 | nop | |
6981 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6982 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6983 | If there is a base register we add it to $at before the | |
6984 | lwc1 instructions. If there is a constant we include it | |
6985 | in the lwc1 instructions. */ | |
6986 | used_at = 1; | |
6987 | expr1.X_add_number = offset_expr.X_add_number; | |
6988 | offset_expr.X_add_number = 0; | |
6989 | if (expr1.X_add_number < -0x8000 | |
6990 | || expr1.X_add_number >= 0x8000 - 4) | |
6991 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6992 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6993 | gpdel = 4; |
6994 | else | |
6995 | gpdel = 0; | |
6996 | if (breg == 0) | |
6997 | off = 0; | |
6998 | else | |
6999 | off = 4; | |
7000 | frag_grow (56); | |
7001 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
7002 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
7003 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
7004 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, mips_gp_register); |
7005 | macro_build ((char *) NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
252b5132 RH |
7006 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
7007 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
7008 | if (breg != 0) | |
7009 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 7010 | ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7011 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7012 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
7013 | coproc ? treg + 1 : treg, | |
7014 | (int) BFD_RELOC_LO16, AT); | |
7015 | expr1.X_add_number += 4; | |
7016 | ||
7017 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7018 | nop. */ | |
7019 | hold_mips_optimize = mips_optimize; | |
7020 | mips_optimize = 2; | |
beae10d5 | 7021 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7022 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
7023 | coproc ? treg : treg + 1, | |
7024 | (int) BFD_RELOC_LO16, AT); | |
7025 | mips_optimize = hold_mips_optimize; | |
7026 | expr1.X_add_number -= 4; | |
7027 | ||
7028 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
7029 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
7030 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 7031 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
7032 | if (gpdel > 0) |
7033 | { | |
7034 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
7035 | p += 4; | |
7036 | } | |
f899b4b8 | 7037 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
c9914766 TS |
7038 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
7039 | mips_gp_register); | |
252b5132 RH |
7040 | p += 4; |
7041 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
7042 | p += 4; | |
7043 | if (breg != 0) | |
7044 | { | |
f899b4b8 | 7045 | macro_build (p, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
252b5132 RH |
7046 | "d,v,t", AT, breg, AT); |
7047 | p += 4; | |
7048 | } | |
beae10d5 | 7049 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7050 | macro_build (p, &icnt, &expr1, s, fmt, |
7051 | coproc ? treg + 1 : treg, | |
7052 | (int) BFD_RELOC_LO16, AT); | |
7053 | p += 4; | |
7054 | expr1.X_add_number += 4; | |
7055 | ||
7056 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7057 | nop. */ | |
7058 | hold_mips_optimize = mips_optimize; | |
7059 | mips_optimize = 2; | |
beae10d5 | 7060 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7061 | macro_build (p, &icnt, &expr1, s, fmt, |
7062 | coproc ? treg : treg + 1, | |
7063 | (int) BFD_RELOC_LO16, AT); | |
7064 | mips_optimize = hold_mips_optimize; | |
7065 | } | |
7066 | else if (mips_pic == EMBEDDED_PIC) | |
7067 | { | |
7068 | /* If there is no base register, we use | |
cdf6fd85 TS |
7069 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7070 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7071 | If we have a base register, we use |
7072 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7073 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7074 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7075 | */ |
7076 | if (breg == 0) | |
7077 | { | |
c9914766 | 7078 | tempreg = mips_gp_register; |
252b5132 RH |
7079 | used_at = 0; |
7080 | } | |
7081 | else | |
7082 | { | |
7083 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 TS |
7084 | ADDRESS_ADD_INSN, "d,v,t", AT, breg, |
7085 | mips_gp_register); | |
252b5132 RH |
7086 | tempreg = AT; |
7087 | used_at = 1; | |
7088 | } | |
7089 | ||
beae10d5 | 7090 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7091 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
7092 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 7093 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 | 7094 | offset_expr.X_add_number += 4; |
beae10d5 | 7095 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7096 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
7097 | coproc ? treg : treg + 1, | |
cdf6fd85 | 7098 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7099 | } |
7100 | else | |
7101 | abort (); | |
7102 | ||
7103 | if (! used_at) | |
7104 | return; | |
7105 | ||
7106 | break; | |
7107 | ||
7108 | case M_LD_OB: | |
7109 | s = "lw"; | |
7110 | goto sd_ob; | |
7111 | case M_SD_OB: | |
7112 | s = "sw"; | |
7113 | sd_ob: | |
ca4e0257 | 7114 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
7115 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7116 | (int) BFD_RELOC_LO16, breg); | |
7117 | offset_expr.X_add_number += 4; | |
7118 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
7119 | (int) BFD_RELOC_LO16, breg); | |
7120 | return; | |
7121 | ||
7122 | /* New code added to support COPZ instructions. | |
7123 | This code builds table entries out of the macros in mip_opcodes. | |
7124 | R4000 uses interlocks to handle coproc delays. | |
7125 | Other chips (like the R3000) require nops to be inserted for delays. | |
7126 | ||
f72c8c98 | 7127 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7128 | In order to fill delay slots for non-interlocked chips, |
7129 | we must have a way to specify delays based on the coprocessor. | |
7130 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7131 | What are the side-effects of the cop instruction? | |
7132 | What cache support might we have and what are its effects? | |
7133 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7134 | What registers are read/set/modified? |
252b5132 RH |
7135 | |
7136 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7137 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7138 | |
7139 | case M_COP0: | |
7140 | s = "c0"; | |
7141 | goto copz; | |
7142 | case M_COP1: | |
7143 | s = "c1"; | |
7144 | goto copz; | |
7145 | case M_COP2: | |
7146 | s = "c2"; | |
7147 | goto copz; | |
7148 | case M_COP3: | |
7149 | s = "c3"; | |
7150 | copz: | |
7151 | /* For now we just do C (same as Cz). The parameter will be | |
7152 | stored in insn_opcode by mips_ip. */ | |
7153 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
7154 | ip->insn_opcode); | |
7155 | return; | |
7156 | ||
ea1fb5dc RS |
7157 | case M_MOVE: |
7158 | move_register (&icnt, dreg, sreg); | |
7159 | return; | |
7160 | ||
252b5132 RH |
7161 | #ifdef LOSING_COMPILER |
7162 | default: | |
7163 | /* Try and see if this is a new itbl instruction. | |
7164 | This code builds table entries out of the macros in mip_opcodes. | |
7165 | FIXME: For now we just assemble the expression and pass it's | |
7166 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7167 | We may want to have the assembler assemble this value, |
252b5132 RH |
7168 | so that we gain the assembler's knowledge of delay slots, |
7169 | symbols, etc. | |
7170 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7171 | if (itbl_have_entries |
252b5132 | 7172 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7173 | { |
252b5132 RH |
7174 | s = ip->insn_mo->name; |
7175 | s2 = "cop3"; | |
7176 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
7177 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
7178 | return; | |
beae10d5 | 7179 | } |
252b5132 RH |
7180 | macro2 (ip); |
7181 | return; | |
7182 | } | |
7183 | if (mips_opts.noat) | |
7184 | as_warn (_("Macro used $at after \".set noat\"")); | |
7185 | } | |
bdaaa2e1 | 7186 | |
252b5132 RH |
7187 | static void |
7188 | macro2 (ip) | |
7189 | struct mips_cl_insn *ip; | |
7190 | { | |
7191 | register int treg, sreg, dreg, breg; | |
7192 | int tempreg; | |
7193 | int mask; | |
7194 | int icnt = 0; | |
7195 | int used_at; | |
7196 | expressionS expr1; | |
7197 | const char *s; | |
7198 | const char *s2; | |
7199 | const char *fmt; | |
7200 | int likely = 0; | |
7201 | int dbl = 0; | |
7202 | int coproc = 0; | |
7203 | int lr = 0; | |
7204 | int imm = 0; | |
7205 | int off; | |
7206 | offsetT maxnum; | |
7207 | bfd_reloc_code_real_type r; | |
7208 | char *p; | |
bdaaa2e1 | 7209 | |
252b5132 RH |
7210 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7211 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7212 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7213 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7214 | |
252b5132 RH |
7215 | expr1.X_op = O_constant; |
7216 | expr1.X_op_symbol = NULL; | |
7217 | expr1.X_add_symbol = NULL; | |
7218 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7219 | |
252b5132 RH |
7220 | switch (mask) |
7221 | { | |
7222 | #endif /* LOSING_COMPILER */ | |
7223 | ||
7224 | case M_DMUL: | |
7225 | dbl = 1; | |
7226 | case M_MUL: | |
2396cfb9 TS |
7227 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
7228 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); | |
7229 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
7230 | dreg); | |
252b5132 RH |
7231 | return; |
7232 | ||
7233 | case M_DMUL_I: | |
7234 | dbl = 1; | |
7235 | case M_MUL_I: | |
7236 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7237 | not trying to be that fancy. GCC should do this for us | |
7238 | anyway. */ | |
7239 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7240 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7241 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
2396cfb9 TS |
7242 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
7243 | dreg); | |
252b5132 RH |
7244 | break; |
7245 | ||
7246 | case M_DMULO_I: | |
7247 | dbl = 1; | |
7248 | case M_MULO_I: | |
7249 | imm = 1; | |
7250 | goto do_mulo; | |
7251 | ||
7252 | case M_DMULO: | |
7253 | dbl = 1; | |
7254 | case M_MULO: | |
7255 | do_mulo: | |
b34976b6 | 7256 | mips_emit_delays (TRUE); |
252b5132 RH |
7257 | ++mips_opts.noreorder; |
7258 | mips_any_noreorder = 1; | |
7259 | if (imm) | |
7260 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7261 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7262 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
2396cfb9 TS |
7263 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
7264 | dreg); | |
7265 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f9419b05 | 7266 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); |
2396cfb9 TS |
7267 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
7268 | AT); | |
252b5132 | 7269 | if (mips_trap) |
9bd7d936 MR |
7270 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
7271 | "s,t,q", dreg, AT, 6); | |
252b5132 RH |
7272 | else |
7273 | { | |
7274 | expr1.X_add_number = 8; | |
2396cfb9 TS |
7275 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
7276 | AT); | |
7277 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", | |
7278 | 0); | |
7279 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
7280 | "c", 6); | |
252b5132 RH |
7281 | } |
7282 | --mips_opts.noreorder; | |
2396cfb9 | 7283 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
252b5132 RH |
7284 | break; |
7285 | ||
7286 | case M_DMULOU_I: | |
7287 | dbl = 1; | |
7288 | case M_MULOU_I: | |
7289 | imm = 1; | |
7290 | goto do_mulou; | |
7291 | ||
7292 | case M_DMULOU: | |
7293 | dbl = 1; | |
7294 | case M_MULOU: | |
7295 | do_mulou: | |
b34976b6 | 7296 | mips_emit_delays (TRUE); |
252b5132 RH |
7297 | ++mips_opts.noreorder; |
7298 | mips_any_noreorder = 1; | |
7299 | if (imm) | |
7300 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7301 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
7302 | dbl ? "dmultu" : "multu", |
7303 | "s,t", sreg, imm ? AT : treg); | |
2396cfb9 TS |
7304 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
7305 | AT); | |
7306 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
7307 | dreg); | |
252b5132 | 7308 | if (mips_trap) |
9bd7d936 MR |
7309 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
7310 | "s,t,q", AT, 0, 6); | |
252b5132 RH |
7311 | else |
7312 | { | |
7313 | expr1.X_add_number = 8; | |
7314 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
2396cfb9 TS |
7315 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
7316 | 0); | |
7317 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
7318 | "c", 6); | |
252b5132 RH |
7319 | } |
7320 | --mips_opts.noreorder; | |
7321 | break; | |
7322 | ||
771c7ce4 | 7323 | case M_DROL: |
af7ee8bf | 7324 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
82dd0097 CD |
7325 | { |
7326 | if (dreg == sreg) | |
7327 | { | |
7328 | tempreg = AT; | |
7329 | used_at = 1; | |
7330 | } | |
7331 | else | |
7332 | { | |
7333 | tempreg = dreg; | |
7334 | used_at = 0; | |
7335 | } | |
7336 | macro_build ((char *) NULL, &icnt, NULL, "dnegu", | |
7337 | "d,w", tempreg, treg); | |
7338 | macro_build ((char *) NULL, &icnt, NULL, "drorv", | |
7339 | "d,t,s", dreg, sreg, tempreg); | |
7340 | if (used_at) | |
7341 | break; | |
7342 | return; | |
7343 | } | |
771c7ce4 TS |
7344 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
7345 | "d,v,t", AT, 0, treg); | |
7346 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
7347 | "d,t,s", AT, sreg, AT); | |
7348 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
7349 | "d,t,s", dreg, sreg, treg); | |
7350 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7351 | "d,v,t", dreg, dreg, AT); | |
7352 | break; | |
7353 | ||
252b5132 | 7354 | case M_ROL: |
af7ee8bf | 7355 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
82dd0097 CD |
7356 | { |
7357 | if (dreg == sreg) | |
7358 | { | |
7359 | tempreg = AT; | |
7360 | used_at = 1; | |
7361 | } | |
7362 | else | |
7363 | { | |
7364 | tempreg = dreg; | |
7365 | used_at = 0; | |
7366 | } | |
7367 | macro_build ((char *) NULL, &icnt, NULL, "negu", | |
7368 | "d,w", tempreg, treg); | |
7369 | macro_build ((char *) NULL, &icnt, NULL, "rorv", | |
7370 | "d,t,s", dreg, sreg, tempreg); | |
7371 | if (used_at) | |
7372 | break; | |
7373 | return; | |
7374 | } | |
2396cfb9 TS |
7375 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
7376 | "d,v,t", AT, 0, treg); | |
7377 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
7378 | "d,t,s", AT, sreg, AT); | |
7379 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
7380 | "d,t,s", dreg, sreg, treg); | |
7381 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7382 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7383 | break; |
7384 | ||
771c7ce4 TS |
7385 | case M_DROL_I: |
7386 | { | |
7387 | unsigned int rot; | |
82dd0097 | 7388 | char *l, *r; |
771c7ce4 TS |
7389 | |
7390 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7391 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7392 | rot = imm_expr.X_add_number & 0x3f; |
af7ee8bf | 7393 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
60b63b72 RS |
7394 | { |
7395 | rot = (64 - rot) & 0x3f; | |
7396 | if (rot >= 32) | |
7397 | macro_build ((char *) NULL, &icnt, NULL, "dror32", | |
7398 | "d,w,<", dreg, sreg, rot - 32); | |
7399 | else | |
7400 | macro_build ((char *) NULL, &icnt, NULL, "dror", | |
7401 | "d,w,<", dreg, sreg, rot); | |
82dd0097 | 7402 | return; |
60b63b72 | 7403 | } |
483fc7cd | 7404 | if (rot == 0) |
483fc7cd | 7405 | { |
82dd0097 CD |
7406 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", |
7407 | "d,w,<", dreg, sreg, 0); | |
7408 | return; | |
483fc7cd | 7409 | } |
82dd0097 CD |
7410 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7411 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7412 | rot &= 0x1f; | |
7413 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
7414 | "d,w,<", AT, sreg, rot); | |
7415 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
7416 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7417 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7418 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7419 | } |
7420 | break; | |
7421 | ||
252b5132 | 7422 | case M_ROL_I: |
771c7ce4 TS |
7423 | { |
7424 | unsigned int rot; | |
7425 | ||
7426 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7427 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7428 | rot = imm_expr.X_add_number & 0x1f; |
af7ee8bf | 7429 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
60b63b72 RS |
7430 | { |
7431 | macro_build ((char *) NULL, &icnt, NULL, "ror", | |
7432 | "d,w,<", dreg, sreg, (32 - rot) & 0x1f); | |
82dd0097 | 7433 | return; |
60b63b72 | 7434 | } |
483fc7cd | 7435 | if (rot == 0) |
483fc7cd | 7436 | { |
483fc7cd | 7437 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
82dd0097 CD |
7438 | "d,w,<", dreg, sreg, 0); |
7439 | return; | |
483fc7cd | 7440 | } |
82dd0097 CD |
7441 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", |
7442 | "d,w,<", AT, sreg, rot); | |
7443 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
7444 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7445 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7446 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7447 | } |
7448 | break; | |
7449 | ||
7450 | case M_DROR: | |
af7ee8bf | 7451 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
82dd0097 CD |
7452 | { |
7453 | macro_build ((char *) NULL, &icnt, NULL, "drorv", | |
7454 | "d,t,s", dreg, sreg, treg); | |
7455 | return; | |
7456 | } | |
771c7ce4 TS |
7457 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", |
7458 | "d,v,t", AT, 0, treg); | |
7459 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
7460 | "d,t,s", AT, sreg, AT); | |
7461 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
7462 | "d,t,s", dreg, sreg, treg); | |
7463 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7464 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7465 | break; |
7466 | ||
7467 | case M_ROR: | |
af7ee8bf | 7468 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
82dd0097 CD |
7469 | { |
7470 | macro_build ((char *) NULL, &icnt, NULL, "rorv", | |
7471 | "d,t,s", dreg, sreg, treg); | |
7472 | return; | |
7473 | } | |
2396cfb9 TS |
7474 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
7475 | "d,v,t", AT, 0, treg); | |
7476 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
7477 | "d,t,s", AT, sreg, AT); | |
7478 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
7479 | "d,t,s", dreg, sreg, treg); | |
7480 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7481 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7482 | break; |
7483 | ||
771c7ce4 TS |
7484 | case M_DROR_I: |
7485 | { | |
7486 | unsigned int rot; | |
82dd0097 | 7487 | char *l, *r; |
771c7ce4 TS |
7488 | |
7489 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7490 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7491 | rot = imm_expr.X_add_number & 0x3f; |
af7ee8bf | 7492 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_arch)) |
82dd0097 CD |
7493 | { |
7494 | if (rot >= 32) | |
7495 | macro_build ((char *) NULL, &icnt, NULL, "dror32", | |
7496 | "d,w,<", dreg, sreg, rot - 32); | |
7497 | else | |
7498 | macro_build ((char *) NULL, &icnt, NULL, "dror", | |
7499 | "d,w,<", dreg, sreg, rot); | |
7500 | return; | |
7501 | } | |
483fc7cd | 7502 | if (rot == 0) |
483fc7cd | 7503 | { |
82dd0097 CD |
7504 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", |
7505 | "d,w,<", dreg, sreg, 0); | |
7506 | return; | |
483fc7cd | 7507 | } |
82dd0097 CD |
7508 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7509 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7510 | rot &= 0x1f; | |
7511 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
7512 | "d,w,<", AT, sreg, rot); | |
7513 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
7514 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7515 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7516 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7517 | } |
7518 | break; | |
7519 | ||
252b5132 | 7520 | case M_ROR_I: |
771c7ce4 TS |
7521 | { |
7522 | unsigned int rot; | |
7523 | ||
7524 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7525 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7526 | rot = imm_expr.X_add_number & 0x1f; |
af7ee8bf | 7527 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_arch)) |
82dd0097 CD |
7528 | { |
7529 | macro_build ((char *) NULL, &icnt, NULL, "ror", | |
7530 | "d,w,<", dreg, sreg, rot); | |
7531 | return; | |
7532 | } | |
483fc7cd | 7533 | if (rot == 0) |
483fc7cd RS |
7534 | { |
7535 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
82dd0097 CD |
7536 | "d,w,<", dreg, sreg, 0); |
7537 | return; | |
483fc7cd | 7538 | } |
82dd0097 CD |
7539 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", |
7540 | "d,w,<", AT, sreg, rot); | |
7541 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
7542 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7543 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
7544 | "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7545 | } |
252b5132 RH |
7546 | break; |
7547 | ||
7548 | case M_S_DOB: | |
ec68c924 | 7549 | if (mips_arch == CPU_R4650) |
252b5132 RH |
7550 | { |
7551 | as_bad (_("opcode not supported on this processor")); | |
7552 | return; | |
7553 | } | |
e7af610e | 7554 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7555 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7556 | to adjust when storing to memory. */ | |
7557 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
7558 | target_big_endian ? treg + 1 : treg, | |
7559 | (int) BFD_RELOC_LO16, breg); | |
7560 | offset_expr.X_add_number += 4; | |
7561 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
7562 | target_big_endian ? treg : treg + 1, | |
7563 | (int) BFD_RELOC_LO16, breg); | |
7564 | return; | |
7565 | ||
7566 | case M_SEQ: | |
7567 | if (sreg == 0) | |
7568 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7569 | treg, (int) BFD_RELOC_LO16); | |
7570 | else if (treg == 0) | |
7571 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7572 | sreg, (int) BFD_RELOC_LO16); | |
7573 | else | |
7574 | { | |
2396cfb9 TS |
7575 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7576 | "d,v,t", dreg, sreg, treg); | |
252b5132 RH |
7577 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
7578 | dreg, (int) BFD_RELOC_LO16); | |
7579 | } | |
7580 | return; | |
7581 | ||
7582 | case M_SEQ_I: | |
7583 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7584 | { | |
7585 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
7586 | sreg, (int) BFD_RELOC_LO16); | |
7587 | return; | |
7588 | } | |
7589 | if (sreg == 0) | |
7590 | { | |
7591 | as_warn (_("Instruction %s: result is always false"), | |
7592 | ip->insn_mo->name); | |
ea1fb5dc | 7593 | move_register (&icnt, dreg, 0); |
252b5132 RH |
7594 | return; |
7595 | } | |
7596 | if (imm_expr.X_op == O_constant | |
7597 | && imm_expr.X_add_number >= 0 | |
7598 | && imm_expr.X_add_number < 0x10000) | |
7599 | { | |
7600 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
7601 | sreg, (int) BFD_RELOC_LO16); | |
7602 | used_at = 0; | |
7603 | } | |
7604 | else if (imm_expr.X_op == O_constant | |
7605 | && imm_expr.X_add_number > -0x8000 | |
7606 | && imm_expr.X_add_number < 0) | |
7607 | { | |
7608 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7609 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7610 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
f899b4b8 | 7611 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
252b5132 RH |
7612 | used_at = 0; |
7613 | } | |
7614 | else | |
7615 | { | |
4d34fb5f | 7616 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7617 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7618 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7619 | used_at = 1; |
7620 | } | |
7621 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
7622 | (int) BFD_RELOC_LO16); | |
7623 | if (used_at) | |
7624 | break; | |
7625 | return; | |
7626 | ||
7627 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7628 | s = "slt"; | |
7629 | goto sge; | |
7630 | case M_SGEU: | |
7631 | s = "sltu"; | |
7632 | sge: | |
2396cfb9 TS |
7633 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7634 | dreg, sreg, treg); | |
252b5132 RH |
7635 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7636 | (int) BFD_RELOC_LO16); | |
7637 | return; | |
7638 | ||
7639 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7640 | case M_SGEU_I: | |
7641 | if (imm_expr.X_op == O_constant | |
7642 | && imm_expr.X_add_number >= -0x8000 | |
7643 | && imm_expr.X_add_number < 0x8000) | |
7644 | { | |
7645 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7646 | mask == M_SGE_I ? "slti" : "sltiu", | |
7647 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7648 | used_at = 0; | |
7649 | } | |
7650 | else | |
7651 | { | |
4d34fb5f | 7652 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7653 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
7654 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, | |
7655 | AT); | |
252b5132 RH |
7656 | used_at = 1; |
7657 | } | |
7658 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7659 | (int) BFD_RELOC_LO16); | |
7660 | if (used_at) | |
7661 | break; | |
7662 | return; | |
7663 | ||
7664 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7665 | s = "slt"; | |
7666 | goto sgt; | |
7667 | case M_SGTU: | |
7668 | s = "sltu"; | |
7669 | sgt: | |
2396cfb9 TS |
7670 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7671 | dreg, treg, sreg); | |
252b5132 RH |
7672 | return; |
7673 | ||
7674 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7675 | s = "slt"; | |
7676 | goto sgti; | |
7677 | case M_SGTU_I: | |
7678 | s = "sltu"; | |
7679 | sgti: | |
4d34fb5f | 7680 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7681 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7682 | dreg, AT, sreg); | |
252b5132 RH |
7683 | break; |
7684 | ||
2396cfb9 | 7685 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7686 | s = "slt"; |
7687 | goto sle; | |
7688 | case M_SLEU: | |
7689 | s = "sltu"; | |
7690 | sle: | |
2396cfb9 TS |
7691 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7692 | dreg, treg, sreg); | |
252b5132 RH |
7693 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7694 | (int) BFD_RELOC_LO16); | |
7695 | return; | |
7696 | ||
2396cfb9 | 7697 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7698 | s = "slt"; |
7699 | goto slei; | |
7700 | case M_SLEU_I: | |
7701 | s = "sltu"; | |
7702 | slei: | |
4d34fb5f | 7703 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7704 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7705 | dreg, AT, sreg); | |
252b5132 RH |
7706 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7707 | (int) BFD_RELOC_LO16); | |
7708 | break; | |
7709 | ||
7710 | case M_SLT_I: | |
7711 | if (imm_expr.X_op == O_constant | |
7712 | && imm_expr.X_add_number >= -0x8000 | |
7713 | && imm_expr.X_add_number < 0x8000) | |
7714 | { | |
7715 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
7716 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7717 | return; | |
7718 | } | |
4d34fb5f | 7719 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7720 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
7721 | dreg, sreg, AT); | |
252b5132 RH |
7722 | break; |
7723 | ||
7724 | case M_SLTU_I: | |
7725 | if (imm_expr.X_op == O_constant | |
7726 | && imm_expr.X_add_number >= -0x8000 | |
7727 | && imm_expr.X_add_number < 0x8000) | |
7728 | { | |
7729 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
7730 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7731 | return; | |
7732 | } | |
4d34fb5f | 7733 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7734 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7735 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7736 | break; |
7737 | ||
7738 | case M_SNE: | |
7739 | if (sreg == 0) | |
2396cfb9 TS |
7740 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7741 | "d,v,t", dreg, 0, treg); | |
252b5132 | 7742 | else if (treg == 0) |
2396cfb9 TS |
7743 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7744 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7745 | else |
7746 | { | |
2396cfb9 TS |
7747 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7748 | "d,v,t", dreg, sreg, treg); | |
7749 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", | |
7750 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7751 | } |
7752 | return; | |
7753 | ||
7754 | case M_SNE_I: | |
7755 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7756 | { | |
2396cfb9 TS |
7757 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7758 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7759 | return; |
7760 | } | |
7761 | if (sreg == 0) | |
7762 | { | |
7763 | as_warn (_("Instruction %s: result is always true"), | |
7764 | ip->insn_mo->name); | |
7765 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 7766 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7767 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
7768 | return; | |
7769 | } | |
7770 | if (imm_expr.X_op == O_constant | |
7771 | && imm_expr.X_add_number >= 0 | |
7772 | && imm_expr.X_add_number < 0x10000) | |
7773 | { | |
7774 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
7775 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7776 | used_at = 0; | |
7777 | } | |
7778 | else if (imm_expr.X_op == O_constant | |
7779 | && imm_expr.X_add_number > -0x8000 | |
7780 | && imm_expr.X_add_number < 0) | |
7781 | { | |
7782 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7783 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7784 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7785 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
7786 | used_at = 0; | |
7787 | } | |
7788 | else | |
7789 | { | |
4d34fb5f | 7790 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7791 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7792 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7793 | used_at = 1; |
7794 | } | |
2396cfb9 TS |
7795 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7796 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7797 | if (used_at) |
7798 | break; | |
7799 | return; | |
7800 | ||
7801 | case M_DSUB_I: | |
7802 | dbl = 1; | |
7803 | case M_SUB_I: | |
7804 | if (imm_expr.X_op == O_constant | |
7805 | && imm_expr.X_add_number > -0x8000 | |
7806 | && imm_expr.X_add_number <= 0x8000) | |
7807 | { | |
7808 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7809 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7810 | dbl ? "daddi" : "addi", | |
7811 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7812 | return; | |
7813 | } | |
7814 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7815 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7816 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7817 | break; |
7818 | ||
7819 | case M_DSUBU_I: | |
7820 | dbl = 1; | |
7821 | case M_SUBU_I: | |
7822 | if (imm_expr.X_op == O_constant | |
7823 | && imm_expr.X_add_number > -0x8000 | |
7824 | && imm_expr.X_add_number <= 0x8000) | |
7825 | { | |
7826 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7827 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7828 | dbl ? "daddiu" : "addiu", | |
7829 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7830 | return; | |
7831 | } | |
7832 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7833 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7834 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7835 | break; |
7836 | ||
7837 | case M_TEQ_I: | |
7838 | s = "teq"; | |
7839 | goto trap; | |
7840 | case M_TGE_I: | |
7841 | s = "tge"; | |
7842 | goto trap; | |
7843 | case M_TGEU_I: | |
7844 | s = "tgeu"; | |
7845 | goto trap; | |
7846 | case M_TLT_I: | |
7847 | s = "tlt"; | |
7848 | goto trap; | |
7849 | case M_TLTU_I: | |
7850 | s = "tltu"; | |
7851 | goto trap; | |
7852 | case M_TNE_I: | |
7853 | s = "tne"; | |
7854 | trap: | |
4d34fb5f | 7855 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7856 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
7857 | AT); | |
252b5132 RH |
7858 | break; |
7859 | ||
252b5132 | 7860 | case M_TRUNCWS: |
43841e91 | 7861 | case M_TRUNCWD: |
e7af610e | 7862 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7863 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7864 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7865 | ||
7866 | /* | |
7867 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7868 | * or is there a reason for it? | |
7869 | */ | |
b34976b6 | 7870 | mips_emit_delays (TRUE); |
252b5132 RH |
7871 | ++mips_opts.noreorder; |
7872 | mips_any_noreorder = 1; | |
2396cfb9 | 7873 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7874 | treg, RA); |
2396cfb9 | 7875 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7876 | treg, RA); |
2396cfb9 | 7877 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7878 | expr1.X_add_number = 3; |
7879 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
7880 | (int) BFD_RELOC_LO16); | |
7881 | expr1.X_add_number = 2; | |
7882 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
7883 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 7884 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7885 | AT, RA); |
2396cfb9 TS |
7886 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
7887 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 7888 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
2396cfb9 | 7889 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7890 | treg, RA); |
2396cfb9 | 7891 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7892 | --mips_opts.noreorder; |
7893 | break; | |
7894 | ||
7895 | case M_ULH: | |
7896 | s = "lb"; | |
7897 | goto ulh; | |
7898 | case M_ULHU: | |
7899 | s = "lbu"; | |
7900 | ulh: | |
7901 | if (offset_expr.X_add_number >= 0x7fff) | |
7902 | as_bad (_("operand overflow")); | |
252b5132 | 7903 | if (! target_big_endian) |
f9419b05 | 7904 | ++offset_expr.X_add_number; |
af22f5b2 | 7905 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", AT, |
252b5132 RH |
7906 | (int) BFD_RELOC_LO16, breg); |
7907 | if (! target_big_endian) | |
f9419b05 | 7908 | --offset_expr.X_add_number; |
252b5132 | 7909 | else |
f9419b05 | 7910 | ++offset_expr.X_add_number; |
af22f5b2 | 7911 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg, |
252b5132 | 7912 | (int) BFD_RELOC_LO16, breg); |
2396cfb9 | 7913 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
af22f5b2 | 7914 | AT, AT, 8); |
2396cfb9 TS |
7915 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", |
7916 | treg, treg, AT); | |
252b5132 RH |
7917 | break; |
7918 | ||
7919 | case M_ULD: | |
7920 | s = "ldl"; | |
7921 | s2 = "ldr"; | |
7922 | off = 7; | |
7923 | goto ulw; | |
7924 | case M_ULW: | |
7925 | s = "lwl"; | |
7926 | s2 = "lwr"; | |
7927 | off = 3; | |
7928 | ulw: | |
7929 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7930 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7931 | if (treg != breg) |
7932 | tempreg = treg; | |
7933 | else | |
7934 | tempreg = AT; | |
252b5132 RH |
7935 | if (! target_big_endian) |
7936 | offset_expr.X_add_number += off; | |
af22f5b2 | 7937 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg, |
252b5132 RH |
7938 | (int) BFD_RELOC_LO16, breg); |
7939 | if (! target_big_endian) | |
7940 | offset_expr.X_add_number -= off; | |
7941 | else | |
7942 | offset_expr.X_add_number += off; | |
af22f5b2 | 7943 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg, |
252b5132 | 7944 | (int) BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7945 | |
7946 | /* If necessary, move the result in tempreg the final destination. */ | |
7947 | if (treg == tempreg) | |
7948 | return; | |
7949 | /* Protect second load's delay slot. */ | |
7950 | if (!gpr_interlocks) | |
7951 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
7952 | move_register (&icnt, treg, tempreg); | |
7953 | break; | |
252b5132 RH |
7954 | |
7955 | case M_ULD_A: | |
7956 | s = "ldl"; | |
7957 | s2 = "ldr"; | |
7958 | off = 7; | |
7959 | goto ulwa; | |
7960 | case M_ULW_A: | |
7961 | s = "lwl"; | |
7962 | s2 = "lwr"; | |
7963 | off = 3; | |
7964 | ulwa: | |
d6bc6245 | 7965 | used_at = 1; |
c9914766 | 7966 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7967 | if (breg != 0) |
7968 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 7969 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7970 | if (! target_big_endian) |
7971 | expr1.X_add_number = off; | |
7972 | else | |
7973 | expr1.X_add_number = 0; | |
7974 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7975 | (int) BFD_RELOC_LO16, AT); | |
7976 | if (! target_big_endian) | |
7977 | expr1.X_add_number = 0; | |
7978 | else | |
7979 | expr1.X_add_number = off; | |
7980 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7981 | (int) BFD_RELOC_LO16, AT); | |
7982 | break; | |
7983 | ||
7984 | case M_ULH_A: | |
7985 | case M_ULHU_A: | |
d6bc6245 | 7986 | used_at = 1; |
c9914766 | 7987 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7988 | if (breg != 0) |
7989 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 7990 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7991 | if (target_big_endian) |
7992 | expr1.X_add_number = 0; | |
7993 | macro_build ((char *) NULL, &icnt, &expr1, | |
7994 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
7995 | (int) BFD_RELOC_LO16, AT); | |
7996 | if (target_big_endian) | |
7997 | expr1.X_add_number = 1; | |
7998 | else | |
7999 | expr1.X_add_number = 0; | |
8000 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
8001 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
8002 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
8003 | treg, treg, 8); | |
8004 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
8005 | treg, treg, AT); | |
252b5132 RH |
8006 | break; |
8007 | ||
8008 | case M_USH: | |
8009 | if (offset_expr.X_add_number >= 0x7fff) | |
8010 | as_bad (_("operand overflow")); | |
8011 | if (target_big_endian) | |
f9419b05 | 8012 | ++offset_expr.X_add_number; |
252b5132 RH |
8013 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
8014 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
8015 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
8016 | AT, treg, 8); | |
252b5132 | 8017 | if (target_big_endian) |
f9419b05 | 8018 | --offset_expr.X_add_number; |
252b5132 | 8019 | else |
f9419b05 | 8020 | ++offset_expr.X_add_number; |
252b5132 RH |
8021 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
8022 | (int) BFD_RELOC_LO16, breg); | |
8023 | break; | |
8024 | ||
8025 | case M_USD: | |
8026 | s = "sdl"; | |
8027 | s2 = "sdr"; | |
8028 | off = 7; | |
8029 | goto usw; | |
8030 | case M_USW: | |
8031 | s = "swl"; | |
8032 | s2 = "swr"; | |
8033 | off = 3; | |
8034 | usw: | |
8035 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8036 | as_bad (_("operand overflow")); | |
8037 | if (! target_big_endian) | |
8038 | offset_expr.X_add_number += off; | |
8039 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
8040 | (int) BFD_RELOC_LO16, breg); | |
8041 | if (! target_big_endian) | |
8042 | offset_expr.X_add_number -= off; | |
8043 | else | |
8044 | offset_expr.X_add_number += off; | |
8045 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
8046 | (int) BFD_RELOC_LO16, breg); | |
8047 | return; | |
8048 | ||
8049 | case M_USD_A: | |
8050 | s = "sdl"; | |
8051 | s2 = "sdr"; | |
8052 | off = 7; | |
8053 | goto uswa; | |
8054 | case M_USW_A: | |
8055 | s = "swl"; | |
8056 | s2 = "swr"; | |
8057 | off = 3; | |
8058 | uswa: | |
d6bc6245 | 8059 | used_at = 1; |
c9914766 | 8060 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
8061 | if (breg != 0) |
8062 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 8063 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8064 | if (! target_big_endian) |
8065 | expr1.X_add_number = off; | |
8066 | else | |
8067 | expr1.X_add_number = 0; | |
8068 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
8069 | (int) BFD_RELOC_LO16, AT); | |
8070 | if (! target_big_endian) | |
8071 | expr1.X_add_number = 0; | |
8072 | else | |
8073 | expr1.X_add_number = off; | |
8074 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
8075 | (int) BFD_RELOC_LO16, AT); | |
8076 | break; | |
8077 | ||
8078 | case M_USH_A: | |
d6bc6245 | 8079 | used_at = 1; |
c9914766 | 8080 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
8081 | if (breg != 0) |
8082 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f899b4b8 | 8083 | ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8084 | if (! target_big_endian) |
8085 | expr1.X_add_number = 0; | |
8086 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
8087 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
8088 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
8089 | treg, treg, 8); | |
252b5132 RH |
8090 | if (! target_big_endian) |
8091 | expr1.X_add_number = 1; | |
8092 | else | |
8093 | expr1.X_add_number = 0; | |
8094 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
8095 | (int) BFD_RELOC_LO16, AT); | |
8096 | if (! target_big_endian) | |
8097 | expr1.X_add_number = 0; | |
8098 | else | |
8099 | expr1.X_add_number = 1; | |
8100 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
8101 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
8102 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
8103 | treg, treg, 8); | |
8104 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
8105 | treg, treg, AT); | |
252b5132 RH |
8106 | break; |
8107 | ||
8108 | default: | |
8109 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8110 | are added dynamically. */ |
252b5132 RH |
8111 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8112 | break; | |
8113 | } | |
8114 | if (mips_opts.noat) | |
8115 | as_warn (_("Macro used $at after \".set noat\"")); | |
8116 | } | |
8117 | ||
8118 | /* Implement macros in mips16 mode. */ | |
8119 | ||
8120 | static void | |
8121 | mips16_macro (ip) | |
8122 | struct mips_cl_insn *ip; | |
8123 | { | |
8124 | int mask; | |
8125 | int xreg, yreg, zreg, tmp; | |
8126 | int icnt; | |
8127 | expressionS expr1; | |
8128 | int dbl; | |
8129 | const char *s, *s2, *s3; | |
8130 | ||
8131 | mask = ip->insn_mo->mask; | |
8132 | ||
8133 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
8134 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
8135 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8136 | ||
8137 | icnt = 0; | |
8138 | ||
8139 | expr1.X_op = O_constant; | |
8140 | expr1.X_op_symbol = NULL; | |
8141 | expr1.X_add_symbol = NULL; | |
8142 | expr1.X_add_number = 1; | |
8143 | ||
8144 | dbl = 0; | |
8145 | ||
8146 | switch (mask) | |
8147 | { | |
8148 | default: | |
8149 | internalError (); | |
8150 | ||
8151 | case M_DDIV_3: | |
8152 | dbl = 1; | |
8153 | case M_DIV_3: | |
8154 | s = "mflo"; | |
8155 | goto do_div3; | |
8156 | case M_DREM_3: | |
8157 | dbl = 1; | |
8158 | case M_REM_3: | |
8159 | s = "mfhi"; | |
8160 | do_div3: | |
b34976b6 | 8161 | mips_emit_delays (TRUE); |
252b5132 RH |
8162 | ++mips_opts.noreorder; |
8163 | mips_any_noreorder = 1; | |
2396cfb9 | 8164 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
8165 | dbl ? "ddiv" : "div", |
8166 | "0,x,y", xreg, yreg); | |
8167 | expr1.X_add_number = 2; | |
8168 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
8169 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
8170 | 7); | |
bdaaa2e1 | 8171 | |
252b5132 RH |
8172 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8173 | since that causes an overflow. We should do that as well, | |
8174 | but I don't see how to do the comparisons without a temporary | |
8175 | register. */ | |
8176 | --mips_opts.noreorder; | |
2396cfb9 | 8177 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
252b5132 RH |
8178 | break; |
8179 | ||
8180 | case M_DIVU_3: | |
8181 | s = "divu"; | |
8182 | s2 = "mflo"; | |
8183 | goto do_divu3; | |
8184 | case M_REMU_3: | |
8185 | s = "divu"; | |
8186 | s2 = "mfhi"; | |
8187 | goto do_divu3; | |
8188 | case M_DDIVU_3: | |
8189 | s = "ddivu"; | |
8190 | s2 = "mflo"; | |
8191 | goto do_divu3; | |
8192 | case M_DREMU_3: | |
8193 | s = "ddivu"; | |
8194 | s2 = "mfhi"; | |
8195 | do_divu3: | |
b34976b6 | 8196 | mips_emit_delays (TRUE); |
252b5132 RH |
8197 | ++mips_opts.noreorder; |
8198 | mips_any_noreorder = 1; | |
2396cfb9 TS |
8199 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
8200 | xreg, yreg); | |
252b5132 RH |
8201 | expr1.X_add_number = 2; |
8202 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
98d3f06f KH |
8203 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
8204 | "6", 7); | |
252b5132 | 8205 | --mips_opts.noreorder; |
2396cfb9 | 8206 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
252b5132 RH |
8207 | break; |
8208 | ||
8209 | case M_DMUL: | |
8210 | dbl = 1; | |
8211 | case M_MUL: | |
2396cfb9 | 8212 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 8213 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
2396cfb9 TS |
8214 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
8215 | zreg); | |
252b5132 RH |
8216 | return; |
8217 | ||
8218 | case M_DSUBU_I: | |
8219 | dbl = 1; | |
8220 | goto do_subu; | |
8221 | case M_SUBU_I: | |
8222 | do_subu: | |
8223 | if (imm_expr.X_op != O_constant) | |
8224 | as_bad (_("Unsupported large constant")); | |
8225 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
8226 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 8227 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8228 | break; |
8229 | ||
8230 | case M_SUBU_I_2: | |
8231 | if (imm_expr.X_op != O_constant) | |
8232 | as_bad (_("Unsupported large constant")); | |
8233 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
8234 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
8235 | "x,k", xreg); | |
8236 | break; | |
8237 | ||
8238 | case M_DSUBU_I_2: | |
8239 | if (imm_expr.X_op != O_constant) | |
8240 | as_bad (_("Unsupported large constant")); | |
8241 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
8242 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
8243 | "y,j", yreg); | |
8244 | break; | |
8245 | ||
8246 | case M_BEQ: | |
8247 | s = "cmp"; | |
8248 | s2 = "bteqz"; | |
8249 | goto do_branch; | |
8250 | case M_BNE: | |
8251 | s = "cmp"; | |
8252 | s2 = "btnez"; | |
8253 | goto do_branch; | |
8254 | case M_BLT: | |
8255 | s = "slt"; | |
8256 | s2 = "btnez"; | |
8257 | goto do_branch; | |
8258 | case M_BLTU: | |
8259 | s = "sltu"; | |
8260 | s2 = "btnez"; | |
8261 | goto do_branch; | |
8262 | case M_BLE: | |
8263 | s = "slt"; | |
8264 | s2 = "bteqz"; | |
8265 | goto do_reverse_branch; | |
8266 | case M_BLEU: | |
8267 | s = "sltu"; | |
8268 | s2 = "bteqz"; | |
8269 | goto do_reverse_branch; | |
8270 | case M_BGE: | |
8271 | s = "slt"; | |
8272 | s2 = "bteqz"; | |
8273 | goto do_branch; | |
8274 | case M_BGEU: | |
8275 | s = "sltu"; | |
8276 | s2 = "bteqz"; | |
8277 | goto do_branch; | |
8278 | case M_BGT: | |
8279 | s = "slt"; | |
8280 | s2 = "btnez"; | |
8281 | goto do_reverse_branch; | |
8282 | case M_BGTU: | |
8283 | s = "sltu"; | |
8284 | s2 = "btnez"; | |
8285 | ||
8286 | do_reverse_branch: | |
8287 | tmp = xreg; | |
8288 | xreg = yreg; | |
8289 | yreg = tmp; | |
8290 | ||
8291 | do_branch: | |
8292 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
8293 | xreg, yreg); | |
8294 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
8295 | break; | |
8296 | ||
8297 | case M_BEQ_I: | |
8298 | s = "cmpi"; | |
8299 | s2 = "bteqz"; | |
8300 | s3 = "x,U"; | |
8301 | goto do_branch_i; | |
8302 | case M_BNE_I: | |
8303 | s = "cmpi"; | |
8304 | s2 = "btnez"; | |
8305 | s3 = "x,U"; | |
8306 | goto do_branch_i; | |
8307 | case M_BLT_I: | |
8308 | s = "slti"; | |
8309 | s2 = "btnez"; | |
8310 | s3 = "x,8"; | |
8311 | goto do_branch_i; | |
8312 | case M_BLTU_I: | |
8313 | s = "sltiu"; | |
8314 | s2 = "btnez"; | |
8315 | s3 = "x,8"; | |
8316 | goto do_branch_i; | |
8317 | case M_BLE_I: | |
8318 | s = "slti"; | |
8319 | s2 = "btnez"; | |
8320 | s3 = "x,8"; | |
8321 | goto do_addone_branch_i; | |
8322 | case M_BLEU_I: | |
8323 | s = "sltiu"; | |
8324 | s2 = "btnez"; | |
8325 | s3 = "x,8"; | |
8326 | goto do_addone_branch_i; | |
8327 | case M_BGE_I: | |
8328 | s = "slti"; | |
8329 | s2 = "bteqz"; | |
8330 | s3 = "x,8"; | |
8331 | goto do_branch_i; | |
8332 | case M_BGEU_I: | |
8333 | s = "sltiu"; | |
8334 | s2 = "bteqz"; | |
8335 | s3 = "x,8"; | |
8336 | goto do_branch_i; | |
8337 | case M_BGT_I: | |
8338 | s = "slti"; | |
8339 | s2 = "bteqz"; | |
8340 | s3 = "x,8"; | |
8341 | goto do_addone_branch_i; | |
8342 | case M_BGTU_I: | |
8343 | s = "sltiu"; | |
8344 | s2 = "bteqz"; | |
8345 | s3 = "x,8"; | |
8346 | ||
8347 | do_addone_branch_i: | |
8348 | if (imm_expr.X_op != O_constant) | |
8349 | as_bad (_("Unsupported large constant")); | |
8350 | ++imm_expr.X_add_number; | |
8351 | ||
8352 | do_branch_i: | |
8353 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
8354 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
8355 | break; | |
8356 | ||
8357 | case M_ABS: | |
8358 | expr1.X_add_number = 0; | |
98d3f06f | 8359 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 8360 | if (xreg != yreg) |
ea1fb5dc | 8361 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
8362 | expr1.X_add_number = 2; |
8363 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
8364 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
8365 | "neg", "x,w", xreg, xreg); | |
8366 | } | |
8367 | } | |
8368 | ||
8369 | /* For consistency checking, verify that all bits are specified either | |
8370 | by the match/mask part of the instruction definition, or by the | |
8371 | operand list. */ | |
8372 | static int | |
8373 | validate_mips_insn (opc) | |
8374 | const struct mips_opcode *opc; | |
8375 | { | |
8376 | const char *p = opc->args; | |
8377 | char c; | |
8378 | unsigned long used_bits = opc->mask; | |
8379 | ||
8380 | if ((used_bits & opc->match) != opc->match) | |
8381 | { | |
8382 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8383 | opc->name, opc->args); | |
8384 | return 0; | |
8385 | } | |
8386 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8387 | while (*p) | |
8388 | switch (c = *p++) | |
8389 | { | |
8390 | case ',': break; | |
8391 | case '(': break; | |
8392 | case ')': break; | |
af7ee8bf CD |
8393 | case '+': |
8394 | switch (c = *p++) | |
8395 | { | |
8396 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8397 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8398 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8399 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8400 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8401 | default: |
8402 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8403 | c, opc->name, opc->args); | |
8404 | return 0; | |
8405 | } | |
8406 | break; | |
252b5132 RH |
8407 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8408 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8409 | case 'A': break; | |
4372b673 | 8410 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8411 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8412 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8413 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8414 | case 'F': break; | |
8415 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8416 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8417 | case 'I': break; |
e972090a | 8418 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8419 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8420 | case 'L': break; |
8421 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8422 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8423 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8424 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8425 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8426 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8427 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8428 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8429 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8430 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8431 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8432 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8433 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8434 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8435 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8436 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8437 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8438 | case 'f': break; | |
8439 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8440 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8441 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8442 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8443 | case 'l': break; | |
8444 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8445 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8446 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8447 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8448 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8449 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8450 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8451 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8452 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8453 | case 'x': break; | |
8454 | case 'z': break; | |
8455 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8456 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8457 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8458 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8459 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8460 | case '[': break; | |
8461 | case ']': break; | |
252b5132 RH |
8462 | default: |
8463 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8464 | c, opc->name, opc->args); | |
8465 | return 0; | |
8466 | } | |
8467 | #undef USE_BITS | |
8468 | if (used_bits != 0xffffffff) | |
8469 | { | |
8470 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8471 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8472 | return 0; | |
8473 | } | |
8474 | return 1; | |
8475 | } | |
8476 | ||
8477 | /* This routine assembles an instruction into its binary format. As a | |
8478 | side effect, it sets one of the global variables imm_reloc or | |
8479 | offset_reloc to the type of relocation to do if one of the operands | |
8480 | is an address expression. */ | |
8481 | ||
8482 | static void | |
8483 | mips_ip (str, ip) | |
8484 | char *str; | |
8485 | struct mips_cl_insn *ip; | |
8486 | { | |
8487 | char *s; | |
8488 | const char *args; | |
43841e91 | 8489 | char c = 0; |
252b5132 RH |
8490 | struct mips_opcode *insn; |
8491 | char *argsStart; | |
8492 | unsigned int regno; | |
8493 | unsigned int lastregno = 0; | |
af7ee8bf | 8494 | unsigned int lastpos = 0; |
071742cf | 8495 | unsigned int limlo, limhi; |
252b5132 RH |
8496 | char *s_reset; |
8497 | char save_c = 0; | |
252b5132 RH |
8498 | |
8499 | insn_error = NULL; | |
8500 | ||
8501 | /* If the instruction contains a '.', we first try to match an instruction | |
8502 | including the '.'. Then we try again without the '.'. */ | |
8503 | insn = NULL; | |
3882b010 | 8504 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8505 | continue; |
8506 | ||
8507 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8508 | the call to hash_find. Save the character we replaced just in case we | |
8509 | have to re-parse the instruction. */ | |
3882b010 | 8510 | if (ISSPACE (*s)) |
252b5132 RH |
8511 | { |
8512 | save_c = *s; | |
8513 | *s++ = '\0'; | |
8514 | } | |
bdaaa2e1 | 8515 | |
252b5132 RH |
8516 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8517 | ||
8518 | /* If we didn't find the instruction in the opcode table, try again, but | |
8519 | this time with just the instruction up to, but not including the | |
8520 | first '.'. */ | |
8521 | if (insn == NULL) | |
8522 | { | |
bdaaa2e1 | 8523 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8524 | if (save_c) |
8525 | *(--s) = save_c; | |
8526 | ||
8527 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8528 | for (s = str; |
8529 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8530 | ++s) | |
252b5132 RH |
8531 | continue; |
8532 | ||
8533 | /* If we did not find a '.', then we can quit now. */ | |
8534 | if (*s != '.') | |
8535 | { | |
8536 | insn_error = "unrecognized opcode"; | |
8537 | return; | |
8538 | } | |
8539 | ||
8540 | /* Lookup the instruction in the hash table. */ | |
8541 | *s++ = '\0'; | |
8542 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8543 | { | |
8544 | insn_error = "unrecognized opcode"; | |
8545 | return; | |
8546 | } | |
252b5132 RH |
8547 | } |
8548 | ||
8549 | argsStart = s; | |
8550 | for (;;) | |
8551 | { | |
b34976b6 | 8552 | bfd_boolean ok; |
252b5132 RH |
8553 | |
8554 | assert (strcmp (insn->name, str) == 0); | |
8555 | ||
1f25f5d3 CD |
8556 | if (OPCODE_IS_MEMBER (insn, |
8557 | (mips_opts.isa | |
3396de36 | 8558 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8559 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8560 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
1f25f5d3 | 8561 | mips_arch)) |
b34976b6 | 8562 | ok = TRUE; |
bdaaa2e1 | 8563 | else |
b34976b6 | 8564 | ok = FALSE; |
bdaaa2e1 | 8565 | |
252b5132 RH |
8566 | if (insn->pinfo != INSN_MACRO) |
8567 | { | |
ec68c924 | 8568 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8569 | ok = FALSE; |
252b5132 RH |
8570 | } |
8571 | ||
8572 | if (! ok) | |
8573 | { | |
8574 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8575 | && strcmp (insn->name, insn[1].name) == 0) | |
8576 | { | |
8577 | ++insn; | |
8578 | continue; | |
8579 | } | |
252b5132 | 8580 | else |
beae10d5 | 8581 | { |
268f6bed L |
8582 | if (!insn_error) |
8583 | { | |
8584 | static char buf[100]; | |
316f5878 RS |
8585 | if (mips_arch_info->is_isa) |
8586 | sprintf (buf, | |
8587 | _("opcode not supported at this ISA level (%s)"), | |
8588 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8589 | else | |
8590 | sprintf (buf, | |
8591 | _("opcode not supported on this processor: %s (%s)"), | |
8592 | mips_arch_info->name, | |
8593 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8594 | insn_error = buf; |
8595 | } | |
8596 | if (save_c) | |
8597 | *(--s) = save_c; | |
2bd7f1f3 | 8598 | return; |
252b5132 | 8599 | } |
252b5132 RH |
8600 | } |
8601 | ||
8602 | ip->insn_mo = insn; | |
8603 | ip->insn_opcode = insn->match; | |
268f6bed | 8604 | insn_error = NULL; |
252b5132 RH |
8605 | for (args = insn->args;; ++args) |
8606 | { | |
deec1734 CD |
8607 | int is_mdmx; |
8608 | ||
ad8d3bb3 | 8609 | s += strspn (s, " \t"); |
deec1734 | 8610 | is_mdmx = 0; |
252b5132 RH |
8611 | switch (*args) |
8612 | { | |
8613 | case '\0': /* end of args */ | |
8614 | if (*s == '\0') | |
8615 | return; | |
8616 | break; | |
8617 | ||
8618 | case ',': | |
8619 | if (*s++ == *args) | |
8620 | continue; | |
8621 | s--; | |
8622 | switch (*++args) | |
8623 | { | |
8624 | case 'r': | |
8625 | case 'v': | |
38487616 | 8626 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8627 | continue; |
8628 | ||
8629 | case 'w': | |
38487616 TS |
8630 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8631 | continue; | |
8632 | ||
252b5132 | 8633 | case 'W': |
38487616 | 8634 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8635 | continue; |
8636 | ||
8637 | case 'V': | |
38487616 | 8638 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8639 | continue; |
8640 | } | |
8641 | break; | |
8642 | ||
8643 | case '(': | |
8644 | /* Handle optional base register. | |
8645 | Either the base register is omitted or | |
bdaaa2e1 | 8646 | we must have a left paren. */ |
252b5132 RH |
8647 | /* This is dependent on the next operand specifier |
8648 | is a base register specification. */ | |
8649 | assert (args[1] == 'b' || args[1] == '5' | |
8650 | || args[1] == '-' || args[1] == '4'); | |
8651 | if (*s == '\0') | |
8652 | return; | |
8653 | ||
8654 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8655 | case '[': |
8656 | case ']': | |
252b5132 RH |
8657 | if (*s++ == *args) |
8658 | continue; | |
8659 | break; | |
8660 | ||
af7ee8bf CD |
8661 | case '+': /* Opcode extension character. */ |
8662 | switch (*++args) | |
8663 | { | |
071742cf CD |
8664 | case 'A': /* ins/ext position, becomes LSB. */ |
8665 | limlo = 0; | |
8666 | limhi = 31; | |
8667 | my_getExpression (&imm_expr, s); | |
8668 | check_absolute_expr (ip, &imm_expr); | |
8669 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8670 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8671 | { | |
8672 | as_bad (_("Improper position (%lu)"), | |
8673 | (unsigned long) imm_expr.X_add_number); | |
8674 | imm_expr.X_add_number = limlo; | |
8675 | } | |
8676 | lastpos = imm_expr.X_add_number; | |
8677 | ip->insn_opcode |= (imm_expr.X_add_number | |
8678 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8679 | imm_expr.X_op = O_absent; | |
8680 | s = expr_end; | |
8681 | continue; | |
8682 | ||
8683 | case 'B': /* ins size, becomes MSB. */ | |
8684 | limlo = 1; | |
8685 | limhi = 32; | |
8686 | my_getExpression (&imm_expr, s); | |
8687 | check_absolute_expr (ip, &imm_expr); | |
8688 | /* Check for negative input so that small negative numbers | |
8689 | will not succeed incorrectly. The checks against | |
8690 | (pos+size) transitively check "size" itself, | |
8691 | assuming that "pos" is reasonable. */ | |
8692 | if ((long) imm_expr.X_add_number < 0 | |
8693 | || ((unsigned long) imm_expr.X_add_number | |
8694 | + lastpos) < limlo | |
8695 | || ((unsigned long) imm_expr.X_add_number | |
8696 | + lastpos) > limhi) | |
8697 | { | |
8698 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8699 | (unsigned long) imm_expr.X_add_number, | |
8700 | (unsigned long) lastpos); | |
8701 | imm_expr.X_add_number = limlo - lastpos; | |
8702 | } | |
8703 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8704 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8705 | imm_expr.X_op = O_absent; | |
8706 | s = expr_end; | |
8707 | continue; | |
8708 | ||
8709 | case 'C': /* ext size, becomes MSBD. */ | |
8710 | limlo = 1; | |
8711 | limhi = 32; | |
8712 | my_getExpression (&imm_expr, s); | |
8713 | check_absolute_expr (ip, &imm_expr); | |
8714 | /* Check for negative input so that small negative numbers | |
8715 | will not succeed incorrectly. The checks against | |
8716 | (pos+size) transitively check "size" itself, | |
8717 | assuming that "pos" is reasonable. */ | |
8718 | if ((long) imm_expr.X_add_number < 0 | |
8719 | || ((unsigned long) imm_expr.X_add_number | |
8720 | + lastpos) < limlo | |
8721 | || ((unsigned long) imm_expr.X_add_number | |
8722 | + lastpos) > limhi) | |
8723 | { | |
8724 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8725 | (unsigned long) imm_expr.X_add_number, | |
8726 | (unsigned long) lastpos); | |
8727 | imm_expr.X_add_number = limlo - lastpos; | |
8728 | } | |
8729 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8730 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8731 | imm_expr.X_op = O_absent; | |
8732 | s = expr_end; | |
8733 | continue; | |
af7ee8bf | 8734 | |
bbcc0807 CD |
8735 | case 'D': |
8736 | /* +D is for disassembly only; never match. */ | |
8737 | break; | |
8738 | ||
af7ee8bf CD |
8739 | default: |
8740 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8741 | *args, insn->name, insn->args); | |
8742 | /* Further processing is fruitless. */ | |
8743 | return; | |
8744 | } | |
8745 | break; | |
8746 | ||
252b5132 RH |
8747 | case '<': /* must be at least one digit */ |
8748 | /* | |
8749 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8750 | * than 31 or less than 0, then the shift amount should be |
8751 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8752 | * We issue a warning and mask out all but the low 5 bits. |
8753 | */ | |
8754 | my_getExpression (&imm_expr, s); | |
8755 | check_absolute_expr (ip, &imm_expr); | |
8756 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8757 | { | |
793b27f4 TS |
8758 | as_warn (_("Improper shift amount (%lu)"), |
8759 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8760 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8761 | } |
38487616 | 8762 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8763 | imm_expr.X_op = O_absent; |
8764 | s = expr_end; | |
8765 | continue; | |
8766 | ||
8767 | case '>': /* shift amount minus 32 */ | |
8768 | my_getExpression (&imm_expr, s); | |
8769 | check_absolute_expr (ip, &imm_expr); | |
8770 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8771 | || (unsigned long) imm_expr.X_add_number > 63) | |
8772 | break; | |
38487616 | 8773 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8774 | imm_expr.X_op = O_absent; |
8775 | s = expr_end; | |
8776 | continue; | |
8777 | ||
252b5132 RH |
8778 | case 'k': /* cache code */ |
8779 | case 'h': /* prefx code */ | |
8780 | my_getExpression (&imm_expr, s); | |
8781 | check_absolute_expr (ip, &imm_expr); | |
8782 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8783 | { | |
8784 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8785 | ip->insn_mo->name, | |
8786 | (unsigned long) imm_expr.X_add_number); | |
8787 | imm_expr.X_add_number &= 0x1f; | |
8788 | } | |
8789 | if (*args == 'k') | |
8790 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8791 | else | |
8792 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8793 | imm_expr.X_op = O_absent; | |
8794 | s = expr_end; | |
8795 | continue; | |
8796 | ||
8797 | case 'c': /* break code */ | |
8798 | my_getExpression (&imm_expr, s); | |
8799 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8800 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8801 | { |
793b27f4 TS |
8802 | as_warn (_("Illegal break code (%lu)"), |
8803 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8804 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8805 | } |
38487616 | 8806 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8807 | imm_expr.X_op = O_absent; |
8808 | s = expr_end; | |
8809 | continue; | |
8810 | ||
8811 | case 'q': /* lower break code */ | |
8812 | my_getExpression (&imm_expr, s); | |
8813 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8814 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8815 | { |
793b27f4 TS |
8816 | as_warn (_("Illegal lower break code (%lu)"), |
8817 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8818 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8819 | } |
38487616 | 8820 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8821 | imm_expr.X_op = O_absent; |
8822 | s = expr_end; | |
8823 | continue; | |
8824 | ||
4372b673 | 8825 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8826 | my_getExpression (&imm_expr, s); |
156c2f8b | 8827 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8828 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8829 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8830 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8831 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8832 | imm_expr.X_op = O_absent; |
8833 | s = expr_end; | |
8834 | continue; | |
8835 | ||
98d3f06f | 8836 | case 'C': /* Coprocessor code */ |
beae10d5 | 8837 | my_getExpression (&imm_expr, s); |
252b5132 | 8838 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8839 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8840 | { |
793b27f4 TS |
8841 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8842 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8843 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8844 | } |
beae10d5 KH |
8845 | ip->insn_opcode |= imm_expr.X_add_number; |
8846 | imm_expr.X_op = O_absent; | |
8847 | s = expr_end; | |
8848 | continue; | |
252b5132 | 8849 | |
4372b673 NC |
8850 | case 'J': /* 19-bit wait code. */ |
8851 | my_getExpression (&imm_expr, s); | |
8852 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8853 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8854 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8855 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8856 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8857 | imm_expr.X_op = O_absent; |
8858 | s = expr_end; | |
8859 | continue; | |
8860 | ||
252b5132 | 8861 | case 'P': /* Performance register */ |
beae10d5 | 8862 | my_getExpression (&imm_expr, s); |
252b5132 | 8863 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8864 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8865 | { |
793b27f4 TS |
8866 | as_warn (_("Invalid performance register (%lu)"), |
8867 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8868 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8869 | } |
38487616 | 8870 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8871 | imm_expr.X_op = O_absent; |
8872 | s = expr_end; | |
8873 | continue; | |
252b5132 RH |
8874 | |
8875 | case 'b': /* base register */ | |
8876 | case 'd': /* destination register */ | |
8877 | case 's': /* source register */ | |
8878 | case 't': /* target register */ | |
8879 | case 'r': /* both target and source */ | |
8880 | case 'v': /* both dest and source */ | |
8881 | case 'w': /* both dest and target */ | |
8882 | case 'E': /* coprocessor target register */ | |
8883 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8884 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8885 | case 'x': /* ignore register name */ |
8886 | case 'z': /* must be zero register */ | |
4372b673 | 8887 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8888 | s_reset = s; |
8889 | if (s[0] == '$') | |
8890 | { | |
8891 | ||
3882b010 | 8892 | if (ISDIGIT (s[1])) |
252b5132 RH |
8893 | { |
8894 | ++s; | |
8895 | regno = 0; | |
8896 | do | |
8897 | { | |
8898 | regno *= 10; | |
8899 | regno += *s - '0'; | |
8900 | ++s; | |
8901 | } | |
3882b010 | 8902 | while (ISDIGIT (*s)); |
252b5132 RH |
8903 | if (regno > 31) |
8904 | as_bad (_("Invalid register number (%d)"), regno); | |
8905 | } | |
af7ee8bf | 8906 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8907 | goto notreg; |
8908 | else | |
8909 | { | |
76db943d TS |
8910 | if (s[1] == 'r' && s[2] == 'a') |
8911 | { | |
8912 | s += 3; | |
8913 | regno = RA; | |
8914 | } | |
8915 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8916 | { |
8917 | s += 3; | |
8918 | regno = FP; | |
8919 | } | |
8920 | else if (s[1] == 's' && s[2] == 'p') | |
8921 | { | |
8922 | s += 3; | |
8923 | regno = SP; | |
8924 | } | |
8925 | else if (s[1] == 'g' && s[2] == 'p') | |
8926 | { | |
8927 | s += 3; | |
8928 | regno = GP; | |
8929 | } | |
8930 | else if (s[1] == 'a' && s[2] == 't') | |
8931 | { | |
8932 | s += 3; | |
8933 | regno = AT; | |
8934 | } | |
8935 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8936 | { | |
8937 | s += 4; | |
8938 | regno = KT0; | |
8939 | } | |
8940 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8941 | { | |
8942 | s += 4; | |
8943 | regno = KT1; | |
8944 | } | |
85b51719 TS |
8945 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8946 | { | |
8947 | s += 5; | |
8948 | regno = ZERO; | |
8949 | } | |
252b5132 RH |
8950 | else if (itbl_have_entries) |
8951 | { | |
8952 | char *p, *n; | |
d7ba4a77 | 8953 | unsigned long r; |
252b5132 | 8954 | |
d7ba4a77 | 8955 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8956 | n = itbl_get_field (&p); /* n is name */ |
8957 | ||
d7ba4a77 ILT |
8958 | /* See if this is a register defined in an |
8959 | itbl entry. */ | |
8960 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8961 | { |
8962 | /* Get_field advances to the start of | |
8963 | the next field, so we need to back | |
d7ba4a77 | 8964 | rack to the end of the last field. */ |
bdaaa2e1 | 8965 | if (p) |
252b5132 | 8966 | s = p - 1; |
bdaaa2e1 | 8967 | else |
d7ba4a77 | 8968 | s = strchr (s, '\0'); |
252b5132 RH |
8969 | regno = r; |
8970 | } | |
8971 | else | |
8972 | goto notreg; | |
beae10d5 | 8973 | } |
252b5132 RH |
8974 | else |
8975 | goto notreg; | |
8976 | } | |
8977 | if (regno == AT | |
8978 | && ! mips_opts.noat | |
8979 | && *args != 'E' | |
af7ee8bf CD |
8980 | && *args != 'G' |
8981 | && *args != 'K') | |
252b5132 RH |
8982 | as_warn (_("Used $at without \".set noat\"")); |
8983 | c = *args; | |
8984 | if (*s == ' ') | |
f9419b05 | 8985 | ++s; |
252b5132 RH |
8986 | if (args[1] != *s) |
8987 | { | |
8988 | if (c == 'r' || c == 'v' || c == 'w') | |
8989 | { | |
8990 | regno = lastregno; | |
8991 | s = s_reset; | |
f9419b05 | 8992 | ++args; |
252b5132 RH |
8993 | } |
8994 | } | |
8995 | /* 'z' only matches $0. */ | |
8996 | if (c == 'z' && regno != 0) | |
8997 | break; | |
8998 | ||
bdaaa2e1 KH |
8999 | /* Now that we have assembled one operand, we use the args string |
9000 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9001 | switch (c) |
9002 | { | |
9003 | case 'r': | |
9004 | case 's': | |
9005 | case 'v': | |
9006 | case 'b': | |
38487616 | 9007 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
9008 | break; |
9009 | case 'd': | |
9010 | case 'G': | |
af7ee8bf | 9011 | case 'K': |
38487616 | 9012 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 9013 | break; |
4372b673 | 9014 | case 'U': |
38487616 TS |
9015 | ip->insn_opcode |= regno << OP_SH_RD; |
9016 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 9017 | break; |
252b5132 RH |
9018 | case 'w': |
9019 | case 't': | |
9020 | case 'E': | |
38487616 | 9021 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
9022 | break; |
9023 | case 'x': | |
9024 | /* This case exists because on the r3000 trunc | |
9025 | expands into a macro which requires a gp | |
9026 | register. On the r6000 or r4000 it is | |
9027 | assembled into a single instruction which | |
9028 | ignores the register. Thus the insn version | |
9029 | is MIPS_ISA2 and uses 'x', and the macro | |
9030 | version is MIPS_ISA1 and uses 't'. */ | |
9031 | break; | |
9032 | case 'z': | |
9033 | /* This case is for the div instruction, which | |
9034 | acts differently if the destination argument | |
9035 | is $0. This only matches $0, and is checked | |
9036 | outside the switch. */ | |
9037 | break; | |
9038 | case 'D': | |
9039 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9040 | break; | |
9041 | /* What about all other operands like 'i', which | |
9042 | can be specified in the opcode table? */ | |
9043 | } | |
9044 | lastregno = regno; | |
9045 | continue; | |
9046 | } | |
9047 | notreg: | |
9048 | switch (*args++) | |
9049 | { | |
9050 | case 'r': | |
9051 | case 'v': | |
38487616 | 9052 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
9053 | continue; |
9054 | case 'w': | |
38487616 | 9055 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
9056 | continue; |
9057 | } | |
9058 | break; | |
9059 | ||
deec1734 CD |
9060 | case 'O': /* MDMX alignment immediate constant. */ |
9061 | my_getExpression (&imm_expr, s); | |
9062 | check_absolute_expr (ip, &imm_expr); | |
9063 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
9064 | { | |
9065 | as_warn ("Improper align amount (%ld), using low bits", | |
9066 | (long) imm_expr.X_add_number); | |
9067 | imm_expr.X_add_number &= OP_MASK_ALN; | |
9068 | } | |
9069 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
9070 | imm_expr.X_op = O_absent; | |
9071 | s = expr_end; | |
9072 | continue; | |
9073 | ||
9074 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9075 | if (s[0] != '$') | |
9076 | { | |
9077 | /* MDMX Immediate. */ | |
9078 | my_getExpression (&imm_expr, s); | |
9079 | check_absolute_expr (ip, &imm_expr); | |
9080 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
9081 | { | |
9082 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
9083 | (long) imm_expr.X_add_number); | |
9084 | imm_expr.X_add_number &= OP_MASK_FT; | |
9085 | } | |
9086 | imm_expr.X_add_number &= OP_MASK_FT; | |
9087 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9088 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9089 | else | |
9090 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
9091 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
9092 | imm_expr.X_op = O_absent; | |
9093 | s = expr_end; | |
9094 | continue; | |
9095 | } | |
9096 | /* Not MDMX Immediate. Fall through. */ | |
9097 | case 'X': /* MDMX destination register. */ | |
9098 | case 'Y': /* MDMX source register. */ | |
9099 | case 'Z': /* MDMX target register. */ | |
9100 | is_mdmx = 1; | |
252b5132 RH |
9101 | case 'D': /* floating point destination register */ |
9102 | case 'S': /* floating point source register */ | |
9103 | case 'T': /* floating point target register */ | |
9104 | case 'R': /* floating point source register */ | |
9105 | case 'V': | |
9106 | case 'W': | |
9107 | s_reset = s; | |
deec1734 CD |
9108 | /* Accept $fN for FP and MDMX register numbers, and in |
9109 | addition accept $vN for MDMX register numbers. */ | |
9110 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
9111 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
9112 | && ISDIGIT (s[2]))) | |
252b5132 RH |
9113 | { |
9114 | s += 2; | |
9115 | regno = 0; | |
9116 | do | |
9117 | { | |
9118 | regno *= 10; | |
9119 | regno += *s - '0'; | |
9120 | ++s; | |
9121 | } | |
3882b010 | 9122 | while (ISDIGIT (*s)); |
252b5132 RH |
9123 | |
9124 | if (regno > 31) | |
9125 | as_bad (_("Invalid float register number (%d)"), regno); | |
9126 | ||
9127 | if ((regno & 1) != 0 | |
ca4e0257 | 9128 | && HAVE_32BIT_FPRS |
252b5132 RH |
9129 | && ! (strcmp (str, "mtc1") == 0 |
9130 | || strcmp (str, "mfc1") == 0 | |
9131 | || strcmp (str, "lwc1") == 0 | |
9132 | || strcmp (str, "swc1") == 0 | |
9133 | || strcmp (str, "l.s") == 0 | |
9134 | || strcmp (str, "s.s") == 0)) | |
9135 | as_warn (_("Float register should be even, was %d"), | |
9136 | regno); | |
9137 | ||
9138 | c = *args; | |
9139 | if (*s == ' ') | |
f9419b05 | 9140 | ++s; |
252b5132 RH |
9141 | if (args[1] != *s) |
9142 | { | |
9143 | if (c == 'V' || c == 'W') | |
9144 | { | |
9145 | regno = lastregno; | |
9146 | s = s_reset; | |
f9419b05 | 9147 | ++args; |
252b5132 RH |
9148 | } |
9149 | } | |
9150 | switch (c) | |
9151 | { | |
9152 | case 'D': | |
deec1734 | 9153 | case 'X': |
38487616 | 9154 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
9155 | break; |
9156 | case 'V': | |
9157 | case 'S': | |
deec1734 | 9158 | case 'Y': |
38487616 | 9159 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 9160 | break; |
deec1734 CD |
9161 | case 'Q': |
9162 | /* This is like 'Z', but also needs to fix the MDMX | |
9163 | vector/scalar select bits. Note that the | |
9164 | scalar immediate case is handled above. */ | |
9165 | if (*s == '[') | |
9166 | { | |
9167 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9168 | int max_el = (is_qh ? 3 : 7); | |
9169 | s++; | |
9170 | my_getExpression(&imm_expr, s); | |
9171 | check_absolute_expr (ip, &imm_expr); | |
9172 | s = expr_end; | |
9173 | if (imm_expr.X_add_number > max_el) | |
9174 | as_bad(_("Bad element selector %ld"), | |
9175 | (long) imm_expr.X_add_number); | |
9176 | imm_expr.X_add_number &= max_el; | |
9177 | ip->insn_opcode |= (imm_expr.X_add_number | |
9178 | << (OP_SH_VSEL + | |
9179 | (is_qh ? 2 : 1))); | |
9180 | if (*s != ']') | |
9181 | as_warn(_("Expecting ']' found '%s'"), s); | |
9182 | else | |
9183 | s++; | |
9184 | } | |
9185 | else | |
9186 | { | |
9187 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9188 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9189 | << OP_SH_VSEL); | |
9190 | else | |
9191 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9192 | OP_SH_VSEL); | |
9193 | } | |
9194 | /* Fall through */ | |
252b5132 RH |
9195 | case 'W': |
9196 | case 'T': | |
deec1734 | 9197 | case 'Z': |
38487616 | 9198 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
9199 | break; |
9200 | case 'R': | |
38487616 | 9201 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
9202 | break; |
9203 | } | |
9204 | lastregno = regno; | |
9205 | continue; | |
9206 | } | |
9207 | ||
252b5132 RH |
9208 | switch (*args++) |
9209 | { | |
9210 | case 'V': | |
38487616 | 9211 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
9212 | continue; |
9213 | case 'W': | |
38487616 | 9214 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
9215 | continue; |
9216 | } | |
9217 | break; | |
9218 | ||
9219 | case 'I': | |
9220 | my_getExpression (&imm_expr, s); | |
9221 | if (imm_expr.X_op != O_big | |
9222 | && imm_expr.X_op != O_constant) | |
9223 | insn_error = _("absolute expression required"); | |
9224 | s = expr_end; | |
9225 | continue; | |
9226 | ||
9227 | case 'A': | |
9228 | my_getExpression (&offset_expr, s); | |
f6688943 | 9229 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9230 | s = expr_end; |
9231 | continue; | |
9232 | ||
9233 | case 'F': | |
9234 | case 'L': | |
9235 | case 'f': | |
9236 | case 'l': | |
9237 | { | |
9238 | int f64; | |
ca4e0257 | 9239 | int using_gprs; |
252b5132 RH |
9240 | char *save_in; |
9241 | char *err; | |
9242 | unsigned char temp[8]; | |
9243 | int len; | |
9244 | unsigned int length; | |
9245 | segT seg; | |
9246 | subsegT subseg; | |
9247 | char *p; | |
9248 | ||
9249 | /* These only appear as the last operand in an | |
9250 | instruction, and every instruction that accepts | |
9251 | them in any variant accepts them in all variants. | |
9252 | This means we don't have to worry about backing out | |
9253 | any changes if the instruction does not match. | |
9254 | ||
9255 | The difference between them is the size of the | |
9256 | floating point constant and where it goes. For 'F' | |
9257 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9258 | is 32 bits. Where the constant is placed is based | |
9259 | on how the MIPS assembler does things: | |
9260 | F -- .rdata | |
9261 | L -- .lit8 | |
9262 | f -- immediate value | |
9263 | l -- .lit4 | |
9264 | ||
9265 | The .lit4 and .lit8 sections are only used if | |
9266 | permitted by the -G argument. | |
9267 | ||
9268 | When generating embedded PIC code, we use the | |
9269 | .lit8 section but not the .lit4 section (we can do | |
9270 | .lit4 inline easily; we need to put .lit8 | |
9271 | somewhere in the data segment, and using .lit8 | |
9272 | permits the linker to eventually combine identical | |
ca4e0257 RS |
9273 | .lit8 entries). |
9274 | ||
9275 | The code below needs to know whether the target register | |
9276 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9277 | 'F' are used with GPR-based instructions and 'l' and | |
9278 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9279 | |
9280 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9281 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9282 | |
9283 | save_in = input_line_pointer; | |
9284 | input_line_pointer = s; | |
9285 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9286 | length = len; | |
9287 | s = input_line_pointer; | |
9288 | input_line_pointer = save_in; | |
9289 | if (err != NULL && *err != '\0') | |
9290 | { | |
9291 | as_bad (_("Bad floating point constant: %s"), err); | |
9292 | memset (temp, '\0', sizeof temp); | |
9293 | length = f64 ? 8 : 4; | |
9294 | } | |
9295 | ||
156c2f8b | 9296 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9297 | |
9298 | if (*args == 'f' | |
9299 | || (*args == 'l' | |
9300 | && (! USE_GLOBAL_POINTER_OPT | |
9301 | || mips_pic == EMBEDDED_PIC | |
9302 | || g_switch_value < 4 | |
9303 | || (temp[0] == 0 && temp[1] == 0) | |
9304 | || (temp[2] == 0 && temp[3] == 0)))) | |
9305 | { | |
9306 | imm_expr.X_op = O_constant; | |
9307 | if (! target_big_endian) | |
9308 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9309 | else | |
9310 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9311 | } | |
9312 | else if (length > 4 | |
119d663a | 9313 | && ! mips_disable_float_construction |
ca4e0257 RS |
9314 | /* Constants can only be constructed in GPRs and |
9315 | copied to FPRs if the GPRs are at least as wide | |
9316 | as the FPRs. Force the constant into memory if | |
9317 | we are using 64-bit FPRs but the GPRs are only | |
9318 | 32 bits wide. */ | |
9319 | && (using_gprs | |
9320 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9321 | && ((temp[0] == 0 && temp[1] == 0) |
9322 | || (temp[2] == 0 && temp[3] == 0)) | |
9323 | && ((temp[4] == 0 && temp[5] == 0) | |
9324 | || (temp[6] == 0 && temp[7] == 0))) | |
9325 | { | |
ca4e0257 RS |
9326 | /* The value is simple enough to load with a couple of |
9327 | instructions. If using 32-bit registers, set | |
9328 | imm_expr to the high order 32 bits and offset_expr to | |
9329 | the low order 32 bits. Otherwise, set imm_expr to | |
9330 | the entire 64 bit constant. */ | |
9331 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9332 | { |
9333 | imm_expr.X_op = O_constant; | |
9334 | offset_expr.X_op = O_constant; | |
9335 | if (! target_big_endian) | |
9336 | { | |
9337 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9338 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9339 | } | |
9340 | else | |
9341 | { | |
9342 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9343 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9344 | } | |
9345 | if (offset_expr.X_add_number == 0) | |
9346 | offset_expr.X_op = O_absent; | |
9347 | } | |
9348 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9349 | { | |
9350 | imm_expr.X_op = O_constant; | |
9351 | if (! target_big_endian) | |
9352 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9353 | else | |
9354 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9355 | } | |
9356 | else | |
9357 | { | |
9358 | imm_expr.X_op = O_big; | |
9359 | imm_expr.X_add_number = 4; | |
9360 | if (! target_big_endian) | |
9361 | { | |
9362 | generic_bignum[0] = bfd_getl16 (temp); | |
9363 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9364 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9365 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9366 | } | |
9367 | else | |
9368 | { | |
9369 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9370 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9371 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9372 | generic_bignum[3] = bfd_getb16 (temp); | |
9373 | } | |
9374 | } | |
9375 | } | |
9376 | else | |
9377 | { | |
9378 | const char *newname; | |
9379 | segT new_seg; | |
9380 | ||
9381 | /* Switch to the right section. */ | |
9382 | seg = now_seg; | |
9383 | subseg = now_subseg; | |
9384 | switch (*args) | |
9385 | { | |
9386 | default: /* unused default case avoids warnings. */ | |
9387 | case 'L': | |
9388 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
9389 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
9390 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
9391 | newname = ".lit8"; |
9392 | break; | |
9393 | case 'F': | |
bb2d6cd7 GK |
9394 | if (mips_pic == EMBEDDED_PIC) |
9395 | newname = ".lit8"; | |
9396 | else | |
9397 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
9398 | break; |
9399 | case 'l': | |
9400 | assert (!USE_GLOBAL_POINTER_OPT | |
9401 | || g_switch_value >= 4); | |
9402 | newname = ".lit4"; | |
9403 | break; | |
9404 | } | |
9405 | new_seg = subseg_new (newname, (subsegT) 0); | |
9406 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9407 | bfd_set_section_flags (stdoutput, new_seg, | |
9408 | (SEC_ALLOC | |
9409 | | SEC_LOAD | |
9410 | | SEC_READONLY | |
9411 | | SEC_DATA)); | |
9412 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9413 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9414 | && strcmp (TARGET_OS, "elf") != 0) | |
9415 | record_alignment (new_seg, 4); | |
9416 | else | |
9417 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9418 | if (seg == now_seg) | |
9419 | as_bad (_("Can't use floating point insn in this section")); | |
9420 | ||
9421 | /* Set the argument to the current address in the | |
9422 | section. */ | |
9423 | offset_expr.X_op = O_symbol; | |
9424 | offset_expr.X_add_symbol = | |
9425 | symbol_new ("L0\001", now_seg, | |
9426 | (valueT) frag_now_fix (), frag_now); | |
9427 | offset_expr.X_add_number = 0; | |
9428 | ||
9429 | /* Put the floating point number into the section. */ | |
9430 | p = frag_more ((int) length); | |
9431 | memcpy (p, temp, length); | |
9432 | ||
9433 | /* Switch back to the original section. */ | |
9434 | subseg_set (seg, subseg); | |
9435 | } | |
9436 | } | |
9437 | continue; | |
9438 | ||
9439 | case 'i': /* 16 bit unsigned immediate */ | |
9440 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9441 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9442 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9443 | { |
9444 | int more; | |
5e0116d5 RS |
9445 | offsetT minval, maxval; |
9446 | ||
9447 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9448 | && strcmp (insn->name, insn[1].name) == 0); | |
9449 | ||
9450 | /* If the expression was written as an unsigned number, | |
9451 | only treat it as signed if there are no more | |
9452 | alternatives. */ | |
9453 | if (more | |
9454 | && *args == 'j' | |
9455 | && sizeof (imm_expr.X_add_number) <= 4 | |
9456 | && imm_expr.X_op == O_constant | |
9457 | && imm_expr.X_add_number < 0 | |
9458 | && imm_expr.X_unsigned | |
9459 | && HAVE_64BIT_GPRS) | |
9460 | break; | |
9461 | ||
9462 | /* For compatibility with older assemblers, we accept | |
9463 | 0x8000-0xffff as signed 16-bit numbers when only | |
9464 | signed numbers are allowed. */ | |
9465 | if (*args == 'i') | |
9466 | minval = 0, maxval = 0xffff; | |
9467 | else if (more) | |
9468 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9469 | else |
5e0116d5 RS |
9470 | minval = -0x8000, maxval = 0xffff; |
9471 | ||
9472 | if (imm_expr.X_op != O_constant | |
9473 | || imm_expr.X_add_number < minval | |
9474 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9475 | { |
9476 | if (more) | |
9477 | break; | |
2ae7e77b AH |
9478 | if (imm_expr.X_op == O_constant |
9479 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9480 | as_bad (_("expression out of range")); |
252b5132 RH |
9481 | } |
9482 | } | |
9483 | s = expr_end; | |
9484 | continue; | |
9485 | ||
9486 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9487 | /* Check whether there is only a single bracketed expression |
9488 | left. If so, it must be the base register and the | |
9489 | constant must be zero. */ | |
9490 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9491 | { | |
9492 | offset_expr.X_op = O_constant; | |
9493 | offset_expr.X_add_number = 0; | |
9494 | continue; | |
9495 | } | |
252b5132 RH |
9496 | |
9497 | /* If this value won't fit into a 16 bit offset, then go | |
9498 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9499 | code pattern. */ |
5e0116d5 | 9500 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9501 | && (offset_expr.X_op != O_constant |
9502 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9503 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9504 | break; |
9505 | ||
252b5132 RH |
9506 | s = expr_end; |
9507 | continue; | |
9508 | ||
9509 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9510 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9511 | my_getExpression (&offset_expr, s); |
9512 | s = expr_end; | |
9513 | continue; | |
9514 | ||
9515 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9516 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9517 | && imm_expr.X_op == O_constant | |
9518 | && (imm_expr.X_add_number < 0 | |
9519 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9520 | as_bad (_("lui expression not in range 0..65535")); |
9521 | s = expr_end; | |
9522 | continue; | |
9523 | ||
9524 | case 'a': /* 26 bit address */ | |
9525 | my_getExpression (&offset_expr, s); | |
9526 | s = expr_end; | |
f6688943 | 9527 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9528 | continue; |
9529 | ||
9530 | case 'N': /* 3 bit branch condition code */ | |
9531 | case 'M': /* 3 bit compare condition code */ | |
9532 | if (strncmp (s, "$fcc", 4) != 0) | |
9533 | break; | |
9534 | s += 4; | |
9535 | regno = 0; | |
9536 | do | |
9537 | { | |
9538 | regno *= 10; | |
9539 | regno += *s - '0'; | |
9540 | ++s; | |
9541 | } | |
3882b010 | 9542 | while (ISDIGIT (*s)); |
252b5132 RH |
9543 | if (regno > 7) |
9544 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
9545 | if (*args == 'N') | |
9546 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9547 | else | |
9548 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9549 | continue; |
252b5132 | 9550 | |
156c2f8b NC |
9551 | case 'H': |
9552 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9553 | s += 2; | |
3882b010 | 9554 | if (ISDIGIT (*s)) |
156c2f8b NC |
9555 | { |
9556 | c = 0; | |
9557 | do | |
9558 | { | |
9559 | c *= 10; | |
9560 | c += *s - '0'; | |
9561 | ++s; | |
9562 | } | |
3882b010 | 9563 | while (ISDIGIT (*s)); |
156c2f8b NC |
9564 | } |
9565 | else | |
9566 | c = 8; /* Invalid sel value. */ | |
9567 | ||
9568 | if (c > 7) | |
9569 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9570 | ip->insn_opcode |= c; | |
9571 | continue; | |
9572 | ||
60b63b72 RS |
9573 | case 'e': |
9574 | /* Must be at least one digit. */ | |
9575 | my_getExpression (&imm_expr, s); | |
9576 | check_absolute_expr (ip, &imm_expr); | |
9577 | ||
9578 | if ((unsigned long) imm_expr.X_add_number | |
9579 | > (unsigned long) OP_MASK_VECBYTE) | |
9580 | { | |
9581 | as_bad (_("bad byte vector index (%ld)"), | |
9582 | (long) imm_expr.X_add_number); | |
9583 | imm_expr.X_add_number = 0; | |
9584 | } | |
9585 | ||
9586 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9587 | imm_expr.X_op = O_absent; | |
9588 | s = expr_end; | |
9589 | continue; | |
9590 | ||
9591 | case '%': | |
9592 | my_getExpression (&imm_expr, s); | |
9593 | check_absolute_expr (ip, &imm_expr); | |
9594 | ||
9595 | if ((unsigned long) imm_expr.X_add_number | |
9596 | > (unsigned long) OP_MASK_VECALIGN) | |
9597 | { | |
9598 | as_bad (_("bad byte vector index (%ld)"), | |
9599 | (long) imm_expr.X_add_number); | |
9600 | imm_expr.X_add_number = 0; | |
9601 | } | |
9602 | ||
9603 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9604 | imm_expr.X_op = O_absent; | |
9605 | s = expr_end; | |
9606 | continue; | |
9607 | ||
252b5132 RH |
9608 | default: |
9609 | as_bad (_("bad char = '%c'\n"), *args); | |
9610 | internalError (); | |
9611 | } | |
9612 | break; | |
9613 | } | |
9614 | /* Args don't match. */ | |
9615 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9616 | !strcmp (insn->name, insn[1].name)) | |
9617 | { | |
9618 | ++insn; | |
9619 | s = argsStart; | |
268f6bed | 9620 | insn_error = _("illegal operands"); |
252b5132 RH |
9621 | continue; |
9622 | } | |
268f6bed L |
9623 | if (save_c) |
9624 | *(--s) = save_c; | |
252b5132 RH |
9625 | insn_error = _("illegal operands"); |
9626 | return; | |
9627 | } | |
9628 | } | |
9629 | ||
9630 | /* This routine assembles an instruction into its binary format when | |
9631 | assembling for the mips16. As a side effect, it sets one of the | |
9632 | global variables imm_reloc or offset_reloc to the type of | |
9633 | relocation to do if one of the operands is an address expression. | |
9634 | It also sets mips16_small and mips16_ext if the user explicitly | |
9635 | requested a small or extended instruction. */ | |
9636 | ||
9637 | static void | |
9638 | mips16_ip (str, ip) | |
9639 | char *str; | |
9640 | struct mips_cl_insn *ip; | |
9641 | { | |
9642 | char *s; | |
9643 | const char *args; | |
9644 | struct mips_opcode *insn; | |
9645 | char *argsstart; | |
9646 | unsigned int regno; | |
9647 | unsigned int lastregno = 0; | |
9648 | char *s_reset; | |
9649 | ||
9650 | insn_error = NULL; | |
9651 | ||
b34976b6 AM |
9652 | mips16_small = FALSE; |
9653 | mips16_ext = FALSE; | |
252b5132 | 9654 | |
3882b010 | 9655 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9656 | ; |
9657 | switch (*s) | |
9658 | { | |
9659 | case '\0': | |
9660 | break; | |
9661 | ||
9662 | case ' ': | |
9663 | *s++ = '\0'; | |
9664 | break; | |
9665 | ||
9666 | case '.': | |
9667 | if (s[1] == 't' && s[2] == ' ') | |
9668 | { | |
9669 | *s = '\0'; | |
b34976b6 | 9670 | mips16_small = TRUE; |
252b5132 RH |
9671 | s += 3; |
9672 | break; | |
9673 | } | |
9674 | else if (s[1] == 'e' && s[2] == ' ') | |
9675 | { | |
9676 | *s = '\0'; | |
b34976b6 | 9677 | mips16_ext = TRUE; |
252b5132 RH |
9678 | s += 3; |
9679 | break; | |
9680 | } | |
9681 | /* Fall through. */ | |
9682 | default: | |
9683 | insn_error = _("unknown opcode"); | |
9684 | return; | |
9685 | } | |
9686 | ||
9687 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9688 | mips16_small = TRUE; |
252b5132 RH |
9689 | |
9690 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9691 | { | |
9692 | insn_error = _("unrecognized opcode"); | |
9693 | return; | |
9694 | } | |
9695 | ||
9696 | argsstart = s; | |
9697 | for (;;) | |
9698 | { | |
9699 | assert (strcmp (insn->name, str) == 0); | |
9700 | ||
9701 | ip->insn_mo = insn; | |
9702 | ip->insn_opcode = insn->match; | |
b34976b6 | 9703 | ip->use_extend = FALSE; |
252b5132 | 9704 | imm_expr.X_op = O_absent; |
f6688943 TS |
9705 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9706 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9707 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 9708 | offset_expr.X_op = O_absent; |
f6688943 TS |
9709 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9710 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9711 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9712 | for (args = insn->args; 1; ++args) |
9713 | { | |
9714 | int c; | |
9715 | ||
9716 | if (*s == ' ') | |
9717 | ++s; | |
9718 | ||
9719 | /* In this switch statement we call break if we did not find | |
9720 | a match, continue if we did find a match, or return if we | |
9721 | are done. */ | |
9722 | ||
9723 | c = *args; | |
9724 | switch (c) | |
9725 | { | |
9726 | case '\0': | |
9727 | if (*s == '\0') | |
9728 | { | |
9729 | /* Stuff the immediate value in now, if we can. */ | |
9730 | if (imm_expr.X_op == O_constant | |
f6688943 | 9731 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9732 | && insn->pinfo != INSN_MACRO) |
9733 | { | |
c4e7957c | 9734 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9735 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9736 | mips16_ext, &ip->insn_opcode, |
9737 | &ip->use_extend, &ip->extend); | |
9738 | imm_expr.X_op = O_absent; | |
f6688943 | 9739 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9740 | } |
9741 | ||
9742 | return; | |
9743 | } | |
9744 | break; | |
9745 | ||
9746 | case ',': | |
9747 | if (*s++ == c) | |
9748 | continue; | |
9749 | s--; | |
9750 | switch (*++args) | |
9751 | { | |
9752 | case 'v': | |
9753 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9754 | continue; | |
9755 | case 'w': | |
9756 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9757 | continue; | |
9758 | } | |
9759 | break; | |
9760 | ||
9761 | case '(': | |
9762 | case ')': | |
9763 | if (*s++ == c) | |
9764 | continue; | |
9765 | break; | |
9766 | ||
9767 | case 'v': | |
9768 | case 'w': | |
9769 | if (s[0] != '$') | |
9770 | { | |
9771 | if (c == 'v') | |
9772 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9773 | else | |
9774 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9775 | ++args; | |
9776 | continue; | |
9777 | } | |
9778 | /* Fall through. */ | |
9779 | case 'x': | |
9780 | case 'y': | |
9781 | case 'z': | |
9782 | case 'Z': | |
9783 | case '0': | |
9784 | case 'S': | |
9785 | case 'R': | |
9786 | case 'X': | |
9787 | case 'Y': | |
9788 | if (s[0] != '$') | |
9789 | break; | |
9790 | s_reset = s; | |
3882b010 | 9791 | if (ISDIGIT (s[1])) |
252b5132 RH |
9792 | { |
9793 | ++s; | |
9794 | regno = 0; | |
9795 | do | |
9796 | { | |
9797 | regno *= 10; | |
9798 | regno += *s - '0'; | |
9799 | ++s; | |
9800 | } | |
3882b010 | 9801 | while (ISDIGIT (*s)); |
252b5132 RH |
9802 | if (regno > 31) |
9803 | { | |
9804 | as_bad (_("invalid register number (%d)"), regno); | |
9805 | regno = 2; | |
9806 | } | |
9807 | } | |
9808 | else | |
9809 | { | |
76db943d TS |
9810 | if (s[1] == 'r' && s[2] == 'a') |
9811 | { | |
9812 | s += 3; | |
9813 | regno = RA; | |
9814 | } | |
9815 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9816 | { |
9817 | s += 3; | |
9818 | regno = FP; | |
9819 | } | |
9820 | else if (s[1] == 's' && s[2] == 'p') | |
9821 | { | |
9822 | s += 3; | |
9823 | regno = SP; | |
9824 | } | |
9825 | else if (s[1] == 'g' && s[2] == 'p') | |
9826 | { | |
9827 | s += 3; | |
9828 | regno = GP; | |
9829 | } | |
9830 | else if (s[1] == 'a' && s[2] == 't') | |
9831 | { | |
9832 | s += 3; | |
9833 | regno = AT; | |
9834 | } | |
9835 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9836 | { | |
9837 | s += 4; | |
9838 | regno = KT0; | |
9839 | } | |
9840 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9841 | { | |
9842 | s += 4; | |
9843 | regno = KT1; | |
9844 | } | |
85b51719 TS |
9845 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9846 | { | |
9847 | s += 5; | |
9848 | regno = ZERO; | |
9849 | } | |
252b5132 RH |
9850 | else |
9851 | break; | |
9852 | } | |
9853 | ||
9854 | if (*s == ' ') | |
9855 | ++s; | |
9856 | if (args[1] != *s) | |
9857 | { | |
9858 | if (c == 'v' || c == 'w') | |
9859 | { | |
9860 | regno = mips16_to_32_reg_map[lastregno]; | |
9861 | s = s_reset; | |
f9419b05 | 9862 | ++args; |
252b5132 RH |
9863 | } |
9864 | } | |
9865 | ||
9866 | switch (c) | |
9867 | { | |
9868 | case 'x': | |
9869 | case 'y': | |
9870 | case 'z': | |
9871 | case 'v': | |
9872 | case 'w': | |
9873 | case 'Z': | |
9874 | regno = mips32_to_16_reg_map[regno]; | |
9875 | break; | |
9876 | ||
9877 | case '0': | |
9878 | if (regno != 0) | |
9879 | regno = ILLEGAL_REG; | |
9880 | break; | |
9881 | ||
9882 | case 'S': | |
9883 | if (regno != SP) | |
9884 | regno = ILLEGAL_REG; | |
9885 | break; | |
9886 | ||
9887 | case 'R': | |
9888 | if (regno != RA) | |
9889 | regno = ILLEGAL_REG; | |
9890 | break; | |
9891 | ||
9892 | case 'X': | |
9893 | case 'Y': | |
9894 | if (regno == AT && ! mips_opts.noat) | |
9895 | as_warn (_("used $at without \".set noat\"")); | |
9896 | break; | |
9897 | ||
9898 | default: | |
9899 | internalError (); | |
9900 | } | |
9901 | ||
9902 | if (regno == ILLEGAL_REG) | |
9903 | break; | |
9904 | ||
9905 | switch (c) | |
9906 | { | |
9907 | case 'x': | |
9908 | case 'v': | |
9909 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9910 | break; | |
9911 | case 'y': | |
9912 | case 'w': | |
9913 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9914 | break; | |
9915 | case 'z': | |
9916 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9917 | break; | |
9918 | case 'Z': | |
9919 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9920 | case '0': | |
9921 | case 'S': | |
9922 | case 'R': | |
9923 | break; | |
9924 | case 'X': | |
9925 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9926 | break; | |
9927 | case 'Y': | |
9928 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9929 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9930 | break; | |
9931 | default: | |
9932 | internalError (); | |
9933 | } | |
9934 | ||
9935 | lastregno = regno; | |
9936 | continue; | |
9937 | ||
9938 | case 'P': | |
9939 | if (strncmp (s, "$pc", 3) == 0) | |
9940 | { | |
9941 | s += 3; | |
9942 | continue; | |
9943 | } | |
9944 | break; | |
9945 | ||
9946 | case '<': | |
9947 | case '>': | |
9948 | case '[': | |
9949 | case ']': | |
9950 | case '4': | |
9951 | case '5': | |
9952 | case 'H': | |
9953 | case 'W': | |
9954 | case 'D': | |
9955 | case 'j': | |
9956 | case '8': | |
9957 | case 'V': | |
9958 | case 'C': | |
9959 | case 'U': | |
9960 | case 'k': | |
9961 | case 'K': | |
9962 | if (s[0] == '%' | |
9963 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9964 | { | |
9965 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9966 | and generate the appropriate reloc. If the text | |
9967 | inside %gprel is not a symbol name with an | |
9968 | optional offset, then we generate a normal reloc | |
9969 | and will probably fail later. */ | |
9970 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9971 | if (imm_expr.X_op == O_symbol) | |
9972 | { | |
b34976b6 | 9973 | mips16_ext = TRUE; |
f6688943 | 9974 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9975 | s = expr_end; |
b34976b6 | 9976 | ip->use_extend = TRUE; |
252b5132 RH |
9977 | ip->extend = 0; |
9978 | continue; | |
9979 | } | |
9980 | } | |
9981 | else | |
9982 | { | |
9983 | /* Just pick up a normal expression. */ | |
9984 | my_getExpression (&imm_expr, s); | |
9985 | } | |
9986 | ||
9987 | if (imm_expr.X_op == O_register) | |
9988 | { | |
9989 | /* What we thought was an expression turned out to | |
9990 | be a register. */ | |
9991 | ||
9992 | if (s[0] == '(' && args[1] == '(') | |
9993 | { | |
9994 | /* It looks like the expression was omitted | |
9995 | before a register indirection, which means | |
9996 | that the expression is implicitly zero. We | |
9997 | still set up imm_expr, so that we handle | |
9998 | explicit extensions correctly. */ | |
9999 | imm_expr.X_op = O_constant; | |
10000 | imm_expr.X_add_number = 0; | |
f6688943 | 10001 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10002 | continue; |
10003 | } | |
10004 | ||
10005 | break; | |
10006 | } | |
10007 | ||
10008 | /* We need to relax this instruction. */ | |
f6688943 | 10009 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10010 | s = expr_end; |
10011 | continue; | |
10012 | ||
10013 | case 'p': | |
10014 | case 'q': | |
10015 | case 'A': | |
10016 | case 'B': | |
10017 | case 'E': | |
10018 | /* We use offset_reloc rather than imm_reloc for the PC | |
10019 | relative operands. This lets macros with both | |
10020 | immediate and address operands work correctly. */ | |
10021 | my_getExpression (&offset_expr, s); | |
10022 | ||
10023 | if (offset_expr.X_op == O_register) | |
10024 | break; | |
10025 | ||
10026 | /* We need to relax this instruction. */ | |
f6688943 | 10027 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10028 | s = expr_end; |
10029 | continue; | |
10030 | ||
10031 | case '6': /* break code */ | |
10032 | my_getExpression (&imm_expr, s); | |
10033 | check_absolute_expr (ip, &imm_expr); | |
10034 | if ((unsigned long) imm_expr.X_add_number > 63) | |
10035 | { | |
10036 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10037 | ip->insn_mo->name, | |
10038 | (unsigned long) imm_expr.X_add_number); | |
10039 | imm_expr.X_add_number &= 0x3f; | |
10040 | } | |
10041 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
10042 | imm_expr.X_op = O_absent; | |
10043 | s = expr_end; | |
10044 | continue; | |
10045 | ||
10046 | case 'a': /* 26 bit address */ | |
10047 | my_getExpression (&offset_expr, s); | |
10048 | s = expr_end; | |
f6688943 | 10049 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10050 | ip->insn_opcode <<= 16; |
10051 | continue; | |
10052 | ||
10053 | case 'l': /* register list for entry macro */ | |
10054 | case 'L': /* register list for exit macro */ | |
10055 | { | |
10056 | int mask; | |
10057 | ||
10058 | if (c == 'l') | |
10059 | mask = 0; | |
10060 | else | |
10061 | mask = 7 << 3; | |
10062 | while (*s != '\0') | |
10063 | { | |
10064 | int freg, reg1, reg2; | |
10065 | ||
10066 | while (*s == ' ' || *s == ',') | |
10067 | ++s; | |
10068 | if (*s != '$') | |
10069 | { | |
10070 | as_bad (_("can't parse register list")); | |
10071 | break; | |
10072 | } | |
10073 | ++s; | |
10074 | if (*s != 'f') | |
10075 | freg = 0; | |
10076 | else | |
10077 | { | |
10078 | freg = 1; | |
10079 | ++s; | |
10080 | } | |
10081 | reg1 = 0; | |
3882b010 | 10082 | while (ISDIGIT (*s)) |
252b5132 RH |
10083 | { |
10084 | reg1 *= 10; | |
10085 | reg1 += *s - '0'; | |
10086 | ++s; | |
10087 | } | |
10088 | if (*s == ' ') | |
10089 | ++s; | |
10090 | if (*s != '-') | |
10091 | reg2 = reg1; | |
10092 | else | |
10093 | { | |
10094 | ++s; | |
10095 | if (*s != '$') | |
10096 | break; | |
10097 | ++s; | |
10098 | if (freg) | |
10099 | { | |
10100 | if (*s == 'f') | |
10101 | ++s; | |
10102 | else | |
10103 | { | |
10104 | as_bad (_("invalid register list")); | |
10105 | break; | |
10106 | } | |
10107 | } | |
10108 | reg2 = 0; | |
3882b010 | 10109 | while (ISDIGIT (*s)) |
252b5132 RH |
10110 | { |
10111 | reg2 *= 10; | |
10112 | reg2 += *s - '0'; | |
10113 | ++s; | |
10114 | } | |
10115 | } | |
10116 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10117 | { | |
10118 | mask &= ~ (7 << 3); | |
10119 | mask |= 5 << 3; | |
10120 | } | |
10121 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10122 | { | |
10123 | mask &= ~ (7 << 3); | |
10124 | mask |= 6 << 3; | |
10125 | } | |
10126 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10127 | mask |= (reg2 - 3) << 3; | |
10128 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10129 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10130 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10131 | mask |= 1; |
10132 | else | |
10133 | { | |
10134 | as_bad (_("invalid register list")); | |
10135 | break; | |
10136 | } | |
10137 | } | |
10138 | /* The mask is filled in in the opcode table for the | |
10139 | benefit of the disassembler. We remove it before | |
10140 | applying the actual mask. */ | |
10141 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10142 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10143 | } | |
10144 | continue; | |
10145 | ||
10146 | case 'e': /* extend code */ | |
10147 | my_getExpression (&imm_expr, s); | |
10148 | check_absolute_expr (ip, &imm_expr); | |
10149 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10150 | { | |
10151 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10152 | ip->insn_mo->name, | |
10153 | (unsigned long) imm_expr.X_add_number); | |
10154 | imm_expr.X_add_number &= 0x7ff; | |
10155 | } | |
10156 | ip->insn_opcode |= imm_expr.X_add_number; | |
10157 | imm_expr.X_op = O_absent; | |
10158 | s = expr_end; | |
10159 | continue; | |
10160 | ||
10161 | default: | |
10162 | internalError (); | |
10163 | } | |
10164 | break; | |
10165 | } | |
10166 | ||
10167 | /* Args don't match. */ | |
10168 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10169 | strcmp (insn->name, insn[1].name) == 0) | |
10170 | { | |
10171 | ++insn; | |
10172 | s = argsstart; | |
10173 | continue; | |
10174 | } | |
10175 | ||
10176 | insn_error = _("illegal operands"); | |
10177 | ||
10178 | return; | |
10179 | } | |
10180 | } | |
10181 | ||
10182 | /* This structure holds information we know about a mips16 immediate | |
10183 | argument type. */ | |
10184 | ||
e972090a NC |
10185 | struct mips16_immed_operand |
10186 | { | |
252b5132 RH |
10187 | /* The type code used in the argument string in the opcode table. */ |
10188 | int type; | |
10189 | /* The number of bits in the short form of the opcode. */ | |
10190 | int nbits; | |
10191 | /* The number of bits in the extended form of the opcode. */ | |
10192 | int extbits; | |
10193 | /* The amount by which the short form is shifted when it is used; | |
10194 | for example, the sw instruction has a shift count of 2. */ | |
10195 | int shift; | |
10196 | /* The amount by which the short form is shifted when it is stored | |
10197 | into the instruction code. */ | |
10198 | int op_shift; | |
10199 | /* Non-zero if the short form is unsigned. */ | |
10200 | int unsp; | |
10201 | /* Non-zero if the extended form is unsigned. */ | |
10202 | int extu; | |
10203 | /* Non-zero if the value is PC relative. */ | |
10204 | int pcrel; | |
10205 | }; | |
10206 | ||
10207 | /* The mips16 immediate operand types. */ | |
10208 | ||
10209 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10210 | { | |
10211 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10212 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10213 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10214 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10215 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10216 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10217 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10218 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10219 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10220 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10221 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10222 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10223 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10224 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10225 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10226 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10227 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10228 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10229 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10230 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10231 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10232 | }; | |
10233 | ||
10234 | #define MIPS16_NUM_IMMED \ | |
10235 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10236 | ||
10237 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10238 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10239 | whether an extended value is needed; if one is needed, it sets | |
10240 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10241 | If SMALL is true, an unextended opcode was explicitly requested. | |
10242 | If EXT is true, an extended opcode was explicitly requested. If | |
10243 | WARN is true, warn if EXT does not match reality. */ | |
10244 | ||
10245 | static void | |
10246 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
10247 | extend) | |
10248 | char *file; | |
10249 | unsigned int line; | |
10250 | int type; | |
10251 | offsetT val; | |
b34976b6 AM |
10252 | bfd_boolean warn; |
10253 | bfd_boolean small; | |
10254 | bfd_boolean ext; | |
252b5132 | 10255 | unsigned long *insn; |
b34976b6 | 10256 | bfd_boolean *use_extend; |
252b5132 RH |
10257 | unsigned short *extend; |
10258 | { | |
10259 | register const struct mips16_immed_operand *op; | |
10260 | int mintiny, maxtiny; | |
b34976b6 | 10261 | bfd_boolean needext; |
252b5132 RH |
10262 | |
10263 | op = mips16_immed_operands; | |
10264 | while (op->type != type) | |
10265 | { | |
10266 | ++op; | |
10267 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10268 | } | |
10269 | ||
10270 | if (op->unsp) | |
10271 | { | |
10272 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10273 | { | |
10274 | mintiny = 1; | |
10275 | maxtiny = 1 << op->nbits; | |
10276 | } | |
10277 | else | |
10278 | { | |
10279 | mintiny = 0; | |
10280 | maxtiny = (1 << op->nbits) - 1; | |
10281 | } | |
10282 | } | |
10283 | else | |
10284 | { | |
10285 | mintiny = - (1 << (op->nbits - 1)); | |
10286 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10287 | } | |
10288 | ||
10289 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10290 | if (type == 'p' || type == 'q') | |
10291 | val /= 2; | |
10292 | ||
10293 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10294 | || val < (mintiny << op->shift) | |
10295 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10296 | needext = TRUE; |
252b5132 | 10297 | else |
b34976b6 | 10298 | needext = FALSE; |
252b5132 RH |
10299 | |
10300 | if (warn && ext && ! needext) | |
beae10d5 KH |
10301 | as_warn_where (file, line, |
10302 | _("extended operand requested but not required")); | |
252b5132 RH |
10303 | if (small && needext) |
10304 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10305 | ||
10306 | if (small || (! ext && ! needext)) | |
10307 | { | |
10308 | int insnval; | |
10309 | ||
b34976b6 | 10310 | *use_extend = FALSE; |
252b5132 RH |
10311 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10312 | insnval <<= op->op_shift; | |
10313 | *insn |= insnval; | |
10314 | } | |
10315 | else | |
10316 | { | |
10317 | long minext, maxext; | |
10318 | int extval; | |
10319 | ||
10320 | if (op->extu) | |
10321 | { | |
10322 | minext = 0; | |
10323 | maxext = (1 << op->extbits) - 1; | |
10324 | } | |
10325 | else | |
10326 | { | |
10327 | minext = - (1 << (op->extbits - 1)); | |
10328 | maxext = (1 << (op->extbits - 1)) - 1; | |
10329 | } | |
10330 | if (val < minext || val > maxext) | |
10331 | as_bad_where (file, line, | |
10332 | _("operand value out of range for instruction")); | |
10333 | ||
b34976b6 | 10334 | *use_extend = TRUE; |
252b5132 RH |
10335 | if (op->extbits == 16) |
10336 | { | |
10337 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10338 | val &= 0x1f; | |
10339 | } | |
10340 | else if (op->extbits == 15) | |
10341 | { | |
10342 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10343 | val &= 0xf; | |
10344 | } | |
10345 | else | |
10346 | { | |
10347 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10348 | val = 0; | |
10349 | } | |
10350 | ||
10351 | *extend = (unsigned short) extval; | |
10352 | *insn |= val; | |
10353 | } | |
10354 | } | |
10355 | \f | |
5e0116d5 | 10356 | static const struct percent_op_match |
ad8d3bb3 | 10357 | { |
5e0116d5 RS |
10358 | const char *str; |
10359 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
10360 | } percent_op[] = |
10361 | { | |
5e0116d5 | 10362 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10363 | #ifdef OBJ_ELF |
5e0116d5 RS |
10364 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10365 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10366 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10367 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10368 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10369 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10370 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10371 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10372 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10373 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10374 | {"%half", BFD_RELOC_16}, | |
10375 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10376 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10377 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 10378 | #endif |
5e0116d5 | 10379 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10380 | }; |
10381 | ||
252b5132 | 10382 | |
5e0116d5 RS |
10383 | /* Return true if *STR points to a relocation operator. When returning true, |
10384 | move *STR over the operator and store its relocation code in *RELOC. | |
10385 | Leave both *STR and *RELOC alone when returning false. */ | |
10386 | ||
10387 | static bfd_boolean | |
10388 | parse_relocation (str, reloc) | |
ad8d3bb3 | 10389 | char **str; |
5e0116d5 | 10390 | bfd_reloc_code_real_type *reloc; |
252b5132 | 10391 | { |
5e0116d5 | 10392 | size_t i; |
76b3015f | 10393 | |
5e0116d5 RS |
10394 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
10395 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 10396 | { |
5e0116d5 RS |
10397 | *str += strlen (percent_op[i].str); |
10398 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10399 | |
5e0116d5 RS |
10400 | /* Check whether the output BFD supports this relocation. |
10401 | If not, issue an error and fall back on something safe. */ | |
10402 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10403 | { |
5e0116d5 RS |
10404 | as_bad ("relocation %s isn't supported by the current ABI", |
10405 | percent_op[i].str); | |
10406 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 10407 | } |
5e0116d5 | 10408 | return TRUE; |
394f9b3a | 10409 | } |
5e0116d5 | 10410 | return FALSE; |
394f9b3a | 10411 | } |
ad8d3bb3 | 10412 | |
ad8d3bb3 | 10413 | |
5e0116d5 RS |
10414 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10415 | expression in *EP and the relocations in the array starting | |
10416 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10417 | |
5e0116d5 RS |
10418 | On exit, EXPR_END points to the first character after the expression. |
10419 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 10420 | |
5e0116d5 RS |
10421 | static size_t |
10422 | my_getSmallExpression (ep, reloc, str) | |
ad8d3bb3 | 10423 | expressionS *ep; |
5e0116d5 | 10424 | bfd_reloc_code_real_type *reloc; |
ad8d3bb3 TS |
10425 | char *str; |
10426 | { | |
5e0116d5 RS |
10427 | bfd_reloc_code_real_type reversed_reloc[3]; |
10428 | size_t reloc_index, i; | |
09b8f35a RS |
10429 | int crux_depth, str_depth; |
10430 | char *crux; | |
5e0116d5 RS |
10431 | |
10432 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10433 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10434 | of the main expression and with CRUX_DEPTH containing the number | |
10435 | of open brackets at that point. */ | |
10436 | reloc_index = -1; | |
10437 | str_depth = 0; | |
10438 | do | |
fb1b3232 | 10439 | { |
09b8f35a RS |
10440 | reloc_index++; |
10441 | crux = str; | |
10442 | crux_depth = str_depth; | |
10443 | ||
10444 | /* Skip over whitespace and brackets, keeping count of the number | |
10445 | of brackets. */ | |
10446 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10447 | if (*str++ == '(') | |
10448 | str_depth++; | |
5e0116d5 | 10449 | } |
09b8f35a RS |
10450 | while (*str == '%' |
10451 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10452 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10453 | |
09b8f35a | 10454 | my_getExpression (ep, crux); |
5e0116d5 | 10455 | str = expr_end; |
394f9b3a | 10456 | |
5e0116d5 | 10457 | /* Match every open bracket. */ |
09b8f35a | 10458 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10459 | if (*str++ == ')') |
09b8f35a | 10460 | crux_depth--; |
394f9b3a | 10461 | |
09b8f35a | 10462 | if (crux_depth > 0) |
5e0116d5 | 10463 | as_bad ("unclosed '('"); |
394f9b3a | 10464 | |
5e0116d5 | 10465 | expr_end = str; |
252b5132 | 10466 | |
64bdfcaf RS |
10467 | if (reloc_index == 0) |
10468 | reloc[0] = BFD_RELOC_LO16; | |
10469 | else | |
10470 | { | |
10471 | prev_reloc_op_frag = frag_now; | |
10472 | for (i = 0; i < reloc_index; i++) | |
10473 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10474 | } | |
fb1b3232 | 10475 | |
5e0116d5 | 10476 | return reloc_index; |
252b5132 RH |
10477 | } |
10478 | ||
10479 | static void | |
10480 | my_getExpression (ep, str) | |
10481 | expressionS *ep; | |
10482 | char *str; | |
10483 | { | |
10484 | char *save_in; | |
98aa84af | 10485 | valueT val; |
252b5132 RH |
10486 | |
10487 | save_in = input_line_pointer; | |
10488 | input_line_pointer = str; | |
10489 | expression (ep); | |
10490 | expr_end = input_line_pointer; | |
10491 | input_line_pointer = save_in; | |
10492 | ||
10493 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10494 | then we bump the value of the symbol by 1 since that is how other | |
10495 | text symbols are handled. We don't bother to handle complex | |
10496 | expressions, just `.' plus or minus a constant. */ | |
10497 | if (mips_opts.mips16 | |
10498 | && ep->X_op == O_symbol | |
10499 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10500 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10501 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10502 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10503 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10504 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10505 | } |
10506 | ||
10507 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10508 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10509 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10510 | returned, or NULL on OK. */ |
10511 | ||
10512 | char * | |
10513 | md_atof (type, litP, sizeP) | |
10514 | int type; | |
10515 | char *litP; | |
10516 | int *sizeP; | |
10517 | { | |
10518 | int prec; | |
10519 | LITTLENUM_TYPE words[4]; | |
10520 | char *t; | |
10521 | int i; | |
10522 | ||
10523 | switch (type) | |
10524 | { | |
10525 | case 'f': | |
10526 | prec = 2; | |
10527 | break; | |
10528 | ||
10529 | case 'd': | |
10530 | prec = 4; | |
10531 | break; | |
10532 | ||
10533 | default: | |
10534 | *sizeP = 0; | |
10535 | return _("bad call to md_atof"); | |
10536 | } | |
10537 | ||
10538 | t = atof_ieee (input_line_pointer, type, words); | |
10539 | if (t) | |
10540 | input_line_pointer = t; | |
10541 | ||
10542 | *sizeP = prec * 2; | |
10543 | ||
10544 | if (! target_big_endian) | |
10545 | { | |
10546 | for (i = prec - 1; i >= 0; i--) | |
10547 | { | |
10548 | md_number_to_chars (litP, (valueT) words[i], 2); | |
10549 | litP += 2; | |
10550 | } | |
10551 | } | |
10552 | else | |
10553 | { | |
10554 | for (i = 0; i < prec; i++) | |
10555 | { | |
10556 | md_number_to_chars (litP, (valueT) words[i], 2); | |
10557 | litP += 2; | |
10558 | } | |
10559 | } | |
bdaaa2e1 | 10560 | |
252b5132 RH |
10561 | return NULL; |
10562 | } | |
10563 | ||
10564 | void | |
10565 | md_number_to_chars (buf, val, n) | |
10566 | char *buf; | |
10567 | valueT val; | |
10568 | int n; | |
10569 | { | |
10570 | if (target_big_endian) | |
10571 | number_to_chars_bigendian (buf, val, n); | |
10572 | else | |
10573 | number_to_chars_littleendian (buf, val, n); | |
10574 | } | |
10575 | \f | |
ae948b86 | 10576 | #ifdef OBJ_ELF |
e013f690 TS |
10577 | static int support_64bit_objects(void) |
10578 | { | |
10579 | const char **list, **l; | |
aa3d8fdf | 10580 | int yes; |
e013f690 TS |
10581 | |
10582 | list = bfd_target_list (); | |
10583 | for (l = list; *l != NULL; l++) | |
10584 | #ifdef TE_TMIPS | |
10585 | /* This is traditional mips */ | |
10586 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10587 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10588 | #else | |
10589 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10590 | || strcmp (*l, "elf64-littlemips") == 0) | |
10591 | #endif | |
10592 | break; | |
aa3d8fdf | 10593 | yes = (*l != NULL); |
e013f690 | 10594 | free (list); |
aa3d8fdf | 10595 | return yes; |
e013f690 | 10596 | } |
ae948b86 | 10597 | #endif /* OBJ_ELF */ |
e013f690 | 10598 | |
5a38dc70 | 10599 | const char *md_shortopts = "nO::g::G:"; |
252b5132 | 10600 | |
e972090a NC |
10601 | struct option md_longopts[] = |
10602 | { | |
f9b4148d CD |
10603 | /* Options which specify architecture. */ |
10604 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10605 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10606 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10607 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10608 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10609 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10610 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10611 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10612 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10613 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10614 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10615 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10616 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10617 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10618 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10619 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10620 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10621 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10622 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10623 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10624 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10625 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
10626 | ||
10627 | /* Options which specify Application Specific Extensions (ASEs). */ | |
10628 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10) | |
10629 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) | |
10630 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10631 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10632 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10633 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10634 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10635 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10636 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10637 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10638 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10639 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10640 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10641 | ||
10642 | /* Old-style architecture options. Don't add more of these. */ | |
10643 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10644 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10645 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10646 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10647 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10648 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10649 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10650 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10651 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10652 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10653 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10654 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10655 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10656 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10657 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10658 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10659 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10660 | ||
10661 | /* Options which enable bug fixes. */ | |
10662 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10663 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10664 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10665 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10666 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10667 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10668 | #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2) | |
10669 | #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3) | |
10670 | {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, | |
10671 | {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, | |
10672 | ||
10673 | /* Miscellaneous options. */ | |
10674 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
10675 | #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) | |
252b5132 | 10676 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
f9b4148d | 10677 | #define OPTION_TRAP (OPTION_MISC_BASE + 1) |
252b5132 RH |
10678 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10679 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
f9b4148d | 10680 | #define OPTION_BREAK (OPTION_MISC_BASE + 2) |
252b5132 RH |
10681 | {"break", no_argument, NULL, OPTION_BREAK}, |
10682 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
f9b4148d | 10683 | #define OPTION_EB (OPTION_MISC_BASE + 3) |
252b5132 | 10684 | {"EB", no_argument, NULL, OPTION_EB}, |
f9b4148d | 10685 | #define OPTION_EL (OPTION_MISC_BASE + 4) |
252b5132 | 10686 | {"EL", no_argument, NULL, OPTION_EL}, |
f9b4148d | 10687 | #define OPTION_FP32 (OPTION_MISC_BASE + 5) |
ae948b86 | 10688 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
f9b4148d | 10689 | #define OPTION_GP32 (OPTION_MISC_BASE + 6) |
c97ef257 | 10690 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
f9b4148d | 10691 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10692 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
f9b4148d | 10693 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) |
119d663a | 10694 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
f9b4148d | 10695 | #define OPTION_FP64 (OPTION_MISC_BASE + 9) |
316f5878 | 10696 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
f9b4148d | 10697 | #define OPTION_GP64 (OPTION_MISC_BASE + 10) |
ae948b86 | 10698 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
f9b4148d CD |
10699 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) |
10700 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) | |
4a6a3df4 AO |
10701 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10702 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10703 | |
10704 | /* ELF-specific options. */ | |
156c2f8b | 10705 | #ifdef OBJ_ELF |
f9b4148d | 10706 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) |
156c2f8b | 10707 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10708 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10709 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10710 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10711 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10712 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10713 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10714 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10715 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10716 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10717 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10718 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10719 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10720 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10721 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10722 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10723 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10724 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10725 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
ae948b86 | 10726 | #endif /* OBJ_ELF */ |
f9b4148d | 10727 | |
252b5132 RH |
10728 | {NULL, no_argument, NULL, 0} |
10729 | }; | |
156c2f8b | 10730 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10731 | |
316f5878 RS |
10732 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10733 | NEW_VALUE. Warn if another value was already specified. Note: | |
10734 | we have to defer parsing the -march and -mtune arguments in order | |
10735 | to handle 'from-abi' correctly, since the ABI might be specified | |
10736 | in a later argument. */ | |
10737 | ||
10738 | static void | |
10739 | mips_set_option_string (string_ptr, new_value) | |
10740 | const char **string_ptr, *new_value; | |
10741 | { | |
10742 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10743 | as_warn (_("A different %s was already specified, is now %s"), | |
10744 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10745 | new_value); | |
10746 | ||
10747 | *string_ptr = new_value; | |
10748 | } | |
10749 | ||
252b5132 RH |
10750 | int |
10751 | md_parse_option (c, arg) | |
10752 | int c; | |
10753 | char *arg; | |
10754 | { | |
10755 | switch (c) | |
10756 | { | |
119d663a NC |
10757 | case OPTION_CONSTRUCT_FLOATS: |
10758 | mips_disable_float_construction = 0; | |
10759 | break; | |
bdaaa2e1 | 10760 | |
119d663a NC |
10761 | case OPTION_NO_CONSTRUCT_FLOATS: |
10762 | mips_disable_float_construction = 1; | |
10763 | break; | |
bdaaa2e1 | 10764 | |
252b5132 RH |
10765 | case OPTION_TRAP: |
10766 | mips_trap = 1; | |
10767 | break; | |
10768 | ||
10769 | case OPTION_BREAK: | |
10770 | mips_trap = 0; | |
10771 | break; | |
10772 | ||
10773 | case OPTION_EB: | |
10774 | target_big_endian = 1; | |
10775 | break; | |
10776 | ||
10777 | case OPTION_EL: | |
10778 | target_big_endian = 0; | |
10779 | break; | |
10780 | ||
39c0a331 L |
10781 | case 'n': |
10782 | warn_nops = 1; | |
10783 | break; | |
10784 | ||
252b5132 RH |
10785 | case 'O': |
10786 | if (arg && arg[1] == '0') | |
10787 | mips_optimize = 1; | |
10788 | else | |
10789 | mips_optimize = 2; | |
10790 | break; | |
10791 | ||
10792 | case 'g': | |
10793 | if (arg == NULL) | |
10794 | mips_debug = 2; | |
10795 | else | |
10796 | mips_debug = atoi (arg); | |
10797 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10798 | optimizations which limit full symbolic debugging. We take | |
10799 | that to be equivalent to -O0. */ | |
10800 | if (mips_debug == 2) | |
10801 | mips_optimize = 1; | |
10802 | break; | |
10803 | ||
10804 | case OPTION_MIPS1: | |
316f5878 | 10805 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10806 | break; |
10807 | ||
10808 | case OPTION_MIPS2: | |
316f5878 | 10809 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10810 | break; |
10811 | ||
10812 | case OPTION_MIPS3: | |
316f5878 | 10813 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10814 | break; |
10815 | ||
10816 | case OPTION_MIPS4: | |
316f5878 | 10817 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10818 | break; |
10819 | ||
84ea6cf2 | 10820 | case OPTION_MIPS5: |
316f5878 | 10821 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10822 | break; |
10823 | ||
e7af610e | 10824 | case OPTION_MIPS32: |
316f5878 | 10825 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10826 | break; |
10827 | ||
af7ee8bf CD |
10828 | case OPTION_MIPS32R2: |
10829 | file_mips_isa = ISA_MIPS32R2; | |
10830 | break; | |
10831 | ||
84ea6cf2 | 10832 | case OPTION_MIPS64: |
316f5878 | 10833 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10834 | break; |
10835 | ||
ec68c924 | 10836 | case OPTION_MTUNE: |
316f5878 RS |
10837 | mips_set_option_string (&mips_tune_string, arg); |
10838 | break; | |
ec68c924 | 10839 | |
316f5878 RS |
10840 | case OPTION_MARCH: |
10841 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10842 | break; |
10843 | ||
10844 | case OPTION_M4650: | |
316f5878 RS |
10845 | mips_set_option_string (&mips_arch_string, "4650"); |
10846 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10847 | break; |
10848 | ||
10849 | case OPTION_NO_M4650: | |
10850 | break; | |
10851 | ||
10852 | case OPTION_M4010: | |
316f5878 RS |
10853 | mips_set_option_string (&mips_arch_string, "4010"); |
10854 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10855 | break; |
10856 | ||
10857 | case OPTION_NO_M4010: | |
10858 | break; | |
10859 | ||
10860 | case OPTION_M4100: | |
316f5878 RS |
10861 | mips_set_option_string (&mips_arch_string, "4100"); |
10862 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10863 | break; |
10864 | ||
10865 | case OPTION_NO_M4100: | |
10866 | break; | |
10867 | ||
252b5132 | 10868 | case OPTION_M3900: |
316f5878 RS |
10869 | mips_set_option_string (&mips_arch_string, "3900"); |
10870 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10871 | break; |
bdaaa2e1 | 10872 | |
252b5132 RH |
10873 | case OPTION_NO_M3900: |
10874 | break; | |
10875 | ||
deec1734 CD |
10876 | case OPTION_MDMX: |
10877 | mips_opts.ase_mdmx = 1; | |
10878 | break; | |
10879 | ||
10880 | case OPTION_NO_MDMX: | |
10881 | mips_opts.ase_mdmx = 0; | |
10882 | break; | |
10883 | ||
252b5132 RH |
10884 | case OPTION_MIPS16: |
10885 | mips_opts.mips16 = 1; | |
b34976b6 | 10886 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10887 | break; |
10888 | ||
10889 | case OPTION_NO_MIPS16: | |
10890 | mips_opts.mips16 = 0; | |
b34976b6 | 10891 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10892 | break; |
10893 | ||
1f25f5d3 CD |
10894 | case OPTION_MIPS3D: |
10895 | mips_opts.ase_mips3d = 1; | |
10896 | break; | |
10897 | ||
10898 | case OPTION_NO_MIPS3D: | |
10899 | mips_opts.ase_mips3d = 0; | |
10900 | break; | |
10901 | ||
252b5132 RH |
10902 | case OPTION_MEMBEDDED_PIC: |
10903 | mips_pic = EMBEDDED_PIC; | |
10904 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10905 | { | |
10906 | as_bad (_("-G may not be used with embedded PIC code")); | |
10907 | return 0; | |
10908 | } | |
10909 | g_switch_value = 0x7fffffff; | |
10910 | break; | |
10911 | ||
60b63b72 RS |
10912 | case OPTION_FIX_VR4122: |
10913 | mips_fix_4122_bugs = 1; | |
10914 | break; | |
10915 | ||
10916 | case OPTION_NO_FIX_VR4122: | |
10917 | mips_fix_4122_bugs = 0; | |
10918 | break; | |
10919 | ||
4a6a3df4 AO |
10920 | case OPTION_RELAX_BRANCH: |
10921 | mips_relax_branch = 1; | |
10922 | break; | |
10923 | ||
10924 | case OPTION_NO_RELAX_BRANCH: | |
10925 | mips_relax_branch = 0; | |
10926 | break; | |
10927 | ||
0f074f60 | 10928 | #ifdef OBJ_ELF |
252b5132 RH |
10929 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10930 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10931 | intended to be compatible with Irix 5. */ | |
10932 | case OPTION_CALL_SHARED: | |
10933 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10934 | { | |
10935 | as_bad (_("-call_shared is supported only for ELF format")); | |
10936 | return 0; | |
10937 | } | |
10938 | mips_pic = SVR4_PIC; | |
143d77c5 | 10939 | mips_abicalls = TRUE; |
252b5132 RH |
10940 | if (g_switch_seen && g_switch_value != 0) |
10941 | { | |
10942 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10943 | return 0; | |
10944 | } | |
10945 | g_switch_value = 0; | |
10946 | break; | |
10947 | ||
10948 | case OPTION_NON_SHARED: | |
10949 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10950 | { | |
10951 | as_bad (_("-non_shared is supported only for ELF format")); | |
10952 | return 0; | |
10953 | } | |
10954 | mips_pic = NO_PIC; | |
143d77c5 | 10955 | mips_abicalls = FALSE; |
252b5132 RH |
10956 | break; |
10957 | ||
10958 | /* The -xgot option tells the assembler to use 32 offsets when | |
10959 | accessing the got in SVR4_PIC mode. It is for Irix | |
10960 | compatibility. */ | |
10961 | case OPTION_XGOT: | |
10962 | mips_big_got = 1; | |
10963 | break; | |
0f074f60 | 10964 | #endif /* OBJ_ELF */ |
252b5132 RH |
10965 | |
10966 | case 'G': | |
10967 | if (! USE_GLOBAL_POINTER_OPT) | |
10968 | { | |
10969 | as_bad (_("-G is not supported for this configuration")); | |
10970 | return 0; | |
10971 | } | |
10972 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10973 | { | |
10974 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10975 | return 0; | |
10976 | } | |
10977 | else | |
10978 | g_switch_value = atoi (arg); | |
10979 | g_switch_seen = 1; | |
10980 | break; | |
10981 | ||
0f074f60 | 10982 | #ifdef OBJ_ELF |
34ba82a8 TS |
10983 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10984 | and -mabi=64. */ | |
252b5132 | 10985 | case OPTION_32: |
34ba82a8 TS |
10986 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10987 | { | |
10988 | as_bad (_("-32 is supported for ELF format only")); | |
10989 | return 0; | |
10990 | } | |
316f5878 | 10991 | mips_abi = O32_ABI; |
252b5132 RH |
10992 | break; |
10993 | ||
e013f690 | 10994 | case OPTION_N32: |
34ba82a8 TS |
10995 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10996 | { | |
10997 | as_bad (_("-n32 is supported for ELF format only")); | |
10998 | return 0; | |
10999 | } | |
316f5878 | 11000 | mips_abi = N32_ABI; |
e013f690 | 11001 | break; |
252b5132 | 11002 | |
e013f690 | 11003 | case OPTION_64: |
34ba82a8 TS |
11004 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11005 | { | |
11006 | as_bad (_("-64 is supported for ELF format only")); | |
11007 | return 0; | |
11008 | } | |
316f5878 | 11009 | mips_abi = N64_ABI; |
e013f690 TS |
11010 | if (! support_64bit_objects()) |
11011 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 11012 | break; |
ae948b86 | 11013 | #endif /* OBJ_ELF */ |
252b5132 | 11014 | |
c97ef257 | 11015 | case OPTION_GP32: |
a325df1d | 11016 | file_mips_gp32 = 1; |
c97ef257 AH |
11017 | break; |
11018 | ||
11019 | case OPTION_GP64: | |
a325df1d | 11020 | file_mips_gp32 = 0; |
c97ef257 | 11021 | break; |
252b5132 | 11022 | |
ca4e0257 | 11023 | case OPTION_FP32: |
a325df1d | 11024 | file_mips_fp32 = 1; |
316f5878 RS |
11025 | break; |
11026 | ||
11027 | case OPTION_FP64: | |
11028 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11029 | break; |
11030 | ||
ae948b86 | 11031 | #ifdef OBJ_ELF |
252b5132 | 11032 | case OPTION_MABI: |
34ba82a8 TS |
11033 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11034 | { | |
11035 | as_bad (_("-mabi is supported for ELF format only")); | |
11036 | return 0; | |
11037 | } | |
e013f690 | 11038 | if (strcmp (arg, "32") == 0) |
316f5878 | 11039 | mips_abi = O32_ABI; |
e013f690 | 11040 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11041 | mips_abi = O64_ABI; |
e013f690 | 11042 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11043 | mips_abi = N32_ABI; |
e013f690 TS |
11044 | else if (strcmp (arg, "64") == 0) |
11045 | { | |
316f5878 | 11046 | mips_abi = N64_ABI; |
e013f690 TS |
11047 | if (! support_64bit_objects()) |
11048 | as_fatal (_("No compiled in support for 64 bit object file " | |
11049 | "format")); | |
11050 | } | |
11051 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11052 | mips_abi = EABI_ABI; |
e013f690 | 11053 | else |
da0e507f TS |
11054 | { |
11055 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11056 | return 0; | |
11057 | } | |
252b5132 | 11058 | break; |
e013f690 | 11059 | #endif /* OBJ_ELF */ |
252b5132 | 11060 | |
6b76fefe | 11061 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11062 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11063 | break; |
11064 | ||
9ee72ff1 | 11065 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11066 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11067 | break; |
11068 | ||
ecb4347a DJ |
11069 | #ifdef OBJ_ELF |
11070 | case OPTION_MDEBUG: | |
b34976b6 | 11071 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11072 | break; |
11073 | ||
11074 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11075 | mips_flag_mdebug = FALSE; |
ecb4347a DJ |
11076 | break; |
11077 | #endif /* OBJ_ELF */ | |
11078 | ||
252b5132 RH |
11079 | default: |
11080 | return 0; | |
11081 | } | |
11082 | ||
11083 | return 1; | |
11084 | } | |
316f5878 RS |
11085 | \f |
11086 | /* Set up globals to generate code for the ISA or processor | |
11087 | described by INFO. */ | |
252b5132 | 11088 | |
252b5132 | 11089 | static void |
316f5878 RS |
11090 | mips_set_architecture (info) |
11091 | const struct mips_cpu_info *info; | |
252b5132 | 11092 | { |
316f5878 | 11093 | if (info != 0) |
252b5132 | 11094 | { |
316f5878 RS |
11095 | mips_arch_info = info; |
11096 | mips_arch = info->cpu; | |
11097 | mips_opts.isa = info->isa; | |
252b5132 | 11098 | } |
252b5132 RH |
11099 | } |
11100 | ||
252b5132 | 11101 | |
316f5878 | 11102 | /* Likewise for tuning. */ |
252b5132 | 11103 | |
316f5878 RS |
11104 | static void |
11105 | mips_set_tune (info) | |
11106 | const struct mips_cpu_info *info; | |
11107 | { | |
11108 | if (info != 0) | |
11109 | { | |
11110 | mips_tune_info = info; | |
11111 | mips_tune = info->cpu; | |
11112 | } | |
11113 | } | |
80cc45a5 | 11114 | |
34ba82a8 | 11115 | |
252b5132 | 11116 | void |
e9670677 MR |
11117 | mips_after_parse_args () |
11118 | { | |
e9670677 MR |
11119 | /* GP relative stuff not working for PE */ |
11120 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
11121 | && g_switch_value != 0) | |
11122 | { | |
11123 | if (g_switch_seen) | |
11124 | as_bad (_("-G not supported in this configuration.")); | |
11125 | g_switch_value = 0; | |
11126 | } | |
11127 | ||
cac012d6 AO |
11128 | if (mips_abi == NO_ABI) |
11129 | mips_abi = MIPS_DEFAULT_ABI; | |
11130 | ||
22923709 RS |
11131 | /* The following code determines the architecture and register size. |
11132 | Similar code was added to GCC 3.3 (see override_options() in | |
11133 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11134 | as much as possible. */ | |
e9670677 | 11135 | |
316f5878 RS |
11136 | if (mips_arch_string != 0) |
11137 | mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string)); | |
e9670677 | 11138 | |
316f5878 RS |
11139 | if (mips_tune_string != 0) |
11140 | mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string)); | |
e9670677 | 11141 | |
316f5878 | 11142 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11143 | { |
316f5878 RS |
11144 | /* Handle -mipsN. At this point, file_mips_isa contains the |
11145 | ISA level specified by -mipsN, while mips_opts.isa contains | |
11146 | the -march selection (if any). */ | |
11147 | if (mips_arch_info != 0) | |
e9670677 | 11148 | { |
316f5878 RS |
11149 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11150 | There's no harm in specifying both as long as the ISA levels | |
11151 | are the same. */ | |
11152 | if (file_mips_isa != mips_opts.isa) | |
11153 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), | |
11154 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
11155 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 11156 | } |
316f5878 RS |
11157 | else |
11158 | mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa)); | |
e9670677 MR |
11159 | } |
11160 | ||
316f5878 RS |
11161 | if (mips_arch_info == 0) |
11162 | mips_set_architecture (mips_parse_cpu ("default CPU", | |
11163 | MIPS_CPU_STRING_DEFAULT)); | |
e9670677 | 11164 | |
316f5878 RS |
11165 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
11166 | as_bad ("-march=%s is not compatible with the selected ABI", | |
11167 | mips_arch_info->name); | |
e9670677 | 11168 | |
316f5878 RS |
11169 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
11170 | if (mips_tune_info == 0) | |
11171 | mips_set_tune (mips_arch_info); | |
e9670677 | 11172 | |
316f5878 | 11173 | if (file_mips_gp32 >= 0) |
e9670677 | 11174 | { |
316f5878 RS |
11175 | /* The user specified the size of the integer registers. Make sure |
11176 | it agrees with the ABI and ISA. */ | |
11177 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11178 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11179 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11180 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11181 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11182 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11183 | } |
11184 | else | |
11185 | { | |
316f5878 RS |
11186 | /* Infer the integer register size from the ABI and processor. |
11187 | Restrict ourselves to 32-bit registers if that's all the | |
11188 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11189 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11190 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11191 | } |
11192 | ||
316f5878 RS |
11193 | /* ??? GAS treats single-float processors as though they had 64-bit |
11194 | float registers (although it complains when double-precision | |
11195 | instructions are used). As things stand, saying they have 32-bit | |
11196 | registers would lead to spurious "register must be even" messages. | |
11197 | So here we assume float registers are always the same size as | |
11198 | integer ones, unless the user says otherwise. */ | |
11199 | if (file_mips_fp32 < 0) | |
11200 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 11201 | |
316f5878 | 11202 | /* End of GCC-shared inference code. */ |
e9670677 | 11203 | |
316f5878 RS |
11204 | /* ??? When do we want this flag to be set? Who uses it? */ |
11205 | if (file_mips_gp32 == 1 | |
11206 | && mips_abi == NO_ABI | |
11207 | && ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11208 | mips_32bitmode = 1; | |
e9670677 MR |
11209 | |
11210 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11211 | as_bad (_("trap exception not supported at ISA 1")); | |
11212 | ||
e9670677 MR |
11213 | /* If the selected architecture includes support for ASEs, enable |
11214 | generation of code for them. */ | |
a4672219 TS |
11215 | if (mips_opts.mips16 == -1) |
11216 | mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0; | |
ffdefa66 | 11217 | if (mips_opts.ase_mips3d == -1) |
a4672219 | 11218 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0; |
ffdefa66 | 11219 | if (mips_opts.ase_mdmx == -1) |
a4672219 | 11220 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0; |
e9670677 | 11221 | |
e9670677 | 11222 | file_mips_isa = mips_opts.isa; |
a4672219 | 11223 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11224 | file_ase_mips3d = mips_opts.ase_mips3d; |
11225 | file_ase_mdmx = mips_opts.ase_mdmx; | |
11226 | mips_opts.gp32 = file_mips_gp32; | |
11227 | mips_opts.fp32 = file_mips_fp32; | |
11228 | ||
ecb4347a DJ |
11229 | if (mips_flag_mdebug < 0) |
11230 | { | |
11231 | #ifdef OBJ_MAYBE_ECOFF | |
11232 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11233 | mips_flag_mdebug = 1; | |
11234 | else | |
11235 | #endif /* OBJ_MAYBE_ECOFF */ | |
11236 | mips_flag_mdebug = 0; | |
11237 | } | |
e9670677 MR |
11238 | } |
11239 | \f | |
11240 | void | |
252b5132 RH |
11241 | mips_init_after_args () |
11242 | { | |
11243 | /* initialize opcodes */ | |
11244 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11245 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11246 | } |
11247 | ||
11248 | long | |
11249 | md_pcrel_from (fixP) | |
11250 | fixS *fixP; | |
11251 | { | |
a7ebbfdf TS |
11252 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11253 | switch (fixP->fx_r_type) | |
11254 | { | |
11255 | case BFD_RELOC_16_PCREL_S2: | |
11256 | case BFD_RELOC_MIPS_JMP: | |
11257 | /* Return the address of the delay slot. */ | |
11258 | return addr + 4; | |
11259 | default: | |
11260 | return addr; | |
11261 | } | |
252b5132 RH |
11262 | } |
11263 | ||
252b5132 RH |
11264 | /* This is called before the symbol table is processed. In order to |
11265 | work with gcc when using mips-tfile, we must keep all local labels. | |
11266 | However, in other cases, we want to discard them. If we were | |
11267 | called with -g, but we didn't see any debugging information, it may | |
11268 | mean that gcc is smuggling debugging information through to | |
11269 | mips-tfile, in which case we must generate all local labels. */ | |
11270 | ||
11271 | void | |
11272 | mips_frob_file_before_adjust () | |
11273 | { | |
11274 | #ifndef NO_ECOFF_DEBUGGING | |
11275 | if (ECOFF_DEBUGGING | |
11276 | && mips_debug != 0 | |
11277 | && ! ecoff_debugging_seen) | |
11278 | flag_keep_locals = 1; | |
11279 | #endif | |
11280 | } | |
11281 | ||
11282 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 11283 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
11284 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
11285 | explicit use of the %hi modifier. */ | |
11286 | ||
11287 | void | |
11288 | mips_frob_file () | |
11289 | { | |
11290 | struct mips_hi_fixup *l; | |
11291 | ||
11292 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11293 | { | |
11294 | segment_info_type *seginfo; | |
11295 | int pass; | |
11296 | ||
5919d012 | 11297 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11298 | |
5919d012 RS |
11299 | /* If a GOT16 relocation turns out to be against a global symbol, |
11300 | there isn't supposed to be a matching LO. */ | |
11301 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11302 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11303 | continue; | |
11304 | ||
11305 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11306 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11307 | continue; |
11308 | ||
11309 | /* Look through the fixups for this segment for a matching %lo. | |
11310 | When we find one, move the %hi just in front of it. We do | |
11311 | this in two passes. In the first pass, we try to find a | |
11312 | unique %lo. In the second pass, we permit multiple %hi | |
11313 | relocs for a single %lo (this is a GNU extension). */ | |
11314 | seginfo = seg_info (l->seg); | |
11315 | for (pass = 0; pass < 2; pass++) | |
11316 | { | |
11317 | fixS *f, *prev; | |
11318 | ||
11319 | prev = NULL; | |
11320 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
11321 | { | |
11322 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
11323 | if (f->fx_r_type == BFD_RELOC_LO16 | |
11324 | && f->fx_addsy == l->fixp->fx_addsy | |
11325 | && f->fx_offset == l->fixp->fx_offset | |
11326 | && (pass == 1 | |
11327 | || prev == NULL | |
5919d012 RS |
11328 | || !reloc_needs_lo_p (prev->fx_r_type) |
11329 | || !fixup_has_matching_lo_p (prev))) | |
252b5132 RH |
11330 | { |
11331 | fixS **pf; | |
11332 | ||
11333 | /* Move l->fixp before f. */ | |
11334 | for (pf = &seginfo->fix_root; | |
11335 | *pf != l->fixp; | |
11336 | pf = &(*pf)->fx_next) | |
11337 | assert (*pf != NULL); | |
11338 | ||
11339 | *pf = l->fixp->fx_next; | |
11340 | ||
11341 | l->fixp->fx_next = f; | |
11342 | if (prev == NULL) | |
11343 | seginfo->fix_root = l->fixp; | |
11344 | else | |
11345 | prev->fx_next = l->fixp; | |
11346 | ||
11347 | break; | |
11348 | } | |
11349 | ||
11350 | prev = f; | |
11351 | } | |
11352 | ||
11353 | if (f != NULL) | |
11354 | break; | |
11355 | ||
11356 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
11357 | can leave a %hi without a %lo. */ | |
11358 | if (pass == 1) | |
11359 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
11360 | _("Unmatched %%hi reloc")); | |
11361 | #endif | |
11362 | } | |
11363 | } | |
11364 | } | |
11365 | ||
11366 | /* When generating embedded PIC code we need to use a special | |
11367 | relocation to represent the difference of two symbols in the .text | |
11368 | section (switch tables use a difference of this sort). See | |
11369 | include/coff/mips.h for details. This macro checks whether this | |
11370 | fixup requires the special reloc. */ | |
11371 | #define SWITCH_TABLE(fixp) \ | |
11372 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 11373 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
11374 | && (fixp)->fx_addsy != NULL \ |
11375 | && (fixp)->fx_subsy != NULL \ | |
11376 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
11377 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
11378 | ||
11379 | /* When generating embedded PIC code we must keep all PC relative | |
11380 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
11381 | to keep relocations for switch table entries. |
11382 | ||
11383 | We may have combined relocations without symbols in the N32/N64 ABI. | |
11384 | We have to prevent gas from dropping them. */ | |
252b5132 | 11385 | |
252b5132 RH |
11386 | int |
11387 | mips_force_relocation (fixp) | |
11388 | fixS *fixp; | |
11389 | { | |
ae6063d4 | 11390 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11391 | return 1; |
11392 | ||
f6688943 TS |
11393 | if (HAVE_NEWABI |
11394 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11395 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11396 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11397 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11398 | return 1; | |
11399 | ||
252b5132 RH |
11400 | return (mips_pic == EMBEDDED_PIC |
11401 | && (fixp->fx_pcrel | |
11402 | || SWITCH_TABLE (fixp) | |
11403 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
11404 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
11405 | } | |
11406 | ||
45f8dfe8 AO |
11407 | /* This hook is called before a fix is simplified. We don't really |
11408 | decide whether to skip a fix here. Rather, we turn global symbols | |
11409 | used as branch targets into local symbols, such that they undergo | |
11410 | simplification. We can only do this if the symbol is defined and | |
11411 | it is in the same section as the branch. If this doesn't hold, we | |
11412 | emit a better error message than just saying the relocation is not | |
11413 | valid for the selected object format. | |
11414 | ||
11415 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
11416 | segment in which the fix up occurs. The return value should be | |
11417 | non-zero to indicate the fix-up is valid for further | |
11418 | simplifications. */ | |
11419 | ||
11420 | int | |
11421 | mips_validate_fix (fixP, seg) | |
11422 | struct fix *fixP; | |
11423 | asection *seg; | |
11424 | { | |
11425 | /* There's a lot of discussion on whether it should be possible to | |
11426 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11427 | seems to be that it can, but gas/bfd are very broken in creating | |
11428 | RELA relocations for this, so for now we only accept branches to | |
11429 | symbols in the same section. Anything else is of dubious value, | |
11430 | since there's no guarantee that at link time the symbol would be | |
11431 | in range. Even for branches to local symbols this is arguably | |
11432 | wrong, since it we assume the symbol is not going to be | |
11433 | overridden, which should be possible per ELF library semantics, | |
11434 | but then, there isn't a dynamic relocation that could be used to | |
11435 | this effect, and the target would likely be out of range as well. | |
11436 | ||
11437 | Unfortunately, it seems that there is too much code out there | |
11438 | that relies on branches to symbols that are global to be resolved | |
11439 | as if they were local, like the IRIX tools do, so we do it as | |
11440 | well, but with a warning so that people are reminded to fix their | |
11441 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11442 | targets, this entire block should go away (and probably the | |
11443 | whole function). */ | |
11444 | ||
11445 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
11446 | && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
11447 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11448 | && mips_pic != EMBEDDED_PIC) | |
11449 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) | |
11450 | && fixP->fx_addsy) | |
11451 | { | |
11452 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11453 | { | |
11454 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11455 | _("Cannot branch to undefined symbol.")); | |
11456 | /* Avoid any further errors about this fixup. */ | |
11457 | fixP->fx_done = 1; | |
11458 | } | |
11459 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11460 | { | |
11461 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11462 | _("Cannot branch to symbol in another section.")); | |
11463 | fixP->fx_done = 1; | |
11464 | } | |
11465 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11466 | { | |
11467 | symbolS *sym = fixP->fx_addsy; | |
11468 | ||
11469 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11470 | _("Pretending global symbol used as branch target is local.")); | |
11471 | ||
11472 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11473 | S_GET_SEGMENT (sym), | |
11474 | S_GET_VALUE (sym), | |
11475 | symbol_get_frag (sym)); | |
11476 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11477 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11478 | assert (symbol_resolved_p (sym)); | |
11479 | symbol_mark_resolved (fixP->fx_addsy); | |
11480 | } | |
11481 | } | |
11482 | ||
11483 | return 1; | |
11484 | } | |
11485 | ||
add55e1f RS |
11486 | #ifdef OBJ_ELF |
11487 | static int | |
11488 | mips_need_elf_addend_fixup (fixP) | |
11489 | fixS *fixP; | |
11490 | { | |
2d2bf3e0 CD |
11491 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
11492 | return 1; | |
b25a253c CD |
11493 | if (mips_pic == EMBEDDED_PIC |
11494 | && S_IS_WEAK (fixP->fx_addsy)) | |
11495 | return 1; | |
11496 | if (mips_pic != EMBEDDED_PIC | |
11497 | && (S_IS_WEAK (fixP->fx_addsy) | |
bad9ca53 | 11498 | || S_IS_EXTERNAL (fixP->fx_addsy)) |
2d2bf3e0 CD |
11499 | && !S_IS_COMMON (fixP->fx_addsy)) |
11500 | return 1; | |
9204e615 DJ |
11501 | if (((bfd_get_section_flags (stdoutput, |
11502 | S_GET_SEGMENT (fixP->fx_addsy)) | |
11503 | & (SEC_LINK_ONCE | SEC_MERGE)) != 0) | |
11504 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
11505 | ".gnu.linkonce", | |
11506 | sizeof (".gnu.linkonce") - 1)) | |
2d2bf3e0 CD |
11507 | return 1; |
11508 | return 0; | |
add55e1f RS |
11509 | } |
11510 | #endif | |
11511 | ||
252b5132 RH |
11512 | /* Apply a fixup to the object file. */ |
11513 | ||
94f592af NC |
11514 | void |
11515 | md_apply_fix3 (fixP, valP, seg) | |
252b5132 | 11516 | fixS *fixP; |
98d3f06f | 11517 | valueT *valP; |
94f592af | 11518 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 11519 | { |
874e8986 | 11520 | bfd_byte *buf; |
98aa84af | 11521 | long insn; |
ed6fb7bd | 11522 | static int previous_fx_r_type = 0; |
a7ebbfdf | 11523 | reloc_howto_type *howto; |
252b5132 | 11524 | |
a7ebbfdf TS |
11525 | /* We ignore generic BFD relocations we don't know about. */ |
11526 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11527 | if (! howto) | |
11528 | return; | |
65551fa4 | 11529 | |
252b5132 RH |
11530 | assert (fixP->fx_size == 4 |
11531 | || fixP->fx_r_type == BFD_RELOC_16 | |
11532 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11533 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11534 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11535 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11536 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11537 | |
a7ebbfdf | 11538 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 RH |
11539 | |
11540 | /* If we aren't adjusting this fixup to be against the section | |
11541 | symbol, we need to adjust the value. */ | |
11542 | #ifdef OBJ_ELF | |
11543 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 11544 | { |
a7ebbfdf TS |
11545 | if (mips_need_elf_addend_fixup (fixP) |
11546 | && howto->partial_inplace | |
11547 | && fixP->fx_r_type != BFD_RELOC_GPREL16 | |
11548 | && fixP->fx_r_type != BFD_RELOC_GPREL32 | |
11549 | && fixP->fx_r_type != BFD_RELOC_MIPS16_GPREL) | |
11550 | { | |
11551 | /* In this case, the bfd_install_relocation routine will | |
11552 | incorrectly add the symbol value back in. We just want | |
11553 | the addend to appear in the object file. | |
11554 | ||
11555 | The condition above used to include | |
11556 | "&& (! fixP->fx_pcrel || howto->pcrel_offset)". | |
11557 | ||
11558 | However, howto can't be trusted here, because we | |
11559 | might change the reloc type in tc_gen_reloc. We can | |
11560 | check howto->partial_inplace because that conversion | |
11561 | happens to preserve howto->partial_inplace; but it | |
11562 | does not preserve howto->pcrel_offset. I've just | |
11563 | eliminated the check, because all MIPS PC-relative | |
11564 | relocations are marked howto->pcrel_offset. | |
11565 | ||
11566 | howto->pcrel_offset was originally added for | |
11567 | R_MIPS_PC16, which is generated for code like | |
11568 | ||
11569 | globl g1 .text | |
11570 | .text | |
11571 | .space 20 | |
11572 | g1: | |
11573 | x: | |
11574 | bal g1 | |
11575 | */ | |
11576 | *valP -= S_GET_VALUE (fixP->fx_addsy); | |
98aa84af | 11577 | } |
252b5132 | 11578 | |
bb2d6cd7 GK |
11579 | /* This code was generated using trial and error and so is |
11580 | fragile and not trustworthy. If you change it, you should | |
11581 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
11582 | they still pass. */ | |
a7ebbfdf | 11583 | if (fixP->fx_pcrel) |
bb2d6cd7 | 11584 | { |
a7ebbfdf | 11585 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
bb2d6cd7 GK |
11586 | |
11587 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
11588 | This gives the right results, but it can't possibly | |
11589 | be the way things are supposed to work. */ | |
a7ebbfdf | 11590 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
bb2d6cd7 GK |
11591 | } |
11592 | } | |
11593 | #endif | |
252b5132 | 11594 | |
ed6fb7bd SC |
11595 | /* We are not done if this is a composite relocation to set up gp. */ |
11596 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
11597 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10181a0d AO |
11598 | || (fixP->fx_r_type == BFD_RELOC_64 |
11599 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
11600 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
11601 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
11602 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
11603 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 11604 | fixP->fx_done = 1; |
ed6fb7bd | 11605 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
11606 | |
11607 | switch (fixP->fx_r_type) | |
11608 | { | |
11609 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11610 | case BFD_RELOC_MIPS_SHIFT5: |
11611 | case BFD_RELOC_MIPS_SHIFT6: | |
11612 | case BFD_RELOC_MIPS_GOT_DISP: | |
11613 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11614 | case BFD_RELOC_MIPS_GOT_OFST: | |
11615 | case BFD_RELOC_MIPS_SUB: | |
11616 | case BFD_RELOC_MIPS_INSERT_A: | |
11617 | case BFD_RELOC_MIPS_INSERT_B: | |
11618 | case BFD_RELOC_MIPS_DELETE: | |
11619 | case BFD_RELOC_MIPS_HIGHEST: | |
11620 | case BFD_RELOC_MIPS_HIGHER: | |
11621 | case BFD_RELOC_MIPS_SCN_DISP: | |
11622 | case BFD_RELOC_MIPS_REL16: | |
11623 | case BFD_RELOC_MIPS_RELGOT: | |
11624 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11625 | case BFD_RELOC_HI16: |
11626 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11627 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11628 | case BFD_RELOC_MIPS_LITERAL: |
11629 | case BFD_RELOC_MIPS_CALL16: | |
11630 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11631 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11632 | case BFD_RELOC_MIPS_GOT_HI16: |
11633 | case BFD_RELOC_MIPS_GOT_LO16: | |
11634 | case BFD_RELOC_MIPS_CALL_HI16: | |
11635 | case BFD_RELOC_MIPS_CALL_LO16: | |
11636 | case BFD_RELOC_MIPS16_GPREL: | |
11637 | if (fixP->fx_pcrel) | |
11638 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11639 | _("Invalid PC relative reloc")); | |
11640 | /* Nothing needed to do. The value comes from the reloc entry */ | |
11641 | break; | |
11642 | ||
11643 | case BFD_RELOC_MIPS16_JMP: | |
11644 | /* We currently always generate a reloc against a symbol, which | |
11645 | means that we don't want an addend even if the symbol is | |
11646 | defined. */ | |
a7ebbfdf | 11647 | *valP = 0; |
252b5132 RH |
11648 | break; |
11649 | ||
11650 | case BFD_RELOC_PCREL_HI16_S: | |
11651 | /* The addend for this is tricky if it is internal, so we just | |
11652 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11653 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11654 | break; |
11655 | if (fixP->fx_addsy | |
11656 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
11657 | { |
11658 | /* For an external symbol adjust by the address to make it | |
11659 | pcrel_offset. We use the address of the RELLO reloc | |
11660 | which follows this one. */ | |
a7ebbfdf | 11661 | *valP += (fixP->fx_next->fx_frag->fr_address |
252b5132 RH |
11662 | + fixP->fx_next->fx_where); |
11663 | } | |
a7ebbfdf | 11664 | *valP = ((*valP + 0x8000) >> 16) & 0xffff; |
252b5132 RH |
11665 | if (target_big_endian) |
11666 | buf += 2; | |
a7ebbfdf | 11667 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11668 | break; |
11669 | ||
11670 | case BFD_RELOC_PCREL_LO16: | |
11671 | /* The addend for this is tricky if it is internal, so we just | |
11672 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11673 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11674 | break; |
11675 | if (fixP->fx_addsy | |
11676 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
a7ebbfdf | 11677 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
252b5132 RH |
11678 | if (target_big_endian) |
11679 | buf += 2; | |
a7ebbfdf | 11680 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11681 | break; |
11682 | ||
11683 | case BFD_RELOC_64: | |
11684 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11685 | extended value if we are only 32 bits. */ | |
11686 | if (fixP->fx_done | |
11687 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11688 | { | |
11689 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 11690 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11691 | else |
11692 | { | |
a7ebbfdf | 11693 | valueT hiv; |
252b5132 | 11694 | |
a7ebbfdf | 11695 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11696 | hiv = 0xffffffff; |
11697 | else | |
11698 | hiv = 0; | |
a7ebbfdf TS |
11699 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11700 | *valP, 4); | |
11701 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11702 | hiv, 4); | |
252b5132 RH |
11703 | } |
11704 | } | |
11705 | break; | |
11706 | ||
056350c6 | 11707 | case BFD_RELOC_RVA: |
252b5132 RH |
11708 | case BFD_RELOC_32: |
11709 | /* If we are deleting this reloc entry, we must fill in the | |
11710 | value now. This can happen if we have a .word which is not | |
11711 | resolved when it appears but is later defined. We also need | |
11712 | to fill in the value if this is an embedded PIC switch table | |
11713 | entry. */ | |
11714 | if (fixP->fx_done | |
11715 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
a7ebbfdf | 11716 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11717 | break; |
11718 | ||
11719 | case BFD_RELOC_16: | |
11720 | /* If we are deleting this reloc entry, we must fill in the | |
11721 | value now. */ | |
11722 | assert (fixP->fx_size == 2); | |
11723 | if (fixP->fx_done) | |
a7ebbfdf | 11724 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11725 | break; |
11726 | ||
11727 | case BFD_RELOC_LO16: | |
11728 | /* When handling an embedded PIC switch statement, we can wind | |
11729 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11730 | if (fixP->fx_done) | |
11731 | { | |
a7ebbfdf | 11732 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11733 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11734 | _("relocation overflow")); | |
252b5132 RH |
11735 | if (target_big_endian) |
11736 | buf += 2; | |
a7ebbfdf | 11737 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11738 | } |
11739 | break; | |
11740 | ||
11741 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11742 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11743 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11744 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11745 | |
252b5132 RH |
11746 | /* |
11747 | * We need to save the bits in the instruction since fixup_segment() | |
11748 | * might be deleting the relocation entry (i.e., a branch within | |
11749 | * the current segment). | |
11750 | */ | |
a7ebbfdf | 11751 | if (! fixP->fx_done) |
bb2d6cd7 | 11752 | break; |
252b5132 RH |
11753 | |
11754 | /* update old instruction data */ | |
252b5132 RH |
11755 | if (target_big_endian) |
11756 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11757 | else | |
11758 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11759 | ||
a7ebbfdf TS |
11760 | if (*valP + 0x20000 <= 0x3ffff) |
11761 | { | |
11762 | insn |= (*valP >> 2) & 0xffff; | |
11763 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
11764 | } | |
11765 | else if (mips_pic == NO_PIC | |
11766 | && fixP->fx_done | |
11767 | && fixP->fx_frag->fr_address >= text_section->vma | |
11768 | && (fixP->fx_frag->fr_address | |
11769 | < text_section->vma + text_section->_raw_size) | |
11770 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11771 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11772 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11773 | { |
11774 | /* The branch offset is too large. If this is an | |
11775 | unconditional branch, and we are not generating PIC code, | |
11776 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11777 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11778 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11779 | else |
a7ebbfdf TS |
11780 | insn = 0x08000000; /* j */ |
11781 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11782 | fixP->fx_done = 0; | |
11783 | fixP->fx_addsy = section_symbol (text_section); | |
11784 | *valP += md_pcrel_from (fixP); | |
11785 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
11786 | } | |
11787 | else | |
11788 | { | |
11789 | /* If we got here, we have branch-relaxation disabled, | |
11790 | and there's nothing we can do to fix this instruction | |
11791 | without turning it into a longer sequence. */ | |
11792 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11793 | _("Branch out of range")); | |
252b5132 | 11794 | } |
252b5132 RH |
11795 | break; |
11796 | ||
11797 | case BFD_RELOC_VTABLE_INHERIT: | |
11798 | fixP->fx_done = 0; | |
11799 | if (fixP->fx_addsy | |
11800 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11801 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11802 | S_SET_WEAK (fixP->fx_addsy); | |
11803 | break; | |
11804 | ||
11805 | case BFD_RELOC_VTABLE_ENTRY: | |
11806 | fixP->fx_done = 0; | |
11807 | break; | |
11808 | ||
11809 | default: | |
11810 | internalError (); | |
11811 | } | |
a7ebbfdf TS |
11812 | |
11813 | /* Remember value for tc_gen_reloc. */ | |
11814 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11815 | } |
11816 | ||
11817 | #if 0 | |
11818 | void | |
11819 | printInsn (oc) | |
11820 | unsigned long oc; | |
11821 | { | |
11822 | const struct mips_opcode *p; | |
11823 | int treg, sreg, dreg, shamt; | |
11824 | short imm; | |
11825 | const char *args; | |
11826 | int i; | |
11827 | ||
11828 | for (i = 0; i < NUMOPCODES; ++i) | |
11829 | { | |
11830 | p = &mips_opcodes[i]; | |
11831 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11832 | { | |
11833 | printf ("%08lx %s\t", oc, p->name); | |
11834 | treg = (oc >> 16) & 0x1f; | |
11835 | sreg = (oc >> 21) & 0x1f; | |
11836 | dreg = (oc >> 11) & 0x1f; | |
11837 | shamt = (oc >> 6) & 0x1f; | |
11838 | imm = oc; | |
11839 | for (args = p->args;; ++args) | |
11840 | { | |
11841 | switch (*args) | |
11842 | { | |
11843 | case '\0': | |
11844 | printf ("\n"); | |
11845 | break; | |
11846 | ||
11847 | case ',': | |
11848 | case '(': | |
11849 | case ')': | |
11850 | printf ("%c", *args); | |
11851 | continue; | |
11852 | ||
11853 | case 'r': | |
11854 | assert (treg == sreg); | |
11855 | printf ("$%d,$%d", treg, sreg); | |
11856 | continue; | |
11857 | ||
11858 | case 'd': | |
11859 | case 'G': | |
11860 | printf ("$%d", dreg); | |
11861 | continue; | |
11862 | ||
11863 | case 't': | |
11864 | case 'E': | |
11865 | printf ("$%d", treg); | |
11866 | continue; | |
11867 | ||
11868 | case 'k': | |
11869 | printf ("0x%x", treg); | |
11870 | continue; | |
11871 | ||
11872 | case 'b': | |
11873 | case 's': | |
11874 | printf ("$%d", sreg); | |
11875 | continue; | |
11876 | ||
11877 | case 'a': | |
11878 | printf ("0x%08lx", oc & 0x1ffffff); | |
11879 | continue; | |
11880 | ||
11881 | case 'i': | |
11882 | case 'j': | |
11883 | case 'o': | |
11884 | case 'u': | |
11885 | printf ("%d", imm); | |
11886 | continue; | |
11887 | ||
11888 | case '<': | |
11889 | case '>': | |
11890 | printf ("$%d", shamt); | |
11891 | continue; | |
11892 | ||
11893 | default: | |
11894 | internalError (); | |
11895 | } | |
11896 | break; | |
11897 | } | |
11898 | return; | |
11899 | } | |
11900 | } | |
11901 | printf (_("%08lx UNDEFINED\n"), oc); | |
11902 | } | |
11903 | #endif | |
11904 | ||
11905 | static symbolS * | |
11906 | get_symbol () | |
11907 | { | |
11908 | int c; | |
11909 | char *name; | |
11910 | symbolS *p; | |
11911 | ||
11912 | name = input_line_pointer; | |
11913 | c = get_symbol_end (); | |
11914 | p = (symbolS *) symbol_find_or_make (name); | |
11915 | *input_line_pointer = c; | |
11916 | return p; | |
11917 | } | |
11918 | ||
11919 | /* Align the current frag to a given power of two. The MIPS assembler | |
11920 | also automatically adjusts any preceding label. */ | |
11921 | ||
11922 | static void | |
11923 | mips_align (to, fill, label) | |
11924 | int to; | |
11925 | int fill; | |
11926 | symbolS *label; | |
11927 | { | |
b34976b6 | 11928 | mips_emit_delays (FALSE); |
252b5132 RH |
11929 | frag_align (to, fill, 0); |
11930 | record_alignment (now_seg, to); | |
11931 | if (label != NULL) | |
11932 | { | |
11933 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11934 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11935 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11936 | } | |
11937 | } | |
11938 | ||
11939 | /* Align to a given power of two. .align 0 turns off the automatic | |
11940 | alignment used by the data creating pseudo-ops. */ | |
11941 | ||
11942 | static void | |
11943 | s_align (x) | |
43841e91 | 11944 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11945 | { |
11946 | register int temp; | |
11947 | register long temp_fill; | |
11948 | long max_alignment = 15; | |
11949 | ||
11950 | /* | |
11951 | ||
11952 | o Note that the assembler pulls down any immediately preceeding label | |
11953 | to the aligned address. | |
11954 | o It's not documented but auto alignment is reinstated by | |
11955 | a .align pseudo instruction. | |
11956 | o Note also that after auto alignment is turned off the mips assembler | |
11957 | issues an error on attempt to assemble an improperly aligned data item. | |
11958 | We don't. | |
11959 | ||
11960 | */ | |
11961 | ||
11962 | temp = get_absolute_expression (); | |
11963 | if (temp > max_alignment) | |
11964 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11965 | else if (temp < 0) | |
11966 | { | |
11967 | as_warn (_("Alignment negative: 0 assumed.")); | |
11968 | temp = 0; | |
11969 | } | |
11970 | if (*input_line_pointer == ',') | |
11971 | { | |
f9419b05 | 11972 | ++input_line_pointer; |
252b5132 RH |
11973 | temp_fill = get_absolute_expression (); |
11974 | } | |
11975 | else | |
11976 | temp_fill = 0; | |
11977 | if (temp) | |
11978 | { | |
11979 | auto_align = 1; | |
11980 | mips_align (temp, (int) temp_fill, | |
11981 | insn_labels != NULL ? insn_labels->label : NULL); | |
11982 | } | |
11983 | else | |
11984 | { | |
11985 | auto_align = 0; | |
11986 | } | |
11987 | ||
11988 | demand_empty_rest_of_line (); | |
11989 | } | |
11990 | ||
11991 | void | |
11992 | mips_flush_pending_output () | |
11993 | { | |
b34976b6 | 11994 | mips_emit_delays (FALSE); |
252b5132 RH |
11995 | mips_clear_insn_labels (); |
11996 | } | |
11997 | ||
11998 | static void | |
11999 | s_change_sec (sec) | |
12000 | int sec; | |
12001 | { | |
12002 | segT seg; | |
12003 | ||
12004 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
12005 | .sdata and .sbss sections. We change the .data and .rdata | |
12006 | pseudo-ops to use .sdata. */ | |
12007 | if (mips_pic == EMBEDDED_PIC | |
12008 | && (sec == 'd' || sec == 'r')) | |
12009 | sec = 's'; | |
12010 | ||
12011 | #ifdef OBJ_ELF | |
12012 | /* The ELF backend needs to know that we are changing sections, so | |
12013 | that .previous works correctly. We could do something like check | |
b6ff326e | 12014 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12015 | as it would not be appropriate to use it in the section changing |
12016 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12017 | This should be cleaner, somehow. */ | |
12018 | obj_elf_section_change_hook (); | |
12019 | #endif | |
12020 | ||
b34976b6 | 12021 | mips_emit_delays (FALSE); |
252b5132 RH |
12022 | switch (sec) |
12023 | { | |
12024 | case 't': | |
12025 | s_text (0); | |
12026 | break; | |
12027 | case 'd': | |
12028 | s_data (0); | |
12029 | break; | |
12030 | case 'b': | |
12031 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12032 | demand_empty_rest_of_line (); | |
12033 | break; | |
12034 | ||
12035 | case 'r': | |
12036 | if (USE_GLOBAL_POINTER_OPT) | |
12037 | { | |
12038 | seg = subseg_new (RDATA_SECTION_NAME, | |
12039 | (subsegT) get_absolute_expression ()); | |
12040 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
12041 | { | |
12042 | bfd_set_section_flags (stdoutput, seg, | |
12043 | (SEC_ALLOC | |
12044 | | SEC_LOAD | |
12045 | | SEC_READONLY | |
12046 | | SEC_RELOC | |
12047 | | SEC_DATA)); | |
12048 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 12049 | record_alignment (seg, 4); |
252b5132 RH |
12050 | } |
12051 | demand_empty_rest_of_line (); | |
12052 | } | |
12053 | else | |
12054 | { | |
12055 | as_bad (_("No read only data section in this object file format")); | |
12056 | demand_empty_rest_of_line (); | |
12057 | return; | |
12058 | } | |
12059 | break; | |
12060 | ||
12061 | case 's': | |
12062 | if (USE_GLOBAL_POINTER_OPT) | |
12063 | { | |
12064 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
12065 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
12066 | { | |
12067 | bfd_set_section_flags (stdoutput, seg, | |
12068 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
12069 | | SEC_DATA); | |
12070 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 12071 | record_alignment (seg, 4); |
252b5132 RH |
12072 | } |
12073 | demand_empty_rest_of_line (); | |
12074 | break; | |
12075 | } | |
12076 | else | |
12077 | { | |
12078 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
12079 | demand_empty_rest_of_line (); | |
12080 | return; | |
12081 | } | |
12082 | } | |
12083 | ||
12084 | auto_align = 1; | |
12085 | } | |
b34976b6 | 12086 | |
cca86cc8 SC |
12087 | void |
12088 | s_change_section (ignore) | |
12089 | int ignore ATTRIBUTE_UNUSED; | |
12090 | { | |
7ed4a06a | 12091 | #ifdef OBJ_ELF |
cca86cc8 SC |
12092 | char *section_name; |
12093 | char c; | |
684022ea | 12094 | char next_c = 0; |
cca86cc8 SC |
12095 | int section_type; |
12096 | int section_flag; | |
12097 | int section_entry_size; | |
12098 | int section_alignment; | |
b34976b6 | 12099 | |
7ed4a06a TS |
12100 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
12101 | return; | |
12102 | ||
cca86cc8 SC |
12103 | section_name = input_line_pointer; |
12104 | c = get_symbol_end (); | |
a816d1ed AO |
12105 | if (c) |
12106 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12107 | |
4cf0dd0d TS |
12108 | /* Do we have .section Name<,"flags">? */ |
12109 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12110 | { |
4cf0dd0d TS |
12111 | /* just after name is now '\0'. */ |
12112 | *input_line_pointer = c; | |
cca86cc8 SC |
12113 | input_line_pointer = section_name; |
12114 | obj_elf_section (ignore); | |
12115 | return; | |
12116 | } | |
12117 | input_line_pointer++; | |
12118 | ||
12119 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12120 | if (c == ',') | |
12121 | section_type = get_absolute_expression (); | |
12122 | else | |
12123 | section_type = 0; | |
12124 | if (*input_line_pointer++ == ',') | |
12125 | section_flag = get_absolute_expression (); | |
12126 | else | |
12127 | section_flag = 0; | |
12128 | if (*input_line_pointer++ == ',') | |
12129 | section_entry_size = get_absolute_expression (); | |
12130 | else | |
12131 | section_entry_size = 0; | |
12132 | if (*input_line_pointer++ == ',') | |
12133 | section_alignment = get_absolute_expression (); | |
12134 | else | |
12135 | section_alignment = 0; | |
12136 | ||
a816d1ed AO |
12137 | section_name = xstrdup (section_name); |
12138 | ||
cca86cc8 SC |
12139 | obj_elf_change_section (section_name, section_type, section_flag, |
12140 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12141 | |
12142 | if (now_seg->name != section_name) | |
12143 | free (section_name); | |
7ed4a06a | 12144 | #endif /* OBJ_ELF */ |
cca86cc8 | 12145 | } |
252b5132 RH |
12146 | |
12147 | void | |
12148 | mips_enable_auto_align () | |
12149 | { | |
12150 | auto_align = 1; | |
12151 | } | |
12152 | ||
12153 | static void | |
12154 | s_cons (log_size) | |
12155 | int log_size; | |
12156 | { | |
12157 | symbolS *label; | |
12158 | ||
12159 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12160 | mips_emit_delays (FALSE); |
252b5132 RH |
12161 | if (log_size > 0 && auto_align) |
12162 | mips_align (log_size, 0, label); | |
12163 | mips_clear_insn_labels (); | |
12164 | cons (1 << log_size); | |
12165 | } | |
12166 | ||
12167 | static void | |
12168 | s_float_cons (type) | |
12169 | int type; | |
12170 | { | |
12171 | symbolS *label; | |
12172 | ||
12173 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
12174 | ||
b34976b6 | 12175 | mips_emit_delays (FALSE); |
252b5132 RH |
12176 | |
12177 | if (auto_align) | |
49309057 ILT |
12178 | { |
12179 | if (type == 'd') | |
12180 | mips_align (3, 0, label); | |
12181 | else | |
12182 | mips_align (2, 0, label); | |
12183 | } | |
252b5132 RH |
12184 | |
12185 | mips_clear_insn_labels (); | |
12186 | ||
12187 | float_cons (type); | |
12188 | } | |
12189 | ||
12190 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12191 | permitted to say | |
12192 | .globl foo .text | |
12193 | where foo is an undefined symbol, to mean that foo should be | |
12194 | considered to be the address of a function. */ | |
12195 | ||
12196 | static void | |
12197 | s_mips_globl (x) | |
43841e91 | 12198 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12199 | { |
12200 | char *name; | |
12201 | int c; | |
12202 | symbolS *symbolP; | |
12203 | flagword flag; | |
12204 | ||
12205 | name = input_line_pointer; | |
12206 | c = get_symbol_end (); | |
12207 | symbolP = symbol_find_or_make (name); | |
12208 | *input_line_pointer = c; | |
12209 | SKIP_WHITESPACE (); | |
12210 | ||
12211 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
12212 | being a function is apparently labelled as being an object. */ | |
12213 | flag = BSF_OBJECT; | |
12214 | ||
12215 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12216 | { | |
12217 | char *secname; | |
12218 | asection *sec; | |
12219 | ||
12220 | secname = input_line_pointer; | |
12221 | c = get_symbol_end (); | |
12222 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12223 | if (sec == NULL) | |
12224 | as_bad (_("%s: no such section"), secname); | |
12225 | *input_line_pointer = c; | |
12226 | ||
12227 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12228 | flag = BSF_FUNCTION; | |
12229 | } | |
12230 | ||
49309057 | 12231 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
12232 | |
12233 | S_SET_EXTERNAL (symbolP); | |
12234 | demand_empty_rest_of_line (); | |
12235 | } | |
12236 | ||
12237 | static void | |
12238 | s_option (x) | |
43841e91 | 12239 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12240 | { |
12241 | char *opt; | |
12242 | char c; | |
12243 | ||
12244 | opt = input_line_pointer; | |
12245 | c = get_symbol_end (); | |
12246 | ||
12247 | if (*opt == 'O') | |
12248 | { | |
12249 | /* FIXME: What does this mean? */ | |
12250 | } | |
12251 | else if (strncmp (opt, "pic", 3) == 0) | |
12252 | { | |
12253 | int i; | |
12254 | ||
12255 | i = atoi (opt + 3); | |
12256 | if (i == 0) | |
12257 | mips_pic = NO_PIC; | |
12258 | else if (i == 2) | |
143d77c5 | 12259 | { |
252b5132 | 12260 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12261 | mips_abicalls = TRUE; |
12262 | } | |
252b5132 RH |
12263 | else |
12264 | as_bad (_(".option pic%d not supported"), i); | |
12265 | ||
12266 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
12267 | { | |
12268 | if (g_switch_seen && g_switch_value != 0) | |
12269 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12270 | g_switch_value = 0; | |
12271 | bfd_set_gp_size (stdoutput, 0); | |
12272 | } | |
12273 | } | |
12274 | else | |
12275 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12276 | ||
12277 | *input_line_pointer = c; | |
12278 | demand_empty_rest_of_line (); | |
12279 | } | |
12280 | ||
12281 | /* This structure is used to hold a stack of .set values. */ | |
12282 | ||
e972090a NC |
12283 | struct mips_option_stack |
12284 | { | |
252b5132 RH |
12285 | struct mips_option_stack *next; |
12286 | struct mips_set_options options; | |
12287 | }; | |
12288 | ||
12289 | static struct mips_option_stack *mips_opts_stack; | |
12290 | ||
12291 | /* Handle the .set pseudo-op. */ | |
12292 | ||
12293 | static void | |
12294 | s_mipsset (x) | |
43841e91 | 12295 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12296 | { |
12297 | char *name = input_line_pointer, ch; | |
12298 | ||
12299 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12300 | ++input_line_pointer; |
252b5132 RH |
12301 | ch = *input_line_pointer; |
12302 | *input_line_pointer = '\0'; | |
12303 | ||
12304 | if (strcmp (name, "reorder") == 0) | |
12305 | { | |
12306 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
12307 | { | |
12308 | /* If we still have pending nops, we can discard them. The | |
12309 | usual nop handling will insert any that are still | |
bdaaa2e1 | 12310 | needed. */ |
252b5132 RH |
12311 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
12312 | * (mips_opts.mips16 ? 2 : 4)); | |
12313 | prev_nop_frag = NULL; | |
12314 | } | |
12315 | mips_opts.noreorder = 0; | |
12316 | } | |
12317 | else if (strcmp (name, "noreorder") == 0) | |
12318 | { | |
b34976b6 | 12319 | mips_emit_delays (TRUE); |
252b5132 RH |
12320 | mips_opts.noreorder = 1; |
12321 | mips_any_noreorder = 1; | |
12322 | } | |
12323 | else if (strcmp (name, "at") == 0) | |
12324 | { | |
12325 | mips_opts.noat = 0; | |
12326 | } | |
12327 | else if (strcmp (name, "noat") == 0) | |
12328 | { | |
12329 | mips_opts.noat = 1; | |
12330 | } | |
12331 | else if (strcmp (name, "macro") == 0) | |
12332 | { | |
12333 | mips_opts.warn_about_macros = 0; | |
12334 | } | |
12335 | else if (strcmp (name, "nomacro") == 0) | |
12336 | { | |
12337 | if (mips_opts.noreorder == 0) | |
12338 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12339 | mips_opts.warn_about_macros = 1; | |
12340 | } | |
12341 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12342 | { | |
12343 | mips_opts.nomove = 0; | |
12344 | } | |
12345 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12346 | { | |
12347 | mips_opts.nomove = 1; | |
12348 | } | |
12349 | else if (strcmp (name, "bopt") == 0) | |
12350 | { | |
12351 | mips_opts.nobopt = 0; | |
12352 | } | |
12353 | else if (strcmp (name, "nobopt") == 0) | |
12354 | { | |
12355 | mips_opts.nobopt = 1; | |
12356 | } | |
12357 | else if (strcmp (name, "mips16") == 0 | |
12358 | || strcmp (name, "MIPS-16") == 0) | |
12359 | mips_opts.mips16 = 1; | |
12360 | else if (strcmp (name, "nomips16") == 0 | |
12361 | || strcmp (name, "noMIPS-16") == 0) | |
12362 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
12363 | else if (strcmp (name, "mips3d") == 0) |
12364 | mips_opts.ase_mips3d = 1; | |
12365 | else if (strcmp (name, "nomips3d") == 0) | |
12366 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12367 | else if (strcmp (name, "mdmx") == 0) |
12368 | mips_opts.ase_mdmx = 1; | |
12369 | else if (strcmp (name, "nomdmx") == 0) | |
12370 | mips_opts.ase_mdmx = 0; | |
252b5132 RH |
12371 | else if (strncmp (name, "mips", 4) == 0) |
12372 | { | |
af7ee8bf | 12373 | int reset = 0; |
252b5132 RH |
12374 | |
12375 | /* Permit the user to change the ISA on the fly. Needless to | |
12376 | say, misuse can cause serious problems. */ | |
af7ee8bf CD |
12377 | if (strcmp (name, "mips0") == 0) |
12378 | { | |
12379 | reset = 1; | |
12380 | mips_opts.isa = file_mips_isa; | |
12381 | } | |
12382 | else if (strcmp (name, "mips1") == 0) | |
12383 | mips_opts.isa = ISA_MIPS1; | |
12384 | else if (strcmp (name, "mips2") == 0) | |
12385 | mips_opts.isa = ISA_MIPS2; | |
12386 | else if (strcmp (name, "mips3") == 0) | |
12387 | mips_opts.isa = ISA_MIPS3; | |
12388 | else if (strcmp (name, "mips4") == 0) | |
12389 | mips_opts.isa = ISA_MIPS4; | |
12390 | else if (strcmp (name, "mips5") == 0) | |
12391 | mips_opts.isa = ISA_MIPS5; | |
12392 | else if (strcmp (name, "mips32") == 0) | |
12393 | mips_opts.isa = ISA_MIPS32; | |
12394 | else if (strcmp (name, "mips32r2") == 0) | |
12395 | mips_opts.isa = ISA_MIPS32R2; | |
12396 | else if (strcmp (name, "mips64") == 0) | |
12397 | mips_opts.isa = ISA_MIPS64; | |
12398 | else | |
12399 | as_bad (_("unknown ISA level %s"), name + 4); | |
12400 | ||
12401 | switch (mips_opts.isa) | |
98d3f06f KH |
12402 | { |
12403 | case 0: | |
98d3f06f | 12404 | break; |
af7ee8bf CD |
12405 | case ISA_MIPS1: |
12406 | case ISA_MIPS2: | |
12407 | case ISA_MIPS32: | |
12408 | case ISA_MIPS32R2: | |
98d3f06f KH |
12409 | mips_opts.gp32 = 1; |
12410 | mips_opts.fp32 = 1; | |
12411 | break; | |
af7ee8bf CD |
12412 | case ISA_MIPS3: |
12413 | case ISA_MIPS4: | |
12414 | case ISA_MIPS5: | |
12415 | case ISA_MIPS64: | |
98d3f06f KH |
12416 | mips_opts.gp32 = 0; |
12417 | mips_opts.fp32 = 0; | |
12418 | break; | |
12419 | default: | |
12420 | as_bad (_("unknown ISA level %s"), name + 4); | |
12421 | break; | |
12422 | } | |
af7ee8bf | 12423 | if (reset) |
98d3f06f | 12424 | { |
af7ee8bf CD |
12425 | mips_opts.gp32 = file_mips_gp32; |
12426 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12427 | } |
252b5132 RH |
12428 | } |
12429 | else if (strcmp (name, "autoextend") == 0) | |
12430 | mips_opts.noautoextend = 0; | |
12431 | else if (strcmp (name, "noautoextend") == 0) | |
12432 | mips_opts.noautoextend = 1; | |
12433 | else if (strcmp (name, "push") == 0) | |
12434 | { | |
12435 | struct mips_option_stack *s; | |
12436 | ||
12437 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12438 | s->next = mips_opts_stack; | |
12439 | s->options = mips_opts; | |
12440 | mips_opts_stack = s; | |
12441 | } | |
12442 | else if (strcmp (name, "pop") == 0) | |
12443 | { | |
12444 | struct mips_option_stack *s; | |
12445 | ||
12446 | s = mips_opts_stack; | |
12447 | if (s == NULL) | |
12448 | as_bad (_(".set pop with no .set push")); | |
12449 | else | |
12450 | { | |
12451 | /* If we're changing the reorder mode we need to handle | |
12452 | delay slots correctly. */ | |
12453 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 12454 | mips_emit_delays (TRUE); |
252b5132 RH |
12455 | else if (! s->options.noreorder && mips_opts.noreorder) |
12456 | { | |
12457 | if (prev_nop_frag != NULL) | |
12458 | { | |
12459 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
12460 | * (mips_opts.mips16 ? 2 : 4)); | |
12461 | prev_nop_frag = NULL; | |
12462 | } | |
12463 | } | |
12464 | ||
12465 | mips_opts = s->options; | |
12466 | mips_opts_stack = s->next; | |
12467 | free (s); | |
12468 | } | |
12469 | } | |
12470 | else | |
12471 | { | |
12472 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12473 | } | |
12474 | *input_line_pointer = ch; | |
12475 | demand_empty_rest_of_line (); | |
12476 | } | |
12477 | ||
12478 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12479 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12480 | ||
12481 | static void | |
12482 | s_abicalls (ignore) | |
43841e91 | 12483 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12484 | { |
12485 | mips_pic = SVR4_PIC; | |
143d77c5 | 12486 | mips_abicalls = TRUE; |
252b5132 RH |
12487 | if (USE_GLOBAL_POINTER_OPT) |
12488 | { | |
12489 | if (g_switch_seen && g_switch_value != 0) | |
12490 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12491 | g_switch_value = 0; | |
12492 | } | |
12493 | bfd_set_gp_size (stdoutput, 0); | |
12494 | demand_empty_rest_of_line (); | |
12495 | } | |
12496 | ||
12497 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12498 | PIC code. It sets the $gp register for the function based on the | |
12499 | function address, which is in the register named in the argument. | |
12500 | This uses a relocation against _gp_disp, which is handled specially | |
12501 | by the linker. The result is: | |
12502 | lui $gp,%hi(_gp_disp) | |
12503 | addiu $gp,$gp,%lo(_gp_disp) | |
12504 | addu $gp,$gp,.cpload argument | |
12505 | The .cpload argument is normally $25 == $t9. */ | |
12506 | ||
12507 | static void | |
12508 | s_cpload (ignore) | |
43841e91 | 12509 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12510 | { |
12511 | expressionS ex; | |
12512 | int icnt = 0; | |
12513 | ||
6478892d TS |
12514 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12515 | .cpload is ignored. */ | |
12516 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12517 | { |
12518 | s_ignore (0); | |
12519 | return; | |
12520 | } | |
12521 | ||
d3ecfc59 | 12522 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12523 | if (mips_opts.noreorder == 0) |
12524 | as_warn (_(".cpload not in noreorder section")); | |
12525 | ||
12526 | ex.X_op = O_symbol; | |
12527 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
12528 | ex.X_op_symbol = NULL; | |
12529 | ex.X_add_number = 0; | |
12530 | ||
12531 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12532 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12533 | |
c9914766 TS |
12534 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
12535 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", | |
12536 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16); | |
252b5132 RH |
12537 | |
12538 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
c9914766 | 12539 | mips_gp_register, mips_gp_register, tc_get_register (0)); |
252b5132 RH |
12540 | |
12541 | demand_empty_rest_of_line (); | |
12542 | } | |
12543 | ||
6478892d TS |
12544 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12545 | .cpsetup $reg1, offset|$reg2, label | |
12546 | ||
12547 | If offset is given, this results in: | |
12548 | sd $gp, offset($sp) | |
956cd1d6 | 12549 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12550 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12551 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12552 | |
12553 | If $reg2 is given, this results in: | |
12554 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12555 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12556 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12557 | daddu $gp, $gp, $reg1 | |
12558 | $reg1 is normally $25 == $t9. */ | |
6478892d TS |
12559 | static void |
12560 | s_cpsetup (ignore) | |
12561 | int ignore ATTRIBUTE_UNUSED; | |
12562 | { | |
12563 | expressionS ex_off; | |
12564 | expressionS ex_sym; | |
12565 | int reg1; | |
12566 | int icnt = 0; | |
f21f8242 | 12567 | char *f; |
6478892d | 12568 | |
8586fc66 | 12569 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12570 | We also need NewABI support. */ |
12571 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12572 | { | |
12573 | s_ignore (0); | |
12574 | return; | |
12575 | } | |
12576 | ||
12577 | reg1 = tc_get_register (0); | |
12578 | SKIP_WHITESPACE (); | |
12579 | if (*input_line_pointer != ',') | |
12580 | { | |
12581 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12582 | return; | |
12583 | } | |
12584 | else | |
80245285 | 12585 | ++input_line_pointer; |
6478892d TS |
12586 | SKIP_WHITESPACE (); |
12587 | if (*input_line_pointer == '$') | |
80245285 TS |
12588 | { |
12589 | mips_cpreturn_register = tc_get_register (0); | |
12590 | mips_cpreturn_offset = -1; | |
12591 | } | |
6478892d | 12592 | else |
80245285 TS |
12593 | { |
12594 | mips_cpreturn_offset = get_absolute_expression (); | |
12595 | mips_cpreturn_register = -1; | |
12596 | } | |
6478892d TS |
12597 | SKIP_WHITESPACE (); |
12598 | if (*input_line_pointer != ',') | |
12599 | { | |
12600 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12601 | return; | |
12602 | } | |
12603 | else | |
f9419b05 | 12604 | ++input_line_pointer; |
6478892d | 12605 | SKIP_WHITESPACE (); |
f21f8242 | 12606 | expression (&ex_sym); |
6478892d TS |
12607 | |
12608 | if (mips_cpreturn_register == -1) | |
12609 | { | |
12610 | ex_off.X_op = O_constant; | |
12611 | ex_off.X_add_symbol = NULL; | |
12612 | ex_off.X_op_symbol = NULL; | |
12613 | ex_off.X_add_number = mips_cpreturn_offset; | |
12614 | ||
12615 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
8c1a34cd | 12616 | mips_gp_register, (int) BFD_RELOC_LO16, mips_frame_reg); |
6478892d TS |
12617 | } |
12618 | else | |
12619 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
12620 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
12621 | ||
f21f8242 AO |
12622 | /* Ensure there's room for the next two instructions, so that `f' |
12623 | doesn't end up with an address in the wrong frag. */ | |
12624 | frag_grow (8); | |
12625 | f = frag_more (0); | |
6478892d TS |
12626 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, |
12627 | (int) BFD_RELOC_GPREL16); | |
f21f8242 | 12628 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12629 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12630 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12631 | 4, NULL, 0, 0, BFD_RELOC_HI16_S); |
f21f8242 AO |
12632 | |
12633 | f = frag_more (0); | |
6478892d TS |
12634 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", |
12635 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
f21f8242 | 12636 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12637 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12638 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12639 | 4, NULL, 0, 0, BFD_RELOC_LO16); |
f21f8242 | 12640 | |
f899b4b8 TS |
12641 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
12642 | "d,v,t", mips_gp_register, mips_gp_register, reg1); | |
6478892d TS |
12643 | |
12644 | demand_empty_rest_of_line (); | |
12645 | } | |
12646 | ||
12647 | static void | |
12648 | s_cplocal (ignore) | |
12649 | int ignore ATTRIBUTE_UNUSED; | |
12650 | { | |
12651 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12652 | .cplocal is ignored. */ | |
12653 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12654 | { | |
12655 | s_ignore (0); | |
12656 | return; | |
12657 | } | |
12658 | ||
12659 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12660 | demand_empty_rest_of_line (); |
6478892d TS |
12661 | } |
12662 | ||
252b5132 RH |
12663 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12664 | offset from $sp. The offset is remembered, and after making a PIC | |
12665 | call $gp is restored from that location. */ | |
12666 | ||
12667 | static void | |
12668 | s_cprestore (ignore) | |
43841e91 | 12669 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12670 | { |
12671 | expressionS ex; | |
12672 | int icnt = 0; | |
12673 | ||
6478892d | 12674 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12675 | .cprestore is ignored. */ |
6478892d | 12676 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12677 | { |
12678 | s_ignore (0); | |
12679 | return; | |
12680 | } | |
12681 | ||
12682 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12683 | mips_cprestore_valid = 1; |
252b5132 RH |
12684 | |
12685 | ex.X_op = O_constant; | |
12686 | ex.X_add_symbol = NULL; | |
12687 | ex.X_op_symbol = NULL; | |
12688 | ex.X_add_number = mips_cprestore_offset; | |
12689 | ||
f899b4b8 | 12690 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex, ADDRESS_STORE_INSN, |
8c1a34cd | 12691 | mips_gp_register, mips_frame_reg); |
252b5132 RH |
12692 | |
12693 | demand_empty_rest_of_line (); | |
12694 | } | |
12695 | ||
6478892d TS |
12696 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
12697 | was given in the preceeding .gpsetup, it results in: | |
12698 | ld $gp, offset($sp) | |
76b3015f | 12699 | |
6478892d TS |
12700 | If a register $reg2 was given there, it results in: |
12701 | daddiu $gp, $gp, $reg2 | |
12702 | */ | |
12703 | static void | |
12704 | s_cpreturn (ignore) | |
12705 | int ignore ATTRIBUTE_UNUSED; | |
12706 | { | |
12707 | expressionS ex; | |
12708 | int icnt = 0; | |
12709 | ||
12710 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12711 | We also need NewABI support. */ | |
12712 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12713 | { | |
12714 | s_ignore (0); | |
12715 | return; | |
12716 | } | |
12717 | ||
12718 | if (mips_cpreturn_register == -1) | |
12719 | { | |
12720 | ex.X_op = O_constant; | |
12721 | ex.X_add_symbol = NULL; | |
12722 | ex.X_op_symbol = NULL; | |
12723 | ex.X_add_number = mips_cpreturn_offset; | |
12724 | ||
12725 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
8c1a34cd | 12726 | mips_gp_register, (int) BFD_RELOC_LO16, mips_frame_reg); |
6478892d TS |
12727 | } |
12728 | else | |
12729 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
12730 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
12731 | ||
12732 | demand_empty_rest_of_line (); | |
12733 | } | |
12734 | ||
12735 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12736 | code. It sets the offset to use in gp_rel relocations. */ | |
12737 | ||
12738 | static void | |
12739 | s_gpvalue (ignore) | |
12740 | int ignore ATTRIBUTE_UNUSED; | |
12741 | { | |
12742 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12743 | We also need NewABI support. */ | |
12744 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12745 | { | |
12746 | s_ignore (0); | |
12747 | return; | |
12748 | } | |
12749 | ||
def2e0dd | 12750 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12751 | |
12752 | demand_empty_rest_of_line (); | |
12753 | } | |
12754 | ||
252b5132 RH |
12755 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12756 | code. It generates a 32 bit GP relative reloc. */ | |
12757 | ||
12758 | static void | |
12759 | s_gpword (ignore) | |
43841e91 | 12760 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12761 | { |
12762 | symbolS *label; | |
12763 | expressionS ex; | |
12764 | char *p; | |
12765 | ||
12766 | /* When not generating PIC code, this is treated as .word. */ | |
12767 | if (mips_pic != SVR4_PIC) | |
12768 | { | |
12769 | s_cons (2); | |
12770 | return; | |
12771 | } | |
12772 | ||
12773 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12774 | mips_emit_delays (TRUE); |
252b5132 RH |
12775 | if (auto_align) |
12776 | mips_align (2, 0, label); | |
12777 | mips_clear_insn_labels (); | |
12778 | ||
12779 | expression (&ex); | |
12780 | ||
12781 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12782 | { | |
12783 | as_bad (_("Unsupported use of .gpword")); | |
12784 | ignore_rest_of_line (); | |
12785 | } | |
12786 | ||
12787 | p = frag_more (4); | |
12788 | md_number_to_chars (p, (valueT) 0, 4); | |
b34976b6 | 12789 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12790 | BFD_RELOC_GPREL32); |
252b5132 RH |
12791 | |
12792 | demand_empty_rest_of_line (); | |
12793 | } | |
12794 | ||
10181a0d AO |
12795 | static void |
12796 | s_gpdword (ignore) | |
12797 | int ignore ATTRIBUTE_UNUSED; | |
12798 | { | |
12799 | symbolS *label; | |
12800 | expressionS ex; | |
12801 | char *p; | |
12802 | ||
12803 | /* When not generating PIC code, this is treated as .dword. */ | |
12804 | if (mips_pic != SVR4_PIC) | |
12805 | { | |
12806 | s_cons (3); | |
12807 | return; | |
12808 | } | |
12809 | ||
12810 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12811 | mips_emit_delays (TRUE); |
10181a0d AO |
12812 | if (auto_align) |
12813 | mips_align (3, 0, label); | |
12814 | mips_clear_insn_labels (); | |
12815 | ||
12816 | expression (&ex); | |
12817 | ||
12818 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12819 | { | |
12820 | as_bad (_("Unsupported use of .gpdword")); | |
12821 | ignore_rest_of_line (); | |
12822 | } | |
12823 | ||
12824 | p = frag_more (8); | |
12825 | md_number_to_chars (p, (valueT) 0, 8); | |
a105a300 | 12826 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
10181a0d AO |
12827 | BFD_RELOC_GPREL32); |
12828 | ||
12829 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12830 | ex.X_op = O_absent; | |
12831 | ex.X_add_symbol = 0; | |
12832 | ex.X_add_number = 0; | |
b34976b6 | 12833 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12834 | BFD_RELOC_64); |
12835 | ||
12836 | demand_empty_rest_of_line (); | |
12837 | } | |
12838 | ||
252b5132 RH |
12839 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12840 | tables in SVR4 PIC code. */ | |
12841 | ||
12842 | static void | |
12843 | s_cpadd (ignore) | |
43841e91 | 12844 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12845 | { |
12846 | int icnt = 0; | |
12847 | int reg; | |
12848 | ||
10181a0d AO |
12849 | /* This is ignored when not generating SVR4 PIC code. */ |
12850 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12851 | { |
12852 | s_ignore (0); | |
12853 | return; | |
12854 | } | |
12855 | ||
12856 | /* Add $gp to the register named as an argument. */ | |
12857 | reg = tc_get_register (0); | |
f899b4b8 | 12858 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, ADDRESS_ADD_INSN, |
c9914766 | 12859 | "d,v,t", reg, reg, mips_gp_register); |
252b5132 | 12860 | |
bdaaa2e1 | 12861 | demand_empty_rest_of_line (); |
252b5132 RH |
12862 | } |
12863 | ||
12864 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12865 | mips16 mode. This permits the linker to handle them specially, | |
12866 | such as generating jalx instructions when needed. We also make | |
12867 | them odd for the duration of the assembly, in order to generate the | |
12868 | right sort of code. We will make them even in the adjust_symtab | |
12869 | routine, while leaving them marked. This is convenient for the | |
12870 | debugger and the disassembler. The linker knows to make them odd | |
12871 | again. */ | |
12872 | ||
12873 | static void | |
12874 | s_insn (ignore) | |
43841e91 | 12875 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 12876 | { |
f9419b05 | 12877 | mips16_mark_labels (); |
252b5132 RH |
12878 | |
12879 | demand_empty_rest_of_line (); | |
12880 | } | |
12881 | ||
12882 | /* Handle a .stabn directive. We need these in order to mark a label | |
12883 | as being a mips16 text label correctly. Sometimes the compiler | |
12884 | will emit a label, followed by a .stabn, and then switch sections. | |
12885 | If the label and .stabn are in mips16 mode, then the label is | |
12886 | really a mips16 text label. */ | |
12887 | ||
12888 | static void | |
12889 | s_mips_stab (type) | |
12890 | int type; | |
12891 | { | |
f9419b05 | 12892 | if (type == 'n') |
252b5132 RH |
12893 | mips16_mark_labels (); |
12894 | ||
12895 | s_stab (type); | |
12896 | } | |
12897 | ||
12898 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12899 | */ | |
12900 | ||
12901 | static void | |
12902 | s_mips_weakext (ignore) | |
43841e91 | 12903 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12904 | { |
12905 | char *name; | |
12906 | int c; | |
12907 | symbolS *symbolP; | |
12908 | expressionS exp; | |
12909 | ||
12910 | name = input_line_pointer; | |
12911 | c = get_symbol_end (); | |
12912 | symbolP = symbol_find_or_make (name); | |
12913 | S_SET_WEAK (symbolP); | |
12914 | *input_line_pointer = c; | |
12915 | ||
12916 | SKIP_WHITESPACE (); | |
12917 | ||
12918 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12919 | { | |
12920 | if (S_IS_DEFINED (symbolP)) | |
12921 | { | |
956cd1d6 | 12922 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12923 | S_GET_NAME (symbolP)); |
12924 | ignore_rest_of_line (); | |
12925 | return; | |
12926 | } | |
bdaaa2e1 | 12927 | |
252b5132 RH |
12928 | if (*input_line_pointer == ',') |
12929 | { | |
12930 | ++input_line_pointer; | |
12931 | SKIP_WHITESPACE (); | |
12932 | } | |
bdaaa2e1 | 12933 | |
252b5132 RH |
12934 | expression (&exp); |
12935 | if (exp.X_op != O_symbol) | |
12936 | { | |
12937 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12938 | ignore_rest_of_line (); |
252b5132 RH |
12939 | return; |
12940 | } | |
49309057 | 12941 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12942 | } |
12943 | ||
12944 | demand_empty_rest_of_line (); | |
12945 | } | |
12946 | ||
12947 | /* Parse a register string into a number. Called from the ECOFF code | |
12948 | to parse .frame. The argument is non-zero if this is the frame | |
12949 | register, so that we can record it in mips_frame_reg. */ | |
12950 | ||
12951 | int | |
12952 | tc_get_register (frame) | |
12953 | int frame; | |
12954 | { | |
12955 | int reg; | |
12956 | ||
12957 | SKIP_WHITESPACE (); | |
12958 | if (*input_line_pointer++ != '$') | |
12959 | { | |
12960 | as_warn (_("expected `$'")); | |
85b51719 | 12961 | reg = ZERO; |
252b5132 | 12962 | } |
3882b010 | 12963 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12964 | { |
12965 | reg = get_absolute_expression (); | |
12966 | if (reg < 0 || reg >= 32) | |
12967 | { | |
12968 | as_warn (_("Bad register number")); | |
85b51719 | 12969 | reg = ZERO; |
252b5132 RH |
12970 | } |
12971 | } | |
12972 | else | |
12973 | { | |
76db943d | 12974 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12975 | { |
12976 | reg = RA; | |
12977 | input_line_pointer += 2; | |
12978 | } | |
76db943d | 12979 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12980 | { |
12981 | reg = FP; | |
12982 | input_line_pointer += 2; | |
12983 | } | |
252b5132 | 12984 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12985 | { |
12986 | reg = SP; | |
12987 | input_line_pointer += 2; | |
12988 | } | |
252b5132 | 12989 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12990 | { |
12991 | reg = GP; | |
12992 | input_line_pointer += 2; | |
12993 | } | |
252b5132 | 12994 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12995 | { |
12996 | reg = AT; | |
12997 | input_line_pointer += 2; | |
12998 | } | |
12999 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
13000 | { | |
13001 | reg = KT0; | |
13002 | input_line_pointer += 3; | |
13003 | } | |
13004 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
13005 | { | |
13006 | reg = KT1; | |
13007 | input_line_pointer += 3; | |
13008 | } | |
13009 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
13010 | { | |
13011 | reg = ZERO; | |
13012 | input_line_pointer += 4; | |
13013 | } | |
252b5132 RH |
13014 | else |
13015 | { | |
13016 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
13017 | reg = ZERO; |
13018 | while (ISALNUM(*input_line_pointer)) | |
13019 | input_line_pointer++; | |
252b5132 | 13020 | } |
252b5132 RH |
13021 | } |
13022 | if (frame) | |
7a621144 DJ |
13023 | { |
13024 | mips_frame_reg = reg != 0 ? reg : SP; | |
13025 | mips_frame_reg_valid = 1; | |
13026 | mips_cprestore_valid = 0; | |
13027 | } | |
252b5132 RH |
13028 | return reg; |
13029 | } | |
13030 | ||
13031 | valueT | |
13032 | md_section_align (seg, addr) | |
13033 | asection *seg; | |
13034 | valueT addr; | |
13035 | { | |
13036 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13037 | ||
13038 | #ifdef OBJ_ELF | |
13039 | /* We don't need to align ELF sections to the full alignment. | |
13040 | However, Irix 5 may prefer that we align them at least to a 16 | |
13041 | byte boundary. We don't bother to align the sections if we are | |
13042 | targeted for an embedded system. */ | |
13043 | if (strcmp (TARGET_OS, "elf") == 0) | |
13044 | return addr; | |
13045 | if (align > 4) | |
13046 | align = 4; | |
13047 | #endif | |
13048 | ||
13049 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13050 | } | |
13051 | ||
13052 | /* Utility routine, called from above as well. If called while the | |
13053 | input file is still being read, it's only an approximation. (For | |
13054 | example, a symbol may later become defined which appeared to be | |
13055 | undefined earlier.) */ | |
13056 | ||
13057 | static int | |
13058 | nopic_need_relax (sym, before_relaxing) | |
13059 | symbolS *sym; | |
13060 | int before_relaxing; | |
13061 | { | |
13062 | if (sym == 0) | |
13063 | return 0; | |
13064 | ||
6478892d | 13065 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
13066 | { |
13067 | const char *symname; | |
13068 | int change; | |
13069 | ||
c9914766 | 13070 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13071 | register. It can be if it is smaller than the -G size or if |
13072 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13073 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13074 | they can. */ |
13075 | symname = S_GET_NAME (sym); | |
13076 | if (symname != (const char *) NULL | |
13077 | && (strcmp (symname, "eprol") == 0 | |
13078 | || strcmp (symname, "etext") == 0 | |
13079 | || strcmp (symname, "_gp") == 0 | |
13080 | || strcmp (symname, "edata") == 0 | |
13081 | || strcmp (symname, "_fbss") == 0 | |
13082 | || strcmp (symname, "_fdata") == 0 | |
13083 | || strcmp (symname, "_ftext") == 0 | |
13084 | || strcmp (symname, "end") == 0 | |
13085 | || strcmp (symname, "_gp_disp") == 0)) | |
13086 | change = 1; | |
13087 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13088 | && (0 | |
13089 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13090 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13091 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13092 | <= g_switch_value)) | |
252b5132 RH |
13093 | #endif |
13094 | /* We must defer this decision until after the whole | |
13095 | file has been read, since there might be a .extern | |
13096 | after the first use of this symbol. */ | |
13097 | || (before_relaxing | |
13098 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13099 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13100 | #endif |
13101 | && S_GET_VALUE (sym) == 0) | |
13102 | || (S_GET_VALUE (sym) != 0 | |
13103 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13104 | change = 0; | |
13105 | else | |
13106 | { | |
13107 | const char *segname; | |
13108 | ||
13109 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13110 | assert (strcmp (segname, ".lit8") != 0 | |
13111 | && strcmp (segname, ".lit4") != 0); | |
13112 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13113 | && strcmp (segname, ".sbss") != 0 |
13114 | && strncmp (segname, ".sdata.", 7) != 0 | |
13115 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
13116 | } |
13117 | return change; | |
13118 | } | |
13119 | else | |
c9914766 | 13120 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13121 | return 1; |
13122 | } | |
13123 | ||
5919d012 RS |
13124 | |
13125 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13126 | ||
13127 | static bfd_boolean | |
13128 | pic_need_relax (sym, segtype) | |
13129 | symbolS *sym; | |
13130 | asection *segtype; | |
13131 | { | |
13132 | asection *symsec; | |
13133 | bfd_boolean linkonce; | |
13134 | ||
13135 | /* Handle the case of a symbol equated to another symbol. */ | |
13136 | while (symbol_equated_reloc_p (sym)) | |
13137 | { | |
13138 | symbolS *n; | |
13139 | ||
13140 | /* It's possible to get a loop here in a badly written | |
13141 | program. */ | |
13142 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
13143 | if (n == sym) | |
13144 | break; | |
13145 | sym = n; | |
13146 | } | |
13147 | ||
13148 | symsec = S_GET_SEGMENT (sym); | |
13149 | ||
13150 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
13151 | linkonce = FALSE; | |
13152 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
13153 | { | |
13154 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
13155 | != 0) | |
13156 | linkonce = TRUE; | |
13157 | ||
13158 | /* The GNU toolchain uses an extension for ELF: a section | |
13159 | beginning with the magic string .gnu.linkonce is a linkonce | |
13160 | section. */ | |
13161 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
13162 | sizeof ".gnu.linkonce" - 1) == 0) | |
13163 | linkonce = TRUE; | |
13164 | } | |
13165 | ||
13166 | /* This must duplicate the test in adjust_reloc_syms. */ | |
13167 | return (symsec != &bfd_und_section | |
13168 | && symsec != &bfd_abs_section | |
13169 | && ! bfd_is_com_section (symsec) | |
13170 | && !linkonce | |
13171 | #ifdef OBJ_ELF | |
13172 | /* A global or weak symbol is treated as external. */ | |
13173 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
13174 | || (! S_IS_WEAK (sym) | |
13175 | && (! S_IS_EXTERNAL (sym) | |
13176 | || mips_pic == EMBEDDED_PIC))) | |
13177 | #endif | |
13178 | ); | |
13179 | } | |
13180 | ||
13181 | ||
252b5132 RH |
13182 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13183 | extended opcode. SEC is the section the frag is in. */ | |
13184 | ||
13185 | static int | |
13186 | mips16_extended_frag (fragp, sec, stretch) | |
13187 | fragS *fragp; | |
13188 | asection *sec; | |
13189 | long stretch; | |
13190 | { | |
13191 | int type; | |
13192 | register const struct mips16_immed_operand *op; | |
13193 | offsetT val; | |
13194 | int mintiny, maxtiny; | |
13195 | segT symsec; | |
98aa84af | 13196 | fragS *sym_frag; |
252b5132 RH |
13197 | |
13198 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13199 | return 0; | |
13200 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13201 | return 1; | |
13202 | ||
13203 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13204 | op = mips16_immed_operands; | |
13205 | while (op->type != type) | |
13206 | { | |
13207 | ++op; | |
13208 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13209 | } | |
13210 | ||
13211 | if (op->unsp) | |
13212 | { | |
13213 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13214 | { | |
13215 | mintiny = 1; | |
13216 | maxtiny = 1 << op->nbits; | |
13217 | } | |
13218 | else | |
13219 | { | |
13220 | mintiny = 0; | |
13221 | maxtiny = (1 << op->nbits) - 1; | |
13222 | } | |
13223 | } | |
13224 | else | |
13225 | { | |
13226 | mintiny = - (1 << (op->nbits - 1)); | |
13227 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13228 | } | |
13229 | ||
98aa84af | 13230 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13231 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13232 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13233 | |
13234 | if (op->pcrel) | |
13235 | { | |
13236 | addressT addr; | |
13237 | ||
13238 | /* We won't have the section when we are called from | |
13239 | mips_relax_frag. However, we will always have been called | |
13240 | from md_estimate_size_before_relax first. If this is a | |
13241 | branch to a different section, we mark it as such. If SEC is | |
13242 | NULL, and the frag is not marked, then it must be a branch to | |
13243 | the same section. */ | |
13244 | if (sec == NULL) | |
13245 | { | |
13246 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13247 | return 1; | |
13248 | } | |
13249 | else | |
13250 | { | |
98aa84af | 13251 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13252 | if (symsec != sec) |
13253 | { | |
13254 | fragp->fr_subtype = | |
13255 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13256 | ||
13257 | /* FIXME: We should support this, and let the linker | |
13258 | catch branches and loads that are out of range. */ | |
13259 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13260 | _("unsupported PC relative reference to different section")); | |
13261 | ||
13262 | return 1; | |
13263 | } | |
98aa84af AM |
13264 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13265 | /* Assume non-extended on the first relaxation pass. | |
13266 | The address we have calculated will be bogus if this is | |
13267 | a forward branch to another frag, as the forward frag | |
13268 | will have fr_address == 0. */ | |
13269 | return 0; | |
252b5132 RH |
13270 | } |
13271 | ||
13272 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13273 | the same section. If the relax_marker of the symbol fragment |
13274 | differs from the relax_marker of this fragment, we have not | |
13275 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13276 | in STRETCH in order to get a better estimate of the address. |
13277 | This particularly matters because of the shift bits. */ | |
13278 | if (stretch != 0 | |
98aa84af | 13279 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13280 | { |
13281 | fragS *f; | |
13282 | ||
13283 | /* Adjust stretch for any alignment frag. Note that if have | |
13284 | been expanding the earlier code, the symbol may be | |
13285 | defined in what appears to be an earlier frag. FIXME: | |
13286 | This doesn't handle the fr_subtype field, which specifies | |
13287 | a maximum number of bytes to skip when doing an | |
13288 | alignment. */ | |
98aa84af | 13289 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13290 | { |
13291 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13292 | { | |
13293 | if (stretch < 0) | |
13294 | stretch = - ((- stretch) | |
13295 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13296 | else | |
13297 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13298 | if (stretch == 0) | |
13299 | break; | |
13300 | } | |
13301 | } | |
13302 | if (f != NULL) | |
13303 | val += stretch; | |
13304 | } | |
13305 | ||
13306 | addr = fragp->fr_address + fragp->fr_fix; | |
13307 | ||
13308 | /* The base address rules are complicated. The base address of | |
13309 | a branch is the following instruction. The base address of a | |
13310 | PC relative load or add is the instruction itself, but if it | |
13311 | is in a delay slot (in which case it can not be extended) use | |
13312 | the address of the instruction whose delay slot it is in. */ | |
13313 | if (type == 'p' || type == 'q') | |
13314 | { | |
13315 | addr += 2; | |
13316 | ||
13317 | /* If we are currently assuming that this frag should be | |
13318 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13319 | higher. */ |
252b5132 RH |
13320 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13321 | addr += 2; | |
13322 | ||
13323 | /* Ignore the low bit in the target, since it will be set | |
13324 | for a text label. */ | |
13325 | if ((val & 1) != 0) | |
13326 | --val; | |
13327 | } | |
13328 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13329 | addr -= 4; | |
13330 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13331 | addr -= 2; | |
13332 | ||
13333 | val -= addr & ~ ((1 << op->shift) - 1); | |
13334 | ||
13335 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13336 | if (type == 'p' || type == 'q') | |
13337 | val /= 2; | |
13338 | ||
13339 | /* If any of the shifted bits are set, we must use an extended | |
13340 | opcode. If the address depends on the size of this | |
13341 | instruction, this can lead to a loop, so we arrange to always | |
13342 | use an extended opcode. We only check this when we are in | |
13343 | the main relaxation loop, when SEC is NULL. */ | |
13344 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13345 | { | |
13346 | fragp->fr_subtype = | |
13347 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13348 | return 1; | |
13349 | } | |
13350 | ||
13351 | /* If we are about to mark a frag as extended because the value | |
13352 | is precisely maxtiny + 1, then there is a chance of an | |
13353 | infinite loop as in the following code: | |
13354 | la $4,foo | |
13355 | .skip 1020 | |
13356 | .align 2 | |
13357 | foo: | |
13358 | In this case when the la is extended, foo is 0x3fc bytes | |
13359 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13360 | the la must be extended. To avoid this loop, we mark the | |
13361 | frag as extended if it was small, and is about to become | |
13362 | extended with a value of maxtiny + 1. */ | |
13363 | if (val == ((maxtiny + 1) << op->shift) | |
13364 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13365 | && sec == NULL) | |
13366 | { | |
13367 | fragp->fr_subtype = | |
13368 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13369 | return 1; | |
13370 | } | |
13371 | } | |
13372 | else if (symsec != absolute_section && sec != NULL) | |
13373 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13374 | ||
13375 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13376 | || val < (mintiny << op->shift) | |
13377 | || val > (maxtiny << op->shift)) | |
13378 | return 1; | |
13379 | else | |
13380 | return 0; | |
13381 | } | |
13382 | ||
4a6a3df4 AO |
13383 | /* Compute the length of a branch sequence, and adjust the |
13384 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13385 | worst-case length is computed, with UPDATE being used to indicate | |
13386 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13387 | branch is to be computed. */ | |
13388 | static int | |
13389 | relaxed_branch_length (fragp, sec, update) | |
13390 | fragS *fragp; | |
13391 | asection *sec; | |
13392 | int update; | |
13393 | { | |
b34976b6 | 13394 | bfd_boolean toofar; |
4a6a3df4 AO |
13395 | int length; |
13396 | ||
13397 | if (fragp | |
13398 | && S_IS_DEFINED (fragp->fr_symbol) | |
13399 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13400 | { | |
13401 | addressT addr; | |
13402 | offsetT val; | |
13403 | ||
13404 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13405 | ||
13406 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13407 | ||
13408 | val -= addr; | |
13409 | ||
13410 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13411 | } | |
13412 | else if (fragp) | |
13413 | /* If the symbol is not defined or it's in a different segment, | |
13414 | assume the user knows what's going on and emit a short | |
13415 | branch. */ | |
b34976b6 | 13416 | toofar = FALSE; |
4a6a3df4 | 13417 | else |
b34976b6 | 13418 | toofar = TRUE; |
4a6a3df4 AO |
13419 | |
13420 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13421 | fragp->fr_subtype | |
af6ae2ad | 13422 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13423 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13424 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13425 | toofar); | |
13426 | ||
13427 | length = 4; | |
13428 | if (toofar) | |
13429 | { | |
13430 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13431 | length += 8; | |
13432 | ||
13433 | if (mips_pic != NO_PIC) | |
13434 | { | |
13435 | /* Additional space for PIC loading of target address. */ | |
13436 | length += 8; | |
13437 | if (mips_opts.isa == ISA_MIPS1) | |
13438 | /* Additional space for $at-stabilizing nop. */ | |
13439 | length += 4; | |
13440 | } | |
13441 | ||
13442 | /* If branch is conditional. */ | |
13443 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13444 | length += 8; | |
13445 | } | |
b34976b6 | 13446 | |
4a6a3df4 AO |
13447 | return length; |
13448 | } | |
13449 | ||
252b5132 RH |
13450 | /* Estimate the size of a frag before relaxing. Unless this is the |
13451 | mips16, we are not really relaxing here, and the final size is | |
13452 | encoded in the subtype information. For the mips16, we have to | |
13453 | decide whether we are using an extended opcode or not. */ | |
13454 | ||
252b5132 RH |
13455 | int |
13456 | md_estimate_size_before_relax (fragp, segtype) | |
13457 | fragS *fragp; | |
13458 | asection *segtype; | |
13459 | { | |
5919d012 | 13460 | int change; |
252b5132 | 13461 | |
4a6a3df4 AO |
13462 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13463 | { | |
13464 | ||
b34976b6 AM |
13465 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13466 | ||
4a6a3df4 AO |
13467 | return fragp->fr_var; |
13468 | } | |
13469 | ||
252b5132 | 13470 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13471 | /* We don't want to modify the EXTENDED bit here; it might get us |
13472 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13473 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13474 | |
13475 | if (mips_pic == NO_PIC) | |
5919d012 | 13476 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13477 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13478 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
13479 | else |
13480 | abort (); | |
13481 | ||
13482 | if (change) | |
13483 | { | |
13484 | /* Record the offset to the first reloc in the fr_opcode field. | |
13485 | This lets md_convert_frag and tc_gen_reloc know that the code | |
13486 | must be expanded. */ | |
13487 | fragp->fr_opcode = (fragp->fr_literal | |
13488 | + fragp->fr_fix | |
13489 | - RELAX_OLD (fragp->fr_subtype) | |
13490 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
13491 | /* FIXME: This really needs as_warn_where. */ | |
13492 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
13493 | as_warn (_("AT used after \".set noat\" or macro used after " |
13494 | "\".set nomacro\"")); | |
13495 | ||
13496 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
13497 | } |
13498 | ||
9a41af64 | 13499 | return 0; |
252b5132 RH |
13500 | } |
13501 | ||
13502 | /* This is called to see whether a reloc against a defined symbol | |
13503 | should be converted into a reloc against a section. Don't adjust | |
13504 | MIPS16 jump relocations, so we don't have to worry about the format | |
13505 | of the offset in the .o file. Don't adjust relocations against | |
13506 | mips16 symbols, so that the linker can find them if it needs to set | |
13507 | up a stub. */ | |
13508 | ||
13509 | int | |
13510 | mips_fix_adjustable (fixp) | |
13511 | fixS *fixp; | |
13512 | { | |
13513 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
13514 | return 0; | |
a161fe53 | 13515 | |
252b5132 RH |
13516 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13517 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13518 | return 0; | |
a161fe53 | 13519 | |
252b5132 RH |
13520 | if (fixp->fx_addsy == NULL) |
13521 | return 1; | |
a161fe53 | 13522 | |
252b5132 RH |
13523 | #ifdef OBJ_ELF |
13524 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
13525 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13526 | && fixp->fx_subsy == NULL) | |
13527 | return 0; | |
13528 | #endif | |
a161fe53 | 13529 | |
252b5132 RH |
13530 | return 1; |
13531 | } | |
13532 | ||
13533 | /* Translate internal representation of relocation info to BFD target | |
13534 | format. */ | |
13535 | ||
13536 | arelent ** | |
13537 | tc_gen_reloc (section, fixp) | |
43841e91 | 13538 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
13539 | fixS *fixp; |
13540 | { | |
13541 | static arelent *retval[4]; | |
13542 | arelent *reloc; | |
13543 | bfd_reloc_code_real_type code; | |
13544 | ||
4b0cff4e TS |
13545 | memset (retval, 0, sizeof(retval)); |
13546 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13547 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13548 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13549 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13550 | ||
13551 | if (mips_pic == EMBEDDED_PIC | |
13552 | && SWITCH_TABLE (fixp)) | |
13553 | { | |
13554 | /* For a switch table entry we use a special reloc. The addend | |
13555 | is actually the difference between the reloc address and the | |
13556 | subtrahend. */ | |
13557 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13558 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
13559 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
13560 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
13561 | } | |
13562 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
13563 | { | |
4514d474 CD |
13564 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13565 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13566 | else |
4514d474 CD |
13567 | { |
13568 | /* We use a special addend for an internal RELLO reloc. */ | |
13569 | if (symbol_section_p (fixp->fx_addsy)) | |
13570 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13571 | else | |
13572 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13573 | } | |
252b5132 RH |
13574 | } |
13575 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
13576 | { | |
13577 | assert (fixp->fx_next != NULL | |
13578 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
13579 | |
13580 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 13581 | accordingly. */ |
4514d474 CD |
13582 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13583 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 13584 | else |
4514d474 CD |
13585 | { |
13586 | /* We use a special addend for an internal RELHI reloc. */ | |
13587 | if (symbol_section_p (fixp->fx_addsy)) | |
13588 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
13589 | + fixp->fx_next->fx_where | |
13590 | - S_GET_VALUE (fixp->fx_subsy)); | |
13591 | else | |
13592 | reloc->addend = (fixp->fx_addnumber | |
13593 | + fixp->fx_next->fx_frag->fr_address | |
13594 | + fixp->fx_next->fx_where); | |
13595 | } | |
252b5132 | 13596 | } |
4514d474 CD |
13597 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13598 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
13599 | else |
13600 | { | |
13601 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
13602 | /* A gruesome hack which is a result of the gruesome gas reloc | |
13603 | handling. */ | |
13604 | reloc->addend = reloc->address; | |
13605 | else | |
13606 | reloc->addend = -reloc->address; | |
13607 | } | |
13608 | ||
13609 | /* If this is a variant frag, we may need to adjust the existing | |
13610 | reloc and generate a new one. */ | |
13611 | if (fixp->fx_frag->fr_opcode != NULL | |
ed6fb7bd SC |
13612 | && ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13613 | && ! HAVE_NEWABI) | |
f5040a92 AO |
13614 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP |
13615 | && HAVE_NEWABI) | |
252b5132 RH |
13616 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
13617 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
13618 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
13619 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
13620 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d | 13621 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
ed6fb7bd | 13622 | ) |
252b5132 RH |
13623 | { |
13624 | arelent *reloc2; | |
13625 | ||
13626 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
13627 | ||
13628 | /* If this is not the last reloc in this frag, then we have two | |
13629 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
13630 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
13631 | the second one handle all of them. */ | |
13632 | if (fixp->fx_next != NULL | |
13633 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
13634 | { | |
cdf6fd85 TS |
13635 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13636 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
13637 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
13638 | && (fixp->fx_next->fx_r_type | |
13639 | == BFD_RELOC_MIPS_GOT_LO16)) | |
13640 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
13641 | && (fixp->fx_next->fx_r_type | |
13642 | == BFD_RELOC_MIPS_CALL_LO16))); | |
13643 | retval[0] = NULL; | |
13644 | return retval; | |
13645 | } | |
13646 | ||
13647 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
13648 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
f5040a92 | 13649 | reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset; |
252b5132 | 13650 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); |
49309057 ILT |
13651 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13652 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13653 | reloc2->address = (reloc->address |
13654 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
13655 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
a7ebbfdf | 13656 | reloc2->addend = fixp->fx_addnumber - S_GET_VALUE (fixp->fx_addsy) |
f5040a92 | 13657 | + fixp->fx_frag->tc_frag_data.tc_fr_offset; |
252b5132 RH |
13658 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); |
13659 | assert (reloc2->howto != NULL); | |
13660 | ||
13661 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
13662 | { | |
13663 | arelent *reloc3; | |
13664 | ||
13665 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
252b5132 RH |
13666 | *reloc3 = *reloc2; |
13667 | reloc3->address += 4; | |
13668 | } | |
13669 | ||
13670 | if (mips_pic == NO_PIC) | |
13671 | { | |
cdf6fd85 | 13672 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
13673 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
13674 | } | |
13675 | else if (mips_pic == SVR4_PIC) | |
13676 | { | |
13677 | switch (fixp->fx_r_type) | |
13678 | { | |
13679 | default: | |
13680 | abort (); | |
13681 | case BFD_RELOC_MIPS_GOT16: | |
13682 | break; | |
252b5132 RH |
13683 | case BFD_RELOC_MIPS_GOT_LO16: |
13684 | case BFD_RELOC_MIPS_CALL_LO16: | |
ed6fb7bd SC |
13685 | if (HAVE_NEWABI) |
13686 | { | |
ed6fb7bd SC |
13687 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE; |
13688 | reloc2->howto = bfd_reloc_type_lookup | |
13689 | (stdoutput, BFD_RELOC_MIPS_GOT_OFST); | |
13690 | } | |
13691 | else | |
13692 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13693 | break; | |
f5040a92 AO |
13694 | case BFD_RELOC_MIPS_CALL16: |
13695 | case BFD_RELOC_MIPS_GOT_OFST: | |
13696 | case BFD_RELOC_MIPS_GOT_DISP: | |
13697 | if (HAVE_NEWABI) | |
13698 | { | |
13699 | /* It may seem nonsensical to relax GOT_DISP to | |
13700 | GOT_DISP, but we're actually turning a GOT_DISP | |
13701 | without offset into a GOT_DISP with an offset, | |
13702 | getting rid of the separate addition, which we can | |
13703 | do when the symbol is found to be local. */ | |
13704 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP; | |
13705 | retval[1] = NULL; | |
13706 | } | |
13707 | else | |
13708 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13709 | break; | |
252b5132 RH |
13710 | } |
13711 | } | |
13712 | else | |
13713 | abort (); | |
13714 | } | |
13715 | ||
438c16b8 TS |
13716 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13717 | entry to be used in the relocation's section offset. */ | |
13718 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13719 | { |
13720 | reloc->address = reloc->addend; | |
13721 | reloc->addend = 0; | |
13722 | } | |
13723 | ||
13724 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
13725 | fixup_segment converted a non-PC relative reloc into a PC | |
13726 | relative reloc. In such a case, we need to convert the reloc | |
13727 | code. */ | |
13728 | code = fixp->fx_r_type; | |
13729 | if (fixp->fx_pcrel) | |
13730 | { | |
13731 | switch (code) | |
13732 | { | |
13733 | case BFD_RELOC_8: | |
13734 | code = BFD_RELOC_8_PCREL; | |
13735 | break; | |
13736 | case BFD_RELOC_16: | |
13737 | code = BFD_RELOC_16_PCREL; | |
13738 | break; | |
13739 | case BFD_RELOC_32: | |
13740 | code = BFD_RELOC_32_PCREL; | |
13741 | break; | |
13742 | case BFD_RELOC_64: | |
13743 | code = BFD_RELOC_64_PCREL; | |
13744 | break; | |
13745 | case BFD_RELOC_8_PCREL: | |
13746 | case BFD_RELOC_16_PCREL: | |
13747 | case BFD_RELOC_32_PCREL: | |
13748 | case BFD_RELOC_64_PCREL: | |
13749 | case BFD_RELOC_16_PCREL_S2: | |
13750 | case BFD_RELOC_PCREL_HI16_S: | |
13751 | case BFD_RELOC_PCREL_LO16: | |
13752 | break; | |
13753 | default: | |
13754 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13755 | _("Cannot make %s relocation PC relative"), | |
13756 | bfd_get_reloc_code_name (code)); | |
13757 | } | |
13758 | } | |
13759 | ||
0b25d3e6 AO |
13760 | /* To support a PC relative reloc when generating embedded PIC code |
13761 | for ECOFF, we use a Cygnus extension. We check for that here to | |
13762 | make sure that we don't let such a reloc escape normally. */ | |
13763 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
13764 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13765 | && code == BFD_RELOC_16_PCREL_S2 | |
13766 | && mips_pic != EMBEDDED_PIC) | |
13767 | reloc->howto = NULL; | |
13768 | else | |
13769 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13770 | ||
252b5132 RH |
13771 | if (reloc->howto == NULL) |
13772 | { | |
13773 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13774 | _("Can not represent %s relocation in this object file format"), | |
13775 | bfd_get_reloc_code_name (code)); | |
13776 | retval[0] = NULL; | |
13777 | } | |
13778 | ||
13779 | return retval; | |
13780 | } | |
13781 | ||
13782 | /* Relax a machine dependent frag. This returns the amount by which | |
13783 | the current size of the frag should change. */ | |
13784 | ||
13785 | int | |
4a6a3df4 AO |
13786 | mips_relax_frag (sec, fragp, stretch) |
13787 | asection *sec; | |
252b5132 RH |
13788 | fragS *fragp; |
13789 | long stretch; | |
13790 | { | |
4a6a3df4 AO |
13791 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13792 | { | |
13793 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13794 | |
13795 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13796 | |
13797 | return fragp->fr_var - old_var; | |
13798 | } | |
13799 | ||
252b5132 RH |
13800 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13801 | return 0; | |
13802 | ||
c4e7957c | 13803 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13804 | { |
13805 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13806 | return 0; | |
13807 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13808 | return 2; | |
13809 | } | |
13810 | else | |
13811 | { | |
13812 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13813 | return 0; | |
13814 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13815 | return -2; | |
13816 | } | |
13817 | ||
13818 | return 0; | |
13819 | } | |
13820 | ||
13821 | /* Convert a machine dependent frag. */ | |
13822 | ||
13823 | void | |
13824 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 13825 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
13826 | segT asec; |
13827 | fragS *fragp; | |
13828 | { | |
13829 | int old, new; | |
13830 | char *fixptr; | |
13831 | ||
4a6a3df4 AO |
13832 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13833 | { | |
13834 | bfd_byte *buf; | |
13835 | unsigned long insn; | |
13836 | expressionS exp; | |
13837 | fixS *fixp; | |
b34976b6 | 13838 | |
4a6a3df4 AO |
13839 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13840 | ||
13841 | if (target_big_endian) | |
13842 | insn = bfd_getb32 (buf); | |
13843 | else | |
13844 | insn = bfd_getl32 (buf); | |
b34976b6 | 13845 | |
4a6a3df4 AO |
13846 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13847 | { | |
13848 | /* We generate a fixup instead of applying it right now | |
13849 | because, if there are linker relaxations, we're going to | |
13850 | need the relocations. */ | |
13851 | exp.X_op = O_symbol; | |
13852 | exp.X_add_symbol = fragp->fr_symbol; | |
13853 | exp.X_add_number = fragp->fr_offset; | |
13854 | ||
13855 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13856 | 4, &exp, 1, |
13857 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13858 | fixp->fx_file = fragp->fr_file; |
13859 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13860 | |
4a6a3df4 AO |
13861 | md_number_to_chars ((char *)buf, insn, 4); |
13862 | buf += 4; | |
13863 | } | |
13864 | else | |
13865 | { | |
13866 | int i; | |
13867 | ||
13868 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13869 | _("relaxed out-of-range branch into a jump")); | |
13870 | ||
13871 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13872 | goto uncond; | |
13873 | ||
13874 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13875 | { | |
13876 | /* Reverse the branch. */ | |
13877 | switch ((insn >> 28) & 0xf) | |
13878 | { | |
13879 | case 4: | |
13880 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13881 | have the condition reversed by tweaking a single | |
13882 | bit, and their opcodes all have 0x4???????. */ | |
13883 | assert ((insn & 0xf1000000) == 0x41000000); | |
13884 | insn ^= 0x00010000; | |
13885 | break; | |
13886 | ||
13887 | case 0: | |
13888 | /* bltz 0x04000000 bgez 0x04010000 | |
13889 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13890 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13891 | insn ^= 0x00010000; | |
13892 | break; | |
b34976b6 | 13893 | |
4a6a3df4 AO |
13894 | case 1: |
13895 | /* beq 0x10000000 bne 0x14000000 | |
13896 | blez 0x18000000 bgtz 0x1c000000 */ | |
13897 | insn ^= 0x04000000; | |
13898 | break; | |
13899 | ||
13900 | default: | |
13901 | abort (); | |
13902 | } | |
13903 | } | |
13904 | ||
13905 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13906 | { | |
13907 | /* Clear the and-link bit. */ | |
13908 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13909 | ||
13910 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13911 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13912 | insn &= ~0x00100000; | |
13913 | } | |
13914 | ||
13915 | /* Branch over the branch (if the branch was likely) or the | |
13916 | full jump (not likely case). Compute the offset from the | |
13917 | current instruction to branch to. */ | |
13918 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13919 | i = 16; | |
13920 | else | |
13921 | { | |
13922 | /* How many bytes in instructions we've already emitted? */ | |
13923 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13924 | /* How many bytes in instructions from here to the end? */ | |
13925 | i = fragp->fr_var - i; | |
13926 | } | |
13927 | /* Convert to instruction count. */ | |
13928 | i >>= 2; | |
13929 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13930 | i--; |
4a6a3df4 AO |
13931 | insn |= i; |
13932 | /* Branch over the jump. */ | |
13933 | md_number_to_chars ((char *)buf, insn, 4); | |
13934 | buf += 4; | |
13935 | ||
13936 | /* Nop */ | |
13937 | md_number_to_chars ((char*)buf, 0, 4); | |
13938 | buf += 4; | |
13939 | ||
13940 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13941 | { | |
13942 | /* beql $0, $0, 2f */ | |
13943 | insn = 0x50000000; | |
13944 | /* Compute the PC offset from the current instruction to | |
13945 | the end of the variable frag. */ | |
13946 | /* How many bytes in instructions we've already emitted? */ | |
13947 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13948 | /* How many bytes in instructions from here to the end? */ | |
13949 | i = fragp->fr_var - i; | |
13950 | /* Convert to instruction count. */ | |
13951 | i >>= 2; | |
13952 | /* Don't decrement i, because we want to branch over the | |
13953 | delay slot. */ | |
13954 | ||
13955 | insn |= i; | |
13956 | md_number_to_chars ((char *)buf, insn, 4); | |
13957 | buf += 4; | |
13958 | ||
13959 | md_number_to_chars ((char *)buf, 0, 4); | |
13960 | buf += 4; | |
13961 | } | |
13962 | ||
13963 | uncond: | |
13964 | if (mips_pic == NO_PIC) | |
13965 | { | |
13966 | /* j or jal. */ | |
13967 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13968 | ? 0x0c000000 : 0x08000000); | |
13969 | exp.X_op = O_symbol; | |
13970 | exp.X_add_symbol = fragp->fr_symbol; | |
13971 | exp.X_add_number = fragp->fr_offset; | |
13972 | ||
13973 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13974 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13975 | fixp->fx_file = fragp->fr_file; | |
13976 | fixp->fx_line = fragp->fr_line; | |
13977 | ||
13978 | md_number_to_chars ((char*)buf, insn, 4); | |
13979 | buf += 4; | |
13980 | } | |
13981 | else | |
13982 | { | |
13983 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13984 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13985 | exp.X_op = O_symbol; | |
13986 | exp.X_add_symbol = fragp->fr_symbol; | |
13987 | exp.X_add_number = fragp->fr_offset; | |
13988 | ||
13989 | if (fragp->fr_offset) | |
13990 | { | |
13991 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13992 | exp.X_add_number = 0; | |
13993 | } | |
13994 | ||
13995 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13996 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13997 | fixp->fx_file = fragp->fr_file; | |
13998 | fixp->fx_line = fragp->fr_line; | |
13999 | ||
14000 | md_number_to_chars ((char*)buf, insn, 4); | |
14001 | buf += 4; | |
b34976b6 | 14002 | |
4a6a3df4 AO |
14003 | if (mips_opts.isa == ISA_MIPS1) |
14004 | { | |
14005 | /* nop */ | |
14006 | md_number_to_chars ((char*)buf, 0, 4); | |
14007 | buf += 4; | |
14008 | } | |
14009 | ||
14010 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
14011 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14012 | ||
14013 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
14014 | 4, &exp, 0, BFD_RELOC_LO16); | |
14015 | fixp->fx_file = fragp->fr_file; | |
14016 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14017 | |
4a6a3df4 AO |
14018 | md_number_to_chars ((char*)buf, insn, 4); |
14019 | buf += 4; | |
14020 | ||
14021 | /* j(al)r $at. */ | |
14022 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14023 | insn = 0x0020f809; | |
14024 | else | |
14025 | insn = 0x00200008; | |
14026 | ||
14027 | md_number_to_chars ((char*)buf, insn, 4); | |
14028 | buf += 4; | |
14029 | } | |
14030 | } | |
14031 | ||
14032 | assert (buf == (bfd_byte *)fragp->fr_literal | |
14033 | + fragp->fr_fix + fragp->fr_var); | |
14034 | ||
14035 | fragp->fr_fix += fragp->fr_var; | |
14036 | ||
14037 | return; | |
14038 | } | |
14039 | ||
252b5132 RH |
14040 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14041 | { | |
14042 | int type; | |
14043 | register const struct mips16_immed_operand *op; | |
b34976b6 | 14044 | bfd_boolean small, ext; |
252b5132 RH |
14045 | offsetT val; |
14046 | bfd_byte *buf; | |
14047 | unsigned long insn; | |
b34976b6 | 14048 | bfd_boolean use_extend; |
252b5132 RH |
14049 | unsigned short extend; |
14050 | ||
14051 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14052 | op = mips16_immed_operands; | |
14053 | while (op->type != type) | |
14054 | ++op; | |
14055 | ||
14056 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14057 | { | |
b34976b6 AM |
14058 | small = FALSE; |
14059 | ext = TRUE; | |
252b5132 RH |
14060 | } |
14061 | else | |
14062 | { | |
b34976b6 AM |
14063 | small = TRUE; |
14064 | ext = FALSE; | |
252b5132 RH |
14065 | } |
14066 | ||
6386f3a7 | 14067 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14068 | val = S_GET_VALUE (fragp->fr_symbol); |
14069 | if (op->pcrel) | |
14070 | { | |
14071 | addressT addr; | |
14072 | ||
14073 | addr = fragp->fr_address + fragp->fr_fix; | |
14074 | ||
14075 | /* The rules for the base address of a PC relative reloc are | |
14076 | complicated; see mips16_extended_frag. */ | |
14077 | if (type == 'p' || type == 'q') | |
14078 | { | |
14079 | addr += 2; | |
14080 | if (ext) | |
14081 | addr += 2; | |
14082 | /* Ignore the low bit in the target, since it will be | |
14083 | set for a text label. */ | |
14084 | if ((val & 1) != 0) | |
14085 | --val; | |
14086 | } | |
14087 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14088 | addr -= 4; | |
14089 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14090 | addr -= 2; | |
14091 | ||
14092 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14093 | val -= addr; | |
14094 | ||
14095 | /* Make sure the section winds up with the alignment we have | |
14096 | assumed. */ | |
14097 | if (op->shift > 0) | |
14098 | record_alignment (asec, op->shift); | |
14099 | } | |
14100 | ||
14101 | if (ext | |
14102 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14103 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14104 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14105 | _("extended instruction in delay slot")); | |
14106 | ||
14107 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14108 | ||
14109 | if (target_big_endian) | |
14110 | insn = bfd_getb16 (buf); | |
14111 | else | |
14112 | insn = bfd_getl16 (buf); | |
14113 | ||
14114 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14115 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14116 | small, ext, &insn, &use_extend, &extend); | |
14117 | ||
14118 | if (use_extend) | |
14119 | { | |
874e8986 | 14120 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14121 | fragp->fr_fix += 2; |
14122 | buf += 2; | |
14123 | } | |
14124 | ||
874e8986 | 14125 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14126 | fragp->fr_fix += 2; |
14127 | buf += 2; | |
14128 | } | |
14129 | else | |
14130 | { | |
14131 | if (fragp->fr_opcode == NULL) | |
14132 | return; | |
14133 | ||
14134 | old = RELAX_OLD (fragp->fr_subtype); | |
14135 | new = RELAX_NEW (fragp->fr_subtype); | |
14136 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
14137 | ||
14138 | if (new > 0) | |
f5040a92 | 14139 | memmove (fixptr - old, fixptr, new); |
252b5132 RH |
14140 | |
14141 | fragp->fr_fix += new - old; | |
14142 | } | |
14143 | } | |
14144 | ||
14145 | #ifdef OBJ_ELF | |
14146 | ||
14147 | /* This function is called after the relocs have been generated. | |
14148 | We've been storing mips16 text labels as odd. Here we convert them | |
14149 | back to even for the convenience of the debugger. */ | |
14150 | ||
14151 | void | |
14152 | mips_frob_file_after_relocs () | |
14153 | { | |
14154 | asymbol **syms; | |
14155 | unsigned int count, i; | |
14156 | ||
14157 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
14158 | return; | |
14159 | ||
14160 | syms = bfd_get_outsymbols (stdoutput); | |
14161 | count = bfd_get_symcount (stdoutput); | |
14162 | for (i = 0; i < count; i++, syms++) | |
14163 | { | |
14164 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
14165 | && ((*syms)->value & 1) != 0) | |
14166 | { | |
14167 | (*syms)->value &= ~1; | |
14168 | /* If the symbol has an odd size, it was probably computed | |
14169 | incorrectly, so adjust that as well. */ | |
14170 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14171 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14172 | } | |
14173 | } | |
14174 | } | |
14175 | ||
14176 | #endif | |
14177 | ||
14178 | /* This function is called whenever a label is defined. It is used | |
14179 | when handling branch delays; if a branch has a label, we assume we | |
14180 | can not move it. */ | |
14181 | ||
14182 | void | |
14183 | mips_define_label (sym) | |
14184 | symbolS *sym; | |
14185 | { | |
14186 | struct insn_label_list *l; | |
14187 | ||
14188 | if (free_insn_labels == NULL) | |
14189 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14190 | else | |
14191 | { | |
14192 | l = free_insn_labels; | |
14193 | free_insn_labels = l->next; | |
14194 | } | |
14195 | ||
14196 | l->label = sym; | |
14197 | l->next = insn_labels; | |
14198 | insn_labels = l; | |
14199 | } | |
14200 | \f | |
14201 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14202 | ||
14203 | /* Some special processing for a MIPS ELF file. */ | |
14204 | ||
14205 | void | |
14206 | mips_elf_final_processing () | |
14207 | { | |
14208 | /* Write out the register information. */ | |
316f5878 | 14209 | if (mips_abi != N64_ABI) |
252b5132 RH |
14210 | { |
14211 | Elf32_RegInfo s; | |
14212 | ||
14213 | s.ri_gprmask = mips_gprmask; | |
14214 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14215 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14216 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14217 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14218 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14219 | ||
14220 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14221 | ((Elf32_External_RegInfo *) | |
14222 | mips_regmask_frag)); | |
14223 | } | |
14224 | else | |
14225 | { | |
14226 | Elf64_Internal_RegInfo s; | |
14227 | ||
14228 | s.ri_gprmask = mips_gprmask; | |
14229 | s.ri_pad = 0; | |
14230 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14231 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14232 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14233 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14234 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14235 | ||
14236 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14237 | ((Elf64_External_RegInfo *) | |
14238 | mips_regmask_frag)); | |
14239 | } | |
14240 | ||
14241 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14242 | sort of BFD interface for this. */ | |
14243 | if (mips_any_noreorder) | |
14244 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14245 | if (mips_pic != NO_PIC) | |
143d77c5 | 14246 | { |
252b5132 | 14247 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14248 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14249 | } | |
14250 | if (mips_abicalls) | |
14251 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14252 | |
98d3f06f | 14253 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
14254 | if (file_ase_mips16) |
14255 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14256 | #if 0 /* XXX FIXME */ |
14257 | if (file_ase_mips3d) | |
14258 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14259 | #endif | |
deec1734 CD |
14260 | if (file_ase_mdmx) |
14261 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14262 | |
bdaaa2e1 | 14263 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14264 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14265 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14266 | else if (mips_abi == O64_ABI) |
252b5132 | 14267 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14268 | else if (mips_abi == EABI_ABI) |
252b5132 | 14269 | { |
316f5878 | 14270 | if (!file_mips_gp32) |
252b5132 RH |
14271 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14272 | else | |
14273 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14274 | } | |
316f5878 | 14275 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14276 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14277 | ||
c9914766 | 14278 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14279 | |
14280 | if (mips_32bitmode) | |
14281 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
14282 | } | |
14283 | ||
14284 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14285 | \f | |
beae10d5 KH |
14286 | typedef struct proc { |
14287 | symbolS *isym; | |
14288 | unsigned long reg_mask; | |
14289 | unsigned long reg_offset; | |
14290 | unsigned long fpreg_mask; | |
14291 | unsigned long fpreg_offset; | |
14292 | unsigned long frame_offset; | |
14293 | unsigned long frame_reg; | |
14294 | unsigned long pc_reg; | |
14295 | } procS; | |
252b5132 RH |
14296 | |
14297 | static procS cur_proc; | |
14298 | static procS *cur_proc_ptr; | |
14299 | static int numprocs; | |
14300 | ||
0a9ef439 | 14301 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 14302 | |
0a9ef439 RH |
14303 | void |
14304 | mips_handle_align (fragp) | |
14305 | fragS *fragp; | |
a19d8eb0 | 14306 | { |
0a9ef439 RH |
14307 | if (fragp->fr_type != rs_align_code) |
14308 | return; | |
14309 | ||
14310 | if (mips_opts.mips16) | |
a19d8eb0 CP |
14311 | { |
14312 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
14313 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
14314 | ||
0a9ef439 RH |
14315 | int bytes; |
14316 | char *p; | |
a19d8eb0 | 14317 | |
0a9ef439 RH |
14318 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14319 | p = fragp->fr_literal + fragp->fr_fix; | |
14320 | ||
14321 | if (bytes & 1) | |
14322 | { | |
14323 | *p++ = 0; | |
f9419b05 | 14324 | fragp->fr_fix++; |
0a9ef439 RH |
14325 | } |
14326 | ||
14327 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14328 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14329 | } |
14330 | ||
0a9ef439 | 14331 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14332 | } |
14333 | ||
252b5132 RH |
14334 | static void |
14335 | md_obj_begin () | |
14336 | { | |
14337 | } | |
14338 | ||
14339 | static void | |
14340 | md_obj_end () | |
14341 | { | |
14342 | /* check for premature end, nesting errors, etc */ | |
14343 | if (cur_proc_ptr) | |
9a41af64 | 14344 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14345 | } |
14346 | ||
14347 | static long | |
14348 | get_number () | |
14349 | { | |
14350 | int negative = 0; | |
14351 | long val = 0; | |
14352 | ||
14353 | if (*input_line_pointer == '-') | |
14354 | { | |
14355 | ++input_line_pointer; | |
14356 | negative = 1; | |
14357 | } | |
3882b010 | 14358 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14359 | as_bad (_("expected simple number")); |
252b5132 RH |
14360 | if (input_line_pointer[0] == '0') |
14361 | { | |
14362 | if (input_line_pointer[1] == 'x') | |
14363 | { | |
14364 | input_line_pointer += 2; | |
3882b010 | 14365 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14366 | { |
14367 | val <<= 4; | |
14368 | val |= hex_value (*input_line_pointer++); | |
14369 | } | |
14370 | return negative ? -val : val; | |
14371 | } | |
14372 | else | |
14373 | { | |
14374 | ++input_line_pointer; | |
3882b010 | 14375 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14376 | { |
14377 | val <<= 3; | |
14378 | val |= *input_line_pointer++ - '0'; | |
14379 | } | |
14380 | return negative ? -val : val; | |
14381 | } | |
14382 | } | |
3882b010 | 14383 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14384 | { |
14385 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14386 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14387 | as_warn (_("invalid number")); |
252b5132 RH |
14388 | return -1; |
14389 | } | |
3882b010 | 14390 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14391 | { |
14392 | val *= 10; | |
14393 | val += *input_line_pointer++ - '0'; | |
14394 | } | |
14395 | return negative ? -val : val; | |
14396 | } | |
14397 | ||
14398 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14399 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14400 | case .file implies DWARF-2. */ | |
14401 | ||
14402 | static void | |
14403 | s_mips_file (x) | |
14404 | int x ATTRIBUTE_UNUSED; | |
14405 | { | |
ecb4347a DJ |
14406 | static int first_file_directive = 0; |
14407 | ||
c5dd6aab DJ |
14408 | if (ECOFF_DEBUGGING) |
14409 | { | |
14410 | get_number (); | |
14411 | s_app_file (0); | |
14412 | } | |
14413 | else | |
ecb4347a DJ |
14414 | { |
14415 | char *filename; | |
14416 | ||
14417 | filename = dwarf2_directive_file (0); | |
14418 | ||
14419 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14420 | directive even for stabs output. Make sure that this | |
14421 | ".file" is handled. Note that you need a version of GCC | |
14422 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14423 | if (filename != NULL && ! first_file_directive) | |
14424 | { | |
14425 | (void) new_logical_line (filename, -1); | |
14426 | s_app_file_string (filename); | |
14427 | } | |
14428 | first_file_directive = 1; | |
14429 | } | |
c5dd6aab DJ |
14430 | } |
14431 | ||
14432 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14433 | |
14434 | static void | |
c5dd6aab | 14435 | s_mips_loc (x) |
43841e91 | 14436 | int x ATTRIBUTE_UNUSED; |
252b5132 | 14437 | { |
c5dd6aab DJ |
14438 | if (!ECOFF_DEBUGGING) |
14439 | dwarf2_directive_loc (0); | |
252b5132 RH |
14440 | } |
14441 | ||
252b5132 RH |
14442 | /* The .end directive. */ |
14443 | ||
14444 | static void | |
14445 | s_mips_end (x) | |
43841e91 | 14446 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
14447 | { |
14448 | symbolS *p; | |
252b5132 | 14449 | |
7a621144 DJ |
14450 | /* Following functions need their own .frame and .cprestore directives. */ |
14451 | mips_frame_reg_valid = 0; | |
14452 | mips_cprestore_valid = 0; | |
14453 | ||
252b5132 RH |
14454 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14455 | { | |
14456 | p = get_symbol (); | |
14457 | demand_empty_rest_of_line (); | |
14458 | } | |
14459 | else | |
14460 | p = NULL; | |
14461 | ||
14949570 | 14462 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14463 | as_warn (_(".end not in text section")); |
14464 | ||
14465 | if (!cur_proc_ptr) | |
14466 | { | |
14467 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14468 | demand_empty_rest_of_line (); | |
14469 | return; | |
14470 | } | |
14471 | ||
14472 | if (p != NULL) | |
14473 | { | |
14474 | assert (S_GET_NAME (p)); | |
14475 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
14476 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
14477 | |
14478 | if (debug_type == DEBUG_STABS) | |
14479 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14480 | S_GET_NAME (p)); | |
252b5132 RH |
14481 | } |
14482 | else | |
14483 | as_warn (_(".end directive missing or unknown symbol")); | |
14484 | ||
ecb4347a DJ |
14485 | #ifdef OBJ_ELF |
14486 | /* Generate a .pdr section. */ | |
14487 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14488 | { | |
14489 | segT saved_seg = now_seg; | |
14490 | subsegT saved_subseg = now_subseg; | |
14491 | valueT dot; | |
14492 | expressionS exp; | |
14493 | char *fragp; | |
252b5132 | 14494 | |
ecb4347a | 14495 | dot = frag_now_fix (); |
252b5132 RH |
14496 | |
14497 | #ifdef md_flush_pending_output | |
ecb4347a | 14498 | md_flush_pending_output (); |
252b5132 RH |
14499 | #endif |
14500 | ||
ecb4347a DJ |
14501 | assert (pdr_seg); |
14502 | subseg_set (pdr_seg, 0); | |
252b5132 | 14503 | |
ecb4347a DJ |
14504 | /* Write the symbol. */ |
14505 | exp.X_op = O_symbol; | |
14506 | exp.X_add_symbol = p; | |
14507 | exp.X_add_number = 0; | |
14508 | emit_expr (&exp, 4); | |
252b5132 | 14509 | |
ecb4347a | 14510 | fragp = frag_more (7 * 4); |
252b5132 | 14511 | |
ecb4347a DJ |
14512 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
14513 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
14514 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
14515 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
14516 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
14517 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
14518 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14519 | |
ecb4347a DJ |
14520 | subseg_set (saved_seg, saved_subseg); |
14521 | } | |
14522 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14523 | |
14524 | cur_proc_ptr = NULL; | |
14525 | } | |
14526 | ||
14527 | /* The .aent and .ent directives. */ | |
14528 | ||
14529 | static void | |
14530 | s_mips_ent (aent) | |
14531 | int aent; | |
14532 | { | |
252b5132 | 14533 | symbolS *symbolP; |
252b5132 RH |
14534 | |
14535 | symbolP = get_symbol (); | |
14536 | if (*input_line_pointer == ',') | |
f9419b05 | 14537 | ++input_line_pointer; |
252b5132 | 14538 | SKIP_WHITESPACE (); |
3882b010 | 14539 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14540 | || *input_line_pointer == '-') |
874e8986 | 14541 | get_number (); |
252b5132 | 14542 | |
14949570 | 14543 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14544 | as_warn (_(".ent or .aent not in text section.")); |
14545 | ||
14546 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14547 | as_warn (_("missing .end")); |
252b5132 RH |
14548 | |
14549 | if (!aent) | |
14550 | { | |
7a621144 DJ |
14551 | /* This function needs its own .frame and .cprestore directives. */ |
14552 | mips_frame_reg_valid = 0; | |
14553 | mips_cprestore_valid = 0; | |
14554 | ||
252b5132 RH |
14555 | cur_proc_ptr = &cur_proc; |
14556 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14557 | ||
14558 | cur_proc_ptr->isym = symbolP; | |
14559 | ||
49309057 | 14560 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14561 | |
f9419b05 | 14562 | ++numprocs; |
ecb4347a DJ |
14563 | |
14564 | if (debug_type == DEBUG_STABS) | |
14565 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14566 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14567 | } |
14568 | ||
14569 | demand_empty_rest_of_line (); | |
14570 | } | |
14571 | ||
14572 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14573 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14574 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14575 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14576 | symbol table (in the mdebug section). */ |
14577 | ||
14578 | static void | |
14579 | s_mips_frame (ignore) | |
2b3c5a5d | 14580 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 14581 | { |
ecb4347a DJ |
14582 | #ifdef OBJ_ELF |
14583 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14584 | { | |
14585 | long val; | |
252b5132 | 14586 | |
ecb4347a DJ |
14587 | if (cur_proc_ptr == (procS *) NULL) |
14588 | { | |
14589 | as_warn (_(".frame outside of .ent")); | |
14590 | demand_empty_rest_of_line (); | |
14591 | return; | |
14592 | } | |
252b5132 | 14593 | |
ecb4347a DJ |
14594 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14595 | ||
14596 | SKIP_WHITESPACE (); | |
14597 | if (*input_line_pointer++ != ',' | |
14598 | || get_absolute_expression_and_terminator (&val) != ',') | |
14599 | { | |
14600 | as_warn (_("Bad .frame directive")); | |
14601 | --input_line_pointer; | |
14602 | demand_empty_rest_of_line (); | |
14603 | return; | |
14604 | } | |
252b5132 | 14605 | |
ecb4347a DJ |
14606 | cur_proc_ptr->frame_offset = val; |
14607 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14608 | |
252b5132 | 14609 | demand_empty_rest_of_line (); |
252b5132 | 14610 | } |
ecb4347a DJ |
14611 | else |
14612 | #endif /* OBJ_ELF */ | |
14613 | s_ignore (ignore); | |
252b5132 RH |
14614 | } |
14615 | ||
bdaaa2e1 KH |
14616 | /* The .fmask and .mask directives. If the mdebug section is present |
14617 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14618 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14619 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14620 | make reference to the ecoff symbol table (in the mdebug section). */ |
14621 | ||
14622 | static void | |
14623 | s_mips_mask (reg_type) | |
14624 | char reg_type; | |
14625 | { | |
ecb4347a DJ |
14626 | #ifdef OBJ_ELF |
14627 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14628 | { |
ecb4347a | 14629 | long mask, off; |
252b5132 | 14630 | |
ecb4347a DJ |
14631 | if (cur_proc_ptr == (procS *) NULL) |
14632 | { | |
14633 | as_warn (_(".mask/.fmask outside of .ent")); | |
14634 | demand_empty_rest_of_line (); | |
14635 | return; | |
14636 | } | |
252b5132 | 14637 | |
ecb4347a DJ |
14638 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14639 | { | |
14640 | as_warn (_("Bad .mask/.fmask directive")); | |
14641 | --input_line_pointer; | |
14642 | demand_empty_rest_of_line (); | |
14643 | return; | |
14644 | } | |
252b5132 | 14645 | |
ecb4347a DJ |
14646 | off = get_absolute_expression (); |
14647 | ||
14648 | if (reg_type == 'F') | |
14649 | { | |
14650 | cur_proc_ptr->fpreg_mask = mask; | |
14651 | cur_proc_ptr->fpreg_offset = off; | |
14652 | } | |
14653 | else | |
14654 | { | |
14655 | cur_proc_ptr->reg_mask = mask; | |
14656 | cur_proc_ptr->reg_offset = off; | |
14657 | } | |
14658 | ||
14659 | demand_empty_rest_of_line (); | |
252b5132 RH |
14660 | } |
14661 | else | |
ecb4347a DJ |
14662 | #endif /* OBJ_ELF */ |
14663 | s_ignore (reg_type); | |
252b5132 RH |
14664 | } |
14665 | ||
14666 | /* The .loc directive. */ | |
14667 | ||
14668 | #if 0 | |
14669 | static void | |
14670 | s_loc (x) | |
14671 | int x; | |
14672 | { | |
14673 | symbolS *symbolP; | |
14674 | int lineno; | |
14675 | int addroff; | |
14676 | ||
14677 | assert (now_seg == text_section); | |
14678 | ||
14679 | lineno = get_number (); | |
14680 | addroff = frag_now_fix (); | |
14681 | ||
14682 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
14683 | S_SET_TYPE (symbolP, N_SLINE); | |
14684 | S_SET_OTHER (symbolP, 0); | |
14685 | S_SET_DESC (symbolP, lineno); | |
14686 | symbolP->sy_segment = now_seg; | |
14687 | } | |
14688 | #endif | |
e7af610e | 14689 | |
316f5878 RS |
14690 | /* A table describing all the processors gas knows about. Names are |
14691 | matched in the order listed. | |
e7af610e | 14692 | |
316f5878 RS |
14693 | To ease comparison, please keep this table in the same order as |
14694 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14695 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14696 | { | |
316f5878 RS |
14697 | /* Entries for generic ISAs */ |
14698 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14699 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14700 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14701 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14702 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14703 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14704 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 RS |
14705 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
14706 | ||
14707 | /* MIPS I */ | |
14708 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14709 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14710 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14711 | ||
14712 | /* MIPS II */ | |
14713 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14714 | ||
14715 | /* MIPS III */ | |
14716 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14717 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14718 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14719 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14720 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14721 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14722 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14723 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14724 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14725 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14726 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14727 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14728 | ||
14729 | /* MIPS IV */ | |
14730 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14731 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14732 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14733 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14734 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14735 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14736 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14737 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14738 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14739 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14740 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14741 | { "r7000", 0, ISA_MIPS4, CPU_R5000 }, | |
14742 | ||
14743 | /* MIPS 32 */ | |
14744 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, | |
14745 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14746 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14747 | |
316f5878 RS |
14748 | /* MIPS 64 */ |
14749 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14750 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 14751 | |
c7a23324 | 14752 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14753 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14754 | |
316f5878 RS |
14755 | /* End marker */ |
14756 | { NULL, 0, 0, 0 } | |
14757 | }; | |
e7af610e | 14758 | |
84ea6cf2 | 14759 | |
316f5878 RS |
14760 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14761 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14762 | |
316f5878 | 14763 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14764 | |
b34976b6 | 14765 | static bfd_boolean |
316f5878 RS |
14766 | mips_strict_matching_cpu_name_p (canonical, given) |
14767 | const char *canonical, *given; | |
14768 | { | |
14769 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14770 | given++, canonical++; | |
14771 | ||
14772 | return ((*given == 0 && *canonical == 0) | |
14773 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14774 | } | |
14775 | ||
14776 | ||
14777 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14778 | CPU name. We've traditionally allowed a lot of variation here. | |
14779 | ||
14780 | Note: this function is shared between GCC and GAS. */ | |
14781 | ||
b34976b6 | 14782 | static bfd_boolean |
316f5878 RS |
14783 | mips_matching_cpu_name_p (canonical, given) |
14784 | const char *canonical, *given; | |
14785 | { | |
14786 | /* First see if the name matches exactly, or with a final "000" | |
14787 | turned into "k". */ | |
14788 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14789 | return TRUE; |
316f5878 RS |
14790 | |
14791 | /* If not, try comparing based on numerical designation alone. | |
14792 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14793 | if (TOLOWER (*given) == 'r') | |
14794 | given++; | |
14795 | if (!ISDIGIT (*given)) | |
b34976b6 | 14796 | return FALSE; |
316f5878 RS |
14797 | |
14798 | /* Skip over some well-known prefixes in the canonical name, | |
14799 | hoping to find a number there too. */ | |
14800 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14801 | canonical += 2; | |
14802 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14803 | canonical += 2; | |
14804 | else if (TOLOWER (canonical[0]) == 'r') | |
14805 | canonical += 1; | |
14806 | ||
14807 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14808 | } | |
14809 | ||
14810 | ||
14811 | /* Parse an option that takes the name of a processor as its argument. | |
14812 | OPTION is the name of the option and CPU_STRING is the argument. | |
14813 | Return the corresponding processor enumeration if the CPU_STRING is | |
14814 | recognized, otherwise report an error and return null. | |
14815 | ||
14816 | A similar function exists in GCC. */ | |
e7af610e NC |
14817 | |
14818 | static const struct mips_cpu_info * | |
316f5878 RS |
14819 | mips_parse_cpu (option, cpu_string) |
14820 | const char *option, *cpu_string; | |
e7af610e | 14821 | { |
316f5878 | 14822 | const struct mips_cpu_info *p; |
e7af610e | 14823 | |
316f5878 RS |
14824 | /* 'from-abi' selects the most compatible architecture for the given |
14825 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14826 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14827 | version. Look first at the -mgp options, if given, otherwise base | |
14828 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14829 | |
316f5878 RS |
14830 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14831 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14832 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14833 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14834 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14835 | { | |
14836 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14837 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14838 | ||
14839 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14840 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14841 | ||
14842 | if (file_mips_gp32 >= 0) | |
14843 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14844 | ||
14845 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14846 | ? ISA_MIPS3 | |
14847 | : ISA_MIPS1); | |
14848 | } | |
14849 | ||
14850 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14851 | if (strcasecmp (cpu_string, "default") == 0) | |
14852 | return 0; | |
14853 | ||
14854 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14855 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14856 | return p; | |
14857 | ||
14858 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14859 | return 0; | |
e7af610e NC |
14860 | } |
14861 | ||
316f5878 RS |
14862 | /* Return the canonical processor information for ISA (a member of the |
14863 | ISA_MIPS* enumeration). */ | |
14864 | ||
e7af610e NC |
14865 | static const struct mips_cpu_info * |
14866 | mips_cpu_info_from_isa (isa) | |
14867 | int isa; | |
14868 | { | |
14869 | int i; | |
14870 | ||
14871 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14872 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14873 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14874 | return (&mips_cpu_info_table[i]); |
14875 | ||
e972090a | 14876 | return NULL; |
e7af610e | 14877 | } |
316f5878 RS |
14878 | \f |
14879 | static void | |
14880 | show (stream, string, col_p, first_p) | |
14881 | FILE *stream; | |
14882 | const char *string; | |
14883 | int *col_p; | |
14884 | int *first_p; | |
14885 | { | |
14886 | if (*first_p) | |
14887 | { | |
14888 | fprintf (stream, "%24s", ""); | |
14889 | *col_p = 24; | |
14890 | } | |
14891 | else | |
14892 | { | |
14893 | fprintf (stream, ", "); | |
14894 | *col_p += 2; | |
14895 | } | |
e7af610e | 14896 | |
316f5878 RS |
14897 | if (*col_p + strlen (string) > 72) |
14898 | { | |
14899 | fprintf (stream, "\n%24s", ""); | |
14900 | *col_p = 24; | |
14901 | } | |
14902 | ||
14903 | fprintf (stream, "%s", string); | |
14904 | *col_p += strlen (string); | |
14905 | ||
14906 | *first_p = 0; | |
14907 | } | |
14908 | ||
14909 | void | |
14910 | md_show_usage (stream) | |
14911 | FILE *stream; | |
e7af610e | 14912 | { |
316f5878 RS |
14913 | int column, first; |
14914 | size_t i; | |
14915 | ||
14916 | fprintf (stream, _("\ | |
14917 | MIPS options:\n\ | |
14918 | -membedded-pic generate embedded position independent code\n\ | |
14919 | -EB generate big endian output\n\ | |
14920 | -EL generate little endian output\n\ | |
14921 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14922 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14923 | implicitly with the gp register [default 8]\n")); | |
14924 | fprintf (stream, _("\ | |
14925 | -mips1 generate MIPS ISA I instructions\n\ | |
14926 | -mips2 generate MIPS ISA II instructions\n\ | |
14927 | -mips3 generate MIPS ISA III instructions\n\ | |
14928 | -mips4 generate MIPS ISA IV instructions\n\ | |
14929 | -mips5 generate MIPS ISA V instructions\n\ | |
14930 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14931 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 RS |
14932 | -mips64 generate MIPS64 ISA instructions\n\ |
14933 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); | |
14934 | ||
14935 | first = 1; | |
e7af610e NC |
14936 | |
14937 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14938 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14939 | show (stream, "from-abi", &column, &first); | |
14940 | fputc ('\n', stream); | |
e7af610e | 14941 | |
316f5878 RS |
14942 | fprintf (stream, _("\ |
14943 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14944 | -no-mCPU don't generate code specific to CPU.\n\ | |
14945 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14946 | ||
14947 | first = 1; | |
14948 | ||
14949 | show (stream, "3900", &column, &first); | |
14950 | show (stream, "4010", &column, &first); | |
14951 | show (stream, "4100", &column, &first); | |
14952 | show (stream, "4650", &column, &first); | |
14953 | fputc ('\n', stream); | |
14954 | ||
14955 | fprintf (stream, _("\ | |
14956 | -mips16 generate mips16 instructions\n\ | |
14957 | -no-mips16 do not generate mips16 instructions\n")); | |
14958 | fprintf (stream, _("\ | |
14959 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ | |
14960 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14961 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14962 | -O remove unneeded NOPs and swap branches\n\ | |
14963 | -n warn about NOPs generated from macros\n\ | |
14964 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ | |
14965 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14966 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14967 | #ifdef OBJ_ELF | |
14968 | fprintf (stream, _("\ | |
14969 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14970 | -non_shared do not generate position independent code\n\ | |
14971 | -xgot assume a 32 bit GOT\n\ | |
14972 | -mabi=ABI create ABI conformant object file for:\n")); | |
14973 | ||
14974 | first = 1; | |
14975 | ||
14976 | show (stream, "32", &column, &first); | |
14977 | show (stream, "o64", &column, &first); | |
14978 | show (stream, "n32", &column, &first); | |
14979 | show (stream, "64", &column, &first); | |
14980 | show (stream, "eabi", &column, &first); | |
14981 | ||
14982 | fputc ('\n', stream); | |
14983 | ||
14984 | fprintf (stream, _("\ | |
14985 | -32 create o32 ABI object file (default)\n\ | |
14986 | -n32 create n32 ABI object file\n\ | |
14987 | -64 create 64 ABI object file\n")); | |
14988 | #endif | |
e7af610e | 14989 | } |
14e777e0 KB |
14990 | |
14991 | enum dwarf2_format | |
14992 | mips_dwarf2_format () | |
14993 | { | |
14994 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14995 | { |
14996 | #ifdef TE_IRIX | |
14997 | return dwarf2_format_64bit_irix; | |
14998 | #else | |
14999 | return dwarf2_format_64bit; | |
15000 | #endif | |
15001 | } | |
14e777e0 KB |
15002 | else |
15003 | return dwarf2_format_32bit; | |
15004 | } |