Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | /* Allow override of standard little-endian ECOFF format. */ |
108 | ||
109 | #ifndef ECOFF_LITTLE_FORMAT | |
110 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
111 | #endif | |
112 | ||
113 | extern int target_big_endian; | |
114 | ||
252b5132 | 115 | /* The name of the readonly data section. */ |
4d0d148d | 116 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 117 | ? ".rdata" \ |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
47e39b9d RS |
124 | /* Information about an instruction, including its format, operands |
125 | and fixups. */ | |
126 | struct mips_cl_insn | |
127 | { | |
128 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
129 | const struct mips_opcode *insn_mo; | |
130 | ||
131 | /* True if this is a mips16 instruction and if we want the extended | |
132 | form of INSN_MO. */ | |
133 | bfd_boolean use_extend; | |
134 | ||
135 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
136 | unsigned short extend; | |
137 | ||
138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
139 | a copy of INSN_MO->match with the operands filled in. */ | |
140 | unsigned long insn_opcode; | |
141 | ||
142 | /* The frag that contains the instruction. */ | |
143 | struct frag *frag; | |
144 | ||
145 | /* The offset into FRAG of the first instruction byte. */ | |
146 | long where; | |
147 | ||
148 | /* The relocs associated with the instruction, if any. */ | |
149 | fixS *fixp[3]; | |
150 | ||
a38419a5 RS |
151 | /* True if this entry cannot be moved from its current position. */ |
152 | unsigned int fixed_p : 1; | |
47e39b9d | 153 | |
708587a4 | 154 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
155 | unsigned int noreorder_p : 1; |
156 | ||
2fa15973 RS |
157 | /* True for mips16 instructions that jump to an absolute address. */ |
158 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
159 | }; |
160 | ||
a325df1d TS |
161 | /* The ABI to use. */ |
162 | enum mips_abi_level | |
163 | { | |
164 | NO_ABI = 0, | |
165 | O32_ABI, | |
166 | O64_ABI, | |
167 | N32_ABI, | |
168 | N64_ABI, | |
169 | EABI_ABI | |
170 | }; | |
171 | ||
172 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 173 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 174 | |
143d77c5 EC |
175 | /* Whether or not we have code that can call pic code. */ |
176 | int mips_abicalls = FALSE; | |
177 | ||
aa6975fb ILT |
178 | /* Whether or not we have code which can be put into a shared |
179 | library. */ | |
180 | static bfd_boolean mips_in_shared = TRUE; | |
181 | ||
252b5132 RH |
182 | /* This is the set of options which may be modified by the .set |
183 | pseudo-op. We use a struct so that .set push and .set pop are more | |
184 | reliable. */ | |
185 | ||
e972090a NC |
186 | struct mips_set_options |
187 | { | |
252b5132 RH |
188 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
189 | if it has not been initialized. Changed by `.set mipsN', and the | |
190 | -mipsN command line option, and the default CPU. */ | |
191 | int isa; | |
1f25f5d3 CD |
192 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
193 | if they have not been initialized. Changed by `.set <asename>', by | |
194 | command line options, and based on the default architecture. */ | |
195 | int ase_mips3d; | |
deec1734 | 196 | int ase_mdmx; |
e16bfa71 | 197 | int ase_smartmips; |
74cd071d | 198 | int ase_dsp; |
8b082fb1 | 199 | int ase_dspr2; |
ef2e4d86 | 200 | int ase_mt; |
252b5132 RH |
201 | /* Whether we are assembling for the mips16 processor. 0 if we are |
202 | not, 1 if we are, and -1 if the value has not been initialized. | |
203 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
204 | -nomips16 command line options, and the default CPU. */ | |
205 | int mips16; | |
206 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
207 | reorder' and `.set noreorder'. */ | |
208 | int noreorder; | |
741fe287 MR |
209 | /* Non-zero if we should not permit the register designated "assembler |
210 | temporary" to be used in instructions. The value is the register | |
211 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
212 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
213 | unsigned int at; | |
252b5132 RH |
214 | /* Non-zero if we should warn when a macro instruction expands into |
215 | more than one machine instruction. Changed by `.set nomacro' and | |
216 | `.set macro'. */ | |
217 | int warn_about_macros; | |
218 | /* Non-zero if we should not move instructions. Changed by `.set | |
219 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
220 | int nomove; | |
221 | /* Non-zero if we should not optimize branches by moving the target | |
222 | of the branch into the delay slot. Actually, we don't perform | |
223 | this optimization anyhow. Changed by `.set bopt' and `.set | |
224 | nobopt'. */ | |
225 | int nobopt; | |
226 | /* Non-zero if we should not autoextend mips16 instructions. | |
227 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
228 | int noautoextend; | |
a325df1d TS |
229 | /* Restrict general purpose registers and floating point registers |
230 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
231 | is passed but can changed if the assembler code uses .set mipsN. */ | |
232 | int gp32; | |
233 | int fp32; | |
fef14a42 TS |
234 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
235 | command line option, and the default CPU. */ | |
236 | int arch; | |
aed1a261 RS |
237 | /* True if ".set sym32" is in effect. */ |
238 | bfd_boolean sym32; | |
037b32b9 AN |
239 | /* True if floating-point operations are not allowed. Changed by .set |
240 | softfloat or .set hardfloat, by command line options -msoft-float or | |
241 | -mhard-float. The default is false. */ | |
242 | bfd_boolean soft_float; | |
243 | ||
244 | /* True if only single-precision floating-point operations are allowed. | |
245 | Changed by .set singlefloat or .set doublefloat, command-line options | |
246 | -msingle-float or -mdouble-float. The default is false. */ | |
247 | bfd_boolean single_float; | |
252b5132 RH |
248 | }; |
249 | ||
037b32b9 AN |
250 | /* This is the struct we use to hold the current set of options. Note |
251 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
252 | -1 to indicate that they have not been initialized. */ | |
253 | ||
a325df1d | 254 | /* True if -mgp32 was passed. */ |
a8e8e863 | 255 | static int file_mips_gp32 = -1; |
a325df1d TS |
256 | |
257 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 258 | static int file_mips_fp32 = -1; |
a325df1d | 259 | |
037b32b9 AN |
260 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
261 | static int file_mips_soft_float = 0; | |
262 | ||
263 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
264 | static int file_mips_single_float = 0; | |
252b5132 | 265 | |
e972090a NC |
266 | static struct mips_set_options mips_opts = |
267 | { | |
037b32b9 AN |
268 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
269 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
270 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
271 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
272 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
273 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 274 | }; |
252b5132 RH |
275 | |
276 | /* These variables are filled in with the masks of registers used. | |
277 | The object format code reads them and puts them in the appropriate | |
278 | place. */ | |
279 | unsigned long mips_gprmask; | |
280 | unsigned long mips_cprmask[4]; | |
281 | ||
282 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 283 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 284 | |
738f4d98 | 285 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
286 | static int file_ase_mips16; |
287 | ||
3994f87e TS |
288 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
289 | || mips_opts.isa == ISA_MIPS32R2 \ | |
290 | || mips_opts.isa == ISA_MIPS64 \ | |
291 | || mips_opts.isa == ISA_MIPS64R2) | |
292 | ||
b12dd2e4 CF |
293 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
294 | #ifdef TE_IRIX | |
1180b5a4 | 295 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 296 | #else |
1180b5a4 RS |
297 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
298 | because there's no place for any addend, the only acceptable | |
299 | expression is a bare symbol. */ | |
300 | #define MIPS_JALR_HINT_P(EXPR) \ | |
301 | (!HAVE_IN_PLACE_ADDENDS \ | |
302 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
303 | #endif |
304 | ||
1f25f5d3 CD |
305 | /* True if -mips3d was passed or implied by arguments passed on the |
306 | command line (e.g., by -march). */ | |
307 | static int file_ase_mips3d; | |
308 | ||
deec1734 CD |
309 | /* True if -mdmx was passed or implied by arguments passed on the |
310 | command line (e.g., by -march). */ | |
311 | static int file_ase_mdmx; | |
312 | ||
e16bfa71 TS |
313 | /* True if -msmartmips was passed or implied by arguments passed on the |
314 | command line (e.g., by -march). */ | |
315 | static int file_ase_smartmips; | |
316 | ||
ad3fea08 TS |
317 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
318 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 319 | |
74cd071d CF |
320 | /* True if -mdsp was passed or implied by arguments passed on the |
321 | command line (e.g., by -march). */ | |
322 | static int file_ase_dsp; | |
323 | ||
ad3fea08 TS |
324 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
325 | || mips_opts.isa == ISA_MIPS64R2) | |
326 | ||
65263ce3 TS |
327 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
328 | ||
8b082fb1 TS |
329 | /* True if -mdspr2 was passed or implied by arguments passed on the |
330 | command line (e.g., by -march). */ | |
331 | static int file_ase_dspr2; | |
332 | ||
333 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
334 | || mips_opts.isa == ISA_MIPS64R2) | |
335 | ||
ef2e4d86 CF |
336 | /* True if -mmt was passed or implied by arguments passed on the |
337 | command line (e.g., by -march). */ | |
338 | static int file_ase_mt; | |
339 | ||
ad3fea08 TS |
340 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
341 | || mips_opts.isa == ISA_MIPS64R2) | |
342 | ||
ec68c924 | 343 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 344 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 345 | static const char *mips_arch_string; |
ec68c924 EC |
346 | |
347 | /* The argument of the -mtune= flag. The architecture for which we | |
348 | are optimizing. */ | |
349 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 350 | static const char *mips_tune_string; |
ec68c924 | 351 | |
316f5878 | 352 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
353 | static int mips_32bitmode = 0; |
354 | ||
316f5878 RS |
355 | /* True if the given ABI requires 32-bit registers. */ |
356 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
357 | ||
358 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
359 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
360 | ((ABI) == N32_ABI \ | |
361 | || (ABI) == N64_ABI \ | |
316f5878 RS |
362 | || (ABI) == O64_ABI) |
363 | ||
ad3fea08 | 364 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
365 | #define ISA_HAS_64BIT_REGS(ISA) \ |
366 | ((ISA) == ISA_MIPS3 \ | |
367 | || (ISA) == ISA_MIPS4 \ | |
368 | || (ISA) == ISA_MIPS5 \ | |
369 | || (ISA) == ISA_MIPS64 \ | |
370 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 371 | |
ad3fea08 TS |
372 | /* Return true if ISA supports 64 bit wide float registers. */ |
373 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
374 | ((ISA) == ISA_MIPS3 \ | |
375 | || (ISA) == ISA_MIPS4 \ | |
376 | || (ISA) == ISA_MIPS5 \ | |
377 | || (ISA) == ISA_MIPS32R2 \ | |
378 | || (ISA) == ISA_MIPS64 \ | |
379 | || (ISA) == ISA_MIPS64R2) | |
380 | ||
af7ee8bf CD |
381 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
382 | instructions. */ | |
707bfff6 TS |
383 | #define ISA_HAS_DROR(ISA) \ |
384 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
385 | |
386 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
387 | instructions. */ | |
707bfff6 TS |
388 | #define ISA_HAS_ROR(ISA) \ |
389 | ((ISA) == ISA_MIPS32R2 \ | |
390 | || (ISA) == ISA_MIPS64R2 \ | |
391 | || mips_opts.ase_smartmips) | |
392 | ||
7455baf8 TS |
393 | /* Return true if ISA supports single-precision floats in odd registers. */ |
394 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
395 | ((ISA) == ISA_MIPS32 \ | |
396 | || (ISA) == ISA_MIPS32R2 \ | |
397 | || (ISA) == ISA_MIPS64 \ | |
398 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 399 | |
ad3fea08 TS |
400 | /* Return true if ISA supports move to/from high part of a 64-bit |
401 | floating-point register. */ | |
402 | #define ISA_HAS_MXHC1(ISA) \ | |
403 | ((ISA) == ISA_MIPS32R2 \ | |
404 | || (ISA) == ISA_MIPS64R2) | |
405 | ||
e013f690 | 406 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 407 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 408 | |
e013f690 | 409 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 410 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 411 | |
ad3fea08 TS |
412 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
413 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 414 | |
316f5878 | 415 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 416 | |
316f5878 | 417 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 418 | |
3b91255e RS |
419 | /* True if relocations are stored in-place. */ |
420 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
421 | ||
aed1a261 RS |
422 | /* The ABI-derived address size. */ |
423 | #define HAVE_64BIT_ADDRESSES \ | |
424 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
425 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 426 | |
aed1a261 RS |
427 | /* The size of symbolic constants (i.e., expressions of the form |
428 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
429 | #define HAVE_32BIT_SYMBOLS \ | |
430 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
431 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 432 | |
b7c7d6c1 TS |
433 | /* Addresses are loaded in different ways, depending on the address size |
434 | in use. The n32 ABI Documentation also mandates the use of additions | |
435 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 436 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 437 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
438 | |
439 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 440 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
441 | |
442 | #define ADDRESS_LOAD_INSN \ | |
443 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
444 | ||
445 | #define ADDRESS_STORE_INSN \ | |
446 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
447 | ||
a4672219 | 448 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
449 | #define CPU_HAS_MIPS16(cpu) \ |
450 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
451 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 452 | |
60b63b72 RS |
453 | /* True if CPU has a dror instruction. */ |
454 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
455 | ||
456 | /* True if CPU has a ror instruction. */ | |
457 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
458 | ||
dd3cbb7e NC |
459 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
460 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
461 | ||
b19e8a9b AN |
462 | /* True if CPU does not implement the all the coprocessor insns. For these |
463 | CPUs only those COP insns are accepted that are explicitly marked to be | |
464 | available on the CPU. ISA membership for COP insns is ignored. */ | |
465 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
466 | ||
c8978940 CD |
467 | /* True if mflo and mfhi can be immediately followed by instructions |
468 | which write to the HI and LO registers. | |
469 | ||
470 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
471 | (at least) two instructions between the reads of HI/LO and | |
472 | instructions which write them, and later ISAs do not. Contradicting | |
473 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
474 | the UM for the NEC Vr5000) document needing the instructions between | |
475 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
476 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
477 | earlier-ISA CPUs for which CPU documentation declares that the | |
478 | instructions are really interlocked. */ | |
479 | #define hilo_interlocks \ | |
480 | (mips_opts.isa == ISA_MIPS32 \ | |
481 | || mips_opts.isa == ISA_MIPS32R2 \ | |
482 | || mips_opts.isa == ISA_MIPS64 \ | |
483 | || mips_opts.isa == ISA_MIPS64R2 \ | |
484 | || mips_opts.arch == CPU_R4010 \ | |
485 | || mips_opts.arch == CPU_R10000 \ | |
486 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
487 | || mips_opts.arch == CPU_R14000 \ |
488 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 489 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 CD |
490 | || mips_opts.arch == CPU_VR5500 \ |
491 | ) | |
252b5132 RH |
492 | |
493 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
494 | from the GPRs after they are loaded from memory, and thus does not |
495 | require nops to be inserted. This applies to instructions marked | |
496 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
497 | level I. */ | |
252b5132 | 498 | #define gpr_interlocks \ |
e7af610e | 499 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 500 | || mips_opts.arch == CPU_R3900) |
252b5132 | 501 | |
81912461 ILT |
502 | /* Whether the processor uses hardware interlocks to avoid delays |
503 | required by coprocessor instructions, and thus does not require | |
504 | nops to be inserted. This applies to instructions marked | |
505 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
506 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
507 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
508 | levels I, II, and III. */ | |
bdaaa2e1 | 509 | /* Itbl support may require additional care here. */ |
81912461 ILT |
510 | #define cop_interlocks \ |
511 | ((mips_opts.isa != ISA_MIPS1 \ | |
512 | && mips_opts.isa != ISA_MIPS2 \ | |
513 | && mips_opts.isa != ISA_MIPS3) \ | |
514 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
515 | ) |
516 | ||
517 | /* Whether the processor uses hardware interlocks to protect reads | |
518 | from coprocessor registers after they are loaded from memory, and | |
519 | thus does not require nops to be inserted. This applies to | |
520 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
521 | requires at MIPS ISA level I. */ | |
522 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 523 | |
6b76fefe CM |
524 | /* Is this a mfhi or mflo instruction? */ |
525 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
526 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
527 | ||
528 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
529 | or writing the condition code is only possible on the coprocessors and | |
530 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 531 | condition-code flags. */ |
b19e8a9b AN |
532 | #define COP_INSN(PINFO) \ |
533 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
534 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
535 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 536 | |
252b5132 RH |
537 | /* MIPS PIC level. */ |
538 | ||
a161fe53 | 539 | enum mips_pic_level mips_pic; |
252b5132 | 540 | |
c9914766 | 541 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 542 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 543 | static int mips_big_got = 0; |
252b5132 RH |
544 | |
545 | /* 1 if trap instructions should used for overflow rather than break | |
546 | instructions. */ | |
c9914766 | 547 | static int mips_trap = 0; |
252b5132 | 548 | |
119d663a | 549 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 550 | by assembling two single width halves into two single width floating |
119d663a NC |
551 | point registers which just happen to alias the double width destination |
552 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 553 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
554 | automatically at assemble time. */ |
555 | static int mips_disable_float_construction; | |
556 | ||
252b5132 RH |
557 | /* Non-zero if any .set noreorder directives were used. */ |
558 | ||
559 | static int mips_any_noreorder; | |
560 | ||
6b76fefe CM |
561 | /* Non-zero if nops should be inserted when the register referenced in |
562 | an mfhi/mflo instruction is read in the next two instructions. */ | |
563 | static int mips_7000_hilo_fix; | |
564 | ||
02ffd3e4 | 565 | /* The size of objects in the small data section. */ |
156c2f8b | 566 | static unsigned int g_switch_value = 8; |
252b5132 RH |
567 | /* Whether the -G option was used. */ |
568 | static int g_switch_seen = 0; | |
569 | ||
570 | #define N_RMASK 0xc4 | |
571 | #define N_VFP 0xd4 | |
572 | ||
573 | /* If we can determine in advance that GP optimization won't be | |
574 | possible, we can skip the relaxation stuff that tries to produce | |
575 | GP-relative references. This makes delay slot optimization work | |
576 | better. | |
577 | ||
578 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
579 | gcc output. It needs to guess right for gcc, otherwise gcc |
580 | will put what it thinks is a GP-relative instruction in a branch | |
581 | delay slot. | |
252b5132 RH |
582 | |
583 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
584 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 585 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
586 | |
587 | /* handle of the OPCODE hash table */ | |
588 | static struct hash_control *op_hash = NULL; | |
589 | ||
590 | /* The opcode hash table we use for the mips16. */ | |
591 | static struct hash_control *mips16_op_hash = NULL; | |
592 | ||
593 | /* This array holds the chars that always start a comment. If the | |
594 | pre-processor is disabled, these aren't very useful */ | |
595 | const char comment_chars[] = "#"; | |
596 | ||
597 | /* This array holds the chars that only start a comment at the beginning of | |
598 | a line. If the line seems to have the form '# 123 filename' | |
599 | .line and .file directives will appear in the pre-processed output */ | |
600 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
601 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 602 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
603 | /* Also note that C style comments are always supported. */ |
604 | const char line_comment_chars[] = "#"; | |
605 | ||
bdaaa2e1 | 606 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 607 | const char line_separator_chars[] = ";"; |
252b5132 RH |
608 | |
609 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
610 | const char EXP_CHARS[] = "eE"; | |
611 | ||
612 | /* Chars that mean this number is a floating point constant */ | |
613 | /* As in 0f12.456 */ | |
614 | /* or 0d1.2345e12 */ | |
615 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
616 | ||
617 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
618 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
619 | but nothing is ideal around here. | |
620 | */ | |
621 | ||
622 | static char *insn_error; | |
623 | ||
624 | static int auto_align = 1; | |
625 | ||
626 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
627 | offset in the stack frame from which to restore the $gp register. | |
628 | This is set by the .cprestore pseudo-op, and saved in this | |
629 | variable. */ | |
630 | static offsetT mips_cprestore_offset = -1; | |
631 | ||
67c1ffbe | 632 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 633 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 634 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
635 | static offsetT mips_cpreturn_offset = -1; |
636 | static int mips_cpreturn_register = -1; | |
637 | static int mips_gp_register = GP; | |
def2e0dd | 638 | static int mips_gprel_offset = 0; |
6478892d | 639 | |
7a621144 DJ |
640 | /* Whether mips_cprestore_offset has been set in the current function |
641 | (or whether it has already been warned about, if not). */ | |
642 | static int mips_cprestore_valid = 0; | |
643 | ||
252b5132 RH |
644 | /* This is the register which holds the stack frame, as set by the |
645 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
646 | static int mips_frame_reg = SP; | |
647 | ||
7a621144 DJ |
648 | /* Whether mips_frame_reg has been set in the current function |
649 | (or whether it has already been warned about, if not). */ | |
650 | static int mips_frame_reg_valid = 0; | |
651 | ||
252b5132 RH |
652 | /* To output NOP instructions correctly, we need to keep information |
653 | about the previous two instructions. */ | |
654 | ||
655 | /* Whether we are optimizing. The default value of 2 means to remove | |
656 | unneeded NOPs and swap branch instructions when possible. A value | |
657 | of 1 means to not swap branches. A value of 0 means to always | |
658 | insert NOPs. */ | |
659 | static int mips_optimize = 2; | |
660 | ||
661 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
662 | equivalent to seeing no -g option at all. */ | |
663 | static int mips_debug = 0; | |
664 | ||
7d8e00cf RS |
665 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
666 | #define MAX_VR4130_NOPS 4 | |
667 | ||
668 | /* The maximum number of NOPs needed to fill delay slots. */ | |
669 | #define MAX_DELAY_NOPS 2 | |
670 | ||
671 | /* The maximum number of NOPs needed for any purpose. */ | |
672 | #define MAX_NOPS 4 | |
71400594 RS |
673 | |
674 | /* A list of previous instructions, with index 0 being the most recent. | |
675 | We need to look back MAX_NOPS instructions when filling delay slots | |
676 | or working around processor errata. We need to look back one | |
677 | instruction further if we're thinking about using history[0] to | |
678 | fill a branch delay slot. */ | |
679 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 680 | |
1e915849 RS |
681 | /* Nop instructions used by emit_nop. */ |
682 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
683 | ||
684 | /* The appropriate nop for the current mode. */ | |
685 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 686 | |
252b5132 RH |
687 | /* If this is set, it points to a frag holding nop instructions which |
688 | were inserted before the start of a noreorder section. If those | |
689 | nops turn out to be unnecessary, the size of the frag can be | |
690 | decreased. */ | |
691 | static fragS *prev_nop_frag; | |
692 | ||
693 | /* The number of nop instructions we created in prev_nop_frag. */ | |
694 | static int prev_nop_frag_holds; | |
695 | ||
696 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 697 | prev_nop_frag. */ |
252b5132 RH |
698 | static int prev_nop_frag_required; |
699 | ||
700 | /* The number of instructions we've seen since prev_nop_frag. */ | |
701 | static int prev_nop_frag_since; | |
702 | ||
703 | /* For ECOFF and ELF, relocations against symbols are done in two | |
704 | parts, with a HI relocation and a LO relocation. Each relocation | |
705 | has only 16 bits of space to store an addend. This means that in | |
706 | order for the linker to handle carries correctly, it must be able | |
707 | to locate both the HI and the LO relocation. This means that the | |
708 | relocations must appear in order in the relocation table. | |
709 | ||
710 | In order to implement this, we keep track of each unmatched HI | |
711 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 712 | corresponding LO relocation. */ |
252b5132 | 713 | |
e972090a NC |
714 | struct mips_hi_fixup |
715 | { | |
252b5132 RH |
716 | /* Next HI fixup. */ |
717 | struct mips_hi_fixup *next; | |
718 | /* This fixup. */ | |
719 | fixS *fixp; | |
720 | /* The section this fixup is in. */ | |
721 | segT seg; | |
722 | }; | |
723 | ||
724 | /* The list of unmatched HI relocs. */ | |
725 | ||
726 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
727 | ||
64bdfcaf RS |
728 | /* The frag containing the last explicit relocation operator. |
729 | Null if explicit relocations have not been used. */ | |
730 | ||
731 | static fragS *prev_reloc_op_frag; | |
732 | ||
252b5132 RH |
733 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
734 | ||
735 | #define X ILLEGAL_REG | |
e972090a NC |
736 | static const int mips32_to_16_reg_map[] = |
737 | { | |
252b5132 RH |
738 | X, X, 2, 3, 4, 5, 6, 7, |
739 | X, X, X, X, X, X, X, X, | |
740 | 0, 1, X, X, X, X, X, X, | |
741 | X, X, X, X, X, X, X, X | |
742 | }; | |
743 | #undef X | |
744 | ||
745 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
746 | ||
e972090a NC |
747 | static const unsigned int mips16_to_32_reg_map[] = |
748 | { | |
252b5132 RH |
749 | 16, 17, 2, 3, 4, 5, 6, 7 |
750 | }; | |
60b63b72 | 751 | |
71400594 RS |
752 | /* Classifies the kind of instructions we're interested in when |
753 | implementing -mfix-vr4120. */ | |
c67a084a NC |
754 | enum fix_vr4120_class |
755 | { | |
71400594 RS |
756 | FIX_VR4120_MACC, |
757 | FIX_VR4120_DMACC, | |
758 | FIX_VR4120_MULT, | |
759 | FIX_VR4120_DMULT, | |
760 | FIX_VR4120_DIV, | |
761 | FIX_VR4120_MTHILO, | |
762 | NUM_FIX_VR4120_CLASSES | |
763 | }; | |
764 | ||
c67a084a NC |
765 | /* ...likewise -mfix-loongson2f-jump. */ |
766 | static bfd_boolean mips_fix_loongson2f_jump; | |
767 | ||
768 | /* ...likewise -mfix-loongson2f-nop. */ | |
769 | static bfd_boolean mips_fix_loongson2f_nop; | |
770 | ||
771 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
772 | static bfd_boolean mips_fix_loongson2f; | |
773 | ||
71400594 RS |
774 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
775 | there must be at least one other instruction between an instruction | |
776 | of type X and an instruction of type Y. */ | |
777 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
778 | ||
779 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 780 | static int mips_fix_vr4120; |
4a6a3df4 | 781 | |
7d8e00cf RS |
782 | /* ...likewise -mfix-vr4130. */ |
783 | static int mips_fix_vr4130; | |
784 | ||
6a32d874 CM |
785 | /* ...likewise -mfix-24k. */ |
786 | static int mips_fix_24k; | |
787 | ||
d954098f DD |
788 | /* ...likewise -mfix-cn63xxp1 */ |
789 | static bfd_boolean mips_fix_cn63xxp1; | |
790 | ||
4a6a3df4 AO |
791 | /* We don't relax branches by default, since this causes us to expand |
792 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
793 | fail to compute the offset before expanding the macro to the most | |
794 | efficient expansion. */ | |
795 | ||
796 | static int mips_relax_branch; | |
252b5132 | 797 | \f |
4d7206a2 RS |
798 | /* The expansion of many macros depends on the type of symbol that |
799 | they refer to. For example, when generating position-dependent code, | |
800 | a macro that refers to a symbol may have two different expansions, | |
801 | one which uses GP-relative addresses and one which uses absolute | |
802 | addresses. When generating SVR4-style PIC, a macro may have | |
803 | different expansions for local and global symbols. | |
804 | ||
805 | We handle these situations by generating both sequences and putting | |
806 | them in variant frags. In position-dependent code, the first sequence | |
807 | will be the GP-relative one and the second sequence will be the | |
808 | absolute one. In SVR4 PIC, the first sequence will be for global | |
809 | symbols and the second will be for local symbols. | |
810 | ||
584892a6 RS |
811 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
812 | SECOND are the lengths of the two sequences in bytes. These fields | |
813 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
814 | the subtype has the following flags: | |
4d7206a2 | 815 | |
584892a6 RS |
816 | RELAX_USE_SECOND |
817 | Set if it has been decided that we should use the second | |
818 | sequence instead of the first. | |
819 | ||
820 | RELAX_SECOND_LONGER | |
821 | Set in the first variant frag if the macro's second implementation | |
822 | is longer than its first. This refers to the macro as a whole, | |
823 | not an individual relaxation. | |
824 | ||
825 | RELAX_NOMACRO | |
826 | Set in the first variant frag if the macro appeared in a .set nomacro | |
827 | block and if one alternative requires a warning but the other does not. | |
828 | ||
829 | RELAX_DELAY_SLOT | |
830 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
831 | delay slot. | |
4d7206a2 RS |
832 | |
833 | The frag's "opcode" points to the first fixup for relaxable code. | |
834 | ||
835 | Relaxable macros are generated using a sequence such as: | |
836 | ||
837 | relax_start (SYMBOL); | |
838 | ... generate first expansion ... | |
839 | relax_switch (); | |
840 | ... generate second expansion ... | |
841 | relax_end (); | |
842 | ||
843 | The code and fixups for the unwanted alternative are discarded | |
844 | by md_convert_frag. */ | |
584892a6 | 845 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 846 | |
584892a6 RS |
847 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
848 | #define RELAX_SECOND(X) ((X) & 0xff) | |
849 | #define RELAX_USE_SECOND 0x10000 | |
850 | #define RELAX_SECOND_LONGER 0x20000 | |
851 | #define RELAX_NOMACRO 0x40000 | |
852 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 853 | |
4a6a3df4 AO |
854 | /* Branch without likely bit. If label is out of range, we turn: |
855 | ||
856 | beq reg1, reg2, label | |
857 | delay slot | |
858 | ||
859 | into | |
860 | ||
861 | bne reg1, reg2, 0f | |
862 | nop | |
863 | j label | |
864 | 0: delay slot | |
865 | ||
866 | with the following opcode replacements: | |
867 | ||
868 | beq <-> bne | |
869 | blez <-> bgtz | |
870 | bltz <-> bgez | |
871 | bc1f <-> bc1t | |
872 | ||
873 | bltzal <-> bgezal (with jal label instead of j label) | |
874 | ||
875 | Even though keeping the delay slot instruction in the delay slot of | |
876 | the branch would be more efficient, it would be very tricky to do | |
877 | correctly, because we'd have to introduce a variable frag *after* | |
878 | the delay slot instruction, and expand that instead. Let's do it | |
879 | the easy way for now, even if the branch-not-taken case now costs | |
880 | one additional instruction. Out-of-range branches are not supposed | |
881 | to be common, anyway. | |
882 | ||
883 | Branch likely. If label is out of range, we turn: | |
884 | ||
885 | beql reg1, reg2, label | |
886 | delay slot (annulled if branch not taken) | |
887 | ||
888 | into | |
889 | ||
890 | beql reg1, reg2, 1f | |
891 | nop | |
892 | beql $0, $0, 2f | |
893 | nop | |
894 | 1: j[al] label | |
895 | delay slot (executed only if branch taken) | |
896 | 2: | |
897 | ||
898 | It would be possible to generate a shorter sequence by losing the | |
899 | likely bit, generating something like: | |
b34976b6 | 900 | |
4a6a3df4 AO |
901 | bne reg1, reg2, 0f |
902 | nop | |
903 | j[al] label | |
904 | delay slot (executed only if branch taken) | |
905 | 0: | |
906 | ||
907 | beql -> bne | |
908 | bnel -> beq | |
909 | blezl -> bgtz | |
910 | bgtzl -> blez | |
911 | bltzl -> bgez | |
912 | bgezl -> bltz | |
913 | bc1fl -> bc1t | |
914 | bc1tl -> bc1f | |
915 | ||
916 | bltzall -> bgezal (with jal label instead of j label) | |
917 | bgezall -> bltzal (ditto) | |
918 | ||
919 | ||
920 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
921 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
922 | ((relax_substateT) \ | |
923 | (0xc0000000 \ | |
924 | | ((at) & 0x1f) \ | |
925 | | ((toofar) ? 0x20 : 0) \ | |
926 | | ((link) ? 0x40 : 0) \ | |
927 | | ((likely) ? 0x80 : 0) \ | |
928 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 929 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
930 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
931 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
932 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
933 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
934 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 935 | |
252b5132 RH |
936 | /* For mips16 code, we use an entirely different form of relaxation. |
937 | mips16 supports two versions of most instructions which take | |
938 | immediate values: a small one which takes some small value, and a | |
939 | larger one which takes a 16 bit value. Since branches also follow | |
940 | this pattern, relaxing these values is required. | |
941 | ||
942 | We can assemble both mips16 and normal MIPS code in a single | |
943 | object. Therefore, we need to support this type of relaxation at | |
944 | the same time that we support the relaxation described above. We | |
945 | use the high bit of the subtype field to distinguish these cases. | |
946 | ||
947 | The information we store for this type of relaxation is the | |
948 | argument code found in the opcode file for this relocation, whether | |
949 | the user explicitly requested a small or extended form, and whether | |
950 | the relocation is in a jump or jal delay slot. That tells us the | |
951 | size of the value, and how it should be stored. We also store | |
952 | whether the fragment is considered to be extended or not. We also | |
953 | store whether this is known to be a branch to a different section, | |
954 | whether we have tried to relax this frag yet, and whether we have | |
955 | ever extended a PC relative fragment because of a shift count. */ | |
956 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
957 | (0x80000000 \ | |
958 | | ((type) & 0xff) \ | |
959 | | ((small) ? 0x100 : 0) \ | |
960 | | ((ext) ? 0x200 : 0) \ | |
961 | | ((dslot) ? 0x400 : 0) \ | |
962 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 963 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
964 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
965 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
966 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
967 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
968 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
969 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
970 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
971 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
972 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
973 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
974 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
975 | |
976 | /* Is the given value a sign-extended 32-bit value? */ | |
977 | #define IS_SEXT_32BIT_NUM(x) \ | |
978 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
979 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
980 | ||
981 | /* Is the given value a sign-extended 16-bit value? */ | |
982 | #define IS_SEXT_16BIT_NUM(x) \ | |
983 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
984 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
985 | ||
2051e8c4 MR |
986 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
987 | #define IS_ZEXT_32BIT_NUM(x) \ | |
988 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
989 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
990 | ||
bf12938e RS |
991 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
992 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
993 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
994 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
995 | | (((VALUE) & (MASK)) << (SHIFT))) | |
996 | ||
997 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
998 | SHIFT places. */ | |
999 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1000 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1001 | ||
1002 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1003 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1004 | ||
1005 | include/opcode/mips.h specifies operand fields using the macros | |
1006 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1007 | with "MIPS16OP" instead of "OP". */ | |
1008 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1009 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1010 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1011 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1012 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1013 | ||
1014 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
1015 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
1016 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1017 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
1018 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1019 | MIPS16OP_MASK_##FIELD, \ | |
1020 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
1021 | \f |
1022 | /* Global variables used when generating relaxable macros. See the | |
1023 | comment above RELAX_ENCODE for more details about how relaxation | |
1024 | is used. */ | |
1025 | static struct { | |
1026 | /* 0 if we're not emitting a relaxable macro. | |
1027 | 1 if we're emitting the first of the two relaxation alternatives. | |
1028 | 2 if we're emitting the second alternative. */ | |
1029 | int sequence; | |
1030 | ||
1031 | /* The first relaxable fixup in the current frag. (In other words, | |
1032 | the first fixup that refers to relaxable code.) */ | |
1033 | fixS *first_fixup; | |
1034 | ||
1035 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1036 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1037 | unsigned int sizes[2]; | |
1038 | ||
1039 | /* The symbol on which the choice of sequence depends. */ | |
1040 | symbolS *symbol; | |
1041 | } mips_relax; | |
252b5132 | 1042 | \f |
584892a6 RS |
1043 | /* Global variables used to decide whether a macro needs a warning. */ |
1044 | static struct { | |
1045 | /* True if the macro is in a branch delay slot. */ | |
1046 | bfd_boolean delay_slot_p; | |
1047 | ||
1048 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1049 | in bytes and sizes[1] is the length of the second alternative. | |
1050 | For non-relaxable macros, both elements give the length of the | |
1051 | macro in bytes. */ | |
1052 | unsigned int sizes[2]; | |
1053 | ||
1054 | /* The first variant frag for this macro. */ | |
1055 | fragS *first_frag; | |
1056 | } mips_macro_warning; | |
1057 | \f | |
252b5132 RH |
1058 | /* Prototypes for static functions. */ |
1059 | ||
17a2f251 | 1060 | #define internalError() \ |
252b5132 | 1061 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1062 | |
1063 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1064 | ||
b34976b6 | 1065 | static void append_insn |
c67a084a | 1066 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *); |
7d10b47d | 1067 | static void mips_no_prev_insn (void); |
c67a084a | 1068 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1069 | static void mips16_macro_build |
03ea81db | 1070 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1071 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1072 | static void macro_start (void); |
1073 | static void macro_end (void); | |
17a2f251 TS |
1074 | static void macro (struct mips_cl_insn * ip); |
1075 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1076 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1077 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1078 | static void mips16_immed |
17a2f251 TS |
1079 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1080 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1081 | static size_t my_getSmallExpression |
17a2f251 TS |
1082 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1083 | static void my_getExpression (expressionS *, char *); | |
1084 | static void s_align (int); | |
1085 | static void s_change_sec (int); | |
1086 | static void s_change_section (int); | |
1087 | static void s_cons (int); | |
1088 | static void s_float_cons (int); | |
1089 | static void s_mips_globl (int); | |
1090 | static void s_option (int); | |
1091 | static void s_mipsset (int); | |
1092 | static void s_abicalls (int); | |
1093 | static void s_cpload (int); | |
1094 | static void s_cpsetup (int); | |
1095 | static void s_cplocal (int); | |
1096 | static void s_cprestore (int); | |
1097 | static void s_cpreturn (int); | |
741d6ea8 JM |
1098 | static void s_dtprelword (int); |
1099 | static void s_dtpreldword (int); | |
17a2f251 TS |
1100 | static void s_gpvalue (int); |
1101 | static void s_gpword (int); | |
1102 | static void s_gpdword (int); | |
1103 | static void s_cpadd (int); | |
1104 | static void s_insn (int); | |
1105 | static void md_obj_begin (void); | |
1106 | static void md_obj_end (void); | |
1107 | static void s_mips_ent (int); | |
1108 | static void s_mips_end (int); | |
1109 | static void s_mips_frame (int); | |
1110 | static void s_mips_mask (int reg_type); | |
1111 | static void s_mips_stab (int); | |
1112 | static void s_mips_weakext (int); | |
1113 | static void s_mips_file (int); | |
1114 | static void s_mips_loc (int); | |
1115 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1116 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1117 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1118 | |
1119 | /* Table and functions used to map between CPU/ISA names, and | |
1120 | ISA levels, and CPU numbers. */ | |
1121 | ||
e972090a NC |
1122 | struct mips_cpu_info |
1123 | { | |
e7af610e | 1124 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1125 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1126 | int isa; /* ISA level. */ |
1127 | int cpu; /* CPU number (default CPU if ISA). */ | |
1128 | }; | |
1129 | ||
ad3fea08 TS |
1130 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1131 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1132 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1133 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1134 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1135 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1136 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1137 | |
17a2f251 TS |
1138 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1139 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1140 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1141 | \f |
1142 | /* Pseudo-op table. | |
1143 | ||
1144 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1145 | should be defined here, but are currently unsupported: .alias, | |
1146 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1147 | ||
1148 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1149 | specific to the type of debugging information being generated, and | |
1150 | should be defined by the object format: .aent, .begin, .bend, | |
1151 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1152 | .vreg. | |
1153 | ||
1154 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1155 | not MIPS CPU specific, but are also not specific to the object file | |
1156 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1157 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1158 | |
e972090a NC |
1159 | static const pseudo_typeS mips_pseudo_table[] = |
1160 | { | |
beae10d5 | 1161 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1162 | {"option", s_option, 0}, |
1163 | {"set", s_mipsset, 0}, | |
1164 | {"rdata", s_change_sec, 'r'}, | |
1165 | {"sdata", s_change_sec, 's'}, | |
1166 | {"livereg", s_ignore, 0}, | |
1167 | {"abicalls", s_abicalls, 0}, | |
1168 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1169 | {"cpsetup", s_cpsetup, 0}, |
1170 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1171 | {"cprestore", s_cprestore, 0}, |
6478892d | 1172 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1173 | {"dtprelword", s_dtprelword, 0}, |
1174 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1175 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1176 | {"gpword", s_gpword, 0}, |
10181a0d | 1177 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1178 | {"cpadd", s_cpadd, 0}, |
1179 | {"insn", s_insn, 0}, | |
1180 | ||
beae10d5 | 1181 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1182 | chips. */ |
38a57ae7 | 1183 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1184 | {"bss", s_change_sec, 'b'}, |
1185 | {"err", s_err, 0}, | |
1186 | {"half", s_cons, 1}, | |
1187 | {"dword", s_cons, 3}, | |
1188 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1189 | {"origin", s_org, 0}, |
1190 | {"repeat", s_rept, 0}, | |
252b5132 | 1191 | |
998b3c36 MR |
1192 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1193 | {"sbss", s_change_sec, 'B'}, | |
1194 | ||
beae10d5 | 1195 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1196 | here for one reason or another. */ |
1197 | {"align", s_align, 0}, | |
1198 | {"byte", s_cons, 0}, | |
1199 | {"data", s_change_sec, 'd'}, | |
1200 | {"double", s_float_cons, 'd'}, | |
1201 | {"float", s_float_cons, 'f'}, | |
1202 | {"globl", s_mips_globl, 0}, | |
1203 | {"global", s_mips_globl, 0}, | |
1204 | {"hword", s_cons, 1}, | |
1205 | {"int", s_cons, 2}, | |
1206 | {"long", s_cons, 2}, | |
1207 | {"octa", s_cons, 4}, | |
1208 | {"quad", s_cons, 3}, | |
cca86cc8 | 1209 | {"section", s_change_section, 0}, |
252b5132 RH |
1210 | {"short", s_cons, 1}, |
1211 | {"single", s_float_cons, 'f'}, | |
1212 | {"stabn", s_mips_stab, 'n'}, | |
1213 | {"text", s_change_sec, 't'}, | |
1214 | {"word", s_cons, 2}, | |
add56521 | 1215 | |
add56521 | 1216 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1217 | |
43841e91 | 1218 | { NULL, NULL, 0 }, |
252b5132 RH |
1219 | }; |
1220 | ||
e972090a NC |
1221 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1222 | { | |
beae10d5 KH |
1223 | /* These pseudo-ops should be defined by the object file format. |
1224 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1225 | {"aent", s_mips_ent, 1}, |
1226 | {"bgnb", s_ignore, 0}, | |
1227 | {"end", s_mips_end, 0}, | |
1228 | {"endb", s_ignore, 0}, | |
1229 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1230 | {"file", s_mips_file, 0}, |
252b5132 RH |
1231 | {"fmask", s_mips_mask, 'F'}, |
1232 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1233 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1234 | {"mask", s_mips_mask, 'R'}, |
1235 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1236 | { NULL, NULL, 0 }, |
252b5132 RH |
1237 | }; |
1238 | ||
3ae8dd8d MR |
1239 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1240 | purpose of the `.dc.a' internal pseudo-op. */ | |
1241 | ||
1242 | int | |
1243 | mips_address_bytes (void) | |
1244 | { | |
1245 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1246 | } | |
1247 | ||
17a2f251 | 1248 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1249 | |
1250 | void | |
17a2f251 | 1251 | mips_pop_insert (void) |
252b5132 RH |
1252 | { |
1253 | pop_insert (mips_pseudo_table); | |
1254 | if (! ECOFF_DEBUGGING) | |
1255 | pop_insert (mips_nonecoff_pseudo_table); | |
1256 | } | |
1257 | \f | |
1258 | /* Symbols labelling the current insn. */ | |
1259 | ||
e972090a NC |
1260 | struct insn_label_list |
1261 | { | |
252b5132 RH |
1262 | struct insn_label_list *next; |
1263 | symbolS *label; | |
1264 | }; | |
1265 | ||
252b5132 | 1266 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1267 | #define label_list tc_segment_info_data.labels |
252b5132 | 1268 | |
17a2f251 | 1269 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1270 | |
1271 | static inline void | |
17a2f251 | 1272 | mips_clear_insn_labels (void) |
252b5132 RH |
1273 | { |
1274 | register struct insn_label_list **pl; | |
a8dbcb85 | 1275 | segment_info_type *si; |
252b5132 | 1276 | |
a8dbcb85 TS |
1277 | if (now_seg) |
1278 | { | |
1279 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1280 | ; | |
1281 | ||
1282 | si = seg_info (now_seg); | |
1283 | *pl = si->label_list; | |
1284 | si->label_list = NULL; | |
1285 | } | |
252b5132 | 1286 | } |
a8dbcb85 | 1287 | |
252b5132 RH |
1288 | \f |
1289 | static char *expr_end; | |
1290 | ||
1291 | /* Expressions which appear in instructions. These are set by | |
1292 | mips_ip. */ | |
1293 | ||
1294 | static expressionS imm_expr; | |
5f74bc13 | 1295 | static expressionS imm2_expr; |
252b5132 RH |
1296 | static expressionS offset_expr; |
1297 | ||
1298 | /* Relocs associated with imm_expr and offset_expr. */ | |
1299 | ||
f6688943 TS |
1300 | static bfd_reloc_code_real_type imm_reloc[3] |
1301 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1302 | static bfd_reloc_code_real_type offset_reloc[3] | |
1303 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1304 | |
252b5132 RH |
1305 | /* These are set by mips16_ip if an explicit extension is used. */ |
1306 | ||
b34976b6 | 1307 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1308 | |
7ed4a06a | 1309 | #ifdef OBJ_ELF |
ecb4347a DJ |
1310 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1311 | ECOFF debugging. */ | |
252b5132 RH |
1312 | |
1313 | static segT pdr_seg; | |
7ed4a06a | 1314 | #endif |
252b5132 | 1315 | |
e013f690 TS |
1316 | /* The default target format to use. */ |
1317 | ||
aeffff67 RS |
1318 | #if defined (TE_FreeBSD) |
1319 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1320 | #elif defined (TE_TMIPS) | |
1321 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1322 | #else | |
1323 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1324 | #endif | |
1325 | ||
e013f690 | 1326 | const char * |
17a2f251 | 1327 | mips_target_format (void) |
e013f690 TS |
1328 | { |
1329 | switch (OUTPUT_FLAVOR) | |
1330 | { | |
e013f690 TS |
1331 | case bfd_target_ecoff_flavour: |
1332 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1333 | case bfd_target_coff_flavour: | |
1334 | return "pe-mips"; | |
1335 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1336 | #ifdef TE_VXWORKS |
1337 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1338 | return (target_big_endian | |
1339 | ? "elf32-bigmips-vxworks" | |
1340 | : "elf32-littlemips-vxworks"); | |
1341 | #endif | |
e013f690 | 1342 | return (target_big_endian |
cfe86eaa | 1343 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1344 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1345 | : (HAVE_NEWABI |
aeffff67 RS |
1346 | ? ELF_TARGET ("elf32-n", "big") |
1347 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1348 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1349 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1350 | : (HAVE_NEWABI |
aeffff67 RS |
1351 | ? ELF_TARGET ("elf32-n", "little") |
1352 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1353 | default: |
1354 | abort (); | |
1355 | return NULL; | |
1356 | } | |
1357 | } | |
1358 | ||
1e915849 RS |
1359 | /* Return the length of instruction INSN. */ |
1360 | ||
1361 | static inline unsigned int | |
1362 | insn_length (const struct mips_cl_insn *insn) | |
1363 | { | |
1364 | if (!mips_opts.mips16) | |
1365 | return 4; | |
1366 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1367 | } | |
1368 | ||
1369 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1370 | ||
1371 | static void | |
1372 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1373 | { | |
1374 | size_t i; | |
1375 | ||
1376 | insn->insn_mo = mo; | |
1377 | insn->use_extend = FALSE; | |
1378 | insn->extend = 0; | |
1379 | insn->insn_opcode = mo->match; | |
1380 | insn->frag = NULL; | |
1381 | insn->where = 0; | |
1382 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1383 | insn->fixp[i] = NULL; | |
1384 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1385 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1386 | insn->mips16_absolute_jump_p = 0; | |
1387 | } | |
1388 | ||
742a56fe RS |
1389 | /* Record the current MIPS16 mode in now_seg. */ |
1390 | ||
1391 | static void | |
1392 | mips_record_mips16_mode (void) | |
1393 | { | |
1394 | segment_info_type *si; | |
1395 | ||
1396 | si = seg_info (now_seg); | |
1397 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1398 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1399 | } | |
1400 | ||
1e915849 RS |
1401 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1402 | ||
1403 | static void | |
1404 | install_insn (const struct mips_cl_insn *insn) | |
1405 | { | |
1406 | char *f = insn->frag->fr_literal + insn->where; | |
1407 | if (!mips_opts.mips16) | |
1408 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1409 | else if (insn->mips16_absolute_jump_p) | |
1410 | { | |
1411 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1412 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1413 | } | |
1414 | else | |
1415 | { | |
1416 | if (insn->use_extend) | |
1417 | { | |
1418 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1419 | f += 2; | |
1420 | } | |
1421 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1422 | } | |
742a56fe | 1423 | mips_record_mips16_mode (); |
1e915849 RS |
1424 | } |
1425 | ||
1426 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1427 | and install the opcode in the new location. */ | |
1428 | ||
1429 | static void | |
1430 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1431 | { | |
1432 | size_t i; | |
1433 | ||
1434 | insn->frag = frag; | |
1435 | insn->where = where; | |
1436 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1437 | if (insn->fixp[i] != NULL) | |
1438 | { | |
1439 | insn->fixp[i]->fx_frag = frag; | |
1440 | insn->fixp[i]->fx_where = where; | |
1441 | } | |
1442 | install_insn (insn); | |
1443 | } | |
1444 | ||
1445 | /* Add INSN to the end of the output. */ | |
1446 | ||
1447 | static void | |
1448 | add_fixed_insn (struct mips_cl_insn *insn) | |
1449 | { | |
1450 | char *f = frag_more (insn_length (insn)); | |
1451 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1452 | } | |
1453 | ||
1454 | /* Start a variant frag and move INSN to the start of the variant part, | |
1455 | marking it as fixed. The other arguments are as for frag_var. */ | |
1456 | ||
1457 | static void | |
1458 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1459 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1460 | { | |
1461 | frag_grow (max_chars); | |
1462 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1463 | insn->fixed_p = 1; | |
1464 | frag_var (rs_machine_dependent, max_chars, var, | |
1465 | subtype, symbol, offset, NULL); | |
1466 | } | |
1467 | ||
1468 | /* Insert N copies of INSN into the history buffer, starting at | |
1469 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1470 | ||
1471 | static void | |
1472 | insert_into_history (unsigned int first, unsigned int n, | |
1473 | const struct mips_cl_insn *insn) | |
1474 | { | |
1475 | if (mips_relax.sequence != 2) | |
1476 | { | |
1477 | unsigned int i; | |
1478 | ||
1479 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1480 | if (i >= first + n) | |
1481 | history[i] = history[i - n]; | |
1482 | else | |
1483 | history[i] = *insn; | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1488 | ||
1489 | static void | |
1490 | emit_nop (void) | |
1491 | { | |
1492 | add_fixed_insn (NOP_INSN); | |
1493 | insert_into_history (0, 1, NOP_INSN); | |
1494 | } | |
1495 | ||
71400594 RS |
1496 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1497 | the idea is to make it obvious at a glance that each errata is | |
1498 | included. */ | |
1499 | ||
1500 | static void | |
1501 | init_vr4120_conflicts (void) | |
1502 | { | |
1503 | #define CONFLICT(FIRST, SECOND) \ | |
1504 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1505 | ||
1506 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1507 | CONFLICT (MACC, DIV); | |
1508 | CONFLICT (DMACC, DIV); | |
1509 | ||
1510 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1511 | CONFLICT (DMULT, DMULT); | |
1512 | CONFLICT (DMULT, DMACC); | |
1513 | CONFLICT (DMACC, DMULT); | |
1514 | CONFLICT (DMACC, DMACC); | |
1515 | ||
1516 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1517 | CONFLICT (MACC, MTHILO); | |
1518 | CONFLICT (DMACC, MTHILO); | |
1519 | ||
1520 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1521 | instruction is executed immediately after a MACC or DMACC | |
1522 | instruction, the result of [either instruction] is incorrect." */ | |
1523 | CONFLICT (MACC, MULT); | |
1524 | CONFLICT (MACC, DMULT); | |
1525 | CONFLICT (DMACC, MULT); | |
1526 | CONFLICT (DMACC, DMULT); | |
1527 | ||
1528 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1529 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1530 | DDIV or DDIVU instruction, the result of the MACC or | |
1531 | DMACC instruction is incorrect.". */ | |
1532 | CONFLICT (DMULT, MACC); | |
1533 | CONFLICT (DMULT, DMACC); | |
1534 | CONFLICT (DIV, MACC); | |
1535 | CONFLICT (DIV, DMACC); | |
1536 | ||
1537 | #undef CONFLICT | |
1538 | } | |
1539 | ||
707bfff6 TS |
1540 | struct regname { |
1541 | const char *name; | |
1542 | unsigned int num; | |
1543 | }; | |
1544 | ||
1545 | #define RTYPE_MASK 0x1ff00 | |
1546 | #define RTYPE_NUM 0x00100 | |
1547 | #define RTYPE_FPU 0x00200 | |
1548 | #define RTYPE_FCC 0x00400 | |
1549 | #define RTYPE_VEC 0x00800 | |
1550 | #define RTYPE_GP 0x01000 | |
1551 | #define RTYPE_CP0 0x02000 | |
1552 | #define RTYPE_PC 0x04000 | |
1553 | #define RTYPE_ACC 0x08000 | |
1554 | #define RTYPE_CCC 0x10000 | |
1555 | #define RNUM_MASK 0x000ff | |
1556 | #define RWARN 0x80000 | |
1557 | ||
1558 | #define GENERIC_REGISTER_NUMBERS \ | |
1559 | {"$0", RTYPE_NUM | 0}, \ | |
1560 | {"$1", RTYPE_NUM | 1}, \ | |
1561 | {"$2", RTYPE_NUM | 2}, \ | |
1562 | {"$3", RTYPE_NUM | 3}, \ | |
1563 | {"$4", RTYPE_NUM | 4}, \ | |
1564 | {"$5", RTYPE_NUM | 5}, \ | |
1565 | {"$6", RTYPE_NUM | 6}, \ | |
1566 | {"$7", RTYPE_NUM | 7}, \ | |
1567 | {"$8", RTYPE_NUM | 8}, \ | |
1568 | {"$9", RTYPE_NUM | 9}, \ | |
1569 | {"$10", RTYPE_NUM | 10}, \ | |
1570 | {"$11", RTYPE_NUM | 11}, \ | |
1571 | {"$12", RTYPE_NUM | 12}, \ | |
1572 | {"$13", RTYPE_NUM | 13}, \ | |
1573 | {"$14", RTYPE_NUM | 14}, \ | |
1574 | {"$15", RTYPE_NUM | 15}, \ | |
1575 | {"$16", RTYPE_NUM | 16}, \ | |
1576 | {"$17", RTYPE_NUM | 17}, \ | |
1577 | {"$18", RTYPE_NUM | 18}, \ | |
1578 | {"$19", RTYPE_NUM | 19}, \ | |
1579 | {"$20", RTYPE_NUM | 20}, \ | |
1580 | {"$21", RTYPE_NUM | 21}, \ | |
1581 | {"$22", RTYPE_NUM | 22}, \ | |
1582 | {"$23", RTYPE_NUM | 23}, \ | |
1583 | {"$24", RTYPE_NUM | 24}, \ | |
1584 | {"$25", RTYPE_NUM | 25}, \ | |
1585 | {"$26", RTYPE_NUM | 26}, \ | |
1586 | {"$27", RTYPE_NUM | 27}, \ | |
1587 | {"$28", RTYPE_NUM | 28}, \ | |
1588 | {"$29", RTYPE_NUM | 29}, \ | |
1589 | {"$30", RTYPE_NUM | 30}, \ | |
1590 | {"$31", RTYPE_NUM | 31} | |
1591 | ||
1592 | #define FPU_REGISTER_NAMES \ | |
1593 | {"$f0", RTYPE_FPU | 0}, \ | |
1594 | {"$f1", RTYPE_FPU | 1}, \ | |
1595 | {"$f2", RTYPE_FPU | 2}, \ | |
1596 | {"$f3", RTYPE_FPU | 3}, \ | |
1597 | {"$f4", RTYPE_FPU | 4}, \ | |
1598 | {"$f5", RTYPE_FPU | 5}, \ | |
1599 | {"$f6", RTYPE_FPU | 6}, \ | |
1600 | {"$f7", RTYPE_FPU | 7}, \ | |
1601 | {"$f8", RTYPE_FPU | 8}, \ | |
1602 | {"$f9", RTYPE_FPU | 9}, \ | |
1603 | {"$f10", RTYPE_FPU | 10}, \ | |
1604 | {"$f11", RTYPE_FPU | 11}, \ | |
1605 | {"$f12", RTYPE_FPU | 12}, \ | |
1606 | {"$f13", RTYPE_FPU | 13}, \ | |
1607 | {"$f14", RTYPE_FPU | 14}, \ | |
1608 | {"$f15", RTYPE_FPU | 15}, \ | |
1609 | {"$f16", RTYPE_FPU | 16}, \ | |
1610 | {"$f17", RTYPE_FPU | 17}, \ | |
1611 | {"$f18", RTYPE_FPU | 18}, \ | |
1612 | {"$f19", RTYPE_FPU | 19}, \ | |
1613 | {"$f20", RTYPE_FPU | 20}, \ | |
1614 | {"$f21", RTYPE_FPU | 21}, \ | |
1615 | {"$f22", RTYPE_FPU | 22}, \ | |
1616 | {"$f23", RTYPE_FPU | 23}, \ | |
1617 | {"$f24", RTYPE_FPU | 24}, \ | |
1618 | {"$f25", RTYPE_FPU | 25}, \ | |
1619 | {"$f26", RTYPE_FPU | 26}, \ | |
1620 | {"$f27", RTYPE_FPU | 27}, \ | |
1621 | {"$f28", RTYPE_FPU | 28}, \ | |
1622 | {"$f29", RTYPE_FPU | 29}, \ | |
1623 | {"$f30", RTYPE_FPU | 30}, \ | |
1624 | {"$f31", RTYPE_FPU | 31} | |
1625 | ||
1626 | #define FPU_CONDITION_CODE_NAMES \ | |
1627 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1628 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1629 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1630 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1631 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1632 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1633 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1634 | {"$fcc7", RTYPE_FCC | 7} | |
1635 | ||
1636 | #define COPROC_CONDITION_CODE_NAMES \ | |
1637 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1638 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1639 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1640 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1641 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1642 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1643 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1644 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1645 | ||
1646 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1647 | {"$a4", RTYPE_GP | 8}, \ | |
1648 | {"$a5", RTYPE_GP | 9}, \ | |
1649 | {"$a6", RTYPE_GP | 10}, \ | |
1650 | {"$a7", RTYPE_GP | 11}, \ | |
1651 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1652 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1653 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1654 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1655 | {"$t0", RTYPE_GP | 12}, \ | |
1656 | {"$t1", RTYPE_GP | 13}, \ | |
1657 | {"$t2", RTYPE_GP | 14}, \ | |
1658 | {"$t3", RTYPE_GP | 15} | |
1659 | ||
1660 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1661 | {"$t0", RTYPE_GP | 8}, \ | |
1662 | {"$t1", RTYPE_GP | 9}, \ | |
1663 | {"$t2", RTYPE_GP | 10}, \ | |
1664 | {"$t3", RTYPE_GP | 11}, \ | |
1665 | {"$t4", RTYPE_GP | 12}, \ | |
1666 | {"$t5", RTYPE_GP | 13}, \ | |
1667 | {"$t6", RTYPE_GP | 14}, \ | |
1668 | {"$t7", RTYPE_GP | 15}, \ | |
1669 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1670 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1671 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1672 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1673 | ||
1674 | /* Remaining symbolic register names */ | |
1675 | #define SYMBOLIC_REGISTER_NAMES \ | |
1676 | {"$zero", RTYPE_GP | 0}, \ | |
1677 | {"$at", RTYPE_GP | 1}, \ | |
1678 | {"$AT", RTYPE_GP | 1}, \ | |
1679 | {"$v0", RTYPE_GP | 2}, \ | |
1680 | {"$v1", RTYPE_GP | 3}, \ | |
1681 | {"$a0", RTYPE_GP | 4}, \ | |
1682 | {"$a1", RTYPE_GP | 5}, \ | |
1683 | {"$a2", RTYPE_GP | 6}, \ | |
1684 | {"$a3", RTYPE_GP | 7}, \ | |
1685 | {"$s0", RTYPE_GP | 16}, \ | |
1686 | {"$s1", RTYPE_GP | 17}, \ | |
1687 | {"$s2", RTYPE_GP | 18}, \ | |
1688 | {"$s3", RTYPE_GP | 19}, \ | |
1689 | {"$s4", RTYPE_GP | 20}, \ | |
1690 | {"$s5", RTYPE_GP | 21}, \ | |
1691 | {"$s6", RTYPE_GP | 22}, \ | |
1692 | {"$s7", RTYPE_GP | 23}, \ | |
1693 | {"$t8", RTYPE_GP | 24}, \ | |
1694 | {"$t9", RTYPE_GP | 25}, \ | |
1695 | {"$k0", RTYPE_GP | 26}, \ | |
1696 | {"$kt0", RTYPE_GP | 26}, \ | |
1697 | {"$k1", RTYPE_GP | 27}, \ | |
1698 | {"$kt1", RTYPE_GP | 27}, \ | |
1699 | {"$gp", RTYPE_GP | 28}, \ | |
1700 | {"$sp", RTYPE_GP | 29}, \ | |
1701 | {"$s8", RTYPE_GP | 30}, \ | |
1702 | {"$fp", RTYPE_GP | 30}, \ | |
1703 | {"$ra", RTYPE_GP | 31} | |
1704 | ||
1705 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1706 | {"$pc", RTYPE_PC | 0} | |
1707 | ||
1708 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1709 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1710 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1711 | {"$v2", RTYPE_VEC | 2}, \ | |
1712 | {"$v3", RTYPE_VEC | 3}, \ | |
1713 | {"$v4", RTYPE_VEC | 4}, \ | |
1714 | {"$v5", RTYPE_VEC | 5}, \ | |
1715 | {"$v6", RTYPE_VEC | 6}, \ | |
1716 | {"$v7", RTYPE_VEC | 7}, \ | |
1717 | {"$v8", RTYPE_VEC | 8}, \ | |
1718 | {"$v9", RTYPE_VEC | 9}, \ | |
1719 | {"$v10", RTYPE_VEC | 10}, \ | |
1720 | {"$v11", RTYPE_VEC | 11}, \ | |
1721 | {"$v12", RTYPE_VEC | 12}, \ | |
1722 | {"$v13", RTYPE_VEC | 13}, \ | |
1723 | {"$v14", RTYPE_VEC | 14}, \ | |
1724 | {"$v15", RTYPE_VEC | 15}, \ | |
1725 | {"$v16", RTYPE_VEC | 16}, \ | |
1726 | {"$v17", RTYPE_VEC | 17}, \ | |
1727 | {"$v18", RTYPE_VEC | 18}, \ | |
1728 | {"$v19", RTYPE_VEC | 19}, \ | |
1729 | {"$v20", RTYPE_VEC | 20}, \ | |
1730 | {"$v21", RTYPE_VEC | 21}, \ | |
1731 | {"$v22", RTYPE_VEC | 22}, \ | |
1732 | {"$v23", RTYPE_VEC | 23}, \ | |
1733 | {"$v24", RTYPE_VEC | 24}, \ | |
1734 | {"$v25", RTYPE_VEC | 25}, \ | |
1735 | {"$v26", RTYPE_VEC | 26}, \ | |
1736 | {"$v27", RTYPE_VEC | 27}, \ | |
1737 | {"$v28", RTYPE_VEC | 28}, \ | |
1738 | {"$v29", RTYPE_VEC | 29}, \ | |
1739 | {"$v30", RTYPE_VEC | 30}, \ | |
1740 | {"$v31", RTYPE_VEC | 31} | |
1741 | ||
1742 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1743 | {"$ac0", RTYPE_ACC | 0}, \ | |
1744 | {"$ac1", RTYPE_ACC | 1}, \ | |
1745 | {"$ac2", RTYPE_ACC | 2}, \ | |
1746 | {"$ac3", RTYPE_ACC | 3} | |
1747 | ||
1748 | static const struct regname reg_names[] = { | |
1749 | GENERIC_REGISTER_NUMBERS, | |
1750 | FPU_REGISTER_NAMES, | |
1751 | FPU_CONDITION_CODE_NAMES, | |
1752 | COPROC_CONDITION_CODE_NAMES, | |
1753 | ||
1754 | /* The $txx registers depends on the abi, | |
1755 | these will be added later into the symbol table from | |
1756 | one of the tables below once mips_abi is set after | |
1757 | parsing of arguments from the command line. */ | |
1758 | SYMBOLIC_REGISTER_NAMES, | |
1759 | ||
1760 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1761 | MDMX_VECTOR_REGISTER_NAMES, | |
1762 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1763 | {0, 0} | |
1764 | }; | |
1765 | ||
1766 | static const struct regname reg_names_o32[] = { | |
1767 | O32_SYMBOLIC_REGISTER_NAMES, | |
1768 | {0, 0} | |
1769 | }; | |
1770 | ||
1771 | static const struct regname reg_names_n32n64[] = { | |
1772 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1773 | {0, 0} | |
1774 | }; | |
1775 | ||
1776 | static int | |
1777 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1778 | { | |
1779 | symbolS *symbolP; | |
1780 | char *e; | |
1781 | char save_c; | |
1782 | int reg = -1; | |
1783 | ||
1784 | /* Find end of name. */ | |
1785 | e = *s; | |
1786 | if (is_name_beginner (*e)) | |
1787 | ++e; | |
1788 | while (is_part_of_name (*e)) | |
1789 | ++e; | |
1790 | ||
1791 | /* Terminate name. */ | |
1792 | save_c = *e; | |
1793 | *e = '\0'; | |
1794 | ||
1795 | /* Look for a register symbol. */ | |
1796 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1797 | { | |
1798 | int r = S_GET_VALUE (symbolP); | |
1799 | if (r & types) | |
1800 | reg = r & RNUM_MASK; | |
1801 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1802 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1803 | reg = (r & RNUM_MASK) - 2; | |
1804 | } | |
1805 | /* Else see if this is a register defined in an itbl entry. */ | |
1806 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1807 | { | |
1808 | char *n = *s; | |
1809 | unsigned long r; | |
1810 | ||
1811 | if (*n == '$') | |
1812 | ++n; | |
1813 | if (itbl_get_reg_val (n, &r)) | |
1814 | reg = r & RNUM_MASK; | |
1815 | } | |
1816 | ||
1817 | /* Advance to next token if a register was recognised. */ | |
1818 | if (reg >= 0) | |
1819 | *s = e; | |
1820 | else if (types & RWARN) | |
20203fb9 | 1821 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
1822 | |
1823 | *e = save_c; | |
1824 | if (regnop) | |
1825 | *regnop = reg; | |
1826 | return reg >= 0; | |
1827 | } | |
1828 | ||
037b32b9 | 1829 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 1830 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
1831 | |
1832 | static bfd_boolean | |
f79e2745 | 1833 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
1834 | { |
1835 | int isa = mips_opts.isa; | |
1836 | int fp_s, fp_d; | |
1837 | ||
1838 | if (mips_opts.ase_mdmx) | |
1839 | isa |= INSN_MDMX; | |
1840 | if (mips_opts.ase_dsp) | |
1841 | isa |= INSN_DSP; | |
1842 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1843 | isa |= INSN_DSP64; | |
1844 | if (mips_opts.ase_dspr2) | |
1845 | isa |= INSN_DSPR2; | |
1846 | if (mips_opts.ase_mt) | |
1847 | isa |= INSN_MT; | |
1848 | if (mips_opts.ase_mips3d) | |
1849 | isa |= INSN_MIPS3D; | |
1850 | if (mips_opts.ase_smartmips) | |
1851 | isa |= INSN_SMARTMIPS; | |
1852 | ||
b19e8a9b AN |
1853 | /* Don't accept instructions based on the ISA if the CPU does not implement |
1854 | all the coprocessor insns. */ | |
1855 | if (NO_ISA_COP (mips_opts.arch) | |
1856 | && COP_INSN (mo->pinfo)) | |
1857 | isa = 0; | |
1858 | ||
037b32b9 AN |
1859 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
1860 | return FALSE; | |
1861 | ||
1862 | /* Check whether the instruction or macro requires single-precision or | |
1863 | double-precision floating-point support. Note that this information is | |
1864 | stored differently in the opcode table for insns and macros. */ | |
1865 | if (mo->pinfo == INSN_MACRO) | |
1866 | { | |
1867 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1868 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1869 | } | |
1870 | else | |
1871 | { | |
1872 | fp_s = mo->pinfo & FP_S; | |
1873 | fp_d = mo->pinfo & FP_D; | |
1874 | } | |
1875 | ||
1876 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1877 | return FALSE; | |
1878 | ||
1879 | if (fp_s && mips_opts.soft_float) | |
1880 | return FALSE; | |
1881 | ||
1882 | return TRUE; | |
1883 | } | |
1884 | ||
1885 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1886 | selected ISA and architecture. */ | |
1887 | ||
1888 | static bfd_boolean | |
1889 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1890 | { | |
1891 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1892 | } | |
1893 | ||
707bfff6 TS |
1894 | /* This function is called once, at assembler startup time. It should set up |
1895 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1896 | |
252b5132 | 1897 | void |
17a2f251 | 1898 | md_begin (void) |
252b5132 | 1899 | { |
3994f87e | 1900 | const char *retval = NULL; |
156c2f8b | 1901 | int i = 0; |
252b5132 | 1902 | int broken = 0; |
1f25f5d3 | 1903 | |
0a44bf69 RS |
1904 | if (mips_pic != NO_PIC) |
1905 | { | |
1906 | if (g_switch_seen && g_switch_value != 0) | |
1907 | as_bad (_("-G may not be used in position-independent code")); | |
1908 | g_switch_value = 0; | |
1909 | } | |
1910 | ||
fef14a42 | 1911 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1912 | as_warn (_("Could not set architecture and machine")); |
1913 | ||
252b5132 RH |
1914 | op_hash = hash_new (); |
1915 | ||
1916 | for (i = 0; i < NUMOPCODES;) | |
1917 | { | |
1918 | const char *name = mips_opcodes[i].name; | |
1919 | ||
17a2f251 | 1920 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1921 | if (retval != NULL) |
1922 | { | |
1923 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1924 | mips_opcodes[i].name, retval); | |
1925 | /* Probably a memory allocation problem? Give up now. */ | |
1926 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1927 | } | |
1928 | do | |
1929 | { | |
1930 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1931 | { | |
1932 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1933 | broken = 1; | |
1e915849 RS |
1934 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1935 | { | |
1936 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
1937 | if (mips_fix_loongson2f_nop) |
1938 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
1939 | nop_insn.fixed_p = 1; |
1940 | } | |
252b5132 RH |
1941 | } |
1942 | ++i; | |
1943 | } | |
1944 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1945 | } | |
1946 | ||
1947 | mips16_op_hash = hash_new (); | |
1948 | ||
1949 | i = 0; | |
1950 | while (i < bfd_mips16_num_opcodes) | |
1951 | { | |
1952 | const char *name = mips16_opcodes[i].name; | |
1953 | ||
17a2f251 | 1954 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1955 | if (retval != NULL) |
1956 | as_fatal (_("internal: can't hash `%s': %s"), | |
1957 | mips16_opcodes[i].name, retval); | |
1958 | do | |
1959 | { | |
1960 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1961 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1962 | != mips16_opcodes[i].match)) | |
1963 | { | |
1964 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1965 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1966 | broken = 1; | |
1967 | } | |
1e915849 RS |
1968 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1969 | { | |
1970 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1971 | mips16_nop_insn.fixed_p = 1; | |
1972 | } | |
252b5132 RH |
1973 | ++i; |
1974 | } | |
1975 | while (i < bfd_mips16_num_opcodes | |
1976 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1977 | } | |
1978 | ||
1979 | if (broken) | |
1980 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1981 | ||
1982 | /* We add all the general register names to the symbol table. This | |
1983 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1984 | for (i = 0; reg_names[i].name; i++) |
1985 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 1986 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
1987 | &zero_address_frag)); |
1988 | if (HAVE_NEWABI) | |
1989 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1990 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 1991 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 1992 | &zero_address_frag)); |
707bfff6 TS |
1993 | else |
1994 | for (i = 0; reg_names_o32[i].name; i++) | |
1995 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 1996 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 1997 | &zero_address_frag)); |
6047c971 | 1998 | |
7d10b47d | 1999 | mips_no_prev_insn (); |
252b5132 RH |
2000 | |
2001 | mips_gprmask = 0; | |
2002 | mips_cprmask[0] = 0; | |
2003 | mips_cprmask[1] = 0; | |
2004 | mips_cprmask[2] = 0; | |
2005 | mips_cprmask[3] = 0; | |
2006 | ||
2007 | /* set the default alignment for the text section (2**2) */ | |
2008 | record_alignment (text_section, 2); | |
2009 | ||
4d0d148d | 2010 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2011 | |
707bfff6 | 2012 | #ifdef OBJ_ELF |
f43abd2b | 2013 | if (IS_ELF) |
252b5132 | 2014 | { |
0a44bf69 RS |
2015 | /* On a native system other than VxWorks, sections must be aligned |
2016 | to 16 byte boundaries. When configured for an embedded ELF | |
2017 | target, we don't bother. */ | |
c41e87e3 CF |
2018 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2019 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2020 | { |
2021 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2022 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2023 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2024 | } | |
2025 | ||
2026 | /* Create a .reginfo section for register masks and a .mdebug | |
2027 | section for debugging information. */ | |
2028 | { | |
2029 | segT seg; | |
2030 | subsegT subseg; | |
2031 | flagword flags; | |
2032 | segT sec; | |
2033 | ||
2034 | seg = now_seg; | |
2035 | subseg = now_subseg; | |
2036 | ||
2037 | /* The ABI says this section should be loaded so that the | |
2038 | running program can access it. However, we don't load it | |
2039 | if we are configured for an embedded target */ | |
2040 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2041 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2042 | flags |= SEC_ALLOC | SEC_LOAD; |
2043 | ||
316f5878 | 2044 | if (mips_abi != N64_ABI) |
252b5132 RH |
2045 | { |
2046 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2047 | ||
195325d2 TS |
2048 | bfd_set_section_flags (stdoutput, sec, flags); |
2049 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2050 | |
252b5132 | 2051 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2052 | } |
2053 | else | |
2054 | { | |
2055 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2056 | .reginfo section. */ | |
2057 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2058 | bfd_set_section_flags (stdoutput, sec, flags); |
2059 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2060 | |
252b5132 RH |
2061 | /* Set up the option header. */ |
2062 | { | |
2063 | Elf_Internal_Options opthdr; | |
2064 | char *f; | |
2065 | ||
2066 | opthdr.kind = ODK_REGINFO; | |
2067 | opthdr.size = (sizeof (Elf_External_Options) | |
2068 | + sizeof (Elf64_External_RegInfo)); | |
2069 | opthdr.section = 0; | |
2070 | opthdr.info = 0; | |
2071 | f = frag_more (sizeof (Elf_External_Options)); | |
2072 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2073 | (Elf_External_Options *) f); | |
2074 | ||
2075 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2076 | } | |
252b5132 RH |
2077 | } |
2078 | ||
2079 | if (ECOFF_DEBUGGING) | |
2080 | { | |
2081 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2082 | (void) bfd_set_section_flags (stdoutput, sec, | |
2083 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2084 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2085 | } | |
f43abd2b | 2086 | else if (mips_flag_pdr) |
ecb4347a DJ |
2087 | { |
2088 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2089 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2090 | SEC_READONLY | SEC_RELOC | |
2091 | | SEC_DEBUGGING); | |
2092 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2093 | } | |
252b5132 RH |
2094 | |
2095 | subseg_set (seg, subseg); | |
2096 | } | |
2097 | } | |
707bfff6 | 2098 | #endif /* OBJ_ELF */ |
252b5132 RH |
2099 | |
2100 | if (! ECOFF_DEBUGGING) | |
2101 | md_obj_begin (); | |
71400594 RS |
2102 | |
2103 | if (mips_fix_vr4120) | |
2104 | init_vr4120_conflicts (); | |
252b5132 RH |
2105 | } |
2106 | ||
2107 | void | |
17a2f251 | 2108 | md_mips_end (void) |
252b5132 RH |
2109 | { |
2110 | if (! ECOFF_DEBUGGING) | |
2111 | md_obj_end (); | |
2112 | } | |
2113 | ||
2114 | void | |
17a2f251 | 2115 | md_assemble (char *str) |
252b5132 RH |
2116 | { |
2117 | struct mips_cl_insn insn; | |
f6688943 TS |
2118 | bfd_reloc_code_real_type unused_reloc[3] |
2119 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2120 | |
2121 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2122 | imm2_expr.X_op = O_absent; |
252b5132 | 2123 | offset_expr.X_op = O_absent; |
f6688943 TS |
2124 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2125 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2126 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2127 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2128 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2129 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2130 | |
2131 | if (mips_opts.mips16) | |
2132 | mips16_ip (str, &insn); | |
2133 | else | |
2134 | { | |
2135 | mips_ip (str, &insn); | |
beae10d5 KH |
2136 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2137 | str, insn.insn_opcode)); | |
252b5132 RH |
2138 | } |
2139 | ||
2140 | if (insn_error) | |
2141 | { | |
2142 | as_bad ("%s `%s'", insn_error, str); | |
2143 | return; | |
2144 | } | |
2145 | ||
2146 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2147 | { | |
584892a6 | 2148 | macro_start (); |
252b5132 RH |
2149 | if (mips_opts.mips16) |
2150 | mips16_macro (&insn); | |
2151 | else | |
2152 | macro (&insn); | |
584892a6 | 2153 | macro_end (); |
252b5132 RH |
2154 | } |
2155 | else | |
2156 | { | |
2157 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2158 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2159 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2160 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2161 | else |
4d7206a2 | 2162 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2163 | } |
2164 | } | |
2165 | ||
738e5348 RS |
2166 | /* Convenience functions for abstracting away the differences between |
2167 | MIPS16 and non-MIPS16 relocations. */ | |
2168 | ||
2169 | static inline bfd_boolean | |
2170 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2171 | { | |
2172 | switch (reloc) | |
2173 | { | |
2174 | case BFD_RELOC_MIPS16_JMP: | |
2175 | case BFD_RELOC_MIPS16_GPREL: | |
2176 | case BFD_RELOC_MIPS16_GOT16: | |
2177 | case BFD_RELOC_MIPS16_CALL16: | |
2178 | case BFD_RELOC_MIPS16_HI16_S: | |
2179 | case BFD_RELOC_MIPS16_HI16: | |
2180 | case BFD_RELOC_MIPS16_LO16: | |
2181 | return TRUE; | |
2182 | ||
2183 | default: | |
2184 | return FALSE; | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | static inline bfd_boolean | |
2189 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2190 | { | |
2191 | return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16; | |
2192 | } | |
2193 | ||
2194 | static inline bfd_boolean | |
2195 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2196 | { | |
2197 | return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S; | |
2198 | } | |
2199 | ||
2200 | static inline bfd_boolean | |
2201 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2202 | { | |
2203 | return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16; | |
2204 | } | |
2205 | ||
5919d012 | 2206 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2207 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2208 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2209 | |
2210 | static inline bfd_boolean | |
17a2f251 | 2211 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2212 | { |
3b91255e | 2213 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2214 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2215 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2216 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2217 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2218 | } | |
2219 | ||
2220 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2221 | reloc_needs_lo_p. */ | |
2222 | ||
2223 | static inline bfd_reloc_code_real_type | |
2224 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2225 | { | |
2226 | return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16; | |
5919d012 RS |
2227 | } |
2228 | ||
2229 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2230 | relocation. */ | |
2231 | ||
2232 | static inline bfd_boolean | |
17a2f251 | 2233 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2234 | { |
2235 | return (fixp->fx_next != NULL | |
738e5348 | 2236 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2237 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2238 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2239 | } | |
2240 | ||
252b5132 RH |
2241 | /* See whether instruction IP reads register REG. CLASS is the type |
2242 | of register. */ | |
2243 | ||
2244 | static int | |
71400594 | 2245 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
96d56e9f | 2246 | enum mips_regclass regclass) |
252b5132 | 2247 | { |
96d56e9f | 2248 | if (regclass == MIPS16_REG) |
252b5132 | 2249 | { |
9c2799c2 | 2250 | gas_assert (mips_opts.mips16); |
252b5132 | 2251 | reg = mips16_to_32_reg_map[reg]; |
96d56e9f | 2252 | regclass = MIPS_GR_REG; |
252b5132 RH |
2253 | } |
2254 | ||
85b51719 | 2255 | /* Don't report on general register ZERO, since it never changes. */ |
96d56e9f | 2256 | if (regclass == MIPS_GR_REG && reg == ZERO) |
252b5132 RH |
2257 | return 0; |
2258 | ||
96d56e9f | 2259 | if (regclass == MIPS_FP_REG) |
252b5132 | 2260 | { |
9c2799c2 | 2261 | gas_assert (! mips_opts.mips16); |
252b5132 RH |
2262 | /* If we are called with either $f0 or $f1, we must check $f0. |
2263 | This is not optimal, because it will introduce an unnecessary | |
2264 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2265 | need to distinguish reading both $f0 and $f1 or just one of | |
2266 | them. Note that we don't have to check the other way, | |
2267 | because there is no instruction that sets both $f0 and $f1 | |
2268 | and requires a delay. */ | |
2269 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2270 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2271 | == (reg &~ (unsigned) 1))) |
2272 | return 1; | |
2273 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2274 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2275 | == (reg &~ (unsigned) 1))) |
2276 | return 1; | |
98675402 RS |
2277 | if ((ip->insn_mo->pinfo2 & INSN2_READ_FPR_Z) |
2278 | && ((EXTRACT_OPERAND (FZ, *ip) & ~(unsigned) 1) | |
2279 | == (reg &~ (unsigned) 1))) | |
2280 | return 1; | |
252b5132 RH |
2281 | } |
2282 | else if (! mips_opts.mips16) | |
2283 | { | |
2284 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2285 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2286 | return 1; |
2287 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2288 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 | 2289 | return 1; |
98675402 RS |
2290 | if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_D) |
2291 | && EXTRACT_OPERAND (RD, *ip) == reg) | |
2292 | return 1; | |
2293 | if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_Z) | |
2294 | && EXTRACT_OPERAND (RZ, *ip) == reg) | |
2295 | return 1; | |
252b5132 RH |
2296 | } |
2297 | else | |
2298 | { | |
2299 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2300 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2301 | return 1; |
2302 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2303 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2304 | return 1; |
2305 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2306 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2307 | == reg)) |
2308 | return 1; | |
2309 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2310 | return 1; | |
2311 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2312 | return 1; | |
2313 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2314 | return 1; | |
2315 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2316 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2317 | return 1; |
2318 | } | |
2319 | ||
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | /* This function returns true if modifying a register requires a | |
2324 | delay. */ | |
2325 | ||
2326 | static int | |
17a2f251 | 2327 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2328 | { |
2329 | unsigned long prev_pinfo; | |
2330 | ||
47e39b9d | 2331 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2332 | if (! mips_opts.noreorder |
81912461 ILT |
2333 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2334 | && ! gpr_interlocks) | |
2335 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2336 | && ! cop_interlocks))) | |
252b5132 | 2337 | { |
81912461 ILT |
2338 | /* A load from a coprocessor or from memory. All load delays |
2339 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2340 | /* Itbl support may require additional care here. */ |
252b5132 | 2341 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2342 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2343 | return 1; |
2344 | } | |
2345 | ||
2346 | return 0; | |
2347 | } | |
2348 | ||
404a8071 RS |
2349 | /* Move all labels in insn_labels to the current insertion point. */ |
2350 | ||
2351 | static void | |
2352 | mips_move_labels (void) | |
2353 | { | |
a8dbcb85 | 2354 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2355 | struct insn_label_list *l; |
2356 | valueT val; | |
2357 | ||
a8dbcb85 | 2358 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2359 | { |
9c2799c2 | 2360 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2361 | symbol_set_frag (l->label, frag_now); |
2362 | val = (valueT) frag_now_fix (); | |
2363 | /* mips16 text labels are stored as odd. */ | |
2364 | if (mips_opts.mips16) | |
2365 | ++val; | |
2366 | S_SET_VALUE (l->label, val); | |
2367 | } | |
2368 | } | |
2369 | ||
5f0fe04b TS |
2370 | static bfd_boolean |
2371 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2372 | { | |
2373 | bfd_boolean linkonce = FALSE; | |
2374 | segT symseg = S_GET_SEGMENT (sym); | |
2375 | ||
2376 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2377 | { | |
2378 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2379 | linkonce = TRUE; | |
2380 | #ifdef OBJ_ELF | |
2381 | /* The GNU toolchain uses an extension for ELF: a section | |
2382 | beginning with the magic string .gnu.linkonce is a | |
2383 | linkonce section. */ | |
2384 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2385 | sizeof ".gnu.linkonce" - 1) == 0) | |
2386 | linkonce = TRUE; | |
2387 | #endif | |
2388 | } | |
2389 | return linkonce; | |
2390 | } | |
2391 | ||
252b5132 RH |
2392 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2393 | handle them specially, such as generating jalx instructions when | |
2394 | needed. We also make them odd for the duration of the assembly, in | |
2395 | order to generate the right sort of code. We will make them even | |
2396 | in the adjust_symtab routine, while leaving them marked. This is | |
2397 | convenient for the debugger and the disassembler. The linker knows | |
2398 | to make them odd again. */ | |
2399 | ||
2400 | static void | |
17a2f251 | 2401 | mips16_mark_labels (void) |
252b5132 | 2402 | { |
a8dbcb85 TS |
2403 | segment_info_type *si = seg_info (now_seg); |
2404 | struct insn_label_list *l; | |
252b5132 | 2405 | |
a8dbcb85 TS |
2406 | if (!mips_opts.mips16) |
2407 | return; | |
2408 | ||
2409 | for (l = si->label_list; l != NULL; l = l->next) | |
2410 | { | |
2411 | symbolS *label = l->label; | |
2412 | ||
2413 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2414 | if (IS_ELF) |
30c09090 | 2415 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
252b5132 | 2416 | #endif |
5f0fe04b TS |
2417 | if ((S_GET_VALUE (label) & 1) == 0 |
2418 | /* Don't adjust the address if the label is global or weak, or | |
2419 | in a link-once section, since we'll be emitting symbol reloc | |
2420 | references to it which will be patched up by the linker, and | |
2421 | the final value of the symbol may or may not be MIPS16. */ | |
2422 | && ! S_IS_WEAK (label) | |
2423 | && ! S_IS_EXTERNAL (label) | |
2424 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2425 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2426 | } |
2427 | } | |
2428 | ||
4d7206a2 RS |
2429 | /* End the current frag. Make it a variant frag and record the |
2430 | relaxation info. */ | |
2431 | ||
2432 | static void | |
2433 | relax_close_frag (void) | |
2434 | { | |
584892a6 | 2435 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2436 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2437 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2438 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2439 | ||
2440 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2441 | mips_relax.first_fixup = 0; | |
2442 | } | |
2443 | ||
2444 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2445 | See the comment above RELAX_ENCODE for more details. */ | |
2446 | ||
2447 | static void | |
2448 | relax_start (symbolS *symbol) | |
2449 | { | |
9c2799c2 | 2450 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2451 | mips_relax.sequence = 1; |
2452 | mips_relax.symbol = symbol; | |
2453 | } | |
2454 | ||
2455 | /* Start generating the second version of a relaxable sequence. | |
2456 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2457 | |
2458 | static void | |
4d7206a2 RS |
2459 | relax_switch (void) |
2460 | { | |
9c2799c2 | 2461 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2462 | mips_relax.sequence = 2; |
2463 | } | |
2464 | ||
2465 | /* End the current relaxable sequence. */ | |
2466 | ||
2467 | static void | |
2468 | relax_end (void) | |
2469 | { | |
9c2799c2 | 2470 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2471 | relax_close_frag (); |
2472 | mips_relax.sequence = 0; | |
2473 | } | |
2474 | ||
71400594 RS |
2475 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2476 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2477 | by VR4120 errata. */ | |
4d7206a2 | 2478 | |
71400594 RS |
2479 | static unsigned int |
2480 | classify_vr4120_insn (const char *name) | |
252b5132 | 2481 | { |
71400594 RS |
2482 | if (strncmp (name, "macc", 4) == 0) |
2483 | return FIX_VR4120_MACC; | |
2484 | if (strncmp (name, "dmacc", 5) == 0) | |
2485 | return FIX_VR4120_DMACC; | |
2486 | if (strncmp (name, "mult", 4) == 0) | |
2487 | return FIX_VR4120_MULT; | |
2488 | if (strncmp (name, "dmult", 5) == 0) | |
2489 | return FIX_VR4120_DMULT; | |
2490 | if (strstr (name, "div")) | |
2491 | return FIX_VR4120_DIV; | |
2492 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2493 | return FIX_VR4120_MTHILO; | |
2494 | return NUM_FIX_VR4120_CLASSES; | |
2495 | } | |
252b5132 | 2496 | |
ff239038 CM |
2497 | #define INSN_ERET 0x42000018 |
2498 | #define INSN_DERET 0x4200001f | |
2499 | ||
71400594 RS |
2500 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2501 | where INSN1 is the earlier instruction. Return the worst-case value | |
2502 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2503 | |
71400594 RS |
2504 | static unsigned int |
2505 | insns_between (const struct mips_cl_insn *insn1, | |
2506 | const struct mips_cl_insn *insn2) | |
2507 | { | |
2508 | unsigned long pinfo1, pinfo2; | |
2509 | ||
2510 | /* This function needs to know which pinfo flags are set for INSN2 | |
2511 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2512 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2513 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2514 | pinfo1 = insn1->insn_mo->pinfo; | |
2515 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2516 | |
71400594 RS |
2517 | #define INSN2_USES_REG(REG, CLASS) \ |
2518 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2519 | ||
2520 | /* For most targets, write-after-read dependencies on the HI and LO | |
2521 | registers must be separated by at least two instructions. */ | |
2522 | if (!hilo_interlocks) | |
252b5132 | 2523 | { |
71400594 RS |
2524 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2525 | return 2; | |
2526 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2527 | return 2; | |
2528 | } | |
2529 | ||
2530 | /* If we're working around r7000 errata, there must be two instructions | |
2531 | between an mfhi or mflo and any instruction that uses the result. */ | |
2532 | if (mips_7000_hilo_fix | |
2533 | && MF_HILO_INSN (pinfo1) | |
2534 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2535 | return 2; | |
2536 | ||
ff239038 CM |
2537 | /* If we're working around 24K errata, one instruction is required |
2538 | if an ERET or DERET is followed by a branch instruction. */ | |
2539 | if (mips_fix_24k) | |
2540 | { | |
2541 | if (insn1->insn_opcode == INSN_ERET | |
2542 | || insn1->insn_opcode == INSN_DERET) | |
2543 | { | |
2544 | if (insn2 == NULL | |
2545 | || insn2->insn_opcode == INSN_ERET | |
2546 | || insn2->insn_opcode == INSN_DERET | |
2547 | || (insn2->insn_mo->pinfo | |
2548 | & (INSN_UNCOND_BRANCH_DELAY | |
2549 | | INSN_COND_BRANCH_DELAY | |
2550 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
2551 | return 1; | |
2552 | } | |
2553 | } | |
2554 | ||
71400594 RS |
2555 | /* If working around VR4120 errata, check for combinations that need |
2556 | a single intervening instruction. */ | |
2557 | if (mips_fix_vr4120) | |
2558 | { | |
2559 | unsigned int class1, class2; | |
252b5132 | 2560 | |
71400594 RS |
2561 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2562 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2563 | { |
71400594 RS |
2564 | if (insn2 == NULL) |
2565 | return 1; | |
2566 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2567 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2568 | return 1; | |
252b5132 | 2569 | } |
71400594 RS |
2570 | } |
2571 | ||
2572 | if (!mips_opts.mips16) | |
2573 | { | |
2574 | /* Check for GPR or coprocessor load delays. All such delays | |
2575 | are on the RT register. */ | |
2576 | /* Itbl support may require additional care here. */ | |
2577 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2578 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2579 | { |
71400594 RS |
2580 | know (pinfo1 & INSN_WRITE_GPR_T); |
2581 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2582 | return 1; | |
2583 | } | |
2584 | ||
2585 | /* Check for generic coprocessor hazards. | |
2586 | ||
2587 | This case is not handled very well. There is no special | |
2588 | knowledge of CP0 handling, and the coprocessors other than | |
2589 | the floating point unit are not distinguished at all. */ | |
2590 | /* Itbl support may require additional care here. FIXME! | |
2591 | Need to modify this to include knowledge about | |
2592 | user specified delays! */ | |
2593 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2594 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2595 | { | |
2596 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2597 | register. There must be a one instruction delay before INSN2 | |
2598 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2599 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2600 | { |
71400594 RS |
2601 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2602 | return 1; | |
252b5132 | 2603 | } |
71400594 | 2604 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2605 | { |
71400594 RS |
2606 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2607 | return 1; | |
252b5132 RH |
2608 | } |
2609 | else | |
2610 | { | |
71400594 RS |
2611 | /* Read-after-write dependencies on the control registers |
2612 | require a two-instruction gap. */ | |
2613 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2614 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2615 | return 2; | |
2616 | ||
2617 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2618 | also a coprocessor instruction, assume there must be | |
2619 | a one instruction gap. */ | |
2620 | if (pinfo2 & INSN_COP) | |
2621 | return 1; | |
252b5132 RH |
2622 | } |
2623 | } | |
6b76fefe | 2624 | |
71400594 RS |
2625 | /* Check for read-after-write dependencies on the coprocessor |
2626 | control registers in cases where INSN1 does not need a general | |
2627 | coprocessor delay. This means that INSN1 is a floating point | |
2628 | comparison instruction. */ | |
2629 | /* Itbl support may require additional care here. */ | |
2630 | else if (!cop_interlocks | |
2631 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2632 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2633 | return 1; | |
2634 | } | |
6b76fefe | 2635 | |
71400594 | 2636 | #undef INSN2_USES_REG |
6b76fefe | 2637 | |
71400594 RS |
2638 | return 0; |
2639 | } | |
6b76fefe | 2640 | |
7d8e00cf RS |
2641 | /* Return the number of nops that would be needed to work around the |
2642 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
91d6fa6a | 2643 | the MAX_VR4130_NOPS instructions described by HIST. */ |
7d8e00cf RS |
2644 | |
2645 | static int | |
91d6fa6a | 2646 | nops_for_vr4130 (const struct mips_cl_insn *hist, |
7d8e00cf RS |
2647 | const struct mips_cl_insn *insn) |
2648 | { | |
2649 | int i, j, reg; | |
2650 | ||
2651 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2652 | are not affected by the errata. */ | |
2653 | if (insn != 0 | |
2654 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2655 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2656 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2657 | return 0; | |
2658 | ||
2659 | /* Search for the first MFLO or MFHI. */ | |
2660 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 2661 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
2662 | { |
2663 | /* Extract the destination register. */ | |
2664 | if (mips_opts.mips16) | |
91d6fa6a | 2665 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])]; |
7d8e00cf | 2666 | else |
91d6fa6a | 2667 | reg = EXTRACT_OPERAND (RD, hist[i]); |
7d8e00cf RS |
2668 | |
2669 | /* No nops are needed if INSN reads that register. */ | |
2670 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2671 | return 0; | |
2672 | ||
2673 | /* ...or if any of the intervening instructions do. */ | |
2674 | for (j = 0; j < i; j++) | |
91d6fa6a | 2675 | if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG)) |
7d8e00cf RS |
2676 | return 0; |
2677 | ||
2678 | return MAX_VR4130_NOPS - i; | |
2679 | } | |
2680 | return 0; | |
2681 | } | |
2682 | ||
71400594 | 2683 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a NC |
2684 | immediately followed the MAX_NOPS instructions given by HIST, |
2685 | where HIST[0] is the most recent instruction. If INSN is null, | |
71400594 | 2686 | return the worse-case number of nops for any instruction. */ |
bdaaa2e1 | 2687 | |
71400594 | 2688 | static int |
91d6fa6a | 2689 | nops_for_insn (const struct mips_cl_insn *hist, |
71400594 RS |
2690 | const struct mips_cl_insn *insn) |
2691 | { | |
2692 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2693 | |
71400594 | 2694 | nops = 0; |
7d8e00cf | 2695 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
65b02341 | 2696 | { |
91d6fa6a | 2697 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
2698 | if (tmp_nops > nops) |
2699 | nops = tmp_nops; | |
2700 | } | |
7d8e00cf RS |
2701 | |
2702 | if (mips_fix_vr4130) | |
2703 | { | |
91d6fa6a | 2704 | tmp_nops = nops_for_vr4130 (hist, insn); |
7d8e00cf RS |
2705 | if (tmp_nops > nops) |
2706 | nops = tmp_nops; | |
2707 | } | |
2708 | ||
71400594 RS |
2709 | return nops; |
2710 | } | |
252b5132 | 2711 | |
71400594 | 2712 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 2713 | might be added to HIST. Return the largest number of nops that |
71400594 | 2714 | would be needed after the extended sequence. */ |
252b5132 | 2715 | |
71400594 | 2716 | static int |
91d6fa6a | 2717 | nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...) |
71400594 RS |
2718 | { |
2719 | va_list args; | |
2720 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2721 | struct mips_cl_insn *cursor; | |
2722 | int nops; | |
2723 | ||
91d6fa6a | 2724 | va_start (args, hist); |
71400594 | 2725 | cursor = buffer + num_insns; |
91d6fa6a | 2726 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
2727 | while (cursor > buffer) |
2728 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2729 | ||
2730 | nops = nops_for_insn (buffer, NULL); | |
2731 | va_end (args); | |
2732 | return nops; | |
2733 | } | |
252b5132 | 2734 | |
71400594 RS |
2735 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2736 | worst-case delay for the branch target. */ | |
252b5132 | 2737 | |
71400594 | 2738 | static int |
91d6fa6a | 2739 | nops_for_insn_or_target (const struct mips_cl_insn *hist, |
71400594 RS |
2740 | const struct mips_cl_insn *insn) |
2741 | { | |
2742 | int nops, tmp_nops; | |
60b63b72 | 2743 | |
91d6fa6a | 2744 | nops = nops_for_insn (hist, insn); |
71400594 RS |
2745 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
2746 | | INSN_COND_BRANCH_DELAY | |
2747 | | INSN_COND_BRANCH_LIKELY)) | |
2748 | { | |
91d6fa6a | 2749 | tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN); |
71400594 RS |
2750 | if (tmp_nops > nops) |
2751 | nops = tmp_nops; | |
2752 | } | |
9a2c7088 MR |
2753 | else if (mips_opts.mips16 |
2754 | && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2755 | | MIPS16_INSN_COND_BRANCH))) | |
71400594 | 2756 | { |
91d6fa6a | 2757 | tmp_nops = nops_for_sequence (1, hist, insn); |
71400594 RS |
2758 | if (tmp_nops > nops) |
2759 | nops = tmp_nops; | |
2760 | } | |
2761 | return nops; | |
2762 | } | |
2763 | ||
c67a084a NC |
2764 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
2765 | ||
2766 | static void | |
2767 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
2768 | { | |
2769 | if (strcmp (ip->insn_mo->name, "nop") == 0) | |
2770 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
2771 | } | |
2772 | ||
2773 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
2774 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
2775 | ||
2776 | static void | |
2777 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
2778 | { | |
2779 | if (strcmp (ip->insn_mo->name, "j") == 0 | |
2780 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
2781 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
2782 | { | |
2783 | int sreg; | |
2784 | expressionS ep; | |
2785 | ||
2786 | if (! mips_opts.at) | |
2787 | return; | |
2788 | ||
2789 | sreg = EXTRACT_OPERAND (RS, *ip); | |
2790 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) | |
2791 | return; | |
2792 | ||
2793 | ep.X_op = O_constant; | |
2794 | ep.X_add_number = 0xcfff0000; | |
2795 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
2796 | ep.X_add_number = 0xffff; | |
2797 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
2798 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
2799 | } | |
2800 | } | |
2801 | ||
2802 | static void | |
2803 | fix_loongson2f (struct mips_cl_insn * ip) | |
2804 | { | |
2805 | if (mips_fix_loongson2f_nop) | |
2806 | fix_loongson2f_nop (ip); | |
2807 | ||
2808 | if (mips_fix_loongson2f_jump) | |
2809 | fix_loongson2f_jump (ip); | |
2810 | } | |
2811 | ||
71400594 RS |
2812 | /* Output an instruction. IP is the instruction information. |
2813 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2814 | RELOC_TYPE. */ | |
2815 | ||
2816 | static void | |
2817 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2818 | bfd_reloc_code_real_type *reloc_type) | |
2819 | { | |
3994f87e | 2820 | unsigned long prev_pinfo, pinfo; |
98675402 | 2821 | unsigned long prev_pinfo2, pinfo2; |
71400594 RS |
2822 | relax_stateT prev_insn_frag_type = 0; |
2823 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2824 | segment_info_type *si = seg_info (now_seg); |
71400594 | 2825 | |
c67a084a NC |
2826 | if (mips_fix_loongson2f) |
2827 | fix_loongson2f (ip); | |
2828 | ||
71400594 RS |
2829 | /* Mark instruction labels in mips16 mode. */ |
2830 | mips16_mark_labels (); | |
2831 | ||
738f4d98 MR |
2832 | file_ase_mips16 |= mips_opts.mips16; |
2833 | ||
71400594 | 2834 | prev_pinfo = history[0].insn_mo->pinfo; |
98675402 | 2835 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 2836 | pinfo = ip->insn_mo->pinfo; |
98675402 | 2837 | pinfo2 = ip->insn_mo->pinfo2; |
71400594 RS |
2838 | |
2839 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2840 | { | |
2841 | /* There are a lot of optimizations we could do that we don't. | |
2842 | In particular, we do not, in general, reorder instructions. | |
2843 | If you use gcc with optimization, it will reorder | |
2844 | instructions and generally do much more optimization then we | |
2845 | do here; repeating all that work in the assembler would only | |
2846 | benefit hand written assembly code, and does not seem worth | |
2847 | it. */ | |
2848 | int nops = (mips_optimize == 0 | |
2849 | ? nops_for_insn (history, NULL) | |
2850 | : nops_for_insn_or_target (history, ip)); | |
2851 | if (nops > 0) | |
252b5132 RH |
2852 | { |
2853 | fragS *old_frag; | |
2854 | unsigned long old_frag_offset; | |
2855 | int i; | |
252b5132 RH |
2856 | |
2857 | old_frag = frag_now; | |
2858 | old_frag_offset = frag_now_fix (); | |
2859 | ||
2860 | for (i = 0; i < nops; i++) | |
2861 | emit_nop (); | |
2862 | ||
2863 | if (listing) | |
2864 | { | |
2865 | listing_prev_line (); | |
2866 | /* We may be at the start of a variant frag. In case we | |
2867 | are, make sure there is enough space for the frag | |
2868 | after the frags created by listing_prev_line. The | |
2869 | argument to frag_grow here must be at least as large | |
2870 | as the argument to all other calls to frag_grow in | |
2871 | this file. We don't have to worry about being in the | |
2872 | middle of a variant frag, because the variants insert | |
2873 | all needed nop instructions themselves. */ | |
2874 | frag_grow (40); | |
2875 | } | |
2876 | ||
404a8071 | 2877 | mips_move_labels (); |
252b5132 RH |
2878 | |
2879 | #ifndef NO_ECOFF_DEBUGGING | |
2880 | if (ECOFF_DEBUGGING) | |
2881 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2882 | #endif | |
2883 | } | |
71400594 RS |
2884 | } |
2885 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2886 | { | |
2887 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2888 | int nops = nops_for_insn_or_target (history, ip); | |
9c2799c2 | 2889 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 2890 | |
71400594 RS |
2891 | /* Enforce NOPS as a minimum. */ |
2892 | if (nops > prev_nop_frag_required) | |
2893 | prev_nop_frag_required = nops; | |
252b5132 | 2894 | |
71400594 RS |
2895 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2896 | { | |
2897 | /* Settle for the current number of nops. Update the history | |
2898 | accordingly (for the benefit of any future .set reorder code). */ | |
2899 | prev_nop_frag = NULL; | |
2900 | insert_into_history (prev_nop_frag_since, | |
2901 | prev_nop_frag_holds, NOP_INSN); | |
2902 | } | |
2903 | else | |
2904 | { | |
2905 | /* Allow this instruction to replace one of the nops that was | |
2906 | tentatively added to prev_nop_frag. */ | |
2907 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2908 | prev_nop_frag_holds--; | |
2909 | prev_nop_frag_since++; | |
252b5132 RH |
2910 | } |
2911 | } | |
2912 | ||
58e2ea4d MR |
2913 | #ifdef OBJ_ELF |
2914 | /* The value passed to dwarf2_emit_insn is the distance between | |
2915 | the beginning of the current instruction and the address that | |
2916 | should be recorded in the debug tables. For MIPS16 debug info | |
2917 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2918 | address higher by one than the current. */ | |
2919 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2920 | #endif | |
2921 | ||
895921c9 | 2922 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2923 | if (history[0].frag) |
2924 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2925 | |
4d7206a2 | 2926 | if (address_expr |
0b25d3e6 | 2927 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2928 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2929 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2930 | && mips_relax_branch | |
2931 | /* Don't try branch relaxation within .set nomacro, or within | |
2932 | .set noat if we use $at for PIC computations. If it turns | |
2933 | out that the branch was out-of-range, we'll get an error. */ | |
2934 | && !mips_opts.warn_about_macros | |
741fe287 | 2935 | && (mips_opts.at || mips_pic == NO_PIC) |
d455268f MR |
2936 | /* Don't relax BPOSGE32/64 as they have no complementing branches. */ |
2937 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)) | |
4a6a3df4 AO |
2938 | && !mips_opts.mips16) |
2939 | { | |
895921c9 | 2940 | relaxed_branch = TRUE; |
1e915849 RS |
2941 | add_relaxed_insn (ip, (relaxed_branch_length |
2942 | (NULL, NULL, | |
2943 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2944 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2945 | : 0)), 4, | |
2946 | RELAX_BRANCH_ENCODE | |
66b3e8da MR |
2947 | (AT, |
2948 | pinfo & INSN_UNCOND_BRANCH_DELAY, | |
1e915849 RS |
2949 | pinfo & INSN_COND_BRANCH_LIKELY, |
2950 | pinfo & INSN_WRITE_GPR_31, | |
2951 | 0), | |
2952 | address_expr->X_add_symbol, | |
2953 | address_expr->X_add_number); | |
4a6a3df4 AO |
2954 | *reloc_type = BFD_RELOC_UNUSED; |
2955 | } | |
2956 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2957 | { |
2958 | /* We need to set up a variant frag. */ | |
9c2799c2 | 2959 | gas_assert (mips_opts.mips16 && address_expr != NULL); |
1e915849 RS |
2960 | add_relaxed_insn (ip, 4, 0, |
2961 | RELAX_MIPS16_ENCODE | |
2962 | (*reloc_type - BFD_RELOC_UNUSED, | |
2963 | mips16_small, mips16_ext, | |
2964 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2965 | history[0].mips16_absolute_jump_p), | |
2966 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2967 | } |
252b5132 RH |
2968 | else if (mips_opts.mips16 |
2969 | && ! ip->use_extend | |
f6688943 | 2970 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2971 | { |
b8ee1a6e DU |
2972 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2973 | /* Make sure there is enough room to swap this instruction with | |
2974 | a following jump instruction. */ | |
2975 | frag_grow (6); | |
1e915849 | 2976 | add_fixed_insn (ip); |
252b5132 RH |
2977 | } |
2978 | else | |
2979 | { | |
2980 | if (mips_opts.mips16 | |
2981 | && mips_opts.noreorder | |
2982 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2983 | as_warn (_("extended instruction in delay slot")); | |
2984 | ||
4d7206a2 RS |
2985 | if (mips_relax.sequence) |
2986 | { | |
2987 | /* If we've reached the end of this frag, turn it into a variant | |
2988 | frag and record the information for the instructions we've | |
2989 | written so far. */ | |
2990 | if (frag_room () < 4) | |
2991 | relax_close_frag (); | |
2992 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2993 | } | |
2994 | ||
584892a6 RS |
2995 | if (mips_relax.sequence != 2) |
2996 | mips_macro_warning.sizes[0] += 4; | |
2997 | if (mips_relax.sequence != 1) | |
2998 | mips_macro_warning.sizes[1] += 4; | |
2999 | ||
1e915849 RS |
3000 | if (mips_opts.mips16) |
3001 | { | |
3002 | ip->fixed_p = 1; | |
3003 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
3004 | } | |
3005 | add_fixed_insn (ip); | |
252b5132 RH |
3006 | } |
3007 | ||
01a3f561 | 3008 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
3009 | { |
3010 | if (address_expr->X_op == O_constant) | |
3011 | { | |
f17c130b | 3012 | unsigned int tmp; |
f6688943 TS |
3013 | |
3014 | switch (*reloc_type) | |
252b5132 RH |
3015 | { |
3016 | case BFD_RELOC_32: | |
3017 | ip->insn_opcode |= address_expr->X_add_number; | |
3018 | break; | |
3019 | ||
f6688943 | 3020 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
3021 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
3022 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3023 | break; |
3024 | ||
3025 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
3026 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
3027 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3028 | break; |
3029 | ||
3030 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
3031 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
3032 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3033 | break; |
3034 | ||
3035 | case BFD_RELOC_HI16: | |
3036 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
3037 | break; | |
3038 | ||
01a3f561 | 3039 | case BFD_RELOC_UNUSED: |
252b5132 | 3040 | case BFD_RELOC_LO16: |
ed6fb7bd | 3041 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
3042 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
3043 | break; | |
3044 | ||
3045 | case BFD_RELOC_MIPS_JMP: | |
3046 | if ((address_expr->X_add_number & 3) != 0) | |
3047 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3048 | (unsigned long) address_expr->X_add_number); | |
3049 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
3050 | break; | |
3051 | ||
3052 | case BFD_RELOC_MIPS16_JMP: | |
3053 | if ((address_expr->X_add_number & 3) != 0) | |
3054 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3055 | (unsigned long) address_expr->X_add_number); | |
3056 | ip->insn_opcode |= | |
3057 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
3058 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
3059 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
3060 | break; | |
3061 | ||
252b5132 | 3062 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
3063 | if ((address_expr->X_add_number & 3) != 0) |
3064 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3065 | (unsigned long) address_expr->X_add_number); | |
3066 | if (mips_relax_branch) | |
3067 | goto need_reloc; | |
3068 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
3069 | as_bad (_("branch address range overflow (0x%lx)"), | |
3070 | (unsigned long) address_expr->X_add_number); | |
3071 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
3072 | break; | |
252b5132 RH |
3073 | |
3074 | default: | |
3075 | internalError (); | |
3076 | } | |
3077 | } | |
01a3f561 | 3078 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 3079 | need_reloc: |
4d7206a2 RS |
3080 | { |
3081 | reloc_howto_type *howto; | |
3082 | int i; | |
34ce925e | 3083 | |
4d7206a2 RS |
3084 | /* In a compound relocation, it is the final (outermost) |
3085 | operator that determines the relocated field. */ | |
3086 | for (i = 1; i < 3; i++) | |
3087 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
3088 | break; | |
34ce925e | 3089 | |
4d7206a2 | 3090 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
23fce1e3 NC |
3091 | if (howto == NULL) |
3092 | { | |
3093 | /* To reproduce this failure try assembling gas/testsuites/ | |
3094 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
3095 | assembler. */ | |
3096 | as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]); | |
3097 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); | |
3098 | } | |
3099 | ||
1e915849 RS |
3100 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
3101 | bfd_get_reloc_size (howto), | |
3102 | address_expr, | |
3103 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
3104 | reloc_type[0]); | |
4d7206a2 | 3105 | |
b314ec0e RS |
3106 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
3107 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
3108 | && ip->fixp[0]->fx_addsy) | |
3109 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
3110 | ||
4d7206a2 RS |
3111 | /* These relocations can have an addend that won't fit in |
3112 | 4 octets for 64bit assembly. */ | |
3113 | if (HAVE_64BIT_GPRS | |
3114 | && ! howto->partial_inplace | |
3115 | && (reloc_type[0] == BFD_RELOC_16 | |
3116 | || reloc_type[0] == BFD_RELOC_32 | |
3117 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4d7206a2 RS |
3118 | || reloc_type[0] == BFD_RELOC_GPREL16 |
3119 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
3120 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
3121 | || reloc_type[0] == BFD_RELOC_64 | |
3122 | || reloc_type[0] == BFD_RELOC_CTOR | |
3123 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
3124 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
3125 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
3126 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
3127 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
3128 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
3129 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
738e5348 RS |
3130 | || hi16_reloc_p (reloc_type[0]) |
3131 | || lo16_reloc_p (reloc_type[0]))) | |
1e915849 | 3132 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
3133 | |
3134 | if (mips_relax.sequence) | |
3135 | { | |
3136 | if (mips_relax.first_fixup == 0) | |
1e915849 | 3137 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
3138 | } |
3139 | else if (reloc_needs_lo_p (*reloc_type)) | |
3140 | { | |
3141 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 3142 | |
4d7206a2 RS |
3143 | /* Reuse the last entry if it already has a matching %lo. */ |
3144 | hi_fixup = mips_hi_fixup_list; | |
3145 | if (hi_fixup == 0 | |
3146 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
3147 | { | |
3148 | hi_fixup = ((struct mips_hi_fixup *) | |
3149 | xmalloc (sizeof (struct mips_hi_fixup))); | |
3150 | hi_fixup->next = mips_hi_fixup_list; | |
3151 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 3152 | } |
1e915849 | 3153 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
3154 | hi_fixup->seg = now_seg; |
3155 | } | |
f6688943 | 3156 | |
4d7206a2 RS |
3157 | /* Add fixups for the second and third relocations, if given. |
3158 | Note that the ABI allows the second relocation to be | |
3159 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
3160 | moment we only use RSS_UNDEF, but we could add support | |
3161 | for the others if it ever becomes necessary. */ | |
3162 | for (i = 1; i < 3; i++) | |
3163 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
3164 | { | |
1e915849 RS |
3165 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
3166 | ip->fixp[0]->fx_size, NULL, 0, | |
3167 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
3168 | |
3169 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
3170 | ip->fixp[0]->fx_tcbit = 1; |
3171 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 3172 | } |
252b5132 RH |
3173 | } |
3174 | } | |
1e915849 | 3175 | install_insn (ip); |
252b5132 RH |
3176 | |
3177 | /* Update the register mask information. */ | |
3178 | if (! mips_opts.mips16) | |
3179 | { | |
98675402 | 3180 | if ((pinfo & INSN_WRITE_GPR_D) || (pinfo2 & INSN2_READ_GPR_D)) |
bf12938e | 3181 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 3182 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 3183 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 3184 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 3185 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 3186 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 3187 | mips_gprmask |= 1 << RA; |
98675402 RS |
3188 | if (pinfo2 & (INSN2_WRITE_GPR_Z | INSN2_READ_GPR_Z)) |
3189 | mips_gprmask |= 1 << EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 3190 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 3191 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 3192 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 3193 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 3194 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 3195 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 3196 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 3197 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
98675402 RS |
3198 | if (pinfo2 & (INSN2_WRITE_FPR_Z | INSN2_READ_FPR_Z)) |
3199 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FZ, *ip); | |
252b5132 RH |
3200 | if (pinfo & INSN_COP) |
3201 | { | |
bdaaa2e1 KH |
3202 | /* We don't keep enough information to sort these cases out. |
3203 | The itbl support does keep this information however, although | |
3204 | we currently don't support itbl fprmats as part of the cop | |
3205 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
3206 | } |
3207 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 3208 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
3209 | } |
3210 | else | |
3211 | { | |
3212 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 3213 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 3214 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 3215 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 3216 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 3217 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
3218 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
3219 | mips_gprmask |= 1 << TREG; | |
3220 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
3221 | mips_gprmask |= 1 << SP; | |
3222 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
3223 | mips_gprmask |= 1 << RA; | |
3224 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3225 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3226 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 3227 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 3228 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 3229 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
3230 | } |
3231 | ||
4d7206a2 | 3232 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3233 | { |
3234 | /* Filling the branch delay slot is more complex. We try to | |
3235 | switch the branch with the previous instruction, which we can | |
3236 | do if the previous instruction does not set up a condition | |
3237 | that the branch tests and if the branch is not itself the | |
3238 | target of any branch. */ | |
3239 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3240 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3241 | { | |
3242 | if (mips_optimize < 2 | |
3243 | /* If we have seen .set volatile or .set nomove, don't | |
3244 | optimize. */ | |
3245 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3246 | /* We can't swap if the previous instruction's position |
3247 | is fixed. */ | |
3248 | || history[0].fixed_p | |
252b5132 RH |
3249 | /* If the previous previous insn was in a .set |
3250 | noreorder, we can't swap. Actually, the MIPS | |
3251 | assembler will swap in this situation. However, gcc | |
3252 | configured -with-gnu-as will generate code like | |
3253 | .set noreorder | |
3254 | lw $4,XXX | |
3255 | .set reorder | |
3256 | INSN | |
3257 | bne $4,$0,foo | |
3258 | in which we can not swap the bne and INSN. If gcc is | |
3259 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3260 | .set pseudo-ops. */ |
47e39b9d | 3261 | || history[1].noreorder_p |
252b5132 RH |
3262 | /* If the branch is itself the target of a branch, we |
3263 | can not swap. We cheat on this; all we check for is | |
3264 | whether there is a label on this instruction. If | |
3265 | there are any branches to anything other than a | |
3266 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3267 | || si->label_list != NULL |
895921c9 MR |
3268 | /* If the previous instruction is in a variant frag |
3269 | other than this branch's one, we cannot do the swap. | |
3270 | This does not apply to the mips16, which uses variant | |
3271 | frags for different purposes. */ | |
252b5132 | 3272 | || (! mips_opts.mips16 |
895921c9 | 3273 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3274 | /* Check for conflicts between the branch and the instructions |
3275 | before the candidate delay slot. */ | |
3276 | || nops_for_insn (history + 1, ip) > 0 | |
3277 | /* Check for conflicts between the swapped sequence and the | |
3278 | target of the branch. */ | |
3279 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
3280 | /* We do not swap with a trap instruction, since it |
3281 | complicates trap handlers to have the trap | |
3282 | instruction be in a delay slot. */ | |
3283 | || (prev_pinfo & INSN_TRAP) | |
3284 | /* If the branch reads a register that the previous | |
3285 | instruction sets, we can not swap. */ | |
3286 | || (! mips_opts.mips16 | |
3287 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 3288 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
3289 | MIPS_GR_REG)) |
3290 | || (! mips_opts.mips16 | |
3291 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3292 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 | 3293 | MIPS_GR_REG)) |
98675402 RS |
3294 | || (! mips_opts.mips16 |
3295 | && (prev_pinfo2 & INSN2_WRITE_GPR_Z) | |
3296 | && insn_uses_reg (ip, EXTRACT_OPERAND (RZ, history[0]), | |
3297 | MIPS_GR_REG)) | |
252b5132 RH |
3298 | || (mips_opts.mips16 |
3299 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
3300 | && (insn_uses_reg |
3301 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
3302 | MIPS16_REG))) | |
252b5132 | 3303 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
3304 | && (insn_uses_reg |
3305 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
3306 | MIPS16_REG))) | |
252b5132 | 3307 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
3308 | && (insn_uses_reg |
3309 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
3310 | MIPS16_REG))) | |
252b5132 RH |
3311 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
3312 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3313 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3314 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3315 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3316 | && insn_uses_reg (ip, | |
47e39b9d RS |
3317 | MIPS16OP_EXTRACT_REG32R |
3318 | (history[0].insn_opcode), | |
252b5132 RH |
3319 | MIPS_GR_REG)))) |
3320 | /* If the branch writes a register that the previous | |
3321 | instruction sets, we can not swap (we know that | |
3322 | branches write only to RD or to $31). */ | |
3323 | || (! mips_opts.mips16 | |
3324 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3325 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3326 | && (EXTRACT_OPERAND (RT, history[0]) |
3327 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3328 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3329 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3330 | || (! mips_opts.mips16 |
3331 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3332 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3333 | && (EXTRACT_OPERAND (RD, history[0]) |
3334 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3335 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3336 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3337 | || (mips_opts.mips16 |
3338 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3339 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3340 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3341 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3342 | == RA)))) |
3343 | /* If the branch writes a register that the previous | |
3344 | instruction reads, we can not swap (we know that | |
3345 | branches only write to RD or to $31). */ | |
3346 | || (! mips_opts.mips16 | |
3347 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3348 | && insn_uses_reg (&history[0], |
bf12938e | 3349 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3350 | MIPS_GR_REG)) |
3351 | || (! mips_opts.mips16 | |
3352 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3353 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3354 | || (mips_opts.mips16 |
3355 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3356 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3357 | /* If one instruction sets a condition code and the |
3358 | other one uses a condition code, we can not swap. */ | |
3359 | || ((pinfo & INSN_READ_COND_CODE) | |
3360 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3361 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3362 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3363 | /* If the previous instruction uses the PC, we can not | |
3364 | swap. */ | |
3365 | || (mips_opts.mips16 | |
3366 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3367 | /* If the previous instruction had a fixup in mips16 |
3368 | mode, we can not swap. This normally means that the | |
3369 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3370 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3371 | /* If the previous instruction is a sync, sync.l, or |
3372 | sync.p, we can not swap. */ | |
6a32d874 CM |
3373 | || (prev_pinfo & INSN_SYNC) |
3374 | /* If the previous instruction is an ERET or | |
3375 | DERET, avoid the swap. */ | |
3376 | || (history[0].insn_opcode == INSN_ERET) | |
3377 | || (history[0].insn_opcode == INSN_DERET)) | |
252b5132 | 3378 | { |
29024861 DU |
3379 | if (mips_opts.mips16 |
3380 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3381 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3382 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3383 | { |
3384 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3385 | ip->insn_opcode |= 0x0080; | |
3386 | install_insn (ip); | |
3387 | insert_into_history (0, 1, ip); | |
3388 | } | |
3389 | else | |
3390 | { | |
3391 | /* We could do even better for unconditional branches to | |
3392 | portions of this object file; we could pick up the | |
3393 | instruction at the destination, put it in the delay | |
3394 | slot, and bump the destination address. */ | |
3395 | insert_into_history (0, 1, ip); | |
3396 | emit_nop (); | |
3397 | } | |
3398 | ||
dd22970f ILT |
3399 | if (mips_relax.sequence) |
3400 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3401 | } |
3402 | else | |
3403 | { | |
3404 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3405 | struct mips_cl_insn delay = history[0]; |
3406 | if (mips_opts.mips16) | |
252b5132 | 3407 | { |
b8ee1a6e DU |
3408 | know (delay.frag == ip->frag); |
3409 | move_insn (ip, delay.frag, delay.where); | |
3410 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3411 | } |
3412 | else if (relaxed_branch) | |
3413 | { | |
3414 | /* Add the delay slot instruction to the end of the | |
3415 | current frag and shrink the fixed part of the | |
3416 | original frag. If the branch occupies the tail of | |
3417 | the latter, move it backwards to cover the gap. */ | |
3418 | delay.frag->fr_fix -= 4; | |
3419 | if (delay.frag == ip->frag) | |
3420 | move_insn (ip, ip->frag, ip->where - 4); | |
3421 | add_fixed_insn (&delay); | |
252b5132 RH |
3422 | } |
3423 | else | |
3424 | { | |
1e915849 RS |
3425 | move_insn (&delay, ip->frag, ip->where); |
3426 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3427 | } |
1e915849 RS |
3428 | history[0] = *ip; |
3429 | delay.fixed_p = 1; | |
3430 | insert_into_history (0, 1, &delay); | |
252b5132 | 3431 | } |
252b5132 RH |
3432 | |
3433 | /* If that was an unconditional branch, forget the previous | |
3434 | insn information. */ | |
3435 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
6a32d874 | 3436 | { |
6a32d874 CM |
3437 | mips_no_prev_insn (); |
3438 | } | |
252b5132 RH |
3439 | } |
3440 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3441 | { | |
3442 | /* We don't yet optimize a branch likely. What we should do | |
3443 | is look at the target, copy the instruction found there | |
3444 | into the delay slot, and increment the branch to jump to | |
3445 | the next instruction. */ | |
1e915849 | 3446 | insert_into_history (0, 1, ip); |
252b5132 | 3447 | emit_nop (); |
252b5132 RH |
3448 | } |
3449 | else | |
1e915849 | 3450 | insert_into_history (0, 1, ip); |
252b5132 | 3451 | } |
1e915849 RS |
3452 | else |
3453 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3454 | |
3455 | /* We just output an insn, so the next one doesn't have a label. */ | |
3456 | mips_clear_insn_labels (); | |
252b5132 RH |
3457 | } |
3458 | ||
7d10b47d | 3459 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3460 | |
3461 | static void | |
7d10b47d | 3462 | mips_no_prev_insn (void) |
252b5132 | 3463 | { |
7d10b47d RS |
3464 | prev_nop_frag = NULL; |
3465 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3466 | mips_clear_insn_labels (); |
3467 | } | |
3468 | ||
7d10b47d RS |
3469 | /* This function must be called before we emit something other than |
3470 | instructions. It is like mips_no_prev_insn except that it inserts | |
3471 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3472 | |
7d10b47d RS |
3473 | void |
3474 | mips_emit_delays (void) | |
252b5132 RH |
3475 | { |
3476 | if (! mips_opts.noreorder) | |
3477 | { | |
71400594 | 3478 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3479 | if (nops > 0) |
3480 | { | |
7d10b47d RS |
3481 | while (nops-- > 0) |
3482 | add_fixed_insn (NOP_INSN); | |
3483 | mips_move_labels (); | |
3484 | } | |
3485 | } | |
3486 | mips_no_prev_insn (); | |
3487 | } | |
3488 | ||
3489 | /* Start a (possibly nested) noreorder block. */ | |
3490 | ||
3491 | static void | |
3492 | start_noreorder (void) | |
3493 | { | |
3494 | if (mips_opts.noreorder == 0) | |
3495 | { | |
3496 | unsigned int i; | |
3497 | int nops; | |
3498 | ||
3499 | /* None of the instructions before the .set noreorder can be moved. */ | |
3500 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3501 | history[i].fixed_p = 1; | |
3502 | ||
3503 | /* Insert any nops that might be needed between the .set noreorder | |
3504 | block and the previous instructions. We will later remove any | |
3505 | nops that turn out not to be needed. */ | |
3506 | nops = nops_for_insn (history, NULL); | |
3507 | if (nops > 0) | |
3508 | { | |
3509 | if (mips_optimize != 0) | |
252b5132 RH |
3510 | { |
3511 | /* Record the frag which holds the nop instructions, so | |
3512 | that we can remove them if we don't need them. */ | |
3513 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3514 | prev_nop_frag = frag_now; | |
3515 | prev_nop_frag_holds = nops; | |
3516 | prev_nop_frag_required = 0; | |
3517 | prev_nop_frag_since = 0; | |
3518 | } | |
3519 | ||
3520 | for (; nops > 0; --nops) | |
1e915849 | 3521 | add_fixed_insn (NOP_INSN); |
252b5132 | 3522 | |
7d10b47d RS |
3523 | /* Move on to a new frag, so that it is safe to simply |
3524 | decrease the size of prev_nop_frag. */ | |
3525 | frag_wane (frag_now); | |
3526 | frag_new (0); | |
404a8071 | 3527 | mips_move_labels (); |
252b5132 | 3528 | } |
7d10b47d RS |
3529 | mips16_mark_labels (); |
3530 | mips_clear_insn_labels (); | |
252b5132 | 3531 | } |
7d10b47d RS |
3532 | mips_opts.noreorder++; |
3533 | mips_any_noreorder = 1; | |
3534 | } | |
252b5132 | 3535 | |
7d10b47d | 3536 | /* End a nested noreorder block. */ |
252b5132 | 3537 | |
7d10b47d RS |
3538 | static void |
3539 | end_noreorder (void) | |
3540 | { | |
6a32d874 | 3541 | |
7d10b47d RS |
3542 | mips_opts.noreorder--; |
3543 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3544 | { | |
3545 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3546 | handling nop insertion the .set reorder way. */ | |
3547 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3548 | * (mips_opts.mips16 ? 2 : 4)); | |
3549 | insert_into_history (prev_nop_frag_since, | |
3550 | prev_nop_frag_required, NOP_INSN); | |
3551 | prev_nop_frag = NULL; | |
3552 | } | |
252b5132 RH |
3553 | } |
3554 | ||
584892a6 RS |
3555 | /* Set up global variables for the start of a new macro. */ |
3556 | ||
3557 | static void | |
3558 | macro_start (void) | |
3559 | { | |
3560 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3561 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3562 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3563 | & (INSN_UNCOND_BRANCH_DELAY |
3564 | | INSN_COND_BRANCH_DELAY | |
3565 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3566 | } | |
3567 | ||
3568 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3569 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3570 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3571 | ||
3572 | static const char * | |
3573 | macro_warning (relax_substateT subtype) | |
3574 | { | |
3575 | if (subtype & RELAX_DELAY_SLOT) | |
3576 | return _("Macro instruction expanded into multiple instructions" | |
3577 | " in a branch delay slot"); | |
3578 | else if (subtype & RELAX_NOMACRO) | |
3579 | return _("Macro instruction expanded into multiple instructions"); | |
3580 | else | |
3581 | return 0; | |
3582 | } | |
3583 | ||
3584 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3585 | ||
3586 | static void | |
3587 | macro_end (void) | |
3588 | { | |
3589 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3590 | { | |
3591 | relax_substateT subtype; | |
3592 | ||
3593 | /* Set up the relaxation warning flags. */ | |
3594 | subtype = 0; | |
3595 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3596 | subtype |= RELAX_SECOND_LONGER; | |
3597 | if (mips_opts.warn_about_macros) | |
3598 | subtype |= RELAX_NOMACRO; | |
3599 | if (mips_macro_warning.delay_slot_p) | |
3600 | subtype |= RELAX_DELAY_SLOT; | |
3601 | ||
3602 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3603 | { | |
3604 | /* Either the macro has a single implementation or both | |
3605 | implementations are longer than 4 bytes. Emit the | |
3606 | warning now. */ | |
3607 | const char *msg = macro_warning (subtype); | |
3608 | if (msg != 0) | |
520725ea | 3609 | as_warn ("%s", msg); |
584892a6 RS |
3610 | } |
3611 | else | |
3612 | { | |
3613 | /* One implementation might need a warning but the other | |
3614 | definitely doesn't. */ | |
3615 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3616 | } | |
3617 | } | |
3618 | } | |
3619 | ||
6e1304d8 RS |
3620 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3621 | The first argument in *ARGS will be either the code for a single | |
3622 | relocation or -1 followed by the three codes that make up a | |
3623 | composite relocation. */ | |
3624 | ||
3625 | static void | |
3626 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3627 | { | |
3628 | int i, next; | |
3629 | ||
3630 | next = va_arg (*args, int); | |
3631 | if (next >= 0) | |
3632 | r[0] = (bfd_reloc_code_real_type) next; | |
3633 | else | |
3634 | for (i = 0; i < 3; i++) | |
3635 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3636 | } | |
3637 | ||
252b5132 RH |
3638 | /* Build an instruction created by a macro expansion. This is passed |
3639 | a pointer to the count of instructions created so far, an | |
3640 | expression, the name of the instruction to build, an operand format | |
3641 | string, and corresponding arguments. */ | |
3642 | ||
252b5132 | 3643 | static void |
67c0d1eb | 3644 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3645 | { |
1e915849 | 3646 | const struct mips_opcode *mo; |
252b5132 | 3647 | struct mips_cl_insn insn; |
f6688943 | 3648 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3649 | va_list args; |
252b5132 | 3650 | |
252b5132 | 3651 | va_start (args, fmt); |
252b5132 | 3652 | |
252b5132 RH |
3653 | if (mips_opts.mips16) |
3654 | { | |
03ea81db | 3655 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
3656 | va_end (args); |
3657 | return; | |
3658 | } | |
3659 | ||
f6688943 TS |
3660 | r[0] = BFD_RELOC_UNUSED; |
3661 | r[1] = BFD_RELOC_UNUSED; | |
3662 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 | 3663 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
9c2799c2 NC |
3664 | gas_assert (mo); |
3665 | gas_assert (strcmp (name, mo->name) == 0); | |
1e915849 | 3666 | |
8b082fb1 TS |
3667 | while (1) |
3668 | { | |
3669 | /* Search until we get a match for NAME. It is assumed here that | |
3670 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3671 | if (strcmp (fmt, mo->args) == 0 | |
3672 | && mo->pinfo != INSN_MACRO | |
f79e2745 | 3673 | && is_opcode_valid (mo)) |
8b082fb1 TS |
3674 | break; |
3675 | ||
1e915849 | 3676 | ++mo; |
9c2799c2 NC |
3677 | gas_assert (mo->name); |
3678 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3679 | } |
3680 | ||
1e915849 | 3681 | create_insn (&insn, mo); |
252b5132 RH |
3682 | for (;;) |
3683 | { | |
3684 | switch (*fmt++) | |
3685 | { | |
3686 | case '\0': | |
3687 | break; | |
3688 | ||
3689 | case ',': | |
3690 | case '(': | |
3691 | case ')': | |
3692 | continue; | |
3693 | ||
5f74bc13 CD |
3694 | case '+': |
3695 | switch (*fmt++) | |
3696 | { | |
3697 | case 'A': | |
3698 | case 'E': | |
bf12938e | 3699 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3700 | continue; |
3701 | ||
3702 | case 'B': | |
3703 | case 'F': | |
3704 | /* Note that in the macro case, these arguments are already | |
3705 | in MSB form. (When handling the instruction in the | |
3706 | non-macro case, these arguments are sizes from which | |
3707 | MSB values must be calculated.) */ | |
bf12938e | 3708 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3709 | continue; |
3710 | ||
3711 | case 'C': | |
3712 | case 'G': | |
3713 | case 'H': | |
3714 | /* Note that in the macro case, these arguments are already | |
3715 | in MSBD form. (When handling the instruction in the | |
3716 | non-macro case, these arguments are sizes from which | |
3717 | MSBD values must be calculated.) */ | |
bf12938e | 3718 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3719 | continue; |
3720 | ||
dd3cbb7e NC |
3721 | case 'Q': |
3722 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3723 | continue; | |
3724 | ||
5f74bc13 CD |
3725 | default: |
3726 | internalError (); | |
3727 | } | |
3728 | continue; | |
3729 | ||
8b082fb1 TS |
3730 | case '2': |
3731 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3732 | continue; | |
3733 | ||
252b5132 RH |
3734 | case 't': |
3735 | case 'w': | |
3736 | case 'E': | |
bf12938e | 3737 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3738 | continue; |
3739 | ||
3740 | case 'c': | |
bf12938e | 3741 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3742 | continue; |
3743 | ||
252b5132 RH |
3744 | case 'T': |
3745 | case 'W': | |
bf12938e | 3746 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3747 | continue; |
3748 | ||
3749 | case 'd': | |
3750 | case 'G': | |
af7ee8bf | 3751 | case 'K': |
bf12938e | 3752 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3753 | continue; |
3754 | ||
4372b673 NC |
3755 | case 'U': |
3756 | { | |
3757 | int tmp = va_arg (args, int); | |
3758 | ||
bf12938e RS |
3759 | INSERT_OPERAND (RT, insn, tmp); |
3760 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3761 | continue; |
4372b673 NC |
3762 | } |
3763 | ||
252b5132 RH |
3764 | case 'V': |
3765 | case 'S': | |
bf12938e | 3766 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3767 | continue; |
3768 | ||
3769 | case 'z': | |
3770 | continue; | |
3771 | ||
3772 | case '<': | |
bf12938e | 3773 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3774 | continue; |
3775 | ||
3776 | case 'D': | |
bf12938e | 3777 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3778 | continue; |
3779 | ||
3780 | case 'B': | |
bf12938e | 3781 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3782 | continue; |
3783 | ||
4372b673 | 3784 | case 'J': |
bf12938e | 3785 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3786 | continue; |
3787 | ||
252b5132 | 3788 | case 'q': |
bf12938e | 3789 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3790 | continue; |
3791 | ||
3792 | case 'b': | |
3793 | case 's': | |
3794 | case 'r': | |
3795 | case 'v': | |
bf12938e | 3796 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3797 | continue; |
3798 | ||
3799 | case 'i': | |
3800 | case 'j': | |
6e1304d8 | 3801 | macro_read_relocs (&args, r); |
9c2799c2 | 3802 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
3803 | || *r == BFD_RELOC_MIPS_HIGHER |
3804 | || *r == BFD_RELOC_HI16_S | |
3805 | || *r == BFD_RELOC_LO16 | |
3806 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
3807 | continue; | |
3808 | ||
3809 | case 'o': | |
3810 | macro_read_relocs (&args, r); | |
252b5132 RH |
3811 | continue; |
3812 | ||
3813 | case 'u': | |
6e1304d8 | 3814 | macro_read_relocs (&args, r); |
9c2799c2 | 3815 | gas_assert (ep != NULL |
90ecf173 MR |
3816 | && (ep->X_op == O_constant |
3817 | || (ep->X_op == O_symbol | |
3818 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
3819 | || *r == BFD_RELOC_HI16_S | |
3820 | || *r == BFD_RELOC_HI16 | |
3821 | || *r == BFD_RELOC_GPREL16 | |
3822 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3823 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
3824 | continue; |
3825 | ||
3826 | case 'p': | |
9c2799c2 | 3827 | gas_assert (ep != NULL); |
bad36eac | 3828 | |
252b5132 RH |
3829 | /* |
3830 | * This allows macro() to pass an immediate expression for | |
3831 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3832 | * |
3833 | * We don't allow branch relaxation for these branches, as | |
3834 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3835 | */ |
3836 | if (ep->X_op == O_constant) | |
3837 | { | |
bad36eac DJ |
3838 | if ((ep->X_add_number & 3) != 0) |
3839 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3840 | (unsigned long) ep->X_add_number); | |
3841 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3842 | as_bad (_("branch address range overflow (0x%lx)"), | |
3843 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3844 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3845 | ep = NULL; | |
3846 | } | |
3847 | else | |
0b25d3e6 | 3848 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3849 | continue; |
3850 | ||
3851 | case 'a': | |
9c2799c2 | 3852 | gas_assert (ep != NULL); |
f6688943 | 3853 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3854 | continue; |
3855 | ||
3856 | case 'C': | |
a9e24354 | 3857 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3858 | continue; |
3859 | ||
d43b4baf | 3860 | case 'k': |
a9e24354 | 3861 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3862 | continue; |
3863 | ||
252b5132 RH |
3864 | default: |
3865 | internalError (); | |
3866 | } | |
3867 | break; | |
3868 | } | |
3869 | va_end (args); | |
9c2799c2 | 3870 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3871 | |
4d7206a2 | 3872 | append_insn (&insn, ep, r); |
252b5132 RH |
3873 | } |
3874 | ||
3875 | static void | |
67c0d1eb | 3876 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 3877 | va_list *args) |
252b5132 | 3878 | { |
1e915849 | 3879 | struct mips_opcode *mo; |
252b5132 | 3880 | struct mips_cl_insn insn; |
f6688943 TS |
3881 | bfd_reloc_code_real_type r[3] |
3882 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3883 | |
1e915849 | 3884 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
3885 | gas_assert (mo); |
3886 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3887 | |
1e915849 | 3888 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3889 | { |
1e915849 | 3890 | ++mo; |
9c2799c2 NC |
3891 | gas_assert (mo->name); |
3892 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3893 | } |
3894 | ||
1e915849 | 3895 | create_insn (&insn, mo); |
252b5132 RH |
3896 | for (;;) |
3897 | { | |
3898 | int c; | |
3899 | ||
3900 | c = *fmt++; | |
3901 | switch (c) | |
3902 | { | |
3903 | case '\0': | |
3904 | break; | |
3905 | ||
3906 | case ',': | |
3907 | case '(': | |
3908 | case ')': | |
3909 | continue; | |
3910 | ||
3911 | case 'y': | |
3912 | case 'w': | |
03ea81db | 3913 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
3914 | continue; |
3915 | ||
3916 | case 'x': | |
3917 | case 'v': | |
03ea81db | 3918 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
3919 | continue; |
3920 | ||
3921 | case 'z': | |
03ea81db | 3922 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
3923 | continue; |
3924 | ||
3925 | case 'Z': | |
03ea81db | 3926 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
3927 | continue; |
3928 | ||
3929 | case '0': | |
3930 | case 'S': | |
3931 | case 'P': | |
3932 | case 'R': | |
3933 | continue; | |
3934 | ||
3935 | case 'X': | |
03ea81db | 3936 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
3937 | continue; |
3938 | ||
3939 | case 'Y': | |
3940 | { | |
3941 | int regno; | |
3942 | ||
03ea81db | 3943 | regno = va_arg (*args, int); |
252b5132 | 3944 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 3945 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3946 | } |
3947 | continue; | |
3948 | ||
3949 | case '<': | |
3950 | case '>': | |
3951 | case '4': | |
3952 | case '5': | |
3953 | case 'H': | |
3954 | case 'W': | |
3955 | case 'D': | |
3956 | case 'j': | |
3957 | case '8': | |
3958 | case 'V': | |
3959 | case 'C': | |
3960 | case 'U': | |
3961 | case 'k': | |
3962 | case 'K': | |
3963 | case 'p': | |
3964 | case 'q': | |
3965 | { | |
9c2799c2 | 3966 | gas_assert (ep != NULL); |
252b5132 RH |
3967 | |
3968 | if (ep->X_op != O_constant) | |
874e8986 | 3969 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3970 | else |
3971 | { | |
b34976b6 AM |
3972 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3973 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3974 | &insn.extend); |
252b5132 | 3975 | ep = NULL; |
f6688943 | 3976 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3977 | } |
3978 | } | |
3979 | continue; | |
3980 | ||
3981 | case '6': | |
03ea81db | 3982 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
3983 | continue; |
3984 | } | |
3985 | ||
3986 | break; | |
3987 | } | |
3988 | ||
9c2799c2 | 3989 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3990 | |
4d7206a2 | 3991 | append_insn (&insn, ep, r); |
252b5132 RH |
3992 | } |
3993 | ||
2051e8c4 MR |
3994 | /* |
3995 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3996 | * higher bits unset. | |
3997 | */ | |
9f872bbe | 3998 | static void |
2051e8c4 MR |
3999 | normalize_constant_expr (expressionS *ex) |
4000 | { | |
9ee2a2d4 | 4001 | if (ex->X_op == O_constant |
2051e8c4 MR |
4002 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
4003 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4004 | - 0x80000000); | |
4005 | } | |
4006 | ||
4007 | /* | |
4008 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
4009 | * all higher bits unset. | |
4010 | */ | |
4011 | static void | |
4012 | normalize_address_expr (expressionS *ex) | |
4013 | { | |
4014 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
4015 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
4016 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
4017 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
4018 | - 0x80000000); | |
4019 | } | |
4020 | ||
438c16b8 TS |
4021 | /* |
4022 | * Generate a "jalr" instruction with a relocation hint to the called | |
4023 | * function. This occurs in NewABI PIC code. | |
4024 | */ | |
4025 | static void | |
67c0d1eb | 4026 | macro_build_jalr (expressionS *ep) |
438c16b8 | 4027 | { |
685736be | 4028 | char *f = NULL; |
b34976b6 | 4029 | |
1180b5a4 | 4030 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4031 | { |
cc3d92a5 | 4032 | frag_grow (8); |
f21f8242 AO |
4033 | f = frag_more (0); |
4034 | } | |
67c0d1eb | 4035 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
1180b5a4 | 4036 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4037 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 4038 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
4039 | } |
4040 | ||
252b5132 RH |
4041 | /* |
4042 | * Generate a "lui" instruction. | |
4043 | */ | |
4044 | static void | |
67c0d1eb | 4045 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
4046 | { |
4047 | expressionS high_expr; | |
1e915849 | 4048 | const struct mips_opcode *mo; |
252b5132 | 4049 | struct mips_cl_insn insn; |
f6688943 TS |
4050 | bfd_reloc_code_real_type r[3] |
4051 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
4052 | const char *name = "lui"; |
4053 | const char *fmt = "t,u"; | |
252b5132 | 4054 | |
9c2799c2 | 4055 | gas_assert (! mips_opts.mips16); |
252b5132 | 4056 | |
4d7206a2 | 4057 | high_expr = *ep; |
252b5132 RH |
4058 | |
4059 | if (high_expr.X_op == O_constant) | |
4060 | { | |
54f4ddb3 | 4061 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
4062 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
4063 | >> 16) & 0xffff; | |
f6688943 | 4064 | *r = BFD_RELOC_UNUSED; |
252b5132 | 4065 | } |
78e1bb40 | 4066 | else |
252b5132 | 4067 | { |
9c2799c2 | 4068 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
4069 | /* _gp_disp is a special case, used from s_cpload. |
4070 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 4071 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 4072 | || (! HAVE_NEWABI |
aa6975fb ILT |
4073 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
4074 | || (! mips_in_shared | |
bbe506e8 TS |
4075 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
4076 | "__gnu_local_gp") == 0)); | |
f6688943 | 4077 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
4078 | } |
4079 | ||
1e915849 | 4080 | mo = hash_find (op_hash, name); |
9c2799c2 NC |
4081 | gas_assert (strcmp (name, mo->name) == 0); |
4082 | gas_assert (strcmp (fmt, mo->args) == 0); | |
1e915849 | 4083 | create_insn (&insn, mo); |
252b5132 | 4084 | |
bf12938e RS |
4085 | insn.insn_opcode = insn.insn_mo->match; |
4086 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 4087 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
4088 | { |
4089 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 4090 | append_insn (&insn, NULL, r); |
252b5132 RH |
4091 | } |
4092 | else | |
4d7206a2 | 4093 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
4094 | } |
4095 | ||
885add95 CD |
4096 | /* Generate a sequence of instructions to do a load or store from a constant |
4097 | offset off of a base register (breg) into/from a target register (treg), | |
4098 | using AT if necessary. */ | |
4099 | static void | |
67c0d1eb RS |
4100 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
4101 | int treg, int breg, int dbl) | |
885add95 | 4102 | { |
9c2799c2 | 4103 | gas_assert (ep->X_op == O_constant); |
885add95 | 4104 | |
256ab948 | 4105 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
4106 | if (!dbl) |
4107 | normalize_constant_expr (ep); | |
256ab948 | 4108 | |
67c1ffbe | 4109 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 4110 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
4111 | as_warn (_("operand overflow")); |
4112 | ||
4113 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
4114 | { | |
4115 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 4116 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
4117 | } |
4118 | else | |
4119 | { | |
4120 | /* 32-bit offset, need multiple instructions and AT, like: | |
4121 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
4122 | addu $tempreg,$tempreg,$breg | |
4123 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
4124 | to handle the complete offset. */ | |
67c0d1eb RS |
4125 | macro_build_lui (ep, AT); |
4126 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
4127 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 4128 | |
741fe287 | 4129 | if (!mips_opts.at) |
8fc2e39e | 4130 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
4131 | } |
4132 | } | |
4133 | ||
252b5132 RH |
4134 | /* set_at() |
4135 | * Generates code to set the $at register to true (one) | |
4136 | * if reg is less than the immediate expression. | |
4137 | */ | |
4138 | static void | |
67c0d1eb | 4139 | set_at (int reg, int unsignedp) |
252b5132 RH |
4140 | { |
4141 | if (imm_expr.X_op == O_constant | |
4142 | && imm_expr.X_add_number >= -0x8000 | |
4143 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
4144 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
4145 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
4146 | else |
4147 | { | |
67c0d1eb RS |
4148 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4149 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
4150 | } |
4151 | } | |
4152 | ||
4153 | /* Warn if an expression is not a constant. */ | |
4154 | ||
4155 | static void | |
17a2f251 | 4156 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
4157 | { |
4158 | if (ex->X_op == O_big) | |
4159 | as_bad (_("unsupported large constant")); | |
4160 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
4161 | as_bad (_("Instruction %s requires absolute expression"), |
4162 | ip->insn_mo->name); | |
13757d0c | 4163 | |
9ee2a2d4 MR |
4164 | if (HAVE_32BIT_GPRS) |
4165 | normalize_constant_expr (ex); | |
252b5132 RH |
4166 | } |
4167 | ||
4168 | /* Count the leading zeroes by performing a binary chop. This is a | |
4169 | bulky bit of source, but performance is a LOT better for the | |
4170 | majority of values than a simple loop to count the bits: | |
4171 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
4172 | if ((v) & (1 << (31 - lcnt))) | |
4173 | break; | |
4174 | However it is not code size friendly, and the gain will drop a bit | |
4175 | on certain cached systems. | |
4176 | */ | |
4177 | #define COUNT_TOP_ZEROES(v) \ | |
4178 | (((v) & ~0xffff) == 0 \ | |
4179 | ? ((v) & ~0xff) == 0 \ | |
4180 | ? ((v) & ~0xf) == 0 \ | |
4181 | ? ((v) & ~0x3) == 0 \ | |
4182 | ? ((v) & ~0x1) == 0 \ | |
4183 | ? !(v) \ | |
4184 | ? 32 \ | |
4185 | : 31 \ | |
4186 | : 30 \ | |
4187 | : ((v) & ~0x7) == 0 \ | |
4188 | ? 29 \ | |
4189 | : 28 \ | |
4190 | : ((v) & ~0x3f) == 0 \ | |
4191 | ? ((v) & ~0x1f) == 0 \ | |
4192 | ? 27 \ | |
4193 | : 26 \ | |
4194 | : ((v) & ~0x7f) == 0 \ | |
4195 | ? 25 \ | |
4196 | : 24 \ | |
4197 | : ((v) & ~0xfff) == 0 \ | |
4198 | ? ((v) & ~0x3ff) == 0 \ | |
4199 | ? ((v) & ~0x1ff) == 0 \ | |
4200 | ? 23 \ | |
4201 | : 22 \ | |
4202 | : ((v) & ~0x7ff) == 0 \ | |
4203 | ? 21 \ | |
4204 | : 20 \ | |
4205 | : ((v) & ~0x3fff) == 0 \ | |
4206 | ? ((v) & ~0x1fff) == 0 \ | |
4207 | ? 19 \ | |
4208 | : 18 \ | |
4209 | : ((v) & ~0x7fff) == 0 \ | |
4210 | ? 17 \ | |
4211 | : 16 \ | |
4212 | : ((v) & ~0xffffff) == 0 \ | |
4213 | ? ((v) & ~0xfffff) == 0 \ | |
4214 | ? ((v) & ~0x3ffff) == 0 \ | |
4215 | ? ((v) & ~0x1ffff) == 0 \ | |
4216 | ? 15 \ | |
4217 | : 14 \ | |
4218 | : ((v) & ~0x7ffff) == 0 \ | |
4219 | ? 13 \ | |
4220 | : 12 \ | |
4221 | : ((v) & ~0x3fffff) == 0 \ | |
4222 | ? ((v) & ~0x1fffff) == 0 \ | |
4223 | ? 11 \ | |
4224 | : 10 \ | |
4225 | : ((v) & ~0x7fffff) == 0 \ | |
4226 | ? 9 \ | |
4227 | : 8 \ | |
4228 | : ((v) & ~0xfffffff) == 0 \ | |
4229 | ? ((v) & ~0x3ffffff) == 0 \ | |
4230 | ? ((v) & ~0x1ffffff) == 0 \ | |
4231 | ? 7 \ | |
4232 | : 6 \ | |
4233 | : ((v) & ~0x7ffffff) == 0 \ | |
4234 | ? 5 \ | |
4235 | : 4 \ | |
4236 | : ((v) & ~0x3fffffff) == 0 \ | |
4237 | ? ((v) & ~0x1fffffff) == 0 \ | |
4238 | ? 3 \ | |
4239 | : 2 \ | |
4240 | : ((v) & ~0x7fffffff) == 0 \ | |
4241 | ? 1 \ | |
4242 | : 0) | |
4243 | ||
4244 | /* load_register() | |
67c1ffbe | 4245 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4246 | * an absolute expression value into a register. |
4247 | */ | |
4248 | static void | |
67c0d1eb | 4249 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4250 | { |
4251 | int freg; | |
4252 | expressionS hi32, lo32; | |
4253 | ||
4254 | if (ep->X_op != O_big) | |
4255 | { | |
9c2799c2 | 4256 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
4257 | |
4258 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4259 | if (!dbl) |
4260 | normalize_constant_expr (ep); | |
256ab948 TS |
4261 | |
4262 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4263 | { |
4264 | /* We can handle 16 bit signed values with an addiu to | |
4265 | $zero. No need to ever use daddiu here, since $zero and | |
4266 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4267 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4268 | return; |
4269 | } | |
4270 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4271 | { | |
4272 | /* We can handle 16 bit unsigned values with an ori to | |
4273 | $zero. */ | |
67c0d1eb | 4274 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4275 | return; |
4276 | } | |
256ab948 | 4277 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4278 | { |
4279 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4280 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4281 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4282 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4283 | return; |
4284 | } | |
4285 | } | |
4286 | ||
4287 | /* The value is larger than 32 bits. */ | |
4288 | ||
2051e8c4 | 4289 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4290 | { |
55e08f71 NC |
4291 | char value[32]; |
4292 | ||
4293 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4294 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4295 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4296 | return; |
4297 | } | |
4298 | ||
4299 | if (ep->X_op != O_big) | |
4300 | { | |
4301 | hi32 = *ep; | |
4302 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4303 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4304 | hi32.X_add_number &= 0xffffffff; | |
4305 | lo32 = *ep; | |
4306 | lo32.X_add_number &= 0xffffffff; | |
4307 | } | |
4308 | else | |
4309 | { | |
9c2799c2 | 4310 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
4311 | if (ep->X_add_number == 3) |
4312 | generic_bignum[3] = 0; | |
4313 | else if (ep->X_add_number > 4) | |
4314 | as_bad (_("Number larger than 64 bits")); | |
4315 | lo32.X_op = O_constant; | |
4316 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4317 | hi32.X_op = O_constant; | |
4318 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4319 | } | |
4320 | ||
4321 | if (hi32.X_add_number == 0) | |
4322 | freg = 0; | |
4323 | else | |
4324 | { | |
4325 | int shift, bit; | |
4326 | unsigned long hi, lo; | |
4327 | ||
956cd1d6 | 4328 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4329 | { |
4330 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4331 | { | |
67c0d1eb | 4332 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4333 | return; |
4334 | } | |
4335 | if (lo32.X_add_number & 0x80000000) | |
4336 | { | |
67c0d1eb | 4337 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4338 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4339 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4340 | return; |
4341 | } | |
4342 | } | |
252b5132 RH |
4343 | |
4344 | /* Check for 16bit shifted constant. We know that hi32 is | |
4345 | non-zero, so start the mask on the first bit of the hi32 | |
4346 | value. */ | |
4347 | shift = 17; | |
4348 | do | |
beae10d5 KH |
4349 | { |
4350 | unsigned long himask, lomask; | |
4351 | ||
4352 | if (shift < 32) | |
4353 | { | |
4354 | himask = 0xffff >> (32 - shift); | |
4355 | lomask = (0xffff << shift) & 0xffffffff; | |
4356 | } | |
4357 | else | |
4358 | { | |
4359 | himask = 0xffff << (shift - 32); | |
4360 | lomask = 0; | |
4361 | } | |
4362 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4363 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4364 | { | |
4365 | expressionS tmp; | |
4366 | ||
4367 | tmp.X_op = O_constant; | |
4368 | if (shift < 32) | |
4369 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4370 | | (lo32.X_add_number >> shift)); | |
4371 | else | |
4372 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4373 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4374 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4375 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4376 | return; |
4377 | } | |
f9419b05 | 4378 | ++shift; |
beae10d5 KH |
4379 | } |
4380 | while (shift <= (64 - 16)); | |
252b5132 RH |
4381 | |
4382 | /* Find the bit number of the lowest one bit, and store the | |
4383 | shifted value in hi/lo. */ | |
4384 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4385 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4386 | if (lo != 0) | |
4387 | { | |
4388 | bit = 0; | |
4389 | while ((lo & 1) == 0) | |
4390 | { | |
4391 | lo >>= 1; | |
4392 | ++bit; | |
4393 | } | |
4394 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4395 | hi >>= bit; | |
4396 | } | |
4397 | else | |
4398 | { | |
4399 | bit = 32; | |
4400 | while ((hi & 1) == 0) | |
4401 | { | |
4402 | hi >>= 1; | |
4403 | ++bit; | |
4404 | } | |
4405 | lo = hi; | |
4406 | hi = 0; | |
4407 | } | |
4408 | ||
4409 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4410 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4411 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4412 | { |
4413 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4414 | if (shift != 0) |
beae10d5 | 4415 | { |
252b5132 RH |
4416 | expressionS tmp; |
4417 | ||
4418 | /* This instruction will set the register to be all | |
4419 | ones. */ | |
beae10d5 KH |
4420 | tmp.X_op = O_constant; |
4421 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4422 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4423 | if (bit != 0) |
4424 | { | |
4425 | bit += shift; | |
67c0d1eb RS |
4426 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4427 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4428 | } |
67c0d1eb RS |
4429 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4430 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4431 | return; |
4432 | } | |
4433 | } | |
252b5132 RH |
4434 | |
4435 | /* Sign extend hi32 before calling load_register, because we can | |
4436 | generally get better code when we load a sign extended value. */ | |
4437 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4438 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4439 | load_register (reg, &hi32, 0); |
252b5132 RH |
4440 | freg = reg; |
4441 | } | |
4442 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4443 | { | |
4444 | if (freg != 0) | |
4445 | { | |
67c0d1eb | 4446 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4447 | freg = reg; |
4448 | } | |
4449 | } | |
4450 | else | |
4451 | { | |
4452 | expressionS mid16; | |
4453 | ||
956cd1d6 | 4454 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4455 | { |
67c0d1eb RS |
4456 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4457 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4458 | return; |
4459 | } | |
252b5132 RH |
4460 | |
4461 | if (freg != 0) | |
4462 | { | |
67c0d1eb | 4463 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4464 | freg = reg; |
4465 | } | |
4466 | mid16 = lo32; | |
4467 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4468 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4469 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4470 | freg = reg; |
4471 | } | |
4472 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4473 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4474 | } |
4475 | ||
269137b2 TS |
4476 | static inline void |
4477 | load_delay_nop (void) | |
4478 | { | |
4479 | if (!gpr_interlocks) | |
4480 | macro_build (NULL, "nop", ""); | |
4481 | } | |
4482 | ||
252b5132 RH |
4483 | /* Load an address into a register. */ |
4484 | ||
4485 | static void | |
67c0d1eb | 4486 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4487 | { |
252b5132 RH |
4488 | if (ep->X_op != O_constant |
4489 | && ep->X_op != O_symbol) | |
4490 | { | |
4491 | as_bad (_("expression too complex")); | |
4492 | ep->X_op = O_constant; | |
4493 | } | |
4494 | ||
4495 | if (ep->X_op == O_constant) | |
4496 | { | |
67c0d1eb | 4497 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4498 | return; |
4499 | } | |
4500 | ||
4501 | if (mips_pic == NO_PIC) | |
4502 | { | |
4503 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4504 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4505 | Otherwise we want |
4506 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4507 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4508 | If we have an addend, we always use the latter form. |
76b3015f | 4509 | |
d6bc6245 TS |
4510 | With 64bit address space and a usable $at we want |
4511 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4512 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4513 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4514 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4515 | dsll32 $reg,0 | |
3a482fd5 | 4516 | daddu $reg,$reg,$at |
76b3015f | 4517 | |
c03099e6 | 4518 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4519 | on superscalar processors. |
4520 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4521 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4522 | dsll $reg,16 | |
4523 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4524 | dsll $reg,16 | |
4525 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4526 | |
4527 | For GP relative symbols in 64bit address space we can use | |
4528 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4529 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4530 | { |
6caf9ef4 TS |
4531 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4532 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4533 | { | |
4534 | relax_start (ep->X_add_symbol); | |
4535 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4536 | mips_gp_register, BFD_RELOC_GPREL16); | |
4537 | relax_switch (); | |
4538 | } | |
d6bc6245 | 4539 | |
741fe287 | 4540 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4541 | { |
67c0d1eb RS |
4542 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4543 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4544 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4545 | BFD_RELOC_MIPS_HIGHER); | |
4546 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4547 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4548 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4549 | *used_at = 1; |
4550 | } | |
4551 | else | |
4552 | { | |
67c0d1eb RS |
4553 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4554 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4555 | BFD_RELOC_MIPS_HIGHER); | |
4556 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4557 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4558 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4559 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4560 | } |
6caf9ef4 TS |
4561 | |
4562 | if (mips_relax.sequence) | |
4563 | relax_end (); | |
d6bc6245 | 4564 | } |
252b5132 RH |
4565 | else |
4566 | { | |
d6bc6245 | 4567 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4568 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4569 | { |
4d7206a2 | 4570 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4571 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4572 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4573 | relax_switch (); |
d6bc6245 | 4574 | } |
67c0d1eb RS |
4575 | macro_build_lui (ep, reg); |
4576 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4577 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4578 | if (mips_relax.sequence) |
4579 | relax_end (); | |
d6bc6245 | 4580 | } |
252b5132 | 4581 | } |
0a44bf69 | 4582 | else if (!mips_big_got) |
252b5132 RH |
4583 | { |
4584 | expressionS ex; | |
4585 | ||
4586 | /* If this is a reference to an external symbol, we want | |
4587 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4588 | Otherwise we want | |
4589 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4590 | nop | |
4591 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4592 | If there is a constant, it must be added in after. |
4593 | ||
ed6fb7bd | 4594 | If we have NewABI, we want |
f5040a92 AO |
4595 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4596 | unless we're referencing a global symbol with a non-zero | |
4597 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4598 | if (HAVE_NEWABI) |
4599 | { | |
f5040a92 AO |
4600 | if (ep->X_add_number) |
4601 | { | |
4d7206a2 | 4602 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4603 | ep->X_add_number = 0; |
4d7206a2 | 4604 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4605 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4606 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4607 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4608 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4609 | ex.X_op = O_constant; | |
67c0d1eb | 4610 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4611 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4612 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4613 | relax_switch (); |
f5040a92 | 4614 | } |
67c0d1eb | 4615 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4616 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4617 | if (mips_relax.sequence) |
4618 | relax_end (); | |
ed6fb7bd SC |
4619 | } |
4620 | else | |
4621 | { | |
f5040a92 AO |
4622 | ex.X_add_number = ep->X_add_number; |
4623 | ep->X_add_number = 0; | |
67c0d1eb RS |
4624 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4625 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4626 | load_delay_nop (); |
4d7206a2 RS |
4627 | relax_start (ep->X_add_symbol); |
4628 | relax_switch (); | |
67c0d1eb | 4629 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4630 | BFD_RELOC_LO16); |
4d7206a2 | 4631 | relax_end (); |
ed6fb7bd | 4632 | |
f5040a92 AO |
4633 | if (ex.X_add_number != 0) |
4634 | { | |
4635 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4636 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4637 | ex.X_op = O_constant; | |
67c0d1eb | 4638 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4639 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4640 | } |
252b5132 RH |
4641 | } |
4642 | } | |
0a44bf69 | 4643 | else if (mips_big_got) |
252b5132 RH |
4644 | { |
4645 | expressionS ex; | |
252b5132 RH |
4646 | |
4647 | /* This is the large GOT case. If this is a reference to an | |
4648 | external symbol, we want | |
4649 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4650 | addu $reg,$reg,$gp | |
4651 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4652 | |
4653 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4654 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4655 | nop | |
4656 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4657 | If there is a constant, it must be added in after. |
f5040a92 AO |
4658 | |
4659 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4660 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4661 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4662 | */ |
438c16b8 TS |
4663 | if (HAVE_NEWABI) |
4664 | { | |
4d7206a2 | 4665 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4666 | ep->X_add_number = 0; |
4d7206a2 | 4667 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4668 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4669 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4670 | reg, reg, mips_gp_register); | |
4671 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4672 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4673 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4674 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4675 | else if (ex.X_add_number) | |
4676 | { | |
4677 | ex.X_op = O_constant; | |
67c0d1eb RS |
4678 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4679 | BFD_RELOC_LO16); | |
f5040a92 AO |
4680 | } |
4681 | ||
4682 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4683 | relax_switch (); |
67c0d1eb | 4684 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4685 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4686 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4687 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4688 | relax_end (); |
438c16b8 | 4689 | } |
252b5132 | 4690 | else |
438c16b8 | 4691 | { |
f5040a92 AO |
4692 | ex.X_add_number = ep->X_add_number; |
4693 | ep->X_add_number = 0; | |
4d7206a2 | 4694 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4695 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4696 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4697 | reg, reg, mips_gp_register); | |
4698 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4699 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4700 | relax_switch (); |
4701 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4702 | { |
4703 | /* We need a nop before loading from $gp. This special | |
4704 | check is required because the lui which starts the main | |
4705 | instruction stream does not refer to $gp, and so will not | |
4706 | insert the nop which may be required. */ | |
67c0d1eb | 4707 | macro_build (NULL, "nop", ""); |
438c16b8 | 4708 | } |
67c0d1eb | 4709 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4710 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4711 | load_delay_nop (); |
67c0d1eb | 4712 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4713 | BFD_RELOC_LO16); |
4d7206a2 | 4714 | relax_end (); |
438c16b8 | 4715 | |
f5040a92 AO |
4716 | if (ex.X_add_number != 0) |
4717 | { | |
4718 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4719 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4720 | ex.X_op = O_constant; | |
67c0d1eb RS |
4721 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4722 | BFD_RELOC_LO16); | |
f5040a92 | 4723 | } |
252b5132 RH |
4724 | } |
4725 | } | |
252b5132 RH |
4726 | else |
4727 | abort (); | |
8fc2e39e | 4728 | |
741fe287 | 4729 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4730 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4731 | } |
4732 | ||
ea1fb5dc RS |
4733 | /* Move the contents of register SOURCE into register DEST. */ |
4734 | ||
4735 | static void | |
67c0d1eb | 4736 | move_register (int dest, int source) |
ea1fb5dc | 4737 | { |
67c0d1eb RS |
4738 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4739 | dest, source, 0); | |
ea1fb5dc RS |
4740 | } |
4741 | ||
4d7206a2 | 4742 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4743 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4744 | The two alternatives are: | |
4d7206a2 RS |
4745 | |
4746 | Global symbol Local sybmol | |
4747 | ------------- ------------ | |
4748 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4749 | ... ... | |
4750 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4751 | ||
4752 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4753 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4754 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4755 | |
4756 | static void | |
67c0d1eb | 4757 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4758 | { |
4759 | expressionS global; | |
4760 | ||
4761 | global = *local; | |
4762 | global.X_add_number = 0; | |
4763 | ||
4764 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4765 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4766 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4767 | relax_switch (); |
67c0d1eb RS |
4768 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4769 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4770 | relax_end (); |
4771 | } | |
4772 | ||
4773 | static void | |
67c0d1eb | 4774 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4775 | { |
4776 | expressionS global; | |
4777 | ||
4778 | global.X_op = O_constant; | |
4779 | global.X_op_symbol = NULL; | |
4780 | global.X_add_symbol = NULL; | |
4781 | global.X_add_number = local->X_add_number; | |
4782 | ||
4783 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4784 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4785 | dest, dest, BFD_RELOC_LO16); |
4786 | relax_switch (); | |
67c0d1eb | 4787 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4788 | relax_end (); |
4789 | } | |
4790 | ||
f6a22291 MR |
4791 | static void |
4792 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4793 | { | |
4794 | expressionS global; | |
4795 | int hold_mips_optimize; | |
4796 | ||
4797 | global.X_op = O_constant; | |
4798 | global.X_op_symbol = NULL; | |
4799 | global.X_add_symbol = NULL; | |
4800 | global.X_add_number = local->X_add_number; | |
4801 | ||
4802 | relax_start (local->X_add_symbol); | |
4803 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4804 | relax_switch (); | |
4805 | /* Set mips_optimize around the lui instruction to avoid | |
4806 | inserting an unnecessary nop after the lw. */ | |
4807 | hold_mips_optimize = mips_optimize; | |
4808 | mips_optimize = 2; | |
4809 | macro_build_lui (&global, tmp); | |
4810 | mips_optimize = hold_mips_optimize; | |
4811 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4812 | relax_end (); | |
4813 | ||
4814 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4815 | } | |
4816 | ||
252b5132 RH |
4817 | /* |
4818 | * Build macros | |
4819 | * This routine implements the seemingly endless macro or synthesized | |
4820 | * instructions and addressing modes in the mips assembly language. Many | |
4821 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4822 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4823 | * this verbose method. Others are not simple macros but are more like |
4824 | * optimizing code generation. | |
4825 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4826 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4827 | * The ensuing load upper instructions are ommited. This implies some kind |
4828 | * of global optimization. We currently only optimize within a single macro. | |
4829 | * For many of the load and store macros if the address is specified as a | |
4830 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4831 | * first load register 'at' with zero and use it as the base register. The | |
4832 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4833 | * we're missing. | |
4834 | */ | |
4835 | static void | |
17a2f251 | 4836 | macro (struct mips_cl_insn *ip) |
252b5132 | 4837 | { |
741fe287 MR |
4838 | unsigned int treg, sreg, dreg, breg; |
4839 | unsigned int tempreg; | |
252b5132 | 4840 | int mask; |
43841e91 | 4841 | int used_at = 0; |
252b5132 RH |
4842 | expressionS expr1; |
4843 | const char *s; | |
4844 | const char *s2; | |
4845 | const char *fmt; | |
4846 | int likely = 0; | |
4847 | int dbl = 0; | |
4848 | int coproc = 0; | |
4849 | int lr = 0; | |
4850 | int imm = 0; | |
1abe91b1 | 4851 | int call = 0; |
252b5132 | 4852 | int off; |
67c0d1eb | 4853 | offsetT maxnum; |
252b5132 | 4854 | bfd_reloc_code_real_type r; |
252b5132 RH |
4855 | int hold_mips_optimize; |
4856 | ||
9c2799c2 | 4857 | gas_assert (! mips_opts.mips16); |
252b5132 | 4858 | |
bbea7ebc MR |
4859 | treg = EXTRACT_OPERAND (RT, *ip); |
4860 | dreg = EXTRACT_OPERAND (RD, *ip); | |
4861 | sreg = breg = EXTRACT_OPERAND (RS, *ip); | |
252b5132 RH |
4862 | mask = ip->insn_mo->mask; |
4863 | ||
4864 | expr1.X_op = O_constant; | |
4865 | expr1.X_op_symbol = NULL; | |
4866 | expr1.X_add_symbol = NULL; | |
4867 | expr1.X_add_number = 1; | |
4868 | ||
4869 | switch (mask) | |
4870 | { | |
4871 | case M_DABS: | |
4872 | dbl = 1; | |
4873 | case M_ABS: | |
4874 | /* bgez $a0,.+12 | |
4875 | move v0,$a0 | |
4876 | sub v0,$zero,$a0 | |
4877 | */ | |
4878 | ||
7d10b47d | 4879 | start_noreorder (); |
252b5132 RH |
4880 | |
4881 | expr1.X_add_number = 8; | |
67c0d1eb | 4882 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4883 | if (dreg == sreg) |
a605d2b3 | 4884 | macro_build (NULL, "nop", ""); |
252b5132 | 4885 | else |
67c0d1eb RS |
4886 | move_register (dreg, sreg); |
4887 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4888 | |
7d10b47d | 4889 | end_noreorder (); |
8fc2e39e | 4890 | break; |
252b5132 RH |
4891 | |
4892 | case M_ADD_I: | |
4893 | s = "addi"; | |
4894 | s2 = "add"; | |
4895 | goto do_addi; | |
4896 | case M_ADDU_I: | |
4897 | s = "addiu"; | |
4898 | s2 = "addu"; | |
4899 | goto do_addi; | |
4900 | case M_DADD_I: | |
4901 | dbl = 1; | |
4902 | s = "daddi"; | |
4903 | s2 = "dadd"; | |
4904 | goto do_addi; | |
4905 | case M_DADDU_I: | |
4906 | dbl = 1; | |
4907 | s = "daddiu"; | |
4908 | s2 = "daddu"; | |
4909 | do_addi: | |
4910 | if (imm_expr.X_op == O_constant | |
4911 | && imm_expr.X_add_number >= -0x8000 | |
4912 | && imm_expr.X_add_number < 0x8000) | |
4913 | { | |
67c0d1eb | 4914 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4915 | break; |
252b5132 | 4916 | } |
8fc2e39e | 4917 | used_at = 1; |
67c0d1eb RS |
4918 | load_register (AT, &imm_expr, dbl); |
4919 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4920 | break; |
4921 | ||
4922 | case M_AND_I: | |
4923 | s = "andi"; | |
4924 | s2 = "and"; | |
4925 | goto do_bit; | |
4926 | case M_OR_I: | |
4927 | s = "ori"; | |
4928 | s2 = "or"; | |
4929 | goto do_bit; | |
4930 | case M_NOR_I: | |
4931 | s = ""; | |
4932 | s2 = "nor"; | |
4933 | goto do_bit; | |
4934 | case M_XOR_I: | |
4935 | s = "xori"; | |
4936 | s2 = "xor"; | |
4937 | do_bit: | |
4938 | if (imm_expr.X_op == O_constant | |
4939 | && imm_expr.X_add_number >= 0 | |
4940 | && imm_expr.X_add_number < 0x10000) | |
4941 | { | |
4942 | if (mask != M_NOR_I) | |
67c0d1eb | 4943 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4944 | else |
4945 | { | |
67c0d1eb RS |
4946 | macro_build (&imm_expr, "ori", "t,r,i", |
4947 | treg, sreg, BFD_RELOC_LO16); | |
4948 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4949 | } |
8fc2e39e | 4950 | break; |
252b5132 RH |
4951 | } |
4952 | ||
8fc2e39e | 4953 | used_at = 1; |
67c0d1eb RS |
4954 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4955 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4956 | break; |
4957 | ||
8b082fb1 TS |
4958 | case M_BALIGN: |
4959 | switch (imm_expr.X_add_number) | |
4960 | { | |
4961 | case 0: | |
4962 | macro_build (NULL, "nop", ""); | |
4963 | break; | |
4964 | case 2: | |
4965 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4966 | break; | |
4967 | default: | |
4968 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 4969 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
4970 | break; |
4971 | } | |
4972 | break; | |
4973 | ||
252b5132 RH |
4974 | case M_BEQ_I: |
4975 | s = "beq"; | |
4976 | goto beq_i; | |
4977 | case M_BEQL_I: | |
4978 | s = "beql"; | |
4979 | likely = 1; | |
4980 | goto beq_i; | |
4981 | case M_BNE_I: | |
4982 | s = "bne"; | |
4983 | goto beq_i; | |
4984 | case M_BNEL_I: | |
4985 | s = "bnel"; | |
4986 | likely = 1; | |
4987 | beq_i: | |
4988 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4989 | { | |
c80c840e | 4990 | macro_build (&offset_expr, s, "s,t,p", sreg, ZERO); |
8fc2e39e | 4991 | break; |
252b5132 | 4992 | } |
8fc2e39e | 4993 | used_at = 1; |
67c0d1eb RS |
4994 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4995 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4996 | break; |
4997 | ||
4998 | case M_BGEL: | |
4999 | likely = 1; | |
5000 | case M_BGE: | |
5001 | if (treg == 0) | |
5002 | { | |
67c0d1eb | 5003 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5004 | break; |
252b5132 RH |
5005 | } |
5006 | if (sreg == 0) | |
5007 | { | |
67c0d1eb | 5008 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 5009 | break; |
252b5132 | 5010 | } |
8fc2e39e | 5011 | used_at = 1; |
67c0d1eb | 5012 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5013 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5014 | break; |
5015 | ||
5016 | case M_BGTL_I: | |
5017 | likely = 1; | |
5018 | case M_BGT_I: | |
90ecf173 | 5019 | /* Check for > max integer. */ |
252b5132 | 5020 | maxnum = 0x7fffffff; |
ca4e0257 | 5021 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5022 | { |
5023 | maxnum <<= 16; | |
5024 | maxnum |= 0xffff; | |
5025 | maxnum <<= 16; | |
5026 | maxnum |= 0xffff; | |
5027 | } | |
5028 | if (imm_expr.X_op == O_constant | |
5029 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5030 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5031 | { |
5032 | do_false: | |
90ecf173 | 5033 | /* Result is always false. */ |
252b5132 | 5034 | if (! likely) |
a605d2b3 | 5035 | macro_build (NULL, "nop", ""); |
252b5132 | 5036 | else |
c80c840e | 5037 | macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO); |
8fc2e39e | 5038 | break; |
252b5132 RH |
5039 | } |
5040 | if (imm_expr.X_op != O_constant) | |
5041 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5042 | ++imm_expr.X_add_number; |
252b5132 RH |
5043 | /* FALLTHROUGH */ |
5044 | case M_BGE_I: | |
5045 | case M_BGEL_I: | |
5046 | if (mask == M_BGEL_I) | |
5047 | likely = 1; | |
5048 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5049 | { | |
67c0d1eb | 5050 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5051 | break; |
252b5132 RH |
5052 | } |
5053 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5054 | { | |
67c0d1eb | 5055 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5056 | break; |
252b5132 RH |
5057 | } |
5058 | maxnum = 0x7fffffff; | |
ca4e0257 | 5059 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5060 | { |
5061 | maxnum <<= 16; | |
5062 | maxnum |= 0xffff; | |
5063 | maxnum <<= 16; | |
5064 | maxnum |= 0xffff; | |
5065 | } | |
5066 | maxnum = - maxnum - 1; | |
5067 | if (imm_expr.X_op == O_constant | |
5068 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 5069 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5070 | { |
5071 | do_true: | |
5072 | /* result is always true */ | |
5073 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 5074 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5075 | break; |
252b5132 | 5076 | } |
8fc2e39e | 5077 | used_at = 1; |
67c0d1eb | 5078 | set_at (sreg, 0); |
c80c840e | 5079 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5080 | break; |
5081 | ||
5082 | case M_BGEUL: | |
5083 | likely = 1; | |
5084 | case M_BGEU: | |
5085 | if (treg == 0) | |
5086 | goto do_true; | |
5087 | if (sreg == 0) | |
5088 | { | |
67c0d1eb | 5089 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5090 | "s,t,p", ZERO, treg); |
8fc2e39e | 5091 | break; |
252b5132 | 5092 | } |
8fc2e39e | 5093 | used_at = 1; |
67c0d1eb | 5094 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5095 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5096 | break; |
5097 | ||
5098 | case M_BGTUL_I: | |
5099 | likely = 1; | |
5100 | case M_BGTU_I: | |
5101 | if (sreg == 0 | |
ca4e0257 | 5102 | || (HAVE_32BIT_GPRS |
252b5132 | 5103 | && imm_expr.X_op == O_constant |
f01dc953 | 5104 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5105 | goto do_false; |
5106 | if (imm_expr.X_op != O_constant) | |
5107 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5108 | ++imm_expr.X_add_number; |
252b5132 RH |
5109 | /* FALLTHROUGH */ |
5110 | case M_BGEU_I: | |
5111 | case M_BGEUL_I: | |
5112 | if (mask == M_BGEUL_I) | |
5113 | likely = 1; | |
5114 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5115 | goto do_true; | |
5116 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5117 | { | |
67c0d1eb | 5118 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5119 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5120 | break; |
252b5132 | 5121 | } |
8fc2e39e | 5122 | used_at = 1; |
67c0d1eb | 5123 | set_at (sreg, 1); |
c80c840e | 5124 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5125 | break; |
5126 | ||
5127 | case M_BGTL: | |
5128 | likely = 1; | |
5129 | case M_BGT: | |
5130 | if (treg == 0) | |
5131 | { | |
67c0d1eb | 5132 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5133 | break; |
252b5132 RH |
5134 | } |
5135 | if (sreg == 0) | |
5136 | { | |
67c0d1eb | 5137 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 5138 | break; |
252b5132 | 5139 | } |
8fc2e39e | 5140 | used_at = 1; |
67c0d1eb | 5141 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5142 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5143 | break; |
5144 | ||
5145 | case M_BGTUL: | |
5146 | likely = 1; | |
5147 | case M_BGTU: | |
5148 | if (treg == 0) | |
5149 | { | |
67c0d1eb | 5150 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5151 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5152 | break; |
252b5132 RH |
5153 | } |
5154 | if (sreg == 0) | |
5155 | goto do_false; | |
8fc2e39e | 5156 | used_at = 1; |
67c0d1eb | 5157 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5158 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5159 | break; |
5160 | ||
5161 | case M_BLEL: | |
5162 | likely = 1; | |
5163 | case M_BLE: | |
5164 | if (treg == 0) | |
5165 | { | |
67c0d1eb | 5166 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5167 | break; |
252b5132 RH |
5168 | } |
5169 | if (sreg == 0) | |
5170 | { | |
67c0d1eb | 5171 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 5172 | break; |
252b5132 | 5173 | } |
8fc2e39e | 5174 | used_at = 1; |
67c0d1eb | 5175 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
c80c840e | 5176 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5177 | break; |
5178 | ||
5179 | case M_BLEL_I: | |
5180 | likely = 1; | |
5181 | case M_BLE_I: | |
5182 | maxnum = 0x7fffffff; | |
ca4e0257 | 5183 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5184 | { |
5185 | maxnum <<= 16; | |
5186 | maxnum |= 0xffff; | |
5187 | maxnum <<= 16; | |
5188 | maxnum |= 0xffff; | |
5189 | } | |
5190 | if (imm_expr.X_op == O_constant | |
5191 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5192 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5193 | goto do_true; |
5194 | if (imm_expr.X_op != O_constant) | |
5195 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5196 | ++imm_expr.X_add_number; |
252b5132 RH |
5197 | /* FALLTHROUGH */ |
5198 | case M_BLT_I: | |
5199 | case M_BLTL_I: | |
5200 | if (mask == M_BLTL_I) | |
5201 | likely = 1; | |
5202 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5203 | { | |
67c0d1eb | 5204 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5205 | break; |
252b5132 RH |
5206 | } |
5207 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5208 | { | |
67c0d1eb | 5209 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5210 | break; |
252b5132 | 5211 | } |
8fc2e39e | 5212 | used_at = 1; |
67c0d1eb | 5213 | set_at (sreg, 0); |
c80c840e | 5214 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5215 | break; |
5216 | ||
5217 | case M_BLEUL: | |
5218 | likely = 1; | |
5219 | case M_BLEU: | |
5220 | if (treg == 0) | |
5221 | { | |
67c0d1eb | 5222 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5223 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5224 | break; |
252b5132 RH |
5225 | } |
5226 | if (sreg == 0) | |
5227 | goto do_true; | |
8fc2e39e | 5228 | used_at = 1; |
67c0d1eb | 5229 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
c80c840e | 5230 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO); |
252b5132 RH |
5231 | break; |
5232 | ||
5233 | case M_BLEUL_I: | |
5234 | likely = 1; | |
5235 | case M_BLEU_I: | |
5236 | if (sreg == 0 | |
ca4e0257 | 5237 | || (HAVE_32BIT_GPRS |
252b5132 | 5238 | && imm_expr.X_op == O_constant |
f01dc953 | 5239 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
5240 | goto do_true; |
5241 | if (imm_expr.X_op != O_constant) | |
5242 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5243 | ++imm_expr.X_add_number; |
252b5132 RH |
5244 | /* FALLTHROUGH */ |
5245 | case M_BLTU_I: | |
5246 | case M_BLTUL_I: | |
5247 | if (mask == M_BLTUL_I) | |
5248 | likely = 1; | |
5249 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5250 | goto do_false; | |
5251 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5252 | { | |
67c0d1eb | 5253 | macro_build (&offset_expr, likely ? "beql" : "beq", |
c80c840e | 5254 | "s,t,p", sreg, ZERO); |
8fc2e39e | 5255 | break; |
252b5132 | 5256 | } |
8fc2e39e | 5257 | used_at = 1; |
67c0d1eb | 5258 | set_at (sreg, 1); |
c80c840e | 5259 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5260 | break; |
5261 | ||
5262 | case M_BLTL: | |
5263 | likely = 1; | |
5264 | case M_BLT: | |
5265 | if (treg == 0) | |
5266 | { | |
67c0d1eb | 5267 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5268 | break; |
252b5132 RH |
5269 | } |
5270 | if (sreg == 0) | |
5271 | { | |
67c0d1eb | 5272 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5273 | break; |
252b5132 | 5274 | } |
8fc2e39e | 5275 | used_at = 1; |
67c0d1eb | 5276 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
c80c840e | 5277 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5278 | break; |
5279 | ||
5280 | case M_BLTUL: | |
5281 | likely = 1; | |
5282 | case M_BLTU: | |
5283 | if (treg == 0) | |
5284 | goto do_false; | |
5285 | if (sreg == 0) | |
5286 | { | |
67c0d1eb | 5287 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
c80c840e | 5288 | "s,t,p", ZERO, treg); |
8fc2e39e | 5289 | break; |
252b5132 | 5290 | } |
8fc2e39e | 5291 | used_at = 1; |
67c0d1eb | 5292 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
c80c840e | 5293 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO); |
252b5132 RH |
5294 | break; |
5295 | ||
5f74bc13 CD |
5296 | case M_DEXT: |
5297 | { | |
d5818fca MR |
5298 | /* Use unsigned arithmetic. */ |
5299 | addressT pos; | |
5300 | addressT size; | |
5f74bc13 | 5301 | |
90ecf173 | 5302 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5303 | { |
5304 | as_bad (_("Unsupported large constant")); | |
5305 | pos = size = 1; | |
5306 | } | |
5307 | else | |
5308 | { | |
d5818fca MR |
5309 | pos = imm_expr.X_add_number; |
5310 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5311 | } |
5312 | ||
5313 | if (pos > 63) | |
5314 | { | |
d5818fca | 5315 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5316 | pos = 1; |
5317 | } | |
90ecf173 | 5318 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5319 | { |
5320 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 5321 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5322 | size = 1; |
5323 | } | |
5324 | ||
5325 | if (size <= 32 && pos < 32) | |
5326 | { | |
5327 | s = "dext"; | |
5328 | fmt = "t,r,+A,+C"; | |
5329 | } | |
5330 | else if (size <= 32) | |
5331 | { | |
5332 | s = "dextu"; | |
5333 | fmt = "t,r,+E,+H"; | |
5334 | } | |
5335 | else | |
5336 | { | |
5337 | s = "dextm"; | |
5338 | fmt = "t,r,+A,+G"; | |
5339 | } | |
d5818fca MR |
5340 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5341 | (int) (size - 1)); | |
5f74bc13 | 5342 | } |
8fc2e39e | 5343 | break; |
5f74bc13 CD |
5344 | |
5345 | case M_DINS: | |
5346 | { | |
d5818fca MR |
5347 | /* Use unsigned arithmetic. */ |
5348 | addressT pos; | |
5349 | addressT size; | |
5f74bc13 | 5350 | |
90ecf173 | 5351 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
5352 | { |
5353 | as_bad (_("Unsupported large constant")); | |
5354 | pos = size = 1; | |
5355 | } | |
5356 | else | |
5357 | { | |
d5818fca MR |
5358 | pos = imm_expr.X_add_number; |
5359 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
5360 | } |
5361 | ||
5362 | if (pos > 63) | |
5363 | { | |
d5818fca | 5364 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
5365 | pos = 1; |
5366 | } | |
90ecf173 | 5367 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
5368 | { |
5369 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 5370 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
5371 | size = 1; |
5372 | } | |
5373 | ||
5374 | if (pos < 32 && (pos + size - 1) < 32) | |
5375 | { | |
5376 | s = "dins"; | |
5377 | fmt = "t,r,+A,+B"; | |
5378 | } | |
5379 | else if (pos >= 32) | |
5380 | { | |
5381 | s = "dinsu"; | |
5382 | fmt = "t,r,+E,+F"; | |
5383 | } | |
5384 | else | |
5385 | { | |
5386 | s = "dinsm"; | |
5387 | fmt = "t,r,+A,+F"; | |
5388 | } | |
750bdd57 AS |
5389 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5390 | (int) (pos + size - 1)); | |
5f74bc13 | 5391 | } |
8fc2e39e | 5392 | break; |
5f74bc13 | 5393 | |
252b5132 RH |
5394 | case M_DDIV_3: |
5395 | dbl = 1; | |
5396 | case M_DIV_3: | |
5397 | s = "mflo"; | |
5398 | goto do_div3; | |
5399 | case M_DREM_3: | |
5400 | dbl = 1; | |
5401 | case M_REM_3: | |
5402 | s = "mfhi"; | |
5403 | do_div3: | |
5404 | if (treg == 0) | |
5405 | { | |
5406 | as_warn (_("Divide by zero.")); | |
5407 | if (mips_trap) | |
c80c840e | 5408 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5409 | else |
67c0d1eb | 5410 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5411 | break; |
252b5132 RH |
5412 | } |
5413 | ||
7d10b47d | 5414 | start_noreorder (); |
252b5132 RH |
5415 | if (mips_trap) |
5416 | { | |
c80c840e | 5417 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5418 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
5419 | } |
5420 | else | |
5421 | { | |
5422 | expr1.X_add_number = 8; | |
c80c840e | 5423 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb RS |
5424 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
5425 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5426 | } |
5427 | expr1.X_add_number = -1; | |
8fc2e39e | 5428 | used_at = 1; |
f6a22291 | 5429 | load_register (AT, &expr1, dbl); |
252b5132 | 5430 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5431 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5432 | if (dbl) |
5433 | { | |
5434 | expr1.X_add_number = 1; | |
f6a22291 | 5435 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5436 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5437 | } |
5438 | else | |
5439 | { | |
5440 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5441 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5442 | } |
5443 | if (mips_trap) | |
5444 | { | |
67c0d1eb | 5445 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5446 | /* We want to close the noreorder block as soon as possible, so |
5447 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5448 | end_noreorder (); |
252b5132 RH |
5449 | } |
5450 | else | |
5451 | { | |
5452 | expr1.X_add_number = 8; | |
67c0d1eb | 5453 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
a605d2b3 | 5454 | macro_build (NULL, "nop", ""); |
252b5132 RH |
5455 | |
5456 | /* We want to close the noreorder block as soon as possible, so | |
5457 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5458 | end_noreorder (); |
252b5132 | 5459 | |
67c0d1eb | 5460 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5461 | } |
67c0d1eb | 5462 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5463 | break; |
5464 | ||
5465 | case M_DIV_3I: | |
5466 | s = "div"; | |
5467 | s2 = "mflo"; | |
5468 | goto do_divi; | |
5469 | case M_DIVU_3I: | |
5470 | s = "divu"; | |
5471 | s2 = "mflo"; | |
5472 | goto do_divi; | |
5473 | case M_REM_3I: | |
5474 | s = "div"; | |
5475 | s2 = "mfhi"; | |
5476 | goto do_divi; | |
5477 | case M_REMU_3I: | |
5478 | s = "divu"; | |
5479 | s2 = "mfhi"; | |
5480 | goto do_divi; | |
5481 | case M_DDIV_3I: | |
5482 | dbl = 1; | |
5483 | s = "ddiv"; | |
5484 | s2 = "mflo"; | |
5485 | goto do_divi; | |
5486 | case M_DDIVU_3I: | |
5487 | dbl = 1; | |
5488 | s = "ddivu"; | |
5489 | s2 = "mflo"; | |
5490 | goto do_divi; | |
5491 | case M_DREM_3I: | |
5492 | dbl = 1; | |
5493 | s = "ddiv"; | |
5494 | s2 = "mfhi"; | |
5495 | goto do_divi; | |
5496 | case M_DREMU_3I: | |
5497 | dbl = 1; | |
5498 | s = "ddivu"; | |
5499 | s2 = "mfhi"; | |
5500 | do_divi: | |
5501 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5502 | { | |
5503 | as_warn (_("Divide by zero.")); | |
5504 | if (mips_trap) | |
c80c840e | 5505 | macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7); |
252b5132 | 5506 | else |
67c0d1eb | 5507 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5508 | break; |
252b5132 RH |
5509 | } |
5510 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5511 | { | |
5512 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5513 | move_register (dreg, sreg); |
252b5132 | 5514 | else |
c80c840e | 5515 | move_register (dreg, ZERO); |
8fc2e39e | 5516 | break; |
252b5132 RH |
5517 | } |
5518 | if (imm_expr.X_op == O_constant | |
5519 | && imm_expr.X_add_number == -1 | |
5520 | && s[strlen (s) - 1] != 'u') | |
5521 | { | |
5522 | if (strcmp (s2, "mflo") == 0) | |
5523 | { | |
67c0d1eb | 5524 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5525 | } |
5526 | else | |
c80c840e | 5527 | move_register (dreg, ZERO); |
8fc2e39e | 5528 | break; |
252b5132 RH |
5529 | } |
5530 | ||
8fc2e39e | 5531 | used_at = 1; |
67c0d1eb RS |
5532 | load_register (AT, &imm_expr, dbl); |
5533 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5534 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5535 | break; |
5536 | ||
5537 | case M_DIVU_3: | |
5538 | s = "divu"; | |
5539 | s2 = "mflo"; | |
5540 | goto do_divu3; | |
5541 | case M_REMU_3: | |
5542 | s = "divu"; | |
5543 | s2 = "mfhi"; | |
5544 | goto do_divu3; | |
5545 | case M_DDIVU_3: | |
5546 | s = "ddivu"; | |
5547 | s2 = "mflo"; | |
5548 | goto do_divu3; | |
5549 | case M_DREMU_3: | |
5550 | s = "ddivu"; | |
5551 | s2 = "mfhi"; | |
5552 | do_divu3: | |
7d10b47d | 5553 | start_noreorder (); |
252b5132 RH |
5554 | if (mips_trap) |
5555 | { | |
c80c840e | 5556 | macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7); |
67c0d1eb | 5557 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5558 | /* We want to close the noreorder block as soon as possible, so |
5559 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5560 | end_noreorder (); |
252b5132 RH |
5561 | } |
5562 | else | |
5563 | { | |
5564 | expr1.X_add_number = 8; | |
c80c840e | 5565 | macro_build (&expr1, "bne", "s,t,p", treg, ZERO); |
67c0d1eb | 5566 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
5567 | |
5568 | /* We want to close the noreorder block as soon as possible, so | |
5569 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5570 | end_noreorder (); |
67c0d1eb | 5571 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5572 | } |
67c0d1eb | 5573 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5574 | break; |
252b5132 | 5575 | |
1abe91b1 MR |
5576 | case M_DLCA_AB: |
5577 | dbl = 1; | |
5578 | case M_LCA_AB: | |
5579 | call = 1; | |
5580 | goto do_la; | |
252b5132 RH |
5581 | case M_DLA_AB: |
5582 | dbl = 1; | |
5583 | case M_LA_AB: | |
1abe91b1 | 5584 | do_la: |
252b5132 RH |
5585 | /* Load the address of a symbol into a register. If breg is not |
5586 | zero, we then add a base register to it. */ | |
5587 | ||
3bec30a8 TS |
5588 | if (dbl && HAVE_32BIT_GPRS) |
5589 | as_warn (_("dla used to load 32-bit register")); | |
5590 | ||
90ecf173 | 5591 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5592 | as_warn (_("la used to load 64-bit address")); |
5593 | ||
0c11417f MR |
5594 | if (offset_expr.X_op == O_constant |
5595 | && offset_expr.X_add_number >= -0x8000 | |
5596 | && offset_expr.X_add_number < 0x8000) | |
5597 | { | |
aed1a261 | 5598 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5599 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5600 | break; |
0c11417f MR |
5601 | } |
5602 | ||
741fe287 | 5603 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5604 | { |
5605 | tempreg = AT; | |
5606 | used_at = 1; | |
5607 | } | |
5608 | else | |
5609 | { | |
5610 | tempreg = treg; | |
afdbd6d0 CD |
5611 | } |
5612 | ||
252b5132 RH |
5613 | if (offset_expr.X_op != O_symbol |
5614 | && offset_expr.X_op != O_constant) | |
5615 | { | |
f71d0d44 | 5616 | as_bad (_("Expression too complex")); |
252b5132 RH |
5617 | offset_expr.X_op = O_constant; |
5618 | } | |
5619 | ||
252b5132 | 5620 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5621 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5622 | else if (mips_pic == NO_PIC) |
5623 | { | |
d6bc6245 | 5624 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5625 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5626 | Otherwise we want |
5627 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5628 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5629 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5630 | so we may as well always use the latter form. |
76b3015f | 5631 | |
6caf9ef4 TS |
5632 | With 64bit address space and a usable $at we want |
5633 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5634 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5635 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5636 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5637 | dsll32 $tempreg,0 | |
5638 | daddu $tempreg,$tempreg,$at | |
5639 | ||
5640 | If $at is already in use, we use a path which is suboptimal | |
5641 | on superscalar processors. | |
5642 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5643 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5644 | dsll $tempreg,16 | |
5645 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5646 | dsll $tempreg,16 | |
5647 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5648 | ||
5649 | For GP relative symbols in 64bit address space we can use | |
5650 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5651 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5652 | { |
6caf9ef4 TS |
5653 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5654 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5655 | { | |
5656 | relax_start (offset_expr.X_add_symbol); | |
5657 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5658 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5659 | relax_switch (); | |
5660 | } | |
d6bc6245 | 5661 | |
741fe287 | 5662 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5663 | { |
67c0d1eb | 5664 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5665 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5666 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5667 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5668 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5669 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5670 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5671 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5672 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5673 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5674 | used_at = 1; |
5675 | } | |
5676 | else | |
5677 | { | |
67c0d1eb | 5678 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5679 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5680 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5681 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5682 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5683 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5684 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5685 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5686 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5687 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5688 | } |
6caf9ef4 TS |
5689 | |
5690 | if (mips_relax.sequence) | |
5691 | relax_end (); | |
98d3f06f KH |
5692 | } |
5693 | else | |
5694 | { | |
5695 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5696 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5697 | { |
4d7206a2 | 5698 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5699 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5700 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5701 | relax_switch (); |
98d3f06f | 5702 | } |
6943caf0 | 5703 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 5704 | as_bad (_("Offset too large")); |
67c0d1eb RS |
5705 | macro_build_lui (&offset_expr, tempreg); |
5706 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5707 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5708 | if (mips_relax.sequence) |
5709 | relax_end (); | |
98d3f06f | 5710 | } |
252b5132 | 5711 | } |
0a44bf69 | 5712 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5713 | { |
9117d219 NC |
5714 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5715 | ||
252b5132 RH |
5716 | /* If this is a reference to an external symbol, and there |
5717 | is no constant, we want | |
5718 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5719 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5720 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5721 | For a local symbol, we want |
5722 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5723 | nop | |
5724 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5725 | ||
5726 | If we have a small constant, and this is a reference to | |
5727 | an external symbol, we want | |
5728 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5729 | nop | |
5730 | addiu $tempreg,$tempreg,<constant> | |
5731 | For a local symbol, we want the same instruction | |
5732 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5733 | addiu instruction. | |
5734 | ||
5735 | If we have a large constant, and this is a reference to | |
5736 | an external symbol, we want | |
5737 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5738 | lui $at,<hiconstant> | |
5739 | addiu $at,$at,<loconstant> | |
5740 | addu $tempreg,$tempreg,$at | |
5741 | For a local symbol, we want the same instruction | |
5742 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5743 | addiu instruction. |
ed6fb7bd SC |
5744 | */ |
5745 | ||
4d7206a2 | 5746 | if (offset_expr.X_add_number == 0) |
252b5132 | 5747 | { |
0a44bf69 RS |
5748 | if (mips_pic == SVR4_PIC |
5749 | && breg == 0 | |
5750 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5751 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5752 | ||
5753 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5754 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5755 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5756 | if (breg != 0) |
252b5132 RH |
5757 | { |
5758 | /* We're going to put in an addu instruction using | |
5759 | tempreg, so we may as well insert the nop right | |
5760 | now. */ | |
269137b2 | 5761 | load_delay_nop (); |
252b5132 | 5762 | } |
4d7206a2 | 5763 | relax_switch (); |
67c0d1eb RS |
5764 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5765 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5766 | load_delay_nop (); |
67c0d1eb RS |
5767 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5768 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5769 | relax_end (); |
252b5132 RH |
5770 | /* FIXME: If breg == 0, and the next instruction uses |
5771 | $tempreg, then if this variant case is used an extra | |
5772 | nop will be generated. */ | |
5773 | } | |
4d7206a2 RS |
5774 | else if (offset_expr.X_add_number >= -0x8000 |
5775 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5776 | { |
67c0d1eb | 5777 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5778 | load_delay_nop (); |
67c0d1eb | 5779 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5780 | } |
5781 | else | |
5782 | { | |
4d7206a2 RS |
5783 | expr1.X_add_number = offset_expr.X_add_number; |
5784 | offset_expr.X_add_number = | |
5785 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5786 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5787 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5788 | /* If we are going to add in a base register, and the |
5789 | target register and the base register are the same, | |
5790 | then we are using AT as a temporary register. Since | |
5791 | we want to load the constant into AT, we add our | |
5792 | current AT (from the global offset table) and the | |
5793 | register into the register now, and pretend we were | |
5794 | not using a base register. */ | |
67c0d1eb | 5795 | if (breg == treg) |
252b5132 | 5796 | { |
269137b2 | 5797 | load_delay_nop (); |
67c0d1eb | 5798 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5799 | treg, AT, breg); |
252b5132 RH |
5800 | breg = 0; |
5801 | tempreg = treg; | |
252b5132 | 5802 | } |
f6a22291 | 5803 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5804 | used_at = 1; |
5805 | } | |
5806 | } | |
0a44bf69 | 5807 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5808 | { |
67c0d1eb | 5809 | int add_breg_early = 0; |
f5040a92 AO |
5810 | |
5811 | /* If this is a reference to an external, and there is no | |
5812 | constant, or local symbol (*), with or without a | |
5813 | constant, we want | |
5814 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5815 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5816 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5817 | ||
5818 | If we have a small constant, and this is a reference to | |
5819 | an external symbol, we want | |
5820 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5821 | addiu $tempreg,$tempreg,<constant> | |
5822 | ||
5823 | If we have a large constant, and this is a reference to | |
5824 | an external symbol, we want | |
5825 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5826 | lui $at,<hiconstant> | |
5827 | addiu $at,$at,<loconstant> | |
5828 | addu $tempreg,$tempreg,$at | |
5829 | ||
5830 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5831 | local symbols, even though it introduces an additional | |
5832 | instruction. */ | |
5833 | ||
f5040a92 AO |
5834 | if (offset_expr.X_add_number) |
5835 | { | |
4d7206a2 | 5836 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5837 | offset_expr.X_add_number = 0; |
5838 | ||
4d7206a2 | 5839 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5840 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5841 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5842 | |
5843 | if (expr1.X_add_number >= -0x8000 | |
5844 | && expr1.X_add_number < 0x8000) | |
5845 | { | |
67c0d1eb RS |
5846 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5847 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5848 | } |
ecd13cd3 | 5849 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 5850 | { |
f5040a92 AO |
5851 | /* If we are going to add in a base register, and the |
5852 | target register and the base register are the same, | |
5853 | then we are using AT as a temporary register. Since | |
5854 | we want to load the constant into AT, we add our | |
5855 | current AT (from the global offset table) and the | |
5856 | register into the register now, and pretend we were | |
5857 | not using a base register. */ | |
5858 | if (breg != treg) | |
5859 | dreg = tempreg; | |
5860 | else | |
5861 | { | |
9c2799c2 | 5862 | gas_assert (tempreg == AT); |
67c0d1eb RS |
5863 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5864 | treg, AT, breg); | |
f5040a92 | 5865 | dreg = treg; |
67c0d1eb | 5866 | add_breg_early = 1; |
f5040a92 AO |
5867 | } |
5868 | ||
f6a22291 | 5869 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5870 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5871 | dreg, dreg, AT); |
f5040a92 | 5872 | |
f5040a92 AO |
5873 | used_at = 1; |
5874 | } | |
5875 | else | |
5876 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5877 | ||
4d7206a2 | 5878 | relax_switch (); |
f5040a92 AO |
5879 | offset_expr.X_add_number = expr1.X_add_number; |
5880 | ||
67c0d1eb RS |
5881 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5882 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5883 | if (add_breg_early) | |
f5040a92 | 5884 | { |
67c0d1eb | 5885 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5886 | treg, tempreg, breg); |
f5040a92 AO |
5887 | breg = 0; |
5888 | tempreg = treg; | |
5889 | } | |
4d7206a2 | 5890 | relax_end (); |
f5040a92 | 5891 | } |
4d7206a2 | 5892 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5893 | { |
4d7206a2 | 5894 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5895 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5896 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5897 | relax_switch (); |
67c0d1eb RS |
5898 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5899 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5900 | relax_end (); |
f5040a92 | 5901 | } |
4d7206a2 | 5902 | else |
f5040a92 | 5903 | { |
67c0d1eb RS |
5904 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5905 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5906 | } |
5907 | } | |
0a44bf69 | 5908 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5909 | { |
67c0d1eb | 5910 | int gpdelay; |
9117d219 NC |
5911 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5912 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5913 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5914 | |
5915 | /* This is the large GOT case. If this is a reference to an | |
5916 | external symbol, and there is no constant, we want | |
5917 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5918 | addu $tempreg,$tempreg,$gp | |
5919 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5920 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5921 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5922 | addu $tempreg,$tempreg,$gp | |
5923 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5924 | For a local symbol, we want |
5925 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5926 | nop | |
5927 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5928 | ||
5929 | If we have a small constant, and this is a reference to | |
5930 | an external symbol, we want | |
5931 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5932 | addu $tempreg,$tempreg,$gp | |
5933 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5934 | nop | |
5935 | addiu $tempreg,$tempreg,<constant> | |
5936 | For a local symbol, we want | |
5937 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5938 | nop | |
5939 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5940 | ||
5941 | If we have a large constant, and this is a reference to | |
5942 | an external symbol, we want | |
5943 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5944 | addu $tempreg,$tempreg,$gp | |
5945 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5946 | lui $at,<hiconstant> | |
5947 | addiu $at,$at,<loconstant> | |
5948 | addu $tempreg,$tempreg,$at | |
5949 | For a local symbol, we want | |
5950 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5951 | lui $at,<hiconstant> | |
5952 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5953 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5954 | */ |
438c16b8 | 5955 | |
252b5132 RH |
5956 | expr1.X_add_number = offset_expr.X_add_number; |
5957 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5958 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5959 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5960 | if (expr1.X_add_number == 0 && breg == 0 |
5961 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5962 | { |
5963 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5964 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5965 | } | |
67c0d1eb RS |
5966 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5967 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5968 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5969 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5970 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5971 | if (expr1.X_add_number == 0) |
5972 | { | |
67c0d1eb | 5973 | if (breg != 0) |
252b5132 RH |
5974 | { |
5975 | /* We're going to put in an addu instruction using | |
5976 | tempreg, so we may as well insert the nop right | |
5977 | now. */ | |
269137b2 | 5978 | load_delay_nop (); |
252b5132 | 5979 | } |
252b5132 RH |
5980 | } |
5981 | else if (expr1.X_add_number >= -0x8000 | |
5982 | && expr1.X_add_number < 0x8000) | |
5983 | { | |
269137b2 | 5984 | load_delay_nop (); |
67c0d1eb | 5985 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5986 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5987 | } |
5988 | else | |
5989 | { | |
252b5132 RH |
5990 | /* If we are going to add in a base register, and the |
5991 | target register and the base register are the same, | |
5992 | then we are using AT as a temporary register. Since | |
5993 | we want to load the constant into AT, we add our | |
5994 | current AT (from the global offset table) and the | |
5995 | register into the register now, and pretend we were | |
5996 | not using a base register. */ | |
5997 | if (breg != treg) | |
67c0d1eb | 5998 | dreg = tempreg; |
252b5132 RH |
5999 | else |
6000 | { | |
9c2799c2 | 6001 | gas_assert (tempreg == AT); |
269137b2 | 6002 | load_delay_nop (); |
67c0d1eb | 6003 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6004 | treg, AT, breg); |
252b5132 | 6005 | dreg = treg; |
252b5132 RH |
6006 | } |
6007 | ||
f6a22291 | 6008 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6009 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 6010 | |
252b5132 RH |
6011 | used_at = 1; |
6012 | } | |
4d7206a2 RS |
6013 | offset_expr.X_add_number = |
6014 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
6015 | relax_switch (); | |
252b5132 | 6016 | |
67c0d1eb | 6017 | if (gpdelay) |
252b5132 RH |
6018 | { |
6019 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 6020 | the first instruction on the main stream does not. */ |
67c0d1eb | 6021 | macro_build (NULL, "nop", ""); |
252b5132 | 6022 | } |
ed6fb7bd | 6023 | |
67c0d1eb RS |
6024 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6025 | local_reloc_type, mips_gp_register); | |
f5040a92 | 6026 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
6027 | && expr1.X_add_number < 0x8000) |
6028 | { | |
269137b2 | 6029 | load_delay_nop (); |
67c0d1eb RS |
6030 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6031 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 6032 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
6033 | register, the external symbol case ended with a load, |
6034 | so if the symbol turns out to not be external, and | |
6035 | the next instruction uses tempreg, an unnecessary nop | |
6036 | will be inserted. */ | |
252b5132 RH |
6037 | } |
6038 | else | |
6039 | { | |
6040 | if (breg == treg) | |
6041 | { | |
6042 | /* We must add in the base register now, as in the | |
f5040a92 | 6043 | external symbol case. */ |
9c2799c2 | 6044 | gas_assert (tempreg == AT); |
269137b2 | 6045 | load_delay_nop (); |
67c0d1eb | 6046 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6047 | treg, AT, breg); |
252b5132 RH |
6048 | tempreg = treg; |
6049 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 6050 | it in in both cases. */ |
252b5132 RH |
6051 | breg = 0; |
6052 | } | |
6053 | ||
67c0d1eb RS |
6054 | macro_build_lui (&expr1, AT); |
6055 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 6056 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 6057 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6058 | tempreg, tempreg, AT); |
8fc2e39e | 6059 | used_at = 1; |
252b5132 | 6060 | } |
4d7206a2 | 6061 | relax_end (); |
252b5132 | 6062 | } |
0a44bf69 | 6063 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6064 | { |
f5040a92 AO |
6065 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6066 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 6067 | int add_breg_early = 0; |
f5040a92 AO |
6068 | |
6069 | /* This is the large GOT case. If this is a reference to an | |
6070 | external symbol, and there is no constant, we want | |
6071 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6072 | add $tempreg,$tempreg,$gp | |
6073 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6074 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
6075 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6076 | add $tempreg,$tempreg,$gp | |
6077 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
6078 | ||
6079 | If we have a small constant, and this is a reference to | |
6080 | an external symbol, we want | |
6081 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6082 | add $tempreg,$tempreg,$gp | |
6083 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6084 | addi $tempreg,$tempreg,<constant> | |
6085 | ||
6086 | If we have a large constant, and this is a reference to | |
6087 | an external symbol, we want | |
6088 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6089 | addu $tempreg,$tempreg,$gp | |
6090 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6091 | lui $at,<hiconstant> | |
6092 | addi $at,$at,<loconstant> | |
6093 | add $tempreg,$tempreg,$at | |
6094 | ||
6095 | If we have NewABI, and we know it's a local symbol, we want | |
6096 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6097 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6098 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
6099 | ||
4d7206a2 | 6100 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 6101 | |
4d7206a2 | 6102 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6103 | offset_expr.X_add_number = 0; |
6104 | ||
1abe91b1 MR |
6105 | if (expr1.X_add_number == 0 && breg == 0 |
6106 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
6107 | { |
6108 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6109 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6110 | } | |
67c0d1eb RS |
6111 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6112 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6113 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
6114 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6115 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
6116 | |
6117 | if (expr1.X_add_number == 0) | |
4d7206a2 | 6118 | ; |
f5040a92 AO |
6119 | else if (expr1.X_add_number >= -0x8000 |
6120 | && expr1.X_add_number < 0x8000) | |
6121 | { | |
67c0d1eb | 6122 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6123 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 6124 | } |
ecd13cd3 | 6125 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6126 | { |
f5040a92 AO |
6127 | /* If we are going to add in a base register, and the |
6128 | target register and the base register are the same, | |
6129 | then we are using AT as a temporary register. Since | |
6130 | we want to load the constant into AT, we add our | |
6131 | current AT (from the global offset table) and the | |
6132 | register into the register now, and pretend we were | |
6133 | not using a base register. */ | |
6134 | if (breg != treg) | |
6135 | dreg = tempreg; | |
6136 | else | |
6137 | { | |
9c2799c2 | 6138 | gas_assert (tempreg == AT); |
67c0d1eb | 6139 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6140 | treg, AT, breg); |
f5040a92 | 6141 | dreg = treg; |
67c0d1eb | 6142 | add_breg_early = 1; |
f5040a92 AO |
6143 | } |
6144 | ||
f6a22291 | 6145 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6146 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 6147 | |
f5040a92 AO |
6148 | used_at = 1; |
6149 | } | |
6150 | else | |
6151 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6152 | ||
4d7206a2 | 6153 | relax_switch (); |
f5040a92 | 6154 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6155 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6156 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
6157 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6158 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
6159 | if (add_breg_early) | |
f5040a92 | 6160 | { |
67c0d1eb | 6161 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6162 | treg, tempreg, breg); |
f5040a92 AO |
6163 | breg = 0; |
6164 | tempreg = treg; | |
6165 | } | |
4d7206a2 | 6166 | relax_end (); |
f5040a92 | 6167 | } |
252b5132 RH |
6168 | else |
6169 | abort (); | |
6170 | ||
6171 | if (breg != 0) | |
aed1a261 | 6172 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
6173 | break; |
6174 | ||
52b6b6b9 JM |
6175 | case M_MSGSND: |
6176 | { | |
6177 | unsigned long temp = (treg << 16) | (0x01); | |
6178 | macro_build (NULL, "c2", "C", temp); | |
6179 | } | |
c7af4273 | 6180 | break; |
52b6b6b9 JM |
6181 | |
6182 | case M_MSGLD: | |
6183 | { | |
6184 | unsigned long temp = (0x02); | |
6185 | macro_build (NULL, "c2", "C", temp); | |
6186 | } | |
c7af4273 | 6187 | break; |
52b6b6b9 JM |
6188 | |
6189 | case M_MSGLD_T: | |
6190 | { | |
6191 | unsigned long temp = (treg << 16) | (0x02); | |
6192 | macro_build (NULL, "c2", "C", temp); | |
6193 | } | |
c7af4273 | 6194 | break; |
52b6b6b9 JM |
6195 | |
6196 | case M_MSGWAIT: | |
6197 | macro_build (NULL, "c2", "C", 3); | |
c7af4273 | 6198 | break; |
52b6b6b9 JM |
6199 | |
6200 | case M_MSGWAIT_T: | |
6201 | { | |
6202 | unsigned long temp = (treg << 16) | 0x03; | |
6203 | macro_build (NULL, "c2", "C", temp); | |
6204 | } | |
c7af4273 | 6205 | break; |
52b6b6b9 | 6206 | |
252b5132 RH |
6207 | case M_J_A: |
6208 | /* The j instruction may not be used in PIC code, since it | |
6209 | requires an absolute address. We convert it to a b | |
6210 | instruction. */ | |
6211 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6212 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 6213 | else |
67c0d1eb | 6214 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6215 | break; |
252b5132 RH |
6216 | |
6217 | /* The jal instructions must be handled as macros because when | |
6218 | generating PIC code they expand to multi-instruction | |
6219 | sequences. Normally they are simple instructions. */ | |
6220 | case M_JAL_1: | |
6221 | dreg = RA; | |
6222 | /* Fall through. */ | |
6223 | case M_JAL_2: | |
3e722fb5 | 6224 | if (mips_pic == NO_PIC) |
67c0d1eb | 6225 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6226 | else |
252b5132 RH |
6227 | { |
6228 | if (sreg != PIC_CALL_REG) | |
6229 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 6230 | |
67c0d1eb | 6231 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6232 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 6233 | { |
6478892d TS |
6234 | if (mips_cprestore_offset < 0) |
6235 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6236 | else | |
6237 | { | |
90ecf173 | 6238 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6239 | { |
6240 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6241 | /* Quiet this warning. */ | |
6242 | mips_frame_reg_valid = 1; | |
6243 | } | |
90ecf173 | 6244 | if (!mips_cprestore_valid) |
7a621144 DJ |
6245 | { |
6246 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6247 | /* Quiet this warning. */ | |
6248 | mips_cprestore_valid = 1; | |
6249 | } | |
d3fca0b5 MR |
6250 | if (mips_opts.noreorder) |
6251 | macro_build (NULL, "nop", ""); | |
6478892d | 6252 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6253 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6254 | mips_gp_register, |
256ab948 TS |
6255 | mips_frame_reg, |
6256 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6257 | } |
252b5132 RH |
6258 | } |
6259 | } | |
252b5132 | 6260 | |
8fc2e39e | 6261 | break; |
252b5132 RH |
6262 | |
6263 | case M_JAL_A: | |
6264 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6265 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6266 | else if (mips_pic == SVR4_PIC) |
6267 | { | |
6268 | /* If this is a reference to an external symbol, and we are | |
6269 | using a small GOT, we want | |
6270 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6271 | nop | |
f9419b05 | 6272 | jalr $ra,$25 |
252b5132 RH |
6273 | nop |
6274 | lw $gp,cprestore($sp) | |
6275 | The cprestore value is set using the .cprestore | |
6276 | pseudo-op. If we are using a big GOT, we want | |
6277 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6278 | addu $25,$25,$gp | |
6279 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6280 | nop | |
f9419b05 | 6281 | jalr $ra,$25 |
252b5132 RH |
6282 | nop |
6283 | lw $gp,cprestore($sp) | |
6284 | If the symbol is not external, we want | |
6285 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6286 | nop | |
6287 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6288 | jalr $ra,$25 |
252b5132 | 6289 | nop |
438c16b8 | 6290 | lw $gp,cprestore($sp) |
f5040a92 AO |
6291 | |
6292 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6293 | sequences above, minus nops, unless the symbol is local, | |
6294 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6295 | GOT_DISP. */ | |
438c16b8 | 6296 | if (HAVE_NEWABI) |
252b5132 | 6297 | { |
90ecf173 | 6298 | if (!mips_big_got) |
f5040a92 | 6299 | { |
4d7206a2 | 6300 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6301 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6302 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6303 | mips_gp_register); |
4d7206a2 | 6304 | relax_switch (); |
67c0d1eb RS |
6305 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6306 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6307 | mips_gp_register); |
6308 | relax_end (); | |
f5040a92 AO |
6309 | } |
6310 | else | |
6311 | { | |
4d7206a2 | 6312 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6313 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6314 | BFD_RELOC_MIPS_CALL_HI16); | |
6315 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6316 | PIC_CALL_REG, mips_gp_register); | |
6317 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6318 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6319 | PIC_CALL_REG); | |
4d7206a2 | 6320 | relax_switch (); |
67c0d1eb RS |
6321 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6322 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6323 | mips_gp_register); | |
6324 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6325 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6326 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6327 | relax_end (); |
f5040a92 | 6328 | } |
684022ea | 6329 | |
67c0d1eb | 6330 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6331 | } |
6332 | else | |
6333 | { | |
4d7206a2 | 6334 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 6335 | if (!mips_big_got) |
438c16b8 | 6336 | { |
67c0d1eb RS |
6337 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6338 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6339 | mips_gp_register); |
269137b2 | 6340 | load_delay_nop (); |
4d7206a2 | 6341 | relax_switch (); |
438c16b8 | 6342 | } |
252b5132 | 6343 | else |
252b5132 | 6344 | { |
67c0d1eb RS |
6345 | int gpdelay; |
6346 | ||
6347 | gpdelay = reg_needs_delay (mips_gp_register); | |
6348 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6349 | BFD_RELOC_MIPS_CALL_HI16); | |
6350 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6351 | PIC_CALL_REG, mips_gp_register); | |
6352 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6353 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6354 | PIC_CALL_REG); | |
269137b2 | 6355 | load_delay_nop (); |
4d7206a2 | 6356 | relax_switch (); |
67c0d1eb RS |
6357 | if (gpdelay) |
6358 | macro_build (NULL, "nop", ""); | |
252b5132 | 6359 | } |
67c0d1eb RS |
6360 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6361 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6362 | mips_gp_register); |
269137b2 | 6363 | load_delay_nop (); |
67c0d1eb RS |
6364 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6365 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6366 | relax_end (); |
67c0d1eb | 6367 | macro_build_jalr (&offset_expr); |
438c16b8 | 6368 | |
6478892d TS |
6369 | if (mips_cprestore_offset < 0) |
6370 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6371 | else | |
6372 | { | |
90ecf173 | 6373 | if (!mips_frame_reg_valid) |
7a621144 DJ |
6374 | { |
6375 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6376 | /* Quiet this warning. */ | |
6377 | mips_frame_reg_valid = 1; | |
6378 | } | |
90ecf173 | 6379 | if (!mips_cprestore_valid) |
7a621144 DJ |
6380 | { |
6381 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6382 | /* Quiet this warning. */ | |
6383 | mips_cprestore_valid = 1; | |
6384 | } | |
6478892d | 6385 | if (mips_opts.noreorder) |
67c0d1eb | 6386 | macro_build (NULL, "nop", ""); |
6478892d | 6387 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6388 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6389 | mips_gp_register, |
256ab948 TS |
6390 | mips_frame_reg, |
6391 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6392 | } |
252b5132 RH |
6393 | } |
6394 | } | |
0a44bf69 RS |
6395 | else if (mips_pic == VXWORKS_PIC) |
6396 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6397 | else |
6398 | abort (); | |
6399 | ||
8fc2e39e | 6400 | break; |
252b5132 RH |
6401 | |
6402 | case M_LB_AB: | |
6403 | s = "lb"; | |
6404 | goto ld; | |
6405 | case M_LBU_AB: | |
6406 | s = "lbu"; | |
6407 | goto ld; | |
6408 | case M_LH_AB: | |
6409 | s = "lh"; | |
6410 | goto ld; | |
6411 | case M_LHU_AB: | |
6412 | s = "lhu"; | |
6413 | goto ld; | |
6414 | case M_LW_AB: | |
6415 | s = "lw"; | |
6416 | goto ld; | |
6417 | case M_LWC0_AB: | |
6418 | s = "lwc0"; | |
bdaaa2e1 | 6419 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6420 | coproc = 1; |
6421 | goto ld; | |
6422 | case M_LWC1_AB: | |
6423 | s = "lwc1"; | |
bdaaa2e1 | 6424 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6425 | coproc = 1; |
6426 | goto ld; | |
6427 | case M_LWC2_AB: | |
6428 | s = "lwc2"; | |
bdaaa2e1 | 6429 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6430 | coproc = 1; |
6431 | goto ld; | |
6432 | case M_LWC3_AB: | |
6433 | s = "lwc3"; | |
bdaaa2e1 | 6434 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6435 | coproc = 1; |
6436 | goto ld; | |
6437 | case M_LWL_AB: | |
6438 | s = "lwl"; | |
6439 | lr = 1; | |
6440 | goto ld; | |
6441 | case M_LWR_AB: | |
6442 | s = "lwr"; | |
6443 | lr = 1; | |
6444 | goto ld; | |
6445 | case M_LDC1_AB: | |
252b5132 | 6446 | s = "ldc1"; |
bdaaa2e1 | 6447 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6448 | coproc = 1; |
6449 | goto ld; | |
6450 | case M_LDC2_AB: | |
6451 | s = "ldc2"; | |
bdaaa2e1 | 6452 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6453 | coproc = 1; |
6454 | goto ld; | |
6455 | case M_LDC3_AB: | |
6456 | s = "ldc3"; | |
bdaaa2e1 | 6457 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6458 | coproc = 1; |
6459 | goto ld; | |
6460 | case M_LDL_AB: | |
6461 | s = "ldl"; | |
6462 | lr = 1; | |
6463 | goto ld; | |
6464 | case M_LDR_AB: | |
6465 | s = "ldr"; | |
6466 | lr = 1; | |
6467 | goto ld; | |
6468 | case M_LL_AB: | |
6469 | s = "ll"; | |
6470 | goto ld; | |
6471 | case M_LLD_AB: | |
6472 | s = "lld"; | |
6473 | goto ld; | |
6474 | case M_LWU_AB: | |
6475 | s = "lwu"; | |
6476 | ld: | |
8fc2e39e | 6477 | if (breg == treg || coproc || lr) |
252b5132 RH |
6478 | { |
6479 | tempreg = AT; | |
6480 | used_at = 1; | |
6481 | } | |
6482 | else | |
6483 | { | |
6484 | tempreg = treg; | |
252b5132 RH |
6485 | } |
6486 | goto ld_st; | |
6487 | case M_SB_AB: | |
6488 | s = "sb"; | |
6489 | goto st; | |
6490 | case M_SH_AB: | |
6491 | s = "sh"; | |
6492 | goto st; | |
6493 | case M_SW_AB: | |
6494 | s = "sw"; | |
6495 | goto st; | |
6496 | case M_SWC0_AB: | |
6497 | s = "swc0"; | |
bdaaa2e1 | 6498 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6499 | coproc = 1; |
6500 | goto st; | |
6501 | case M_SWC1_AB: | |
6502 | s = "swc1"; | |
bdaaa2e1 | 6503 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6504 | coproc = 1; |
6505 | goto st; | |
6506 | case M_SWC2_AB: | |
6507 | s = "swc2"; | |
bdaaa2e1 | 6508 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6509 | coproc = 1; |
6510 | goto st; | |
6511 | case M_SWC3_AB: | |
6512 | s = "swc3"; | |
bdaaa2e1 | 6513 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6514 | coproc = 1; |
6515 | goto st; | |
6516 | case M_SWL_AB: | |
6517 | s = "swl"; | |
6518 | goto st; | |
6519 | case M_SWR_AB: | |
6520 | s = "swr"; | |
6521 | goto st; | |
6522 | case M_SC_AB: | |
6523 | s = "sc"; | |
6524 | goto st; | |
6525 | case M_SCD_AB: | |
6526 | s = "scd"; | |
6527 | goto st; | |
d43b4baf TS |
6528 | case M_CACHE_AB: |
6529 | s = "cache"; | |
6530 | goto st; | |
3eebd5eb MR |
6531 | case M_PREF_AB: |
6532 | s = "pref"; | |
6533 | goto st; | |
252b5132 | 6534 | case M_SDC1_AB: |
252b5132 RH |
6535 | s = "sdc1"; |
6536 | coproc = 1; | |
bdaaa2e1 | 6537 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6538 | goto st; |
6539 | case M_SDC2_AB: | |
6540 | s = "sdc2"; | |
bdaaa2e1 | 6541 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6542 | coproc = 1; |
6543 | goto st; | |
6544 | case M_SDC3_AB: | |
6545 | s = "sdc3"; | |
bdaaa2e1 | 6546 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6547 | coproc = 1; |
6548 | goto st; | |
6549 | case M_SDL_AB: | |
6550 | s = "sdl"; | |
6551 | goto st; | |
6552 | case M_SDR_AB: | |
6553 | s = "sdr"; | |
6554 | st: | |
8fc2e39e TS |
6555 | tempreg = AT; |
6556 | used_at = 1; | |
252b5132 | 6557 | ld_st: |
b19e8a9b AN |
6558 | if (coproc |
6559 | && NO_ISA_COP (mips_opts.arch) | |
6560 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
6561 | { | |
f71d0d44 | 6562 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
6563 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
6564 | break; | |
6565 | } | |
6566 | ||
bdaaa2e1 | 6567 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6568 | if (mask == M_LWC1_AB |
6569 | || mask == M_SWC1_AB | |
6570 | || mask == M_LDC1_AB | |
6571 | || mask == M_SDC1_AB | |
6572 | || mask == M_L_DAB | |
6573 | || mask == M_S_DAB) | |
6574 | fmt = "T,o(b)"; | |
3eebd5eb | 6575 | else if (mask == M_CACHE_AB || mask == M_PREF_AB) |
d43b4baf | 6576 | fmt = "k,o(b)"; |
252b5132 RH |
6577 | else if (coproc) |
6578 | fmt = "E,o(b)"; | |
6579 | else | |
6580 | fmt = "t,o(b)"; | |
6581 | ||
6582 | if (offset_expr.X_op != O_constant | |
6583 | && offset_expr.X_op != O_symbol) | |
6584 | { | |
f71d0d44 | 6585 | as_bad (_("Expression too complex")); |
252b5132 RH |
6586 | offset_expr.X_op = O_constant; |
6587 | } | |
6588 | ||
2051e8c4 MR |
6589 | if (HAVE_32BIT_ADDRESSES |
6590 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6591 | { |
6592 | char value [32]; | |
6593 | ||
6594 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6595 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6596 | } |
2051e8c4 | 6597 | |
252b5132 RH |
6598 | /* A constant expression in PIC code can be handled just as it |
6599 | is in non PIC code. */ | |
aed1a261 RS |
6600 | if (offset_expr.X_op == O_constant) |
6601 | { | |
842f8b2a | 6602 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 6603 | normalize_address_expr (&expr1); |
842f8b2a MR |
6604 | if (!IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
6605 | { | |
6606 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
6607 | & ~(bfd_vma) 0xffff); | |
6608 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
6609 | if (breg != 0) | |
6610 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6611 | tempreg, tempreg, breg); | |
6612 | breg = tempreg; | |
6613 | } | |
6614 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
aed1a261 RS |
6615 | } |
6616 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6617 | { |
6618 | /* If this is a reference to a GP relative symbol, and there | |
6619 | is no base register, we want | |
cdf6fd85 | 6620 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6621 | Otherwise, if there is no base register, we want |
6622 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6623 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6624 | If we have a constant, we need two instructions anyhow, | |
6625 | so we always use the latter form. | |
6626 | ||
6627 | If we have a base register, and this is a reference to a | |
6628 | GP relative symbol, we want | |
6629 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6630 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6631 | Otherwise we want |
6632 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6633 | addu $tempreg,$tempreg,$breg | |
6634 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6635 | With a constant we always use the latter case. |
76b3015f | 6636 | |
d6bc6245 TS |
6637 | With 64bit address space and no base register and $at usable, |
6638 | we want | |
6639 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6640 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6641 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6642 | dsll32 $tempreg,0 | |
6643 | daddu $tempreg,$at | |
6644 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6645 | If we have a base register, we want | |
6646 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6647 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6648 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6649 | daddu $at,$breg | |
6650 | dsll32 $tempreg,0 | |
6651 | daddu $tempreg,$at | |
6652 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6653 | ||
6654 | Without $at we can't generate the optimal path for superscalar | |
6655 | processors here since this would require two temporary registers. | |
6656 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6657 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6658 | dsll $tempreg,16 | |
6659 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6660 | dsll $tempreg,16 | |
6661 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6662 | If we have a base register, we want | |
6663 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6664 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6665 | dsll $tempreg,16 | |
6666 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6667 | dsll $tempreg,16 | |
6668 | daddu $tempreg,$tempreg,$breg | |
6669 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6670 | |
6caf9ef4 | 6671 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6672 | the same sequence as in 32bit address space. */ |
6673 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6674 | { |
aed1a261 | 6675 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6676 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6677 | { | |
6678 | relax_start (offset_expr.X_add_symbol); | |
6679 | if (breg == 0) | |
6680 | { | |
6681 | macro_build (&offset_expr, s, fmt, treg, | |
6682 | BFD_RELOC_GPREL16, mips_gp_register); | |
6683 | } | |
6684 | else | |
6685 | { | |
6686 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6687 | tempreg, breg, mips_gp_register); | |
6688 | macro_build (&offset_expr, s, fmt, treg, | |
6689 | BFD_RELOC_GPREL16, tempreg); | |
6690 | } | |
6691 | relax_switch (); | |
6692 | } | |
d6bc6245 | 6693 | |
741fe287 | 6694 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6695 | { |
67c0d1eb RS |
6696 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6697 | BFD_RELOC_MIPS_HIGHEST); | |
6698 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6699 | BFD_RELOC_HI16_S); | |
6700 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6701 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6702 | if (breg != 0) |
67c0d1eb RS |
6703 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6704 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6705 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6706 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6707 | tempreg); | |
d6bc6245 TS |
6708 | used_at = 1; |
6709 | } | |
6710 | else | |
6711 | { | |
67c0d1eb RS |
6712 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6713 | BFD_RELOC_MIPS_HIGHEST); | |
6714 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6715 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6716 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6717 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6718 | tempreg, BFD_RELOC_HI16_S); | |
6719 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6720 | if (breg != 0) |
67c0d1eb | 6721 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6722 | tempreg, tempreg, breg); |
67c0d1eb | 6723 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6724 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6725 | } |
6caf9ef4 TS |
6726 | |
6727 | if (mips_relax.sequence) | |
6728 | relax_end (); | |
8fc2e39e | 6729 | break; |
d6bc6245 | 6730 | } |
256ab948 | 6731 | |
252b5132 RH |
6732 | if (breg == 0) |
6733 | { | |
67c0d1eb | 6734 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6735 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6736 | { |
4d7206a2 | 6737 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6738 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6739 | mips_gp_register); | |
4d7206a2 | 6740 | relax_switch (); |
252b5132 | 6741 | } |
67c0d1eb RS |
6742 | macro_build_lui (&offset_expr, tempreg); |
6743 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6744 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6745 | if (mips_relax.sequence) |
6746 | relax_end (); | |
252b5132 RH |
6747 | } |
6748 | else | |
6749 | { | |
67c0d1eb | 6750 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6751 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6752 | { |
4d7206a2 | 6753 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6754 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6755 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6756 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6757 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6758 | relax_switch (); |
252b5132 | 6759 | } |
67c0d1eb RS |
6760 | macro_build_lui (&offset_expr, tempreg); |
6761 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6762 | tempreg, tempreg, breg); |
67c0d1eb | 6763 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6764 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6765 | if (mips_relax.sequence) |
6766 | relax_end (); | |
252b5132 RH |
6767 | } |
6768 | } | |
0a44bf69 | 6769 | else if (!mips_big_got) |
252b5132 | 6770 | { |
ed6fb7bd | 6771 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6772 | |
252b5132 RH |
6773 | /* If this is a reference to an external symbol, we want |
6774 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6775 | nop | |
6776 | <op> $treg,0($tempreg) | |
6777 | Otherwise we want | |
6778 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6779 | nop | |
6780 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6781 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6782 | |
6783 | For NewABI, we want | |
6784 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6785 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6786 | ||
252b5132 RH |
6787 | If there is a base register, we add it to $tempreg before |
6788 | the <op>. If there is a constant, we stick it in the | |
6789 | <op> instruction. We don't handle constants larger than | |
6790 | 16 bits, because we have no way to load the upper 16 bits | |
6791 | (actually, we could handle them for the subset of cases | |
6792 | in which we are not using $at). */ | |
9c2799c2 | 6793 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
6794 | if (HAVE_NEWABI) |
6795 | { | |
67c0d1eb RS |
6796 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6797 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6798 | if (breg != 0) |
67c0d1eb | 6799 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6800 | tempreg, tempreg, breg); |
67c0d1eb | 6801 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6802 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6803 | break; |
6804 | } | |
252b5132 RH |
6805 | expr1.X_add_number = offset_expr.X_add_number; |
6806 | offset_expr.X_add_number = 0; | |
6807 | if (expr1.X_add_number < -0x8000 | |
6808 | || expr1.X_add_number >= 0x8000) | |
6809 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6810 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6811 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6812 | load_delay_nop (); |
4d7206a2 RS |
6813 | relax_start (offset_expr.X_add_symbol); |
6814 | relax_switch (); | |
67c0d1eb RS |
6815 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6816 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6817 | relax_end (); |
252b5132 | 6818 | if (breg != 0) |
67c0d1eb | 6819 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6820 | tempreg, tempreg, breg); |
67c0d1eb | 6821 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6822 | } |
0a44bf69 | 6823 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6824 | { |
67c0d1eb | 6825 | int gpdelay; |
252b5132 RH |
6826 | |
6827 | /* If this is a reference to an external symbol, we want | |
6828 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6829 | addu $tempreg,$tempreg,$gp | |
6830 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6831 | <op> $treg,0($tempreg) | |
6832 | Otherwise we want | |
6833 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6834 | nop | |
6835 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6836 | <op> $treg,0($tempreg) | |
6837 | If there is a base register, we add it to $tempreg before | |
6838 | the <op>. If there is a constant, we stick it in the | |
6839 | <op> instruction. We don't handle constants larger than | |
6840 | 16 bits, because we have no way to load the upper 16 bits | |
6841 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6842 | in which we are not using $at). */ |
9c2799c2 | 6843 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
6844 | expr1.X_add_number = offset_expr.X_add_number; |
6845 | offset_expr.X_add_number = 0; | |
6846 | if (expr1.X_add_number < -0x8000 | |
6847 | || expr1.X_add_number >= 0x8000) | |
6848 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6849 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6850 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6851 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6852 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6853 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6854 | mips_gp_register); | |
6855 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6856 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6857 | relax_switch (); |
67c0d1eb RS |
6858 | if (gpdelay) |
6859 | macro_build (NULL, "nop", ""); | |
6860 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6861 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6862 | load_delay_nop (); |
67c0d1eb RS |
6863 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6864 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6865 | relax_end (); |
6866 | ||
252b5132 | 6867 | if (breg != 0) |
67c0d1eb | 6868 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6869 | tempreg, tempreg, breg); |
67c0d1eb | 6870 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6871 | } |
0a44bf69 | 6872 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6873 | { |
f5040a92 AO |
6874 | /* If this is a reference to an external symbol, we want |
6875 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6876 | add $tempreg,$tempreg,$gp | |
6877 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6878 | <op> $treg,<ofst>($tempreg) | |
6879 | Otherwise, for local symbols, we want: | |
6880 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6881 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 6882 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 6883 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6884 | offset_expr.X_add_number = 0; |
6885 | if (expr1.X_add_number < -0x8000 | |
6886 | || expr1.X_add_number >= 0x8000) | |
6887 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6888 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6889 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6890 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6891 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6892 | mips_gp_register); | |
6893 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6894 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6895 | if (breg != 0) |
67c0d1eb | 6896 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6897 | tempreg, tempreg, breg); |
67c0d1eb | 6898 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6899 | |
4d7206a2 | 6900 | relax_switch (); |
f5040a92 | 6901 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6902 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6903 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6904 | if (breg != 0) |
67c0d1eb | 6905 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6906 | tempreg, tempreg, breg); |
67c0d1eb | 6907 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6908 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6909 | relax_end (); |
f5040a92 | 6910 | } |
252b5132 RH |
6911 | else |
6912 | abort (); | |
6913 | ||
252b5132 RH |
6914 | break; |
6915 | ||
6916 | case M_LI: | |
6917 | case M_LI_S: | |
67c0d1eb | 6918 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6919 | break; |
252b5132 RH |
6920 | |
6921 | case M_DLI: | |
67c0d1eb | 6922 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6923 | break; |
252b5132 RH |
6924 | |
6925 | case M_LI_SS: | |
6926 | if (imm_expr.X_op == O_constant) | |
6927 | { | |
8fc2e39e | 6928 | used_at = 1; |
67c0d1eb RS |
6929 | load_register (AT, &imm_expr, 0); |
6930 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6931 | break; |
6932 | } | |
6933 | else | |
6934 | { | |
9c2799c2 | 6935 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
6936 | && strcmp (segment_name (S_GET_SEGMENT |
6937 | (offset_expr.X_add_symbol)), | |
6938 | ".lit4") == 0 | |
6939 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6940 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6941 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6942 | break; |
252b5132 RH |
6943 | } |
6944 | ||
6945 | case M_LI_D: | |
ca4e0257 RS |
6946 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6947 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6948 | order 32 bits of the value and the low order 32 bits are either | |
6949 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6950 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6951 | { | |
ca4e0257 | 6952 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6953 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6954 | else |
6955 | { | |
6956 | int hreg, lreg; | |
6957 | ||
6958 | if (target_big_endian) | |
6959 | { | |
6960 | hreg = treg; | |
6961 | lreg = treg + 1; | |
6962 | } | |
6963 | else | |
6964 | { | |
6965 | hreg = treg + 1; | |
6966 | lreg = treg; | |
6967 | } | |
6968 | ||
6969 | if (hreg <= 31) | |
67c0d1eb | 6970 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6971 | if (lreg <= 31) |
6972 | { | |
6973 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6974 | move_register (lreg, 0); |
252b5132 RH |
6975 | else |
6976 | { | |
9c2799c2 | 6977 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 6978 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6979 | } |
6980 | } | |
6981 | } | |
8fc2e39e | 6982 | break; |
252b5132 RH |
6983 | } |
6984 | ||
6985 | /* We know that sym is in the .rdata section. First we get the | |
6986 | upper 16 bits of the address. */ | |
6987 | if (mips_pic == NO_PIC) | |
6988 | { | |
67c0d1eb | 6989 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6990 | used_at = 1; |
252b5132 | 6991 | } |
0a44bf69 | 6992 | else |
252b5132 | 6993 | { |
67c0d1eb RS |
6994 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6995 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6996 | used_at = 1; |
252b5132 | 6997 | } |
bdaaa2e1 | 6998 | |
252b5132 | 6999 | /* Now we load the register(s). */ |
ca4e0257 | 7000 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
7001 | { |
7002 | used_at = 1; | |
7003 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
7004 | } | |
252b5132 RH |
7005 | else |
7006 | { | |
8fc2e39e | 7007 | used_at = 1; |
67c0d1eb | 7008 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 7009 | if (treg != RA) |
252b5132 RH |
7010 | { |
7011 | /* FIXME: How in the world do we deal with the possible | |
7012 | overflow here? */ | |
7013 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7014 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 7015 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
7016 | } |
7017 | } | |
252b5132 RH |
7018 | break; |
7019 | ||
7020 | case M_LI_DD: | |
ca4e0257 RS |
7021 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
7022 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
7023 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
7024 | the value and the low order 32 bits are either zero or in | |
7025 | OFFSET_EXPR. */ | |
252b5132 RH |
7026 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
7027 | { | |
8fc2e39e | 7028 | used_at = 1; |
67c0d1eb | 7029 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
7030 | if (HAVE_64BIT_FPRS) |
7031 | { | |
9c2799c2 | 7032 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 7033 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 7034 | } |
252b5132 RH |
7035 | else |
7036 | { | |
67c0d1eb | 7037 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 7038 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 7039 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
7040 | else |
7041 | { | |
9c2799c2 | 7042 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
7043 | load_register (AT, &offset_expr, 0); |
7044 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7045 | } |
7046 | } | |
7047 | break; | |
7048 | } | |
7049 | ||
9c2799c2 | 7050 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 7051 | && offset_expr.X_add_number == 0); |
252b5132 RH |
7052 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
7053 | if (strcmp (s, ".lit8") == 0) | |
7054 | { | |
e7af610e | 7055 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7056 | { |
67c0d1eb | 7057 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 7058 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7059 | break; |
252b5132 | 7060 | } |
c9914766 | 7061 | breg = mips_gp_register; |
252b5132 RH |
7062 | r = BFD_RELOC_MIPS_LITERAL; |
7063 | goto dob; | |
7064 | } | |
7065 | else | |
7066 | { | |
9c2799c2 | 7067 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 7068 | used_at = 1; |
0a44bf69 | 7069 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
7070 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7071 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
7072 | else |
7073 | { | |
7074 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 7075 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7076 | } |
bdaaa2e1 | 7077 | |
e7af610e | 7078 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7079 | { |
67c0d1eb RS |
7080 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
7081 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7082 | break; |
7083 | } | |
7084 | breg = AT; | |
7085 | r = BFD_RELOC_LO16; | |
7086 | goto dob; | |
7087 | } | |
7088 | ||
7089 | case M_L_DOB: | |
252b5132 RH |
7090 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7091 | to adjust when loading from memory. */ | |
7092 | r = BFD_RELOC_LO16; | |
7093 | dob: | |
9c2799c2 | 7094 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 7095 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7096 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
7097 | /* FIXME: A possible overflow which I don't know how to deal |
7098 | with. */ | |
7099 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7100 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7101 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
7102 | break; |
7103 | ||
c4a68bea MR |
7104 | case M_S_DOB: |
7105 | gas_assert (mips_opts.isa == ISA_MIPS1); | |
7106 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
7107 | to adjust when storing to memory. */ | |
7108 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7109 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
7110 | offset_expr.X_add_number += 4; | |
7111 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
7112 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
7113 | break; | |
7114 | ||
252b5132 RH |
7115 | case M_L_DAB: |
7116 | /* | |
7117 | * The MIPS assembler seems to check for X_add_number not | |
7118 | * being double aligned and generating: | |
7119 | * lui at,%hi(foo+1) | |
7120 | * addu at,at,v1 | |
7121 | * addiu at,at,%lo(foo+1) | |
7122 | * lwc1 f2,0(at) | |
7123 | * lwc1 f3,4(at) | |
7124 | * But, the resulting address is the same after relocation so why | |
7125 | * generate the extra instruction? | |
7126 | */ | |
bdaaa2e1 | 7127 | /* Itbl support may require additional care here. */ |
252b5132 | 7128 | coproc = 1; |
e7af610e | 7129 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7130 | { |
7131 | s = "ldc1"; | |
7132 | goto ld; | |
7133 | } | |
7134 | ||
7135 | s = "lwc1"; | |
7136 | fmt = "T,o(b)"; | |
7137 | goto ldd_std; | |
7138 | ||
7139 | case M_S_DAB: | |
e7af610e | 7140 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7141 | { |
7142 | s = "sdc1"; | |
7143 | goto st; | |
7144 | } | |
7145 | ||
7146 | s = "swc1"; | |
7147 | fmt = "T,o(b)"; | |
bdaaa2e1 | 7148 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7149 | coproc = 1; |
7150 | goto ldd_std; | |
7151 | ||
7152 | case M_LD_AB: | |
ca4e0257 | 7153 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7154 | { |
7155 | s = "ld"; | |
7156 | goto ld; | |
7157 | } | |
7158 | ||
7159 | s = "lw"; | |
7160 | fmt = "t,o(b)"; | |
7161 | goto ldd_std; | |
7162 | ||
7163 | case M_SD_AB: | |
ca4e0257 | 7164 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7165 | { |
7166 | s = "sd"; | |
7167 | goto st; | |
7168 | } | |
7169 | ||
7170 | s = "sw"; | |
7171 | fmt = "t,o(b)"; | |
7172 | ||
7173 | ldd_std: | |
7174 | if (offset_expr.X_op != O_symbol | |
7175 | && offset_expr.X_op != O_constant) | |
7176 | { | |
f71d0d44 | 7177 | as_bad (_("Expression too complex")); |
252b5132 RH |
7178 | offset_expr.X_op = O_constant; |
7179 | } | |
7180 | ||
2051e8c4 MR |
7181 | if (HAVE_32BIT_ADDRESSES |
7182 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
7183 | { |
7184 | char value [32]; | |
7185 | ||
7186 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 7187 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 7188 | } |
2051e8c4 | 7189 | |
252b5132 RH |
7190 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7191 | to adjust when loading from memory. We set coproc if we must | |
7192 | load $fn+1 first. */ | |
bdaaa2e1 | 7193 | /* Itbl support may require additional care here. */ |
90ecf173 | 7194 | if (!target_big_endian) |
252b5132 RH |
7195 | coproc = 0; |
7196 | ||
90ecf173 | 7197 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
7198 | { |
7199 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
7200 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7201 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7202 | If we have a base register, we use this |
7203 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7204 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7205 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7206 | If this is not a GP relative symbol, we want |
7207 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7208 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7209 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7210 | If there is a base register, we add it to $at after the | |
7211 | lui instruction. If there is a constant, we always use | |
7212 | the last case. */ | |
39a59cf8 MR |
7213 | if (offset_expr.X_op == O_symbol |
7214 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7215 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7216 | { |
4d7206a2 | 7217 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
7218 | if (breg == 0) |
7219 | { | |
c9914766 | 7220 | tempreg = mips_gp_register; |
252b5132 RH |
7221 | } |
7222 | else | |
7223 | { | |
67c0d1eb | 7224 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7225 | AT, breg, mips_gp_register); |
252b5132 | 7226 | tempreg = AT; |
252b5132 RH |
7227 | used_at = 1; |
7228 | } | |
7229 | ||
beae10d5 | 7230 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7231 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7232 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7233 | offset_expr.X_add_number += 4; |
7234 | ||
7235 | /* Set mips_optimize to 2 to avoid inserting an | |
7236 | undesired nop. */ | |
7237 | hold_mips_optimize = mips_optimize; | |
7238 | mips_optimize = 2; | |
beae10d5 | 7239 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7240 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7241 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7242 | mips_optimize = hold_mips_optimize; |
7243 | ||
4d7206a2 | 7244 | relax_switch (); |
252b5132 | 7245 | |
0970e49e | 7246 | offset_expr.X_add_number -= 4; |
252b5132 | 7247 | } |
8fc2e39e | 7248 | used_at = 1; |
67c0d1eb | 7249 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7250 | if (breg != 0) |
67c0d1eb | 7251 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7252 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7253 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7254 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7255 | /* FIXME: How do we handle overflow here? */ |
7256 | offset_expr.X_add_number += 4; | |
beae10d5 | 7257 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7258 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7259 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7260 | if (mips_relax.sequence) |
7261 | relax_end (); | |
bdaaa2e1 | 7262 | } |
0a44bf69 | 7263 | else if (!mips_big_got) |
252b5132 | 7264 | { |
252b5132 RH |
7265 | /* If this is a reference to an external symbol, we want |
7266 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7267 | nop | |
7268 | <op> $treg,0($at) | |
7269 | <op> $treg+1,4($at) | |
7270 | Otherwise we want | |
7271 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7272 | nop | |
7273 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7274 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7275 | If there is a base register we add it to $at before the | |
7276 | lwc1 instructions. If there is a constant we include it | |
7277 | in the lwc1 instructions. */ | |
7278 | used_at = 1; | |
7279 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7280 | if (expr1.X_add_number < -0x8000 |
7281 | || expr1.X_add_number >= 0x8000 - 4) | |
7282 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7283 | load_got_offset (AT, &offset_expr); |
269137b2 | 7284 | load_delay_nop (); |
252b5132 | 7285 | if (breg != 0) |
67c0d1eb | 7286 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7287 | |
7288 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7289 | nop. */ | |
7290 | hold_mips_optimize = mips_optimize; | |
7291 | mips_optimize = 2; | |
4d7206a2 | 7292 | |
beae10d5 | 7293 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7294 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7295 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7296 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7297 | expr1.X_add_number += 4; |
67c0d1eb RS |
7298 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7299 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7300 | relax_switch (); |
67c0d1eb RS |
7301 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7302 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7303 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7304 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7305 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7306 | relax_end (); |
252b5132 | 7307 | |
4d7206a2 | 7308 | mips_optimize = hold_mips_optimize; |
252b5132 | 7309 | } |
0a44bf69 | 7310 | else if (mips_big_got) |
252b5132 | 7311 | { |
67c0d1eb | 7312 | int gpdelay; |
252b5132 RH |
7313 | |
7314 | /* If this is a reference to an external symbol, we want | |
7315 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7316 | addu $at,$at,$gp | |
7317 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7318 | nop | |
7319 | <op> $treg,0($at) | |
7320 | <op> $treg+1,4($at) | |
7321 | Otherwise we want | |
7322 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7323 | nop | |
7324 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7325 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7326 | If there is a base register we add it to $at before the | |
7327 | lwc1 instructions. If there is a constant we include it | |
7328 | in the lwc1 instructions. */ | |
7329 | used_at = 1; | |
7330 | expr1.X_add_number = offset_expr.X_add_number; | |
7331 | offset_expr.X_add_number = 0; | |
7332 | if (expr1.X_add_number < -0x8000 | |
7333 | || expr1.X_add_number >= 0x8000 - 4) | |
7334 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7335 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7336 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7337 | macro_build (&offset_expr, "lui", "t,u", |
7338 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7339 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7340 | AT, AT, mips_gp_register); |
67c0d1eb | 7341 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7342 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7343 | load_delay_nop (); |
252b5132 | 7344 | if (breg != 0) |
67c0d1eb | 7345 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7346 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7347 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7348 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7349 | expr1.X_add_number += 4; |
7350 | ||
7351 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7352 | nop. */ | |
7353 | hold_mips_optimize = mips_optimize; | |
7354 | mips_optimize = 2; | |
beae10d5 | 7355 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7356 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7357 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7358 | mips_optimize = hold_mips_optimize; |
7359 | expr1.X_add_number -= 4; | |
7360 | ||
4d7206a2 RS |
7361 | relax_switch (); |
7362 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7363 | if (gpdelay) |
7364 | macro_build (NULL, "nop", ""); | |
7365 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7366 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7367 | load_delay_nop (); |
252b5132 | 7368 | if (breg != 0) |
67c0d1eb | 7369 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7370 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7371 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7372 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7373 | offset_expr.X_add_number += 4; |
252b5132 RH |
7374 | |
7375 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7376 | nop. */ | |
7377 | hold_mips_optimize = mips_optimize; | |
7378 | mips_optimize = 2; | |
beae10d5 | 7379 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7380 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7381 | BFD_RELOC_LO16, AT); | |
252b5132 | 7382 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7383 | relax_end (); |
252b5132 | 7384 | } |
252b5132 RH |
7385 | else |
7386 | abort (); | |
7387 | ||
252b5132 RH |
7388 | break; |
7389 | ||
7390 | case M_LD_OB: | |
704897fb | 7391 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
7392 | goto sd_ob; |
7393 | case M_SD_OB: | |
704897fb | 7394 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 7395 | sd_ob: |
4614d845 MR |
7396 | macro_build (&offset_expr, s, "t,o(b)", treg, |
7397 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
7398 | breg); | |
704897fb MR |
7399 | if (!HAVE_64BIT_GPRS) |
7400 | { | |
7401 | offset_expr.X_add_number += 4; | |
7402 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
7403 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
7404 | breg); | |
704897fb | 7405 | } |
8fc2e39e | 7406 | break; |
252b5132 RH |
7407 | |
7408 | /* New code added to support COPZ instructions. | |
7409 | This code builds table entries out of the macros in mip_opcodes. | |
7410 | R4000 uses interlocks to handle coproc delays. | |
7411 | Other chips (like the R3000) require nops to be inserted for delays. | |
7412 | ||
f72c8c98 | 7413 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7414 | In order to fill delay slots for non-interlocked chips, |
7415 | we must have a way to specify delays based on the coprocessor. | |
7416 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7417 | What are the side-effects of the cop instruction? | |
7418 | What cache support might we have and what are its effects? | |
7419 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7420 | What registers are read/set/modified? |
252b5132 RH |
7421 | |
7422 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7423 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7424 | |
7425 | case M_COP0: | |
7426 | s = "c0"; | |
7427 | goto copz; | |
7428 | case M_COP1: | |
7429 | s = "c1"; | |
7430 | goto copz; | |
7431 | case M_COP2: | |
7432 | s = "c2"; | |
7433 | goto copz; | |
7434 | case M_COP3: | |
7435 | s = "c3"; | |
7436 | copz: | |
b19e8a9b AN |
7437 | if (NO_ISA_COP (mips_opts.arch) |
7438 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
7439 | { | |
7440 | as_bad (_("opcode not supported on this processor: %s"), | |
7441 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
7442 | break; | |
7443 | } | |
7444 | ||
252b5132 RH |
7445 | /* For now we just do C (same as Cz). The parameter will be |
7446 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7447 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7448 | break; |
252b5132 | 7449 | |
ea1fb5dc | 7450 | case M_MOVE: |
67c0d1eb | 7451 | move_register (dreg, sreg); |
8fc2e39e | 7452 | break; |
ea1fb5dc | 7453 | |
252b5132 RH |
7454 | case M_DMUL: |
7455 | dbl = 1; | |
7456 | case M_MUL: | |
67c0d1eb RS |
7457 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7458 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7459 | break; |
252b5132 RH |
7460 | |
7461 | case M_DMUL_I: | |
7462 | dbl = 1; | |
7463 | case M_MUL_I: | |
7464 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7465 | not trying to be that fancy. GCC should do this for us | |
7466 | anyway. */ | |
8fc2e39e | 7467 | used_at = 1; |
67c0d1eb RS |
7468 | load_register (AT, &imm_expr, dbl); |
7469 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7470 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7471 | break; |
7472 | ||
7473 | case M_DMULO_I: | |
7474 | dbl = 1; | |
7475 | case M_MULO_I: | |
7476 | imm = 1; | |
7477 | goto do_mulo; | |
7478 | ||
7479 | case M_DMULO: | |
7480 | dbl = 1; | |
7481 | case M_MULO: | |
7482 | do_mulo: | |
7d10b47d | 7483 | start_noreorder (); |
8fc2e39e | 7484 | used_at = 1; |
252b5132 | 7485 | if (imm) |
67c0d1eb RS |
7486 | load_register (AT, &imm_expr, dbl); |
7487 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7488 | macro_build (NULL, "mflo", "d", dreg); | |
7489 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7490 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7491 | if (mips_trap) |
67c0d1eb | 7492 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7493 | else |
7494 | { | |
7495 | expr1.X_add_number = 8; | |
67c0d1eb | 7496 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
a605d2b3 | 7497 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7498 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7499 | } |
7d10b47d | 7500 | end_noreorder (); |
67c0d1eb | 7501 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7502 | break; |
7503 | ||
7504 | case M_DMULOU_I: | |
7505 | dbl = 1; | |
7506 | case M_MULOU_I: | |
7507 | imm = 1; | |
7508 | goto do_mulou; | |
7509 | ||
7510 | case M_DMULOU: | |
7511 | dbl = 1; | |
7512 | case M_MULOU: | |
7513 | do_mulou: | |
7d10b47d | 7514 | start_noreorder (); |
8fc2e39e | 7515 | used_at = 1; |
252b5132 | 7516 | if (imm) |
67c0d1eb RS |
7517 | load_register (AT, &imm_expr, dbl); |
7518 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7519 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7520 | macro_build (NULL, "mfhi", "d", AT); |
7521 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7522 | if (mips_trap) |
c80c840e | 7523 | macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6); |
252b5132 RH |
7524 | else |
7525 | { | |
7526 | expr1.X_add_number = 8; | |
c80c840e | 7527 | macro_build (&expr1, "beq", "s,t,p", AT, ZERO); |
a605d2b3 | 7528 | macro_build (NULL, "nop", ""); |
67c0d1eb | 7529 | macro_build (NULL, "break", "c", 6); |
252b5132 | 7530 | } |
7d10b47d | 7531 | end_noreorder (); |
252b5132 RH |
7532 | break; |
7533 | ||
771c7ce4 | 7534 | case M_DROL: |
fef14a42 | 7535 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7536 | { |
7537 | if (dreg == sreg) | |
7538 | { | |
7539 | tempreg = AT; | |
7540 | used_at = 1; | |
7541 | } | |
7542 | else | |
7543 | { | |
7544 | tempreg = dreg; | |
82dd0097 | 7545 | } |
67c0d1eb RS |
7546 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7547 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7548 | break; |
82dd0097 | 7549 | } |
8fc2e39e | 7550 | used_at = 1; |
c80c840e | 7551 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7552 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
7553 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7554 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7555 | break; |
7556 | ||
252b5132 | 7557 | case M_ROL: |
fef14a42 | 7558 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7559 | { |
7560 | if (dreg == sreg) | |
7561 | { | |
7562 | tempreg = AT; | |
7563 | used_at = 1; | |
7564 | } | |
7565 | else | |
7566 | { | |
7567 | tempreg = dreg; | |
82dd0097 | 7568 | } |
67c0d1eb RS |
7569 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7570 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7571 | break; |
82dd0097 | 7572 | } |
8fc2e39e | 7573 | used_at = 1; |
c80c840e | 7574 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7575 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
7576 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7577 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7578 | break; |
7579 | ||
771c7ce4 TS |
7580 | case M_DROL_I: |
7581 | { | |
7582 | unsigned int rot; | |
91d6fa6a NC |
7583 | char *l; |
7584 | char *rr; | |
771c7ce4 TS |
7585 | |
7586 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7587 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7588 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7589 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7590 | { |
7591 | rot = (64 - rot) & 0x3f; | |
7592 | if (rot >= 32) | |
67c0d1eb | 7593 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7594 | else |
67c0d1eb | 7595 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7596 | break; |
60b63b72 | 7597 | } |
483fc7cd | 7598 | if (rot == 0) |
483fc7cd | 7599 | { |
67c0d1eb | 7600 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7601 | break; |
483fc7cd | 7602 | } |
82dd0097 | 7603 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 7604 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 7605 | rot &= 0x1f; |
8fc2e39e | 7606 | used_at = 1; |
67c0d1eb | 7607 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
91d6fa6a | 7608 | macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
67c0d1eb | 7609 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
7610 | } |
7611 | break; | |
7612 | ||
252b5132 | 7613 | case M_ROL_I: |
771c7ce4 TS |
7614 | { |
7615 | unsigned int rot; | |
7616 | ||
7617 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7618 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7619 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7620 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7621 | { |
67c0d1eb | 7622 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7623 | break; |
60b63b72 | 7624 | } |
483fc7cd | 7625 | if (rot == 0) |
483fc7cd | 7626 | { |
67c0d1eb | 7627 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7628 | break; |
483fc7cd | 7629 | } |
8fc2e39e | 7630 | used_at = 1; |
67c0d1eb RS |
7631 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7632 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7633 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7634 | } |
7635 | break; | |
7636 | ||
7637 | case M_DROR: | |
fef14a42 | 7638 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7639 | { |
67c0d1eb | 7640 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7641 | break; |
82dd0097 | 7642 | } |
8fc2e39e | 7643 | used_at = 1; |
c80c840e | 7644 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7645 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
7646 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7647 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7648 | break; |
7649 | ||
7650 | case M_ROR: | |
fef14a42 | 7651 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7652 | { |
67c0d1eb | 7653 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7654 | break; |
82dd0097 | 7655 | } |
8fc2e39e | 7656 | used_at = 1; |
c80c840e | 7657 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
7658 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
7659 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7660 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7661 | break; |
7662 | ||
771c7ce4 TS |
7663 | case M_DROR_I: |
7664 | { | |
7665 | unsigned int rot; | |
91d6fa6a NC |
7666 | char *l; |
7667 | char *rr; | |
771c7ce4 TS |
7668 | |
7669 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7670 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7671 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7672 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7673 | { |
7674 | if (rot >= 32) | |
67c0d1eb | 7675 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7676 | else |
67c0d1eb | 7677 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7678 | break; |
82dd0097 | 7679 | } |
483fc7cd | 7680 | if (rot == 0) |
483fc7cd | 7681 | { |
67c0d1eb | 7682 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7683 | break; |
483fc7cd | 7684 | } |
91d6fa6a | 7685 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
7686 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
7687 | rot &= 0x1f; | |
8fc2e39e | 7688 | used_at = 1; |
91d6fa6a | 7689 | macro_build (NULL, rr, "d,w,<", AT, sreg, rot); |
67c0d1eb RS |
7690 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
7691 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7692 | } |
7693 | break; | |
7694 | ||
252b5132 | 7695 | case M_ROR_I: |
771c7ce4 TS |
7696 | { |
7697 | unsigned int rot; | |
7698 | ||
7699 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7700 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7701 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7702 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7703 | { |
67c0d1eb | 7704 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7705 | break; |
82dd0097 | 7706 | } |
483fc7cd | 7707 | if (rot == 0) |
483fc7cd | 7708 | { |
67c0d1eb | 7709 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7710 | break; |
483fc7cd | 7711 | } |
8fc2e39e | 7712 | used_at = 1; |
67c0d1eb RS |
7713 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7714 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7715 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7716 | } |
252b5132 RH |
7717 | break; |
7718 | ||
252b5132 RH |
7719 | case M_SEQ: |
7720 | if (sreg == 0) | |
67c0d1eb | 7721 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7722 | else if (treg == 0) |
67c0d1eb | 7723 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7724 | else |
7725 | { | |
67c0d1eb RS |
7726 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7727 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7728 | } |
8fc2e39e | 7729 | break; |
252b5132 RH |
7730 | |
7731 | case M_SEQ_I: | |
7732 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7733 | { | |
67c0d1eb | 7734 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7735 | break; |
252b5132 RH |
7736 | } |
7737 | if (sreg == 0) | |
7738 | { | |
7739 | as_warn (_("Instruction %s: result is always false"), | |
7740 | ip->insn_mo->name); | |
67c0d1eb | 7741 | move_register (dreg, 0); |
8fc2e39e | 7742 | break; |
252b5132 | 7743 | } |
dd3cbb7e NC |
7744 | if (CPU_HAS_SEQ (mips_opts.arch) |
7745 | && -512 <= imm_expr.X_add_number | |
7746 | && imm_expr.X_add_number < 512) | |
7747 | { | |
7748 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7749 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7750 | break; |
7751 | } | |
252b5132 RH |
7752 | if (imm_expr.X_op == O_constant |
7753 | && imm_expr.X_add_number >= 0 | |
7754 | && imm_expr.X_add_number < 0x10000) | |
7755 | { | |
67c0d1eb | 7756 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7757 | } |
7758 | else if (imm_expr.X_op == O_constant | |
7759 | && imm_expr.X_add_number > -0x8000 | |
7760 | && imm_expr.X_add_number < 0) | |
7761 | { | |
7762 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7763 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7764 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7765 | } |
dd3cbb7e NC |
7766 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7767 | { | |
7768 | used_at = 1; | |
7769 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7770 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
7771 | break; | |
7772 | } | |
252b5132 RH |
7773 | else |
7774 | { | |
67c0d1eb RS |
7775 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7776 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7777 | used_at = 1; |
7778 | } | |
67c0d1eb | 7779 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7780 | break; |
252b5132 RH |
7781 | |
7782 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7783 | s = "slt"; | |
7784 | goto sge; | |
7785 | case M_SGEU: | |
7786 | s = "sltu"; | |
7787 | sge: | |
67c0d1eb RS |
7788 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7789 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7790 | break; |
252b5132 RH |
7791 | |
7792 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7793 | case M_SGEU_I: | |
7794 | if (imm_expr.X_op == O_constant | |
7795 | && imm_expr.X_add_number >= -0x8000 | |
7796 | && imm_expr.X_add_number < 0x8000) | |
7797 | { | |
67c0d1eb RS |
7798 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7799 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7800 | } |
7801 | else | |
7802 | { | |
67c0d1eb RS |
7803 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7804 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7805 | dreg, sreg, AT); | |
252b5132 RH |
7806 | used_at = 1; |
7807 | } | |
67c0d1eb | 7808 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7809 | break; |
252b5132 RH |
7810 | |
7811 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7812 | s = "slt"; | |
7813 | goto sgt; | |
7814 | case M_SGTU: | |
7815 | s = "sltu"; | |
7816 | sgt: | |
67c0d1eb | 7817 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7818 | break; |
252b5132 RH |
7819 | |
7820 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7821 | s = "slt"; | |
7822 | goto sgti; | |
7823 | case M_SGTU_I: | |
7824 | s = "sltu"; | |
7825 | sgti: | |
8fc2e39e | 7826 | used_at = 1; |
67c0d1eb RS |
7827 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7828 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7829 | break; |
7830 | ||
2396cfb9 | 7831 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7832 | s = "slt"; |
7833 | goto sle; | |
7834 | case M_SLEU: | |
7835 | s = "sltu"; | |
7836 | sle: | |
67c0d1eb RS |
7837 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7838 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7839 | break; |
252b5132 | 7840 | |
2396cfb9 | 7841 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7842 | s = "slt"; |
7843 | goto slei; | |
7844 | case M_SLEU_I: | |
7845 | s = "sltu"; | |
7846 | slei: | |
8fc2e39e | 7847 | used_at = 1; |
67c0d1eb RS |
7848 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7849 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7850 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7851 | break; |
7852 | ||
7853 | case M_SLT_I: | |
7854 | if (imm_expr.X_op == O_constant | |
7855 | && imm_expr.X_add_number >= -0x8000 | |
7856 | && imm_expr.X_add_number < 0x8000) | |
7857 | { | |
67c0d1eb | 7858 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7859 | break; |
252b5132 | 7860 | } |
8fc2e39e | 7861 | used_at = 1; |
67c0d1eb RS |
7862 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7863 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7864 | break; |
7865 | ||
7866 | case M_SLTU_I: | |
7867 | if (imm_expr.X_op == O_constant | |
7868 | && imm_expr.X_add_number >= -0x8000 | |
7869 | && imm_expr.X_add_number < 0x8000) | |
7870 | { | |
67c0d1eb | 7871 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7872 | BFD_RELOC_LO16); |
8fc2e39e | 7873 | break; |
252b5132 | 7874 | } |
8fc2e39e | 7875 | used_at = 1; |
67c0d1eb RS |
7876 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7877 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7878 | break; |
7879 | ||
7880 | case M_SNE: | |
7881 | if (sreg == 0) | |
67c0d1eb | 7882 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7883 | else if (treg == 0) |
67c0d1eb | 7884 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7885 | else |
7886 | { | |
67c0d1eb RS |
7887 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7888 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7889 | } |
8fc2e39e | 7890 | break; |
252b5132 RH |
7891 | |
7892 | case M_SNE_I: | |
7893 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7894 | { | |
67c0d1eb | 7895 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7896 | break; |
252b5132 RH |
7897 | } |
7898 | if (sreg == 0) | |
7899 | { | |
7900 | as_warn (_("Instruction %s: result is always true"), | |
7901 | ip->insn_mo->name); | |
67c0d1eb RS |
7902 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7903 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7904 | break; |
252b5132 | 7905 | } |
dd3cbb7e NC |
7906 | if (CPU_HAS_SEQ (mips_opts.arch) |
7907 | && -512 <= imm_expr.X_add_number | |
7908 | && imm_expr.X_add_number < 512) | |
7909 | { | |
7910 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7911 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7912 | break; |
7913 | } | |
252b5132 RH |
7914 | if (imm_expr.X_op == O_constant |
7915 | && imm_expr.X_add_number >= 0 | |
7916 | && imm_expr.X_add_number < 0x10000) | |
7917 | { | |
67c0d1eb | 7918 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7919 | } |
7920 | else if (imm_expr.X_op == O_constant | |
7921 | && imm_expr.X_add_number > -0x8000 | |
7922 | && imm_expr.X_add_number < 0) | |
7923 | { | |
7924 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7925 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7926 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7927 | } |
dd3cbb7e NC |
7928 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7929 | { | |
7930 | used_at = 1; | |
7931 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7932 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
7933 | break; | |
7934 | } | |
252b5132 RH |
7935 | else |
7936 | { | |
67c0d1eb RS |
7937 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7938 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7939 | used_at = 1; |
7940 | } | |
67c0d1eb | 7941 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7942 | break; |
252b5132 RH |
7943 | |
7944 | case M_DSUB_I: | |
7945 | dbl = 1; | |
7946 | case M_SUB_I: | |
7947 | if (imm_expr.X_op == O_constant | |
7948 | && imm_expr.X_add_number > -0x8000 | |
7949 | && imm_expr.X_add_number <= 0x8000) | |
7950 | { | |
7951 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7952 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7953 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7954 | break; |
252b5132 | 7955 | } |
8fc2e39e | 7956 | used_at = 1; |
67c0d1eb RS |
7957 | load_register (AT, &imm_expr, dbl); |
7958 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7959 | break; |
7960 | ||
7961 | case M_DSUBU_I: | |
7962 | dbl = 1; | |
7963 | case M_SUBU_I: | |
7964 | if (imm_expr.X_op == O_constant | |
7965 | && imm_expr.X_add_number > -0x8000 | |
7966 | && imm_expr.X_add_number <= 0x8000) | |
7967 | { | |
7968 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7969 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7970 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7971 | break; |
252b5132 | 7972 | } |
8fc2e39e | 7973 | used_at = 1; |
67c0d1eb RS |
7974 | load_register (AT, &imm_expr, dbl); |
7975 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7976 | break; |
7977 | ||
7978 | case M_TEQ_I: | |
7979 | s = "teq"; | |
7980 | goto trap; | |
7981 | case M_TGE_I: | |
7982 | s = "tge"; | |
7983 | goto trap; | |
7984 | case M_TGEU_I: | |
7985 | s = "tgeu"; | |
7986 | goto trap; | |
7987 | case M_TLT_I: | |
7988 | s = "tlt"; | |
7989 | goto trap; | |
7990 | case M_TLTU_I: | |
7991 | s = "tltu"; | |
7992 | goto trap; | |
7993 | case M_TNE_I: | |
7994 | s = "tne"; | |
7995 | trap: | |
8fc2e39e | 7996 | used_at = 1; |
67c0d1eb RS |
7997 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7998 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7999 | break; |
8000 | ||
252b5132 | 8001 | case M_TRUNCWS: |
43841e91 | 8002 | case M_TRUNCWD: |
9c2799c2 | 8003 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 8004 | used_at = 1; |
252b5132 RH |
8005 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
8006 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
8007 | ||
8008 | /* | |
8009 | * Is the double cfc1 instruction a bug in the mips assembler; | |
8010 | * or is there a reason for it? | |
8011 | */ | |
7d10b47d | 8012 | start_noreorder (); |
67c0d1eb RS |
8013 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
8014 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
8015 | macro_build (NULL, "nop", ""); | |
252b5132 | 8016 | expr1.X_add_number = 3; |
67c0d1eb | 8017 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 8018 | expr1.X_add_number = 2; |
67c0d1eb RS |
8019 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
8020 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
8021 | macro_build (NULL, "nop", ""); | |
8022 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
8023 | dreg, sreg); | |
8024 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
8025 | macro_build (NULL, "nop", ""); | |
7d10b47d | 8026 | end_noreorder (); |
252b5132 RH |
8027 | break; |
8028 | ||
8029 | case M_ULH: | |
8030 | s = "lb"; | |
8031 | goto ulh; | |
8032 | case M_ULHU: | |
8033 | s = "lbu"; | |
8034 | ulh: | |
8fc2e39e | 8035 | used_at = 1; |
252b5132 | 8036 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8037 | as_bad (_("Operand overflow")); |
90ecf173 | 8038 | if (!target_big_endian) |
f9419b05 | 8039 | ++offset_expr.X_add_number; |
67c0d1eb | 8040 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
90ecf173 | 8041 | if (!target_big_endian) |
f9419b05 | 8042 | --offset_expr.X_add_number; |
252b5132 | 8043 | else |
f9419b05 | 8044 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8045 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8046 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
8047 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8048 | break; |
8049 | ||
8050 | case M_ULD: | |
8051 | s = "ldl"; | |
8052 | s2 = "ldr"; | |
8053 | off = 7; | |
8054 | goto ulw; | |
8055 | case M_ULW: | |
8056 | s = "lwl"; | |
8057 | s2 = "lwr"; | |
8058 | off = 3; | |
8059 | ulw: | |
8060 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8061 | as_bad (_("Operand overflow")); |
af22f5b2 CD |
8062 | if (treg != breg) |
8063 | tempreg = treg; | |
8064 | else | |
8fc2e39e TS |
8065 | { |
8066 | used_at = 1; | |
8067 | tempreg = AT; | |
8068 | } | |
90ecf173 | 8069 | if (!target_big_endian) |
252b5132 | 8070 | offset_expr.X_add_number += off; |
67c0d1eb | 8071 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
90ecf173 | 8072 | if (!target_big_endian) |
252b5132 RH |
8073 | offset_expr.X_add_number -= off; |
8074 | else | |
8075 | offset_expr.X_add_number += off; | |
67c0d1eb | 8076 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 | 8077 | |
90ecf173 | 8078 | /* If necessary, move the result in tempreg to the final destination. */ |
af22f5b2 | 8079 | if (treg == tempreg) |
8fc2e39e | 8080 | break; |
af22f5b2 | 8081 | /* Protect second load's delay slot. */ |
017315e4 | 8082 | load_delay_nop (); |
67c0d1eb | 8083 | move_register (treg, tempreg); |
af22f5b2 | 8084 | break; |
252b5132 RH |
8085 | |
8086 | case M_ULD_A: | |
8087 | s = "ldl"; | |
8088 | s2 = "ldr"; | |
8089 | off = 7; | |
8090 | goto ulwa; | |
8091 | case M_ULW_A: | |
8092 | s = "lwl"; | |
8093 | s2 = "lwr"; | |
8094 | off = 3; | |
8095 | ulwa: | |
d6bc6245 | 8096 | used_at = 1; |
67c0d1eb | 8097 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8098 | if (breg != 0) |
67c0d1eb | 8099 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8100 | if (!target_big_endian) |
252b5132 RH |
8101 | expr1.X_add_number = off; |
8102 | else | |
8103 | expr1.X_add_number = 0; | |
67c0d1eb | 8104 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8105 | if (!target_big_endian) |
252b5132 RH |
8106 | expr1.X_add_number = 0; |
8107 | else | |
8108 | expr1.X_add_number = off; | |
67c0d1eb | 8109 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8110 | break; |
8111 | ||
8112 | case M_ULH_A: | |
8113 | case M_ULHU_A: | |
d6bc6245 | 8114 | used_at = 1; |
67c0d1eb | 8115 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8116 | if (breg != 0) |
67c0d1eb | 8117 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8118 | if (target_big_endian) |
8119 | expr1.X_add_number = 0; | |
67c0d1eb | 8120 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 8121 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8122 | if (target_big_endian) |
8123 | expr1.X_add_number = 1; | |
8124 | else | |
8125 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8126 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8127 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8128 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8129 | break; |
8130 | ||
8131 | case M_USH: | |
8fc2e39e | 8132 | used_at = 1; |
252b5132 | 8133 | if (offset_expr.X_add_number >= 0x7fff) |
f71d0d44 | 8134 | as_bad (_("Operand overflow")); |
252b5132 | 8135 | if (target_big_endian) |
f9419b05 | 8136 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8137 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8138 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 8139 | if (target_big_endian) |
f9419b05 | 8140 | --offset_expr.X_add_number; |
252b5132 | 8141 | else |
f9419b05 | 8142 | ++offset_expr.X_add_number; |
67c0d1eb | 8143 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
8144 | break; |
8145 | ||
8146 | case M_USD: | |
8147 | s = "sdl"; | |
8148 | s2 = "sdr"; | |
8149 | off = 7; | |
8150 | goto usw; | |
8151 | case M_USW: | |
8152 | s = "swl"; | |
8153 | s2 = "swr"; | |
8154 | off = 3; | |
8155 | usw: | |
8156 | if (offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 8157 | as_bad (_("Operand overflow")); |
90ecf173 | 8158 | if (!target_big_endian) |
252b5132 | 8159 | offset_expr.X_add_number += off; |
67c0d1eb | 8160 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
90ecf173 | 8161 | if (!target_big_endian) |
252b5132 RH |
8162 | offset_expr.X_add_number -= off; |
8163 | else | |
8164 | offset_expr.X_add_number += off; | |
67c0d1eb | 8165 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 8166 | break; |
252b5132 RH |
8167 | |
8168 | case M_USD_A: | |
8169 | s = "sdl"; | |
8170 | s2 = "sdr"; | |
8171 | off = 7; | |
8172 | goto uswa; | |
8173 | case M_USW_A: | |
8174 | s = "swl"; | |
8175 | s2 = "swr"; | |
8176 | off = 3; | |
8177 | uswa: | |
d6bc6245 | 8178 | used_at = 1; |
67c0d1eb | 8179 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8180 | if (breg != 0) |
67c0d1eb | 8181 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8182 | if (!target_big_endian) |
252b5132 RH |
8183 | expr1.X_add_number = off; |
8184 | else | |
8185 | expr1.X_add_number = 0; | |
67c0d1eb | 8186 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8187 | if (!target_big_endian) |
252b5132 RH |
8188 | expr1.X_add_number = 0; |
8189 | else | |
8190 | expr1.X_add_number = off; | |
67c0d1eb | 8191 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8192 | break; |
8193 | ||
8194 | case M_USH_A: | |
d6bc6245 | 8195 | used_at = 1; |
67c0d1eb | 8196 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8197 | if (breg != 0) |
67c0d1eb | 8198 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
90ecf173 | 8199 | if (!target_big_endian) |
252b5132 | 8200 | expr1.X_add_number = 0; |
67c0d1eb RS |
8201 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8202 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
90ecf173 | 8203 | if (!target_big_endian) |
252b5132 RH |
8204 | expr1.X_add_number = 1; |
8205 | else | |
8206 | expr1.X_add_number = 0; | |
67c0d1eb | 8207 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
90ecf173 | 8208 | if (!target_big_endian) |
252b5132 RH |
8209 | expr1.X_add_number = 0; |
8210 | else | |
8211 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8212 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8213 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8214 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8215 | break; |
8216 | ||
8217 | default: | |
8218 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8219 | are added dynamically. */ |
252b5132 RH |
8220 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8221 | break; | |
8222 | } | |
741fe287 | 8223 | if (!mips_opts.at && used_at) |
8fc2e39e | 8224 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8225 | } |
8226 | ||
8227 | /* Implement macros in mips16 mode. */ | |
8228 | ||
8229 | static void | |
17a2f251 | 8230 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8231 | { |
8232 | int mask; | |
8233 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8234 | expressionS expr1; |
8235 | int dbl; | |
8236 | const char *s, *s2, *s3; | |
8237 | ||
8238 | mask = ip->insn_mo->mask; | |
8239 | ||
bf12938e RS |
8240 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8241 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8242 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8243 | |
252b5132 RH |
8244 | expr1.X_op = O_constant; |
8245 | expr1.X_op_symbol = NULL; | |
8246 | expr1.X_add_symbol = NULL; | |
8247 | expr1.X_add_number = 1; | |
8248 | ||
8249 | dbl = 0; | |
8250 | ||
8251 | switch (mask) | |
8252 | { | |
8253 | default: | |
8254 | internalError (); | |
8255 | ||
8256 | case M_DDIV_3: | |
8257 | dbl = 1; | |
8258 | case M_DIV_3: | |
8259 | s = "mflo"; | |
8260 | goto do_div3; | |
8261 | case M_DREM_3: | |
8262 | dbl = 1; | |
8263 | case M_REM_3: | |
8264 | s = "mfhi"; | |
8265 | do_div3: | |
7d10b47d | 8266 | start_noreorder (); |
67c0d1eb | 8267 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8268 | expr1.X_add_number = 2; |
67c0d1eb RS |
8269 | macro_build (&expr1, "bnez", "x,p", yreg); |
8270 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8271 | |
252b5132 RH |
8272 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8273 | since that causes an overflow. We should do that as well, | |
8274 | but I don't see how to do the comparisons without a temporary | |
8275 | register. */ | |
7d10b47d | 8276 | end_noreorder (); |
67c0d1eb | 8277 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8278 | break; |
8279 | ||
8280 | case M_DIVU_3: | |
8281 | s = "divu"; | |
8282 | s2 = "mflo"; | |
8283 | goto do_divu3; | |
8284 | case M_REMU_3: | |
8285 | s = "divu"; | |
8286 | s2 = "mfhi"; | |
8287 | goto do_divu3; | |
8288 | case M_DDIVU_3: | |
8289 | s = "ddivu"; | |
8290 | s2 = "mflo"; | |
8291 | goto do_divu3; | |
8292 | case M_DREMU_3: | |
8293 | s = "ddivu"; | |
8294 | s2 = "mfhi"; | |
8295 | do_divu3: | |
7d10b47d | 8296 | start_noreorder (); |
67c0d1eb | 8297 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8298 | expr1.X_add_number = 2; |
67c0d1eb RS |
8299 | macro_build (&expr1, "bnez", "x,p", yreg); |
8300 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8301 | end_noreorder (); |
67c0d1eb | 8302 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8303 | break; |
8304 | ||
8305 | case M_DMUL: | |
8306 | dbl = 1; | |
8307 | case M_MUL: | |
67c0d1eb RS |
8308 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8309 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8310 | break; |
252b5132 RH |
8311 | |
8312 | case M_DSUBU_I: | |
8313 | dbl = 1; | |
8314 | goto do_subu; | |
8315 | case M_SUBU_I: | |
8316 | do_subu: | |
8317 | if (imm_expr.X_op != O_constant) | |
8318 | as_bad (_("Unsupported large constant")); | |
8319 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8320 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8321 | break; |
8322 | ||
8323 | case M_SUBU_I_2: | |
8324 | if (imm_expr.X_op != O_constant) | |
8325 | as_bad (_("Unsupported large constant")); | |
8326 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8327 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8328 | break; |
8329 | ||
8330 | case M_DSUBU_I_2: | |
8331 | if (imm_expr.X_op != O_constant) | |
8332 | as_bad (_("Unsupported large constant")); | |
8333 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8334 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8335 | break; |
8336 | ||
8337 | case M_BEQ: | |
8338 | s = "cmp"; | |
8339 | s2 = "bteqz"; | |
8340 | goto do_branch; | |
8341 | case M_BNE: | |
8342 | s = "cmp"; | |
8343 | s2 = "btnez"; | |
8344 | goto do_branch; | |
8345 | case M_BLT: | |
8346 | s = "slt"; | |
8347 | s2 = "btnez"; | |
8348 | goto do_branch; | |
8349 | case M_BLTU: | |
8350 | s = "sltu"; | |
8351 | s2 = "btnez"; | |
8352 | goto do_branch; | |
8353 | case M_BLE: | |
8354 | s = "slt"; | |
8355 | s2 = "bteqz"; | |
8356 | goto do_reverse_branch; | |
8357 | case M_BLEU: | |
8358 | s = "sltu"; | |
8359 | s2 = "bteqz"; | |
8360 | goto do_reverse_branch; | |
8361 | case M_BGE: | |
8362 | s = "slt"; | |
8363 | s2 = "bteqz"; | |
8364 | goto do_branch; | |
8365 | case M_BGEU: | |
8366 | s = "sltu"; | |
8367 | s2 = "bteqz"; | |
8368 | goto do_branch; | |
8369 | case M_BGT: | |
8370 | s = "slt"; | |
8371 | s2 = "btnez"; | |
8372 | goto do_reverse_branch; | |
8373 | case M_BGTU: | |
8374 | s = "sltu"; | |
8375 | s2 = "btnez"; | |
8376 | ||
8377 | do_reverse_branch: | |
8378 | tmp = xreg; | |
8379 | xreg = yreg; | |
8380 | yreg = tmp; | |
8381 | ||
8382 | do_branch: | |
67c0d1eb RS |
8383 | macro_build (NULL, s, "x,y", xreg, yreg); |
8384 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8385 | break; |
8386 | ||
8387 | case M_BEQ_I: | |
8388 | s = "cmpi"; | |
8389 | s2 = "bteqz"; | |
8390 | s3 = "x,U"; | |
8391 | goto do_branch_i; | |
8392 | case M_BNE_I: | |
8393 | s = "cmpi"; | |
8394 | s2 = "btnez"; | |
8395 | s3 = "x,U"; | |
8396 | goto do_branch_i; | |
8397 | case M_BLT_I: | |
8398 | s = "slti"; | |
8399 | s2 = "btnez"; | |
8400 | s3 = "x,8"; | |
8401 | goto do_branch_i; | |
8402 | case M_BLTU_I: | |
8403 | s = "sltiu"; | |
8404 | s2 = "btnez"; | |
8405 | s3 = "x,8"; | |
8406 | goto do_branch_i; | |
8407 | case M_BLE_I: | |
8408 | s = "slti"; | |
8409 | s2 = "btnez"; | |
8410 | s3 = "x,8"; | |
8411 | goto do_addone_branch_i; | |
8412 | case M_BLEU_I: | |
8413 | s = "sltiu"; | |
8414 | s2 = "btnez"; | |
8415 | s3 = "x,8"; | |
8416 | goto do_addone_branch_i; | |
8417 | case M_BGE_I: | |
8418 | s = "slti"; | |
8419 | s2 = "bteqz"; | |
8420 | s3 = "x,8"; | |
8421 | goto do_branch_i; | |
8422 | case M_BGEU_I: | |
8423 | s = "sltiu"; | |
8424 | s2 = "bteqz"; | |
8425 | s3 = "x,8"; | |
8426 | goto do_branch_i; | |
8427 | case M_BGT_I: | |
8428 | s = "slti"; | |
8429 | s2 = "bteqz"; | |
8430 | s3 = "x,8"; | |
8431 | goto do_addone_branch_i; | |
8432 | case M_BGTU_I: | |
8433 | s = "sltiu"; | |
8434 | s2 = "bteqz"; | |
8435 | s3 = "x,8"; | |
8436 | ||
8437 | do_addone_branch_i: | |
8438 | if (imm_expr.X_op != O_constant) | |
8439 | as_bad (_("Unsupported large constant")); | |
8440 | ++imm_expr.X_add_number; | |
8441 | ||
8442 | do_branch_i: | |
67c0d1eb RS |
8443 | macro_build (&imm_expr, s, s3, xreg); |
8444 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8445 | break; |
8446 | ||
8447 | case M_ABS: | |
8448 | expr1.X_add_number = 0; | |
67c0d1eb | 8449 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8450 | if (xreg != yreg) |
67c0d1eb | 8451 | move_register (xreg, yreg); |
252b5132 | 8452 | expr1.X_add_number = 2; |
67c0d1eb RS |
8453 | macro_build (&expr1, "bteqz", "p"); |
8454 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8455 | } |
8456 | } | |
8457 | ||
8458 | /* For consistency checking, verify that all bits are specified either | |
8459 | by the match/mask part of the instruction definition, or by the | |
8460 | operand list. */ | |
8461 | static int | |
17a2f251 | 8462 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8463 | { |
8464 | const char *p = opc->args; | |
8465 | char c; | |
8466 | unsigned long used_bits = opc->mask; | |
8467 | ||
8468 | if ((used_bits & opc->match) != opc->match) | |
8469 | { | |
8470 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8471 | opc->name, opc->args); | |
8472 | return 0; | |
8473 | } | |
8474 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8475 | while (*p) | |
8476 | switch (c = *p++) | |
8477 | { | |
8478 | case ',': break; | |
8479 | case '(': break; | |
8480 | case ')': break; | |
af7ee8bf CD |
8481 | case '+': |
8482 | switch (c = *p++) | |
8483 | { | |
9bcd4f99 TS |
8484 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8485 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8486 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8487 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8488 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8489 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8490 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8491 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8492 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8493 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8494 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8495 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8496 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8497 | case 'I': break; | |
ef2e4d86 CF |
8498 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8499 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8500 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8501 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8502 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8503 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8504 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8505 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8506 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8507 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
8508 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
8509 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
8510 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
8511 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
8512 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 8513 | |
af7ee8bf CD |
8514 | default: |
8515 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8516 | c, opc->name, opc->args); | |
8517 | return 0; | |
8518 | } | |
8519 | break; | |
252b5132 RH |
8520 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8521 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8522 | case 'A': break; | |
4372b673 | 8523 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8524 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8525 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8526 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8527 | case 'F': break; | |
8528 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8529 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8530 | case 'I': break; |
e972090a | 8531 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8532 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8533 | case 'L': break; |
8534 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8535 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8536 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8537 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8538 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8539 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8540 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8541 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8542 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8543 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8544 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8545 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8546 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8547 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8548 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8549 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8550 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8551 | case 'f': break; | |
8552 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8553 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8554 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8555 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8556 | case 'l': break; | |
8557 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8558 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8559 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8560 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8561 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8562 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8563 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8564 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8565 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8566 | case 'x': break; | |
8567 | case 'z': break; | |
8568 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8569 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8570 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8571 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8572 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8573 | case '[': break; | |
8574 | case ']': break; | |
620edafd | 8575 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 8576 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8577 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8578 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8579 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8580 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8581 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8582 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8583 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8584 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8585 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8586 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8587 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8588 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8589 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8590 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8591 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8592 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8593 | default: |
8594 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8595 | c, opc->name, opc->args); | |
8596 | return 0; | |
8597 | } | |
8598 | #undef USE_BITS | |
8599 | if (used_bits != 0xffffffff) | |
8600 | { | |
8601 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8602 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8603 | return 0; | |
8604 | } | |
8605 | return 1; | |
8606 | } | |
8607 | ||
9bcd4f99 TS |
8608 | /* UDI immediates. */ |
8609 | struct mips_immed { | |
8610 | char type; | |
8611 | unsigned int shift; | |
8612 | unsigned long mask; | |
8613 | const char * desc; | |
8614 | }; | |
8615 | ||
8616 | static const struct mips_immed mips_immed[] = { | |
8617 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8618 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8619 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8620 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8621 | { 0,0,0,0 } | |
8622 | }; | |
8623 | ||
7455baf8 TS |
8624 | /* Check whether an odd floating-point register is allowed. */ |
8625 | static int | |
8626 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8627 | { | |
8628 | const char *s = insn->name; | |
8629 | ||
8630 | if (insn->pinfo == INSN_MACRO) | |
8631 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8632 | return 1; | |
8633 | ||
8634 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8635 | { | |
8636 | /* Allow odd registers for single-precision ops. */ | |
8637 | switch (insn->pinfo & (FP_S | FP_D)) | |
8638 | { | |
8639 | case FP_S: | |
8640 | case 0: | |
8641 | return 1; /* both single precision - ok */ | |
8642 | case FP_D: | |
8643 | return 0; /* both double precision - fail */ | |
8644 | default: | |
8645 | break; | |
8646 | } | |
8647 | ||
8648 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8649 | s = strchr (insn->name, '.'); | |
8650 | if (argnum == 2) | |
8651 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8652 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8653 | } | |
8654 | ||
8655 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8656 | if ((insn->pinfo & FP_S) | |
8657 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8658 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8659 | return 1; | |
8660 | ||
8661 | return 0; | |
8662 | } | |
8663 | ||
252b5132 RH |
8664 | /* This routine assembles an instruction into its binary format. As a |
8665 | side effect, it sets one of the global variables imm_reloc or | |
8666 | offset_reloc to the type of relocation to do if one of the operands | |
8667 | is an address expression. */ | |
8668 | ||
8669 | static void | |
17a2f251 | 8670 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8671 | { |
8672 | char *s; | |
8673 | const char *args; | |
43841e91 | 8674 | char c = 0; |
252b5132 RH |
8675 | struct mips_opcode *insn; |
8676 | char *argsStart; | |
8677 | unsigned int regno; | |
34224acf | 8678 | unsigned int lastregno; |
af7ee8bf | 8679 | unsigned int lastpos = 0; |
071742cf | 8680 | unsigned int limlo, limhi; |
252b5132 RH |
8681 | char *s_reset; |
8682 | char save_c = 0; | |
74cd071d | 8683 | offsetT min_range, max_range; |
707bfff6 TS |
8684 | int argnum; |
8685 | unsigned int rtype; | |
252b5132 RH |
8686 | |
8687 | insn_error = NULL; | |
8688 | ||
8689 | /* If the instruction contains a '.', we first try to match an instruction | |
8690 | including the '.'. Then we try again without the '.'. */ | |
8691 | insn = NULL; | |
3882b010 | 8692 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8693 | continue; |
8694 | ||
8695 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8696 | the call to hash_find. Save the character we replaced just in case we | |
8697 | have to re-parse the instruction. */ | |
3882b010 | 8698 | if (ISSPACE (*s)) |
252b5132 RH |
8699 | { |
8700 | save_c = *s; | |
8701 | *s++ = '\0'; | |
8702 | } | |
bdaaa2e1 | 8703 | |
252b5132 RH |
8704 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8705 | ||
8706 | /* If we didn't find the instruction in the opcode table, try again, but | |
8707 | this time with just the instruction up to, but not including the | |
8708 | first '.'. */ | |
8709 | if (insn == NULL) | |
8710 | { | |
bdaaa2e1 | 8711 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8712 | if (save_c) |
8713 | *(--s) = save_c; | |
8714 | ||
8715 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8716 | for (s = str; |
8717 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8718 | ++s) | |
252b5132 RH |
8719 | continue; |
8720 | ||
8721 | /* If we did not find a '.', then we can quit now. */ | |
8722 | if (*s != '.') | |
8723 | { | |
f71d0d44 | 8724 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8725 | return; |
8726 | } | |
8727 | ||
8728 | /* Lookup the instruction in the hash table. */ | |
8729 | *s++ = '\0'; | |
8730 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8731 | { | |
f71d0d44 | 8732 | insn_error = _("Unrecognized opcode"); |
252b5132 RH |
8733 | return; |
8734 | } | |
252b5132 RH |
8735 | } |
8736 | ||
8737 | argsStart = s; | |
8738 | for (;;) | |
8739 | { | |
b34976b6 | 8740 | bfd_boolean ok; |
252b5132 | 8741 | |
9c2799c2 | 8742 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 8743 | |
f79e2745 | 8744 | ok = is_opcode_valid (insn); |
252b5132 RH |
8745 | if (! ok) |
8746 | { | |
8747 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8748 | && strcmp (insn->name, insn[1].name) == 0) | |
8749 | { | |
8750 | ++insn; | |
8751 | continue; | |
8752 | } | |
252b5132 | 8753 | else |
beae10d5 | 8754 | { |
268f6bed L |
8755 | if (!insn_error) |
8756 | { | |
8757 | static char buf[100]; | |
fef14a42 TS |
8758 | sprintf (buf, |
8759 | _("opcode not supported on this processor: %s (%s)"), | |
8760 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8761 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8762 | insn_error = buf; |
8763 | } | |
8764 | if (save_c) | |
8765 | *(--s) = save_c; | |
2bd7f1f3 | 8766 | return; |
252b5132 | 8767 | } |
252b5132 RH |
8768 | } |
8769 | ||
1e915849 | 8770 | create_insn (ip, insn); |
268f6bed | 8771 | insn_error = NULL; |
707bfff6 | 8772 | argnum = 1; |
24864476 | 8773 | lastregno = 0xffffffff; |
252b5132 RH |
8774 | for (args = insn->args;; ++args) |
8775 | { | |
deec1734 CD |
8776 | int is_mdmx; |
8777 | ||
ad8d3bb3 | 8778 | s += strspn (s, " \t"); |
deec1734 | 8779 | is_mdmx = 0; |
252b5132 RH |
8780 | switch (*args) |
8781 | { | |
8782 | case '\0': /* end of args */ | |
8783 | if (*s == '\0') | |
8784 | return; | |
8785 | break; | |
8786 | ||
90ecf173 | 8787 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
8b082fb1 TS |
8788 | my_getExpression (&imm_expr, s); |
8789 | check_absolute_expr (ip, &imm_expr); | |
8790 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8791 | && (unsigned long) imm_expr.X_add_number != 3) | |
8792 | { | |
8793 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8794 | (unsigned long) imm_expr.X_add_number); | |
8795 | } | |
8796 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8797 | imm_expr.X_op = O_absent; | |
8798 | s = expr_end; | |
8799 | continue; | |
8800 | ||
90ecf173 | 8801 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8802 | my_getExpression (&imm_expr, s); |
8803 | check_absolute_expr (ip, &imm_expr); | |
8804 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8805 | { | |
a9e24354 TS |
8806 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8807 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8808 | } |
a9e24354 | 8809 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8810 | imm_expr.X_op = O_absent; |
8811 | s = expr_end; | |
8812 | continue; | |
8813 | ||
90ecf173 | 8814 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8815 | my_getExpression (&imm_expr, s); |
8816 | check_absolute_expr (ip, &imm_expr); | |
8817 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8818 | { | |
a9e24354 TS |
8819 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8820 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8821 | } |
a9e24354 | 8822 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8823 | imm_expr.X_op = O_absent; |
8824 | s = expr_end; | |
8825 | continue; | |
8826 | ||
90ecf173 | 8827 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
74cd071d CF |
8828 | my_getExpression (&imm_expr, s); |
8829 | check_absolute_expr (ip, &imm_expr); | |
8830 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8831 | { | |
a9e24354 TS |
8832 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8833 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8834 | } |
a9e24354 | 8835 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8836 | imm_expr.X_op = O_absent; |
8837 | s = expr_end; | |
8838 | continue; | |
8839 | ||
90ecf173 | 8840 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
74cd071d CF |
8841 | my_getExpression (&imm_expr, s); |
8842 | check_absolute_expr (ip, &imm_expr); | |
8843 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8844 | { | |
a9e24354 TS |
8845 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8846 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8847 | } |
a9e24354 | 8848 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8849 | imm_expr.X_op = O_absent; |
8850 | s = expr_end; | |
8851 | continue; | |
8852 | ||
90ecf173 | 8853 | case '7': /* Four DSP accumulators in bits 11,12. */ |
74cd071d CF |
8854 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8855 | s[3] >= '0' && s[3] <= '3') | |
8856 | { | |
8857 | regno = s[3] - '0'; | |
8858 | s += 4; | |
a9e24354 | 8859 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8860 | continue; |
8861 | } | |
8862 | else | |
8863 | as_bad (_("Invalid dsp acc register")); | |
8864 | break; | |
8865 | ||
90ecf173 | 8866 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
74cd071d CF |
8867 | my_getExpression (&imm_expr, s); |
8868 | check_absolute_expr (ip, &imm_expr); | |
8869 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8870 | { | |
a9e24354 TS |
8871 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8872 | OP_MASK_WRDSP, | |
8873 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8874 | } |
a9e24354 | 8875 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8876 | imm_expr.X_op = O_absent; |
8877 | s = expr_end; | |
8878 | continue; | |
8879 | ||
90ecf173 | 8880 | case '9': /* Four DSP accumulators in bits 21,22. */ |
74cd071d CF |
8881 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8882 | s[3] >= '0' && s[3] <= '3') | |
8883 | { | |
8884 | regno = s[3] - '0'; | |
8885 | s += 4; | |
a9e24354 | 8886 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8887 | continue; |
8888 | } | |
8889 | else | |
8890 | as_bad (_("Invalid dsp acc register")); | |
8891 | break; | |
8892 | ||
90ecf173 | 8893 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
74cd071d CF |
8894 | my_getExpression (&imm_expr, s); |
8895 | check_absolute_expr (ip, &imm_expr); | |
8896 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8897 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8898 | if (imm_expr.X_add_number < min_range || | |
8899 | imm_expr.X_add_number > max_range) | |
8900 | { | |
a9e24354 TS |
8901 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8902 | (long) min_range, (long) max_range, | |
8903 | (long) imm_expr.X_add_number); | |
74cd071d | 8904 | } |
a9e24354 | 8905 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8906 | imm_expr.X_op = O_absent; |
8907 | s = expr_end; | |
8908 | continue; | |
8909 | ||
90ecf173 | 8910 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
74cd071d CF |
8911 | my_getExpression (&imm_expr, s); |
8912 | check_absolute_expr (ip, &imm_expr); | |
8913 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8914 | { | |
a9e24354 TS |
8915 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8916 | OP_MASK_RDDSP, | |
8917 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8918 | } |
a9e24354 | 8919 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8920 | imm_expr.X_op = O_absent; |
8921 | s = expr_end; | |
8922 | continue; | |
8923 | ||
90ecf173 | 8924 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
74cd071d CF |
8925 | my_getExpression (&imm_expr, s); |
8926 | check_absolute_expr (ip, &imm_expr); | |
8927 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8928 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8929 | if (imm_expr.X_add_number < min_range || | |
8930 | imm_expr.X_add_number > max_range) | |
8931 | { | |
a9e24354 TS |
8932 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8933 | (long) min_range, (long) max_range, | |
8934 | (long) imm_expr.X_add_number); | |
74cd071d | 8935 | } |
a9e24354 | 8936 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8937 | imm_expr.X_op = O_absent; |
8938 | s = expr_end; | |
8939 | continue; | |
8940 | ||
90ecf173 | 8941 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
74cd071d CF |
8942 | my_getExpression (&imm_expr, s); |
8943 | check_absolute_expr (ip, &imm_expr); | |
8944 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8945 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8946 | if (imm_expr.X_add_number < min_range || | |
8947 | imm_expr.X_add_number > max_range) | |
8948 | { | |
a9e24354 TS |
8949 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8950 | (long) min_range, (long) max_range, | |
8951 | (long) imm_expr.X_add_number); | |
74cd071d | 8952 | } |
a9e24354 | 8953 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8954 | imm_expr.X_op = O_absent; |
8955 | s = expr_end; | |
8956 | continue; | |
8957 | ||
a9e24354 | 8958 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8959 | my_getExpression (&imm_expr, s); |
8960 | check_absolute_expr (ip, &imm_expr); | |
8961 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8962 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8963 | (unsigned long) imm_expr.X_add_number); | |
8964 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8965 | imm_expr.X_op = O_absent; |
8966 | s = expr_end; | |
8967 | continue; | |
8968 | ||
a9e24354 | 8969 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8970 | my_getExpression (&imm_expr, s); |
8971 | check_absolute_expr (ip, &imm_expr); | |
8972 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8973 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8974 | (unsigned long) imm_expr.X_add_number); | |
8975 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8976 | imm_expr.X_op = O_absent; |
8977 | s = expr_end; | |
8978 | continue; | |
8979 | ||
90ecf173 | 8980 | case '*': /* Four DSP accumulators in bits 18,19. */ |
ef2e4d86 CF |
8981 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8982 | s[3] >= '0' && s[3] <= '3') | |
8983 | { | |
8984 | regno = s[3] - '0'; | |
8985 | s += 4; | |
a9e24354 | 8986 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8987 | continue; |
8988 | } | |
8989 | else | |
8990 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8991 | break; | |
8992 | ||
90ecf173 | 8993 | case '&': /* Four DSP accumulators in bits 13,14. */ |
ef2e4d86 CF |
8994 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
8995 | s[3] >= '0' && s[3] <= '3') | |
8996 | { | |
8997 | regno = s[3] - '0'; | |
8998 | s += 4; | |
a9e24354 | 8999 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
9000 | continue; |
9001 | } | |
9002 | else | |
9003 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9004 | break; | |
9005 | ||
252b5132 | 9006 | case ',': |
a339155f | 9007 | ++argnum; |
252b5132 RH |
9008 | if (*s++ == *args) |
9009 | continue; | |
9010 | s--; | |
9011 | switch (*++args) | |
9012 | { | |
9013 | case 'r': | |
9014 | case 'v': | |
bf12938e | 9015 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9016 | continue; |
9017 | ||
9018 | case 'w': | |
bf12938e | 9019 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
9020 | continue; |
9021 | ||
252b5132 | 9022 | case 'W': |
bf12938e | 9023 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9024 | continue; |
9025 | ||
9026 | case 'V': | |
bf12938e | 9027 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9028 | continue; |
9029 | } | |
9030 | break; | |
9031 | ||
9032 | case '(': | |
9033 | /* Handle optional base register. | |
9034 | Either the base register is omitted or | |
bdaaa2e1 | 9035 | we must have a left paren. */ |
252b5132 RH |
9036 | /* This is dependent on the next operand specifier |
9037 | is a base register specification. */ | |
f9bbfb18 | 9038 | gas_assert (args[1] == 'b'); |
252b5132 RH |
9039 | if (*s == '\0') |
9040 | return; | |
9041 | ||
90ecf173 | 9042 | case ')': /* These must match exactly. */ |
60b63b72 RS |
9043 | case '[': |
9044 | case ']': | |
252b5132 RH |
9045 | if (*s++ == *args) |
9046 | continue; | |
9047 | break; | |
9048 | ||
af7ee8bf CD |
9049 | case '+': /* Opcode extension character. */ |
9050 | switch (*++args) | |
9051 | { | |
9bcd4f99 TS |
9052 | case '1': /* UDI immediates. */ |
9053 | case '2': | |
9054 | case '3': | |
9055 | case '4': | |
9056 | { | |
9057 | const struct mips_immed *imm = mips_immed; | |
9058 | ||
9059 | while (imm->type && imm->type != *args) | |
9060 | ++imm; | |
9061 | if (! imm->type) | |
9062 | internalError (); | |
9063 | my_getExpression (&imm_expr, s); | |
9064 | check_absolute_expr (ip, &imm_expr); | |
9065 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
9066 | { | |
9067 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
9068 | imm->desc ? imm->desc : ip->insn_mo->name, | |
9069 | (unsigned long) imm_expr.X_add_number, | |
9070 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 9071 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
9072 | } |
9073 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
9074 | << imm->shift); | |
9075 | imm_expr.X_op = O_absent; | |
9076 | s = expr_end; | |
9077 | } | |
9078 | continue; | |
90ecf173 | 9079 | |
071742cf CD |
9080 | case 'A': /* ins/ext position, becomes LSB. */ |
9081 | limlo = 0; | |
9082 | limhi = 31; | |
5f74bc13 CD |
9083 | goto do_lsb; |
9084 | case 'E': | |
9085 | limlo = 32; | |
9086 | limhi = 63; | |
9087 | goto do_lsb; | |
90ecf173 | 9088 | do_lsb: |
071742cf CD |
9089 | my_getExpression (&imm_expr, s); |
9090 | check_absolute_expr (ip, &imm_expr); | |
9091 | if ((unsigned long) imm_expr.X_add_number < limlo | |
9092 | || (unsigned long) imm_expr.X_add_number > limhi) | |
9093 | { | |
9094 | as_bad (_("Improper position (%lu)"), | |
9095 | (unsigned long) imm_expr.X_add_number); | |
9096 | imm_expr.X_add_number = limlo; | |
9097 | } | |
9098 | lastpos = imm_expr.X_add_number; | |
bf12938e | 9099 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
9100 | imm_expr.X_op = O_absent; |
9101 | s = expr_end; | |
9102 | continue; | |
9103 | ||
9104 | case 'B': /* ins size, becomes MSB. */ | |
9105 | limlo = 1; | |
9106 | limhi = 32; | |
5f74bc13 CD |
9107 | goto do_msb; |
9108 | case 'F': | |
9109 | limlo = 33; | |
9110 | limhi = 64; | |
9111 | goto do_msb; | |
90ecf173 | 9112 | do_msb: |
071742cf CD |
9113 | my_getExpression (&imm_expr, s); |
9114 | check_absolute_expr (ip, &imm_expr); | |
9115 | /* Check for negative input so that small negative numbers | |
9116 | will not succeed incorrectly. The checks against | |
9117 | (pos+size) transitively check "size" itself, | |
9118 | assuming that "pos" is reasonable. */ | |
9119 | if ((long) imm_expr.X_add_number < 0 | |
9120 | || ((unsigned long) imm_expr.X_add_number | |
9121 | + lastpos) < limlo | |
9122 | || ((unsigned long) imm_expr.X_add_number | |
9123 | + lastpos) > limhi) | |
9124 | { | |
9125 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
9126 | (unsigned long) imm_expr.X_add_number, | |
9127 | (unsigned long) lastpos); | |
9128 | imm_expr.X_add_number = limlo - lastpos; | |
9129 | } | |
bf12938e RS |
9130 | INSERT_OPERAND (INSMSB, *ip, |
9131 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
9132 | imm_expr.X_op = O_absent; |
9133 | s = expr_end; | |
9134 | continue; | |
9135 | ||
9136 | case 'C': /* ext size, becomes MSBD. */ | |
9137 | limlo = 1; | |
9138 | limhi = 32; | |
5f74bc13 CD |
9139 | goto do_msbd; |
9140 | case 'G': | |
9141 | limlo = 33; | |
9142 | limhi = 64; | |
9143 | goto do_msbd; | |
9144 | case 'H': | |
9145 | limlo = 33; | |
9146 | limhi = 64; | |
9147 | goto do_msbd; | |
90ecf173 | 9148 | do_msbd: |
071742cf CD |
9149 | my_getExpression (&imm_expr, s); |
9150 | check_absolute_expr (ip, &imm_expr); | |
9151 | /* Check for negative input so that small negative numbers | |
9152 | will not succeed incorrectly. The checks against | |
9153 | (pos+size) transitively check "size" itself, | |
9154 | assuming that "pos" is reasonable. */ | |
9155 | if ((long) imm_expr.X_add_number < 0 | |
9156 | || ((unsigned long) imm_expr.X_add_number | |
9157 | + lastpos) < limlo | |
9158 | || ((unsigned long) imm_expr.X_add_number | |
9159 | + lastpos) > limhi) | |
9160 | { | |
9161 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
9162 | (unsigned long) imm_expr.X_add_number, | |
9163 | (unsigned long) lastpos); | |
9164 | imm_expr.X_add_number = limlo - lastpos; | |
9165 | } | |
bf12938e | 9166 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
9167 | imm_expr.X_op = O_absent; |
9168 | s = expr_end; | |
9169 | continue; | |
af7ee8bf | 9170 | |
bbcc0807 CD |
9171 | case 'D': |
9172 | /* +D is for disassembly only; never match. */ | |
9173 | break; | |
9174 | ||
5f74bc13 CD |
9175 | case 'I': |
9176 | /* "+I" is like "I", except that imm2_expr is used. */ | |
9177 | my_getExpression (&imm2_expr, s); | |
9178 | if (imm2_expr.X_op != O_big | |
9179 | && imm2_expr.X_op != O_constant) | |
9180 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9181 | if (HAVE_32BIT_GPRS) |
9182 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
9183 | s = expr_end; |
9184 | continue; | |
9185 | ||
707bfff6 | 9186 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
9187 | /* +T is for disassembly only; never match. */ |
9188 | break; | |
9189 | ||
707bfff6 | 9190 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
9191 | if (s[0] == '$' && ISDIGIT (s[1])) |
9192 | { | |
9193 | ++s; | |
9194 | regno = 0; | |
9195 | do | |
9196 | { | |
9197 | regno *= 10; | |
9198 | regno += *s - '0'; | |
9199 | ++s; | |
9200 | } | |
9201 | while (ISDIGIT (*s)); | |
9202 | if (regno > 31) | |
9203 | as_bad (_("Invalid register number (%d)"), regno); | |
9204 | else | |
9205 | { | |
a9e24354 | 9206 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9207 | continue; |
9208 | } | |
9209 | } | |
9210 | else | |
9211 | as_bad (_("Invalid coprocessor 0 register number")); | |
9212 | break; | |
9213 | ||
bb35fb24 NC |
9214 | case 'x': |
9215 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9216 | is not in the valid range. */ | |
9217 | my_getExpression (&imm_expr, s); | |
9218 | check_absolute_expr (ip, &imm_expr); | |
9219 | if ((unsigned) imm_expr.X_add_number > 31) | |
9220 | { | |
9221 | as_bad (_("Improper bit index (%lu)"), | |
9222 | (unsigned long) imm_expr.X_add_number); | |
9223 | imm_expr.X_add_number = 0; | |
9224 | } | |
9225 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9226 | imm_expr.X_op = O_absent; | |
9227 | s = expr_end; | |
9228 | continue; | |
9229 | ||
9230 | case 'X': | |
9231 | /* bbit[01] bit index when bbit is used but we generate | |
9232 | bbit[01]32 because the index is over 32. Move to the | |
9233 | next candidate if index is not in the valid range. */ | |
9234 | my_getExpression (&imm_expr, s); | |
9235 | check_absolute_expr (ip, &imm_expr); | |
9236 | if ((unsigned) imm_expr.X_add_number < 32 | |
9237 | || (unsigned) imm_expr.X_add_number > 63) | |
9238 | break; | |
9239 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9240 | imm_expr.X_op = O_absent; | |
9241 | s = expr_end; | |
9242 | continue; | |
9243 | ||
9244 | case 'p': | |
9245 | /* cins, cins32, exts and exts32 position field. Give error | |
9246 | if it's not in the valid range. */ | |
9247 | my_getExpression (&imm_expr, s); | |
9248 | check_absolute_expr (ip, &imm_expr); | |
9249 | if ((unsigned) imm_expr.X_add_number > 31) | |
9250 | { | |
9251 | as_bad (_("Improper position (%lu)"), | |
9252 | (unsigned long) imm_expr.X_add_number); | |
9253 | imm_expr.X_add_number = 0; | |
9254 | } | |
9255 | /* Make the pos explicit to simplify +S. */ | |
9256 | lastpos = imm_expr.X_add_number + 32; | |
9257 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9258 | imm_expr.X_op = O_absent; | |
9259 | s = expr_end; | |
9260 | continue; | |
9261 | ||
9262 | case 'P': | |
9263 | /* cins, cins32, exts and exts32 position field. Move to | |
9264 | the next candidate if it's not in the valid range. */ | |
9265 | my_getExpression (&imm_expr, s); | |
9266 | check_absolute_expr (ip, &imm_expr); | |
9267 | if ((unsigned) imm_expr.X_add_number < 32 | |
9268 | || (unsigned) imm_expr.X_add_number > 63) | |
9269 | break; | |
9270 | lastpos = imm_expr.X_add_number; | |
9271 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9272 | imm_expr.X_op = O_absent; | |
9273 | s = expr_end; | |
9274 | continue; | |
9275 | ||
9276 | case 's': | |
9277 | /* cins and exts length-minus-one field. */ | |
9278 | my_getExpression (&imm_expr, s); | |
9279 | check_absolute_expr (ip, &imm_expr); | |
9280 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9281 | { | |
9282 | as_bad (_("Improper size (%lu)"), | |
9283 | (unsigned long) imm_expr.X_add_number); | |
9284 | imm_expr.X_add_number = 0; | |
9285 | } | |
9286 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9287 | imm_expr.X_op = O_absent; | |
9288 | s = expr_end; | |
9289 | continue; | |
9290 | ||
9291 | case 'S': | |
9292 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9293 | length-minus-one field. */ | |
9294 | my_getExpression (&imm_expr, s); | |
9295 | check_absolute_expr (ip, &imm_expr); | |
9296 | if ((long) imm_expr.X_add_number < 0 | |
9297 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9298 | { | |
9299 | as_bad (_("Improper size (%lu)"), | |
9300 | (unsigned long) imm_expr.X_add_number); | |
9301 | imm_expr.X_add_number = 0; | |
9302 | } | |
9303 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9304 | imm_expr.X_op = O_absent; | |
9305 | s = expr_end; | |
9306 | continue; | |
9307 | ||
dd3cbb7e NC |
9308 | case 'Q': |
9309 | /* seqi/snei immediate field. */ | |
9310 | my_getExpression (&imm_expr, s); | |
9311 | check_absolute_expr (ip, &imm_expr); | |
9312 | if ((long) imm_expr.X_add_number < -512 | |
9313 | || (long) imm_expr.X_add_number >= 512) | |
9314 | { | |
9315 | as_bad (_("Improper immediate (%ld)"), | |
9316 | (long) imm_expr.X_add_number); | |
9317 | imm_expr.X_add_number = 0; | |
9318 | } | |
9319 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9320 | imm_expr.X_op = O_absent; | |
9321 | s = expr_end; | |
9322 | continue; | |
9323 | ||
98675402 RS |
9324 | case 'a': /* 8-bit signed offset in bit 6 */ |
9325 | my_getExpression (&imm_expr, s); | |
9326 | check_absolute_expr (ip, &imm_expr); | |
9327 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
9328 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
9329 | if (imm_expr.X_add_number < min_range | |
9330 | || imm_expr.X_add_number > max_range) | |
9331 | { | |
c95354ed | 9332 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9333 | (long) min_range, (long) max_range, |
9334 | (long) imm_expr.X_add_number); | |
9335 | } | |
9336 | INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number); | |
9337 | imm_expr.X_op = O_absent; | |
9338 | s = expr_end; | |
9339 | continue; | |
9340 | ||
9341 | case 'b': /* 8-bit signed offset in bit 3 */ | |
9342 | my_getExpression (&imm_expr, s); | |
9343 | check_absolute_expr (ip, &imm_expr); | |
9344 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
9345 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
9346 | if (imm_expr.X_add_number < min_range | |
9347 | || imm_expr.X_add_number > max_range) | |
9348 | { | |
c95354ed | 9349 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9350 | (long) min_range, (long) max_range, |
9351 | (long) imm_expr.X_add_number); | |
9352 | } | |
9353 | INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number); | |
9354 | imm_expr.X_op = O_absent; | |
9355 | s = expr_end; | |
9356 | continue; | |
9357 | ||
9358 | case 'c': /* 9-bit signed offset in bit 6 */ | |
9359 | my_getExpression (&imm_expr, s); | |
9360 | check_absolute_expr (ip, &imm_expr); | |
9361 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
9362 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
9363 | /* We check the offset range before adjusted. */ |
9364 | min_range <<= 4; | |
9365 | max_range <<= 4; | |
98675402 RS |
9366 | if (imm_expr.X_add_number < min_range |
9367 | || imm_expr.X_add_number > max_range) | |
9368 | { | |
c95354ed | 9369 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
9370 | (long) min_range, (long) max_range, |
9371 | (long) imm_expr.X_add_number); | |
9372 | } | |
c95354ed MX |
9373 | if (imm_expr.X_add_number & 0xf) |
9374 | { | |
9375 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
9376 | (long) imm_expr.X_add_number); | |
9377 | } | |
9378 | /* Right shift 4 bits to adjust the offset operand. */ | |
9379 | INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4); | |
98675402 RS |
9380 | imm_expr.X_op = O_absent; |
9381 | s = expr_end; | |
9382 | continue; | |
9383 | ||
9384 | case 'z': | |
9385 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
9386 | break; | |
9387 | if (regno == AT && mips_opts.at) | |
9388 | { | |
9389 | if (mips_opts.at == ATREG) | |
9390 | as_warn (_("used $at without \".set noat\"")); | |
9391 | else | |
9392 | as_warn (_("used $%u with \".set at=$%u\""), | |
9393 | regno, mips_opts.at); | |
9394 | } | |
9395 | INSERT_OPERAND (RZ, *ip, regno); | |
9396 | continue; | |
9397 | ||
9398 | case 'Z': | |
9399 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) | |
9400 | break; | |
9401 | INSERT_OPERAND (FZ, *ip, regno); | |
9402 | continue; | |
9403 | ||
af7ee8bf | 9404 | default: |
f71d0d44 | 9405 | as_bad (_("Internal error: bad mips opcode " |
90ecf173 MR |
9406 | "(unknown extension operand type `+%c'): %s %s"), |
9407 | *args, insn->name, insn->args); | |
af7ee8bf CD |
9408 | /* Further processing is fruitless. */ |
9409 | return; | |
9410 | } | |
9411 | break; | |
9412 | ||
252b5132 RH |
9413 | case '<': /* must be at least one digit */ |
9414 | /* | |
9415 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9416 | * than 31 or less than 0, then the shift amount should be |
9417 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9418 | * We issue a warning and mask out all but the low 5 bits. |
9419 | */ | |
9420 | my_getExpression (&imm_expr, s); | |
9421 | check_absolute_expr (ip, &imm_expr); | |
9422 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9423 | as_warn (_("Improper shift amount (%lu)"), |
9424 | (unsigned long) imm_expr.X_add_number); | |
9425 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9426 | imm_expr.X_op = O_absent; |
9427 | s = expr_end; | |
9428 | continue; | |
9429 | ||
9430 | case '>': /* shift amount minus 32 */ | |
9431 | my_getExpression (&imm_expr, s); | |
9432 | check_absolute_expr (ip, &imm_expr); | |
9433 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9434 | || (unsigned long) imm_expr.X_add_number > 63) | |
9435 | break; | |
bf12938e | 9436 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9437 | imm_expr.X_op = O_absent; |
9438 | s = expr_end; | |
9439 | continue; | |
9440 | ||
90ecf173 MR |
9441 | case 'k': /* CACHE code. */ |
9442 | case 'h': /* PREFX code. */ | |
9443 | case '1': /* SYNC type. */ | |
252b5132 RH |
9444 | my_getExpression (&imm_expr, s); |
9445 | check_absolute_expr (ip, &imm_expr); | |
9446 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9447 | as_warn (_("Invalid value for `%s' (%lu)"), |
9448 | ip->insn_mo->name, | |
9449 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9450 | if (*args == 'k') |
d954098f DD |
9451 | { |
9452 | if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0) | |
9453 | switch (imm_expr.X_add_number) | |
9454 | { | |
9455 | case 5: | |
9456 | case 25: | |
9457 | case 26: | |
9458 | case 27: | |
9459 | case 28: | |
9460 | case 29: | |
9461 | case 30: | |
9462 | case 31: /* These are ok. */ | |
9463 | break; | |
9464 | ||
9465 | default: /* The rest must be changed to 28. */ | |
9466 | imm_expr.X_add_number = 28; | |
9467 | break; | |
9468 | } | |
9469 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); | |
9470 | } | |
620edafd | 9471 | else if (*args == 'h') |
bf12938e | 9472 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
620edafd CF |
9473 | else |
9474 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9475 | imm_expr.X_op = O_absent; |
9476 | s = expr_end; | |
9477 | continue; | |
9478 | ||
90ecf173 | 9479 | case 'c': /* BREAK code. */ |
252b5132 RH |
9480 | my_getExpression (&imm_expr, s); |
9481 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9482 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9483 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9484 | ip->insn_mo->name, | |
bf12938e RS |
9485 | (unsigned long) imm_expr.X_add_number); |
9486 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9487 | imm_expr.X_op = O_absent; |
9488 | s = expr_end; | |
9489 | continue; | |
9490 | ||
90ecf173 | 9491 | case 'q': /* Lower BREAK code. */ |
252b5132 RH |
9492 | my_getExpression (&imm_expr, s); |
9493 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9494 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9495 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9496 | ip->insn_mo->name, | |
bf12938e RS |
9497 | (unsigned long) imm_expr.X_add_number); |
9498 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9499 | imm_expr.X_op = O_absent; |
9500 | s = expr_end; | |
9501 | continue; | |
9502 | ||
90ecf173 | 9503 | case 'B': /* 20-bit SYSCALL/BREAK code. */ |
156c2f8b | 9504 | my_getExpression (&imm_expr, s); |
156c2f8b | 9505 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9506 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9507 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9508 | ip->insn_mo->name, | |
793b27f4 | 9509 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9510 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9511 | imm_expr.X_op = O_absent; |
9512 | s = expr_end; | |
9513 | continue; | |
9514 | ||
90ecf173 | 9515 | case 'C': /* Coprocessor code. */ |
beae10d5 | 9516 | my_getExpression (&imm_expr, s); |
252b5132 | 9517 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9518 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9519 | { |
793b27f4 TS |
9520 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9521 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9522 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9523 | } |
a9e24354 | 9524 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9525 | imm_expr.X_op = O_absent; |
9526 | s = expr_end; | |
9527 | continue; | |
252b5132 | 9528 | |
90ecf173 | 9529 | case 'J': /* 19-bit WAIT code. */ |
4372b673 NC |
9530 | my_getExpression (&imm_expr, s); |
9531 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9532 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9533 | { |
9534 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9535 | (unsigned long) imm_expr.X_add_number); | |
9536 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9537 | } | |
bf12938e | 9538 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9539 | imm_expr.X_op = O_absent; |
9540 | s = expr_end; | |
9541 | continue; | |
9542 | ||
707bfff6 | 9543 | case 'P': /* Performance register. */ |
beae10d5 | 9544 | my_getExpression (&imm_expr, s); |
252b5132 | 9545 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9546 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9547 | as_warn (_("Invalid performance register (%lu)"), |
9548 | (unsigned long) imm_expr.X_add_number); | |
9549 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9550 | imm_expr.X_op = O_absent; |
9551 | s = expr_end; | |
9552 | continue; | |
252b5132 | 9553 | |
707bfff6 TS |
9554 | case 'G': /* Coprocessor destination register. */ |
9555 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9556 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9557 | else | |
9558 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9559 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9560 | if (ok) |
9561 | { | |
9562 | lastregno = regno; | |
9563 | continue; | |
9564 | } | |
9565 | else | |
9566 | break; | |
9567 | ||
90ecf173 MR |
9568 | case 'b': /* Base register. */ |
9569 | case 'd': /* Destination register. */ | |
9570 | case 's': /* Source register. */ | |
9571 | case 't': /* Target register. */ | |
9572 | case 'r': /* Both target and source. */ | |
9573 | case 'v': /* Both dest and source. */ | |
9574 | case 'w': /* Both dest and target. */ | |
9575 | case 'E': /* Coprocessor target register. */ | |
9576 | case 'K': /* RDHWR destination register. */ | |
9577 | case 'x': /* Ignore register name. */ | |
9578 | case 'z': /* Must be zero register. */ | |
9579 | case 'U': /* Destination register (CLO/CLZ). */ | |
9580 | case 'g': /* Coprocessor destination register. */ | |
9581 | s_reset = s; | |
707bfff6 TS |
9582 | if (*args == 'E' || *args == 'K') |
9583 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9584 | else | |
9585 | { | |
9586 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9587 | if (regno == AT && mips_opts.at) |
9588 | { | |
9589 | if (mips_opts.at == ATREG) | |
f71d0d44 | 9590 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 9591 | else |
f71d0d44 | 9592 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
9593 | regno, mips_opts.at); |
9594 | } | |
707bfff6 TS |
9595 | } |
9596 | if (ok) | |
252b5132 | 9597 | { |
252b5132 RH |
9598 | c = *args; |
9599 | if (*s == ' ') | |
f9419b05 | 9600 | ++s; |
252b5132 RH |
9601 | if (args[1] != *s) |
9602 | { | |
9603 | if (c == 'r' || c == 'v' || c == 'w') | |
9604 | { | |
9605 | regno = lastregno; | |
9606 | s = s_reset; | |
f9419b05 | 9607 | ++args; |
252b5132 RH |
9608 | } |
9609 | } | |
9610 | /* 'z' only matches $0. */ | |
9611 | if (c == 'z' && regno != 0) | |
9612 | break; | |
9613 | ||
24864476 | 9614 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
9615 | { |
9616 | if (regno == lastregno) | |
90ecf173 MR |
9617 | { |
9618 | insn_error | |
f71d0d44 | 9619 | = _("Source and destination must be different"); |
e7c604dd | 9620 | continue; |
90ecf173 | 9621 | } |
24864476 | 9622 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
9623 | { |
9624 | insn_error | |
f71d0d44 | 9625 | = _("A destination register must be supplied"); |
e7c604dd | 9626 | continue; |
90ecf173 | 9627 | } |
e7c604dd | 9628 | } |
90ecf173 MR |
9629 | /* Now that we have assembled one operand, we use the args |
9630 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
9631 | switch (c) |
9632 | { | |
9633 | case 'r': | |
9634 | case 's': | |
9635 | case 'v': | |
9636 | case 'b': | |
bf12938e | 9637 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9638 | break; |
9639 | case 'd': | |
af7ee8bf | 9640 | case 'K': |
ef2e4d86 | 9641 | case 'g': |
bf12938e | 9642 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9643 | break; |
4372b673 | 9644 | case 'U': |
bf12938e RS |
9645 | INSERT_OPERAND (RD, *ip, regno); |
9646 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9647 | break; |
252b5132 RH |
9648 | case 'w': |
9649 | case 't': | |
9650 | case 'E': | |
bf12938e | 9651 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9652 | break; |
9653 | case 'x': | |
9654 | /* This case exists because on the r3000 trunc | |
9655 | expands into a macro which requires a gp | |
9656 | register. On the r6000 or r4000 it is | |
9657 | assembled into a single instruction which | |
9658 | ignores the register. Thus the insn version | |
9659 | is MIPS_ISA2 and uses 'x', and the macro | |
9660 | version is MIPS_ISA1 and uses 't'. */ | |
9661 | break; | |
9662 | case 'z': | |
9663 | /* This case is for the div instruction, which | |
9664 | acts differently if the destination argument | |
9665 | is $0. This only matches $0, and is checked | |
9666 | outside the switch. */ | |
9667 | break; | |
252b5132 RH |
9668 | } |
9669 | lastregno = regno; | |
9670 | continue; | |
9671 | } | |
252b5132 RH |
9672 | switch (*args++) |
9673 | { | |
9674 | case 'r': | |
9675 | case 'v': | |
bf12938e | 9676 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9677 | continue; |
9678 | case 'w': | |
bf12938e | 9679 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9680 | continue; |
9681 | } | |
9682 | break; | |
9683 | ||
deec1734 CD |
9684 | case 'O': /* MDMX alignment immediate constant. */ |
9685 | my_getExpression (&imm_expr, s); | |
9686 | check_absolute_expr (ip, &imm_expr); | |
9687 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 9688 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e RS |
9689 | (long) imm_expr.X_add_number); |
9690 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9691 | imm_expr.X_op = O_absent; |
9692 | s = expr_end; | |
9693 | continue; | |
9694 | ||
9695 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9696 | if (s[0] != '$') | |
9697 | { | |
9698 | /* MDMX Immediate. */ | |
9699 | my_getExpression (&imm_expr, s); | |
9700 | check_absolute_expr (ip, &imm_expr); | |
9701 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9702 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9703 | (long) imm_expr.X_add_number); | |
9704 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9705 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9706 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9707 | else | |
9708 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9709 | imm_expr.X_op = O_absent; |
9710 | s = expr_end; | |
9711 | continue; | |
9712 | } | |
9713 | /* Not MDMX Immediate. Fall through. */ | |
9714 | case 'X': /* MDMX destination register. */ | |
9715 | case 'Y': /* MDMX source register. */ | |
9716 | case 'Z': /* MDMX target register. */ | |
9717 | is_mdmx = 1; | |
90ecf173 MR |
9718 | case 'D': /* Floating point destination register. */ |
9719 | case 'S': /* Floating point source register. */ | |
9720 | case 'T': /* Floating point target register. */ | |
9721 | case 'R': /* Floating point source register. */ | |
252b5132 RH |
9722 | case 'V': |
9723 | case 'W': | |
707bfff6 TS |
9724 | rtype = RTYPE_FPU; |
9725 | if (is_mdmx | |
9726 | || (mips_opts.ase_mdmx | |
9727 | && (ip->insn_mo->pinfo & FP_D) | |
9728 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9729 | | INSN_COPROC_MEMORY_DELAY | |
9730 | | INSN_LOAD_COPROC_DELAY | |
9731 | | INSN_LOAD_MEMORY_DELAY | |
9732 | | INSN_STORE_MEMORY)))) | |
9733 | rtype |= RTYPE_VEC; | |
252b5132 | 9734 | s_reset = s; |
707bfff6 | 9735 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9736 | { |
252b5132 | 9737 | if ((regno & 1) != 0 |
ca4e0257 | 9738 | && HAVE_32BIT_FPRS |
90ecf173 | 9739 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9740 | as_warn (_("Float register should be even, was %d"), |
9741 | regno); | |
9742 | ||
9743 | c = *args; | |
9744 | if (*s == ' ') | |
f9419b05 | 9745 | ++s; |
252b5132 RH |
9746 | if (args[1] != *s) |
9747 | { | |
9748 | if (c == 'V' || c == 'W') | |
9749 | { | |
9750 | regno = lastregno; | |
9751 | s = s_reset; | |
f9419b05 | 9752 | ++args; |
252b5132 RH |
9753 | } |
9754 | } | |
9755 | switch (c) | |
9756 | { | |
9757 | case 'D': | |
deec1734 | 9758 | case 'X': |
bf12938e | 9759 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9760 | break; |
9761 | case 'V': | |
9762 | case 'S': | |
deec1734 | 9763 | case 'Y': |
bf12938e | 9764 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9765 | break; |
deec1734 CD |
9766 | case 'Q': |
9767 | /* This is like 'Z', but also needs to fix the MDMX | |
9768 | vector/scalar select bits. Note that the | |
9769 | scalar immediate case is handled above. */ | |
9770 | if (*s == '[') | |
9771 | { | |
9772 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9773 | int max_el = (is_qh ? 3 : 7); | |
9774 | s++; | |
9775 | my_getExpression(&imm_expr, s); | |
9776 | check_absolute_expr (ip, &imm_expr); | |
9777 | s = expr_end; | |
9778 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
9779 | as_bad (_("Bad element selector %ld"), |
9780 | (long) imm_expr.X_add_number); | |
deec1734 CD |
9781 | imm_expr.X_add_number &= max_el; |
9782 | ip->insn_opcode |= (imm_expr.X_add_number | |
9783 | << (OP_SH_VSEL + | |
9784 | (is_qh ? 2 : 1))); | |
01a3f561 | 9785 | imm_expr.X_op = O_absent; |
deec1734 | 9786 | if (*s != ']') |
20203fb9 | 9787 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
9788 | else |
9789 | s++; | |
9790 | } | |
9791 | else | |
9792 | { | |
9793 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9794 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9795 | << OP_SH_VSEL); | |
9796 | else | |
9797 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9798 | OP_SH_VSEL); | |
9799 | } | |
90ecf173 | 9800 | /* Fall through. */ |
252b5132 RH |
9801 | case 'W': |
9802 | case 'T': | |
deec1734 | 9803 | case 'Z': |
bf12938e | 9804 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9805 | break; |
9806 | case 'R': | |
bf12938e | 9807 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9808 | break; |
9809 | } | |
9810 | lastregno = regno; | |
9811 | continue; | |
9812 | } | |
9813 | ||
252b5132 RH |
9814 | switch (*args++) |
9815 | { | |
9816 | case 'V': | |
bf12938e | 9817 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9818 | continue; |
9819 | case 'W': | |
bf12938e | 9820 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9821 | continue; |
9822 | } | |
9823 | break; | |
9824 | ||
9825 | case 'I': | |
9826 | my_getExpression (&imm_expr, s); | |
9827 | if (imm_expr.X_op != O_big | |
9828 | && imm_expr.X_op != O_constant) | |
9829 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9830 | if (HAVE_32BIT_GPRS) |
9831 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9832 | s = expr_end; |
9833 | continue; | |
9834 | ||
9835 | case 'A': | |
9836 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9837 | normalize_address_expr (&offset_expr); |
f6688943 | 9838 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9839 | s = expr_end; |
9840 | continue; | |
9841 | ||
9842 | case 'F': | |
9843 | case 'L': | |
9844 | case 'f': | |
9845 | case 'l': | |
9846 | { | |
9847 | int f64; | |
ca4e0257 | 9848 | int using_gprs; |
252b5132 RH |
9849 | char *save_in; |
9850 | char *err; | |
9851 | unsigned char temp[8]; | |
9852 | int len; | |
9853 | unsigned int length; | |
9854 | segT seg; | |
9855 | subsegT subseg; | |
9856 | char *p; | |
9857 | ||
9858 | /* These only appear as the last operand in an | |
9859 | instruction, and every instruction that accepts | |
9860 | them in any variant accepts them in all variants. | |
9861 | This means we don't have to worry about backing out | |
9862 | any changes if the instruction does not match. | |
9863 | ||
9864 | The difference between them is the size of the | |
9865 | floating point constant and where it goes. For 'F' | |
9866 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9867 | is 32 bits. Where the constant is placed is based | |
9868 | on how the MIPS assembler does things: | |
9869 | F -- .rdata | |
9870 | L -- .lit8 | |
9871 | f -- immediate value | |
9872 | l -- .lit4 | |
9873 | ||
9874 | The .lit4 and .lit8 sections are only used if | |
9875 | permitted by the -G argument. | |
9876 | ||
ca4e0257 RS |
9877 | The code below needs to know whether the target register |
9878 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9879 | 'F' are used with GPR-based instructions and 'l' and | |
9880 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9881 | |
9882 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9883 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9884 | |
9885 | save_in = input_line_pointer; | |
9886 | input_line_pointer = s; | |
9887 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9888 | length = len; | |
9889 | s = input_line_pointer; | |
9890 | input_line_pointer = save_in; | |
9891 | if (err != NULL && *err != '\0') | |
9892 | { | |
9893 | as_bad (_("Bad floating point constant: %s"), err); | |
9894 | memset (temp, '\0', sizeof temp); | |
9895 | length = f64 ? 8 : 4; | |
9896 | } | |
9897 | ||
9c2799c2 | 9898 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9899 | |
9900 | if (*args == 'f' | |
9901 | || (*args == 'l' | |
3e722fb5 | 9902 | && (g_switch_value < 4 |
252b5132 RH |
9903 | || (temp[0] == 0 && temp[1] == 0) |
9904 | || (temp[2] == 0 && temp[3] == 0)))) | |
9905 | { | |
9906 | imm_expr.X_op = O_constant; | |
90ecf173 | 9907 | if (!target_big_endian) |
252b5132 RH |
9908 | imm_expr.X_add_number = bfd_getl32 (temp); |
9909 | else | |
9910 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9911 | } | |
9912 | else if (length > 4 | |
90ecf173 | 9913 | && !mips_disable_float_construction |
ca4e0257 RS |
9914 | /* Constants can only be constructed in GPRs and |
9915 | copied to FPRs if the GPRs are at least as wide | |
9916 | as the FPRs. Force the constant into memory if | |
9917 | we are using 64-bit FPRs but the GPRs are only | |
9918 | 32 bits wide. */ | |
9919 | && (using_gprs | |
90ecf173 | 9920 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
9921 | && ((temp[0] == 0 && temp[1] == 0) |
9922 | || (temp[2] == 0 && temp[3] == 0)) | |
9923 | && ((temp[4] == 0 && temp[5] == 0) | |
9924 | || (temp[6] == 0 && temp[7] == 0))) | |
9925 | { | |
ca4e0257 | 9926 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
9927 | instructions. If using 32-bit registers, set |
9928 | imm_expr to the high order 32 bits and offset_expr to | |
9929 | the low order 32 bits. Otherwise, set imm_expr to | |
9930 | the entire 64 bit constant. */ | |
ca4e0257 | 9931 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
9932 | { |
9933 | imm_expr.X_op = O_constant; | |
9934 | offset_expr.X_op = O_constant; | |
90ecf173 | 9935 | if (!target_big_endian) |
252b5132 RH |
9936 | { |
9937 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9938 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9939 | } | |
9940 | else | |
9941 | { | |
9942 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9943 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9944 | } | |
9945 | if (offset_expr.X_add_number == 0) | |
9946 | offset_expr.X_op = O_absent; | |
9947 | } | |
9948 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9949 | { | |
9950 | imm_expr.X_op = O_constant; | |
90ecf173 | 9951 | if (!target_big_endian) |
252b5132 RH |
9952 | imm_expr.X_add_number = bfd_getl64 (temp); |
9953 | else | |
9954 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9955 | } | |
9956 | else | |
9957 | { | |
9958 | imm_expr.X_op = O_big; | |
9959 | imm_expr.X_add_number = 4; | |
90ecf173 | 9960 | if (!target_big_endian) |
252b5132 RH |
9961 | { |
9962 | generic_bignum[0] = bfd_getl16 (temp); | |
9963 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9964 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9965 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9966 | } | |
9967 | else | |
9968 | { | |
9969 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9970 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9971 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9972 | generic_bignum[3] = bfd_getb16 (temp); | |
9973 | } | |
9974 | } | |
9975 | } | |
9976 | else | |
9977 | { | |
9978 | const char *newname; | |
9979 | segT new_seg; | |
9980 | ||
9981 | /* Switch to the right section. */ | |
9982 | seg = now_seg; | |
9983 | subseg = now_subseg; | |
9984 | switch (*args) | |
9985 | { | |
9986 | default: /* unused default case avoids warnings. */ | |
9987 | case 'L': | |
9988 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9989 | if (g_switch_value >= 8) |
252b5132 RH |
9990 | newname = ".lit8"; |
9991 | break; | |
9992 | case 'F': | |
3e722fb5 | 9993 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9994 | break; |
9995 | case 'l': | |
9c2799c2 | 9996 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
9997 | newname = ".lit4"; |
9998 | break; | |
9999 | } | |
10000 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 10001 | if (IS_ELF) |
252b5132 RH |
10002 | bfd_set_section_flags (stdoutput, new_seg, |
10003 | (SEC_ALLOC | |
10004 | | SEC_LOAD | |
10005 | | SEC_READONLY | |
10006 | | SEC_DATA)); | |
10007 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 10008 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
10009 | record_alignment (new_seg, 4); |
10010 | else | |
10011 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
10012 | if (seg == now_seg) | |
10013 | as_bad (_("Can't use floating point insn in this section")); | |
10014 | ||
10015 | /* Set the argument to the current address in the | |
10016 | section. */ | |
10017 | offset_expr.X_op = O_symbol; | |
8680f6e1 | 10018 | offset_expr.X_add_symbol = symbol_temp_new_now (); |
252b5132 RH |
10019 | offset_expr.X_add_number = 0; |
10020 | ||
10021 | /* Put the floating point number into the section. */ | |
10022 | p = frag_more ((int) length); | |
10023 | memcpy (p, temp, length); | |
10024 | ||
10025 | /* Switch back to the original section. */ | |
10026 | subseg_set (seg, subseg); | |
10027 | } | |
10028 | } | |
10029 | continue; | |
10030 | ||
90ecf173 MR |
10031 | case 'i': /* 16-bit unsigned immediate. */ |
10032 | case 'j': /* 16-bit signed immediate. */ | |
f6688943 | 10033 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 10034 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
10035 | { |
10036 | int more; | |
5e0116d5 RS |
10037 | offsetT minval, maxval; |
10038 | ||
10039 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
10040 | && strcmp (insn->name, insn[1].name) == 0); | |
10041 | ||
10042 | /* If the expression was written as an unsigned number, | |
10043 | only treat it as signed if there are no more | |
10044 | alternatives. */ | |
10045 | if (more | |
10046 | && *args == 'j' | |
10047 | && sizeof (imm_expr.X_add_number) <= 4 | |
10048 | && imm_expr.X_op == O_constant | |
10049 | && imm_expr.X_add_number < 0 | |
10050 | && imm_expr.X_unsigned | |
10051 | && HAVE_64BIT_GPRS) | |
10052 | break; | |
10053 | ||
10054 | /* For compatibility with older assemblers, we accept | |
10055 | 0x8000-0xffff as signed 16-bit numbers when only | |
10056 | signed numbers are allowed. */ | |
10057 | if (*args == 'i') | |
10058 | minval = 0, maxval = 0xffff; | |
10059 | else if (more) | |
10060 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 10061 | else |
5e0116d5 RS |
10062 | minval = -0x8000, maxval = 0xffff; |
10063 | ||
10064 | if (imm_expr.X_op != O_constant | |
10065 | || imm_expr.X_add_number < minval | |
10066 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
10067 | { |
10068 | if (more) | |
10069 | break; | |
2ae7e77b AH |
10070 | if (imm_expr.X_op == O_constant |
10071 | || imm_expr.X_op == O_big) | |
f71d0d44 | 10072 | as_bad (_("Expression out of range")); |
252b5132 RH |
10073 | } |
10074 | } | |
10075 | s = expr_end; | |
10076 | continue; | |
10077 | ||
90ecf173 | 10078 | case 'o': /* 16-bit offset. */ |
4614d845 MR |
10079 | offset_reloc[0] = BFD_RELOC_LO16; |
10080 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10081 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
10082 | ||
5e0116d5 RS |
10083 | /* Check whether there is only a single bracketed expression |
10084 | left. If so, it must be the base register and the | |
10085 | constant must be zero. */ | |
10086 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
10087 | { | |
10088 | offset_expr.X_op = O_constant; | |
10089 | offset_expr.X_add_number = 0; | |
10090 | continue; | |
10091 | } | |
252b5132 RH |
10092 | |
10093 | /* If this value won't fit into a 16 bit offset, then go | |
10094 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 10095 | code pattern. */ |
5e0116d5 | 10096 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
10097 | && (offset_expr.X_op != O_constant |
10098 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 10099 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
10100 | break; |
10101 | ||
252b5132 RH |
10102 | s = expr_end; |
10103 | continue; | |
10104 | ||
90ecf173 | 10105 | case 'p': /* PC-relative offset. */ |
0b25d3e6 | 10106 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
10107 | my_getExpression (&offset_expr, s); |
10108 | s = expr_end; | |
10109 | continue; | |
10110 | ||
90ecf173 | 10111 | case 'u': /* Upper 16 bits. */ |
5e0116d5 RS |
10112 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
10113 | && imm_expr.X_op == O_constant | |
10114 | && (imm_expr.X_add_number < 0 | |
10115 | || imm_expr.X_add_number >= 0x10000)) | |
88320db2 MR |
10116 | as_bad (_("lui expression (%lu) not in range 0..65535"), |
10117 | (unsigned long) imm_expr.X_add_number); | |
252b5132 RH |
10118 | s = expr_end; |
10119 | continue; | |
10120 | ||
90ecf173 | 10121 | case 'a': /* 26-bit address. */ |
252b5132 RH |
10122 | my_getExpression (&offset_expr, s); |
10123 | s = expr_end; | |
f6688943 | 10124 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
10125 | continue; |
10126 | ||
90ecf173 MR |
10127 | case 'N': /* 3-bit branch condition code. */ |
10128 | case 'M': /* 3-bit compare condition code. */ | |
707bfff6 | 10129 | rtype = RTYPE_CCC; |
90ecf173 | 10130 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) |
707bfff6 TS |
10131 | rtype |= RTYPE_FCC; |
10132 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 10133 | break; |
90ecf173 MR |
10134 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 |
10135 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
10136 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
30c378fd | 10137 | && (regno & 1) != 0) |
90ecf173 MR |
10138 | as_warn (_("Condition code register should be even for %s, " |
10139 | "was %d"), | |
20203fb9 | 10140 | str, regno); |
90ecf173 MR |
10141 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 |
10142 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
30c378fd | 10143 | && (regno & 3) != 0) |
90ecf173 MR |
10144 | as_warn (_("Condition code register should be 0 or 4 for %s, " |
10145 | "was %d"), | |
20203fb9 | 10146 | str, regno); |
252b5132 | 10147 | if (*args == 'N') |
bf12938e | 10148 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 10149 | else |
bf12938e | 10150 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 10151 | continue; |
252b5132 | 10152 | |
156c2f8b NC |
10153 | case 'H': |
10154 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
10155 | s += 2; | |
3882b010 | 10156 | if (ISDIGIT (*s)) |
156c2f8b NC |
10157 | { |
10158 | c = 0; | |
10159 | do | |
10160 | { | |
10161 | c *= 10; | |
10162 | c += *s - '0'; | |
10163 | ++s; | |
10164 | } | |
3882b010 | 10165 | while (ISDIGIT (*s)); |
156c2f8b NC |
10166 | } |
10167 | else | |
10168 | c = 8; /* Invalid sel value. */ | |
10169 | ||
10170 | if (c > 7) | |
f71d0d44 | 10171 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); |
156c2f8b NC |
10172 | ip->insn_opcode |= c; |
10173 | continue; | |
10174 | ||
60b63b72 RS |
10175 | case 'e': |
10176 | /* Must be at least one digit. */ | |
10177 | my_getExpression (&imm_expr, s); | |
10178 | check_absolute_expr (ip, &imm_expr); | |
10179 | ||
10180 | if ((unsigned long) imm_expr.X_add_number | |
10181 | > (unsigned long) OP_MASK_VECBYTE) | |
10182 | { | |
10183 | as_bad (_("bad byte vector index (%ld)"), | |
10184 | (long) imm_expr.X_add_number); | |
10185 | imm_expr.X_add_number = 0; | |
10186 | } | |
10187 | ||
bf12938e | 10188 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10189 | imm_expr.X_op = O_absent; |
10190 | s = expr_end; | |
10191 | continue; | |
10192 | ||
10193 | case '%': | |
10194 | my_getExpression (&imm_expr, s); | |
10195 | check_absolute_expr (ip, &imm_expr); | |
10196 | ||
10197 | if ((unsigned long) imm_expr.X_add_number | |
10198 | > (unsigned long) OP_MASK_VECALIGN) | |
10199 | { | |
10200 | as_bad (_("bad byte vector index (%ld)"), | |
10201 | (long) imm_expr.X_add_number); | |
10202 | imm_expr.X_add_number = 0; | |
10203 | } | |
10204 | ||
bf12938e | 10205 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10206 | imm_expr.X_op = O_absent; |
10207 | s = expr_end; | |
10208 | continue; | |
10209 | ||
252b5132 | 10210 | default: |
f71d0d44 | 10211 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
10212 | internalError (); |
10213 | } | |
10214 | break; | |
10215 | } | |
10216 | /* Args don't match. */ | |
10217 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
10218 | !strcmp (insn->name, insn[1].name)) | |
10219 | { | |
10220 | ++insn; | |
10221 | s = argsStart; | |
f71d0d44 | 10222 | insn_error = _("Illegal operands"); |
252b5132 RH |
10223 | continue; |
10224 | } | |
268f6bed | 10225 | if (save_c) |
570de991 | 10226 | *(--argsStart) = save_c; |
f71d0d44 | 10227 | insn_error = _("Illegal operands"); |
252b5132 RH |
10228 | return; |
10229 | } | |
10230 | } | |
10231 | ||
0499d65b TS |
10232 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
10233 | ||
252b5132 RH |
10234 | /* This routine assembles an instruction into its binary format when |
10235 | assembling for the mips16. As a side effect, it sets one of the | |
10236 | global variables imm_reloc or offset_reloc to the type of | |
10237 | relocation to do if one of the operands is an address expression. | |
10238 | It also sets mips16_small and mips16_ext if the user explicitly | |
10239 | requested a small or extended instruction. */ | |
10240 | ||
10241 | static void | |
17a2f251 | 10242 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
10243 | { |
10244 | char *s; | |
10245 | const char *args; | |
10246 | struct mips_opcode *insn; | |
10247 | char *argsstart; | |
10248 | unsigned int regno; | |
10249 | unsigned int lastregno = 0; | |
10250 | char *s_reset; | |
d6f16593 | 10251 | size_t i; |
252b5132 RH |
10252 | |
10253 | insn_error = NULL; | |
10254 | ||
b34976b6 AM |
10255 | mips16_small = FALSE; |
10256 | mips16_ext = FALSE; | |
252b5132 | 10257 | |
3882b010 | 10258 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
10259 | ; |
10260 | switch (*s) | |
10261 | { | |
10262 | case '\0': | |
10263 | break; | |
10264 | ||
10265 | case ' ': | |
10266 | *s++ = '\0'; | |
10267 | break; | |
10268 | ||
10269 | case '.': | |
10270 | if (s[1] == 't' && s[2] == ' ') | |
10271 | { | |
10272 | *s = '\0'; | |
b34976b6 | 10273 | mips16_small = TRUE; |
252b5132 RH |
10274 | s += 3; |
10275 | break; | |
10276 | } | |
10277 | else if (s[1] == 'e' && s[2] == ' ') | |
10278 | { | |
10279 | *s = '\0'; | |
b34976b6 | 10280 | mips16_ext = TRUE; |
252b5132 RH |
10281 | s += 3; |
10282 | break; | |
10283 | } | |
10284 | /* Fall through. */ | |
10285 | default: | |
10286 | insn_error = _("unknown opcode"); | |
10287 | return; | |
10288 | } | |
10289 | ||
10290 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 10291 | mips16_small = TRUE; |
252b5132 RH |
10292 | |
10293 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
10294 | { | |
10295 | insn_error = _("unrecognized opcode"); | |
10296 | return; | |
10297 | } | |
10298 | ||
10299 | argsstart = s; | |
10300 | for (;;) | |
10301 | { | |
9b3f89ee TS |
10302 | bfd_boolean ok; |
10303 | ||
9c2799c2 | 10304 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 10305 | |
037b32b9 | 10306 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10307 | if (! ok) |
10308 | { | |
10309 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10310 | && strcmp (insn->name, insn[1].name) == 0) | |
10311 | { | |
10312 | ++insn; | |
10313 | continue; | |
10314 | } | |
10315 | else | |
10316 | { | |
10317 | if (!insn_error) | |
10318 | { | |
10319 | static char buf[100]; | |
10320 | sprintf (buf, | |
10321 | _("opcode not supported on this processor: %s (%s)"), | |
10322 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10323 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10324 | insn_error = buf; | |
10325 | } | |
10326 | return; | |
10327 | } | |
10328 | } | |
10329 | ||
1e915849 | 10330 | create_insn (ip, insn); |
252b5132 | 10331 | imm_expr.X_op = O_absent; |
f6688943 TS |
10332 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10333 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10334 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10335 | imm2_expr.X_op = O_absent; |
252b5132 | 10336 | offset_expr.X_op = O_absent; |
f6688943 TS |
10337 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10338 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10339 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10340 | for (args = insn->args; 1; ++args) |
10341 | { | |
10342 | int c; | |
10343 | ||
10344 | if (*s == ' ') | |
10345 | ++s; | |
10346 | ||
10347 | /* In this switch statement we call break if we did not find | |
10348 | a match, continue if we did find a match, or return if we | |
10349 | are done. */ | |
10350 | ||
10351 | c = *args; | |
10352 | switch (c) | |
10353 | { | |
10354 | case '\0': | |
10355 | if (*s == '\0') | |
10356 | { | |
10357 | /* Stuff the immediate value in now, if we can. */ | |
10358 | if (imm_expr.X_op == O_constant | |
f6688943 | 10359 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
10360 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
10361 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
10362 | && insn->pinfo != INSN_MACRO) |
10363 | { | |
d6f16593 MR |
10364 | valueT tmp; |
10365 | ||
10366 | switch (*offset_reloc) | |
10367 | { | |
10368 | case BFD_RELOC_MIPS16_HI16_S: | |
10369 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10370 | break; | |
10371 | ||
10372 | case BFD_RELOC_MIPS16_HI16: | |
10373 | tmp = imm_expr.X_add_number >> 16; | |
10374 | break; | |
10375 | ||
10376 | case BFD_RELOC_MIPS16_LO16: | |
10377 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10378 | - 0x8000; | |
10379 | break; | |
10380 | ||
10381 | case BFD_RELOC_UNUSED: | |
10382 | tmp = imm_expr.X_add_number; | |
10383 | break; | |
10384 | ||
10385 | default: | |
10386 | internalError (); | |
10387 | } | |
10388 | *offset_reloc = BFD_RELOC_UNUSED; | |
10389 | ||
c4e7957c | 10390 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10391 | tmp, TRUE, mips16_small, |
252b5132 RH |
10392 | mips16_ext, &ip->insn_opcode, |
10393 | &ip->use_extend, &ip->extend); | |
10394 | imm_expr.X_op = O_absent; | |
f6688943 | 10395 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10396 | } |
10397 | ||
10398 | return; | |
10399 | } | |
10400 | break; | |
10401 | ||
10402 | case ',': | |
10403 | if (*s++ == c) | |
10404 | continue; | |
10405 | s--; | |
10406 | switch (*++args) | |
10407 | { | |
10408 | case 'v': | |
bf12938e | 10409 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10410 | continue; |
10411 | case 'w': | |
bf12938e | 10412 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10413 | continue; |
10414 | } | |
10415 | break; | |
10416 | ||
10417 | case '(': | |
10418 | case ')': | |
10419 | if (*s++ == c) | |
10420 | continue; | |
10421 | break; | |
10422 | ||
10423 | case 'v': | |
10424 | case 'w': | |
10425 | if (s[0] != '$') | |
10426 | { | |
10427 | if (c == 'v') | |
bf12938e | 10428 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10429 | else |
bf12938e | 10430 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10431 | ++args; |
10432 | continue; | |
10433 | } | |
10434 | /* Fall through. */ | |
10435 | case 'x': | |
10436 | case 'y': | |
10437 | case 'z': | |
10438 | case 'Z': | |
10439 | case '0': | |
10440 | case 'S': | |
10441 | case 'R': | |
10442 | case 'X': | |
10443 | case 'Y': | |
707bfff6 TS |
10444 | s_reset = s; |
10445 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10446 | { |
707bfff6 | 10447 | if (c == 'v' || c == 'w') |
85b51719 | 10448 | { |
707bfff6 | 10449 | if (c == 'v') |
a9e24354 | 10450 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10451 | else |
a9e24354 | 10452 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10453 | ++args; |
10454 | continue; | |
85b51719 | 10455 | } |
707bfff6 | 10456 | break; |
252b5132 RH |
10457 | } |
10458 | ||
10459 | if (*s == ' ') | |
10460 | ++s; | |
10461 | if (args[1] != *s) | |
10462 | { | |
10463 | if (c == 'v' || c == 'w') | |
10464 | { | |
10465 | regno = mips16_to_32_reg_map[lastregno]; | |
10466 | s = s_reset; | |
f9419b05 | 10467 | ++args; |
252b5132 RH |
10468 | } |
10469 | } | |
10470 | ||
10471 | switch (c) | |
10472 | { | |
10473 | case 'x': | |
10474 | case 'y': | |
10475 | case 'z': | |
10476 | case 'v': | |
10477 | case 'w': | |
10478 | case 'Z': | |
10479 | regno = mips32_to_16_reg_map[regno]; | |
10480 | break; | |
10481 | ||
10482 | case '0': | |
10483 | if (regno != 0) | |
10484 | regno = ILLEGAL_REG; | |
10485 | break; | |
10486 | ||
10487 | case 'S': | |
10488 | if (regno != SP) | |
10489 | regno = ILLEGAL_REG; | |
10490 | break; | |
10491 | ||
10492 | case 'R': | |
10493 | if (regno != RA) | |
10494 | regno = ILLEGAL_REG; | |
10495 | break; | |
10496 | ||
10497 | case 'X': | |
10498 | case 'Y': | |
741fe287 MR |
10499 | if (regno == AT && mips_opts.at) |
10500 | { | |
10501 | if (mips_opts.at == ATREG) | |
10502 | as_warn (_("used $at without \".set noat\"")); | |
10503 | else | |
10504 | as_warn (_("used $%u with \".set at=$%u\""), | |
10505 | regno, mips_opts.at); | |
10506 | } | |
252b5132 RH |
10507 | break; |
10508 | ||
10509 | default: | |
10510 | internalError (); | |
10511 | } | |
10512 | ||
10513 | if (regno == ILLEGAL_REG) | |
10514 | break; | |
10515 | ||
10516 | switch (c) | |
10517 | { | |
10518 | case 'x': | |
10519 | case 'v': | |
bf12938e | 10520 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10521 | break; |
10522 | case 'y': | |
10523 | case 'w': | |
bf12938e | 10524 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10525 | break; |
10526 | case 'z': | |
bf12938e | 10527 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10528 | break; |
10529 | case 'Z': | |
bf12938e | 10530 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10531 | case '0': |
10532 | case 'S': | |
10533 | case 'R': | |
10534 | break; | |
10535 | case 'X': | |
bf12938e | 10536 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10537 | break; |
10538 | case 'Y': | |
10539 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10540 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10541 | break; |
10542 | default: | |
10543 | internalError (); | |
10544 | } | |
10545 | ||
10546 | lastregno = regno; | |
10547 | continue; | |
10548 | ||
10549 | case 'P': | |
10550 | if (strncmp (s, "$pc", 3) == 0) | |
10551 | { | |
10552 | s += 3; | |
10553 | continue; | |
10554 | } | |
10555 | break; | |
10556 | ||
252b5132 RH |
10557 | case '5': |
10558 | case 'H': | |
10559 | case 'W': | |
10560 | case 'D': | |
10561 | case 'j': | |
252b5132 RH |
10562 | case 'V': |
10563 | case 'C': | |
10564 | case 'U': | |
10565 | case 'k': | |
10566 | case 'K': | |
d6f16593 MR |
10567 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10568 | if (i > 0) | |
252b5132 | 10569 | { |
d6f16593 | 10570 | if (imm_expr.X_op != O_constant) |
252b5132 | 10571 | { |
b34976b6 | 10572 | mips16_ext = TRUE; |
b34976b6 | 10573 | ip->use_extend = TRUE; |
252b5132 | 10574 | ip->extend = 0; |
252b5132 | 10575 | } |
d6f16593 MR |
10576 | else |
10577 | { | |
10578 | /* We need to relax this instruction. */ | |
10579 | *offset_reloc = *imm_reloc; | |
10580 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10581 | } | |
10582 | s = expr_end; | |
10583 | continue; | |
252b5132 | 10584 | } |
d6f16593 MR |
10585 | *imm_reloc = BFD_RELOC_UNUSED; |
10586 | /* Fall through. */ | |
10587 | case '<': | |
10588 | case '>': | |
10589 | case '[': | |
10590 | case ']': | |
10591 | case '4': | |
10592 | case '8': | |
10593 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10594 | if (imm_expr.X_op == O_register) |
10595 | { | |
10596 | /* What we thought was an expression turned out to | |
10597 | be a register. */ | |
10598 | ||
10599 | if (s[0] == '(' && args[1] == '(') | |
10600 | { | |
10601 | /* It looks like the expression was omitted | |
10602 | before a register indirection, which means | |
10603 | that the expression is implicitly zero. We | |
10604 | still set up imm_expr, so that we handle | |
10605 | explicit extensions correctly. */ | |
10606 | imm_expr.X_op = O_constant; | |
10607 | imm_expr.X_add_number = 0; | |
f6688943 | 10608 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10609 | continue; |
10610 | } | |
10611 | ||
10612 | break; | |
10613 | } | |
10614 | ||
10615 | /* We need to relax this instruction. */ | |
f6688943 | 10616 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10617 | s = expr_end; |
10618 | continue; | |
10619 | ||
10620 | case 'p': | |
10621 | case 'q': | |
10622 | case 'A': | |
10623 | case 'B': | |
10624 | case 'E': | |
10625 | /* We use offset_reloc rather than imm_reloc for the PC | |
10626 | relative operands. This lets macros with both | |
10627 | immediate and address operands work correctly. */ | |
10628 | my_getExpression (&offset_expr, s); | |
10629 | ||
10630 | if (offset_expr.X_op == O_register) | |
10631 | break; | |
10632 | ||
10633 | /* We need to relax this instruction. */ | |
f6688943 | 10634 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10635 | s = expr_end; |
10636 | continue; | |
10637 | ||
10638 | case '6': /* break code */ | |
10639 | my_getExpression (&imm_expr, s); | |
10640 | check_absolute_expr (ip, &imm_expr); | |
10641 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10642 | as_warn (_("Invalid value for `%s' (%lu)"), |
10643 | ip->insn_mo->name, | |
10644 | (unsigned long) imm_expr.X_add_number); | |
10645 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10646 | imm_expr.X_op = O_absent; |
10647 | s = expr_end; | |
10648 | continue; | |
10649 | ||
10650 | case 'a': /* 26 bit address */ | |
10651 | my_getExpression (&offset_expr, s); | |
10652 | s = expr_end; | |
f6688943 | 10653 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10654 | ip->insn_opcode <<= 16; |
10655 | continue; | |
10656 | ||
10657 | case 'l': /* register list for entry macro */ | |
10658 | case 'L': /* register list for exit macro */ | |
10659 | { | |
10660 | int mask; | |
10661 | ||
10662 | if (c == 'l') | |
10663 | mask = 0; | |
10664 | else | |
10665 | mask = 7 << 3; | |
10666 | while (*s != '\0') | |
10667 | { | |
707bfff6 | 10668 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10669 | |
10670 | while (*s == ' ' || *s == ',') | |
10671 | ++s; | |
707bfff6 | 10672 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10673 | freg = 0; |
707bfff6 TS |
10674 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10675 | freg = 1; | |
252b5132 RH |
10676 | else |
10677 | { | |
707bfff6 TS |
10678 | as_bad (_("can't parse register list")); |
10679 | break; | |
252b5132 RH |
10680 | } |
10681 | if (*s == ' ') | |
10682 | ++s; | |
10683 | if (*s != '-') | |
10684 | reg2 = reg1; | |
10685 | else | |
10686 | { | |
10687 | ++s; | |
707bfff6 TS |
10688 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10689 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10690 | { |
707bfff6 TS |
10691 | as_bad (_("invalid register list")); |
10692 | break; | |
252b5132 RH |
10693 | } |
10694 | } | |
10695 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10696 | { | |
10697 | mask &= ~ (7 << 3); | |
10698 | mask |= 5 << 3; | |
10699 | } | |
10700 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10701 | { | |
10702 | mask &= ~ (7 << 3); | |
10703 | mask |= 6 << 3; | |
10704 | } | |
10705 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10706 | mask |= (reg2 - 3) << 3; | |
10707 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10708 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10709 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10710 | mask |= 1; |
10711 | else | |
10712 | { | |
10713 | as_bad (_("invalid register list")); | |
10714 | break; | |
10715 | } | |
10716 | } | |
10717 | /* The mask is filled in in the opcode table for the | |
10718 | benefit of the disassembler. We remove it before | |
10719 | applying the actual mask. */ | |
10720 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10721 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10722 | } | |
10723 | continue; | |
10724 | ||
0499d65b TS |
10725 | case 'm': /* Register list for save insn. */ |
10726 | case 'M': /* Register list for restore insn. */ | |
10727 | { | |
10728 | int opcode = 0; | |
10729 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 10730 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
10731 | |
10732 | while (*s != '\0') | |
10733 | { | |
10734 | unsigned int reg1, reg2; | |
10735 | ||
10736 | SKIP_SPACE_TABS (s); | |
10737 | while (*s == ',') | |
10738 | ++s; | |
10739 | SKIP_SPACE_TABS (s); | |
10740 | ||
10741 | my_getExpression (&imm_expr, s); | |
10742 | if (imm_expr.X_op == O_constant) | |
10743 | { | |
10744 | /* Handle the frame size. */ | |
10745 | if (seen_framesz) | |
10746 | { | |
10747 | as_bad (_("more than one frame size in list")); | |
10748 | break; | |
10749 | } | |
10750 | seen_framesz = 1; | |
10751 | framesz = imm_expr.X_add_number; | |
10752 | imm_expr.X_op = O_absent; | |
10753 | s = expr_end; | |
10754 | continue; | |
10755 | } | |
10756 | ||
707bfff6 | 10757 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10758 | { |
10759 | as_bad (_("can't parse register list")); | |
10760 | break; | |
10761 | } | |
0499d65b | 10762 | |
707bfff6 TS |
10763 | while (*s == ' ') |
10764 | ++s; | |
10765 | ||
0499d65b TS |
10766 | if (*s != '-') |
10767 | reg2 = reg1; | |
10768 | else | |
10769 | { | |
10770 | ++s; | |
707bfff6 TS |
10771 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10772 | || reg2 < reg1) | |
0499d65b TS |
10773 | { |
10774 | as_bad (_("can't parse register list")); | |
10775 | break; | |
10776 | } | |
0499d65b TS |
10777 | } |
10778 | ||
10779 | while (reg1 <= reg2) | |
10780 | { | |
10781 | if (reg1 >= 4 && reg1 <= 7) | |
10782 | { | |
3a93f742 | 10783 | if (!seen_framesz) |
0499d65b | 10784 | /* args $a0-$a3 */ |
91d6fa6a | 10785 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
10786 | else |
10787 | /* statics $a0-$a3 */ | |
10788 | statics |= 1 << (reg1 - 4); | |
10789 | } | |
10790 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10791 | { | |
10792 | /* $s0-$s8 */ | |
10793 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10794 | } | |
10795 | else if (reg1 == 31) | |
10796 | { | |
10797 | /* Add $ra to insn. */ | |
10798 | opcode |= 0x40; | |
10799 | } | |
10800 | else | |
10801 | { | |
10802 | as_bad (_("unexpected register in list")); | |
10803 | break; | |
10804 | } | |
10805 | if (++reg1 == 24) | |
10806 | reg1 = 30; | |
10807 | } | |
10808 | } | |
10809 | ||
10810 | /* Encode args/statics combination. */ | |
91d6fa6a | 10811 | if (nargs & statics) |
0499d65b | 10812 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 10813 | else if (nargs == 0xf) |
0499d65b TS |
10814 | /* All $a0-$a3 are args. */ |
10815 | opcode |= MIPS16_ALL_ARGS << 16; | |
10816 | else if (statics == 0xf) | |
10817 | /* All $a0-$a3 are statics. */ | |
10818 | opcode |= MIPS16_ALL_STATICS << 16; | |
10819 | else | |
10820 | { | |
10821 | int narg = 0, nstat = 0; | |
10822 | ||
10823 | /* Count arg registers. */ | |
91d6fa6a | 10824 | while (nargs & 0x1) |
0499d65b | 10825 | { |
91d6fa6a | 10826 | nargs >>= 1; |
0499d65b TS |
10827 | narg++; |
10828 | } | |
91d6fa6a | 10829 | if (nargs != 0) |
0499d65b TS |
10830 | as_bad (_("invalid arg register list")); |
10831 | ||
10832 | /* Count static registers. */ | |
10833 | while (statics & 0x8) | |
10834 | { | |
10835 | statics = (statics << 1) & 0xf; | |
10836 | nstat++; | |
10837 | } | |
10838 | if (statics != 0) | |
10839 | as_bad (_("invalid static register list")); | |
10840 | ||
10841 | /* Encode args/statics. */ | |
10842 | opcode |= ((narg << 2) | nstat) << 16; | |
10843 | } | |
10844 | ||
10845 | /* Encode $s0/$s1. */ | |
10846 | if (sregs & (1 << 0)) /* $s0 */ | |
10847 | opcode |= 0x20; | |
10848 | if (sregs & (1 << 1)) /* $s1 */ | |
10849 | opcode |= 0x10; | |
10850 | sregs >>= 2; | |
10851 | ||
10852 | if (sregs != 0) | |
10853 | { | |
10854 | /* Count regs $s2-$s8. */ | |
10855 | int nsreg = 0; | |
10856 | while (sregs & 1) | |
10857 | { | |
10858 | sregs >>= 1; | |
10859 | nsreg++; | |
10860 | } | |
10861 | if (sregs != 0) | |
10862 | as_bad (_("invalid static register list")); | |
10863 | /* Encode $s2-$s8. */ | |
10864 | opcode |= nsreg << 24; | |
10865 | } | |
10866 | ||
10867 | /* Encode frame size. */ | |
10868 | if (!seen_framesz) | |
10869 | as_bad (_("missing frame size")); | |
10870 | else if ((framesz & 7) != 0 || framesz < 0 | |
10871 | || framesz > 0xff * 8) | |
10872 | as_bad (_("invalid frame size")); | |
10873 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10874 | { | |
10875 | framesz /= 8; | |
10876 | opcode |= (((framesz & 0xf0) << 16) | |
10877 | | (framesz & 0x0f)); | |
10878 | } | |
10879 | ||
10880 | /* Finally build the instruction. */ | |
10881 | if ((opcode >> 16) != 0 || framesz == 0) | |
10882 | { | |
10883 | ip->use_extend = TRUE; | |
10884 | ip->extend = opcode >> 16; | |
10885 | } | |
10886 | ip->insn_opcode |= opcode & 0x7f; | |
10887 | } | |
10888 | continue; | |
10889 | ||
252b5132 RH |
10890 | case 'e': /* extend code */ |
10891 | my_getExpression (&imm_expr, s); | |
10892 | check_absolute_expr (ip, &imm_expr); | |
10893 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10894 | { | |
10895 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10896 | ip->insn_mo->name, | |
10897 | (unsigned long) imm_expr.X_add_number); | |
10898 | imm_expr.X_add_number &= 0x7ff; | |
10899 | } | |
10900 | ip->insn_opcode |= imm_expr.X_add_number; | |
10901 | imm_expr.X_op = O_absent; | |
10902 | s = expr_end; | |
10903 | continue; | |
10904 | ||
10905 | default: | |
10906 | internalError (); | |
10907 | } | |
10908 | break; | |
10909 | } | |
10910 | ||
10911 | /* Args don't match. */ | |
10912 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10913 | strcmp (insn->name, insn[1].name) == 0) | |
10914 | { | |
10915 | ++insn; | |
10916 | s = argsstart; | |
10917 | continue; | |
10918 | } | |
10919 | ||
10920 | insn_error = _("illegal operands"); | |
10921 | ||
10922 | return; | |
10923 | } | |
10924 | } | |
10925 | ||
10926 | /* This structure holds information we know about a mips16 immediate | |
10927 | argument type. */ | |
10928 | ||
e972090a NC |
10929 | struct mips16_immed_operand |
10930 | { | |
252b5132 RH |
10931 | /* The type code used in the argument string in the opcode table. */ |
10932 | int type; | |
10933 | /* The number of bits in the short form of the opcode. */ | |
10934 | int nbits; | |
10935 | /* The number of bits in the extended form of the opcode. */ | |
10936 | int extbits; | |
10937 | /* The amount by which the short form is shifted when it is used; | |
10938 | for example, the sw instruction has a shift count of 2. */ | |
10939 | int shift; | |
10940 | /* The amount by which the short form is shifted when it is stored | |
10941 | into the instruction code. */ | |
10942 | int op_shift; | |
10943 | /* Non-zero if the short form is unsigned. */ | |
10944 | int unsp; | |
10945 | /* Non-zero if the extended form is unsigned. */ | |
10946 | int extu; | |
10947 | /* Non-zero if the value is PC relative. */ | |
10948 | int pcrel; | |
10949 | }; | |
10950 | ||
10951 | /* The mips16 immediate operand types. */ | |
10952 | ||
10953 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10954 | { | |
10955 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10956 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10957 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10958 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10959 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10960 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10961 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10962 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10963 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10964 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10965 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10966 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10967 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10968 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10969 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10970 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10971 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10972 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10973 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10974 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10975 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10976 | }; | |
10977 | ||
10978 | #define MIPS16_NUM_IMMED \ | |
10979 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10980 | ||
10981 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10982 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10983 | whether an extended value is needed; if one is needed, it sets | |
10984 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10985 | If SMALL is true, an unextended opcode was explicitly requested. | |
10986 | If EXT is true, an extended opcode was explicitly requested. If | |
10987 | WARN is true, warn if EXT does not match reality. */ | |
10988 | ||
10989 | static void | |
17a2f251 TS |
10990 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10991 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10992 | unsigned long *insn, bfd_boolean *use_extend, | |
10993 | unsigned short *extend) | |
252b5132 | 10994 | { |
3994f87e | 10995 | const struct mips16_immed_operand *op; |
252b5132 | 10996 | int mintiny, maxtiny; |
b34976b6 | 10997 | bfd_boolean needext; |
252b5132 RH |
10998 | |
10999 | op = mips16_immed_operands; | |
11000 | while (op->type != type) | |
11001 | { | |
11002 | ++op; | |
9c2799c2 | 11003 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
11004 | } |
11005 | ||
11006 | if (op->unsp) | |
11007 | { | |
11008 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11009 | { | |
11010 | mintiny = 1; | |
11011 | maxtiny = 1 << op->nbits; | |
11012 | } | |
11013 | else | |
11014 | { | |
11015 | mintiny = 0; | |
11016 | maxtiny = (1 << op->nbits) - 1; | |
11017 | } | |
11018 | } | |
11019 | else | |
11020 | { | |
11021 | mintiny = - (1 << (op->nbits - 1)); | |
11022 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11023 | } | |
11024 | ||
11025 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11026 | if (type == 'p' || type == 'q') | |
11027 | val /= 2; | |
11028 | ||
11029 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11030 | || val < (mintiny << op->shift) | |
11031 | || val > (maxtiny << op->shift)) | |
b34976b6 | 11032 | needext = TRUE; |
252b5132 | 11033 | else |
b34976b6 | 11034 | needext = FALSE; |
252b5132 RH |
11035 | |
11036 | if (warn && ext && ! needext) | |
beae10d5 KH |
11037 | as_warn_where (file, line, |
11038 | _("extended operand requested but not required")); | |
252b5132 RH |
11039 | if (small && needext) |
11040 | as_bad_where (file, line, _("invalid unextended operand value")); | |
11041 | ||
11042 | if (small || (! ext && ! needext)) | |
11043 | { | |
11044 | int insnval; | |
11045 | ||
b34976b6 | 11046 | *use_extend = FALSE; |
252b5132 RH |
11047 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
11048 | insnval <<= op->op_shift; | |
11049 | *insn |= insnval; | |
11050 | } | |
11051 | else | |
11052 | { | |
11053 | long minext, maxext; | |
11054 | int extval; | |
11055 | ||
11056 | if (op->extu) | |
11057 | { | |
11058 | minext = 0; | |
11059 | maxext = (1 << op->extbits) - 1; | |
11060 | } | |
11061 | else | |
11062 | { | |
11063 | minext = - (1 << (op->extbits - 1)); | |
11064 | maxext = (1 << (op->extbits - 1)) - 1; | |
11065 | } | |
11066 | if (val < minext || val > maxext) | |
11067 | as_bad_where (file, line, | |
11068 | _("operand value out of range for instruction")); | |
11069 | ||
b34976b6 | 11070 | *use_extend = TRUE; |
252b5132 RH |
11071 | if (op->extbits == 16) |
11072 | { | |
11073 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
11074 | val &= 0x1f; | |
11075 | } | |
11076 | else if (op->extbits == 15) | |
11077 | { | |
11078 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
11079 | val &= 0xf; | |
11080 | } | |
11081 | else | |
11082 | { | |
11083 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
11084 | val = 0; | |
11085 | } | |
11086 | ||
11087 | *extend = (unsigned short) extval; | |
11088 | *insn |= val; | |
11089 | } | |
11090 | } | |
11091 | \f | |
d6f16593 | 11092 | struct percent_op_match |
ad8d3bb3 | 11093 | { |
5e0116d5 RS |
11094 | const char *str; |
11095 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
11096 | }; |
11097 | ||
11098 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 11099 | { |
5e0116d5 | 11100 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 11101 | #ifdef OBJ_ELF |
5e0116d5 RS |
11102 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
11103 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
11104 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
11105 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
11106 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
11107 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
11108 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
11109 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
11110 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
11111 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
11112 | {"%half", BFD_RELOC_16}, | |
11113 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
11114 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
11115 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
11116 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
11117 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
11118 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
11119 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
11120 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
11121 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
11122 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 11123 | #endif |
5e0116d5 | 11124 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
11125 | }; |
11126 | ||
d6f16593 MR |
11127 | static const struct percent_op_match mips16_percent_op[] = |
11128 | { | |
11129 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
11130 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
11131 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
11132 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
11133 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
11134 | }; | |
11135 | ||
252b5132 | 11136 | |
5e0116d5 RS |
11137 | /* Return true if *STR points to a relocation operator. When returning true, |
11138 | move *STR over the operator and store its relocation code in *RELOC. | |
11139 | Leave both *STR and *RELOC alone when returning false. */ | |
11140 | ||
11141 | static bfd_boolean | |
17a2f251 | 11142 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 11143 | { |
d6f16593 MR |
11144 | const struct percent_op_match *percent_op; |
11145 | size_t limit, i; | |
11146 | ||
11147 | if (mips_opts.mips16) | |
11148 | { | |
11149 | percent_op = mips16_percent_op; | |
11150 | limit = ARRAY_SIZE (mips16_percent_op); | |
11151 | } | |
11152 | else | |
11153 | { | |
11154 | percent_op = mips_percent_op; | |
11155 | limit = ARRAY_SIZE (mips_percent_op); | |
11156 | } | |
76b3015f | 11157 | |
d6f16593 | 11158 | for (i = 0; i < limit; i++) |
5e0116d5 | 11159 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 11160 | { |
3f98094e DJ |
11161 | int len = strlen (percent_op[i].str); |
11162 | ||
11163 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
11164 | continue; | |
11165 | ||
5e0116d5 RS |
11166 | *str += strlen (percent_op[i].str); |
11167 | *reloc = percent_op[i].reloc; | |
394f9b3a | 11168 | |
5e0116d5 RS |
11169 | /* Check whether the output BFD supports this relocation. |
11170 | If not, issue an error and fall back on something safe. */ | |
11171 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 11172 | { |
20203fb9 | 11173 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 11174 | percent_op[i].str); |
01a3f561 | 11175 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 11176 | } |
5e0116d5 | 11177 | return TRUE; |
394f9b3a | 11178 | } |
5e0116d5 | 11179 | return FALSE; |
394f9b3a | 11180 | } |
ad8d3bb3 | 11181 | |
ad8d3bb3 | 11182 | |
5e0116d5 RS |
11183 | /* Parse string STR as a 16-bit relocatable operand. Store the |
11184 | expression in *EP and the relocations in the array starting | |
11185 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 11186 | |
01a3f561 | 11187 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 11188 | |
5e0116d5 | 11189 | static size_t |
17a2f251 TS |
11190 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
11191 | char *str) | |
ad8d3bb3 | 11192 | { |
5e0116d5 RS |
11193 | bfd_reloc_code_real_type reversed_reloc[3]; |
11194 | size_t reloc_index, i; | |
09b8f35a RS |
11195 | int crux_depth, str_depth; |
11196 | char *crux; | |
5e0116d5 RS |
11197 | |
11198 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
11199 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
11200 | of the main expression and with CRUX_DEPTH containing the number | |
11201 | of open brackets at that point. */ | |
11202 | reloc_index = -1; | |
11203 | str_depth = 0; | |
11204 | do | |
fb1b3232 | 11205 | { |
09b8f35a RS |
11206 | reloc_index++; |
11207 | crux = str; | |
11208 | crux_depth = str_depth; | |
11209 | ||
11210 | /* Skip over whitespace and brackets, keeping count of the number | |
11211 | of brackets. */ | |
11212 | while (*str == ' ' || *str == '\t' || *str == '(') | |
11213 | if (*str++ == '(') | |
11214 | str_depth++; | |
5e0116d5 | 11215 | } |
09b8f35a RS |
11216 | while (*str == '%' |
11217 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
11218 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 11219 | |
09b8f35a | 11220 | my_getExpression (ep, crux); |
5e0116d5 | 11221 | str = expr_end; |
394f9b3a | 11222 | |
5e0116d5 | 11223 | /* Match every open bracket. */ |
09b8f35a | 11224 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 11225 | if (*str++ == ')') |
09b8f35a | 11226 | crux_depth--; |
394f9b3a | 11227 | |
09b8f35a | 11228 | if (crux_depth > 0) |
20203fb9 | 11229 | as_bad (_("unclosed '('")); |
394f9b3a | 11230 | |
5e0116d5 | 11231 | expr_end = str; |
252b5132 | 11232 | |
01a3f561 | 11233 | if (reloc_index != 0) |
64bdfcaf RS |
11234 | { |
11235 | prev_reloc_op_frag = frag_now; | |
11236 | for (i = 0; i < reloc_index; i++) | |
11237 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
11238 | } | |
fb1b3232 | 11239 | |
5e0116d5 | 11240 | return reloc_index; |
252b5132 RH |
11241 | } |
11242 | ||
11243 | static void | |
17a2f251 | 11244 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
11245 | { |
11246 | char *save_in; | |
11247 | ||
11248 | save_in = input_line_pointer; | |
11249 | input_line_pointer = str; | |
11250 | expression (ep); | |
11251 | expr_end = input_line_pointer; | |
11252 | input_line_pointer = save_in; | |
252b5132 RH |
11253 | } |
11254 | ||
252b5132 | 11255 | char * |
17a2f251 | 11256 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11257 | { |
499ac353 | 11258 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
11259 | } |
11260 | ||
11261 | void | |
17a2f251 | 11262 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
11263 | { |
11264 | if (target_big_endian) | |
11265 | number_to_chars_bigendian (buf, val, n); | |
11266 | else | |
11267 | number_to_chars_littleendian (buf, val, n); | |
11268 | } | |
11269 | \f | |
ae948b86 | 11270 | #ifdef OBJ_ELF |
e013f690 TS |
11271 | static int support_64bit_objects(void) |
11272 | { | |
11273 | const char **list, **l; | |
aa3d8fdf | 11274 | int yes; |
e013f690 TS |
11275 | |
11276 | list = bfd_target_list (); | |
11277 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
11278 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
11279 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 11280 | break; |
aa3d8fdf | 11281 | yes = (*l != NULL); |
e013f690 | 11282 | free (list); |
aa3d8fdf | 11283 | return yes; |
e013f690 | 11284 | } |
ae948b86 | 11285 | #endif /* OBJ_ELF */ |
e013f690 | 11286 | |
78849248 | 11287 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11288 | |
23fce1e3 NC |
11289 | enum options |
11290 | { | |
11291 | OPTION_MARCH = OPTION_MD_BASE, | |
11292 | OPTION_MTUNE, | |
11293 | OPTION_MIPS1, | |
11294 | OPTION_MIPS2, | |
11295 | OPTION_MIPS3, | |
11296 | OPTION_MIPS4, | |
11297 | OPTION_MIPS5, | |
11298 | OPTION_MIPS32, | |
11299 | OPTION_MIPS64, | |
11300 | OPTION_MIPS32R2, | |
11301 | OPTION_MIPS64R2, | |
11302 | OPTION_MIPS16, | |
11303 | OPTION_NO_MIPS16, | |
11304 | OPTION_MIPS3D, | |
11305 | OPTION_NO_MIPS3D, | |
11306 | OPTION_MDMX, | |
11307 | OPTION_NO_MDMX, | |
11308 | OPTION_DSP, | |
11309 | OPTION_NO_DSP, | |
11310 | OPTION_MT, | |
11311 | OPTION_NO_MT, | |
11312 | OPTION_SMARTMIPS, | |
11313 | OPTION_NO_SMARTMIPS, | |
11314 | OPTION_DSPR2, | |
11315 | OPTION_NO_DSPR2, | |
11316 | OPTION_COMPAT_ARCH_BASE, | |
11317 | OPTION_M4650, | |
11318 | OPTION_NO_M4650, | |
11319 | OPTION_M4010, | |
11320 | OPTION_NO_M4010, | |
11321 | OPTION_M4100, | |
11322 | OPTION_NO_M4100, | |
11323 | OPTION_M3900, | |
11324 | OPTION_NO_M3900, | |
11325 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
11326 | OPTION_MNO_7000_HILO_FIX, |
11327 | OPTION_FIX_24K, | |
11328 | OPTION_NO_FIX_24K, | |
c67a084a NC |
11329 | OPTION_FIX_LOONGSON2F_JUMP, |
11330 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
11331 | OPTION_FIX_LOONGSON2F_NOP, | |
11332 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
11333 | OPTION_FIX_VR4120, |
11334 | OPTION_NO_FIX_VR4120, | |
11335 | OPTION_FIX_VR4130, | |
11336 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
11337 | OPTION_FIX_CN63XXP1, |
11338 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
11339 | OPTION_TRAP, |
11340 | OPTION_BREAK, | |
11341 | OPTION_EB, | |
11342 | OPTION_EL, | |
11343 | OPTION_FP32, | |
11344 | OPTION_GP32, | |
11345 | OPTION_CONSTRUCT_FLOATS, | |
11346 | OPTION_NO_CONSTRUCT_FLOATS, | |
11347 | OPTION_FP64, | |
11348 | OPTION_GP64, | |
11349 | OPTION_RELAX_BRANCH, | |
11350 | OPTION_NO_RELAX_BRANCH, | |
11351 | OPTION_MSHARED, | |
11352 | OPTION_MNO_SHARED, | |
11353 | OPTION_MSYM32, | |
11354 | OPTION_MNO_SYM32, | |
11355 | OPTION_SOFT_FLOAT, | |
11356 | OPTION_HARD_FLOAT, | |
11357 | OPTION_SINGLE_FLOAT, | |
11358 | OPTION_DOUBLE_FLOAT, | |
11359 | OPTION_32, | |
11360 | #ifdef OBJ_ELF | |
11361 | OPTION_CALL_SHARED, | |
11362 | OPTION_CALL_NONPIC, | |
11363 | OPTION_NON_SHARED, | |
11364 | OPTION_XGOT, | |
11365 | OPTION_MABI, | |
11366 | OPTION_N32, | |
11367 | OPTION_64, | |
11368 | OPTION_MDEBUG, | |
11369 | OPTION_NO_MDEBUG, | |
11370 | OPTION_PDR, | |
11371 | OPTION_NO_PDR, | |
11372 | OPTION_MVXWORKS_PIC, | |
11373 | #endif /* OBJ_ELF */ | |
11374 | OPTION_END_OF_ENUM | |
11375 | }; | |
11376 | ||
e972090a NC |
11377 | struct option md_longopts[] = |
11378 | { | |
f9b4148d | 11379 | /* Options which specify architecture. */ |
f9b4148d | 11380 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 11381 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
11382 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11383 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 11384 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 11385 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 11386 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 11387 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 11388 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 11389 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 11390 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 11391 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
11392 | |
11393 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 11394 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 11395 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 11396 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 11397 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 11398 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 11399 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 11400 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 11401 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 11402 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 11403 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 11404 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 11405 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 11406 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 11407 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
f9b4148d CD |
11408 | |
11409 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 11410 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 11411 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 11412 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 11413 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 11414 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 11415 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 11416 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
11417 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
11418 | ||
11419 | /* Options which enable bug fixes. */ | |
f9b4148d | 11420 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
11421 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
11422 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
11423 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
11424 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
11425 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
11426 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
11427 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
11428 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11429 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
11430 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
11431 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
11432 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
11433 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
11434 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
11435 | |
11436 | /* Miscellaneous options. */ | |
252b5132 RH |
11437 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11438 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
11439 | {"break", no_argument, NULL, OPTION_BREAK}, |
11440 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 11441 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 11442 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 11443 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 11444 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 11445 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 11446 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 11447 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 11448 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
11449 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11450 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11451 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
11452 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11453 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
11454 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11455 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
11456 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
11457 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
11458 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
11459 | |
11460 | /* Strictly speaking this next option is ELF specific, | |
11461 | but we allow it for other ports as well in order to | |
11462 | make testing easier. */ | |
11463 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 11464 | |
f9b4148d | 11465 | /* ELF-specific options. */ |
156c2f8b | 11466 | #ifdef OBJ_ELF |
156c2f8b NC |
11467 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11468 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 11469 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
11470 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
11471 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 11472 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 11473 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 11474 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 11475 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 11476 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 11477 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 11478 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 11479 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 11480 | #endif /* OBJ_ELF */ |
f9b4148d | 11481 | |
252b5132 RH |
11482 | {NULL, no_argument, NULL, 0} |
11483 | }; | |
156c2f8b | 11484 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11485 | |
316f5878 RS |
11486 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11487 | NEW_VALUE. Warn if another value was already specified. Note: | |
11488 | we have to defer parsing the -march and -mtune arguments in order | |
11489 | to handle 'from-abi' correctly, since the ABI might be specified | |
11490 | in a later argument. */ | |
11491 | ||
11492 | static void | |
17a2f251 | 11493 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11494 | { |
11495 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11496 | as_warn (_("A different %s was already specified, is now %s"), | |
11497 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11498 | new_value); | |
11499 | ||
11500 | *string_ptr = new_value; | |
11501 | } | |
11502 | ||
252b5132 | 11503 | int |
17a2f251 | 11504 | md_parse_option (int c, char *arg) |
252b5132 RH |
11505 | { |
11506 | switch (c) | |
11507 | { | |
119d663a NC |
11508 | case OPTION_CONSTRUCT_FLOATS: |
11509 | mips_disable_float_construction = 0; | |
11510 | break; | |
bdaaa2e1 | 11511 | |
119d663a NC |
11512 | case OPTION_NO_CONSTRUCT_FLOATS: |
11513 | mips_disable_float_construction = 1; | |
11514 | break; | |
bdaaa2e1 | 11515 | |
252b5132 RH |
11516 | case OPTION_TRAP: |
11517 | mips_trap = 1; | |
11518 | break; | |
11519 | ||
11520 | case OPTION_BREAK: | |
11521 | mips_trap = 0; | |
11522 | break; | |
11523 | ||
11524 | case OPTION_EB: | |
11525 | target_big_endian = 1; | |
11526 | break; | |
11527 | ||
11528 | case OPTION_EL: | |
11529 | target_big_endian = 0; | |
11530 | break; | |
11531 | ||
11532 | case 'O': | |
4ffff32f TS |
11533 | if (arg == NULL) |
11534 | mips_optimize = 1; | |
11535 | else if (arg[0] == '0') | |
11536 | mips_optimize = 0; | |
11537 | else if (arg[0] == '1') | |
252b5132 RH |
11538 | mips_optimize = 1; |
11539 | else | |
11540 | mips_optimize = 2; | |
11541 | break; | |
11542 | ||
11543 | case 'g': | |
11544 | if (arg == NULL) | |
11545 | mips_debug = 2; | |
11546 | else | |
11547 | mips_debug = atoi (arg); | |
252b5132 RH |
11548 | break; |
11549 | ||
11550 | case OPTION_MIPS1: | |
316f5878 | 11551 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11552 | break; |
11553 | ||
11554 | case OPTION_MIPS2: | |
316f5878 | 11555 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11556 | break; |
11557 | ||
11558 | case OPTION_MIPS3: | |
316f5878 | 11559 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11560 | break; |
11561 | ||
11562 | case OPTION_MIPS4: | |
316f5878 | 11563 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11564 | break; |
11565 | ||
84ea6cf2 | 11566 | case OPTION_MIPS5: |
316f5878 | 11567 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11568 | break; |
11569 | ||
e7af610e | 11570 | case OPTION_MIPS32: |
316f5878 | 11571 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11572 | break; |
11573 | ||
af7ee8bf CD |
11574 | case OPTION_MIPS32R2: |
11575 | file_mips_isa = ISA_MIPS32R2; | |
11576 | break; | |
11577 | ||
5f74bc13 CD |
11578 | case OPTION_MIPS64R2: |
11579 | file_mips_isa = ISA_MIPS64R2; | |
11580 | break; | |
11581 | ||
84ea6cf2 | 11582 | case OPTION_MIPS64: |
316f5878 | 11583 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11584 | break; |
11585 | ||
ec68c924 | 11586 | case OPTION_MTUNE: |
316f5878 RS |
11587 | mips_set_option_string (&mips_tune_string, arg); |
11588 | break; | |
ec68c924 | 11589 | |
316f5878 RS |
11590 | case OPTION_MARCH: |
11591 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11592 | break; |
11593 | ||
11594 | case OPTION_M4650: | |
316f5878 RS |
11595 | mips_set_option_string (&mips_arch_string, "4650"); |
11596 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11597 | break; |
11598 | ||
11599 | case OPTION_NO_M4650: | |
11600 | break; | |
11601 | ||
11602 | case OPTION_M4010: | |
316f5878 RS |
11603 | mips_set_option_string (&mips_arch_string, "4010"); |
11604 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11605 | break; |
11606 | ||
11607 | case OPTION_NO_M4010: | |
11608 | break; | |
11609 | ||
11610 | case OPTION_M4100: | |
316f5878 RS |
11611 | mips_set_option_string (&mips_arch_string, "4100"); |
11612 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11613 | break; |
11614 | ||
11615 | case OPTION_NO_M4100: | |
11616 | break; | |
11617 | ||
252b5132 | 11618 | case OPTION_M3900: |
316f5878 RS |
11619 | mips_set_option_string (&mips_arch_string, "3900"); |
11620 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11621 | break; |
bdaaa2e1 | 11622 | |
252b5132 RH |
11623 | case OPTION_NO_M3900: |
11624 | break; | |
11625 | ||
deec1734 CD |
11626 | case OPTION_MDMX: |
11627 | mips_opts.ase_mdmx = 1; | |
11628 | break; | |
11629 | ||
11630 | case OPTION_NO_MDMX: | |
11631 | mips_opts.ase_mdmx = 0; | |
11632 | break; | |
11633 | ||
74cd071d CF |
11634 | case OPTION_DSP: |
11635 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11636 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11637 | break; |
11638 | ||
11639 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11640 | mips_opts.ase_dsp = 0; |
11641 | mips_opts.ase_dspr2 = 0; | |
11642 | break; | |
11643 | ||
11644 | case OPTION_DSPR2: | |
11645 | mips_opts.ase_dspr2 = 1; | |
11646 | mips_opts.ase_dsp = 1; | |
11647 | break; | |
11648 | ||
11649 | case OPTION_NO_DSPR2: | |
11650 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11651 | mips_opts.ase_dsp = 0; |
11652 | break; | |
11653 | ||
ef2e4d86 CF |
11654 | case OPTION_MT: |
11655 | mips_opts.ase_mt = 1; | |
11656 | break; | |
11657 | ||
11658 | case OPTION_NO_MT: | |
11659 | mips_opts.ase_mt = 0; | |
11660 | break; | |
11661 | ||
252b5132 RH |
11662 | case OPTION_MIPS16: |
11663 | mips_opts.mips16 = 1; | |
7d10b47d | 11664 | mips_no_prev_insn (); |
252b5132 RH |
11665 | break; |
11666 | ||
11667 | case OPTION_NO_MIPS16: | |
11668 | mips_opts.mips16 = 0; | |
7d10b47d | 11669 | mips_no_prev_insn (); |
252b5132 RH |
11670 | break; |
11671 | ||
1f25f5d3 CD |
11672 | case OPTION_MIPS3D: |
11673 | mips_opts.ase_mips3d = 1; | |
11674 | break; | |
11675 | ||
11676 | case OPTION_NO_MIPS3D: | |
11677 | mips_opts.ase_mips3d = 0; | |
11678 | break; | |
11679 | ||
e16bfa71 TS |
11680 | case OPTION_SMARTMIPS: |
11681 | mips_opts.ase_smartmips = 1; | |
11682 | break; | |
11683 | ||
11684 | case OPTION_NO_SMARTMIPS: | |
11685 | mips_opts.ase_smartmips = 0; | |
11686 | break; | |
11687 | ||
6a32d874 CM |
11688 | case OPTION_FIX_24K: |
11689 | mips_fix_24k = 1; | |
11690 | break; | |
11691 | ||
11692 | case OPTION_NO_FIX_24K: | |
11693 | mips_fix_24k = 0; | |
11694 | break; | |
11695 | ||
c67a084a NC |
11696 | case OPTION_FIX_LOONGSON2F_JUMP: |
11697 | mips_fix_loongson2f_jump = TRUE; | |
11698 | break; | |
11699 | ||
11700 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
11701 | mips_fix_loongson2f_jump = FALSE; | |
11702 | break; | |
11703 | ||
11704 | case OPTION_FIX_LOONGSON2F_NOP: | |
11705 | mips_fix_loongson2f_nop = TRUE; | |
11706 | break; | |
11707 | ||
11708 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
11709 | mips_fix_loongson2f_nop = FALSE; | |
11710 | break; | |
11711 | ||
d766e8ec RS |
11712 | case OPTION_FIX_VR4120: |
11713 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11714 | break; |
11715 | ||
d766e8ec RS |
11716 | case OPTION_NO_FIX_VR4120: |
11717 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11718 | break; |
11719 | ||
7d8e00cf RS |
11720 | case OPTION_FIX_VR4130: |
11721 | mips_fix_vr4130 = 1; | |
11722 | break; | |
11723 | ||
11724 | case OPTION_NO_FIX_VR4130: | |
11725 | mips_fix_vr4130 = 0; | |
11726 | break; | |
11727 | ||
d954098f DD |
11728 | case OPTION_FIX_CN63XXP1: |
11729 | mips_fix_cn63xxp1 = TRUE; | |
11730 | break; | |
11731 | ||
11732 | case OPTION_NO_FIX_CN63XXP1: | |
11733 | mips_fix_cn63xxp1 = FALSE; | |
11734 | break; | |
11735 | ||
4a6a3df4 AO |
11736 | case OPTION_RELAX_BRANCH: |
11737 | mips_relax_branch = 1; | |
11738 | break; | |
11739 | ||
11740 | case OPTION_NO_RELAX_BRANCH: | |
11741 | mips_relax_branch = 0; | |
11742 | break; | |
11743 | ||
aa6975fb ILT |
11744 | case OPTION_MSHARED: |
11745 | mips_in_shared = TRUE; | |
11746 | break; | |
11747 | ||
11748 | case OPTION_MNO_SHARED: | |
11749 | mips_in_shared = FALSE; | |
11750 | break; | |
11751 | ||
aed1a261 RS |
11752 | case OPTION_MSYM32: |
11753 | mips_opts.sym32 = TRUE; | |
11754 | break; | |
11755 | ||
11756 | case OPTION_MNO_SYM32: | |
11757 | mips_opts.sym32 = FALSE; | |
11758 | break; | |
11759 | ||
0f074f60 | 11760 | #ifdef OBJ_ELF |
252b5132 RH |
11761 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11762 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11763 | intended to be compatible with Irix 5. */ | |
11764 | case OPTION_CALL_SHARED: | |
f43abd2b | 11765 | if (!IS_ELF) |
252b5132 RH |
11766 | { |
11767 | as_bad (_("-call_shared is supported only for ELF format")); | |
11768 | return 0; | |
11769 | } | |
11770 | mips_pic = SVR4_PIC; | |
143d77c5 | 11771 | mips_abicalls = TRUE; |
252b5132 RH |
11772 | break; |
11773 | ||
861fb55a DJ |
11774 | case OPTION_CALL_NONPIC: |
11775 | if (!IS_ELF) | |
11776 | { | |
11777 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
11778 | return 0; | |
11779 | } | |
11780 | mips_pic = NO_PIC; | |
11781 | mips_abicalls = TRUE; | |
11782 | break; | |
11783 | ||
252b5132 | 11784 | case OPTION_NON_SHARED: |
f43abd2b | 11785 | if (!IS_ELF) |
252b5132 RH |
11786 | { |
11787 | as_bad (_("-non_shared is supported only for ELF format")); | |
11788 | return 0; | |
11789 | } | |
11790 | mips_pic = NO_PIC; | |
143d77c5 | 11791 | mips_abicalls = FALSE; |
252b5132 RH |
11792 | break; |
11793 | ||
44075ae2 TS |
11794 | /* The -xgot option tells the assembler to use 32 bit offsets |
11795 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11796 | compatibility. */ |
11797 | case OPTION_XGOT: | |
11798 | mips_big_got = 1; | |
11799 | break; | |
0f074f60 | 11800 | #endif /* OBJ_ELF */ |
252b5132 RH |
11801 | |
11802 | case 'G': | |
6caf9ef4 TS |
11803 | g_switch_value = atoi (arg); |
11804 | g_switch_seen = 1; | |
252b5132 RH |
11805 | break; |
11806 | ||
34ba82a8 TS |
11807 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11808 | and -mabi=64. */ | |
252b5132 | 11809 | case OPTION_32: |
23fce1e3 NC |
11810 | if (IS_ELF) |
11811 | mips_abi = O32_ABI; | |
11812 | /* We silently ignore -32 for non-ELF targets. This greatly | |
11813 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
11814 | break; |
11815 | ||
23fce1e3 | 11816 | #ifdef OBJ_ELF |
e013f690 | 11817 | case OPTION_N32: |
f43abd2b | 11818 | if (!IS_ELF) |
34ba82a8 TS |
11819 | { |
11820 | as_bad (_("-n32 is supported for ELF format only")); | |
11821 | return 0; | |
11822 | } | |
316f5878 | 11823 | mips_abi = N32_ABI; |
e013f690 | 11824 | break; |
252b5132 | 11825 | |
e013f690 | 11826 | case OPTION_64: |
f43abd2b | 11827 | if (!IS_ELF) |
34ba82a8 TS |
11828 | { |
11829 | as_bad (_("-64 is supported for ELF format only")); | |
11830 | return 0; | |
11831 | } | |
316f5878 | 11832 | mips_abi = N64_ABI; |
f43abd2b | 11833 | if (!support_64bit_objects()) |
e013f690 | 11834 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11835 | break; |
ae948b86 | 11836 | #endif /* OBJ_ELF */ |
252b5132 | 11837 | |
c97ef257 | 11838 | case OPTION_GP32: |
a325df1d | 11839 | file_mips_gp32 = 1; |
c97ef257 AH |
11840 | break; |
11841 | ||
11842 | case OPTION_GP64: | |
a325df1d | 11843 | file_mips_gp32 = 0; |
c97ef257 | 11844 | break; |
252b5132 | 11845 | |
ca4e0257 | 11846 | case OPTION_FP32: |
a325df1d | 11847 | file_mips_fp32 = 1; |
316f5878 RS |
11848 | break; |
11849 | ||
11850 | case OPTION_FP64: | |
11851 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11852 | break; |
11853 | ||
037b32b9 AN |
11854 | case OPTION_SINGLE_FLOAT: |
11855 | file_mips_single_float = 1; | |
11856 | break; | |
11857 | ||
11858 | case OPTION_DOUBLE_FLOAT: | |
11859 | file_mips_single_float = 0; | |
11860 | break; | |
11861 | ||
11862 | case OPTION_SOFT_FLOAT: | |
11863 | file_mips_soft_float = 1; | |
11864 | break; | |
11865 | ||
11866 | case OPTION_HARD_FLOAT: | |
11867 | file_mips_soft_float = 0; | |
11868 | break; | |
11869 | ||
ae948b86 | 11870 | #ifdef OBJ_ELF |
252b5132 | 11871 | case OPTION_MABI: |
f43abd2b | 11872 | if (!IS_ELF) |
34ba82a8 TS |
11873 | { |
11874 | as_bad (_("-mabi is supported for ELF format only")); | |
11875 | return 0; | |
11876 | } | |
e013f690 | 11877 | if (strcmp (arg, "32") == 0) |
316f5878 | 11878 | mips_abi = O32_ABI; |
e013f690 | 11879 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11880 | mips_abi = O64_ABI; |
e013f690 | 11881 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11882 | mips_abi = N32_ABI; |
e013f690 TS |
11883 | else if (strcmp (arg, "64") == 0) |
11884 | { | |
316f5878 | 11885 | mips_abi = N64_ABI; |
e013f690 TS |
11886 | if (! support_64bit_objects()) |
11887 | as_fatal (_("No compiled in support for 64 bit object file " | |
11888 | "format")); | |
11889 | } | |
11890 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11891 | mips_abi = EABI_ABI; |
e013f690 | 11892 | else |
da0e507f TS |
11893 | { |
11894 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11895 | return 0; | |
11896 | } | |
252b5132 | 11897 | break; |
e013f690 | 11898 | #endif /* OBJ_ELF */ |
252b5132 | 11899 | |
6b76fefe | 11900 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11901 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11902 | break; |
11903 | ||
9ee72ff1 | 11904 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11905 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11906 | break; |
11907 | ||
ecb4347a DJ |
11908 | #ifdef OBJ_ELF |
11909 | case OPTION_MDEBUG: | |
b34976b6 | 11910 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11911 | break; |
11912 | ||
11913 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11914 | mips_flag_mdebug = FALSE; |
ecb4347a | 11915 | break; |
dcd410fe RO |
11916 | |
11917 | case OPTION_PDR: | |
11918 | mips_flag_pdr = TRUE; | |
11919 | break; | |
11920 | ||
11921 | case OPTION_NO_PDR: | |
11922 | mips_flag_pdr = FALSE; | |
11923 | break; | |
0a44bf69 RS |
11924 | |
11925 | case OPTION_MVXWORKS_PIC: | |
11926 | mips_pic = VXWORKS_PIC; | |
11927 | break; | |
ecb4347a DJ |
11928 | #endif /* OBJ_ELF */ |
11929 | ||
252b5132 RH |
11930 | default: |
11931 | return 0; | |
11932 | } | |
11933 | ||
c67a084a NC |
11934 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
11935 | ||
252b5132 RH |
11936 | return 1; |
11937 | } | |
316f5878 RS |
11938 | \f |
11939 | /* Set up globals to generate code for the ISA or processor | |
11940 | described by INFO. */ | |
252b5132 | 11941 | |
252b5132 | 11942 | static void |
17a2f251 | 11943 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11944 | { |
316f5878 | 11945 | if (info != 0) |
252b5132 | 11946 | { |
fef14a42 TS |
11947 | file_mips_arch = info->cpu; |
11948 | mips_opts.arch = info->cpu; | |
316f5878 | 11949 | mips_opts.isa = info->isa; |
252b5132 | 11950 | } |
252b5132 RH |
11951 | } |
11952 | ||
252b5132 | 11953 | |
316f5878 | 11954 | /* Likewise for tuning. */ |
252b5132 | 11955 | |
316f5878 | 11956 | static void |
17a2f251 | 11957 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11958 | { |
11959 | if (info != 0) | |
fef14a42 | 11960 | mips_tune = info->cpu; |
316f5878 | 11961 | } |
80cc45a5 | 11962 | |
34ba82a8 | 11963 | |
252b5132 | 11964 | void |
17a2f251 | 11965 | mips_after_parse_args (void) |
e9670677 | 11966 | { |
fef14a42 TS |
11967 | const struct mips_cpu_info *arch_info = 0; |
11968 | const struct mips_cpu_info *tune_info = 0; | |
11969 | ||
e9670677 | 11970 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11971 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11972 | { |
6caf9ef4 | 11973 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11974 | as_bad (_("-G not supported in this configuration.")); |
11975 | g_switch_value = 0; | |
11976 | } | |
11977 | ||
cac012d6 AO |
11978 | if (mips_abi == NO_ABI) |
11979 | mips_abi = MIPS_DEFAULT_ABI; | |
11980 | ||
22923709 RS |
11981 | /* The following code determines the architecture and register size. |
11982 | Similar code was added to GCC 3.3 (see override_options() in | |
11983 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11984 | as much as possible. */ | |
e9670677 | 11985 | |
316f5878 | 11986 | if (mips_arch_string != 0) |
fef14a42 | 11987 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11988 | |
316f5878 | 11989 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11990 | { |
316f5878 | 11991 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11992 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11993 | the -march selection (if any). */ |
fef14a42 | 11994 | if (arch_info != 0) |
e9670677 | 11995 | { |
316f5878 RS |
11996 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11997 | There's no harm in specifying both as long as the ISA levels | |
11998 | are the same. */ | |
fef14a42 | 11999 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
12000 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
12001 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 12002 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 12003 | } |
316f5878 | 12004 | else |
fef14a42 | 12005 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
12006 | } |
12007 | ||
fef14a42 TS |
12008 | if (arch_info == 0) |
12009 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 12010 | |
fef14a42 | 12011 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 12012 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
12013 | arch_info->name); |
12014 | ||
12015 | mips_set_architecture (arch_info); | |
12016 | ||
12017 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
12018 | if (mips_tune_string != 0) | |
12019 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 12020 | |
fef14a42 TS |
12021 | if (tune_info == 0) |
12022 | mips_set_tune (arch_info); | |
12023 | else | |
12024 | mips_set_tune (tune_info); | |
e9670677 | 12025 | |
316f5878 | 12026 | if (file_mips_gp32 >= 0) |
e9670677 | 12027 | { |
316f5878 RS |
12028 | /* The user specified the size of the integer registers. Make sure |
12029 | it agrees with the ABI and ISA. */ | |
12030 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12031 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
12032 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12033 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
12034 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
12035 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
12036 | } |
12037 | else | |
12038 | { | |
316f5878 RS |
12039 | /* Infer the integer register size from the ABI and processor. |
12040 | Restrict ourselves to 32-bit registers if that's all the | |
12041 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
12042 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12043 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
12044 | } |
12045 | ||
ad3fea08 TS |
12046 | switch (file_mips_fp32) |
12047 | { | |
12048 | default: | |
12049 | case -1: | |
12050 | /* No user specified float register size. | |
12051 | ??? GAS treats single-float processors as though they had 64-bit | |
12052 | float registers (although it complains when double-precision | |
12053 | instructions are used). As things stand, saying they have 32-bit | |
12054 | registers would lead to spurious "register must be even" messages. | |
12055 | So here we assume float registers are never smaller than the | |
12056 | integer ones. */ | |
12057 | if (file_mips_gp32 == 0) | |
12058 | /* 64-bit integer registers implies 64-bit float registers. */ | |
12059 | file_mips_fp32 = 0; | |
12060 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
12061 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12062 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
12063 | file_mips_fp32 = 0; | |
12064 | else | |
12065 | /* 32-bit float registers. */ | |
12066 | file_mips_fp32 = 1; | |
12067 | break; | |
12068 | ||
12069 | /* The user specified the size of the float registers. Check if it | |
12070 | agrees with the ABI and ISA. */ | |
12071 | case 0: | |
12072 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12073 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
12074 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12075 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12076 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
12077 | break; | |
12078 | case 1: | |
12079 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12080 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
12081 | break; | |
12082 | } | |
e9670677 | 12083 | |
316f5878 | 12084 | /* End of GCC-shared inference code. */ |
e9670677 | 12085 | |
17a2f251 TS |
12086 | /* This flag is set when we have a 64-bit capable CPU but use only |
12087 | 32-bit wide registers. Note that EABI does not use it. */ | |
12088 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
12089 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
12090 | || mips_abi == O32_ABI)) | |
316f5878 | 12091 | mips_32bitmode = 1; |
e9670677 MR |
12092 | |
12093 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
12094 | as_bad (_("trap exception not supported at ISA 1")); | |
12095 | ||
e9670677 MR |
12096 | /* If the selected architecture includes support for ASEs, enable |
12097 | generation of code for them. */ | |
a4672219 | 12098 | if (mips_opts.mips16 == -1) |
fef14a42 | 12099 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 12100 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 12101 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
12102 | && file_mips_fp32 == 0) ? 1 : 0; |
12103 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
12104 | as_bad (_("-mfp32 used with -mips3d")); | |
12105 | ||
ffdefa66 | 12106 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 12107 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
12108 | && file_mips_fp32 == 0) ? 1 : 0; |
12109 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
12110 | as_bad (_("-mfp32 used with -mdmx")); | |
12111 | ||
12112 | if (mips_opts.ase_smartmips == -1) | |
12113 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
12114 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
12115 | as_warn (_("%s ISA does not support SmartMIPS"), |
12116 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12117 | |
74cd071d | 12118 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
12119 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
12120 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
12121 | as_warn (_("%s ISA does not support DSP ASE"), |
12122 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12123 | |
8b082fb1 TS |
12124 | if (mips_opts.ase_dspr2 == -1) |
12125 | { | |
12126 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
12127 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
12128 | } | |
12129 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
12130 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
12131 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 12132 | |
ef2e4d86 | 12133 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
12134 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
12135 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
12136 | as_warn (_("%s ISA does not support MT ASE"), |
12137 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 12138 | |
e9670677 | 12139 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
12140 | file_ase_mips3d = mips_opts.ase_mips3d; |
12141 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 12142 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 12143 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 12144 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 12145 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
12146 | mips_opts.gp32 = file_mips_gp32; |
12147 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
12148 | mips_opts.soft_float = file_mips_soft_float; |
12149 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 12150 | |
ecb4347a DJ |
12151 | if (mips_flag_mdebug < 0) |
12152 | { | |
12153 | #ifdef OBJ_MAYBE_ECOFF | |
12154 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
12155 | mips_flag_mdebug = 1; | |
12156 | else | |
12157 | #endif /* OBJ_MAYBE_ECOFF */ | |
12158 | mips_flag_mdebug = 0; | |
12159 | } | |
e9670677 MR |
12160 | } |
12161 | \f | |
12162 | void | |
17a2f251 | 12163 | mips_init_after_args (void) |
252b5132 RH |
12164 | { |
12165 | /* initialize opcodes */ | |
12166 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 12167 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
12168 | } |
12169 | ||
12170 | long | |
17a2f251 | 12171 | md_pcrel_from (fixS *fixP) |
252b5132 | 12172 | { |
a7ebbfdf TS |
12173 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
12174 | switch (fixP->fx_r_type) | |
12175 | { | |
12176 | case BFD_RELOC_16_PCREL_S2: | |
12177 | case BFD_RELOC_MIPS_JMP: | |
12178 | /* Return the address of the delay slot. */ | |
12179 | return addr + 4; | |
12180 | default: | |
58ea3d6a | 12181 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
12182 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
12183 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12184 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
12185 | return addr; |
12186 | } | |
252b5132 RH |
12187 | } |
12188 | ||
252b5132 RH |
12189 | /* This is called before the symbol table is processed. In order to |
12190 | work with gcc when using mips-tfile, we must keep all local labels. | |
12191 | However, in other cases, we want to discard them. If we were | |
12192 | called with -g, but we didn't see any debugging information, it may | |
12193 | mean that gcc is smuggling debugging information through to | |
12194 | mips-tfile, in which case we must generate all local labels. */ | |
12195 | ||
12196 | void | |
17a2f251 | 12197 | mips_frob_file_before_adjust (void) |
252b5132 RH |
12198 | { |
12199 | #ifndef NO_ECOFF_DEBUGGING | |
12200 | if (ECOFF_DEBUGGING | |
12201 | && mips_debug != 0 | |
12202 | && ! ecoff_debugging_seen) | |
12203 | flag_keep_locals = 1; | |
12204 | #endif | |
12205 | } | |
12206 | ||
3b91255e | 12207 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 12208 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
12209 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
12210 | relocation operators. | |
12211 | ||
12212 | For our purposes, a %lo() expression matches a %got() or %hi() | |
12213 | expression if: | |
12214 | ||
12215 | (a) it refers to the same symbol; and | |
12216 | (b) the offset applied in the %lo() expression is no lower than | |
12217 | the offset applied in the %got() or %hi(). | |
12218 | ||
12219 | (b) allows us to cope with code like: | |
12220 | ||
12221 | lui $4,%hi(foo) | |
12222 | lh $4,%lo(foo+2)($4) | |
12223 | ||
12224 | ...which is legal on RELA targets, and has a well-defined behaviour | |
12225 | if the user knows that adding 2 to "foo" will not induce a carry to | |
12226 | the high 16 bits. | |
12227 | ||
12228 | When several %lo()s match a particular %got() or %hi(), we use the | |
12229 | following rules to distinguish them: | |
12230 | ||
12231 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
12232 | higher offsets. | |
12233 | ||
12234 | (2) %lo()s with no matching %got() or %hi() are better than those | |
12235 | that already have a matching %got() or %hi(). | |
12236 | ||
12237 | (3) later %lo()s are better than earlier %lo()s. | |
12238 | ||
12239 | These rules are applied in order. | |
12240 | ||
12241 | (1) means, among other things, that %lo()s with identical offsets are | |
12242 | chosen if they exist. | |
12243 | ||
12244 | (2) means that we won't associate several high-part relocations with | |
12245 | the same low-part relocation unless there's no alternative. Having | |
12246 | several high parts for the same low part is a GNU extension; this rule | |
12247 | allows careful users to avoid it. | |
12248 | ||
12249 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
12250 | with the last high-part relocation being at the front of the list. | |
12251 | It therefore makes sense to choose the last matching low-part | |
12252 | relocation, all other things being equal. It's also easier | |
12253 | to code that way. */ | |
252b5132 RH |
12254 | |
12255 | void | |
17a2f251 | 12256 | mips_frob_file (void) |
252b5132 RH |
12257 | { |
12258 | struct mips_hi_fixup *l; | |
35903be0 | 12259 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
12260 | |
12261 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
12262 | { | |
12263 | segment_info_type *seginfo; | |
3b91255e RS |
12264 | bfd_boolean matched_lo_p; |
12265 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 12266 | |
9c2799c2 | 12267 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 12268 | |
5919d012 RS |
12269 | /* If a GOT16 relocation turns out to be against a global symbol, |
12270 | there isn't supposed to be a matching LO. */ | |
738e5348 | 12271 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
12272 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
12273 | continue; | |
12274 | ||
12275 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
12276 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
12277 | continue; |
12278 | ||
252b5132 | 12279 | seginfo = seg_info (l->seg); |
252b5132 | 12280 | |
3b91255e RS |
12281 | /* Set HI_POS to the position of this relocation in the chain. |
12282 | Set LO_POS to the position of the chosen low-part relocation. | |
12283 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
12284 | relocation that matches an immediately-preceding high-part | |
12285 | relocation. */ | |
12286 | hi_pos = NULL; | |
12287 | lo_pos = NULL; | |
12288 | matched_lo_p = FALSE; | |
738e5348 | 12289 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 12290 | |
3b91255e RS |
12291 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
12292 | { | |
12293 | if (*pos == l->fixp) | |
12294 | hi_pos = pos; | |
12295 | ||
35903be0 | 12296 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 12297 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
12298 | && (*pos)->fx_offset >= l->fixp->fx_offset |
12299 | && (lo_pos == NULL | |
12300 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
12301 | || (!matched_lo_p | |
12302 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
12303 | lo_pos = pos; | |
12304 | ||
12305 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
12306 | && fixup_has_matching_lo_p (*pos)); | |
12307 | } | |
12308 | ||
12309 | /* If we found a match, remove the high-part relocation from its | |
12310 | current position and insert it before the low-part relocation. | |
12311 | Make the offsets match so that fixup_has_matching_lo_p() | |
12312 | will return true. | |
12313 | ||
12314 | We don't warn about unmatched high-part relocations since some | |
12315 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
12316 | instructions. */ | |
12317 | if (lo_pos != NULL) | |
12318 | { | |
12319 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
12320 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 12321 | { |
3b91255e RS |
12322 | *hi_pos = l->fixp->fx_next; |
12323 | l->fixp->fx_next = *lo_pos; | |
12324 | *lo_pos = l->fixp; | |
252b5132 | 12325 | } |
252b5132 RH |
12326 | } |
12327 | } | |
12328 | } | |
12329 | ||
3e722fb5 | 12330 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 12331 | We have to prevent gas from dropping them. */ |
252b5132 | 12332 | |
252b5132 | 12333 | int |
17a2f251 | 12334 | mips_force_relocation (fixS *fixp) |
252b5132 | 12335 | { |
ae6063d4 | 12336 | if (generic_force_reloc (fixp)) |
252b5132 RH |
12337 | return 1; |
12338 | ||
f6688943 TS |
12339 | if (HAVE_NEWABI |
12340 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
12341 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
12342 | || hi16_reloc_p (fixp->fx_r_type) |
12343 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
12344 | return 1; |
12345 | ||
3e722fb5 | 12346 | return 0; |
252b5132 RH |
12347 | } |
12348 | ||
12349 | /* Apply a fixup to the object file. */ | |
12350 | ||
94f592af | 12351 | void |
55cf6793 | 12352 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12353 | { |
874e8986 | 12354 | bfd_byte *buf; |
98aa84af | 12355 | long insn; |
a7ebbfdf | 12356 | reloc_howto_type *howto; |
252b5132 | 12357 | |
a7ebbfdf TS |
12358 | /* We ignore generic BFD relocations we don't know about. */ |
12359 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12360 | if (! howto) | |
12361 | return; | |
65551fa4 | 12362 | |
9c2799c2 | 12363 | gas_assert (fixP->fx_size == 4 |
90ecf173 MR |
12364 | || fixP->fx_r_type == BFD_RELOC_16 |
12365 | || fixP->fx_r_type == BFD_RELOC_64 | |
12366 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
12367 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
12368 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12369 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
12370 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12371 | |
a7ebbfdf | 12372 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12373 | |
9c2799c2 | 12374 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12375 | |
12376 | /* Don't treat parts of a composite relocation as done. There are two | |
12377 | reasons for this: | |
12378 | ||
12379 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12380 | should nevertheless be emitted if the first part is. | |
12381 | ||
12382 | (2) In normal usage, composite relocations are never assembly-time | |
12383 | constants. The easiest way of dealing with the pathological | |
12384 | exceptions is to generate a relocation against STN_UNDEF and | |
12385 | leave everything up to the linker. */ | |
3994f87e | 12386 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12387 | fixP->fx_done = 1; |
12388 | ||
12389 | switch (fixP->fx_r_type) | |
12390 | { | |
3f98094e DJ |
12391 | case BFD_RELOC_MIPS_TLS_GD: |
12392 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12393 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12394 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12395 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12396 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12397 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12398 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12399 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12400 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12401 | /* fall through */ | |
12402 | ||
252b5132 | 12403 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12404 | case BFD_RELOC_MIPS_SHIFT5: |
12405 | case BFD_RELOC_MIPS_SHIFT6: | |
12406 | case BFD_RELOC_MIPS_GOT_DISP: | |
12407 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12408 | case BFD_RELOC_MIPS_GOT_OFST: | |
12409 | case BFD_RELOC_MIPS_SUB: | |
12410 | case BFD_RELOC_MIPS_INSERT_A: | |
12411 | case BFD_RELOC_MIPS_INSERT_B: | |
12412 | case BFD_RELOC_MIPS_DELETE: | |
12413 | case BFD_RELOC_MIPS_HIGHEST: | |
12414 | case BFD_RELOC_MIPS_HIGHER: | |
12415 | case BFD_RELOC_MIPS_SCN_DISP: | |
12416 | case BFD_RELOC_MIPS_REL16: | |
12417 | case BFD_RELOC_MIPS_RELGOT: | |
12418 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12419 | case BFD_RELOC_HI16: |
12420 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12421 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12422 | case BFD_RELOC_MIPS_LITERAL: |
12423 | case BFD_RELOC_MIPS_CALL16: | |
12424 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12425 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12426 | case BFD_RELOC_MIPS_GOT_HI16: |
12427 | case BFD_RELOC_MIPS_GOT_LO16: | |
12428 | case BFD_RELOC_MIPS_CALL_HI16: | |
12429 | case BFD_RELOC_MIPS_CALL_LO16: | |
12430 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
12431 | case BFD_RELOC_MIPS16_GOT16: |
12432 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
12433 | case BFD_RELOC_MIPS16_HI16: |
12434 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12435 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12436 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12437 | break; |
12438 | ||
252b5132 RH |
12439 | case BFD_RELOC_64: |
12440 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12441 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12442 | if (fixP->fx_done) |
252b5132 RH |
12443 | { |
12444 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12445 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12446 | else |
12447 | { | |
a7ebbfdf | 12448 | valueT hiv; |
252b5132 | 12449 | |
a7ebbfdf | 12450 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12451 | hiv = 0xffffffff; |
12452 | else | |
12453 | hiv = 0; | |
b215186b | 12454 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12455 | *valP, 4); |
b215186b | 12456 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12457 | hiv, 4); |
252b5132 RH |
12458 | } |
12459 | } | |
12460 | break; | |
12461 | ||
056350c6 | 12462 | case BFD_RELOC_RVA: |
252b5132 | 12463 | case BFD_RELOC_32: |
252b5132 RH |
12464 | case BFD_RELOC_16: |
12465 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12466 | value now. This can happen if we have a .word which is not |
12467 | resolved when it appears but is later defined. */ | |
252b5132 | 12468 | if (fixP->fx_done) |
54f4ddb3 | 12469 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12470 | break; |
12471 | ||
12472 | case BFD_RELOC_LO16: | |
d6f16593 | 12473 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12474 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12475 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12476 | /* When handling an embedded PIC switch statement, we can wind |
12477 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12478 | if (fixP->fx_done) | |
12479 | { | |
a7ebbfdf | 12480 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12481 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12482 | _("relocation overflow")); | |
252b5132 RH |
12483 | if (target_big_endian) |
12484 | buf += 2; | |
2132e3a3 | 12485 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12486 | } |
12487 | break; | |
12488 | ||
12489 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12490 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12491 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12492 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12493 | |
54f4ddb3 TS |
12494 | /* We need to save the bits in the instruction since fixup_segment() |
12495 | might be deleting the relocation entry (i.e., a branch within | |
12496 | the current segment). */ | |
a7ebbfdf | 12497 | if (! fixP->fx_done) |
bb2d6cd7 | 12498 | break; |
252b5132 | 12499 | |
54f4ddb3 | 12500 | /* Update old instruction data. */ |
252b5132 RH |
12501 | if (target_big_endian) |
12502 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12503 | else | |
12504 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12505 | ||
a7ebbfdf TS |
12506 | if (*valP + 0x20000 <= 0x3ffff) |
12507 | { | |
12508 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12509 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12510 | } |
12511 | else if (mips_pic == NO_PIC | |
12512 | && fixP->fx_done | |
12513 | && fixP->fx_frag->fr_address >= text_section->vma | |
12514 | && (fixP->fx_frag->fr_address | |
587aac4e | 12515 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12516 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12517 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12518 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12519 | { |
12520 | /* The branch offset is too large. If this is an | |
12521 | unconditional branch, and we are not generating PIC code, | |
12522 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12523 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12524 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12525 | else |
a7ebbfdf TS |
12526 | insn = 0x08000000; /* j */ |
12527 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12528 | fixP->fx_done = 0; | |
12529 | fixP->fx_addsy = section_symbol (text_section); | |
12530 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12531 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12532 | } |
12533 | else | |
12534 | { | |
12535 | /* If we got here, we have branch-relaxation disabled, | |
12536 | and there's nothing we can do to fix this instruction | |
12537 | without turning it into a longer sequence. */ | |
12538 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12539 | _("Branch out of range")); | |
252b5132 | 12540 | } |
252b5132 RH |
12541 | break; |
12542 | ||
12543 | case BFD_RELOC_VTABLE_INHERIT: | |
12544 | fixP->fx_done = 0; | |
12545 | if (fixP->fx_addsy | |
12546 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12547 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12548 | S_SET_WEAK (fixP->fx_addsy); | |
12549 | break; | |
12550 | ||
12551 | case BFD_RELOC_VTABLE_ENTRY: | |
12552 | fixP->fx_done = 0; | |
12553 | break; | |
12554 | ||
12555 | default: | |
12556 | internalError (); | |
12557 | } | |
a7ebbfdf TS |
12558 | |
12559 | /* Remember value for tc_gen_reloc. */ | |
12560 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12561 | } |
12562 | ||
252b5132 | 12563 | static symbolS * |
17a2f251 | 12564 | get_symbol (void) |
252b5132 RH |
12565 | { |
12566 | int c; | |
12567 | char *name; | |
12568 | symbolS *p; | |
12569 | ||
12570 | name = input_line_pointer; | |
12571 | c = get_symbol_end (); | |
12572 | p = (symbolS *) symbol_find_or_make (name); | |
12573 | *input_line_pointer = c; | |
12574 | return p; | |
12575 | } | |
12576 | ||
742a56fe RS |
12577 | /* Align the current frag to a given power of two. If a particular |
12578 | fill byte should be used, FILL points to an integer that contains | |
12579 | that byte, otherwise FILL is null. | |
12580 | ||
12581 | The MIPS assembler also automatically adjusts any preceding | |
12582 | label. */ | |
252b5132 RH |
12583 | |
12584 | static void | |
742a56fe | 12585 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12586 | { |
7d10b47d | 12587 | mips_emit_delays (); |
742a56fe RS |
12588 | mips_record_mips16_mode (); |
12589 | if (fill == NULL && subseg_text_p (now_seg)) | |
12590 | frag_align_code (to, 0); | |
12591 | else | |
12592 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12593 | record_alignment (now_seg, to); |
12594 | if (label != NULL) | |
12595 | { | |
9c2799c2 | 12596 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 12597 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12598 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12599 | } | |
12600 | } | |
12601 | ||
12602 | /* Align to a given power of two. .align 0 turns off the automatic | |
12603 | alignment used by the data creating pseudo-ops. */ | |
12604 | ||
12605 | static void | |
17a2f251 | 12606 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12607 | { |
742a56fe | 12608 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12609 | long max_alignment = 28; |
252b5132 | 12610 | |
54f4ddb3 | 12611 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12612 | to the aligned address. |
54f4ddb3 | 12613 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12614 | a .align pseudo instruction. |
54f4ddb3 | 12615 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12616 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12617 | We don't. */ |
252b5132 RH |
12618 | |
12619 | temp = get_absolute_expression (); | |
12620 | if (temp > max_alignment) | |
12621 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12622 | else if (temp < 0) | |
12623 | { | |
12624 | as_warn (_("Alignment negative: 0 assumed.")); | |
12625 | temp = 0; | |
12626 | } | |
12627 | if (*input_line_pointer == ',') | |
12628 | { | |
f9419b05 | 12629 | ++input_line_pointer; |
742a56fe RS |
12630 | fill_value = get_absolute_expression (); |
12631 | fill_ptr = &fill_value; | |
252b5132 RH |
12632 | } |
12633 | else | |
742a56fe | 12634 | fill_ptr = 0; |
252b5132 RH |
12635 | if (temp) |
12636 | { | |
a8dbcb85 TS |
12637 | segment_info_type *si = seg_info (now_seg); |
12638 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12639 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12640 | auto_align = 1; |
742a56fe | 12641 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12642 | } |
12643 | else | |
12644 | { | |
12645 | auto_align = 0; | |
12646 | } | |
12647 | ||
12648 | demand_empty_rest_of_line (); | |
12649 | } | |
12650 | ||
252b5132 | 12651 | static void |
17a2f251 | 12652 | s_change_sec (int sec) |
252b5132 RH |
12653 | { |
12654 | segT seg; | |
12655 | ||
252b5132 RH |
12656 | #ifdef OBJ_ELF |
12657 | /* The ELF backend needs to know that we are changing sections, so | |
12658 | that .previous works correctly. We could do something like check | |
b6ff326e | 12659 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12660 | as it would not be appropriate to use it in the section changing |
12661 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12662 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12663 | if (IS_ELF) |
12664 | obj_elf_section_change_hook (); | |
252b5132 RH |
12665 | #endif |
12666 | ||
7d10b47d | 12667 | mips_emit_delays (); |
6a32d874 | 12668 | |
252b5132 RH |
12669 | switch (sec) |
12670 | { | |
12671 | case 't': | |
12672 | s_text (0); | |
12673 | break; | |
12674 | case 'd': | |
12675 | s_data (0); | |
12676 | break; | |
12677 | case 'b': | |
12678 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12679 | demand_empty_rest_of_line (); | |
12680 | break; | |
12681 | ||
12682 | case 'r': | |
4d0d148d TS |
12683 | seg = subseg_new (RDATA_SECTION_NAME, |
12684 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12685 | if (IS_ELF) |
252b5132 | 12686 | { |
4d0d148d TS |
12687 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12688 | | SEC_READONLY | SEC_RELOC | |
12689 | | SEC_DATA)); | |
c41e87e3 | 12690 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12691 | record_alignment (seg, 4); |
252b5132 | 12692 | } |
4d0d148d | 12693 | demand_empty_rest_of_line (); |
252b5132 RH |
12694 | break; |
12695 | ||
12696 | case 's': | |
4d0d148d | 12697 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12698 | if (IS_ELF) |
252b5132 | 12699 | { |
4d0d148d TS |
12700 | bfd_set_section_flags (stdoutput, seg, |
12701 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12702 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12703 | record_alignment (seg, 4); |
252b5132 | 12704 | } |
4d0d148d TS |
12705 | demand_empty_rest_of_line (); |
12706 | break; | |
998b3c36 MR |
12707 | |
12708 | case 'B': | |
12709 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
12710 | if (IS_ELF) | |
12711 | { | |
12712 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
12713 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
12714 | record_alignment (seg, 4); | |
12715 | } | |
12716 | demand_empty_rest_of_line (); | |
12717 | break; | |
252b5132 RH |
12718 | } |
12719 | ||
12720 | auto_align = 1; | |
12721 | } | |
b34976b6 | 12722 | |
cca86cc8 | 12723 | void |
17a2f251 | 12724 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12725 | { |
7ed4a06a | 12726 | #ifdef OBJ_ELF |
cca86cc8 SC |
12727 | char *section_name; |
12728 | char c; | |
684022ea | 12729 | char next_c = 0; |
cca86cc8 SC |
12730 | int section_type; |
12731 | int section_flag; | |
12732 | int section_entry_size; | |
12733 | int section_alignment; | |
b34976b6 | 12734 | |
f43abd2b | 12735 | if (!IS_ELF) |
7ed4a06a TS |
12736 | return; |
12737 | ||
cca86cc8 SC |
12738 | section_name = input_line_pointer; |
12739 | c = get_symbol_end (); | |
a816d1ed AO |
12740 | if (c) |
12741 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12742 | |
4cf0dd0d TS |
12743 | /* Do we have .section Name<,"flags">? */ |
12744 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12745 | { |
4cf0dd0d TS |
12746 | /* just after name is now '\0'. */ |
12747 | *input_line_pointer = c; | |
cca86cc8 SC |
12748 | input_line_pointer = section_name; |
12749 | obj_elf_section (ignore); | |
12750 | return; | |
12751 | } | |
12752 | input_line_pointer++; | |
12753 | ||
12754 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12755 | if (c == ',') | |
12756 | section_type = get_absolute_expression (); | |
12757 | else | |
12758 | section_type = 0; | |
12759 | if (*input_line_pointer++ == ',') | |
12760 | section_flag = get_absolute_expression (); | |
12761 | else | |
12762 | section_flag = 0; | |
12763 | if (*input_line_pointer++ == ',') | |
12764 | section_entry_size = get_absolute_expression (); | |
12765 | else | |
12766 | section_entry_size = 0; | |
12767 | if (*input_line_pointer++ == ',') | |
12768 | section_alignment = get_absolute_expression (); | |
12769 | else | |
12770 | section_alignment = 0; | |
87975d2a AM |
12771 | /* FIXME: really ignore? */ |
12772 | (void) section_alignment; | |
cca86cc8 | 12773 | |
a816d1ed AO |
12774 | section_name = xstrdup (section_name); |
12775 | ||
8ab8a5c8 RS |
12776 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12777 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12778 | traditionally had to fall back on the more common @progbits instead. | |
12779 | ||
12780 | There's nothing really harmful in this, since bfd will correct | |
12781 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12782 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12783 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12784 | ||
12785 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12786 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12787 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12788 | generic type-checking code. */ | |
12789 | if (section_type == SHT_MIPS_DWARF) | |
12790 | section_type = SHT_PROGBITS; | |
12791 | ||
cca86cc8 SC |
12792 | obj_elf_change_section (section_name, section_type, section_flag, |
12793 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12794 | |
12795 | if (now_seg->name != section_name) | |
12796 | free (section_name); | |
7ed4a06a | 12797 | #endif /* OBJ_ELF */ |
cca86cc8 | 12798 | } |
252b5132 RH |
12799 | |
12800 | void | |
17a2f251 | 12801 | mips_enable_auto_align (void) |
252b5132 RH |
12802 | { |
12803 | auto_align = 1; | |
12804 | } | |
12805 | ||
12806 | static void | |
17a2f251 | 12807 | s_cons (int log_size) |
252b5132 | 12808 | { |
a8dbcb85 TS |
12809 | segment_info_type *si = seg_info (now_seg); |
12810 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12811 | symbolS *label; |
12812 | ||
a8dbcb85 | 12813 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12814 | mips_emit_delays (); |
252b5132 RH |
12815 | if (log_size > 0 && auto_align) |
12816 | mips_align (log_size, 0, label); | |
252b5132 | 12817 | cons (1 << log_size); |
a1facbec | 12818 | mips_clear_insn_labels (); |
252b5132 RH |
12819 | } |
12820 | ||
12821 | static void | |
17a2f251 | 12822 | s_float_cons (int type) |
252b5132 | 12823 | { |
a8dbcb85 TS |
12824 | segment_info_type *si = seg_info (now_seg); |
12825 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12826 | symbolS *label; |
12827 | ||
a8dbcb85 | 12828 | label = l != NULL ? l->label : NULL; |
252b5132 | 12829 | |
7d10b47d | 12830 | mips_emit_delays (); |
252b5132 RH |
12831 | |
12832 | if (auto_align) | |
49309057 ILT |
12833 | { |
12834 | if (type == 'd') | |
12835 | mips_align (3, 0, label); | |
12836 | else | |
12837 | mips_align (2, 0, label); | |
12838 | } | |
252b5132 | 12839 | |
252b5132 | 12840 | float_cons (type); |
a1facbec | 12841 | mips_clear_insn_labels (); |
252b5132 RH |
12842 | } |
12843 | ||
12844 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12845 | permitted to say | |
12846 | .globl foo .text | |
12847 | where foo is an undefined symbol, to mean that foo should be | |
12848 | considered to be the address of a function. */ | |
12849 | ||
12850 | static void | |
17a2f251 | 12851 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12852 | { |
12853 | char *name; | |
12854 | int c; | |
12855 | symbolS *symbolP; | |
12856 | flagword flag; | |
12857 | ||
8a06b769 | 12858 | do |
252b5132 | 12859 | { |
8a06b769 | 12860 | name = input_line_pointer; |
252b5132 | 12861 | c = get_symbol_end (); |
8a06b769 TS |
12862 | symbolP = symbol_find_or_make (name); |
12863 | S_SET_EXTERNAL (symbolP); | |
12864 | ||
252b5132 | 12865 | *input_line_pointer = c; |
8a06b769 | 12866 | SKIP_WHITESPACE (); |
252b5132 | 12867 | |
8a06b769 TS |
12868 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12869 | being a function is apparently labelled as being an object. */ | |
12870 | flag = BSF_OBJECT; | |
252b5132 | 12871 | |
8a06b769 TS |
12872 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12873 | && (*input_line_pointer != ',')) | |
12874 | { | |
12875 | char *secname; | |
12876 | asection *sec; | |
12877 | ||
12878 | secname = input_line_pointer; | |
12879 | c = get_symbol_end (); | |
12880 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12881 | if (sec == NULL) | |
12882 | as_bad (_("%s: no such section"), secname); | |
12883 | *input_line_pointer = c; | |
12884 | ||
12885 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12886 | flag = BSF_FUNCTION; | |
12887 | } | |
12888 | ||
12889 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12890 | ||
12891 | c = *input_line_pointer; | |
12892 | if (c == ',') | |
12893 | { | |
12894 | input_line_pointer++; | |
12895 | SKIP_WHITESPACE (); | |
12896 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12897 | c = '\n'; | |
12898 | } | |
12899 | } | |
12900 | while (c == ','); | |
252b5132 | 12901 | |
252b5132 RH |
12902 | demand_empty_rest_of_line (); |
12903 | } | |
12904 | ||
12905 | static void | |
17a2f251 | 12906 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12907 | { |
12908 | char *opt; | |
12909 | char c; | |
12910 | ||
12911 | opt = input_line_pointer; | |
12912 | c = get_symbol_end (); | |
12913 | ||
12914 | if (*opt == 'O') | |
12915 | { | |
12916 | /* FIXME: What does this mean? */ | |
12917 | } | |
12918 | else if (strncmp (opt, "pic", 3) == 0) | |
12919 | { | |
12920 | int i; | |
12921 | ||
12922 | i = atoi (opt + 3); | |
12923 | if (i == 0) | |
12924 | mips_pic = NO_PIC; | |
12925 | else if (i == 2) | |
143d77c5 | 12926 | { |
252b5132 | 12927 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12928 | mips_abicalls = TRUE; |
12929 | } | |
252b5132 RH |
12930 | else |
12931 | as_bad (_(".option pic%d not supported"), i); | |
12932 | ||
4d0d148d | 12933 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12934 | { |
12935 | if (g_switch_seen && g_switch_value != 0) | |
12936 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12937 | g_switch_value = 0; | |
12938 | bfd_set_gp_size (stdoutput, 0); | |
12939 | } | |
12940 | } | |
12941 | else | |
12942 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12943 | ||
12944 | *input_line_pointer = c; | |
12945 | demand_empty_rest_of_line (); | |
12946 | } | |
12947 | ||
12948 | /* This structure is used to hold a stack of .set values. */ | |
12949 | ||
e972090a NC |
12950 | struct mips_option_stack |
12951 | { | |
252b5132 RH |
12952 | struct mips_option_stack *next; |
12953 | struct mips_set_options options; | |
12954 | }; | |
12955 | ||
12956 | static struct mips_option_stack *mips_opts_stack; | |
12957 | ||
12958 | /* Handle the .set pseudo-op. */ | |
12959 | ||
12960 | static void | |
17a2f251 | 12961 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12962 | { |
12963 | char *name = input_line_pointer, ch; | |
12964 | ||
12965 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12966 | ++input_line_pointer; |
252b5132 RH |
12967 | ch = *input_line_pointer; |
12968 | *input_line_pointer = '\0'; | |
12969 | ||
12970 | if (strcmp (name, "reorder") == 0) | |
12971 | { | |
7d10b47d RS |
12972 | if (mips_opts.noreorder) |
12973 | end_noreorder (); | |
252b5132 RH |
12974 | } |
12975 | else if (strcmp (name, "noreorder") == 0) | |
12976 | { | |
7d10b47d RS |
12977 | if (!mips_opts.noreorder) |
12978 | start_noreorder (); | |
252b5132 | 12979 | } |
741fe287 MR |
12980 | else if (strncmp (name, "at=", 3) == 0) |
12981 | { | |
12982 | char *s = name + 3; | |
12983 | ||
12984 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
12985 | as_bad (_("Unrecognized register name `%s'"), s); | |
12986 | } | |
252b5132 RH |
12987 | else if (strcmp (name, "at") == 0) |
12988 | { | |
741fe287 | 12989 | mips_opts.at = ATREG; |
252b5132 RH |
12990 | } |
12991 | else if (strcmp (name, "noat") == 0) | |
12992 | { | |
741fe287 | 12993 | mips_opts.at = ZERO; |
252b5132 RH |
12994 | } |
12995 | else if (strcmp (name, "macro") == 0) | |
12996 | { | |
12997 | mips_opts.warn_about_macros = 0; | |
12998 | } | |
12999 | else if (strcmp (name, "nomacro") == 0) | |
13000 | { | |
13001 | if (mips_opts.noreorder == 0) | |
13002 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
13003 | mips_opts.warn_about_macros = 1; | |
13004 | } | |
13005 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
13006 | { | |
13007 | mips_opts.nomove = 0; | |
13008 | } | |
13009 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
13010 | { | |
13011 | mips_opts.nomove = 1; | |
13012 | } | |
13013 | else if (strcmp (name, "bopt") == 0) | |
13014 | { | |
13015 | mips_opts.nobopt = 0; | |
13016 | } | |
13017 | else if (strcmp (name, "nobopt") == 0) | |
13018 | { | |
13019 | mips_opts.nobopt = 1; | |
13020 | } | |
ad3fea08 TS |
13021 | else if (strcmp (name, "gp=default") == 0) |
13022 | mips_opts.gp32 = file_mips_gp32; | |
13023 | else if (strcmp (name, "gp=32") == 0) | |
13024 | mips_opts.gp32 = 1; | |
13025 | else if (strcmp (name, "gp=64") == 0) | |
13026 | { | |
13027 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 13028 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
13029 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13030 | mips_opts.gp32 = 0; | |
13031 | } | |
13032 | else if (strcmp (name, "fp=default") == 0) | |
13033 | mips_opts.fp32 = file_mips_fp32; | |
13034 | else if (strcmp (name, "fp=32") == 0) | |
13035 | mips_opts.fp32 = 1; | |
13036 | else if (strcmp (name, "fp=64") == 0) | |
13037 | { | |
13038 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 13039 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
13040 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13041 | mips_opts.fp32 = 0; | |
13042 | } | |
037b32b9 AN |
13043 | else if (strcmp (name, "softfloat") == 0) |
13044 | mips_opts.soft_float = 1; | |
13045 | else if (strcmp (name, "hardfloat") == 0) | |
13046 | mips_opts.soft_float = 0; | |
13047 | else if (strcmp (name, "singlefloat") == 0) | |
13048 | mips_opts.single_float = 1; | |
13049 | else if (strcmp (name, "doublefloat") == 0) | |
13050 | mips_opts.single_float = 0; | |
252b5132 RH |
13051 | else if (strcmp (name, "mips16") == 0 |
13052 | || strcmp (name, "MIPS-16") == 0) | |
13053 | mips_opts.mips16 = 1; | |
13054 | else if (strcmp (name, "nomips16") == 0 | |
13055 | || strcmp (name, "noMIPS-16") == 0) | |
13056 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
13057 | else if (strcmp (name, "smartmips") == 0) |
13058 | { | |
ad3fea08 | 13059 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 13060 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
13061 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13062 | mips_opts.ase_smartmips = 1; | |
13063 | } | |
13064 | else if (strcmp (name, "nosmartmips") == 0) | |
13065 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
13066 | else if (strcmp (name, "mips3d") == 0) |
13067 | mips_opts.ase_mips3d = 1; | |
13068 | else if (strcmp (name, "nomips3d") == 0) | |
13069 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
13070 | else if (strcmp (name, "mdmx") == 0) |
13071 | mips_opts.ase_mdmx = 1; | |
13072 | else if (strcmp (name, "nomdmx") == 0) | |
13073 | mips_opts.ase_mdmx = 0; | |
74cd071d | 13074 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
13075 | { |
13076 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 13077 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
13078 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13079 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 13080 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 13081 | } |
74cd071d | 13082 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
13083 | { |
13084 | mips_opts.ase_dsp = 0; | |
13085 | mips_opts.ase_dspr2 = 0; | |
13086 | } | |
13087 | else if (strcmp (name, "dspr2") == 0) | |
13088 | { | |
13089 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 13090 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
13091 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13092 | mips_opts.ase_dspr2 = 1; | |
13093 | mips_opts.ase_dsp = 1; | |
13094 | } | |
13095 | else if (strcmp (name, "nodspr2") == 0) | |
13096 | { | |
13097 | mips_opts.ase_dspr2 = 0; | |
13098 | mips_opts.ase_dsp = 0; | |
13099 | } | |
ef2e4d86 | 13100 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
13101 | { |
13102 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 13103 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
13104 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13105 | mips_opts.ase_mt = 1; | |
13106 | } | |
ef2e4d86 CF |
13107 | else if (strcmp (name, "nomt") == 0) |
13108 | mips_opts.ase_mt = 0; | |
1a2c1fad | 13109 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 13110 | { |
af7ee8bf | 13111 | int reset = 0; |
252b5132 | 13112 | |
1a2c1fad CD |
13113 | /* Permit the user to change the ISA and architecture on the fly. |
13114 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 13115 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
13116 | { |
13117 | reset = 1; | |
13118 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 13119 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
13120 | } |
13121 | else if (strncmp (name, "arch=", 5) == 0) | |
13122 | { | |
13123 | const struct mips_cpu_info *p; | |
13124 | ||
13125 | p = mips_parse_cpu("internal use", name + 5); | |
13126 | if (!p) | |
13127 | as_bad (_("unknown architecture %s"), name + 5); | |
13128 | else | |
13129 | { | |
13130 | mips_opts.arch = p->cpu; | |
13131 | mips_opts.isa = p->isa; | |
13132 | } | |
13133 | } | |
81a21e38 TS |
13134 | else if (strncmp (name, "mips", 4) == 0) |
13135 | { | |
13136 | const struct mips_cpu_info *p; | |
13137 | ||
13138 | p = mips_parse_cpu("internal use", name); | |
13139 | if (!p) | |
13140 | as_bad (_("unknown ISA level %s"), name + 4); | |
13141 | else | |
13142 | { | |
13143 | mips_opts.arch = p->cpu; | |
13144 | mips_opts.isa = p->isa; | |
13145 | } | |
13146 | } | |
af7ee8bf | 13147 | else |
81a21e38 | 13148 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
13149 | |
13150 | switch (mips_opts.isa) | |
98d3f06f KH |
13151 | { |
13152 | case 0: | |
98d3f06f | 13153 | break; |
af7ee8bf CD |
13154 | case ISA_MIPS1: |
13155 | case ISA_MIPS2: | |
13156 | case ISA_MIPS32: | |
13157 | case ISA_MIPS32R2: | |
98d3f06f KH |
13158 | mips_opts.gp32 = 1; |
13159 | mips_opts.fp32 = 1; | |
13160 | break; | |
af7ee8bf CD |
13161 | case ISA_MIPS3: |
13162 | case ISA_MIPS4: | |
13163 | case ISA_MIPS5: | |
13164 | case ISA_MIPS64: | |
5f74bc13 | 13165 | case ISA_MIPS64R2: |
98d3f06f KH |
13166 | mips_opts.gp32 = 0; |
13167 | mips_opts.fp32 = 0; | |
13168 | break; | |
13169 | default: | |
13170 | as_bad (_("unknown ISA level %s"), name + 4); | |
13171 | break; | |
13172 | } | |
af7ee8bf | 13173 | if (reset) |
98d3f06f | 13174 | { |
af7ee8bf CD |
13175 | mips_opts.gp32 = file_mips_gp32; |
13176 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 13177 | } |
252b5132 RH |
13178 | } |
13179 | else if (strcmp (name, "autoextend") == 0) | |
13180 | mips_opts.noautoextend = 0; | |
13181 | else if (strcmp (name, "noautoextend") == 0) | |
13182 | mips_opts.noautoextend = 1; | |
13183 | else if (strcmp (name, "push") == 0) | |
13184 | { | |
13185 | struct mips_option_stack *s; | |
13186 | ||
13187 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
13188 | s->next = mips_opts_stack; | |
13189 | s->options = mips_opts; | |
13190 | mips_opts_stack = s; | |
13191 | } | |
13192 | else if (strcmp (name, "pop") == 0) | |
13193 | { | |
13194 | struct mips_option_stack *s; | |
13195 | ||
13196 | s = mips_opts_stack; | |
13197 | if (s == NULL) | |
13198 | as_bad (_(".set pop with no .set push")); | |
13199 | else | |
13200 | { | |
13201 | /* If we're changing the reorder mode we need to handle | |
13202 | delay slots correctly. */ | |
13203 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 13204 | start_noreorder (); |
252b5132 | 13205 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 13206 | end_noreorder (); |
252b5132 RH |
13207 | |
13208 | mips_opts = s->options; | |
13209 | mips_opts_stack = s->next; | |
13210 | free (s); | |
13211 | } | |
13212 | } | |
aed1a261 RS |
13213 | else if (strcmp (name, "sym32") == 0) |
13214 | mips_opts.sym32 = TRUE; | |
13215 | else if (strcmp (name, "nosym32") == 0) | |
13216 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
13217 | else if (strchr (name, ',')) |
13218 | { | |
13219 | /* Generic ".set" directive; use the generic handler. */ | |
13220 | *input_line_pointer = ch; | |
13221 | input_line_pointer = name; | |
13222 | s_set (0); | |
13223 | return; | |
13224 | } | |
252b5132 RH |
13225 | else |
13226 | { | |
13227 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
13228 | } | |
13229 | *input_line_pointer = ch; | |
13230 | demand_empty_rest_of_line (); | |
13231 | } | |
13232 | ||
13233 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
13234 | .option pic2. It means to generate SVR4 PIC calls. */ | |
13235 | ||
13236 | static void | |
17a2f251 | 13237 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13238 | { |
13239 | mips_pic = SVR4_PIC; | |
143d77c5 | 13240 | mips_abicalls = TRUE; |
4d0d148d TS |
13241 | |
13242 | if (g_switch_seen && g_switch_value != 0) | |
13243 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13244 | g_switch_value = 0; | |
13245 | ||
252b5132 RH |
13246 | bfd_set_gp_size (stdoutput, 0); |
13247 | demand_empty_rest_of_line (); | |
13248 | } | |
13249 | ||
13250 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
13251 | PIC code. It sets the $gp register for the function based on the | |
13252 | function address, which is in the register named in the argument. | |
13253 | This uses a relocation against _gp_disp, which is handled specially | |
13254 | by the linker. The result is: | |
13255 | lui $gp,%hi(_gp_disp) | |
13256 | addiu $gp,$gp,%lo(_gp_disp) | |
13257 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
13258 | The .cpload argument is normally $25 == $t9. |
13259 | ||
13260 | The -mno-shared option changes this to: | |
bbe506e8 TS |
13261 | lui $gp,%hi(__gnu_local_gp) |
13262 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
13263 | and the argument is ignored. This saves an instruction, but the |
13264 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
13265 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
13266 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
13267 | |
13268 | static void | |
17a2f251 | 13269 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13270 | { |
13271 | expressionS ex; | |
aa6975fb ILT |
13272 | int reg; |
13273 | int in_shared; | |
252b5132 | 13274 | |
6478892d TS |
13275 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
13276 | .cpload is ignored. */ | |
13277 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
13278 | { |
13279 | s_ignore (0); | |
13280 | return; | |
13281 | } | |
13282 | ||
d3ecfc59 | 13283 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
13284 | if (mips_opts.noreorder == 0) |
13285 | as_warn (_(".cpload not in noreorder section")); | |
13286 | ||
aa6975fb ILT |
13287 | reg = tc_get_register (0); |
13288 | ||
13289 | /* If we need to produce a 64-bit address, we are better off using | |
13290 | the default instruction sequence. */ | |
aed1a261 | 13291 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 13292 | |
252b5132 | 13293 | ex.X_op = O_symbol; |
bbe506e8 TS |
13294 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
13295 | "__gnu_local_gp"); | |
252b5132 RH |
13296 | ex.X_op_symbol = NULL; |
13297 | ex.X_add_number = 0; | |
13298 | ||
13299 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 13300 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 13301 | |
584892a6 | 13302 | macro_start (); |
67c0d1eb RS |
13303 | macro_build_lui (&ex, mips_gp_register); |
13304 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 13305 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
13306 | if (in_shared) |
13307 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
13308 | mips_gp_register, reg); | |
584892a6 | 13309 | macro_end (); |
252b5132 RH |
13310 | |
13311 | demand_empty_rest_of_line (); | |
13312 | } | |
13313 | ||
6478892d TS |
13314 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
13315 | .cpsetup $reg1, offset|$reg2, label | |
13316 | ||
13317 | If offset is given, this results in: | |
13318 | sd $gp, offset($sp) | |
956cd1d6 | 13319 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13320 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13321 | daddu $gp, $gp, $reg1 | |
6478892d TS |
13322 | |
13323 | If $reg2 is given, this results in: | |
13324 | daddu $reg2, $gp, $0 | |
956cd1d6 | 13325 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13326 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13327 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
13328 | $reg1 is normally $25 == $t9. |
13329 | ||
13330 | The -mno-shared option replaces the last three instructions with | |
13331 | lui $gp,%hi(_gp) | |
54f4ddb3 | 13332 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 13333 | |
6478892d | 13334 | static void |
17a2f251 | 13335 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13336 | { |
13337 | expressionS ex_off; | |
13338 | expressionS ex_sym; | |
13339 | int reg1; | |
6478892d | 13340 | |
8586fc66 | 13341 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
13342 | We also need NewABI support. */ |
13343 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13344 | { | |
13345 | s_ignore (0); | |
13346 | return; | |
13347 | } | |
13348 | ||
13349 | reg1 = tc_get_register (0); | |
13350 | SKIP_WHITESPACE (); | |
13351 | if (*input_line_pointer != ',') | |
13352 | { | |
13353 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13354 | return; | |
13355 | } | |
13356 | else | |
80245285 | 13357 | ++input_line_pointer; |
6478892d TS |
13358 | SKIP_WHITESPACE (); |
13359 | if (*input_line_pointer == '$') | |
80245285 TS |
13360 | { |
13361 | mips_cpreturn_register = tc_get_register (0); | |
13362 | mips_cpreturn_offset = -1; | |
13363 | } | |
6478892d | 13364 | else |
80245285 TS |
13365 | { |
13366 | mips_cpreturn_offset = get_absolute_expression (); | |
13367 | mips_cpreturn_register = -1; | |
13368 | } | |
6478892d TS |
13369 | SKIP_WHITESPACE (); |
13370 | if (*input_line_pointer != ',') | |
13371 | { | |
13372 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13373 | return; | |
13374 | } | |
13375 | else | |
f9419b05 | 13376 | ++input_line_pointer; |
6478892d | 13377 | SKIP_WHITESPACE (); |
f21f8242 | 13378 | expression (&ex_sym); |
6478892d | 13379 | |
584892a6 | 13380 | macro_start (); |
6478892d TS |
13381 | if (mips_cpreturn_register == -1) |
13382 | { | |
13383 | ex_off.X_op = O_constant; | |
13384 | ex_off.X_add_symbol = NULL; | |
13385 | ex_off.X_op_symbol = NULL; | |
13386 | ex_off.X_add_number = mips_cpreturn_offset; | |
13387 | ||
67c0d1eb | 13388 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13389 | BFD_RELOC_LO16, SP); |
6478892d TS |
13390 | } |
13391 | else | |
67c0d1eb | 13392 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13393 | mips_gp_register, 0); |
6478892d | 13394 | |
aed1a261 | 13395 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13396 | { |
13397 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13398 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13399 | BFD_RELOC_HI16_S); | |
13400 | ||
13401 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13402 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13403 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13404 | ||
13405 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13406 | mips_gp_register, reg1); | |
13407 | } | |
13408 | else | |
13409 | { | |
13410 | expressionS ex; | |
13411 | ||
13412 | ex.X_op = O_symbol; | |
4184909a | 13413 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13414 | ex.X_op_symbol = NULL; |
13415 | ex.X_add_number = 0; | |
6e1304d8 | 13416 | |
aa6975fb ILT |
13417 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13418 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13419 | ||
13420 | macro_build_lui (&ex, mips_gp_register); | |
13421 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13422 | mips_gp_register, BFD_RELOC_LO16); | |
13423 | } | |
f21f8242 | 13424 | |
584892a6 | 13425 | macro_end (); |
6478892d TS |
13426 | |
13427 | demand_empty_rest_of_line (); | |
13428 | } | |
13429 | ||
13430 | static void | |
17a2f251 | 13431 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13432 | { |
13433 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13434 | .cplocal is ignored. */ |
6478892d TS |
13435 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13436 | { | |
13437 | s_ignore (0); | |
13438 | return; | |
13439 | } | |
13440 | ||
13441 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13442 | demand_empty_rest_of_line (); |
6478892d TS |
13443 | } |
13444 | ||
252b5132 RH |
13445 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13446 | offset from $sp. The offset is remembered, and after making a PIC | |
13447 | call $gp is restored from that location. */ | |
13448 | ||
13449 | static void | |
17a2f251 | 13450 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13451 | { |
13452 | expressionS ex; | |
252b5132 | 13453 | |
6478892d | 13454 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13455 | .cprestore is ignored. */ |
6478892d | 13456 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13457 | { |
13458 | s_ignore (0); | |
13459 | return; | |
13460 | } | |
13461 | ||
13462 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13463 | mips_cprestore_valid = 1; |
252b5132 RH |
13464 | |
13465 | ex.X_op = O_constant; | |
13466 | ex.X_add_symbol = NULL; | |
13467 | ex.X_op_symbol = NULL; | |
13468 | ex.X_add_number = mips_cprestore_offset; | |
13469 | ||
584892a6 | 13470 | macro_start (); |
67c0d1eb RS |
13471 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13472 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13473 | macro_end (); |
252b5132 RH |
13474 | |
13475 | demand_empty_rest_of_line (); | |
13476 | } | |
13477 | ||
6478892d | 13478 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13479 | was given in the preceding .cpsetup, it results in: |
6478892d | 13480 | ld $gp, offset($sp) |
76b3015f | 13481 | |
6478892d | 13482 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13483 | daddu $gp, $reg2, $0 */ |
13484 | ||
6478892d | 13485 | static void |
17a2f251 | 13486 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13487 | { |
13488 | expressionS ex; | |
6478892d TS |
13489 | |
13490 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13491 | We also need NewABI support. */ | |
13492 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13493 | { | |
13494 | s_ignore (0); | |
13495 | return; | |
13496 | } | |
13497 | ||
584892a6 | 13498 | macro_start (); |
6478892d TS |
13499 | if (mips_cpreturn_register == -1) |
13500 | { | |
13501 | ex.X_op = O_constant; | |
13502 | ex.X_add_symbol = NULL; | |
13503 | ex.X_op_symbol = NULL; | |
13504 | ex.X_add_number = mips_cpreturn_offset; | |
13505 | ||
67c0d1eb | 13506 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13507 | } |
13508 | else | |
67c0d1eb | 13509 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13510 | mips_cpreturn_register, 0); |
584892a6 | 13511 | macro_end (); |
6478892d TS |
13512 | |
13513 | demand_empty_rest_of_line (); | |
13514 | } | |
13515 | ||
741d6ea8 JM |
13516 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13517 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13518 | use in DWARF debug information. */ | |
13519 | ||
13520 | static void | |
13521 | s_dtprel_internal (size_t bytes) | |
13522 | { | |
13523 | expressionS ex; | |
13524 | char *p; | |
13525 | ||
13526 | expression (&ex); | |
13527 | ||
13528 | if (ex.X_op != O_symbol) | |
13529 | { | |
13530 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13531 | ? ".dtpreldword" | |
13532 | : ".dtprelword")); | |
13533 | ignore_rest_of_line (); | |
13534 | } | |
13535 | ||
13536 | p = frag_more (bytes); | |
13537 | md_number_to_chars (p, 0, bytes); | |
13538 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13539 | (bytes == 8 | |
13540 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13541 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13542 | ||
13543 | demand_empty_rest_of_line (); | |
13544 | } | |
13545 | ||
13546 | /* Handle .dtprelword. */ | |
13547 | ||
13548 | static void | |
13549 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13550 | { | |
13551 | s_dtprel_internal (4); | |
13552 | } | |
13553 | ||
13554 | /* Handle .dtpreldword. */ | |
13555 | ||
13556 | static void | |
13557 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13558 | { | |
13559 | s_dtprel_internal (8); | |
13560 | } | |
13561 | ||
6478892d TS |
13562 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13563 | code. It sets the offset to use in gp_rel relocations. */ | |
13564 | ||
13565 | static void | |
17a2f251 | 13566 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13567 | { |
13568 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13569 | We also need NewABI support. */ | |
13570 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13571 | { | |
13572 | s_ignore (0); | |
13573 | return; | |
13574 | } | |
13575 | ||
def2e0dd | 13576 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13577 | |
13578 | demand_empty_rest_of_line (); | |
13579 | } | |
13580 | ||
252b5132 RH |
13581 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13582 | code. It generates a 32 bit GP relative reloc. */ | |
13583 | ||
13584 | static void | |
17a2f251 | 13585 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13586 | { |
a8dbcb85 TS |
13587 | segment_info_type *si; |
13588 | struct insn_label_list *l; | |
252b5132 RH |
13589 | symbolS *label; |
13590 | expressionS ex; | |
13591 | char *p; | |
13592 | ||
13593 | /* When not generating PIC code, this is treated as .word. */ | |
13594 | if (mips_pic != SVR4_PIC) | |
13595 | { | |
13596 | s_cons (2); | |
13597 | return; | |
13598 | } | |
13599 | ||
a8dbcb85 TS |
13600 | si = seg_info (now_seg); |
13601 | l = si->label_list; | |
13602 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13603 | mips_emit_delays (); |
252b5132 RH |
13604 | if (auto_align) |
13605 | mips_align (2, 0, label); | |
252b5132 RH |
13606 | |
13607 | expression (&ex); | |
a1facbec | 13608 | mips_clear_insn_labels (); |
252b5132 RH |
13609 | |
13610 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13611 | { | |
13612 | as_bad (_("Unsupported use of .gpword")); | |
13613 | ignore_rest_of_line (); | |
13614 | } | |
13615 | ||
13616 | p = frag_more (4); | |
17a2f251 | 13617 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13618 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13619 | BFD_RELOC_GPREL32); |
252b5132 RH |
13620 | |
13621 | demand_empty_rest_of_line (); | |
13622 | } | |
13623 | ||
10181a0d | 13624 | static void |
17a2f251 | 13625 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13626 | { |
a8dbcb85 TS |
13627 | segment_info_type *si; |
13628 | struct insn_label_list *l; | |
10181a0d AO |
13629 | symbolS *label; |
13630 | expressionS ex; | |
13631 | char *p; | |
13632 | ||
13633 | /* When not generating PIC code, this is treated as .dword. */ | |
13634 | if (mips_pic != SVR4_PIC) | |
13635 | { | |
13636 | s_cons (3); | |
13637 | return; | |
13638 | } | |
13639 | ||
a8dbcb85 TS |
13640 | si = seg_info (now_seg); |
13641 | l = si->label_list; | |
13642 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13643 | mips_emit_delays (); |
10181a0d AO |
13644 | if (auto_align) |
13645 | mips_align (3, 0, label); | |
10181a0d AO |
13646 | |
13647 | expression (&ex); | |
a1facbec | 13648 | mips_clear_insn_labels (); |
10181a0d AO |
13649 | |
13650 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13651 | { | |
13652 | as_bad (_("Unsupported use of .gpdword")); | |
13653 | ignore_rest_of_line (); | |
13654 | } | |
13655 | ||
13656 | p = frag_more (8); | |
17a2f251 | 13657 | md_number_to_chars (p, 0, 8); |
a105a300 | 13658 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13659 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13660 | |
13661 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13662 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13663 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13664 | |
13665 | demand_empty_rest_of_line (); | |
13666 | } | |
13667 | ||
252b5132 RH |
13668 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13669 | tables in SVR4 PIC code. */ | |
13670 | ||
13671 | static void | |
17a2f251 | 13672 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13673 | { |
252b5132 RH |
13674 | int reg; |
13675 | ||
10181a0d AO |
13676 | /* This is ignored when not generating SVR4 PIC code. */ |
13677 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13678 | { |
13679 | s_ignore (0); | |
13680 | return; | |
13681 | } | |
13682 | ||
13683 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13684 | macro_start (); |
252b5132 | 13685 | reg = tc_get_register (0); |
67c0d1eb | 13686 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13687 | macro_end (); |
252b5132 | 13688 | |
bdaaa2e1 | 13689 | demand_empty_rest_of_line (); |
252b5132 RH |
13690 | } |
13691 | ||
13692 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13693 | mips16 mode. This permits the linker to handle them specially, | |
13694 | such as generating jalx instructions when needed. We also make | |
13695 | them odd for the duration of the assembly, in order to generate the | |
13696 | right sort of code. We will make them even in the adjust_symtab | |
13697 | routine, while leaving them marked. This is convenient for the | |
13698 | debugger and the disassembler. The linker knows to make them odd | |
13699 | again. */ | |
13700 | ||
13701 | static void | |
17a2f251 | 13702 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13703 | { |
f9419b05 | 13704 | mips16_mark_labels (); |
252b5132 RH |
13705 | |
13706 | demand_empty_rest_of_line (); | |
13707 | } | |
13708 | ||
13709 | /* Handle a .stabn directive. We need these in order to mark a label | |
13710 | as being a mips16 text label correctly. Sometimes the compiler | |
13711 | will emit a label, followed by a .stabn, and then switch sections. | |
13712 | If the label and .stabn are in mips16 mode, then the label is | |
13713 | really a mips16 text label. */ | |
13714 | ||
13715 | static void | |
17a2f251 | 13716 | s_mips_stab (int type) |
252b5132 | 13717 | { |
f9419b05 | 13718 | if (type == 'n') |
252b5132 RH |
13719 | mips16_mark_labels (); |
13720 | ||
13721 | s_stab (type); | |
13722 | } | |
13723 | ||
54f4ddb3 | 13724 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13725 | |
13726 | static void | |
17a2f251 | 13727 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13728 | { |
13729 | char *name; | |
13730 | int c; | |
13731 | symbolS *symbolP; | |
13732 | expressionS exp; | |
13733 | ||
13734 | name = input_line_pointer; | |
13735 | c = get_symbol_end (); | |
13736 | symbolP = symbol_find_or_make (name); | |
13737 | S_SET_WEAK (symbolP); | |
13738 | *input_line_pointer = c; | |
13739 | ||
13740 | SKIP_WHITESPACE (); | |
13741 | ||
13742 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13743 | { | |
13744 | if (S_IS_DEFINED (symbolP)) | |
13745 | { | |
20203fb9 | 13746 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
13747 | S_GET_NAME (symbolP)); |
13748 | ignore_rest_of_line (); | |
13749 | return; | |
13750 | } | |
bdaaa2e1 | 13751 | |
252b5132 RH |
13752 | if (*input_line_pointer == ',') |
13753 | { | |
13754 | ++input_line_pointer; | |
13755 | SKIP_WHITESPACE (); | |
13756 | } | |
bdaaa2e1 | 13757 | |
252b5132 RH |
13758 | expression (&exp); |
13759 | if (exp.X_op != O_symbol) | |
13760 | { | |
20203fb9 | 13761 | as_bad (_("bad .weakext directive")); |
98d3f06f | 13762 | ignore_rest_of_line (); |
252b5132 RH |
13763 | return; |
13764 | } | |
49309057 | 13765 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13766 | } |
13767 | ||
13768 | demand_empty_rest_of_line (); | |
13769 | } | |
13770 | ||
13771 | /* Parse a register string into a number. Called from the ECOFF code | |
13772 | to parse .frame. The argument is non-zero if this is the frame | |
13773 | register, so that we can record it in mips_frame_reg. */ | |
13774 | ||
13775 | int | |
17a2f251 | 13776 | tc_get_register (int frame) |
252b5132 | 13777 | { |
707bfff6 | 13778 | unsigned int reg; |
252b5132 RH |
13779 | |
13780 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13781 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13782 | reg = 0; | |
252b5132 | 13783 | if (frame) |
7a621144 DJ |
13784 | { |
13785 | mips_frame_reg = reg != 0 ? reg : SP; | |
13786 | mips_frame_reg_valid = 1; | |
13787 | mips_cprestore_valid = 0; | |
13788 | } | |
252b5132 RH |
13789 | return reg; |
13790 | } | |
13791 | ||
13792 | valueT | |
17a2f251 | 13793 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13794 | { |
13795 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13796 | ||
b4c71f56 TS |
13797 | if (IS_ELF) |
13798 | { | |
13799 | /* We don't need to align ELF sections to the full alignment. | |
13800 | However, Irix 5 may prefer that we align them at least to a 16 | |
13801 | byte boundary. We don't bother to align the sections if we | |
13802 | are targeted for an embedded system. */ | |
c41e87e3 | 13803 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13804 | return addr; |
13805 | if (align > 4) | |
13806 | align = 4; | |
13807 | } | |
252b5132 RH |
13808 | |
13809 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13810 | } | |
13811 | ||
13812 | /* Utility routine, called from above as well. If called while the | |
13813 | input file is still being read, it's only an approximation. (For | |
13814 | example, a symbol may later become defined which appeared to be | |
13815 | undefined earlier.) */ | |
13816 | ||
13817 | static int | |
17a2f251 | 13818 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13819 | { |
13820 | if (sym == 0) | |
13821 | return 0; | |
13822 | ||
4d0d148d | 13823 | if (g_switch_value > 0) |
252b5132 RH |
13824 | { |
13825 | const char *symname; | |
13826 | int change; | |
13827 | ||
c9914766 | 13828 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13829 | register. It can be if it is smaller than the -G size or if |
13830 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13831 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13832 | they can. */ |
13833 | symname = S_GET_NAME (sym); | |
13834 | if (symname != (const char *) NULL | |
13835 | && (strcmp (symname, "eprol") == 0 | |
13836 | || strcmp (symname, "etext") == 0 | |
13837 | || strcmp (symname, "_gp") == 0 | |
13838 | || strcmp (symname, "edata") == 0 | |
13839 | || strcmp (symname, "_fbss") == 0 | |
13840 | || strcmp (symname, "_fdata") == 0 | |
13841 | || strcmp (symname, "_ftext") == 0 | |
13842 | || strcmp (symname, "end") == 0 | |
13843 | || strcmp (symname, "_gp_disp") == 0)) | |
13844 | change = 1; | |
13845 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13846 | && (0 | |
13847 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13848 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13849 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13850 | <= g_switch_value)) | |
252b5132 RH |
13851 | #endif |
13852 | /* We must defer this decision until after the whole | |
13853 | file has been read, since there might be a .extern | |
13854 | after the first use of this symbol. */ | |
13855 | || (before_relaxing | |
13856 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13857 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13858 | #endif |
13859 | && S_GET_VALUE (sym) == 0) | |
13860 | || (S_GET_VALUE (sym) != 0 | |
13861 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13862 | change = 0; | |
13863 | else | |
13864 | { | |
13865 | const char *segname; | |
13866 | ||
13867 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 13868 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
13869 | && strcmp (segname, ".lit4") != 0); |
13870 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13871 | && strcmp (segname, ".sbss") != 0 |
13872 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13873 | && strncmp (segname, ".sbss.", 6) != 0 |
13874 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13875 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13876 | } |
13877 | return change; | |
13878 | } | |
13879 | else | |
c9914766 | 13880 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13881 | return 1; |
13882 | } | |
13883 | ||
5919d012 RS |
13884 | |
13885 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13886 | ||
13887 | static bfd_boolean | |
17a2f251 | 13888 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13889 | { |
13890 | asection *symsec; | |
5919d012 RS |
13891 | |
13892 | /* Handle the case of a symbol equated to another symbol. */ | |
13893 | while (symbol_equated_reloc_p (sym)) | |
13894 | { | |
13895 | symbolS *n; | |
13896 | ||
5f0fe04b | 13897 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13898 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13899 | if (n == sym) | |
13900 | break; | |
13901 | sym = n; | |
13902 | } | |
13903 | ||
df1f3cda DD |
13904 | if (symbol_section_p (sym)) |
13905 | return TRUE; | |
13906 | ||
5919d012 RS |
13907 | symsec = S_GET_SEGMENT (sym); |
13908 | ||
5919d012 RS |
13909 | /* This must duplicate the test in adjust_reloc_syms. */ |
13910 | return (symsec != &bfd_und_section | |
13911 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13912 | && !bfd_is_com_section (symsec) |
13913 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13914 | #ifdef OBJ_ELF |
13915 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13916 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13917 | #endif |
13918 | ); | |
13919 | } | |
13920 | ||
13921 | ||
252b5132 RH |
13922 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13923 | extended opcode. SEC is the section the frag is in. */ | |
13924 | ||
13925 | static int | |
17a2f251 | 13926 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13927 | { |
13928 | int type; | |
3994f87e | 13929 | const struct mips16_immed_operand *op; |
252b5132 RH |
13930 | offsetT val; |
13931 | int mintiny, maxtiny; | |
13932 | segT symsec; | |
98aa84af | 13933 | fragS *sym_frag; |
252b5132 RH |
13934 | |
13935 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13936 | return 0; | |
13937 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13938 | return 1; | |
13939 | ||
13940 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13941 | op = mips16_immed_operands; | |
13942 | while (op->type != type) | |
13943 | { | |
13944 | ++op; | |
9c2799c2 | 13945 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13946 | } |
13947 | ||
13948 | if (op->unsp) | |
13949 | { | |
13950 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13951 | { | |
13952 | mintiny = 1; | |
13953 | maxtiny = 1 << op->nbits; | |
13954 | } | |
13955 | else | |
13956 | { | |
13957 | mintiny = 0; | |
13958 | maxtiny = (1 << op->nbits) - 1; | |
13959 | } | |
13960 | } | |
13961 | else | |
13962 | { | |
13963 | mintiny = - (1 << (op->nbits - 1)); | |
13964 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13965 | } | |
13966 | ||
98aa84af | 13967 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13968 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13969 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13970 | |
13971 | if (op->pcrel) | |
13972 | { | |
13973 | addressT addr; | |
13974 | ||
13975 | /* We won't have the section when we are called from | |
13976 | mips_relax_frag. However, we will always have been called | |
13977 | from md_estimate_size_before_relax first. If this is a | |
13978 | branch to a different section, we mark it as such. If SEC is | |
13979 | NULL, and the frag is not marked, then it must be a branch to | |
13980 | the same section. */ | |
13981 | if (sec == NULL) | |
13982 | { | |
13983 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13984 | return 1; | |
13985 | } | |
13986 | else | |
13987 | { | |
98aa84af | 13988 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13989 | if (symsec != sec) |
13990 | { | |
13991 | fragp->fr_subtype = | |
13992 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13993 | ||
13994 | /* FIXME: We should support this, and let the linker | |
13995 | catch branches and loads that are out of range. */ | |
13996 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13997 | _("unsupported PC relative reference to different section")); | |
13998 | ||
13999 | return 1; | |
14000 | } | |
98aa84af AM |
14001 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
14002 | /* Assume non-extended on the first relaxation pass. | |
14003 | The address we have calculated will be bogus if this is | |
14004 | a forward branch to another frag, as the forward frag | |
14005 | will have fr_address == 0. */ | |
14006 | return 0; | |
252b5132 RH |
14007 | } |
14008 | ||
14009 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
14010 | the same section. If the relax_marker of the symbol fragment |
14011 | differs from the relax_marker of this fragment, we have not | |
14012 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
14013 | in STRETCH in order to get a better estimate of the address. |
14014 | This particularly matters because of the shift bits. */ | |
14015 | if (stretch != 0 | |
98aa84af | 14016 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
14017 | { |
14018 | fragS *f; | |
14019 | ||
14020 | /* Adjust stretch for any alignment frag. Note that if have | |
14021 | been expanding the earlier code, the symbol may be | |
14022 | defined in what appears to be an earlier frag. FIXME: | |
14023 | This doesn't handle the fr_subtype field, which specifies | |
14024 | a maximum number of bytes to skip when doing an | |
14025 | alignment. */ | |
98aa84af | 14026 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
14027 | { |
14028 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
14029 | { | |
14030 | if (stretch < 0) | |
14031 | stretch = - ((- stretch) | |
14032 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
14033 | else | |
14034 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
14035 | if (stretch == 0) | |
14036 | break; | |
14037 | } | |
14038 | } | |
14039 | if (f != NULL) | |
14040 | val += stretch; | |
14041 | } | |
14042 | ||
14043 | addr = fragp->fr_address + fragp->fr_fix; | |
14044 | ||
14045 | /* The base address rules are complicated. The base address of | |
14046 | a branch is the following instruction. The base address of a | |
14047 | PC relative load or add is the instruction itself, but if it | |
14048 | is in a delay slot (in which case it can not be extended) use | |
14049 | the address of the instruction whose delay slot it is in. */ | |
14050 | if (type == 'p' || type == 'q') | |
14051 | { | |
14052 | addr += 2; | |
14053 | ||
14054 | /* If we are currently assuming that this frag should be | |
14055 | extended, then, the current address is two bytes | |
bdaaa2e1 | 14056 | higher. */ |
252b5132 RH |
14057 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
14058 | addr += 2; | |
14059 | ||
14060 | /* Ignore the low bit in the target, since it will be set | |
14061 | for a text label. */ | |
14062 | if ((val & 1) != 0) | |
14063 | --val; | |
14064 | } | |
14065 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14066 | addr -= 4; | |
14067 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14068 | addr -= 2; | |
14069 | ||
14070 | val -= addr & ~ ((1 << op->shift) - 1); | |
14071 | ||
14072 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14073 | if (type == 'p' || type == 'q') | |
14074 | val /= 2; | |
14075 | ||
14076 | /* If any of the shifted bits are set, we must use an extended | |
14077 | opcode. If the address depends on the size of this | |
14078 | instruction, this can lead to a loop, so we arrange to always | |
14079 | use an extended opcode. We only check this when we are in | |
14080 | the main relaxation loop, when SEC is NULL. */ | |
14081 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
14082 | { | |
14083 | fragp->fr_subtype = | |
14084 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14085 | return 1; | |
14086 | } | |
14087 | ||
14088 | /* If we are about to mark a frag as extended because the value | |
14089 | is precisely maxtiny + 1, then there is a chance of an | |
14090 | infinite loop as in the following code: | |
14091 | la $4,foo | |
14092 | .skip 1020 | |
14093 | .align 2 | |
14094 | foo: | |
14095 | In this case when the la is extended, foo is 0x3fc bytes | |
14096 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
14097 | the la must be extended. To avoid this loop, we mark the | |
14098 | frag as extended if it was small, and is about to become | |
14099 | extended with a value of maxtiny + 1. */ | |
14100 | if (val == ((maxtiny + 1) << op->shift) | |
14101 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
14102 | && sec == NULL) | |
14103 | { | |
14104 | fragp->fr_subtype = | |
14105 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14106 | return 1; | |
14107 | } | |
14108 | } | |
14109 | else if (symsec != absolute_section && sec != NULL) | |
14110 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
14111 | ||
14112 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14113 | || val < (mintiny << op->shift) | |
14114 | || val > (maxtiny << op->shift)) | |
14115 | return 1; | |
14116 | else | |
14117 | return 0; | |
14118 | } | |
14119 | ||
4a6a3df4 AO |
14120 | /* Compute the length of a branch sequence, and adjust the |
14121 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
14122 | worst-case length is computed, with UPDATE being used to indicate | |
14123 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
14124 | branch is to be computed. */ | |
14125 | static int | |
17a2f251 | 14126 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 14127 | { |
b34976b6 | 14128 | bfd_boolean toofar; |
4a6a3df4 AO |
14129 | int length; |
14130 | ||
14131 | if (fragp | |
14132 | && S_IS_DEFINED (fragp->fr_symbol) | |
14133 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
14134 | { | |
14135 | addressT addr; | |
14136 | offsetT val; | |
14137 | ||
14138 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
14139 | ||
14140 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
14141 | ||
14142 | val -= addr; | |
14143 | ||
14144 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
14145 | } | |
14146 | else if (fragp) | |
14147 | /* If the symbol is not defined or it's in a different segment, | |
14148 | assume the user knows what's going on and emit a short | |
14149 | branch. */ | |
b34976b6 | 14150 | toofar = FALSE; |
4a6a3df4 | 14151 | else |
b34976b6 | 14152 | toofar = TRUE; |
4a6a3df4 AO |
14153 | |
14154 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
14155 | fragp->fr_subtype | |
66b3e8da MR |
14156 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
14157 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
14158 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
14159 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
14160 | toofar); | |
14161 | ||
14162 | length = 4; | |
14163 | if (toofar) | |
14164 | { | |
14165 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
14166 | length += 8; | |
14167 | ||
14168 | if (mips_pic != NO_PIC) | |
14169 | { | |
14170 | /* Additional space for PIC loading of target address. */ | |
14171 | length += 8; | |
14172 | if (mips_opts.isa == ISA_MIPS1) | |
14173 | /* Additional space for $at-stabilizing nop. */ | |
14174 | length += 4; | |
14175 | } | |
14176 | ||
14177 | /* If branch is conditional. */ | |
14178 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
14179 | length += 8; | |
14180 | } | |
b34976b6 | 14181 | |
4a6a3df4 AO |
14182 | return length; |
14183 | } | |
14184 | ||
252b5132 RH |
14185 | /* Estimate the size of a frag before relaxing. Unless this is the |
14186 | mips16, we are not really relaxing here, and the final size is | |
14187 | encoded in the subtype information. For the mips16, we have to | |
14188 | decide whether we are using an extended opcode or not. */ | |
14189 | ||
252b5132 | 14190 | int |
17a2f251 | 14191 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 14192 | { |
5919d012 | 14193 | int change; |
252b5132 | 14194 | |
4a6a3df4 AO |
14195 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14196 | { | |
14197 | ||
b34976b6 AM |
14198 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
14199 | ||
4a6a3df4 AO |
14200 | return fragp->fr_var; |
14201 | } | |
14202 | ||
252b5132 | 14203 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
14204 | /* We don't want to modify the EXTENDED bit here; it might get us |
14205 | into infinite loops. We change it only in mips_relax_frag(). */ | |
14206 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
14207 | |
14208 | if (mips_pic == NO_PIC) | |
5919d012 | 14209 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 14210 | else if (mips_pic == SVR4_PIC) |
5919d012 | 14211 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
14212 | else if (mips_pic == VXWORKS_PIC) |
14213 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
14214 | change = 0; | |
252b5132 RH |
14215 | else |
14216 | abort (); | |
14217 | ||
14218 | if (change) | |
14219 | { | |
4d7206a2 | 14220 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 14221 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 14222 | } |
4d7206a2 RS |
14223 | else |
14224 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
14225 | } |
14226 | ||
14227 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 14228 | should be converted into a reloc against a section. */ |
252b5132 RH |
14229 | |
14230 | int | |
17a2f251 | 14231 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 14232 | { |
252b5132 RH |
14233 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14234 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14235 | return 0; | |
a161fe53 | 14236 | |
252b5132 RH |
14237 | if (fixp->fx_addsy == NULL) |
14238 | return 1; | |
a161fe53 | 14239 | |
de7e6852 RS |
14240 | /* If symbol SYM is in a mergeable section, relocations of the form |
14241 | SYM + 0 can usually be made section-relative. The mergeable data | |
14242 | is then identified by the section offset rather than by the symbol. | |
14243 | ||
14244 | However, if we're generating REL LO16 relocations, the offset is split | |
14245 | between the LO16 and parterning high part relocation. The linker will | |
14246 | need to recalculate the complete offset in order to correctly identify | |
14247 | the merge data. | |
14248 | ||
14249 | The linker has traditionally not looked for the parterning high part | |
14250 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
14251 | placed anywhere. Rather than break backwards compatibility by changing | |
14252 | this, it seems better not to force the issue, and instead keep the | |
14253 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 14254 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 14255 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
14256 | && HAVE_IN_PLACE_ADDENDS |
14257 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
14258 | return 0; | |
14259 | ||
ce70d90a MR |
14260 | /* There is no place to store an in-place offset for JALR relocations. |
14261 | Likewise an in-range offset of PC-relative relocations may overflow | |
14262 | the in-place relocatable field if recalculated against the start | |
14263 | address of the symbol's containing section. */ | |
14264 | if (HAVE_IN_PLACE_ADDENDS | |
14265 | && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR)) | |
1180b5a4 RS |
14266 | return 0; |
14267 | ||
252b5132 | 14268 | #ifdef OBJ_ELF |
b314ec0e RS |
14269 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
14270 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
14271 | relocations against MIPS16 functions; in this case, the stub becomes | |
14272 | the function's canonical address. | |
14273 | ||
14274 | Floating-point stubs are stored in unique .mips16.call.* or | |
14275 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
14276 | the first relocation in section S must be against F; this is how the | |
14277 | linker determines the target function. All relocations that might | |
14278 | resolve to T must also be against F. We therefore have the following | |
14279 | restrictions, which are given in an intentionally-redundant way: | |
14280 | ||
14281 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
14282 | symbols. | |
14283 | ||
14284 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
14285 | if that stub might be used. | |
14286 | ||
14287 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
14288 | symbols. | |
14289 | ||
14290 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
14291 | that stub might be used. | |
14292 | ||
14293 | There is a further restriction: | |
14294 | ||
14295 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
14296 | on targets with in-place addends; the relocation field cannot | |
14297 | encode the low bit. | |
14298 | ||
14299 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
14300 | against a MIPS16 symbol. | |
14301 | ||
14302 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
14303 | relocation against some symbol R, no relocation against R may be | |
14304 | reduced. (Note that this deals with (2) as well as (1) because | |
14305 | relocations against global symbols will never be reduced on ELF | |
14306 | targets.) This approach is a little simpler than trying to detect | |
14307 | stub sections, and gives the "all or nothing" per-symbol consistency | |
14308 | that we have for MIPS16 symbols. */ | |
f43abd2b | 14309 | if (IS_ELF |
b314ec0e | 14310 | && fixp->fx_subsy == NULL |
30c09090 | 14311 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
b314ec0e | 14312 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 RH |
14313 | return 0; |
14314 | #endif | |
a161fe53 | 14315 | |
252b5132 RH |
14316 | return 1; |
14317 | } | |
14318 | ||
14319 | /* Translate internal representation of relocation info to BFD target | |
14320 | format. */ | |
14321 | ||
14322 | arelent ** | |
17a2f251 | 14323 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14324 | { |
14325 | static arelent *retval[4]; | |
14326 | arelent *reloc; | |
14327 | bfd_reloc_code_real_type code; | |
14328 | ||
4b0cff4e TS |
14329 | memset (retval, 0, sizeof(retval)); |
14330 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
14331 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
14332 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
14333 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
14334 | ||
bad36eac DJ |
14335 | if (fixp->fx_pcrel) |
14336 | { | |
9c2799c2 | 14337 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); |
bad36eac DJ |
14338 | |
14339 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
14340 | Relocations want only the symbol offset. */ | |
14341 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 14342 | if (!IS_ELF) |
bad36eac DJ |
14343 | { |
14344 | /* A gruesome hack which is a result of the gruesome gas | |
14345 | reloc handling. What's worse, for COFF (as opposed to | |
14346 | ECOFF), we might need yet another copy of reloc->address. | |
14347 | See bfd_install_relocation. */ | |
14348 | reloc->addend += reloc->address; | |
14349 | } | |
14350 | } | |
14351 | else | |
14352 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 14353 | |
438c16b8 TS |
14354 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
14355 | entry to be used in the relocation's section offset. */ | |
14356 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
14357 | { |
14358 | reloc->address = reloc->addend; | |
14359 | reloc->addend = 0; | |
14360 | } | |
14361 | ||
252b5132 | 14362 | code = fixp->fx_r_type; |
252b5132 | 14363 | |
bad36eac | 14364 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
14365 | if (reloc->howto == NULL) |
14366 | { | |
14367 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14368 | _("Can not represent %s relocation in this object file format"), | |
14369 | bfd_get_reloc_code_name (code)); | |
14370 | retval[0] = NULL; | |
14371 | } | |
14372 | ||
14373 | return retval; | |
14374 | } | |
14375 | ||
14376 | /* Relax a machine dependent frag. This returns the amount by which | |
14377 | the current size of the frag should change. */ | |
14378 | ||
14379 | int | |
17a2f251 | 14380 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14381 | { |
4a6a3df4 AO |
14382 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14383 | { | |
14384 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14385 | |
14386 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14387 | |
14388 | return fragp->fr_var - old_var; | |
14389 | } | |
14390 | ||
252b5132 RH |
14391 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14392 | return 0; | |
14393 | ||
c4e7957c | 14394 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14395 | { |
14396 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14397 | return 0; | |
14398 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14399 | return 2; | |
14400 | } | |
14401 | else | |
14402 | { | |
14403 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14404 | return 0; | |
14405 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14406 | return -2; | |
14407 | } | |
14408 | ||
14409 | return 0; | |
14410 | } | |
14411 | ||
14412 | /* Convert a machine dependent frag. */ | |
14413 | ||
14414 | void | |
17a2f251 | 14415 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14416 | { |
4a6a3df4 AO |
14417 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14418 | { | |
14419 | bfd_byte *buf; | |
14420 | unsigned long insn; | |
14421 | expressionS exp; | |
14422 | fixS *fixp; | |
b34976b6 | 14423 | |
4a6a3df4 AO |
14424 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14425 | ||
14426 | if (target_big_endian) | |
14427 | insn = bfd_getb32 (buf); | |
14428 | else | |
14429 | insn = bfd_getl32 (buf); | |
b34976b6 | 14430 | |
4a6a3df4 AO |
14431 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14432 | { | |
14433 | /* We generate a fixup instead of applying it right now | |
14434 | because, if there are linker relaxations, we're going to | |
14435 | need the relocations. */ | |
14436 | exp.X_op = O_symbol; | |
14437 | exp.X_add_symbol = fragp->fr_symbol; | |
14438 | exp.X_add_number = fragp->fr_offset; | |
14439 | ||
14440 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14441 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14442 | fixp->fx_file = fragp->fr_file; |
14443 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14444 | |
2132e3a3 | 14445 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14446 | buf += 4; |
14447 | } | |
14448 | else | |
14449 | { | |
14450 | int i; | |
14451 | ||
14452 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 14453 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
14454 | |
14455 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14456 | goto uncond; | |
14457 | ||
14458 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14459 | { | |
14460 | /* Reverse the branch. */ | |
14461 | switch ((insn >> 28) & 0xf) | |
14462 | { | |
14463 | case 4: | |
14464 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14465 | have the condition reversed by tweaking a single | |
14466 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 14467 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
14468 | insn ^= 0x00010000; |
14469 | break; | |
14470 | ||
14471 | case 0: | |
14472 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14473 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 14474 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
14475 | insn ^= 0x00010000; |
14476 | break; | |
b34976b6 | 14477 | |
4a6a3df4 AO |
14478 | case 1: |
14479 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14480 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14481 | insn ^= 0x04000000; |
14482 | break; | |
14483 | ||
14484 | default: | |
14485 | abort (); | |
14486 | } | |
14487 | } | |
14488 | ||
14489 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14490 | { | |
14491 | /* Clear the and-link bit. */ | |
9c2799c2 | 14492 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 14493 | |
54f4ddb3 TS |
14494 | /* bltzal 0x04100000 bgezal 0x04110000 |
14495 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14496 | insn &= ~0x00100000; |
14497 | } | |
14498 | ||
14499 | /* Branch over the branch (if the branch was likely) or the | |
14500 | full jump (not likely case). Compute the offset from the | |
14501 | current instruction to branch to. */ | |
14502 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14503 | i = 16; | |
14504 | else | |
14505 | { | |
14506 | /* How many bytes in instructions we've already emitted? */ | |
14507 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14508 | /* How many bytes in instructions from here to the end? */ | |
14509 | i = fragp->fr_var - i; | |
14510 | } | |
14511 | /* Convert to instruction count. */ | |
14512 | i >>= 2; | |
14513 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14514 | i--; |
4a6a3df4 AO |
14515 | insn |= i; |
14516 | /* Branch over the jump. */ | |
2132e3a3 | 14517 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14518 | buf += 4; |
14519 | ||
54f4ddb3 | 14520 | /* nop */ |
2132e3a3 | 14521 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14522 | buf += 4; |
14523 | ||
14524 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14525 | { | |
14526 | /* beql $0, $0, 2f */ | |
14527 | insn = 0x50000000; | |
14528 | /* Compute the PC offset from the current instruction to | |
14529 | the end of the variable frag. */ | |
14530 | /* How many bytes in instructions we've already emitted? */ | |
14531 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14532 | /* How many bytes in instructions from here to the end? */ | |
14533 | i = fragp->fr_var - i; | |
14534 | /* Convert to instruction count. */ | |
14535 | i >>= 2; | |
14536 | /* Don't decrement i, because we want to branch over the | |
14537 | delay slot. */ | |
14538 | ||
14539 | insn |= i; | |
2132e3a3 | 14540 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14541 | buf += 4; |
14542 | ||
2132e3a3 | 14543 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14544 | buf += 4; |
14545 | } | |
14546 | ||
14547 | uncond: | |
14548 | if (mips_pic == NO_PIC) | |
14549 | { | |
14550 | /* j or jal. */ | |
14551 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14552 | ? 0x0c000000 : 0x08000000); | |
14553 | exp.X_op = O_symbol; | |
14554 | exp.X_add_symbol = fragp->fr_symbol; | |
14555 | exp.X_add_number = fragp->fr_offset; | |
14556 | ||
14557 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14558 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14559 | fixp->fx_file = fragp->fr_file; |
14560 | fixp->fx_line = fragp->fr_line; | |
14561 | ||
2132e3a3 | 14562 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14563 | buf += 4; |
14564 | } | |
14565 | else | |
14566 | { | |
66b3e8da MR |
14567 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
14568 | ||
4a6a3df4 | 14569 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
14570 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
14571 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
14572 | exp.X_op = O_symbol; |
14573 | exp.X_add_symbol = fragp->fr_symbol; | |
14574 | exp.X_add_number = fragp->fr_offset; | |
14575 | ||
14576 | if (fragp->fr_offset) | |
14577 | { | |
14578 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14579 | exp.X_add_number = 0; | |
14580 | } | |
14581 | ||
14582 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14583 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14584 | fixp->fx_file = fragp->fr_file; |
14585 | fixp->fx_line = fragp->fr_line; | |
14586 | ||
2132e3a3 | 14587 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14588 | buf += 4; |
b34976b6 | 14589 | |
4a6a3df4 AO |
14590 | if (mips_opts.isa == ISA_MIPS1) |
14591 | { | |
14592 | /* nop */ | |
2132e3a3 | 14593 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14594 | buf += 4; |
14595 | } | |
14596 | ||
14597 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
14598 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
14599 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
14600 | |
14601 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14602 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14603 | fixp->fx_file = fragp->fr_file; |
14604 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14605 | |
2132e3a3 | 14606 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14607 | buf += 4; |
14608 | ||
14609 | /* j(al)r $at. */ | |
14610 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 14611 | insn = 0x0000f809; |
4a6a3df4 | 14612 | else |
66b3e8da MR |
14613 | insn = 0x00000008; |
14614 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 14615 | |
2132e3a3 | 14616 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14617 | buf += 4; |
14618 | } | |
14619 | } | |
14620 | ||
9c2799c2 | 14621 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
14622 | + fragp->fr_fix + fragp->fr_var); |
14623 | ||
14624 | fragp->fr_fix += fragp->fr_var; | |
14625 | ||
14626 | return; | |
14627 | } | |
14628 | ||
252b5132 RH |
14629 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14630 | { | |
14631 | int type; | |
3994f87e | 14632 | const struct mips16_immed_operand *op; |
b34976b6 | 14633 | bfd_boolean small, ext; |
252b5132 RH |
14634 | offsetT val; |
14635 | bfd_byte *buf; | |
14636 | unsigned long insn; | |
b34976b6 | 14637 | bfd_boolean use_extend; |
252b5132 RH |
14638 | unsigned short extend; |
14639 | ||
14640 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14641 | op = mips16_immed_operands; | |
14642 | while (op->type != type) | |
14643 | ++op; | |
14644 | ||
14645 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14646 | { | |
b34976b6 AM |
14647 | small = FALSE; |
14648 | ext = TRUE; | |
252b5132 RH |
14649 | } |
14650 | else | |
14651 | { | |
b34976b6 AM |
14652 | small = TRUE; |
14653 | ext = FALSE; | |
252b5132 RH |
14654 | } |
14655 | ||
5f5f22c0 | 14656 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14657 | if (op->pcrel) |
14658 | { | |
14659 | addressT addr; | |
14660 | ||
14661 | addr = fragp->fr_address + fragp->fr_fix; | |
14662 | ||
14663 | /* The rules for the base address of a PC relative reloc are | |
14664 | complicated; see mips16_extended_frag. */ | |
14665 | if (type == 'p' || type == 'q') | |
14666 | { | |
14667 | addr += 2; | |
14668 | if (ext) | |
14669 | addr += 2; | |
14670 | /* Ignore the low bit in the target, since it will be | |
14671 | set for a text label. */ | |
14672 | if ((val & 1) != 0) | |
14673 | --val; | |
14674 | } | |
14675 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14676 | addr -= 4; | |
14677 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14678 | addr -= 2; | |
14679 | ||
14680 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14681 | val -= addr; | |
14682 | ||
14683 | /* Make sure the section winds up with the alignment we have | |
14684 | assumed. */ | |
14685 | if (op->shift > 0) | |
14686 | record_alignment (asec, op->shift); | |
14687 | } | |
14688 | ||
14689 | if (ext | |
14690 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14691 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14692 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14693 | _("extended instruction in delay slot")); | |
14694 | ||
14695 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14696 | ||
14697 | if (target_big_endian) | |
14698 | insn = bfd_getb16 (buf); | |
14699 | else | |
14700 | insn = bfd_getl16 (buf); | |
14701 | ||
14702 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14703 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14704 | small, ext, &insn, &use_extend, &extend); | |
14705 | ||
14706 | if (use_extend) | |
14707 | { | |
2132e3a3 | 14708 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14709 | fragp->fr_fix += 2; |
14710 | buf += 2; | |
14711 | } | |
14712 | ||
2132e3a3 | 14713 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14714 | fragp->fr_fix += 2; |
14715 | buf += 2; | |
14716 | } | |
14717 | else | |
14718 | { | |
4d7206a2 RS |
14719 | int first, second; |
14720 | fixS *fixp; | |
252b5132 | 14721 | |
4d7206a2 RS |
14722 | first = RELAX_FIRST (fragp->fr_subtype); |
14723 | second = RELAX_SECOND (fragp->fr_subtype); | |
14724 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14725 | |
584892a6 RS |
14726 | /* Possibly emit a warning if we've chosen the longer option. */ |
14727 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14728 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14729 | { | |
14730 | const char *msg = macro_warning (fragp->fr_subtype); | |
14731 | if (msg != 0) | |
520725ea | 14732 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
584892a6 RS |
14733 | } |
14734 | ||
4d7206a2 RS |
14735 | /* Go through all the fixups for the first sequence. Disable them |
14736 | (by marking them as done) if we're going to use the second | |
14737 | sequence instead. */ | |
14738 | while (fixp | |
14739 | && fixp->fx_frag == fragp | |
14740 | && fixp->fx_where < fragp->fr_fix - second) | |
14741 | { | |
14742 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14743 | fixp->fx_done = 1; | |
14744 | fixp = fixp->fx_next; | |
14745 | } | |
252b5132 | 14746 | |
4d7206a2 RS |
14747 | /* Go through the fixups for the second sequence. Disable them if |
14748 | we're going to use the first sequence, otherwise adjust their | |
14749 | addresses to account for the relaxation. */ | |
14750 | while (fixp && fixp->fx_frag == fragp) | |
14751 | { | |
14752 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14753 | fixp->fx_where -= first; | |
14754 | else | |
14755 | fixp->fx_done = 1; | |
14756 | fixp = fixp->fx_next; | |
14757 | } | |
14758 | ||
14759 | /* Now modify the frag contents. */ | |
14760 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14761 | { | |
14762 | char *start; | |
14763 | ||
14764 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14765 | memmove (start, start + first, second); | |
14766 | fragp->fr_fix -= first; | |
14767 | } | |
14768 | else | |
14769 | fragp->fr_fix -= second; | |
252b5132 RH |
14770 | } |
14771 | } | |
14772 | ||
14773 | #ifdef OBJ_ELF | |
14774 | ||
14775 | /* This function is called after the relocs have been generated. | |
14776 | We've been storing mips16 text labels as odd. Here we convert them | |
14777 | back to even for the convenience of the debugger. */ | |
14778 | ||
14779 | void | |
17a2f251 | 14780 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14781 | { |
14782 | asymbol **syms; | |
14783 | unsigned int count, i; | |
14784 | ||
f43abd2b | 14785 | if (!IS_ELF) |
252b5132 RH |
14786 | return; |
14787 | ||
14788 | syms = bfd_get_outsymbols (stdoutput); | |
14789 | count = bfd_get_symcount (stdoutput); | |
14790 | for (i = 0; i < count; i++, syms++) | |
14791 | { | |
30c09090 | 14792 | if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other) |
252b5132 RH |
14793 | && ((*syms)->value & 1) != 0) |
14794 | { | |
14795 | (*syms)->value &= ~1; | |
14796 | /* If the symbol has an odd size, it was probably computed | |
14797 | incorrectly, so adjust that as well. */ | |
14798 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14799 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14800 | } | |
14801 | } | |
14802 | } | |
14803 | ||
14804 | #endif | |
14805 | ||
a1facbec MR |
14806 | /* This function is called whenever a label is defined, including fake |
14807 | labels instantiated off the dot special symbol. It is used when | |
14808 | handling branch delays; if a branch has a label, we assume we cannot | |
14809 | move it. This also bumps the value of the symbol by 1 in compressed | |
14810 | code. */ | |
252b5132 RH |
14811 | |
14812 | void | |
a1facbec | 14813 | mips_record_label (symbolS *sym) |
252b5132 | 14814 | { |
a8dbcb85 | 14815 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14816 | struct insn_label_list *l; |
14817 | ||
14818 | if (free_insn_labels == NULL) | |
14819 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14820 | else | |
14821 | { | |
14822 | l = free_insn_labels; | |
14823 | free_insn_labels = l->next; | |
14824 | } | |
14825 | ||
14826 | l->label = sym; | |
a8dbcb85 TS |
14827 | l->next = si->label_list; |
14828 | si->label_list = l; | |
a1facbec | 14829 | } |
07a53e5c | 14830 | |
a1facbec MR |
14831 | /* This function is called as tc_frob_label() whenever a label is defined |
14832 | and adds a DWARF-2 record we only want for true labels. */ | |
14833 | ||
14834 | void | |
14835 | mips_define_label (symbolS *sym) | |
14836 | { | |
14837 | mips_record_label (sym); | |
07a53e5c RH |
14838 | #ifdef OBJ_ELF |
14839 | dwarf2_emit_label (sym); | |
14840 | #endif | |
252b5132 RH |
14841 | } |
14842 | \f | |
14843 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14844 | ||
14845 | /* Some special processing for a MIPS ELF file. */ | |
14846 | ||
14847 | void | |
17a2f251 | 14848 | mips_elf_final_processing (void) |
252b5132 RH |
14849 | { |
14850 | /* Write out the register information. */ | |
316f5878 | 14851 | if (mips_abi != N64_ABI) |
252b5132 RH |
14852 | { |
14853 | Elf32_RegInfo s; | |
14854 | ||
14855 | s.ri_gprmask = mips_gprmask; | |
14856 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14857 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14858 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14859 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14860 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14861 | ||
14862 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14863 | ((Elf32_External_RegInfo *) | |
14864 | mips_regmask_frag)); | |
14865 | } | |
14866 | else | |
14867 | { | |
14868 | Elf64_Internal_RegInfo s; | |
14869 | ||
14870 | s.ri_gprmask = mips_gprmask; | |
14871 | s.ri_pad = 0; | |
14872 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14873 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14874 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14875 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14876 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14877 | ||
14878 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14879 | ((Elf64_External_RegInfo *) | |
14880 | mips_regmask_frag)); | |
14881 | } | |
14882 | ||
14883 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14884 | sort of BFD interface for this. */ | |
14885 | if (mips_any_noreorder) | |
14886 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14887 | if (mips_pic != NO_PIC) | |
143d77c5 | 14888 | { |
252b5132 | 14889 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14890 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14891 | } | |
14892 | if (mips_abicalls) | |
14893 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14894 | |
98d3f06f | 14895 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14896 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14897 | file_ase_dsp is true. */ | |
8b082fb1 | 14898 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14899 | /* We may need to define a new flag for MT ASE, and set this flag when |
14900 | file_ase_mt is true. */ | |
a4672219 TS |
14901 | if (file_ase_mips16) |
14902 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14903 | #if 0 /* XXX FIXME */ |
14904 | if (file_ase_mips3d) | |
14905 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14906 | #endif | |
deec1734 CD |
14907 | if (file_ase_mdmx) |
14908 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14909 | |
bdaaa2e1 | 14910 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14911 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14912 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14913 | else if (mips_abi == O64_ABI) |
252b5132 | 14914 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14915 | else if (mips_abi == EABI_ABI) |
252b5132 | 14916 | { |
316f5878 | 14917 | if (!file_mips_gp32) |
252b5132 RH |
14918 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14919 | else | |
14920 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14921 | } | |
316f5878 | 14922 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14923 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14924 | ||
c9914766 | 14925 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14926 | |
14927 | if (mips_32bitmode) | |
14928 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14929 | |
14930 | #if 0 /* XXX FIXME */ | |
14931 | /* 32 bit code with 64 bit FP registers. */ | |
14932 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14933 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14934 | #endif | |
252b5132 RH |
14935 | } |
14936 | ||
14937 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14938 | \f | |
beae10d5 | 14939 | typedef struct proc { |
9b2f1d35 EC |
14940 | symbolS *func_sym; |
14941 | symbolS *func_end_sym; | |
beae10d5 KH |
14942 | unsigned long reg_mask; |
14943 | unsigned long reg_offset; | |
14944 | unsigned long fpreg_mask; | |
14945 | unsigned long fpreg_offset; | |
14946 | unsigned long frame_offset; | |
14947 | unsigned long frame_reg; | |
14948 | unsigned long pc_reg; | |
14949 | } procS; | |
252b5132 RH |
14950 | |
14951 | static procS cur_proc; | |
14952 | static procS *cur_proc_ptr; | |
14953 | static int numprocs; | |
14954 | ||
742a56fe RS |
14955 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
14956 | nop as "0". */ | |
14957 | ||
14958 | char | |
14959 | mips_nop_opcode (void) | |
14960 | { | |
14961 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
14962 | } | |
14963 | ||
14964 | /* Fill in an rs_align_code fragment. This only needs to do something | |
14965 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 14966 | |
0a9ef439 | 14967 | void |
17a2f251 | 14968 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14969 | { |
742a56fe | 14970 | char *p; |
c67a084a NC |
14971 | int bytes, size, excess; |
14972 | valueT opcode; | |
742a56fe | 14973 | |
0a9ef439 RH |
14974 | if (fragp->fr_type != rs_align_code) |
14975 | return; | |
14976 | ||
742a56fe RS |
14977 | p = fragp->fr_literal + fragp->fr_fix; |
14978 | if (*p) | |
a19d8eb0 | 14979 | { |
c67a084a NC |
14980 | opcode = mips16_nop_insn.insn_opcode; |
14981 | size = 2; | |
14982 | } | |
14983 | else | |
14984 | { | |
14985 | opcode = nop_insn.insn_opcode; | |
14986 | size = 4; | |
14987 | } | |
a19d8eb0 | 14988 | |
c67a084a NC |
14989 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14990 | excess = bytes % size; | |
14991 | if (excess != 0) | |
14992 | { | |
14993 | /* If we're not inserting a whole number of instructions, | |
14994 | pad the end of the fixed part of the frag with zeros. */ | |
14995 | memset (p, 0, excess); | |
14996 | p += excess; | |
14997 | fragp->fr_fix += excess; | |
a19d8eb0 | 14998 | } |
c67a084a NC |
14999 | |
15000 | md_number_to_chars (p, opcode, size); | |
15001 | fragp->fr_var = size; | |
a19d8eb0 CP |
15002 | } |
15003 | ||
252b5132 | 15004 | static void |
17a2f251 | 15005 | md_obj_begin (void) |
252b5132 RH |
15006 | { |
15007 | } | |
15008 | ||
15009 | static void | |
17a2f251 | 15010 | md_obj_end (void) |
252b5132 | 15011 | { |
54f4ddb3 | 15012 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 15013 | if (cur_proc_ptr) |
9a41af64 | 15014 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
15015 | } |
15016 | ||
15017 | static long | |
17a2f251 | 15018 | get_number (void) |
252b5132 RH |
15019 | { |
15020 | int negative = 0; | |
15021 | long val = 0; | |
15022 | ||
15023 | if (*input_line_pointer == '-') | |
15024 | { | |
15025 | ++input_line_pointer; | |
15026 | negative = 1; | |
15027 | } | |
3882b010 | 15028 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 15029 | as_bad (_("expected simple number")); |
252b5132 RH |
15030 | if (input_line_pointer[0] == '0') |
15031 | { | |
15032 | if (input_line_pointer[1] == 'x') | |
15033 | { | |
15034 | input_line_pointer += 2; | |
3882b010 | 15035 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
15036 | { |
15037 | val <<= 4; | |
15038 | val |= hex_value (*input_line_pointer++); | |
15039 | } | |
15040 | return negative ? -val : val; | |
15041 | } | |
15042 | else | |
15043 | { | |
15044 | ++input_line_pointer; | |
3882b010 | 15045 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15046 | { |
15047 | val <<= 3; | |
15048 | val |= *input_line_pointer++ - '0'; | |
15049 | } | |
15050 | return negative ? -val : val; | |
15051 | } | |
15052 | } | |
3882b010 | 15053 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15054 | { |
15055 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
15056 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 15057 | as_warn (_("invalid number")); |
252b5132 RH |
15058 | return -1; |
15059 | } | |
3882b010 | 15060 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15061 | { |
15062 | val *= 10; | |
15063 | val += *input_line_pointer++ - '0'; | |
15064 | } | |
15065 | return negative ? -val : val; | |
15066 | } | |
15067 | ||
15068 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
15069 | is an initial number which is the ECOFF file index. In the non-ECOFF |
15070 | case .file implies DWARF-2. */ | |
15071 | ||
15072 | static void | |
17a2f251 | 15073 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 15074 | { |
ecb4347a DJ |
15075 | static int first_file_directive = 0; |
15076 | ||
c5dd6aab DJ |
15077 | if (ECOFF_DEBUGGING) |
15078 | { | |
15079 | get_number (); | |
15080 | s_app_file (0); | |
15081 | } | |
15082 | else | |
ecb4347a DJ |
15083 | { |
15084 | char *filename; | |
15085 | ||
15086 | filename = dwarf2_directive_file (0); | |
15087 | ||
15088 | /* Versions of GCC up to 3.1 start files with a ".file" | |
15089 | directive even for stabs output. Make sure that this | |
15090 | ".file" is handled. Note that you need a version of GCC | |
15091 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
15092 | if (filename != NULL && ! first_file_directive) | |
15093 | { | |
15094 | (void) new_logical_line (filename, -1); | |
c04f5787 | 15095 | s_app_file_string (filename, 0); |
ecb4347a DJ |
15096 | } |
15097 | first_file_directive = 1; | |
15098 | } | |
c5dd6aab DJ |
15099 | } |
15100 | ||
15101 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
15102 | |
15103 | static void | |
17a2f251 | 15104 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 15105 | { |
c5dd6aab DJ |
15106 | if (!ECOFF_DEBUGGING) |
15107 | dwarf2_directive_loc (0); | |
252b5132 RH |
15108 | } |
15109 | ||
252b5132 RH |
15110 | /* The .end directive. */ |
15111 | ||
15112 | static void | |
17a2f251 | 15113 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15114 | { |
15115 | symbolS *p; | |
252b5132 | 15116 | |
7a621144 DJ |
15117 | /* Following functions need their own .frame and .cprestore directives. */ |
15118 | mips_frame_reg_valid = 0; | |
15119 | mips_cprestore_valid = 0; | |
15120 | ||
252b5132 RH |
15121 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
15122 | { | |
15123 | p = get_symbol (); | |
15124 | demand_empty_rest_of_line (); | |
15125 | } | |
15126 | else | |
15127 | p = NULL; | |
15128 | ||
14949570 | 15129 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15130 | as_warn (_(".end not in text section")); |
15131 | ||
15132 | if (!cur_proc_ptr) | |
15133 | { | |
15134 | as_warn (_(".end directive without a preceding .ent directive.")); | |
15135 | demand_empty_rest_of_line (); | |
15136 | return; | |
15137 | } | |
15138 | ||
15139 | if (p != NULL) | |
15140 | { | |
9c2799c2 | 15141 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 15142 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 15143 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
15144 | |
15145 | if (debug_type == DEBUG_STABS) | |
15146 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
15147 | S_GET_NAME (p)); | |
252b5132 RH |
15148 | } |
15149 | else | |
15150 | as_warn (_(".end directive missing or unknown symbol")); | |
15151 | ||
2132e3a3 | 15152 | #ifdef OBJ_ELF |
9b2f1d35 EC |
15153 | /* Create an expression to calculate the size of the function. */ |
15154 | if (p && cur_proc_ptr) | |
15155 | { | |
15156 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
15157 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
15158 | ||
15159 | obj->size = exp; | |
15160 | exp->X_op = O_subtract; | |
15161 | exp->X_add_symbol = symbol_temp_new_now (); | |
15162 | exp->X_op_symbol = p; | |
15163 | exp->X_add_number = 0; | |
15164 | ||
15165 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
15166 | } | |
15167 | ||
ecb4347a | 15168 | /* Generate a .pdr section. */ |
f43abd2b | 15169 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
15170 | { |
15171 | segT saved_seg = now_seg; | |
15172 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
15173 | expressionS exp; |
15174 | char *fragp; | |
252b5132 | 15175 | |
252b5132 | 15176 | #ifdef md_flush_pending_output |
ecb4347a | 15177 | md_flush_pending_output (); |
252b5132 RH |
15178 | #endif |
15179 | ||
9c2799c2 | 15180 | gas_assert (pdr_seg); |
ecb4347a | 15181 | subseg_set (pdr_seg, 0); |
252b5132 | 15182 | |
ecb4347a DJ |
15183 | /* Write the symbol. */ |
15184 | exp.X_op = O_symbol; | |
15185 | exp.X_add_symbol = p; | |
15186 | exp.X_add_number = 0; | |
15187 | emit_expr (&exp, 4); | |
252b5132 | 15188 | |
ecb4347a | 15189 | fragp = frag_more (7 * 4); |
252b5132 | 15190 | |
17a2f251 TS |
15191 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
15192 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
15193 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
15194 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
15195 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
15196 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
15197 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 15198 | |
ecb4347a DJ |
15199 | subseg_set (saved_seg, saved_subseg); |
15200 | } | |
15201 | #endif /* OBJ_ELF */ | |
252b5132 RH |
15202 | |
15203 | cur_proc_ptr = NULL; | |
15204 | } | |
15205 | ||
15206 | /* The .aent and .ent directives. */ | |
15207 | ||
15208 | static void | |
17a2f251 | 15209 | s_mips_ent (int aent) |
252b5132 | 15210 | { |
252b5132 | 15211 | symbolS *symbolP; |
252b5132 RH |
15212 | |
15213 | symbolP = get_symbol (); | |
15214 | if (*input_line_pointer == ',') | |
f9419b05 | 15215 | ++input_line_pointer; |
252b5132 | 15216 | SKIP_WHITESPACE (); |
3882b010 | 15217 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 15218 | || *input_line_pointer == '-') |
874e8986 | 15219 | get_number (); |
252b5132 | 15220 | |
14949570 | 15221 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15222 | as_warn (_(".ent or .aent not in text section.")); |
15223 | ||
15224 | if (!aent && cur_proc_ptr) | |
9a41af64 | 15225 | as_warn (_("missing .end")); |
252b5132 RH |
15226 | |
15227 | if (!aent) | |
15228 | { | |
7a621144 DJ |
15229 | /* This function needs its own .frame and .cprestore directives. */ |
15230 | mips_frame_reg_valid = 0; | |
15231 | mips_cprestore_valid = 0; | |
15232 | ||
252b5132 RH |
15233 | cur_proc_ptr = &cur_proc; |
15234 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
15235 | ||
9b2f1d35 | 15236 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 15237 | |
f9419b05 | 15238 | ++numprocs; |
ecb4347a DJ |
15239 | |
15240 | if (debug_type == DEBUG_STABS) | |
15241 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
15242 | S_GET_NAME (symbolP)); | |
252b5132 RH |
15243 | } |
15244 | ||
7c0fc524 MR |
15245 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
15246 | ||
252b5132 RH |
15247 | demand_empty_rest_of_line (); |
15248 | } | |
15249 | ||
15250 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 15251 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 15252 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 15253 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
15254 | symbol table (in the mdebug section). */ |
15255 | ||
15256 | static void | |
17a2f251 | 15257 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15258 | { |
ecb4347a | 15259 | #ifdef OBJ_ELF |
f43abd2b | 15260 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
15261 | { |
15262 | long val; | |
252b5132 | 15263 | |
ecb4347a DJ |
15264 | if (cur_proc_ptr == (procS *) NULL) |
15265 | { | |
15266 | as_warn (_(".frame outside of .ent")); | |
15267 | demand_empty_rest_of_line (); | |
15268 | return; | |
15269 | } | |
252b5132 | 15270 | |
ecb4347a DJ |
15271 | cur_proc_ptr->frame_reg = tc_get_register (1); |
15272 | ||
15273 | SKIP_WHITESPACE (); | |
15274 | if (*input_line_pointer++ != ',' | |
15275 | || get_absolute_expression_and_terminator (&val) != ',') | |
15276 | { | |
15277 | as_warn (_("Bad .frame directive")); | |
15278 | --input_line_pointer; | |
15279 | demand_empty_rest_of_line (); | |
15280 | return; | |
15281 | } | |
252b5132 | 15282 | |
ecb4347a DJ |
15283 | cur_proc_ptr->frame_offset = val; |
15284 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 15285 | |
252b5132 | 15286 | demand_empty_rest_of_line (); |
252b5132 | 15287 | } |
ecb4347a DJ |
15288 | else |
15289 | #endif /* OBJ_ELF */ | |
15290 | s_ignore (ignore); | |
252b5132 RH |
15291 | } |
15292 | ||
bdaaa2e1 KH |
15293 | /* The .fmask and .mask directives. If the mdebug section is present |
15294 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 15295 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 15296 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
15297 | make reference to the ecoff symbol table (in the mdebug section). */ |
15298 | ||
15299 | static void | |
17a2f251 | 15300 | s_mips_mask (int reg_type) |
252b5132 | 15301 | { |
ecb4347a | 15302 | #ifdef OBJ_ELF |
f43abd2b | 15303 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 15304 | { |
ecb4347a | 15305 | long mask, off; |
252b5132 | 15306 | |
ecb4347a DJ |
15307 | if (cur_proc_ptr == (procS *) NULL) |
15308 | { | |
15309 | as_warn (_(".mask/.fmask outside of .ent")); | |
15310 | demand_empty_rest_of_line (); | |
15311 | return; | |
15312 | } | |
252b5132 | 15313 | |
ecb4347a DJ |
15314 | if (get_absolute_expression_and_terminator (&mask) != ',') |
15315 | { | |
15316 | as_warn (_("Bad .mask/.fmask directive")); | |
15317 | --input_line_pointer; | |
15318 | demand_empty_rest_of_line (); | |
15319 | return; | |
15320 | } | |
252b5132 | 15321 | |
ecb4347a DJ |
15322 | off = get_absolute_expression (); |
15323 | ||
15324 | if (reg_type == 'F') | |
15325 | { | |
15326 | cur_proc_ptr->fpreg_mask = mask; | |
15327 | cur_proc_ptr->fpreg_offset = off; | |
15328 | } | |
15329 | else | |
15330 | { | |
15331 | cur_proc_ptr->reg_mask = mask; | |
15332 | cur_proc_ptr->reg_offset = off; | |
15333 | } | |
15334 | ||
15335 | demand_empty_rest_of_line (); | |
252b5132 RH |
15336 | } |
15337 | else | |
ecb4347a DJ |
15338 | #endif /* OBJ_ELF */ |
15339 | s_ignore (reg_type); | |
252b5132 RH |
15340 | } |
15341 | ||
316f5878 RS |
15342 | /* A table describing all the processors gas knows about. Names are |
15343 | matched in the order listed. | |
e7af610e | 15344 | |
316f5878 RS |
15345 | To ease comparison, please keep this table in the same order as |
15346 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
15347 | static const struct mips_cpu_info mips_cpu_info_table[] = |
15348 | { | |
316f5878 | 15349 | /* Entries for generic ISAs */ |
ad3fea08 TS |
15350 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
15351 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
15352 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
15353 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
15354 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
15355 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
15356 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15357 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
15358 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
15359 | |
15360 | /* MIPS I */ | |
ad3fea08 TS |
15361 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
15362 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
15363 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
15364 | |
15365 | /* MIPS II */ | |
ad3fea08 | 15366 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
15367 | |
15368 | /* MIPS III */ | |
ad3fea08 TS |
15369 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
15370 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
15371 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
15372 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
15373 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
15374 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
15375 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
15376 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
15377 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
15378 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
15379 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
15380 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
15381 | /* ST Microelectronics Loongson 2E and 2F cores */ |
15382 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
15383 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
15384 | |
15385 | /* MIPS IV */ | |
ad3fea08 TS |
15386 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
15387 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
15388 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
15389 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
15390 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
15391 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
15392 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
15393 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
15394 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
15395 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15396 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15397 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15398 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15399 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15400 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15401 | |
15402 | /* MIPS 32 */ | |
ad3fea08 TS |
15403 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15404 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15405 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15406 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15407 | ||
15408 | /* MIPS 32 Release 2 */ | |
15409 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15410 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15411 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15412 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15413 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15414 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15415 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15416 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15417 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15418 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15419 | /* Deprecated forms of the above. */ | |
15420 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15421 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15422 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15423 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15424 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15425 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15426 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15427 | /* Deprecated forms of the above. */ | |
15428 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15429 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15430 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15431 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15432 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15433 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15434 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15435 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15436 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15437 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15438 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15439 | /* Deprecated forms of the above. */ | |
15440 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15441 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15442 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15443 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15444 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15445 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15446 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15447 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15448 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15449 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15450 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15451 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15452 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15453 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15454 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15455 | /* Deprecated forms of the above. */ | |
15456 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15457 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15458 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15459 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
15460 | /* 1004K cores are multiprocessor versions of the 34K. */ |
15461 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15462 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15463 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15464 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15465 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15466 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15467 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15468 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15469 | |
316f5878 | 15470 | /* MIPS 64 */ |
ad3fea08 TS |
15471 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15472 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15473 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15474 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 15475 | |
c7a23324 | 15476 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15477 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15478 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15479 | /* Broadcom SB-1A CPU core */ |
15480 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15481 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
15482 | |
15483 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 15484 | |
ed163775 MR |
15485 | /* MIPS 64 Release 2 */ |
15486 | ||
967344c6 AN |
15487 | /* Cavium Networks Octeon CPU core */ |
15488 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15489 | ||
52b6b6b9 JM |
15490 | /* RMI Xlr */ |
15491 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
15492 | ||
316f5878 RS |
15493 | /* End marker */ |
15494 | { NULL, 0, 0, 0 } | |
15495 | }; | |
e7af610e | 15496 | |
84ea6cf2 | 15497 | |
316f5878 RS |
15498 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15499 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15500 | |
316f5878 | 15501 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15502 | |
b34976b6 | 15503 | static bfd_boolean |
17a2f251 | 15504 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15505 | { |
15506 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15507 | given++, canonical++; | |
15508 | ||
15509 | return ((*given == 0 && *canonical == 0) | |
15510 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15511 | } | |
15512 | ||
15513 | ||
15514 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15515 | CPU name. We've traditionally allowed a lot of variation here. | |
15516 | ||
15517 | Note: this function is shared between GCC and GAS. */ | |
15518 | ||
b34976b6 | 15519 | static bfd_boolean |
17a2f251 | 15520 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15521 | { |
15522 | /* First see if the name matches exactly, or with a final "000" | |
15523 | turned into "k". */ | |
15524 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15525 | return TRUE; |
316f5878 RS |
15526 | |
15527 | /* If not, try comparing based on numerical designation alone. | |
15528 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15529 | if (TOLOWER (*given) == 'r') | |
15530 | given++; | |
15531 | if (!ISDIGIT (*given)) | |
b34976b6 | 15532 | return FALSE; |
316f5878 RS |
15533 | |
15534 | /* Skip over some well-known prefixes in the canonical name, | |
15535 | hoping to find a number there too. */ | |
15536 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15537 | canonical += 2; | |
15538 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15539 | canonical += 2; | |
15540 | else if (TOLOWER (canonical[0]) == 'r') | |
15541 | canonical += 1; | |
15542 | ||
15543 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15544 | } | |
15545 | ||
15546 | ||
15547 | /* Parse an option that takes the name of a processor as its argument. | |
15548 | OPTION is the name of the option and CPU_STRING is the argument. | |
15549 | Return the corresponding processor enumeration if the CPU_STRING is | |
15550 | recognized, otherwise report an error and return null. | |
15551 | ||
15552 | A similar function exists in GCC. */ | |
e7af610e NC |
15553 | |
15554 | static const struct mips_cpu_info * | |
17a2f251 | 15555 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15556 | { |
316f5878 | 15557 | const struct mips_cpu_info *p; |
e7af610e | 15558 | |
316f5878 RS |
15559 | /* 'from-abi' selects the most compatible architecture for the given |
15560 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15561 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15562 | version. Look first at the -mgp options, if given, otherwise base | |
15563 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15564 | |
316f5878 RS |
15565 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15566 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15567 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15568 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15569 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15570 | { | |
15571 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15572 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15573 | ||
15574 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15575 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15576 | ||
15577 | if (file_mips_gp32 >= 0) | |
15578 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15579 | ||
15580 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15581 | ? ISA_MIPS3 | |
15582 | : ISA_MIPS1); | |
15583 | } | |
15584 | ||
15585 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15586 | if (strcasecmp (cpu_string, "default") == 0) | |
15587 | return 0; | |
15588 | ||
15589 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15590 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15591 | return p; | |
15592 | ||
20203fb9 | 15593 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 15594 | return 0; |
e7af610e NC |
15595 | } |
15596 | ||
316f5878 RS |
15597 | /* Return the canonical processor information for ISA (a member of the |
15598 | ISA_MIPS* enumeration). */ | |
15599 | ||
e7af610e | 15600 | static const struct mips_cpu_info * |
17a2f251 | 15601 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15602 | { |
15603 | int i; | |
15604 | ||
15605 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15606 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15607 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15608 | return (&mips_cpu_info_table[i]); |
15609 | ||
e972090a | 15610 | return NULL; |
e7af610e | 15611 | } |
fef14a42 TS |
15612 | |
15613 | static const struct mips_cpu_info * | |
17a2f251 | 15614 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15615 | { |
15616 | int i; | |
15617 | ||
15618 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15619 | if (arch == mips_cpu_info_table[i].cpu) | |
15620 | return (&mips_cpu_info_table[i]); | |
15621 | ||
15622 | return NULL; | |
15623 | } | |
316f5878 RS |
15624 | \f |
15625 | static void | |
17a2f251 | 15626 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15627 | { |
15628 | if (*first_p) | |
15629 | { | |
15630 | fprintf (stream, "%24s", ""); | |
15631 | *col_p = 24; | |
15632 | } | |
15633 | else | |
15634 | { | |
15635 | fprintf (stream, ", "); | |
15636 | *col_p += 2; | |
15637 | } | |
e7af610e | 15638 | |
316f5878 RS |
15639 | if (*col_p + strlen (string) > 72) |
15640 | { | |
15641 | fprintf (stream, "\n%24s", ""); | |
15642 | *col_p = 24; | |
15643 | } | |
15644 | ||
15645 | fprintf (stream, "%s", string); | |
15646 | *col_p += strlen (string); | |
15647 | ||
15648 | *first_p = 0; | |
15649 | } | |
15650 | ||
15651 | void | |
17a2f251 | 15652 | md_show_usage (FILE *stream) |
e7af610e | 15653 | { |
316f5878 RS |
15654 | int column, first; |
15655 | size_t i; | |
15656 | ||
15657 | fprintf (stream, _("\ | |
15658 | MIPS options:\n\ | |
316f5878 RS |
15659 | -EB generate big endian output\n\ |
15660 | -EL generate little endian output\n\ | |
15661 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15662 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15663 | implicitly with the gp register [default 8]\n")); | |
15664 | fprintf (stream, _("\ | |
15665 | -mips1 generate MIPS ISA I instructions\n\ | |
15666 | -mips2 generate MIPS ISA II instructions\n\ | |
15667 | -mips3 generate MIPS ISA III instructions\n\ | |
15668 | -mips4 generate MIPS ISA IV instructions\n\ | |
15669 | -mips5 generate MIPS ISA V instructions\n\ | |
15670 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15671 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15672 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15673 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15674 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15675 | ||
15676 | first = 1; | |
e7af610e NC |
15677 | |
15678 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15679 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15680 | show (stream, "from-abi", &column, &first); | |
15681 | fputc ('\n', stream); | |
e7af610e | 15682 | |
316f5878 RS |
15683 | fprintf (stream, _("\ |
15684 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15685 | -no-mCPU don't generate code specific to CPU.\n\ | |
15686 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15687 | ||
15688 | first = 1; | |
15689 | ||
15690 | show (stream, "3900", &column, &first); | |
15691 | show (stream, "4010", &column, &first); | |
15692 | show (stream, "4100", &column, &first); | |
15693 | show (stream, "4650", &column, &first); | |
15694 | fputc ('\n', stream); | |
15695 | ||
15696 | fprintf (stream, _("\ | |
15697 | -mips16 generate mips16 instructions\n\ | |
15698 | -no-mips16 do not generate mips16 instructions\n")); | |
15699 | fprintf (stream, _("\ | |
e16bfa71 TS |
15700 | -msmartmips generate smartmips instructions\n\ |
15701 | -mno-smartmips do not generate smartmips instructions\n")); | |
15702 | fprintf (stream, _("\ | |
74cd071d CF |
15703 | -mdsp generate DSP instructions\n\ |
15704 | -mno-dsp do not generate DSP instructions\n")); | |
15705 | fprintf (stream, _("\ | |
8b082fb1 TS |
15706 | -mdspr2 generate DSP R2 instructions\n\ |
15707 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15708 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15709 | -mmt generate MT instructions\n\ |
15710 | -mno-mt do not generate MT instructions\n")); | |
15711 | fprintf (stream, _("\ | |
c67a084a NC |
15712 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
15713 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 15714 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15715 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 15716 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 15717 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
15718 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15719 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15720 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15721 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15722 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15723 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15724 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15725 | fprintf (stream, _("\ |
15726 | -mhard-float allow floating-point instructions\n\ | |
15727 | -msoft-float do not allow floating-point instructions\n\ | |
15728 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15729 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15730 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15731 | )); | |
316f5878 RS |
15732 | #ifdef OBJ_ELF |
15733 | fprintf (stream, _("\ | |
15734 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 15735 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 15736 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 15737 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 15738 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 15739 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15740 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15741 | position dependent (non shared) code\n\ |
316f5878 RS |
15742 | -mabi=ABI create ABI conformant object file for:\n")); |
15743 | ||
15744 | first = 1; | |
15745 | ||
15746 | show (stream, "32", &column, &first); | |
15747 | show (stream, "o64", &column, &first); | |
15748 | show (stream, "n32", &column, &first); | |
15749 | show (stream, "64", &column, &first); | |
15750 | show (stream, "eabi", &column, &first); | |
15751 | ||
15752 | fputc ('\n', stream); | |
15753 | ||
15754 | fprintf (stream, _("\ | |
15755 | -32 create o32 ABI object file (default)\n\ | |
15756 | -n32 create n32 ABI object file\n\ | |
15757 | -64 create 64 ABI object file\n")); | |
15758 | #endif | |
e7af610e | 15759 | } |
14e777e0 | 15760 | |
1575952e | 15761 | #ifdef TE_IRIX |
14e777e0 | 15762 | enum dwarf2_format |
413a266c | 15763 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 15764 | { |
369943fe | 15765 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 15766 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
15767 | else |
15768 | return dwarf2_format_32bit; | |
15769 | } | |
1575952e | 15770 | #endif |
73369e65 EC |
15771 | |
15772 | int | |
15773 | mips_dwarf2_addr_size (void) | |
15774 | { | |
6b6b3450 | 15775 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 15776 | return 8; |
73369e65 EC |
15777 | else |
15778 | return 4; | |
15779 | } | |
5862107c EC |
15780 | |
15781 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15782 | void | |
15783 | mips_cfi_frame_initial_instructions (void) | |
15784 | { | |
15785 | cfi_add_CFA_def_cfa_register (SP); | |
15786 | } | |
15787 | ||
707bfff6 TS |
15788 | int |
15789 | tc_mips_regname_to_dw2regnum (char *regname) | |
15790 | { | |
15791 | unsigned int regnum = -1; | |
15792 | unsigned int reg; | |
15793 | ||
15794 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15795 | regnum = reg; | |
15796 | ||
15797 | return regnum; | |
15798 | } |