Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e7c604dd | 3 | 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 RH |
31 | #include "opcode/mips.h" |
32 | #include "itbl-ops.h" | |
c5dd6aab | 33 | #include "dwarf2dbg.h" |
5862107c | 34 | #include "dw2gencfi.h" |
252b5132 RH |
35 | |
36 | #ifdef DEBUG | |
37 | #define DBG(x) printf x | |
38 | #else | |
39 | #define DBG(x) | |
40 | #endif | |
41 | ||
42 | #ifdef OBJ_MAYBE_ELF | |
43 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
44 | static int mips_output_flavor (void); |
45 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
46 | #undef OBJ_PROCESS_STAB |
47 | #undef OUTPUT_FLAVOR | |
48 | #undef S_GET_ALIGN | |
49 | #undef S_GET_SIZE | |
50 | #undef S_SET_ALIGN | |
51 | #undef S_SET_SIZE | |
252b5132 RH |
52 | #undef obj_frob_file |
53 | #undef obj_frob_file_after_relocs | |
54 | #undef obj_frob_symbol | |
55 | #undef obj_pop_insert | |
56 | #undef obj_sec_sym_ok_for_reloc | |
57 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
58 | ||
59 | #include "obj-elf.h" | |
60 | /* Fix any of them that we actually care about. */ | |
61 | #undef OUTPUT_FLAVOR | |
62 | #define OUTPUT_FLAVOR mips_output_flavor() | |
63 | #endif | |
64 | ||
65 | #if defined (OBJ_ELF) | |
66 | #include "elf/mips.h" | |
67 | #endif | |
68 | ||
69 | #ifndef ECOFF_DEBUGGING | |
70 | #define NO_ECOFF_DEBUGGING | |
71 | #define ECOFF_DEBUGGING 0 | |
72 | #endif | |
73 | ||
ecb4347a DJ |
74 | int mips_flag_mdebug = -1; |
75 | ||
dcd410fe RO |
76 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
77 | linker doesn't know about and discards them, but relocations against them | |
78 | remain, leading to rld crashes. */ | |
79 | #ifdef TE_IRIX | |
80 | int mips_flag_pdr = FALSE; | |
81 | #else | |
82 | int mips_flag_pdr = TRUE; | |
83 | #endif | |
84 | ||
252b5132 RH |
85 | #include "ecoff.h" |
86 | ||
87 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
88 | static char *mips_regmask_frag; | |
89 | #endif | |
90 | ||
85b51719 | 91 | #define ZERO 0 |
741fe287 | 92 | #define ATREG 1 |
252b5132 RH |
93 | #define TREG 24 |
94 | #define PIC_CALL_REG 25 | |
95 | #define KT0 26 | |
96 | #define KT1 27 | |
97 | #define GP 28 | |
98 | #define SP 29 | |
99 | #define FP 30 | |
100 | #define RA 31 | |
101 | ||
102 | #define ILLEGAL_REG (32) | |
103 | ||
741fe287 MR |
104 | #define AT mips_opts.at |
105 | ||
252b5132 RH |
106 | /* Allow override of standard little-endian ECOFF format. */ |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d | 152 | |
708587a4 | 153 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
154 | unsigned int noreorder_p : 1; |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
e16bfa71 | 196 | int ase_smartmips; |
74cd071d | 197 | int ase_dsp; |
8b082fb1 | 198 | int ase_dspr2; |
ef2e4d86 | 199 | int ase_mt; |
252b5132 RH |
200 | /* Whether we are assembling for the mips16 processor. 0 if we are |
201 | not, 1 if we are, and -1 if the value has not been initialized. | |
202 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
203 | -nomips16 command line options, and the default CPU. */ | |
204 | int mips16; | |
205 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
206 | reorder' and `.set noreorder'. */ | |
207 | int noreorder; | |
741fe287 MR |
208 | /* Non-zero if we should not permit the register designated "assembler |
209 | temporary" to be used in instructions. The value is the register | |
210 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
211 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
212 | unsigned int at; | |
252b5132 RH |
213 | /* Non-zero if we should warn when a macro instruction expands into |
214 | more than one machine instruction. Changed by `.set nomacro' and | |
215 | `.set macro'. */ | |
216 | int warn_about_macros; | |
217 | /* Non-zero if we should not move instructions. Changed by `.set | |
218 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
219 | int nomove; | |
220 | /* Non-zero if we should not optimize branches by moving the target | |
221 | of the branch into the delay slot. Actually, we don't perform | |
222 | this optimization anyhow. Changed by `.set bopt' and `.set | |
223 | nobopt'. */ | |
224 | int nobopt; | |
225 | /* Non-zero if we should not autoextend mips16 instructions. | |
226 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
227 | int noautoextend; | |
a325df1d TS |
228 | /* Restrict general purpose registers and floating point registers |
229 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
230 | is passed but can changed if the assembler code uses .set mipsN. */ | |
231 | int gp32; | |
232 | int fp32; | |
fef14a42 TS |
233 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
234 | command line option, and the default CPU. */ | |
235 | int arch; | |
aed1a261 RS |
236 | /* True if ".set sym32" is in effect. */ |
237 | bfd_boolean sym32; | |
037b32b9 AN |
238 | /* True if floating-point operations are not allowed. Changed by .set |
239 | softfloat or .set hardfloat, by command line options -msoft-float or | |
240 | -mhard-float. The default is false. */ | |
241 | bfd_boolean soft_float; | |
242 | ||
243 | /* True if only single-precision floating-point operations are allowed. | |
244 | Changed by .set singlefloat or .set doublefloat, command-line options | |
245 | -msingle-float or -mdouble-float. The default is false. */ | |
246 | bfd_boolean single_float; | |
252b5132 RH |
247 | }; |
248 | ||
037b32b9 AN |
249 | /* This is the struct we use to hold the current set of options. Note |
250 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
251 | -1 to indicate that they have not been initialized. */ | |
252 | ||
a325df1d | 253 | /* True if -mgp32 was passed. */ |
a8e8e863 | 254 | static int file_mips_gp32 = -1; |
a325df1d TS |
255 | |
256 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 257 | static int file_mips_fp32 = -1; |
a325df1d | 258 | |
037b32b9 AN |
259 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
260 | static int file_mips_soft_float = 0; | |
261 | ||
262 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
263 | static int file_mips_single_float = 0; | |
252b5132 | 264 | |
e972090a NC |
265 | static struct mips_set_options mips_opts = |
266 | { | |
037b32b9 AN |
267 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
268 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
269 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
270 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
271 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
272 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 273 | }; |
252b5132 RH |
274 | |
275 | /* These variables are filled in with the masks of registers used. | |
276 | The object format code reads them and puts them in the appropriate | |
277 | place. */ | |
278 | unsigned long mips_gprmask; | |
279 | unsigned long mips_cprmask[4]; | |
280 | ||
281 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 282 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 283 | |
a4672219 TS |
284 | /* True if -mips16 was passed or implied by arguments passed on the |
285 | command line (e.g., by -march). */ | |
286 | static int file_ase_mips16; | |
287 | ||
3994f87e TS |
288 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
289 | || mips_opts.isa == ISA_MIPS32R2 \ | |
290 | || mips_opts.isa == ISA_MIPS64 \ | |
291 | || mips_opts.isa == ISA_MIPS64R2) | |
292 | ||
1f25f5d3 CD |
293 | /* True if -mips3d was passed or implied by arguments passed on the |
294 | command line (e.g., by -march). */ | |
295 | static int file_ase_mips3d; | |
296 | ||
deec1734 CD |
297 | /* True if -mdmx was passed or implied by arguments passed on the |
298 | command line (e.g., by -march). */ | |
299 | static int file_ase_mdmx; | |
300 | ||
e16bfa71 TS |
301 | /* True if -msmartmips was passed or implied by arguments passed on the |
302 | command line (e.g., by -march). */ | |
303 | static int file_ase_smartmips; | |
304 | ||
ad3fea08 TS |
305 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
306 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 307 | |
74cd071d CF |
308 | /* True if -mdsp was passed or implied by arguments passed on the |
309 | command line (e.g., by -march). */ | |
310 | static int file_ase_dsp; | |
311 | ||
ad3fea08 TS |
312 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
313 | || mips_opts.isa == ISA_MIPS64R2) | |
314 | ||
65263ce3 TS |
315 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
316 | ||
8b082fb1 TS |
317 | /* True if -mdspr2 was passed or implied by arguments passed on the |
318 | command line (e.g., by -march). */ | |
319 | static int file_ase_dspr2; | |
320 | ||
321 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
322 | || mips_opts.isa == ISA_MIPS64R2) | |
323 | ||
ef2e4d86 CF |
324 | /* True if -mmt was passed or implied by arguments passed on the |
325 | command line (e.g., by -march). */ | |
326 | static int file_ase_mt; | |
327 | ||
ad3fea08 TS |
328 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
329 | || mips_opts.isa == ISA_MIPS64R2) | |
330 | ||
ec68c924 | 331 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 332 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 333 | static const char *mips_arch_string; |
ec68c924 EC |
334 | |
335 | /* The argument of the -mtune= flag. The architecture for which we | |
336 | are optimizing. */ | |
337 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 338 | static const char *mips_tune_string; |
ec68c924 | 339 | |
316f5878 | 340 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
341 | static int mips_32bitmode = 0; |
342 | ||
316f5878 RS |
343 | /* True if the given ABI requires 32-bit registers. */ |
344 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
345 | ||
346 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
347 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
348 | ((ABI) == N32_ABI \ | |
349 | || (ABI) == N64_ABI \ | |
316f5878 RS |
350 | || (ABI) == O64_ABI) |
351 | ||
ad3fea08 | 352 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
353 | #define ISA_HAS_64BIT_REGS(ISA) \ |
354 | ((ISA) == ISA_MIPS3 \ | |
355 | || (ISA) == ISA_MIPS4 \ | |
356 | || (ISA) == ISA_MIPS5 \ | |
357 | || (ISA) == ISA_MIPS64 \ | |
358 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 359 | |
ad3fea08 TS |
360 | /* Return true if ISA supports 64 bit wide float registers. */ |
361 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS32R2 \ | |
366 | || (ISA) == ISA_MIPS64 \ | |
367 | || (ISA) == ISA_MIPS64R2) | |
368 | ||
af7ee8bf CD |
369 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
370 | instructions. */ | |
707bfff6 TS |
371 | #define ISA_HAS_DROR(ISA) \ |
372 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
373 | |
374 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
375 | instructions. */ | |
707bfff6 TS |
376 | #define ISA_HAS_ROR(ISA) \ |
377 | ((ISA) == ISA_MIPS32R2 \ | |
378 | || (ISA) == ISA_MIPS64R2 \ | |
379 | || mips_opts.ase_smartmips) | |
380 | ||
7455baf8 TS |
381 | /* Return true if ISA supports single-precision floats in odd registers. */ |
382 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
383 | ((ISA) == ISA_MIPS32 \ | |
384 | || (ISA) == ISA_MIPS32R2 \ | |
385 | || (ISA) == ISA_MIPS64 \ | |
386 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 387 | |
ad3fea08 TS |
388 | /* Return true if ISA supports move to/from high part of a 64-bit |
389 | floating-point register. */ | |
390 | #define ISA_HAS_MXHC1(ISA) \ | |
391 | ((ISA) == ISA_MIPS32R2 \ | |
392 | || (ISA) == ISA_MIPS64R2) | |
393 | ||
e013f690 | 394 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 395 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 396 | |
e013f690 | 397 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 398 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 399 | |
ad3fea08 TS |
400 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
401 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 402 | |
316f5878 | 403 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 404 | |
316f5878 | 405 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 406 | |
3b91255e RS |
407 | /* True if relocations are stored in-place. */ |
408 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
409 | ||
aed1a261 RS |
410 | /* The ABI-derived address size. */ |
411 | #define HAVE_64BIT_ADDRESSES \ | |
412 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
413 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 414 | |
aed1a261 RS |
415 | /* The size of symbolic constants (i.e., expressions of the form |
416 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
417 | #define HAVE_32BIT_SYMBOLS \ | |
418 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
419 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 420 | |
b7c7d6c1 TS |
421 | /* Addresses are loaded in different ways, depending on the address size |
422 | in use. The n32 ABI Documentation also mandates the use of additions | |
423 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 424 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 425 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
426 | |
427 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 428 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
429 | |
430 | #define ADDRESS_LOAD_INSN \ | |
431 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
432 | ||
433 | #define ADDRESS_STORE_INSN \ | |
434 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
435 | ||
a4672219 | 436 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
437 | #define CPU_HAS_MIPS16(cpu) \ |
438 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
439 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 440 | |
60b63b72 RS |
441 | /* True if CPU has a dror instruction. */ |
442 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
443 | ||
444 | /* True if CPU has a ror instruction. */ | |
445 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
446 | ||
c8978940 CD |
447 | /* True if mflo and mfhi can be immediately followed by instructions |
448 | which write to the HI and LO registers. | |
449 | ||
450 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
451 | (at least) two instructions between the reads of HI/LO and | |
452 | instructions which write them, and later ISAs do not. Contradicting | |
453 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
454 | the UM for the NEC Vr5000) document needing the instructions between | |
455 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
456 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
457 | earlier-ISA CPUs for which CPU documentation declares that the | |
458 | instructions are really interlocked. */ | |
459 | #define hilo_interlocks \ | |
460 | (mips_opts.isa == ISA_MIPS32 \ | |
461 | || mips_opts.isa == ISA_MIPS32R2 \ | |
462 | || mips_opts.isa == ISA_MIPS64 \ | |
463 | || mips_opts.isa == ISA_MIPS64R2 \ | |
464 | || mips_opts.arch == CPU_R4010 \ | |
465 | || mips_opts.arch == CPU_R10000 \ | |
466 | || mips_opts.arch == CPU_R12000 \ | |
467 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
468 | || mips_opts.arch == CPU_VR5500 \ |
469 | ) | |
252b5132 RH |
470 | |
471 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
472 | from the GPRs after they are loaded from memory, and thus does not |
473 | require nops to be inserted. This applies to instructions marked | |
474 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
475 | level I. */ | |
252b5132 | 476 | #define gpr_interlocks \ |
e7af610e | 477 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 478 | || mips_opts.arch == CPU_R3900) |
252b5132 | 479 | |
81912461 ILT |
480 | /* Whether the processor uses hardware interlocks to avoid delays |
481 | required by coprocessor instructions, and thus does not require | |
482 | nops to be inserted. This applies to instructions marked | |
483 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
484 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
485 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
486 | levels I, II, and III. */ | |
bdaaa2e1 | 487 | /* Itbl support may require additional care here. */ |
81912461 ILT |
488 | #define cop_interlocks \ |
489 | ((mips_opts.isa != ISA_MIPS1 \ | |
490 | && mips_opts.isa != ISA_MIPS2 \ | |
491 | && mips_opts.isa != ISA_MIPS3) \ | |
492 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
493 | ) |
494 | ||
495 | /* Whether the processor uses hardware interlocks to protect reads | |
496 | from coprocessor registers after they are loaded from memory, and | |
497 | thus does not require nops to be inserted. This applies to | |
498 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
499 | requires at MIPS ISA level I. */ | |
500 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 501 | |
6b76fefe CM |
502 | /* Is this a mfhi or mflo instruction? */ |
503 | #define MF_HILO_INSN(PINFO) \ | |
504 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
505 | ||
252b5132 RH |
506 | /* MIPS PIC level. */ |
507 | ||
a161fe53 | 508 | enum mips_pic_level mips_pic; |
252b5132 | 509 | |
c9914766 | 510 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 511 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 512 | static int mips_big_got = 0; |
252b5132 RH |
513 | |
514 | /* 1 if trap instructions should used for overflow rather than break | |
515 | instructions. */ | |
c9914766 | 516 | static int mips_trap = 0; |
252b5132 | 517 | |
119d663a | 518 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 519 | by assembling two single width halves into two single width floating |
119d663a NC |
520 | point registers which just happen to alias the double width destination |
521 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 522 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
523 | automatically at assemble time. */ |
524 | static int mips_disable_float_construction; | |
525 | ||
252b5132 RH |
526 | /* Non-zero if any .set noreorder directives were used. */ |
527 | ||
528 | static int mips_any_noreorder; | |
529 | ||
6b76fefe CM |
530 | /* Non-zero if nops should be inserted when the register referenced in |
531 | an mfhi/mflo instruction is read in the next two instructions. */ | |
532 | static int mips_7000_hilo_fix; | |
533 | ||
02ffd3e4 | 534 | /* The size of objects in the small data section. */ |
156c2f8b | 535 | static unsigned int g_switch_value = 8; |
252b5132 RH |
536 | /* Whether the -G option was used. */ |
537 | static int g_switch_seen = 0; | |
538 | ||
539 | #define N_RMASK 0xc4 | |
540 | #define N_VFP 0xd4 | |
541 | ||
542 | /* If we can determine in advance that GP optimization won't be | |
543 | possible, we can skip the relaxation stuff that tries to produce | |
544 | GP-relative references. This makes delay slot optimization work | |
545 | better. | |
546 | ||
547 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
548 | gcc output. It needs to guess right for gcc, otherwise gcc |
549 | will put what it thinks is a GP-relative instruction in a branch | |
550 | delay slot. | |
252b5132 RH |
551 | |
552 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
553 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 554 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
555 | |
556 | /* handle of the OPCODE hash table */ | |
557 | static struct hash_control *op_hash = NULL; | |
558 | ||
559 | /* The opcode hash table we use for the mips16. */ | |
560 | static struct hash_control *mips16_op_hash = NULL; | |
561 | ||
562 | /* This array holds the chars that always start a comment. If the | |
563 | pre-processor is disabled, these aren't very useful */ | |
564 | const char comment_chars[] = "#"; | |
565 | ||
566 | /* This array holds the chars that only start a comment at the beginning of | |
567 | a line. If the line seems to have the form '# 123 filename' | |
568 | .line and .file directives will appear in the pre-processed output */ | |
569 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
570 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 571 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
572 | /* Also note that C style comments are always supported. */ |
573 | const char line_comment_chars[] = "#"; | |
574 | ||
bdaaa2e1 | 575 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 576 | const char line_separator_chars[] = ";"; |
252b5132 RH |
577 | |
578 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
579 | const char EXP_CHARS[] = "eE"; | |
580 | ||
581 | /* Chars that mean this number is a floating point constant */ | |
582 | /* As in 0f12.456 */ | |
583 | /* or 0d1.2345e12 */ | |
584 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
585 | ||
586 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
587 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
588 | but nothing is ideal around here. | |
589 | */ | |
590 | ||
591 | static char *insn_error; | |
592 | ||
593 | static int auto_align = 1; | |
594 | ||
595 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
596 | offset in the stack frame from which to restore the $gp register. | |
597 | This is set by the .cprestore pseudo-op, and saved in this | |
598 | variable. */ | |
599 | static offsetT mips_cprestore_offset = -1; | |
600 | ||
67c1ffbe | 601 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 602 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 603 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
604 | static offsetT mips_cpreturn_offset = -1; |
605 | static int mips_cpreturn_register = -1; | |
606 | static int mips_gp_register = GP; | |
def2e0dd | 607 | static int mips_gprel_offset = 0; |
6478892d | 608 | |
7a621144 DJ |
609 | /* Whether mips_cprestore_offset has been set in the current function |
610 | (or whether it has already been warned about, if not). */ | |
611 | static int mips_cprestore_valid = 0; | |
612 | ||
252b5132 RH |
613 | /* This is the register which holds the stack frame, as set by the |
614 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
615 | static int mips_frame_reg = SP; | |
616 | ||
7a621144 DJ |
617 | /* Whether mips_frame_reg has been set in the current function |
618 | (or whether it has already been warned about, if not). */ | |
619 | static int mips_frame_reg_valid = 0; | |
620 | ||
252b5132 RH |
621 | /* To output NOP instructions correctly, we need to keep information |
622 | about the previous two instructions. */ | |
623 | ||
624 | /* Whether we are optimizing. The default value of 2 means to remove | |
625 | unneeded NOPs and swap branch instructions when possible. A value | |
626 | of 1 means to not swap branches. A value of 0 means to always | |
627 | insert NOPs. */ | |
628 | static int mips_optimize = 2; | |
629 | ||
630 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
631 | equivalent to seeing no -g option at all. */ | |
632 | static int mips_debug = 0; | |
633 | ||
7d8e00cf RS |
634 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
635 | #define MAX_VR4130_NOPS 4 | |
636 | ||
637 | /* The maximum number of NOPs needed to fill delay slots. */ | |
638 | #define MAX_DELAY_NOPS 2 | |
639 | ||
640 | /* The maximum number of NOPs needed for any purpose. */ | |
641 | #define MAX_NOPS 4 | |
71400594 RS |
642 | |
643 | /* A list of previous instructions, with index 0 being the most recent. | |
644 | We need to look back MAX_NOPS instructions when filling delay slots | |
645 | or working around processor errata. We need to look back one | |
646 | instruction further if we're thinking about using history[0] to | |
647 | fill a branch delay slot. */ | |
648 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 649 | |
1e915849 RS |
650 | /* Nop instructions used by emit_nop. */ |
651 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
652 | ||
653 | /* The appropriate nop for the current mode. */ | |
654 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 655 | |
252b5132 RH |
656 | /* If this is set, it points to a frag holding nop instructions which |
657 | were inserted before the start of a noreorder section. If those | |
658 | nops turn out to be unnecessary, the size of the frag can be | |
659 | decreased. */ | |
660 | static fragS *prev_nop_frag; | |
661 | ||
662 | /* The number of nop instructions we created in prev_nop_frag. */ | |
663 | static int prev_nop_frag_holds; | |
664 | ||
665 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 666 | prev_nop_frag. */ |
252b5132 RH |
667 | static int prev_nop_frag_required; |
668 | ||
669 | /* The number of instructions we've seen since prev_nop_frag. */ | |
670 | static int prev_nop_frag_since; | |
671 | ||
672 | /* For ECOFF and ELF, relocations against symbols are done in two | |
673 | parts, with a HI relocation and a LO relocation. Each relocation | |
674 | has only 16 bits of space to store an addend. This means that in | |
675 | order for the linker to handle carries correctly, it must be able | |
676 | to locate both the HI and the LO relocation. This means that the | |
677 | relocations must appear in order in the relocation table. | |
678 | ||
679 | In order to implement this, we keep track of each unmatched HI | |
680 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 681 | corresponding LO relocation. */ |
252b5132 | 682 | |
e972090a NC |
683 | struct mips_hi_fixup |
684 | { | |
252b5132 RH |
685 | /* Next HI fixup. */ |
686 | struct mips_hi_fixup *next; | |
687 | /* This fixup. */ | |
688 | fixS *fixp; | |
689 | /* The section this fixup is in. */ | |
690 | segT seg; | |
691 | }; | |
692 | ||
693 | /* The list of unmatched HI relocs. */ | |
694 | ||
695 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
696 | ||
64bdfcaf RS |
697 | /* The frag containing the last explicit relocation operator. |
698 | Null if explicit relocations have not been used. */ | |
699 | ||
700 | static fragS *prev_reloc_op_frag; | |
701 | ||
252b5132 RH |
702 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
703 | ||
704 | #define X ILLEGAL_REG | |
e972090a NC |
705 | static const int mips32_to_16_reg_map[] = |
706 | { | |
252b5132 RH |
707 | X, X, 2, 3, 4, 5, 6, 7, |
708 | X, X, X, X, X, X, X, X, | |
709 | 0, 1, X, X, X, X, X, X, | |
710 | X, X, X, X, X, X, X, X | |
711 | }; | |
712 | #undef X | |
713 | ||
714 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
715 | ||
e972090a NC |
716 | static const unsigned int mips16_to_32_reg_map[] = |
717 | { | |
252b5132 RH |
718 | 16, 17, 2, 3, 4, 5, 6, 7 |
719 | }; | |
60b63b72 | 720 | |
71400594 RS |
721 | /* Classifies the kind of instructions we're interested in when |
722 | implementing -mfix-vr4120. */ | |
723 | enum fix_vr4120_class { | |
724 | FIX_VR4120_MACC, | |
725 | FIX_VR4120_DMACC, | |
726 | FIX_VR4120_MULT, | |
727 | FIX_VR4120_DMULT, | |
728 | FIX_VR4120_DIV, | |
729 | FIX_VR4120_MTHILO, | |
730 | NUM_FIX_VR4120_CLASSES | |
731 | }; | |
732 | ||
733 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
734 | there must be at least one other instruction between an instruction | |
735 | of type X and an instruction of type Y. */ | |
736 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
737 | ||
738 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 739 | static int mips_fix_vr4120; |
4a6a3df4 | 740 | |
7d8e00cf RS |
741 | /* ...likewise -mfix-vr4130. */ |
742 | static int mips_fix_vr4130; | |
743 | ||
4a6a3df4 AO |
744 | /* We don't relax branches by default, since this causes us to expand |
745 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
746 | fail to compute the offset before expanding the macro to the most | |
747 | efficient expansion. */ | |
748 | ||
749 | static int mips_relax_branch; | |
252b5132 | 750 | \f |
4d7206a2 RS |
751 | /* The expansion of many macros depends on the type of symbol that |
752 | they refer to. For example, when generating position-dependent code, | |
753 | a macro that refers to a symbol may have two different expansions, | |
754 | one which uses GP-relative addresses and one which uses absolute | |
755 | addresses. When generating SVR4-style PIC, a macro may have | |
756 | different expansions for local and global symbols. | |
757 | ||
758 | We handle these situations by generating both sequences and putting | |
759 | them in variant frags. In position-dependent code, the first sequence | |
760 | will be the GP-relative one and the second sequence will be the | |
761 | absolute one. In SVR4 PIC, the first sequence will be for global | |
762 | symbols and the second will be for local symbols. | |
763 | ||
584892a6 RS |
764 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
765 | SECOND are the lengths of the two sequences in bytes. These fields | |
766 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
767 | the subtype has the following flags: | |
4d7206a2 | 768 | |
584892a6 RS |
769 | RELAX_USE_SECOND |
770 | Set if it has been decided that we should use the second | |
771 | sequence instead of the first. | |
772 | ||
773 | RELAX_SECOND_LONGER | |
774 | Set in the first variant frag if the macro's second implementation | |
775 | is longer than its first. This refers to the macro as a whole, | |
776 | not an individual relaxation. | |
777 | ||
778 | RELAX_NOMACRO | |
779 | Set in the first variant frag if the macro appeared in a .set nomacro | |
780 | block and if one alternative requires a warning but the other does not. | |
781 | ||
782 | RELAX_DELAY_SLOT | |
783 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
784 | delay slot. | |
4d7206a2 RS |
785 | |
786 | The frag's "opcode" points to the first fixup for relaxable code. | |
787 | ||
788 | Relaxable macros are generated using a sequence such as: | |
789 | ||
790 | relax_start (SYMBOL); | |
791 | ... generate first expansion ... | |
792 | relax_switch (); | |
793 | ... generate second expansion ... | |
794 | relax_end (); | |
795 | ||
796 | The code and fixups for the unwanted alternative are discarded | |
797 | by md_convert_frag. */ | |
584892a6 | 798 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 799 | |
584892a6 RS |
800 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
801 | #define RELAX_SECOND(X) ((X) & 0xff) | |
802 | #define RELAX_USE_SECOND 0x10000 | |
803 | #define RELAX_SECOND_LONGER 0x20000 | |
804 | #define RELAX_NOMACRO 0x40000 | |
805 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 806 | |
4a6a3df4 AO |
807 | /* Branch without likely bit. If label is out of range, we turn: |
808 | ||
809 | beq reg1, reg2, label | |
810 | delay slot | |
811 | ||
812 | into | |
813 | ||
814 | bne reg1, reg2, 0f | |
815 | nop | |
816 | j label | |
817 | 0: delay slot | |
818 | ||
819 | with the following opcode replacements: | |
820 | ||
821 | beq <-> bne | |
822 | blez <-> bgtz | |
823 | bltz <-> bgez | |
824 | bc1f <-> bc1t | |
825 | ||
826 | bltzal <-> bgezal (with jal label instead of j label) | |
827 | ||
828 | Even though keeping the delay slot instruction in the delay slot of | |
829 | the branch would be more efficient, it would be very tricky to do | |
830 | correctly, because we'd have to introduce a variable frag *after* | |
831 | the delay slot instruction, and expand that instead. Let's do it | |
832 | the easy way for now, even if the branch-not-taken case now costs | |
833 | one additional instruction. Out-of-range branches are not supposed | |
834 | to be common, anyway. | |
835 | ||
836 | Branch likely. If label is out of range, we turn: | |
837 | ||
838 | beql reg1, reg2, label | |
839 | delay slot (annulled if branch not taken) | |
840 | ||
841 | into | |
842 | ||
843 | beql reg1, reg2, 1f | |
844 | nop | |
845 | beql $0, $0, 2f | |
846 | nop | |
847 | 1: j[al] label | |
848 | delay slot (executed only if branch taken) | |
849 | 2: | |
850 | ||
851 | It would be possible to generate a shorter sequence by losing the | |
852 | likely bit, generating something like: | |
b34976b6 | 853 | |
4a6a3df4 AO |
854 | bne reg1, reg2, 0f |
855 | nop | |
856 | j[al] label | |
857 | delay slot (executed only if branch taken) | |
858 | 0: | |
859 | ||
860 | beql -> bne | |
861 | bnel -> beq | |
862 | blezl -> bgtz | |
863 | bgtzl -> blez | |
864 | bltzl -> bgez | |
865 | bgezl -> bltz | |
866 | bc1fl -> bc1t | |
867 | bc1tl -> bc1f | |
868 | ||
869 | bltzall -> bgezal (with jal label instead of j label) | |
870 | bgezall -> bltzal (ditto) | |
871 | ||
872 | ||
873 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 874 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
875 | ((relax_substateT) \ |
876 | (0xc0000000 \ | |
877 | | ((toofar) ? 1 : 0) \ | |
878 | | ((link) ? 2 : 0) \ | |
879 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 880 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 881 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
882 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
883 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
884 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 885 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 886 | |
252b5132 RH |
887 | /* For mips16 code, we use an entirely different form of relaxation. |
888 | mips16 supports two versions of most instructions which take | |
889 | immediate values: a small one which takes some small value, and a | |
890 | larger one which takes a 16 bit value. Since branches also follow | |
891 | this pattern, relaxing these values is required. | |
892 | ||
893 | We can assemble both mips16 and normal MIPS code in a single | |
894 | object. Therefore, we need to support this type of relaxation at | |
895 | the same time that we support the relaxation described above. We | |
896 | use the high bit of the subtype field to distinguish these cases. | |
897 | ||
898 | The information we store for this type of relaxation is the | |
899 | argument code found in the opcode file for this relocation, whether | |
900 | the user explicitly requested a small or extended form, and whether | |
901 | the relocation is in a jump or jal delay slot. That tells us the | |
902 | size of the value, and how it should be stored. We also store | |
903 | whether the fragment is considered to be extended or not. We also | |
904 | store whether this is known to be a branch to a different section, | |
905 | whether we have tried to relax this frag yet, and whether we have | |
906 | ever extended a PC relative fragment because of a shift count. */ | |
907 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
908 | (0x80000000 \ | |
909 | | ((type) & 0xff) \ | |
910 | | ((small) ? 0x100 : 0) \ | |
911 | | ((ext) ? 0x200 : 0) \ | |
912 | | ((dslot) ? 0x400 : 0) \ | |
913 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 914 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
915 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
916 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
917 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
918 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
919 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
920 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
921 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
922 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
923 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
924 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
925 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
926 | |
927 | /* Is the given value a sign-extended 32-bit value? */ | |
928 | #define IS_SEXT_32BIT_NUM(x) \ | |
929 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
930 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
931 | ||
932 | /* Is the given value a sign-extended 16-bit value? */ | |
933 | #define IS_SEXT_16BIT_NUM(x) \ | |
934 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
935 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
936 | ||
2051e8c4 MR |
937 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
938 | #define IS_ZEXT_32BIT_NUM(x) \ | |
939 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
940 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
941 | ||
bf12938e RS |
942 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
943 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
944 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
945 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
946 | | (((VALUE) & (MASK)) << (SHIFT))) | |
947 | ||
948 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
949 | SHIFT places. */ | |
950 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
951 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
952 | ||
953 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
954 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
955 | ||
956 | include/opcode/mips.h specifies operand fields using the macros | |
957 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
958 | with "MIPS16OP" instead of "OP". */ | |
959 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
960 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
961 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
962 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
963 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
964 | ||
965 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
966 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
967 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
968 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
969 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
970 | MIPS16OP_MASK_##FIELD, \ | |
971 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
972 | \f |
973 | /* Global variables used when generating relaxable macros. See the | |
974 | comment above RELAX_ENCODE for more details about how relaxation | |
975 | is used. */ | |
976 | static struct { | |
977 | /* 0 if we're not emitting a relaxable macro. | |
978 | 1 if we're emitting the first of the two relaxation alternatives. | |
979 | 2 if we're emitting the second alternative. */ | |
980 | int sequence; | |
981 | ||
982 | /* The first relaxable fixup in the current frag. (In other words, | |
983 | the first fixup that refers to relaxable code.) */ | |
984 | fixS *first_fixup; | |
985 | ||
986 | /* sizes[0] says how many bytes of the first alternative are stored in | |
987 | the current frag. Likewise sizes[1] for the second alternative. */ | |
988 | unsigned int sizes[2]; | |
989 | ||
990 | /* The symbol on which the choice of sequence depends. */ | |
991 | symbolS *symbol; | |
992 | } mips_relax; | |
252b5132 | 993 | \f |
584892a6 RS |
994 | /* Global variables used to decide whether a macro needs a warning. */ |
995 | static struct { | |
996 | /* True if the macro is in a branch delay slot. */ | |
997 | bfd_boolean delay_slot_p; | |
998 | ||
999 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1000 | in bytes and sizes[1] is the length of the second alternative. | |
1001 | For non-relaxable macros, both elements give the length of the | |
1002 | macro in bytes. */ | |
1003 | unsigned int sizes[2]; | |
1004 | ||
1005 | /* The first variant frag for this macro. */ | |
1006 | fragS *first_frag; | |
1007 | } mips_macro_warning; | |
1008 | \f | |
252b5132 RH |
1009 | /* Prototypes for static functions. */ |
1010 | ||
17a2f251 | 1011 | #define internalError() \ |
252b5132 | 1012 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1013 | |
1014 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1015 | ||
b34976b6 | 1016 | static void append_insn |
4d7206a2 | 1017 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 1018 | static void mips_no_prev_insn (void); |
b34976b6 | 1019 | static void mips16_macro_build |
67c0d1eb RS |
1020 | (expressionS *, const char *, const char *, va_list); |
1021 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
1022 | static void macro_start (void); |
1023 | static void macro_end (void); | |
17a2f251 TS |
1024 | static void macro (struct mips_cl_insn * ip); |
1025 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 1026 | #ifdef LOSING_COMPILER |
17a2f251 | 1027 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 1028 | #endif |
17a2f251 TS |
1029 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1030 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1031 | static void mips16_immed |
17a2f251 TS |
1032 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1033 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1034 | static size_t my_getSmallExpression |
17a2f251 TS |
1035 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1036 | static void my_getExpression (expressionS *, char *); | |
1037 | static void s_align (int); | |
1038 | static void s_change_sec (int); | |
1039 | static void s_change_section (int); | |
1040 | static void s_cons (int); | |
1041 | static void s_float_cons (int); | |
1042 | static void s_mips_globl (int); | |
1043 | static void s_option (int); | |
1044 | static void s_mipsset (int); | |
1045 | static void s_abicalls (int); | |
1046 | static void s_cpload (int); | |
1047 | static void s_cpsetup (int); | |
1048 | static void s_cplocal (int); | |
1049 | static void s_cprestore (int); | |
1050 | static void s_cpreturn (int); | |
741d6ea8 JM |
1051 | static void s_dtprelword (int); |
1052 | static void s_dtpreldword (int); | |
17a2f251 TS |
1053 | static void s_gpvalue (int); |
1054 | static void s_gpword (int); | |
1055 | static void s_gpdword (int); | |
1056 | static void s_cpadd (int); | |
1057 | static void s_insn (int); | |
1058 | static void md_obj_begin (void); | |
1059 | static void md_obj_end (void); | |
1060 | static void s_mips_ent (int); | |
1061 | static void s_mips_end (int); | |
1062 | static void s_mips_frame (int); | |
1063 | static void s_mips_mask (int reg_type); | |
1064 | static void s_mips_stab (int); | |
1065 | static void s_mips_weakext (int); | |
1066 | static void s_mips_file (int); | |
1067 | static void s_mips_loc (int); | |
1068 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1069 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1070 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1071 | |
1072 | /* Table and functions used to map between CPU/ISA names, and | |
1073 | ISA levels, and CPU numbers. */ | |
1074 | ||
e972090a NC |
1075 | struct mips_cpu_info |
1076 | { | |
e7af610e | 1077 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1078 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1079 | int isa; /* ISA level. */ |
1080 | int cpu; /* CPU number (default CPU if ISA). */ | |
1081 | }; | |
1082 | ||
ad3fea08 TS |
1083 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1084 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1085 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1086 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1087 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1088 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1089 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1090 | |
17a2f251 TS |
1091 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1092 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1093 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1094 | \f |
1095 | /* Pseudo-op table. | |
1096 | ||
1097 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1098 | should be defined here, but are currently unsupported: .alias, | |
1099 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1100 | ||
1101 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1102 | specific to the type of debugging information being generated, and | |
1103 | should be defined by the object format: .aent, .begin, .bend, | |
1104 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1105 | .vreg. | |
1106 | ||
1107 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1108 | not MIPS CPU specific, but are also not specific to the object file | |
1109 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1110 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1111 | |
e972090a NC |
1112 | static const pseudo_typeS mips_pseudo_table[] = |
1113 | { | |
beae10d5 | 1114 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1115 | {"option", s_option, 0}, |
1116 | {"set", s_mipsset, 0}, | |
1117 | {"rdata", s_change_sec, 'r'}, | |
1118 | {"sdata", s_change_sec, 's'}, | |
1119 | {"livereg", s_ignore, 0}, | |
1120 | {"abicalls", s_abicalls, 0}, | |
1121 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1122 | {"cpsetup", s_cpsetup, 0}, |
1123 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1124 | {"cprestore", s_cprestore, 0}, |
6478892d | 1125 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1126 | {"dtprelword", s_dtprelword, 0}, |
1127 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1128 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1129 | {"gpword", s_gpword, 0}, |
10181a0d | 1130 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1131 | {"cpadd", s_cpadd, 0}, |
1132 | {"insn", s_insn, 0}, | |
1133 | ||
beae10d5 | 1134 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1135 | chips. */ |
38a57ae7 | 1136 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1137 | {"bss", s_change_sec, 'b'}, |
1138 | {"err", s_err, 0}, | |
1139 | {"half", s_cons, 1}, | |
1140 | {"dword", s_cons, 3}, | |
1141 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1142 | {"origin", s_org, 0}, |
1143 | {"repeat", s_rept, 0}, | |
252b5132 | 1144 | |
beae10d5 | 1145 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1146 | here for one reason or another. */ |
1147 | {"align", s_align, 0}, | |
1148 | {"byte", s_cons, 0}, | |
1149 | {"data", s_change_sec, 'd'}, | |
1150 | {"double", s_float_cons, 'd'}, | |
1151 | {"float", s_float_cons, 'f'}, | |
1152 | {"globl", s_mips_globl, 0}, | |
1153 | {"global", s_mips_globl, 0}, | |
1154 | {"hword", s_cons, 1}, | |
1155 | {"int", s_cons, 2}, | |
1156 | {"long", s_cons, 2}, | |
1157 | {"octa", s_cons, 4}, | |
1158 | {"quad", s_cons, 3}, | |
cca86cc8 | 1159 | {"section", s_change_section, 0}, |
252b5132 RH |
1160 | {"short", s_cons, 1}, |
1161 | {"single", s_float_cons, 'f'}, | |
1162 | {"stabn", s_mips_stab, 'n'}, | |
1163 | {"text", s_change_sec, 't'}, | |
1164 | {"word", s_cons, 2}, | |
add56521 | 1165 | |
add56521 | 1166 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1167 | |
43841e91 | 1168 | { NULL, NULL, 0 }, |
252b5132 RH |
1169 | }; |
1170 | ||
e972090a NC |
1171 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1172 | { | |
beae10d5 KH |
1173 | /* These pseudo-ops should be defined by the object file format. |
1174 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1175 | {"aent", s_mips_ent, 1}, |
1176 | {"bgnb", s_ignore, 0}, | |
1177 | {"end", s_mips_end, 0}, | |
1178 | {"endb", s_ignore, 0}, | |
1179 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1180 | {"file", s_mips_file, 0}, |
252b5132 RH |
1181 | {"fmask", s_mips_mask, 'F'}, |
1182 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1183 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1184 | {"mask", s_mips_mask, 'R'}, |
1185 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1186 | { NULL, NULL, 0 }, |
252b5132 RH |
1187 | }; |
1188 | ||
17a2f251 | 1189 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1190 | |
1191 | void | |
17a2f251 | 1192 | mips_pop_insert (void) |
252b5132 RH |
1193 | { |
1194 | pop_insert (mips_pseudo_table); | |
1195 | if (! ECOFF_DEBUGGING) | |
1196 | pop_insert (mips_nonecoff_pseudo_table); | |
1197 | } | |
1198 | \f | |
1199 | /* Symbols labelling the current insn. */ | |
1200 | ||
e972090a NC |
1201 | struct insn_label_list |
1202 | { | |
252b5132 RH |
1203 | struct insn_label_list *next; |
1204 | symbolS *label; | |
1205 | }; | |
1206 | ||
252b5132 | 1207 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1208 | #define label_list tc_segment_info_data.labels |
252b5132 | 1209 | |
17a2f251 | 1210 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1211 | |
1212 | static inline void | |
17a2f251 | 1213 | mips_clear_insn_labels (void) |
252b5132 RH |
1214 | { |
1215 | register struct insn_label_list **pl; | |
a8dbcb85 | 1216 | segment_info_type *si; |
252b5132 | 1217 | |
a8dbcb85 TS |
1218 | if (now_seg) |
1219 | { | |
1220 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1221 | ; | |
1222 | ||
1223 | si = seg_info (now_seg); | |
1224 | *pl = si->label_list; | |
1225 | si->label_list = NULL; | |
1226 | } | |
252b5132 | 1227 | } |
a8dbcb85 | 1228 | |
252b5132 RH |
1229 | \f |
1230 | static char *expr_end; | |
1231 | ||
1232 | /* Expressions which appear in instructions. These are set by | |
1233 | mips_ip. */ | |
1234 | ||
1235 | static expressionS imm_expr; | |
5f74bc13 | 1236 | static expressionS imm2_expr; |
252b5132 RH |
1237 | static expressionS offset_expr; |
1238 | ||
1239 | /* Relocs associated with imm_expr and offset_expr. */ | |
1240 | ||
f6688943 TS |
1241 | static bfd_reloc_code_real_type imm_reloc[3] |
1242 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1243 | static bfd_reloc_code_real_type offset_reloc[3] | |
1244 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1245 | |
252b5132 RH |
1246 | /* These are set by mips16_ip if an explicit extension is used. */ |
1247 | ||
b34976b6 | 1248 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1249 | |
7ed4a06a | 1250 | #ifdef OBJ_ELF |
ecb4347a DJ |
1251 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1252 | ECOFF debugging. */ | |
252b5132 RH |
1253 | |
1254 | static segT pdr_seg; | |
7ed4a06a | 1255 | #endif |
252b5132 | 1256 | |
e013f690 TS |
1257 | /* The default target format to use. */ |
1258 | ||
1259 | const char * | |
17a2f251 | 1260 | mips_target_format (void) |
e013f690 TS |
1261 | { |
1262 | switch (OUTPUT_FLAVOR) | |
1263 | { | |
e013f690 TS |
1264 | case bfd_target_ecoff_flavour: |
1265 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1266 | case bfd_target_coff_flavour: | |
1267 | return "pe-mips"; | |
1268 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1269 | #ifdef TE_VXWORKS |
1270 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1271 | return (target_big_endian | |
1272 | ? "elf32-bigmips-vxworks" | |
1273 | : "elf32-littlemips-vxworks"); | |
1274 | #endif | |
e013f690 | 1275 | #ifdef TE_TMIPS |
cfe86eaa | 1276 | /* This is traditional mips. */ |
e013f690 | 1277 | return (target_big_endian |
cfe86eaa TS |
1278 | ? (HAVE_64BIT_OBJECTS |
1279 | ? "elf64-tradbigmips" | |
1280 | : (HAVE_NEWABI | |
1281 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1282 | : (HAVE_64BIT_OBJECTS | |
1283 | ? "elf64-tradlittlemips" | |
1284 | : (HAVE_NEWABI | |
1285 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1286 | #else |
1287 | return (target_big_endian | |
cfe86eaa TS |
1288 | ? (HAVE_64BIT_OBJECTS |
1289 | ? "elf64-bigmips" | |
1290 | : (HAVE_NEWABI | |
1291 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1292 | : (HAVE_64BIT_OBJECTS | |
1293 | ? "elf64-littlemips" | |
1294 | : (HAVE_NEWABI | |
1295 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1296 | #endif |
1297 | default: | |
1298 | abort (); | |
1299 | return NULL; | |
1300 | } | |
1301 | } | |
1302 | ||
1e915849 RS |
1303 | /* Return the length of instruction INSN. */ |
1304 | ||
1305 | static inline unsigned int | |
1306 | insn_length (const struct mips_cl_insn *insn) | |
1307 | { | |
1308 | if (!mips_opts.mips16) | |
1309 | return 4; | |
1310 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1311 | } | |
1312 | ||
1313 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1314 | ||
1315 | static void | |
1316 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1317 | { | |
1318 | size_t i; | |
1319 | ||
1320 | insn->insn_mo = mo; | |
1321 | insn->use_extend = FALSE; | |
1322 | insn->extend = 0; | |
1323 | insn->insn_opcode = mo->match; | |
1324 | insn->frag = NULL; | |
1325 | insn->where = 0; | |
1326 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1327 | insn->fixp[i] = NULL; | |
1328 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1329 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1330 | insn->mips16_absolute_jump_p = 0; | |
1331 | } | |
1332 | ||
742a56fe RS |
1333 | /* Record the current MIPS16 mode in now_seg. */ |
1334 | ||
1335 | static void | |
1336 | mips_record_mips16_mode (void) | |
1337 | { | |
1338 | segment_info_type *si; | |
1339 | ||
1340 | si = seg_info (now_seg); | |
1341 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1342 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1343 | } | |
1344 | ||
1e915849 RS |
1345 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1346 | ||
1347 | static void | |
1348 | install_insn (const struct mips_cl_insn *insn) | |
1349 | { | |
1350 | char *f = insn->frag->fr_literal + insn->where; | |
1351 | if (!mips_opts.mips16) | |
1352 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1353 | else if (insn->mips16_absolute_jump_p) | |
1354 | { | |
1355 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1356 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1357 | } | |
1358 | else | |
1359 | { | |
1360 | if (insn->use_extend) | |
1361 | { | |
1362 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1363 | f += 2; | |
1364 | } | |
1365 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1366 | } | |
742a56fe | 1367 | mips_record_mips16_mode (); |
1e915849 RS |
1368 | } |
1369 | ||
1370 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1371 | and install the opcode in the new location. */ | |
1372 | ||
1373 | static void | |
1374 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1375 | { | |
1376 | size_t i; | |
1377 | ||
1378 | insn->frag = frag; | |
1379 | insn->where = where; | |
1380 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1381 | if (insn->fixp[i] != NULL) | |
1382 | { | |
1383 | insn->fixp[i]->fx_frag = frag; | |
1384 | insn->fixp[i]->fx_where = where; | |
1385 | } | |
1386 | install_insn (insn); | |
1387 | } | |
1388 | ||
1389 | /* Add INSN to the end of the output. */ | |
1390 | ||
1391 | static void | |
1392 | add_fixed_insn (struct mips_cl_insn *insn) | |
1393 | { | |
1394 | char *f = frag_more (insn_length (insn)); | |
1395 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1396 | } | |
1397 | ||
1398 | /* Start a variant frag and move INSN to the start of the variant part, | |
1399 | marking it as fixed. The other arguments are as for frag_var. */ | |
1400 | ||
1401 | static void | |
1402 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1403 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1404 | { | |
1405 | frag_grow (max_chars); | |
1406 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1407 | insn->fixed_p = 1; | |
1408 | frag_var (rs_machine_dependent, max_chars, var, | |
1409 | subtype, symbol, offset, NULL); | |
1410 | } | |
1411 | ||
1412 | /* Insert N copies of INSN into the history buffer, starting at | |
1413 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1414 | ||
1415 | static void | |
1416 | insert_into_history (unsigned int first, unsigned int n, | |
1417 | const struct mips_cl_insn *insn) | |
1418 | { | |
1419 | if (mips_relax.sequence != 2) | |
1420 | { | |
1421 | unsigned int i; | |
1422 | ||
1423 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1424 | if (i >= first + n) | |
1425 | history[i] = history[i - n]; | |
1426 | else | |
1427 | history[i] = *insn; | |
1428 | } | |
1429 | } | |
1430 | ||
1431 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1432 | ||
1433 | static void | |
1434 | emit_nop (void) | |
1435 | { | |
1436 | add_fixed_insn (NOP_INSN); | |
1437 | insert_into_history (0, 1, NOP_INSN); | |
1438 | } | |
1439 | ||
71400594 RS |
1440 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1441 | the idea is to make it obvious at a glance that each errata is | |
1442 | included. */ | |
1443 | ||
1444 | static void | |
1445 | init_vr4120_conflicts (void) | |
1446 | { | |
1447 | #define CONFLICT(FIRST, SECOND) \ | |
1448 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1449 | ||
1450 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1451 | CONFLICT (MACC, DIV); | |
1452 | CONFLICT (DMACC, DIV); | |
1453 | ||
1454 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1455 | CONFLICT (DMULT, DMULT); | |
1456 | CONFLICT (DMULT, DMACC); | |
1457 | CONFLICT (DMACC, DMULT); | |
1458 | CONFLICT (DMACC, DMACC); | |
1459 | ||
1460 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1461 | CONFLICT (MACC, MTHILO); | |
1462 | CONFLICT (DMACC, MTHILO); | |
1463 | ||
1464 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1465 | instruction is executed immediately after a MACC or DMACC | |
1466 | instruction, the result of [either instruction] is incorrect." */ | |
1467 | CONFLICT (MACC, MULT); | |
1468 | CONFLICT (MACC, DMULT); | |
1469 | CONFLICT (DMACC, MULT); | |
1470 | CONFLICT (DMACC, DMULT); | |
1471 | ||
1472 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1473 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1474 | DDIV or DDIVU instruction, the result of the MACC or | |
1475 | DMACC instruction is incorrect.". */ | |
1476 | CONFLICT (DMULT, MACC); | |
1477 | CONFLICT (DMULT, DMACC); | |
1478 | CONFLICT (DIV, MACC); | |
1479 | CONFLICT (DIV, DMACC); | |
1480 | ||
1481 | #undef CONFLICT | |
1482 | } | |
1483 | ||
707bfff6 TS |
1484 | struct regname { |
1485 | const char *name; | |
1486 | unsigned int num; | |
1487 | }; | |
1488 | ||
1489 | #define RTYPE_MASK 0x1ff00 | |
1490 | #define RTYPE_NUM 0x00100 | |
1491 | #define RTYPE_FPU 0x00200 | |
1492 | #define RTYPE_FCC 0x00400 | |
1493 | #define RTYPE_VEC 0x00800 | |
1494 | #define RTYPE_GP 0x01000 | |
1495 | #define RTYPE_CP0 0x02000 | |
1496 | #define RTYPE_PC 0x04000 | |
1497 | #define RTYPE_ACC 0x08000 | |
1498 | #define RTYPE_CCC 0x10000 | |
1499 | #define RNUM_MASK 0x000ff | |
1500 | #define RWARN 0x80000 | |
1501 | ||
1502 | #define GENERIC_REGISTER_NUMBERS \ | |
1503 | {"$0", RTYPE_NUM | 0}, \ | |
1504 | {"$1", RTYPE_NUM | 1}, \ | |
1505 | {"$2", RTYPE_NUM | 2}, \ | |
1506 | {"$3", RTYPE_NUM | 3}, \ | |
1507 | {"$4", RTYPE_NUM | 4}, \ | |
1508 | {"$5", RTYPE_NUM | 5}, \ | |
1509 | {"$6", RTYPE_NUM | 6}, \ | |
1510 | {"$7", RTYPE_NUM | 7}, \ | |
1511 | {"$8", RTYPE_NUM | 8}, \ | |
1512 | {"$9", RTYPE_NUM | 9}, \ | |
1513 | {"$10", RTYPE_NUM | 10}, \ | |
1514 | {"$11", RTYPE_NUM | 11}, \ | |
1515 | {"$12", RTYPE_NUM | 12}, \ | |
1516 | {"$13", RTYPE_NUM | 13}, \ | |
1517 | {"$14", RTYPE_NUM | 14}, \ | |
1518 | {"$15", RTYPE_NUM | 15}, \ | |
1519 | {"$16", RTYPE_NUM | 16}, \ | |
1520 | {"$17", RTYPE_NUM | 17}, \ | |
1521 | {"$18", RTYPE_NUM | 18}, \ | |
1522 | {"$19", RTYPE_NUM | 19}, \ | |
1523 | {"$20", RTYPE_NUM | 20}, \ | |
1524 | {"$21", RTYPE_NUM | 21}, \ | |
1525 | {"$22", RTYPE_NUM | 22}, \ | |
1526 | {"$23", RTYPE_NUM | 23}, \ | |
1527 | {"$24", RTYPE_NUM | 24}, \ | |
1528 | {"$25", RTYPE_NUM | 25}, \ | |
1529 | {"$26", RTYPE_NUM | 26}, \ | |
1530 | {"$27", RTYPE_NUM | 27}, \ | |
1531 | {"$28", RTYPE_NUM | 28}, \ | |
1532 | {"$29", RTYPE_NUM | 29}, \ | |
1533 | {"$30", RTYPE_NUM | 30}, \ | |
1534 | {"$31", RTYPE_NUM | 31} | |
1535 | ||
1536 | #define FPU_REGISTER_NAMES \ | |
1537 | {"$f0", RTYPE_FPU | 0}, \ | |
1538 | {"$f1", RTYPE_FPU | 1}, \ | |
1539 | {"$f2", RTYPE_FPU | 2}, \ | |
1540 | {"$f3", RTYPE_FPU | 3}, \ | |
1541 | {"$f4", RTYPE_FPU | 4}, \ | |
1542 | {"$f5", RTYPE_FPU | 5}, \ | |
1543 | {"$f6", RTYPE_FPU | 6}, \ | |
1544 | {"$f7", RTYPE_FPU | 7}, \ | |
1545 | {"$f8", RTYPE_FPU | 8}, \ | |
1546 | {"$f9", RTYPE_FPU | 9}, \ | |
1547 | {"$f10", RTYPE_FPU | 10}, \ | |
1548 | {"$f11", RTYPE_FPU | 11}, \ | |
1549 | {"$f12", RTYPE_FPU | 12}, \ | |
1550 | {"$f13", RTYPE_FPU | 13}, \ | |
1551 | {"$f14", RTYPE_FPU | 14}, \ | |
1552 | {"$f15", RTYPE_FPU | 15}, \ | |
1553 | {"$f16", RTYPE_FPU | 16}, \ | |
1554 | {"$f17", RTYPE_FPU | 17}, \ | |
1555 | {"$f18", RTYPE_FPU | 18}, \ | |
1556 | {"$f19", RTYPE_FPU | 19}, \ | |
1557 | {"$f20", RTYPE_FPU | 20}, \ | |
1558 | {"$f21", RTYPE_FPU | 21}, \ | |
1559 | {"$f22", RTYPE_FPU | 22}, \ | |
1560 | {"$f23", RTYPE_FPU | 23}, \ | |
1561 | {"$f24", RTYPE_FPU | 24}, \ | |
1562 | {"$f25", RTYPE_FPU | 25}, \ | |
1563 | {"$f26", RTYPE_FPU | 26}, \ | |
1564 | {"$f27", RTYPE_FPU | 27}, \ | |
1565 | {"$f28", RTYPE_FPU | 28}, \ | |
1566 | {"$f29", RTYPE_FPU | 29}, \ | |
1567 | {"$f30", RTYPE_FPU | 30}, \ | |
1568 | {"$f31", RTYPE_FPU | 31} | |
1569 | ||
1570 | #define FPU_CONDITION_CODE_NAMES \ | |
1571 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1572 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1573 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1574 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1575 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1576 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1577 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1578 | {"$fcc7", RTYPE_FCC | 7} | |
1579 | ||
1580 | #define COPROC_CONDITION_CODE_NAMES \ | |
1581 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1582 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1583 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1584 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1585 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1586 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1587 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1588 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1589 | ||
1590 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1591 | {"$a4", RTYPE_GP | 8}, \ | |
1592 | {"$a5", RTYPE_GP | 9}, \ | |
1593 | {"$a6", RTYPE_GP | 10}, \ | |
1594 | {"$a7", RTYPE_GP | 11}, \ | |
1595 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1596 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1597 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1598 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1599 | {"$t0", RTYPE_GP | 12}, \ | |
1600 | {"$t1", RTYPE_GP | 13}, \ | |
1601 | {"$t2", RTYPE_GP | 14}, \ | |
1602 | {"$t3", RTYPE_GP | 15} | |
1603 | ||
1604 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1605 | {"$t0", RTYPE_GP | 8}, \ | |
1606 | {"$t1", RTYPE_GP | 9}, \ | |
1607 | {"$t2", RTYPE_GP | 10}, \ | |
1608 | {"$t3", RTYPE_GP | 11}, \ | |
1609 | {"$t4", RTYPE_GP | 12}, \ | |
1610 | {"$t5", RTYPE_GP | 13}, \ | |
1611 | {"$t6", RTYPE_GP | 14}, \ | |
1612 | {"$t7", RTYPE_GP | 15}, \ | |
1613 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1614 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1615 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1616 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1617 | ||
1618 | /* Remaining symbolic register names */ | |
1619 | #define SYMBOLIC_REGISTER_NAMES \ | |
1620 | {"$zero", RTYPE_GP | 0}, \ | |
1621 | {"$at", RTYPE_GP | 1}, \ | |
1622 | {"$AT", RTYPE_GP | 1}, \ | |
1623 | {"$v0", RTYPE_GP | 2}, \ | |
1624 | {"$v1", RTYPE_GP | 3}, \ | |
1625 | {"$a0", RTYPE_GP | 4}, \ | |
1626 | {"$a1", RTYPE_GP | 5}, \ | |
1627 | {"$a2", RTYPE_GP | 6}, \ | |
1628 | {"$a3", RTYPE_GP | 7}, \ | |
1629 | {"$s0", RTYPE_GP | 16}, \ | |
1630 | {"$s1", RTYPE_GP | 17}, \ | |
1631 | {"$s2", RTYPE_GP | 18}, \ | |
1632 | {"$s3", RTYPE_GP | 19}, \ | |
1633 | {"$s4", RTYPE_GP | 20}, \ | |
1634 | {"$s5", RTYPE_GP | 21}, \ | |
1635 | {"$s6", RTYPE_GP | 22}, \ | |
1636 | {"$s7", RTYPE_GP | 23}, \ | |
1637 | {"$t8", RTYPE_GP | 24}, \ | |
1638 | {"$t9", RTYPE_GP | 25}, \ | |
1639 | {"$k0", RTYPE_GP | 26}, \ | |
1640 | {"$kt0", RTYPE_GP | 26}, \ | |
1641 | {"$k1", RTYPE_GP | 27}, \ | |
1642 | {"$kt1", RTYPE_GP | 27}, \ | |
1643 | {"$gp", RTYPE_GP | 28}, \ | |
1644 | {"$sp", RTYPE_GP | 29}, \ | |
1645 | {"$s8", RTYPE_GP | 30}, \ | |
1646 | {"$fp", RTYPE_GP | 30}, \ | |
1647 | {"$ra", RTYPE_GP | 31} | |
1648 | ||
1649 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1650 | {"$pc", RTYPE_PC | 0} | |
1651 | ||
1652 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1653 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1654 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1655 | {"$v2", RTYPE_VEC | 2}, \ | |
1656 | {"$v3", RTYPE_VEC | 3}, \ | |
1657 | {"$v4", RTYPE_VEC | 4}, \ | |
1658 | {"$v5", RTYPE_VEC | 5}, \ | |
1659 | {"$v6", RTYPE_VEC | 6}, \ | |
1660 | {"$v7", RTYPE_VEC | 7}, \ | |
1661 | {"$v8", RTYPE_VEC | 8}, \ | |
1662 | {"$v9", RTYPE_VEC | 9}, \ | |
1663 | {"$v10", RTYPE_VEC | 10}, \ | |
1664 | {"$v11", RTYPE_VEC | 11}, \ | |
1665 | {"$v12", RTYPE_VEC | 12}, \ | |
1666 | {"$v13", RTYPE_VEC | 13}, \ | |
1667 | {"$v14", RTYPE_VEC | 14}, \ | |
1668 | {"$v15", RTYPE_VEC | 15}, \ | |
1669 | {"$v16", RTYPE_VEC | 16}, \ | |
1670 | {"$v17", RTYPE_VEC | 17}, \ | |
1671 | {"$v18", RTYPE_VEC | 18}, \ | |
1672 | {"$v19", RTYPE_VEC | 19}, \ | |
1673 | {"$v20", RTYPE_VEC | 20}, \ | |
1674 | {"$v21", RTYPE_VEC | 21}, \ | |
1675 | {"$v22", RTYPE_VEC | 22}, \ | |
1676 | {"$v23", RTYPE_VEC | 23}, \ | |
1677 | {"$v24", RTYPE_VEC | 24}, \ | |
1678 | {"$v25", RTYPE_VEC | 25}, \ | |
1679 | {"$v26", RTYPE_VEC | 26}, \ | |
1680 | {"$v27", RTYPE_VEC | 27}, \ | |
1681 | {"$v28", RTYPE_VEC | 28}, \ | |
1682 | {"$v29", RTYPE_VEC | 29}, \ | |
1683 | {"$v30", RTYPE_VEC | 30}, \ | |
1684 | {"$v31", RTYPE_VEC | 31} | |
1685 | ||
1686 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1687 | {"$ac0", RTYPE_ACC | 0}, \ | |
1688 | {"$ac1", RTYPE_ACC | 1}, \ | |
1689 | {"$ac2", RTYPE_ACC | 2}, \ | |
1690 | {"$ac3", RTYPE_ACC | 3} | |
1691 | ||
1692 | static const struct regname reg_names[] = { | |
1693 | GENERIC_REGISTER_NUMBERS, | |
1694 | FPU_REGISTER_NAMES, | |
1695 | FPU_CONDITION_CODE_NAMES, | |
1696 | COPROC_CONDITION_CODE_NAMES, | |
1697 | ||
1698 | /* The $txx registers depends on the abi, | |
1699 | these will be added later into the symbol table from | |
1700 | one of the tables below once mips_abi is set after | |
1701 | parsing of arguments from the command line. */ | |
1702 | SYMBOLIC_REGISTER_NAMES, | |
1703 | ||
1704 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1705 | MDMX_VECTOR_REGISTER_NAMES, | |
1706 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1707 | {0, 0} | |
1708 | }; | |
1709 | ||
1710 | static const struct regname reg_names_o32[] = { | |
1711 | O32_SYMBOLIC_REGISTER_NAMES, | |
1712 | {0, 0} | |
1713 | }; | |
1714 | ||
1715 | static const struct regname reg_names_n32n64[] = { | |
1716 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1717 | {0, 0} | |
1718 | }; | |
1719 | ||
1720 | static int | |
1721 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1722 | { | |
1723 | symbolS *symbolP; | |
1724 | char *e; | |
1725 | char save_c; | |
1726 | int reg = -1; | |
1727 | ||
1728 | /* Find end of name. */ | |
1729 | e = *s; | |
1730 | if (is_name_beginner (*e)) | |
1731 | ++e; | |
1732 | while (is_part_of_name (*e)) | |
1733 | ++e; | |
1734 | ||
1735 | /* Terminate name. */ | |
1736 | save_c = *e; | |
1737 | *e = '\0'; | |
1738 | ||
1739 | /* Look for a register symbol. */ | |
1740 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1741 | { | |
1742 | int r = S_GET_VALUE (symbolP); | |
1743 | if (r & types) | |
1744 | reg = r & RNUM_MASK; | |
1745 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1746 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1747 | reg = (r & RNUM_MASK) - 2; | |
1748 | } | |
1749 | /* Else see if this is a register defined in an itbl entry. */ | |
1750 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1751 | { | |
1752 | char *n = *s; | |
1753 | unsigned long r; | |
1754 | ||
1755 | if (*n == '$') | |
1756 | ++n; | |
1757 | if (itbl_get_reg_val (n, &r)) | |
1758 | reg = r & RNUM_MASK; | |
1759 | } | |
1760 | ||
1761 | /* Advance to next token if a register was recognised. */ | |
1762 | if (reg >= 0) | |
1763 | *s = e; | |
1764 | else if (types & RWARN) | |
1765 | as_warn ("Unrecognized register name `%s'", *s); | |
1766 | ||
1767 | *e = save_c; | |
1768 | if (regnop) | |
1769 | *regnop = reg; | |
1770 | return reg >= 0; | |
1771 | } | |
1772 | ||
037b32b9 AN |
1773 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
1774 | architecture. If EXPANSIONP is TRUE then this check is done while | |
1775 | expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
1776 | ||
1777 | static bfd_boolean | |
1778 | is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp) | |
1779 | { | |
1780 | int isa = mips_opts.isa; | |
1781 | int fp_s, fp_d; | |
1782 | ||
1783 | if (mips_opts.ase_mdmx) | |
1784 | isa |= INSN_MDMX; | |
1785 | if (mips_opts.ase_dsp) | |
1786 | isa |= INSN_DSP; | |
1787 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1788 | isa |= INSN_DSP64; | |
1789 | if (mips_opts.ase_dspr2) | |
1790 | isa |= INSN_DSPR2; | |
1791 | if (mips_opts.ase_mt) | |
1792 | isa |= INSN_MT; | |
1793 | if (mips_opts.ase_mips3d) | |
1794 | isa |= INSN_MIPS3D; | |
1795 | if (mips_opts.ase_smartmips) | |
1796 | isa |= INSN_SMARTMIPS; | |
1797 | ||
1798 | /* For user code we don't check for mips_opts.mips16 since we want | |
1799 | to allow jalx if -mips16 was specified on the command line. */ | |
1800 | if (expansionp ? mips_opts.mips16 : file_ase_mips16) | |
1801 | isa |= INSN_MIPS16; | |
1802 | ||
1803 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) | |
1804 | return FALSE; | |
1805 | ||
1806 | /* Check whether the instruction or macro requires single-precision or | |
1807 | double-precision floating-point support. Note that this information is | |
1808 | stored differently in the opcode table for insns and macros. */ | |
1809 | if (mo->pinfo == INSN_MACRO) | |
1810 | { | |
1811 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1812 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1813 | } | |
1814 | else | |
1815 | { | |
1816 | fp_s = mo->pinfo & FP_S; | |
1817 | fp_d = mo->pinfo & FP_D; | |
1818 | } | |
1819 | ||
1820 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1821 | return FALSE; | |
1822 | ||
1823 | if (fp_s && mips_opts.soft_float) | |
1824 | return FALSE; | |
1825 | ||
1826 | return TRUE; | |
1827 | } | |
1828 | ||
1829 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1830 | selected ISA and architecture. */ | |
1831 | ||
1832 | static bfd_boolean | |
1833 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1834 | { | |
1835 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1836 | } | |
1837 | ||
707bfff6 TS |
1838 | /* This function is called once, at assembler startup time. It should set up |
1839 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1840 | |
252b5132 | 1841 | void |
17a2f251 | 1842 | md_begin (void) |
252b5132 | 1843 | { |
3994f87e | 1844 | const char *retval = NULL; |
156c2f8b | 1845 | int i = 0; |
252b5132 | 1846 | int broken = 0; |
1f25f5d3 | 1847 | |
0a44bf69 RS |
1848 | if (mips_pic != NO_PIC) |
1849 | { | |
1850 | if (g_switch_seen && g_switch_value != 0) | |
1851 | as_bad (_("-G may not be used in position-independent code")); | |
1852 | g_switch_value = 0; | |
1853 | } | |
1854 | ||
fef14a42 | 1855 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1856 | as_warn (_("Could not set architecture and machine")); |
1857 | ||
252b5132 RH |
1858 | op_hash = hash_new (); |
1859 | ||
1860 | for (i = 0; i < NUMOPCODES;) | |
1861 | { | |
1862 | const char *name = mips_opcodes[i].name; | |
1863 | ||
17a2f251 | 1864 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1865 | if (retval != NULL) |
1866 | { | |
1867 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1868 | mips_opcodes[i].name, retval); | |
1869 | /* Probably a memory allocation problem? Give up now. */ | |
1870 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1871 | } | |
1872 | do | |
1873 | { | |
1874 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1875 | { | |
1876 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1877 | broken = 1; | |
1e915849 RS |
1878 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1879 | { | |
1880 | create_insn (&nop_insn, mips_opcodes + i); | |
1881 | nop_insn.fixed_p = 1; | |
1882 | } | |
252b5132 RH |
1883 | } |
1884 | ++i; | |
1885 | } | |
1886 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1887 | } | |
1888 | ||
1889 | mips16_op_hash = hash_new (); | |
1890 | ||
1891 | i = 0; | |
1892 | while (i < bfd_mips16_num_opcodes) | |
1893 | { | |
1894 | const char *name = mips16_opcodes[i].name; | |
1895 | ||
17a2f251 | 1896 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1897 | if (retval != NULL) |
1898 | as_fatal (_("internal: can't hash `%s': %s"), | |
1899 | mips16_opcodes[i].name, retval); | |
1900 | do | |
1901 | { | |
1902 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1903 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1904 | != mips16_opcodes[i].match)) | |
1905 | { | |
1906 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1907 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1908 | broken = 1; | |
1909 | } | |
1e915849 RS |
1910 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1911 | { | |
1912 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1913 | mips16_nop_insn.fixed_p = 1; | |
1914 | } | |
252b5132 RH |
1915 | ++i; |
1916 | } | |
1917 | while (i < bfd_mips16_num_opcodes | |
1918 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1919 | } | |
1920 | ||
1921 | if (broken) | |
1922 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1923 | ||
1924 | /* We add all the general register names to the symbol table. This | |
1925 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1926 | for (i = 0; reg_names[i].name; i++) |
1927 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
1928 | reg_names[i].num, // & RNUM_MASK, | |
1929 | &zero_address_frag)); | |
1930 | if (HAVE_NEWABI) | |
1931 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1932 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
1933 | reg_names_n32n64[i].num, // & RNUM_MASK, | |
252b5132 | 1934 | &zero_address_frag)); |
707bfff6 TS |
1935 | else |
1936 | for (i = 0; reg_names_o32[i].name; i++) | |
1937 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
1938 | reg_names_o32[i].num, // & RNUM_MASK, | |
6047c971 | 1939 | &zero_address_frag)); |
6047c971 | 1940 | |
7d10b47d | 1941 | mips_no_prev_insn (); |
252b5132 RH |
1942 | |
1943 | mips_gprmask = 0; | |
1944 | mips_cprmask[0] = 0; | |
1945 | mips_cprmask[1] = 0; | |
1946 | mips_cprmask[2] = 0; | |
1947 | mips_cprmask[3] = 0; | |
1948 | ||
1949 | /* set the default alignment for the text section (2**2) */ | |
1950 | record_alignment (text_section, 2); | |
1951 | ||
4d0d148d | 1952 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 1953 | |
707bfff6 | 1954 | #ifdef OBJ_ELF |
f43abd2b | 1955 | if (IS_ELF) |
252b5132 | 1956 | { |
0a44bf69 RS |
1957 | /* On a native system other than VxWorks, sections must be aligned |
1958 | to 16 byte boundaries. When configured for an embedded ELF | |
1959 | target, we don't bother. */ | |
c41e87e3 CF |
1960 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
1961 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
1962 | { |
1963 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1964 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1965 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1966 | } | |
1967 | ||
1968 | /* Create a .reginfo section for register masks and a .mdebug | |
1969 | section for debugging information. */ | |
1970 | { | |
1971 | segT seg; | |
1972 | subsegT subseg; | |
1973 | flagword flags; | |
1974 | segT sec; | |
1975 | ||
1976 | seg = now_seg; | |
1977 | subseg = now_subseg; | |
1978 | ||
1979 | /* The ABI says this section should be loaded so that the | |
1980 | running program can access it. However, we don't load it | |
1981 | if we are configured for an embedded target */ | |
1982 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 1983 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
1984 | flags |= SEC_ALLOC | SEC_LOAD; |
1985 | ||
316f5878 | 1986 | if (mips_abi != N64_ABI) |
252b5132 RH |
1987 | { |
1988 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1989 | ||
195325d2 TS |
1990 | bfd_set_section_flags (stdoutput, sec, flags); |
1991 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1992 | |
252b5132 | 1993 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
1994 | } |
1995 | else | |
1996 | { | |
1997 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1998 | .reginfo section. */ | |
1999 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2000 | bfd_set_section_flags (stdoutput, sec, flags); |
2001 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2002 | |
252b5132 RH |
2003 | /* Set up the option header. */ |
2004 | { | |
2005 | Elf_Internal_Options opthdr; | |
2006 | char *f; | |
2007 | ||
2008 | opthdr.kind = ODK_REGINFO; | |
2009 | opthdr.size = (sizeof (Elf_External_Options) | |
2010 | + sizeof (Elf64_External_RegInfo)); | |
2011 | opthdr.section = 0; | |
2012 | opthdr.info = 0; | |
2013 | f = frag_more (sizeof (Elf_External_Options)); | |
2014 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2015 | (Elf_External_Options *) f); | |
2016 | ||
2017 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2018 | } | |
252b5132 RH |
2019 | } |
2020 | ||
2021 | if (ECOFF_DEBUGGING) | |
2022 | { | |
2023 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2024 | (void) bfd_set_section_flags (stdoutput, sec, | |
2025 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2026 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2027 | } | |
f43abd2b | 2028 | else if (mips_flag_pdr) |
ecb4347a DJ |
2029 | { |
2030 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2031 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2032 | SEC_READONLY | SEC_RELOC | |
2033 | | SEC_DEBUGGING); | |
2034 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2035 | } | |
252b5132 RH |
2036 | |
2037 | subseg_set (seg, subseg); | |
2038 | } | |
2039 | } | |
707bfff6 | 2040 | #endif /* OBJ_ELF */ |
252b5132 RH |
2041 | |
2042 | if (! ECOFF_DEBUGGING) | |
2043 | md_obj_begin (); | |
71400594 RS |
2044 | |
2045 | if (mips_fix_vr4120) | |
2046 | init_vr4120_conflicts (); | |
252b5132 RH |
2047 | } |
2048 | ||
2049 | void | |
17a2f251 | 2050 | md_mips_end (void) |
252b5132 RH |
2051 | { |
2052 | if (! ECOFF_DEBUGGING) | |
2053 | md_obj_end (); | |
2054 | } | |
2055 | ||
2056 | void | |
17a2f251 | 2057 | md_assemble (char *str) |
252b5132 RH |
2058 | { |
2059 | struct mips_cl_insn insn; | |
f6688943 TS |
2060 | bfd_reloc_code_real_type unused_reloc[3] |
2061 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2062 | |
2063 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2064 | imm2_expr.X_op = O_absent; |
252b5132 | 2065 | offset_expr.X_op = O_absent; |
f6688943 TS |
2066 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2067 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2068 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2069 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2070 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2071 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2072 | |
2073 | if (mips_opts.mips16) | |
2074 | mips16_ip (str, &insn); | |
2075 | else | |
2076 | { | |
2077 | mips_ip (str, &insn); | |
beae10d5 KH |
2078 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2079 | str, insn.insn_opcode)); | |
252b5132 RH |
2080 | } |
2081 | ||
2082 | if (insn_error) | |
2083 | { | |
2084 | as_bad ("%s `%s'", insn_error, str); | |
2085 | return; | |
2086 | } | |
2087 | ||
2088 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2089 | { | |
584892a6 | 2090 | macro_start (); |
252b5132 RH |
2091 | if (mips_opts.mips16) |
2092 | mips16_macro (&insn); | |
2093 | else | |
2094 | macro (&insn); | |
584892a6 | 2095 | macro_end (); |
252b5132 RH |
2096 | } |
2097 | else | |
2098 | { | |
2099 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2100 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2101 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2102 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2103 | else |
4d7206a2 | 2104 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2105 | } |
2106 | } | |
2107 | ||
5919d012 | 2108 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2109 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2110 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2111 | |
2112 | static inline bfd_boolean | |
17a2f251 | 2113 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2114 | { |
3b91255e RS |
2115 | return (HAVE_IN_PLACE_ADDENDS |
2116 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
2117 | || reloc == BFD_RELOC_MIPS16_HI16_S |
2118 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
2119 | all GOT16 relocations evaluate to "G". */ | |
2120 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
2121 | } |
2122 | ||
2123 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2124 | relocation. */ | |
2125 | ||
2126 | static inline bfd_boolean | |
17a2f251 | 2127 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2128 | { |
2129 | return (fixp->fx_next != NULL | |
d6f16593 MR |
2130 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
2131 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
2132 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2133 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2134 | } | |
2135 | ||
252b5132 RH |
2136 | /* See whether instruction IP reads register REG. CLASS is the type |
2137 | of register. */ | |
2138 | ||
2139 | static int | |
71400594 | 2140 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 2141 | enum mips_regclass class) |
252b5132 RH |
2142 | { |
2143 | if (class == MIPS16_REG) | |
2144 | { | |
2145 | assert (mips_opts.mips16); | |
2146 | reg = mips16_to_32_reg_map[reg]; | |
2147 | class = MIPS_GR_REG; | |
2148 | } | |
2149 | ||
85b51719 TS |
2150 | /* Don't report on general register ZERO, since it never changes. */ |
2151 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
2152 | return 0; |
2153 | ||
2154 | if (class == MIPS_FP_REG) | |
2155 | { | |
2156 | assert (! mips_opts.mips16); | |
2157 | /* If we are called with either $f0 or $f1, we must check $f0. | |
2158 | This is not optimal, because it will introduce an unnecessary | |
2159 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2160 | need to distinguish reading both $f0 and $f1 or just one of | |
2161 | them. Note that we don't have to check the other way, | |
2162 | because there is no instruction that sets both $f0 and $f1 | |
2163 | and requires a delay. */ | |
2164 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2165 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2166 | == (reg &~ (unsigned) 1))) |
2167 | return 1; | |
2168 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2169 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2170 | == (reg &~ (unsigned) 1))) |
2171 | return 1; | |
2172 | } | |
2173 | else if (! mips_opts.mips16) | |
2174 | { | |
2175 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2176 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2177 | return 1; |
2178 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2179 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2180 | return 1; |
2181 | } | |
2182 | else | |
2183 | { | |
2184 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2185 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2186 | return 1; |
2187 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2188 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2189 | return 1; |
2190 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2191 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2192 | == reg)) |
2193 | return 1; | |
2194 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2195 | return 1; | |
2196 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2197 | return 1; | |
2198 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2199 | return 1; | |
2200 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2201 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2202 | return 1; |
2203 | } | |
2204 | ||
2205 | return 0; | |
2206 | } | |
2207 | ||
2208 | /* This function returns true if modifying a register requires a | |
2209 | delay. */ | |
2210 | ||
2211 | static int | |
17a2f251 | 2212 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2213 | { |
2214 | unsigned long prev_pinfo; | |
2215 | ||
47e39b9d | 2216 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2217 | if (! mips_opts.noreorder |
81912461 ILT |
2218 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2219 | && ! gpr_interlocks) | |
2220 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2221 | && ! cop_interlocks))) | |
252b5132 | 2222 | { |
81912461 ILT |
2223 | /* A load from a coprocessor or from memory. All load delays |
2224 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2225 | /* Itbl support may require additional care here. */ |
252b5132 | 2226 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2227 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2228 | return 1; |
2229 | } | |
2230 | ||
2231 | return 0; | |
2232 | } | |
2233 | ||
404a8071 RS |
2234 | /* Move all labels in insn_labels to the current insertion point. */ |
2235 | ||
2236 | static void | |
2237 | mips_move_labels (void) | |
2238 | { | |
a8dbcb85 | 2239 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2240 | struct insn_label_list *l; |
2241 | valueT val; | |
2242 | ||
a8dbcb85 | 2243 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 RS |
2244 | { |
2245 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
2246 | symbol_set_frag (l->label, frag_now); | |
2247 | val = (valueT) frag_now_fix (); | |
2248 | /* mips16 text labels are stored as odd. */ | |
2249 | if (mips_opts.mips16) | |
2250 | ++val; | |
2251 | S_SET_VALUE (l->label, val); | |
2252 | } | |
2253 | } | |
2254 | ||
5f0fe04b TS |
2255 | static bfd_boolean |
2256 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2257 | { | |
2258 | bfd_boolean linkonce = FALSE; | |
2259 | segT symseg = S_GET_SEGMENT (sym); | |
2260 | ||
2261 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2262 | { | |
2263 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2264 | linkonce = TRUE; | |
2265 | #ifdef OBJ_ELF | |
2266 | /* The GNU toolchain uses an extension for ELF: a section | |
2267 | beginning with the magic string .gnu.linkonce is a | |
2268 | linkonce section. */ | |
2269 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2270 | sizeof ".gnu.linkonce" - 1) == 0) | |
2271 | linkonce = TRUE; | |
2272 | #endif | |
2273 | } | |
2274 | return linkonce; | |
2275 | } | |
2276 | ||
252b5132 RH |
2277 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2278 | handle them specially, such as generating jalx instructions when | |
2279 | needed. We also make them odd for the duration of the assembly, in | |
2280 | order to generate the right sort of code. We will make them even | |
2281 | in the adjust_symtab routine, while leaving them marked. This is | |
2282 | convenient for the debugger and the disassembler. The linker knows | |
2283 | to make them odd again. */ | |
2284 | ||
2285 | static void | |
17a2f251 | 2286 | mips16_mark_labels (void) |
252b5132 | 2287 | { |
a8dbcb85 TS |
2288 | segment_info_type *si = seg_info (now_seg); |
2289 | struct insn_label_list *l; | |
252b5132 | 2290 | |
a8dbcb85 TS |
2291 | if (!mips_opts.mips16) |
2292 | return; | |
2293 | ||
2294 | for (l = si->label_list; l != NULL; l = l->next) | |
2295 | { | |
2296 | symbolS *label = l->label; | |
2297 | ||
2298 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2299 | if (IS_ELF) |
a8dbcb85 | 2300 | S_SET_OTHER (label, STO_MIPS16); |
252b5132 | 2301 | #endif |
5f0fe04b TS |
2302 | if ((S_GET_VALUE (label) & 1) == 0 |
2303 | /* Don't adjust the address if the label is global or weak, or | |
2304 | in a link-once section, since we'll be emitting symbol reloc | |
2305 | references to it which will be patched up by the linker, and | |
2306 | the final value of the symbol may or may not be MIPS16. */ | |
2307 | && ! S_IS_WEAK (label) | |
2308 | && ! S_IS_EXTERNAL (label) | |
2309 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2310 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2311 | } |
2312 | } | |
2313 | ||
4d7206a2 RS |
2314 | /* End the current frag. Make it a variant frag and record the |
2315 | relaxation info. */ | |
2316 | ||
2317 | static void | |
2318 | relax_close_frag (void) | |
2319 | { | |
584892a6 | 2320 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2321 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2322 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2323 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2324 | ||
2325 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2326 | mips_relax.first_fixup = 0; | |
2327 | } | |
2328 | ||
2329 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2330 | See the comment above RELAX_ENCODE for more details. */ | |
2331 | ||
2332 | static void | |
2333 | relax_start (symbolS *symbol) | |
2334 | { | |
2335 | assert (mips_relax.sequence == 0); | |
2336 | mips_relax.sequence = 1; | |
2337 | mips_relax.symbol = symbol; | |
2338 | } | |
2339 | ||
2340 | /* Start generating the second version of a relaxable sequence. | |
2341 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2342 | |
2343 | static void | |
4d7206a2 RS |
2344 | relax_switch (void) |
2345 | { | |
2346 | assert (mips_relax.sequence == 1); | |
2347 | mips_relax.sequence = 2; | |
2348 | } | |
2349 | ||
2350 | /* End the current relaxable sequence. */ | |
2351 | ||
2352 | static void | |
2353 | relax_end (void) | |
2354 | { | |
2355 | assert (mips_relax.sequence == 2); | |
2356 | relax_close_frag (); | |
2357 | mips_relax.sequence = 0; | |
2358 | } | |
2359 | ||
71400594 RS |
2360 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2361 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2362 | by VR4120 errata. */ | |
4d7206a2 | 2363 | |
71400594 RS |
2364 | static unsigned int |
2365 | classify_vr4120_insn (const char *name) | |
252b5132 | 2366 | { |
71400594 RS |
2367 | if (strncmp (name, "macc", 4) == 0) |
2368 | return FIX_VR4120_MACC; | |
2369 | if (strncmp (name, "dmacc", 5) == 0) | |
2370 | return FIX_VR4120_DMACC; | |
2371 | if (strncmp (name, "mult", 4) == 0) | |
2372 | return FIX_VR4120_MULT; | |
2373 | if (strncmp (name, "dmult", 5) == 0) | |
2374 | return FIX_VR4120_DMULT; | |
2375 | if (strstr (name, "div")) | |
2376 | return FIX_VR4120_DIV; | |
2377 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2378 | return FIX_VR4120_MTHILO; | |
2379 | return NUM_FIX_VR4120_CLASSES; | |
2380 | } | |
252b5132 | 2381 | |
71400594 RS |
2382 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2383 | where INSN1 is the earlier instruction. Return the worst-case value | |
2384 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2385 | |
71400594 RS |
2386 | static unsigned int |
2387 | insns_between (const struct mips_cl_insn *insn1, | |
2388 | const struct mips_cl_insn *insn2) | |
2389 | { | |
2390 | unsigned long pinfo1, pinfo2; | |
2391 | ||
2392 | /* This function needs to know which pinfo flags are set for INSN2 | |
2393 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2394 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2395 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2396 | pinfo1 = insn1->insn_mo->pinfo; | |
2397 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2398 | |
71400594 RS |
2399 | #define INSN2_USES_REG(REG, CLASS) \ |
2400 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2401 | ||
2402 | /* For most targets, write-after-read dependencies on the HI and LO | |
2403 | registers must be separated by at least two instructions. */ | |
2404 | if (!hilo_interlocks) | |
252b5132 | 2405 | { |
71400594 RS |
2406 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2407 | return 2; | |
2408 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2409 | return 2; | |
2410 | } | |
2411 | ||
2412 | /* If we're working around r7000 errata, there must be two instructions | |
2413 | between an mfhi or mflo and any instruction that uses the result. */ | |
2414 | if (mips_7000_hilo_fix | |
2415 | && MF_HILO_INSN (pinfo1) | |
2416 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2417 | return 2; | |
2418 | ||
2419 | /* If working around VR4120 errata, check for combinations that need | |
2420 | a single intervening instruction. */ | |
2421 | if (mips_fix_vr4120) | |
2422 | { | |
2423 | unsigned int class1, class2; | |
252b5132 | 2424 | |
71400594 RS |
2425 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2426 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2427 | { |
71400594 RS |
2428 | if (insn2 == NULL) |
2429 | return 1; | |
2430 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2431 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2432 | return 1; | |
252b5132 | 2433 | } |
71400594 RS |
2434 | } |
2435 | ||
2436 | if (!mips_opts.mips16) | |
2437 | { | |
2438 | /* Check for GPR or coprocessor load delays. All such delays | |
2439 | are on the RT register. */ | |
2440 | /* Itbl support may require additional care here. */ | |
2441 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2442 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2443 | { |
71400594 RS |
2444 | know (pinfo1 & INSN_WRITE_GPR_T); |
2445 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2446 | return 1; | |
2447 | } | |
2448 | ||
2449 | /* Check for generic coprocessor hazards. | |
2450 | ||
2451 | This case is not handled very well. There is no special | |
2452 | knowledge of CP0 handling, and the coprocessors other than | |
2453 | the floating point unit are not distinguished at all. */ | |
2454 | /* Itbl support may require additional care here. FIXME! | |
2455 | Need to modify this to include knowledge about | |
2456 | user specified delays! */ | |
2457 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2458 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2459 | { | |
2460 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2461 | register. There must be a one instruction delay before INSN2 | |
2462 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2463 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2464 | { |
71400594 RS |
2465 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2466 | return 1; | |
252b5132 | 2467 | } |
71400594 | 2468 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2469 | { |
71400594 RS |
2470 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2471 | return 1; | |
252b5132 RH |
2472 | } |
2473 | else | |
2474 | { | |
71400594 RS |
2475 | /* Read-after-write dependencies on the control registers |
2476 | require a two-instruction gap. */ | |
2477 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2478 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2479 | return 2; | |
2480 | ||
2481 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2482 | also a coprocessor instruction, assume there must be | |
2483 | a one instruction gap. */ | |
2484 | if (pinfo2 & INSN_COP) | |
2485 | return 1; | |
252b5132 RH |
2486 | } |
2487 | } | |
6b76fefe | 2488 | |
71400594 RS |
2489 | /* Check for read-after-write dependencies on the coprocessor |
2490 | control registers in cases where INSN1 does not need a general | |
2491 | coprocessor delay. This means that INSN1 is a floating point | |
2492 | comparison instruction. */ | |
2493 | /* Itbl support may require additional care here. */ | |
2494 | else if (!cop_interlocks | |
2495 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2496 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2497 | return 1; | |
2498 | } | |
6b76fefe | 2499 | |
71400594 | 2500 | #undef INSN2_USES_REG |
6b76fefe | 2501 | |
71400594 RS |
2502 | return 0; |
2503 | } | |
6b76fefe | 2504 | |
7d8e00cf RS |
2505 | /* Return the number of nops that would be needed to work around the |
2506 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2507 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2508 | ||
2509 | static int | |
2510 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2511 | const struct mips_cl_insn *insn) | |
2512 | { | |
2513 | int i, j, reg; | |
2514 | ||
2515 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2516 | are not affected by the errata. */ | |
2517 | if (insn != 0 | |
2518 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2519 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2520 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2521 | return 0; | |
2522 | ||
2523 | /* Search for the first MFLO or MFHI. */ | |
2524 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2525 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2526 | { | |
2527 | /* Extract the destination register. */ | |
2528 | if (mips_opts.mips16) | |
2529 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2530 | else | |
2531 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2532 | ||
2533 | /* No nops are needed if INSN reads that register. */ | |
2534 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2535 | return 0; | |
2536 | ||
2537 | /* ...or if any of the intervening instructions do. */ | |
2538 | for (j = 0; j < i; j++) | |
2539 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2540 | return 0; | |
2541 | ||
2542 | return MAX_VR4130_NOPS - i; | |
2543 | } | |
2544 | return 0; | |
2545 | } | |
2546 | ||
71400594 RS |
2547 | /* Return the number of nops that would be needed if instruction INSN |
2548 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2549 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2550 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2551 | |
71400594 RS |
2552 | static int |
2553 | nops_for_insn (const struct mips_cl_insn *history, | |
2554 | const struct mips_cl_insn *insn) | |
2555 | { | |
2556 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2557 | |
71400594 | 2558 | nops = 0; |
7d8e00cf | 2559 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2560 | if (!history[i].noreorder_p) |
2561 | { | |
2562 | tmp_nops = insns_between (history + i, insn) - i; | |
2563 | if (tmp_nops > nops) | |
2564 | nops = tmp_nops; | |
2565 | } | |
7d8e00cf RS |
2566 | |
2567 | if (mips_fix_vr4130) | |
2568 | { | |
2569 | tmp_nops = nops_for_vr4130 (history, insn); | |
2570 | if (tmp_nops > nops) | |
2571 | nops = tmp_nops; | |
2572 | } | |
2573 | ||
71400594 RS |
2574 | return nops; |
2575 | } | |
252b5132 | 2576 | |
71400594 RS |
2577 | /* The variable arguments provide NUM_INSNS extra instructions that |
2578 | might be added to HISTORY. Return the largest number of nops that | |
2579 | would be needed after the extended sequence. */ | |
252b5132 | 2580 | |
71400594 RS |
2581 | static int |
2582 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2583 | { | |
2584 | va_list args; | |
2585 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2586 | struct mips_cl_insn *cursor; | |
2587 | int nops; | |
2588 | ||
2589 | va_start (args, history); | |
2590 | cursor = buffer + num_insns; | |
2591 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2592 | while (cursor > buffer) | |
2593 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2594 | ||
2595 | nops = nops_for_insn (buffer, NULL); | |
2596 | va_end (args); | |
2597 | return nops; | |
2598 | } | |
252b5132 | 2599 | |
71400594 RS |
2600 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2601 | worst-case delay for the branch target. */ | |
252b5132 | 2602 | |
71400594 RS |
2603 | static int |
2604 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2605 | const struct mips_cl_insn *insn) | |
2606 | { | |
2607 | int nops, tmp_nops; | |
60b63b72 | 2608 | |
71400594 RS |
2609 | nops = nops_for_insn (history, insn); |
2610 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2611 | | INSN_COND_BRANCH_DELAY | |
2612 | | INSN_COND_BRANCH_LIKELY)) | |
2613 | { | |
2614 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2615 | if (tmp_nops > nops) | |
2616 | nops = tmp_nops; | |
2617 | } | |
2618 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2619 | { | |
2620 | tmp_nops = nops_for_sequence (1, history, insn); | |
2621 | if (tmp_nops > nops) | |
2622 | nops = tmp_nops; | |
2623 | } | |
2624 | return nops; | |
2625 | } | |
2626 | ||
2627 | /* Output an instruction. IP is the instruction information. | |
2628 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2629 | RELOC_TYPE. */ | |
2630 | ||
2631 | static void | |
2632 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2633 | bfd_reloc_code_real_type *reloc_type) | |
2634 | { | |
3994f87e | 2635 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2636 | relax_stateT prev_insn_frag_type = 0; |
2637 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2638 | segment_info_type *si = seg_info (now_seg); |
71400594 RS |
2639 | |
2640 | /* Mark instruction labels in mips16 mode. */ | |
2641 | mips16_mark_labels (); | |
2642 | ||
2643 | prev_pinfo = history[0].insn_mo->pinfo; | |
2644 | pinfo = ip->insn_mo->pinfo; | |
2645 | ||
2646 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2647 | { | |
2648 | /* There are a lot of optimizations we could do that we don't. | |
2649 | In particular, we do not, in general, reorder instructions. | |
2650 | If you use gcc with optimization, it will reorder | |
2651 | instructions and generally do much more optimization then we | |
2652 | do here; repeating all that work in the assembler would only | |
2653 | benefit hand written assembly code, and does not seem worth | |
2654 | it. */ | |
2655 | int nops = (mips_optimize == 0 | |
2656 | ? nops_for_insn (history, NULL) | |
2657 | : nops_for_insn_or_target (history, ip)); | |
2658 | if (nops > 0) | |
252b5132 RH |
2659 | { |
2660 | fragS *old_frag; | |
2661 | unsigned long old_frag_offset; | |
2662 | int i; | |
252b5132 RH |
2663 | |
2664 | old_frag = frag_now; | |
2665 | old_frag_offset = frag_now_fix (); | |
2666 | ||
2667 | for (i = 0; i < nops; i++) | |
2668 | emit_nop (); | |
2669 | ||
2670 | if (listing) | |
2671 | { | |
2672 | listing_prev_line (); | |
2673 | /* We may be at the start of a variant frag. In case we | |
2674 | are, make sure there is enough space for the frag | |
2675 | after the frags created by listing_prev_line. The | |
2676 | argument to frag_grow here must be at least as large | |
2677 | as the argument to all other calls to frag_grow in | |
2678 | this file. We don't have to worry about being in the | |
2679 | middle of a variant frag, because the variants insert | |
2680 | all needed nop instructions themselves. */ | |
2681 | frag_grow (40); | |
2682 | } | |
2683 | ||
404a8071 | 2684 | mips_move_labels (); |
252b5132 RH |
2685 | |
2686 | #ifndef NO_ECOFF_DEBUGGING | |
2687 | if (ECOFF_DEBUGGING) | |
2688 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2689 | #endif | |
2690 | } | |
71400594 RS |
2691 | } |
2692 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2693 | { | |
2694 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2695 | int nops = nops_for_insn_or_target (history, ip); | |
2696 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2697 | |
71400594 RS |
2698 | /* Enforce NOPS as a minimum. */ |
2699 | if (nops > prev_nop_frag_required) | |
2700 | prev_nop_frag_required = nops; | |
252b5132 | 2701 | |
71400594 RS |
2702 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2703 | { | |
2704 | /* Settle for the current number of nops. Update the history | |
2705 | accordingly (for the benefit of any future .set reorder code). */ | |
2706 | prev_nop_frag = NULL; | |
2707 | insert_into_history (prev_nop_frag_since, | |
2708 | prev_nop_frag_holds, NOP_INSN); | |
2709 | } | |
2710 | else | |
2711 | { | |
2712 | /* Allow this instruction to replace one of the nops that was | |
2713 | tentatively added to prev_nop_frag. */ | |
2714 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2715 | prev_nop_frag_holds--; | |
2716 | prev_nop_frag_since++; | |
252b5132 RH |
2717 | } |
2718 | } | |
2719 | ||
58e2ea4d MR |
2720 | #ifdef OBJ_ELF |
2721 | /* The value passed to dwarf2_emit_insn is the distance between | |
2722 | the beginning of the current instruction and the address that | |
2723 | should be recorded in the debug tables. For MIPS16 debug info | |
2724 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2725 | address higher by one than the current. */ | |
2726 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2727 | #endif | |
2728 | ||
895921c9 | 2729 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2730 | if (history[0].frag) |
2731 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2732 | |
4d7206a2 | 2733 | if (address_expr |
0b25d3e6 | 2734 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2735 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2736 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2737 | && mips_relax_branch | |
2738 | /* Don't try branch relaxation within .set nomacro, or within | |
2739 | .set noat if we use $at for PIC computations. If it turns | |
2740 | out that the branch was out-of-range, we'll get an error. */ | |
2741 | && !mips_opts.warn_about_macros | |
741fe287 | 2742 | && (mips_opts.at || mips_pic == NO_PIC) |
4a6a3df4 AO |
2743 | && !mips_opts.mips16) |
2744 | { | |
895921c9 | 2745 | relaxed_branch = TRUE; |
1e915849 RS |
2746 | add_relaxed_insn (ip, (relaxed_branch_length |
2747 | (NULL, NULL, | |
2748 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2749 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2750 | : 0)), 4, | |
2751 | RELAX_BRANCH_ENCODE | |
2752 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2753 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2754 | pinfo & INSN_WRITE_GPR_31, | |
2755 | 0), | |
2756 | address_expr->X_add_symbol, | |
2757 | address_expr->X_add_number); | |
4a6a3df4 AO |
2758 | *reloc_type = BFD_RELOC_UNUSED; |
2759 | } | |
2760 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2761 | { |
2762 | /* We need to set up a variant frag. */ | |
2763 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2764 | add_relaxed_insn (ip, 4, 0, |
2765 | RELAX_MIPS16_ENCODE | |
2766 | (*reloc_type - BFD_RELOC_UNUSED, | |
2767 | mips16_small, mips16_ext, | |
2768 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2769 | history[0].mips16_absolute_jump_p), | |
2770 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2771 | } |
252b5132 RH |
2772 | else if (mips_opts.mips16 |
2773 | && ! ip->use_extend | |
f6688943 | 2774 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2775 | { |
b8ee1a6e DU |
2776 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2777 | /* Make sure there is enough room to swap this instruction with | |
2778 | a following jump instruction. */ | |
2779 | frag_grow (6); | |
1e915849 | 2780 | add_fixed_insn (ip); |
252b5132 RH |
2781 | } |
2782 | else | |
2783 | { | |
2784 | if (mips_opts.mips16 | |
2785 | && mips_opts.noreorder | |
2786 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2787 | as_warn (_("extended instruction in delay slot")); | |
2788 | ||
4d7206a2 RS |
2789 | if (mips_relax.sequence) |
2790 | { | |
2791 | /* If we've reached the end of this frag, turn it into a variant | |
2792 | frag and record the information for the instructions we've | |
2793 | written so far. */ | |
2794 | if (frag_room () < 4) | |
2795 | relax_close_frag (); | |
2796 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2797 | } | |
2798 | ||
584892a6 RS |
2799 | if (mips_relax.sequence != 2) |
2800 | mips_macro_warning.sizes[0] += 4; | |
2801 | if (mips_relax.sequence != 1) | |
2802 | mips_macro_warning.sizes[1] += 4; | |
2803 | ||
1e915849 RS |
2804 | if (mips_opts.mips16) |
2805 | { | |
2806 | ip->fixed_p = 1; | |
2807 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2808 | } | |
2809 | add_fixed_insn (ip); | |
252b5132 RH |
2810 | } |
2811 | ||
01a3f561 | 2812 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2813 | { |
2814 | if (address_expr->X_op == O_constant) | |
2815 | { | |
f17c130b | 2816 | unsigned int tmp; |
f6688943 TS |
2817 | |
2818 | switch (*reloc_type) | |
252b5132 RH |
2819 | { |
2820 | case BFD_RELOC_32: | |
2821 | ip->insn_opcode |= address_expr->X_add_number; | |
2822 | break; | |
2823 | ||
f6688943 | 2824 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2825 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2826 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2827 | break; |
2828 | ||
2829 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2830 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2831 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2832 | break; |
2833 | ||
2834 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2835 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2836 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2837 | break; |
2838 | ||
2839 | case BFD_RELOC_HI16: | |
2840 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2841 | break; | |
2842 | ||
01a3f561 | 2843 | case BFD_RELOC_UNUSED: |
252b5132 | 2844 | case BFD_RELOC_LO16: |
ed6fb7bd | 2845 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2846 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2847 | break; | |
2848 | ||
2849 | case BFD_RELOC_MIPS_JMP: | |
2850 | if ((address_expr->X_add_number & 3) != 0) | |
2851 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2852 | (unsigned long) address_expr->X_add_number); | |
2853 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2854 | break; | |
2855 | ||
2856 | case BFD_RELOC_MIPS16_JMP: | |
2857 | if ((address_expr->X_add_number & 3) != 0) | |
2858 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2859 | (unsigned long) address_expr->X_add_number); | |
2860 | ip->insn_opcode |= | |
2861 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2862 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2863 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2864 | break; | |
2865 | ||
252b5132 | 2866 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2867 | if ((address_expr->X_add_number & 3) != 0) |
2868 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2869 | (unsigned long) address_expr->X_add_number); | |
2870 | if (mips_relax_branch) | |
2871 | goto need_reloc; | |
2872 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2873 | as_bad (_("branch address range overflow (0x%lx)"), | |
2874 | (unsigned long) address_expr->X_add_number); | |
2875 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2876 | break; | |
252b5132 RH |
2877 | |
2878 | default: | |
2879 | internalError (); | |
2880 | } | |
2881 | } | |
01a3f561 | 2882 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2883 | need_reloc: |
4d7206a2 RS |
2884 | { |
2885 | reloc_howto_type *howto; | |
2886 | int i; | |
34ce925e | 2887 | |
4d7206a2 RS |
2888 | /* In a compound relocation, it is the final (outermost) |
2889 | operator that determines the relocated field. */ | |
2890 | for (i = 1; i < 3; i++) | |
2891 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2892 | break; | |
34ce925e | 2893 | |
4d7206a2 | 2894 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2895 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2896 | bfd_get_reloc_size (howto), | |
2897 | address_expr, | |
2898 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2899 | reloc_type[0]); | |
4d7206a2 | 2900 | |
b314ec0e RS |
2901 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
2902 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
2903 | && ip->fixp[0]->fx_addsy) | |
2904 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
2905 | ||
4d7206a2 RS |
2906 | /* These relocations can have an addend that won't fit in |
2907 | 4 octets for 64bit assembly. */ | |
2908 | if (HAVE_64BIT_GPRS | |
2909 | && ! howto->partial_inplace | |
2910 | && (reloc_type[0] == BFD_RELOC_16 | |
2911 | || reloc_type[0] == BFD_RELOC_32 | |
2912 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2913 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2914 | || reloc_type[0] == BFD_RELOC_LO16 | |
2915 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2916 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2917 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2918 | || reloc_type[0] == BFD_RELOC_64 | |
2919 | || reloc_type[0] == BFD_RELOC_CTOR | |
2920 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2921 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2922 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2923 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2924 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2925 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2926 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2927 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2928 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2929 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2930 | |
2931 | if (mips_relax.sequence) | |
2932 | { | |
2933 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2934 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2935 | } |
2936 | else if (reloc_needs_lo_p (*reloc_type)) | |
2937 | { | |
2938 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2939 | |
4d7206a2 RS |
2940 | /* Reuse the last entry if it already has a matching %lo. */ |
2941 | hi_fixup = mips_hi_fixup_list; | |
2942 | if (hi_fixup == 0 | |
2943 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2944 | { | |
2945 | hi_fixup = ((struct mips_hi_fixup *) | |
2946 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2947 | hi_fixup->next = mips_hi_fixup_list; | |
2948 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2949 | } |
1e915849 | 2950 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2951 | hi_fixup->seg = now_seg; |
2952 | } | |
f6688943 | 2953 | |
4d7206a2 RS |
2954 | /* Add fixups for the second and third relocations, if given. |
2955 | Note that the ABI allows the second relocation to be | |
2956 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2957 | moment we only use RSS_UNDEF, but we could add support | |
2958 | for the others if it ever becomes necessary. */ | |
2959 | for (i = 1; i < 3; i++) | |
2960 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2961 | { | |
1e915849 RS |
2962 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2963 | ip->fixp[0]->fx_size, NULL, 0, | |
2964 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2965 | |
2966 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2967 | ip->fixp[0]->fx_tcbit = 1; |
2968 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2969 | } |
252b5132 RH |
2970 | } |
2971 | } | |
1e915849 | 2972 | install_insn (ip); |
252b5132 RH |
2973 | |
2974 | /* Update the register mask information. */ | |
2975 | if (! mips_opts.mips16) | |
2976 | { | |
2977 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2978 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2979 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2980 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2981 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2982 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2983 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2984 | mips_gprmask |= 1 << RA; |
252b5132 | 2985 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2986 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2987 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2988 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2989 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2990 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2991 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2992 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2993 | if (pinfo & INSN_COP) |
2994 | { | |
bdaaa2e1 KH |
2995 | /* We don't keep enough information to sort these cases out. |
2996 | The itbl support does keep this information however, although | |
2997 | we currently don't support itbl fprmats as part of the cop | |
2998 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2999 | } |
3000 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 3001 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
3002 | } |
3003 | else | |
3004 | { | |
3005 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 3006 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 3007 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 3008 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 3009 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 3010 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
3011 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
3012 | mips_gprmask |= 1 << TREG; | |
3013 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
3014 | mips_gprmask |= 1 << SP; | |
3015 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
3016 | mips_gprmask |= 1 << RA; | |
3017 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3018 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3019 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 3020 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 3021 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 3022 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
3023 | } |
3024 | ||
4d7206a2 | 3025 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3026 | { |
3027 | /* Filling the branch delay slot is more complex. We try to | |
3028 | switch the branch with the previous instruction, which we can | |
3029 | do if the previous instruction does not set up a condition | |
3030 | that the branch tests and if the branch is not itself the | |
3031 | target of any branch. */ | |
3032 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3033 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3034 | { | |
3035 | if (mips_optimize < 2 | |
3036 | /* If we have seen .set volatile or .set nomove, don't | |
3037 | optimize. */ | |
3038 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3039 | /* We can't swap if the previous instruction's position |
3040 | is fixed. */ | |
3041 | || history[0].fixed_p | |
252b5132 RH |
3042 | /* If the previous previous insn was in a .set |
3043 | noreorder, we can't swap. Actually, the MIPS | |
3044 | assembler will swap in this situation. However, gcc | |
3045 | configured -with-gnu-as will generate code like | |
3046 | .set noreorder | |
3047 | lw $4,XXX | |
3048 | .set reorder | |
3049 | INSN | |
3050 | bne $4,$0,foo | |
3051 | in which we can not swap the bne and INSN. If gcc is | |
3052 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3053 | .set pseudo-ops. */ |
47e39b9d | 3054 | || history[1].noreorder_p |
252b5132 RH |
3055 | /* If the branch is itself the target of a branch, we |
3056 | can not swap. We cheat on this; all we check for is | |
3057 | whether there is a label on this instruction. If | |
3058 | there are any branches to anything other than a | |
3059 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3060 | || si->label_list != NULL |
895921c9 MR |
3061 | /* If the previous instruction is in a variant frag |
3062 | other than this branch's one, we cannot do the swap. | |
3063 | This does not apply to the mips16, which uses variant | |
3064 | frags for different purposes. */ | |
252b5132 | 3065 | || (! mips_opts.mips16 |
895921c9 | 3066 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3067 | /* Check for conflicts between the branch and the instructions |
3068 | before the candidate delay slot. */ | |
3069 | || nops_for_insn (history + 1, ip) > 0 | |
3070 | /* Check for conflicts between the swapped sequence and the | |
3071 | target of the branch. */ | |
3072 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
3073 | /* We do not swap with a trap instruction, since it |
3074 | complicates trap handlers to have the trap | |
3075 | instruction be in a delay slot. */ | |
3076 | || (prev_pinfo & INSN_TRAP) | |
3077 | /* If the branch reads a register that the previous | |
3078 | instruction sets, we can not swap. */ | |
3079 | || (! mips_opts.mips16 | |
3080 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 3081 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
3082 | MIPS_GR_REG)) |
3083 | || (! mips_opts.mips16 | |
3084 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3085 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
3086 | MIPS_GR_REG)) |
3087 | || (mips_opts.mips16 | |
3088 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
3089 | && (insn_uses_reg |
3090 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
3091 | MIPS16_REG))) | |
252b5132 | 3092 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
3093 | && (insn_uses_reg |
3094 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
3095 | MIPS16_REG))) | |
252b5132 | 3096 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
3097 | && (insn_uses_reg |
3098 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
3099 | MIPS16_REG))) | |
252b5132 RH |
3100 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
3101 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3102 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3103 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3104 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3105 | && insn_uses_reg (ip, | |
47e39b9d RS |
3106 | MIPS16OP_EXTRACT_REG32R |
3107 | (history[0].insn_opcode), | |
252b5132 RH |
3108 | MIPS_GR_REG)))) |
3109 | /* If the branch writes a register that the previous | |
3110 | instruction sets, we can not swap (we know that | |
3111 | branches write only to RD or to $31). */ | |
3112 | || (! mips_opts.mips16 | |
3113 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3114 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3115 | && (EXTRACT_OPERAND (RT, history[0]) |
3116 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3117 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3118 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3119 | || (! mips_opts.mips16 |
3120 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3121 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3122 | && (EXTRACT_OPERAND (RD, history[0]) |
3123 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3124 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3125 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3126 | || (mips_opts.mips16 |
3127 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3128 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3129 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3130 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3131 | == RA)))) |
3132 | /* If the branch writes a register that the previous | |
3133 | instruction reads, we can not swap (we know that | |
3134 | branches only write to RD or to $31). */ | |
3135 | || (! mips_opts.mips16 | |
3136 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3137 | && insn_uses_reg (&history[0], |
bf12938e | 3138 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3139 | MIPS_GR_REG)) |
3140 | || (! mips_opts.mips16 | |
3141 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3142 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3143 | || (mips_opts.mips16 |
3144 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3145 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3146 | /* If one instruction sets a condition code and the |
3147 | other one uses a condition code, we can not swap. */ | |
3148 | || ((pinfo & INSN_READ_COND_CODE) | |
3149 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3150 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3151 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3152 | /* If the previous instruction uses the PC, we can not | |
3153 | swap. */ | |
3154 | || (mips_opts.mips16 | |
3155 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3156 | /* If the previous instruction had a fixup in mips16 |
3157 | mode, we can not swap. This normally means that the | |
3158 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3159 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3160 | /* If the previous instruction is a sync, sync.l, or |
3161 | sync.p, we can not swap. */ | |
f173e82e | 3162 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 3163 | { |
29024861 DU |
3164 | if (mips_opts.mips16 |
3165 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3166 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3167 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3168 | { |
3169 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3170 | ip->insn_opcode |= 0x0080; | |
3171 | install_insn (ip); | |
3172 | insert_into_history (0, 1, ip); | |
3173 | } | |
3174 | else | |
3175 | { | |
3176 | /* We could do even better for unconditional branches to | |
3177 | portions of this object file; we could pick up the | |
3178 | instruction at the destination, put it in the delay | |
3179 | slot, and bump the destination address. */ | |
3180 | insert_into_history (0, 1, ip); | |
3181 | emit_nop (); | |
3182 | } | |
3183 | ||
dd22970f ILT |
3184 | if (mips_relax.sequence) |
3185 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3186 | } |
3187 | else | |
3188 | { | |
3189 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3190 | struct mips_cl_insn delay = history[0]; |
3191 | if (mips_opts.mips16) | |
252b5132 | 3192 | { |
b8ee1a6e DU |
3193 | know (delay.frag == ip->frag); |
3194 | move_insn (ip, delay.frag, delay.where); | |
3195 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3196 | } |
3197 | else if (relaxed_branch) | |
3198 | { | |
3199 | /* Add the delay slot instruction to the end of the | |
3200 | current frag and shrink the fixed part of the | |
3201 | original frag. If the branch occupies the tail of | |
3202 | the latter, move it backwards to cover the gap. */ | |
3203 | delay.frag->fr_fix -= 4; | |
3204 | if (delay.frag == ip->frag) | |
3205 | move_insn (ip, ip->frag, ip->where - 4); | |
3206 | add_fixed_insn (&delay); | |
252b5132 RH |
3207 | } |
3208 | else | |
3209 | { | |
1e915849 RS |
3210 | move_insn (&delay, ip->frag, ip->where); |
3211 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3212 | } |
1e915849 RS |
3213 | history[0] = *ip; |
3214 | delay.fixed_p = 1; | |
3215 | insert_into_history (0, 1, &delay); | |
252b5132 | 3216 | } |
252b5132 RH |
3217 | |
3218 | /* If that was an unconditional branch, forget the previous | |
3219 | insn information. */ | |
3220 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 3221 | mips_no_prev_insn (); |
252b5132 RH |
3222 | } |
3223 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3224 | { | |
3225 | /* We don't yet optimize a branch likely. What we should do | |
3226 | is look at the target, copy the instruction found there | |
3227 | into the delay slot, and increment the branch to jump to | |
3228 | the next instruction. */ | |
1e915849 | 3229 | insert_into_history (0, 1, ip); |
252b5132 | 3230 | emit_nop (); |
252b5132 RH |
3231 | } |
3232 | else | |
1e915849 | 3233 | insert_into_history (0, 1, ip); |
252b5132 | 3234 | } |
1e915849 RS |
3235 | else |
3236 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3237 | |
3238 | /* We just output an insn, so the next one doesn't have a label. */ | |
3239 | mips_clear_insn_labels (); | |
252b5132 RH |
3240 | } |
3241 | ||
7d10b47d | 3242 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3243 | |
3244 | static void | |
7d10b47d | 3245 | mips_no_prev_insn (void) |
252b5132 | 3246 | { |
7d10b47d RS |
3247 | prev_nop_frag = NULL; |
3248 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3249 | mips_clear_insn_labels (); |
3250 | } | |
3251 | ||
7d10b47d RS |
3252 | /* This function must be called before we emit something other than |
3253 | instructions. It is like mips_no_prev_insn except that it inserts | |
3254 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3255 | |
7d10b47d RS |
3256 | void |
3257 | mips_emit_delays (void) | |
252b5132 RH |
3258 | { |
3259 | if (! mips_opts.noreorder) | |
3260 | { | |
71400594 | 3261 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3262 | if (nops > 0) |
3263 | { | |
7d10b47d RS |
3264 | while (nops-- > 0) |
3265 | add_fixed_insn (NOP_INSN); | |
3266 | mips_move_labels (); | |
3267 | } | |
3268 | } | |
3269 | mips_no_prev_insn (); | |
3270 | } | |
3271 | ||
3272 | /* Start a (possibly nested) noreorder block. */ | |
3273 | ||
3274 | static void | |
3275 | start_noreorder (void) | |
3276 | { | |
3277 | if (mips_opts.noreorder == 0) | |
3278 | { | |
3279 | unsigned int i; | |
3280 | int nops; | |
3281 | ||
3282 | /* None of the instructions before the .set noreorder can be moved. */ | |
3283 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3284 | history[i].fixed_p = 1; | |
3285 | ||
3286 | /* Insert any nops that might be needed between the .set noreorder | |
3287 | block and the previous instructions. We will later remove any | |
3288 | nops that turn out not to be needed. */ | |
3289 | nops = nops_for_insn (history, NULL); | |
3290 | if (nops > 0) | |
3291 | { | |
3292 | if (mips_optimize != 0) | |
252b5132 RH |
3293 | { |
3294 | /* Record the frag which holds the nop instructions, so | |
3295 | that we can remove them if we don't need them. */ | |
3296 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3297 | prev_nop_frag = frag_now; | |
3298 | prev_nop_frag_holds = nops; | |
3299 | prev_nop_frag_required = 0; | |
3300 | prev_nop_frag_since = 0; | |
3301 | } | |
3302 | ||
3303 | for (; nops > 0; --nops) | |
1e915849 | 3304 | add_fixed_insn (NOP_INSN); |
252b5132 | 3305 | |
7d10b47d RS |
3306 | /* Move on to a new frag, so that it is safe to simply |
3307 | decrease the size of prev_nop_frag. */ | |
3308 | frag_wane (frag_now); | |
3309 | frag_new (0); | |
404a8071 | 3310 | mips_move_labels (); |
252b5132 | 3311 | } |
7d10b47d RS |
3312 | mips16_mark_labels (); |
3313 | mips_clear_insn_labels (); | |
252b5132 | 3314 | } |
7d10b47d RS |
3315 | mips_opts.noreorder++; |
3316 | mips_any_noreorder = 1; | |
3317 | } | |
252b5132 | 3318 | |
7d10b47d | 3319 | /* End a nested noreorder block. */ |
252b5132 | 3320 | |
7d10b47d RS |
3321 | static void |
3322 | end_noreorder (void) | |
3323 | { | |
3324 | mips_opts.noreorder--; | |
3325 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3326 | { | |
3327 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3328 | handling nop insertion the .set reorder way. */ | |
3329 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3330 | * (mips_opts.mips16 ? 2 : 4)); | |
3331 | insert_into_history (prev_nop_frag_since, | |
3332 | prev_nop_frag_required, NOP_INSN); | |
3333 | prev_nop_frag = NULL; | |
3334 | } | |
252b5132 RH |
3335 | } |
3336 | ||
584892a6 RS |
3337 | /* Set up global variables for the start of a new macro. */ |
3338 | ||
3339 | static void | |
3340 | macro_start (void) | |
3341 | { | |
3342 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3343 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3344 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3345 | & (INSN_UNCOND_BRANCH_DELAY |
3346 | | INSN_COND_BRANCH_DELAY | |
3347 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3348 | } | |
3349 | ||
3350 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3351 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3352 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3353 | ||
3354 | static const char * | |
3355 | macro_warning (relax_substateT subtype) | |
3356 | { | |
3357 | if (subtype & RELAX_DELAY_SLOT) | |
3358 | return _("Macro instruction expanded into multiple instructions" | |
3359 | " in a branch delay slot"); | |
3360 | else if (subtype & RELAX_NOMACRO) | |
3361 | return _("Macro instruction expanded into multiple instructions"); | |
3362 | else | |
3363 | return 0; | |
3364 | } | |
3365 | ||
3366 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3367 | ||
3368 | static void | |
3369 | macro_end (void) | |
3370 | { | |
3371 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3372 | { | |
3373 | relax_substateT subtype; | |
3374 | ||
3375 | /* Set up the relaxation warning flags. */ | |
3376 | subtype = 0; | |
3377 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3378 | subtype |= RELAX_SECOND_LONGER; | |
3379 | if (mips_opts.warn_about_macros) | |
3380 | subtype |= RELAX_NOMACRO; | |
3381 | if (mips_macro_warning.delay_slot_p) | |
3382 | subtype |= RELAX_DELAY_SLOT; | |
3383 | ||
3384 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3385 | { | |
3386 | /* Either the macro has a single implementation or both | |
3387 | implementations are longer than 4 bytes. Emit the | |
3388 | warning now. */ | |
3389 | const char *msg = macro_warning (subtype); | |
3390 | if (msg != 0) | |
3391 | as_warn (msg); | |
3392 | } | |
3393 | else | |
3394 | { | |
3395 | /* One implementation might need a warning but the other | |
3396 | definitely doesn't. */ | |
3397 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3398 | } | |
3399 | } | |
3400 | } | |
3401 | ||
6e1304d8 RS |
3402 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3403 | The first argument in *ARGS will be either the code for a single | |
3404 | relocation or -1 followed by the three codes that make up a | |
3405 | composite relocation. */ | |
3406 | ||
3407 | static void | |
3408 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3409 | { | |
3410 | int i, next; | |
3411 | ||
3412 | next = va_arg (*args, int); | |
3413 | if (next >= 0) | |
3414 | r[0] = (bfd_reloc_code_real_type) next; | |
3415 | else | |
3416 | for (i = 0; i < 3; i++) | |
3417 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3418 | } | |
3419 | ||
252b5132 RH |
3420 | /* Build an instruction created by a macro expansion. This is passed |
3421 | a pointer to the count of instructions created so far, an | |
3422 | expression, the name of the instruction to build, an operand format | |
3423 | string, and corresponding arguments. */ | |
3424 | ||
252b5132 | 3425 | static void |
67c0d1eb | 3426 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3427 | { |
1e915849 | 3428 | const struct mips_opcode *mo; |
252b5132 | 3429 | struct mips_cl_insn insn; |
f6688943 | 3430 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3431 | va_list args; |
252b5132 | 3432 | |
252b5132 | 3433 | va_start (args, fmt); |
252b5132 | 3434 | |
252b5132 RH |
3435 | if (mips_opts.mips16) |
3436 | { | |
67c0d1eb | 3437 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3438 | va_end (args); |
3439 | return; | |
3440 | } | |
3441 | ||
f6688943 TS |
3442 | r[0] = BFD_RELOC_UNUSED; |
3443 | r[1] = BFD_RELOC_UNUSED; | |
3444 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3445 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3446 | assert (mo); | |
3447 | assert (strcmp (name, mo->name) == 0); | |
3448 | ||
8b082fb1 TS |
3449 | while (1) |
3450 | { | |
3451 | /* Search until we get a match for NAME. It is assumed here that | |
3452 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3453 | if (strcmp (fmt, mo->args) == 0 | |
3454 | && mo->pinfo != INSN_MACRO | |
037b32b9 | 3455 | && is_opcode_valid (mo, TRUE)) |
8b082fb1 TS |
3456 | break; |
3457 | ||
1e915849 RS |
3458 | ++mo; |
3459 | assert (mo->name); | |
3460 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3461 | } |
3462 | ||
1e915849 | 3463 | create_insn (&insn, mo); |
252b5132 RH |
3464 | for (;;) |
3465 | { | |
3466 | switch (*fmt++) | |
3467 | { | |
3468 | case '\0': | |
3469 | break; | |
3470 | ||
3471 | case ',': | |
3472 | case '(': | |
3473 | case ')': | |
3474 | continue; | |
3475 | ||
5f74bc13 CD |
3476 | case '+': |
3477 | switch (*fmt++) | |
3478 | { | |
3479 | case 'A': | |
3480 | case 'E': | |
bf12938e | 3481 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3482 | continue; |
3483 | ||
3484 | case 'B': | |
3485 | case 'F': | |
3486 | /* Note that in the macro case, these arguments are already | |
3487 | in MSB form. (When handling the instruction in the | |
3488 | non-macro case, these arguments are sizes from which | |
3489 | MSB values must be calculated.) */ | |
bf12938e | 3490 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3491 | continue; |
3492 | ||
3493 | case 'C': | |
3494 | case 'G': | |
3495 | case 'H': | |
3496 | /* Note that in the macro case, these arguments are already | |
3497 | in MSBD form. (When handling the instruction in the | |
3498 | non-macro case, these arguments are sizes from which | |
3499 | MSBD values must be calculated.) */ | |
bf12938e | 3500 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3501 | continue; |
3502 | ||
3503 | default: | |
3504 | internalError (); | |
3505 | } | |
3506 | continue; | |
3507 | ||
8b082fb1 TS |
3508 | case '2': |
3509 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3510 | continue; | |
3511 | ||
252b5132 RH |
3512 | case 't': |
3513 | case 'w': | |
3514 | case 'E': | |
bf12938e | 3515 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3516 | continue; |
3517 | ||
3518 | case 'c': | |
bf12938e | 3519 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3520 | continue; |
3521 | ||
252b5132 RH |
3522 | case 'T': |
3523 | case 'W': | |
bf12938e | 3524 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3525 | continue; |
3526 | ||
3527 | case 'd': | |
3528 | case 'G': | |
af7ee8bf | 3529 | case 'K': |
bf12938e | 3530 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3531 | continue; |
3532 | ||
4372b673 NC |
3533 | case 'U': |
3534 | { | |
3535 | int tmp = va_arg (args, int); | |
3536 | ||
bf12938e RS |
3537 | INSERT_OPERAND (RT, insn, tmp); |
3538 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3539 | continue; |
4372b673 NC |
3540 | } |
3541 | ||
252b5132 RH |
3542 | case 'V': |
3543 | case 'S': | |
bf12938e | 3544 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3545 | continue; |
3546 | ||
3547 | case 'z': | |
3548 | continue; | |
3549 | ||
3550 | case '<': | |
bf12938e | 3551 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3552 | continue; |
3553 | ||
3554 | case 'D': | |
bf12938e | 3555 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3556 | continue; |
3557 | ||
3558 | case 'B': | |
bf12938e | 3559 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3560 | continue; |
3561 | ||
4372b673 | 3562 | case 'J': |
bf12938e | 3563 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3564 | continue; |
3565 | ||
252b5132 | 3566 | case 'q': |
bf12938e | 3567 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3568 | continue; |
3569 | ||
3570 | case 'b': | |
3571 | case 's': | |
3572 | case 'r': | |
3573 | case 'v': | |
bf12938e | 3574 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3575 | continue; |
3576 | ||
3577 | case 'i': | |
3578 | case 'j': | |
3579 | case 'o': | |
6e1304d8 | 3580 | macro_read_relocs (&args, r); |
cdf6fd85 | 3581 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3582 | || *r == BFD_RELOC_MIPS_LITERAL |
3583 | || *r == BFD_RELOC_MIPS_HIGHER | |
3584 | || *r == BFD_RELOC_HI16_S | |
3585 | || *r == BFD_RELOC_LO16 | |
3586 | || *r == BFD_RELOC_MIPS_GOT16 | |
3587 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3588 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3589 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3590 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3591 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3592 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3593 | continue; |
3594 | ||
3595 | case 'u': | |
6e1304d8 | 3596 | macro_read_relocs (&args, r); |
252b5132 RH |
3597 | assert (ep != NULL |
3598 | && (ep->X_op == O_constant | |
3599 | || (ep->X_op == O_symbol | |
f6688943 TS |
3600 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3601 | || *r == BFD_RELOC_HI16_S | |
3602 | || *r == BFD_RELOC_HI16 | |
3603 | || *r == BFD_RELOC_GPREL16 | |
3604 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3605 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3606 | continue; |
3607 | ||
3608 | case 'p': | |
3609 | assert (ep != NULL); | |
bad36eac | 3610 | |
252b5132 RH |
3611 | /* |
3612 | * This allows macro() to pass an immediate expression for | |
3613 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3614 | * |
3615 | * We don't allow branch relaxation for these branches, as | |
3616 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3617 | */ |
3618 | if (ep->X_op == O_constant) | |
3619 | { | |
bad36eac DJ |
3620 | if ((ep->X_add_number & 3) != 0) |
3621 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3622 | (unsigned long) ep->X_add_number); | |
3623 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3624 | as_bad (_("branch address range overflow (0x%lx)"), | |
3625 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3626 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3627 | ep = NULL; | |
3628 | } | |
3629 | else | |
0b25d3e6 | 3630 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3631 | continue; |
3632 | ||
3633 | case 'a': | |
3634 | assert (ep != NULL); | |
f6688943 | 3635 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3636 | continue; |
3637 | ||
3638 | case 'C': | |
a9e24354 | 3639 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3640 | continue; |
3641 | ||
d43b4baf | 3642 | case 'k': |
a9e24354 | 3643 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3644 | continue; |
3645 | ||
252b5132 RH |
3646 | default: |
3647 | internalError (); | |
3648 | } | |
3649 | break; | |
3650 | } | |
3651 | va_end (args); | |
f6688943 | 3652 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3653 | |
4d7206a2 | 3654 | append_insn (&insn, ep, r); |
252b5132 RH |
3655 | } |
3656 | ||
3657 | static void | |
67c0d1eb | 3658 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3659 | va_list args) |
252b5132 | 3660 | { |
1e915849 | 3661 | struct mips_opcode *mo; |
252b5132 | 3662 | struct mips_cl_insn insn; |
f6688943 TS |
3663 | bfd_reloc_code_real_type r[3] |
3664 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3665 | |
1e915849 RS |
3666 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3667 | assert (mo); | |
3668 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3669 | |
1e915849 | 3670 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3671 | { |
1e915849 RS |
3672 | ++mo; |
3673 | assert (mo->name); | |
3674 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3675 | } |
3676 | ||
1e915849 | 3677 | create_insn (&insn, mo); |
252b5132 RH |
3678 | for (;;) |
3679 | { | |
3680 | int c; | |
3681 | ||
3682 | c = *fmt++; | |
3683 | switch (c) | |
3684 | { | |
3685 | case '\0': | |
3686 | break; | |
3687 | ||
3688 | case ',': | |
3689 | case '(': | |
3690 | case ')': | |
3691 | continue; | |
3692 | ||
3693 | case 'y': | |
3694 | case 'w': | |
bf12938e | 3695 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3696 | continue; |
3697 | ||
3698 | case 'x': | |
3699 | case 'v': | |
bf12938e | 3700 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3701 | continue; |
3702 | ||
3703 | case 'z': | |
bf12938e | 3704 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3705 | continue; |
3706 | ||
3707 | case 'Z': | |
bf12938e | 3708 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3709 | continue; |
3710 | ||
3711 | case '0': | |
3712 | case 'S': | |
3713 | case 'P': | |
3714 | case 'R': | |
3715 | continue; | |
3716 | ||
3717 | case 'X': | |
bf12938e | 3718 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3719 | continue; |
3720 | ||
3721 | case 'Y': | |
3722 | { | |
3723 | int regno; | |
3724 | ||
3725 | regno = va_arg (args, int); | |
3726 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3727 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3728 | } |
3729 | continue; | |
3730 | ||
3731 | case '<': | |
3732 | case '>': | |
3733 | case '4': | |
3734 | case '5': | |
3735 | case 'H': | |
3736 | case 'W': | |
3737 | case 'D': | |
3738 | case 'j': | |
3739 | case '8': | |
3740 | case 'V': | |
3741 | case 'C': | |
3742 | case 'U': | |
3743 | case 'k': | |
3744 | case 'K': | |
3745 | case 'p': | |
3746 | case 'q': | |
3747 | { | |
3748 | assert (ep != NULL); | |
3749 | ||
3750 | if (ep->X_op != O_constant) | |
874e8986 | 3751 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3752 | else |
3753 | { | |
b34976b6 AM |
3754 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3755 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3756 | &insn.extend); |
252b5132 | 3757 | ep = NULL; |
f6688943 | 3758 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3759 | } |
3760 | } | |
3761 | continue; | |
3762 | ||
3763 | case '6': | |
bf12938e | 3764 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3765 | continue; |
3766 | } | |
3767 | ||
3768 | break; | |
3769 | } | |
3770 | ||
f6688943 | 3771 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3772 | |
4d7206a2 | 3773 | append_insn (&insn, ep, r); |
252b5132 RH |
3774 | } |
3775 | ||
2051e8c4 MR |
3776 | /* |
3777 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3778 | * higher bits unset. | |
3779 | */ | |
9f872bbe | 3780 | static void |
2051e8c4 MR |
3781 | normalize_constant_expr (expressionS *ex) |
3782 | { | |
9ee2a2d4 | 3783 | if (ex->X_op == O_constant |
2051e8c4 MR |
3784 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3785 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3786 | - 0x80000000); | |
3787 | } | |
3788 | ||
3789 | /* | |
3790 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3791 | * all higher bits unset. | |
3792 | */ | |
3793 | static void | |
3794 | normalize_address_expr (expressionS *ex) | |
3795 | { | |
3796 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3797 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3798 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3799 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3800 | - 0x80000000); | |
3801 | } | |
3802 | ||
438c16b8 TS |
3803 | /* |
3804 | * Generate a "jalr" instruction with a relocation hint to the called | |
3805 | * function. This occurs in NewABI PIC code. | |
3806 | */ | |
3807 | static void | |
67c0d1eb | 3808 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3809 | { |
685736be | 3810 | char *f = NULL; |
b34976b6 | 3811 | |
438c16b8 | 3812 | if (HAVE_NEWABI) |
f21f8242 | 3813 | { |
cc3d92a5 | 3814 | frag_grow (8); |
f21f8242 AO |
3815 | f = frag_more (0); |
3816 | } | |
67c0d1eb | 3817 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3818 | if (HAVE_NEWABI) |
f21f8242 | 3819 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3820 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3821 | } |
3822 | ||
252b5132 RH |
3823 | /* |
3824 | * Generate a "lui" instruction. | |
3825 | */ | |
3826 | static void | |
67c0d1eb | 3827 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3828 | { |
3829 | expressionS high_expr; | |
1e915849 | 3830 | const struct mips_opcode *mo; |
252b5132 | 3831 | struct mips_cl_insn insn; |
f6688943 TS |
3832 | bfd_reloc_code_real_type r[3] |
3833 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3834 | const char *name = "lui"; |
3835 | const char *fmt = "t,u"; | |
252b5132 RH |
3836 | |
3837 | assert (! mips_opts.mips16); | |
3838 | ||
4d7206a2 | 3839 | high_expr = *ep; |
252b5132 RH |
3840 | |
3841 | if (high_expr.X_op == O_constant) | |
3842 | { | |
54f4ddb3 | 3843 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
3844 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3845 | >> 16) & 0xffff; | |
f6688943 | 3846 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3847 | } |
78e1bb40 | 3848 | else |
252b5132 RH |
3849 | { |
3850 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3851 | /* _gp_disp is a special case, used from s_cpload. |
3852 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3853 | assert (mips_pic == NO_PIC |
78e1bb40 | 3854 | || (! HAVE_NEWABI |
aa6975fb ILT |
3855 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3856 | || (! mips_in_shared | |
bbe506e8 TS |
3857 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3858 | "__gnu_local_gp") == 0)); | |
f6688943 | 3859 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3860 | } |
3861 | ||
1e915849 RS |
3862 | mo = hash_find (op_hash, name); |
3863 | assert (strcmp (name, mo->name) == 0); | |
3864 | assert (strcmp (fmt, mo->args) == 0); | |
3865 | create_insn (&insn, mo); | |
252b5132 | 3866 | |
bf12938e RS |
3867 | insn.insn_opcode = insn.insn_mo->match; |
3868 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3869 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3870 | { |
3871 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3872 | append_insn (&insn, NULL, r); |
252b5132 RH |
3873 | } |
3874 | else | |
4d7206a2 | 3875 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3876 | } |
3877 | ||
885add95 CD |
3878 | /* Generate a sequence of instructions to do a load or store from a constant |
3879 | offset off of a base register (breg) into/from a target register (treg), | |
3880 | using AT if necessary. */ | |
3881 | static void | |
67c0d1eb RS |
3882 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3883 | int treg, int breg, int dbl) | |
885add95 CD |
3884 | { |
3885 | assert (ep->X_op == O_constant); | |
3886 | ||
256ab948 | 3887 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3888 | if (!dbl) |
3889 | normalize_constant_expr (ep); | |
256ab948 | 3890 | |
67c1ffbe | 3891 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3892 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3893 | as_warn (_("operand overflow")); |
3894 | ||
3895 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3896 | { | |
3897 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3898 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3899 | } |
3900 | else | |
3901 | { | |
3902 | /* 32-bit offset, need multiple instructions and AT, like: | |
3903 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3904 | addu $tempreg,$tempreg,$breg | |
3905 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3906 | to handle the complete offset. */ | |
67c0d1eb RS |
3907 | macro_build_lui (ep, AT); |
3908 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3909 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 3910 | |
741fe287 | 3911 | if (!mips_opts.at) |
8fc2e39e | 3912 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3913 | } |
3914 | } | |
3915 | ||
252b5132 RH |
3916 | /* set_at() |
3917 | * Generates code to set the $at register to true (one) | |
3918 | * if reg is less than the immediate expression. | |
3919 | */ | |
3920 | static void | |
67c0d1eb | 3921 | set_at (int reg, int unsignedp) |
252b5132 RH |
3922 | { |
3923 | if (imm_expr.X_op == O_constant | |
3924 | && imm_expr.X_add_number >= -0x8000 | |
3925 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3926 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3927 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3928 | else |
3929 | { | |
67c0d1eb RS |
3930 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3931 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3932 | } |
3933 | } | |
3934 | ||
3935 | /* Warn if an expression is not a constant. */ | |
3936 | ||
3937 | static void | |
17a2f251 | 3938 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3939 | { |
3940 | if (ex->X_op == O_big) | |
3941 | as_bad (_("unsupported large constant")); | |
3942 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3943 | as_bad (_("Instruction %s requires absolute expression"), |
3944 | ip->insn_mo->name); | |
13757d0c | 3945 | |
9ee2a2d4 MR |
3946 | if (HAVE_32BIT_GPRS) |
3947 | normalize_constant_expr (ex); | |
252b5132 RH |
3948 | } |
3949 | ||
3950 | /* Count the leading zeroes by performing a binary chop. This is a | |
3951 | bulky bit of source, but performance is a LOT better for the | |
3952 | majority of values than a simple loop to count the bits: | |
3953 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3954 | if ((v) & (1 << (31 - lcnt))) | |
3955 | break; | |
3956 | However it is not code size friendly, and the gain will drop a bit | |
3957 | on certain cached systems. | |
3958 | */ | |
3959 | #define COUNT_TOP_ZEROES(v) \ | |
3960 | (((v) & ~0xffff) == 0 \ | |
3961 | ? ((v) & ~0xff) == 0 \ | |
3962 | ? ((v) & ~0xf) == 0 \ | |
3963 | ? ((v) & ~0x3) == 0 \ | |
3964 | ? ((v) & ~0x1) == 0 \ | |
3965 | ? !(v) \ | |
3966 | ? 32 \ | |
3967 | : 31 \ | |
3968 | : 30 \ | |
3969 | : ((v) & ~0x7) == 0 \ | |
3970 | ? 29 \ | |
3971 | : 28 \ | |
3972 | : ((v) & ~0x3f) == 0 \ | |
3973 | ? ((v) & ~0x1f) == 0 \ | |
3974 | ? 27 \ | |
3975 | : 26 \ | |
3976 | : ((v) & ~0x7f) == 0 \ | |
3977 | ? 25 \ | |
3978 | : 24 \ | |
3979 | : ((v) & ~0xfff) == 0 \ | |
3980 | ? ((v) & ~0x3ff) == 0 \ | |
3981 | ? ((v) & ~0x1ff) == 0 \ | |
3982 | ? 23 \ | |
3983 | : 22 \ | |
3984 | : ((v) & ~0x7ff) == 0 \ | |
3985 | ? 21 \ | |
3986 | : 20 \ | |
3987 | : ((v) & ~0x3fff) == 0 \ | |
3988 | ? ((v) & ~0x1fff) == 0 \ | |
3989 | ? 19 \ | |
3990 | : 18 \ | |
3991 | : ((v) & ~0x7fff) == 0 \ | |
3992 | ? 17 \ | |
3993 | : 16 \ | |
3994 | : ((v) & ~0xffffff) == 0 \ | |
3995 | ? ((v) & ~0xfffff) == 0 \ | |
3996 | ? ((v) & ~0x3ffff) == 0 \ | |
3997 | ? ((v) & ~0x1ffff) == 0 \ | |
3998 | ? 15 \ | |
3999 | : 14 \ | |
4000 | : ((v) & ~0x7ffff) == 0 \ | |
4001 | ? 13 \ | |
4002 | : 12 \ | |
4003 | : ((v) & ~0x3fffff) == 0 \ | |
4004 | ? ((v) & ~0x1fffff) == 0 \ | |
4005 | ? 11 \ | |
4006 | : 10 \ | |
4007 | : ((v) & ~0x7fffff) == 0 \ | |
4008 | ? 9 \ | |
4009 | : 8 \ | |
4010 | : ((v) & ~0xfffffff) == 0 \ | |
4011 | ? ((v) & ~0x3ffffff) == 0 \ | |
4012 | ? ((v) & ~0x1ffffff) == 0 \ | |
4013 | ? 7 \ | |
4014 | : 6 \ | |
4015 | : ((v) & ~0x7ffffff) == 0 \ | |
4016 | ? 5 \ | |
4017 | : 4 \ | |
4018 | : ((v) & ~0x3fffffff) == 0 \ | |
4019 | ? ((v) & ~0x1fffffff) == 0 \ | |
4020 | ? 3 \ | |
4021 | : 2 \ | |
4022 | : ((v) & ~0x7fffffff) == 0 \ | |
4023 | ? 1 \ | |
4024 | : 0) | |
4025 | ||
4026 | /* load_register() | |
67c1ffbe | 4027 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4028 | * an absolute expression value into a register. |
4029 | */ | |
4030 | static void | |
67c0d1eb | 4031 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4032 | { |
4033 | int freg; | |
4034 | expressionS hi32, lo32; | |
4035 | ||
4036 | if (ep->X_op != O_big) | |
4037 | { | |
4038 | assert (ep->X_op == O_constant); | |
256ab948 TS |
4039 | |
4040 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4041 | if (!dbl) |
4042 | normalize_constant_expr (ep); | |
256ab948 TS |
4043 | |
4044 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4045 | { |
4046 | /* We can handle 16 bit signed values with an addiu to | |
4047 | $zero. No need to ever use daddiu here, since $zero and | |
4048 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4049 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4050 | return; |
4051 | } | |
4052 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4053 | { | |
4054 | /* We can handle 16 bit unsigned values with an ori to | |
4055 | $zero. */ | |
67c0d1eb | 4056 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4057 | return; |
4058 | } | |
256ab948 | 4059 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4060 | { |
4061 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4062 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4063 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4064 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4065 | return; |
4066 | } | |
4067 | } | |
4068 | ||
4069 | /* The value is larger than 32 bits. */ | |
4070 | ||
2051e8c4 | 4071 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4072 | { |
55e08f71 NC |
4073 | char value[32]; |
4074 | ||
4075 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4076 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4077 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4078 | return; |
4079 | } | |
4080 | ||
4081 | if (ep->X_op != O_big) | |
4082 | { | |
4083 | hi32 = *ep; | |
4084 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4085 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4086 | hi32.X_add_number &= 0xffffffff; | |
4087 | lo32 = *ep; | |
4088 | lo32.X_add_number &= 0xffffffff; | |
4089 | } | |
4090 | else | |
4091 | { | |
4092 | assert (ep->X_add_number > 2); | |
4093 | if (ep->X_add_number == 3) | |
4094 | generic_bignum[3] = 0; | |
4095 | else if (ep->X_add_number > 4) | |
4096 | as_bad (_("Number larger than 64 bits")); | |
4097 | lo32.X_op = O_constant; | |
4098 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4099 | hi32.X_op = O_constant; | |
4100 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4101 | } | |
4102 | ||
4103 | if (hi32.X_add_number == 0) | |
4104 | freg = 0; | |
4105 | else | |
4106 | { | |
4107 | int shift, bit; | |
4108 | unsigned long hi, lo; | |
4109 | ||
956cd1d6 | 4110 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4111 | { |
4112 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4113 | { | |
67c0d1eb | 4114 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4115 | return; |
4116 | } | |
4117 | if (lo32.X_add_number & 0x80000000) | |
4118 | { | |
67c0d1eb | 4119 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4120 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4121 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4122 | return; |
4123 | } | |
4124 | } | |
252b5132 RH |
4125 | |
4126 | /* Check for 16bit shifted constant. We know that hi32 is | |
4127 | non-zero, so start the mask on the first bit of the hi32 | |
4128 | value. */ | |
4129 | shift = 17; | |
4130 | do | |
beae10d5 KH |
4131 | { |
4132 | unsigned long himask, lomask; | |
4133 | ||
4134 | if (shift < 32) | |
4135 | { | |
4136 | himask = 0xffff >> (32 - shift); | |
4137 | lomask = (0xffff << shift) & 0xffffffff; | |
4138 | } | |
4139 | else | |
4140 | { | |
4141 | himask = 0xffff << (shift - 32); | |
4142 | lomask = 0; | |
4143 | } | |
4144 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4145 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4146 | { | |
4147 | expressionS tmp; | |
4148 | ||
4149 | tmp.X_op = O_constant; | |
4150 | if (shift < 32) | |
4151 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4152 | | (lo32.X_add_number >> shift)); | |
4153 | else | |
4154 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4155 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4156 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4157 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4158 | return; |
4159 | } | |
f9419b05 | 4160 | ++shift; |
beae10d5 KH |
4161 | } |
4162 | while (shift <= (64 - 16)); | |
252b5132 RH |
4163 | |
4164 | /* Find the bit number of the lowest one bit, and store the | |
4165 | shifted value in hi/lo. */ | |
4166 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4167 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4168 | if (lo != 0) | |
4169 | { | |
4170 | bit = 0; | |
4171 | while ((lo & 1) == 0) | |
4172 | { | |
4173 | lo >>= 1; | |
4174 | ++bit; | |
4175 | } | |
4176 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4177 | hi >>= bit; | |
4178 | } | |
4179 | else | |
4180 | { | |
4181 | bit = 32; | |
4182 | while ((hi & 1) == 0) | |
4183 | { | |
4184 | hi >>= 1; | |
4185 | ++bit; | |
4186 | } | |
4187 | lo = hi; | |
4188 | hi = 0; | |
4189 | } | |
4190 | ||
4191 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4192 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4193 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4194 | { |
4195 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4196 | if (shift != 0) |
beae10d5 | 4197 | { |
252b5132 RH |
4198 | expressionS tmp; |
4199 | ||
4200 | /* This instruction will set the register to be all | |
4201 | ones. */ | |
beae10d5 KH |
4202 | tmp.X_op = O_constant; |
4203 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4204 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4205 | if (bit != 0) |
4206 | { | |
4207 | bit += shift; | |
67c0d1eb RS |
4208 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4209 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4210 | } |
67c0d1eb RS |
4211 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4212 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4213 | return; |
4214 | } | |
4215 | } | |
252b5132 RH |
4216 | |
4217 | /* Sign extend hi32 before calling load_register, because we can | |
4218 | generally get better code when we load a sign extended value. */ | |
4219 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4220 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4221 | load_register (reg, &hi32, 0); |
252b5132 RH |
4222 | freg = reg; |
4223 | } | |
4224 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4225 | { | |
4226 | if (freg != 0) | |
4227 | { | |
67c0d1eb | 4228 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4229 | freg = reg; |
4230 | } | |
4231 | } | |
4232 | else | |
4233 | { | |
4234 | expressionS mid16; | |
4235 | ||
956cd1d6 | 4236 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4237 | { |
67c0d1eb RS |
4238 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4239 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4240 | return; |
4241 | } | |
252b5132 RH |
4242 | |
4243 | if (freg != 0) | |
4244 | { | |
67c0d1eb | 4245 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4246 | freg = reg; |
4247 | } | |
4248 | mid16 = lo32; | |
4249 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4250 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4251 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4252 | freg = reg; |
4253 | } | |
4254 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4255 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4256 | } |
4257 | ||
269137b2 TS |
4258 | static inline void |
4259 | load_delay_nop (void) | |
4260 | { | |
4261 | if (!gpr_interlocks) | |
4262 | macro_build (NULL, "nop", ""); | |
4263 | } | |
4264 | ||
252b5132 RH |
4265 | /* Load an address into a register. */ |
4266 | ||
4267 | static void | |
67c0d1eb | 4268 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4269 | { |
252b5132 RH |
4270 | if (ep->X_op != O_constant |
4271 | && ep->X_op != O_symbol) | |
4272 | { | |
4273 | as_bad (_("expression too complex")); | |
4274 | ep->X_op = O_constant; | |
4275 | } | |
4276 | ||
4277 | if (ep->X_op == O_constant) | |
4278 | { | |
67c0d1eb | 4279 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4280 | return; |
4281 | } | |
4282 | ||
4283 | if (mips_pic == NO_PIC) | |
4284 | { | |
4285 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4286 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4287 | Otherwise we want |
4288 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4289 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4290 | If we have an addend, we always use the latter form. |
76b3015f | 4291 | |
d6bc6245 TS |
4292 | With 64bit address space and a usable $at we want |
4293 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4294 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4295 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4296 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4297 | dsll32 $reg,0 | |
3a482fd5 | 4298 | daddu $reg,$reg,$at |
76b3015f | 4299 | |
c03099e6 | 4300 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4301 | on superscalar processors. |
4302 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4303 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4304 | dsll $reg,16 | |
4305 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4306 | dsll $reg,16 | |
4307 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4308 | |
4309 | For GP relative symbols in 64bit address space we can use | |
4310 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4311 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4312 | { |
6caf9ef4 TS |
4313 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4314 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4315 | { | |
4316 | relax_start (ep->X_add_symbol); | |
4317 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4318 | mips_gp_register, BFD_RELOC_GPREL16); | |
4319 | relax_switch (); | |
4320 | } | |
d6bc6245 | 4321 | |
741fe287 | 4322 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4323 | { |
67c0d1eb RS |
4324 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4325 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4326 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4327 | BFD_RELOC_MIPS_HIGHER); | |
4328 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4329 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4330 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4331 | *used_at = 1; |
4332 | } | |
4333 | else | |
4334 | { | |
67c0d1eb RS |
4335 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4336 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4337 | BFD_RELOC_MIPS_HIGHER); | |
4338 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4339 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4340 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4341 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4342 | } |
6caf9ef4 TS |
4343 | |
4344 | if (mips_relax.sequence) | |
4345 | relax_end (); | |
d6bc6245 | 4346 | } |
252b5132 RH |
4347 | else |
4348 | { | |
d6bc6245 | 4349 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4350 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4351 | { |
4d7206a2 | 4352 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4353 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4354 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4355 | relax_switch (); |
d6bc6245 | 4356 | } |
67c0d1eb RS |
4357 | macro_build_lui (ep, reg); |
4358 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4359 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4360 | if (mips_relax.sequence) |
4361 | relax_end (); | |
d6bc6245 | 4362 | } |
252b5132 | 4363 | } |
0a44bf69 | 4364 | else if (!mips_big_got) |
252b5132 RH |
4365 | { |
4366 | expressionS ex; | |
4367 | ||
4368 | /* If this is a reference to an external symbol, we want | |
4369 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4370 | Otherwise we want | |
4371 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4372 | nop | |
4373 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4374 | If there is a constant, it must be added in after. |
4375 | ||
ed6fb7bd | 4376 | If we have NewABI, we want |
f5040a92 AO |
4377 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4378 | unless we're referencing a global symbol with a non-zero | |
4379 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4380 | if (HAVE_NEWABI) |
4381 | { | |
f5040a92 AO |
4382 | if (ep->X_add_number) |
4383 | { | |
4d7206a2 | 4384 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4385 | ep->X_add_number = 0; |
4d7206a2 | 4386 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4387 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4388 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4389 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4390 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4391 | ex.X_op = O_constant; | |
67c0d1eb | 4392 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4393 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4394 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4395 | relax_switch (); |
f5040a92 | 4396 | } |
67c0d1eb | 4397 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4398 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4399 | if (mips_relax.sequence) |
4400 | relax_end (); | |
ed6fb7bd SC |
4401 | } |
4402 | else | |
4403 | { | |
f5040a92 AO |
4404 | ex.X_add_number = ep->X_add_number; |
4405 | ep->X_add_number = 0; | |
67c0d1eb RS |
4406 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4407 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4408 | load_delay_nop (); |
4d7206a2 RS |
4409 | relax_start (ep->X_add_symbol); |
4410 | relax_switch (); | |
67c0d1eb | 4411 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4412 | BFD_RELOC_LO16); |
4d7206a2 | 4413 | relax_end (); |
ed6fb7bd | 4414 | |
f5040a92 AO |
4415 | if (ex.X_add_number != 0) |
4416 | { | |
4417 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4418 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4419 | ex.X_op = O_constant; | |
67c0d1eb | 4420 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4421 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4422 | } |
252b5132 RH |
4423 | } |
4424 | } | |
0a44bf69 | 4425 | else if (mips_big_got) |
252b5132 RH |
4426 | { |
4427 | expressionS ex; | |
252b5132 RH |
4428 | |
4429 | /* This is the large GOT case. If this is a reference to an | |
4430 | external symbol, we want | |
4431 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4432 | addu $reg,$reg,$gp | |
4433 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4434 | |
4435 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4436 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4437 | nop | |
4438 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4439 | If there is a constant, it must be added in after. |
f5040a92 AO |
4440 | |
4441 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4442 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4443 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4444 | */ |
438c16b8 TS |
4445 | if (HAVE_NEWABI) |
4446 | { | |
4d7206a2 | 4447 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4448 | ep->X_add_number = 0; |
4d7206a2 | 4449 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4450 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4451 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4452 | reg, reg, mips_gp_register); | |
4453 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4454 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4455 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4456 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4457 | else if (ex.X_add_number) | |
4458 | { | |
4459 | ex.X_op = O_constant; | |
67c0d1eb RS |
4460 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4461 | BFD_RELOC_LO16); | |
f5040a92 AO |
4462 | } |
4463 | ||
4464 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4465 | relax_switch (); |
67c0d1eb | 4466 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4467 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4468 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4469 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4470 | relax_end (); |
438c16b8 | 4471 | } |
252b5132 | 4472 | else |
438c16b8 | 4473 | { |
f5040a92 AO |
4474 | ex.X_add_number = ep->X_add_number; |
4475 | ep->X_add_number = 0; | |
4d7206a2 | 4476 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4477 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4478 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4479 | reg, reg, mips_gp_register); | |
4480 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4481 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4482 | relax_switch (); |
4483 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4484 | { |
4485 | /* We need a nop before loading from $gp. This special | |
4486 | check is required because the lui which starts the main | |
4487 | instruction stream does not refer to $gp, and so will not | |
4488 | insert the nop which may be required. */ | |
67c0d1eb | 4489 | macro_build (NULL, "nop", ""); |
438c16b8 | 4490 | } |
67c0d1eb | 4491 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4492 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4493 | load_delay_nop (); |
67c0d1eb | 4494 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4495 | BFD_RELOC_LO16); |
4d7206a2 | 4496 | relax_end (); |
438c16b8 | 4497 | |
f5040a92 AO |
4498 | if (ex.X_add_number != 0) |
4499 | { | |
4500 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4501 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4502 | ex.X_op = O_constant; | |
67c0d1eb RS |
4503 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4504 | BFD_RELOC_LO16); | |
f5040a92 | 4505 | } |
252b5132 RH |
4506 | } |
4507 | } | |
252b5132 RH |
4508 | else |
4509 | abort (); | |
8fc2e39e | 4510 | |
741fe287 | 4511 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4512 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4513 | } |
4514 | ||
ea1fb5dc RS |
4515 | /* Move the contents of register SOURCE into register DEST. */ |
4516 | ||
4517 | static void | |
67c0d1eb | 4518 | move_register (int dest, int source) |
ea1fb5dc | 4519 | { |
67c0d1eb RS |
4520 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4521 | dest, source, 0); | |
ea1fb5dc RS |
4522 | } |
4523 | ||
4d7206a2 | 4524 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4525 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4526 | The two alternatives are: | |
4d7206a2 RS |
4527 | |
4528 | Global symbol Local sybmol | |
4529 | ------------- ------------ | |
4530 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4531 | ... ... | |
4532 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4533 | ||
4534 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4535 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4536 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4537 | |
4538 | static void | |
67c0d1eb | 4539 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4540 | { |
4541 | expressionS global; | |
4542 | ||
4543 | global = *local; | |
4544 | global.X_add_number = 0; | |
4545 | ||
4546 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4547 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4548 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4549 | relax_switch (); |
67c0d1eb RS |
4550 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4551 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4552 | relax_end (); |
4553 | } | |
4554 | ||
4555 | static void | |
67c0d1eb | 4556 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4557 | { |
4558 | expressionS global; | |
4559 | ||
4560 | global.X_op = O_constant; | |
4561 | global.X_op_symbol = NULL; | |
4562 | global.X_add_symbol = NULL; | |
4563 | global.X_add_number = local->X_add_number; | |
4564 | ||
4565 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4566 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4567 | dest, dest, BFD_RELOC_LO16); |
4568 | relax_switch (); | |
67c0d1eb | 4569 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4570 | relax_end (); |
4571 | } | |
4572 | ||
f6a22291 MR |
4573 | static void |
4574 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4575 | { | |
4576 | expressionS global; | |
4577 | int hold_mips_optimize; | |
4578 | ||
4579 | global.X_op = O_constant; | |
4580 | global.X_op_symbol = NULL; | |
4581 | global.X_add_symbol = NULL; | |
4582 | global.X_add_number = local->X_add_number; | |
4583 | ||
4584 | relax_start (local->X_add_symbol); | |
4585 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4586 | relax_switch (); | |
4587 | /* Set mips_optimize around the lui instruction to avoid | |
4588 | inserting an unnecessary nop after the lw. */ | |
4589 | hold_mips_optimize = mips_optimize; | |
4590 | mips_optimize = 2; | |
4591 | macro_build_lui (&global, tmp); | |
4592 | mips_optimize = hold_mips_optimize; | |
4593 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4594 | relax_end (); | |
4595 | ||
4596 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4597 | } | |
4598 | ||
252b5132 RH |
4599 | /* |
4600 | * Build macros | |
4601 | * This routine implements the seemingly endless macro or synthesized | |
4602 | * instructions and addressing modes in the mips assembly language. Many | |
4603 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4604 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4605 | * this verbose method. Others are not simple macros but are more like |
4606 | * optimizing code generation. | |
4607 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4608 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4609 | * The ensuing load upper instructions are ommited. This implies some kind |
4610 | * of global optimization. We currently only optimize within a single macro. | |
4611 | * For many of the load and store macros if the address is specified as a | |
4612 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4613 | * first load register 'at' with zero and use it as the base register. The | |
4614 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4615 | * we're missing. | |
4616 | */ | |
4617 | static void | |
17a2f251 | 4618 | macro (struct mips_cl_insn *ip) |
252b5132 | 4619 | { |
741fe287 MR |
4620 | unsigned int treg, sreg, dreg, breg; |
4621 | unsigned int tempreg; | |
252b5132 | 4622 | int mask; |
43841e91 | 4623 | int used_at = 0; |
252b5132 RH |
4624 | expressionS expr1; |
4625 | const char *s; | |
4626 | const char *s2; | |
4627 | const char *fmt; | |
4628 | int likely = 0; | |
4629 | int dbl = 0; | |
4630 | int coproc = 0; | |
4631 | int lr = 0; | |
4632 | int imm = 0; | |
1abe91b1 | 4633 | int call = 0; |
252b5132 | 4634 | int off; |
67c0d1eb | 4635 | offsetT maxnum; |
252b5132 | 4636 | bfd_reloc_code_real_type r; |
252b5132 RH |
4637 | int hold_mips_optimize; |
4638 | ||
4639 | assert (! mips_opts.mips16); | |
4640 | ||
4641 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4642 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4643 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4644 | mask = ip->insn_mo->mask; | |
4645 | ||
4646 | expr1.X_op = O_constant; | |
4647 | expr1.X_op_symbol = NULL; | |
4648 | expr1.X_add_symbol = NULL; | |
4649 | expr1.X_add_number = 1; | |
4650 | ||
4651 | switch (mask) | |
4652 | { | |
4653 | case M_DABS: | |
4654 | dbl = 1; | |
4655 | case M_ABS: | |
4656 | /* bgez $a0,.+12 | |
4657 | move v0,$a0 | |
4658 | sub v0,$zero,$a0 | |
4659 | */ | |
4660 | ||
7d10b47d | 4661 | start_noreorder (); |
252b5132 RH |
4662 | |
4663 | expr1.X_add_number = 8; | |
67c0d1eb | 4664 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4665 | if (dreg == sreg) |
67c0d1eb | 4666 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4667 | else |
67c0d1eb RS |
4668 | move_register (dreg, sreg); |
4669 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4670 | |
7d10b47d | 4671 | end_noreorder (); |
8fc2e39e | 4672 | break; |
252b5132 RH |
4673 | |
4674 | case M_ADD_I: | |
4675 | s = "addi"; | |
4676 | s2 = "add"; | |
4677 | goto do_addi; | |
4678 | case M_ADDU_I: | |
4679 | s = "addiu"; | |
4680 | s2 = "addu"; | |
4681 | goto do_addi; | |
4682 | case M_DADD_I: | |
4683 | dbl = 1; | |
4684 | s = "daddi"; | |
4685 | s2 = "dadd"; | |
4686 | goto do_addi; | |
4687 | case M_DADDU_I: | |
4688 | dbl = 1; | |
4689 | s = "daddiu"; | |
4690 | s2 = "daddu"; | |
4691 | do_addi: | |
4692 | if (imm_expr.X_op == O_constant | |
4693 | && imm_expr.X_add_number >= -0x8000 | |
4694 | && imm_expr.X_add_number < 0x8000) | |
4695 | { | |
67c0d1eb | 4696 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4697 | break; |
252b5132 | 4698 | } |
8fc2e39e | 4699 | used_at = 1; |
67c0d1eb RS |
4700 | load_register (AT, &imm_expr, dbl); |
4701 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4702 | break; |
4703 | ||
4704 | case M_AND_I: | |
4705 | s = "andi"; | |
4706 | s2 = "and"; | |
4707 | goto do_bit; | |
4708 | case M_OR_I: | |
4709 | s = "ori"; | |
4710 | s2 = "or"; | |
4711 | goto do_bit; | |
4712 | case M_NOR_I: | |
4713 | s = ""; | |
4714 | s2 = "nor"; | |
4715 | goto do_bit; | |
4716 | case M_XOR_I: | |
4717 | s = "xori"; | |
4718 | s2 = "xor"; | |
4719 | do_bit: | |
4720 | if (imm_expr.X_op == O_constant | |
4721 | && imm_expr.X_add_number >= 0 | |
4722 | && imm_expr.X_add_number < 0x10000) | |
4723 | { | |
4724 | if (mask != M_NOR_I) | |
67c0d1eb | 4725 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4726 | else |
4727 | { | |
67c0d1eb RS |
4728 | macro_build (&imm_expr, "ori", "t,r,i", |
4729 | treg, sreg, BFD_RELOC_LO16); | |
4730 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4731 | } |
8fc2e39e | 4732 | break; |
252b5132 RH |
4733 | } |
4734 | ||
8fc2e39e | 4735 | used_at = 1; |
67c0d1eb RS |
4736 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4737 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4738 | break; |
4739 | ||
8b082fb1 TS |
4740 | case M_BALIGN: |
4741 | switch (imm_expr.X_add_number) | |
4742 | { | |
4743 | case 0: | |
4744 | macro_build (NULL, "nop", ""); | |
4745 | break; | |
4746 | case 2: | |
4747 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4748 | break; | |
4749 | default: | |
4750 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
4751 | (int)imm_expr.X_add_number); | |
4752 | break; | |
4753 | } | |
4754 | break; | |
4755 | ||
252b5132 RH |
4756 | case M_BEQ_I: |
4757 | s = "beq"; | |
4758 | goto beq_i; | |
4759 | case M_BEQL_I: | |
4760 | s = "beql"; | |
4761 | likely = 1; | |
4762 | goto beq_i; | |
4763 | case M_BNE_I: | |
4764 | s = "bne"; | |
4765 | goto beq_i; | |
4766 | case M_BNEL_I: | |
4767 | s = "bnel"; | |
4768 | likely = 1; | |
4769 | beq_i: | |
4770 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4771 | { | |
67c0d1eb | 4772 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4773 | break; |
252b5132 | 4774 | } |
8fc2e39e | 4775 | used_at = 1; |
67c0d1eb RS |
4776 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4777 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4778 | break; |
4779 | ||
4780 | case M_BGEL: | |
4781 | likely = 1; | |
4782 | case M_BGE: | |
4783 | if (treg == 0) | |
4784 | { | |
67c0d1eb | 4785 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4786 | break; |
252b5132 RH |
4787 | } |
4788 | if (sreg == 0) | |
4789 | { | |
67c0d1eb | 4790 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4791 | break; |
252b5132 | 4792 | } |
8fc2e39e | 4793 | used_at = 1; |
67c0d1eb RS |
4794 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4795 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4796 | break; |
4797 | ||
4798 | case M_BGTL_I: | |
4799 | likely = 1; | |
4800 | case M_BGT_I: | |
4801 | /* check for > max integer */ | |
4802 | maxnum = 0x7fffffff; | |
ca4e0257 | 4803 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4804 | { |
4805 | maxnum <<= 16; | |
4806 | maxnum |= 0xffff; | |
4807 | maxnum <<= 16; | |
4808 | maxnum |= 0xffff; | |
4809 | } | |
4810 | if (imm_expr.X_op == O_constant | |
4811 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4812 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4813 | { |
4814 | do_false: | |
4815 | /* result is always false */ | |
4816 | if (! likely) | |
67c0d1eb | 4817 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4818 | else |
67c0d1eb | 4819 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4820 | break; |
252b5132 RH |
4821 | } |
4822 | if (imm_expr.X_op != O_constant) | |
4823 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4824 | ++imm_expr.X_add_number; |
252b5132 RH |
4825 | /* FALLTHROUGH */ |
4826 | case M_BGE_I: | |
4827 | case M_BGEL_I: | |
4828 | if (mask == M_BGEL_I) | |
4829 | likely = 1; | |
4830 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4831 | { | |
67c0d1eb | 4832 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4833 | break; |
252b5132 RH |
4834 | } |
4835 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4836 | { | |
67c0d1eb | 4837 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4838 | break; |
252b5132 RH |
4839 | } |
4840 | maxnum = 0x7fffffff; | |
ca4e0257 | 4841 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4842 | { |
4843 | maxnum <<= 16; | |
4844 | maxnum |= 0xffff; | |
4845 | maxnum <<= 16; | |
4846 | maxnum |= 0xffff; | |
4847 | } | |
4848 | maxnum = - maxnum - 1; | |
4849 | if (imm_expr.X_op == O_constant | |
4850 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4851 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4852 | { |
4853 | do_true: | |
4854 | /* result is always true */ | |
4855 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4856 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4857 | break; |
252b5132 | 4858 | } |
8fc2e39e | 4859 | used_at = 1; |
67c0d1eb RS |
4860 | set_at (sreg, 0); |
4861 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4862 | break; |
4863 | ||
4864 | case M_BGEUL: | |
4865 | likely = 1; | |
4866 | case M_BGEU: | |
4867 | if (treg == 0) | |
4868 | goto do_true; | |
4869 | if (sreg == 0) | |
4870 | { | |
67c0d1eb | 4871 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4872 | "s,t,p", 0, treg); |
8fc2e39e | 4873 | break; |
252b5132 | 4874 | } |
8fc2e39e | 4875 | used_at = 1; |
67c0d1eb RS |
4876 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4877 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4878 | break; |
4879 | ||
4880 | case M_BGTUL_I: | |
4881 | likely = 1; | |
4882 | case M_BGTU_I: | |
4883 | if (sreg == 0 | |
ca4e0257 | 4884 | || (HAVE_32BIT_GPRS |
252b5132 | 4885 | && imm_expr.X_op == O_constant |
956cd1d6 | 4886 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4887 | goto do_false; |
4888 | if (imm_expr.X_op != O_constant) | |
4889 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4890 | ++imm_expr.X_add_number; |
252b5132 RH |
4891 | /* FALLTHROUGH */ |
4892 | case M_BGEU_I: | |
4893 | case M_BGEUL_I: | |
4894 | if (mask == M_BGEUL_I) | |
4895 | likely = 1; | |
4896 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4897 | goto do_true; | |
4898 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4899 | { | |
67c0d1eb | 4900 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4901 | "s,t,p", sreg, 0); |
8fc2e39e | 4902 | break; |
252b5132 | 4903 | } |
8fc2e39e | 4904 | used_at = 1; |
67c0d1eb RS |
4905 | set_at (sreg, 1); |
4906 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4907 | break; |
4908 | ||
4909 | case M_BGTL: | |
4910 | likely = 1; | |
4911 | case M_BGT: | |
4912 | if (treg == 0) | |
4913 | { | |
67c0d1eb | 4914 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4915 | break; |
252b5132 RH |
4916 | } |
4917 | if (sreg == 0) | |
4918 | { | |
67c0d1eb | 4919 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4920 | break; |
252b5132 | 4921 | } |
8fc2e39e | 4922 | used_at = 1; |
67c0d1eb RS |
4923 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4924 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4925 | break; |
4926 | ||
4927 | case M_BGTUL: | |
4928 | likely = 1; | |
4929 | case M_BGTU: | |
4930 | if (treg == 0) | |
4931 | { | |
67c0d1eb | 4932 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4933 | "s,t,p", sreg, 0); |
8fc2e39e | 4934 | break; |
252b5132 RH |
4935 | } |
4936 | if (sreg == 0) | |
4937 | goto do_false; | |
8fc2e39e | 4938 | used_at = 1; |
67c0d1eb RS |
4939 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4940 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4941 | break; |
4942 | ||
4943 | case M_BLEL: | |
4944 | likely = 1; | |
4945 | case M_BLE: | |
4946 | if (treg == 0) | |
4947 | { | |
67c0d1eb | 4948 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4949 | break; |
252b5132 RH |
4950 | } |
4951 | if (sreg == 0) | |
4952 | { | |
67c0d1eb | 4953 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4954 | break; |
252b5132 | 4955 | } |
8fc2e39e | 4956 | used_at = 1; |
67c0d1eb RS |
4957 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4958 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4959 | break; |
4960 | ||
4961 | case M_BLEL_I: | |
4962 | likely = 1; | |
4963 | case M_BLE_I: | |
4964 | maxnum = 0x7fffffff; | |
ca4e0257 | 4965 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4966 | { |
4967 | maxnum <<= 16; | |
4968 | maxnum |= 0xffff; | |
4969 | maxnum <<= 16; | |
4970 | maxnum |= 0xffff; | |
4971 | } | |
4972 | if (imm_expr.X_op == O_constant | |
4973 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4974 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4975 | goto do_true; |
4976 | if (imm_expr.X_op != O_constant) | |
4977 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4978 | ++imm_expr.X_add_number; |
252b5132 RH |
4979 | /* FALLTHROUGH */ |
4980 | case M_BLT_I: | |
4981 | case M_BLTL_I: | |
4982 | if (mask == M_BLTL_I) | |
4983 | likely = 1; | |
4984 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4985 | { | |
67c0d1eb | 4986 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4987 | break; |
252b5132 RH |
4988 | } |
4989 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4990 | { | |
67c0d1eb | 4991 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4992 | break; |
252b5132 | 4993 | } |
8fc2e39e | 4994 | used_at = 1; |
67c0d1eb RS |
4995 | set_at (sreg, 0); |
4996 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4997 | break; |
4998 | ||
4999 | case M_BLEUL: | |
5000 | likely = 1; | |
5001 | case M_BLEU: | |
5002 | if (treg == 0) | |
5003 | { | |
67c0d1eb | 5004 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 5005 | "s,t,p", sreg, 0); |
8fc2e39e | 5006 | break; |
252b5132 RH |
5007 | } |
5008 | if (sreg == 0) | |
5009 | goto do_true; | |
8fc2e39e | 5010 | used_at = 1; |
67c0d1eb RS |
5011 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
5012 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5013 | break; |
5014 | ||
5015 | case M_BLEUL_I: | |
5016 | likely = 1; | |
5017 | case M_BLEU_I: | |
5018 | if (sreg == 0 | |
ca4e0257 | 5019 | || (HAVE_32BIT_GPRS |
252b5132 | 5020 | && imm_expr.X_op == O_constant |
956cd1d6 | 5021 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
5022 | goto do_true; |
5023 | if (imm_expr.X_op != O_constant) | |
5024 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5025 | ++imm_expr.X_add_number; |
252b5132 RH |
5026 | /* FALLTHROUGH */ |
5027 | case M_BLTU_I: | |
5028 | case M_BLTUL_I: | |
5029 | if (mask == M_BLTUL_I) | |
5030 | likely = 1; | |
5031 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5032 | goto do_false; | |
5033 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5034 | { | |
67c0d1eb | 5035 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 5036 | "s,t,p", sreg, 0); |
8fc2e39e | 5037 | break; |
252b5132 | 5038 | } |
8fc2e39e | 5039 | used_at = 1; |
67c0d1eb RS |
5040 | set_at (sreg, 1); |
5041 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5042 | break; |
5043 | ||
5044 | case M_BLTL: | |
5045 | likely = 1; | |
5046 | case M_BLT: | |
5047 | if (treg == 0) | |
5048 | { | |
67c0d1eb | 5049 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5050 | break; |
252b5132 RH |
5051 | } |
5052 | if (sreg == 0) | |
5053 | { | |
67c0d1eb | 5054 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5055 | break; |
252b5132 | 5056 | } |
8fc2e39e | 5057 | used_at = 1; |
67c0d1eb RS |
5058 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
5059 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5060 | break; |
5061 | ||
5062 | case M_BLTUL: | |
5063 | likely = 1; | |
5064 | case M_BLTU: | |
5065 | if (treg == 0) | |
5066 | goto do_false; | |
5067 | if (sreg == 0) | |
5068 | { | |
67c0d1eb | 5069 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5070 | "s,t,p", 0, treg); |
8fc2e39e | 5071 | break; |
252b5132 | 5072 | } |
8fc2e39e | 5073 | used_at = 1; |
67c0d1eb RS |
5074 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
5075 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5076 | break; |
5077 | ||
5f74bc13 CD |
5078 | case M_DEXT: |
5079 | { | |
5080 | unsigned long pos; | |
5081 | unsigned long size; | |
5082 | ||
5083 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5084 | { | |
5085 | as_bad (_("Unsupported large constant")); | |
5086 | pos = size = 1; | |
5087 | } | |
5088 | else | |
5089 | { | |
5090 | pos = (unsigned long) imm_expr.X_add_number; | |
5091 | size = (unsigned long) imm2_expr.X_add_number; | |
5092 | } | |
5093 | ||
5094 | if (pos > 63) | |
5095 | { | |
5096 | as_bad (_("Improper position (%lu)"), pos); | |
5097 | pos = 1; | |
5098 | } | |
5099 | if (size == 0 || size > 64 | |
5100 | || (pos + size - 1) > 63) | |
5101 | { | |
5102 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
5103 | size, pos); | |
5104 | size = 1; | |
5105 | } | |
5106 | ||
5107 | if (size <= 32 && pos < 32) | |
5108 | { | |
5109 | s = "dext"; | |
5110 | fmt = "t,r,+A,+C"; | |
5111 | } | |
5112 | else if (size <= 32) | |
5113 | { | |
5114 | s = "dextu"; | |
5115 | fmt = "t,r,+E,+H"; | |
5116 | } | |
5117 | else | |
5118 | { | |
5119 | s = "dextm"; | |
5120 | fmt = "t,r,+A,+G"; | |
5121 | } | |
67c0d1eb | 5122 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 5123 | } |
8fc2e39e | 5124 | break; |
5f74bc13 CD |
5125 | |
5126 | case M_DINS: | |
5127 | { | |
5128 | unsigned long pos; | |
5129 | unsigned long size; | |
5130 | ||
5131 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5132 | { | |
5133 | as_bad (_("Unsupported large constant")); | |
5134 | pos = size = 1; | |
5135 | } | |
5136 | else | |
5137 | { | |
5138 | pos = (unsigned long) imm_expr.X_add_number; | |
5139 | size = (unsigned long) imm2_expr.X_add_number; | |
5140 | } | |
5141 | ||
5142 | if (pos > 63) | |
5143 | { | |
5144 | as_bad (_("Improper position (%lu)"), pos); | |
5145 | pos = 1; | |
5146 | } | |
5147 | if (size == 0 || size > 64 | |
5148 | || (pos + size - 1) > 63) | |
5149 | { | |
5150 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
5151 | size, pos); | |
5152 | size = 1; | |
5153 | } | |
5154 | ||
5155 | if (pos < 32 && (pos + size - 1) < 32) | |
5156 | { | |
5157 | s = "dins"; | |
5158 | fmt = "t,r,+A,+B"; | |
5159 | } | |
5160 | else if (pos >= 32) | |
5161 | { | |
5162 | s = "dinsu"; | |
5163 | fmt = "t,r,+E,+F"; | |
5164 | } | |
5165 | else | |
5166 | { | |
5167 | s = "dinsm"; | |
5168 | fmt = "t,r,+A,+F"; | |
5169 | } | |
67c0d1eb RS |
5170 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
5171 | pos + size - 1); | |
5f74bc13 | 5172 | } |
8fc2e39e | 5173 | break; |
5f74bc13 | 5174 | |
252b5132 RH |
5175 | case M_DDIV_3: |
5176 | dbl = 1; | |
5177 | case M_DIV_3: | |
5178 | s = "mflo"; | |
5179 | goto do_div3; | |
5180 | case M_DREM_3: | |
5181 | dbl = 1; | |
5182 | case M_REM_3: | |
5183 | s = "mfhi"; | |
5184 | do_div3: | |
5185 | if (treg == 0) | |
5186 | { | |
5187 | as_warn (_("Divide by zero.")); | |
5188 | if (mips_trap) | |
67c0d1eb | 5189 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5190 | else |
67c0d1eb | 5191 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5192 | break; |
252b5132 RH |
5193 | } |
5194 | ||
7d10b47d | 5195 | start_noreorder (); |
252b5132 RH |
5196 | if (mips_trap) |
5197 | { | |
67c0d1eb RS |
5198 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5199 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5200 | } |
5201 | else | |
5202 | { | |
5203 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5204 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5205 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5206 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5207 | } |
5208 | expr1.X_add_number = -1; | |
8fc2e39e | 5209 | used_at = 1; |
f6a22291 | 5210 | load_register (AT, &expr1, dbl); |
252b5132 | 5211 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5212 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5213 | if (dbl) |
5214 | { | |
5215 | expr1.X_add_number = 1; | |
f6a22291 | 5216 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5217 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5218 | } |
5219 | else | |
5220 | { | |
5221 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5222 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5223 | } |
5224 | if (mips_trap) | |
5225 | { | |
67c0d1eb | 5226 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5227 | /* We want to close the noreorder block as soon as possible, so |
5228 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5229 | end_noreorder (); |
252b5132 RH |
5230 | } |
5231 | else | |
5232 | { | |
5233 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5234 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5235 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5236 | |
5237 | /* We want to close the noreorder block as soon as possible, so | |
5238 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5239 | end_noreorder (); |
252b5132 | 5240 | |
67c0d1eb | 5241 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5242 | } |
67c0d1eb | 5243 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5244 | break; |
5245 | ||
5246 | case M_DIV_3I: | |
5247 | s = "div"; | |
5248 | s2 = "mflo"; | |
5249 | goto do_divi; | |
5250 | case M_DIVU_3I: | |
5251 | s = "divu"; | |
5252 | s2 = "mflo"; | |
5253 | goto do_divi; | |
5254 | case M_REM_3I: | |
5255 | s = "div"; | |
5256 | s2 = "mfhi"; | |
5257 | goto do_divi; | |
5258 | case M_REMU_3I: | |
5259 | s = "divu"; | |
5260 | s2 = "mfhi"; | |
5261 | goto do_divi; | |
5262 | case M_DDIV_3I: | |
5263 | dbl = 1; | |
5264 | s = "ddiv"; | |
5265 | s2 = "mflo"; | |
5266 | goto do_divi; | |
5267 | case M_DDIVU_3I: | |
5268 | dbl = 1; | |
5269 | s = "ddivu"; | |
5270 | s2 = "mflo"; | |
5271 | goto do_divi; | |
5272 | case M_DREM_3I: | |
5273 | dbl = 1; | |
5274 | s = "ddiv"; | |
5275 | s2 = "mfhi"; | |
5276 | goto do_divi; | |
5277 | case M_DREMU_3I: | |
5278 | dbl = 1; | |
5279 | s = "ddivu"; | |
5280 | s2 = "mfhi"; | |
5281 | do_divi: | |
5282 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5283 | { | |
5284 | as_warn (_("Divide by zero.")); | |
5285 | if (mips_trap) | |
67c0d1eb | 5286 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5287 | else |
67c0d1eb | 5288 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5289 | break; |
252b5132 RH |
5290 | } |
5291 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5292 | { | |
5293 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5294 | move_register (dreg, sreg); |
252b5132 | 5295 | else |
67c0d1eb | 5296 | move_register (dreg, 0); |
8fc2e39e | 5297 | break; |
252b5132 RH |
5298 | } |
5299 | if (imm_expr.X_op == O_constant | |
5300 | && imm_expr.X_add_number == -1 | |
5301 | && s[strlen (s) - 1] != 'u') | |
5302 | { | |
5303 | if (strcmp (s2, "mflo") == 0) | |
5304 | { | |
67c0d1eb | 5305 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5306 | } |
5307 | else | |
67c0d1eb | 5308 | move_register (dreg, 0); |
8fc2e39e | 5309 | break; |
252b5132 RH |
5310 | } |
5311 | ||
8fc2e39e | 5312 | used_at = 1; |
67c0d1eb RS |
5313 | load_register (AT, &imm_expr, dbl); |
5314 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5315 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5316 | break; |
5317 | ||
5318 | case M_DIVU_3: | |
5319 | s = "divu"; | |
5320 | s2 = "mflo"; | |
5321 | goto do_divu3; | |
5322 | case M_REMU_3: | |
5323 | s = "divu"; | |
5324 | s2 = "mfhi"; | |
5325 | goto do_divu3; | |
5326 | case M_DDIVU_3: | |
5327 | s = "ddivu"; | |
5328 | s2 = "mflo"; | |
5329 | goto do_divu3; | |
5330 | case M_DREMU_3: | |
5331 | s = "ddivu"; | |
5332 | s2 = "mfhi"; | |
5333 | do_divu3: | |
7d10b47d | 5334 | start_noreorder (); |
252b5132 RH |
5335 | if (mips_trap) |
5336 | { | |
67c0d1eb RS |
5337 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5338 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5339 | /* We want to close the noreorder block as soon as possible, so |
5340 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5341 | end_noreorder (); |
252b5132 RH |
5342 | } |
5343 | else | |
5344 | { | |
5345 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5346 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5347 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5348 | |
5349 | /* We want to close the noreorder block as soon as possible, so | |
5350 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5351 | end_noreorder (); |
67c0d1eb | 5352 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5353 | } |
67c0d1eb | 5354 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5355 | break; |
252b5132 | 5356 | |
1abe91b1 MR |
5357 | case M_DLCA_AB: |
5358 | dbl = 1; | |
5359 | case M_LCA_AB: | |
5360 | call = 1; | |
5361 | goto do_la; | |
252b5132 RH |
5362 | case M_DLA_AB: |
5363 | dbl = 1; | |
5364 | case M_LA_AB: | |
1abe91b1 | 5365 | do_la: |
252b5132 RH |
5366 | /* Load the address of a symbol into a register. If breg is not |
5367 | zero, we then add a base register to it. */ | |
5368 | ||
3bec30a8 TS |
5369 | if (dbl && HAVE_32BIT_GPRS) |
5370 | as_warn (_("dla used to load 32-bit register")); | |
5371 | ||
c90bbe5b | 5372 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5373 | as_warn (_("la used to load 64-bit address")); |
5374 | ||
0c11417f MR |
5375 | if (offset_expr.X_op == O_constant |
5376 | && offset_expr.X_add_number >= -0x8000 | |
5377 | && offset_expr.X_add_number < 0x8000) | |
5378 | { | |
aed1a261 | 5379 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5380 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5381 | break; |
0c11417f MR |
5382 | } |
5383 | ||
741fe287 | 5384 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5385 | { |
5386 | tempreg = AT; | |
5387 | used_at = 1; | |
5388 | } | |
5389 | else | |
5390 | { | |
5391 | tempreg = treg; | |
afdbd6d0 CD |
5392 | } |
5393 | ||
252b5132 RH |
5394 | if (offset_expr.X_op != O_symbol |
5395 | && offset_expr.X_op != O_constant) | |
5396 | { | |
5397 | as_bad (_("expression too complex")); | |
5398 | offset_expr.X_op = O_constant; | |
5399 | } | |
5400 | ||
252b5132 | 5401 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5402 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5403 | else if (mips_pic == NO_PIC) |
5404 | { | |
d6bc6245 | 5405 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5406 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5407 | Otherwise we want |
5408 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5409 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5410 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5411 | so we may as well always use the latter form. |
76b3015f | 5412 | |
6caf9ef4 TS |
5413 | With 64bit address space and a usable $at we want |
5414 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5415 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5416 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5417 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5418 | dsll32 $tempreg,0 | |
5419 | daddu $tempreg,$tempreg,$at | |
5420 | ||
5421 | If $at is already in use, we use a path which is suboptimal | |
5422 | on superscalar processors. | |
5423 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5424 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5425 | dsll $tempreg,16 | |
5426 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5427 | dsll $tempreg,16 | |
5428 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5429 | ||
5430 | For GP relative symbols in 64bit address space we can use | |
5431 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5432 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5433 | { |
6caf9ef4 TS |
5434 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5435 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5436 | { | |
5437 | relax_start (offset_expr.X_add_symbol); | |
5438 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5439 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5440 | relax_switch (); | |
5441 | } | |
d6bc6245 | 5442 | |
741fe287 | 5443 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5444 | { |
67c0d1eb | 5445 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5446 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5447 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5448 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5449 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5450 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5451 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5452 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5453 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5454 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5455 | used_at = 1; |
5456 | } | |
5457 | else | |
5458 | { | |
67c0d1eb | 5459 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5460 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5461 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5462 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5463 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5464 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5465 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5466 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5467 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5468 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5469 | } |
6caf9ef4 TS |
5470 | |
5471 | if (mips_relax.sequence) | |
5472 | relax_end (); | |
98d3f06f KH |
5473 | } |
5474 | else | |
5475 | { | |
5476 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5477 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5478 | { |
4d7206a2 | 5479 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5480 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5481 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5482 | relax_switch (); |
98d3f06f | 5483 | } |
6943caf0 ILT |
5484 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5485 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5486 | macro_build_lui (&offset_expr, tempreg); |
5487 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5488 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5489 | if (mips_relax.sequence) |
5490 | relax_end (); | |
98d3f06f | 5491 | } |
252b5132 | 5492 | } |
0a44bf69 | 5493 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5494 | { |
9117d219 NC |
5495 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5496 | ||
252b5132 RH |
5497 | /* If this is a reference to an external symbol, and there |
5498 | is no constant, we want | |
5499 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5500 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5501 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5502 | For a local symbol, we want |
5503 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5504 | nop | |
5505 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5506 | ||
5507 | If we have a small constant, and this is a reference to | |
5508 | an external symbol, we want | |
5509 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5510 | nop | |
5511 | addiu $tempreg,$tempreg,<constant> | |
5512 | For a local symbol, we want the same instruction | |
5513 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5514 | addiu instruction. | |
5515 | ||
5516 | If we have a large constant, and this is a reference to | |
5517 | an external symbol, we want | |
5518 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5519 | lui $at,<hiconstant> | |
5520 | addiu $at,$at,<loconstant> | |
5521 | addu $tempreg,$tempreg,$at | |
5522 | For a local symbol, we want the same instruction | |
5523 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5524 | addiu instruction. |
ed6fb7bd SC |
5525 | */ |
5526 | ||
4d7206a2 | 5527 | if (offset_expr.X_add_number == 0) |
252b5132 | 5528 | { |
0a44bf69 RS |
5529 | if (mips_pic == SVR4_PIC |
5530 | && breg == 0 | |
5531 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5532 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5533 | ||
5534 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5535 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5536 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5537 | if (breg != 0) |
252b5132 RH |
5538 | { |
5539 | /* We're going to put in an addu instruction using | |
5540 | tempreg, so we may as well insert the nop right | |
5541 | now. */ | |
269137b2 | 5542 | load_delay_nop (); |
252b5132 | 5543 | } |
4d7206a2 | 5544 | relax_switch (); |
67c0d1eb RS |
5545 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5546 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5547 | load_delay_nop (); |
67c0d1eb RS |
5548 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5549 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5550 | relax_end (); |
252b5132 RH |
5551 | /* FIXME: If breg == 0, and the next instruction uses |
5552 | $tempreg, then if this variant case is used an extra | |
5553 | nop will be generated. */ | |
5554 | } | |
4d7206a2 RS |
5555 | else if (offset_expr.X_add_number >= -0x8000 |
5556 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5557 | { |
67c0d1eb | 5558 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5559 | load_delay_nop (); |
67c0d1eb | 5560 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5561 | } |
5562 | else | |
5563 | { | |
4d7206a2 RS |
5564 | expr1.X_add_number = offset_expr.X_add_number; |
5565 | offset_expr.X_add_number = | |
5566 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5567 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5568 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5569 | /* If we are going to add in a base register, and the |
5570 | target register and the base register are the same, | |
5571 | then we are using AT as a temporary register. Since | |
5572 | we want to load the constant into AT, we add our | |
5573 | current AT (from the global offset table) and the | |
5574 | register into the register now, and pretend we were | |
5575 | not using a base register. */ | |
67c0d1eb | 5576 | if (breg == treg) |
252b5132 | 5577 | { |
269137b2 | 5578 | load_delay_nop (); |
67c0d1eb | 5579 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5580 | treg, AT, breg); |
252b5132 RH |
5581 | breg = 0; |
5582 | tempreg = treg; | |
252b5132 | 5583 | } |
f6a22291 | 5584 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5585 | used_at = 1; |
5586 | } | |
5587 | } | |
0a44bf69 | 5588 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5589 | { |
67c0d1eb | 5590 | int add_breg_early = 0; |
f5040a92 AO |
5591 | |
5592 | /* If this is a reference to an external, and there is no | |
5593 | constant, or local symbol (*), with or without a | |
5594 | constant, we want | |
5595 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5596 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5597 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5598 | ||
5599 | If we have a small constant, and this is a reference to | |
5600 | an external symbol, we want | |
5601 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5602 | addiu $tempreg,$tempreg,<constant> | |
5603 | ||
5604 | If we have a large constant, and this is a reference to | |
5605 | an external symbol, we want | |
5606 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5607 | lui $at,<hiconstant> | |
5608 | addiu $at,$at,<loconstant> | |
5609 | addu $tempreg,$tempreg,$at | |
5610 | ||
5611 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5612 | local symbols, even though it introduces an additional | |
5613 | instruction. */ | |
5614 | ||
f5040a92 AO |
5615 | if (offset_expr.X_add_number) |
5616 | { | |
4d7206a2 | 5617 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5618 | offset_expr.X_add_number = 0; |
5619 | ||
4d7206a2 | 5620 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5621 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5622 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5623 | |
5624 | if (expr1.X_add_number >= -0x8000 | |
5625 | && expr1.X_add_number < 0x8000) | |
5626 | { | |
67c0d1eb RS |
5627 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5628 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5629 | } |
ecd13cd3 | 5630 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5631 | { |
5632 | int dreg; | |
5633 | ||
5634 | /* If we are going to add in a base register, and the | |
5635 | target register and the base register are the same, | |
5636 | then we are using AT as a temporary register. Since | |
5637 | we want to load the constant into AT, we add our | |
5638 | current AT (from the global offset table) and the | |
5639 | register into the register now, and pretend we were | |
5640 | not using a base register. */ | |
5641 | if (breg != treg) | |
5642 | dreg = tempreg; | |
5643 | else | |
5644 | { | |
5645 | assert (tempreg == AT); | |
67c0d1eb RS |
5646 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5647 | treg, AT, breg); | |
f5040a92 | 5648 | dreg = treg; |
67c0d1eb | 5649 | add_breg_early = 1; |
f5040a92 AO |
5650 | } |
5651 | ||
f6a22291 | 5652 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5653 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5654 | dreg, dreg, AT); |
f5040a92 | 5655 | |
f5040a92 AO |
5656 | used_at = 1; |
5657 | } | |
5658 | else | |
5659 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5660 | ||
4d7206a2 | 5661 | relax_switch (); |
f5040a92 AO |
5662 | offset_expr.X_add_number = expr1.X_add_number; |
5663 | ||
67c0d1eb RS |
5664 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5665 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5666 | if (add_breg_early) | |
f5040a92 | 5667 | { |
67c0d1eb | 5668 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5669 | treg, tempreg, breg); |
f5040a92 AO |
5670 | breg = 0; |
5671 | tempreg = treg; | |
5672 | } | |
4d7206a2 | 5673 | relax_end (); |
f5040a92 | 5674 | } |
4d7206a2 | 5675 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5676 | { |
4d7206a2 | 5677 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5678 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5679 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5680 | relax_switch (); |
67c0d1eb RS |
5681 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5682 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5683 | relax_end (); |
f5040a92 | 5684 | } |
4d7206a2 | 5685 | else |
f5040a92 | 5686 | { |
67c0d1eb RS |
5687 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5688 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5689 | } |
5690 | } | |
0a44bf69 | 5691 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5692 | { |
67c0d1eb | 5693 | int gpdelay; |
9117d219 NC |
5694 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5695 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5696 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5697 | |
5698 | /* This is the large GOT case. If this is a reference to an | |
5699 | external symbol, and there is no constant, we want | |
5700 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5701 | addu $tempreg,$tempreg,$gp | |
5702 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5703 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5704 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5705 | addu $tempreg,$tempreg,$gp | |
5706 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5707 | For a local symbol, we want |
5708 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5709 | nop | |
5710 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5711 | ||
5712 | If we have a small constant, and this is a reference to | |
5713 | an external symbol, we want | |
5714 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5715 | addu $tempreg,$tempreg,$gp | |
5716 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5717 | nop | |
5718 | addiu $tempreg,$tempreg,<constant> | |
5719 | For a local symbol, we want | |
5720 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5721 | nop | |
5722 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5723 | ||
5724 | If we have a large constant, and this is a reference to | |
5725 | an external symbol, we want | |
5726 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5727 | addu $tempreg,$tempreg,$gp | |
5728 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5729 | lui $at,<hiconstant> | |
5730 | addiu $at,$at,<loconstant> | |
5731 | addu $tempreg,$tempreg,$at | |
5732 | For a local symbol, we want | |
5733 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5734 | lui $at,<hiconstant> | |
5735 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5736 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5737 | */ |
438c16b8 | 5738 | |
252b5132 RH |
5739 | expr1.X_add_number = offset_expr.X_add_number; |
5740 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5741 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5742 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5743 | if (expr1.X_add_number == 0 && breg == 0 |
5744 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5745 | { |
5746 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5747 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5748 | } | |
67c0d1eb RS |
5749 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5750 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5751 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5752 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5753 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5754 | if (expr1.X_add_number == 0) |
5755 | { | |
67c0d1eb | 5756 | if (breg != 0) |
252b5132 RH |
5757 | { |
5758 | /* We're going to put in an addu instruction using | |
5759 | tempreg, so we may as well insert the nop right | |
5760 | now. */ | |
269137b2 | 5761 | load_delay_nop (); |
252b5132 | 5762 | } |
252b5132 RH |
5763 | } |
5764 | else if (expr1.X_add_number >= -0x8000 | |
5765 | && expr1.X_add_number < 0x8000) | |
5766 | { | |
269137b2 | 5767 | load_delay_nop (); |
67c0d1eb | 5768 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5769 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5770 | } |
5771 | else | |
5772 | { | |
67c0d1eb | 5773 | int dreg; |
252b5132 RH |
5774 | |
5775 | /* If we are going to add in a base register, and the | |
5776 | target register and the base register are the same, | |
5777 | then we are using AT as a temporary register. Since | |
5778 | we want to load the constant into AT, we add our | |
5779 | current AT (from the global offset table) and the | |
5780 | register into the register now, and pretend we were | |
5781 | not using a base register. */ | |
5782 | if (breg != treg) | |
67c0d1eb | 5783 | dreg = tempreg; |
252b5132 RH |
5784 | else |
5785 | { | |
5786 | assert (tempreg == AT); | |
269137b2 | 5787 | load_delay_nop (); |
67c0d1eb | 5788 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5789 | treg, AT, breg); |
252b5132 | 5790 | dreg = treg; |
252b5132 RH |
5791 | } |
5792 | ||
f6a22291 | 5793 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5794 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5795 | |
252b5132 RH |
5796 | used_at = 1; |
5797 | } | |
4d7206a2 RS |
5798 | offset_expr.X_add_number = |
5799 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5800 | relax_switch (); | |
252b5132 | 5801 | |
67c0d1eb | 5802 | if (gpdelay) |
252b5132 RH |
5803 | { |
5804 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5805 | the first instruction on the main stream does not. */ |
67c0d1eb | 5806 | macro_build (NULL, "nop", ""); |
252b5132 | 5807 | } |
ed6fb7bd | 5808 | |
67c0d1eb RS |
5809 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5810 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5811 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5812 | && expr1.X_add_number < 0x8000) |
5813 | { | |
269137b2 | 5814 | load_delay_nop (); |
67c0d1eb RS |
5815 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5816 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5817 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5818 | register, the external symbol case ended with a load, |
5819 | so if the symbol turns out to not be external, and | |
5820 | the next instruction uses tempreg, an unnecessary nop | |
5821 | will be inserted. */ | |
252b5132 RH |
5822 | } |
5823 | else | |
5824 | { | |
5825 | if (breg == treg) | |
5826 | { | |
5827 | /* We must add in the base register now, as in the | |
f5040a92 | 5828 | external symbol case. */ |
252b5132 | 5829 | assert (tempreg == AT); |
269137b2 | 5830 | load_delay_nop (); |
67c0d1eb | 5831 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5832 | treg, AT, breg); |
252b5132 RH |
5833 | tempreg = treg; |
5834 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5835 | it in in both cases. */ |
252b5132 RH |
5836 | breg = 0; |
5837 | } | |
5838 | ||
67c0d1eb RS |
5839 | macro_build_lui (&expr1, AT); |
5840 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5841 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5842 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5843 | tempreg, tempreg, AT); |
8fc2e39e | 5844 | used_at = 1; |
252b5132 | 5845 | } |
4d7206a2 | 5846 | relax_end (); |
252b5132 | 5847 | } |
0a44bf69 | 5848 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5849 | { |
f5040a92 AO |
5850 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5851 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5852 | int add_breg_early = 0; |
f5040a92 AO |
5853 | |
5854 | /* This is the large GOT case. If this is a reference to an | |
5855 | external symbol, and there is no constant, we want | |
5856 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5857 | add $tempreg,$tempreg,$gp | |
5858 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5859 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5860 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5861 | add $tempreg,$tempreg,$gp | |
5862 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5863 | ||
5864 | If we have a small constant, and this is a reference to | |
5865 | an external symbol, we want | |
5866 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5867 | add $tempreg,$tempreg,$gp | |
5868 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5869 | addi $tempreg,$tempreg,<constant> | |
5870 | ||
5871 | If we have a large constant, and this is a reference to | |
5872 | an external symbol, we want | |
5873 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5874 | addu $tempreg,$tempreg,$gp | |
5875 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5876 | lui $at,<hiconstant> | |
5877 | addi $at,$at,<loconstant> | |
5878 | add $tempreg,$tempreg,$at | |
5879 | ||
5880 | If we have NewABI, and we know it's a local symbol, we want | |
5881 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5882 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5883 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5884 | ||
4d7206a2 | 5885 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5886 | |
4d7206a2 | 5887 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5888 | offset_expr.X_add_number = 0; |
5889 | ||
1abe91b1 MR |
5890 | if (expr1.X_add_number == 0 && breg == 0 |
5891 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5892 | { |
5893 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5894 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5895 | } | |
67c0d1eb RS |
5896 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5897 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5898 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5899 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5900 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5901 | |
5902 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5903 | ; |
f5040a92 AO |
5904 | else if (expr1.X_add_number >= -0x8000 |
5905 | && expr1.X_add_number < 0x8000) | |
5906 | { | |
67c0d1eb | 5907 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5908 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5909 | } |
ecd13cd3 | 5910 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5911 | { |
5912 | int dreg; | |
5913 | ||
5914 | /* If we are going to add in a base register, and the | |
5915 | target register and the base register are the same, | |
5916 | then we are using AT as a temporary register. Since | |
5917 | we want to load the constant into AT, we add our | |
5918 | current AT (from the global offset table) and the | |
5919 | register into the register now, and pretend we were | |
5920 | not using a base register. */ | |
5921 | if (breg != treg) | |
5922 | dreg = tempreg; | |
5923 | else | |
5924 | { | |
5925 | assert (tempreg == AT); | |
67c0d1eb | 5926 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5927 | treg, AT, breg); |
f5040a92 | 5928 | dreg = treg; |
67c0d1eb | 5929 | add_breg_early = 1; |
f5040a92 AO |
5930 | } |
5931 | ||
f6a22291 | 5932 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5933 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5934 | |
f5040a92 AO |
5935 | used_at = 1; |
5936 | } | |
5937 | else | |
5938 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5939 | ||
4d7206a2 | 5940 | relax_switch (); |
f5040a92 | 5941 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5942 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5943 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5944 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5945 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5946 | if (add_breg_early) | |
f5040a92 | 5947 | { |
67c0d1eb | 5948 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5949 | treg, tempreg, breg); |
f5040a92 AO |
5950 | breg = 0; |
5951 | tempreg = treg; | |
5952 | } | |
4d7206a2 | 5953 | relax_end (); |
f5040a92 | 5954 | } |
252b5132 RH |
5955 | else |
5956 | abort (); | |
5957 | ||
5958 | if (breg != 0) | |
aed1a261 | 5959 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5960 | break; |
5961 | ||
5962 | case M_J_A: | |
5963 | /* The j instruction may not be used in PIC code, since it | |
5964 | requires an absolute address. We convert it to a b | |
5965 | instruction. */ | |
5966 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5967 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5968 | else |
67c0d1eb | 5969 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5970 | break; |
252b5132 RH |
5971 | |
5972 | /* The jal instructions must be handled as macros because when | |
5973 | generating PIC code they expand to multi-instruction | |
5974 | sequences. Normally they are simple instructions. */ | |
5975 | case M_JAL_1: | |
5976 | dreg = RA; | |
5977 | /* Fall through. */ | |
5978 | case M_JAL_2: | |
3e722fb5 | 5979 | if (mips_pic == NO_PIC) |
67c0d1eb | 5980 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5981 | else |
252b5132 RH |
5982 | { |
5983 | if (sreg != PIC_CALL_REG) | |
5984 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5985 | |
67c0d1eb | 5986 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5987 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5988 | { |
6478892d TS |
5989 | if (mips_cprestore_offset < 0) |
5990 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5991 | else | |
5992 | { | |
7a621144 DJ |
5993 | if (! mips_frame_reg_valid) |
5994 | { | |
5995 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5996 | /* Quiet this warning. */ | |
5997 | mips_frame_reg_valid = 1; | |
5998 | } | |
5999 | if (! mips_cprestore_valid) | |
6000 | { | |
6001 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6002 | /* Quiet this warning. */ | |
6003 | mips_cprestore_valid = 1; | |
6004 | } | |
6478892d | 6005 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6006 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6007 | mips_gp_register, |
256ab948 TS |
6008 | mips_frame_reg, |
6009 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6010 | } |
252b5132 RH |
6011 | } |
6012 | } | |
252b5132 | 6013 | |
8fc2e39e | 6014 | break; |
252b5132 RH |
6015 | |
6016 | case M_JAL_A: | |
6017 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6018 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6019 | else if (mips_pic == SVR4_PIC) |
6020 | { | |
6021 | /* If this is a reference to an external symbol, and we are | |
6022 | using a small GOT, we want | |
6023 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6024 | nop | |
f9419b05 | 6025 | jalr $ra,$25 |
252b5132 RH |
6026 | nop |
6027 | lw $gp,cprestore($sp) | |
6028 | The cprestore value is set using the .cprestore | |
6029 | pseudo-op. If we are using a big GOT, we want | |
6030 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6031 | addu $25,$25,$gp | |
6032 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6033 | nop | |
f9419b05 | 6034 | jalr $ra,$25 |
252b5132 RH |
6035 | nop |
6036 | lw $gp,cprestore($sp) | |
6037 | If the symbol is not external, we want | |
6038 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6039 | nop | |
6040 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6041 | jalr $ra,$25 |
252b5132 | 6042 | nop |
438c16b8 | 6043 | lw $gp,cprestore($sp) |
f5040a92 AO |
6044 | |
6045 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6046 | sequences above, minus nops, unless the symbol is local, | |
6047 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6048 | GOT_DISP. */ | |
438c16b8 | 6049 | if (HAVE_NEWABI) |
252b5132 | 6050 | { |
f5040a92 AO |
6051 | if (! mips_big_got) |
6052 | { | |
4d7206a2 | 6053 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6054 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6055 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6056 | mips_gp_register); |
4d7206a2 | 6057 | relax_switch (); |
67c0d1eb RS |
6058 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6059 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6060 | mips_gp_register); |
6061 | relax_end (); | |
f5040a92 AO |
6062 | } |
6063 | else | |
6064 | { | |
4d7206a2 | 6065 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6066 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6067 | BFD_RELOC_MIPS_CALL_HI16); | |
6068 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6069 | PIC_CALL_REG, mips_gp_register); | |
6070 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6071 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6072 | PIC_CALL_REG); | |
4d7206a2 | 6073 | relax_switch (); |
67c0d1eb RS |
6074 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6075 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6076 | mips_gp_register); | |
6077 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6078 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6079 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6080 | relax_end (); |
f5040a92 | 6081 | } |
684022ea | 6082 | |
67c0d1eb | 6083 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6084 | } |
6085 | else | |
6086 | { | |
4d7206a2 | 6087 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
6088 | if (! mips_big_got) |
6089 | { | |
67c0d1eb RS |
6090 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6091 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6092 | mips_gp_register); |
269137b2 | 6093 | load_delay_nop (); |
4d7206a2 | 6094 | relax_switch (); |
438c16b8 | 6095 | } |
252b5132 | 6096 | else |
252b5132 | 6097 | { |
67c0d1eb RS |
6098 | int gpdelay; |
6099 | ||
6100 | gpdelay = reg_needs_delay (mips_gp_register); | |
6101 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6102 | BFD_RELOC_MIPS_CALL_HI16); | |
6103 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6104 | PIC_CALL_REG, mips_gp_register); | |
6105 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6106 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6107 | PIC_CALL_REG); | |
269137b2 | 6108 | load_delay_nop (); |
4d7206a2 | 6109 | relax_switch (); |
67c0d1eb RS |
6110 | if (gpdelay) |
6111 | macro_build (NULL, "nop", ""); | |
252b5132 | 6112 | } |
67c0d1eb RS |
6113 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6114 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6115 | mips_gp_register); |
269137b2 | 6116 | load_delay_nop (); |
67c0d1eb RS |
6117 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6118 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6119 | relax_end (); |
67c0d1eb | 6120 | macro_build_jalr (&offset_expr); |
438c16b8 | 6121 | |
6478892d TS |
6122 | if (mips_cprestore_offset < 0) |
6123 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6124 | else | |
6125 | { | |
7a621144 DJ |
6126 | if (! mips_frame_reg_valid) |
6127 | { | |
6128 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6129 | /* Quiet this warning. */ | |
6130 | mips_frame_reg_valid = 1; | |
6131 | } | |
6132 | if (! mips_cprestore_valid) | |
6133 | { | |
6134 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6135 | /* Quiet this warning. */ | |
6136 | mips_cprestore_valid = 1; | |
6137 | } | |
6478892d | 6138 | if (mips_opts.noreorder) |
67c0d1eb | 6139 | macro_build (NULL, "nop", ""); |
6478892d | 6140 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6141 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6142 | mips_gp_register, |
256ab948 TS |
6143 | mips_frame_reg, |
6144 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6145 | } |
252b5132 RH |
6146 | } |
6147 | } | |
0a44bf69 RS |
6148 | else if (mips_pic == VXWORKS_PIC) |
6149 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6150 | else |
6151 | abort (); | |
6152 | ||
8fc2e39e | 6153 | break; |
252b5132 RH |
6154 | |
6155 | case M_LB_AB: | |
6156 | s = "lb"; | |
6157 | goto ld; | |
6158 | case M_LBU_AB: | |
6159 | s = "lbu"; | |
6160 | goto ld; | |
6161 | case M_LH_AB: | |
6162 | s = "lh"; | |
6163 | goto ld; | |
6164 | case M_LHU_AB: | |
6165 | s = "lhu"; | |
6166 | goto ld; | |
6167 | case M_LW_AB: | |
6168 | s = "lw"; | |
6169 | goto ld; | |
6170 | case M_LWC0_AB: | |
6171 | s = "lwc0"; | |
bdaaa2e1 | 6172 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6173 | coproc = 1; |
6174 | goto ld; | |
6175 | case M_LWC1_AB: | |
6176 | s = "lwc1"; | |
bdaaa2e1 | 6177 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6178 | coproc = 1; |
6179 | goto ld; | |
6180 | case M_LWC2_AB: | |
6181 | s = "lwc2"; | |
bdaaa2e1 | 6182 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6183 | coproc = 1; |
6184 | goto ld; | |
6185 | case M_LWC3_AB: | |
6186 | s = "lwc3"; | |
bdaaa2e1 | 6187 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6188 | coproc = 1; |
6189 | goto ld; | |
6190 | case M_LWL_AB: | |
6191 | s = "lwl"; | |
6192 | lr = 1; | |
6193 | goto ld; | |
6194 | case M_LWR_AB: | |
6195 | s = "lwr"; | |
6196 | lr = 1; | |
6197 | goto ld; | |
6198 | case M_LDC1_AB: | |
252b5132 | 6199 | s = "ldc1"; |
bdaaa2e1 | 6200 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6201 | coproc = 1; |
6202 | goto ld; | |
6203 | case M_LDC2_AB: | |
6204 | s = "ldc2"; | |
bdaaa2e1 | 6205 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6206 | coproc = 1; |
6207 | goto ld; | |
6208 | case M_LDC3_AB: | |
6209 | s = "ldc3"; | |
bdaaa2e1 | 6210 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6211 | coproc = 1; |
6212 | goto ld; | |
6213 | case M_LDL_AB: | |
6214 | s = "ldl"; | |
6215 | lr = 1; | |
6216 | goto ld; | |
6217 | case M_LDR_AB: | |
6218 | s = "ldr"; | |
6219 | lr = 1; | |
6220 | goto ld; | |
6221 | case M_LL_AB: | |
6222 | s = "ll"; | |
6223 | goto ld; | |
6224 | case M_LLD_AB: | |
6225 | s = "lld"; | |
6226 | goto ld; | |
6227 | case M_LWU_AB: | |
6228 | s = "lwu"; | |
6229 | ld: | |
8fc2e39e | 6230 | if (breg == treg || coproc || lr) |
252b5132 RH |
6231 | { |
6232 | tempreg = AT; | |
6233 | used_at = 1; | |
6234 | } | |
6235 | else | |
6236 | { | |
6237 | tempreg = treg; | |
252b5132 RH |
6238 | } |
6239 | goto ld_st; | |
6240 | case M_SB_AB: | |
6241 | s = "sb"; | |
6242 | goto st; | |
6243 | case M_SH_AB: | |
6244 | s = "sh"; | |
6245 | goto st; | |
6246 | case M_SW_AB: | |
6247 | s = "sw"; | |
6248 | goto st; | |
6249 | case M_SWC0_AB: | |
6250 | s = "swc0"; | |
bdaaa2e1 | 6251 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6252 | coproc = 1; |
6253 | goto st; | |
6254 | case M_SWC1_AB: | |
6255 | s = "swc1"; | |
bdaaa2e1 | 6256 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6257 | coproc = 1; |
6258 | goto st; | |
6259 | case M_SWC2_AB: | |
6260 | s = "swc2"; | |
bdaaa2e1 | 6261 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6262 | coproc = 1; |
6263 | goto st; | |
6264 | case M_SWC3_AB: | |
6265 | s = "swc3"; | |
bdaaa2e1 | 6266 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6267 | coproc = 1; |
6268 | goto st; | |
6269 | case M_SWL_AB: | |
6270 | s = "swl"; | |
6271 | goto st; | |
6272 | case M_SWR_AB: | |
6273 | s = "swr"; | |
6274 | goto st; | |
6275 | case M_SC_AB: | |
6276 | s = "sc"; | |
6277 | goto st; | |
6278 | case M_SCD_AB: | |
6279 | s = "scd"; | |
6280 | goto st; | |
d43b4baf TS |
6281 | case M_CACHE_AB: |
6282 | s = "cache"; | |
6283 | goto st; | |
252b5132 | 6284 | case M_SDC1_AB: |
252b5132 RH |
6285 | s = "sdc1"; |
6286 | coproc = 1; | |
bdaaa2e1 | 6287 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6288 | goto st; |
6289 | case M_SDC2_AB: | |
6290 | s = "sdc2"; | |
bdaaa2e1 | 6291 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6292 | coproc = 1; |
6293 | goto st; | |
6294 | case M_SDC3_AB: | |
6295 | s = "sdc3"; | |
bdaaa2e1 | 6296 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6297 | coproc = 1; |
6298 | goto st; | |
6299 | case M_SDL_AB: | |
6300 | s = "sdl"; | |
6301 | goto st; | |
6302 | case M_SDR_AB: | |
6303 | s = "sdr"; | |
6304 | st: | |
8fc2e39e TS |
6305 | tempreg = AT; |
6306 | used_at = 1; | |
252b5132 | 6307 | ld_st: |
bdaaa2e1 | 6308 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6309 | if (mask == M_LWC1_AB |
6310 | || mask == M_SWC1_AB | |
6311 | || mask == M_LDC1_AB | |
6312 | || mask == M_SDC1_AB | |
6313 | || mask == M_L_DAB | |
6314 | || mask == M_S_DAB) | |
6315 | fmt = "T,o(b)"; | |
d43b4baf TS |
6316 | else if (mask == M_CACHE_AB) |
6317 | fmt = "k,o(b)"; | |
252b5132 RH |
6318 | else if (coproc) |
6319 | fmt = "E,o(b)"; | |
6320 | else | |
6321 | fmt = "t,o(b)"; | |
6322 | ||
6323 | if (offset_expr.X_op != O_constant | |
6324 | && offset_expr.X_op != O_symbol) | |
6325 | { | |
6326 | as_bad (_("expression too complex")); | |
6327 | offset_expr.X_op = O_constant; | |
6328 | } | |
6329 | ||
2051e8c4 MR |
6330 | if (HAVE_32BIT_ADDRESSES |
6331 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6332 | { |
6333 | char value [32]; | |
6334 | ||
6335 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6336 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6337 | } |
2051e8c4 | 6338 | |
252b5132 RH |
6339 | /* A constant expression in PIC code can be handled just as it |
6340 | is in non PIC code. */ | |
aed1a261 RS |
6341 | if (offset_expr.X_op == O_constant) |
6342 | { | |
aed1a261 RS |
6343 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6344 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6345 | normalize_address_expr (&expr1); |
aed1a261 RS |
6346 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6347 | if (breg != 0) | |
6348 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6349 | tempreg, tempreg, breg); | |
6350 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6351 | } | |
6352 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6353 | { |
6354 | /* If this is a reference to a GP relative symbol, and there | |
6355 | is no base register, we want | |
cdf6fd85 | 6356 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6357 | Otherwise, if there is no base register, we want |
6358 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6359 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6360 | If we have a constant, we need two instructions anyhow, | |
6361 | so we always use the latter form. | |
6362 | ||
6363 | If we have a base register, and this is a reference to a | |
6364 | GP relative symbol, we want | |
6365 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6366 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6367 | Otherwise we want |
6368 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6369 | addu $tempreg,$tempreg,$breg | |
6370 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6371 | With a constant we always use the latter case. |
76b3015f | 6372 | |
d6bc6245 TS |
6373 | With 64bit address space and no base register and $at usable, |
6374 | we want | |
6375 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6376 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6377 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6378 | dsll32 $tempreg,0 | |
6379 | daddu $tempreg,$at | |
6380 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6381 | If we have a base register, we want | |
6382 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6383 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6384 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6385 | daddu $at,$breg | |
6386 | dsll32 $tempreg,0 | |
6387 | daddu $tempreg,$at | |
6388 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6389 | ||
6390 | Without $at we can't generate the optimal path for superscalar | |
6391 | processors here since this would require two temporary registers. | |
6392 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6393 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6394 | dsll $tempreg,16 | |
6395 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6396 | dsll $tempreg,16 | |
6397 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6398 | If we have a base register, we want | |
6399 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6400 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6401 | dsll $tempreg,16 | |
6402 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6403 | dsll $tempreg,16 | |
6404 | daddu $tempreg,$tempreg,$breg | |
6405 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6406 | |
6caf9ef4 | 6407 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6408 | the same sequence as in 32bit address space. */ |
6409 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6410 | { |
aed1a261 | 6411 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6412 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6413 | { | |
6414 | relax_start (offset_expr.X_add_symbol); | |
6415 | if (breg == 0) | |
6416 | { | |
6417 | macro_build (&offset_expr, s, fmt, treg, | |
6418 | BFD_RELOC_GPREL16, mips_gp_register); | |
6419 | } | |
6420 | else | |
6421 | { | |
6422 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6423 | tempreg, breg, mips_gp_register); | |
6424 | macro_build (&offset_expr, s, fmt, treg, | |
6425 | BFD_RELOC_GPREL16, tempreg); | |
6426 | } | |
6427 | relax_switch (); | |
6428 | } | |
d6bc6245 | 6429 | |
741fe287 | 6430 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6431 | { |
67c0d1eb RS |
6432 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6433 | BFD_RELOC_MIPS_HIGHEST); | |
6434 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6435 | BFD_RELOC_HI16_S); | |
6436 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6437 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6438 | if (breg != 0) |
67c0d1eb RS |
6439 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6440 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6441 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6442 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6443 | tempreg); | |
d6bc6245 TS |
6444 | used_at = 1; |
6445 | } | |
6446 | else | |
6447 | { | |
67c0d1eb RS |
6448 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6449 | BFD_RELOC_MIPS_HIGHEST); | |
6450 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6451 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6452 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6453 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6454 | tempreg, BFD_RELOC_HI16_S); | |
6455 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6456 | if (breg != 0) |
67c0d1eb | 6457 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6458 | tempreg, tempreg, breg); |
67c0d1eb | 6459 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6460 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6461 | } |
6caf9ef4 TS |
6462 | |
6463 | if (mips_relax.sequence) | |
6464 | relax_end (); | |
8fc2e39e | 6465 | break; |
d6bc6245 | 6466 | } |
256ab948 | 6467 | |
252b5132 RH |
6468 | if (breg == 0) |
6469 | { | |
67c0d1eb | 6470 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6471 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6472 | { |
4d7206a2 | 6473 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6474 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6475 | mips_gp_register); | |
4d7206a2 | 6476 | relax_switch (); |
252b5132 | 6477 | } |
67c0d1eb RS |
6478 | macro_build_lui (&offset_expr, tempreg); |
6479 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6480 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6481 | if (mips_relax.sequence) |
6482 | relax_end (); | |
252b5132 RH |
6483 | } |
6484 | else | |
6485 | { | |
67c0d1eb | 6486 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6487 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6488 | { |
4d7206a2 | 6489 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6490 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6491 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6492 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6493 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6494 | relax_switch (); |
252b5132 | 6495 | } |
67c0d1eb RS |
6496 | macro_build_lui (&offset_expr, tempreg); |
6497 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6498 | tempreg, tempreg, breg); |
67c0d1eb | 6499 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6500 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6501 | if (mips_relax.sequence) |
6502 | relax_end (); | |
252b5132 RH |
6503 | } |
6504 | } | |
0a44bf69 | 6505 | else if (!mips_big_got) |
252b5132 | 6506 | { |
ed6fb7bd | 6507 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6508 | |
252b5132 RH |
6509 | /* If this is a reference to an external symbol, we want |
6510 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6511 | nop | |
6512 | <op> $treg,0($tempreg) | |
6513 | Otherwise we want | |
6514 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6515 | nop | |
6516 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6517 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6518 | |
6519 | For NewABI, we want | |
6520 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6521 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6522 | ||
252b5132 RH |
6523 | If there is a base register, we add it to $tempreg before |
6524 | the <op>. If there is a constant, we stick it in the | |
6525 | <op> instruction. We don't handle constants larger than | |
6526 | 16 bits, because we have no way to load the upper 16 bits | |
6527 | (actually, we could handle them for the subset of cases | |
6528 | in which we are not using $at). */ | |
6529 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6530 | if (HAVE_NEWABI) |
6531 | { | |
67c0d1eb RS |
6532 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6533 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6534 | if (breg != 0) |
67c0d1eb | 6535 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6536 | tempreg, tempreg, breg); |
67c0d1eb | 6537 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6538 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6539 | break; |
6540 | } | |
252b5132 RH |
6541 | expr1.X_add_number = offset_expr.X_add_number; |
6542 | offset_expr.X_add_number = 0; | |
6543 | if (expr1.X_add_number < -0x8000 | |
6544 | || expr1.X_add_number >= 0x8000) | |
6545 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6546 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6547 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6548 | load_delay_nop (); |
4d7206a2 RS |
6549 | relax_start (offset_expr.X_add_symbol); |
6550 | relax_switch (); | |
67c0d1eb RS |
6551 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6552 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6553 | relax_end (); |
252b5132 | 6554 | if (breg != 0) |
67c0d1eb | 6555 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6556 | tempreg, tempreg, breg); |
67c0d1eb | 6557 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6558 | } |
0a44bf69 | 6559 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6560 | { |
67c0d1eb | 6561 | int gpdelay; |
252b5132 RH |
6562 | |
6563 | /* If this is a reference to an external symbol, we want | |
6564 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6565 | addu $tempreg,$tempreg,$gp | |
6566 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6567 | <op> $treg,0($tempreg) | |
6568 | Otherwise we want | |
6569 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6570 | nop | |
6571 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6572 | <op> $treg,0($tempreg) | |
6573 | If there is a base register, we add it to $tempreg before | |
6574 | the <op>. If there is a constant, we stick it in the | |
6575 | <op> instruction. We don't handle constants larger than | |
6576 | 16 bits, because we have no way to load the upper 16 bits | |
6577 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6578 | in which we are not using $at). */ |
252b5132 RH |
6579 | assert (offset_expr.X_op == O_symbol); |
6580 | expr1.X_add_number = offset_expr.X_add_number; | |
6581 | offset_expr.X_add_number = 0; | |
6582 | if (expr1.X_add_number < -0x8000 | |
6583 | || expr1.X_add_number >= 0x8000) | |
6584 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6585 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6586 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6587 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6588 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6589 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6590 | mips_gp_register); | |
6591 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6592 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6593 | relax_switch (); |
67c0d1eb RS |
6594 | if (gpdelay) |
6595 | macro_build (NULL, "nop", ""); | |
6596 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6597 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6598 | load_delay_nop (); |
67c0d1eb RS |
6599 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6600 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6601 | relax_end (); |
6602 | ||
252b5132 | 6603 | if (breg != 0) |
67c0d1eb | 6604 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6605 | tempreg, tempreg, breg); |
67c0d1eb | 6606 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6607 | } |
0a44bf69 | 6608 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6609 | { |
f5040a92 AO |
6610 | /* If this is a reference to an external symbol, we want |
6611 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6612 | add $tempreg,$tempreg,$gp | |
6613 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6614 | <op> $treg,<ofst>($tempreg) | |
6615 | Otherwise, for local symbols, we want: | |
6616 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6617 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6618 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6619 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6620 | offset_expr.X_add_number = 0; |
6621 | if (expr1.X_add_number < -0x8000 | |
6622 | || expr1.X_add_number >= 0x8000) | |
6623 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6624 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6625 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6626 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6627 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6628 | mips_gp_register); | |
6629 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6630 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6631 | if (breg != 0) |
67c0d1eb | 6632 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6633 | tempreg, tempreg, breg); |
67c0d1eb | 6634 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6635 | |
4d7206a2 | 6636 | relax_switch (); |
f5040a92 | 6637 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6638 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6639 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6640 | if (breg != 0) |
67c0d1eb | 6641 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6642 | tempreg, tempreg, breg); |
67c0d1eb | 6643 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6644 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6645 | relax_end (); |
f5040a92 | 6646 | } |
252b5132 RH |
6647 | else |
6648 | abort (); | |
6649 | ||
252b5132 RH |
6650 | break; |
6651 | ||
6652 | case M_LI: | |
6653 | case M_LI_S: | |
67c0d1eb | 6654 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6655 | break; |
252b5132 RH |
6656 | |
6657 | case M_DLI: | |
67c0d1eb | 6658 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6659 | break; |
252b5132 RH |
6660 | |
6661 | case M_LI_SS: | |
6662 | if (imm_expr.X_op == O_constant) | |
6663 | { | |
8fc2e39e | 6664 | used_at = 1; |
67c0d1eb RS |
6665 | load_register (AT, &imm_expr, 0); |
6666 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6667 | break; |
6668 | } | |
6669 | else | |
6670 | { | |
6671 | assert (offset_expr.X_op == O_symbol | |
6672 | && strcmp (segment_name (S_GET_SEGMENT | |
6673 | (offset_expr.X_add_symbol)), | |
6674 | ".lit4") == 0 | |
6675 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6676 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6677 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6678 | break; |
252b5132 RH |
6679 | } |
6680 | ||
6681 | case M_LI_D: | |
ca4e0257 RS |
6682 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6683 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6684 | order 32 bits of the value and the low order 32 bits are either | |
6685 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6686 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6687 | { | |
ca4e0257 | 6688 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6689 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6690 | else |
6691 | { | |
6692 | int hreg, lreg; | |
6693 | ||
6694 | if (target_big_endian) | |
6695 | { | |
6696 | hreg = treg; | |
6697 | lreg = treg + 1; | |
6698 | } | |
6699 | else | |
6700 | { | |
6701 | hreg = treg + 1; | |
6702 | lreg = treg; | |
6703 | } | |
6704 | ||
6705 | if (hreg <= 31) | |
67c0d1eb | 6706 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6707 | if (lreg <= 31) |
6708 | { | |
6709 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6710 | move_register (lreg, 0); |
252b5132 RH |
6711 | else |
6712 | { | |
6713 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6714 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6715 | } |
6716 | } | |
6717 | } | |
8fc2e39e | 6718 | break; |
252b5132 RH |
6719 | } |
6720 | ||
6721 | /* We know that sym is in the .rdata section. First we get the | |
6722 | upper 16 bits of the address. */ | |
6723 | if (mips_pic == NO_PIC) | |
6724 | { | |
67c0d1eb | 6725 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6726 | used_at = 1; |
252b5132 | 6727 | } |
0a44bf69 | 6728 | else |
252b5132 | 6729 | { |
67c0d1eb RS |
6730 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6731 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6732 | used_at = 1; |
252b5132 | 6733 | } |
bdaaa2e1 | 6734 | |
252b5132 | 6735 | /* Now we load the register(s). */ |
ca4e0257 | 6736 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6737 | { |
6738 | used_at = 1; | |
6739 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6740 | } | |
252b5132 RH |
6741 | else |
6742 | { | |
8fc2e39e | 6743 | used_at = 1; |
67c0d1eb | 6744 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6745 | if (treg != RA) |
252b5132 RH |
6746 | { |
6747 | /* FIXME: How in the world do we deal with the possible | |
6748 | overflow here? */ | |
6749 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6750 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6751 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6752 | } |
6753 | } | |
252b5132 RH |
6754 | break; |
6755 | ||
6756 | case M_LI_DD: | |
ca4e0257 RS |
6757 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6758 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6759 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6760 | the value and the low order 32 bits are either zero or in | |
6761 | OFFSET_EXPR. */ | |
252b5132 RH |
6762 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6763 | { | |
8fc2e39e | 6764 | used_at = 1; |
67c0d1eb | 6765 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6766 | if (HAVE_64BIT_FPRS) |
6767 | { | |
6768 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6769 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6770 | } |
252b5132 RH |
6771 | else |
6772 | { | |
67c0d1eb | 6773 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6774 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6775 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6776 | else |
6777 | { | |
6778 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6779 | load_register (AT, &offset_expr, 0); |
6780 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6781 | } |
6782 | } | |
6783 | break; | |
6784 | } | |
6785 | ||
6786 | assert (offset_expr.X_op == O_symbol | |
6787 | && offset_expr.X_add_number == 0); | |
6788 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6789 | if (strcmp (s, ".lit8") == 0) | |
6790 | { | |
e7af610e | 6791 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6792 | { |
67c0d1eb | 6793 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6794 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6795 | break; |
252b5132 | 6796 | } |
c9914766 | 6797 | breg = mips_gp_register; |
252b5132 RH |
6798 | r = BFD_RELOC_MIPS_LITERAL; |
6799 | goto dob; | |
6800 | } | |
6801 | else | |
6802 | { | |
6803 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6804 | used_at = 1; |
0a44bf69 | 6805 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6806 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6807 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6808 | else |
6809 | { | |
6810 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6811 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6812 | } |
bdaaa2e1 | 6813 | |
e7af610e | 6814 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6815 | { |
67c0d1eb RS |
6816 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6817 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6818 | break; |
6819 | } | |
6820 | breg = AT; | |
6821 | r = BFD_RELOC_LO16; | |
6822 | goto dob; | |
6823 | } | |
6824 | ||
6825 | case M_L_DOB: | |
252b5132 RH |
6826 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6827 | to adjust when loading from memory. */ | |
6828 | r = BFD_RELOC_LO16; | |
6829 | dob: | |
e7af610e | 6830 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6831 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6832 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6833 | /* FIXME: A possible overflow which I don't know how to deal |
6834 | with. */ | |
6835 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6836 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6837 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6838 | break; |
6839 | ||
6840 | case M_L_DAB: | |
6841 | /* | |
6842 | * The MIPS assembler seems to check for X_add_number not | |
6843 | * being double aligned and generating: | |
6844 | * lui at,%hi(foo+1) | |
6845 | * addu at,at,v1 | |
6846 | * addiu at,at,%lo(foo+1) | |
6847 | * lwc1 f2,0(at) | |
6848 | * lwc1 f3,4(at) | |
6849 | * But, the resulting address is the same after relocation so why | |
6850 | * generate the extra instruction? | |
6851 | */ | |
bdaaa2e1 | 6852 | /* Itbl support may require additional care here. */ |
252b5132 | 6853 | coproc = 1; |
e7af610e | 6854 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6855 | { |
6856 | s = "ldc1"; | |
6857 | goto ld; | |
6858 | } | |
6859 | ||
6860 | s = "lwc1"; | |
6861 | fmt = "T,o(b)"; | |
6862 | goto ldd_std; | |
6863 | ||
6864 | case M_S_DAB: | |
e7af610e | 6865 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6866 | { |
6867 | s = "sdc1"; | |
6868 | goto st; | |
6869 | } | |
6870 | ||
6871 | s = "swc1"; | |
6872 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6873 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6874 | coproc = 1; |
6875 | goto ldd_std; | |
6876 | ||
6877 | case M_LD_AB: | |
ca4e0257 | 6878 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6879 | { |
6880 | s = "ld"; | |
6881 | goto ld; | |
6882 | } | |
6883 | ||
6884 | s = "lw"; | |
6885 | fmt = "t,o(b)"; | |
6886 | goto ldd_std; | |
6887 | ||
6888 | case M_SD_AB: | |
ca4e0257 | 6889 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6890 | { |
6891 | s = "sd"; | |
6892 | goto st; | |
6893 | } | |
6894 | ||
6895 | s = "sw"; | |
6896 | fmt = "t,o(b)"; | |
6897 | ||
6898 | ldd_std: | |
6899 | if (offset_expr.X_op != O_symbol | |
6900 | && offset_expr.X_op != O_constant) | |
6901 | { | |
6902 | as_bad (_("expression too complex")); | |
6903 | offset_expr.X_op = O_constant; | |
6904 | } | |
6905 | ||
2051e8c4 MR |
6906 | if (HAVE_32BIT_ADDRESSES |
6907 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6908 | { |
6909 | char value [32]; | |
6910 | ||
6911 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6912 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6913 | } |
2051e8c4 | 6914 | |
252b5132 RH |
6915 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6916 | to adjust when loading from memory. We set coproc if we must | |
6917 | load $fn+1 first. */ | |
bdaaa2e1 | 6918 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6919 | if (! target_big_endian) |
6920 | coproc = 0; | |
6921 | ||
6922 | if (mips_pic == NO_PIC | |
6923 | || offset_expr.X_op == O_constant) | |
6924 | { | |
6925 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6926 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6927 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6928 | If we have a base register, we use this |
6929 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6930 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6931 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6932 | If this is not a GP relative symbol, we want |
6933 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6934 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6935 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6936 | If there is a base register, we add it to $at after the | |
6937 | lui instruction. If there is a constant, we always use | |
6938 | the last case. */ | |
39a59cf8 MR |
6939 | if (offset_expr.X_op == O_symbol |
6940 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6941 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6942 | { |
4d7206a2 | 6943 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6944 | if (breg == 0) |
6945 | { | |
c9914766 | 6946 | tempreg = mips_gp_register; |
252b5132 RH |
6947 | } |
6948 | else | |
6949 | { | |
67c0d1eb | 6950 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6951 | AT, breg, mips_gp_register); |
252b5132 | 6952 | tempreg = AT; |
252b5132 RH |
6953 | used_at = 1; |
6954 | } | |
6955 | ||
beae10d5 | 6956 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6957 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6958 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6959 | offset_expr.X_add_number += 4; |
6960 | ||
6961 | /* Set mips_optimize to 2 to avoid inserting an | |
6962 | undesired nop. */ | |
6963 | hold_mips_optimize = mips_optimize; | |
6964 | mips_optimize = 2; | |
beae10d5 | 6965 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6966 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6967 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6968 | mips_optimize = hold_mips_optimize; |
6969 | ||
4d7206a2 | 6970 | relax_switch (); |
252b5132 RH |
6971 | |
6972 | /* We just generated two relocs. When tc_gen_reloc | |
6973 | handles this case, it will skip the first reloc and | |
6974 | handle the second. The second reloc already has an | |
6975 | extra addend of 4, which we added above. We must | |
6976 | subtract it out, and then subtract another 4 to make | |
6977 | the first reloc come out right. The second reloc | |
6978 | will come out right because we are going to add 4 to | |
6979 | offset_expr when we build its instruction below. | |
6980 | ||
6981 | If we have a symbol, then we don't want to include | |
6982 | the offset, because it will wind up being included | |
6983 | when we generate the reloc. */ | |
6984 | ||
6985 | if (offset_expr.X_op == O_constant) | |
6986 | offset_expr.X_add_number -= 8; | |
6987 | else | |
6988 | { | |
6989 | offset_expr.X_add_number = -4; | |
6990 | offset_expr.X_op = O_constant; | |
6991 | } | |
6992 | } | |
8fc2e39e | 6993 | used_at = 1; |
67c0d1eb | 6994 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6995 | if (breg != 0) |
67c0d1eb | 6996 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6997 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6998 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6999 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7000 | /* FIXME: How do we handle overflow here? */ |
7001 | offset_expr.X_add_number += 4; | |
beae10d5 | 7002 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7003 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7004 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7005 | if (mips_relax.sequence) |
7006 | relax_end (); | |
bdaaa2e1 | 7007 | } |
0a44bf69 | 7008 | else if (!mips_big_got) |
252b5132 | 7009 | { |
252b5132 RH |
7010 | /* If this is a reference to an external symbol, we want |
7011 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7012 | nop | |
7013 | <op> $treg,0($at) | |
7014 | <op> $treg+1,4($at) | |
7015 | Otherwise we want | |
7016 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7017 | nop | |
7018 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7019 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7020 | If there is a base register we add it to $at before the | |
7021 | lwc1 instructions. If there is a constant we include it | |
7022 | in the lwc1 instructions. */ | |
7023 | used_at = 1; | |
7024 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7025 | if (expr1.X_add_number < -0x8000 |
7026 | || expr1.X_add_number >= 0x8000 - 4) | |
7027 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7028 | load_got_offset (AT, &offset_expr); |
269137b2 | 7029 | load_delay_nop (); |
252b5132 | 7030 | if (breg != 0) |
67c0d1eb | 7031 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7032 | |
7033 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7034 | nop. */ | |
7035 | hold_mips_optimize = mips_optimize; | |
7036 | mips_optimize = 2; | |
4d7206a2 | 7037 | |
beae10d5 | 7038 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7039 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7040 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7041 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7042 | expr1.X_add_number += 4; |
67c0d1eb RS |
7043 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7044 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7045 | relax_switch (); |
67c0d1eb RS |
7046 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7047 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7048 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7049 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7050 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7051 | relax_end (); |
252b5132 | 7052 | |
4d7206a2 | 7053 | mips_optimize = hold_mips_optimize; |
252b5132 | 7054 | } |
0a44bf69 | 7055 | else if (mips_big_got) |
252b5132 | 7056 | { |
67c0d1eb | 7057 | int gpdelay; |
252b5132 RH |
7058 | |
7059 | /* If this is a reference to an external symbol, we want | |
7060 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7061 | addu $at,$at,$gp | |
7062 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7063 | nop | |
7064 | <op> $treg,0($at) | |
7065 | <op> $treg+1,4($at) | |
7066 | Otherwise we want | |
7067 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7068 | nop | |
7069 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7070 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7071 | If there is a base register we add it to $at before the | |
7072 | lwc1 instructions. If there is a constant we include it | |
7073 | in the lwc1 instructions. */ | |
7074 | used_at = 1; | |
7075 | expr1.X_add_number = offset_expr.X_add_number; | |
7076 | offset_expr.X_add_number = 0; | |
7077 | if (expr1.X_add_number < -0x8000 | |
7078 | || expr1.X_add_number >= 0x8000 - 4) | |
7079 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7080 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7081 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7082 | macro_build (&offset_expr, "lui", "t,u", |
7083 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7084 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7085 | AT, AT, mips_gp_register); |
67c0d1eb | 7086 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7087 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7088 | load_delay_nop (); |
252b5132 | 7089 | if (breg != 0) |
67c0d1eb | 7090 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7091 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7092 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7093 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7094 | expr1.X_add_number += 4; |
7095 | ||
7096 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7097 | nop. */ | |
7098 | hold_mips_optimize = mips_optimize; | |
7099 | mips_optimize = 2; | |
beae10d5 | 7100 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7101 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7102 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7103 | mips_optimize = hold_mips_optimize; |
7104 | expr1.X_add_number -= 4; | |
7105 | ||
4d7206a2 RS |
7106 | relax_switch (); |
7107 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7108 | if (gpdelay) |
7109 | macro_build (NULL, "nop", ""); | |
7110 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7111 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7112 | load_delay_nop (); |
252b5132 | 7113 | if (breg != 0) |
67c0d1eb | 7114 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7115 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7116 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7117 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7118 | offset_expr.X_add_number += 4; |
252b5132 RH |
7119 | |
7120 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7121 | nop. */ | |
7122 | hold_mips_optimize = mips_optimize; | |
7123 | mips_optimize = 2; | |
beae10d5 | 7124 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7125 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7126 | BFD_RELOC_LO16, AT); | |
252b5132 | 7127 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7128 | relax_end (); |
252b5132 | 7129 | } |
252b5132 RH |
7130 | else |
7131 | abort (); | |
7132 | ||
252b5132 RH |
7133 | break; |
7134 | ||
7135 | case M_LD_OB: | |
7136 | s = "lw"; | |
7137 | goto sd_ob; | |
7138 | case M_SD_OB: | |
7139 | s = "sw"; | |
7140 | sd_ob: | |
ca4e0257 | 7141 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7142 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7143 | offset_expr.X_add_number += 4; |
67c0d1eb | 7144 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7145 | break; |
252b5132 RH |
7146 | |
7147 | /* New code added to support COPZ instructions. | |
7148 | This code builds table entries out of the macros in mip_opcodes. | |
7149 | R4000 uses interlocks to handle coproc delays. | |
7150 | Other chips (like the R3000) require nops to be inserted for delays. | |
7151 | ||
f72c8c98 | 7152 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7153 | In order to fill delay slots for non-interlocked chips, |
7154 | we must have a way to specify delays based on the coprocessor. | |
7155 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7156 | What are the side-effects of the cop instruction? | |
7157 | What cache support might we have and what are its effects? | |
7158 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7159 | What registers are read/set/modified? |
252b5132 RH |
7160 | |
7161 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7162 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7163 | |
7164 | case M_COP0: | |
7165 | s = "c0"; | |
7166 | goto copz; | |
7167 | case M_COP1: | |
7168 | s = "c1"; | |
7169 | goto copz; | |
7170 | case M_COP2: | |
7171 | s = "c2"; | |
7172 | goto copz; | |
7173 | case M_COP3: | |
7174 | s = "c3"; | |
7175 | copz: | |
7176 | /* For now we just do C (same as Cz). The parameter will be | |
7177 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7178 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7179 | break; |
252b5132 | 7180 | |
ea1fb5dc | 7181 | case M_MOVE: |
67c0d1eb | 7182 | move_register (dreg, sreg); |
8fc2e39e | 7183 | break; |
ea1fb5dc | 7184 | |
252b5132 RH |
7185 | #ifdef LOSING_COMPILER |
7186 | default: | |
7187 | /* Try and see if this is a new itbl instruction. | |
7188 | This code builds table entries out of the macros in mip_opcodes. | |
7189 | FIXME: For now we just assemble the expression and pass it's | |
7190 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7191 | We may want to have the assembler assemble this value, |
252b5132 RH |
7192 | so that we gain the assembler's knowledge of delay slots, |
7193 | symbols, etc. | |
7194 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7195 | if (itbl_have_entries |
252b5132 | 7196 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7197 | { |
252b5132 RH |
7198 | s = ip->insn_mo->name; |
7199 | s2 = "cop3"; | |
7200 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7201 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7202 | break; |
beae10d5 | 7203 | } |
252b5132 | 7204 | macro2 (ip); |
8fc2e39e | 7205 | break; |
252b5132 | 7206 | } |
741fe287 | 7207 | if (!mips_opts.at && used_at) |
8fc2e39e | 7208 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 | 7209 | } |
bdaaa2e1 | 7210 | |
252b5132 | 7211 | static void |
17a2f251 | 7212 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7213 | { |
741fe287 MR |
7214 | unsigned int treg, sreg, dreg, breg; |
7215 | unsigned int tempreg; | |
252b5132 | 7216 | int mask; |
252b5132 RH |
7217 | int used_at; |
7218 | expressionS expr1; | |
7219 | const char *s; | |
7220 | const char *s2; | |
7221 | const char *fmt; | |
7222 | int likely = 0; | |
7223 | int dbl = 0; | |
7224 | int coproc = 0; | |
7225 | int lr = 0; | |
7226 | int imm = 0; | |
7227 | int off; | |
7228 | offsetT maxnum; | |
7229 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7230 | |
252b5132 RH |
7231 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7232 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7233 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7234 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7235 | |
252b5132 RH |
7236 | expr1.X_op = O_constant; |
7237 | expr1.X_op_symbol = NULL; | |
7238 | expr1.X_add_symbol = NULL; | |
7239 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7240 | |
252b5132 RH |
7241 | switch (mask) |
7242 | { | |
7243 | #endif /* LOSING_COMPILER */ | |
7244 | ||
7245 | case M_DMUL: | |
7246 | dbl = 1; | |
7247 | case M_MUL: | |
67c0d1eb RS |
7248 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7249 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7250 | break; |
252b5132 RH |
7251 | |
7252 | case M_DMUL_I: | |
7253 | dbl = 1; | |
7254 | case M_MUL_I: | |
7255 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7256 | not trying to be that fancy. GCC should do this for us | |
7257 | anyway. */ | |
8fc2e39e | 7258 | used_at = 1; |
67c0d1eb RS |
7259 | load_register (AT, &imm_expr, dbl); |
7260 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7261 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7262 | break; |
7263 | ||
7264 | case M_DMULO_I: | |
7265 | dbl = 1; | |
7266 | case M_MULO_I: | |
7267 | imm = 1; | |
7268 | goto do_mulo; | |
7269 | ||
7270 | case M_DMULO: | |
7271 | dbl = 1; | |
7272 | case M_MULO: | |
7273 | do_mulo: | |
7d10b47d | 7274 | start_noreorder (); |
8fc2e39e | 7275 | used_at = 1; |
252b5132 | 7276 | if (imm) |
67c0d1eb RS |
7277 | load_register (AT, &imm_expr, dbl); |
7278 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7279 | macro_build (NULL, "mflo", "d", dreg); | |
7280 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7281 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7282 | if (mips_trap) |
67c0d1eb | 7283 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7284 | else |
7285 | { | |
7286 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7287 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7288 | macro_build (NULL, "nop", "", 0); | |
7289 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7290 | } |
7d10b47d | 7291 | end_noreorder (); |
67c0d1eb | 7292 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7293 | break; |
7294 | ||
7295 | case M_DMULOU_I: | |
7296 | dbl = 1; | |
7297 | case M_MULOU_I: | |
7298 | imm = 1; | |
7299 | goto do_mulou; | |
7300 | ||
7301 | case M_DMULOU: | |
7302 | dbl = 1; | |
7303 | case M_MULOU: | |
7304 | do_mulou: | |
7d10b47d | 7305 | start_noreorder (); |
8fc2e39e | 7306 | used_at = 1; |
252b5132 | 7307 | if (imm) |
67c0d1eb RS |
7308 | load_register (AT, &imm_expr, dbl); |
7309 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7310 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7311 | macro_build (NULL, "mfhi", "d", AT); |
7312 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7313 | if (mips_trap) |
67c0d1eb | 7314 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7315 | else |
7316 | { | |
7317 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7318 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7319 | macro_build (NULL, "nop", "", 0); | |
7320 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7321 | } |
7d10b47d | 7322 | end_noreorder (); |
252b5132 RH |
7323 | break; |
7324 | ||
771c7ce4 | 7325 | case M_DROL: |
fef14a42 | 7326 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7327 | { |
7328 | if (dreg == sreg) | |
7329 | { | |
7330 | tempreg = AT; | |
7331 | used_at = 1; | |
7332 | } | |
7333 | else | |
7334 | { | |
7335 | tempreg = dreg; | |
82dd0097 | 7336 | } |
67c0d1eb RS |
7337 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7338 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7339 | break; |
82dd0097 | 7340 | } |
8fc2e39e | 7341 | used_at = 1; |
67c0d1eb RS |
7342 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7343 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7344 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7345 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7346 | break; |
7347 | ||
252b5132 | 7348 | case M_ROL: |
fef14a42 | 7349 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7350 | { |
7351 | if (dreg == sreg) | |
7352 | { | |
7353 | tempreg = AT; | |
7354 | used_at = 1; | |
7355 | } | |
7356 | else | |
7357 | { | |
7358 | tempreg = dreg; | |
82dd0097 | 7359 | } |
67c0d1eb RS |
7360 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7361 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7362 | break; |
82dd0097 | 7363 | } |
8fc2e39e | 7364 | used_at = 1; |
67c0d1eb RS |
7365 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7366 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7367 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7368 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7369 | break; |
7370 | ||
771c7ce4 TS |
7371 | case M_DROL_I: |
7372 | { | |
7373 | unsigned int rot; | |
82dd0097 | 7374 | char *l, *r; |
771c7ce4 TS |
7375 | |
7376 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7377 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7378 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7379 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7380 | { |
7381 | rot = (64 - rot) & 0x3f; | |
7382 | if (rot >= 32) | |
67c0d1eb | 7383 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7384 | else |
67c0d1eb | 7385 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7386 | break; |
60b63b72 | 7387 | } |
483fc7cd | 7388 | if (rot == 0) |
483fc7cd | 7389 | { |
67c0d1eb | 7390 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7391 | break; |
483fc7cd | 7392 | } |
82dd0097 CD |
7393 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7394 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7395 | rot &= 0x1f; | |
8fc2e39e | 7396 | used_at = 1; |
67c0d1eb RS |
7397 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7398 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7399 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7400 | } |
7401 | break; | |
7402 | ||
252b5132 | 7403 | case M_ROL_I: |
771c7ce4 TS |
7404 | { |
7405 | unsigned int rot; | |
7406 | ||
7407 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7408 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7409 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7410 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7411 | { |
67c0d1eb | 7412 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7413 | break; |
60b63b72 | 7414 | } |
483fc7cd | 7415 | if (rot == 0) |
483fc7cd | 7416 | { |
67c0d1eb | 7417 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7418 | break; |
483fc7cd | 7419 | } |
8fc2e39e | 7420 | used_at = 1; |
67c0d1eb RS |
7421 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7422 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7423 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7424 | } |
7425 | break; | |
7426 | ||
7427 | case M_DROR: | |
fef14a42 | 7428 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7429 | { |
67c0d1eb | 7430 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7431 | break; |
82dd0097 | 7432 | } |
8fc2e39e | 7433 | used_at = 1; |
67c0d1eb RS |
7434 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7435 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7436 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7437 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7438 | break; |
7439 | ||
7440 | case M_ROR: | |
fef14a42 | 7441 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7442 | { |
67c0d1eb | 7443 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7444 | break; |
82dd0097 | 7445 | } |
8fc2e39e | 7446 | used_at = 1; |
67c0d1eb RS |
7447 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7448 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7449 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7450 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7451 | break; |
7452 | ||
771c7ce4 TS |
7453 | case M_DROR_I: |
7454 | { | |
7455 | unsigned int rot; | |
82dd0097 | 7456 | char *l, *r; |
771c7ce4 TS |
7457 | |
7458 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7459 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7460 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7461 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7462 | { |
7463 | if (rot >= 32) | |
67c0d1eb | 7464 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7465 | else |
67c0d1eb | 7466 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7467 | break; |
82dd0097 | 7468 | } |
483fc7cd | 7469 | if (rot == 0) |
483fc7cd | 7470 | { |
67c0d1eb | 7471 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7472 | break; |
483fc7cd | 7473 | } |
82dd0097 CD |
7474 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7475 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7476 | rot &= 0x1f; | |
8fc2e39e | 7477 | used_at = 1; |
67c0d1eb RS |
7478 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7479 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7480 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7481 | } |
7482 | break; | |
7483 | ||
252b5132 | 7484 | case M_ROR_I: |
771c7ce4 TS |
7485 | { |
7486 | unsigned int rot; | |
7487 | ||
7488 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7489 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7490 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7491 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7492 | { |
67c0d1eb | 7493 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7494 | break; |
82dd0097 | 7495 | } |
483fc7cd | 7496 | if (rot == 0) |
483fc7cd | 7497 | { |
67c0d1eb | 7498 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7499 | break; |
483fc7cd | 7500 | } |
8fc2e39e | 7501 | used_at = 1; |
67c0d1eb RS |
7502 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7503 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7504 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7505 | } |
252b5132 RH |
7506 | break; |
7507 | ||
7508 | case M_S_DOB: | |
e7af610e | 7509 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7510 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7511 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7512 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7513 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7514 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7515 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7516 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7517 | break; |
252b5132 RH |
7518 | |
7519 | case M_SEQ: | |
7520 | if (sreg == 0) | |
67c0d1eb | 7521 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7522 | else if (treg == 0) |
67c0d1eb | 7523 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7524 | else |
7525 | { | |
67c0d1eb RS |
7526 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7527 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7528 | } |
8fc2e39e | 7529 | break; |
252b5132 RH |
7530 | |
7531 | case M_SEQ_I: | |
7532 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7533 | { | |
67c0d1eb | 7534 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7535 | break; |
252b5132 RH |
7536 | } |
7537 | if (sreg == 0) | |
7538 | { | |
7539 | as_warn (_("Instruction %s: result is always false"), | |
7540 | ip->insn_mo->name); | |
67c0d1eb | 7541 | move_register (dreg, 0); |
8fc2e39e | 7542 | break; |
252b5132 RH |
7543 | } |
7544 | if (imm_expr.X_op == O_constant | |
7545 | && imm_expr.X_add_number >= 0 | |
7546 | && imm_expr.X_add_number < 0x10000) | |
7547 | { | |
67c0d1eb | 7548 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7549 | } |
7550 | else if (imm_expr.X_op == O_constant | |
7551 | && imm_expr.X_add_number > -0x8000 | |
7552 | && imm_expr.X_add_number < 0) | |
7553 | { | |
7554 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7555 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7556 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7557 | } |
7558 | else | |
7559 | { | |
67c0d1eb RS |
7560 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7561 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7562 | used_at = 1; |
7563 | } | |
67c0d1eb | 7564 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7565 | break; |
252b5132 RH |
7566 | |
7567 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7568 | s = "slt"; | |
7569 | goto sge; | |
7570 | case M_SGEU: | |
7571 | s = "sltu"; | |
7572 | sge: | |
67c0d1eb RS |
7573 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7574 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7575 | break; |
252b5132 RH |
7576 | |
7577 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7578 | case M_SGEU_I: | |
7579 | if (imm_expr.X_op == O_constant | |
7580 | && imm_expr.X_add_number >= -0x8000 | |
7581 | && imm_expr.X_add_number < 0x8000) | |
7582 | { | |
67c0d1eb RS |
7583 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7584 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7585 | } |
7586 | else | |
7587 | { | |
67c0d1eb RS |
7588 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7589 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7590 | dreg, sreg, AT); | |
252b5132 RH |
7591 | used_at = 1; |
7592 | } | |
67c0d1eb | 7593 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7594 | break; |
252b5132 RH |
7595 | |
7596 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7597 | s = "slt"; | |
7598 | goto sgt; | |
7599 | case M_SGTU: | |
7600 | s = "sltu"; | |
7601 | sgt: | |
67c0d1eb | 7602 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7603 | break; |
252b5132 RH |
7604 | |
7605 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7606 | s = "slt"; | |
7607 | goto sgti; | |
7608 | case M_SGTU_I: | |
7609 | s = "sltu"; | |
7610 | sgti: | |
8fc2e39e | 7611 | used_at = 1; |
67c0d1eb RS |
7612 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7613 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7614 | break; |
7615 | ||
2396cfb9 | 7616 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7617 | s = "slt"; |
7618 | goto sle; | |
7619 | case M_SLEU: | |
7620 | s = "sltu"; | |
7621 | sle: | |
67c0d1eb RS |
7622 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7623 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7624 | break; |
252b5132 | 7625 | |
2396cfb9 | 7626 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7627 | s = "slt"; |
7628 | goto slei; | |
7629 | case M_SLEU_I: | |
7630 | s = "sltu"; | |
7631 | slei: | |
8fc2e39e | 7632 | used_at = 1; |
67c0d1eb RS |
7633 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7634 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7635 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7636 | break; |
7637 | ||
7638 | case M_SLT_I: | |
7639 | if (imm_expr.X_op == O_constant | |
7640 | && imm_expr.X_add_number >= -0x8000 | |
7641 | && imm_expr.X_add_number < 0x8000) | |
7642 | { | |
67c0d1eb | 7643 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7644 | break; |
252b5132 | 7645 | } |
8fc2e39e | 7646 | used_at = 1; |
67c0d1eb RS |
7647 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7648 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7649 | break; |
7650 | ||
7651 | case M_SLTU_I: | |
7652 | if (imm_expr.X_op == O_constant | |
7653 | && imm_expr.X_add_number >= -0x8000 | |
7654 | && imm_expr.X_add_number < 0x8000) | |
7655 | { | |
67c0d1eb | 7656 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7657 | BFD_RELOC_LO16); |
8fc2e39e | 7658 | break; |
252b5132 | 7659 | } |
8fc2e39e | 7660 | used_at = 1; |
67c0d1eb RS |
7661 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7662 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7663 | break; |
7664 | ||
7665 | case M_SNE: | |
7666 | if (sreg == 0) | |
67c0d1eb | 7667 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7668 | else if (treg == 0) |
67c0d1eb | 7669 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7670 | else |
7671 | { | |
67c0d1eb RS |
7672 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7673 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7674 | } |
8fc2e39e | 7675 | break; |
252b5132 RH |
7676 | |
7677 | case M_SNE_I: | |
7678 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7679 | { | |
67c0d1eb | 7680 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7681 | break; |
252b5132 RH |
7682 | } |
7683 | if (sreg == 0) | |
7684 | { | |
7685 | as_warn (_("Instruction %s: result is always true"), | |
7686 | ip->insn_mo->name); | |
67c0d1eb RS |
7687 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7688 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7689 | break; |
252b5132 RH |
7690 | } |
7691 | if (imm_expr.X_op == O_constant | |
7692 | && imm_expr.X_add_number >= 0 | |
7693 | && imm_expr.X_add_number < 0x10000) | |
7694 | { | |
67c0d1eb | 7695 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7696 | } |
7697 | else if (imm_expr.X_op == O_constant | |
7698 | && imm_expr.X_add_number > -0x8000 | |
7699 | && imm_expr.X_add_number < 0) | |
7700 | { | |
7701 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7702 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7703 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7704 | } |
7705 | else | |
7706 | { | |
67c0d1eb RS |
7707 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7708 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7709 | used_at = 1; |
7710 | } | |
67c0d1eb | 7711 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7712 | break; |
252b5132 RH |
7713 | |
7714 | case M_DSUB_I: | |
7715 | dbl = 1; | |
7716 | case M_SUB_I: | |
7717 | if (imm_expr.X_op == O_constant | |
7718 | && imm_expr.X_add_number > -0x8000 | |
7719 | && imm_expr.X_add_number <= 0x8000) | |
7720 | { | |
7721 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7722 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7723 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7724 | break; |
252b5132 | 7725 | } |
8fc2e39e | 7726 | used_at = 1; |
67c0d1eb RS |
7727 | load_register (AT, &imm_expr, dbl); |
7728 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7729 | break; |
7730 | ||
7731 | case M_DSUBU_I: | |
7732 | dbl = 1; | |
7733 | case M_SUBU_I: | |
7734 | if (imm_expr.X_op == O_constant | |
7735 | && imm_expr.X_add_number > -0x8000 | |
7736 | && imm_expr.X_add_number <= 0x8000) | |
7737 | { | |
7738 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7739 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7740 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7741 | break; |
252b5132 | 7742 | } |
8fc2e39e | 7743 | used_at = 1; |
67c0d1eb RS |
7744 | load_register (AT, &imm_expr, dbl); |
7745 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7746 | break; |
7747 | ||
7748 | case M_TEQ_I: | |
7749 | s = "teq"; | |
7750 | goto trap; | |
7751 | case M_TGE_I: | |
7752 | s = "tge"; | |
7753 | goto trap; | |
7754 | case M_TGEU_I: | |
7755 | s = "tgeu"; | |
7756 | goto trap; | |
7757 | case M_TLT_I: | |
7758 | s = "tlt"; | |
7759 | goto trap; | |
7760 | case M_TLTU_I: | |
7761 | s = "tltu"; | |
7762 | goto trap; | |
7763 | case M_TNE_I: | |
7764 | s = "tne"; | |
7765 | trap: | |
8fc2e39e | 7766 | used_at = 1; |
67c0d1eb RS |
7767 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7768 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7769 | break; |
7770 | ||
252b5132 | 7771 | case M_TRUNCWS: |
43841e91 | 7772 | case M_TRUNCWD: |
e7af610e | 7773 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7774 | used_at = 1; |
252b5132 RH |
7775 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7776 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7777 | ||
7778 | /* | |
7779 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7780 | * or is there a reason for it? | |
7781 | */ | |
7d10b47d | 7782 | start_noreorder (); |
67c0d1eb RS |
7783 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7784 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7785 | macro_build (NULL, "nop", ""); | |
252b5132 | 7786 | expr1.X_add_number = 3; |
67c0d1eb | 7787 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7788 | expr1.X_add_number = 2; |
67c0d1eb RS |
7789 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7790 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7791 | macro_build (NULL, "nop", ""); | |
7792 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7793 | dreg, sreg); | |
7794 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7795 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7796 | end_noreorder (); |
252b5132 RH |
7797 | break; |
7798 | ||
7799 | case M_ULH: | |
7800 | s = "lb"; | |
7801 | goto ulh; | |
7802 | case M_ULHU: | |
7803 | s = "lbu"; | |
7804 | ulh: | |
8fc2e39e | 7805 | used_at = 1; |
252b5132 RH |
7806 | if (offset_expr.X_add_number >= 0x7fff) |
7807 | as_bad (_("operand overflow")); | |
252b5132 | 7808 | if (! target_big_endian) |
f9419b05 | 7809 | ++offset_expr.X_add_number; |
67c0d1eb | 7810 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7811 | if (! target_big_endian) |
f9419b05 | 7812 | --offset_expr.X_add_number; |
252b5132 | 7813 | else |
f9419b05 | 7814 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7815 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7816 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7817 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7818 | break; |
7819 | ||
7820 | case M_ULD: | |
7821 | s = "ldl"; | |
7822 | s2 = "ldr"; | |
7823 | off = 7; | |
7824 | goto ulw; | |
7825 | case M_ULW: | |
7826 | s = "lwl"; | |
7827 | s2 = "lwr"; | |
7828 | off = 3; | |
7829 | ulw: | |
7830 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7831 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7832 | if (treg != breg) |
7833 | tempreg = treg; | |
7834 | else | |
8fc2e39e TS |
7835 | { |
7836 | used_at = 1; | |
7837 | tempreg = AT; | |
7838 | } | |
252b5132 RH |
7839 | if (! target_big_endian) |
7840 | offset_expr.X_add_number += off; | |
67c0d1eb | 7841 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7842 | if (! target_big_endian) |
7843 | offset_expr.X_add_number -= off; | |
7844 | else | |
7845 | offset_expr.X_add_number += off; | |
67c0d1eb | 7846 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7847 | |
7848 | /* If necessary, move the result in tempreg the final destination. */ | |
7849 | if (treg == tempreg) | |
8fc2e39e | 7850 | break; |
af22f5b2 | 7851 | /* Protect second load's delay slot. */ |
017315e4 | 7852 | load_delay_nop (); |
67c0d1eb | 7853 | move_register (treg, tempreg); |
af22f5b2 | 7854 | break; |
252b5132 RH |
7855 | |
7856 | case M_ULD_A: | |
7857 | s = "ldl"; | |
7858 | s2 = "ldr"; | |
7859 | off = 7; | |
7860 | goto ulwa; | |
7861 | case M_ULW_A: | |
7862 | s = "lwl"; | |
7863 | s2 = "lwr"; | |
7864 | off = 3; | |
7865 | ulwa: | |
d6bc6245 | 7866 | used_at = 1; |
67c0d1eb | 7867 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7868 | if (breg != 0) |
67c0d1eb | 7869 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7870 | if (! target_big_endian) |
7871 | expr1.X_add_number = off; | |
7872 | else | |
7873 | expr1.X_add_number = 0; | |
67c0d1eb | 7874 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7875 | if (! target_big_endian) |
7876 | expr1.X_add_number = 0; | |
7877 | else | |
7878 | expr1.X_add_number = off; | |
67c0d1eb | 7879 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7880 | break; |
7881 | ||
7882 | case M_ULH_A: | |
7883 | case M_ULHU_A: | |
d6bc6245 | 7884 | used_at = 1; |
67c0d1eb | 7885 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7886 | if (breg != 0) |
67c0d1eb | 7887 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7888 | if (target_big_endian) |
7889 | expr1.X_add_number = 0; | |
67c0d1eb | 7890 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7891 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7892 | if (target_big_endian) |
7893 | expr1.X_add_number = 1; | |
7894 | else | |
7895 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7896 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7897 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7898 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7899 | break; |
7900 | ||
7901 | case M_USH: | |
8fc2e39e | 7902 | used_at = 1; |
252b5132 RH |
7903 | if (offset_expr.X_add_number >= 0x7fff) |
7904 | as_bad (_("operand overflow")); | |
7905 | if (target_big_endian) | |
f9419b05 | 7906 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7907 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7908 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7909 | if (target_big_endian) |
f9419b05 | 7910 | --offset_expr.X_add_number; |
252b5132 | 7911 | else |
f9419b05 | 7912 | ++offset_expr.X_add_number; |
67c0d1eb | 7913 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7914 | break; |
7915 | ||
7916 | case M_USD: | |
7917 | s = "sdl"; | |
7918 | s2 = "sdr"; | |
7919 | off = 7; | |
7920 | goto usw; | |
7921 | case M_USW: | |
7922 | s = "swl"; | |
7923 | s2 = "swr"; | |
7924 | off = 3; | |
7925 | usw: | |
7926 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7927 | as_bad (_("operand overflow")); | |
7928 | if (! target_big_endian) | |
7929 | offset_expr.X_add_number += off; | |
67c0d1eb | 7930 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7931 | if (! target_big_endian) |
7932 | offset_expr.X_add_number -= off; | |
7933 | else | |
7934 | offset_expr.X_add_number += off; | |
67c0d1eb | 7935 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7936 | break; |
252b5132 RH |
7937 | |
7938 | case M_USD_A: | |
7939 | s = "sdl"; | |
7940 | s2 = "sdr"; | |
7941 | off = 7; | |
7942 | goto uswa; | |
7943 | case M_USW_A: | |
7944 | s = "swl"; | |
7945 | s2 = "swr"; | |
7946 | off = 3; | |
7947 | uswa: | |
d6bc6245 | 7948 | used_at = 1; |
67c0d1eb | 7949 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7950 | if (breg != 0) |
67c0d1eb | 7951 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7952 | if (! target_big_endian) |
7953 | expr1.X_add_number = off; | |
7954 | else | |
7955 | expr1.X_add_number = 0; | |
67c0d1eb | 7956 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7957 | if (! target_big_endian) |
7958 | expr1.X_add_number = 0; | |
7959 | else | |
7960 | expr1.X_add_number = off; | |
67c0d1eb | 7961 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7962 | break; |
7963 | ||
7964 | case M_USH_A: | |
d6bc6245 | 7965 | used_at = 1; |
67c0d1eb | 7966 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7967 | if (breg != 0) |
67c0d1eb | 7968 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7969 | if (! target_big_endian) |
7970 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7971 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7972 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7973 | if (! target_big_endian) |
7974 | expr1.X_add_number = 1; | |
7975 | else | |
7976 | expr1.X_add_number = 0; | |
67c0d1eb | 7977 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7978 | if (! target_big_endian) |
7979 | expr1.X_add_number = 0; | |
7980 | else | |
7981 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7982 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7983 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7984 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7985 | break; |
7986 | ||
7987 | default: | |
7988 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7989 | are added dynamically. */ |
252b5132 RH |
7990 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7991 | break; | |
7992 | } | |
741fe287 | 7993 | if (!mips_opts.at && used_at) |
8fc2e39e | 7994 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
7995 | } |
7996 | ||
7997 | /* Implement macros in mips16 mode. */ | |
7998 | ||
7999 | static void | |
17a2f251 | 8000 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8001 | { |
8002 | int mask; | |
8003 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8004 | expressionS expr1; |
8005 | int dbl; | |
8006 | const char *s, *s2, *s3; | |
8007 | ||
8008 | mask = ip->insn_mo->mask; | |
8009 | ||
bf12938e RS |
8010 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8011 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8012 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8013 | |
252b5132 RH |
8014 | expr1.X_op = O_constant; |
8015 | expr1.X_op_symbol = NULL; | |
8016 | expr1.X_add_symbol = NULL; | |
8017 | expr1.X_add_number = 1; | |
8018 | ||
8019 | dbl = 0; | |
8020 | ||
8021 | switch (mask) | |
8022 | { | |
8023 | default: | |
8024 | internalError (); | |
8025 | ||
8026 | case M_DDIV_3: | |
8027 | dbl = 1; | |
8028 | case M_DIV_3: | |
8029 | s = "mflo"; | |
8030 | goto do_div3; | |
8031 | case M_DREM_3: | |
8032 | dbl = 1; | |
8033 | case M_REM_3: | |
8034 | s = "mfhi"; | |
8035 | do_div3: | |
7d10b47d | 8036 | start_noreorder (); |
67c0d1eb | 8037 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8038 | expr1.X_add_number = 2; |
67c0d1eb RS |
8039 | macro_build (&expr1, "bnez", "x,p", yreg); |
8040 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8041 | |
252b5132 RH |
8042 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8043 | since that causes an overflow. We should do that as well, | |
8044 | but I don't see how to do the comparisons without a temporary | |
8045 | register. */ | |
7d10b47d | 8046 | end_noreorder (); |
67c0d1eb | 8047 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8048 | break; |
8049 | ||
8050 | case M_DIVU_3: | |
8051 | s = "divu"; | |
8052 | s2 = "mflo"; | |
8053 | goto do_divu3; | |
8054 | case M_REMU_3: | |
8055 | s = "divu"; | |
8056 | s2 = "mfhi"; | |
8057 | goto do_divu3; | |
8058 | case M_DDIVU_3: | |
8059 | s = "ddivu"; | |
8060 | s2 = "mflo"; | |
8061 | goto do_divu3; | |
8062 | case M_DREMU_3: | |
8063 | s = "ddivu"; | |
8064 | s2 = "mfhi"; | |
8065 | do_divu3: | |
7d10b47d | 8066 | start_noreorder (); |
67c0d1eb | 8067 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8068 | expr1.X_add_number = 2; |
67c0d1eb RS |
8069 | macro_build (&expr1, "bnez", "x,p", yreg); |
8070 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8071 | end_noreorder (); |
67c0d1eb | 8072 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8073 | break; |
8074 | ||
8075 | case M_DMUL: | |
8076 | dbl = 1; | |
8077 | case M_MUL: | |
67c0d1eb RS |
8078 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8079 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8080 | break; |
252b5132 RH |
8081 | |
8082 | case M_DSUBU_I: | |
8083 | dbl = 1; | |
8084 | goto do_subu; | |
8085 | case M_SUBU_I: | |
8086 | do_subu: | |
8087 | if (imm_expr.X_op != O_constant) | |
8088 | as_bad (_("Unsupported large constant")); | |
8089 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8090 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8091 | break; |
8092 | ||
8093 | case M_SUBU_I_2: | |
8094 | if (imm_expr.X_op != O_constant) | |
8095 | as_bad (_("Unsupported large constant")); | |
8096 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8097 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8098 | break; |
8099 | ||
8100 | case M_DSUBU_I_2: | |
8101 | if (imm_expr.X_op != O_constant) | |
8102 | as_bad (_("Unsupported large constant")); | |
8103 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8104 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8105 | break; |
8106 | ||
8107 | case M_BEQ: | |
8108 | s = "cmp"; | |
8109 | s2 = "bteqz"; | |
8110 | goto do_branch; | |
8111 | case M_BNE: | |
8112 | s = "cmp"; | |
8113 | s2 = "btnez"; | |
8114 | goto do_branch; | |
8115 | case M_BLT: | |
8116 | s = "slt"; | |
8117 | s2 = "btnez"; | |
8118 | goto do_branch; | |
8119 | case M_BLTU: | |
8120 | s = "sltu"; | |
8121 | s2 = "btnez"; | |
8122 | goto do_branch; | |
8123 | case M_BLE: | |
8124 | s = "slt"; | |
8125 | s2 = "bteqz"; | |
8126 | goto do_reverse_branch; | |
8127 | case M_BLEU: | |
8128 | s = "sltu"; | |
8129 | s2 = "bteqz"; | |
8130 | goto do_reverse_branch; | |
8131 | case M_BGE: | |
8132 | s = "slt"; | |
8133 | s2 = "bteqz"; | |
8134 | goto do_branch; | |
8135 | case M_BGEU: | |
8136 | s = "sltu"; | |
8137 | s2 = "bteqz"; | |
8138 | goto do_branch; | |
8139 | case M_BGT: | |
8140 | s = "slt"; | |
8141 | s2 = "btnez"; | |
8142 | goto do_reverse_branch; | |
8143 | case M_BGTU: | |
8144 | s = "sltu"; | |
8145 | s2 = "btnez"; | |
8146 | ||
8147 | do_reverse_branch: | |
8148 | tmp = xreg; | |
8149 | xreg = yreg; | |
8150 | yreg = tmp; | |
8151 | ||
8152 | do_branch: | |
67c0d1eb RS |
8153 | macro_build (NULL, s, "x,y", xreg, yreg); |
8154 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8155 | break; |
8156 | ||
8157 | case M_BEQ_I: | |
8158 | s = "cmpi"; | |
8159 | s2 = "bteqz"; | |
8160 | s3 = "x,U"; | |
8161 | goto do_branch_i; | |
8162 | case M_BNE_I: | |
8163 | s = "cmpi"; | |
8164 | s2 = "btnez"; | |
8165 | s3 = "x,U"; | |
8166 | goto do_branch_i; | |
8167 | case M_BLT_I: | |
8168 | s = "slti"; | |
8169 | s2 = "btnez"; | |
8170 | s3 = "x,8"; | |
8171 | goto do_branch_i; | |
8172 | case M_BLTU_I: | |
8173 | s = "sltiu"; | |
8174 | s2 = "btnez"; | |
8175 | s3 = "x,8"; | |
8176 | goto do_branch_i; | |
8177 | case M_BLE_I: | |
8178 | s = "slti"; | |
8179 | s2 = "btnez"; | |
8180 | s3 = "x,8"; | |
8181 | goto do_addone_branch_i; | |
8182 | case M_BLEU_I: | |
8183 | s = "sltiu"; | |
8184 | s2 = "btnez"; | |
8185 | s3 = "x,8"; | |
8186 | goto do_addone_branch_i; | |
8187 | case M_BGE_I: | |
8188 | s = "slti"; | |
8189 | s2 = "bteqz"; | |
8190 | s3 = "x,8"; | |
8191 | goto do_branch_i; | |
8192 | case M_BGEU_I: | |
8193 | s = "sltiu"; | |
8194 | s2 = "bteqz"; | |
8195 | s3 = "x,8"; | |
8196 | goto do_branch_i; | |
8197 | case M_BGT_I: | |
8198 | s = "slti"; | |
8199 | s2 = "bteqz"; | |
8200 | s3 = "x,8"; | |
8201 | goto do_addone_branch_i; | |
8202 | case M_BGTU_I: | |
8203 | s = "sltiu"; | |
8204 | s2 = "bteqz"; | |
8205 | s3 = "x,8"; | |
8206 | ||
8207 | do_addone_branch_i: | |
8208 | if (imm_expr.X_op != O_constant) | |
8209 | as_bad (_("Unsupported large constant")); | |
8210 | ++imm_expr.X_add_number; | |
8211 | ||
8212 | do_branch_i: | |
67c0d1eb RS |
8213 | macro_build (&imm_expr, s, s3, xreg); |
8214 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8215 | break; |
8216 | ||
8217 | case M_ABS: | |
8218 | expr1.X_add_number = 0; | |
67c0d1eb | 8219 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8220 | if (xreg != yreg) |
67c0d1eb | 8221 | move_register (xreg, yreg); |
252b5132 | 8222 | expr1.X_add_number = 2; |
67c0d1eb RS |
8223 | macro_build (&expr1, "bteqz", "p"); |
8224 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8225 | } |
8226 | } | |
8227 | ||
8228 | /* For consistency checking, verify that all bits are specified either | |
8229 | by the match/mask part of the instruction definition, or by the | |
8230 | operand list. */ | |
8231 | static int | |
17a2f251 | 8232 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8233 | { |
8234 | const char *p = opc->args; | |
8235 | char c; | |
8236 | unsigned long used_bits = opc->mask; | |
8237 | ||
8238 | if ((used_bits & opc->match) != opc->match) | |
8239 | { | |
8240 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8241 | opc->name, opc->args); | |
8242 | return 0; | |
8243 | } | |
8244 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8245 | while (*p) | |
8246 | switch (c = *p++) | |
8247 | { | |
8248 | case ',': break; | |
8249 | case '(': break; | |
8250 | case ')': break; | |
af7ee8bf CD |
8251 | case '+': |
8252 | switch (c = *p++) | |
8253 | { | |
9bcd4f99 TS |
8254 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8255 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8256 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8257 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8258 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8259 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8260 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8261 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8262 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8263 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8264 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8265 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8266 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8267 | case 'I': break; | |
ef2e4d86 CF |
8268 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8269 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8270 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8271 | default: |
8272 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8273 | c, opc->name, opc->args); | |
8274 | return 0; | |
8275 | } | |
8276 | break; | |
252b5132 RH |
8277 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8278 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8279 | case 'A': break; | |
4372b673 | 8280 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8281 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8282 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8283 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8284 | case 'F': break; | |
8285 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8286 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8287 | case 'I': break; |
e972090a | 8288 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8289 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8290 | case 'L': break; |
8291 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8292 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8293 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8294 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8295 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8296 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8297 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8298 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8299 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8300 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8301 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8302 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8303 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8304 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8305 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8306 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8307 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8308 | case 'f': break; | |
8309 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8310 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8311 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8312 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8313 | case 'l': break; | |
8314 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8315 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8316 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8317 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8318 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8319 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8320 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8321 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8322 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8323 | case 'x': break; | |
8324 | case 'z': break; | |
8325 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8326 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8327 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8328 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8329 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8330 | case '[': break; | |
8331 | case ']': break; | |
8b082fb1 | 8332 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8333 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8334 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8335 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8336 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8337 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8338 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8339 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8340 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8341 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8342 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8343 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8344 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8345 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8346 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8347 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8348 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8349 | default: |
8350 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8351 | c, opc->name, opc->args); | |
8352 | return 0; | |
8353 | } | |
8354 | #undef USE_BITS | |
8355 | if (used_bits != 0xffffffff) | |
8356 | { | |
8357 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8358 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8359 | return 0; | |
8360 | } | |
8361 | return 1; | |
8362 | } | |
8363 | ||
9bcd4f99 TS |
8364 | /* UDI immediates. */ |
8365 | struct mips_immed { | |
8366 | char type; | |
8367 | unsigned int shift; | |
8368 | unsigned long mask; | |
8369 | const char * desc; | |
8370 | }; | |
8371 | ||
8372 | static const struct mips_immed mips_immed[] = { | |
8373 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8374 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8375 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8376 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8377 | { 0,0,0,0 } | |
8378 | }; | |
8379 | ||
7455baf8 TS |
8380 | /* Check whether an odd floating-point register is allowed. */ |
8381 | static int | |
8382 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8383 | { | |
8384 | const char *s = insn->name; | |
8385 | ||
8386 | if (insn->pinfo == INSN_MACRO) | |
8387 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8388 | return 1; | |
8389 | ||
8390 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8391 | { | |
8392 | /* Allow odd registers for single-precision ops. */ | |
8393 | switch (insn->pinfo & (FP_S | FP_D)) | |
8394 | { | |
8395 | case FP_S: | |
8396 | case 0: | |
8397 | return 1; /* both single precision - ok */ | |
8398 | case FP_D: | |
8399 | return 0; /* both double precision - fail */ | |
8400 | default: | |
8401 | break; | |
8402 | } | |
8403 | ||
8404 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8405 | s = strchr (insn->name, '.'); | |
8406 | if (argnum == 2) | |
8407 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8408 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8409 | } | |
8410 | ||
8411 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8412 | if ((insn->pinfo & FP_S) | |
8413 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8414 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8415 | return 1; | |
8416 | ||
8417 | return 0; | |
8418 | } | |
8419 | ||
252b5132 RH |
8420 | /* This routine assembles an instruction into its binary format. As a |
8421 | side effect, it sets one of the global variables imm_reloc or | |
8422 | offset_reloc to the type of relocation to do if one of the operands | |
8423 | is an address expression. */ | |
8424 | ||
8425 | static void | |
17a2f251 | 8426 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8427 | { |
8428 | char *s; | |
8429 | const char *args; | |
43841e91 | 8430 | char c = 0; |
252b5132 RH |
8431 | struct mips_opcode *insn; |
8432 | char *argsStart; | |
8433 | unsigned int regno; | |
8434 | unsigned int lastregno = 0; | |
af7ee8bf | 8435 | unsigned int lastpos = 0; |
071742cf | 8436 | unsigned int limlo, limhi; |
252b5132 RH |
8437 | char *s_reset; |
8438 | char save_c = 0; | |
74cd071d | 8439 | offsetT min_range, max_range; |
707bfff6 TS |
8440 | int argnum; |
8441 | unsigned int rtype; | |
252b5132 RH |
8442 | |
8443 | insn_error = NULL; | |
8444 | ||
8445 | /* If the instruction contains a '.', we first try to match an instruction | |
8446 | including the '.'. Then we try again without the '.'. */ | |
8447 | insn = NULL; | |
3882b010 | 8448 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8449 | continue; |
8450 | ||
8451 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8452 | the call to hash_find. Save the character we replaced just in case we | |
8453 | have to re-parse the instruction. */ | |
3882b010 | 8454 | if (ISSPACE (*s)) |
252b5132 RH |
8455 | { |
8456 | save_c = *s; | |
8457 | *s++ = '\0'; | |
8458 | } | |
bdaaa2e1 | 8459 | |
252b5132 RH |
8460 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8461 | ||
8462 | /* If we didn't find the instruction in the opcode table, try again, but | |
8463 | this time with just the instruction up to, but not including the | |
8464 | first '.'. */ | |
8465 | if (insn == NULL) | |
8466 | { | |
bdaaa2e1 | 8467 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8468 | if (save_c) |
8469 | *(--s) = save_c; | |
8470 | ||
8471 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8472 | for (s = str; |
8473 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8474 | ++s) | |
252b5132 RH |
8475 | continue; |
8476 | ||
8477 | /* If we did not find a '.', then we can quit now. */ | |
8478 | if (*s != '.') | |
8479 | { | |
8480 | insn_error = "unrecognized opcode"; | |
8481 | return; | |
8482 | } | |
8483 | ||
8484 | /* Lookup the instruction in the hash table. */ | |
8485 | *s++ = '\0'; | |
8486 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8487 | { | |
8488 | insn_error = "unrecognized opcode"; | |
8489 | return; | |
8490 | } | |
252b5132 RH |
8491 | } |
8492 | ||
8493 | argsStart = s; | |
8494 | for (;;) | |
8495 | { | |
b34976b6 | 8496 | bfd_boolean ok; |
252b5132 RH |
8497 | |
8498 | assert (strcmp (insn->name, str) == 0); | |
8499 | ||
037b32b9 | 8500 | ok = is_opcode_valid (insn, FALSE); |
252b5132 RH |
8501 | if (! ok) |
8502 | { | |
8503 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8504 | && strcmp (insn->name, insn[1].name) == 0) | |
8505 | { | |
8506 | ++insn; | |
8507 | continue; | |
8508 | } | |
252b5132 | 8509 | else |
beae10d5 | 8510 | { |
268f6bed L |
8511 | if (!insn_error) |
8512 | { | |
8513 | static char buf[100]; | |
fef14a42 TS |
8514 | sprintf (buf, |
8515 | _("opcode not supported on this processor: %s (%s)"), | |
8516 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8517 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8518 | insn_error = buf; |
8519 | } | |
8520 | if (save_c) | |
8521 | *(--s) = save_c; | |
2bd7f1f3 | 8522 | return; |
252b5132 | 8523 | } |
252b5132 RH |
8524 | } |
8525 | ||
1e915849 | 8526 | create_insn (ip, insn); |
268f6bed | 8527 | insn_error = NULL; |
707bfff6 | 8528 | argnum = 1; |
252b5132 RH |
8529 | for (args = insn->args;; ++args) |
8530 | { | |
deec1734 CD |
8531 | int is_mdmx; |
8532 | ||
ad8d3bb3 | 8533 | s += strspn (s, " \t"); |
deec1734 | 8534 | is_mdmx = 0; |
252b5132 RH |
8535 | switch (*args) |
8536 | { | |
8537 | case '\0': /* end of args */ | |
8538 | if (*s == '\0') | |
8539 | return; | |
8540 | break; | |
8541 | ||
8b082fb1 TS |
8542 | case '2': /* dsp 2-bit unsigned immediate in bit 11 */ |
8543 | my_getExpression (&imm_expr, s); | |
8544 | check_absolute_expr (ip, &imm_expr); | |
8545 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8546 | && (unsigned long) imm_expr.X_add_number != 3) | |
8547 | { | |
8548 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8549 | (unsigned long) imm_expr.X_add_number); | |
8550 | } | |
8551 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8552 | imm_expr.X_op = O_absent; | |
8553 | s = expr_end; | |
8554 | continue; | |
8555 | ||
74cd071d CF |
8556 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8557 | my_getExpression (&imm_expr, s); | |
8558 | check_absolute_expr (ip, &imm_expr); | |
8559 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8560 | { | |
a9e24354 TS |
8561 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8562 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8563 | } |
a9e24354 | 8564 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8565 | imm_expr.X_op = O_absent; |
8566 | s = expr_end; | |
8567 | continue; | |
8568 | ||
8569 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8570 | my_getExpression (&imm_expr, s); | |
8571 | check_absolute_expr (ip, &imm_expr); | |
8572 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8573 | { | |
a9e24354 TS |
8574 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8575 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8576 | } |
a9e24354 | 8577 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8578 | imm_expr.X_op = O_absent; |
8579 | s = expr_end; | |
8580 | continue; | |
8581 | ||
8582 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8583 | my_getExpression (&imm_expr, s); | |
8584 | check_absolute_expr (ip, &imm_expr); | |
8585 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8586 | { | |
a9e24354 TS |
8587 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8588 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8589 | } |
a9e24354 | 8590 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8591 | imm_expr.X_op = O_absent; |
8592 | s = expr_end; | |
8593 | continue; | |
8594 | ||
8595 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8596 | my_getExpression (&imm_expr, s); | |
8597 | check_absolute_expr (ip, &imm_expr); | |
8598 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8599 | { | |
a9e24354 TS |
8600 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8601 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8602 | } |
a9e24354 | 8603 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8604 | imm_expr.X_op = O_absent; |
8605 | s = expr_end; | |
8606 | continue; | |
8607 | ||
8608 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8609 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8610 | s[3] >= '0' && s[3] <= '3') | |
8611 | { | |
8612 | regno = s[3] - '0'; | |
8613 | s += 4; | |
a9e24354 | 8614 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8615 | continue; |
8616 | } | |
8617 | else | |
8618 | as_bad (_("Invalid dsp acc register")); | |
8619 | break; | |
8620 | ||
8621 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8622 | my_getExpression (&imm_expr, s); | |
8623 | check_absolute_expr (ip, &imm_expr); | |
8624 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8625 | { | |
a9e24354 TS |
8626 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8627 | OP_MASK_WRDSP, | |
8628 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8629 | } |
a9e24354 | 8630 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8631 | imm_expr.X_op = O_absent; |
8632 | s = expr_end; | |
8633 | continue; | |
8634 | ||
8635 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8636 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8637 | s[3] >= '0' && s[3] <= '3') | |
8638 | { | |
8639 | regno = s[3] - '0'; | |
8640 | s += 4; | |
a9e24354 | 8641 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8642 | continue; |
8643 | } | |
8644 | else | |
8645 | as_bad (_("Invalid dsp acc register")); | |
8646 | break; | |
8647 | ||
8648 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8649 | my_getExpression (&imm_expr, s); | |
8650 | check_absolute_expr (ip, &imm_expr); | |
8651 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8652 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8653 | if (imm_expr.X_add_number < min_range || | |
8654 | imm_expr.X_add_number > max_range) | |
8655 | { | |
a9e24354 TS |
8656 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8657 | (long) min_range, (long) max_range, | |
8658 | (long) imm_expr.X_add_number); | |
74cd071d | 8659 | } |
a9e24354 | 8660 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8661 | imm_expr.X_op = O_absent; |
8662 | s = expr_end; | |
8663 | continue; | |
8664 | ||
8665 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8666 | my_getExpression (&imm_expr, s); | |
8667 | check_absolute_expr (ip, &imm_expr); | |
8668 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8669 | { | |
a9e24354 TS |
8670 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8671 | OP_MASK_RDDSP, | |
8672 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8673 | } |
a9e24354 | 8674 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8675 | imm_expr.X_op = O_absent; |
8676 | s = expr_end; | |
8677 | continue; | |
8678 | ||
8679 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8680 | my_getExpression (&imm_expr, s); | |
8681 | check_absolute_expr (ip, &imm_expr); | |
8682 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8683 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8684 | if (imm_expr.X_add_number < min_range || | |
8685 | imm_expr.X_add_number > max_range) | |
8686 | { | |
a9e24354 TS |
8687 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8688 | (long) min_range, (long) max_range, | |
8689 | (long) imm_expr.X_add_number); | |
74cd071d | 8690 | } |
a9e24354 | 8691 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8692 | imm_expr.X_op = O_absent; |
8693 | s = expr_end; | |
8694 | continue; | |
8695 | ||
8696 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8697 | my_getExpression (&imm_expr, s); | |
8698 | check_absolute_expr (ip, &imm_expr); | |
8699 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8700 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8701 | if (imm_expr.X_add_number < min_range || | |
8702 | imm_expr.X_add_number > max_range) | |
8703 | { | |
a9e24354 TS |
8704 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8705 | (long) min_range, (long) max_range, | |
8706 | (long) imm_expr.X_add_number); | |
74cd071d | 8707 | } |
a9e24354 | 8708 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8709 | imm_expr.X_op = O_absent; |
8710 | s = expr_end; | |
8711 | continue; | |
8712 | ||
a9e24354 | 8713 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8714 | my_getExpression (&imm_expr, s); |
8715 | check_absolute_expr (ip, &imm_expr); | |
8716 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8717 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8718 | (unsigned long) imm_expr.X_add_number); | |
8719 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8720 | imm_expr.X_op = O_absent; |
8721 | s = expr_end; | |
8722 | continue; | |
8723 | ||
a9e24354 | 8724 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8725 | my_getExpression (&imm_expr, s); |
8726 | check_absolute_expr (ip, &imm_expr); | |
8727 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8728 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8729 | (unsigned long) imm_expr.X_add_number); | |
8730 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8731 | imm_expr.X_op = O_absent; |
8732 | s = expr_end; | |
8733 | continue; | |
8734 | ||
8735 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8736 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8737 | s[3] >= '0' && s[3] <= '3') | |
8738 | { | |
8739 | regno = s[3] - '0'; | |
8740 | s += 4; | |
a9e24354 | 8741 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8742 | continue; |
8743 | } | |
8744 | else | |
8745 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8746 | break; | |
8747 | ||
8748 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8749 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8750 | s[3] >= '0' && s[3] <= '3') | |
8751 | { | |
8752 | regno = s[3] - '0'; | |
8753 | s += 4; | |
a9e24354 | 8754 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8755 | continue; |
8756 | } | |
8757 | else | |
8758 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8759 | break; | |
8760 | ||
252b5132 | 8761 | case ',': |
a339155f | 8762 | ++argnum; |
252b5132 RH |
8763 | if (*s++ == *args) |
8764 | continue; | |
8765 | s--; | |
8766 | switch (*++args) | |
8767 | { | |
8768 | case 'r': | |
8769 | case 'v': | |
bf12938e | 8770 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8771 | continue; |
8772 | ||
8773 | case 'w': | |
bf12938e | 8774 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8775 | continue; |
8776 | ||
252b5132 | 8777 | case 'W': |
bf12938e | 8778 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8779 | continue; |
8780 | ||
8781 | case 'V': | |
bf12938e | 8782 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8783 | continue; |
8784 | } | |
8785 | break; | |
8786 | ||
8787 | case '(': | |
8788 | /* Handle optional base register. | |
8789 | Either the base register is omitted or | |
bdaaa2e1 | 8790 | we must have a left paren. */ |
252b5132 RH |
8791 | /* This is dependent on the next operand specifier |
8792 | is a base register specification. */ | |
8793 | assert (args[1] == 'b' || args[1] == '5' | |
8794 | || args[1] == '-' || args[1] == '4'); | |
8795 | if (*s == '\0') | |
8796 | return; | |
8797 | ||
8798 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8799 | case '[': |
8800 | case ']': | |
252b5132 RH |
8801 | if (*s++ == *args) |
8802 | continue; | |
8803 | break; | |
8804 | ||
af7ee8bf CD |
8805 | case '+': /* Opcode extension character. */ |
8806 | switch (*++args) | |
8807 | { | |
9bcd4f99 TS |
8808 | case '1': /* UDI immediates. */ |
8809 | case '2': | |
8810 | case '3': | |
8811 | case '4': | |
8812 | { | |
8813 | const struct mips_immed *imm = mips_immed; | |
8814 | ||
8815 | while (imm->type && imm->type != *args) | |
8816 | ++imm; | |
8817 | if (! imm->type) | |
8818 | internalError (); | |
8819 | my_getExpression (&imm_expr, s); | |
8820 | check_absolute_expr (ip, &imm_expr); | |
8821 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8822 | { | |
8823 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8824 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8825 | (unsigned long) imm_expr.X_add_number, | |
8826 | (unsigned long) imm_expr.X_add_number); | |
8827 | imm_expr.X_add_number &= imm->mask; | |
8828 | } | |
8829 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8830 | << imm->shift); | |
8831 | imm_expr.X_op = O_absent; | |
8832 | s = expr_end; | |
8833 | } | |
8834 | continue; | |
8835 | ||
071742cf CD |
8836 | case 'A': /* ins/ext position, becomes LSB. */ |
8837 | limlo = 0; | |
8838 | limhi = 31; | |
5f74bc13 CD |
8839 | goto do_lsb; |
8840 | case 'E': | |
8841 | limlo = 32; | |
8842 | limhi = 63; | |
8843 | goto do_lsb; | |
8844 | do_lsb: | |
071742cf CD |
8845 | my_getExpression (&imm_expr, s); |
8846 | check_absolute_expr (ip, &imm_expr); | |
8847 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8848 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8849 | { | |
8850 | as_bad (_("Improper position (%lu)"), | |
8851 | (unsigned long) imm_expr.X_add_number); | |
8852 | imm_expr.X_add_number = limlo; | |
8853 | } | |
8854 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8855 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8856 | imm_expr.X_op = O_absent; |
8857 | s = expr_end; | |
8858 | continue; | |
8859 | ||
8860 | case 'B': /* ins size, becomes MSB. */ | |
8861 | limlo = 1; | |
8862 | limhi = 32; | |
5f74bc13 CD |
8863 | goto do_msb; |
8864 | case 'F': | |
8865 | limlo = 33; | |
8866 | limhi = 64; | |
8867 | goto do_msb; | |
8868 | do_msb: | |
071742cf CD |
8869 | my_getExpression (&imm_expr, s); |
8870 | check_absolute_expr (ip, &imm_expr); | |
8871 | /* Check for negative input so that small negative numbers | |
8872 | will not succeed incorrectly. The checks against | |
8873 | (pos+size) transitively check "size" itself, | |
8874 | assuming that "pos" is reasonable. */ | |
8875 | if ((long) imm_expr.X_add_number < 0 | |
8876 | || ((unsigned long) imm_expr.X_add_number | |
8877 | + lastpos) < limlo | |
8878 | || ((unsigned long) imm_expr.X_add_number | |
8879 | + lastpos) > limhi) | |
8880 | { | |
8881 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8882 | (unsigned long) imm_expr.X_add_number, | |
8883 | (unsigned long) lastpos); | |
8884 | imm_expr.X_add_number = limlo - lastpos; | |
8885 | } | |
bf12938e RS |
8886 | INSERT_OPERAND (INSMSB, *ip, |
8887 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8888 | imm_expr.X_op = O_absent; |
8889 | s = expr_end; | |
8890 | continue; | |
8891 | ||
8892 | case 'C': /* ext size, becomes MSBD. */ | |
8893 | limlo = 1; | |
8894 | limhi = 32; | |
5f74bc13 CD |
8895 | goto do_msbd; |
8896 | case 'G': | |
8897 | limlo = 33; | |
8898 | limhi = 64; | |
8899 | goto do_msbd; | |
8900 | case 'H': | |
8901 | limlo = 33; | |
8902 | limhi = 64; | |
8903 | goto do_msbd; | |
8904 | do_msbd: | |
071742cf CD |
8905 | my_getExpression (&imm_expr, s); |
8906 | check_absolute_expr (ip, &imm_expr); | |
8907 | /* Check for negative input so that small negative numbers | |
8908 | will not succeed incorrectly. The checks against | |
8909 | (pos+size) transitively check "size" itself, | |
8910 | assuming that "pos" is reasonable. */ | |
8911 | if ((long) imm_expr.X_add_number < 0 | |
8912 | || ((unsigned long) imm_expr.X_add_number | |
8913 | + lastpos) < limlo | |
8914 | || ((unsigned long) imm_expr.X_add_number | |
8915 | + lastpos) > limhi) | |
8916 | { | |
8917 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8918 | (unsigned long) imm_expr.X_add_number, | |
8919 | (unsigned long) lastpos); | |
8920 | imm_expr.X_add_number = limlo - lastpos; | |
8921 | } | |
bf12938e | 8922 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8923 | imm_expr.X_op = O_absent; |
8924 | s = expr_end; | |
8925 | continue; | |
af7ee8bf | 8926 | |
bbcc0807 CD |
8927 | case 'D': |
8928 | /* +D is for disassembly only; never match. */ | |
8929 | break; | |
8930 | ||
5f74bc13 CD |
8931 | case 'I': |
8932 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8933 | my_getExpression (&imm2_expr, s); | |
8934 | if (imm2_expr.X_op != O_big | |
8935 | && imm2_expr.X_op != O_constant) | |
8936 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8937 | if (HAVE_32BIT_GPRS) |
8938 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8939 | s = expr_end; |
8940 | continue; | |
8941 | ||
707bfff6 | 8942 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
8943 | /* +T is for disassembly only; never match. */ |
8944 | break; | |
8945 | ||
707bfff6 | 8946 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
8947 | if (s[0] == '$' && ISDIGIT (s[1])) |
8948 | { | |
8949 | ++s; | |
8950 | regno = 0; | |
8951 | do | |
8952 | { | |
8953 | regno *= 10; | |
8954 | regno += *s - '0'; | |
8955 | ++s; | |
8956 | } | |
8957 | while (ISDIGIT (*s)); | |
8958 | if (regno > 31) | |
8959 | as_bad (_("Invalid register number (%d)"), regno); | |
8960 | else | |
8961 | { | |
a9e24354 | 8962 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
8963 | continue; |
8964 | } | |
8965 | } | |
8966 | else | |
8967 | as_bad (_("Invalid coprocessor 0 register number")); | |
8968 | break; | |
8969 | ||
af7ee8bf CD |
8970 | default: |
8971 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8972 | *args, insn->name, insn->args); | |
8973 | /* Further processing is fruitless. */ | |
8974 | return; | |
8975 | } | |
8976 | break; | |
8977 | ||
252b5132 RH |
8978 | case '<': /* must be at least one digit */ |
8979 | /* | |
8980 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8981 | * than 31 or less than 0, then the shift amount should be |
8982 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8983 | * We issue a warning and mask out all but the low 5 bits. |
8984 | */ | |
8985 | my_getExpression (&imm_expr, s); | |
8986 | check_absolute_expr (ip, &imm_expr); | |
8987 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8988 | as_warn (_("Improper shift amount (%lu)"), |
8989 | (unsigned long) imm_expr.X_add_number); | |
8990 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8991 | imm_expr.X_op = O_absent; |
8992 | s = expr_end; | |
8993 | continue; | |
8994 | ||
8995 | case '>': /* shift amount minus 32 */ | |
8996 | my_getExpression (&imm_expr, s); | |
8997 | check_absolute_expr (ip, &imm_expr); | |
8998 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8999 | || (unsigned long) imm_expr.X_add_number > 63) | |
9000 | break; | |
bf12938e | 9001 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9002 | imm_expr.X_op = O_absent; |
9003 | s = expr_end; | |
9004 | continue; | |
9005 | ||
252b5132 RH |
9006 | case 'k': /* cache code */ |
9007 | case 'h': /* prefx code */ | |
9008 | my_getExpression (&imm_expr, s); | |
9009 | check_absolute_expr (ip, &imm_expr); | |
9010 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9011 | as_warn (_("Invalid value for `%s' (%lu)"), |
9012 | ip->insn_mo->name, | |
9013 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9014 | if (*args == 'k') |
bf12938e | 9015 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 9016 | else |
bf12938e | 9017 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
9018 | imm_expr.X_op = O_absent; |
9019 | s = expr_end; | |
9020 | continue; | |
9021 | ||
9022 | case 'c': /* break code */ | |
9023 | my_getExpression (&imm_expr, s); | |
9024 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9025 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9026 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9027 | ip->insn_mo->name, | |
bf12938e RS |
9028 | (unsigned long) imm_expr.X_add_number); |
9029 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9030 | imm_expr.X_op = O_absent; |
9031 | s = expr_end; | |
9032 | continue; | |
9033 | ||
9034 | case 'q': /* lower break code */ | |
9035 | my_getExpression (&imm_expr, s); | |
9036 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9037 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9038 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9039 | ip->insn_mo->name, | |
bf12938e RS |
9040 | (unsigned long) imm_expr.X_add_number); |
9041 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9042 | imm_expr.X_op = O_absent; |
9043 | s = expr_end; | |
9044 | continue; | |
9045 | ||
4372b673 | 9046 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 9047 | my_getExpression (&imm_expr, s); |
156c2f8b | 9048 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9049 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9050 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9051 | ip->insn_mo->name, | |
793b27f4 | 9052 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9053 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9054 | imm_expr.X_op = O_absent; |
9055 | s = expr_end; | |
9056 | continue; | |
9057 | ||
98d3f06f | 9058 | case 'C': /* Coprocessor code */ |
beae10d5 | 9059 | my_getExpression (&imm_expr, s); |
252b5132 | 9060 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9061 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9062 | { |
793b27f4 TS |
9063 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9064 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9065 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9066 | } |
a9e24354 | 9067 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9068 | imm_expr.X_op = O_absent; |
9069 | s = expr_end; | |
9070 | continue; | |
252b5132 | 9071 | |
4372b673 NC |
9072 | case 'J': /* 19-bit wait code. */ |
9073 | my_getExpression (&imm_expr, s); | |
9074 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9075 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9076 | { |
9077 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9078 | (unsigned long) imm_expr.X_add_number); | |
9079 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9080 | } | |
bf12938e | 9081 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9082 | imm_expr.X_op = O_absent; |
9083 | s = expr_end; | |
9084 | continue; | |
9085 | ||
707bfff6 | 9086 | case 'P': /* Performance register. */ |
beae10d5 | 9087 | my_getExpression (&imm_expr, s); |
252b5132 | 9088 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9089 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9090 | as_warn (_("Invalid performance register (%lu)"), |
9091 | (unsigned long) imm_expr.X_add_number); | |
9092 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9093 | imm_expr.X_op = O_absent; |
9094 | s = expr_end; | |
9095 | continue; | |
252b5132 | 9096 | |
707bfff6 TS |
9097 | case 'G': /* Coprocessor destination register. */ |
9098 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9099 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9100 | else | |
9101 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9102 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9103 | if (ok) |
9104 | { | |
9105 | lastregno = regno; | |
9106 | continue; | |
9107 | } | |
9108 | else | |
9109 | break; | |
9110 | ||
252b5132 RH |
9111 | case 'b': /* base register */ |
9112 | case 'd': /* destination register */ | |
9113 | case 's': /* source register */ | |
9114 | case 't': /* target register */ | |
9115 | case 'r': /* both target and source */ | |
9116 | case 'v': /* both dest and source */ | |
9117 | case 'w': /* both dest and target */ | |
9118 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 9119 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
9120 | case 'x': /* ignore register name */ |
9121 | case 'z': /* must be zero register */ | |
4372b673 | 9122 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 9123 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
9124 | s_reset = s; |
9125 | if (*args == 'E' || *args == 'K') | |
9126 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9127 | else | |
9128 | { | |
9129 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9130 | if (regno == AT && mips_opts.at) |
9131 | { | |
9132 | if (mips_opts.at == ATREG) | |
9133 | as_warn (_("used $at without \".set noat\"")); | |
9134 | else | |
9135 | as_warn (_("used $%u with \".set at=$%u\""), | |
9136 | regno, mips_opts.at); | |
9137 | } | |
707bfff6 TS |
9138 | } |
9139 | if (ok) | |
252b5132 | 9140 | { |
252b5132 RH |
9141 | c = *args; |
9142 | if (*s == ' ') | |
f9419b05 | 9143 | ++s; |
252b5132 RH |
9144 | if (args[1] != *s) |
9145 | { | |
9146 | if (c == 'r' || c == 'v' || c == 'w') | |
9147 | { | |
9148 | regno = lastregno; | |
9149 | s = s_reset; | |
f9419b05 | 9150 | ++args; |
252b5132 RH |
9151 | } |
9152 | } | |
9153 | /* 'z' only matches $0. */ | |
9154 | if (c == 'z' && regno != 0) | |
9155 | break; | |
9156 | ||
e7c604dd CM |
9157 | if (c == 's' && !strcmp (ip->insn_mo->name, "jalr")) |
9158 | { | |
9159 | if (regno == lastregno) | |
9160 | { | |
9161 | insn_error = _("source and destinationations must be different"); | |
9162 | continue; | |
9163 | } | |
9164 | if (regno == 31 && lastregno == 0) | |
9165 | { | |
9166 | insn_error = _("a destination register must be supplied"); | |
9167 | continue; | |
9168 | } | |
9169 | } | |
bdaaa2e1 KH |
9170 | /* Now that we have assembled one operand, we use the args string |
9171 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9172 | switch (c) |
9173 | { | |
9174 | case 'r': | |
9175 | case 's': | |
9176 | case 'v': | |
9177 | case 'b': | |
bf12938e | 9178 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9179 | break; |
9180 | case 'd': | |
9181 | case 'G': | |
af7ee8bf | 9182 | case 'K': |
ef2e4d86 | 9183 | case 'g': |
bf12938e | 9184 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9185 | break; |
4372b673 | 9186 | case 'U': |
bf12938e RS |
9187 | INSERT_OPERAND (RD, *ip, regno); |
9188 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9189 | break; |
252b5132 RH |
9190 | case 'w': |
9191 | case 't': | |
9192 | case 'E': | |
bf12938e | 9193 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9194 | break; |
9195 | case 'x': | |
9196 | /* This case exists because on the r3000 trunc | |
9197 | expands into a macro which requires a gp | |
9198 | register. On the r6000 or r4000 it is | |
9199 | assembled into a single instruction which | |
9200 | ignores the register. Thus the insn version | |
9201 | is MIPS_ISA2 and uses 'x', and the macro | |
9202 | version is MIPS_ISA1 and uses 't'. */ | |
9203 | break; | |
9204 | case 'z': | |
9205 | /* This case is for the div instruction, which | |
9206 | acts differently if the destination argument | |
9207 | is $0. This only matches $0, and is checked | |
9208 | outside the switch. */ | |
9209 | break; | |
9210 | case 'D': | |
9211 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9212 | break; | |
9213 | /* What about all other operands like 'i', which | |
9214 | can be specified in the opcode table? */ | |
9215 | } | |
9216 | lastregno = regno; | |
9217 | continue; | |
9218 | } | |
252b5132 RH |
9219 | switch (*args++) |
9220 | { | |
9221 | case 'r': | |
9222 | case 'v': | |
bf12938e | 9223 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9224 | continue; |
9225 | case 'w': | |
bf12938e | 9226 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9227 | continue; |
9228 | } | |
9229 | break; | |
9230 | ||
deec1734 CD |
9231 | case 'O': /* MDMX alignment immediate constant. */ |
9232 | my_getExpression (&imm_expr, s); | |
9233 | check_absolute_expr (ip, &imm_expr); | |
9234 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
9235 | as_warn ("Improper align amount (%ld), using low bits", |
9236 | (long) imm_expr.X_add_number); | |
9237 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9238 | imm_expr.X_op = O_absent; |
9239 | s = expr_end; | |
9240 | continue; | |
9241 | ||
9242 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9243 | if (s[0] != '$') | |
9244 | { | |
9245 | /* MDMX Immediate. */ | |
9246 | my_getExpression (&imm_expr, s); | |
9247 | check_absolute_expr (ip, &imm_expr); | |
9248 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9249 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9250 | (long) imm_expr.X_add_number); | |
9251 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9252 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9253 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9254 | else | |
9255 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9256 | imm_expr.X_op = O_absent; |
9257 | s = expr_end; | |
9258 | continue; | |
9259 | } | |
9260 | /* Not MDMX Immediate. Fall through. */ | |
9261 | case 'X': /* MDMX destination register. */ | |
9262 | case 'Y': /* MDMX source register. */ | |
9263 | case 'Z': /* MDMX target register. */ | |
9264 | is_mdmx = 1; | |
252b5132 RH |
9265 | case 'D': /* floating point destination register */ |
9266 | case 'S': /* floating point source register */ | |
9267 | case 'T': /* floating point target register */ | |
9268 | case 'R': /* floating point source register */ | |
9269 | case 'V': | |
9270 | case 'W': | |
707bfff6 TS |
9271 | rtype = RTYPE_FPU; |
9272 | if (is_mdmx | |
9273 | || (mips_opts.ase_mdmx | |
9274 | && (ip->insn_mo->pinfo & FP_D) | |
9275 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9276 | | INSN_COPROC_MEMORY_DELAY | |
9277 | | INSN_LOAD_COPROC_DELAY | |
9278 | | INSN_LOAD_MEMORY_DELAY | |
9279 | | INSN_STORE_MEMORY)))) | |
9280 | rtype |= RTYPE_VEC; | |
252b5132 | 9281 | s_reset = s; |
707bfff6 | 9282 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9283 | { |
252b5132 | 9284 | if ((regno & 1) != 0 |
ca4e0257 | 9285 | && HAVE_32BIT_FPRS |
7455baf8 | 9286 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9287 | as_warn (_("Float register should be even, was %d"), |
9288 | regno); | |
9289 | ||
9290 | c = *args; | |
9291 | if (*s == ' ') | |
f9419b05 | 9292 | ++s; |
252b5132 RH |
9293 | if (args[1] != *s) |
9294 | { | |
9295 | if (c == 'V' || c == 'W') | |
9296 | { | |
9297 | regno = lastregno; | |
9298 | s = s_reset; | |
f9419b05 | 9299 | ++args; |
252b5132 RH |
9300 | } |
9301 | } | |
9302 | switch (c) | |
9303 | { | |
9304 | case 'D': | |
deec1734 | 9305 | case 'X': |
bf12938e | 9306 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9307 | break; |
9308 | case 'V': | |
9309 | case 'S': | |
deec1734 | 9310 | case 'Y': |
bf12938e | 9311 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9312 | break; |
deec1734 CD |
9313 | case 'Q': |
9314 | /* This is like 'Z', but also needs to fix the MDMX | |
9315 | vector/scalar select bits. Note that the | |
9316 | scalar immediate case is handled above. */ | |
9317 | if (*s == '[') | |
9318 | { | |
9319 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9320 | int max_el = (is_qh ? 3 : 7); | |
9321 | s++; | |
9322 | my_getExpression(&imm_expr, s); | |
9323 | check_absolute_expr (ip, &imm_expr); | |
9324 | s = expr_end; | |
9325 | if (imm_expr.X_add_number > max_el) | |
9326 | as_bad(_("Bad element selector %ld"), | |
9327 | (long) imm_expr.X_add_number); | |
9328 | imm_expr.X_add_number &= max_el; | |
9329 | ip->insn_opcode |= (imm_expr.X_add_number | |
9330 | << (OP_SH_VSEL + | |
9331 | (is_qh ? 2 : 1))); | |
01a3f561 | 9332 | imm_expr.X_op = O_absent; |
deec1734 CD |
9333 | if (*s != ']') |
9334 | as_warn(_("Expecting ']' found '%s'"), s); | |
9335 | else | |
9336 | s++; | |
9337 | } | |
9338 | else | |
9339 | { | |
9340 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9341 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9342 | << OP_SH_VSEL); | |
9343 | else | |
9344 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9345 | OP_SH_VSEL); | |
9346 | } | |
9347 | /* Fall through */ | |
252b5132 RH |
9348 | case 'W': |
9349 | case 'T': | |
deec1734 | 9350 | case 'Z': |
bf12938e | 9351 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9352 | break; |
9353 | case 'R': | |
bf12938e | 9354 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9355 | break; |
9356 | } | |
9357 | lastregno = regno; | |
9358 | continue; | |
9359 | } | |
9360 | ||
252b5132 RH |
9361 | switch (*args++) |
9362 | { | |
9363 | case 'V': | |
bf12938e | 9364 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9365 | continue; |
9366 | case 'W': | |
bf12938e | 9367 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9368 | continue; |
9369 | } | |
9370 | break; | |
9371 | ||
9372 | case 'I': | |
9373 | my_getExpression (&imm_expr, s); | |
9374 | if (imm_expr.X_op != O_big | |
9375 | && imm_expr.X_op != O_constant) | |
9376 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9377 | if (HAVE_32BIT_GPRS) |
9378 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9379 | s = expr_end; |
9380 | continue; | |
9381 | ||
9382 | case 'A': | |
9383 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9384 | normalize_address_expr (&offset_expr); |
f6688943 | 9385 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9386 | s = expr_end; |
9387 | continue; | |
9388 | ||
9389 | case 'F': | |
9390 | case 'L': | |
9391 | case 'f': | |
9392 | case 'l': | |
9393 | { | |
9394 | int f64; | |
ca4e0257 | 9395 | int using_gprs; |
252b5132 RH |
9396 | char *save_in; |
9397 | char *err; | |
9398 | unsigned char temp[8]; | |
9399 | int len; | |
9400 | unsigned int length; | |
9401 | segT seg; | |
9402 | subsegT subseg; | |
9403 | char *p; | |
9404 | ||
9405 | /* These only appear as the last operand in an | |
9406 | instruction, and every instruction that accepts | |
9407 | them in any variant accepts them in all variants. | |
9408 | This means we don't have to worry about backing out | |
9409 | any changes if the instruction does not match. | |
9410 | ||
9411 | The difference between them is the size of the | |
9412 | floating point constant and where it goes. For 'F' | |
9413 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9414 | is 32 bits. Where the constant is placed is based | |
9415 | on how the MIPS assembler does things: | |
9416 | F -- .rdata | |
9417 | L -- .lit8 | |
9418 | f -- immediate value | |
9419 | l -- .lit4 | |
9420 | ||
9421 | The .lit4 and .lit8 sections are only used if | |
9422 | permitted by the -G argument. | |
9423 | ||
ca4e0257 RS |
9424 | The code below needs to know whether the target register |
9425 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9426 | 'F' are used with GPR-based instructions and 'l' and | |
9427 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9428 | |
9429 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9430 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9431 | |
9432 | save_in = input_line_pointer; | |
9433 | input_line_pointer = s; | |
9434 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9435 | length = len; | |
9436 | s = input_line_pointer; | |
9437 | input_line_pointer = save_in; | |
9438 | if (err != NULL && *err != '\0') | |
9439 | { | |
9440 | as_bad (_("Bad floating point constant: %s"), err); | |
9441 | memset (temp, '\0', sizeof temp); | |
9442 | length = f64 ? 8 : 4; | |
9443 | } | |
9444 | ||
156c2f8b | 9445 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9446 | |
9447 | if (*args == 'f' | |
9448 | || (*args == 'l' | |
3e722fb5 | 9449 | && (g_switch_value < 4 |
252b5132 RH |
9450 | || (temp[0] == 0 && temp[1] == 0) |
9451 | || (temp[2] == 0 && temp[3] == 0)))) | |
9452 | { | |
9453 | imm_expr.X_op = O_constant; | |
9454 | if (! target_big_endian) | |
9455 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9456 | else | |
9457 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9458 | } | |
9459 | else if (length > 4 | |
119d663a | 9460 | && ! mips_disable_float_construction |
ca4e0257 RS |
9461 | /* Constants can only be constructed in GPRs and |
9462 | copied to FPRs if the GPRs are at least as wide | |
9463 | as the FPRs. Force the constant into memory if | |
9464 | we are using 64-bit FPRs but the GPRs are only | |
9465 | 32 bits wide. */ | |
9466 | && (using_gprs | |
9467 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9468 | && ((temp[0] == 0 && temp[1] == 0) |
9469 | || (temp[2] == 0 && temp[3] == 0)) | |
9470 | && ((temp[4] == 0 && temp[5] == 0) | |
9471 | || (temp[6] == 0 && temp[7] == 0))) | |
9472 | { | |
ca4e0257 RS |
9473 | /* The value is simple enough to load with a couple of |
9474 | instructions. If using 32-bit registers, set | |
9475 | imm_expr to the high order 32 bits and offset_expr to | |
9476 | the low order 32 bits. Otherwise, set imm_expr to | |
9477 | the entire 64 bit constant. */ | |
9478 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9479 | { |
9480 | imm_expr.X_op = O_constant; | |
9481 | offset_expr.X_op = O_constant; | |
9482 | if (! target_big_endian) | |
9483 | { | |
9484 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9485 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9486 | } | |
9487 | else | |
9488 | { | |
9489 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9490 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9491 | } | |
9492 | if (offset_expr.X_add_number == 0) | |
9493 | offset_expr.X_op = O_absent; | |
9494 | } | |
9495 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9496 | { | |
9497 | imm_expr.X_op = O_constant; | |
9498 | if (! target_big_endian) | |
9499 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9500 | else | |
9501 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9502 | } | |
9503 | else | |
9504 | { | |
9505 | imm_expr.X_op = O_big; | |
9506 | imm_expr.X_add_number = 4; | |
9507 | if (! target_big_endian) | |
9508 | { | |
9509 | generic_bignum[0] = bfd_getl16 (temp); | |
9510 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9511 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9512 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9513 | } | |
9514 | else | |
9515 | { | |
9516 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9517 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9518 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9519 | generic_bignum[3] = bfd_getb16 (temp); | |
9520 | } | |
9521 | } | |
9522 | } | |
9523 | else | |
9524 | { | |
9525 | const char *newname; | |
9526 | segT new_seg; | |
9527 | ||
9528 | /* Switch to the right section. */ | |
9529 | seg = now_seg; | |
9530 | subseg = now_subseg; | |
9531 | switch (*args) | |
9532 | { | |
9533 | default: /* unused default case avoids warnings. */ | |
9534 | case 'L': | |
9535 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9536 | if (g_switch_value >= 8) |
252b5132 RH |
9537 | newname = ".lit8"; |
9538 | break; | |
9539 | case 'F': | |
3e722fb5 | 9540 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9541 | break; |
9542 | case 'l': | |
4d0d148d | 9543 | assert (g_switch_value >= 4); |
252b5132 RH |
9544 | newname = ".lit4"; |
9545 | break; | |
9546 | } | |
9547 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9548 | if (IS_ELF) |
252b5132 RH |
9549 | bfd_set_section_flags (stdoutput, new_seg, |
9550 | (SEC_ALLOC | |
9551 | | SEC_LOAD | |
9552 | | SEC_READONLY | |
9553 | | SEC_DATA)); | |
9554 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 9555 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
9556 | record_alignment (new_seg, 4); |
9557 | else | |
9558 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9559 | if (seg == now_seg) | |
9560 | as_bad (_("Can't use floating point insn in this section")); | |
9561 | ||
9562 | /* Set the argument to the current address in the | |
9563 | section. */ | |
9564 | offset_expr.X_op = O_symbol; | |
9565 | offset_expr.X_add_symbol = | |
9566 | symbol_new ("L0\001", now_seg, | |
9567 | (valueT) frag_now_fix (), frag_now); | |
9568 | offset_expr.X_add_number = 0; | |
9569 | ||
9570 | /* Put the floating point number into the section. */ | |
9571 | p = frag_more ((int) length); | |
9572 | memcpy (p, temp, length); | |
9573 | ||
9574 | /* Switch back to the original section. */ | |
9575 | subseg_set (seg, subseg); | |
9576 | } | |
9577 | } | |
9578 | continue; | |
9579 | ||
9580 | case 'i': /* 16 bit unsigned immediate */ | |
9581 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9582 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9583 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9584 | { |
9585 | int more; | |
5e0116d5 RS |
9586 | offsetT minval, maxval; |
9587 | ||
9588 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9589 | && strcmp (insn->name, insn[1].name) == 0); | |
9590 | ||
9591 | /* If the expression was written as an unsigned number, | |
9592 | only treat it as signed if there are no more | |
9593 | alternatives. */ | |
9594 | if (more | |
9595 | && *args == 'j' | |
9596 | && sizeof (imm_expr.X_add_number) <= 4 | |
9597 | && imm_expr.X_op == O_constant | |
9598 | && imm_expr.X_add_number < 0 | |
9599 | && imm_expr.X_unsigned | |
9600 | && HAVE_64BIT_GPRS) | |
9601 | break; | |
9602 | ||
9603 | /* For compatibility with older assemblers, we accept | |
9604 | 0x8000-0xffff as signed 16-bit numbers when only | |
9605 | signed numbers are allowed. */ | |
9606 | if (*args == 'i') | |
9607 | minval = 0, maxval = 0xffff; | |
9608 | else if (more) | |
9609 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9610 | else |
5e0116d5 RS |
9611 | minval = -0x8000, maxval = 0xffff; |
9612 | ||
9613 | if (imm_expr.X_op != O_constant | |
9614 | || imm_expr.X_add_number < minval | |
9615 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9616 | { |
9617 | if (more) | |
9618 | break; | |
2ae7e77b AH |
9619 | if (imm_expr.X_op == O_constant |
9620 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9621 | as_bad (_("expression out of range")); |
252b5132 RH |
9622 | } |
9623 | } | |
9624 | s = expr_end; | |
9625 | continue; | |
9626 | ||
9627 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9628 | /* Check whether there is only a single bracketed expression |
9629 | left. If so, it must be the base register and the | |
9630 | constant must be zero. */ | |
9631 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9632 | { | |
9633 | offset_expr.X_op = O_constant; | |
9634 | offset_expr.X_add_number = 0; | |
9635 | continue; | |
9636 | } | |
252b5132 RH |
9637 | |
9638 | /* If this value won't fit into a 16 bit offset, then go | |
9639 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9640 | code pattern. */ |
5e0116d5 | 9641 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9642 | && (offset_expr.X_op != O_constant |
9643 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9644 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9645 | break; |
9646 | ||
252b5132 RH |
9647 | s = expr_end; |
9648 | continue; | |
9649 | ||
9650 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9651 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9652 | my_getExpression (&offset_expr, s); |
9653 | s = expr_end; | |
9654 | continue; | |
9655 | ||
9656 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9657 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9658 | && imm_expr.X_op == O_constant | |
9659 | && (imm_expr.X_add_number < 0 | |
9660 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9661 | as_bad (_("lui expression not in range 0..65535")); |
9662 | s = expr_end; | |
9663 | continue; | |
9664 | ||
9665 | case 'a': /* 26 bit address */ | |
9666 | my_getExpression (&offset_expr, s); | |
9667 | s = expr_end; | |
f6688943 | 9668 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9669 | continue; |
9670 | ||
9671 | case 'N': /* 3 bit branch condition code */ | |
9672 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
9673 | rtype = RTYPE_CCC; |
9674 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
9675 | rtype |= RTYPE_FCC; | |
9676 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 9677 | break; |
30c378fd CD |
9678 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
9679 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9680 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9681 | && (regno & 1) != 0) | |
9682 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9683 | str, regno); | |
9684 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9685 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9686 | && (regno & 3) != 0) | |
9687 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9688 | str, regno); | |
252b5132 | 9689 | if (*args == 'N') |
bf12938e | 9690 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9691 | else |
bf12938e | 9692 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9693 | continue; |
252b5132 | 9694 | |
156c2f8b NC |
9695 | case 'H': |
9696 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9697 | s += 2; | |
3882b010 | 9698 | if (ISDIGIT (*s)) |
156c2f8b NC |
9699 | { |
9700 | c = 0; | |
9701 | do | |
9702 | { | |
9703 | c *= 10; | |
9704 | c += *s - '0'; | |
9705 | ++s; | |
9706 | } | |
3882b010 | 9707 | while (ISDIGIT (*s)); |
156c2f8b NC |
9708 | } |
9709 | else | |
9710 | c = 8; /* Invalid sel value. */ | |
9711 | ||
9712 | if (c > 7) | |
9713 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9714 | ip->insn_opcode |= c; | |
9715 | continue; | |
9716 | ||
60b63b72 RS |
9717 | case 'e': |
9718 | /* Must be at least one digit. */ | |
9719 | my_getExpression (&imm_expr, s); | |
9720 | check_absolute_expr (ip, &imm_expr); | |
9721 | ||
9722 | if ((unsigned long) imm_expr.X_add_number | |
9723 | > (unsigned long) OP_MASK_VECBYTE) | |
9724 | { | |
9725 | as_bad (_("bad byte vector index (%ld)"), | |
9726 | (long) imm_expr.X_add_number); | |
9727 | imm_expr.X_add_number = 0; | |
9728 | } | |
9729 | ||
bf12938e | 9730 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9731 | imm_expr.X_op = O_absent; |
9732 | s = expr_end; | |
9733 | continue; | |
9734 | ||
9735 | case '%': | |
9736 | my_getExpression (&imm_expr, s); | |
9737 | check_absolute_expr (ip, &imm_expr); | |
9738 | ||
9739 | if ((unsigned long) imm_expr.X_add_number | |
9740 | > (unsigned long) OP_MASK_VECALIGN) | |
9741 | { | |
9742 | as_bad (_("bad byte vector index (%ld)"), | |
9743 | (long) imm_expr.X_add_number); | |
9744 | imm_expr.X_add_number = 0; | |
9745 | } | |
9746 | ||
bf12938e | 9747 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9748 | imm_expr.X_op = O_absent; |
9749 | s = expr_end; | |
9750 | continue; | |
9751 | ||
252b5132 RH |
9752 | default: |
9753 | as_bad (_("bad char = '%c'\n"), *args); | |
9754 | internalError (); | |
9755 | } | |
9756 | break; | |
9757 | } | |
9758 | /* Args don't match. */ | |
9759 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9760 | !strcmp (insn->name, insn[1].name)) | |
9761 | { | |
9762 | ++insn; | |
9763 | s = argsStart; | |
268f6bed | 9764 | insn_error = _("illegal operands"); |
252b5132 RH |
9765 | continue; |
9766 | } | |
268f6bed L |
9767 | if (save_c) |
9768 | *(--s) = save_c; | |
252b5132 RH |
9769 | insn_error = _("illegal operands"); |
9770 | return; | |
9771 | } | |
9772 | } | |
9773 | ||
0499d65b TS |
9774 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9775 | ||
252b5132 RH |
9776 | /* This routine assembles an instruction into its binary format when |
9777 | assembling for the mips16. As a side effect, it sets one of the | |
9778 | global variables imm_reloc or offset_reloc to the type of | |
9779 | relocation to do if one of the operands is an address expression. | |
9780 | It also sets mips16_small and mips16_ext if the user explicitly | |
9781 | requested a small or extended instruction. */ | |
9782 | ||
9783 | static void | |
17a2f251 | 9784 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9785 | { |
9786 | char *s; | |
9787 | const char *args; | |
9788 | struct mips_opcode *insn; | |
9789 | char *argsstart; | |
9790 | unsigned int regno; | |
9791 | unsigned int lastregno = 0; | |
9792 | char *s_reset; | |
d6f16593 | 9793 | size_t i; |
252b5132 RH |
9794 | |
9795 | insn_error = NULL; | |
9796 | ||
b34976b6 AM |
9797 | mips16_small = FALSE; |
9798 | mips16_ext = FALSE; | |
252b5132 | 9799 | |
3882b010 | 9800 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9801 | ; |
9802 | switch (*s) | |
9803 | { | |
9804 | case '\0': | |
9805 | break; | |
9806 | ||
9807 | case ' ': | |
9808 | *s++ = '\0'; | |
9809 | break; | |
9810 | ||
9811 | case '.': | |
9812 | if (s[1] == 't' && s[2] == ' ') | |
9813 | { | |
9814 | *s = '\0'; | |
b34976b6 | 9815 | mips16_small = TRUE; |
252b5132 RH |
9816 | s += 3; |
9817 | break; | |
9818 | } | |
9819 | else if (s[1] == 'e' && s[2] == ' ') | |
9820 | { | |
9821 | *s = '\0'; | |
b34976b6 | 9822 | mips16_ext = TRUE; |
252b5132 RH |
9823 | s += 3; |
9824 | break; | |
9825 | } | |
9826 | /* Fall through. */ | |
9827 | default: | |
9828 | insn_error = _("unknown opcode"); | |
9829 | return; | |
9830 | } | |
9831 | ||
9832 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9833 | mips16_small = TRUE; |
252b5132 RH |
9834 | |
9835 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9836 | { | |
9837 | insn_error = _("unrecognized opcode"); | |
9838 | return; | |
9839 | } | |
9840 | ||
9841 | argsstart = s; | |
9842 | for (;;) | |
9843 | { | |
9b3f89ee TS |
9844 | bfd_boolean ok; |
9845 | ||
252b5132 RH |
9846 | assert (strcmp (insn->name, str) == 0); |
9847 | ||
037b32b9 | 9848 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
9849 | if (! ok) |
9850 | { | |
9851 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
9852 | && strcmp (insn->name, insn[1].name) == 0) | |
9853 | { | |
9854 | ++insn; | |
9855 | continue; | |
9856 | } | |
9857 | else | |
9858 | { | |
9859 | if (!insn_error) | |
9860 | { | |
9861 | static char buf[100]; | |
9862 | sprintf (buf, | |
9863 | _("opcode not supported on this processor: %s (%s)"), | |
9864 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
9865 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
9866 | insn_error = buf; | |
9867 | } | |
9868 | return; | |
9869 | } | |
9870 | } | |
9871 | ||
1e915849 | 9872 | create_insn (ip, insn); |
252b5132 | 9873 | imm_expr.X_op = O_absent; |
f6688943 TS |
9874 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9875 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9876 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9877 | imm2_expr.X_op = O_absent; |
252b5132 | 9878 | offset_expr.X_op = O_absent; |
f6688943 TS |
9879 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9880 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9881 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9882 | for (args = insn->args; 1; ++args) |
9883 | { | |
9884 | int c; | |
9885 | ||
9886 | if (*s == ' ') | |
9887 | ++s; | |
9888 | ||
9889 | /* In this switch statement we call break if we did not find | |
9890 | a match, continue if we did find a match, or return if we | |
9891 | are done. */ | |
9892 | ||
9893 | c = *args; | |
9894 | switch (c) | |
9895 | { | |
9896 | case '\0': | |
9897 | if (*s == '\0') | |
9898 | { | |
9899 | /* Stuff the immediate value in now, if we can. */ | |
9900 | if (imm_expr.X_op == O_constant | |
f6688943 | 9901 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9902 | && insn->pinfo != INSN_MACRO) |
9903 | { | |
d6f16593 MR |
9904 | valueT tmp; |
9905 | ||
9906 | switch (*offset_reloc) | |
9907 | { | |
9908 | case BFD_RELOC_MIPS16_HI16_S: | |
9909 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9910 | break; | |
9911 | ||
9912 | case BFD_RELOC_MIPS16_HI16: | |
9913 | tmp = imm_expr.X_add_number >> 16; | |
9914 | break; | |
9915 | ||
9916 | case BFD_RELOC_MIPS16_LO16: | |
9917 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9918 | - 0x8000; | |
9919 | break; | |
9920 | ||
9921 | case BFD_RELOC_UNUSED: | |
9922 | tmp = imm_expr.X_add_number; | |
9923 | break; | |
9924 | ||
9925 | default: | |
9926 | internalError (); | |
9927 | } | |
9928 | *offset_reloc = BFD_RELOC_UNUSED; | |
9929 | ||
c4e7957c | 9930 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9931 | tmp, TRUE, mips16_small, |
252b5132 RH |
9932 | mips16_ext, &ip->insn_opcode, |
9933 | &ip->use_extend, &ip->extend); | |
9934 | imm_expr.X_op = O_absent; | |
f6688943 | 9935 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9936 | } |
9937 | ||
9938 | return; | |
9939 | } | |
9940 | break; | |
9941 | ||
9942 | case ',': | |
9943 | if (*s++ == c) | |
9944 | continue; | |
9945 | s--; | |
9946 | switch (*++args) | |
9947 | { | |
9948 | case 'v': | |
bf12938e | 9949 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9950 | continue; |
9951 | case 'w': | |
bf12938e | 9952 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9953 | continue; |
9954 | } | |
9955 | break; | |
9956 | ||
9957 | case '(': | |
9958 | case ')': | |
9959 | if (*s++ == c) | |
9960 | continue; | |
9961 | break; | |
9962 | ||
9963 | case 'v': | |
9964 | case 'w': | |
9965 | if (s[0] != '$') | |
9966 | { | |
9967 | if (c == 'v') | |
bf12938e | 9968 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9969 | else |
bf12938e | 9970 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9971 | ++args; |
9972 | continue; | |
9973 | } | |
9974 | /* Fall through. */ | |
9975 | case 'x': | |
9976 | case 'y': | |
9977 | case 'z': | |
9978 | case 'Z': | |
9979 | case '0': | |
9980 | case 'S': | |
9981 | case 'R': | |
9982 | case 'X': | |
9983 | case 'Y': | |
707bfff6 TS |
9984 | s_reset = s; |
9985 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 9986 | { |
707bfff6 | 9987 | if (c == 'v' || c == 'w') |
85b51719 | 9988 | { |
707bfff6 | 9989 | if (c == 'v') |
a9e24354 | 9990 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 9991 | else |
a9e24354 | 9992 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
9993 | ++args; |
9994 | continue; | |
85b51719 | 9995 | } |
707bfff6 | 9996 | break; |
252b5132 RH |
9997 | } |
9998 | ||
9999 | if (*s == ' ') | |
10000 | ++s; | |
10001 | if (args[1] != *s) | |
10002 | { | |
10003 | if (c == 'v' || c == 'w') | |
10004 | { | |
10005 | regno = mips16_to_32_reg_map[lastregno]; | |
10006 | s = s_reset; | |
f9419b05 | 10007 | ++args; |
252b5132 RH |
10008 | } |
10009 | } | |
10010 | ||
10011 | switch (c) | |
10012 | { | |
10013 | case 'x': | |
10014 | case 'y': | |
10015 | case 'z': | |
10016 | case 'v': | |
10017 | case 'w': | |
10018 | case 'Z': | |
10019 | regno = mips32_to_16_reg_map[regno]; | |
10020 | break; | |
10021 | ||
10022 | case '0': | |
10023 | if (regno != 0) | |
10024 | regno = ILLEGAL_REG; | |
10025 | break; | |
10026 | ||
10027 | case 'S': | |
10028 | if (regno != SP) | |
10029 | regno = ILLEGAL_REG; | |
10030 | break; | |
10031 | ||
10032 | case 'R': | |
10033 | if (regno != RA) | |
10034 | regno = ILLEGAL_REG; | |
10035 | break; | |
10036 | ||
10037 | case 'X': | |
10038 | case 'Y': | |
741fe287 MR |
10039 | if (regno == AT && mips_opts.at) |
10040 | { | |
10041 | if (mips_opts.at == ATREG) | |
10042 | as_warn (_("used $at without \".set noat\"")); | |
10043 | else | |
10044 | as_warn (_("used $%u with \".set at=$%u\""), | |
10045 | regno, mips_opts.at); | |
10046 | } | |
252b5132 RH |
10047 | break; |
10048 | ||
10049 | default: | |
10050 | internalError (); | |
10051 | } | |
10052 | ||
10053 | if (regno == ILLEGAL_REG) | |
10054 | break; | |
10055 | ||
10056 | switch (c) | |
10057 | { | |
10058 | case 'x': | |
10059 | case 'v': | |
bf12938e | 10060 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10061 | break; |
10062 | case 'y': | |
10063 | case 'w': | |
bf12938e | 10064 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10065 | break; |
10066 | case 'z': | |
bf12938e | 10067 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10068 | break; |
10069 | case 'Z': | |
bf12938e | 10070 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10071 | case '0': |
10072 | case 'S': | |
10073 | case 'R': | |
10074 | break; | |
10075 | case 'X': | |
bf12938e | 10076 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10077 | break; |
10078 | case 'Y': | |
10079 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10080 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10081 | break; |
10082 | default: | |
10083 | internalError (); | |
10084 | } | |
10085 | ||
10086 | lastregno = regno; | |
10087 | continue; | |
10088 | ||
10089 | case 'P': | |
10090 | if (strncmp (s, "$pc", 3) == 0) | |
10091 | { | |
10092 | s += 3; | |
10093 | continue; | |
10094 | } | |
10095 | break; | |
10096 | ||
252b5132 RH |
10097 | case '5': |
10098 | case 'H': | |
10099 | case 'W': | |
10100 | case 'D': | |
10101 | case 'j': | |
252b5132 RH |
10102 | case 'V': |
10103 | case 'C': | |
10104 | case 'U': | |
10105 | case 'k': | |
10106 | case 'K': | |
d6f16593 MR |
10107 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10108 | if (i > 0) | |
252b5132 | 10109 | { |
d6f16593 | 10110 | if (imm_expr.X_op != O_constant) |
252b5132 | 10111 | { |
b34976b6 | 10112 | mips16_ext = TRUE; |
b34976b6 | 10113 | ip->use_extend = TRUE; |
252b5132 | 10114 | ip->extend = 0; |
252b5132 | 10115 | } |
d6f16593 MR |
10116 | else |
10117 | { | |
10118 | /* We need to relax this instruction. */ | |
10119 | *offset_reloc = *imm_reloc; | |
10120 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10121 | } | |
10122 | s = expr_end; | |
10123 | continue; | |
252b5132 | 10124 | } |
d6f16593 MR |
10125 | *imm_reloc = BFD_RELOC_UNUSED; |
10126 | /* Fall through. */ | |
10127 | case '<': | |
10128 | case '>': | |
10129 | case '[': | |
10130 | case ']': | |
10131 | case '4': | |
10132 | case '8': | |
10133 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10134 | if (imm_expr.X_op == O_register) |
10135 | { | |
10136 | /* What we thought was an expression turned out to | |
10137 | be a register. */ | |
10138 | ||
10139 | if (s[0] == '(' && args[1] == '(') | |
10140 | { | |
10141 | /* It looks like the expression was omitted | |
10142 | before a register indirection, which means | |
10143 | that the expression is implicitly zero. We | |
10144 | still set up imm_expr, so that we handle | |
10145 | explicit extensions correctly. */ | |
10146 | imm_expr.X_op = O_constant; | |
10147 | imm_expr.X_add_number = 0; | |
f6688943 | 10148 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10149 | continue; |
10150 | } | |
10151 | ||
10152 | break; | |
10153 | } | |
10154 | ||
10155 | /* We need to relax this instruction. */ | |
f6688943 | 10156 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10157 | s = expr_end; |
10158 | continue; | |
10159 | ||
10160 | case 'p': | |
10161 | case 'q': | |
10162 | case 'A': | |
10163 | case 'B': | |
10164 | case 'E': | |
10165 | /* We use offset_reloc rather than imm_reloc for the PC | |
10166 | relative operands. This lets macros with both | |
10167 | immediate and address operands work correctly. */ | |
10168 | my_getExpression (&offset_expr, s); | |
10169 | ||
10170 | if (offset_expr.X_op == O_register) | |
10171 | break; | |
10172 | ||
10173 | /* We need to relax this instruction. */ | |
f6688943 | 10174 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10175 | s = expr_end; |
10176 | continue; | |
10177 | ||
10178 | case '6': /* break code */ | |
10179 | my_getExpression (&imm_expr, s); | |
10180 | check_absolute_expr (ip, &imm_expr); | |
10181 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10182 | as_warn (_("Invalid value for `%s' (%lu)"), |
10183 | ip->insn_mo->name, | |
10184 | (unsigned long) imm_expr.X_add_number); | |
10185 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10186 | imm_expr.X_op = O_absent; |
10187 | s = expr_end; | |
10188 | continue; | |
10189 | ||
10190 | case 'a': /* 26 bit address */ | |
10191 | my_getExpression (&offset_expr, s); | |
10192 | s = expr_end; | |
f6688943 | 10193 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10194 | ip->insn_opcode <<= 16; |
10195 | continue; | |
10196 | ||
10197 | case 'l': /* register list for entry macro */ | |
10198 | case 'L': /* register list for exit macro */ | |
10199 | { | |
10200 | int mask; | |
10201 | ||
10202 | if (c == 'l') | |
10203 | mask = 0; | |
10204 | else | |
10205 | mask = 7 << 3; | |
10206 | while (*s != '\0') | |
10207 | { | |
707bfff6 | 10208 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10209 | |
10210 | while (*s == ' ' || *s == ',') | |
10211 | ++s; | |
707bfff6 | 10212 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10213 | freg = 0; |
707bfff6 TS |
10214 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10215 | freg = 1; | |
252b5132 RH |
10216 | else |
10217 | { | |
707bfff6 TS |
10218 | as_bad (_("can't parse register list")); |
10219 | break; | |
252b5132 RH |
10220 | } |
10221 | if (*s == ' ') | |
10222 | ++s; | |
10223 | if (*s != '-') | |
10224 | reg2 = reg1; | |
10225 | else | |
10226 | { | |
10227 | ++s; | |
707bfff6 TS |
10228 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10229 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10230 | { |
707bfff6 TS |
10231 | as_bad (_("invalid register list")); |
10232 | break; | |
252b5132 RH |
10233 | } |
10234 | } | |
10235 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10236 | { | |
10237 | mask &= ~ (7 << 3); | |
10238 | mask |= 5 << 3; | |
10239 | } | |
10240 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10241 | { | |
10242 | mask &= ~ (7 << 3); | |
10243 | mask |= 6 << 3; | |
10244 | } | |
10245 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10246 | mask |= (reg2 - 3) << 3; | |
10247 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10248 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10249 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10250 | mask |= 1; |
10251 | else | |
10252 | { | |
10253 | as_bad (_("invalid register list")); | |
10254 | break; | |
10255 | } | |
10256 | } | |
10257 | /* The mask is filled in in the opcode table for the | |
10258 | benefit of the disassembler. We remove it before | |
10259 | applying the actual mask. */ | |
10260 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10261 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10262 | } | |
10263 | continue; | |
10264 | ||
0499d65b TS |
10265 | case 'm': /* Register list for save insn. */ |
10266 | case 'M': /* Register list for restore insn. */ | |
10267 | { | |
10268 | int opcode = 0; | |
10269 | int framesz = 0, seen_framesz = 0; | |
10270 | int args = 0, statics = 0, sregs = 0; | |
10271 | ||
10272 | while (*s != '\0') | |
10273 | { | |
10274 | unsigned int reg1, reg2; | |
10275 | ||
10276 | SKIP_SPACE_TABS (s); | |
10277 | while (*s == ',') | |
10278 | ++s; | |
10279 | SKIP_SPACE_TABS (s); | |
10280 | ||
10281 | my_getExpression (&imm_expr, s); | |
10282 | if (imm_expr.X_op == O_constant) | |
10283 | { | |
10284 | /* Handle the frame size. */ | |
10285 | if (seen_framesz) | |
10286 | { | |
10287 | as_bad (_("more than one frame size in list")); | |
10288 | break; | |
10289 | } | |
10290 | seen_framesz = 1; | |
10291 | framesz = imm_expr.X_add_number; | |
10292 | imm_expr.X_op = O_absent; | |
10293 | s = expr_end; | |
10294 | continue; | |
10295 | } | |
10296 | ||
707bfff6 | 10297 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10298 | { |
10299 | as_bad (_("can't parse register list")); | |
10300 | break; | |
10301 | } | |
0499d65b | 10302 | |
707bfff6 TS |
10303 | while (*s == ' ') |
10304 | ++s; | |
10305 | ||
0499d65b TS |
10306 | if (*s != '-') |
10307 | reg2 = reg1; | |
10308 | else | |
10309 | { | |
10310 | ++s; | |
707bfff6 TS |
10311 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10312 | || reg2 < reg1) | |
0499d65b TS |
10313 | { |
10314 | as_bad (_("can't parse register list")); | |
10315 | break; | |
10316 | } | |
0499d65b TS |
10317 | } |
10318 | ||
10319 | while (reg1 <= reg2) | |
10320 | { | |
10321 | if (reg1 >= 4 && reg1 <= 7) | |
10322 | { | |
3a93f742 | 10323 | if (!seen_framesz) |
0499d65b TS |
10324 | /* args $a0-$a3 */ |
10325 | args |= 1 << (reg1 - 4); | |
10326 | else | |
10327 | /* statics $a0-$a3 */ | |
10328 | statics |= 1 << (reg1 - 4); | |
10329 | } | |
10330 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10331 | { | |
10332 | /* $s0-$s8 */ | |
10333 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10334 | } | |
10335 | else if (reg1 == 31) | |
10336 | { | |
10337 | /* Add $ra to insn. */ | |
10338 | opcode |= 0x40; | |
10339 | } | |
10340 | else | |
10341 | { | |
10342 | as_bad (_("unexpected register in list")); | |
10343 | break; | |
10344 | } | |
10345 | if (++reg1 == 24) | |
10346 | reg1 = 30; | |
10347 | } | |
10348 | } | |
10349 | ||
10350 | /* Encode args/statics combination. */ | |
10351 | if (args & statics) | |
10352 | as_bad (_("arg/static registers overlap")); | |
10353 | else if (args == 0xf) | |
10354 | /* All $a0-$a3 are args. */ | |
10355 | opcode |= MIPS16_ALL_ARGS << 16; | |
10356 | else if (statics == 0xf) | |
10357 | /* All $a0-$a3 are statics. */ | |
10358 | opcode |= MIPS16_ALL_STATICS << 16; | |
10359 | else | |
10360 | { | |
10361 | int narg = 0, nstat = 0; | |
10362 | ||
10363 | /* Count arg registers. */ | |
10364 | while (args & 0x1) | |
10365 | { | |
10366 | args >>= 1; | |
10367 | narg++; | |
10368 | } | |
10369 | if (args != 0) | |
10370 | as_bad (_("invalid arg register list")); | |
10371 | ||
10372 | /* Count static registers. */ | |
10373 | while (statics & 0x8) | |
10374 | { | |
10375 | statics = (statics << 1) & 0xf; | |
10376 | nstat++; | |
10377 | } | |
10378 | if (statics != 0) | |
10379 | as_bad (_("invalid static register list")); | |
10380 | ||
10381 | /* Encode args/statics. */ | |
10382 | opcode |= ((narg << 2) | nstat) << 16; | |
10383 | } | |
10384 | ||
10385 | /* Encode $s0/$s1. */ | |
10386 | if (sregs & (1 << 0)) /* $s0 */ | |
10387 | opcode |= 0x20; | |
10388 | if (sregs & (1 << 1)) /* $s1 */ | |
10389 | opcode |= 0x10; | |
10390 | sregs >>= 2; | |
10391 | ||
10392 | if (sregs != 0) | |
10393 | { | |
10394 | /* Count regs $s2-$s8. */ | |
10395 | int nsreg = 0; | |
10396 | while (sregs & 1) | |
10397 | { | |
10398 | sregs >>= 1; | |
10399 | nsreg++; | |
10400 | } | |
10401 | if (sregs != 0) | |
10402 | as_bad (_("invalid static register list")); | |
10403 | /* Encode $s2-$s8. */ | |
10404 | opcode |= nsreg << 24; | |
10405 | } | |
10406 | ||
10407 | /* Encode frame size. */ | |
10408 | if (!seen_framesz) | |
10409 | as_bad (_("missing frame size")); | |
10410 | else if ((framesz & 7) != 0 || framesz < 0 | |
10411 | || framesz > 0xff * 8) | |
10412 | as_bad (_("invalid frame size")); | |
10413 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10414 | { | |
10415 | framesz /= 8; | |
10416 | opcode |= (((framesz & 0xf0) << 16) | |
10417 | | (framesz & 0x0f)); | |
10418 | } | |
10419 | ||
10420 | /* Finally build the instruction. */ | |
10421 | if ((opcode >> 16) != 0 || framesz == 0) | |
10422 | { | |
10423 | ip->use_extend = TRUE; | |
10424 | ip->extend = opcode >> 16; | |
10425 | } | |
10426 | ip->insn_opcode |= opcode & 0x7f; | |
10427 | } | |
10428 | continue; | |
10429 | ||
252b5132 RH |
10430 | case 'e': /* extend code */ |
10431 | my_getExpression (&imm_expr, s); | |
10432 | check_absolute_expr (ip, &imm_expr); | |
10433 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10434 | { | |
10435 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10436 | ip->insn_mo->name, | |
10437 | (unsigned long) imm_expr.X_add_number); | |
10438 | imm_expr.X_add_number &= 0x7ff; | |
10439 | } | |
10440 | ip->insn_opcode |= imm_expr.X_add_number; | |
10441 | imm_expr.X_op = O_absent; | |
10442 | s = expr_end; | |
10443 | continue; | |
10444 | ||
10445 | default: | |
10446 | internalError (); | |
10447 | } | |
10448 | break; | |
10449 | } | |
10450 | ||
10451 | /* Args don't match. */ | |
10452 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10453 | strcmp (insn->name, insn[1].name) == 0) | |
10454 | { | |
10455 | ++insn; | |
10456 | s = argsstart; | |
10457 | continue; | |
10458 | } | |
10459 | ||
10460 | insn_error = _("illegal operands"); | |
10461 | ||
10462 | return; | |
10463 | } | |
10464 | } | |
10465 | ||
10466 | /* This structure holds information we know about a mips16 immediate | |
10467 | argument type. */ | |
10468 | ||
e972090a NC |
10469 | struct mips16_immed_operand |
10470 | { | |
252b5132 RH |
10471 | /* The type code used in the argument string in the opcode table. */ |
10472 | int type; | |
10473 | /* The number of bits in the short form of the opcode. */ | |
10474 | int nbits; | |
10475 | /* The number of bits in the extended form of the opcode. */ | |
10476 | int extbits; | |
10477 | /* The amount by which the short form is shifted when it is used; | |
10478 | for example, the sw instruction has a shift count of 2. */ | |
10479 | int shift; | |
10480 | /* The amount by which the short form is shifted when it is stored | |
10481 | into the instruction code. */ | |
10482 | int op_shift; | |
10483 | /* Non-zero if the short form is unsigned. */ | |
10484 | int unsp; | |
10485 | /* Non-zero if the extended form is unsigned. */ | |
10486 | int extu; | |
10487 | /* Non-zero if the value is PC relative. */ | |
10488 | int pcrel; | |
10489 | }; | |
10490 | ||
10491 | /* The mips16 immediate operand types. */ | |
10492 | ||
10493 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10494 | { | |
10495 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10496 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10497 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10498 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10499 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10500 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10501 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10502 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10503 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10504 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10505 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10506 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10507 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10508 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10509 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10510 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10511 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10512 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10513 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10514 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10515 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10516 | }; | |
10517 | ||
10518 | #define MIPS16_NUM_IMMED \ | |
10519 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10520 | ||
10521 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10522 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10523 | whether an extended value is needed; if one is needed, it sets | |
10524 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10525 | If SMALL is true, an unextended opcode was explicitly requested. | |
10526 | If EXT is true, an extended opcode was explicitly requested. If | |
10527 | WARN is true, warn if EXT does not match reality. */ | |
10528 | ||
10529 | static void | |
17a2f251 TS |
10530 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10531 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10532 | unsigned long *insn, bfd_boolean *use_extend, | |
10533 | unsigned short *extend) | |
252b5132 | 10534 | { |
3994f87e | 10535 | const struct mips16_immed_operand *op; |
252b5132 | 10536 | int mintiny, maxtiny; |
b34976b6 | 10537 | bfd_boolean needext; |
252b5132 RH |
10538 | |
10539 | op = mips16_immed_operands; | |
10540 | while (op->type != type) | |
10541 | { | |
10542 | ++op; | |
10543 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10544 | } | |
10545 | ||
10546 | if (op->unsp) | |
10547 | { | |
10548 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10549 | { | |
10550 | mintiny = 1; | |
10551 | maxtiny = 1 << op->nbits; | |
10552 | } | |
10553 | else | |
10554 | { | |
10555 | mintiny = 0; | |
10556 | maxtiny = (1 << op->nbits) - 1; | |
10557 | } | |
10558 | } | |
10559 | else | |
10560 | { | |
10561 | mintiny = - (1 << (op->nbits - 1)); | |
10562 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10563 | } | |
10564 | ||
10565 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10566 | if (type == 'p' || type == 'q') | |
10567 | val /= 2; | |
10568 | ||
10569 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10570 | || val < (mintiny << op->shift) | |
10571 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10572 | needext = TRUE; |
252b5132 | 10573 | else |
b34976b6 | 10574 | needext = FALSE; |
252b5132 RH |
10575 | |
10576 | if (warn && ext && ! needext) | |
beae10d5 KH |
10577 | as_warn_where (file, line, |
10578 | _("extended operand requested but not required")); | |
252b5132 RH |
10579 | if (small && needext) |
10580 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10581 | ||
10582 | if (small || (! ext && ! needext)) | |
10583 | { | |
10584 | int insnval; | |
10585 | ||
b34976b6 | 10586 | *use_extend = FALSE; |
252b5132 RH |
10587 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10588 | insnval <<= op->op_shift; | |
10589 | *insn |= insnval; | |
10590 | } | |
10591 | else | |
10592 | { | |
10593 | long minext, maxext; | |
10594 | int extval; | |
10595 | ||
10596 | if (op->extu) | |
10597 | { | |
10598 | minext = 0; | |
10599 | maxext = (1 << op->extbits) - 1; | |
10600 | } | |
10601 | else | |
10602 | { | |
10603 | minext = - (1 << (op->extbits - 1)); | |
10604 | maxext = (1 << (op->extbits - 1)) - 1; | |
10605 | } | |
10606 | if (val < minext || val > maxext) | |
10607 | as_bad_where (file, line, | |
10608 | _("operand value out of range for instruction")); | |
10609 | ||
b34976b6 | 10610 | *use_extend = TRUE; |
252b5132 RH |
10611 | if (op->extbits == 16) |
10612 | { | |
10613 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10614 | val &= 0x1f; | |
10615 | } | |
10616 | else if (op->extbits == 15) | |
10617 | { | |
10618 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10619 | val &= 0xf; | |
10620 | } | |
10621 | else | |
10622 | { | |
10623 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10624 | val = 0; | |
10625 | } | |
10626 | ||
10627 | *extend = (unsigned short) extval; | |
10628 | *insn |= val; | |
10629 | } | |
10630 | } | |
10631 | \f | |
d6f16593 | 10632 | struct percent_op_match |
ad8d3bb3 | 10633 | { |
5e0116d5 RS |
10634 | const char *str; |
10635 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10636 | }; |
10637 | ||
10638 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10639 | { |
5e0116d5 | 10640 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10641 | #ifdef OBJ_ELF |
5e0116d5 RS |
10642 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10643 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10644 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10645 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10646 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10647 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10648 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10649 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10650 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10651 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10652 | {"%half", BFD_RELOC_16}, | |
10653 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10654 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10655 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10656 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10657 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10658 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10659 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10660 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10661 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10662 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10663 | #endif |
5e0116d5 | 10664 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10665 | }; |
10666 | ||
d6f16593 MR |
10667 | static const struct percent_op_match mips16_percent_op[] = |
10668 | { | |
10669 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10670 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10671 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10672 | }; | |
10673 | ||
252b5132 | 10674 | |
5e0116d5 RS |
10675 | /* Return true if *STR points to a relocation operator. When returning true, |
10676 | move *STR over the operator and store its relocation code in *RELOC. | |
10677 | Leave both *STR and *RELOC alone when returning false. */ | |
10678 | ||
10679 | static bfd_boolean | |
17a2f251 | 10680 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10681 | { |
d6f16593 MR |
10682 | const struct percent_op_match *percent_op; |
10683 | size_t limit, i; | |
10684 | ||
10685 | if (mips_opts.mips16) | |
10686 | { | |
10687 | percent_op = mips16_percent_op; | |
10688 | limit = ARRAY_SIZE (mips16_percent_op); | |
10689 | } | |
10690 | else | |
10691 | { | |
10692 | percent_op = mips_percent_op; | |
10693 | limit = ARRAY_SIZE (mips_percent_op); | |
10694 | } | |
76b3015f | 10695 | |
d6f16593 | 10696 | for (i = 0; i < limit; i++) |
5e0116d5 | 10697 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10698 | { |
3f98094e DJ |
10699 | int len = strlen (percent_op[i].str); |
10700 | ||
10701 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10702 | continue; | |
10703 | ||
5e0116d5 RS |
10704 | *str += strlen (percent_op[i].str); |
10705 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10706 | |
5e0116d5 RS |
10707 | /* Check whether the output BFD supports this relocation. |
10708 | If not, issue an error and fall back on something safe. */ | |
10709 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10710 | { |
5e0116d5 RS |
10711 | as_bad ("relocation %s isn't supported by the current ABI", |
10712 | percent_op[i].str); | |
01a3f561 | 10713 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10714 | } |
5e0116d5 | 10715 | return TRUE; |
394f9b3a | 10716 | } |
5e0116d5 | 10717 | return FALSE; |
394f9b3a | 10718 | } |
ad8d3bb3 | 10719 | |
ad8d3bb3 | 10720 | |
5e0116d5 RS |
10721 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10722 | expression in *EP and the relocations in the array starting | |
10723 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10724 | |
01a3f561 | 10725 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10726 | |
5e0116d5 | 10727 | static size_t |
17a2f251 TS |
10728 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10729 | char *str) | |
ad8d3bb3 | 10730 | { |
5e0116d5 RS |
10731 | bfd_reloc_code_real_type reversed_reloc[3]; |
10732 | size_t reloc_index, i; | |
09b8f35a RS |
10733 | int crux_depth, str_depth; |
10734 | char *crux; | |
5e0116d5 RS |
10735 | |
10736 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10737 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10738 | of the main expression and with CRUX_DEPTH containing the number | |
10739 | of open brackets at that point. */ | |
10740 | reloc_index = -1; | |
10741 | str_depth = 0; | |
10742 | do | |
fb1b3232 | 10743 | { |
09b8f35a RS |
10744 | reloc_index++; |
10745 | crux = str; | |
10746 | crux_depth = str_depth; | |
10747 | ||
10748 | /* Skip over whitespace and brackets, keeping count of the number | |
10749 | of brackets. */ | |
10750 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10751 | if (*str++ == '(') | |
10752 | str_depth++; | |
5e0116d5 | 10753 | } |
09b8f35a RS |
10754 | while (*str == '%' |
10755 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10756 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10757 | |
09b8f35a | 10758 | my_getExpression (ep, crux); |
5e0116d5 | 10759 | str = expr_end; |
394f9b3a | 10760 | |
5e0116d5 | 10761 | /* Match every open bracket. */ |
09b8f35a | 10762 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10763 | if (*str++ == ')') |
09b8f35a | 10764 | crux_depth--; |
394f9b3a | 10765 | |
09b8f35a | 10766 | if (crux_depth > 0) |
5e0116d5 | 10767 | as_bad ("unclosed '('"); |
394f9b3a | 10768 | |
5e0116d5 | 10769 | expr_end = str; |
252b5132 | 10770 | |
01a3f561 | 10771 | if (reloc_index != 0) |
64bdfcaf RS |
10772 | { |
10773 | prev_reloc_op_frag = frag_now; | |
10774 | for (i = 0; i < reloc_index; i++) | |
10775 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10776 | } | |
fb1b3232 | 10777 | |
5e0116d5 | 10778 | return reloc_index; |
252b5132 RH |
10779 | } |
10780 | ||
10781 | static void | |
17a2f251 | 10782 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10783 | { |
10784 | char *save_in; | |
98aa84af | 10785 | valueT val; |
252b5132 RH |
10786 | |
10787 | save_in = input_line_pointer; | |
10788 | input_line_pointer = str; | |
10789 | expression (ep); | |
10790 | expr_end = input_line_pointer; | |
10791 | input_line_pointer = save_in; | |
10792 | ||
10793 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10794 | then we bump the value of the symbol by 1 since that is how other | |
10795 | text symbols are handled. We don't bother to handle complex | |
10796 | expressions, just `.' plus or minus a constant. */ | |
10797 | if (mips_opts.mips16 | |
10798 | && ep->X_op == O_symbol | |
10799 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10800 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10801 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10802 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10803 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10804 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10805 | } |
10806 | ||
252b5132 | 10807 | char * |
17a2f251 | 10808 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10809 | { |
499ac353 | 10810 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
10811 | } |
10812 | ||
10813 | void | |
17a2f251 | 10814 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10815 | { |
10816 | if (target_big_endian) | |
10817 | number_to_chars_bigendian (buf, val, n); | |
10818 | else | |
10819 | number_to_chars_littleendian (buf, val, n); | |
10820 | } | |
10821 | \f | |
ae948b86 | 10822 | #ifdef OBJ_ELF |
e013f690 TS |
10823 | static int support_64bit_objects(void) |
10824 | { | |
10825 | const char **list, **l; | |
aa3d8fdf | 10826 | int yes; |
e013f690 TS |
10827 | |
10828 | list = bfd_target_list (); | |
10829 | for (l = list; *l != NULL; l++) | |
10830 | #ifdef TE_TMIPS | |
10831 | /* This is traditional mips */ | |
10832 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10833 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10834 | #else | |
10835 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10836 | || strcmp (*l, "elf64-littlemips") == 0) | |
10837 | #endif | |
10838 | break; | |
aa3d8fdf | 10839 | yes = (*l != NULL); |
e013f690 | 10840 | free (list); |
aa3d8fdf | 10841 | return yes; |
e013f690 | 10842 | } |
ae948b86 | 10843 | #endif /* OBJ_ELF */ |
e013f690 | 10844 | |
78849248 | 10845 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10846 | |
e972090a NC |
10847 | struct option md_longopts[] = |
10848 | { | |
f9b4148d CD |
10849 | /* Options which specify architecture. */ |
10850 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10851 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10852 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10853 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10854 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10855 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10856 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10857 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10858 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10859 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10860 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10861 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10862 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10863 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10864 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10865 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10866 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10867 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10868 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10869 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10870 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10871 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10872 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10873 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10874 | |
10875 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10876 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10877 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10878 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10879 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10880 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10881 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10882 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10883 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10884 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10885 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10886 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10887 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10888 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10889 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10890 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10891 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10892 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10893 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10894 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10895 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10896 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
10897 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
10898 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
10899 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
10900 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
8b082fb1 TS |
10901 | #define OPTION_DSPR2 (OPTION_ASE_BASE + 12) |
10902 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
10903 | #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13) | |
10904 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
f9b4148d CD |
10905 | |
10906 | /* Old-style architecture options. Don't add more of these. */ | |
8b082fb1 | 10907 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14) |
f9b4148d CD |
10908 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10909 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10910 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10911 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10912 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10913 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10914 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10915 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10916 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10917 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10918 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10919 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10920 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10921 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10922 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10923 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10924 | ||
10925 | /* Options which enable bug fixes. */ | |
10926 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10927 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10928 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10929 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10930 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10931 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10932 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10933 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10934 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10935 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10936 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10937 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10938 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10939 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10940 | |
10941 | /* Miscellaneous options. */ | |
7d8e00cf | 10942 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10943 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10944 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10945 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10946 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10947 | {"break", no_argument, NULL, OPTION_BREAK}, |
10948 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10949 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10950 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10951 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10952 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10953 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10954 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10955 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10956 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10957 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10958 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10959 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10960 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10961 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10962 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10963 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10964 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10965 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10966 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10967 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10968 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10969 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10970 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10971 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10972 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10973 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10974 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10975 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10976 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
10977 | #define OPTION_SOFT_FLOAT (OPTION_MISC_BASE + 16) |
10978 | #define OPTION_HARD_FLOAT (OPTION_MISC_BASE + 17) | |
10979 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
10980 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
10981 | #define OPTION_SINGLE_FLOAT (OPTION_MISC_BASE + 18) | |
10982 | #define OPTION_DOUBLE_FLOAT (OPTION_MISC_BASE + 19) | |
10983 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
10984 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
10985 | ||
f9b4148d | 10986 | /* ELF-specific options. */ |
156c2f8b | 10987 | #ifdef OBJ_ELF |
037b32b9 | 10988 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 20) |
156c2f8b | 10989 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10990 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10991 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10992 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10993 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10994 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10995 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10996 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10997 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10998 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10999 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 11000 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 11001 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 11002 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 11003 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
11004 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
11005 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
11006 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
11007 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
11008 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
11009 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
11010 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
11011 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
11012 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
11013 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 11014 | #endif /* OBJ_ELF */ |
f9b4148d | 11015 | |
252b5132 RH |
11016 | {NULL, no_argument, NULL, 0} |
11017 | }; | |
156c2f8b | 11018 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11019 | |
316f5878 RS |
11020 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11021 | NEW_VALUE. Warn if another value was already specified. Note: | |
11022 | we have to defer parsing the -march and -mtune arguments in order | |
11023 | to handle 'from-abi' correctly, since the ABI might be specified | |
11024 | in a later argument. */ | |
11025 | ||
11026 | static void | |
17a2f251 | 11027 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11028 | { |
11029 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11030 | as_warn (_("A different %s was already specified, is now %s"), | |
11031 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11032 | new_value); | |
11033 | ||
11034 | *string_ptr = new_value; | |
11035 | } | |
11036 | ||
252b5132 | 11037 | int |
17a2f251 | 11038 | md_parse_option (int c, char *arg) |
252b5132 RH |
11039 | { |
11040 | switch (c) | |
11041 | { | |
119d663a NC |
11042 | case OPTION_CONSTRUCT_FLOATS: |
11043 | mips_disable_float_construction = 0; | |
11044 | break; | |
bdaaa2e1 | 11045 | |
119d663a NC |
11046 | case OPTION_NO_CONSTRUCT_FLOATS: |
11047 | mips_disable_float_construction = 1; | |
11048 | break; | |
bdaaa2e1 | 11049 | |
252b5132 RH |
11050 | case OPTION_TRAP: |
11051 | mips_trap = 1; | |
11052 | break; | |
11053 | ||
11054 | case OPTION_BREAK: | |
11055 | mips_trap = 0; | |
11056 | break; | |
11057 | ||
11058 | case OPTION_EB: | |
11059 | target_big_endian = 1; | |
11060 | break; | |
11061 | ||
11062 | case OPTION_EL: | |
11063 | target_big_endian = 0; | |
11064 | break; | |
11065 | ||
11066 | case 'O': | |
4ffff32f TS |
11067 | if (arg == NULL) |
11068 | mips_optimize = 1; | |
11069 | else if (arg[0] == '0') | |
11070 | mips_optimize = 0; | |
11071 | else if (arg[0] == '1') | |
252b5132 RH |
11072 | mips_optimize = 1; |
11073 | else | |
11074 | mips_optimize = 2; | |
11075 | break; | |
11076 | ||
11077 | case 'g': | |
11078 | if (arg == NULL) | |
11079 | mips_debug = 2; | |
11080 | else | |
11081 | mips_debug = atoi (arg); | |
252b5132 RH |
11082 | break; |
11083 | ||
11084 | case OPTION_MIPS1: | |
316f5878 | 11085 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11086 | break; |
11087 | ||
11088 | case OPTION_MIPS2: | |
316f5878 | 11089 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11090 | break; |
11091 | ||
11092 | case OPTION_MIPS3: | |
316f5878 | 11093 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11094 | break; |
11095 | ||
11096 | case OPTION_MIPS4: | |
316f5878 | 11097 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11098 | break; |
11099 | ||
84ea6cf2 | 11100 | case OPTION_MIPS5: |
316f5878 | 11101 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11102 | break; |
11103 | ||
e7af610e | 11104 | case OPTION_MIPS32: |
316f5878 | 11105 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11106 | break; |
11107 | ||
af7ee8bf CD |
11108 | case OPTION_MIPS32R2: |
11109 | file_mips_isa = ISA_MIPS32R2; | |
11110 | break; | |
11111 | ||
5f74bc13 CD |
11112 | case OPTION_MIPS64R2: |
11113 | file_mips_isa = ISA_MIPS64R2; | |
11114 | break; | |
11115 | ||
84ea6cf2 | 11116 | case OPTION_MIPS64: |
316f5878 | 11117 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11118 | break; |
11119 | ||
ec68c924 | 11120 | case OPTION_MTUNE: |
316f5878 RS |
11121 | mips_set_option_string (&mips_tune_string, arg); |
11122 | break; | |
ec68c924 | 11123 | |
316f5878 RS |
11124 | case OPTION_MARCH: |
11125 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11126 | break; |
11127 | ||
11128 | case OPTION_M4650: | |
316f5878 RS |
11129 | mips_set_option_string (&mips_arch_string, "4650"); |
11130 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11131 | break; |
11132 | ||
11133 | case OPTION_NO_M4650: | |
11134 | break; | |
11135 | ||
11136 | case OPTION_M4010: | |
316f5878 RS |
11137 | mips_set_option_string (&mips_arch_string, "4010"); |
11138 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11139 | break; |
11140 | ||
11141 | case OPTION_NO_M4010: | |
11142 | break; | |
11143 | ||
11144 | case OPTION_M4100: | |
316f5878 RS |
11145 | mips_set_option_string (&mips_arch_string, "4100"); |
11146 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11147 | break; |
11148 | ||
11149 | case OPTION_NO_M4100: | |
11150 | break; | |
11151 | ||
252b5132 | 11152 | case OPTION_M3900: |
316f5878 RS |
11153 | mips_set_option_string (&mips_arch_string, "3900"); |
11154 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11155 | break; |
bdaaa2e1 | 11156 | |
252b5132 RH |
11157 | case OPTION_NO_M3900: |
11158 | break; | |
11159 | ||
deec1734 CD |
11160 | case OPTION_MDMX: |
11161 | mips_opts.ase_mdmx = 1; | |
11162 | break; | |
11163 | ||
11164 | case OPTION_NO_MDMX: | |
11165 | mips_opts.ase_mdmx = 0; | |
11166 | break; | |
11167 | ||
74cd071d CF |
11168 | case OPTION_DSP: |
11169 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11170 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11171 | break; |
11172 | ||
11173 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11174 | mips_opts.ase_dsp = 0; |
11175 | mips_opts.ase_dspr2 = 0; | |
11176 | break; | |
11177 | ||
11178 | case OPTION_DSPR2: | |
11179 | mips_opts.ase_dspr2 = 1; | |
11180 | mips_opts.ase_dsp = 1; | |
11181 | break; | |
11182 | ||
11183 | case OPTION_NO_DSPR2: | |
11184 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11185 | mips_opts.ase_dsp = 0; |
11186 | break; | |
11187 | ||
ef2e4d86 CF |
11188 | case OPTION_MT: |
11189 | mips_opts.ase_mt = 1; | |
11190 | break; | |
11191 | ||
11192 | case OPTION_NO_MT: | |
11193 | mips_opts.ase_mt = 0; | |
11194 | break; | |
11195 | ||
252b5132 RH |
11196 | case OPTION_MIPS16: |
11197 | mips_opts.mips16 = 1; | |
7d10b47d | 11198 | mips_no_prev_insn (); |
252b5132 RH |
11199 | break; |
11200 | ||
11201 | case OPTION_NO_MIPS16: | |
11202 | mips_opts.mips16 = 0; | |
7d10b47d | 11203 | mips_no_prev_insn (); |
252b5132 RH |
11204 | break; |
11205 | ||
1f25f5d3 CD |
11206 | case OPTION_MIPS3D: |
11207 | mips_opts.ase_mips3d = 1; | |
11208 | break; | |
11209 | ||
11210 | case OPTION_NO_MIPS3D: | |
11211 | mips_opts.ase_mips3d = 0; | |
11212 | break; | |
11213 | ||
e16bfa71 TS |
11214 | case OPTION_SMARTMIPS: |
11215 | mips_opts.ase_smartmips = 1; | |
11216 | break; | |
11217 | ||
11218 | case OPTION_NO_SMARTMIPS: | |
11219 | mips_opts.ase_smartmips = 0; | |
11220 | break; | |
11221 | ||
d766e8ec RS |
11222 | case OPTION_FIX_VR4120: |
11223 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11224 | break; |
11225 | ||
d766e8ec RS |
11226 | case OPTION_NO_FIX_VR4120: |
11227 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11228 | break; |
11229 | ||
7d8e00cf RS |
11230 | case OPTION_FIX_VR4130: |
11231 | mips_fix_vr4130 = 1; | |
11232 | break; | |
11233 | ||
11234 | case OPTION_NO_FIX_VR4130: | |
11235 | mips_fix_vr4130 = 0; | |
11236 | break; | |
11237 | ||
4a6a3df4 AO |
11238 | case OPTION_RELAX_BRANCH: |
11239 | mips_relax_branch = 1; | |
11240 | break; | |
11241 | ||
11242 | case OPTION_NO_RELAX_BRANCH: | |
11243 | mips_relax_branch = 0; | |
11244 | break; | |
11245 | ||
aa6975fb ILT |
11246 | case OPTION_MSHARED: |
11247 | mips_in_shared = TRUE; | |
11248 | break; | |
11249 | ||
11250 | case OPTION_MNO_SHARED: | |
11251 | mips_in_shared = FALSE; | |
11252 | break; | |
11253 | ||
aed1a261 RS |
11254 | case OPTION_MSYM32: |
11255 | mips_opts.sym32 = TRUE; | |
11256 | break; | |
11257 | ||
11258 | case OPTION_MNO_SYM32: | |
11259 | mips_opts.sym32 = FALSE; | |
11260 | break; | |
11261 | ||
0f074f60 | 11262 | #ifdef OBJ_ELF |
252b5132 RH |
11263 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11264 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11265 | intended to be compatible with Irix 5. */ | |
11266 | case OPTION_CALL_SHARED: | |
f43abd2b | 11267 | if (!IS_ELF) |
252b5132 RH |
11268 | { |
11269 | as_bad (_("-call_shared is supported only for ELF format")); | |
11270 | return 0; | |
11271 | } | |
11272 | mips_pic = SVR4_PIC; | |
143d77c5 | 11273 | mips_abicalls = TRUE; |
252b5132 RH |
11274 | break; |
11275 | ||
11276 | case OPTION_NON_SHARED: | |
f43abd2b | 11277 | if (!IS_ELF) |
252b5132 RH |
11278 | { |
11279 | as_bad (_("-non_shared is supported only for ELF format")); | |
11280 | return 0; | |
11281 | } | |
11282 | mips_pic = NO_PIC; | |
143d77c5 | 11283 | mips_abicalls = FALSE; |
252b5132 RH |
11284 | break; |
11285 | ||
44075ae2 TS |
11286 | /* The -xgot option tells the assembler to use 32 bit offsets |
11287 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11288 | compatibility. */ |
11289 | case OPTION_XGOT: | |
11290 | mips_big_got = 1; | |
11291 | break; | |
0f074f60 | 11292 | #endif /* OBJ_ELF */ |
252b5132 RH |
11293 | |
11294 | case 'G': | |
6caf9ef4 TS |
11295 | g_switch_value = atoi (arg); |
11296 | g_switch_seen = 1; | |
252b5132 RH |
11297 | break; |
11298 | ||
0f074f60 | 11299 | #ifdef OBJ_ELF |
34ba82a8 TS |
11300 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11301 | and -mabi=64. */ | |
252b5132 | 11302 | case OPTION_32: |
f43abd2b | 11303 | if (!IS_ELF) |
34ba82a8 TS |
11304 | { |
11305 | as_bad (_("-32 is supported for ELF format only")); | |
11306 | return 0; | |
11307 | } | |
316f5878 | 11308 | mips_abi = O32_ABI; |
252b5132 RH |
11309 | break; |
11310 | ||
e013f690 | 11311 | case OPTION_N32: |
f43abd2b | 11312 | if (!IS_ELF) |
34ba82a8 TS |
11313 | { |
11314 | as_bad (_("-n32 is supported for ELF format only")); | |
11315 | return 0; | |
11316 | } | |
316f5878 | 11317 | mips_abi = N32_ABI; |
e013f690 | 11318 | break; |
252b5132 | 11319 | |
e013f690 | 11320 | case OPTION_64: |
f43abd2b | 11321 | if (!IS_ELF) |
34ba82a8 TS |
11322 | { |
11323 | as_bad (_("-64 is supported for ELF format only")); | |
11324 | return 0; | |
11325 | } | |
316f5878 | 11326 | mips_abi = N64_ABI; |
f43abd2b | 11327 | if (!support_64bit_objects()) |
e013f690 | 11328 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11329 | break; |
ae948b86 | 11330 | #endif /* OBJ_ELF */ |
252b5132 | 11331 | |
c97ef257 | 11332 | case OPTION_GP32: |
a325df1d | 11333 | file_mips_gp32 = 1; |
c97ef257 AH |
11334 | break; |
11335 | ||
11336 | case OPTION_GP64: | |
a325df1d | 11337 | file_mips_gp32 = 0; |
c97ef257 | 11338 | break; |
252b5132 | 11339 | |
ca4e0257 | 11340 | case OPTION_FP32: |
a325df1d | 11341 | file_mips_fp32 = 1; |
316f5878 RS |
11342 | break; |
11343 | ||
11344 | case OPTION_FP64: | |
11345 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11346 | break; |
11347 | ||
037b32b9 AN |
11348 | case OPTION_SINGLE_FLOAT: |
11349 | file_mips_single_float = 1; | |
11350 | break; | |
11351 | ||
11352 | case OPTION_DOUBLE_FLOAT: | |
11353 | file_mips_single_float = 0; | |
11354 | break; | |
11355 | ||
11356 | case OPTION_SOFT_FLOAT: | |
11357 | file_mips_soft_float = 1; | |
11358 | break; | |
11359 | ||
11360 | case OPTION_HARD_FLOAT: | |
11361 | file_mips_soft_float = 0; | |
11362 | break; | |
11363 | ||
ae948b86 | 11364 | #ifdef OBJ_ELF |
252b5132 | 11365 | case OPTION_MABI: |
f43abd2b | 11366 | if (!IS_ELF) |
34ba82a8 TS |
11367 | { |
11368 | as_bad (_("-mabi is supported for ELF format only")); | |
11369 | return 0; | |
11370 | } | |
e013f690 | 11371 | if (strcmp (arg, "32") == 0) |
316f5878 | 11372 | mips_abi = O32_ABI; |
e013f690 | 11373 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11374 | mips_abi = O64_ABI; |
e013f690 | 11375 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11376 | mips_abi = N32_ABI; |
e013f690 TS |
11377 | else if (strcmp (arg, "64") == 0) |
11378 | { | |
316f5878 | 11379 | mips_abi = N64_ABI; |
e013f690 TS |
11380 | if (! support_64bit_objects()) |
11381 | as_fatal (_("No compiled in support for 64 bit object file " | |
11382 | "format")); | |
11383 | } | |
11384 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11385 | mips_abi = EABI_ABI; |
e013f690 | 11386 | else |
da0e507f TS |
11387 | { |
11388 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11389 | return 0; | |
11390 | } | |
252b5132 | 11391 | break; |
e013f690 | 11392 | #endif /* OBJ_ELF */ |
252b5132 | 11393 | |
6b76fefe | 11394 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11395 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11396 | break; |
11397 | ||
9ee72ff1 | 11398 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11399 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11400 | break; |
11401 | ||
ecb4347a DJ |
11402 | #ifdef OBJ_ELF |
11403 | case OPTION_MDEBUG: | |
b34976b6 | 11404 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11405 | break; |
11406 | ||
11407 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11408 | mips_flag_mdebug = FALSE; |
ecb4347a | 11409 | break; |
dcd410fe RO |
11410 | |
11411 | case OPTION_PDR: | |
11412 | mips_flag_pdr = TRUE; | |
11413 | break; | |
11414 | ||
11415 | case OPTION_NO_PDR: | |
11416 | mips_flag_pdr = FALSE; | |
11417 | break; | |
0a44bf69 RS |
11418 | |
11419 | case OPTION_MVXWORKS_PIC: | |
11420 | mips_pic = VXWORKS_PIC; | |
11421 | break; | |
ecb4347a DJ |
11422 | #endif /* OBJ_ELF */ |
11423 | ||
252b5132 RH |
11424 | default: |
11425 | return 0; | |
11426 | } | |
11427 | ||
11428 | return 1; | |
11429 | } | |
316f5878 RS |
11430 | \f |
11431 | /* Set up globals to generate code for the ISA or processor | |
11432 | described by INFO. */ | |
252b5132 | 11433 | |
252b5132 | 11434 | static void |
17a2f251 | 11435 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11436 | { |
316f5878 | 11437 | if (info != 0) |
252b5132 | 11438 | { |
fef14a42 TS |
11439 | file_mips_arch = info->cpu; |
11440 | mips_opts.arch = info->cpu; | |
316f5878 | 11441 | mips_opts.isa = info->isa; |
252b5132 | 11442 | } |
252b5132 RH |
11443 | } |
11444 | ||
252b5132 | 11445 | |
316f5878 | 11446 | /* Likewise for tuning. */ |
252b5132 | 11447 | |
316f5878 | 11448 | static void |
17a2f251 | 11449 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11450 | { |
11451 | if (info != 0) | |
fef14a42 | 11452 | mips_tune = info->cpu; |
316f5878 | 11453 | } |
80cc45a5 | 11454 | |
34ba82a8 | 11455 | |
252b5132 | 11456 | void |
17a2f251 | 11457 | mips_after_parse_args (void) |
e9670677 | 11458 | { |
fef14a42 TS |
11459 | const struct mips_cpu_info *arch_info = 0; |
11460 | const struct mips_cpu_info *tune_info = 0; | |
11461 | ||
e9670677 | 11462 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11463 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11464 | { |
6caf9ef4 | 11465 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11466 | as_bad (_("-G not supported in this configuration.")); |
11467 | g_switch_value = 0; | |
11468 | } | |
11469 | ||
cac012d6 AO |
11470 | if (mips_abi == NO_ABI) |
11471 | mips_abi = MIPS_DEFAULT_ABI; | |
11472 | ||
22923709 RS |
11473 | /* The following code determines the architecture and register size. |
11474 | Similar code was added to GCC 3.3 (see override_options() in | |
11475 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11476 | as much as possible. */ | |
e9670677 | 11477 | |
316f5878 | 11478 | if (mips_arch_string != 0) |
fef14a42 | 11479 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11480 | |
316f5878 | 11481 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11482 | { |
316f5878 | 11483 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11484 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11485 | the -march selection (if any). */ |
fef14a42 | 11486 | if (arch_info != 0) |
e9670677 | 11487 | { |
316f5878 RS |
11488 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11489 | There's no harm in specifying both as long as the ISA levels | |
11490 | are the same. */ | |
fef14a42 | 11491 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11492 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11493 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11494 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11495 | } |
316f5878 | 11496 | else |
fef14a42 | 11497 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11498 | } |
11499 | ||
fef14a42 TS |
11500 | if (arch_info == 0) |
11501 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11502 | |
fef14a42 | 11503 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11504 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11505 | arch_info->name); |
11506 | ||
11507 | mips_set_architecture (arch_info); | |
11508 | ||
11509 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11510 | if (mips_tune_string != 0) | |
11511 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11512 | |
fef14a42 TS |
11513 | if (tune_info == 0) |
11514 | mips_set_tune (arch_info); | |
11515 | else | |
11516 | mips_set_tune (tune_info); | |
e9670677 | 11517 | |
316f5878 | 11518 | if (file_mips_gp32 >= 0) |
e9670677 | 11519 | { |
316f5878 RS |
11520 | /* The user specified the size of the integer registers. Make sure |
11521 | it agrees with the ABI and ISA. */ | |
11522 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11523 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11524 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11525 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11526 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11527 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11528 | } |
11529 | else | |
11530 | { | |
316f5878 RS |
11531 | /* Infer the integer register size from the ABI and processor. |
11532 | Restrict ourselves to 32-bit registers if that's all the | |
11533 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11534 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11535 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11536 | } |
11537 | ||
ad3fea08 TS |
11538 | switch (file_mips_fp32) |
11539 | { | |
11540 | default: | |
11541 | case -1: | |
11542 | /* No user specified float register size. | |
11543 | ??? GAS treats single-float processors as though they had 64-bit | |
11544 | float registers (although it complains when double-precision | |
11545 | instructions are used). As things stand, saying they have 32-bit | |
11546 | registers would lead to spurious "register must be even" messages. | |
11547 | So here we assume float registers are never smaller than the | |
11548 | integer ones. */ | |
11549 | if (file_mips_gp32 == 0) | |
11550 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11551 | file_mips_fp32 = 0; | |
11552 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11553 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11554 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11555 | file_mips_fp32 = 0; | |
11556 | else | |
11557 | /* 32-bit float registers. */ | |
11558 | file_mips_fp32 = 1; | |
11559 | break; | |
11560 | ||
11561 | /* The user specified the size of the float registers. Check if it | |
11562 | agrees with the ABI and ISA. */ | |
11563 | case 0: | |
11564 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11565 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11566 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11567 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11568 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11569 | break; | |
11570 | case 1: | |
11571 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11572 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11573 | break; | |
11574 | } | |
e9670677 | 11575 | |
316f5878 | 11576 | /* End of GCC-shared inference code. */ |
e9670677 | 11577 | |
17a2f251 TS |
11578 | /* This flag is set when we have a 64-bit capable CPU but use only |
11579 | 32-bit wide registers. Note that EABI does not use it. */ | |
11580 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11581 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11582 | || mips_abi == O32_ABI)) | |
316f5878 | 11583 | mips_32bitmode = 1; |
e9670677 MR |
11584 | |
11585 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11586 | as_bad (_("trap exception not supported at ISA 1")); | |
11587 | ||
e9670677 MR |
11588 | /* If the selected architecture includes support for ASEs, enable |
11589 | generation of code for them. */ | |
a4672219 | 11590 | if (mips_opts.mips16 == -1) |
fef14a42 | 11591 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11592 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 11593 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
11594 | && file_mips_fp32 == 0) ? 1 : 0; |
11595 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
11596 | as_bad (_("-mfp32 used with -mips3d")); | |
11597 | ||
ffdefa66 | 11598 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 11599 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
11600 | && file_mips_fp32 == 0) ? 1 : 0; |
11601 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
11602 | as_bad (_("-mfp32 used with -mdmx")); | |
11603 | ||
11604 | if (mips_opts.ase_smartmips == -1) | |
11605 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
11606 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
11607 | as_warn ("%s ISA does not support SmartMIPS", | |
11608 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11609 | ||
74cd071d | 11610 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
11611 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
11612 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
11613 | as_warn ("%s ISA does not support DSP ASE", | |
11614 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11615 | ||
8b082fb1 TS |
11616 | if (mips_opts.ase_dspr2 == -1) |
11617 | { | |
11618 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
11619 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
11620 | } | |
11621 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
11622 | as_warn ("%s ISA does not support DSP R2 ASE", | |
11623 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11624 | ||
ef2e4d86 | 11625 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
11626 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
11627 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
8b082fb1 | 11628 | as_warn ("%s ISA does not support MT ASE", |
ad3fea08 | 11629 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
e9670677 | 11630 | |
e9670677 | 11631 | file_mips_isa = mips_opts.isa; |
a4672219 | 11632 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11633 | file_ase_mips3d = mips_opts.ase_mips3d; |
11634 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11635 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11636 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 11637 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 11638 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11639 | mips_opts.gp32 = file_mips_gp32; |
11640 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
11641 | mips_opts.soft_float = file_mips_soft_float; |
11642 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 11643 | |
ecb4347a DJ |
11644 | if (mips_flag_mdebug < 0) |
11645 | { | |
11646 | #ifdef OBJ_MAYBE_ECOFF | |
11647 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11648 | mips_flag_mdebug = 1; | |
11649 | else | |
11650 | #endif /* OBJ_MAYBE_ECOFF */ | |
11651 | mips_flag_mdebug = 0; | |
11652 | } | |
e9670677 MR |
11653 | } |
11654 | \f | |
11655 | void | |
17a2f251 | 11656 | mips_init_after_args (void) |
252b5132 RH |
11657 | { |
11658 | /* initialize opcodes */ | |
11659 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11660 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11661 | } |
11662 | ||
11663 | long | |
17a2f251 | 11664 | md_pcrel_from (fixS *fixP) |
252b5132 | 11665 | { |
a7ebbfdf TS |
11666 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11667 | switch (fixP->fx_r_type) | |
11668 | { | |
11669 | case BFD_RELOC_16_PCREL_S2: | |
11670 | case BFD_RELOC_MIPS_JMP: | |
11671 | /* Return the address of the delay slot. */ | |
11672 | return addr + 4; | |
11673 | default: | |
58ea3d6a | 11674 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
11675 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
11676 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11677 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
11678 | return addr; |
11679 | } | |
252b5132 RH |
11680 | } |
11681 | ||
252b5132 RH |
11682 | /* This is called before the symbol table is processed. In order to |
11683 | work with gcc when using mips-tfile, we must keep all local labels. | |
11684 | However, in other cases, we want to discard them. If we were | |
11685 | called with -g, but we didn't see any debugging information, it may | |
11686 | mean that gcc is smuggling debugging information through to | |
11687 | mips-tfile, in which case we must generate all local labels. */ | |
11688 | ||
11689 | void | |
17a2f251 | 11690 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11691 | { |
11692 | #ifndef NO_ECOFF_DEBUGGING | |
11693 | if (ECOFF_DEBUGGING | |
11694 | && mips_debug != 0 | |
11695 | && ! ecoff_debugging_seen) | |
11696 | flag_keep_locals = 1; | |
11697 | #endif | |
11698 | } | |
11699 | ||
3b91255e | 11700 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11701 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11702 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11703 | relocation operators. | |
11704 | ||
11705 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11706 | expression if: | |
11707 | ||
11708 | (a) it refers to the same symbol; and | |
11709 | (b) the offset applied in the %lo() expression is no lower than | |
11710 | the offset applied in the %got() or %hi(). | |
11711 | ||
11712 | (b) allows us to cope with code like: | |
11713 | ||
11714 | lui $4,%hi(foo) | |
11715 | lh $4,%lo(foo+2)($4) | |
11716 | ||
11717 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11718 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11719 | the high 16 bits. | |
11720 | ||
11721 | When several %lo()s match a particular %got() or %hi(), we use the | |
11722 | following rules to distinguish them: | |
11723 | ||
11724 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11725 | higher offsets. | |
11726 | ||
11727 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11728 | that already have a matching %got() or %hi(). | |
11729 | ||
11730 | (3) later %lo()s are better than earlier %lo()s. | |
11731 | ||
11732 | These rules are applied in order. | |
11733 | ||
11734 | (1) means, among other things, that %lo()s with identical offsets are | |
11735 | chosen if they exist. | |
11736 | ||
11737 | (2) means that we won't associate several high-part relocations with | |
11738 | the same low-part relocation unless there's no alternative. Having | |
11739 | several high parts for the same low part is a GNU extension; this rule | |
11740 | allows careful users to avoid it. | |
11741 | ||
11742 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11743 | with the last high-part relocation being at the front of the list. | |
11744 | It therefore makes sense to choose the last matching low-part | |
11745 | relocation, all other things being equal. It's also easier | |
11746 | to code that way. */ | |
252b5132 RH |
11747 | |
11748 | void | |
17a2f251 | 11749 | mips_frob_file (void) |
252b5132 RH |
11750 | { |
11751 | struct mips_hi_fixup *l; | |
35903be0 | 11752 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
11753 | |
11754 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11755 | { | |
11756 | segment_info_type *seginfo; | |
3b91255e RS |
11757 | bfd_boolean matched_lo_p; |
11758 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11759 | |
5919d012 | 11760 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11761 | |
5919d012 RS |
11762 | /* If a GOT16 relocation turns out to be against a global symbol, |
11763 | there isn't supposed to be a matching LO. */ | |
11764 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11765 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11766 | continue; | |
11767 | ||
11768 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11769 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11770 | continue; |
11771 | ||
252b5132 | 11772 | seginfo = seg_info (l->seg); |
252b5132 | 11773 | |
3b91255e RS |
11774 | /* Set HI_POS to the position of this relocation in the chain. |
11775 | Set LO_POS to the position of the chosen low-part relocation. | |
11776 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11777 | relocation that matches an immediately-preceding high-part | |
11778 | relocation. */ | |
11779 | hi_pos = NULL; | |
11780 | lo_pos = NULL; | |
11781 | matched_lo_p = FALSE; | |
35903be0 CM |
11782 | |
11783 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS16_HI16 | |
11784 | || l->fixp->fx_r_type == BFD_RELOC_MIPS16_HI16_S) | |
11785 | looking_for_rtype = BFD_RELOC_MIPS16_LO16; | |
11786 | else | |
11787 | looking_for_rtype = BFD_RELOC_LO16; | |
11788 | ||
3b91255e RS |
11789 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
11790 | { | |
11791 | if (*pos == l->fixp) | |
11792 | hi_pos = pos; | |
11793 | ||
35903be0 | 11794 | if ((*pos)->fx_r_type == looking_for_rtype |
3b91255e RS |
11795 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11796 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11797 | && (lo_pos == NULL | |
11798 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11799 | || (!matched_lo_p | |
11800 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11801 | lo_pos = pos; | |
11802 | ||
11803 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11804 | && fixup_has_matching_lo_p (*pos)); | |
11805 | } | |
11806 | ||
11807 | /* If we found a match, remove the high-part relocation from its | |
11808 | current position and insert it before the low-part relocation. | |
11809 | Make the offsets match so that fixup_has_matching_lo_p() | |
11810 | will return true. | |
11811 | ||
11812 | We don't warn about unmatched high-part relocations since some | |
11813 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11814 | instructions. */ | |
11815 | if (lo_pos != NULL) | |
11816 | { | |
11817 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11818 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11819 | { |
3b91255e RS |
11820 | *hi_pos = l->fixp->fx_next; |
11821 | l->fixp->fx_next = *lo_pos; | |
11822 | *lo_pos = l->fixp; | |
252b5132 | 11823 | } |
252b5132 RH |
11824 | } |
11825 | } | |
11826 | } | |
11827 | ||
3e722fb5 | 11828 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11829 | We have to prevent gas from dropping them. */ |
252b5132 | 11830 | |
252b5132 | 11831 | int |
17a2f251 | 11832 | mips_force_relocation (fixS *fixp) |
252b5132 | 11833 | { |
ae6063d4 | 11834 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11835 | return 1; |
11836 | ||
f6688943 TS |
11837 | if (HAVE_NEWABI |
11838 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11839 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11840 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11841 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11842 | return 1; | |
11843 | ||
3e722fb5 | 11844 | return 0; |
252b5132 RH |
11845 | } |
11846 | ||
11847 | /* Apply a fixup to the object file. */ | |
11848 | ||
94f592af | 11849 | void |
55cf6793 | 11850 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11851 | { |
874e8986 | 11852 | bfd_byte *buf; |
98aa84af | 11853 | long insn; |
a7ebbfdf | 11854 | reloc_howto_type *howto; |
252b5132 | 11855 | |
a7ebbfdf TS |
11856 | /* We ignore generic BFD relocations we don't know about. */ |
11857 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11858 | if (! howto) | |
11859 | return; | |
65551fa4 | 11860 | |
252b5132 RH |
11861 | assert (fixP->fx_size == 4 |
11862 | || fixP->fx_r_type == BFD_RELOC_16 | |
11863 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11864 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11865 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11866 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
741d6ea8 JM |
11867 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
11868 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 11869 | |
a7ebbfdf | 11870 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11871 | |
3994f87e | 11872 | assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
11873 | |
11874 | /* Don't treat parts of a composite relocation as done. There are two | |
11875 | reasons for this: | |
11876 | ||
11877 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11878 | should nevertheless be emitted if the first part is. | |
11879 | ||
11880 | (2) In normal usage, composite relocations are never assembly-time | |
11881 | constants. The easiest way of dealing with the pathological | |
11882 | exceptions is to generate a relocation against STN_UNDEF and | |
11883 | leave everything up to the linker. */ | |
3994f87e | 11884 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
11885 | fixP->fx_done = 1; |
11886 | ||
11887 | switch (fixP->fx_r_type) | |
11888 | { | |
3f98094e DJ |
11889 | case BFD_RELOC_MIPS_TLS_GD: |
11890 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
11891 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
11892 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
11893 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
11894 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11895 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11896 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11897 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11898 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11899 | /* fall through */ | |
11900 | ||
252b5132 | 11901 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11902 | case BFD_RELOC_MIPS_SHIFT5: |
11903 | case BFD_RELOC_MIPS_SHIFT6: | |
11904 | case BFD_RELOC_MIPS_GOT_DISP: | |
11905 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11906 | case BFD_RELOC_MIPS_GOT_OFST: | |
11907 | case BFD_RELOC_MIPS_SUB: | |
11908 | case BFD_RELOC_MIPS_INSERT_A: | |
11909 | case BFD_RELOC_MIPS_INSERT_B: | |
11910 | case BFD_RELOC_MIPS_DELETE: | |
11911 | case BFD_RELOC_MIPS_HIGHEST: | |
11912 | case BFD_RELOC_MIPS_HIGHER: | |
11913 | case BFD_RELOC_MIPS_SCN_DISP: | |
11914 | case BFD_RELOC_MIPS_REL16: | |
11915 | case BFD_RELOC_MIPS_RELGOT: | |
11916 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11917 | case BFD_RELOC_HI16: |
11918 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11919 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11920 | case BFD_RELOC_MIPS_LITERAL: |
11921 | case BFD_RELOC_MIPS_CALL16: | |
11922 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11923 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11924 | case BFD_RELOC_MIPS_GOT_HI16: |
11925 | case BFD_RELOC_MIPS_GOT_LO16: | |
11926 | case BFD_RELOC_MIPS_CALL_HI16: | |
11927 | case BFD_RELOC_MIPS_CALL_LO16: | |
11928 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11929 | case BFD_RELOC_MIPS16_HI16: |
11930 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 11931 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 11932 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
11933 | break; |
11934 | ||
252b5132 RH |
11935 | case BFD_RELOC_64: |
11936 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11937 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11938 | if (fixP->fx_done) |
252b5132 RH |
11939 | { |
11940 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11941 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11942 | else |
11943 | { | |
a7ebbfdf | 11944 | valueT hiv; |
252b5132 | 11945 | |
a7ebbfdf | 11946 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11947 | hiv = 0xffffffff; |
11948 | else | |
11949 | hiv = 0; | |
b215186b | 11950 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11951 | *valP, 4); |
b215186b | 11952 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11953 | hiv, 4); |
252b5132 RH |
11954 | } |
11955 | } | |
11956 | break; | |
11957 | ||
056350c6 | 11958 | case BFD_RELOC_RVA: |
252b5132 | 11959 | case BFD_RELOC_32: |
252b5132 RH |
11960 | case BFD_RELOC_16: |
11961 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
11962 | value now. This can happen if we have a .word which is not |
11963 | resolved when it appears but is later defined. */ | |
252b5132 | 11964 | if (fixP->fx_done) |
54f4ddb3 | 11965 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
11966 | break; |
11967 | ||
11968 | case BFD_RELOC_LO16: | |
d6f16593 | 11969 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11970 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11971 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11972 | /* When handling an embedded PIC switch statement, we can wind |
11973 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11974 | if (fixP->fx_done) | |
11975 | { | |
a7ebbfdf | 11976 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11977 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11978 | _("relocation overflow")); | |
252b5132 RH |
11979 | if (target_big_endian) |
11980 | buf += 2; | |
2132e3a3 | 11981 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11982 | } |
11983 | break; | |
11984 | ||
11985 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11986 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11987 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 11988 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 11989 | |
54f4ddb3 TS |
11990 | /* We need to save the bits in the instruction since fixup_segment() |
11991 | might be deleting the relocation entry (i.e., a branch within | |
11992 | the current segment). */ | |
a7ebbfdf | 11993 | if (! fixP->fx_done) |
bb2d6cd7 | 11994 | break; |
252b5132 | 11995 | |
54f4ddb3 | 11996 | /* Update old instruction data. */ |
252b5132 RH |
11997 | if (target_big_endian) |
11998 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11999 | else | |
12000 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12001 | ||
a7ebbfdf TS |
12002 | if (*valP + 0x20000 <= 0x3ffff) |
12003 | { | |
12004 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12005 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12006 | } |
12007 | else if (mips_pic == NO_PIC | |
12008 | && fixP->fx_done | |
12009 | && fixP->fx_frag->fr_address >= text_section->vma | |
12010 | && (fixP->fx_frag->fr_address | |
587aac4e | 12011 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12012 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12013 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12014 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12015 | { |
12016 | /* The branch offset is too large. If this is an | |
12017 | unconditional branch, and we are not generating PIC code, | |
12018 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12019 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12020 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12021 | else |
a7ebbfdf TS |
12022 | insn = 0x08000000; /* j */ |
12023 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12024 | fixP->fx_done = 0; | |
12025 | fixP->fx_addsy = section_symbol (text_section); | |
12026 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12027 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12028 | } |
12029 | else | |
12030 | { | |
12031 | /* If we got here, we have branch-relaxation disabled, | |
12032 | and there's nothing we can do to fix this instruction | |
12033 | without turning it into a longer sequence. */ | |
12034 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12035 | _("Branch out of range")); | |
252b5132 | 12036 | } |
252b5132 RH |
12037 | break; |
12038 | ||
12039 | case BFD_RELOC_VTABLE_INHERIT: | |
12040 | fixP->fx_done = 0; | |
12041 | if (fixP->fx_addsy | |
12042 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12043 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12044 | S_SET_WEAK (fixP->fx_addsy); | |
12045 | break; | |
12046 | ||
12047 | case BFD_RELOC_VTABLE_ENTRY: | |
12048 | fixP->fx_done = 0; | |
12049 | break; | |
12050 | ||
12051 | default: | |
12052 | internalError (); | |
12053 | } | |
a7ebbfdf TS |
12054 | |
12055 | /* Remember value for tc_gen_reloc. */ | |
12056 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12057 | } |
12058 | ||
252b5132 | 12059 | static symbolS * |
17a2f251 | 12060 | get_symbol (void) |
252b5132 RH |
12061 | { |
12062 | int c; | |
12063 | char *name; | |
12064 | symbolS *p; | |
12065 | ||
12066 | name = input_line_pointer; | |
12067 | c = get_symbol_end (); | |
12068 | p = (symbolS *) symbol_find_or_make (name); | |
12069 | *input_line_pointer = c; | |
12070 | return p; | |
12071 | } | |
12072 | ||
742a56fe RS |
12073 | /* Align the current frag to a given power of two. If a particular |
12074 | fill byte should be used, FILL points to an integer that contains | |
12075 | that byte, otherwise FILL is null. | |
12076 | ||
12077 | The MIPS assembler also automatically adjusts any preceding | |
12078 | label. */ | |
252b5132 RH |
12079 | |
12080 | static void | |
742a56fe | 12081 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12082 | { |
7d10b47d | 12083 | mips_emit_delays (); |
742a56fe RS |
12084 | mips_record_mips16_mode (); |
12085 | if (fill == NULL && subseg_text_p (now_seg)) | |
12086 | frag_align_code (to, 0); | |
12087 | else | |
12088 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12089 | record_alignment (now_seg, to); |
12090 | if (label != NULL) | |
12091 | { | |
12092 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 12093 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12094 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12095 | } | |
12096 | } | |
12097 | ||
12098 | /* Align to a given power of two. .align 0 turns off the automatic | |
12099 | alignment used by the data creating pseudo-ops. */ | |
12100 | ||
12101 | static void | |
17a2f251 | 12102 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12103 | { |
742a56fe | 12104 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12105 | long max_alignment = 28; |
252b5132 | 12106 | |
54f4ddb3 | 12107 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12108 | to the aligned address. |
54f4ddb3 | 12109 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12110 | a .align pseudo instruction. |
54f4ddb3 | 12111 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12112 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12113 | We don't. */ |
252b5132 RH |
12114 | |
12115 | temp = get_absolute_expression (); | |
12116 | if (temp > max_alignment) | |
12117 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12118 | else if (temp < 0) | |
12119 | { | |
12120 | as_warn (_("Alignment negative: 0 assumed.")); | |
12121 | temp = 0; | |
12122 | } | |
12123 | if (*input_line_pointer == ',') | |
12124 | { | |
f9419b05 | 12125 | ++input_line_pointer; |
742a56fe RS |
12126 | fill_value = get_absolute_expression (); |
12127 | fill_ptr = &fill_value; | |
252b5132 RH |
12128 | } |
12129 | else | |
742a56fe | 12130 | fill_ptr = 0; |
252b5132 RH |
12131 | if (temp) |
12132 | { | |
a8dbcb85 TS |
12133 | segment_info_type *si = seg_info (now_seg); |
12134 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12135 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12136 | auto_align = 1; |
742a56fe | 12137 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12138 | } |
12139 | else | |
12140 | { | |
12141 | auto_align = 0; | |
12142 | } | |
12143 | ||
12144 | demand_empty_rest_of_line (); | |
12145 | } | |
12146 | ||
252b5132 | 12147 | static void |
17a2f251 | 12148 | s_change_sec (int sec) |
252b5132 RH |
12149 | { |
12150 | segT seg; | |
12151 | ||
252b5132 RH |
12152 | #ifdef OBJ_ELF |
12153 | /* The ELF backend needs to know that we are changing sections, so | |
12154 | that .previous works correctly. We could do something like check | |
b6ff326e | 12155 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12156 | as it would not be appropriate to use it in the section changing |
12157 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12158 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12159 | if (IS_ELF) |
12160 | obj_elf_section_change_hook (); | |
252b5132 RH |
12161 | #endif |
12162 | ||
7d10b47d | 12163 | mips_emit_delays (); |
252b5132 RH |
12164 | switch (sec) |
12165 | { | |
12166 | case 't': | |
12167 | s_text (0); | |
12168 | break; | |
12169 | case 'd': | |
12170 | s_data (0); | |
12171 | break; | |
12172 | case 'b': | |
12173 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12174 | demand_empty_rest_of_line (); | |
12175 | break; | |
12176 | ||
12177 | case 'r': | |
4d0d148d TS |
12178 | seg = subseg_new (RDATA_SECTION_NAME, |
12179 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12180 | if (IS_ELF) |
252b5132 | 12181 | { |
4d0d148d TS |
12182 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12183 | | SEC_READONLY | SEC_RELOC | |
12184 | | SEC_DATA)); | |
c41e87e3 | 12185 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12186 | record_alignment (seg, 4); |
252b5132 | 12187 | } |
4d0d148d | 12188 | demand_empty_rest_of_line (); |
252b5132 RH |
12189 | break; |
12190 | ||
12191 | case 's': | |
4d0d148d | 12192 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12193 | if (IS_ELF) |
252b5132 | 12194 | { |
4d0d148d TS |
12195 | bfd_set_section_flags (stdoutput, seg, |
12196 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12197 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12198 | record_alignment (seg, 4); |
252b5132 | 12199 | } |
4d0d148d TS |
12200 | demand_empty_rest_of_line (); |
12201 | break; | |
252b5132 RH |
12202 | } |
12203 | ||
12204 | auto_align = 1; | |
12205 | } | |
b34976b6 | 12206 | |
cca86cc8 | 12207 | void |
17a2f251 | 12208 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12209 | { |
7ed4a06a | 12210 | #ifdef OBJ_ELF |
cca86cc8 SC |
12211 | char *section_name; |
12212 | char c; | |
684022ea | 12213 | char next_c = 0; |
cca86cc8 SC |
12214 | int section_type; |
12215 | int section_flag; | |
12216 | int section_entry_size; | |
12217 | int section_alignment; | |
b34976b6 | 12218 | |
f43abd2b | 12219 | if (!IS_ELF) |
7ed4a06a TS |
12220 | return; |
12221 | ||
cca86cc8 SC |
12222 | section_name = input_line_pointer; |
12223 | c = get_symbol_end (); | |
a816d1ed AO |
12224 | if (c) |
12225 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12226 | |
4cf0dd0d TS |
12227 | /* Do we have .section Name<,"flags">? */ |
12228 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12229 | { |
4cf0dd0d TS |
12230 | /* just after name is now '\0'. */ |
12231 | *input_line_pointer = c; | |
cca86cc8 SC |
12232 | input_line_pointer = section_name; |
12233 | obj_elf_section (ignore); | |
12234 | return; | |
12235 | } | |
12236 | input_line_pointer++; | |
12237 | ||
12238 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12239 | if (c == ',') | |
12240 | section_type = get_absolute_expression (); | |
12241 | else | |
12242 | section_type = 0; | |
12243 | if (*input_line_pointer++ == ',') | |
12244 | section_flag = get_absolute_expression (); | |
12245 | else | |
12246 | section_flag = 0; | |
12247 | if (*input_line_pointer++ == ',') | |
12248 | section_entry_size = get_absolute_expression (); | |
12249 | else | |
12250 | section_entry_size = 0; | |
12251 | if (*input_line_pointer++ == ',') | |
12252 | section_alignment = get_absolute_expression (); | |
12253 | else | |
12254 | section_alignment = 0; | |
12255 | ||
a816d1ed AO |
12256 | section_name = xstrdup (section_name); |
12257 | ||
8ab8a5c8 RS |
12258 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12259 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12260 | traditionally had to fall back on the more common @progbits instead. | |
12261 | ||
12262 | There's nothing really harmful in this, since bfd will correct | |
12263 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12264 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12265 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12266 | ||
12267 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12268 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12269 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12270 | generic type-checking code. */ | |
12271 | if (section_type == SHT_MIPS_DWARF) | |
12272 | section_type = SHT_PROGBITS; | |
12273 | ||
cca86cc8 SC |
12274 | obj_elf_change_section (section_name, section_type, section_flag, |
12275 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12276 | |
12277 | if (now_seg->name != section_name) | |
12278 | free (section_name); | |
7ed4a06a | 12279 | #endif /* OBJ_ELF */ |
cca86cc8 | 12280 | } |
252b5132 RH |
12281 | |
12282 | void | |
17a2f251 | 12283 | mips_enable_auto_align (void) |
252b5132 RH |
12284 | { |
12285 | auto_align = 1; | |
12286 | } | |
12287 | ||
12288 | static void | |
17a2f251 | 12289 | s_cons (int log_size) |
252b5132 | 12290 | { |
a8dbcb85 TS |
12291 | segment_info_type *si = seg_info (now_seg); |
12292 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12293 | symbolS *label; |
12294 | ||
a8dbcb85 | 12295 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12296 | mips_emit_delays (); |
252b5132 RH |
12297 | if (log_size > 0 && auto_align) |
12298 | mips_align (log_size, 0, label); | |
12299 | mips_clear_insn_labels (); | |
12300 | cons (1 << log_size); | |
12301 | } | |
12302 | ||
12303 | static void | |
17a2f251 | 12304 | s_float_cons (int type) |
252b5132 | 12305 | { |
a8dbcb85 TS |
12306 | segment_info_type *si = seg_info (now_seg); |
12307 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12308 | symbolS *label; |
12309 | ||
a8dbcb85 | 12310 | label = l != NULL ? l->label : NULL; |
252b5132 | 12311 | |
7d10b47d | 12312 | mips_emit_delays (); |
252b5132 RH |
12313 | |
12314 | if (auto_align) | |
49309057 ILT |
12315 | { |
12316 | if (type == 'd') | |
12317 | mips_align (3, 0, label); | |
12318 | else | |
12319 | mips_align (2, 0, label); | |
12320 | } | |
252b5132 RH |
12321 | |
12322 | mips_clear_insn_labels (); | |
12323 | ||
12324 | float_cons (type); | |
12325 | } | |
12326 | ||
12327 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12328 | permitted to say | |
12329 | .globl foo .text | |
12330 | where foo is an undefined symbol, to mean that foo should be | |
12331 | considered to be the address of a function. */ | |
12332 | ||
12333 | static void | |
17a2f251 | 12334 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12335 | { |
12336 | char *name; | |
12337 | int c; | |
12338 | symbolS *symbolP; | |
12339 | flagword flag; | |
12340 | ||
8a06b769 | 12341 | do |
252b5132 | 12342 | { |
8a06b769 | 12343 | name = input_line_pointer; |
252b5132 | 12344 | c = get_symbol_end (); |
8a06b769 TS |
12345 | symbolP = symbol_find_or_make (name); |
12346 | S_SET_EXTERNAL (symbolP); | |
12347 | ||
252b5132 | 12348 | *input_line_pointer = c; |
8a06b769 | 12349 | SKIP_WHITESPACE (); |
252b5132 | 12350 | |
8a06b769 TS |
12351 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12352 | being a function is apparently labelled as being an object. */ | |
12353 | flag = BSF_OBJECT; | |
252b5132 | 12354 | |
8a06b769 TS |
12355 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12356 | && (*input_line_pointer != ',')) | |
12357 | { | |
12358 | char *secname; | |
12359 | asection *sec; | |
12360 | ||
12361 | secname = input_line_pointer; | |
12362 | c = get_symbol_end (); | |
12363 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12364 | if (sec == NULL) | |
12365 | as_bad (_("%s: no such section"), secname); | |
12366 | *input_line_pointer = c; | |
12367 | ||
12368 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12369 | flag = BSF_FUNCTION; | |
12370 | } | |
12371 | ||
12372 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12373 | ||
12374 | c = *input_line_pointer; | |
12375 | if (c == ',') | |
12376 | { | |
12377 | input_line_pointer++; | |
12378 | SKIP_WHITESPACE (); | |
12379 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12380 | c = '\n'; | |
12381 | } | |
12382 | } | |
12383 | while (c == ','); | |
252b5132 | 12384 | |
252b5132 RH |
12385 | demand_empty_rest_of_line (); |
12386 | } | |
12387 | ||
12388 | static void | |
17a2f251 | 12389 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12390 | { |
12391 | char *opt; | |
12392 | char c; | |
12393 | ||
12394 | opt = input_line_pointer; | |
12395 | c = get_symbol_end (); | |
12396 | ||
12397 | if (*opt == 'O') | |
12398 | { | |
12399 | /* FIXME: What does this mean? */ | |
12400 | } | |
12401 | else if (strncmp (opt, "pic", 3) == 0) | |
12402 | { | |
12403 | int i; | |
12404 | ||
12405 | i = atoi (opt + 3); | |
12406 | if (i == 0) | |
12407 | mips_pic = NO_PIC; | |
12408 | else if (i == 2) | |
143d77c5 | 12409 | { |
252b5132 | 12410 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12411 | mips_abicalls = TRUE; |
12412 | } | |
252b5132 RH |
12413 | else |
12414 | as_bad (_(".option pic%d not supported"), i); | |
12415 | ||
4d0d148d | 12416 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12417 | { |
12418 | if (g_switch_seen && g_switch_value != 0) | |
12419 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12420 | g_switch_value = 0; | |
12421 | bfd_set_gp_size (stdoutput, 0); | |
12422 | } | |
12423 | } | |
12424 | else | |
12425 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12426 | ||
12427 | *input_line_pointer = c; | |
12428 | demand_empty_rest_of_line (); | |
12429 | } | |
12430 | ||
12431 | /* This structure is used to hold a stack of .set values. */ | |
12432 | ||
e972090a NC |
12433 | struct mips_option_stack |
12434 | { | |
252b5132 RH |
12435 | struct mips_option_stack *next; |
12436 | struct mips_set_options options; | |
12437 | }; | |
12438 | ||
12439 | static struct mips_option_stack *mips_opts_stack; | |
12440 | ||
12441 | /* Handle the .set pseudo-op. */ | |
12442 | ||
12443 | static void | |
17a2f251 | 12444 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12445 | { |
12446 | char *name = input_line_pointer, ch; | |
12447 | ||
12448 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12449 | ++input_line_pointer; |
252b5132 RH |
12450 | ch = *input_line_pointer; |
12451 | *input_line_pointer = '\0'; | |
12452 | ||
12453 | if (strcmp (name, "reorder") == 0) | |
12454 | { | |
7d10b47d RS |
12455 | if (mips_opts.noreorder) |
12456 | end_noreorder (); | |
252b5132 RH |
12457 | } |
12458 | else if (strcmp (name, "noreorder") == 0) | |
12459 | { | |
7d10b47d RS |
12460 | if (!mips_opts.noreorder) |
12461 | start_noreorder (); | |
252b5132 | 12462 | } |
741fe287 MR |
12463 | else if (strncmp (name, "at=", 3) == 0) |
12464 | { | |
12465 | char *s = name + 3; | |
12466 | ||
12467 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
12468 | as_bad (_("Unrecognized register name `%s'"), s); | |
12469 | } | |
252b5132 RH |
12470 | else if (strcmp (name, "at") == 0) |
12471 | { | |
741fe287 | 12472 | mips_opts.at = ATREG; |
252b5132 RH |
12473 | } |
12474 | else if (strcmp (name, "noat") == 0) | |
12475 | { | |
741fe287 | 12476 | mips_opts.at = ZERO; |
252b5132 RH |
12477 | } |
12478 | else if (strcmp (name, "macro") == 0) | |
12479 | { | |
12480 | mips_opts.warn_about_macros = 0; | |
12481 | } | |
12482 | else if (strcmp (name, "nomacro") == 0) | |
12483 | { | |
12484 | if (mips_opts.noreorder == 0) | |
12485 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12486 | mips_opts.warn_about_macros = 1; | |
12487 | } | |
12488 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12489 | { | |
12490 | mips_opts.nomove = 0; | |
12491 | } | |
12492 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12493 | { | |
12494 | mips_opts.nomove = 1; | |
12495 | } | |
12496 | else if (strcmp (name, "bopt") == 0) | |
12497 | { | |
12498 | mips_opts.nobopt = 0; | |
12499 | } | |
12500 | else if (strcmp (name, "nobopt") == 0) | |
12501 | { | |
12502 | mips_opts.nobopt = 1; | |
12503 | } | |
ad3fea08 TS |
12504 | else if (strcmp (name, "gp=default") == 0) |
12505 | mips_opts.gp32 = file_mips_gp32; | |
12506 | else if (strcmp (name, "gp=32") == 0) | |
12507 | mips_opts.gp32 = 1; | |
12508 | else if (strcmp (name, "gp=64") == 0) | |
12509 | { | |
12510 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12511 | as_warn ("%s isa does not support 64-bit registers", | |
12512 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12513 | mips_opts.gp32 = 0; | |
12514 | } | |
12515 | else if (strcmp (name, "fp=default") == 0) | |
12516 | mips_opts.fp32 = file_mips_fp32; | |
12517 | else if (strcmp (name, "fp=32") == 0) | |
12518 | mips_opts.fp32 = 1; | |
12519 | else if (strcmp (name, "fp=64") == 0) | |
12520 | { | |
12521 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12522 | as_warn ("%s isa does not support 64-bit floating point registers", | |
12523 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12524 | mips_opts.fp32 = 0; | |
12525 | } | |
037b32b9 AN |
12526 | else if (strcmp (name, "softfloat") == 0) |
12527 | mips_opts.soft_float = 1; | |
12528 | else if (strcmp (name, "hardfloat") == 0) | |
12529 | mips_opts.soft_float = 0; | |
12530 | else if (strcmp (name, "singlefloat") == 0) | |
12531 | mips_opts.single_float = 1; | |
12532 | else if (strcmp (name, "doublefloat") == 0) | |
12533 | mips_opts.single_float = 0; | |
252b5132 RH |
12534 | else if (strcmp (name, "mips16") == 0 |
12535 | || strcmp (name, "MIPS-16") == 0) | |
12536 | mips_opts.mips16 = 1; | |
12537 | else if (strcmp (name, "nomips16") == 0 | |
12538 | || strcmp (name, "noMIPS-16") == 0) | |
12539 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12540 | else if (strcmp (name, "smartmips") == 0) |
12541 | { | |
ad3fea08 | 12542 | if (!ISA_SUPPORTS_SMARTMIPS) |
e16bfa71 TS |
12543 | as_warn ("%s ISA does not support SmartMIPS ASE", |
12544 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12545 | mips_opts.ase_smartmips = 1; | |
12546 | } | |
12547 | else if (strcmp (name, "nosmartmips") == 0) | |
12548 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12549 | else if (strcmp (name, "mips3d") == 0) |
12550 | mips_opts.ase_mips3d = 1; | |
12551 | else if (strcmp (name, "nomips3d") == 0) | |
12552 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12553 | else if (strcmp (name, "mdmx") == 0) |
12554 | mips_opts.ase_mdmx = 1; | |
12555 | else if (strcmp (name, "nomdmx") == 0) | |
12556 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12557 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12558 | { |
12559 | if (!ISA_SUPPORTS_DSP_ASE) | |
12560 | as_warn ("%s ISA does not support DSP ASE", | |
12561 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12562 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 12563 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 12564 | } |
74cd071d | 12565 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
12566 | { |
12567 | mips_opts.ase_dsp = 0; | |
12568 | mips_opts.ase_dspr2 = 0; | |
12569 | } | |
12570 | else if (strcmp (name, "dspr2") == 0) | |
12571 | { | |
12572 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
12573 | as_warn ("%s ISA does not support DSP R2 ASE", | |
12574 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12575 | mips_opts.ase_dspr2 = 1; | |
12576 | mips_opts.ase_dsp = 1; | |
12577 | } | |
12578 | else if (strcmp (name, "nodspr2") == 0) | |
12579 | { | |
12580 | mips_opts.ase_dspr2 = 0; | |
12581 | mips_opts.ase_dsp = 0; | |
12582 | } | |
ef2e4d86 | 12583 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
12584 | { |
12585 | if (!ISA_SUPPORTS_MT_ASE) | |
12586 | as_warn ("%s ISA does not support MT ASE", | |
12587 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12588 | mips_opts.ase_mt = 1; | |
12589 | } | |
ef2e4d86 CF |
12590 | else if (strcmp (name, "nomt") == 0) |
12591 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12592 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12593 | { |
af7ee8bf | 12594 | int reset = 0; |
252b5132 | 12595 | |
1a2c1fad CD |
12596 | /* Permit the user to change the ISA and architecture on the fly. |
12597 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12598 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12599 | { |
12600 | reset = 1; | |
12601 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12602 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12603 | } |
12604 | else if (strncmp (name, "arch=", 5) == 0) | |
12605 | { | |
12606 | const struct mips_cpu_info *p; | |
12607 | ||
12608 | p = mips_parse_cpu("internal use", name + 5); | |
12609 | if (!p) | |
12610 | as_bad (_("unknown architecture %s"), name + 5); | |
12611 | else | |
12612 | { | |
12613 | mips_opts.arch = p->cpu; | |
12614 | mips_opts.isa = p->isa; | |
12615 | } | |
12616 | } | |
81a21e38 TS |
12617 | else if (strncmp (name, "mips", 4) == 0) |
12618 | { | |
12619 | const struct mips_cpu_info *p; | |
12620 | ||
12621 | p = mips_parse_cpu("internal use", name); | |
12622 | if (!p) | |
12623 | as_bad (_("unknown ISA level %s"), name + 4); | |
12624 | else | |
12625 | { | |
12626 | mips_opts.arch = p->cpu; | |
12627 | mips_opts.isa = p->isa; | |
12628 | } | |
12629 | } | |
af7ee8bf | 12630 | else |
81a21e38 | 12631 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12632 | |
12633 | switch (mips_opts.isa) | |
98d3f06f KH |
12634 | { |
12635 | case 0: | |
98d3f06f | 12636 | break; |
af7ee8bf CD |
12637 | case ISA_MIPS1: |
12638 | case ISA_MIPS2: | |
12639 | case ISA_MIPS32: | |
12640 | case ISA_MIPS32R2: | |
98d3f06f KH |
12641 | mips_opts.gp32 = 1; |
12642 | mips_opts.fp32 = 1; | |
12643 | break; | |
af7ee8bf CD |
12644 | case ISA_MIPS3: |
12645 | case ISA_MIPS4: | |
12646 | case ISA_MIPS5: | |
12647 | case ISA_MIPS64: | |
5f74bc13 | 12648 | case ISA_MIPS64R2: |
98d3f06f KH |
12649 | mips_opts.gp32 = 0; |
12650 | mips_opts.fp32 = 0; | |
12651 | break; | |
12652 | default: | |
12653 | as_bad (_("unknown ISA level %s"), name + 4); | |
12654 | break; | |
12655 | } | |
af7ee8bf | 12656 | if (reset) |
98d3f06f | 12657 | { |
af7ee8bf CD |
12658 | mips_opts.gp32 = file_mips_gp32; |
12659 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12660 | } |
252b5132 RH |
12661 | } |
12662 | else if (strcmp (name, "autoextend") == 0) | |
12663 | mips_opts.noautoextend = 0; | |
12664 | else if (strcmp (name, "noautoextend") == 0) | |
12665 | mips_opts.noautoextend = 1; | |
12666 | else if (strcmp (name, "push") == 0) | |
12667 | { | |
12668 | struct mips_option_stack *s; | |
12669 | ||
12670 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12671 | s->next = mips_opts_stack; | |
12672 | s->options = mips_opts; | |
12673 | mips_opts_stack = s; | |
12674 | } | |
12675 | else if (strcmp (name, "pop") == 0) | |
12676 | { | |
12677 | struct mips_option_stack *s; | |
12678 | ||
12679 | s = mips_opts_stack; | |
12680 | if (s == NULL) | |
12681 | as_bad (_(".set pop with no .set push")); | |
12682 | else | |
12683 | { | |
12684 | /* If we're changing the reorder mode we need to handle | |
12685 | delay slots correctly. */ | |
12686 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12687 | start_noreorder (); |
252b5132 | 12688 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12689 | end_noreorder (); |
252b5132 RH |
12690 | |
12691 | mips_opts = s->options; | |
12692 | mips_opts_stack = s->next; | |
12693 | free (s); | |
12694 | } | |
12695 | } | |
aed1a261 RS |
12696 | else if (strcmp (name, "sym32") == 0) |
12697 | mips_opts.sym32 = TRUE; | |
12698 | else if (strcmp (name, "nosym32") == 0) | |
12699 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
12700 | else if (strchr (name, ',')) |
12701 | { | |
12702 | /* Generic ".set" directive; use the generic handler. */ | |
12703 | *input_line_pointer = ch; | |
12704 | input_line_pointer = name; | |
12705 | s_set (0); | |
12706 | return; | |
12707 | } | |
252b5132 RH |
12708 | else |
12709 | { | |
12710 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12711 | } | |
12712 | *input_line_pointer = ch; | |
12713 | demand_empty_rest_of_line (); | |
12714 | } | |
12715 | ||
12716 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12717 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12718 | ||
12719 | static void | |
17a2f251 | 12720 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12721 | { |
12722 | mips_pic = SVR4_PIC; | |
143d77c5 | 12723 | mips_abicalls = TRUE; |
4d0d148d TS |
12724 | |
12725 | if (g_switch_seen && g_switch_value != 0) | |
12726 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12727 | g_switch_value = 0; | |
12728 | ||
252b5132 RH |
12729 | bfd_set_gp_size (stdoutput, 0); |
12730 | demand_empty_rest_of_line (); | |
12731 | } | |
12732 | ||
12733 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12734 | PIC code. It sets the $gp register for the function based on the | |
12735 | function address, which is in the register named in the argument. | |
12736 | This uses a relocation against _gp_disp, which is handled specially | |
12737 | by the linker. The result is: | |
12738 | lui $gp,%hi(_gp_disp) | |
12739 | addiu $gp,$gp,%lo(_gp_disp) | |
12740 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12741 | The .cpload argument is normally $25 == $t9. |
12742 | ||
12743 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12744 | lui $gp,%hi(__gnu_local_gp) |
12745 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12746 | and the argument is ignored. This saves an instruction, but the |
12747 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12748 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12749 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12750 | |
12751 | static void | |
17a2f251 | 12752 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12753 | { |
12754 | expressionS ex; | |
aa6975fb ILT |
12755 | int reg; |
12756 | int in_shared; | |
252b5132 | 12757 | |
6478892d TS |
12758 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12759 | .cpload is ignored. */ | |
12760 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12761 | { |
12762 | s_ignore (0); | |
12763 | return; | |
12764 | } | |
12765 | ||
d3ecfc59 | 12766 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12767 | if (mips_opts.noreorder == 0) |
12768 | as_warn (_(".cpload not in noreorder section")); | |
12769 | ||
aa6975fb ILT |
12770 | reg = tc_get_register (0); |
12771 | ||
12772 | /* If we need to produce a 64-bit address, we are better off using | |
12773 | the default instruction sequence. */ | |
aed1a261 | 12774 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12775 | |
252b5132 | 12776 | ex.X_op = O_symbol; |
bbe506e8 TS |
12777 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12778 | "__gnu_local_gp"); | |
252b5132 RH |
12779 | ex.X_op_symbol = NULL; |
12780 | ex.X_add_number = 0; | |
12781 | ||
12782 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12783 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12784 | |
584892a6 | 12785 | macro_start (); |
67c0d1eb RS |
12786 | macro_build_lui (&ex, mips_gp_register); |
12787 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12788 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12789 | if (in_shared) |
12790 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12791 | mips_gp_register, reg); | |
584892a6 | 12792 | macro_end (); |
252b5132 RH |
12793 | |
12794 | demand_empty_rest_of_line (); | |
12795 | } | |
12796 | ||
6478892d TS |
12797 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12798 | .cpsetup $reg1, offset|$reg2, label | |
12799 | ||
12800 | If offset is given, this results in: | |
12801 | sd $gp, offset($sp) | |
956cd1d6 | 12802 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12803 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12804 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12805 | |
12806 | If $reg2 is given, this results in: | |
12807 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12808 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12809 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12810 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12811 | $reg1 is normally $25 == $t9. |
12812 | ||
12813 | The -mno-shared option replaces the last three instructions with | |
12814 | lui $gp,%hi(_gp) | |
54f4ddb3 | 12815 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 12816 | |
6478892d | 12817 | static void |
17a2f251 | 12818 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12819 | { |
12820 | expressionS ex_off; | |
12821 | expressionS ex_sym; | |
12822 | int reg1; | |
6478892d | 12823 | |
8586fc66 | 12824 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12825 | We also need NewABI support. */ |
12826 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12827 | { | |
12828 | s_ignore (0); | |
12829 | return; | |
12830 | } | |
12831 | ||
12832 | reg1 = tc_get_register (0); | |
12833 | SKIP_WHITESPACE (); | |
12834 | if (*input_line_pointer != ',') | |
12835 | { | |
12836 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12837 | return; | |
12838 | } | |
12839 | else | |
80245285 | 12840 | ++input_line_pointer; |
6478892d TS |
12841 | SKIP_WHITESPACE (); |
12842 | if (*input_line_pointer == '$') | |
80245285 TS |
12843 | { |
12844 | mips_cpreturn_register = tc_get_register (0); | |
12845 | mips_cpreturn_offset = -1; | |
12846 | } | |
6478892d | 12847 | else |
80245285 TS |
12848 | { |
12849 | mips_cpreturn_offset = get_absolute_expression (); | |
12850 | mips_cpreturn_register = -1; | |
12851 | } | |
6478892d TS |
12852 | SKIP_WHITESPACE (); |
12853 | if (*input_line_pointer != ',') | |
12854 | { | |
12855 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12856 | return; | |
12857 | } | |
12858 | else | |
f9419b05 | 12859 | ++input_line_pointer; |
6478892d | 12860 | SKIP_WHITESPACE (); |
f21f8242 | 12861 | expression (&ex_sym); |
6478892d | 12862 | |
584892a6 | 12863 | macro_start (); |
6478892d TS |
12864 | if (mips_cpreturn_register == -1) |
12865 | { | |
12866 | ex_off.X_op = O_constant; | |
12867 | ex_off.X_add_symbol = NULL; | |
12868 | ex_off.X_op_symbol = NULL; | |
12869 | ex_off.X_add_number = mips_cpreturn_offset; | |
12870 | ||
67c0d1eb | 12871 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12872 | BFD_RELOC_LO16, SP); |
6478892d TS |
12873 | } |
12874 | else | |
67c0d1eb | 12875 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12876 | mips_gp_register, 0); |
6478892d | 12877 | |
aed1a261 | 12878 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12879 | { |
12880 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12881 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12882 | BFD_RELOC_HI16_S); | |
12883 | ||
12884 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12885 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12886 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12887 | ||
12888 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12889 | mips_gp_register, reg1); | |
12890 | } | |
12891 | else | |
12892 | { | |
12893 | expressionS ex; | |
12894 | ||
12895 | ex.X_op = O_symbol; | |
4184909a | 12896 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12897 | ex.X_op_symbol = NULL; |
12898 | ex.X_add_number = 0; | |
6e1304d8 | 12899 | |
aa6975fb ILT |
12900 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12901 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12902 | ||
12903 | macro_build_lui (&ex, mips_gp_register); | |
12904 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12905 | mips_gp_register, BFD_RELOC_LO16); | |
12906 | } | |
f21f8242 | 12907 | |
584892a6 | 12908 | macro_end (); |
6478892d TS |
12909 | |
12910 | demand_empty_rest_of_line (); | |
12911 | } | |
12912 | ||
12913 | static void | |
17a2f251 | 12914 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12915 | { |
12916 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 12917 | .cplocal is ignored. */ |
6478892d TS |
12918 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
12919 | { | |
12920 | s_ignore (0); | |
12921 | return; | |
12922 | } | |
12923 | ||
12924 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12925 | demand_empty_rest_of_line (); |
6478892d TS |
12926 | } |
12927 | ||
252b5132 RH |
12928 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12929 | offset from $sp. The offset is remembered, and after making a PIC | |
12930 | call $gp is restored from that location. */ | |
12931 | ||
12932 | static void | |
17a2f251 | 12933 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12934 | { |
12935 | expressionS ex; | |
252b5132 | 12936 | |
6478892d | 12937 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12938 | .cprestore is ignored. */ |
6478892d | 12939 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12940 | { |
12941 | s_ignore (0); | |
12942 | return; | |
12943 | } | |
12944 | ||
12945 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12946 | mips_cprestore_valid = 1; |
252b5132 RH |
12947 | |
12948 | ex.X_op = O_constant; | |
12949 | ex.X_add_symbol = NULL; | |
12950 | ex.X_op_symbol = NULL; | |
12951 | ex.X_add_number = mips_cprestore_offset; | |
12952 | ||
584892a6 | 12953 | macro_start (); |
67c0d1eb RS |
12954 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12955 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12956 | macro_end (); |
252b5132 RH |
12957 | |
12958 | demand_empty_rest_of_line (); | |
12959 | } | |
12960 | ||
6478892d | 12961 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12962 | was given in the preceding .cpsetup, it results in: |
6478892d | 12963 | ld $gp, offset($sp) |
76b3015f | 12964 | |
6478892d | 12965 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
12966 | daddu $gp, $reg2, $0 */ |
12967 | ||
6478892d | 12968 | static void |
17a2f251 | 12969 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12970 | { |
12971 | expressionS ex; | |
6478892d TS |
12972 | |
12973 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12974 | We also need NewABI support. */ | |
12975 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12976 | { | |
12977 | s_ignore (0); | |
12978 | return; | |
12979 | } | |
12980 | ||
584892a6 | 12981 | macro_start (); |
6478892d TS |
12982 | if (mips_cpreturn_register == -1) |
12983 | { | |
12984 | ex.X_op = O_constant; | |
12985 | ex.X_add_symbol = NULL; | |
12986 | ex.X_op_symbol = NULL; | |
12987 | ex.X_add_number = mips_cpreturn_offset; | |
12988 | ||
67c0d1eb | 12989 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12990 | } |
12991 | else | |
67c0d1eb | 12992 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12993 | mips_cpreturn_register, 0); |
584892a6 | 12994 | macro_end (); |
6478892d TS |
12995 | |
12996 | demand_empty_rest_of_line (); | |
12997 | } | |
12998 | ||
741d6ea8 JM |
12999 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13000 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13001 | use in DWARF debug information. */ | |
13002 | ||
13003 | static void | |
13004 | s_dtprel_internal (size_t bytes) | |
13005 | { | |
13006 | expressionS ex; | |
13007 | char *p; | |
13008 | ||
13009 | expression (&ex); | |
13010 | ||
13011 | if (ex.X_op != O_symbol) | |
13012 | { | |
13013 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13014 | ? ".dtpreldword" | |
13015 | : ".dtprelword")); | |
13016 | ignore_rest_of_line (); | |
13017 | } | |
13018 | ||
13019 | p = frag_more (bytes); | |
13020 | md_number_to_chars (p, 0, bytes); | |
13021 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13022 | (bytes == 8 | |
13023 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13024 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13025 | ||
13026 | demand_empty_rest_of_line (); | |
13027 | } | |
13028 | ||
13029 | /* Handle .dtprelword. */ | |
13030 | ||
13031 | static void | |
13032 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13033 | { | |
13034 | s_dtprel_internal (4); | |
13035 | } | |
13036 | ||
13037 | /* Handle .dtpreldword. */ | |
13038 | ||
13039 | static void | |
13040 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13041 | { | |
13042 | s_dtprel_internal (8); | |
13043 | } | |
13044 | ||
6478892d TS |
13045 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13046 | code. It sets the offset to use in gp_rel relocations. */ | |
13047 | ||
13048 | static void | |
17a2f251 | 13049 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13050 | { |
13051 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13052 | We also need NewABI support. */ | |
13053 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13054 | { | |
13055 | s_ignore (0); | |
13056 | return; | |
13057 | } | |
13058 | ||
def2e0dd | 13059 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13060 | |
13061 | demand_empty_rest_of_line (); | |
13062 | } | |
13063 | ||
252b5132 RH |
13064 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13065 | code. It generates a 32 bit GP relative reloc. */ | |
13066 | ||
13067 | static void | |
17a2f251 | 13068 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13069 | { |
a8dbcb85 TS |
13070 | segment_info_type *si; |
13071 | struct insn_label_list *l; | |
252b5132 RH |
13072 | symbolS *label; |
13073 | expressionS ex; | |
13074 | char *p; | |
13075 | ||
13076 | /* When not generating PIC code, this is treated as .word. */ | |
13077 | if (mips_pic != SVR4_PIC) | |
13078 | { | |
13079 | s_cons (2); | |
13080 | return; | |
13081 | } | |
13082 | ||
a8dbcb85 TS |
13083 | si = seg_info (now_seg); |
13084 | l = si->label_list; | |
13085 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13086 | mips_emit_delays (); |
252b5132 RH |
13087 | if (auto_align) |
13088 | mips_align (2, 0, label); | |
13089 | mips_clear_insn_labels (); | |
13090 | ||
13091 | expression (&ex); | |
13092 | ||
13093 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13094 | { | |
13095 | as_bad (_("Unsupported use of .gpword")); | |
13096 | ignore_rest_of_line (); | |
13097 | } | |
13098 | ||
13099 | p = frag_more (4); | |
17a2f251 | 13100 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13101 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13102 | BFD_RELOC_GPREL32); |
252b5132 RH |
13103 | |
13104 | demand_empty_rest_of_line (); | |
13105 | } | |
13106 | ||
10181a0d | 13107 | static void |
17a2f251 | 13108 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13109 | { |
a8dbcb85 TS |
13110 | segment_info_type *si; |
13111 | struct insn_label_list *l; | |
10181a0d AO |
13112 | symbolS *label; |
13113 | expressionS ex; | |
13114 | char *p; | |
13115 | ||
13116 | /* When not generating PIC code, this is treated as .dword. */ | |
13117 | if (mips_pic != SVR4_PIC) | |
13118 | { | |
13119 | s_cons (3); | |
13120 | return; | |
13121 | } | |
13122 | ||
a8dbcb85 TS |
13123 | si = seg_info (now_seg); |
13124 | l = si->label_list; | |
13125 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13126 | mips_emit_delays (); |
10181a0d AO |
13127 | if (auto_align) |
13128 | mips_align (3, 0, label); | |
13129 | mips_clear_insn_labels (); | |
13130 | ||
13131 | expression (&ex); | |
13132 | ||
13133 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13134 | { | |
13135 | as_bad (_("Unsupported use of .gpdword")); | |
13136 | ignore_rest_of_line (); | |
13137 | } | |
13138 | ||
13139 | p = frag_more (8); | |
17a2f251 | 13140 | md_number_to_chars (p, 0, 8); |
a105a300 | 13141 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13142 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13143 | |
13144 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13145 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13146 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13147 | |
13148 | demand_empty_rest_of_line (); | |
13149 | } | |
13150 | ||
252b5132 RH |
13151 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13152 | tables in SVR4 PIC code. */ | |
13153 | ||
13154 | static void | |
17a2f251 | 13155 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13156 | { |
252b5132 RH |
13157 | int reg; |
13158 | ||
10181a0d AO |
13159 | /* This is ignored when not generating SVR4 PIC code. */ |
13160 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13161 | { |
13162 | s_ignore (0); | |
13163 | return; | |
13164 | } | |
13165 | ||
13166 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13167 | macro_start (); |
252b5132 | 13168 | reg = tc_get_register (0); |
67c0d1eb | 13169 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13170 | macro_end (); |
252b5132 | 13171 | |
bdaaa2e1 | 13172 | demand_empty_rest_of_line (); |
252b5132 RH |
13173 | } |
13174 | ||
13175 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13176 | mips16 mode. This permits the linker to handle them specially, | |
13177 | such as generating jalx instructions when needed. We also make | |
13178 | them odd for the duration of the assembly, in order to generate the | |
13179 | right sort of code. We will make them even in the adjust_symtab | |
13180 | routine, while leaving them marked. This is convenient for the | |
13181 | debugger and the disassembler. The linker knows to make them odd | |
13182 | again. */ | |
13183 | ||
13184 | static void | |
17a2f251 | 13185 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13186 | { |
f9419b05 | 13187 | mips16_mark_labels (); |
252b5132 RH |
13188 | |
13189 | demand_empty_rest_of_line (); | |
13190 | } | |
13191 | ||
13192 | /* Handle a .stabn directive. We need these in order to mark a label | |
13193 | as being a mips16 text label correctly. Sometimes the compiler | |
13194 | will emit a label, followed by a .stabn, and then switch sections. | |
13195 | If the label and .stabn are in mips16 mode, then the label is | |
13196 | really a mips16 text label. */ | |
13197 | ||
13198 | static void | |
17a2f251 | 13199 | s_mips_stab (int type) |
252b5132 | 13200 | { |
f9419b05 | 13201 | if (type == 'n') |
252b5132 RH |
13202 | mips16_mark_labels (); |
13203 | ||
13204 | s_stab (type); | |
13205 | } | |
13206 | ||
54f4ddb3 | 13207 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13208 | |
13209 | static void | |
17a2f251 | 13210 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13211 | { |
13212 | char *name; | |
13213 | int c; | |
13214 | symbolS *symbolP; | |
13215 | expressionS exp; | |
13216 | ||
13217 | name = input_line_pointer; | |
13218 | c = get_symbol_end (); | |
13219 | symbolP = symbol_find_or_make (name); | |
13220 | S_SET_WEAK (symbolP); | |
13221 | *input_line_pointer = c; | |
13222 | ||
13223 | SKIP_WHITESPACE (); | |
13224 | ||
13225 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13226 | { | |
13227 | if (S_IS_DEFINED (symbolP)) | |
13228 | { | |
956cd1d6 | 13229 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
13230 | S_GET_NAME (symbolP)); |
13231 | ignore_rest_of_line (); | |
13232 | return; | |
13233 | } | |
bdaaa2e1 | 13234 | |
252b5132 RH |
13235 | if (*input_line_pointer == ',') |
13236 | { | |
13237 | ++input_line_pointer; | |
13238 | SKIP_WHITESPACE (); | |
13239 | } | |
bdaaa2e1 | 13240 | |
252b5132 RH |
13241 | expression (&exp); |
13242 | if (exp.X_op != O_symbol) | |
13243 | { | |
13244 | as_bad ("bad .weakext directive"); | |
98d3f06f | 13245 | ignore_rest_of_line (); |
252b5132 RH |
13246 | return; |
13247 | } | |
49309057 | 13248 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13249 | } |
13250 | ||
13251 | demand_empty_rest_of_line (); | |
13252 | } | |
13253 | ||
13254 | /* Parse a register string into a number. Called from the ECOFF code | |
13255 | to parse .frame. The argument is non-zero if this is the frame | |
13256 | register, so that we can record it in mips_frame_reg. */ | |
13257 | ||
13258 | int | |
17a2f251 | 13259 | tc_get_register (int frame) |
252b5132 | 13260 | { |
707bfff6 | 13261 | unsigned int reg; |
252b5132 RH |
13262 | |
13263 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13264 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13265 | reg = 0; | |
252b5132 | 13266 | if (frame) |
7a621144 DJ |
13267 | { |
13268 | mips_frame_reg = reg != 0 ? reg : SP; | |
13269 | mips_frame_reg_valid = 1; | |
13270 | mips_cprestore_valid = 0; | |
13271 | } | |
252b5132 RH |
13272 | return reg; |
13273 | } | |
13274 | ||
13275 | valueT | |
17a2f251 | 13276 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13277 | { |
13278 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13279 | ||
b4c71f56 TS |
13280 | if (IS_ELF) |
13281 | { | |
13282 | /* We don't need to align ELF sections to the full alignment. | |
13283 | However, Irix 5 may prefer that we align them at least to a 16 | |
13284 | byte boundary. We don't bother to align the sections if we | |
13285 | are targeted for an embedded system. */ | |
c41e87e3 | 13286 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13287 | return addr; |
13288 | if (align > 4) | |
13289 | align = 4; | |
13290 | } | |
252b5132 RH |
13291 | |
13292 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13293 | } | |
13294 | ||
13295 | /* Utility routine, called from above as well. If called while the | |
13296 | input file is still being read, it's only an approximation. (For | |
13297 | example, a symbol may later become defined which appeared to be | |
13298 | undefined earlier.) */ | |
13299 | ||
13300 | static int | |
17a2f251 | 13301 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13302 | { |
13303 | if (sym == 0) | |
13304 | return 0; | |
13305 | ||
4d0d148d | 13306 | if (g_switch_value > 0) |
252b5132 RH |
13307 | { |
13308 | const char *symname; | |
13309 | int change; | |
13310 | ||
c9914766 | 13311 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13312 | register. It can be if it is smaller than the -G size or if |
13313 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13314 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13315 | they can. */ |
13316 | symname = S_GET_NAME (sym); | |
13317 | if (symname != (const char *) NULL | |
13318 | && (strcmp (symname, "eprol") == 0 | |
13319 | || strcmp (symname, "etext") == 0 | |
13320 | || strcmp (symname, "_gp") == 0 | |
13321 | || strcmp (symname, "edata") == 0 | |
13322 | || strcmp (symname, "_fbss") == 0 | |
13323 | || strcmp (symname, "_fdata") == 0 | |
13324 | || strcmp (symname, "_ftext") == 0 | |
13325 | || strcmp (symname, "end") == 0 | |
13326 | || strcmp (symname, "_gp_disp") == 0)) | |
13327 | change = 1; | |
13328 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13329 | && (0 | |
13330 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13331 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13332 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13333 | <= g_switch_value)) | |
252b5132 RH |
13334 | #endif |
13335 | /* We must defer this decision until after the whole | |
13336 | file has been read, since there might be a .extern | |
13337 | after the first use of this symbol. */ | |
13338 | || (before_relaxing | |
13339 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13340 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13341 | #endif |
13342 | && S_GET_VALUE (sym) == 0) | |
13343 | || (S_GET_VALUE (sym) != 0 | |
13344 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13345 | change = 0; | |
13346 | else | |
13347 | { | |
13348 | const char *segname; | |
13349 | ||
13350 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13351 | assert (strcmp (segname, ".lit8") != 0 | |
13352 | && strcmp (segname, ".lit4") != 0); | |
13353 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13354 | && strcmp (segname, ".sbss") != 0 |
13355 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13356 | && strncmp (segname, ".sbss.", 6) != 0 |
13357 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13358 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13359 | } |
13360 | return change; | |
13361 | } | |
13362 | else | |
c9914766 | 13363 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13364 | return 1; |
13365 | } | |
13366 | ||
5919d012 RS |
13367 | |
13368 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13369 | ||
13370 | static bfd_boolean | |
17a2f251 | 13371 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13372 | { |
13373 | asection *symsec; | |
5919d012 RS |
13374 | |
13375 | /* Handle the case of a symbol equated to another symbol. */ | |
13376 | while (symbol_equated_reloc_p (sym)) | |
13377 | { | |
13378 | symbolS *n; | |
13379 | ||
5f0fe04b | 13380 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13381 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13382 | if (n == sym) | |
13383 | break; | |
13384 | sym = n; | |
13385 | } | |
13386 | ||
df1f3cda DD |
13387 | if (symbol_section_p (sym)) |
13388 | return TRUE; | |
13389 | ||
5919d012 RS |
13390 | symsec = S_GET_SEGMENT (sym); |
13391 | ||
5919d012 RS |
13392 | /* This must duplicate the test in adjust_reloc_syms. */ |
13393 | return (symsec != &bfd_und_section | |
13394 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13395 | && !bfd_is_com_section (symsec) |
13396 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13397 | #ifdef OBJ_ELF |
13398 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13399 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13400 | #endif |
13401 | ); | |
13402 | } | |
13403 | ||
13404 | ||
252b5132 RH |
13405 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13406 | extended opcode. SEC is the section the frag is in. */ | |
13407 | ||
13408 | static int | |
17a2f251 | 13409 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13410 | { |
13411 | int type; | |
3994f87e | 13412 | const struct mips16_immed_operand *op; |
252b5132 RH |
13413 | offsetT val; |
13414 | int mintiny, maxtiny; | |
13415 | segT symsec; | |
98aa84af | 13416 | fragS *sym_frag; |
252b5132 RH |
13417 | |
13418 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13419 | return 0; | |
13420 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13421 | return 1; | |
13422 | ||
13423 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13424 | op = mips16_immed_operands; | |
13425 | while (op->type != type) | |
13426 | { | |
13427 | ++op; | |
13428 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13429 | } | |
13430 | ||
13431 | if (op->unsp) | |
13432 | { | |
13433 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13434 | { | |
13435 | mintiny = 1; | |
13436 | maxtiny = 1 << op->nbits; | |
13437 | } | |
13438 | else | |
13439 | { | |
13440 | mintiny = 0; | |
13441 | maxtiny = (1 << op->nbits) - 1; | |
13442 | } | |
13443 | } | |
13444 | else | |
13445 | { | |
13446 | mintiny = - (1 << (op->nbits - 1)); | |
13447 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13448 | } | |
13449 | ||
98aa84af | 13450 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13451 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13452 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13453 | |
13454 | if (op->pcrel) | |
13455 | { | |
13456 | addressT addr; | |
13457 | ||
13458 | /* We won't have the section when we are called from | |
13459 | mips_relax_frag. However, we will always have been called | |
13460 | from md_estimate_size_before_relax first. If this is a | |
13461 | branch to a different section, we mark it as such. If SEC is | |
13462 | NULL, and the frag is not marked, then it must be a branch to | |
13463 | the same section. */ | |
13464 | if (sec == NULL) | |
13465 | { | |
13466 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13467 | return 1; | |
13468 | } | |
13469 | else | |
13470 | { | |
98aa84af | 13471 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13472 | if (symsec != sec) |
13473 | { | |
13474 | fragp->fr_subtype = | |
13475 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13476 | ||
13477 | /* FIXME: We should support this, and let the linker | |
13478 | catch branches and loads that are out of range. */ | |
13479 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13480 | _("unsupported PC relative reference to different section")); | |
13481 | ||
13482 | return 1; | |
13483 | } | |
98aa84af AM |
13484 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13485 | /* Assume non-extended on the first relaxation pass. | |
13486 | The address we have calculated will be bogus if this is | |
13487 | a forward branch to another frag, as the forward frag | |
13488 | will have fr_address == 0. */ | |
13489 | return 0; | |
252b5132 RH |
13490 | } |
13491 | ||
13492 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13493 | the same section. If the relax_marker of the symbol fragment |
13494 | differs from the relax_marker of this fragment, we have not | |
13495 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13496 | in STRETCH in order to get a better estimate of the address. |
13497 | This particularly matters because of the shift bits. */ | |
13498 | if (stretch != 0 | |
98aa84af | 13499 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13500 | { |
13501 | fragS *f; | |
13502 | ||
13503 | /* Adjust stretch for any alignment frag. Note that if have | |
13504 | been expanding the earlier code, the symbol may be | |
13505 | defined in what appears to be an earlier frag. FIXME: | |
13506 | This doesn't handle the fr_subtype field, which specifies | |
13507 | a maximum number of bytes to skip when doing an | |
13508 | alignment. */ | |
98aa84af | 13509 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13510 | { |
13511 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13512 | { | |
13513 | if (stretch < 0) | |
13514 | stretch = - ((- stretch) | |
13515 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13516 | else | |
13517 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13518 | if (stretch == 0) | |
13519 | break; | |
13520 | } | |
13521 | } | |
13522 | if (f != NULL) | |
13523 | val += stretch; | |
13524 | } | |
13525 | ||
13526 | addr = fragp->fr_address + fragp->fr_fix; | |
13527 | ||
13528 | /* The base address rules are complicated. The base address of | |
13529 | a branch is the following instruction. The base address of a | |
13530 | PC relative load or add is the instruction itself, but if it | |
13531 | is in a delay slot (in which case it can not be extended) use | |
13532 | the address of the instruction whose delay slot it is in. */ | |
13533 | if (type == 'p' || type == 'q') | |
13534 | { | |
13535 | addr += 2; | |
13536 | ||
13537 | /* If we are currently assuming that this frag should be | |
13538 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13539 | higher. */ |
252b5132 RH |
13540 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13541 | addr += 2; | |
13542 | ||
13543 | /* Ignore the low bit in the target, since it will be set | |
13544 | for a text label. */ | |
13545 | if ((val & 1) != 0) | |
13546 | --val; | |
13547 | } | |
13548 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13549 | addr -= 4; | |
13550 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13551 | addr -= 2; | |
13552 | ||
13553 | val -= addr & ~ ((1 << op->shift) - 1); | |
13554 | ||
13555 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13556 | if (type == 'p' || type == 'q') | |
13557 | val /= 2; | |
13558 | ||
13559 | /* If any of the shifted bits are set, we must use an extended | |
13560 | opcode. If the address depends on the size of this | |
13561 | instruction, this can lead to a loop, so we arrange to always | |
13562 | use an extended opcode. We only check this when we are in | |
13563 | the main relaxation loop, when SEC is NULL. */ | |
13564 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13565 | { | |
13566 | fragp->fr_subtype = | |
13567 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13568 | return 1; | |
13569 | } | |
13570 | ||
13571 | /* If we are about to mark a frag as extended because the value | |
13572 | is precisely maxtiny + 1, then there is a chance of an | |
13573 | infinite loop as in the following code: | |
13574 | la $4,foo | |
13575 | .skip 1020 | |
13576 | .align 2 | |
13577 | foo: | |
13578 | In this case when the la is extended, foo is 0x3fc bytes | |
13579 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13580 | the la must be extended. To avoid this loop, we mark the | |
13581 | frag as extended if it was small, and is about to become | |
13582 | extended with a value of maxtiny + 1. */ | |
13583 | if (val == ((maxtiny + 1) << op->shift) | |
13584 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13585 | && sec == NULL) | |
13586 | { | |
13587 | fragp->fr_subtype = | |
13588 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13589 | return 1; | |
13590 | } | |
13591 | } | |
13592 | else if (symsec != absolute_section && sec != NULL) | |
13593 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13594 | ||
13595 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13596 | || val < (mintiny << op->shift) | |
13597 | || val > (maxtiny << op->shift)) | |
13598 | return 1; | |
13599 | else | |
13600 | return 0; | |
13601 | } | |
13602 | ||
4a6a3df4 AO |
13603 | /* Compute the length of a branch sequence, and adjust the |
13604 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13605 | worst-case length is computed, with UPDATE being used to indicate | |
13606 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13607 | branch is to be computed. */ | |
13608 | static int | |
17a2f251 | 13609 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13610 | { |
b34976b6 | 13611 | bfd_boolean toofar; |
4a6a3df4 AO |
13612 | int length; |
13613 | ||
13614 | if (fragp | |
13615 | && S_IS_DEFINED (fragp->fr_symbol) | |
13616 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13617 | { | |
13618 | addressT addr; | |
13619 | offsetT val; | |
13620 | ||
13621 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13622 | ||
13623 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13624 | ||
13625 | val -= addr; | |
13626 | ||
13627 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13628 | } | |
13629 | else if (fragp) | |
13630 | /* If the symbol is not defined or it's in a different segment, | |
13631 | assume the user knows what's going on and emit a short | |
13632 | branch. */ | |
b34976b6 | 13633 | toofar = FALSE; |
4a6a3df4 | 13634 | else |
b34976b6 | 13635 | toofar = TRUE; |
4a6a3df4 AO |
13636 | |
13637 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13638 | fragp->fr_subtype | |
af6ae2ad | 13639 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13640 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13641 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13642 | toofar); | |
13643 | ||
13644 | length = 4; | |
13645 | if (toofar) | |
13646 | { | |
13647 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13648 | length += 8; | |
13649 | ||
13650 | if (mips_pic != NO_PIC) | |
13651 | { | |
13652 | /* Additional space for PIC loading of target address. */ | |
13653 | length += 8; | |
13654 | if (mips_opts.isa == ISA_MIPS1) | |
13655 | /* Additional space for $at-stabilizing nop. */ | |
13656 | length += 4; | |
13657 | } | |
13658 | ||
13659 | /* If branch is conditional. */ | |
13660 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13661 | length += 8; | |
13662 | } | |
b34976b6 | 13663 | |
4a6a3df4 AO |
13664 | return length; |
13665 | } | |
13666 | ||
252b5132 RH |
13667 | /* Estimate the size of a frag before relaxing. Unless this is the |
13668 | mips16, we are not really relaxing here, and the final size is | |
13669 | encoded in the subtype information. For the mips16, we have to | |
13670 | decide whether we are using an extended opcode or not. */ | |
13671 | ||
252b5132 | 13672 | int |
17a2f251 | 13673 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13674 | { |
5919d012 | 13675 | int change; |
252b5132 | 13676 | |
4a6a3df4 AO |
13677 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13678 | { | |
13679 | ||
b34976b6 AM |
13680 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13681 | ||
4a6a3df4 AO |
13682 | return fragp->fr_var; |
13683 | } | |
13684 | ||
252b5132 | 13685 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13686 | /* We don't want to modify the EXTENDED bit here; it might get us |
13687 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13688 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13689 | |
13690 | if (mips_pic == NO_PIC) | |
5919d012 | 13691 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13692 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13693 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13694 | else if (mips_pic == VXWORKS_PIC) |
13695 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13696 | change = 0; | |
252b5132 RH |
13697 | else |
13698 | abort (); | |
13699 | ||
13700 | if (change) | |
13701 | { | |
4d7206a2 | 13702 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13703 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13704 | } |
4d7206a2 RS |
13705 | else |
13706 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13707 | } |
13708 | ||
13709 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13710 | should be converted into a reloc against a section. */ |
252b5132 RH |
13711 | |
13712 | int | |
17a2f251 | 13713 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13714 | { |
252b5132 RH |
13715 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13716 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13717 | return 0; | |
a161fe53 | 13718 | |
252b5132 RH |
13719 | if (fixp->fx_addsy == NULL) |
13720 | return 1; | |
a161fe53 | 13721 | |
de7e6852 RS |
13722 | /* If symbol SYM is in a mergeable section, relocations of the form |
13723 | SYM + 0 can usually be made section-relative. The mergeable data | |
13724 | is then identified by the section offset rather than by the symbol. | |
13725 | ||
13726 | However, if we're generating REL LO16 relocations, the offset is split | |
13727 | between the LO16 and parterning high part relocation. The linker will | |
13728 | need to recalculate the complete offset in order to correctly identify | |
13729 | the merge data. | |
13730 | ||
13731 | The linker has traditionally not looked for the parterning high part | |
13732 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13733 | placed anywhere. Rather than break backwards compatibility by changing | |
13734 | this, it seems better not to force the issue, and instead keep the | |
13735 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13736 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13737 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13738 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13739 | && HAVE_IN_PLACE_ADDENDS |
13740 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13741 | return 0; | |
13742 | ||
252b5132 | 13743 | #ifdef OBJ_ELF |
b314ec0e RS |
13744 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
13745 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
13746 | relocations against MIPS16 functions; in this case, the stub becomes | |
13747 | the function's canonical address. | |
13748 | ||
13749 | Floating-point stubs are stored in unique .mips16.call.* or | |
13750 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
13751 | the first relocation in section S must be against F; this is how the | |
13752 | linker determines the target function. All relocations that might | |
13753 | resolve to T must also be against F. We therefore have the following | |
13754 | restrictions, which are given in an intentionally-redundant way: | |
13755 | ||
13756 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
13757 | symbols. | |
13758 | ||
13759 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
13760 | if that stub might be used. | |
13761 | ||
13762 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
13763 | symbols. | |
13764 | ||
13765 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
13766 | that stub might be used. | |
13767 | ||
13768 | There is a further restriction: | |
13769 | ||
13770 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
13771 | on targets with in-place addends; the relocation field cannot | |
13772 | encode the low bit. | |
13773 | ||
13774 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
13775 | against a MIPS16 symbol. | |
13776 | ||
13777 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
13778 | relocation against some symbol R, no relocation against R may be | |
13779 | reduced. (Note that this deals with (2) as well as (1) because | |
13780 | relocations against global symbols will never be reduced on ELF | |
13781 | targets.) This approach is a little simpler than trying to detect | |
13782 | stub sections, and gives the "all or nothing" per-symbol consistency | |
13783 | that we have for MIPS16 symbols. */ | |
f43abd2b | 13784 | if (IS_ELF |
b314ec0e RS |
13785 | && fixp->fx_subsy == NULL |
13786 | && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13787 | || *symbol_get_tc (fixp->fx_addsy))) | |
252b5132 RH |
13788 | return 0; |
13789 | #endif | |
a161fe53 | 13790 | |
252b5132 RH |
13791 | return 1; |
13792 | } | |
13793 | ||
13794 | /* Translate internal representation of relocation info to BFD target | |
13795 | format. */ | |
13796 | ||
13797 | arelent ** | |
17a2f251 | 13798 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13799 | { |
13800 | static arelent *retval[4]; | |
13801 | arelent *reloc; | |
13802 | bfd_reloc_code_real_type code; | |
13803 | ||
4b0cff4e TS |
13804 | memset (retval, 0, sizeof(retval)); |
13805 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13806 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13807 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13808 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13809 | ||
bad36eac DJ |
13810 | if (fixp->fx_pcrel) |
13811 | { | |
13812 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13813 | ||
13814 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13815 | Relocations want only the symbol offset. */ | |
13816 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 13817 | if (!IS_ELF) |
bad36eac DJ |
13818 | { |
13819 | /* A gruesome hack which is a result of the gruesome gas | |
13820 | reloc handling. What's worse, for COFF (as opposed to | |
13821 | ECOFF), we might need yet another copy of reloc->address. | |
13822 | See bfd_install_relocation. */ | |
13823 | reloc->addend += reloc->address; | |
13824 | } | |
13825 | } | |
13826 | else | |
13827 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13828 | |
438c16b8 TS |
13829 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13830 | entry to be used in the relocation's section offset. */ | |
13831 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13832 | { |
13833 | reloc->address = reloc->addend; | |
13834 | reloc->addend = 0; | |
13835 | } | |
13836 | ||
252b5132 | 13837 | code = fixp->fx_r_type; |
252b5132 | 13838 | |
bad36eac | 13839 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13840 | if (reloc->howto == NULL) |
13841 | { | |
13842 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13843 | _("Can not represent %s relocation in this object file format"), | |
13844 | bfd_get_reloc_code_name (code)); | |
13845 | retval[0] = NULL; | |
13846 | } | |
13847 | ||
13848 | return retval; | |
13849 | } | |
13850 | ||
13851 | /* Relax a machine dependent frag. This returns the amount by which | |
13852 | the current size of the frag should change. */ | |
13853 | ||
13854 | int | |
17a2f251 | 13855 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13856 | { |
4a6a3df4 AO |
13857 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13858 | { | |
13859 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13860 | |
13861 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13862 | |
13863 | return fragp->fr_var - old_var; | |
13864 | } | |
13865 | ||
252b5132 RH |
13866 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13867 | return 0; | |
13868 | ||
c4e7957c | 13869 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13870 | { |
13871 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13872 | return 0; | |
13873 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13874 | return 2; | |
13875 | } | |
13876 | else | |
13877 | { | |
13878 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13879 | return 0; | |
13880 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13881 | return -2; | |
13882 | } | |
13883 | ||
13884 | return 0; | |
13885 | } | |
13886 | ||
13887 | /* Convert a machine dependent frag. */ | |
13888 | ||
13889 | void | |
17a2f251 | 13890 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13891 | { |
4a6a3df4 AO |
13892 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13893 | { | |
13894 | bfd_byte *buf; | |
13895 | unsigned long insn; | |
13896 | expressionS exp; | |
13897 | fixS *fixp; | |
b34976b6 | 13898 | |
4a6a3df4 AO |
13899 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13900 | ||
13901 | if (target_big_endian) | |
13902 | insn = bfd_getb32 (buf); | |
13903 | else | |
13904 | insn = bfd_getl32 (buf); | |
b34976b6 | 13905 | |
4a6a3df4 AO |
13906 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13907 | { | |
13908 | /* We generate a fixup instead of applying it right now | |
13909 | because, if there are linker relaxations, we're going to | |
13910 | need the relocations. */ | |
13911 | exp.X_op = O_symbol; | |
13912 | exp.X_add_symbol = fragp->fr_symbol; | |
13913 | exp.X_add_number = fragp->fr_offset; | |
13914 | ||
13915 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13916 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13917 | fixp->fx_file = fragp->fr_file; |
13918 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13919 | |
2132e3a3 | 13920 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13921 | buf += 4; |
13922 | } | |
13923 | else | |
13924 | { | |
13925 | int i; | |
13926 | ||
13927 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13928 | _("relaxed out-of-range branch into a jump")); | |
13929 | ||
13930 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13931 | goto uncond; | |
13932 | ||
13933 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13934 | { | |
13935 | /* Reverse the branch. */ | |
13936 | switch ((insn >> 28) & 0xf) | |
13937 | { | |
13938 | case 4: | |
13939 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13940 | have the condition reversed by tweaking a single | |
13941 | bit, and their opcodes all have 0x4???????. */ | |
13942 | assert ((insn & 0xf1000000) == 0x41000000); | |
13943 | insn ^= 0x00010000; | |
13944 | break; | |
13945 | ||
13946 | case 0: | |
13947 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 13948 | bltzal 0x04100000 bgezal 0x04110000 */ |
4a6a3df4 AO |
13949 | assert ((insn & 0xfc0e0000) == 0x04000000); |
13950 | insn ^= 0x00010000; | |
13951 | break; | |
b34976b6 | 13952 | |
4a6a3df4 AO |
13953 | case 1: |
13954 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 13955 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
13956 | insn ^= 0x04000000; |
13957 | break; | |
13958 | ||
13959 | default: | |
13960 | abort (); | |
13961 | } | |
13962 | } | |
13963 | ||
13964 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13965 | { | |
13966 | /* Clear the and-link bit. */ | |
13967 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13968 | ||
54f4ddb3 TS |
13969 | /* bltzal 0x04100000 bgezal 0x04110000 |
13970 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
13971 | insn &= ~0x00100000; |
13972 | } | |
13973 | ||
13974 | /* Branch over the branch (if the branch was likely) or the | |
13975 | full jump (not likely case). Compute the offset from the | |
13976 | current instruction to branch to. */ | |
13977 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13978 | i = 16; | |
13979 | else | |
13980 | { | |
13981 | /* How many bytes in instructions we've already emitted? */ | |
13982 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13983 | /* How many bytes in instructions from here to the end? */ | |
13984 | i = fragp->fr_var - i; | |
13985 | } | |
13986 | /* Convert to instruction count. */ | |
13987 | i >>= 2; | |
13988 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13989 | i--; |
4a6a3df4 AO |
13990 | insn |= i; |
13991 | /* Branch over the jump. */ | |
2132e3a3 | 13992 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13993 | buf += 4; |
13994 | ||
54f4ddb3 | 13995 | /* nop */ |
2132e3a3 | 13996 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13997 | buf += 4; |
13998 | ||
13999 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14000 | { | |
14001 | /* beql $0, $0, 2f */ | |
14002 | insn = 0x50000000; | |
14003 | /* Compute the PC offset from the current instruction to | |
14004 | the end of the variable frag. */ | |
14005 | /* How many bytes in instructions we've already emitted? */ | |
14006 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14007 | /* How many bytes in instructions from here to the end? */ | |
14008 | i = fragp->fr_var - i; | |
14009 | /* Convert to instruction count. */ | |
14010 | i >>= 2; | |
14011 | /* Don't decrement i, because we want to branch over the | |
14012 | delay slot. */ | |
14013 | ||
14014 | insn |= i; | |
2132e3a3 | 14015 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14016 | buf += 4; |
14017 | ||
2132e3a3 | 14018 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14019 | buf += 4; |
14020 | } | |
14021 | ||
14022 | uncond: | |
14023 | if (mips_pic == NO_PIC) | |
14024 | { | |
14025 | /* j or jal. */ | |
14026 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14027 | ? 0x0c000000 : 0x08000000); | |
14028 | exp.X_op = O_symbol; | |
14029 | exp.X_add_symbol = fragp->fr_symbol; | |
14030 | exp.X_add_number = fragp->fr_offset; | |
14031 | ||
14032 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14033 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14034 | fixp->fx_file = fragp->fr_file; |
14035 | fixp->fx_line = fragp->fr_line; | |
14036 | ||
2132e3a3 | 14037 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14038 | buf += 4; |
14039 | } | |
14040 | else | |
14041 | { | |
14042 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
14043 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
14044 | exp.X_op = O_symbol; | |
14045 | exp.X_add_symbol = fragp->fr_symbol; | |
14046 | exp.X_add_number = fragp->fr_offset; | |
14047 | ||
14048 | if (fragp->fr_offset) | |
14049 | { | |
14050 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14051 | exp.X_add_number = 0; | |
14052 | } | |
14053 | ||
14054 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14055 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14056 | fixp->fx_file = fragp->fr_file; |
14057 | fixp->fx_line = fragp->fr_line; | |
14058 | ||
2132e3a3 | 14059 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14060 | buf += 4; |
b34976b6 | 14061 | |
4a6a3df4 AO |
14062 | if (mips_opts.isa == ISA_MIPS1) |
14063 | { | |
14064 | /* nop */ | |
2132e3a3 | 14065 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14066 | buf += 4; |
14067 | } | |
14068 | ||
14069 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
14070 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14071 | ||
14072 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14073 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14074 | fixp->fx_file = fragp->fr_file; |
14075 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14076 | |
2132e3a3 | 14077 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14078 | buf += 4; |
14079 | ||
14080 | /* j(al)r $at. */ | |
14081 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14082 | insn = 0x0020f809; | |
14083 | else | |
14084 | insn = 0x00200008; | |
14085 | ||
2132e3a3 | 14086 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14087 | buf += 4; |
14088 | } | |
14089 | } | |
14090 | ||
14091 | assert (buf == (bfd_byte *)fragp->fr_literal | |
14092 | + fragp->fr_fix + fragp->fr_var); | |
14093 | ||
14094 | fragp->fr_fix += fragp->fr_var; | |
14095 | ||
14096 | return; | |
14097 | } | |
14098 | ||
252b5132 RH |
14099 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14100 | { | |
14101 | int type; | |
3994f87e | 14102 | const struct mips16_immed_operand *op; |
b34976b6 | 14103 | bfd_boolean small, ext; |
252b5132 RH |
14104 | offsetT val; |
14105 | bfd_byte *buf; | |
14106 | unsigned long insn; | |
b34976b6 | 14107 | bfd_boolean use_extend; |
252b5132 RH |
14108 | unsigned short extend; |
14109 | ||
14110 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14111 | op = mips16_immed_operands; | |
14112 | while (op->type != type) | |
14113 | ++op; | |
14114 | ||
14115 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14116 | { | |
b34976b6 AM |
14117 | small = FALSE; |
14118 | ext = TRUE; | |
252b5132 RH |
14119 | } |
14120 | else | |
14121 | { | |
b34976b6 AM |
14122 | small = TRUE; |
14123 | ext = FALSE; | |
252b5132 RH |
14124 | } |
14125 | ||
6386f3a7 | 14126 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14127 | val = S_GET_VALUE (fragp->fr_symbol); |
14128 | if (op->pcrel) | |
14129 | { | |
14130 | addressT addr; | |
14131 | ||
14132 | addr = fragp->fr_address + fragp->fr_fix; | |
14133 | ||
14134 | /* The rules for the base address of a PC relative reloc are | |
14135 | complicated; see mips16_extended_frag. */ | |
14136 | if (type == 'p' || type == 'q') | |
14137 | { | |
14138 | addr += 2; | |
14139 | if (ext) | |
14140 | addr += 2; | |
14141 | /* Ignore the low bit in the target, since it will be | |
14142 | set for a text label. */ | |
14143 | if ((val & 1) != 0) | |
14144 | --val; | |
14145 | } | |
14146 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14147 | addr -= 4; | |
14148 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14149 | addr -= 2; | |
14150 | ||
14151 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14152 | val -= addr; | |
14153 | ||
14154 | /* Make sure the section winds up with the alignment we have | |
14155 | assumed. */ | |
14156 | if (op->shift > 0) | |
14157 | record_alignment (asec, op->shift); | |
14158 | } | |
14159 | ||
14160 | if (ext | |
14161 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14162 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14163 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14164 | _("extended instruction in delay slot")); | |
14165 | ||
14166 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14167 | ||
14168 | if (target_big_endian) | |
14169 | insn = bfd_getb16 (buf); | |
14170 | else | |
14171 | insn = bfd_getl16 (buf); | |
14172 | ||
14173 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14174 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14175 | small, ext, &insn, &use_extend, &extend); | |
14176 | ||
14177 | if (use_extend) | |
14178 | { | |
2132e3a3 | 14179 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14180 | fragp->fr_fix += 2; |
14181 | buf += 2; | |
14182 | } | |
14183 | ||
2132e3a3 | 14184 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14185 | fragp->fr_fix += 2; |
14186 | buf += 2; | |
14187 | } | |
14188 | else | |
14189 | { | |
4d7206a2 RS |
14190 | int first, second; |
14191 | fixS *fixp; | |
252b5132 | 14192 | |
4d7206a2 RS |
14193 | first = RELAX_FIRST (fragp->fr_subtype); |
14194 | second = RELAX_SECOND (fragp->fr_subtype); | |
14195 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14196 | |
584892a6 RS |
14197 | /* Possibly emit a warning if we've chosen the longer option. */ |
14198 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14199 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14200 | { | |
14201 | const char *msg = macro_warning (fragp->fr_subtype); | |
14202 | if (msg != 0) | |
14203 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
14204 | } | |
14205 | ||
4d7206a2 RS |
14206 | /* Go through all the fixups for the first sequence. Disable them |
14207 | (by marking them as done) if we're going to use the second | |
14208 | sequence instead. */ | |
14209 | while (fixp | |
14210 | && fixp->fx_frag == fragp | |
14211 | && fixp->fx_where < fragp->fr_fix - second) | |
14212 | { | |
14213 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14214 | fixp->fx_done = 1; | |
14215 | fixp = fixp->fx_next; | |
14216 | } | |
252b5132 | 14217 | |
4d7206a2 RS |
14218 | /* Go through the fixups for the second sequence. Disable them if |
14219 | we're going to use the first sequence, otherwise adjust their | |
14220 | addresses to account for the relaxation. */ | |
14221 | while (fixp && fixp->fx_frag == fragp) | |
14222 | { | |
14223 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14224 | fixp->fx_where -= first; | |
14225 | else | |
14226 | fixp->fx_done = 1; | |
14227 | fixp = fixp->fx_next; | |
14228 | } | |
14229 | ||
14230 | /* Now modify the frag contents. */ | |
14231 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14232 | { | |
14233 | char *start; | |
14234 | ||
14235 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14236 | memmove (start, start + first, second); | |
14237 | fragp->fr_fix -= first; | |
14238 | } | |
14239 | else | |
14240 | fragp->fr_fix -= second; | |
252b5132 RH |
14241 | } |
14242 | } | |
14243 | ||
14244 | #ifdef OBJ_ELF | |
14245 | ||
14246 | /* This function is called after the relocs have been generated. | |
14247 | We've been storing mips16 text labels as odd. Here we convert them | |
14248 | back to even for the convenience of the debugger. */ | |
14249 | ||
14250 | void | |
17a2f251 | 14251 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14252 | { |
14253 | asymbol **syms; | |
14254 | unsigned int count, i; | |
14255 | ||
f43abd2b | 14256 | if (!IS_ELF) |
252b5132 RH |
14257 | return; |
14258 | ||
14259 | syms = bfd_get_outsymbols (stdoutput); | |
14260 | count = bfd_get_symcount (stdoutput); | |
14261 | for (i = 0; i < count; i++, syms++) | |
14262 | { | |
14263 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
14264 | && ((*syms)->value & 1) != 0) | |
14265 | { | |
14266 | (*syms)->value &= ~1; | |
14267 | /* If the symbol has an odd size, it was probably computed | |
14268 | incorrectly, so adjust that as well. */ | |
14269 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14270 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14271 | } | |
14272 | } | |
14273 | } | |
14274 | ||
14275 | #endif | |
14276 | ||
14277 | /* This function is called whenever a label is defined. It is used | |
14278 | when handling branch delays; if a branch has a label, we assume we | |
14279 | can not move it. */ | |
14280 | ||
14281 | void | |
17a2f251 | 14282 | mips_define_label (symbolS *sym) |
252b5132 | 14283 | { |
a8dbcb85 | 14284 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14285 | struct insn_label_list *l; |
14286 | ||
14287 | if (free_insn_labels == NULL) | |
14288 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14289 | else | |
14290 | { | |
14291 | l = free_insn_labels; | |
14292 | free_insn_labels = l->next; | |
14293 | } | |
14294 | ||
14295 | l->label = sym; | |
a8dbcb85 TS |
14296 | l->next = si->label_list; |
14297 | si->label_list = l; | |
07a53e5c RH |
14298 | |
14299 | #ifdef OBJ_ELF | |
14300 | dwarf2_emit_label (sym); | |
14301 | #endif | |
252b5132 RH |
14302 | } |
14303 | \f | |
14304 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14305 | ||
14306 | /* Some special processing for a MIPS ELF file. */ | |
14307 | ||
14308 | void | |
17a2f251 | 14309 | mips_elf_final_processing (void) |
252b5132 RH |
14310 | { |
14311 | /* Write out the register information. */ | |
316f5878 | 14312 | if (mips_abi != N64_ABI) |
252b5132 RH |
14313 | { |
14314 | Elf32_RegInfo s; | |
14315 | ||
14316 | s.ri_gprmask = mips_gprmask; | |
14317 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14318 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14319 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14320 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14321 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14322 | ||
14323 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14324 | ((Elf32_External_RegInfo *) | |
14325 | mips_regmask_frag)); | |
14326 | } | |
14327 | else | |
14328 | { | |
14329 | Elf64_Internal_RegInfo s; | |
14330 | ||
14331 | s.ri_gprmask = mips_gprmask; | |
14332 | s.ri_pad = 0; | |
14333 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14334 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14335 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14336 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14337 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14338 | ||
14339 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14340 | ((Elf64_External_RegInfo *) | |
14341 | mips_regmask_frag)); | |
14342 | } | |
14343 | ||
14344 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14345 | sort of BFD interface for this. */ | |
14346 | if (mips_any_noreorder) | |
14347 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14348 | if (mips_pic != NO_PIC) | |
143d77c5 | 14349 | { |
252b5132 | 14350 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14351 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14352 | } | |
14353 | if (mips_abicalls) | |
14354 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14355 | |
98d3f06f | 14356 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14357 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14358 | file_ase_dsp is true. */ | |
8b082fb1 | 14359 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14360 | /* We may need to define a new flag for MT ASE, and set this flag when |
14361 | file_ase_mt is true. */ | |
a4672219 TS |
14362 | if (file_ase_mips16) |
14363 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14364 | #if 0 /* XXX FIXME */ |
14365 | if (file_ase_mips3d) | |
14366 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14367 | #endif | |
deec1734 CD |
14368 | if (file_ase_mdmx) |
14369 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14370 | |
bdaaa2e1 | 14371 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14372 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14373 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14374 | else if (mips_abi == O64_ABI) |
252b5132 | 14375 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14376 | else if (mips_abi == EABI_ABI) |
252b5132 | 14377 | { |
316f5878 | 14378 | if (!file_mips_gp32) |
252b5132 RH |
14379 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14380 | else | |
14381 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14382 | } | |
316f5878 | 14383 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14384 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14385 | ||
c9914766 | 14386 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14387 | |
14388 | if (mips_32bitmode) | |
14389 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14390 | |
14391 | #if 0 /* XXX FIXME */ | |
14392 | /* 32 bit code with 64 bit FP registers. */ | |
14393 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14394 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14395 | #endif | |
252b5132 RH |
14396 | } |
14397 | ||
14398 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14399 | \f | |
beae10d5 | 14400 | typedef struct proc { |
9b2f1d35 EC |
14401 | symbolS *func_sym; |
14402 | symbolS *func_end_sym; | |
beae10d5 KH |
14403 | unsigned long reg_mask; |
14404 | unsigned long reg_offset; | |
14405 | unsigned long fpreg_mask; | |
14406 | unsigned long fpreg_offset; | |
14407 | unsigned long frame_offset; | |
14408 | unsigned long frame_reg; | |
14409 | unsigned long pc_reg; | |
14410 | } procS; | |
252b5132 RH |
14411 | |
14412 | static procS cur_proc; | |
14413 | static procS *cur_proc_ptr; | |
14414 | static int numprocs; | |
14415 | ||
742a56fe RS |
14416 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
14417 | nop as "0". */ | |
14418 | ||
14419 | char | |
14420 | mips_nop_opcode (void) | |
14421 | { | |
14422 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
14423 | } | |
14424 | ||
14425 | /* Fill in an rs_align_code fragment. This only needs to do something | |
14426 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 14427 | |
0a9ef439 | 14428 | void |
17a2f251 | 14429 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14430 | { |
742a56fe RS |
14431 | char *p; |
14432 | ||
0a9ef439 RH |
14433 | if (fragp->fr_type != rs_align_code) |
14434 | return; | |
14435 | ||
742a56fe RS |
14436 | p = fragp->fr_literal + fragp->fr_fix; |
14437 | if (*p) | |
a19d8eb0 | 14438 | { |
0a9ef439 | 14439 | int bytes; |
a19d8eb0 | 14440 | |
0a9ef439 | 14441 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
0a9ef439 RH |
14442 | if (bytes & 1) |
14443 | { | |
14444 | *p++ = 0; | |
f9419b05 | 14445 | fragp->fr_fix++; |
0a9ef439 | 14446 | } |
742a56fe | 14447 | md_number_to_chars (p, mips16_nop_insn.insn_opcode, 2); |
0a9ef439 | 14448 | fragp->fr_var = 2; |
a19d8eb0 | 14449 | } |
a19d8eb0 CP |
14450 | } |
14451 | ||
252b5132 | 14452 | static void |
17a2f251 | 14453 | md_obj_begin (void) |
252b5132 RH |
14454 | { |
14455 | } | |
14456 | ||
14457 | static void | |
17a2f251 | 14458 | md_obj_end (void) |
252b5132 | 14459 | { |
54f4ddb3 | 14460 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14461 | if (cur_proc_ptr) |
9a41af64 | 14462 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14463 | } |
14464 | ||
14465 | static long | |
17a2f251 | 14466 | get_number (void) |
252b5132 RH |
14467 | { |
14468 | int negative = 0; | |
14469 | long val = 0; | |
14470 | ||
14471 | if (*input_line_pointer == '-') | |
14472 | { | |
14473 | ++input_line_pointer; | |
14474 | negative = 1; | |
14475 | } | |
3882b010 | 14476 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14477 | as_bad (_("expected simple number")); |
252b5132 RH |
14478 | if (input_line_pointer[0] == '0') |
14479 | { | |
14480 | if (input_line_pointer[1] == 'x') | |
14481 | { | |
14482 | input_line_pointer += 2; | |
3882b010 | 14483 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14484 | { |
14485 | val <<= 4; | |
14486 | val |= hex_value (*input_line_pointer++); | |
14487 | } | |
14488 | return negative ? -val : val; | |
14489 | } | |
14490 | else | |
14491 | { | |
14492 | ++input_line_pointer; | |
3882b010 | 14493 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14494 | { |
14495 | val <<= 3; | |
14496 | val |= *input_line_pointer++ - '0'; | |
14497 | } | |
14498 | return negative ? -val : val; | |
14499 | } | |
14500 | } | |
3882b010 | 14501 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14502 | { |
14503 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14504 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14505 | as_warn (_("invalid number")); |
252b5132 RH |
14506 | return -1; |
14507 | } | |
3882b010 | 14508 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14509 | { |
14510 | val *= 10; | |
14511 | val += *input_line_pointer++ - '0'; | |
14512 | } | |
14513 | return negative ? -val : val; | |
14514 | } | |
14515 | ||
14516 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14517 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14518 | case .file implies DWARF-2. */ | |
14519 | ||
14520 | static void | |
17a2f251 | 14521 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14522 | { |
ecb4347a DJ |
14523 | static int first_file_directive = 0; |
14524 | ||
c5dd6aab DJ |
14525 | if (ECOFF_DEBUGGING) |
14526 | { | |
14527 | get_number (); | |
14528 | s_app_file (0); | |
14529 | } | |
14530 | else | |
ecb4347a DJ |
14531 | { |
14532 | char *filename; | |
14533 | ||
14534 | filename = dwarf2_directive_file (0); | |
14535 | ||
14536 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14537 | directive even for stabs output. Make sure that this | |
14538 | ".file" is handled. Note that you need a version of GCC | |
14539 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14540 | if (filename != NULL && ! first_file_directive) | |
14541 | { | |
14542 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14543 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14544 | } |
14545 | first_file_directive = 1; | |
14546 | } | |
c5dd6aab DJ |
14547 | } |
14548 | ||
14549 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14550 | |
14551 | static void | |
17a2f251 | 14552 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14553 | { |
c5dd6aab DJ |
14554 | if (!ECOFF_DEBUGGING) |
14555 | dwarf2_directive_loc (0); | |
252b5132 RH |
14556 | } |
14557 | ||
252b5132 RH |
14558 | /* The .end directive. */ |
14559 | ||
14560 | static void | |
17a2f251 | 14561 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14562 | { |
14563 | symbolS *p; | |
252b5132 | 14564 | |
7a621144 DJ |
14565 | /* Following functions need their own .frame and .cprestore directives. */ |
14566 | mips_frame_reg_valid = 0; | |
14567 | mips_cprestore_valid = 0; | |
14568 | ||
252b5132 RH |
14569 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14570 | { | |
14571 | p = get_symbol (); | |
14572 | demand_empty_rest_of_line (); | |
14573 | } | |
14574 | else | |
14575 | p = NULL; | |
14576 | ||
14949570 | 14577 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14578 | as_warn (_(".end not in text section")); |
14579 | ||
14580 | if (!cur_proc_ptr) | |
14581 | { | |
14582 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14583 | demand_empty_rest_of_line (); | |
14584 | return; | |
14585 | } | |
14586 | ||
14587 | if (p != NULL) | |
14588 | { | |
14589 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14590 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14591 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14592 | |
14593 | if (debug_type == DEBUG_STABS) | |
14594 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14595 | S_GET_NAME (p)); | |
252b5132 RH |
14596 | } |
14597 | else | |
14598 | as_warn (_(".end directive missing or unknown symbol")); | |
14599 | ||
2132e3a3 | 14600 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14601 | /* Create an expression to calculate the size of the function. */ |
14602 | if (p && cur_proc_ptr) | |
14603 | { | |
14604 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14605 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14606 | ||
14607 | obj->size = exp; | |
14608 | exp->X_op = O_subtract; | |
14609 | exp->X_add_symbol = symbol_temp_new_now (); | |
14610 | exp->X_op_symbol = p; | |
14611 | exp->X_add_number = 0; | |
14612 | ||
14613 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14614 | } | |
14615 | ||
ecb4347a | 14616 | /* Generate a .pdr section. */ |
f43abd2b | 14617 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
14618 | { |
14619 | segT saved_seg = now_seg; | |
14620 | subsegT saved_subseg = now_subseg; | |
14621 | valueT dot; | |
14622 | expressionS exp; | |
14623 | char *fragp; | |
252b5132 | 14624 | |
ecb4347a | 14625 | dot = frag_now_fix (); |
252b5132 RH |
14626 | |
14627 | #ifdef md_flush_pending_output | |
ecb4347a | 14628 | md_flush_pending_output (); |
252b5132 RH |
14629 | #endif |
14630 | ||
ecb4347a DJ |
14631 | assert (pdr_seg); |
14632 | subseg_set (pdr_seg, 0); | |
252b5132 | 14633 | |
ecb4347a DJ |
14634 | /* Write the symbol. */ |
14635 | exp.X_op = O_symbol; | |
14636 | exp.X_add_symbol = p; | |
14637 | exp.X_add_number = 0; | |
14638 | emit_expr (&exp, 4); | |
252b5132 | 14639 | |
ecb4347a | 14640 | fragp = frag_more (7 * 4); |
252b5132 | 14641 | |
17a2f251 TS |
14642 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14643 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14644 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14645 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14646 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14647 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14648 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14649 | |
ecb4347a DJ |
14650 | subseg_set (saved_seg, saved_subseg); |
14651 | } | |
14652 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14653 | |
14654 | cur_proc_ptr = NULL; | |
14655 | } | |
14656 | ||
14657 | /* The .aent and .ent directives. */ | |
14658 | ||
14659 | static void | |
17a2f251 | 14660 | s_mips_ent (int aent) |
252b5132 | 14661 | { |
252b5132 | 14662 | symbolS *symbolP; |
252b5132 RH |
14663 | |
14664 | symbolP = get_symbol (); | |
14665 | if (*input_line_pointer == ',') | |
f9419b05 | 14666 | ++input_line_pointer; |
252b5132 | 14667 | SKIP_WHITESPACE (); |
3882b010 | 14668 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14669 | || *input_line_pointer == '-') |
874e8986 | 14670 | get_number (); |
252b5132 | 14671 | |
14949570 | 14672 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14673 | as_warn (_(".ent or .aent not in text section.")); |
14674 | ||
14675 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14676 | as_warn (_("missing .end")); |
252b5132 RH |
14677 | |
14678 | if (!aent) | |
14679 | { | |
7a621144 DJ |
14680 | /* This function needs its own .frame and .cprestore directives. */ |
14681 | mips_frame_reg_valid = 0; | |
14682 | mips_cprestore_valid = 0; | |
14683 | ||
252b5132 RH |
14684 | cur_proc_ptr = &cur_proc; |
14685 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14686 | ||
9b2f1d35 | 14687 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14688 | |
49309057 | 14689 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14690 | |
f9419b05 | 14691 | ++numprocs; |
ecb4347a DJ |
14692 | |
14693 | if (debug_type == DEBUG_STABS) | |
14694 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14695 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14696 | } |
14697 | ||
14698 | demand_empty_rest_of_line (); | |
14699 | } | |
14700 | ||
14701 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14702 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14703 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14704 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14705 | symbol table (in the mdebug section). */ |
14706 | ||
14707 | static void | |
17a2f251 | 14708 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14709 | { |
ecb4347a | 14710 | #ifdef OBJ_ELF |
f43abd2b | 14711 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
14712 | { |
14713 | long val; | |
252b5132 | 14714 | |
ecb4347a DJ |
14715 | if (cur_proc_ptr == (procS *) NULL) |
14716 | { | |
14717 | as_warn (_(".frame outside of .ent")); | |
14718 | demand_empty_rest_of_line (); | |
14719 | return; | |
14720 | } | |
252b5132 | 14721 | |
ecb4347a DJ |
14722 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14723 | ||
14724 | SKIP_WHITESPACE (); | |
14725 | if (*input_line_pointer++ != ',' | |
14726 | || get_absolute_expression_and_terminator (&val) != ',') | |
14727 | { | |
14728 | as_warn (_("Bad .frame directive")); | |
14729 | --input_line_pointer; | |
14730 | demand_empty_rest_of_line (); | |
14731 | return; | |
14732 | } | |
252b5132 | 14733 | |
ecb4347a DJ |
14734 | cur_proc_ptr->frame_offset = val; |
14735 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14736 | |
252b5132 | 14737 | demand_empty_rest_of_line (); |
252b5132 | 14738 | } |
ecb4347a DJ |
14739 | else |
14740 | #endif /* OBJ_ELF */ | |
14741 | s_ignore (ignore); | |
252b5132 RH |
14742 | } |
14743 | ||
bdaaa2e1 KH |
14744 | /* The .fmask and .mask directives. If the mdebug section is present |
14745 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14746 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14747 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14748 | make reference to the ecoff symbol table (in the mdebug section). */ |
14749 | ||
14750 | static void | |
17a2f251 | 14751 | s_mips_mask (int reg_type) |
252b5132 | 14752 | { |
ecb4347a | 14753 | #ifdef OBJ_ELF |
f43abd2b | 14754 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 14755 | { |
ecb4347a | 14756 | long mask, off; |
252b5132 | 14757 | |
ecb4347a DJ |
14758 | if (cur_proc_ptr == (procS *) NULL) |
14759 | { | |
14760 | as_warn (_(".mask/.fmask outside of .ent")); | |
14761 | demand_empty_rest_of_line (); | |
14762 | return; | |
14763 | } | |
252b5132 | 14764 | |
ecb4347a DJ |
14765 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14766 | { | |
14767 | as_warn (_("Bad .mask/.fmask directive")); | |
14768 | --input_line_pointer; | |
14769 | demand_empty_rest_of_line (); | |
14770 | return; | |
14771 | } | |
252b5132 | 14772 | |
ecb4347a DJ |
14773 | off = get_absolute_expression (); |
14774 | ||
14775 | if (reg_type == 'F') | |
14776 | { | |
14777 | cur_proc_ptr->fpreg_mask = mask; | |
14778 | cur_proc_ptr->fpreg_offset = off; | |
14779 | } | |
14780 | else | |
14781 | { | |
14782 | cur_proc_ptr->reg_mask = mask; | |
14783 | cur_proc_ptr->reg_offset = off; | |
14784 | } | |
14785 | ||
14786 | demand_empty_rest_of_line (); | |
252b5132 RH |
14787 | } |
14788 | else | |
ecb4347a DJ |
14789 | #endif /* OBJ_ELF */ |
14790 | s_ignore (reg_type); | |
252b5132 RH |
14791 | } |
14792 | ||
316f5878 RS |
14793 | /* A table describing all the processors gas knows about. Names are |
14794 | matched in the order listed. | |
e7af610e | 14795 | |
316f5878 RS |
14796 | To ease comparison, please keep this table in the same order as |
14797 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14798 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14799 | { | |
316f5878 | 14800 | /* Entries for generic ISAs */ |
ad3fea08 TS |
14801 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
14802 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
14803 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
14804 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
14805 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
14806 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
14807 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14808 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
14809 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
14810 | |
14811 | /* MIPS I */ | |
ad3fea08 TS |
14812 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
14813 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14814 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
14815 | |
14816 | /* MIPS II */ | |
ad3fea08 | 14817 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
14818 | |
14819 | /* MIPS III */ | |
ad3fea08 TS |
14820 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
14821 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14822 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14823 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
14824 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
14825 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14826 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
14827 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
14828 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14829 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14830 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14831 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
14832 | /* ST Microelectronics Loongson 2E and 2F cores */ |
14833 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
14834 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
14835 | |
14836 | /* MIPS IV */ | |
ad3fea08 TS |
14837 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
14838 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14839 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14840 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
14841 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
14842 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
14843 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
14844 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14845 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14846 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14847 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14848 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
14849 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
14850 | |
14851 | /* MIPS 32 */ | |
ad3fea08 TS |
14852 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
14853 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14854 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14855 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
14856 | ||
14857 | /* MIPS 32 Release 2 */ | |
14858 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14859 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14860 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14861 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14862 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14863 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 14864 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 14865 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 14866 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
14867 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14868 | /* Deprecated forms of the above. */ | |
14869 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 14870 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 14871 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 14872 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 14873 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 14874 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
14875 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14876 | /* Deprecated forms of the above. */ | |
14877 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 14878 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 14879 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
14880 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14881 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14882 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14883 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
14884 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14885 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14886 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14887 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14888 | /* Deprecated forms of the above. */ | |
14889 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
14890 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
14891 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14892 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14893 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
14894 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14895 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14896 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14897 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14898 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14899 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14900 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14901 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14902 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14903 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14904 | /* Deprecated forms of the above. */ | |
14905 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14906 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14907 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14908 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 14909 | |
316f5878 | 14910 | /* MIPS 64 */ |
ad3fea08 TS |
14911 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
14912 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14913 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 14914 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 TS |
14915 | |
14916 | /* MIPS 64 Release 2 */ | |
e7af610e | 14917 | |
c7a23324 | 14918 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
14919 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
14920 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
14921 | /* Broadcom SB-1A CPU core */ |
14922 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
14923 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 14924 | |
967344c6 AN |
14925 | /* Cavium Networks Octeon CPU core */ |
14926 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
14927 | ||
316f5878 RS |
14928 | /* End marker */ |
14929 | { NULL, 0, 0, 0 } | |
14930 | }; | |
e7af610e | 14931 | |
84ea6cf2 | 14932 | |
316f5878 RS |
14933 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14934 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14935 | |
316f5878 | 14936 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14937 | |
b34976b6 | 14938 | static bfd_boolean |
17a2f251 | 14939 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14940 | { |
14941 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14942 | given++, canonical++; | |
14943 | ||
14944 | return ((*given == 0 && *canonical == 0) | |
14945 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14946 | } | |
14947 | ||
14948 | ||
14949 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14950 | CPU name. We've traditionally allowed a lot of variation here. | |
14951 | ||
14952 | Note: this function is shared between GCC and GAS. */ | |
14953 | ||
b34976b6 | 14954 | static bfd_boolean |
17a2f251 | 14955 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14956 | { |
14957 | /* First see if the name matches exactly, or with a final "000" | |
14958 | turned into "k". */ | |
14959 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14960 | return TRUE; |
316f5878 RS |
14961 | |
14962 | /* If not, try comparing based on numerical designation alone. | |
14963 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14964 | if (TOLOWER (*given) == 'r') | |
14965 | given++; | |
14966 | if (!ISDIGIT (*given)) | |
b34976b6 | 14967 | return FALSE; |
316f5878 RS |
14968 | |
14969 | /* Skip over some well-known prefixes in the canonical name, | |
14970 | hoping to find a number there too. */ | |
14971 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14972 | canonical += 2; | |
14973 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14974 | canonical += 2; | |
14975 | else if (TOLOWER (canonical[0]) == 'r') | |
14976 | canonical += 1; | |
14977 | ||
14978 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14979 | } | |
14980 | ||
14981 | ||
14982 | /* Parse an option that takes the name of a processor as its argument. | |
14983 | OPTION is the name of the option and CPU_STRING is the argument. | |
14984 | Return the corresponding processor enumeration if the CPU_STRING is | |
14985 | recognized, otherwise report an error and return null. | |
14986 | ||
14987 | A similar function exists in GCC. */ | |
e7af610e NC |
14988 | |
14989 | static const struct mips_cpu_info * | |
17a2f251 | 14990 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14991 | { |
316f5878 | 14992 | const struct mips_cpu_info *p; |
e7af610e | 14993 | |
316f5878 RS |
14994 | /* 'from-abi' selects the most compatible architecture for the given |
14995 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14996 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14997 | version. Look first at the -mgp options, if given, otherwise base | |
14998 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14999 | |
316f5878 RS |
15000 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15001 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15002 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15003 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15004 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15005 | { | |
15006 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15007 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15008 | ||
15009 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15010 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15011 | ||
15012 | if (file_mips_gp32 >= 0) | |
15013 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15014 | ||
15015 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15016 | ? ISA_MIPS3 | |
15017 | : ISA_MIPS1); | |
15018 | } | |
15019 | ||
15020 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15021 | if (strcasecmp (cpu_string, "default") == 0) | |
15022 | return 0; | |
15023 | ||
15024 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15025 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15026 | return p; | |
15027 | ||
15028 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
15029 | return 0; | |
e7af610e NC |
15030 | } |
15031 | ||
316f5878 RS |
15032 | /* Return the canonical processor information for ISA (a member of the |
15033 | ISA_MIPS* enumeration). */ | |
15034 | ||
e7af610e | 15035 | static const struct mips_cpu_info * |
17a2f251 | 15036 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15037 | { |
15038 | int i; | |
15039 | ||
15040 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15041 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15042 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15043 | return (&mips_cpu_info_table[i]); |
15044 | ||
e972090a | 15045 | return NULL; |
e7af610e | 15046 | } |
fef14a42 TS |
15047 | |
15048 | static const struct mips_cpu_info * | |
17a2f251 | 15049 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15050 | { |
15051 | int i; | |
15052 | ||
15053 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15054 | if (arch == mips_cpu_info_table[i].cpu) | |
15055 | return (&mips_cpu_info_table[i]); | |
15056 | ||
15057 | return NULL; | |
15058 | } | |
316f5878 RS |
15059 | \f |
15060 | static void | |
17a2f251 | 15061 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15062 | { |
15063 | if (*first_p) | |
15064 | { | |
15065 | fprintf (stream, "%24s", ""); | |
15066 | *col_p = 24; | |
15067 | } | |
15068 | else | |
15069 | { | |
15070 | fprintf (stream, ", "); | |
15071 | *col_p += 2; | |
15072 | } | |
e7af610e | 15073 | |
316f5878 RS |
15074 | if (*col_p + strlen (string) > 72) |
15075 | { | |
15076 | fprintf (stream, "\n%24s", ""); | |
15077 | *col_p = 24; | |
15078 | } | |
15079 | ||
15080 | fprintf (stream, "%s", string); | |
15081 | *col_p += strlen (string); | |
15082 | ||
15083 | *first_p = 0; | |
15084 | } | |
15085 | ||
15086 | void | |
17a2f251 | 15087 | md_show_usage (FILE *stream) |
e7af610e | 15088 | { |
316f5878 RS |
15089 | int column, first; |
15090 | size_t i; | |
15091 | ||
15092 | fprintf (stream, _("\ | |
15093 | MIPS options:\n\ | |
316f5878 RS |
15094 | -EB generate big endian output\n\ |
15095 | -EL generate little endian output\n\ | |
15096 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15097 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15098 | implicitly with the gp register [default 8]\n")); | |
15099 | fprintf (stream, _("\ | |
15100 | -mips1 generate MIPS ISA I instructions\n\ | |
15101 | -mips2 generate MIPS ISA II instructions\n\ | |
15102 | -mips3 generate MIPS ISA III instructions\n\ | |
15103 | -mips4 generate MIPS ISA IV instructions\n\ | |
15104 | -mips5 generate MIPS ISA V instructions\n\ | |
15105 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15106 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15107 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15108 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15109 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15110 | ||
15111 | first = 1; | |
e7af610e NC |
15112 | |
15113 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15114 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15115 | show (stream, "from-abi", &column, &first); | |
15116 | fputc ('\n', stream); | |
e7af610e | 15117 | |
316f5878 RS |
15118 | fprintf (stream, _("\ |
15119 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15120 | -no-mCPU don't generate code specific to CPU.\n\ | |
15121 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15122 | ||
15123 | first = 1; | |
15124 | ||
15125 | show (stream, "3900", &column, &first); | |
15126 | show (stream, "4010", &column, &first); | |
15127 | show (stream, "4100", &column, &first); | |
15128 | show (stream, "4650", &column, &first); | |
15129 | fputc ('\n', stream); | |
15130 | ||
15131 | fprintf (stream, _("\ | |
15132 | -mips16 generate mips16 instructions\n\ | |
15133 | -no-mips16 do not generate mips16 instructions\n")); | |
15134 | fprintf (stream, _("\ | |
e16bfa71 TS |
15135 | -msmartmips generate smartmips instructions\n\ |
15136 | -mno-smartmips do not generate smartmips instructions\n")); | |
15137 | fprintf (stream, _("\ | |
74cd071d CF |
15138 | -mdsp generate DSP instructions\n\ |
15139 | -mno-dsp do not generate DSP instructions\n")); | |
15140 | fprintf (stream, _("\ | |
8b082fb1 TS |
15141 | -mdspr2 generate DSP R2 instructions\n\ |
15142 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15143 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15144 | -mmt generate MT instructions\n\ |
15145 | -mno-mt do not generate MT instructions\n")); | |
15146 | fprintf (stream, _("\ | |
d766e8ec | 15147 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15148 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
15149 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15150 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15151 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15152 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15153 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15154 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15155 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15156 | fprintf (stream, _("\ |
15157 | -mhard-float allow floating-point instructions\n\ | |
15158 | -msoft-float do not allow floating-point instructions\n\ | |
15159 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15160 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15161 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15162 | )); | |
316f5878 RS |
15163 | #ifdef OBJ_ELF |
15164 | fprintf (stream, _("\ | |
15165 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
0c000745 | 15166 | -mvxworks-pic generate VxWorks position independent code\n\ |
316f5878 RS |
15167 | -non_shared do not generate position independent code\n\ |
15168 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 15169 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15170 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15171 | position dependent (non shared) code\n\ |
316f5878 RS |
15172 | -mabi=ABI create ABI conformant object file for:\n")); |
15173 | ||
15174 | first = 1; | |
15175 | ||
15176 | show (stream, "32", &column, &first); | |
15177 | show (stream, "o64", &column, &first); | |
15178 | show (stream, "n32", &column, &first); | |
15179 | show (stream, "64", &column, &first); | |
15180 | show (stream, "eabi", &column, &first); | |
15181 | ||
15182 | fputc ('\n', stream); | |
15183 | ||
15184 | fprintf (stream, _("\ | |
15185 | -32 create o32 ABI object file (default)\n\ | |
15186 | -n32 create n32 ABI object file\n\ | |
15187 | -64 create 64 ABI object file\n")); | |
15188 | #endif | |
e7af610e | 15189 | } |
14e777e0 KB |
15190 | |
15191 | enum dwarf2_format | |
17a2f251 | 15192 | mips_dwarf2_format (void) |
14e777e0 | 15193 | { |
369943fe | 15194 | if (HAVE_64BIT_SYMBOLS) |
1de5b6a1 AO |
15195 | { |
15196 | #ifdef TE_IRIX | |
15197 | return dwarf2_format_64bit_irix; | |
15198 | #else | |
15199 | return dwarf2_format_64bit; | |
15200 | #endif | |
15201 | } | |
14e777e0 KB |
15202 | else |
15203 | return dwarf2_format_32bit; | |
15204 | } | |
73369e65 EC |
15205 | |
15206 | int | |
15207 | mips_dwarf2_addr_size (void) | |
15208 | { | |
369943fe | 15209 | if (HAVE_64BIT_SYMBOLS) |
73369e65 | 15210 | return 8; |
73369e65 EC |
15211 | else |
15212 | return 4; | |
15213 | } | |
5862107c EC |
15214 | |
15215 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15216 | void | |
15217 | mips_cfi_frame_initial_instructions (void) | |
15218 | { | |
15219 | cfi_add_CFA_def_cfa_register (SP); | |
15220 | } | |
15221 | ||
707bfff6 TS |
15222 | int |
15223 | tc_mips_regname_to_dw2regnum (char *regname) | |
15224 | { | |
15225 | unsigned int regnum = -1; | |
15226 | unsigned int reg; | |
15227 | ||
15228 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15229 | regnum = reg; | |
15230 | ||
15231 | return regnum; | |
15232 | } |