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3d3c5039 ILT |
1 | /* tc-mips.c -- assemble code for a MIPS chip. |
2 | Copyright (C) 1993 Free Software Foundation, Inc. | |
3 | Contributed by the OSF and Ralph Campbell. | |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to | |
22 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
23 | ||
24 | #include "as.h" | |
8358c818 | 25 | #include "config.h" |
3d3c5039 ILT |
26 | |
27 | #include <ctype.h> | |
28 | ||
29 | #ifndef __STDC__ | |
30 | #ifndef NO_STDARG | |
31 | #define NO_STDARG | |
32 | #endif | |
33 | #endif | |
34 | ||
35 | #ifndef NO_STDARG | |
36 | #include <stdarg.h> | |
37 | #else | |
38 | #ifndef NO_VARARGS | |
39 | #include <varargs.h> | |
40 | #endif /* NO_VARARGS */ | |
41 | #endif /* NO_STDARG */ | |
42 | ||
918692a5 | 43 | #include "opcode/mips.h" |
3d3c5039 | 44 | |
f2a663d3 ILT |
45 | #ifdef OBJ_ELF |
46 | #include "elf/mips.h" | |
47 | ||
48 | static char *mips_regmask_frag; | |
49 | #endif | |
50 | ||
3d3c5039 | 51 | #define AT 1 |
9226253a | 52 | #define PIC_CALL_REG 25 |
670a50eb | 53 | #define GP 28 |
9226253a ILT |
54 | #define SP 29 |
55 | #define FP 30 | |
3d3c5039 ILT |
56 | #define RA 31 |
57 | ||
88225433 ILT |
58 | /* Decide whether to do GP reference optimizations based on the object |
59 | file format. */ | |
60 | #undef GPOPT | |
61 | #ifdef OBJ_ECOFF | |
62 | #define GPOPT | |
63 | #endif | |
64 | #ifdef OBJ_ELF | |
65 | #define GPOPT | |
66 | #endif | |
67 | ||
04cb3372 ILT |
68 | /* The default target format to use. */ |
69 | #ifdef OBJ_AOUT | |
70 | #ifdef TARGET_BYTES_BIG_ENDIAN | |
71 | #define DEFAULT_TARGET_FORMAT "a.out-mips-big" | |
72 | #else | |
73 | #define DEFAULT_TARGET_FORMAT "a.out-mips-little" | |
74 | #endif | |
75 | #endif /* OBJ_AOUT */ | |
76 | #ifdef OBJ_ECOFF | |
77 | #ifdef TARGET_BYTES_BIG_ENDIAN | |
78 | #define DEFAULT_TARGET_FORMAT "ecoff-bigmips" | |
79 | #else | |
80 | #define DEFAULT_TARGET_FORMAT "ecoff-littlemips" | |
81 | #endif | |
82 | #endif /* OBJ_ECOFF */ | |
83 | #ifdef OBJ_ELF | |
84 | #ifdef TARGET_BYTES_BIG_ENDIAN | |
85 | #define DEFAULT_TARGET_FORMAT "elf32-bigmips" | |
86 | #else | |
87 | #define DEFAULT_TARGET_FORMAT "elf32-littlemips" | |
88 | #endif | |
89 | #endif /* OBJ_ELF */ | |
90 | ||
91 | const char *mips_target_format = DEFAULT_TARGET_FORMAT; | |
92 | ||
d2c71068 ILT |
93 | /* The name of the readonly data section. */ |
94 | #ifdef OBJ_AOUT | |
95 | #define RDATA_SECTION_NAME ".data" | |
96 | #endif | |
97 | #ifdef OBJ_ECOFF | |
98 | #define RDATA_SECTION_NAME ".rdata" | |
99 | #endif | |
100 | #ifdef OBJ_ELF | |
101 | #define RDATA_SECTION_NAME ".rodata" | |
102 | #endif | |
103 | ||
1aa6938e ILT |
104 | /* These variables are filled in with the masks of registers used. |
105 | The object format code reads them and puts them in the appropriate | |
106 | place. */ | |
107 | unsigned long mips_gprmask; | |
108 | unsigned long mips_cprmask[4]; | |
109 | ||
1051c97f ILT |
110 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
111 | temporarily using .set mipsN). */ | |
8358c818 ILT |
112 | static int mips_isa = -1; |
113 | ||
1051c97f ILT |
114 | /* MIPS ISA we are using for this output file. */ |
115 | static int file_mips_isa; | |
116 | ||
d9aba805 ILT |
117 | /* MIPS PIC level. */ |
118 | ||
119 | enum mips_pic_level | |
120 | { | |
121 | /* Do not generate PIC code. */ | |
122 | NO_PIC, | |
123 | ||
124 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
125 | not sure what it is supposed to do. */ | |
126 | IRIX4_PIC, | |
127 | ||
128 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
129 | SVR4_PIC, | |
130 | ||
131 | /* Generate PIC code without using a global offset table: the data | |
132 | segment has a maximum size of 64K, all data references are off | |
133 | the $gp register, and all text references are PC relative. This | |
134 | is used on some embedded systems. */ | |
135 | EMBEDDED_PIC | |
136 | }; | |
137 | ||
138 | static enum mips_pic_level mips_pic; | |
9226253a | 139 | |
8ea7f4e8 ILT |
140 | /* 1 if trap instructions should used for overflow rather than break |
141 | instructions. */ | |
142 | static int mips_trap; | |
143 | ||
3d3c5039 ILT |
144 | static int mips_warn_about_macros; |
145 | static int mips_noreorder; | |
0dd2d296 | 146 | static int mips_any_noreorder; |
3d3c5039 ILT |
147 | static int mips_nomove; |
148 | static int mips_noat; | |
149 | static int mips_nobopt; | |
150 | ||
88225433 | 151 | #ifdef GPOPT |
670a50eb ILT |
152 | /* The size of the small data section. */ |
153 | static int g_switch_value = 8; | |
42562568 ILT |
154 | /* Whether the -G option was used. */ |
155 | static int g_switch_seen = 0; | |
670a50eb ILT |
156 | #endif |
157 | ||
3d3c5039 ILT |
158 | #define N_RMASK 0xc4 |
159 | #define N_VFP 0xd4 | |
160 | ||
161 | /* handle of the OPCODE hash table */ | |
162 | static struct hash_control *op_hash = NULL; | |
163 | ||
164 | /* This array holds the chars that always start a comment. If the | |
165 | pre-processor is disabled, these aren't very useful */ | |
166 | const char comment_chars[] = "#"; | |
167 | ||
168 | /* This array holds the chars that only start a comment at the beginning of | |
169 | a line. If the line seems to have the form '# 123 filename' | |
170 | .line and .file directives will appear in the pre-processed output */ | |
171 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
172 | first line of the input file. This is because the compiler outputs | |
173 | #NO_APP at the beginning of its output. */ | |
174 | /* Also note that C style comments are always supported. */ | |
175 | const char line_comment_chars[] = "#"; | |
176 | ||
177 | /* This array holds machine specific line separator characters. */ | |
178 | const char line_separator_chars[] = ""; | |
179 | ||
180 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
181 | const char EXP_CHARS[] = "eE"; | |
182 | ||
183 | /* Chars that mean this number is a floating point constant */ | |
184 | /* As in 0f12.456 */ | |
185 | /* or 0d1.2345e12 */ | |
186 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
187 | ||
188 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
189 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
190 | but nothing is ideal around here. | |
191 | */ | |
192 | ||
670a50eb | 193 | static char *insn_error; |
3d3c5039 ILT |
194 | |
195 | static int byte_order = BYTE_ORDER; | |
196 | ||
197 | static int auto_align = 1; | |
becfe05e ILT |
198 | |
199 | /* Symbol labelling the current insn. */ | |
200 | static symbolS *insn_label; | |
201 | ||
9226253a ILT |
202 | /* When outputting SVR4 PIC code, the assembler needs to know the |
203 | offset in the stack frame from which to restore the $gp register. | |
204 | This is set by the .cprestore pseudo-op, and saved in this | |
205 | variable. */ | |
0dd2d296 ILT |
206 | static offsetT mips_cprestore_offset = -1; |
207 | ||
208 | /* This is the register which holds the stack frame, as set by the | |
209 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
210 | static int mips_frame_reg = SP; | |
9226253a | 211 | |
becfe05e ILT |
212 | /* To output NOP instructions correctly, we need to keep information |
213 | about the previous two instructions. */ | |
214 | ||
0aa07269 ILT |
215 | /* Whether we are optimizing. The default value of 2 means to remove |
216 | unneeded NOPs and swap branch instructions when possible. A value | |
217 | of 1 means to not swap branches. A value of 0 means to always | |
218 | insert NOPs. */ | |
219 | static int mips_optimize = 2; | |
4e95866e | 220 | |
becfe05e ILT |
221 | /* The previous instruction. */ |
222 | static struct mips_cl_insn prev_insn; | |
223 | ||
224 | /* The instruction before prev_insn. */ | |
225 | static struct mips_cl_insn prev_prev_insn; | |
226 | ||
227 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
228 | point the insn_mo field at this dummy integer. */ | |
229 | static const struct mips_opcode dummy_opcode = { 0 }; | |
230 | ||
231 | /* Non-zero if prev_insn is valid. */ | |
232 | static int prev_insn_valid; | |
233 | ||
234 | /* The frag for the previous instruction. */ | |
235 | static struct frag *prev_insn_frag; | |
236 | ||
237 | /* The offset into prev_insn_frag for the previous instruction. */ | |
238 | static long prev_insn_where; | |
239 | ||
240 | /* The reloc for the previous instruction, if any. */ | |
241 | static fixS *prev_insn_fixp; | |
242 | ||
243 | /* Non-zero if the previous instruction was in a delay slot. */ | |
244 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
245 | |
246 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
247 | static int prev_insn_unreordered; | |
248 | ||
249 | /* Non-zero if the previous previous instruction was in a .set | |
250 | noreorder. */ | |
251 | static int prev_prev_insn_unreordered; | |
3d3c5039 | 252 | \f |
0dd2d296 ILT |
253 | /* Since the MIPS does not have multiple forms of PC relative |
254 | instructions, we do not have to do relaxing as is done on other | |
255 | platforms. However, we do have to handle GP relative addressing | |
256 | correctly, which turns out to be a similar problem. | |
257 | ||
258 | Every macro that refers to a symbol can occur in (at least) two | |
259 | forms, one with GP relative addressing and one without. For | |
260 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 261 | a macro instruction like this: |
0dd2d296 ILT |
262 | lw $4,i |
263 | If i can be addressed off the GP register (this is true if it is in | |
264 | the .sbss or .sdata section, or if it is known to be smaller than | |
265 | the -G argument) this will generate the following instruction: | |
266 | lw $4,i($gp) | |
267 | This instruction will use a GPREL reloc. If i can not be addressed | |
268 | off the GP register, the following instruction sequence will be used: | |
269 | lui $at,i | |
270 | lw $4,i($at) | |
271 | In this case the first instruction will have a HI16 reloc, and the | |
272 | second reloc will have a LO16 reloc. Both relocs will be against | |
273 | the symbol i. | |
274 | ||
275 | The issue here is that we may not know whether i is GP addressable | |
276 | until after we see the instruction that uses it. Therefore, we | |
277 | want to be able to choose the final instruction sequence only at | |
278 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 279 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
280 | end of assembly. |
281 | ||
282 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
283 | addressing in quite the same way, but the issue still arises as |
284 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
285 | |
286 | We handle these issues by actually generating both possible | |
287 | instruction sequences. The longer one is put in a frag_var with | |
288 | type rs_machine_dependent. We encode what to do with the frag in | |
289 | the subtype field. We encode (1) the number of existing bytes to | |
290 | replace, (2) the number of new bytes to use, (3) the offset from | |
291 | the start of the existing bytes to the first reloc we must generate | |
292 | (that is, the offset is applied from the start of the existing | |
293 | bytes after they are replaced by the new bytes, if any), (4) the | |
294 | offset from the start of the existing bytes to the second reloc, | |
295 | (5) whether a third reloc is needed (the third reloc is always four | |
296 | bytes after the second reloc), and (6) whether to warn if this | |
297 | variant is used (this is sometimes needed if .set nomacro or .set | |
298 | noat is in effect). All these numbers are reasonably small. | |
299 | ||
300 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
301 | ensure that delay slots are handled correctly. Fortunately, there |
302 | are a limited number of cases. When the second instruction | |
303 | sequence is generated, append_insn is directed to maintain the | |
304 | existing delay slot information, so it continues to apply to any | |
305 | code after the second instruction sequence. This means that the | |
306 | second instruction sequence must not impose any requirements not | |
307 | required by the first instruction sequence. | |
0dd2d296 ILT |
308 | |
309 | These variant frags are then handled in functions called by the | |
310 | machine independent code. md_estimate_size_before_relax returns | |
311 | the final size of the frag. md_convert_frag sets up the final form | |
312 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
313 | one if needed. */ | |
314 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
315 | ((relax_substateT) \ | |
316 | (((old) << 24) \ | |
317 | | ((new) << 16) \ | |
318 | | (((reloc1) + 64) << 9) \ | |
319 | | (((reloc2) + 64) << 2) \ | |
320 | | ((reloc3) ? (1 << 1) : 0) \ | |
321 | | ((warn) ? 1 : 0))) | |
322 | #define RELAX_OLD(i) (((i) >> 24) & 0xff) | |
323 | #define RELAX_NEW(i) (((i) >> 16) & 0xff) | |
324 | #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64) | |
325 | #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64) | |
326 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) | |
327 | #define RELAX_WARN(i) ((i) & 1) | |
328 | \f | |
3d3c5039 ILT |
329 | /* Prototypes for static functions. */ |
330 | ||
331 | #ifdef __STDC__ | |
332 | #define internalError() \ | |
333 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
334 | #else | |
335 | #define internalError() as_fatal ("MIPS internal Error"); | |
336 | #endif | |
337 | ||
becfe05e | 338 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
604633ae | 339 | unsigned int reg, int fpr)); |
0dd2d296 ILT |
340 | static void append_insn PARAMS ((char *place, |
341 | struct mips_cl_insn * ip, | |
670a50eb | 342 | expressionS * p, |
3d3c5039 | 343 | bfd_reloc_code_real_type r)); |
becfe05e ILT |
344 | static void mips_no_prev_insn PARAMS ((void)); |
345 | static void mips_emit_delays PARAMS ((void)); | |
0dd2d296 | 346 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
347 | const char *name, const char *fmt, |
348 | ...)); | |
0dd2d296 ILT |
349 | static void macro_build_lui PARAMS ((char *place, int *counter, |
350 | expressionS * ep, int regnum)); | |
6e8dda9c | 351 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 352 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 353 | expressionS *)); |
0dd2d296 ILT |
354 | static void load_register PARAMS ((int *counter, int reg, expressionS * ep)); |
355 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); | |
670a50eb | 356 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
357 | #ifdef LOSING_COMPILER |
358 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
359 | #endif | |
670a50eb ILT |
360 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
361 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
362 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 363 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 364 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 | 365 | static void s_align PARAMS ((int)); |
becfe05e | 366 | static void s_stringer PARAMS ((int)); |
3d3c5039 ILT |
367 | static void s_change_sec PARAMS ((int)); |
368 | static void s_cons PARAMS ((int)); | |
369 | static void s_err PARAMS ((int)); | |
370 | static void s_extern PARAMS ((int)); | |
371 | static void s_float_cons PARAMS ((int)); | |
372 | static void s_option PARAMS ((int)); | |
373 | static void s_mipsset PARAMS ((int)); | |
becfe05e | 374 | static void s_mips_space PARAMS ((int)); |
9226253a ILT |
375 | static void s_abicalls PARAMS ((int)); |
376 | static void s_cpload PARAMS ((int)); | |
377 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
378 | static void s_gpword PARAMS ((int)); |
379 | static void s_cpadd PARAMS ((int)); | |
380 | #ifndef ECOFF_DEBUGGING | |
3d3c5039 ILT |
381 | static void md_obj_begin PARAMS ((void)); |
382 | static void md_obj_end PARAMS ((void)); | |
383 | static long get_number PARAMS ((void)); | |
384 | static void s_ent PARAMS ((int)); | |
385 | static void s_mipsend PARAMS ((int)); | |
386 | static void s_file PARAMS ((int)); | |
88225433 | 387 | #if 0 |
3d3c5039 ILT |
388 | static void s_frame PARAMS ((int)); |
389 | static void s_loc PARAMS ((int)); | |
390 | static void s_mask PARAMS ((char)); | |
391 | #endif | |
88225433 | 392 | #endif |
3d3c5039 ILT |
393 | \f |
394 | /* Pseudo-op table. | |
395 | ||
396 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
397 | should be defined here, but are currently unsupported: .alias, | |
398 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
399 | ||
400 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
401 | specific to the type of debugging information being generated, and | |
402 | should be defined by the object format: .aent, .begin, .bend, | |
403 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
404 | .vreg. | |
405 | ||
406 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
407 | not MIPS CPU specific, but are also not specific to the object file | |
408 | format. This file is probably the best place to define them, but | |
409 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
410 | .struct, .weakext. */ | |
411 | ||
412 | const pseudo_typeS md_pseudo_table[] = | |
413 | { | |
670a50eb ILT |
414 | /* MIPS specific pseudo-ops. */ |
415 | {"option", s_option, 0}, | |
416 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
417 | {"rdata", s_change_sec, 'r'}, |
418 | {"sdata", s_change_sec, 's'}, | |
419 | {"livereg", s_ignore, 0}, | |
9226253a ILT |
420 | { "abicalls", s_abicalls, 0}, |
421 | { "cpload", s_cpload, 0}, | |
422 | { "cprestore", s_cprestore, 0}, | |
0dd2d296 ILT |
423 | { "gpword", s_gpword, 0}, |
424 | { "cpadd", s_cpadd, 0}, | |
3d3c5039 | 425 | |
670a50eb | 426 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 427 | chips. */ |
becfe05e | 428 | {"asciiz", s_stringer, 1}, |
670a50eb ILT |
429 | {"bss", s_change_sec, 'b'}, |
430 | {"err", s_err, 0}, | |
431 | {"half", s_cons, 1}, | |
52aa70b5 | 432 | {"dword", s_cons, 3}, |
3d3c5039 | 433 | |
670a50eb | 434 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 435 | here for one reason or another. */ |
670a50eb | 436 | {"align", s_align, 0}, |
becfe05e ILT |
437 | {"ascii", s_stringer, 0}, |
438 | {"asciz", s_stringer, 1}, | |
670a50eb ILT |
439 | {"byte", s_cons, 0}, |
440 | {"data", s_change_sec, 'd'}, | |
becfe05e | 441 | {"double", s_float_cons, 'd'}, |
670a50eb | 442 | {"extern", s_extern, 0}, |
becfe05e | 443 | {"float", s_float_cons, 'f'}, |
eb8fd0e9 ILT |
444 | {"hword", s_cons, 1}, |
445 | {"int", s_cons, 2}, | |
446 | {"long", s_cons, 2}, | |
447 | {"octa", s_cons, 4}, | |
448 | {"quad", s_cons, 3}, | |
449 | {"short", s_cons, 1}, | |
450 | {"single", s_float_cons, 'f'}, | |
becfe05e | 451 | {"space", s_mips_space, 0}, |
670a50eb ILT |
452 | {"text", s_change_sec, 't'}, |
453 | {"word", s_cons, 2}, | |
3d3c5039 | 454 | |
0dd2d296 | 455 | #ifndef ECOFF_DEBUGGING |
670a50eb | 456 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 457 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 458 | {"aent", s_ent, 1}, |
9226253a | 459 | {"bgnb", s_ignore, 0}, |
670a50eb | 460 | {"end", s_mipsend, 0}, |
9226253a | 461 | {"endb", s_ignore, 0}, |
670a50eb ILT |
462 | {"ent", s_ent, 0}, |
463 | {"file", s_file, 0}, | |
464 | {"fmask", s_ignore, 'F'}, | |
465 | {"frame", s_ignore, 0}, | |
466 | {"loc", s_ignore, 0}, | |
467 | {"mask", s_ignore, 'R'}, | |
468 | {"verstamp", s_ignore, 0}, | |
3d3c5039 ILT |
469 | #endif |
470 | ||
670a50eb ILT |
471 | /* Sentinel. */ |
472 | {NULL} | |
3d3c5039 ILT |
473 | }; |
474 | \f | |
670a50eb ILT |
475 | const relax_typeS md_relax_table[] = |
476 | { | |
918692a5 | 477 | { 0 } |
3d3c5039 ILT |
478 | }; |
479 | ||
3d3c5039 ILT |
480 | static char *expr_end; |
481 | ||
482 | static expressionS imm_expr; | |
483 | static expressionS offset_expr; | |
484 | static bfd_reloc_code_real_type imm_reloc; | |
485 | static bfd_reloc_code_real_type offset_reloc; | |
486 | ||
abdad6bc ILT |
487 | /* FIXME: This should be handled in a different way. */ |
488 | extern int target_big_endian; | |
489 | ||
3d3c5039 ILT |
490 | /* |
491 | * This function is called once, at assembler startup time. It should | |
492 | * set up all the tables, etc. that the MD part of the assembler will need. | |
493 | */ | |
494 | void | |
670a50eb | 495 | md_begin () |
3d3c5039 | 496 | { |
0dd2d296 | 497 | boolean ok = false; |
604633ae | 498 | register const char *retval = NULL; |
670a50eb | 499 | register unsigned int i = 0; |
3d3c5039 | 500 | |
8358c818 ILT |
501 | if (mips_isa == -1) |
502 | { | |
503 | if (strcmp (TARGET_CPU, "mips") == 0) | |
504 | mips_isa = 1; | |
505 | else if (strcmp (TARGET_CPU, "r6000") == 0 | |
506 | || strcmp (TARGET_CPU, "mips2") == 0) | |
507 | mips_isa = 2; | |
508 | else if (strcmp (TARGET_CPU, "mips64") == 0 | |
509 | || strcmp (TARGET_CPU, "r4000") == 0 | |
510 | || strcmp (TARGET_CPU, "mips3") == 0) | |
511 | mips_isa = 3; | |
512 | else | |
513 | mips_isa = 1; | |
514 | } | |
515 | ||
8ea7f4e8 ILT |
516 | if (mips_isa < 2 && mips_trap) |
517 | as_bad ("trap exception not supported at ISA 1"); | |
518 | ||
97f99d11 ILT |
519 | switch (mips_isa) |
520 | { | |
521 | case 1: | |
522 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
523 | break; | |
524 | case 2: | |
525 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
526 | break; | |
527 | case 3: | |
528 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
529 | break; | |
530 | } | |
531 | if (! ok) | |
532 | as_warn ("Could not set architecture and machine"); | |
533 | ||
1051c97f ILT |
534 | file_mips_isa = mips_isa; |
535 | ||
13fe1379 ILT |
536 | op_hash = hash_new (); |
537 | ||
670a50eb ILT |
538 | for (i = 0; i < NUMOPCODES;) |
539 | { | |
540 | const char *name = mips_opcodes[i].name; | |
541 | ||
604633ae | 542 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 543 | if (retval != NULL) |
670a50eb ILT |
544 | { |
545 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
546 | mips_opcodes[i].name, retval); | |
547 | as_fatal ("Broken assembler. No assembly attempted."); | |
548 | } | |
549 | do | |
550 | { | |
8358c818 ILT |
551 | if (mips_opcodes[i].pinfo != INSN_MACRO |
552 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
553 | != mips_opcodes[i].match)) | |
670a50eb ILT |
554 | { |
555 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
556 | mips_opcodes[i].name, mips_opcodes[i].args); | |
557 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 558 | } |
670a50eb ILT |
559 | ++i; |
560 | } | |
561 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
562 | } |
563 | ||
becfe05e ILT |
564 | mips_no_prev_insn (); |
565 | ||
1aa6938e ILT |
566 | mips_gprmask = 0; |
567 | mips_cprmask[0] = 0; | |
568 | mips_cprmask[1] = 0; | |
569 | mips_cprmask[2] = 0; | |
570 | mips_cprmask[3] = 0; | |
571 | ||
8358c818 ILT |
572 | /* set the default alignment for the text section (2**2) */ |
573 | record_alignment (text_section, 2); | |
574 | ||
abdad6bc ILT |
575 | /* FIXME: This should be handled in a different way. */ |
576 | target_big_endian = byte_order == BIG_ENDIAN; | |
577 | ||
88225433 | 578 | #ifdef GPOPT |
8358c818 ILT |
579 | bfd_set_gp_size (stdoutput, g_switch_value); |
580 | #endif | |
581 | ||
f2a663d3 | 582 | #ifdef OBJ_ELF |
0dd2d296 ILT |
583 | /* Sections must be aligned to 16 byte boundaries. */ |
584 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
585 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
586 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
587 | ||
588 | /* Create a .reginfo section for register masks and a .mdebug | |
589 | section for debugging information. */ | |
f2a663d3 ILT |
590 | { |
591 | segT seg; | |
592 | subsegT subseg; | |
0dd2d296 | 593 | segT sec; |
f2a663d3 ILT |
594 | |
595 | seg = now_seg; | |
596 | subseg = now_subseg; | |
0dd2d296 | 597 | sec = subseg_new (".reginfo", (subsegT) 0); |
f2a663d3 | 598 | |
04cb3372 ILT |
599 | /* The ABI says this section should be loaded so that the running |
600 | program can access it. */ | |
0dd2d296 ILT |
601 | (void) bfd_set_section_flags (stdoutput, sec, |
602 | (SEC_ALLOC | SEC_LOAD | |
603 | | SEC_READONLY | SEC_DATA)); | |
604 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
f2a663d3 ILT |
605 | |
606 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
607 | ||
0dd2d296 ILT |
608 | #ifdef ECOFF_DEBUGGING |
609 | sec = subseg_new (".mdebug", (subsegT) 0); | |
610 | (void) bfd_set_section_flags (stdoutput, sec, | |
611 | SEC_HAS_CONTENTS | SEC_READONLY); | |
612 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
613 | #endif | |
614 | ||
f2a663d3 ILT |
615 | subseg_set (seg, subseg); |
616 | } | |
617 | #endif /* OBJ_ELF */ | |
618 | ||
0dd2d296 | 619 | #ifndef ECOFF_DEBUGGING |
670a50eb | 620 | md_obj_begin (); |
3d3c5039 ILT |
621 | #endif |
622 | } | |
623 | ||
624 | void | |
13fe1379 | 625 | md_mips_end () |
3d3c5039 | 626 | { |
0dd2d296 | 627 | #ifndef ECOFF_DEBUGGING |
3d3c5039 ILT |
628 | md_obj_end (); |
629 | #endif | |
630 | } | |
631 | ||
632 | void | |
670a50eb ILT |
633 | md_assemble (str) |
634 | char *str; | |
3d3c5039 | 635 | { |
670a50eb | 636 | struct mips_cl_insn insn; |
3d3c5039 | 637 | |
5ac34ac3 ILT |
638 | imm_expr.X_op = O_absent; |
639 | offset_expr.X_op = O_absent; | |
3d3c5039 | 640 | |
670a50eb ILT |
641 | mips_ip (str, &insn); |
642 | if (insn_error) | |
643 | { | |
644 | as_bad ("%s `%s'", insn_error, str); | |
645 | return; | |
646 | } | |
647 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
648 | { | |
649 | macro (&insn); | |
3d3c5039 | 650 | } |
670a50eb ILT |
651 | else |
652 | { | |
5ac34ac3 | 653 | if (imm_expr.X_op != O_absent) |
0dd2d296 | 654 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc); |
5ac34ac3 | 655 | else if (offset_expr.X_op != O_absent) |
0dd2d296 | 656 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc); |
670a50eb | 657 | else |
0dd2d296 | 658 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED); |
3d3c5039 ILT |
659 | } |
660 | } | |
661 | ||
becfe05e ILT |
662 | /* See whether instruction IP reads register REG. If FPR is non-zero, |
663 | REG is a floating point register. */ | |
664 | ||
665 | static int | |
666 | insn_uses_reg (ip, reg, fpr) | |
667 | struct mips_cl_insn *ip; | |
604633ae | 668 | unsigned int reg; |
becfe05e ILT |
669 | int fpr; |
670 | { | |
671 | /* Don't report on general register 0, since it never changes. */ | |
672 | if (! fpr && reg == 0) | |
673 | return 0; | |
674 | ||
675 | if (fpr) | |
676 | { | |
677 | /* If we are called with either $f0 or $f1, we must check $f0. | |
678 | This is not optimal, because it will introduce an unnecessary | |
679 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
680 | need to distinguish reading both $f0 and $f1 or just one of | |
681 | them. Note that we don't have to check the other way, | |
682 | because there is no instruction that sets both $f0 and $f1 | |
683 | and requires a delay. */ | |
684 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
685 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
686 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
687 | return 1; |
688 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
689 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
690 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
691 | return 1; |
692 | } | |
693 | else | |
694 | { | |
695 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
696 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
697 | return 1; | |
698 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
699 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
700 | return 1; | |
701 | } | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
0dd2d296 ILT |
706 | /* Output an instruction. PLACE is where to put the instruction; if |
707 | it is NULL, this uses frag_more to get room. IP is the instruction | |
708 | information. ADDRESS_EXPR is an operand of the instruction to be | |
709 | used with RELOC_TYPE. */ | |
3d3c5039 | 710 | |
3d3c5039 | 711 | static void |
0dd2d296 ILT |
712 | append_insn (place, ip, address_expr, reloc_type) |
713 | char *place; | |
670a50eb ILT |
714 | struct mips_cl_insn *ip; |
715 | expressionS *address_expr; | |
716 | bfd_reloc_code_real_type reloc_type; | |
3d3c5039 | 717 | { |
1aa6938e | 718 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 719 | char *f; |
becfe05e ILT |
720 | fixS *fixp; |
721 | int nops = 0; | |
3d3c5039 | 722 | |
1aa6938e ILT |
723 | prev_pinfo = prev_insn.insn_mo->pinfo; |
724 | pinfo = ip->insn_mo->pinfo; | |
725 | ||
0dd2d296 | 726 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
727 | { |
728 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 729 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 730 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
731 | (1) a load from memory delay |
732 | (2) a load from a coprocessor delay | |
733 | (3) an unconditional branch delay | |
734 | (4) a conditional branch delay | |
735 | (5) a move to coprocessor register delay | |
736 | (6) a load coprocessor register from memory delay | |
737 | (7) a coprocessor condition code delay | |
738 | (8) a HI/LO special register delay | |
becfe05e ILT |
739 | |
740 | There are a lot of optimizations we could do that we don't. | |
741 | In particular, we do not, in general, reorder instructions. | |
742 | If you use gcc with optimization, it will reorder | |
743 | instructions and generally do much more optimization then we | |
744 | do here; repeating all that work in the assembler would only | |
745 | benefit hand written assembly code, and does not seem worth | |
746 | it. */ | |
747 | ||
748 | /* This is how a NOP is emitted. */ | |
749 | #define emit_nop() md_number_to_chars (frag_more (4), 0, 4) | |
750 | ||
751 | /* The previous insn might require a delay slot, depending upon | |
752 | the contents of the current insn. */ | |
1aa6938e | 753 | if ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
8358c818 | 754 | || (mips_isa < 2 |
1aa6938e | 755 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))) |
8358c818 ILT |
756 | { |
757 | /* A load from a coprocessor or from memory. All load | |
758 | delays delay the use of general register rt for one | |
759 | instruction on the r3000. The r6000 and r4000 use | |
760 | interlocks. */ | |
1aa6938e | 761 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
762 | if (mips_optimize == 0 |
763 | || insn_uses_reg (ip, | |
764 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
765 | & OP_MASK_RT), | |
766 | 0)) | |
becfe05e ILT |
767 | ++nops; |
768 | } | |
1aa6938e | 769 | else if ((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
8358c818 | 770 | || (mips_isa < 2 |
1aa6938e | 771 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))) |
becfe05e ILT |
772 | { |
773 | /* A generic coprocessor delay. The previous instruction | |
774 | modified a coprocessor general or control register. If | |
775 | it modified a control register, we need to avoid any | |
776 | coprocessor instruction (this is probably not always | |
777 | required, but it sometimes is). If it modified a general | |
778 | register, we avoid using that register. | |
779 | ||
8358c818 ILT |
780 | On the r6000 and r4000 loading a coprocessor register |
781 | from memory is interlocked, and does not require a delay. | |
782 | ||
becfe05e ILT |
783 | This case is not handled very well. There is no special |
784 | knowledge of CP0 handling, and the coprocessors other | |
785 | than the floating point unit are not distinguished at | |
786 | all. */ | |
1aa6938e | 787 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 788 | { |
0aa07269 ILT |
789 | if (mips_optimize == 0 |
790 | || insn_uses_reg (ip, | |
8358c818 ILT |
791 | ((prev_insn.insn_opcode >> OP_SH_FT) |
792 | & OP_MASK_FT), | |
0aa07269 | 793 | 1)) |
becfe05e ILT |
794 | ++nops; |
795 | } | |
1aa6938e | 796 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 797 | { |
0aa07269 ILT |
798 | if (mips_optimize == 0 |
799 | || insn_uses_reg (ip, | |
8358c818 ILT |
800 | ((prev_insn.insn_opcode >> OP_SH_FS) |
801 | & OP_MASK_FS), | |
0aa07269 | 802 | 1)) |
becfe05e ILT |
803 | ++nops; |
804 | } | |
805 | else | |
806 | { | |
807 | /* We don't know exactly what the previous instruction | |
808 | does. If the current instruction uses a coprocessor | |
809 | register, we must insert a NOP. If previous | |
810 | instruction may set the condition codes, and the | |
811 | current instruction uses them, we must insert two | |
812 | NOPS. */ | |
0aa07269 | 813 | if (mips_optimize == 0 |
1aa6938e ILT |
814 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
815 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 816 | nops += 2; |
1aa6938e | 817 | else if (pinfo & INSN_COP) |
becfe05e ILT |
818 | ++nops; |
819 | } | |
820 | } | |
1aa6938e | 821 | else if (prev_pinfo & INSN_WRITE_COND_CODE) |
becfe05e ILT |
822 | { |
823 | /* The previous instruction sets the coprocessor condition | |
824 | codes, but does not require a general coprocessor delay | |
825 | (this means it is a floating point comparison | |
826 | instruction). If this instruction uses the condition | |
827 | codes, we need to insert a single NOP. */ | |
0aa07269 | 828 | if (mips_optimize == 0 |
1aa6938e | 829 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
830 | ++nops; |
831 | } | |
1aa6938e | 832 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
833 | { |
834 | /* The previous instruction reads the LO register; if the | |
835 | current instruction writes to the LO register, we must | |
836 | insert two NOPS. */ | |
0aa07269 | 837 | if (mips_optimize == 0 |
1aa6938e | 838 | || (pinfo & INSN_WRITE_LO)) |
becfe05e ILT |
839 | nops += 2; |
840 | } | |
841 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
842 | { | |
843 | /* The previous instruction reads the HI register; if the | |
844 | current instruction writes to the HI register, we must | |
845 | insert a NOP. */ | |
0aa07269 | 846 | if (mips_optimize == 0 |
1aa6938e | 847 | || (pinfo & INSN_WRITE_HI)) |
becfe05e ILT |
848 | nops += 2; |
849 | } | |
850 | ||
851 | /* There are two cases which require two intervening | |
852 | instructions: 1) setting the condition codes using a move to | |
853 | coprocessor instruction which requires a general coprocessor | |
854 | delay and then reading the condition codes 2) reading the HI | |
855 | or LO register and then writing to it. If we are not already | |
856 | emitting a NOP instruction, we must check for these cases | |
857 | compared to the instruction previous to the previous | |
858 | instruction. */ | |
859 | if (nops == 0 | |
8358c818 | 860 | && (((prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 861 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
1aa6938e | 862 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e | 863 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
1aa6938e | 864 | && (pinfo & INSN_WRITE_LO)) |
becfe05e | 865 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1aa6938e | 866 | && (pinfo & INSN_WRITE_HI)))) |
becfe05e ILT |
867 | ++nops; |
868 | ||
0dd2d296 ILT |
869 | /* If we are being given a nop instruction, don't bother with |
870 | one of the nops we would otherwise output. This will only | |
871 | happen when a nop instruction is used with mips_optimize set | |
872 | to 0. */ | |
873 | if (nops > 0 && ip->insn_opcode == 0) | |
874 | --nops; | |
875 | ||
becfe05e ILT |
876 | /* Now emit the right number of NOP instructions. */ |
877 | if (nops > 0) | |
878 | { | |
879 | emit_nop (); | |
880 | if (nops > 1) | |
881 | emit_nop (); | |
af255ca0 ILT |
882 | if (listing) |
883 | listing_prev_line (); | |
becfe05e ILT |
884 | if (insn_label != NULL) |
885 | { | |
886 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
887 | insn_label->sy_frag = frag_now; | |
604633ae | 888 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e ILT |
889 | } |
890 | } | |
891 | } | |
892 | ||
0dd2d296 ILT |
893 | if (place == NULL) |
894 | f = frag_more (4); | |
895 | else | |
896 | f = place; | |
becfe05e | 897 | fixp = NULL; |
670a50eb ILT |
898 | if (address_expr != NULL) |
899 | { | |
5ac34ac3 | 900 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
901 | { |
902 | switch (reloc_type) | |
903 | { | |
3d3c5039 | 904 | case BFD_RELOC_32: |
670a50eb ILT |
905 | ip->insn_opcode |= address_expr->X_add_number; |
906 | break; | |
3d3c5039 ILT |
907 | |
908 | case BFD_RELOC_LO16: | |
670a50eb ILT |
909 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
910 | break; | |
3d3c5039 ILT |
911 | |
912 | case BFD_RELOC_MIPS_JMP: | |
913 | case BFD_RELOC_16_PCREL_S2: | |
670a50eb | 914 | goto need_reloc; |
3d3c5039 ILT |
915 | |
916 | default: | |
670a50eb | 917 | internalError (); |
3d3c5039 | 918 | } |
670a50eb ILT |
919 | } |
920 | else | |
921 | { | |
922 | assert (reloc_type != BFD_RELOC_UNUSED); | |
3d3c5039 | 923 | need_reloc: |
0dd2d296 ILT |
924 | /* Don't generate a reloc if we are writing into a variant |
925 | frag. */ | |
926 | if (place == NULL) | |
927 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
928 | address_expr, | |
929 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
930 | reloc_type); | |
3d3c5039 ILT |
931 | } |
932 | } | |
becfe05e | 933 | |
670a50eb ILT |
934 | md_number_to_chars (f, ip->insn_opcode, 4); |
935 | ||
1aa6938e ILT |
936 | /* Update the register mask information. */ |
937 | if (pinfo & INSN_WRITE_GPR_D) | |
938 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
939 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
940 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
941 | if (pinfo & INSN_READ_GPR_S) | |
942 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
943 | if (pinfo & INSN_WRITE_GPR_31) | |
944 | mips_gprmask |= 1 << 31; | |
945 | if (pinfo & INSN_WRITE_FPR_D) | |
946 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
947 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
948 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
949 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
950 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
951 | if (pinfo & INSN_COP) | |
952 | { | |
953 | /* We don't keep enough information to sort these cases out. */ | |
954 | } | |
955 | /* Never set the bit for $0, which is always zero. */ | |
956 | mips_gprmask &=~ 1 << 0; | |
957 | ||
0dd2d296 | 958 | if (place == NULL && ! mips_noreorder) |
670a50eb | 959 | { |
becfe05e ILT |
960 | /* Filling the branch delay slot is more complex. We try to |
961 | switch the branch with the previous instruction, which we can | |
962 | do if the previous instruction does not set up a condition | |
963 | that the branch tests and if the branch is not itself the | |
964 | target of any branch. */ | |
1aa6938e ILT |
965 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
966 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 967 | { |
0aa07269 | 968 | if (mips_optimize < 2 |
19ed8960 ILT |
969 | /* If we have seen .set volatile or .set nomove, don't |
970 | optimize. */ | |
971 | || mips_nomove != 0 | |
4e95866e ILT |
972 | /* If we had to emit any NOP instructions, then we |
973 | already know we can not swap. */ | |
974 | || nops != 0 | |
becfe05e ILT |
975 | /* If we don't even know the previous insn, we can not |
976 | swap. */ | |
977 | || ! prev_insn_valid | |
978 | /* If the previous insn is already in a branch delay | |
979 | slot, then we can not swap. */ | |
980 | || prev_insn_is_delay_slot | |
4e95866e ILT |
981 | /* If the previous previous insn was in a .set |
982 | noreorder, we can't swap. Actually, the MIPS | |
983 | assembler will swap in this situation. However, gcc | |
984 | configured -with-gnu-as will generate code like | |
985 | .set noreorder | |
986 | lw $4,XXX | |
987 | .set reorder | |
988 | INSN | |
989 | bne $4,$0,foo | |
990 | in which we can not swap the bne and INSN. If gcc is | |
991 | not configured -with-gnu-as, it does not output the | |
992 | .set pseudo-ops. We don't have to check | |
993 | prev_insn_unreordered, because prev_insn_valid will | |
994 | be 0 in that case. We don't want to use | |
995 | prev_prev_insn_valid, because we do want to be able | |
996 | to swap at the start of a function. */ | |
997 | || prev_prev_insn_unreordered | |
becfe05e ILT |
998 | /* If the branch is itself the target of a branch, we |
999 | can not swap. We cheat on this; all we check for is | |
1000 | whether there is a label on this instruction. If | |
1001 | there are any branches to anything other than a | |
1002 | label, users must use .set noreorder. */ | |
1003 | || insn_label != NULL | |
777ad64d ILT |
1004 | /* If the previous instruction is in a variant frag, we |
1005 | can not do the swap. */ | |
1006 | || prev_insn_frag->fr_type == rs_machine_dependent | |
becfe05e ILT |
1007 | /* If the branch reads the condition codes, we don't |
1008 | even try to swap, because in the sequence | |
1009 | ctc1 $X,$31 | |
1010 | INSN | |
1011 | INSN | |
1012 | bc1t LABEL | |
1013 | we can not swap, and I don't feel like handling that | |
1014 | case. */ | |
1aa6938e | 1015 | || (pinfo & INSN_READ_COND_CODE) |
becfe05e ILT |
1016 | /* We can not swap with an instruction that requires a |
1017 | delay slot, becase the target of the branch might | |
1018 | interfere with that instruction. */ | |
1aa6938e | 1019 | || (prev_pinfo |
8358c818 ILT |
1020 | & (INSN_LOAD_COPROC_DELAY |
1021 | | INSN_COPROC_MOVE_DELAY | |
becfe05e ILT |
1022 | | INSN_WRITE_COND_CODE |
1023 | | INSN_READ_LO | |
1024 | | INSN_READ_HI)) | |
8358c818 | 1025 | || (mips_isa < 2 |
1aa6938e | 1026 | && (prev_pinfo |
8358c818 ILT |
1027 | & (INSN_LOAD_MEMORY_DELAY |
1028 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1029 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1030 | || (prev_pinfo |
6e8dda9c ILT |
1031 | & (INSN_UNCOND_BRANCH_DELAY |
1032 | | INSN_COND_BRANCH_DELAY | |
1033 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1034 | /* We do not swap with a trap instruction, since it |
1035 | complicates trap handlers to have the trap | |
1036 | instruction be in a delay slot. */ | |
1aa6938e | 1037 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1038 | /* If the branch reads a register that the previous |
1039 | instruction sets, we can not swap. */ | |
1aa6938e | 1040 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
1041 | && insn_uses_reg (ip, |
1042 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1043 | & OP_MASK_RT), | |
1044 | 0)) | |
1aa6938e | 1045 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1046 | && insn_uses_reg (ip, |
1047 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1048 | & OP_MASK_RD), | |
1049 | 0)) | |
1849d646 ILT |
1050 | /* If the branch writes a register that the previous |
1051 | instruction sets, we can not swap (we know that | |
1052 | branches write only to RD or to $31). */ | |
1aa6938e ILT |
1053 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
1054 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1055 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1056 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1057 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1058 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1059 | & OP_MASK_RT) | |
1060 | == 31)))) | |
1aa6938e ILT |
1061 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
1062 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1063 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1064 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1065 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1066 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1067 | & OP_MASK_RD) | |
1068 | == 31)))) | |
becfe05e ILT |
1069 | /* If the branch writes a register that the previous |
1070 | instruction reads, we can not swap (we know that | |
1071 | branches only write to RD or to $31). */ | |
1aa6938e | 1072 | || ((pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1073 | && insn_uses_reg (&prev_insn, |
1074 | ((ip->insn_opcode >> OP_SH_RD) | |
1075 | & OP_MASK_RD), | |
1076 | 0)) | |
1aa6938e | 1077 | || ((pinfo & INSN_WRITE_GPR_31) |
becfe05e | 1078 | && insn_uses_reg (&prev_insn, 31, 0)) |
5b63f465 ILT |
1079 | /* If we are generating embedded PIC code, the branch |
1080 | might be expanded into a sequence which uses $at, so | |
1081 | we can't swap with an instruction which reads it. */ | |
1082 | || (mips_pic == EMBEDDED_PIC | |
1083 | && insn_uses_reg (&prev_insn, AT, 0)) | |
becfe05e ILT |
1084 | /* If the previous previous instruction has a load |
1085 | delay, and sets a register that the branch reads, we | |
1086 | can not swap. */ | |
8358c818 ILT |
1087 | || (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1088 | || (mips_isa < 2 | |
1089 | && (prev_prev_insn.insn_mo->pinfo | |
1090 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1091 | && insn_uses_reg (ip, |
1092 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1093 | & OP_MASK_RT), | |
1094 | 0))) | |
1095 | { | |
1096 | /* We could do even better for unconditional branches to | |
1097 | portions of this object file; we could pick up the | |
1098 | instruction at the destination, put it in the delay | |
1099 | slot, and bump the destination address. */ | |
1100 | emit_nop (); | |
1101 | /* Update the previous insn information. */ | |
1102 | prev_prev_insn = *ip; | |
1103 | prev_insn.insn_mo = &dummy_opcode; | |
1104 | } | |
1105 | else | |
1106 | { | |
1107 | char *prev_f; | |
1108 | char temp[4]; | |
1109 | ||
1110 | /* It looks like we can actually do the swap. */ | |
1111 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1112 | memcpy (temp, prev_f, 4); | |
1113 | memcpy (prev_f, f, 4); | |
1114 | memcpy (f, temp, 4); | |
1115 | if (prev_insn_fixp) | |
1116 | { | |
1117 | prev_insn_fixp->fx_frag = frag_now; | |
1118 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1119 | } | |
1120 | if (fixp) | |
1121 | { | |
1122 | fixp->fx_frag = prev_insn_frag; | |
1123 | fixp->fx_where = prev_insn_where; | |
1124 | } | |
1125 | /* Update the previous insn information; leave prev_insn | |
1126 | unchanged. */ | |
1127 | prev_prev_insn = *ip; | |
1128 | } | |
1129 | prev_insn_is_delay_slot = 1; | |
1130 | ||
1131 | /* If that was an unconditional branch, forget the previous | |
1132 | insn information. */ | |
1aa6938e | 1133 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1134 | { |
1135 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1136 | prev_insn.insn_mo = &dummy_opcode; | |
1137 | } | |
1138 | } | |
1aa6938e | 1139 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1140 | { |
1141 | /* We don't yet optimize a branch likely. What we should do | |
1142 | is look at the target, copy the instruction found there | |
1143 | into the delay slot, and increment the branch to jump to | |
1144 | the next instruction. */ | |
1145 | emit_nop (); | |
1146 | /* Update the previous insn information. */ | |
1147 | prev_prev_insn = *ip; | |
1148 | prev_insn.insn_mo = &dummy_opcode; | |
1149 | } | |
becfe05e | 1150 | else |
670a50eb | 1151 | { |
becfe05e ILT |
1152 | /* Update the previous insn information. */ |
1153 | if (nops > 0) | |
1154 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1155 | else | |
1156 | prev_prev_insn = prev_insn; | |
1157 | prev_insn = *ip; | |
1158 | ||
1159 | /* Any time we see a branch, we always fill the delay slot | |
1160 | immediately; since this insn is not a branch, we know it | |
1161 | is not in a delay slot. */ | |
1162 | prev_insn_is_delay_slot = 0; | |
1163 | } | |
1164 | ||
4e95866e ILT |
1165 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1166 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1167 | prev_insn_frag = frag_now; |
1168 | prev_insn_where = f - frag_now->fr_literal; | |
1169 | prev_insn_fixp = fixp; | |
1170 | prev_insn_valid = 1; | |
1171 | } | |
3d3c5039 | 1172 | |
becfe05e ILT |
1173 | /* We just output an insn, so the next one doesn't have a label. */ |
1174 | insn_label = NULL; | |
1175 | } | |
1176 | ||
1177 | /* This function forgets that there was any previous instruction or | |
1178 | label. */ | |
1179 | ||
1180 | static void | |
1181 | mips_no_prev_insn () | |
1182 | { | |
1183 | prev_insn.insn_mo = &dummy_opcode; | |
1184 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1185 | prev_insn_valid = 0; | |
1186 | prev_insn_is_delay_slot = 0; | |
4e95866e ILT |
1187 | prev_insn_unreordered = 0; |
1188 | prev_prev_insn_unreordered = 0; | |
becfe05e ILT |
1189 | insn_label = NULL; |
1190 | } | |
1191 | ||
1192 | /* This function must be called whenever we turn on noreorder or emit | |
1193 | something other than instructions. It inserts any NOPS which might | |
1194 | be needed by the previous instruction, and clears the information | |
1195 | kept for the previous instructions. */ | |
1196 | ||
1197 | static void | |
1198 | mips_emit_delays () | |
1199 | { | |
1200 | if (! mips_noreorder) | |
1201 | { | |
1202 | int nop; | |
1203 | ||
1204 | nop = 0; | |
8358c818 ILT |
1205 | if ((prev_insn.insn_mo->pinfo |
1206 | & (INSN_LOAD_COPROC_DELAY | |
1207 | | INSN_COPROC_MOVE_DELAY | |
1208 | | INSN_WRITE_COND_CODE | |
1209 | | INSN_READ_LO | |
1210 | | INSN_READ_HI)) | |
1211 | || (mips_isa < 2 | |
1212 | && (prev_insn.insn_mo->pinfo | |
1213 | & (INSN_LOAD_MEMORY_DELAY | |
1214 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1215 | { |
1216 | nop = 1; | |
1217 | if ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1218 | || (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1219 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)) | |
1220 | emit_nop (); | |
1221 | } | |
1222 | else if ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1223 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1224 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)) | |
1225 | nop = 1; | |
1226 | if (nop) | |
670a50eb | 1227 | { |
becfe05e ILT |
1228 | emit_nop (); |
1229 | if (insn_label != NULL) | |
1230 | { | |
1231 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
1232 | insn_label->sy_frag = frag_now; | |
604633ae | 1233 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e | 1234 | } |
3d3c5039 ILT |
1235 | } |
1236 | } | |
0221ddf7 ILT |
1237 | |
1238 | mips_no_prev_insn (); | |
3d3c5039 ILT |
1239 | } |
1240 | ||
670a50eb ILT |
1241 | /* Build an instruction created by a macro expansion. This is passed |
1242 | a pointer to the count of instructions created so far, an | |
1243 | expression, the name of the instruction to build, an operand format | |
1244 | string, and corresponding arguments. */ | |
1245 | ||
3d3c5039 ILT |
1246 | #ifndef NO_STDARG |
1247 | static void | |
0dd2d296 ILT |
1248 | macro_build (char *place, |
1249 | int *counter, | |
670a50eb | 1250 | expressionS * ep, |
3d3c5039 ILT |
1251 | const char *name, |
1252 | const char *fmt, | |
1253 | ...) | |
1254 | #else /* ! defined (NO_STDARG) */ | |
1255 | static void | |
0dd2d296 ILT |
1256 | macro_build (place, counter, ep, name, fmt, va_alist) |
1257 | char *place; | |
3d3c5039 ILT |
1258 | int *counter; |
1259 | expressionS *ep; | |
1260 | const char *name; | |
1261 | const char *fmt; | |
1262 | va_dcl | |
1263 | #endif /* ! defined (NO_STDARG) */ | |
1264 | { | |
670a50eb ILT |
1265 | struct mips_cl_insn insn; |
1266 | bfd_reloc_code_real_type r; | |
1267 | va_list args; | |
3d3c5039 ILT |
1268 | |
1269 | #ifndef NO_STDARG | |
670a50eb | 1270 | va_start (args, fmt); |
3d3c5039 | 1271 | #else |
670a50eb | 1272 | va_start (args); |
3d3c5039 ILT |
1273 | #endif |
1274 | ||
670a50eb ILT |
1275 | /* |
1276 | * If the macro is about to expand into a second instruction, | |
1277 | * print a warning if needed. We need to pass ip as a parameter | |
1278 | * to generate a better warning message here... | |
1279 | */ | |
0dd2d296 | 1280 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1281 | as_warn ("Macro instruction expanded into multiple instructions"); |
1282 | ||
0dd2d296 ILT |
1283 | if (place == NULL) |
1284 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1285 | |
1286 | r = BFD_RELOC_UNUSED; | |
1287 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1288 | assert (insn.insn_mo); | |
1289 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1290 | ||
9226253a ILT |
1291 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
1292 | || insn.insn_mo->pinfo == INSN_MACRO) | |
670a50eb ILT |
1293 | { |
1294 | ++insn.insn_mo; | |
1295 | assert (insn.insn_mo->name); | |
1296 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 1297 | } |
670a50eb ILT |
1298 | insn.insn_opcode = insn.insn_mo->match; |
1299 | for (;;) | |
1300 | { | |
1301 | switch (*fmt++) | |
1302 | { | |
3d3c5039 | 1303 | case '\0': |
670a50eb | 1304 | break; |
3d3c5039 ILT |
1305 | |
1306 | case ',': | |
1307 | case '(': | |
1308 | case ')': | |
670a50eb | 1309 | continue; |
3d3c5039 ILT |
1310 | |
1311 | case 't': | |
1312 | case 'w': | |
918692a5 | 1313 | case 'E': |
670a50eb ILT |
1314 | insn.insn_opcode |= va_arg (args, int) << 16; |
1315 | continue; | |
3d3c5039 ILT |
1316 | |
1317 | case 'c': | |
1318 | case 'T': | |
1319 | case 'W': | |
670a50eb ILT |
1320 | insn.insn_opcode |= va_arg (args, int) << 16; |
1321 | continue; | |
3d3c5039 ILT |
1322 | |
1323 | case 'd': | |
918692a5 | 1324 | case 'G': |
670a50eb ILT |
1325 | insn.insn_opcode |= va_arg (args, int) << 11; |
1326 | continue; | |
3d3c5039 ILT |
1327 | |
1328 | case 'V': | |
1329 | case 'S': | |
670a50eb ILT |
1330 | insn.insn_opcode |= va_arg (args, int) << 11; |
1331 | continue; | |
3d3c5039 | 1332 | |
ff3a5c18 ILT |
1333 | case 'z': |
1334 | continue; | |
1335 | ||
3d3c5039 | 1336 | case '<': |
670a50eb ILT |
1337 | insn.insn_opcode |= va_arg (args, int) << 6; |
1338 | continue; | |
3d3c5039 ILT |
1339 | |
1340 | case 'D': | |
670a50eb ILT |
1341 | insn.insn_opcode |= va_arg (args, int) << 6; |
1342 | continue; | |
3d3c5039 | 1343 | |
918692a5 ILT |
1344 | case 'B': |
1345 | insn.insn_opcode |= va_arg (args, int) << 6; | |
1346 | continue; | |
1347 | ||
3d3c5039 ILT |
1348 | case 'b': |
1349 | case 's': | |
1350 | case 'r': | |
1351 | case 'v': | |
670a50eb ILT |
1352 | insn.insn_opcode |= va_arg (args, int) << 21; |
1353 | continue; | |
3d3c5039 ILT |
1354 | |
1355 | case 'i': | |
1356 | case 'j': | |
1357 | case 'o': | |
9226253a | 1358 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
1359 | assert (r == BFD_RELOC_MIPS_GPREL |
1360 | || r == BFD_RELOC_MIPS_LITERAL | |
1361 | || r == BFD_RELOC_LO16 | |
1362 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c ILT |
1363 | || r == BFD_RELOC_MIPS_CALL16 |
1364 | || (ep->X_op == O_subtract | |
1365 | && now_seg == text_section | |
1366 | && S_GET_SEGMENT (ep->X_op_symbol) == text_section | |
1367 | && r == BFD_RELOC_PCREL_LO16)); | |
670a50eb | 1368 | continue; |
3d3c5039 | 1369 | |
6e8dda9c | 1370 | case 'u': |
ecd4ca1c ILT |
1371 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
1372 | assert (ep != NULL | |
1373 | && (ep->X_op == O_constant | |
1374 | || (ep->X_op == O_symbol | |
1375 | && (r == BFD_RELOC_HI16_S | |
1376 | || r == BFD_RELOC_HI16)) | |
1377 | || (ep->X_op == O_subtract | |
1378 | && now_seg == text_section | |
1379 | && S_GET_SEGMENT (ep->X_op_symbol) == text_section | |
1380 | && r == BFD_RELOC_PCREL_HI16_S))); | |
1381 | if (ep->X_op == O_constant) | |
1382 | { | |
1383 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
1384 | ep = NULL; | |
1385 | r = BFD_RELOC_UNUSED; | |
1386 | } | |
6e8dda9c ILT |
1387 | continue; |
1388 | ||
3d3c5039 | 1389 | case 'p': |
670a50eb ILT |
1390 | assert (ep != NULL); |
1391 | /* | |
1392 | * This allows macro() to pass an immediate expression for | |
1393 | * creating short branches without creating a symbol. | |
1394 | * Note that the expression still might come from the assembly | |
1395 | * input, in which case the value is not checked for range nor | |
1396 | * is a relocation entry generated (yuck). | |
1397 | */ | |
5ac34ac3 | 1398 | if (ep->X_op == O_constant) |
670a50eb ILT |
1399 | { |
1400 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
1401 | ep = NULL; | |
1402 | } | |
1403 | else | |
1404 | r = BFD_RELOC_16_PCREL_S2; | |
1405 | continue; | |
3d3c5039 | 1406 | |
9226253a ILT |
1407 | case 'a': |
1408 | assert (ep != NULL); | |
1409 | r = BFD_RELOC_MIPS_JMP; | |
1410 | continue; | |
1411 | ||
3d3c5039 | 1412 | default: |
670a50eb | 1413 | internalError (); |
3d3c5039 | 1414 | } |
670a50eb | 1415 | break; |
3d3c5039 | 1416 | } |
670a50eb ILT |
1417 | va_end (args); |
1418 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1419 | ||
0dd2d296 | 1420 | append_insn (place, &insn, ep, r); |
3d3c5039 ILT |
1421 | } |
1422 | ||
1423 | /* | |
1424 | * Generate a "lui" instruction. | |
1425 | */ | |
1426 | static void | |
0dd2d296 ILT |
1427 | macro_build_lui (place, counter, ep, regnum) |
1428 | char *place; | |
3d3c5039 ILT |
1429 | int *counter; |
1430 | expressionS *ep; | |
1431 | int regnum; | |
1432 | { | |
670a50eb ILT |
1433 | expressionS high_expr; |
1434 | struct mips_cl_insn insn; | |
1435 | bfd_reloc_code_real_type r; | |
1436 | CONST char *name = "lui"; | |
1437 | CONST char *fmt = "t,u"; | |
1438 | ||
0dd2d296 ILT |
1439 | if (place == NULL) |
1440 | high_expr = *ep; | |
1441 | else | |
1442 | { | |
1443 | high_expr.X_op = O_constant; | |
1444 | high_expr.X_add_number = 0; | |
1445 | } | |
670a50eb | 1446 | |
5ac34ac3 | 1447 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
1448 | { |
1449 | /* we can compute the instruction now without a relocation entry */ | |
1450 | if (high_expr.X_add_number & 0x8000) | |
1451 | high_expr.X_add_number += 0x10000; | |
1452 | high_expr.X_add_number = | |
1453 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
1454 | r = BFD_RELOC_UNUSED; | |
1455 | } | |
1456 | else | |
0dd2d296 ILT |
1457 | { |
1458 | assert (ep->X_op == O_symbol); | |
1459 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 1460 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
1461 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
1462 | r = BFD_RELOC_HI16_S; | |
1463 | } | |
670a50eb ILT |
1464 | |
1465 | /* | |
1466 | * If the macro is about to expand into a second instruction, | |
1467 | * print a warning if needed. We need to pass ip as a parameter | |
1468 | * to generate a better warning message here... | |
1469 | */ | |
0dd2d296 | 1470 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1471 | as_warn ("Macro instruction expanded into multiple instructions"); |
1472 | ||
0dd2d296 ILT |
1473 | if (place == NULL) |
1474 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1475 | |
1476 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1477 | assert (insn.insn_mo); | |
1478 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1479 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
1480 | ||
0dd2d296 | 1481 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
1482 | if (r == BFD_RELOC_UNUSED) |
1483 | { | |
1484 | insn.insn_opcode |= high_expr.X_add_number; | |
0dd2d296 | 1485 | append_insn (place, &insn, NULL, r); |
670a50eb ILT |
1486 | } |
1487 | else | |
0dd2d296 | 1488 | append_insn (place, &insn, &high_expr, r); |
3d3c5039 ILT |
1489 | } |
1490 | ||
1491 | /* set_at() | |
1492 | * Generates code to set the $at register to true (one) | |
1493 | * if reg is less than the immediate expression. | |
1494 | */ | |
1495 | static void | |
6e8dda9c | 1496 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
1497 | int *counter; |
1498 | int reg; | |
6e8dda9c | 1499 | int unsignedp; |
3d3c5039 | 1500 | { |
6e8dda9c | 1501 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 1502 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 1503 | unsignedp ? "sltiu" : "slti", |
9226253a | 1504 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 1505 | else |
670a50eb | 1506 | { |
6e8dda9c | 1507 | load_register (counter, AT, &imm_expr); |
0dd2d296 | 1508 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
1509 | unsignedp ? "sltu" : "slt", |
1510 | "d,v,t", AT, reg, AT); | |
670a50eb | 1511 | } |
3d3c5039 ILT |
1512 | } |
1513 | ||
6e8dda9c | 1514 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
1515 | |
1516 | static void | |
19ed8960 | 1517 | check_absolute_expr (ip, ex) |
3d3c5039 | 1518 | struct mips_cl_insn *ip; |
19ed8960 | 1519 | expressionS *ex; |
3d3c5039 | 1520 | { |
19ed8960 | 1521 | if (ex->X_op != O_constant) |
670a50eb | 1522 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
1523 | } |
1524 | ||
1525 | /* load_register() | |
1526 | * This routine generates the least number of instructions neccessary to load | |
1527 | * an absolute expression value into a register. | |
1528 | */ | |
1529 | static void | |
6e8dda9c | 1530 | load_register (counter, reg, ep) |
670a50eb | 1531 | int *counter; |
670a50eb ILT |
1532 | int reg; |
1533 | expressionS *ep; | |
3d3c5039 | 1534 | { |
6e8dda9c ILT |
1535 | assert (ep->X_op == O_constant); |
1536 | if (ep->X_add_number >= -0x8000 && ep->X_add_number < 0x8000) | |
0dd2d296 | 1537 | macro_build ((char *) NULL, counter, ep, |
6e8dda9c | 1538 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 1539 | "t,r,j", reg, 0, (int) BFD_RELOC_LO16); |
6e8dda9c | 1540 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) |
0dd2d296 ILT |
1541 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, |
1542 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
1543 | else if ((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
1544 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
1545 | == ~ (offsetT) 0x7fffffff)) | |
1546 | { | |
ecd4ca1c ILT |
1547 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, |
1548 | (int) BFD_RELOC_HI16); | |
6e8dda9c | 1549 | if ((ep->X_add_number & 0xffff) != 0) |
0dd2d296 | 1550 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, |
9226253a | 1551 | (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
1552 | } |
1553 | else if (mips_isa < 3) | |
670a50eb | 1554 | { |
6e8dda9c | 1555 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 1556 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 1557 | (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
1558 | } |
1559 | else | |
1560 | { | |
1561 | int shift; | |
1562 | expressionS hi32, lo32; | |
1563 | ||
1564 | hi32 = *ep; | |
1565 | shift = 32; | |
1566 | hi32.X_add_number >>= shift; | |
1567 | hi32.X_add_number &= 0xffffffff; | |
1568 | if ((hi32.X_add_number & 0x80000000) != 0) | |
1569 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
1570 | load_register (counter, reg, &hi32); | |
1571 | lo32 = *ep; | |
1572 | lo32.X_add_number &= 0xffffffff; | |
1573 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
0dd2d296 ILT |
1574 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, |
1575 | reg, 0); | |
6e8dda9c ILT |
1576 | else |
1577 | { | |
1578 | expressionS mid16; | |
670a50eb | 1579 | |
0dd2d296 ILT |
1580 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
1581 | reg, 16); | |
6e8dda9c ILT |
1582 | mid16 = lo32; |
1583 | mid16.X_add_number >>= 16; | |
0dd2d296 ILT |
1584 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, |
1585 | reg, (int) BFD_RELOC_LO16); | |
1586 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
1587 | reg, 16); | |
6e8dda9c ILT |
1588 | } |
1589 | if ((lo32.X_add_number & 0xffff) != 0) | |
0dd2d296 | 1590 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, reg, |
9226253a | 1591 | (int) BFD_RELOC_LO16); |
670a50eb | 1592 | } |
3d3c5039 ILT |
1593 | } |
1594 | ||
0dd2d296 ILT |
1595 | /* Load an address into a register. */ |
1596 | ||
1597 | static void | |
1598 | load_address (counter, reg, ep) | |
1599 | int *counter; | |
1600 | int reg; | |
1601 | expressionS *ep; | |
1602 | { | |
1603 | char *p; | |
1604 | ||
1605 | if (ep->X_op != O_constant | |
1606 | && ep->X_op != O_symbol) | |
1607 | { | |
1608 | as_bad ("expression too complex"); | |
1609 | ep->X_op = O_constant; | |
1610 | } | |
1611 | ||
1612 | if (ep->X_op == O_constant) | |
d9aba805 ILT |
1613 | { |
1614 | load_register (counter, reg, ep); | |
1615 | return; | |
1616 | } | |
1617 | ||
1618 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
1619 | { |
1620 | /* If this is a reference to a GP relative symbol, we want | |
1621 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
1622 | Otherwise we want | |
04cb3372 | 1623 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
1624 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
1625 | If we have an addend, we always use the latter form. */ | |
1626 | if (ep->X_add_number != 0) | |
1627 | p = NULL; | |
1628 | else | |
1629 | { | |
8ea7f4e8 | 1630 | frag_grow (20); |
0dd2d296 ILT |
1631 | macro_build ((char *) NULL, counter, ep, |
1632 | mips_isa < 3 ? "addiu" : "daddiu", | |
1633 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
1634 | p = frag_var (rs_machine_dependent, 8, 0, | |
1635 | RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros), | |
1636 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
1637 | } | |
1638 | macro_build_lui (p, counter, ep, reg); | |
1639 | if (p != NULL) | |
1640 | p += 4; | |
1641 | macro_build (p, counter, ep, | |
1642 | mips_isa < 3 ? "addiu" : "daddiu", | |
1643 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1644 | } | |
d9aba805 | 1645 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
1646 | { |
1647 | expressionS ex; | |
1648 | ||
1649 | /* If this is a reference to an external symbol, we want | |
1650 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1651 | Otherwise we want | |
1652 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1653 | nop | |
1654 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 1655 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
1656 | ex.X_add_number = ep->X_add_number; |
1657 | ep->X_add_number = 0; | |
8ea7f4e8 | 1658 | frag_grow (20); |
0dd2d296 ILT |
1659 | macro_build ((char *) NULL, counter, ep, |
1660 | mips_isa < 3 ? "lw" : "ld", | |
1661 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
1662 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
1663 | p = frag_var (rs_machine_dependent, 4, 0, | |
1664 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
1665 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
1666 | macro_build (p, counter, ep, | |
1667 | mips_isa < 3 ? "addiu" : "daddiu", | |
1668 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1669 | if (ex.X_add_number != 0) | |
1670 | { | |
1671 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
1672 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
1673 | ex.X_op = O_constant; | |
1674 | macro_build (p, counter, &ex, | |
1675 | mips_isa < 3 ? "addiu" : "daddiu", | |
1676 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1677 | } | |
d9aba805 ILT |
1678 | } |
1679 | else if (mips_pic == EMBEDDED_PIC) | |
1680 | { | |
1681 | /* We always do | |
1682 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
1683 | */ | |
1684 | macro_build ((char *) NULL, counter, ep, | |
1685 | mips_isa < 3 ? "addiu" : "daddiu", | |
1686 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
1687 | } | |
1688 | else | |
1689 | abort (); | |
0dd2d296 ILT |
1690 | } |
1691 | ||
3d3c5039 ILT |
1692 | /* |
1693 | * Build macros | |
1694 | * This routine implements the seemingly endless macro or synthesized | |
1695 | * instructions and addressing modes in the mips assembly language. Many | |
1696 | * of these macros are simple and are similar to each other. These could | |
1697 | * probably be handled by some kind of table or grammer aproach instead of | |
1698 | * this verbose method. Others are not simple macros but are more like | |
1699 | * optimizing code generation. | |
1700 | * One interesting optimization is when several store macros appear | |
1701 | * consecutivly that would load AT with the upper half of the same address. | |
1702 | * The ensuing load upper instructions are ommited. This implies some kind | |
1703 | * of global optimization. We currently only optimize within a single macro. | |
1704 | * For many of the load and store macros if the address is specified as a | |
1705 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
1706 | * first load register 'at' with zero and use it as the base register. The | |
1707 | * mips assembler simply uses register $zero. Just one tiny optimization | |
1708 | * we're missing. | |
1709 | */ | |
1710 | static void | |
1711 | macro (ip) | |
1712 | struct mips_cl_insn *ip; | |
1713 | { | |
670a50eb ILT |
1714 | register int treg, sreg, dreg, breg; |
1715 | int tempreg; | |
1716 | int mask; | |
1717 | int icnt = 0; | |
1718 | int used_at; | |
670a50eb ILT |
1719 | expressionS expr1; |
1720 | const char *s; | |
8358c818 | 1721 | const char *s2; |
670a50eb | 1722 | const char *fmt; |
8358c818 ILT |
1723 | int likely = 0; |
1724 | int dbl = 0; | |
1725 | int coproc = 0; | |
6e8dda9c | 1726 | offsetT maxnum; |
9226253a | 1727 | bfd_reloc_code_real_type r; |
0dd2d296 | 1728 | char *p; |
670a50eb ILT |
1729 | |
1730 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
1731 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
1732 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
1733 | mask = ip->insn_mo->mask; | |
1734 | ||
5ac34ac3 ILT |
1735 | expr1.X_op = O_constant; |
1736 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
1737 | expr1.X_add_symbol = NULL; |
1738 | expr1.X_add_number = 1; | |
1739 | ||
1740 | switch (mask) | |
1741 | { | |
6e8dda9c ILT |
1742 | case M_DABS: |
1743 | dbl = 1; | |
3d3c5039 | 1744 | case M_ABS: |
6e8dda9c ILT |
1745 | /* bgez $a0,.+12 |
1746 | move v0,$a0 | |
1747 | sub v0,$zero,$a0 | |
1748 | */ | |
3d3c5039 | 1749 | |
becfe05e ILT |
1750 | mips_emit_delays (); |
1751 | ++mips_noreorder; | |
0dd2d296 | 1752 | mips_any_noreorder = 1; |
3d3c5039 | 1753 | |
670a50eb | 1754 | expr1.X_add_number = 8; |
0dd2d296 | 1755 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 1756 | if (dreg == sreg) |
0dd2d296 | 1757 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 1758 | else |
0dd2d296 ILT |
1759 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
1760 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
1761 | dbl ? "dsub" : "sub", |
1762 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 1763 | |
becfe05e | 1764 | --mips_noreorder; |
670a50eb | 1765 | return; |
3d3c5039 ILT |
1766 | |
1767 | case M_ADD_I: | |
8358c818 ILT |
1768 | s = "addi"; |
1769 | s2 = "add"; | |
1770 | goto do_addi; | |
3d3c5039 | 1771 | case M_ADDU_I: |
8358c818 ILT |
1772 | s = "addiu"; |
1773 | s2 = "addu"; | |
1774 | goto do_addi; | |
1775 | case M_DADD_I: | |
6e8dda9c | 1776 | dbl = 1; |
8358c818 ILT |
1777 | s = "daddi"; |
1778 | s2 = "dadd"; | |
1779 | goto do_addi; | |
1780 | case M_DADDU_I: | |
6e8dda9c | 1781 | dbl = 1; |
8358c818 ILT |
1782 | s = "daddiu"; |
1783 | s2 = "daddu"; | |
1784 | do_addi: | |
6e8dda9c | 1785 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 1786 | { |
0dd2d296 | 1787 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 1788 | (int) BFD_RELOC_LO16); |
670a50eb | 1789 | return; |
3d3c5039 | 1790 | } |
6e8dda9c | 1791 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 1792 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 1793 | break; |
3d3c5039 ILT |
1794 | |
1795 | case M_AND_I: | |
6e8dda9c ILT |
1796 | s = "andi"; |
1797 | s2 = "and"; | |
1798 | goto do_bit; | |
3d3c5039 | 1799 | case M_OR_I: |
6e8dda9c ILT |
1800 | s = "ori"; |
1801 | s2 = "or"; | |
1802 | goto do_bit; | |
3d3c5039 | 1803 | case M_NOR_I: |
6e8dda9c ILT |
1804 | s = ""; |
1805 | s2 = "nor"; | |
1806 | goto do_bit; | |
3d3c5039 | 1807 | case M_XOR_I: |
6e8dda9c ILT |
1808 | s = "xori"; |
1809 | s2 = "xor"; | |
1810 | do_bit: | |
1811 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 1812 | { |
6e8dda9c | 1813 | if (mask != M_NOR_I) |
0dd2d296 ILT |
1814 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
1815 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 1816 | else |
670a50eb | 1817 | { |
0dd2d296 ILT |
1818 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
1819 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 1820 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 1821 | treg, treg, 0); |
3d3c5039 | 1822 | } |
6e8dda9c | 1823 | return; |
3d3c5039 | 1824 | } |
6e8dda9c ILT |
1825 | |
1826 | load_register (&icnt, AT, &imm_expr); | |
0dd2d296 | 1827 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 1828 | break; |
3d3c5039 ILT |
1829 | |
1830 | case M_BEQ_I: | |
8358c818 ILT |
1831 | s = "beq"; |
1832 | goto beq_i; | |
1833 | case M_BEQL_I: | |
1834 | s = "beql"; | |
1835 | likely = 1; | |
1836 | goto beq_i; | |
3d3c5039 | 1837 | case M_BNE_I: |
8358c818 ILT |
1838 | s = "bne"; |
1839 | goto beq_i; | |
1840 | case M_BNEL_I: | |
1841 | s = "bnel"; | |
1842 | likely = 1; | |
1843 | beq_i: | |
670a50eb ILT |
1844 | if (imm_expr.X_add_number == 0) |
1845 | { | |
0dd2d296 ILT |
1846 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
1847 | 0); | |
670a50eb ILT |
1848 | return; |
1849 | } | |
6e8dda9c | 1850 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 1851 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 1852 | break; |
3d3c5039 | 1853 | |
8358c818 ILT |
1854 | case M_BGEL: |
1855 | likely = 1; | |
3d3c5039 | 1856 | case M_BGE: |
670a50eb ILT |
1857 | if (treg == 0) |
1858 | { | |
0dd2d296 | 1859 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1860 | likely ? "bgezl" : "bgez", |
1861 | "s,p", sreg); | |
670a50eb | 1862 | return; |
3d3c5039 | 1863 | } |
9a7d824a ILT |
1864 | if (sreg == 0) |
1865 | { | |
0dd2d296 | 1866 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1867 | likely ? "blezl" : "blez", |
1868 | "s,p", treg); | |
9a7d824a ILT |
1869 | return; |
1870 | } | |
0dd2d296 ILT |
1871 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
1872 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
1873 | likely ? "beql" : "beq", |
1874 | "s,t,p", AT, 0); | |
670a50eb | 1875 | break; |
3d3c5039 | 1876 | |
8358c818 ILT |
1877 | case M_BGTL_I: |
1878 | likely = 1; | |
3d3c5039 | 1879 | case M_BGT_I: |
9a7d824a | 1880 | /* check for > max integer */ |
6e8dda9c ILT |
1881 | maxnum = 0x7fffffff; |
1882 | if (mips_isa >= 3) | |
1883 | { | |
1884 | maxnum <<= 16; | |
1885 | maxnum |= 0xffff; | |
1886 | maxnum <<= 16; | |
1887 | maxnum |= 0xffff; | |
1888 | } | |
1889 | if (imm_expr.X_add_number >= maxnum) | |
9a7d824a ILT |
1890 | { |
1891 | do_false: | |
1892 | /* result is always false */ | |
8358c818 ILT |
1893 | if (! likely) |
1894 | { | |
1895 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 1896 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
1897 | } |
1898 | else | |
1899 | { | |
1900 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
1901 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
1902 | "s,t,p", 0, 0); | |
8358c818 | 1903 | } |
9a7d824a ILT |
1904 | return; |
1905 | } | |
670a50eb ILT |
1906 | imm_expr.X_add_number++; |
1907 | /* FALLTHROUGH */ | |
3d3c5039 | 1908 | case M_BGE_I: |
8358c818 ILT |
1909 | case M_BGEL_I: |
1910 | if (mask == M_BGEL_I) | |
1911 | likely = 1; | |
670a50eb ILT |
1912 | if (imm_expr.X_add_number == 0) |
1913 | { | |
0dd2d296 | 1914 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1915 | likely ? "bgezl" : "bgez", |
1916 | "s,p", sreg); | |
670a50eb | 1917 | return; |
3d3c5039 | 1918 | } |
670a50eb ILT |
1919 | if (imm_expr.X_add_number == 1) |
1920 | { | |
0dd2d296 | 1921 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1922 | likely ? "bgtzl" : "bgtz", |
1923 | "s,p", sreg); | |
670a50eb | 1924 | return; |
3d3c5039 | 1925 | } |
6e8dda9c ILT |
1926 | maxnum = 0x7fffffff; |
1927 | if (mips_isa >= 3) | |
1928 | { | |
1929 | maxnum <<= 16; | |
1930 | maxnum |= 0xffff; | |
1931 | maxnum <<= 16; | |
1932 | maxnum |= 0xffff; | |
1933 | } | |
1934 | maxnum = - maxnum - 1; | |
1935 | if (imm_expr.X_add_number <= maxnum) | |
9a7d824a ILT |
1936 | { |
1937 | do_true: | |
1938 | /* result is always true */ | |
1939 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 1940 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
1941 | return; |
1942 | } | |
6e8dda9c | 1943 | set_at (&icnt, sreg, 0); |
0dd2d296 | 1944 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1945 | likely ? "beql" : "beq", |
1946 | "s,t,p", AT, 0); | |
670a50eb | 1947 | break; |
3d3c5039 | 1948 | |
8358c818 ILT |
1949 | case M_BGEUL: |
1950 | likely = 1; | |
3d3c5039 | 1951 | case M_BGEU: |
670a50eb | 1952 | if (treg == 0) |
9a7d824a ILT |
1953 | goto do_true; |
1954 | if (sreg == 0) | |
670a50eb | 1955 | { |
0dd2d296 | 1956 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1957 | likely ? "beql" : "beq", |
1958 | "s,t,p", 0, treg); | |
670a50eb | 1959 | return; |
3d3c5039 | 1960 | } |
0dd2d296 ILT |
1961 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
1962 | treg); | |
1963 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
1964 | likely ? "beql" : "beq", |
1965 | "s,t,p", AT, 0); | |
670a50eb | 1966 | break; |
3d3c5039 | 1967 | |
8358c818 ILT |
1968 | case M_BGTUL_I: |
1969 | likely = 1; | |
9a7d824a | 1970 | case M_BGTU_I: |
6e8dda9c | 1971 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
1972 | goto do_false; |
1973 | imm_expr.X_add_number++; | |
1974 | /* FALLTHROUGH */ | |
3d3c5039 | 1975 | case M_BGEU_I: |
8358c818 ILT |
1976 | case M_BGEUL_I: |
1977 | if (mask == M_BGEUL_I) | |
1978 | likely = 1; | |
670a50eb | 1979 | if (imm_expr.X_add_number == 0) |
9a7d824a | 1980 | goto do_true; |
670a50eb ILT |
1981 | if (imm_expr.X_add_number == 1) |
1982 | { | |
0dd2d296 | 1983 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1984 | likely ? "bnel" : "bne", |
1985 | "s,t,p", sreg, 0); | |
670a50eb | 1986 | return; |
3d3c5039 | 1987 | } |
6e8dda9c | 1988 | set_at (&icnt, sreg, 1); |
0dd2d296 | 1989 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1990 | likely ? "beql" : "beq", |
1991 | "s,t,p", AT, 0); | |
670a50eb | 1992 | break; |
3d3c5039 | 1993 | |
8358c818 ILT |
1994 | case M_BGTL: |
1995 | likely = 1; | |
3d3c5039 | 1996 | case M_BGT: |
670a50eb ILT |
1997 | if (treg == 0) |
1998 | { | |
0dd2d296 | 1999 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2000 | likely ? "bgtzl" : "bgtz", |
2001 | "s,p", sreg); | |
670a50eb | 2002 | return; |
3d3c5039 | 2003 | } |
9a7d824a ILT |
2004 | if (sreg == 0) |
2005 | { | |
0dd2d296 | 2006 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2007 | likely ? "bltzl" : "bltz", |
2008 | "s,p", treg); | |
9a7d824a ILT |
2009 | return; |
2010 | } | |
0dd2d296 ILT |
2011 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2012 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2013 | likely ? "bnel" : "bne", |
2014 | "s,t,p", AT, 0); | |
670a50eb | 2015 | break; |
3d3c5039 | 2016 | |
8358c818 ILT |
2017 | case M_BGTUL: |
2018 | likely = 1; | |
3d3c5039 | 2019 | case M_BGTU: |
670a50eb ILT |
2020 | if (treg == 0) |
2021 | { | |
0dd2d296 | 2022 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2023 | likely ? "bnel" : "bne", |
2024 | "s,t,p", sreg, 0); | |
670a50eb | 2025 | return; |
3d3c5039 | 2026 | } |
9a7d824a ILT |
2027 | if (sreg == 0) |
2028 | goto do_false; | |
0dd2d296 ILT |
2029 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2030 | sreg); | |
2031 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2032 | likely ? "bnel" : "bne", |
2033 | "s,t,p", AT, 0); | |
670a50eb | 2034 | break; |
3d3c5039 | 2035 | |
8358c818 ILT |
2036 | case M_BLEL: |
2037 | likely = 1; | |
3d3c5039 | 2038 | case M_BLE: |
670a50eb ILT |
2039 | if (treg == 0) |
2040 | { | |
0dd2d296 | 2041 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2042 | likely ? "blezl" : "blez", |
2043 | "s,p", sreg); | |
670a50eb ILT |
2044 | return; |
2045 | } | |
9a7d824a ILT |
2046 | if (sreg == 0) |
2047 | { | |
0dd2d296 | 2048 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2049 | likely ? "bgezl" : "bgez", |
2050 | "s,p", treg); | |
9a7d824a ILT |
2051 | return; |
2052 | } | |
0dd2d296 ILT |
2053 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2054 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2055 | likely ? "beql" : "beq", |
2056 | "s,t,p", AT, 0); | |
670a50eb | 2057 | break; |
3d3c5039 | 2058 | |
8358c818 ILT |
2059 | case M_BLEL_I: |
2060 | likely = 1; | |
3d3c5039 | 2061 | case M_BLE_I: |
6e8dda9c ILT |
2062 | maxnum = 0x7fffffff; |
2063 | if (mips_isa >= 3) | |
2064 | { | |
2065 | maxnum <<= 16; | |
2066 | maxnum |= 0xffff; | |
2067 | maxnum <<= 16; | |
2068 | maxnum |= 0xffff; | |
2069 | } | |
2070 | if (imm_expr.X_add_number >= maxnum) | |
9a7d824a ILT |
2071 | goto do_true; |
2072 | imm_expr.X_add_number++; | |
2073 | /* FALLTHROUGH */ | |
9a7d824a | 2074 | case M_BLT_I: |
8358c818 ILT |
2075 | case M_BLTL_I: |
2076 | if (mask == M_BLTL_I) | |
2077 | likely = 1; | |
670a50eb ILT |
2078 | if (imm_expr.X_add_number == 0) |
2079 | { | |
0dd2d296 | 2080 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2081 | likely ? "bltzl" : "bltz", |
2082 | "s,p", sreg); | |
670a50eb ILT |
2083 | return; |
2084 | } | |
9a7d824a | 2085 | if (imm_expr.X_add_number == 1) |
670a50eb | 2086 | { |
0dd2d296 | 2087 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2088 | likely ? "blezl" : "blez", |
2089 | "s,p", sreg); | |
670a50eb ILT |
2090 | return; |
2091 | } | |
6e8dda9c | 2092 | set_at (&icnt, sreg, 0); |
0dd2d296 | 2093 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2094 | likely ? "bnel" : "bne", |
2095 | "s,t,p", AT, 0); | |
670a50eb | 2096 | break; |
3d3c5039 | 2097 | |
8358c818 ILT |
2098 | case M_BLEUL: |
2099 | likely = 1; | |
3d3c5039 | 2100 | case M_BLEU: |
670a50eb ILT |
2101 | if (treg == 0) |
2102 | { | |
0dd2d296 | 2103 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2104 | likely ? "beql" : "beq", |
2105 | "s,t,p", sreg, 0); | |
670a50eb | 2106 | return; |
3d3c5039 | 2107 | } |
9a7d824a ILT |
2108 | if (sreg == 0) |
2109 | goto do_true; | |
0dd2d296 ILT |
2110 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2111 | sreg); | |
2112 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2113 | likely ? "beql" : "beq", |
2114 | "s,t,p", AT, 0); | |
670a50eb | 2115 | break; |
3d3c5039 | 2116 | |
8358c818 ILT |
2117 | case M_BLEUL_I: |
2118 | likely = 1; | |
3d3c5039 | 2119 | case M_BLEU_I: |
6e8dda9c | 2120 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
2121 | goto do_true; |
2122 | imm_expr.X_add_number++; | |
2123 | /* FALLTHROUGH */ | |
9a7d824a | 2124 | case M_BLTU_I: |
8358c818 ILT |
2125 | case M_BLTUL_I: |
2126 | if (mask == M_BLTUL_I) | |
2127 | likely = 1; | |
670a50eb | 2128 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
2129 | goto do_false; |
2130 | if (imm_expr.X_add_number == 1) | |
670a50eb | 2131 | { |
0dd2d296 | 2132 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2133 | likely ? "beql" : "beq", |
2134 | "s,t,p", sreg, 0); | |
670a50eb | 2135 | return; |
3d3c5039 | 2136 | } |
6e8dda9c | 2137 | set_at (&icnt, sreg, 1); |
0dd2d296 | 2138 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2139 | likely ? "bnel" : "bne", |
2140 | "s,t,p", AT, 0); | |
670a50eb | 2141 | break; |
3d3c5039 | 2142 | |
8358c818 ILT |
2143 | case M_BLTL: |
2144 | likely = 1; | |
3d3c5039 | 2145 | case M_BLT: |
670a50eb ILT |
2146 | if (treg == 0) |
2147 | { | |
0dd2d296 | 2148 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2149 | likely ? "bltzl" : "bltz", |
2150 | "s,p", sreg); | |
670a50eb | 2151 | return; |
3d3c5039 | 2152 | } |
9a7d824a | 2153 | if (sreg == 0) |
670a50eb | 2154 | { |
0dd2d296 | 2155 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2156 | likely ? "bgtzl" : "bgtz", |
2157 | "s,p", treg); | |
670a50eb | 2158 | return; |
3d3c5039 | 2159 | } |
0dd2d296 ILT |
2160 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
2161 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2162 | likely ? "bnel" : "bne", |
2163 | "s,t,p", AT, 0); | |
670a50eb | 2164 | break; |
3d3c5039 | 2165 | |
8358c818 ILT |
2166 | case M_BLTUL: |
2167 | likely = 1; | |
3d3c5039 | 2168 | case M_BLTU: |
670a50eb | 2169 | if (treg == 0) |
9a7d824a ILT |
2170 | goto do_false; |
2171 | if (sreg == 0) | |
670a50eb | 2172 | { |
0dd2d296 | 2173 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2174 | likely ? "bnel" : "bne", |
2175 | "s,t,p", 0, treg); | |
670a50eb ILT |
2176 | return; |
2177 | } | |
0dd2d296 ILT |
2178 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
2179 | treg); | |
2180 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2181 | likely ? "bnel" : "bne", |
2182 | "s,t,p", AT, 0); | |
670a50eb | 2183 | break; |
3d3c5039 | 2184 | |
8358c818 ILT |
2185 | case M_DDIV_3: |
2186 | dbl = 1; | |
3d3c5039 | 2187 | case M_DIV_3: |
8358c818 ILT |
2188 | s = "mflo"; |
2189 | goto do_div3; | |
2190 | case M_DREM_3: | |
2191 | dbl = 1; | |
3d3c5039 | 2192 | case M_REM_3: |
8358c818 ILT |
2193 | s = "mfhi"; |
2194 | do_div3: | |
670a50eb ILT |
2195 | if (treg == 0) |
2196 | { | |
2197 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2198 | if (mips_trap) |
2199 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2200 | else | |
2201 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2202 | return; |
2203 | } | |
2204 | ||
becfe05e ILT |
2205 | mips_emit_delays (); |
2206 | ++mips_noreorder; | |
0dd2d296 ILT |
2207 | mips_any_noreorder = 1; |
2208 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 2209 | dbl ? "ddiv" : "div", |
ff3a5c18 | 2210 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
2211 | if (mips_trap) |
2212 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2213 | else | |
2214 | { | |
2215 | expr1.X_add_number = 8; | |
2216 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2217 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2218 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2219 | } | |
670a50eb | 2220 | expr1.X_add_number = -1; |
0dd2d296 | 2221 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 2222 | dbl ? "daddiu" : "addiu", |
9226253a | 2223 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 2224 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 2225 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
2226 | if (dbl) |
2227 | { | |
2228 | expr1.X_add_number = 1; | |
0dd2d296 | 2229 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 2230 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
2231 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
2232 | 31); | |
8358c818 ILT |
2233 | } |
2234 | else | |
2235 | { | |
2236 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
2237 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
2238 | (int) BFD_RELOC_HI16); | |
8358c818 | 2239 | } |
8ea7f4e8 ILT |
2240 | if (mips_trap) |
2241 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
2242 | else | |
2243 | { | |
2244 | expr1.X_add_number = 8; | |
2245 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2246 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2247 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
2248 | } | |
becfe05e | 2249 | --mips_noreorder; |
0dd2d296 | 2250 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 2251 | break; |
3d3c5039 ILT |
2252 | |
2253 | case M_DIV_3I: | |
8358c818 ILT |
2254 | s = "div"; |
2255 | s2 = "mflo"; | |
2256 | goto do_divi; | |
3d3c5039 | 2257 | case M_DIVU_3I: |
8358c818 ILT |
2258 | s = "divu"; |
2259 | s2 = "mflo"; | |
2260 | goto do_divi; | |
3d3c5039 | 2261 | case M_REM_3I: |
8358c818 ILT |
2262 | s = "div"; |
2263 | s2 = "mfhi"; | |
2264 | goto do_divi; | |
3d3c5039 | 2265 | case M_REMU_3I: |
8358c818 ILT |
2266 | s = "divu"; |
2267 | s2 = "mfhi"; | |
2268 | goto do_divi; | |
2269 | case M_DDIV_3I: | |
2270 | dbl = 1; | |
2271 | s = "ddiv"; | |
2272 | s2 = "mflo"; | |
2273 | goto do_divi; | |
2274 | case M_DDIVU_3I: | |
2275 | dbl = 1; | |
2276 | s = "ddivu"; | |
2277 | s2 = "mflo"; | |
2278 | goto do_divi; | |
2279 | case M_DREM_3I: | |
2280 | dbl = 1; | |
2281 | s = "ddiv"; | |
2282 | s2 = "mfhi"; | |
2283 | goto do_divi; | |
2284 | case M_DREMU_3I: | |
2285 | dbl = 1; | |
2286 | s = "ddivu"; | |
2287 | s2 = "mfhi"; | |
2288 | do_divi: | |
670a50eb ILT |
2289 | if (imm_expr.X_add_number == 0) |
2290 | { | |
2291 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2292 | if (mips_trap) |
2293 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2294 | else | |
2295 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2296 | return; |
2297 | } | |
2298 | if (imm_expr.X_add_number == 1) | |
2299 | { | |
8358c818 | 2300 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
2301 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
2302 | sreg); | |
3d3c5039 | 2303 | else |
0dd2d296 | 2304 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
2305 | return; |
2306 | } | |
8358c818 ILT |
2307 | if (imm_expr.X_add_number == -1 |
2308 | && s[strlen (s) - 1] != 'u') | |
2309 | { | |
2310 | if (strcmp (s2, "mflo") == 0) | |
2311 | { | |
2312 | if (dbl) | |
0dd2d296 ILT |
2313 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
2314 | sreg); | |
8358c818 | 2315 | else |
0dd2d296 ILT |
2316 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
2317 | sreg); | |
8358c818 ILT |
2318 | } |
2319 | else | |
0dd2d296 | 2320 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
2321 | return; |
2322 | } | |
3d3c5039 | 2323 | |
6e8dda9c | 2324 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 ILT |
2325 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
2326 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
2327 | break; |
2328 | ||
2329 | case M_DIVU_3: | |
8358c818 ILT |
2330 | s = "divu"; |
2331 | s2 = "mflo"; | |
2332 | goto do_divu3; | |
670a50eb | 2333 | case M_REMU_3: |
8358c818 ILT |
2334 | s = "divu"; |
2335 | s2 = "mfhi"; | |
2336 | goto do_divu3; | |
2337 | case M_DDIVU_3: | |
2338 | s = "ddivu"; | |
2339 | s2 = "mflo"; | |
2340 | goto do_divu3; | |
2341 | case M_DREMU_3: | |
2342 | s = "ddivu"; | |
2343 | s2 = "mfhi"; | |
2344 | do_divu3: | |
becfe05e ILT |
2345 | mips_emit_delays (); |
2346 | ++mips_noreorder; | |
0dd2d296 ILT |
2347 | mips_any_noreorder = 1; |
2348 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
2349 | if (mips_trap) |
2350 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2351 | else | |
2352 | { | |
2353 | expr1.X_add_number = 8; | |
2354 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2355 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2356 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2357 | } | |
becfe05e | 2358 | --mips_noreorder; |
0dd2d296 | 2359 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 2360 | return; |
3d3c5039 | 2361 | |
0dd2d296 | 2362 | case M_LA_AB: |
d9aba805 ILT |
2363 | /* Load the address of a symbol into a register. If breg is not |
2364 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
2365 | |
2366 | /* When generating embedded PIC code, we permit expressions of | |
2367 | the form | |
2368 | la $4,foo-bar | |
2369 | where bar is an address in the .text section. These are used | |
2370 | when getting the addresses of functions. We don't permit | |
2371 | X_add_number to be non-zero, because if the symbol is | |
2372 | external the relaxing code needs to know that any addend is | |
2373 | purely the offset to X_op_symbol. */ | |
2374 | if (mips_pic == EMBEDDED_PIC | |
2375 | && offset_expr.X_op == O_subtract | |
2376 | && now_seg == text_section | |
2377 | && S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
2378 | && breg == 0 | |
2379 | && offset_expr.X_add_number == 0) | |
2380 | { | |
2381 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
2382 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
2383 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2384 | mips_isa < 3 ? "addiu" : "daddiu", | |
2385 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
2386 | return; | |
2387 | } | |
2388 | ||
0dd2d296 ILT |
2389 | if (offset_expr.X_op != O_symbol |
2390 | && offset_expr.X_op != O_constant) | |
670a50eb | 2391 | { |
0dd2d296 ILT |
2392 | as_bad ("expression too complex"); |
2393 | offset_expr.X_op = O_constant; | |
2394 | } | |
2395 | ||
2396 | if (treg == breg) | |
2397 | { | |
2398 | tempreg = AT; | |
2399 | used_at = 1; | |
3d3c5039 | 2400 | } |
670a50eb ILT |
2401 | else |
2402 | { | |
0dd2d296 ILT |
2403 | tempreg = treg; |
2404 | used_at = 0; | |
670a50eb | 2405 | } |
3d3c5039 | 2406 | |
5ac34ac3 | 2407 | if (offset_expr.X_op == O_constant) |
6e8dda9c | 2408 | load_register (&icnt, tempreg, &offset_expr); |
d9aba805 | 2409 | else if (mips_pic == NO_PIC) |
670a50eb | 2410 | { |
0dd2d296 ILT |
2411 | /* If this is a reference to an GP relative symbol, we want |
2412 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2413 | Otherwise we want | |
2414 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
2415 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2416 | If we have a constant, we need two instructions anyhow, | |
2417 | so we may as well always use the latter form. */ | |
2418 | if (offset_expr.X_add_number != 0) | |
2419 | p = NULL; | |
2420 | else | |
2421 | { | |
8ea7f4e8 | 2422 | frag_grow (20); |
0dd2d296 ILT |
2423 | macro_build ((char *) NULL, &icnt, &offset_expr, |
2424 | mips_isa < 3 ? "addiu" : "daddiu", | |
2425 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2426 | p = frag_var (rs_machine_dependent, 8, 0, | |
2427 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
2428 | mips_warn_about_macros), | |
2429 | offset_expr.X_add_symbol, (long) 0, | |
2430 | (char *) NULL); | |
2431 | } | |
2432 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2433 | if (p != NULL) | |
2434 | p += 4; | |
2435 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 2436 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
2437 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
2438 | } | |
d9aba805 | 2439 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
2440 | { |
2441 | /* If this is a reference to an external symbol, and there | |
2442 | is no constant, we want | |
2443 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2444 | For a local symbol, we want | |
2445 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2446 | nop | |
2447 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2448 | ||
2449 | If we have a small constant, and this is a reference to | |
2450 | an external symbol, we want | |
2451 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2452 | nop | |
2453 | addiu $tempreg,$tempreg,<constant> | |
2454 | For a local symbol, we want the same instruction | |
2455 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
2456 | addiu instruction. | |
2457 | ||
2458 | If we have a large constant, and this is a reference to | |
2459 | an external symbol, we want | |
2460 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2461 | lui $at,<hiconstant> | |
2462 | addiu $at,$at,<loconstant> | |
2463 | addu $tempreg,$tempreg,$at | |
2464 | For a local symbol, we want the same instruction | |
2465 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
2466 | addiu instruction. */ | |
2467 | expr1.X_add_number = offset_expr.X_add_number; | |
2468 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 2469 | frag_grow (32); |
0dd2d296 ILT |
2470 | macro_build ((char *) NULL, &icnt, &offset_expr, |
2471 | mips_isa < 3 ? "lw" : "ld", | |
2472 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2473 | if (expr1.X_add_number == 0) | |
2474 | { | |
2475 | int off; | |
2476 | ||
2477 | if (breg == 0) | |
2478 | off = 0; | |
2479 | else | |
2480 | { | |
2481 | /* We're going to put in an addu instruction using | |
2482 | tempreg, so we may as well insert the nop right | |
2483 | now. */ | |
2484 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2485 | "nop", ""); | |
2486 | off = 4; | |
2487 | } | |
2488 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
2489 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
2490 | (breg == 0 | |
2491 | ? mips_warn_about_macros | |
2492 | : 0)), | |
2493 | offset_expr.X_add_symbol, (long) 0, | |
2494 | (char *) NULL); | |
2495 | if (breg == 0) | |
2496 | { | |
2497 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
2498 | p += 4; | |
2499 | } | |
2500 | macro_build (p, &icnt, &expr1, | |
2501 | mips_isa < 3 ? "addiu" : "daddiu", | |
2502 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
2503 | /* FIXME: If breg == 0, and the next instruction uses | |
2504 | $tempreg, then if this variant case is used an extra | |
2505 | nop will be generated. */ | |
2506 | } | |
2507 | else if (expr1.X_add_number >= -0x8000 | |
2508 | && expr1.X_add_number < 0x8000) | |
2509 | { | |
2510 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2511 | "nop", ""); | |
2512 | macro_build ((char *) NULL, &icnt, &expr1, | |
2513 | mips_isa < 3 ? "addiu" : "daddiu", | |
2514 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
2515 | (void) frag_var (rs_machine_dependent, 0, 0, | |
2516 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
2517 | offset_expr.X_add_symbol, (long) 0, | |
2518 | (char *) NULL); | |
2519 | } | |
2520 | else | |
2521 | { | |
2522 | int off1; | |
2523 | ||
2524 | /* If we are going to add in a base register, and the | |
2525 | target register and the base register are the same, | |
2526 | then we are using AT as a temporary register. Since | |
2527 | we want to load the constant into AT, we add our | |
2528 | current AT (from the global offset table) and the | |
2529 | register into the register now, and pretend we were | |
2530 | not using a base register. */ | |
2531 | if (breg != treg) | |
2532 | off1 = 0; | |
2533 | else | |
2534 | { | |
2535 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2536 | "nop", ""); | |
2537 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2538 | mips_isa < 3 ? "addu" : "daddu", | |
2539 | "d,v,t", treg, AT, breg); | |
2540 | breg = 0; | |
2541 | tempreg = treg; | |
2542 | off1 = -8; | |
2543 | } | |
2544 | ||
2545 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
2546 | macro_build ((char *) NULL, &icnt, &expr1, | |
2547 | mips_isa < 3 ? "addiu" : "daddiu", | |
2548 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
2549 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2550 | mips_isa < 3 ? "addu" : "daddu", | |
2551 | "d,v,t", tempreg, tempreg, AT); | |
2552 | (void) frag_var (rs_machine_dependent, 0, 0, | |
2553 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
2554 | offset_expr.X_add_symbol, (long) 0, | |
2555 | (char *) NULL); | |
2556 | used_at = 1; | |
2557 | } | |
670a50eb | 2558 | } |
d9aba805 ILT |
2559 | else if (mips_pic == EMBEDDED_PIC) |
2560 | { | |
2561 | /* We use | |
2562 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2563 | */ | |
2564 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2565 | mips_isa < 3 ? "addiu" : "daddiu", | |
2566 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2567 | } | |
2568 | else | |
2569 | abort (); | |
0dd2d296 | 2570 | |
670a50eb | 2571 | if (breg != 0) |
0dd2d296 ILT |
2572 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
2573 | mips_isa < 3 ? "addu" : "daddu", | |
2574 | "d,v,t", treg, tempreg, breg); | |
2575 | ||
2576 | if (! used_at) | |
2577 | return; | |
2578 | ||
2579 | break; | |
2580 | ||
2581 | case M_J_A: | |
2582 | /* The j instruction may not be used in PIC code, since it | |
2583 | requires an absolute address. We convert it to a b | |
2584 | instruction. */ | |
d9aba805 | 2585 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
2586 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
2587 | else | |
2588 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 2589 | return; |
3d3c5039 | 2590 | |
9226253a ILT |
2591 | /* The jal instructions must be handled as macros because when |
2592 | generating PIC code they expand to multi-instruction | |
2593 | sequences. Normally they are simple instructions. */ | |
2594 | case M_JAL_1: | |
2595 | dreg = RA; | |
2596 | /* Fall through. */ | |
2597 | case M_JAL_2: | |
d9aba805 ILT |
2598 | if (mips_pic == NO_PIC |
2599 | || mips_pic == EMBEDDED_PIC) | |
2600 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
2601 | "d,s", dreg, sreg); | |
2602 | else if (mips_pic == SVR4_PIC) | |
9226253a | 2603 | { |
d9aba805 ILT |
2604 | if (sreg != PIC_CALL_REG) |
2605 | as_warn ("MIPS PIC call to register other than $25"); | |
2606 | ||
0dd2d296 ILT |
2607 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
2608 | "d,s", dreg, sreg); | |
d9aba805 ILT |
2609 | if (mips_cprestore_offset < 0) |
2610 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
2611 | else | |
2612 | { | |
2613 | expr1.X_add_number = mips_cprestore_offset; | |
2614 | macro_build ((char *) NULL, &icnt, &expr1, | |
2615 | mips_isa < 3 ? "lw" : "ld", | |
2616 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
2617 | } | |
9226253a | 2618 | } |
0dd2d296 | 2619 | else |
d9aba805 ILT |
2620 | abort (); |
2621 | ||
9226253a ILT |
2622 | return; |
2623 | ||
2624 | case M_JAL_A: | |
d9aba805 ILT |
2625 | if (mips_pic == NO_PIC) |
2626 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
2627 | else if (mips_pic == SVR4_PIC) | |
9226253a | 2628 | { |
d9aba805 ILT |
2629 | /* If this is a reference to an external symbol, we want |
2630 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
2631 | nop | |
2632 | jalr $25 | |
2633 | nop | |
2634 | lw $gp,cprestore($sp) | |
2635 | The cprestore value is set using the .cprestore | |
2636 | pseudo-op. If the symbol is not external, we want | |
2637 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2638 | nop | |
2639 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
2640 | jalr $25 | |
2641 | nop | |
2642 | lw $gp,cprestore($sp) | |
2643 | */ | |
2644 | frag_grow (20); | |
2645 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
0dd2d296 | 2646 | mips_isa < 3 ? "lw" : "ld", |
d9aba805 ILT |
2647 | "t,o(b)", PIC_CALL_REG, |
2648 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
2649 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
2650 | p = frag_var (rs_machine_dependent, 4, 0, | |
2651 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
2652 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
2653 | macro_build (p, &icnt, &offset_expr, | |
2654 | mips_isa < 3 ? "addiu" : "daddiu", | |
2655 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
2656 | (int) BFD_RELOC_LO16); | |
2657 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2658 | "jalr", "s", PIC_CALL_REG); | |
2659 | if (mips_cprestore_offset < 0) | |
2660 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
2661 | else | |
2662 | { | |
2663 | if (mips_noreorder) | |
2664 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2665 | "nop", ""); | |
2666 | expr1.X_add_number = mips_cprestore_offset; | |
2667 | macro_build ((char *) NULL, &icnt, &expr1, | |
2668 | mips_isa < 3 ? "lw" : "ld", | |
2669 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
2670 | mips_frame_reg); | |
2671 | } | |
0dd2d296 | 2672 | } |
d9aba805 | 2673 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
2674 | { |
2675 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
2676 | /* The linker may expand the call to a longer sequence which | |
2677 | uses $at, so we must break rather than return. */ | |
2678 | break; | |
2679 | } | |
d9aba805 ILT |
2680 | else |
2681 | abort (); | |
2682 | ||
9226253a ILT |
2683 | return; |
2684 | ||
3d3c5039 | 2685 | case M_LB_AB: |
670a50eb ILT |
2686 | s = "lb"; |
2687 | goto ld; | |
3d3c5039 | 2688 | case M_LBU_AB: |
670a50eb ILT |
2689 | s = "lbu"; |
2690 | goto ld; | |
3d3c5039 | 2691 | case M_LH_AB: |
670a50eb ILT |
2692 | s = "lh"; |
2693 | goto ld; | |
3d3c5039 | 2694 | case M_LHU_AB: |
670a50eb ILT |
2695 | s = "lhu"; |
2696 | goto ld; | |
3d3c5039 | 2697 | case M_LW_AB: |
670a50eb ILT |
2698 | s = "lw"; |
2699 | goto ld; | |
3d3c5039 | 2700 | case M_LWC0_AB: |
670a50eb | 2701 | s = "lwc0"; |
8358c818 | 2702 | coproc = 1; |
670a50eb | 2703 | goto ld; |
3d3c5039 | 2704 | case M_LWC1_AB: |
670a50eb | 2705 | s = "lwc1"; |
8358c818 | 2706 | coproc = 1; |
670a50eb | 2707 | goto ld; |
3d3c5039 | 2708 | case M_LWC2_AB: |
670a50eb | 2709 | s = "lwc2"; |
8358c818 | 2710 | coproc = 1; |
670a50eb | 2711 | goto ld; |
3d3c5039 | 2712 | case M_LWC3_AB: |
670a50eb | 2713 | s = "lwc3"; |
8358c818 | 2714 | coproc = 1; |
670a50eb | 2715 | goto ld; |
3d3c5039 | 2716 | case M_LWL_AB: |
670a50eb ILT |
2717 | s = "lwl"; |
2718 | goto ld; | |
3d3c5039 | 2719 | case M_LWR_AB: |
670a50eb | 2720 | s = "lwr"; |
8358c818 ILT |
2721 | goto ld; |
2722 | case M_LDC1_AB: | |
2723 | s = "ldc1"; | |
2724 | coproc = 1; | |
2725 | goto ld; | |
2726 | case M_LDC2_AB: | |
2727 | s = "ldc2"; | |
2728 | coproc = 1; | |
2729 | goto ld; | |
2730 | case M_LDC3_AB: | |
2731 | s = "ldc3"; | |
2732 | coproc = 1; | |
2733 | goto ld; | |
2734 | case M_LDL_AB: | |
2735 | s = "ldl"; | |
2736 | goto ld; | |
2737 | case M_LDR_AB: | |
2738 | s = "ldr"; | |
2739 | goto ld; | |
2740 | case M_LL_AB: | |
2741 | s = "ll"; | |
2742 | goto ld; | |
2743 | case M_LLD_AB: | |
2744 | s = "lld"; | |
2745 | goto ld; | |
2746 | case M_LWU_AB: | |
2747 | s = "lwu"; | |
3d3c5039 | 2748 | ld: |
8358c818 | 2749 | if (breg == treg || coproc) |
670a50eb ILT |
2750 | { |
2751 | tempreg = AT; | |
2752 | used_at = 1; | |
2753 | } | |
2754 | else | |
2755 | { | |
2756 | tempreg = treg; | |
2757 | used_at = 0; | |
2758 | } | |
2759 | goto ld_st; | |
3d3c5039 | 2760 | case M_SB_AB: |
670a50eb ILT |
2761 | s = "sb"; |
2762 | goto st; | |
3d3c5039 | 2763 | case M_SH_AB: |
670a50eb ILT |
2764 | s = "sh"; |
2765 | goto st; | |
3d3c5039 | 2766 | case M_SW_AB: |
670a50eb ILT |
2767 | s = "sw"; |
2768 | goto st; | |
3d3c5039 | 2769 | case M_SWC0_AB: |
670a50eb | 2770 | s = "swc0"; |
8358c818 | 2771 | coproc = 1; |
670a50eb | 2772 | goto st; |
3d3c5039 | 2773 | case M_SWC1_AB: |
670a50eb | 2774 | s = "swc1"; |
8358c818 | 2775 | coproc = 1; |
670a50eb | 2776 | goto st; |
3d3c5039 | 2777 | case M_SWC2_AB: |
670a50eb | 2778 | s = "swc2"; |
8358c818 | 2779 | coproc = 1; |
670a50eb | 2780 | goto st; |
3d3c5039 | 2781 | case M_SWC3_AB: |
670a50eb | 2782 | s = "swc3"; |
8358c818 | 2783 | coproc = 1; |
670a50eb | 2784 | goto st; |
3d3c5039 | 2785 | case M_SWL_AB: |
670a50eb ILT |
2786 | s = "swl"; |
2787 | goto st; | |
3d3c5039 | 2788 | case M_SWR_AB: |
670a50eb | 2789 | s = "swr"; |
8358c818 ILT |
2790 | goto st; |
2791 | case M_SC_AB: | |
2792 | s = "sc"; | |
2793 | goto st; | |
2794 | case M_SCD_AB: | |
2795 | s = "scd"; | |
2796 | goto st; | |
2797 | case M_SDC1_AB: | |
2798 | s = "sdc1"; | |
2799 | coproc = 1; | |
2800 | goto st; | |
2801 | case M_SDC2_AB: | |
2802 | s = "sdc2"; | |
2803 | coproc = 1; | |
2804 | goto st; | |
2805 | case M_SDC3_AB: | |
2806 | s = "sdc3"; | |
2807 | coproc = 1; | |
2808 | goto st; | |
2809 | case M_SDL_AB: | |
2810 | s = "sdl"; | |
2811 | goto st; | |
2812 | case M_SDR_AB: | |
2813 | s = "sdr"; | |
3d3c5039 | 2814 | st: |
670a50eb ILT |
2815 | tempreg = AT; |
2816 | used_at = 1; | |
3d3c5039 | 2817 | ld_st: |
8358c818 ILT |
2818 | if (mask == M_LWC1_AB |
2819 | || mask == M_SWC1_AB | |
8358c818 | 2820 | || mask == M_LDC1_AB |
0dd2d296 ILT |
2821 | || mask == M_SDC1_AB |
2822 | || mask == M_L_DAB | |
2823 | || mask == M_S_DAB) | |
670a50eb | 2824 | fmt = "T,o(b)"; |
8358c818 | 2825 | else if (coproc) |
19ed8960 | 2826 | fmt = "E,o(b)"; |
670a50eb ILT |
2827 | else |
2828 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
2829 | |
2830 | if (offset_expr.X_op != O_constant | |
2831 | && offset_expr.X_op != O_symbol) | |
2832 | { | |
2833 | as_bad ("expression too complex"); | |
2834 | offset_expr.X_op = O_constant; | |
2835 | } | |
2836 | ||
2837 | /* A constant expression in PIC code can be handled just as it | |
2838 | is in non PIC code. */ | |
d9aba805 | 2839 | if (mips_pic == NO_PIC |
0dd2d296 | 2840 | || offset_expr.X_op == O_constant) |
670a50eb | 2841 | { |
0dd2d296 ILT |
2842 | /* If this is a reference to a GP relative symbol, and there |
2843 | is no base register, we want | |
2844 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 2845 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
2846 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
2847 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
2848 | If we have a constant, we need two instructions anyhow, | |
2849 | so we always use the latter form. | |
2850 | ||
2851 | If we have a base register, and this is a reference to a | |
2852 | GP relative symbol, we want | |
2853 | addu $tempreg,$breg,$gp | |
2854 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
2855 | Otherwise we want | |
2856 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
2857 | addu $tempreg,$tempreg,$breg | |
2858 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
2859 | With a constant we always use the latter case. */ | |
670a50eb ILT |
2860 | if (breg == 0) |
2861 | { | |
0dd2d296 ILT |
2862 | if (offset_expr.X_add_number != 0) |
2863 | p = NULL; | |
2864 | else | |
2865 | { | |
8ea7f4e8 | 2866 | frag_grow (20); |
0dd2d296 ILT |
2867 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
2868 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
2869 | p = frag_var (rs_machine_dependent, 8, 0, | |
2870 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
2871 | (mips_warn_about_macros |
2872 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
2873 | offset_expr.X_add_symbol, (long) 0, |
2874 | (char *) NULL); | |
8197b589 | 2875 | used_at = 0; |
0dd2d296 ILT |
2876 | } |
2877 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2878 | if (p != NULL) | |
2879 | p += 4; | |
2880 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
2881 | (int) BFD_RELOC_LO16, tempreg); | |
2882 | } | |
2883 | else | |
2884 | { | |
2885 | if (offset_expr.X_add_number != 0) | |
2886 | p = NULL; | |
2887 | else | |
2888 | { | |
8ea7f4e8 | 2889 | frag_grow (28); |
0dd2d296 ILT |
2890 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
2891 | mips_isa < 3 ? "addu" : "daddu", | |
2892 | "d,v,t", tempreg, breg, GP); | |
2893 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
2894 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
2895 | p = frag_var (rs_machine_dependent, 12, 0, | |
2896 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
2897 | offset_expr.X_add_symbol, (long) 0, | |
2898 | (char *) NULL); | |
2899 | } | |
2900 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2901 | if (p != NULL) | |
2902 | p += 4; | |
2903 | macro_build (p, &icnt, (expressionS *) NULL, | |
2904 | mips_isa < 3 ? "addu" : "daddu", | |
2905 | "d,v,t", tempreg, tempreg, breg); | |
2906 | if (p != NULL) | |
2907 | p += 4; | |
2908 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
2909 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 2910 | } |
670a50eb | 2911 | } |
d9aba805 | 2912 | else if (mips_pic == SVR4_PIC) |
670a50eb | 2913 | { |
0dd2d296 ILT |
2914 | /* If this is a reference to an external symbol, we want |
2915 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2916 | nop | |
2917 | <op> $treg,0($tempreg) | |
2918 | Otherwise we want | |
2919 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2920 | nop | |
2921 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2922 | <op> $treg,0($tempreg) | |
2923 | If there is a base register, we add it to $tempreg before | |
2924 | the <op>. If there is a constant, we stick it in the | |
2925 | <op> instruction. We don't handle constants larger than | |
2926 | 16 bits, because we have no way to load the upper 16 bits | |
2927 | (actually, we could handle them for the subset of cases | |
2928 | in which we are not using $at). */ | |
2929 | assert (offset_expr.X_op == O_symbol); | |
2930 | expr1.X_add_number = offset_expr.X_add_number; | |
2931 | offset_expr.X_add_number = 0; | |
2932 | if (expr1.X_add_number < -0x8000 | |
2933 | || expr1.X_add_number >= 0x8000) | |
2934 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 2935 | frag_grow (20); |
0dd2d296 ILT |
2936 | macro_build ((char *) NULL, &icnt, &offset_expr, |
2937 | mips_isa < 3 ? "lw" : "ld", | |
2938 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2939 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
2940 | p = frag_var (rs_machine_dependent, 4, 0, | |
2941 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
2942 | offset_expr.X_add_symbol, (long) 0, | |
2943 | (char *) NULL); | |
2944 | macro_build (p, &icnt, &offset_expr, | |
2945 | mips_isa < 3 ? "addiu" : "daddiu", | |
2946 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 2947 | if (breg != 0) |
0dd2d296 | 2948 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
2949 | mips_isa < 3 ? "addu" : "daddu", |
2950 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
2951 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
2952 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 2953 | } |
d9aba805 ILT |
2954 | else if (mips_pic == EMBEDDED_PIC) |
2955 | { | |
2956 | /* If there is no base register, we want | |
2957 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
2958 | If there is a base register, we want | |
2959 | addu $tempreg,$breg,$gp | |
2960 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
2961 | */ | |
2962 | assert (offset_expr.X_op == O_symbol); | |
2963 | if (breg == 0) | |
2964 | { | |
2965 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
2966 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
2967 | used_at = 0; | |
2968 | } | |
2969 | else | |
2970 | { | |
2971 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2972 | mips_isa < 3 ? "addu" : "daddu", | |
2973 | "d,v,t", tempreg, breg, GP); | |
2974 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
2975 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
2976 | } | |
2977 | } | |
2978 | else | |
2979 | abort (); | |
0dd2d296 ILT |
2980 | |
2981 | if (! used_at) | |
2982 | return; | |
2983 | ||
2984 | break; | |
3d3c5039 ILT |
2985 | |
2986 | case M_LI: | |
19ed8960 | 2987 | case M_LI_S: |
6e8dda9c | 2988 | load_register (&icnt, treg, &imm_expr); |
670a50eb | 2989 | return; |
3d3c5039 | 2990 | |
0dd2d296 | 2991 | case M_LI_SS: |
d9aba805 | 2992 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
2993 | { |
2994 | assert (offset_expr.X_op == O_symbol | |
2995 | && strcmp (segment_name (S_GET_SEGMENT | |
2996 | (offset_expr.X_add_symbol)), | |
2997 | ".lit4") == 0 | |
2998 | && offset_expr.X_add_number == 0); | |
2999 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
3000 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 | 3001 | return; |
0dd2d296 | 3002 | } |
d9aba805 ILT |
3003 | else if (mips_pic == SVR4_PIC |
3004 | || mips_pic == EMBEDDED_PIC) | |
0dd2d296 ILT |
3005 | { |
3006 | assert (imm_expr.X_op == O_constant); | |
d2c71068 ILT |
3007 | load_register (&icnt, AT, &imm_expr); |
3008 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3009 | "mtc1", "t,G", AT, treg); | |
3010 | break; | |
0dd2d296 | 3011 | } |
d9aba805 | 3012 | else |
d2c71068 ILT |
3013 | { |
3014 | abort (); | |
3015 | return; | |
3016 | } | |
0dd2d296 | 3017 | |
3d3c5039 | 3018 | case M_LI_D: |
d9aba805 ILT |
3019 | /* We know that sym is in the .rdata section. First we get the |
3020 | upper 16 bits of the address. */ | |
3021 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3022 | { |
3023 | /* FIXME: This won't work for a 64 bit address. */ | |
3024 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
3025 | } | |
d9aba805 | 3026 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
3027 | { |
3028 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3029 | mips_isa < 3 ? "lw" : "ld", | |
3030 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3031 | } | |
d9aba805 ILT |
3032 | else if (mips_pic == EMBEDDED_PIC) |
3033 | { | |
3034 | /* For embedded PIC we pick up the entire address off $gp in | |
3035 | a single instruction. */ | |
3036 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3037 | mips_isa < 3 ? "addiu" : "daddiu", | |
3038 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3039 | offset_expr.X_op = O_constant; | |
3040 | offset_expr.X_add_number = 0; | |
3041 | } | |
3042 | else | |
3043 | abort (); | |
3044 | ||
0dd2d296 | 3045 | /* Now we load the register(s). */ |
8358c818 | 3046 | if (mips_isa >= 3) |
0dd2d296 ILT |
3047 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
3048 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
3049 | else |
3050 | { | |
0dd2d296 ILT |
3051 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
3052 | treg, (int) BFD_RELOC_LO16, AT); | |
3053 | if (treg != 31) | |
3054 | { | |
3055 | /* FIXME: How in the world do we deal with the possible | |
3056 | overflow here? */ | |
3057 | offset_expr.X_add_number += 4; | |
3058 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
3059 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
3060 | } | |
8358c818 | 3061 | } |
d2c71068 ILT |
3062 | |
3063 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
3064 | does not become a variant frag. */ | |
3065 | frag_wane (frag_now); | |
3066 | frag_new (0); | |
3067 | ||
670a50eb | 3068 | break; |
3d3c5039 ILT |
3069 | |
3070 | case M_LI_DD: | |
d9aba805 ILT |
3071 | if (mips_pic == NO_PIC |
3072 | || mips_pic == EMBEDDED_PIC) | |
8358c818 | 3073 | { |
0dd2d296 ILT |
3074 | /* Load a floating point number from the .lit8 section. */ |
3075 | assert (offset_expr.X_op == O_symbol | |
3076 | && strcmp (segment_name (S_GET_SEGMENT | |
3077 | (offset_expr.X_add_symbol)), | |
3078 | ".lit8") == 0 | |
3079 | && offset_expr.X_add_number == 0); | |
3080 | if (mips_isa >= 2) | |
3081 | { | |
3082 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
3083 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
3084 | return; | |
3085 | } | |
3086 | breg = GP; | |
3087 | r = BFD_RELOC_MIPS_LITERAL; | |
3088 | goto dob; | |
3089 | } | |
d9aba805 | 3090 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
3091 | { |
3092 | /* Load the double from the .rdata section. */ | |
3093 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3094 | mips_isa < 3 ? "lw" : "ld", | |
3095 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3096 | if (mips_isa >= 2) | |
3097 | { | |
3098 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
3099 | "T,o(b)", treg, (int) BFD_RELOC_LO16, GP); | |
3100 | break; | |
3101 | } | |
3102 | breg = AT; | |
3103 | r = BFD_RELOC_LO16; | |
3104 | goto dob; | |
8358c818 | 3105 | } |
d9aba805 ILT |
3106 | else |
3107 | abort (); | |
9226253a | 3108 | |
3d3c5039 | 3109 | case M_L_DOB: |
9a7d824a ILT |
3110 | /* Even on a big endian machine $fn comes before $fn+1. We have |
3111 | to adjust when loading from memory. */ | |
9226253a ILT |
3112 | r = BFD_RELOC_LO16; |
3113 | dob: | |
8358c818 | 3114 | assert (mips_isa < 2); |
0dd2d296 | 3115 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 3116 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 3117 | (int) r, breg); |
0dd2d296 ILT |
3118 | /* FIXME: A possible overflow which I don't know how to deal |
3119 | with. */ | |
670a50eb | 3120 | offset_expr.X_add_number += 4; |
0dd2d296 | 3121 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 3122 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 3123 | (int) r, breg); |
d2c71068 ILT |
3124 | |
3125 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
3126 | does not become a variant frag. */ | |
3127 | frag_wane (frag_now); | |
3128 | frag_new (0); | |
3129 | ||
0dd2d296 ILT |
3130 | if (breg != AT) |
3131 | return; | |
3132 | break; | |
3d3c5039 ILT |
3133 | |
3134 | case M_L_DAB: | |
670a50eb ILT |
3135 | /* |
3136 | * The MIPS assembler seems to check for X_add_number not | |
3137 | * being double aligned and generating: | |
3138 | * lui at,%hi(foo+1) | |
3139 | * addu at,at,v1 | |
3140 | * addiu at,at,%lo(foo+1) | |
3141 | * lwc1 f2,0(at) | |
3142 | * lwc1 f3,4(at) | |
3143 | * But, the resulting address is the same after relocation so why | |
3144 | * generate the extra instruction? | |
3145 | */ | |
4032d3f0 | 3146 | coproc = 1; |
0dd2d296 | 3147 | if (mips_isa >= 2) |
670a50eb | 3148 | { |
0dd2d296 ILT |
3149 | s = "ldc1"; |
3150 | goto ld; | |
670a50eb | 3151 | } |
0dd2d296 ILT |
3152 | |
3153 | s = "lwc1"; | |
3154 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
3155 | goto ldd_std; |
3156 | ||
3157 | case M_S_DAB: | |
8358c818 | 3158 | if (mips_isa >= 2) |
8358c818 | 3159 | { |
0dd2d296 ILT |
3160 | s = "sdc1"; |
3161 | goto st; | |
8358c818 | 3162 | } |
3d3c5039 | 3163 | |
0dd2d296 ILT |
3164 | s = "swc1"; |
3165 | fmt = "T,o(b)"; | |
3166 | coproc = 1; | |
3167 | goto ldd_std; | |
3d3c5039 ILT |
3168 | |
3169 | case M_LD_AB: | |
0dd2d296 | 3170 | if (mips_isa >= 3) |
670a50eb | 3171 | { |
0dd2d296 ILT |
3172 | s = "ld"; |
3173 | goto ld; | |
670a50eb | 3174 | } |
0dd2d296 ILT |
3175 | |
3176 | s = "lw"; | |
3177 | fmt = "t,o(b)"; | |
3178 | goto ldd_std; | |
3179 | ||
3180 | case M_SD_AB: | |
3181 | if (mips_isa >= 3) | |
670a50eb | 3182 | { |
0dd2d296 ILT |
3183 | s = "sd"; |
3184 | goto st; | |
670a50eb | 3185 | } |
0dd2d296 | 3186 | |
670a50eb | 3187 | s = "sw"; |
0dd2d296 ILT |
3188 | fmt = "t,o(b)"; |
3189 | ||
3190 | ldd_std: | |
3191 | if (offset_expr.X_op != O_symbol | |
3192 | && offset_expr.X_op != O_constant) | |
670a50eb | 3193 | { |
0dd2d296 ILT |
3194 | as_bad ("expression too complex"); |
3195 | offset_expr.X_op = O_constant; | |
3196 | } | |
3197 | ||
3198 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
3199 | to adjust when loading from memory. We set coproc if we must | |
3200 | load $fn+1 first. */ | |
3201 | if (byte_order == LITTLE_ENDIAN) | |
3202 | coproc = 0; | |
3203 | ||
d9aba805 | 3204 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
3205 | || offset_expr.X_op == O_constant) |
3206 | { | |
3207 | /* If this is a reference to a GP relative symbol, we want | |
3208 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3209 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
3210 | If we have a base register, we use this | |
3211 | addu $at,$breg,$gp | |
3212 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
3213 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
3214 | If this is not a GP relative symbol, we want | |
3215 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3216 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
3217 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
3218 | If there is a base register, we add it to $at after the | |
3219 | lui instruction. If there is a constant, we always use | |
3220 | the last case. */ | |
3221 | if (offset_expr.X_add_number != 0) | |
670a50eb | 3222 | { |
0dd2d296 ILT |
3223 | p = NULL; |
3224 | used_at = 1; | |
670a50eb ILT |
3225 | } |
3226 | else | |
0dd2d296 ILT |
3227 | { |
3228 | int off; | |
3229 | ||
3230 | if (breg == 0) | |
3231 | { | |
8ea7f4e8 | 3232 | frag_grow (28); |
0dd2d296 ILT |
3233 | tempreg = GP; |
3234 | off = 0; | |
3235 | used_at = 0; | |
3236 | } | |
3237 | else | |
3238 | { | |
8ea7f4e8 | 3239 | frag_grow (36); |
0dd2d296 ILT |
3240 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3241 | mips_isa < 3 ? "addu" : "daddu", | |
3242 | "d,v,t", AT, breg, GP); | |
3243 | tempreg = AT; | |
3244 | off = 4; | |
3245 | used_at = 1; | |
3246 | } | |
3247 | ||
3248 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3249 | coproc ? treg + 1 : treg, | |
3250 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3251 | offset_expr.X_add_number += 4; | |
3252 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3253 | coproc ? treg : treg + 1, | |
3254 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3255 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3256 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 3257 | used_at && mips_noat), |
0dd2d296 ILT |
3258 | offset_expr.X_add_symbol, (long) 0, |
3259 | (char *) NULL); | |
777ad64d ILT |
3260 | |
3261 | /* We just generated two relocs. When tc_gen_reloc | |
3262 | handles this case, it will skip the first reloc and | |
3263 | handle the second. The second reloc already has an | |
3264 | extra addend of 4, which we added above. We must | |
3265 | subtract it out, and then subtract another 4 to make | |
3266 | the first reloc come out right. The second reloc | |
3267 | will come out right because we are going to add 4 to | |
3268 | offset_expr when we build its instruction below. */ | |
3269 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
3270 | offset_expr.X_op = O_constant; |
3271 | } | |
3272 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
3273 | if (p != NULL) | |
3274 | p += 4; | |
3275 | if (breg != 0) | |
3276 | { | |
3277 | macro_build (p, &icnt, (expressionS *) NULL, | |
3278 | mips_isa < 3 ? "addu" : "daddu", | |
3279 | "d,v,t", AT, breg, AT); | |
3280 | if (p != NULL) | |
3281 | p += 4; | |
3282 | } | |
3283 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
3284 | coproc ? treg + 1 : treg, | |
3285 | (int) BFD_RELOC_LO16, AT); | |
3286 | if (p != NULL) | |
3287 | p += 4; | |
3288 | /* FIXME: How do we handle overflow here? */ | |
3289 | offset_expr.X_add_number += 4; | |
3290 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
3291 | coproc ? treg : treg + 1, | |
3292 | (int) BFD_RELOC_LO16, AT); | |
3293 | } | |
d9aba805 | 3294 | else if (mips_pic == SVR4_PIC) |
670a50eb | 3295 | { |
0dd2d296 ILT |
3296 | int off; |
3297 | ||
3298 | /* If this is a reference to an external symbol, we want | |
3299 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3300 | nop | |
3301 | <op> $treg,0($at) | |
3302 | <op> $treg+1,4($at) | |
3303 | Otherwise we want | |
3304 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3305 | nop | |
3306 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
3307 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
3308 | If there is a base register we add it to $at before the | |
3309 | lwc1 instructions. If there is a constant we include it | |
3310 | in the lwc1 instructions. */ | |
3311 | used_at = 1; | |
3312 | expr1.X_add_number = offset_expr.X_add_number; | |
3313 | offset_expr.X_add_number = 0; | |
3314 | if (expr1.X_add_number < -0x8000 | |
3315 | || expr1.X_add_number >= 0x8000 - 4) | |
3316 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3317 | if (breg == 0) | |
3318 | off = 0; | |
3319 | else | |
3320 | off = 4; | |
8ea7f4e8 | 3321 | frag_grow (24 + off); |
0dd2d296 ILT |
3322 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3323 | mips_isa < 3 ? "lw" : "ld", | |
3324 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3325 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 3326 | if (breg != 0) |
0dd2d296 | 3327 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 3328 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
3329 | "d,v,t", AT, breg, AT); |
3330 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
3331 | coproc ? treg + 1 : treg, | |
3332 | (int) BFD_RELOC_LO16, AT); | |
3333 | expr1.X_add_number += 4; | |
3334 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
3335 | coproc ? treg : treg + 1, | |
3336 | (int) BFD_RELOC_LO16, AT); | |
3337 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3338 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
3339 | offset_expr.X_add_symbol, (long) 0, | |
3340 | (char *) NULL); | |
8358c818 | 3341 | } |
d9aba805 ILT |
3342 | else if (mips_pic == EMBEDDED_PIC) |
3343 | { | |
3344 | /* If there is no base register, we use | |
3345 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3346 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
3347 | If we have a base register, we use | |
3348 | addu $at,$breg,$gp | |
3349 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
3350 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
3351 | */ | |
3352 | if (breg == 0) | |
3353 | { | |
3354 | tempreg = GP; | |
3355 | used_at = 0; | |
3356 | } | |
3357 | else | |
3358 | { | |
3359 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3360 | mips_isa < 3 ? "addu" : "daddu", | |
3361 | "d,v,t", AT, breg, GP); | |
3362 | tempreg = AT; | |
3363 | used_at = 1; | |
3364 | } | |
3365 | ||
3366 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3367 | coproc ? treg + 1 : treg, | |
3368 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3369 | offset_expr.X_add_number += 4; | |
3370 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3371 | coproc ? treg : treg + 1, | |
3372 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3373 | } | |
3374 | else | |
3375 | abort (); | |
0dd2d296 ILT |
3376 | |
3377 | if (! used_at) | |
3378 | return; | |
3379 | ||
3380 | break; | |
3381 | ||
3382 | case M_LD_OB: | |
3383 | s = "lw"; | |
3384 | goto sd_ob; | |
3385 | case M_SD_OB: | |
3386 | s = "sw"; | |
3387 | sd_ob: | |
3388 | assert (mips_isa < 3); | |
3389 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
3390 | (int) BFD_RELOC_LO16, breg); | |
3391 | offset_expr.X_add_number += 4; | |
3392 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
3393 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 3394 | return; |
917fae09 SS |
3395 | #ifdef LOSING_COMPILER |
3396 | default: | |
3397 | macro2 (ip); | |
3398 | return; | |
3399 | } | |
3400 | if (mips_noat) | |
3401 | as_warn ("Macro used $at after \".set noat\""); | |
3402 | } | |
3403 | ||
3404 | static void | |
3405 | macro2 (ip) | |
3406 | struct mips_cl_insn *ip; | |
3407 | { | |
3408 | register int treg, sreg, dreg, breg; | |
3409 | int tempreg; | |
3410 | int mask; | |
3411 | int icnt = 0; | |
3412 | int used_at; | |
3413 | expressionS expr1; | |
3414 | const char *s; | |
3415 | const char *s2; | |
3416 | const char *fmt; | |
3417 | int likely = 0; | |
3418 | int dbl = 0; | |
3419 | int coproc = 0; | |
3420 | offsetT maxnum; | |
3421 | bfd_reloc_code_real_type r; | |
3422 | char *p; | |
3423 | ||
3424 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3425 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3426 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3427 | mask = ip->insn_mo->mask; | |
3428 | ||
3429 | expr1.X_op = O_constant; | |
3430 | expr1.X_op_symbol = NULL; | |
3431 | expr1.X_add_symbol = NULL; | |
3432 | expr1.X_add_number = 1; | |
3433 | ||
3434 | switch (mask) | |
3435 | { | |
3436 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 3437 | |
8358c818 ILT |
3438 | case M_DMUL: |
3439 | dbl = 1; | |
3d3c5039 | 3440 | case M_MUL: |
0dd2d296 | 3441 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3442 | dbl ? "dmultu" : "multu", |
3443 | "s,t", sreg, treg); | |
0dd2d296 | 3444 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 3445 | return; |
3d3c5039 | 3446 | |
8358c818 ILT |
3447 | case M_DMUL_I: |
3448 | dbl = 1; | |
3d3c5039 | 3449 | case M_MUL_I: |
8358c818 ILT |
3450 | /* The MIPS assembler some times generates shifts and adds. I'm |
3451 | not trying to be that fancy. GCC should do this for us | |
3452 | anyway. */ | |
6e8dda9c | 3453 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3454 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3455 | dbl ? "dmult" : "mult", |
3456 | "s,t", sreg, AT); | |
0dd2d296 | 3457 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 3458 | break; |
3d3c5039 | 3459 | |
8358c818 ILT |
3460 | case M_DMULO: |
3461 | dbl = 1; | |
3462 | case M_MULO: | |
3463 | mips_emit_delays (); | |
3464 | ++mips_noreorder; | |
0dd2d296 ILT |
3465 | mips_any_noreorder = 1; |
3466 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
3467 | dbl ? "dmult" : "mult", |
3468 | "s,t", sreg, treg); | |
0dd2d296 ILT |
3469 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
3470 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
3471 | dbl ? "dsra32" : "sra", |
3472 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 3473 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
3474 | if (mips_trap) |
3475 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
3476 | else | |
3477 | { | |
3478 | expr1.X_add_number = 8; | |
3479 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
3480 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3481 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3482 | } | |
8358c818 | 3483 | --mips_noreorder; |
0dd2d296 | 3484 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
3485 | break; |
3486 | ||
3487 | case M_DMULOU: | |
3488 | dbl = 1; | |
3489 | case M_MULOU: | |
3490 | mips_emit_delays (); | |
3491 | ++mips_noreorder; | |
0dd2d296 ILT |
3492 | mips_any_noreorder = 1; |
3493 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
3494 | dbl ? "dmultu" : "multu", |
3495 | "s,t", sreg, treg); | |
0dd2d296 ILT |
3496 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
3497 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
3498 | if (mips_trap) |
3499 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
3500 | else | |
3501 | { | |
3502 | expr1.X_add_number = 8; | |
3503 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
3504 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3505 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3506 | } | |
8358c818 ILT |
3507 | --mips_noreorder; |
3508 | break; | |
3509 | ||
3d3c5039 | 3510 | case M_ROL: |
0dd2d296 ILT |
3511 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
3512 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
3513 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
3514 | treg); | |
3515 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 3516 | break; |
3d3c5039 ILT |
3517 | |
3518 | case M_ROL_I: | |
0dd2d296 | 3519 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
670a50eb | 3520 | imm_expr.X_add_number & 0x1f); |
0dd2d296 | 3521 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
670a50eb | 3522 | (0 - imm_expr.X_add_number) & 0x1f); |
0dd2d296 | 3523 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 3524 | break; |
3d3c5039 ILT |
3525 | |
3526 | case M_ROR: | |
0dd2d296 ILT |
3527 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
3528 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
3529 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
3530 | treg); | |
3531 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 3532 | break; |
3d3c5039 ILT |
3533 | |
3534 | case M_ROR_I: | |
0dd2d296 | 3535 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
670a50eb | 3536 | imm_expr.X_add_number & 0x1f); |
0dd2d296 | 3537 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
670a50eb | 3538 | (0 - imm_expr.X_add_number) & 0x1f); |
0dd2d296 | 3539 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 3540 | break; |
3d3c5039 ILT |
3541 | |
3542 | case M_S_DOB: | |
8358c818 | 3543 | assert (mips_isa < 2); |
9a7d824a ILT |
3544 | /* Even on a big endian machine $fn comes before $fn+1. We have |
3545 | to adjust when storing to memory. */ | |
0dd2d296 | 3546 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 3547 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 3548 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3549 | offset_expr.X_add_number += 4; |
0dd2d296 | 3550 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 3551 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 3552 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3553 | return; |
3d3c5039 | 3554 | |
3d3c5039 | 3555 | case M_SEQ: |
670a50eb | 3556 | if (sreg == 0) |
0dd2d296 ILT |
3557 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
3558 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 3559 | else if (treg == 0) |
0dd2d296 ILT |
3560 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
3561 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
3562 | else |
3563 | { | |
0dd2d296 ILT |
3564 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3565 | sreg, treg); | |
3566 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
3567 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 3568 | } |
670a50eb | 3569 | return; |
3d3c5039 ILT |
3570 | |
3571 | case M_SEQ_I: | |
670a50eb ILT |
3572 | if (imm_expr.X_add_number == 0) |
3573 | { | |
0dd2d296 ILT |
3574 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
3575 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3576 | return; |
3d3c5039 | 3577 | } |
670a50eb ILT |
3578 | if (sreg == 0) |
3579 | { | |
9a7d824a | 3580 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 3581 | ip->insn_mo->name); |
0dd2d296 | 3582 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 3583 | return; |
3d3c5039 | 3584 | } |
6e8dda9c | 3585 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 3586 | { |
0dd2d296 ILT |
3587 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
3588 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3589 | used_at = 0; |
6e8dda9c ILT |
3590 | } |
3591 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
3592 | { | |
3593 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3594 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 3595 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
3596 | "t,r,j", dreg, sreg, |
3597 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
3598 | used_at = 0; |
3599 | } | |
3600 | else | |
3601 | { | |
3602 | load_register (&icnt, AT, &imm_expr); | |
0dd2d296 ILT |
3603 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3604 | sreg, AT); | |
670a50eb ILT |
3605 | used_at = 1; |
3606 | } | |
0dd2d296 | 3607 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 3608 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
3609 | if (used_at) |
3610 | break; | |
3611 | return; | |
3d3c5039 ILT |
3612 | |
3613 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
3614 | s = "slt"; |
3615 | goto sge; | |
3d3c5039 | 3616 | case M_SGEU: |
670a50eb | 3617 | s = "sltu"; |
3d3c5039 | 3618 | sge: |
0dd2d296 ILT |
3619 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
3620 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 3621 | (int) BFD_RELOC_LO16); |
670a50eb | 3622 | return; |
3d3c5039 | 3623 | |
670a50eb | 3624 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 3625 | case M_SGEU_I: |
6e8dda9c | 3626 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3627 | { |
0dd2d296 | 3628 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 3629 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 3630 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
3631 | used_at = 0; |
3632 | } | |
3633 | else | |
3634 | { | |
6e8dda9c | 3635 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3636 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
3637 | mask == M_SGE_I ? "slt" : "sltu", |
3638 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
3639 | used_at = 1; |
3640 | } | |
0dd2d296 | 3641 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 3642 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
3643 | if (used_at) |
3644 | break; | |
3645 | return; | |
3d3c5039 ILT |
3646 | |
3647 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
3648 | s = "slt"; |
3649 | goto sgt; | |
3d3c5039 | 3650 | case M_SGTU: |
670a50eb | 3651 | s = "sltu"; |
3d3c5039 | 3652 | sgt: |
0dd2d296 | 3653 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 3654 | return; |
3d3c5039 | 3655 | |
670a50eb ILT |
3656 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
3657 | s = "slt"; | |
3658 | goto sgti; | |
3d3c5039 | 3659 | case M_SGTU_I: |
670a50eb | 3660 | s = "sltu"; |
3d3c5039 | 3661 | sgti: |
6e8dda9c | 3662 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3663 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 3664 | break; |
3d3c5039 | 3665 | |
670a50eb ILT |
3666 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
3667 | s = "slt"; | |
3668 | goto sle; | |
3d3c5039 | 3669 | case M_SLEU: |
670a50eb | 3670 | s = "sltu"; |
3d3c5039 | 3671 | sle: |
0dd2d296 ILT |
3672 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
3673 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 3674 | (int) BFD_RELOC_LO16); |
670a50eb | 3675 | return; |
3d3c5039 | 3676 | |
670a50eb ILT |
3677 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
3678 | s = "slt"; | |
3679 | goto slei; | |
3d3c5039 | 3680 | case M_SLEU_I: |
670a50eb | 3681 | s = "sltu"; |
3d3c5039 | 3682 | slei: |
6e8dda9c | 3683 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 ILT |
3684 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
3685 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 3686 | (int) BFD_RELOC_LO16); |
670a50eb | 3687 | break; |
3d3c5039 ILT |
3688 | |
3689 | case M_SLT_I: | |
6e8dda9c | 3690 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3691 | { |
0dd2d296 ILT |
3692 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
3693 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3694 | return; |
3d3c5039 | 3695 | } |
6e8dda9c | 3696 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3697 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 3698 | break; |
3d3c5039 ILT |
3699 | |
3700 | case M_SLTU_I: | |
6e8dda9c | 3701 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3702 | { |
0dd2d296 ILT |
3703 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
3704 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3705 | return; |
3d3c5039 | 3706 | } |
6e8dda9c | 3707 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 ILT |
3708 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
3709 | AT); | |
670a50eb | 3710 | break; |
3d3c5039 ILT |
3711 | |
3712 | case M_SNE: | |
670a50eb | 3713 | if (sreg == 0) |
0dd2d296 ILT |
3714 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
3715 | treg); | |
670a50eb | 3716 | else if (treg == 0) |
0dd2d296 ILT |
3717 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
3718 | sreg); | |
670a50eb ILT |
3719 | else |
3720 | { | |
0dd2d296 ILT |
3721 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3722 | sreg, treg); | |
3723 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
3724 | dreg); | |
3d3c5039 | 3725 | } |
670a50eb | 3726 | return; |
3d3c5039 ILT |
3727 | |
3728 | case M_SNE_I: | |
670a50eb ILT |
3729 | if (imm_expr.X_add_number == 0) |
3730 | { | |
0dd2d296 ILT |
3731 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
3732 | sreg); | |
670a50eb | 3733 | return; |
3d3c5039 | 3734 | } |
670a50eb ILT |
3735 | if (sreg == 0) |
3736 | { | |
9a7d824a | 3737 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 3738 | ip->insn_mo->name); |
0dd2d296 | 3739 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 3740 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 3741 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 3742 | return; |
3d3c5039 | 3743 | } |
6e8dda9c | 3744 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 3745 | { |
0dd2d296 ILT |
3746 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
3747 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3748 | used_at = 0; |
6e8dda9c ILT |
3749 | } |
3750 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
3751 | { | |
3752 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3753 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 3754 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 3755 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
3756 | used_at = 0; |
3757 | } | |
3758 | else | |
3759 | { | |
3760 | load_register (&icnt, AT, &imm_expr); | |
0dd2d296 ILT |
3761 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3762 | sreg, AT); | |
670a50eb ILT |
3763 | used_at = 1; |
3764 | } | |
0dd2d296 | 3765 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
3766 | if (used_at) |
3767 | break; | |
3768 | return; | |
3d3c5039 | 3769 | |
8358c818 ILT |
3770 | case M_DSUB_I: |
3771 | dbl = 1; | |
3d3c5039 | 3772 | case M_SUB_I: |
6e8dda9c | 3773 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
3774 | { |
3775 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3776 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 3777 | dbl ? "daddi" : "addi", |
9226253a | 3778 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 3779 | return; |
3d3c5039 | 3780 | } |
6e8dda9c | 3781 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3782 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3783 | dbl ? "dsub" : "sub", |
3784 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 3785 | break; |
3d3c5039 | 3786 | |
8358c818 ILT |
3787 | case M_DSUBU_I: |
3788 | dbl = 1; | |
3d3c5039 | 3789 | case M_SUBU_I: |
6e8dda9c | 3790 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
3791 | { |
3792 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3793 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 3794 | dbl ? "daddiu" : "addiu", |
9226253a | 3795 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 3796 | return; |
3d3c5039 | 3797 | } |
6e8dda9c | 3798 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3799 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3800 | dbl ? "dsubu" : "subu", |
3801 | "d,v,t", dreg, sreg, AT); | |
3802 | break; | |
3803 | ||
3804 | case M_TEQ_I: | |
3805 | s = "teq"; | |
3806 | goto trap; | |
3807 | case M_TGE_I: | |
3808 | s = "tge"; | |
3809 | goto trap; | |
3810 | case M_TGEU_I: | |
3811 | s = "tgeu"; | |
3812 | goto trap; | |
3813 | case M_TLT_I: | |
3814 | s = "tlt"; | |
3815 | goto trap; | |
3816 | case M_TLTU_I: | |
3817 | s = "tltu"; | |
3818 | goto trap; | |
3819 | case M_TNE_I: | |
3820 | s = "tne"; | |
3821 | trap: | |
6e8dda9c | 3822 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3823 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 3824 | break; |
3d3c5039 ILT |
3825 | |
3826 | case M_TRUNCWD: | |
3827 | case M_TRUNCWS: | |
8358c818 | 3828 | assert (mips_isa < 2); |
670a50eb ILT |
3829 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
3830 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
3831 | ||
3832 | /* | |
3833 | * Is the double cfc1 instruction a bug in the mips assembler; | |
3834 | * or is there a reason for it? | |
3835 | */ | |
becfe05e ILT |
3836 | mips_emit_delays (); |
3837 | ++mips_noreorder; | |
0dd2d296 ILT |
3838 | mips_any_noreorder = 1; |
3839 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
3840 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
3841 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 3842 | expr1.X_add_number = 3; |
0dd2d296 | 3843 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 3844 | (int) BFD_RELOC_LO16); |
670a50eb | 3845 | expr1.X_add_number = 2; |
0dd2d296 | 3846 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 3847 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3848 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
3849 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3850 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 3851 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
3852 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
3853 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 3854 | --mips_noreorder; |
670a50eb | 3855 | break; |
3d3c5039 ILT |
3856 | |
3857 | case M_ULH: | |
670a50eb ILT |
3858 | s = "lb"; |
3859 | goto ulh; | |
3d3c5039 | 3860 | case M_ULHU: |
670a50eb | 3861 | s = "lbu"; |
3d3c5039 | 3862 | ulh: |
8ea7f4e8 ILT |
3863 | if (offset_expr.X_add_number >= 0x7fff) |
3864 | as_bad ("operand overflow"); | |
670a50eb | 3865 | /* avoid load delay */ |
8ea7f4e8 ILT |
3866 | if (byte_order == LITTLE_ENDIAN) |
3867 | offset_expr.X_add_number += 1; | |
0dd2d296 | 3868 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 3869 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
3870 | if (byte_order == LITTLE_ENDIAN) |
3871 | offset_expr.X_add_number -= 1; | |
3872 | else | |
3873 | offset_expr.X_add_number += 1; | |
0dd2d296 | 3874 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 3875 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
3876 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
3877 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 3878 | break; |
3d3c5039 ILT |
3879 | |
3880 | case M_ULW: | |
8ea7f4e8 ILT |
3881 | if (offset_expr.X_add_number >= 0x7ffd) |
3882 | as_bad ("operand overflow"); | |
3883 | if (byte_order == LITTLE_ENDIAN) | |
3884 | offset_expr.X_add_number += 3; | |
0dd2d296 | 3885 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwl", "t,o(b)", treg, |
9226253a | 3886 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
3887 | if (byte_order == LITTLE_ENDIAN) |
3888 | offset_expr.X_add_number -= 3; | |
3889 | else | |
3890 | offset_expr.X_add_number += 3; | |
0dd2d296 | 3891 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwr", "t,o(b)", treg, |
9226253a | 3892 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3893 | return; |
3d3c5039 ILT |
3894 | |
3895 | case M_ULH_A: | |
3896 | case M_ULHU_A: | |
3897 | case M_ULW_A: | |
0dd2d296 | 3898 | load_address (&icnt, AT, &offset_expr); |
670a50eb ILT |
3899 | if (mask == M_ULW_A) |
3900 | { | |
8ea7f4e8 ILT |
3901 | if (byte_order == LITTLE_ENDIAN) |
3902 | expr1.X_add_number = 3; | |
3903 | else | |
3904 | expr1.X_add_number = 0; | |
0dd2d296 | 3905 | macro_build ((char *) NULL, &icnt, &expr1, "lwl", "t,o(b)", treg, |
9226253a | 3906 | (int) BFD_RELOC_LO16, AT); |
8ea7f4e8 ILT |
3907 | if (byte_order == LITTLE_ENDIAN) |
3908 | expr1.X_add_number = 0; | |
3909 | else | |
3910 | expr1.X_add_number = 3; | |
0dd2d296 | 3911 | macro_build ((char *) NULL, &icnt, &expr1, "lwr", "t,o(b)", treg, |
9226253a | 3912 | (int) BFD_RELOC_LO16, AT); |
670a50eb ILT |
3913 | } |
3914 | else | |
3915 | { | |
8ea7f4e8 ILT |
3916 | if (byte_order == BIG_ENDIAN) |
3917 | expr1.X_add_number = 0; | |
0dd2d296 | 3918 | macro_build ((char *) NULL, &icnt, &expr1, |
9226253a ILT |
3919 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, |
3920 | (int) BFD_RELOC_LO16, AT); | |
8ea7f4e8 ILT |
3921 | if (byte_order == BIG_ENDIAN) |
3922 | expr1.X_add_number = 1; | |
3923 | else | |
3924 | expr1.X_add_number = 0; | |
0dd2d296 | 3925 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
9226253a | 3926 | (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
3927 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, |
3928 | treg, 8); | |
3929 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
3930 | treg, AT); | |
670a50eb ILT |
3931 | } |
3932 | break; | |
3d3c5039 ILT |
3933 | |
3934 | case M_USH: | |
8ea7f4e8 ILT |
3935 | if (offset_expr.X_add_number >= 0x7fff) |
3936 | as_bad ("operand overflow"); | |
3937 | if (byte_order == BIG_ENDIAN) | |
3938 | offset_expr.X_add_number += 1; | |
0dd2d296 | 3939 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 3940 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 3941 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
8ea7f4e8 ILT |
3942 | if (byte_order == BIG_ENDIAN) |
3943 | offset_expr.X_add_number -= 1; | |
3944 | else | |
3945 | offset_expr.X_add_number += 1; | |
0dd2d296 | 3946 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 3947 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3948 | break; |
3d3c5039 ILT |
3949 | |
3950 | case M_USW: | |
8ea7f4e8 ILT |
3951 | if (offset_expr.X_add_number >= 0x7ffd) |
3952 | as_bad ("operand overflow"); | |
3953 | if (byte_order == LITTLE_ENDIAN) | |
3954 | offset_expr.X_add_number += 3; | |
0dd2d296 | 3955 | macro_build ((char *) NULL, &icnt, &offset_expr, "swl", "t,o(b)", treg, |
9226253a | 3956 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
3957 | if (byte_order == LITTLE_ENDIAN) |
3958 | offset_expr.X_add_number -= 3; | |
3959 | else | |
3960 | offset_expr.X_add_number += 3; | |
0dd2d296 | 3961 | macro_build ((char *) NULL, &icnt, &offset_expr, "swr", "t,o(b)", treg, |
9226253a | 3962 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3963 | return; |
3d3c5039 ILT |
3964 | |
3965 | case M_USH_A: | |
3966 | case M_USW_A: | |
0dd2d296 | 3967 | load_address (&icnt, AT, &offset_expr); |
670a50eb ILT |
3968 | if (mask == M_USW_A) |
3969 | { | |
8ea7f4e8 ILT |
3970 | if (byte_order == LITTLE_ENDIAN) |
3971 | expr1.X_add_number = 3; | |
3972 | else | |
3973 | expr1.X_add_number = 0; | |
0dd2d296 | 3974 | macro_build ((char *) NULL, &icnt, &expr1, "swl", "t,o(b)", treg, |
9226253a | 3975 | (int) BFD_RELOC_LO16, AT); |
8ea7f4e8 ILT |
3976 | if (byte_order == LITTLE_ENDIAN) |
3977 | expr1.X_add_number = 0; | |
3978 | else | |
3979 | expr1.X_add_number = 3; | |
0dd2d296 | 3980 | macro_build ((char *) NULL, &icnt, &expr1, "swr", "t,o(b)", treg, |
9226253a | 3981 | (int) BFD_RELOC_LO16, AT); |
670a50eb ILT |
3982 | } |
3983 | else | |
3984 | { | |
8ea7f4e8 ILT |
3985 | if (byte_order == LITTLE_ENDIAN) |
3986 | expr1.X_add_number = 0; | |
0dd2d296 | 3987 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
9226253a | 3988 | (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
3989 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, |
3990 | treg, 8); | |
8ea7f4e8 ILT |
3991 | if (byte_order == LITTLE_ENDIAN) |
3992 | expr1.X_add_number = 1; | |
3993 | else | |
3994 | expr1.X_add_number = 0; | |
0dd2d296 | 3995 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
9226253a | 3996 | (int) BFD_RELOC_LO16, AT); |
8ea7f4e8 ILT |
3997 | if (byte_order == LITTLE_ENDIAN) |
3998 | expr1.X_add_number = 0; | |
3999 | else | |
4000 | expr1.X_add_number = 1; | |
0dd2d296 | 4001 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
9226253a | 4002 | (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
4003 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, |
4004 | treg, 8); | |
4005 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
4006 | treg, AT); | |
670a50eb ILT |
4007 | } |
4008 | break; | |
3d3c5039 ILT |
4009 | |
4010 | default: | |
670a50eb | 4011 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 4012 | break; |
3d3c5039 | 4013 | } |
670a50eb ILT |
4014 | if (mips_noat) |
4015 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
4016 | } |
4017 | ||
4018 | ||
4019 | /* | |
4020 | This routine assembles an instruction into its binary format. As a side | |
4021 | effect it sets one of the global variables imm_reloc or offset_reloc to the | |
4022 | type of relocation to do if one of the operands is an address expression. | |
4023 | */ | |
4024 | static void | |
4025 | mips_ip (str, ip) | |
4026 | char *str; | |
4027 | struct mips_cl_insn *ip; | |
4028 | { | |
670a50eb ILT |
4029 | char *s; |
4030 | const char *args; | |
4031 | char c; | |
4032 | struct mips_opcode *insn; | |
4033 | char *argsStart; | |
4034 | unsigned int regno; | |
4035 | unsigned int lastregno = 0; | |
4036 | char *s_reset; | |
4037 | ||
4038 | insn_error = NULL; | |
4039 | ||
4040 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '.'; ++s) | |
4041 | continue; | |
4042 | switch (*s) | |
4043 | { | |
3d3c5039 | 4044 | case '\0': |
670a50eb | 4045 | break; |
3d3c5039 ILT |
4046 | |
4047 | case ' ': | |
670a50eb ILT |
4048 | *s++ = '\0'; |
4049 | break; | |
3d3c5039 ILT |
4050 | |
4051 | default: | |
670a50eb ILT |
4052 | as_warn ("Unknown opcode: `%s'", str); |
4053 | exit (1); | |
3d3c5039 | 4054 | } |
670a50eb ILT |
4055 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
4056 | { | |
4057 | as_warn ("`%s' not in hash table.", str); | |
4058 | insn_error = "ERROR: Unrecognized opcode"; | |
4059 | return; | |
3d3c5039 | 4060 | } |
670a50eb ILT |
4061 | argsStart = s; |
4062 | for (;;) | |
4063 | { | |
8358c818 ILT |
4064 | int insn_isa; |
4065 | ||
670a50eb | 4066 | assert (strcmp (insn->name, str) == 0); |
8358c818 ILT |
4067 | |
4068 | if (insn->pinfo == INSN_MACRO) | |
4069 | insn_isa = insn->match; | |
4070 | else if (insn->pinfo & INSN_ISA2) | |
4071 | insn_isa = 2; | |
4072 | else if (insn->pinfo & INSN_ISA3) | |
4073 | insn_isa = 3; | |
4074 | else | |
4075 | insn_isa = 1; | |
4076 | ||
4077 | if (insn_isa > mips_isa) | |
4078 | { | |
4079 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
4080 | && strcmp (insn->name, insn[1].name) == 0) | |
4081 | { | |
4082 | ++insn; | |
4083 | continue; | |
4084 | } | |
8bbad6fd | 4085 | as_warn ("Instruction not supported on this processor"); |
8358c818 ILT |
4086 | } |
4087 | ||
670a50eb ILT |
4088 | ip->insn_mo = insn; |
4089 | ip->insn_opcode = insn->match; | |
4090 | for (args = insn->args;; ++args) | |
4091 | { | |
4092 | if (*s == ' ') | |
4093 | ++s; | |
4094 | switch (*args) | |
4095 | { | |
4096 | case '\0': /* end of args */ | |
4097 | if (*s == '\0') | |
4098 | return; | |
4099 | break; | |
3d3c5039 ILT |
4100 | |
4101 | case ',': | |
670a50eb ILT |
4102 | if (*s++ == *args) |
4103 | continue; | |
4104 | s--; | |
4105 | switch (*++args) | |
4106 | { | |
3d3c5039 ILT |
4107 | case 'r': |
4108 | case 'v': | |
670a50eb ILT |
4109 | ip->insn_opcode |= lastregno << 21; |
4110 | continue; | |
3d3c5039 ILT |
4111 | |
4112 | case 'w': | |
4113 | case 'W': | |
670a50eb ILT |
4114 | ip->insn_opcode |= lastregno << 16; |
4115 | continue; | |
3d3c5039 ILT |
4116 | |
4117 | case 'V': | |
670a50eb ILT |
4118 | ip->insn_opcode |= lastregno << 11; |
4119 | continue; | |
3d3c5039 | 4120 | } |
670a50eb | 4121 | break; |
3d3c5039 ILT |
4122 | |
4123 | case '(': | |
670a50eb ILT |
4124 | /* handle optional base register. |
4125 | Either the base register is omitted or | |
4126 | we must have a left paren. */ | |
4127 | /* this is dependent on the next operand specifier | |
4128 | is a 'b' for base register */ | |
4129 | assert (args[1] == 'b'); | |
4130 | if (*s == '\0') | |
4131 | return; | |
3d3c5039 | 4132 | |
670a50eb ILT |
4133 | case ')': /* these must match exactly */ |
4134 | if (*s++ == *args) | |
3d3c5039 | 4135 | continue; |
670a50eb ILT |
4136 | break; |
4137 | ||
4138 | case '<': /* must be at least one digit */ | |
4139 | /* | |
4140 | * According to the manual, if the shift amount is greater | |
4141 | * than 31 or less than 0 the the shift amount should be | |
4142 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 4143 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
4144 | */ |
4145 | my_getExpression (&imm_expr, s); | |
4146 | check_absolute_expr (ip, &imm_expr); | |
4147 | if ((unsigned long) imm_expr.X_add_number > 31) | |
4148 | { | |
58d4951d ILT |
4149 | as_warn ("Improper shift amount (%ld)", |
4150 | (long) imm_expr.X_add_number); | |
9226253a | 4151 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
4152 | } |
4153 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 4154 | imm_expr.X_op = O_absent; |
670a50eb ILT |
4155 | s = expr_end; |
4156 | continue; | |
4157 | ||
56c96faa ILT |
4158 | case '>': /* shift amount minus 32 */ |
4159 | my_getExpression (&imm_expr, s); | |
4160 | check_absolute_expr (ip, &imm_expr); | |
4161 | if ((unsigned long) imm_expr.X_add_number < 32 | |
4162 | || (unsigned long) imm_expr.X_add_number > 63) | |
4163 | break; | |
4164 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
4165 | imm_expr.X_op = O_absent; | |
4166 | s = expr_end; | |
4167 | continue; | |
4168 | ||
9226253a ILT |
4169 | case 'k': /* cache code */ |
4170 | my_getExpression (&imm_expr, s); | |
4171 | check_absolute_expr (ip, &imm_expr); | |
4172 | if ((unsigned long) imm_expr.X_add_number > 31) | |
4173 | { | |
4174 | as_warn ("Invalid cahce opcode (%lu)", | |
4175 | (unsigned long) imm_expr.X_add_number); | |
4176 | imm_expr.X_add_number &= 0x1f; | |
4177 | } | |
4178 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
4179 | imm_expr.X_op = O_absent; | |
4180 | s = expr_end; | |
4181 | continue; | |
4182 | ||
670a50eb ILT |
4183 | case 'c': /* break code */ |
4184 | my_getExpression (&imm_expr, s); | |
4185 | check_absolute_expr (ip, &imm_expr); | |
4186 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
4187 | as_warn ("Illegal break code (%ld)", |
4188 | (long) imm_expr.X_add_number); | |
670a50eb | 4189 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 4190 | imm_expr.X_op = O_absent; |
670a50eb ILT |
4191 | s = expr_end; |
4192 | continue; | |
4193 | ||
918692a5 ILT |
4194 | case 'B': /* syscall code */ |
4195 | my_getExpression (&imm_expr, s); | |
4196 | check_absolute_expr (ip, &imm_expr); | |
4197 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
4198 | as_warn ("Illegal syscall code (%ld)", |
4199 | (long) imm_expr.X_add_number); | |
918692a5 | 4200 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 4201 | imm_expr.X_op = O_absent; |
918692a5 ILT |
4202 | s = expr_end; |
4203 | continue; | |
4204 | ||
0aa07269 ILT |
4205 | case 'C': /* Coprocessor code */ |
4206 | my_getExpression (&imm_expr, s); | |
4207 | check_absolute_expr (ip, &imm_expr); | |
4208 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
4209 | { | |
58d4951d ILT |
4210 | as_warn ("Coproccesor code > 25 bits (%ld)", |
4211 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
4212 | imm_expr.X_add_number &= ((1<<25) - 1); |
4213 | } | |
4214 | ip->insn_opcode |= imm_expr.X_add_number; | |
4215 | imm_expr.X_op = O_absent; | |
4216 | s = expr_end; | |
4217 | continue; | |
4218 | ||
670a50eb ILT |
4219 | case 'b': /* base register */ |
4220 | case 'd': /* destination register */ | |
4221 | case 's': /* source register */ | |
4222 | case 't': /* target register */ | |
4223 | case 'r': /* both target and source */ | |
4224 | case 'v': /* both dest and source */ | |
4225 | case 'w': /* both dest and target */ | |
918692a5 ILT |
4226 | case 'E': /* coprocessor target register */ |
4227 | case 'G': /* coprocessor destination register */ | |
8358c818 | 4228 | case 'x': /* ignore register name */ |
ff3a5c18 | 4229 | case 'z': /* must be zero register */ |
670a50eb ILT |
4230 | s_reset = s; |
4231 | if (s[0] == '$') | |
4232 | { | |
4233 | if (isdigit (s[1])) | |
4234 | { | |
4235 | ++s; | |
4236 | regno = 0; | |
4237 | do | |
4238 | { | |
4239 | regno *= 10; | |
4240 | regno += *s - '0'; | |
4241 | ++s; | |
4242 | } | |
4243 | while (isdigit (*s)); | |
0aa07269 ILT |
4244 | if (regno > 31) |
4245 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 4246 | } |
0dd2d296 ILT |
4247 | else if (*args == 'E' || *args == 'G') |
4248 | goto notreg; | |
4249 | else | |
670a50eb | 4250 | { |
0aa07269 ILT |
4251 | if (s[1] == 'f' && s[2] == 'p') |
4252 | { | |
4253 | s += 3; | |
9226253a | 4254 | regno = FP; |
0aa07269 ILT |
4255 | } |
4256 | else if (s[1] == 's' && s[2] == 'p') | |
4257 | { | |
4258 | s += 3; | |
9226253a | 4259 | regno = SP; |
0aa07269 ILT |
4260 | } |
4261 | else if (s[1] == 'g' && s[2] == 'p') | |
4262 | { | |
4263 | s += 3; | |
9226253a | 4264 | regno = GP; |
0aa07269 ILT |
4265 | } |
4266 | else if (s[1] == 'a' && s[2] == 't') | |
4267 | { | |
4268 | s += 3; | |
9226253a | 4269 | regno = AT; |
0aa07269 ILT |
4270 | } |
4271 | else | |
4272 | goto notreg; | |
670a50eb | 4273 | } |
13fe1379 ILT |
4274 | if (regno == AT && ! mips_noat) |
4275 | as_warn ("Used $at without \".set noat\""); | |
670a50eb ILT |
4276 | c = *args; |
4277 | if (*s == ' ') | |
4278 | s++; | |
4279 | if (args[1] != *s) | |
4280 | { | |
4281 | if (c == 'r' || c == 'v' || c == 'w') | |
4282 | { | |
4283 | regno = lastregno; | |
4284 | s = s_reset; | |
4285 | args++; | |
4286 | } | |
4287 | } | |
ff3a5c18 ILT |
4288 | /* 'z' only matches $0. */ |
4289 | if (c == 'z' && regno != 0) | |
4290 | break; | |
670a50eb ILT |
4291 | switch (c) |
4292 | { | |
3d3c5039 ILT |
4293 | case 'r': |
4294 | case 's': | |
4295 | case 'v': | |
4296 | case 'b': | |
670a50eb ILT |
4297 | ip->insn_opcode |= regno << 21; |
4298 | break; | |
3d3c5039 | 4299 | case 'd': |
918692a5 | 4300 | case 'G': |
670a50eb ILT |
4301 | ip->insn_opcode |= regno << 11; |
4302 | break; | |
3d3c5039 ILT |
4303 | case 'w': |
4304 | case 't': | |
918692a5 | 4305 | case 'E': |
670a50eb | 4306 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
4307 | break; |
4308 | case 'x': | |
4309 | /* This case exists because on the r3000 trunc | |
4310 | expands into a macro which requires a gp | |
4311 | register. On the r6000 or r4000 it is | |
4312 | assembled into a single instruction which | |
4313 | ignores the register. Thus the insn version | |
4314 | is MIPS_ISA2 and uses 'x', and the macro | |
4315 | version is MIPS_ISA1 and uses 't'. */ | |
4316 | break; | |
ff3a5c18 ILT |
4317 | case 'z': |
4318 | /* This case is for the div instruction, which | |
4319 | acts differently if the destination argument | |
4320 | is $0. This only matches $0, and is checked | |
4321 | outside the switch. */ | |
4322 | break; | |
3d3c5039 | 4323 | } |
670a50eb ILT |
4324 | lastregno = regno; |
4325 | continue; | |
3d3c5039 ILT |
4326 | } |
4327 | notreg: | |
670a50eb ILT |
4328 | switch (*args++) |
4329 | { | |
3d3c5039 ILT |
4330 | case 'r': |
4331 | case 'v': | |
670a50eb ILT |
4332 | ip->insn_opcode |= lastregno << 21; |
4333 | continue; | |
3d3c5039 | 4334 | case 'w': |
670a50eb ILT |
4335 | ip->insn_opcode |= lastregno << 16; |
4336 | continue; | |
3d3c5039 | 4337 | } |
670a50eb | 4338 | break; |
3d3c5039 | 4339 | |
670a50eb ILT |
4340 | case 'D': /* floating point destination register */ |
4341 | case 'S': /* floating point source register */ | |
4342 | case 'T': /* floating point target register */ | |
3d3c5039 ILT |
4343 | case 'V': |
4344 | case 'W': | |
670a50eb ILT |
4345 | s_reset = s; |
4346 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
4347 | { | |
4348 | s += 2; | |
4349 | regno = 0; | |
4350 | do | |
4351 | { | |
4352 | regno *= 10; | |
4353 | regno += *s - '0'; | |
4354 | ++s; | |
4355 | } | |
4356 | while (isdigit (*s)); | |
4357 | ||
4358 | if (regno > 31) | |
4359 | as_bad ("Invalid float register number (%d)", regno); | |
4360 | ||
9226253a ILT |
4361 | if ((regno & 1) != 0 |
4362 | && mips_isa < 3 | |
4363 | && ! (strcmp (str, "mtc1") == 0 || | |
4364 | strcmp (str, "mfc1") == 0 || | |
4365 | strcmp (str, "lwc1") == 0 || | |
4366 | strcmp (str, "swc1") == 0)) | |
670a50eb ILT |
4367 | as_warn ("Float register should be even, was %d", |
4368 | regno); | |
4369 | ||
4370 | c = *args; | |
4371 | if (*s == ' ') | |
4372 | s++; | |
4373 | if (args[1] != *s) | |
4374 | { | |
4375 | if (c == 'V' || c == 'W') | |
4376 | { | |
4377 | regno = lastregno; | |
4378 | s = s_reset; | |
4379 | args++; | |
3d3c5039 ILT |
4380 | } |
4381 | } | |
670a50eb ILT |
4382 | switch (c) |
4383 | { | |
3d3c5039 | 4384 | case 'D': |
670a50eb ILT |
4385 | ip->insn_opcode |= regno << 6; |
4386 | break; | |
3d3c5039 ILT |
4387 | case 'V': |
4388 | case 'S': | |
670a50eb ILT |
4389 | ip->insn_opcode |= regno << 11; |
4390 | break; | |
3d3c5039 ILT |
4391 | case 'W': |
4392 | case 'T': | |
670a50eb | 4393 | ip->insn_opcode |= regno << 16; |
3d3c5039 | 4394 | } |
670a50eb ILT |
4395 | lastregno = regno; |
4396 | continue; | |
3d3c5039 | 4397 | } |
670a50eb ILT |
4398 | switch (*args++) |
4399 | { | |
3d3c5039 | 4400 | case 'V': |
670a50eb ILT |
4401 | ip->insn_opcode |= lastregno << 11; |
4402 | continue; | |
3d3c5039 | 4403 | case 'W': |
670a50eb ILT |
4404 | ip->insn_opcode |= lastregno << 16; |
4405 | continue; | |
3d3c5039 | 4406 | } |
670a50eb | 4407 | break; |
3d3c5039 ILT |
4408 | |
4409 | case 'I': | |
670a50eb ILT |
4410 | my_getExpression (&imm_expr, s); |
4411 | check_absolute_expr (ip, &imm_expr); | |
4412 | s = expr_end; | |
4413 | continue; | |
3d3c5039 ILT |
4414 | |
4415 | case 'A': | |
670a50eb ILT |
4416 | my_getExpression (&offset_expr, s); |
4417 | imm_reloc = BFD_RELOC_32; | |
4418 | s = expr_end; | |
4419 | continue; | |
3d3c5039 ILT |
4420 | |
4421 | case 'F': | |
19ed8960 ILT |
4422 | case 'L': |
4423 | case 'f': | |
4424 | case 'l': | |
4425 | { | |
4426 | int f64; | |
4427 | char *save_in; | |
4428 | char *err; | |
4429 | unsigned char temp[8]; | |
604633ae ILT |
4430 | int len; |
4431 | unsigned int length; | |
19ed8960 ILT |
4432 | segT seg; |
4433 | subsegT subseg; | |
4434 | char *p; | |
4435 | ||
4436 | /* These only appear as the last operand in an | |
4437 | instruction, and every instruction that accepts | |
4438 | them in any variant accepts them in all variants. | |
4439 | This means we don't have to worry about backing out | |
4440 | any changes if the instruction does not match. | |
4441 | ||
4442 | The difference between them is the size of the | |
4443 | floating point constant and where it goes. For 'F' | |
4444 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
4445 | is 32 bits. Where the constant is placed is based | |
4446 | on how the MIPS assembler does things: | |
4447 | F -- .rdata | |
4448 | L -- .lit8 | |
4449 | f -- immediate value | |
4450 | l -- .lit4 | |
0dd2d296 | 4451 | |
d9aba805 ILT |
4452 | When generating SVR4 PIC code, we do not use the |
4453 | .lit8 or .lit4 sections at all, in order to | |
4454 | reserve the entire global offset table. When | |
4455 | generating embedded PIC code, we use the .lit8 | |
4456 | section but not the .lit4 section (we can do .lit4 | |
4457 | inline easily; we need to put .lit8 somewhere in | |
4458 | the data segment, and using .lit8 permits the | |
4459 | linker to eventually combine identical .lit8 | |
4460 | entries). */ | |
19ed8960 ILT |
4461 | |
4462 | f64 = *args == 'F' || *args == 'L'; | |
4463 | ||
4464 | save_in = input_line_pointer; | |
4465 | input_line_pointer = s; | |
604633ae ILT |
4466 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
4467 | length = len; | |
19ed8960 ILT |
4468 | s = input_line_pointer; |
4469 | input_line_pointer = save_in; | |
4470 | if (err != NULL && *err != '\0') | |
4471 | { | |
4472 | as_bad ("Bad floating point constant: %s", err); | |
4473 | memset (temp, '\0', sizeof temp); | |
4474 | length = f64 ? 8 : 4; | |
4475 | } | |
4476 | ||
4477 | assert (length == (f64 ? 8 : 4)); | |
4478 | ||
0dd2d296 | 4479 | if (*args == 'f' |
d9aba805 | 4480 | || (mips_pic != NO_PIC && *args == 'l')) |
19ed8960 ILT |
4481 | { |
4482 | imm_expr.X_op = O_constant; | |
4483 | if (byte_order == LITTLE_ENDIAN) | |
4484 | imm_expr.X_add_number = | |
4485 | (((((((int) temp[3] << 8) | |
4486 | | temp[2]) << 8) | |
4487 | | temp[1]) << 8) | |
4488 | | temp[0]); | |
4489 | else | |
4490 | imm_expr.X_add_number = | |
4491 | (((((((int) temp[0] << 8) | |
4492 | | temp[1]) << 8) | |
4493 | | temp[2]) << 8) | |
4494 | | temp[3]); | |
4495 | } | |
4496 | else | |
4497 | { | |
0dd2d296 ILT |
4498 | const char *newname; |
4499 | segT new_seg; | |
4500 | ||
19ed8960 ILT |
4501 | /* Switch to the right section. */ |
4502 | seg = now_seg; | |
4503 | subseg = now_subseg; | |
4504 | switch (*args) | |
4505 | { | |
0dd2d296 | 4506 | default: /* unused default case avoids warnings. */ |
19ed8960 | 4507 | case 'L': |
d2c71068 ILT |
4508 | newname = (mips_pic != SVR4_PIC |
4509 | ? ".lit8" | |
4510 | : RDATA_SECTION_NAME); | |
0dd2d296 ILT |
4511 | break; |
4512 | case 'F': | |
d2c71068 | 4513 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
4514 | break; |
4515 | case 'l': | |
d9aba805 | 4516 | assert (mips_pic == NO_PIC); |
0dd2d296 | 4517 | newname = ".lit4"; |
19ed8960 ILT |
4518 | break; |
4519 | } | |
0dd2d296 | 4520 | new_seg = subseg_new (newname, (subsegT) 0); |
0221ddf7 | 4521 | frag_align (*args == 'l' ? 2 : 3, 0); |
0dd2d296 | 4522 | #ifdef OBJ_ELF |
0221ddf7 ILT |
4523 | record_alignment (new_seg, 4); |
4524 | #else | |
4525 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
0dd2d296 | 4526 | #endif |
19ed8960 ILT |
4527 | if (seg == now_seg) |
4528 | as_bad ("Can't use floating point insn in this section"); | |
4529 | ||
4530 | /* Set the argument to the current address in the | |
6e8dda9c | 4531 | section. */ |
19ed8960 ILT |
4532 | offset_expr.X_op = O_symbol; |
4533 | offset_expr.X_add_symbol = | |
4534 | symbol_new ("L0\001", now_seg, | |
4535 | (valueT) frag_now_fix (), frag_now); | |
4536 | offset_expr.X_add_number = 0; | |
4537 | ||
4538 | /* Put the floating point number into the section. */ | |
604633ae | 4539 | p = frag_more ((int) length); |
19ed8960 ILT |
4540 | memcpy (p, temp, length); |
4541 | ||
4542 | /* Switch back to the original section. */ | |
4543 | subseg_set (seg, subseg); | |
4544 | } | |
4545 | } | |
670a50eb ILT |
4546 | continue; |
4547 | ||
4548 | case 'i': /* 16 bit unsigned immediate */ | |
4549 | case 'j': /* 16 bit signed immediate */ | |
4550 | imm_reloc = BFD_RELOC_LO16; | |
4551 | c = my_getSmallExpression (&imm_expr, s); | |
4552 | if (c) | |
4553 | { | |
4554 | if (c != 'l') | |
4555 | { | |
5ac34ac3 | 4556 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
4557 | imm_expr.X_add_number = |
4558 | (imm_expr.X_add_number >> 16) & 0xffff; | |
4559 | else if (c == 'h') | |
4560 | imm_reloc = BFD_RELOC_HI16_S; | |
4561 | else | |
4562 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 4563 | } |
670a50eb ILT |
4564 | } |
4565 | else | |
4566 | check_absolute_expr (ip, &imm_expr); | |
4567 | if (*args == 'i') | |
4568 | { | |
6e8dda9c ILT |
4569 | if (imm_expr.X_add_number < 0 |
4570 | || imm_expr.X_add_number >= 0x10000) | |
99c24539 ILT |
4571 | { |
4572 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
4573 | !strcmp (insn->name, insn[1].name)) | |
4574 | break; | |
4575 | as_bad ("16 bit expression not in range 0..65535"); | |
4576 | } | |
670a50eb ILT |
4577 | } |
4578 | else | |
4579 | { | |
d9aba805 ILT |
4580 | int more; |
4581 | offsetT max; | |
4582 | ||
be22008b ILT |
4583 | /* The upper bound should be 0x8000, but |
4584 | unfortunately the MIPS assembler accepts numbers | |
4585 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
4586 | we want to be compatible. We only permit this |
4587 | extended range for an instruction which does not | |
4588 | provide any further alternates, since those | |
4589 | alternates may handle other cases. People should | |
4590 | use the numbers they mean, rather than relying on | |
4591 | a mysterious sign extension. */ | |
4592 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
4593 | strcmp (insn->name, insn[1].name) == 0); | |
4594 | if (more) | |
4595 | max = 0x8000; | |
4596 | else | |
4597 | max = 0x10000; | |
6e8dda9c | 4598 | if (imm_expr.X_add_number < -0x8000 || |
d9aba805 | 4599 | imm_expr.X_add_number >= max) |
99c24539 | 4600 | { |
d9aba805 | 4601 | if (more) |
99c24539 ILT |
4602 | break; |
4603 | as_bad ("16 bit expression not in range -32768..32767"); | |
4604 | } | |
3d3c5039 | 4605 | } |
670a50eb ILT |
4606 | s = expr_end; |
4607 | continue; | |
4608 | ||
4609 | case 'o': /* 16 bit offset */ | |
4610 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
4611 | |
4612 | /* If this value won't fit into a 16 bit offset, then go | |
4613 | find a macro that will generate the 32 bit offset | |
4614 | code pattern. As a special hack, we accept the | |
4615 | difference of two local symbols as a constant. This | |
4616 | is required to suppose embedded PIC switches, which | |
4617 | use an instruction which looks like | |
4618 | lw $4,$L12-$LS12($4) | |
4619 | The problem with handling this in a more general | |
4620 | fashion is that the macro function doesn't expect to | |
4621 | see anything which can be handled in a single | |
4622 | constant instruction. */ | |
4623 | if ((offset_expr.X_op != O_constant | |
4624 | || offset_expr.X_add_number >= 0x8000 | |
4625 | || offset_expr.X_add_number < -0x8000) | |
4626 | && (mips_pic != EMBEDDED_PIC | |
4627 | || offset_expr.X_op != O_subtract | |
4628 | || ! S_IS_LOCAL (offset_expr.X_add_symbol) | |
4629 | || ! S_IS_LOCAL (offset_expr.X_op_symbol))) | |
670a50eb | 4630 | break; |
3d3c5039 | 4631 | |
670a50eb ILT |
4632 | offset_reloc = BFD_RELOC_LO16; |
4633 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
4634 | { |
4635 | assert (offset_expr.X_op == O_constant); | |
4636 | offset_expr.X_add_number = | |
4637 | (offset_expr.X_add_number >> 16) & 0xffff; | |
4638 | } | |
670a50eb ILT |
4639 | s = expr_end; |
4640 | continue; | |
4641 | ||
4642 | case 'p': /* pc relative offset */ | |
4643 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
4644 | my_getExpression (&offset_expr, s); | |
4645 | s = expr_end; | |
4646 | continue; | |
4647 | ||
4648 | case 'u': /* upper 16 bits */ | |
4649 | c = my_getSmallExpression (&imm_expr, s); | |
36a87ad7 ILT |
4650 | if (imm_expr.X_op == O_constant |
4651 | && (imm_expr.X_add_number < 0 | |
4652 | || imm_expr.X_add_number >= 0x10000)) | |
670a50eb ILT |
4653 | as_bad ("lui expression not in range 0..65535"); |
4654 | imm_reloc = BFD_RELOC_LO16; | |
4655 | if (c) | |
4656 | { | |
4657 | if (c != 'l') | |
4658 | { | |
5ac34ac3 | 4659 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
4660 | imm_expr.X_add_number = |
4661 | (imm_expr.X_add_number >> 16) & 0xffff; | |
4662 | else if (c == 'h') | |
4663 | imm_reloc = BFD_RELOC_HI16_S; | |
4664 | else | |
4665 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 ILT |
4666 | } |
4667 | } | |
670a50eb ILT |
4668 | s = expr_end; |
4669 | continue; | |
3d3c5039 | 4670 | |
670a50eb ILT |
4671 | case 'a': /* 26 bit address */ |
4672 | my_getExpression (&offset_expr, s); | |
4673 | s = expr_end; | |
4674 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
4675 | continue; | |
3d3c5039 ILT |
4676 | |
4677 | default: | |
670a50eb ILT |
4678 | fprintf (stderr, "bad char = '%c'\n", *args); |
4679 | internalError (); | |
3d3c5039 | 4680 | } |
670a50eb | 4681 | break; |
3d3c5039 | 4682 | } |
670a50eb ILT |
4683 | /* Args don't match. */ |
4684 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
4685 | !strcmp (insn->name, insn[1].name)) | |
4686 | { | |
4687 | ++insn; | |
4688 | s = argsStart; | |
4689 | continue; | |
3d3c5039 | 4690 | } |
670a50eb ILT |
4691 | insn_error = "ERROR: Illegal operands"; |
4692 | return; | |
3d3c5039 ILT |
4693 | } |
4694 | } | |
4695 | ||
4696 | #define LP '(' | |
4697 | #define RP ')' | |
4698 | ||
4699 | static int | |
4700 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
4701 | expressionS *ep; |
4702 | char *str; | |
3d3c5039 | 4703 | { |
670a50eb ILT |
4704 | char *sp; |
4705 | int c = 0; | |
4706 | ||
4707 | if (*str == ' ') | |
4708 | str++; | |
4709 | if (*str == LP | |
4710 | || (*str == '%' && | |
4711 | ((str[1] == 'h' && str[2] == 'i') | |
4712 | || (str[1] == 'H' && str[2] == 'I') | |
4713 | || (str[1] == 'l' && str[2] == 'o')) | |
4714 | && str[3] == LP)) | |
4715 | { | |
4716 | if (*str == LP) | |
4717 | c = 0; | |
4718 | else | |
4719 | { | |
4720 | c = str[1]; | |
4721 | str += 3; | |
4722 | } | |
4723 | ||
4724 | /* | |
4725 | * A small expression may be followed by a base register. | |
4726 | * Scan to the end of this operand, and then back over a possible | |
4727 | * base register. Then scan the small expression up to that | |
4728 | * point. (Based on code in sparc.c...) | |
4729 | */ | |
4730 | for (sp = str; *sp && *sp != ','; sp++) | |
4731 | ; | |
4732 | if (sp - 4 >= str && sp[-1] == RP) | |
4733 | { | |
4734 | if (isdigit (sp[-2])) | |
4735 | { | |
4736 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
4737 | ; | |
4738 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
4739 | { | |
4740 | sp--; | |
4741 | goto do_it; | |
3d3c5039 | 4742 | } |
670a50eb ILT |
4743 | } |
4744 | else if (sp - 5 >= str | |
4745 | && sp[-5] == LP | |
4746 | && sp[-4] == '$' | |
4747 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
4748 | || (sp[-3] == 's' && sp[-2] == 'p') | |
4749 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
4750 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
4751 | { | |
4752 | sp -= 5; | |
3d3c5039 | 4753 | do_it: |
670a50eb ILT |
4754 | if (sp == str) |
4755 | { | |
4756 | /* no expression means zero offset */ | |
4757 | if (c) | |
4758 | { | |
4759 | /* %xx(reg) is an error */ | |
5ac34ac3 | 4760 | ep->X_op = O_absent; |
670a50eb | 4761 | expr_end = str - 3; |
3d3c5039 | 4762 | } |
670a50eb ILT |
4763 | else |
4764 | { | |
52aa70b5 | 4765 | ep->X_op = O_constant; |
670a50eb ILT |
4766 | expr_end = sp; |
4767 | } | |
4768 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 4769 | ep->X_op_symbol = NULL; |
670a50eb ILT |
4770 | ep->X_add_number = 0; |
4771 | } | |
4772 | else | |
4773 | { | |
4774 | *sp = '\0'; | |
4775 | my_getExpression (ep, str); | |
4776 | *sp = LP; | |
3d3c5039 | 4777 | } |
670a50eb | 4778 | return c; |
3d3c5039 ILT |
4779 | } |
4780 | } | |
4781 | } | |
670a50eb ILT |
4782 | my_getExpression (ep, str); |
4783 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
4784 | } |
4785 | ||
4786 | static void | |
4787 | my_getExpression (ep, str) | |
670a50eb ILT |
4788 | expressionS *ep; |
4789 | char *str; | |
3d3c5039 | 4790 | { |
670a50eb | 4791 | char *save_in; |
670a50eb ILT |
4792 | |
4793 | save_in = input_line_pointer; | |
4794 | input_line_pointer = str; | |
5ac34ac3 | 4795 | expression (ep); |
670a50eb ILT |
4796 | expr_end = input_line_pointer; |
4797 | input_line_pointer = save_in; | |
3d3c5039 ILT |
4798 | } |
4799 | ||
becfe05e ILT |
4800 | /* Turn a string in input_line_pointer into a floating point constant |
4801 | of type type, and store the appropriate bytes in *litP. The number | |
4802 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
4803 | returned, or NULL on OK. */ | |
4804 | ||
3d3c5039 | 4805 | char * |
670a50eb | 4806 | md_atof (type, litP, sizeP) |
becfe05e | 4807 | int type; |
3d3c5039 ILT |
4808 | char *litP; |
4809 | int *sizeP; | |
4810 | { | |
becfe05e ILT |
4811 | int prec; |
4812 | LITTLENUM_TYPE words[4]; | |
4813 | char *t; | |
4814 | int i; | |
4815 | ||
4816 | switch (type) | |
4817 | { | |
4818 | case 'f': | |
4819 | prec = 2; | |
4820 | break; | |
4821 | ||
4822 | case 'd': | |
4823 | prec = 4; | |
4824 | break; | |
4825 | ||
4826 | default: | |
4827 | *sizeP = 0; | |
4828 | return "bad call to md_atof"; | |
4829 | } | |
4830 | ||
4831 | t = atof_ieee (input_line_pointer, type, words); | |
4832 | if (t) | |
4833 | input_line_pointer = t; | |
4834 | ||
4835 | *sizeP = prec * 2; | |
4836 | ||
4837 | if (byte_order == LITTLE_ENDIAN) | |
4838 | { | |
4839 | for (i = prec - 1; i >= 0; i--) | |
4840 | { | |
4841 | md_number_to_chars (litP, (valueT) words[i], 2); | |
4842 | litP += 2; | |
4843 | } | |
4844 | } | |
4845 | else | |
4846 | { | |
4847 | for (i = 0; i < prec; i++) | |
4848 | { | |
4849 | md_number_to_chars (litP, (valueT) words[i], 2); | |
4850 | litP += 2; | |
4851 | } | |
4852 | } | |
4853 | ||
670a50eb | 4854 | return NULL; |
3d3c5039 ILT |
4855 | } |
4856 | ||
4857 | void | |
4858 | md_number_to_chars (buf, val, n) | |
4859 | char *buf; | |
918692a5 | 4860 | valueT val; |
3d3c5039 ILT |
4861 | int n; |
4862 | { | |
670a50eb ILT |
4863 | switch (byte_order) |
4864 | { | |
3d3c5039 | 4865 | case LITTLE_ENDIAN: |
13fe1379 ILT |
4866 | number_to_chars_littleendian (buf, val, n); |
4867 | break; | |
3d3c5039 ILT |
4868 | |
4869 | case BIG_ENDIAN: | |
13fe1379 ILT |
4870 | number_to_chars_bigendian (buf, val, n); |
4871 | break; | |
3d3c5039 ILT |
4872 | |
4873 | default: | |
670a50eb | 4874 | internalError (); |
3d3c5039 ILT |
4875 | } |
4876 | } | |
f3d817d8 DM |
4877 | \f |
4878 | #ifdef GPOPT | |
4879 | CONST char *md_shortopts = "E:O::g::G:"; | |
4880 | #else | |
4881 | CONST char *md_shortopts = "E:O::g::"; | |
4882 | #endif | |
4883 | struct option md_longopts[] = { | |
4884 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
4885 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
4886 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
4887 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
4888 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
4889 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
4890 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
4891 | #define OPTION_MCPU (OPTION_MD_BASE + 4) | |
4892 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
4893 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5) | |
4894 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, | |
4895 | #define OPTION_TRAP (OPTION_MD_BASE + 8) | |
4896 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
4897 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
4898 | #define OPTION_BREAK (OPTION_MD_BASE + 9) | |
4899 | {"break", no_argument, NULL, OPTION_BREAK}, | |
4900 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
4901 | ||
4902 | #ifdef OBJ_ELF | |
4903 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6) | |
4904 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, | |
4905 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
4906 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 7) | |
4907 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
4908 | #endif | |
4909 | ||
4910 | {NULL, no_argument, NULL, 0} | |
4911 | }; | |
4912 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
4913 | |
4914 | int | |
f3d817d8 DM |
4915 | md_parse_option (c, arg) |
4916 | int c; | |
4917 | char *arg; | |
3d3c5039 | 4918 | { |
f3d817d8 | 4919 | switch (c) |
670a50eb | 4920 | { |
f3d817d8 DM |
4921 | case OPTION_TRAP: |
4922 | mips_trap = 1; | |
4923 | break; | |
670a50eb | 4924 | |
f3d817d8 DM |
4925 | case OPTION_BREAK: |
4926 | mips_trap = 0; | |
4927 | break; | |
4928 | ||
4929 | case 'E': | |
4930 | if (arg[1] == 'B') | |
04cb3372 | 4931 | byte_order = BIG_ENDIAN; |
f3d817d8 | 4932 | else if (arg[1] == 'L') |
04cb3372 | 4933 | byte_order = LITTLE_ENDIAN; |
f3d817d8 DM |
4934 | else |
4935 | { | |
4936 | as_bad("invalid endianness -E%c", arg[1]); | |
4937 | return 0; | |
4938 | } | |
04cb3372 ILT |
4939 | |
4940 | #ifdef OBJ_AOUT | |
f3d817d8 | 4941 | if (arg[1] == 'B') |
04cb3372 ILT |
4942 | mips_target_format = "a.out-mips-big"; |
4943 | else | |
4944 | mips_target_format = "a.out-mips-little"; | |
4945 | #endif | |
4946 | #ifdef OBJ_ECOFF | |
f3d817d8 | 4947 | if (arg[1] == 'B') |
04cb3372 ILT |
4948 | mips_target_format = "ecoff-bigmips"; |
4949 | else | |
4950 | mips_target_format = "ecoff-littlemips"; | |
4951 | #endif | |
4952 | #ifdef OBJ_ELF | |
f3d817d8 | 4953 | if (arg[1] == 'B') |
04cb3372 ILT |
4954 | mips_target_format = "elf32-bigmips"; |
4955 | else | |
4956 | mips_target_format = "elf32-littlemips"; | |
4957 | #endif | |
4958 | ||
670a50eb | 4959 | /* FIXME: This breaks -L -EL. */ |
def66e24 | 4960 | flag_keep_locals = 0; |
f3d817d8 | 4961 | break; |
670a50eb | 4962 | |
f3d817d8 DM |
4963 | case 'O': |
4964 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
4965 | mips_optimize = 1; |
4966 | else | |
4967 | mips_optimize = 2; | |
f3d817d8 | 4968 | break; |
0aa07269 | 4969 | |
f3d817d8 DM |
4970 | case 'g': |
4971 | if (arg == NULL || arg[1] == '2') | |
0aa07269 | 4972 | mips_optimize = 0; |
f3d817d8 | 4973 | break; |
4e95866e | 4974 | |
f3d817d8 DM |
4975 | case OPTION_MIPS1: |
4976 | mips_isa = 1; | |
4977 | break; | |
8358c818 | 4978 | |
f3d817d8 DM |
4979 | case OPTION_MIPS2: |
4980 | mips_isa = 2; | |
4981 | break; | |
8358c818 | 4982 | |
f3d817d8 DM |
4983 | case OPTION_MIPS3: |
4984 | mips_isa = 3; | |
4985 | break; | |
8358c818 | 4986 | |
f3d817d8 DM |
4987 | case OPTION_MCPU: |
4988 | { | |
4989 | char *p; | |
4990 | ||
4991 | /* Identify the processor type */ | |
4992 | p = arg; | |
4993 | if (strcmp (p, "default") == 0 | |
4994 | || strcmp (p, "DEFAULT") == 0) | |
8358c818 | 4995 | mips_isa = -1; |
f3d817d8 DM |
4996 | else |
4997 | { | |
4998 | if (*p == 'r' || *p == 'R') | |
4999 | p++; | |
8358c818 | 5000 | |
f3d817d8 DM |
5001 | mips_isa = -1; |
5002 | switch (*p) | |
5003 | { | |
5004 | case '2': | |
5005 | if (strcmp (p, "2000") == 0 | |
5006 | || strcmp (p, "2k") == 0 | |
5007 | || strcmp (p, "2K") == 0) | |
5008 | mips_isa = 1; | |
5009 | break; | |
8358c818 | 5010 | |
f3d817d8 DM |
5011 | case '3': |
5012 | if (strcmp (p, "3000") == 0 | |
5013 | || strcmp (p, "3k") == 0 | |
5014 | || strcmp (p, "3K") == 0) | |
5015 | mips_isa = 1; | |
5016 | break; | |
8358c818 | 5017 | |
f3d817d8 DM |
5018 | case '4': |
5019 | if (strcmp (p, "4000") == 0 | |
5020 | || strcmp (p, "4k") == 0 | |
5021 | || strcmp (p, "4K") == 0) | |
5022 | mips_isa = 3; | |
5023 | break; | |
8358c818 | 5024 | |
f3d817d8 DM |
5025 | case '6': |
5026 | if (strcmp (p, "6000") == 0 | |
5027 | || strcmp (p, "6k") == 0 | |
5028 | || strcmp (p, "6K") == 0) | |
5029 | mips_isa = 2; | |
5030 | break; | |
5031 | } | |
8358c818 | 5032 | |
f3d817d8 DM |
5033 | if (mips_isa == -1) |
5034 | { | |
5035 | as_bad ("invalid architecture -mcpu=%s", arg); | |
5036 | return 0; | |
5037 | } | |
5038 | } | |
5039 | } | |
5040 | break; | |
8358c818 | 5041 | |
f3d817d8 | 5042 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 5043 | mips_pic = EMBEDDED_PIC; |
5b63f465 ILT |
5044 | #ifdef GPOPT |
5045 | if (g_switch_seen) | |
f3d817d8 DM |
5046 | { |
5047 | as_bad ("-G may not be used with embedded PIC code"); | |
5048 | return 0; | |
5049 | } | |
5b63f465 ILT |
5050 | g_switch_value = 0x7fffffff; |
5051 | #endif | |
f3d817d8 | 5052 | break; |
d9aba805 ILT |
5053 | |
5054 | #ifdef OBJ_ELF | |
5055 | /* When generating ELF code, we permit -KPIC and -call_shared to | |
5056 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
5057 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 5058 | case OPTION_CALL_SHARED: |
d9aba805 ILT |
5059 | mips_pic = SVR4_PIC; |
5060 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
5061 | { |
5062 | as_bad ("-G may not be used with SVR4 PIC code"); | |
5063 | return 0; | |
5064 | } | |
d9aba805 | 5065 | g_switch_value = 0; |
f3d817d8 DM |
5066 | break; |
5067 | ||
5068 | case OPTION_NON_SHARED: | |
d9aba805 | 5069 | mips_pic = NO_PIC; |
f3d817d8 | 5070 | break; |
d9aba805 | 5071 | #endif /* OBJ_ELF */ |
8358c818 | 5072 | |
88225433 | 5073 | #ifdef GPOPT |
f3d817d8 | 5074 | case 'G': |
5b63f465 | 5075 | if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) |
670a50eb | 5076 | { |
f3d817d8 DM |
5077 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
5078 | return 0; | |
670a50eb ILT |
5079 | } |
5080 | else | |
f3d817d8 | 5081 | g_switch_value = atoi (arg); |
42562568 | 5082 | g_switch_seen = 1; |
f3d817d8 | 5083 | break; |
670a50eb | 5084 | #endif |
4e95866e | 5085 | |
f3d817d8 DM |
5086 | default: |
5087 | return 0; | |
8ea7f4e8 ILT |
5088 | } |
5089 | ||
f3d817d8 | 5090 | return 1; |
8ea7f4e8 ILT |
5091 | } |
5092 | ||
f3d817d8 DM |
5093 | void |
5094 | md_show_usage (stream) | |
5095 | FILE *stream; | |
5096 | { | |
5097 | fprintf(stream, "\ | |
5098 | MIPS options:\n\ | |
5099 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
5100 | -EB generate big endian output\n\ |
5101 | -EL generate little endian output\n\ | |
5102 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
5103 | -G NUM allow referencing objects up to NUM bytes\n\ | |
5104 | implicitly with the gp register [default 8]\n\ | |
5105 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ | |
5106 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
5107 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
5108 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
5109 | -O remove unneeded NOPs and swap branches\n\ | |
5110 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
5111 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
5112 | #ifdef OBJ_ELF | |
5113 | fprintf(stream, "\ | |
5114 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
5115 | -non_shared do not generate position independent code\n"); | |
5116 | #endif | |
5117 | } | |
5118 | \f | |
3d3c5039 ILT |
5119 | long |
5120 | md_pcrel_from (fixP) | |
5121 | fixS *fixP; | |
5122 | { | |
5b63f465 ILT |
5123 | #ifndef OBJ_AOUT |
5124 | if (fixP->fx_addsy != (symbolS *) NULL | |
5125 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
5126 | { | |
5127 | /* This makes a branch to an undefined symbol be a branch to the | |
5128 | current location. */ | |
5129 | return 4; | |
5130 | } | |
5131 | #endif | |
5132 | ||
670a50eb ILT |
5133 | /* return the address of the delay slot */ |
5134 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
5135 | } |
5136 | ||
abdad6bc ILT |
5137 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
5138 | reloc for a cons. We could use the definition there, except that | |
5139 | we want to handle 64 bit relocs specially. */ | |
5140 | ||
5141 | void | |
5142 | cons_fix_new_mips (frag, where, nbytes, exp) | |
5143 | fragS *frag; | |
5144 | int where; | |
5145 | unsigned int nbytes; | |
5146 | expressionS *exp; | |
5147 | { | |
5148 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a | |
5149 | 4 byte reloc. | |
5150 | FIXME: There is no way to select anything but 32 bit mode right | |
5151 | now. */ | |
5152 | if (nbytes == 8) | |
5153 | { | |
5154 | if (byte_order == BIG_ENDIAN) | |
5155 | where += 4; | |
5156 | nbytes = 4; | |
5157 | } | |
5158 | ||
5159 | if (nbytes != 2 && nbytes != 4) | |
5160 | as_bad ("Unsupported reloc size %d", nbytes); | |
5161 | ||
5162 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
5163 | nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32); | |
5164 | } | |
5165 | ||
1c803e52 ILT |
5166 | /* When generating embedded PIC code we need to use a special |
5167 | relocation to represent the difference of two symbols in the .text | |
5168 | section (switch tables use a difference of this sort). See | |
5169 | include/coff/mips.h for details. This macro checks whether this | |
5170 | fixup requires the special reloc. */ | |
5171 | #define SWITCH_TABLE(fixp) \ | |
5172 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
5173 | && (fixp)->fx_addsy != NULL \ | |
5174 | && (fixp)->fx_subsy != NULL \ | |
5175 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
5176 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
5177 | ||
5b63f465 | 5178 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
5179 | relocations, in case the linker has to relax a call. We also need |
5180 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
5181 | |
5182 | /*ARGSUSED*/ | |
5183 | int | |
5184 | mips_force_relocation (fixp) | |
5185 | fixS *fixp; | |
5186 | { | |
1c803e52 | 5187 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
5188 | && (fixp->fx_pcrel |
5189 | || SWITCH_TABLE (fixp) | |
5190 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
5191 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
5192 | } |
5193 | ||
5194 | /* Apply a fixup to the object file. */ | |
5195 | ||
3d3c5039 ILT |
5196 | int |
5197 | md_apply_fix (fixP, valueP) | |
5198 | fixS *fixP; | |
918692a5 | 5199 | valueT *valueP; |
3d3c5039 | 5200 | { |
670a50eb ILT |
5201 | unsigned char *buf; |
5202 | long insn, value; | |
3d3c5039 | 5203 | |
670a50eb | 5204 | assert (fixP->fx_size == 4); |
3d3c5039 | 5205 | |
670a50eb ILT |
5206 | value = *valueP; |
5207 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
3d3c5039 | 5208 | |
5b63f465 ILT |
5209 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
5210 | fixP->fx_done = 1; | |
5211 | ||
670a50eb ILT |
5212 | switch (fixP->fx_r_type) |
5213 | { | |
3d3c5039 ILT |
5214 | case BFD_RELOC_MIPS_JMP: |
5215 | case BFD_RELOC_HI16: | |
5216 | case BFD_RELOC_HI16_S: | |
670a50eb | 5217 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
5218 | case BFD_RELOC_MIPS_LITERAL: |
5219 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
5220 | case BFD_RELOC_MIPS_GOT16: |
5221 | case BFD_RELOC_MIPS_GPREL32: | |
ecd4ca1c ILT |
5222 | if (fixP->fx_pcrel) |
5223 | as_bad ("Invalid PC relative reloc"); | |
670a50eb | 5224 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 5225 | break; |
3d3c5039 | 5226 | |
ecd4ca1c ILT |
5227 | case BFD_RELOC_PCREL_HI16_S: |
5228 | /* The addend for this is tricky if it is internal, so we just | |
5229 | do everything here rather than in bfd_perform_relocation. */ | |
5230 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
5231 | { | |
5232 | /* For an external symbol adjust by the address to make it | |
5233 | pcrel_offset. We use the address of the RELLO reloc | |
5234 | which follows this one. */ | |
5235 | value += (fixP->fx_next->fx_frag->fr_address | |
5236 | + fixP->fx_next->fx_where); | |
5237 | } | |
5238 | if (value & 0x8000) | |
5239 | value += 0x10000; | |
5240 | value >>= 16; | |
0221ddf7 | 5241 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
5242 | if (byte_order == BIG_ENDIAN) |
5243 | buf += 2; | |
5244 | md_number_to_chars (buf, value, 2); | |
5245 | break; | |
5246 | ||
5247 | case BFD_RELOC_PCREL_LO16: | |
5248 | /* The addend for this is tricky if it is internal, so we just | |
5249 | do everything here rather than in bfd_perform_relocation. */ | |
5250 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
5251 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 5252 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
5253 | if (byte_order == BIG_ENDIAN) |
5254 | buf += 2; | |
5255 | md_number_to_chars (buf, value, 2); | |
5256 | break; | |
5257 | ||
f3645945 ILT |
5258 | case BFD_RELOC_32: |
5259 | /* If we are deleting this reloc entry, we must fill in the | |
5260 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
5261 | resolved when it appears but is later defined. We also need |
5262 | to fill in the value if this is an embedded PIC switch table | |
5263 | entry. */ | |
5264 | if (fixP->fx_done | |
5265 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
5266 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5267 | value, 4); | |
5268 | break; | |
5269 | ||
5270 | case BFD_RELOC_LO16: | |
5271 | /* When handling an embedded PIC switch statement, we can wind | |
5272 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
5273 | if (fixP->fx_done) | |
5274 | { | |
5275 | if (value < -0x8000 || value > 0x7fff) | |
5276 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5277 | "relocation overflow"); | |
0221ddf7 | 5278 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
f3645945 ILT |
5279 | if (byte_order == BIG_ENDIAN) |
5280 | buf += 2; | |
5281 | md_number_to_chars (buf, value, 2); | |
5282 | } | |
5283 | break; | |
5284 | ||
3d3c5039 | 5285 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
5286 | /* |
5287 | * We need to save the bits in the instruction since fixup_segment() | |
5288 | * might be deleting the relocation entry (i.e., a branch within | |
5289 | * the current segment). | |
5290 | */ | |
5291 | if (value & 0x3) | |
58d4951d | 5292 | as_warn ("Branch to odd address (%lx)", value); |
670a50eb ILT |
5293 | value >>= 2; |
5294 | if ((value & ~0xFFFF) && (value & ~0xFFFF) != (-1 & ~0xFFFF)) | |
5295 | as_bad ("Relocation overflow"); | |
5296 | ||
5297 | /* update old instruction data */ | |
5298 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
5299 | switch (byte_order) | |
5300 | { | |
3d3c5039 | 5301 | case LITTLE_ENDIAN: |
670a50eb ILT |
5302 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; |
5303 | break; | |
3d3c5039 ILT |
5304 | |
5305 | case BIG_ENDIAN: | |
670a50eb ILT |
5306 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
5307 | break; | |
3d3c5039 ILT |
5308 | |
5309 | default: | |
670a50eb ILT |
5310 | internalError (); |
5311 | return 0; | |
3d3c5039 | 5312 | } |
670a50eb | 5313 | insn |= value & 0xFFFF; |
604633ae | 5314 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 5315 | break; |
3d3c5039 ILT |
5316 | |
5317 | default: | |
670a50eb | 5318 | internalError (); |
3d3c5039 | 5319 | } |
5b63f465 | 5320 | |
670a50eb | 5321 | return 1; |
3d3c5039 ILT |
5322 | } |
5323 | ||
5324 | #if 0 | |
5325 | void | |
670a50eb ILT |
5326 | printInsn (oc) |
5327 | unsigned long oc; | |
3d3c5039 | 5328 | { |
670a50eb ILT |
5329 | const struct mips_opcode *p; |
5330 | int treg, sreg, dreg, shamt; | |
5331 | short imm; | |
5332 | const char *args; | |
5333 | int i; | |
3d3c5039 | 5334 | |
670a50eb ILT |
5335 | for (i = 0; i < NUMOPCODES; ++i) |
5336 | { | |
5337 | p = &mips_opcodes[i]; | |
5338 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
5339 | { | |
5340 | printf ("%08lx %s\t", oc, p->name); | |
5341 | treg = (oc >> 16) & 0x1f; | |
5342 | sreg = (oc >> 21) & 0x1f; | |
5343 | dreg = (oc >> 11) & 0x1f; | |
5344 | shamt = (oc >> 6) & 0x1f; | |
5345 | imm = oc; | |
5346 | for (args = p->args;; ++args) | |
5347 | { | |
5348 | switch (*args) | |
5349 | { | |
3d3c5039 | 5350 | case '\0': |
670a50eb ILT |
5351 | printf ("\n"); |
5352 | break; | |
3d3c5039 ILT |
5353 | |
5354 | case ',': | |
5355 | case '(': | |
5356 | case ')': | |
670a50eb ILT |
5357 | printf ("%c", *args); |
5358 | continue; | |
3d3c5039 ILT |
5359 | |
5360 | case 'r': | |
670a50eb ILT |
5361 | assert (treg == sreg); |
5362 | printf ("$%d,$%d", treg, sreg); | |
5363 | continue; | |
3d3c5039 ILT |
5364 | |
5365 | case 'd': | |
918692a5 | 5366 | case 'G': |
670a50eb ILT |
5367 | printf ("$%d", dreg); |
5368 | continue; | |
3d3c5039 ILT |
5369 | |
5370 | case 't': | |
918692a5 | 5371 | case 'E': |
670a50eb ILT |
5372 | printf ("$%d", treg); |
5373 | continue; | |
3d3c5039 | 5374 | |
9226253a ILT |
5375 | case 'k': |
5376 | printf ("0x%x", treg); | |
5377 | continue; | |
5378 | ||
3d3c5039 ILT |
5379 | case 'b': |
5380 | case 's': | |
670a50eb ILT |
5381 | printf ("$%d", sreg); |
5382 | continue; | |
3d3c5039 ILT |
5383 | |
5384 | case 'a': | |
670a50eb ILT |
5385 | printf ("0x%08lx", oc & 0x1ffffff); |
5386 | continue; | |
3d3c5039 ILT |
5387 | |
5388 | case 'i': | |
5389 | case 'j': | |
5390 | case 'o': | |
5391 | case 'u': | |
670a50eb ILT |
5392 | printf ("%d", imm); |
5393 | continue; | |
3d3c5039 ILT |
5394 | |
5395 | case '<': | |
56c96faa | 5396 | case '>': |
670a50eb ILT |
5397 | printf ("$%d", shamt); |
5398 | continue; | |
3d3c5039 ILT |
5399 | |
5400 | default: | |
670a50eb | 5401 | internalError (); |
3d3c5039 | 5402 | } |
670a50eb | 5403 | break; |
3d3c5039 | 5404 | } |
670a50eb | 5405 | return; |
3d3c5039 ILT |
5406 | } |
5407 | } | |
670a50eb | 5408 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
5409 | } |
5410 | #endif | |
5411 | ||
5412 | static symbolS * | |
5413 | get_symbol () | |
5414 | { | |
670a50eb ILT |
5415 | int c; |
5416 | char *name; | |
5417 | symbolS *p; | |
5418 | ||
5419 | name = input_line_pointer; | |
5420 | c = get_symbol_end (); | |
5421 | p = (symbolS *) symbol_find_or_make (name); | |
5422 | *input_line_pointer = c; | |
5423 | return p; | |
3d3c5039 ILT |
5424 | } |
5425 | ||
becfe05e ILT |
5426 | /* Align the current frag to a given power of two. The MIPS assembler |
5427 | also automatically adjusts any preceding label. */ | |
5428 | ||
5429 | static void | |
23dc1ae3 | 5430 | mips_align (to, fill, label) |
becfe05e ILT |
5431 | int to; |
5432 | int fill; | |
23dc1ae3 | 5433 | symbolS *label; |
becfe05e ILT |
5434 | { |
5435 | mips_emit_delays (); | |
5436 | frag_align (to, fill); | |
5437 | record_alignment (now_seg, to); | |
23dc1ae3 | 5438 | if (label != NULL) |
becfe05e | 5439 | { |
23dc1ae3 ILT |
5440 | assert (S_GET_SEGMENT (label) == now_seg); |
5441 | label->sy_frag = frag_now; | |
5442 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
5443 | } |
5444 | } | |
5445 | ||
5446 | /* Align to a given power of two. .align 0 turns off the automatic | |
5447 | alignment used by the data creating pseudo-ops. */ | |
5448 | ||
3d3c5039 ILT |
5449 | static void |
5450 | s_align (x) | |
5451 | int x; | |
5452 | { | |
670a50eb ILT |
5453 | register int temp; |
5454 | register long temp_fill; | |
5455 | long max_alignment = 15; | |
3d3c5039 | 5456 | |
670a50eb | 5457 | /* |
3d3c5039 ILT |
5458 | |
5459 | o Note that the assembler pulls down any immediately preceeding label | |
5460 | to the aligned address. | |
5461 | o It's not documented but auto alignment is reinstated by | |
5462 | a .align pseudo instruction. | |
5463 | o Note also that after auto alignment is turned off the mips assembler | |
5464 | issues an error on attempt to assemble an improperly aligned data item. | |
5465 | We don't. | |
5466 | ||
5467 | */ | |
5468 | ||
670a50eb ILT |
5469 | temp = get_absolute_expression (); |
5470 | if (temp > max_alignment) | |
5471 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
5472 | else if (temp < 0) | |
5473 | { | |
5474 | as_warn ("Alignment negative: 0 assumed."); | |
5475 | temp = 0; | |
5476 | } | |
5477 | if (*input_line_pointer == ',') | |
5478 | { | |
5479 | input_line_pointer++; | |
5480 | temp_fill = get_absolute_expression (); | |
5481 | } | |
5482 | else | |
5483 | temp_fill = 0; | |
5484 | if (temp) | |
5485 | { | |
5486 | auto_align = 1; | |
23dc1ae3 | 5487 | mips_align (temp, (int) temp_fill, insn_label); |
3d3c5039 | 5488 | } |
670a50eb ILT |
5489 | else |
5490 | { | |
5491 | auto_align = 0; | |
3d3c5039 ILT |
5492 | } |
5493 | ||
670a50eb | 5494 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
5495 | } |
5496 | ||
becfe05e ILT |
5497 | /* Handle .ascii and .asciiz. This just calls stringer and forgets |
5498 | that there was a previous instruction. */ | |
5499 | ||
5500 | static void | |
5501 | s_stringer (append_zero) | |
5502 | int append_zero; | |
5503 | { | |
5504 | mips_emit_delays (); | |
1849d646 | 5505 | insn_label = NULL; |
becfe05e ILT |
5506 | stringer (append_zero); |
5507 | } | |
5508 | ||
3d3c5039 ILT |
5509 | static void |
5510 | s_change_sec (sec) | |
5511 | int sec; | |
5512 | { | |
88225433 ILT |
5513 | #ifdef GPOPT |
5514 | segT seg; | |
5515 | #endif | |
becfe05e | 5516 | |
5b63f465 ILT |
5517 | /* When generating embedded PIC code, we only use the .text, .lit8, |
5518 | .sdata and .sbss sections. We change the .data and .rdata | |
5519 | pseudo-ops to use .sdata. */ | |
5520 | if (mips_pic == EMBEDDED_PIC | |
5521 | && (sec == 'd' || sec == 'r')) | |
5522 | sec = 's'; | |
5523 | ||
becfe05e | 5524 | mips_emit_delays (); |
670a50eb ILT |
5525 | switch (sec) |
5526 | { | |
3d3c5039 | 5527 | case 't': |
604633ae | 5528 | s_text (0); |
670a50eb | 5529 | break; |
3d3c5039 | 5530 | case 'd': |
604633ae | 5531 | s_data (0); |
670a50eb | 5532 | break; |
3d3c5039 | 5533 | case 'b': |
670a50eb | 5534 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
5535 | demand_empty_rest_of_line (); |
5536 | break; | |
88225433 ILT |
5537 | |
5538 | case 'r': | |
d2c71068 ILT |
5539 | seg = subseg_new (RDATA_SECTION_NAME, |
5540 | (subsegT) get_absolute_expression ()); | |
88225433 | 5541 | #ifdef OBJ_ELF |
88225433 ILT |
5542 | bfd_set_section_flags (stdoutput, seg, |
5543 | (SEC_ALLOC | |
5544 | | SEC_LOAD | |
5545 | | SEC_READONLY | |
5546 | | SEC_RELOC | |
5547 | | SEC_DATA)); | |
0dd2d296 | 5548 | bfd_set_section_alignment (stdoutput, seg, 4); |
d2c71068 | 5549 | #endif |
88225433 ILT |
5550 | demand_empty_rest_of_line (); |
5551 | break; | |
88225433 ILT |
5552 | |
5553 | case 's': | |
5554 | #ifdef GPOPT | |
5555 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
5556 | #ifdef OBJ_ELF | |
5557 | bfd_set_section_flags (stdoutput, seg, | |
5558 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
0dd2d296 | 5559 | bfd_set_section_alignment (stdoutput, seg, 4); |
88225433 ILT |
5560 | #endif |
5561 | demand_empty_rest_of_line (); | |
5562 | break; | |
5563 | #else /* ! defined (GPOPT) */ | |
670a50eb | 5564 | as_bad ("Global pointers not supported; recompile -G 0"); |
becfe05e | 5565 | demand_empty_rest_of_line (); |
670a50eb | 5566 | return; |
88225433 | 5567 | #endif /* ! defined (GPOPT) */ |
3d3c5039 | 5568 | } |
88225433 | 5569 | |
670a50eb | 5570 | auto_align = 1; |
3d3c5039 ILT |
5571 | } |
5572 | ||
5573 | static void | |
5574 | s_cons (log_size) | |
5575 | int log_size; | |
5576 | { | |
23dc1ae3 ILT |
5577 | symbolS *label; |
5578 | ||
5579 | label = insn_label; | |
becfe05e | 5580 | mips_emit_delays (); |
670a50eb | 5581 | if (log_size > 0 && auto_align) |
23dc1ae3 | 5582 | mips_align (log_size, 0, label); |
1849d646 | 5583 | insn_label = NULL; |
670a50eb | 5584 | cons (1 << log_size); |
3d3c5039 ILT |
5585 | } |
5586 | ||
5587 | static void | |
5588 | s_err (x) | |
5589 | int x; | |
5590 | { | |
670a50eb | 5591 | as_fatal ("Encountered `.err', aborting assembly"); |
3d3c5039 ILT |
5592 | } |
5593 | ||
5594 | static void | |
5595 | s_extern (x) | |
5596 | int x; | |
5597 | { | |
604633ae | 5598 | valueT size; |
670a50eb ILT |
5599 | symbolS *symbolP; |
5600 | ||
5601 | symbolP = get_symbol (); | |
5602 | if (*input_line_pointer == ',') | |
5603 | input_line_pointer++; | |
5ac34ac3 | 5604 | size = get_absolute_expression (); |
670a50eb ILT |
5605 | S_SET_EXTERNAL (symbolP); |
5606 | ||
0dd2d296 | 5607 | #ifdef ECOFF_DEBUGGING |
8ea7f4e8 | 5608 | symbolP->ecoff_extern_size = size; |
670a50eb | 5609 | #endif |
3d3c5039 ILT |
5610 | } |
5611 | ||
5612 | static void | |
becfe05e ILT |
5613 | s_float_cons (type) |
5614 | int type; | |
3d3c5039 | 5615 | { |
23dc1ae3 ILT |
5616 | symbolS *label; |
5617 | ||
5618 | label = insn_label; | |
5619 | ||
becfe05e | 5620 | mips_emit_delays (); |
670a50eb ILT |
5621 | |
5622 | if (auto_align) | |
becfe05e | 5623 | if (type == 'd') |
23dc1ae3 | 5624 | mips_align (3, 0, label); |
670a50eb | 5625 | else |
23dc1ae3 | 5626 | mips_align (2, 0, label); |
670a50eb | 5627 | |
1849d646 ILT |
5628 | insn_label = NULL; |
5629 | ||
becfe05e | 5630 | float_cons (type); |
3d3c5039 ILT |
5631 | } |
5632 | ||
5633 | static void | |
5634 | s_option (x) | |
5635 | int x; | |
5636 | { | |
dd3f1f76 ILT |
5637 | char *opt; |
5638 | char c; | |
5639 | ||
5640 | opt = input_line_pointer; | |
5641 | c = get_symbol_end (); | |
5642 | ||
dd3f1f76 | 5643 | if (*opt == 'O') |
9226253a ILT |
5644 | { |
5645 | /* FIXME: What does this mean? */ | |
5646 | } | |
dd3f1f76 | 5647 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 5648 | { |
d9aba805 | 5649 | int i; |
42562568 | 5650 | |
d9aba805 ILT |
5651 | i = atoi (opt + 3); |
5652 | if (i == 0) | |
5653 | mips_pic = NO_PIC; | |
5654 | else if (i == 2) | |
5655 | mips_pic = SVR4_PIC; | |
5656 | else | |
5657 | as_bad (".option pic%d not supported", i); | |
5658 | ||
0221ddf7 | 5659 | #ifdef GPOPT |
d9aba805 | 5660 | if (mips_pic == SVR4_PIC) |
42562568 ILT |
5661 | { |
5662 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 5663 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
5664 | g_switch_value = 0; |
5665 | bfd_set_gp_size (stdoutput, 0); | |
5666 | } | |
0221ddf7 | 5667 | #endif |
9226253a | 5668 | } |
dd3f1f76 ILT |
5669 | else |
5670 | as_warn ("Unrecognized option \"%s\"", opt); | |
5671 | ||
5672 | *input_line_pointer = c; | |
670a50eb | 5673 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
5674 | } |
5675 | ||
5676 | static void | |
5677 | s_mipsset (x) | |
5678 | int x; | |
5679 | { | |
670a50eb ILT |
5680 | char *name = input_line_pointer, ch; |
5681 | ||
5682 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
5683 | input_line_pointer++; | |
5684 | ch = *input_line_pointer; | |
5685 | *input_line_pointer = '\0'; | |
5686 | ||
5687 | if (strcmp (name, "reorder") == 0) | |
5688 | { | |
4e95866e ILT |
5689 | if (mips_noreorder) |
5690 | { | |
5691 | prev_insn_unreordered = 1; | |
5692 | prev_prev_insn_unreordered = 1; | |
5693 | } | |
670a50eb ILT |
5694 | mips_noreorder = 0; |
5695 | } | |
5696 | else if (strcmp (name, "noreorder") == 0) | |
5697 | { | |
becfe05e | 5698 | mips_emit_delays (); |
670a50eb | 5699 | mips_noreorder = 1; |
0dd2d296 | 5700 | mips_any_noreorder = 1; |
670a50eb ILT |
5701 | } |
5702 | else if (strcmp (name, "at") == 0) | |
5703 | { | |
5704 | mips_noat = 0; | |
5705 | } | |
5706 | else if (strcmp (name, "noat") == 0) | |
5707 | { | |
5708 | mips_noat = 1; | |
3d3c5039 | 5709 | } |
670a50eb ILT |
5710 | else if (strcmp (name, "macro") == 0) |
5711 | { | |
5712 | mips_warn_about_macros = 0; | |
5713 | } | |
5714 | else if (strcmp (name, "nomacro") == 0) | |
5715 | { | |
5716 | if (mips_noreorder == 0) | |
5717 | as_bad ("`noreorder' must be set before `nomacro'"); | |
5718 | mips_warn_about_macros = 1; | |
5719 | } | |
5720 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
5721 | { | |
5722 | mips_nomove = 0; | |
5723 | } | |
5724 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
5725 | { | |
5726 | mips_nomove = 1; | |
5727 | } | |
5728 | else if (strcmp (name, "bopt") == 0) | |
5729 | { | |
5730 | mips_nobopt = 0; | |
5731 | } | |
5732 | else if (strcmp (name, "nobopt") == 0) | |
5733 | { | |
5734 | mips_nobopt = 1; | |
5735 | } | |
1051c97f ILT |
5736 | else if (strncmp (name, "mips", 4) == 0) |
5737 | { | |
5738 | int isa; | |
5739 | ||
5740 | /* Permit the user to change the ISA on the fly. Needless to | |
5741 | say, misuse can cause serious problems. */ | |
5742 | isa = atoi (name + 4); | |
5743 | if (isa == 0) | |
5744 | mips_isa = file_mips_isa; | |
5745 | else if (isa < 1 || isa > 3) | |
5746 | as_bad ("unknown ISA level"); | |
5747 | else | |
5748 | mips_isa = isa; | |
5749 | } | |
670a50eb ILT |
5750 | else |
5751 | { | |
5752 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
5753 | } | |
5754 | *input_line_pointer = ch; | |
5755 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
5756 | } |
5757 | ||
becfe05e ILT |
5758 | /* The same as the usual .space directive, except that we have to |
5759 | forget about any previous instruction. */ | |
5760 | ||
5761 | static void | |
5762 | s_mips_space (param) | |
5763 | int param; | |
5764 | { | |
5765 | mips_emit_delays (); | |
1849d646 | 5766 | insn_label = NULL; |
becfe05e ILT |
5767 | s_space (param); |
5768 | } | |
5769 | ||
9226253a ILT |
5770 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
5771 | .option pic2. It means to generate SVR4 PIC calls. */ | |
5772 | ||
5773 | static void | |
5774 | s_abicalls (ignore) | |
5775 | int ignore; | |
5776 | { | |
d9aba805 | 5777 | mips_pic = SVR4_PIC; |
0221ddf7 | 5778 | #ifdef GPOPT |
d9aba805 ILT |
5779 | if (g_switch_seen && g_switch_value != 0) |
5780 | as_warn ("-G may not be used with SVR4 PIC code"); | |
5781 | g_switch_value = 0; | |
0221ddf7 | 5782 | #endif |
d9aba805 | 5783 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
5784 | demand_empty_rest_of_line (); |
5785 | } | |
5786 | ||
5787 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
5788 | PIC code. It sets the $gp register for the function based on the | |
5789 | function address, which is in the register named in the argument. | |
5790 | This uses a relocation against _gp_disp, which is handled specially | |
5791 | by the linker. The result is: | |
5792 | lui $gp,%hi(_gp_disp) | |
5793 | addiu $gp,$gp,%lo(_gp_disp) | |
5794 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 5795 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
5796 | |
5797 | static void | |
5798 | s_cpload (ignore) | |
5799 | int ignore; | |
5800 | { | |
5801 | expressionS ex; | |
5802 | int icnt = 0; | |
5803 | ||
d9aba805 ILT |
5804 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
5805 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
5806 | { |
5807 | s_ignore (0); | |
5808 | return; | |
5809 | } | |
5810 | ||
5811 | /* .cpload should be a in .set noreorder section. */ | |
5812 | if (mips_noreorder == 0) | |
5813 | as_warn (".cpload not in noreorder section"); | |
5814 | ||
9226253a ILT |
5815 | ex.X_op = O_symbol; |
5816 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
5817 | ex.X_op_symbol = NULL; | |
5818 | ex.X_add_number = 0; | |
5819 | ||
0dd2d296 ILT |
5820 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
5821 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
5822 | (int) BFD_RELOC_LO16); |
5823 | ||
0dd2d296 ILT |
5824 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
5825 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
5826 | |
5827 | demand_empty_rest_of_line (); | |
5828 | } | |
5829 | ||
5830 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
5831 | offset from $sp. The offset is remembered, and after making a PIC | |
5832 | call $gp is restored from that location. */ | |
5833 | ||
5834 | static void | |
5835 | s_cprestore (ignore) | |
5836 | int ignore; | |
5837 | { | |
5838 | expressionS ex; | |
5839 | int icnt = 0; | |
5840 | ||
d9aba805 ILT |
5841 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
5842 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
5843 | { |
5844 | s_ignore (0); | |
5845 | return; | |
5846 | } | |
5847 | ||
9226253a ILT |
5848 | mips_cprestore_offset = get_absolute_expression (); |
5849 | ||
5850 | ex.X_op = O_constant; | |
5851 | ex.X_add_symbol = NULL; | |
5852 | ex.X_op_symbol = NULL; | |
5853 | ex.X_add_number = mips_cprestore_offset; | |
5854 | ||
0dd2d296 | 5855 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
5856 | mips_isa < 3 ? "sw" : "sd", |
5857 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
5858 | ||
5859 | demand_empty_rest_of_line (); | |
5860 | } | |
5861 | ||
0dd2d296 ILT |
5862 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
5863 | code. It generates a 32 bit GP relative reloc. */ | |
5864 | ||
5865 | static void | |
5866 | s_gpword (ignore) | |
5867 | int ignore; | |
5868 | { | |
23dc1ae3 | 5869 | symbolS *label; |
0dd2d296 ILT |
5870 | expressionS ex; |
5871 | char *p; | |
5872 | ||
5873 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 5874 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
5875 | { |
5876 | s_cons (2); | |
5877 | return; | |
5878 | } | |
5879 | ||
23dc1ae3 | 5880 | label = insn_label; |
0dd2d296 ILT |
5881 | mips_emit_delays (); |
5882 | if (auto_align) | |
23dc1ae3 | 5883 | mips_align (2, 0, label); |
0dd2d296 ILT |
5884 | insn_label = NULL; |
5885 | ||
5886 | expression (&ex); | |
5887 | ||
5888 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
5889 | { | |
5890 | as_bad ("Unsupported use of .gpword"); | |
5891 | ignore_rest_of_line (); | |
5892 | } | |
5893 | ||
5894 | p = frag_more (4); | |
5895 | md_number_to_chars (p, (valueT) 0, 4); | |
5896 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
5897 | BFD_RELOC_MIPS_GPREL32); | |
5898 | ||
5899 | demand_empty_rest_of_line (); | |
5900 | } | |
5901 | ||
5902 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
5903 | tables in SVR4 PIC code. */ | |
5904 | ||
5905 | static void | |
5906 | s_cpadd (ignore) | |
5907 | int ignore; | |
5908 | { | |
5909 | int icnt = 0; | |
5910 | int reg; | |
5911 | ||
5912 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 5913 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
5914 | { |
5915 | s_ignore (0); | |
5916 | return; | |
5917 | } | |
5918 | ||
5919 | /* Add $gp to the register named as an argument. */ | |
5920 | reg = tc_get_register (0); | |
5921 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5922 | mips_isa < 3 ? "addu" : "daddu", | |
5923 | "d,v,t", reg, reg, GP); | |
5924 | ||
5925 | demand_empty_rest_of_line (); | |
5926 | } | |
5927 | ||
9226253a | 5928 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
5929 | to parse .frame. The argument is non-zero if this is the frame |
5930 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 5931 | |
3d3c5039 | 5932 | int |
0dd2d296 ILT |
5933 | tc_get_register (frame) |
5934 | int frame; | |
3d3c5039 ILT |
5935 | { |
5936 | int reg; | |
5937 | ||
5938 | SKIP_WHITESPACE (); | |
5939 | if (*input_line_pointer++ != '$') | |
5940 | { | |
5941 | as_warn ("expected `$'"); | |
0dd2d296 | 5942 | reg = 0; |
3d3c5039 | 5943 | } |
0dd2d296 | 5944 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
5945 | { |
5946 | reg = get_absolute_expression (); | |
5947 | if (reg < 0 || reg >= 32) | |
5948 | { | |
5949 | as_warn ("Bad register number"); | |
5950 | reg = 0; | |
5951 | } | |
5952 | } | |
5953 | else | |
5954 | { | |
5955 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 5956 | reg = FP; |
3d3c5039 | 5957 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 5958 | reg = SP; |
3d3c5039 | 5959 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 5960 | reg = GP; |
3d3c5039 | 5961 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 5962 | reg = AT; |
3d3c5039 ILT |
5963 | else |
5964 | { | |
5965 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 5966 | reg = 0; |
3d3c5039 ILT |
5967 | } |
5968 | input_line_pointer += 2; | |
5969 | } | |
0dd2d296 ILT |
5970 | if (frame) |
5971 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
5972 | return reg; |
5973 | } | |
5974 | ||
0dd2d296 ILT |
5975 | valueT |
5976 | md_section_align (seg, addr) | |
5977 | asection *seg; | |
5978 | valueT addr; | |
5979 | { | |
5980 | int align = bfd_get_section_alignment (stdoutput, seg); | |
5981 | ||
5982 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
5983 | } | |
5984 | ||
5985 | /* Estimate the size of a frag before relaxing. We are not really | |
5986 | relaxing here, and the final size is encoded in the subtype | |
5987 | information. */ | |
5988 | ||
5989 | /*ARGSUSED*/ | |
5990 | int | |
5991 | md_estimate_size_before_relax (fragp, segtype) | |
5992 | fragS *fragp; | |
5993 | asection *segtype; | |
5994 | { | |
5995 | int change; | |
5996 | ||
d9aba805 | 5997 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
5998 | { |
5999 | #ifdef GPOPT | |
6000 | const char *symname; | |
6001 | ||
6002 | /* Find out whether this symbol can be referenced off the GP | |
6003 | register. It can be if it is smaller than the -G size or if | |
6004 | it is in the .sdata or .sbss section. Certain symbols can | |
6005 | not be referenced off the GP, although it appears as though | |
6006 | they can. */ | |
6007 | symname = S_GET_NAME (fragp->fr_symbol); | |
6008 | if (symname != (const char *) NULL | |
6009 | && (strcmp (symname, "eprol") == 0 | |
6010 | || strcmp (symname, "etext") == 0 | |
6011 | || strcmp (symname, "_gp") == 0 | |
6012 | || strcmp (symname, "edata") == 0 | |
6013 | || strcmp (symname, "_fbss") == 0 | |
6014 | || strcmp (symname, "_fdata") == 0 | |
6015 | || strcmp (symname, "_ftext") == 0 | |
6016 | || strcmp (symname, "end") == 0 | |
6017 | || strcmp (symname, "_gp_disp") == 0)) | |
6018 | change = 1; | |
6019 | else if (! S_IS_DEFINED (fragp->fr_symbol) | |
8ea7f4e8 ILT |
6020 | && ((fragp->fr_symbol->ecoff_extern_size != 0 |
6021 | && fragp->fr_symbol->ecoff_extern_size <= g_switch_value) | |
6022 | || (S_GET_VALUE (fragp->fr_symbol) != 0 | |
6023 | && S_GET_VALUE (fragp->fr_symbol) <= g_switch_value))) | |
0dd2d296 ILT |
6024 | change = 0; |
6025 | else | |
6026 | { | |
6027 | const char *segname; | |
6028 | ||
6029 | segname = segment_name (S_GET_SEGMENT (fragp->fr_symbol)); | |
6030 | assert (strcmp (segname, ".lit8") != 0 | |
6031 | && strcmp (segname, ".lit4") != 0); | |
6032 | change = (strcmp (segname, ".sdata") != 0 | |
6033 | && strcmp (segname, ".sbss") != 0); | |
6034 | } | |
6035 | #else /* ! defined (GPOPT) */ | |
6036 | /* We are not optimizing for the GP register. */ | |
6037 | change = 1; | |
6038 | #endif /* ! defined (GPOPT) */ | |
6039 | } | |
d9aba805 | 6040 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
6041 | { |
6042 | asection *symsec = fragp->fr_symbol->bsym->section; | |
6043 | ||
6044 | /* This must duplicate the test in adjust_reloc_syms. */ | |
6045 | change = (symsec != &bfd_und_section | |
6046 | && symsec != &bfd_abs_section | |
6047 | && ! bfd_is_com_section (symsec)); | |
6048 | } | |
d9aba805 ILT |
6049 | else |
6050 | abort (); | |
0dd2d296 ILT |
6051 | |
6052 | if (change) | |
6053 | { | |
6054 | /* Record the offset to the first reloc in the fr_opcode field. | |
6055 | This lets md_convert_frag and tc_gen_reloc know that the code | |
6056 | must be expanded. */ | |
6057 | fragp->fr_opcode = (fragp->fr_literal | |
6058 | + fragp->fr_fix | |
6059 | - RELAX_OLD (fragp->fr_subtype) | |
6060 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
6061 | /* FIXME: This really needs as_warn_where. */ | |
6062 | if (RELAX_WARN (fragp->fr_subtype)) | |
6063 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
6064 | } | |
6065 | ||
6066 | if (! change) | |
6067 | return 0; | |
6068 | else | |
6069 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
6070 | } | |
6071 | ||
6072 | /* Translate internal representation of relocation info to BFD target | |
6073 | format. */ | |
6074 | ||
6075 | arelent ** | |
3d3c5039 ILT |
6076 | tc_gen_reloc (section, fixp) |
6077 | asection *section; | |
6078 | fixS *fixp; | |
6079 | { | |
0dd2d296 | 6080 | static arelent *retval[4]; |
3d3c5039 ILT |
6081 | arelent *reloc; |
6082 | ||
0dd2d296 ILT |
6083 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
6084 | retval[1] = NULL; | |
3d3c5039 ILT |
6085 | |
6086 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
6087 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
6088 | |
6089 | if (mips_pic == EMBEDDED_PIC | |
6090 | && SWITCH_TABLE (fixp)) | |
6091 | { | |
6092 | /* For a switch table entry we use a special reloc. The addend | |
6093 | is actually the difference between the reloc address and the | |
6094 | subtrahend. */ | |
6095 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
6096 | #ifndef OBJ_ECOFF | |
ecd4ca1c | 6097 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); |
1c803e52 ILT |
6098 | #endif |
6099 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
6100 | } | |
ecd4ca1c ILT |
6101 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
6102 | { | |
6103 | /* We use a special addend for an internal RELLO reloc. */ | |
6104 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
6105 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
6106 | else | |
6107 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
6108 | } | |
6109 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
6110 | { | |
6111 | assert (fixp->fx_next != NULL | |
6112 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
6113 | /* We use a special addend for an internal RELHI reloc. The | |
6114 | reloc is relative to the RELLO; adjust the addend | |
6115 | accordingly. */ | |
6116 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
6117 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
6118 | + fixp->fx_next->fx_where | |
6119 | - S_GET_VALUE (fixp->fx_subsy)); | |
6120 | else | |
6121 | reloc->addend = (fixp->fx_addnumber | |
6122 | + fixp->fx_next->fx_frag->fr_address | |
6123 | + fixp->fx_next->fx_where); | |
6124 | } | |
1c803e52 | 6125 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
6126 | reloc->addend = fixp->fx_addnumber; |
6127 | else | |
5b63f465 | 6128 | { |
d9aba805 | 6129 | #ifndef OBJ_AOUT |
5b63f465 ILT |
6130 | /* A gruesome hack which is a result of the gruesome gas reloc |
6131 | handling. */ | |
6132 | reloc->addend = reloc->address; | |
3d3c5039 | 6133 | #else |
5b63f465 | 6134 | reloc->addend = -reloc->address; |
3d3c5039 | 6135 | #endif |
5b63f465 | 6136 | } |
0dd2d296 ILT |
6137 | |
6138 | /* If this is a variant frag, we may need to adjust the existing | |
6139 | reloc and generate a new one. */ | |
6140 | if (fixp->fx_frag->fr_opcode != NULL | |
6141 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
6142 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
6143 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16)) | |
6144 | { | |
6145 | arelent *reloc2; | |
6146 | ||
6147 | /* If this is not the last reloc in this frag, then we have two | |
6148 | GPREL relocs, both of which are being replaced. Let the | |
6149 | second one handle all of them. */ | |
6150 | if (fixp->fx_next != NULL | |
6151 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
6152 | { | |
6153 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
6154 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
6155 | retval[0] = NULL; | |
6156 | return retval; | |
6157 | } | |
6158 | ||
6159 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
6160 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
6161 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
6162 | retval[2] = NULL; | |
6163 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
6164 | reloc2->address = (reloc->address | |
6165 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
6166 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
6167 | reloc2->addend = fixp->fx_addnumber; | |
6168 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
6169 | assert (reloc2->howto != NULL); | |
6170 | ||
6171 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
6172 | { | |
6173 | arelent *reloc3; | |
6174 | ||
6175 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
6176 | retval[3] = NULL; | |
6177 | *reloc3 = *reloc2; | |
6178 | reloc3->address += 4; | |
6179 | } | |
6180 | ||
d9aba805 | 6181 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
6182 | { |
6183 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
6184 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
6185 | } | |
d9aba805 | 6186 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
6187 | { |
6188 | if (fixp->fx_r_type != BFD_RELOC_MIPS_GOT16) | |
6189 | { | |
6190 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_CALL16); | |
6191 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
6192 | } | |
6193 | } | |
d9aba805 ILT |
6194 | else |
6195 | abort (); | |
0dd2d296 ILT |
6196 | } |
6197 | ||
d9aba805 ILT |
6198 | /* To support a PC relative reloc when generating embedded PIC code |
6199 | for ECOFF, we use a Cygnus extension. We check for that here to | |
6200 | make sure that we don't let such a reloc escape normally. */ | |
6201 | #ifdef OBJ_ECOFF | |
6202 | if (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
6203 | && mips_pic != EMBEDDED_PIC) | |
6204 | reloc->howto = NULL; | |
6205 | else | |
6206 | #endif | |
6207 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
0dd2d296 | 6208 | |
52aa70b5 JW |
6209 | if (reloc->howto == NULL) |
6210 | { | |
6211 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
6212 | "Can not represent relocation in this object file format"); | |
0dd2d296 | 6213 | retval[0] = NULL; |
52aa70b5 | 6214 | } |
3d3c5039 | 6215 | |
0dd2d296 | 6216 | return retval; |
3d3c5039 ILT |
6217 | } |
6218 | ||
0dd2d296 ILT |
6219 | /* Convert a machine dependent frag. */ |
6220 | ||
6221 | void | |
6222 | md_convert_frag (abfd, asec, fragp) | |
6223 | bfd *abfd; | |
6224 | segT asec; | |
6225 | fragS *fragp; | |
3d3c5039 | 6226 | { |
0dd2d296 ILT |
6227 | int old, new; |
6228 | char *fixptr; | |
3d3c5039 | 6229 | |
0dd2d296 ILT |
6230 | if (fragp->fr_opcode == NULL) |
6231 | return; | |
3d3c5039 | 6232 | |
0dd2d296 ILT |
6233 | old = RELAX_OLD (fragp->fr_subtype); |
6234 | new = RELAX_NEW (fragp->fr_subtype); | |
6235 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
6236 | ||
6237 | if (new > 0) | |
6238 | memcpy (fixptr - old, fixptr, new); | |
6239 | ||
6240 | fragp->fr_fix += new - old; | |
6241 | } | |
becfe05e ILT |
6242 | |
6243 | /* This function is called whenever a label is defined. It is used | |
6244 | when handling branch delays; if a branch has a label, we assume we | |
6245 | can not move it. */ | |
6246 | ||
6247 | void | |
6248 | mips_define_label (sym) | |
6249 | symbolS *sym; | |
6250 | { | |
6251 | insn_label = sym; | |
6252 | } | |
3d3c5039 | 6253 | \f |
f2a663d3 ILT |
6254 | #ifdef OBJ_ELF |
6255 | ||
0dd2d296 | 6256 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
6257 | |
6258 | void | |
6259 | mips_elf_final_processing () | |
6260 | { | |
6261 | Elf32_RegInfo s; | |
6262 | ||
0dd2d296 | 6263 | /* Write out the .reginfo section. */ |
f2a663d3 ILT |
6264 | s.ri_gprmask = mips_gprmask; |
6265 | s.ri_cprmask[0] = mips_cprmask[0]; | |
6266 | s.ri_cprmask[1] = mips_cprmask[1]; | |
6267 | s.ri_cprmask[2] = mips_cprmask[2]; | |
6268 | s.ri_cprmask[3] = mips_cprmask[3]; | |
6269 | /* The gp_value field is set by the MIPS ELF backend. */ | |
6270 | ||
6271 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
6272 | ((Elf32_External_RegInfo *) | |
6273 | mips_regmask_frag)); | |
0dd2d296 ILT |
6274 | |
6275 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
6276 | sort of BFD interface for this. */ | |
6277 | if (mips_any_noreorder) | |
6278 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 6279 | if (mips_pic != NO_PIC) |
0dd2d296 | 6280 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
6281 | } |
6282 | ||
6283 | #endif /* OBJ_ELF */ | |
6284 | \f | |
0dd2d296 | 6285 | #ifndef ECOFF_DEBUGGING |
3d3c5039 ILT |
6286 | |
6287 | /* These functions should really be defined by the object file format, | |
6288 | since they are related to debugging information. However, this | |
6289 | code has to work for the a.out format, which does not define them, | |
6290 | so we provide simple versions here. These don't actually generate | |
6291 | any debugging information, but they do simple checking and someday | |
6292 | somebody may make them useful. */ | |
6293 | ||
670a50eb ILT |
6294 | typedef struct loc |
6295 | { | |
6296 | struct loc *loc_next; | |
6297 | unsigned long loc_fileno; | |
6298 | unsigned long loc_lineno; | |
6299 | unsigned long loc_offset; | |
6300 | unsigned short loc_delta; | |
6301 | unsigned short loc_count; | |
3d3c5039 | 6302 | #if 0 |
670a50eb | 6303 | fragS *loc_frag; |
3d3c5039 | 6304 | #endif |
670a50eb ILT |
6305 | } |
6306 | locS; | |
3d3c5039 | 6307 | |
670a50eb ILT |
6308 | typedef struct proc |
6309 | { | |
3d3c5039 ILT |
6310 | struct proc *proc_next; |
6311 | struct symbol *proc_isym; | |
6312 | struct symbol *proc_end; | |
6313 | unsigned long proc_reg_mask; | |
6314 | unsigned long proc_reg_offset; | |
6315 | unsigned long proc_fpreg_mask; | |
6316 | unsigned long proc_fpreg_offset; | |
6317 | unsigned long proc_frameoffset; | |
6318 | unsigned long proc_framereg; | |
6319 | unsigned long proc_pcreg; | |
6320 | locS *proc_iline; | |
6321 | struct file *proc_file; | |
6322 | int proc_index; | |
670a50eb ILT |
6323 | } |
6324 | procS; | |
3d3c5039 | 6325 | |
670a50eb ILT |
6326 | typedef struct file |
6327 | { | |
3d3c5039 ILT |
6328 | struct file *file_next; |
6329 | unsigned long file_fileno; | |
6330 | struct symbol *file_symbol; | |
6331 | struct symbol *file_end; | |
6332 | struct proc *file_proc; | |
6333 | int file_numprocs; | |
670a50eb ILT |
6334 | } |
6335 | fileS; | |
3d3c5039 ILT |
6336 | |
6337 | static struct obstack proc_frags; | |
6338 | static procS *proc_lastP; | |
6339 | static procS *proc_rootP; | |
6340 | static int numprocs; | |
6341 | ||
6342 | static void | |
6343 | md_obj_begin () | |
6344 | { | |
670a50eb | 6345 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
6346 | } |
6347 | ||
6348 | static void | |
6349 | md_obj_end () | |
6350 | { | |
6351 | /* check for premature end, nesting errors, etc */ | |
6352 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 6353 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
6354 | } |
6355 | ||
6356 | extern char hex_value[]; | |
6357 | ||
6358 | static long | |
6359 | get_number () | |
6360 | { | |
670a50eb ILT |
6361 | int negative = 0; |
6362 | long val = 0; | |
3d3c5039 | 6363 | |
670a50eb ILT |
6364 | if (*input_line_pointer == '-') |
6365 | { | |
6366 | ++input_line_pointer; | |
6367 | negative = 1; | |
3d3c5039 | 6368 | } |
670a50eb ILT |
6369 | if (!isdigit (*input_line_pointer)) |
6370 | as_bad ("Expected simple number."); | |
6371 | if (input_line_pointer[0] == '0') | |
6372 | { | |
6373 | if (input_line_pointer[1] == 'x') | |
6374 | { | |
6375 | input_line_pointer += 2; | |
6376 | while (isxdigit (*input_line_pointer)) | |
6377 | { | |
6378 | val <<= 4; | |
6379 | val |= hex_value[(int) *input_line_pointer++]; | |
3d3c5039 | 6380 | } |
670a50eb ILT |
6381 | return negative ? -val : val; |
6382 | } | |
6383 | else | |
6384 | { | |
6385 | ++input_line_pointer; | |
6386 | while (isdigit (*input_line_pointer)) | |
6387 | { | |
6388 | val <<= 3; | |
6389 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 6390 | } |
670a50eb | 6391 | return negative ? -val : val; |
3d3c5039 ILT |
6392 | } |
6393 | } | |
670a50eb ILT |
6394 | if (!isdigit (*input_line_pointer)) |
6395 | { | |
6396 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
6397 | *input_line_pointer, *input_line_pointer); | |
6398 | as_warn ("Invalid number"); | |
6399 | return -1; | |
3d3c5039 | 6400 | } |
670a50eb ILT |
6401 | while (isdigit (*input_line_pointer)) |
6402 | { | |
6403 | val *= 10; | |
6404 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 6405 | } |
670a50eb | 6406 | return negative ? -val : val; |
3d3c5039 ILT |
6407 | } |
6408 | ||
6409 | /* The .file directive; just like the usual .file directive, but there | |
6410 | is an initial number which is the ECOFF file index. */ | |
6411 | ||
6412 | static void | |
6413 | s_file (x) | |
6414 | int x; | |
6415 | { | |
670a50eb | 6416 | int line; |
3d3c5039 | 6417 | |
670a50eb | 6418 | line = get_number (); |
9a7d824a | 6419 | s_app_file (0); |
3d3c5039 ILT |
6420 | } |
6421 | ||
6422 | ||
6423 | /* The .end directive. */ | |
6424 | ||
6425 | static void | |
6426 | s_mipsend (x) | |
6427 | int x; | |
6428 | { | |
670a50eb ILT |
6429 | symbolS *p; |
6430 | ||
6431 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
6432 | { | |
6433 | p = get_symbol (); | |
6434 | demand_empty_rest_of_line (); | |
6435 | } | |
6436 | else | |
6437 | p = NULL; | |
6438 | if (now_seg != text_section) | |
6439 | as_warn (".end not in text section"); | |
6440 | if (!proc_lastP) | |
6441 | { | |
6442 | as_warn (".end and no .ent seen yet."); | |
6443 | return; | |
3d3c5039 ILT |
6444 | } |
6445 | ||
670a50eb ILT |
6446 | if (p != NULL) |
6447 | { | |
6448 | assert (S_GET_NAME (p)); | |
6449 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
6450 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
6451 | } |
6452 | ||
670a50eb | 6453 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
6454 | } |
6455 | ||
6456 | /* The .aent and .ent directives. */ | |
6457 | ||
6458 | static void | |
6459 | s_ent (aent) | |
6460 | int aent; | |
6461 | { | |
670a50eb ILT |
6462 | int number = 0; |
6463 | procS *procP; | |
6464 | symbolS *symbolP; | |
6465 | ||
6466 | symbolP = get_symbol (); | |
6467 | if (*input_line_pointer == ',') | |
6468 | input_line_pointer++; | |
dd3f1f76 | 6469 | SKIP_WHITESPACE (); |
670a50eb ILT |
6470 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
6471 | number = get_number (); | |
6472 | if (now_seg != text_section) | |
6473 | as_warn (".ent or .aent not in text section."); | |
6474 | ||
6475 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
6476 | as_warn ("missing `.end'"); | |
6477 | ||
6478 | if (!aent) | |
6479 | { | |
6480 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
6481 | procP->proc_isym = symbolP; | |
6482 | procP->proc_reg_mask = 0; | |
6483 | procP->proc_reg_offset = 0; | |
6484 | procP->proc_fpreg_mask = 0; | |
6485 | procP->proc_fpreg_offset = 0; | |
6486 | procP->proc_frameoffset = 0; | |
6487 | procP->proc_framereg = 0; | |
6488 | procP->proc_pcreg = 0; | |
6489 | procP->proc_end = NULL; | |
6490 | procP->proc_next = NULL; | |
6491 | if (proc_lastP) | |
6492 | proc_lastP->proc_next = procP; | |
6493 | else | |
6494 | proc_rootP = procP; | |
6495 | proc_lastP = procP; | |
6496 | numprocs++; | |
3d3c5039 | 6497 | } |
670a50eb | 6498 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
6499 | } |
6500 | ||
6501 | /* The .frame directive. */ | |
6502 | ||
88225433 | 6503 | #if 0 |
3d3c5039 ILT |
6504 | static void |
6505 | s_frame (x) | |
670a50eb | 6506 | int x; |
3d3c5039 | 6507 | { |
670a50eb ILT |
6508 | char str[100]; |
6509 | symbolS *symP; | |
6510 | int frame_reg; | |
6511 | int frame_off; | |
6512 | int pcreg; | |
6513 | ||
0dd2d296 | 6514 | frame_reg = tc_get_register (1); |
670a50eb ILT |
6515 | if (*input_line_pointer == ',') |
6516 | input_line_pointer++; | |
5ac34ac3 | 6517 | frame_off = get_absolute_expression (); |
670a50eb ILT |
6518 | if (*input_line_pointer == ',') |
6519 | input_line_pointer++; | |
0dd2d296 | 6520 | pcreg = tc_get_register (0); |
670a50eb ILT |
6521 | |
6522 | /* bob third eye */ | |
6523 | assert (proc_rootP); | |
6524 | proc_rootP->proc_framereg = frame_reg; | |
6525 | proc_rootP->proc_frameoffset = frame_off; | |
6526 | proc_rootP->proc_pcreg = pcreg; | |
6527 | /* bob macho .frame */ | |
6528 | ||
6529 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 6530 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
6531 | { |
6532 | if (!proc_lastP) | |
6533 | as_warn ("No .ent for .frame to use."); | |
6534 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
6535 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
6536 | S_SET_TYPE (symP, N_RMASK); | |
6537 | S_SET_OTHER (symP, 0); | |
6538 | S_SET_DESC (symP, 0); | |
6539 | symP->sy_forward = proc_lastP->proc_isym; | |
6540 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 6541 | } |
670a50eb | 6542 | demand_empty_rest_of_line (); |
3d3c5039 | 6543 | } |
88225433 | 6544 | #endif |
3d3c5039 ILT |
6545 | |
6546 | /* The .fmask and .mask directives. */ | |
6547 | ||
88225433 | 6548 | #if 0 |
3d3c5039 ILT |
6549 | static void |
6550 | s_mask (reg_type) | |
6551 | char reg_type; | |
6552 | { | |
670a50eb ILT |
6553 | char str[100], *strP; |
6554 | symbolS *symP; | |
6555 | int i; | |
6556 | unsigned int mask; | |
6557 | int off; | |
6558 | ||
6559 | mask = get_number (); | |
6560 | if (*input_line_pointer == ',') | |
6561 | input_line_pointer++; | |
6562 | off = get_absolute_expression (); | |
6563 | ||
6564 | /* bob only for coff */ | |
6565 | assert (proc_rootP); | |
6566 | if (reg_type == 'F') | |
6567 | { | |
6568 | proc_rootP->proc_fpreg_mask = mask; | |
6569 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 6570 | } |
670a50eb ILT |
6571 | else |
6572 | { | |
6573 | proc_rootP->proc_reg_mask = mask; | |
6574 | proc_rootP->proc_reg_offset = off; | |
6575 | } | |
6576 | ||
6577 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 6578 | |
670a50eb ILT |
6579 | /* We don't have to write out a mask stab if no saved regs. */ |
6580 | if (!(mask == 0)) | |
6581 | { | |
6582 | if (!proc_lastP) | |
6583 | as_warn ("No .ent for .mask to use."); | |
6584 | strP = str; | |
6585 | for (i = 0; i < 32; i++) | |
6586 | { | |
6587 | if (mask % 2) | |
6588 | { | |
6589 | sprintf (strP, "%c%d,", reg_type, i); | |
6590 | strP += strlen (strP); | |
6591 | } | |
3d3c5039 | 6592 | mask /= 2; |
670a50eb ILT |
6593 | } |
6594 | sprintf (strP, ";%d,", off); | |
6595 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
6596 | S_SET_TYPE (symP, N_RMASK); | |
6597 | S_SET_OTHER (symP, 0); | |
6598 | S_SET_DESC (symP, 0); | |
6599 | symP->sy_forward = proc_lastP->proc_isym; | |
6600 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 6601 | } |
3d3c5039 | 6602 | } |
88225433 | 6603 | #endif |
3d3c5039 ILT |
6604 | |
6605 | /* The .loc directive. */ | |
6606 | ||
88225433 | 6607 | #if 0 |
3d3c5039 ILT |
6608 | static void |
6609 | s_loc (x) | |
6610 | int x; | |
6611 | { | |
670a50eb ILT |
6612 | symbolS *symbolP; |
6613 | int lineno; | |
6614 | int addroff; | |
3d3c5039 | 6615 | |
670a50eb | 6616 | assert (now_seg == text_section); |
3d3c5039 | 6617 | |
670a50eb ILT |
6618 | lineno = get_number (); |
6619 | addroff = obstack_next_free (&frags) - frag_now->fr_literal; | |
3d3c5039 | 6620 | |
670a50eb ILT |
6621 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
6622 | S_SET_TYPE (symbolP, N_SLINE); | |
6623 | S_SET_OTHER (symbolP, 0); | |
6624 | S_SET_DESC (symbolP, lineno); | |
6625 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 6626 | } |
88225433 | 6627 | #endif |
3d3c5039 | 6628 | |
0dd2d296 | 6629 | #endif /* ! defined (ECOFF_DEBUGGING) */ |