Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
82704155 | 2 | Copyright (C) 1993-2019 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
6f2117ba PH |
144 | /* The name if this is an label. */ |
145 | char label[16]; | |
146 | ||
147 | /* The target label name if this is an branch. */ | |
148 | char target[16]; | |
149 | ||
47e39b9d RS |
150 | /* The frag that contains the instruction. */ |
151 | struct frag *frag; | |
152 | ||
153 | /* The offset into FRAG of the first instruction byte. */ | |
154 | long where; | |
155 | ||
156 | /* The relocs associated with the instruction, if any. */ | |
157 | fixS *fixp[3]; | |
158 | ||
a38419a5 RS |
159 | /* True if this entry cannot be moved from its current position. */ |
160 | unsigned int fixed_p : 1; | |
47e39b9d | 161 | |
708587a4 | 162 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
163 | unsigned int noreorder_p : 1; |
164 | ||
2fa15973 RS |
165 | /* True for mips16 instructions that jump to an absolute address. */ |
166 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
167 | |
168 | /* True if this instruction is complete. */ | |
169 | unsigned int complete_p : 1; | |
e407c74b NC |
170 | |
171 | /* True if this instruction is cleared from history by unconditional | |
172 | branch. */ | |
173 | unsigned int cleared_p : 1; | |
47e39b9d RS |
174 | }; |
175 | ||
a325df1d TS |
176 | /* The ABI to use. */ |
177 | enum mips_abi_level | |
178 | { | |
179 | NO_ABI = 0, | |
180 | O32_ABI, | |
181 | O64_ABI, | |
182 | N32_ABI, | |
183 | N64_ABI, | |
184 | EABI_ABI | |
185 | }; | |
186 | ||
187 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 188 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 189 | |
143d77c5 EC |
190 | /* Whether or not we have code that can call pic code. */ |
191 | int mips_abicalls = FALSE; | |
192 | ||
aa6975fb ILT |
193 | /* Whether or not we have code which can be put into a shared |
194 | library. */ | |
195 | static bfd_boolean mips_in_shared = TRUE; | |
196 | ||
252b5132 RH |
197 | /* This is the set of options which may be modified by the .set |
198 | pseudo-op. We use a struct so that .set push and .set pop are more | |
199 | reliable. */ | |
200 | ||
e972090a NC |
201 | struct mips_set_options |
202 | { | |
252b5132 RH |
203 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
204 | if it has not been initialized. Changed by `.set mipsN', and the | |
205 | -mipsN command line option, and the default CPU. */ | |
206 | int isa; | |
846ef2d0 RS |
207 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
208 | <asename>', by command line options, and based on the default | |
209 | architecture. */ | |
210 | int ase; | |
252b5132 RH |
211 | /* Whether we are assembling for the mips16 processor. 0 if we are |
212 | not, 1 if we are, and -1 if the value has not been initialized. | |
213 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
214 | -nomips16 command line options, and the default CPU. */ | |
215 | int mips16; | |
df58fc94 RS |
216 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
217 | 1 if we are, and -1 if the value has not been initialized. Changed | |
218 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
219 | and -mno-micromips command line options, and the default CPU. */ | |
220 | int micromips; | |
252b5132 RH |
221 | /* Non-zero if we should not reorder instructions. Changed by `.set |
222 | reorder' and `.set noreorder'. */ | |
223 | int noreorder; | |
741fe287 MR |
224 | /* Non-zero if we should not permit the register designated "assembler |
225 | temporary" to be used in instructions. The value is the register | |
226 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
227 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
228 | unsigned int at; | |
252b5132 RH |
229 | /* Non-zero if we should warn when a macro instruction expands into |
230 | more than one machine instruction. Changed by `.set nomacro' and | |
231 | `.set macro'. */ | |
232 | int warn_about_macros; | |
233 | /* Non-zero if we should not move instructions. Changed by `.set | |
234 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
235 | int nomove; | |
236 | /* Non-zero if we should not optimize branches by moving the target | |
237 | of the branch into the delay slot. Actually, we don't perform | |
238 | this optimization anyhow. Changed by `.set bopt' and `.set | |
239 | nobopt'. */ | |
240 | int nobopt; | |
241 | /* Non-zero if we should not autoextend mips16 instructions. | |
242 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
243 | int noautoextend; | |
833794fc MR |
244 | /* True if we should only emit 32-bit microMIPS instructions. |
245 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
246 | and -mno-insn32 command line options. */ | |
247 | bfd_boolean insn32; | |
a325df1d TS |
248 | /* Restrict general purpose registers and floating point registers |
249 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
250 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 251 | int gp; |
0b35dfee | 252 | int fp; |
fef14a42 TS |
253 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
254 | command line option, and the default CPU. */ | |
255 | int arch; | |
aed1a261 RS |
256 | /* True if ".set sym32" is in effect. */ |
257 | bfd_boolean sym32; | |
037b32b9 AN |
258 | /* True if floating-point operations are not allowed. Changed by .set |
259 | softfloat or .set hardfloat, by command line options -msoft-float or | |
260 | -mhard-float. The default is false. */ | |
261 | bfd_boolean soft_float; | |
262 | ||
263 | /* True if only single-precision floating-point operations are allowed. | |
264 | Changed by .set singlefloat or .set doublefloat, command-line options | |
265 | -msingle-float or -mdouble-float. The default is false. */ | |
266 | bfd_boolean single_float; | |
351cdf24 MF |
267 | |
268 | /* 1 if single-precision operations on odd-numbered registers are | |
269 | allowed. */ | |
270 | int oddspreg; | |
3315614d MF |
271 | |
272 | /* The set of ASEs that should be enabled for the user specified | |
273 | architecture. This cannot be inferred from 'arch' for all cores | |
274 | as processors only have a unique 'arch' if they add architecture | |
275 | specific instructions (UDI). */ | |
276 | int init_ase; | |
252b5132 RH |
277 | }; |
278 | ||
919731af | 279 | /* Specifies whether module level options have been checked yet. */ |
280 | static bfd_boolean file_mips_opts_checked = FALSE; | |
281 | ||
7361da2c AB |
282 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
283 | value has not been initialized. Changed by `.nan legacy' and | |
284 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
285 | options, and the default CPU. */ | |
286 | static int mips_nan2008 = -1; | |
a325df1d | 287 | |
0b35dfee | 288 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 289 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 290 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 291 | |
0b35dfee | 292 | static struct mips_set_options file_mips_opts = |
293 | { | |
294 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
295 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
296 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 297 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
3315614d MF |
298 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, |
299 | /* init_ase */ 0 | |
0b35dfee | 300 | }; |
252b5132 | 301 | |
0b35dfee | 302 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 303 | |
e972090a NC |
304 | static struct mips_set_options mips_opts = |
305 | { | |
846ef2d0 | 306 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 307 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 308 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 309 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
3315614d MF |
310 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, |
311 | /* init_ase */ 0 | |
e7af610e | 312 | }; |
252b5132 | 313 | |
846ef2d0 RS |
314 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
315 | static unsigned int file_ase_explicit; | |
316 | ||
252b5132 RH |
317 | /* These variables are filled in with the masks of registers used. |
318 | The object format code reads them and puts them in the appropriate | |
319 | place. */ | |
320 | unsigned long mips_gprmask; | |
321 | unsigned long mips_cprmask[4]; | |
322 | ||
738f4d98 | 323 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
324 | static int file_ase_mips16; |
325 | ||
3994f87e TS |
326 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
327 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
328 | || mips_opts.isa == ISA_MIPS32R3 \ |
329 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 330 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
331 | || mips_opts.isa == ISA_MIPS64R2 \ |
332 | || mips_opts.isa == ISA_MIPS64R3 \ | |
333 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 334 | |
df58fc94 RS |
335 | /* True if any microMIPS code was produced. */ |
336 | static int file_ase_micromips; | |
337 | ||
b12dd2e4 CF |
338 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
339 | #ifdef TE_IRIX | |
1180b5a4 | 340 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 341 | #else |
1180b5a4 RS |
342 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
343 | because there's no place for any addend, the only acceptable | |
344 | expression is a bare symbol. */ | |
345 | #define MIPS_JALR_HINT_P(EXPR) \ | |
346 | (!HAVE_IN_PLACE_ADDENDS \ | |
347 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
348 | #endif |
349 | ||
ec68c924 | 350 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 351 | static const char *mips_arch_string; |
ec68c924 EC |
352 | |
353 | /* The argument of the -mtune= flag. The architecture for which we | |
354 | are optimizing. */ | |
355 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 356 | static const char *mips_tune_string; |
ec68c924 | 357 | |
316f5878 | 358 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
359 | static int mips_32bitmode = 0; |
360 | ||
316f5878 RS |
361 | /* True if the given ABI requires 32-bit registers. */ |
362 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
363 | ||
364 | /* Likewise 64-bit registers. */ | |
707bfff6 | 365 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 366 | ((ABI) == N32_ABI \ |
707bfff6 | 367 | || (ABI) == N64_ABI \ |
316f5878 RS |
368 | || (ABI) == O64_ABI) |
369 | ||
7361da2c AB |
370 | #define ISA_IS_R6(ISA) \ |
371 | ((ISA) == ISA_MIPS32R6 \ | |
372 | || (ISA) == ISA_MIPS64R6) | |
373 | ||
ad3fea08 | 374 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
375 | #define ISA_HAS_64BIT_REGS(ISA) \ |
376 | ((ISA) == ISA_MIPS3 \ | |
377 | || (ISA) == ISA_MIPS4 \ | |
378 | || (ISA) == ISA_MIPS5 \ | |
379 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
380 | || (ISA) == ISA_MIPS64R2 \ |
381 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
382 | || (ISA) == ISA_MIPS64R5 \ |
383 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 384 | |
ad3fea08 TS |
385 | /* Return true if ISA supports 64 bit wide float registers. */ |
386 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
387 | ((ISA) == ISA_MIPS3 \ | |
388 | || (ISA) == ISA_MIPS4 \ | |
389 | || (ISA) == ISA_MIPS5 \ | |
390 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
391 | || (ISA) == ISA_MIPS32R3 \ |
392 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 393 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 394 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
395 | || (ISA) == ISA_MIPS64R2 \ |
396 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
397 | || (ISA) == ISA_MIPS64R5 \ |
398 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 399 | |
af7ee8bf CD |
400 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
401 | instructions. */ | |
707bfff6 | 402 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 403 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
404 | || (ISA) == ISA_MIPS64R3 \ |
405 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 406 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
407 | || (mips_opts.micromips \ |
408 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
409 | ) | |
af7ee8bf CD |
410 | |
411 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
412 | instructions. */ | |
707bfff6 TS |
413 | #define ISA_HAS_ROR(ISA) \ |
414 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
415 | || (ISA) == ISA_MIPS32R3 \ |
416 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 417 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 418 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
419 | || (ISA) == ISA_MIPS64R3 \ |
420 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 421 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 422 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
423 | || mips_opts.micromips \ |
424 | ) | |
707bfff6 | 425 | |
7455baf8 | 426 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
427 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
428 | (((ISA) == ISA_MIPS32 \ | |
429 | || (ISA) == ISA_MIPS32R2 \ | |
430 | || (ISA) == ISA_MIPS32R3 \ | |
431 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 432 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
433 | || (ISA) == ISA_MIPS64 \ |
434 | || (ISA) == ISA_MIPS64R2 \ | |
435 | || (ISA) == ISA_MIPS64R3 \ | |
436 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 437 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 | 438 | || (CPU) == CPU_R5900) \ |
bd782c07 | 439 | && ((CPU) != CPU_GS464 \ |
9108bc33 CX |
440 | || (CPU) != CPU_GS464E \ |
441 | || (CPU) != CPU_GS264E)) | |
af7ee8bf | 442 | |
ad3fea08 TS |
443 | /* Return true if ISA supports move to/from high part of a 64-bit |
444 | floating-point register. */ | |
445 | #define ISA_HAS_MXHC1(ISA) \ | |
446 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
447 | || (ISA) == ISA_MIPS32R3 \ |
448 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
449 | || (ISA) == ISA_MIPS32R6 \ |
450 | || (ISA) == ISA_MIPS64R2 \ | |
451 | || (ISA) == ISA_MIPS64R3 \ | |
452 | || (ISA) == ISA_MIPS64R5 \ | |
453 | || (ISA) == ISA_MIPS64R6) | |
454 | ||
455 | /* Return true if ISA supports legacy NAN. */ | |
456 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
457 | ((ISA) == ISA_MIPS1 \ | |
458 | || (ISA) == ISA_MIPS2 \ | |
459 | || (ISA) == ISA_MIPS3 \ | |
460 | || (ISA) == ISA_MIPS4 \ | |
461 | || (ISA) == ISA_MIPS5 \ | |
462 | || (ISA) == ISA_MIPS32 \ | |
463 | || (ISA) == ISA_MIPS32R2 \ | |
464 | || (ISA) == ISA_MIPS32R3 \ | |
465 | || (ISA) == ISA_MIPS32R5 \ | |
466 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
467 | || (ISA) == ISA_MIPS64R2 \ |
468 | || (ISA) == ISA_MIPS64R3 \ | |
469 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 470 | |
bad1aba3 | 471 | #define GPR_SIZE \ |
472 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
473 | ? 32 \ | |
474 | : mips_opts.gp) | |
ca4e0257 | 475 | |
bad1aba3 | 476 | #define FPR_SIZE \ |
477 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
478 | ? 32 \ | |
479 | : mips_opts.fp) | |
ca4e0257 | 480 | |
316f5878 | 481 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 482 | |
316f5878 | 483 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 484 | |
3b91255e RS |
485 | /* True if relocations are stored in-place. */ |
486 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
487 | ||
aed1a261 RS |
488 | /* The ABI-derived address size. */ |
489 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 490 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 491 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 492 | |
aed1a261 RS |
493 | /* The size of symbolic constants (i.e., expressions of the form |
494 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
495 | #define HAVE_32BIT_SYMBOLS \ | |
496 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
497 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 498 | |
b7c7d6c1 TS |
499 | /* Addresses are loaded in different ways, depending on the address size |
500 | in use. The n32 ABI Documentation also mandates the use of additions | |
501 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 502 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 503 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
504 | |
505 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 506 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
507 | |
508 | #define ADDRESS_LOAD_INSN \ | |
509 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
510 | ||
511 | #define ADDRESS_STORE_INSN \ | |
512 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
513 | ||
a4672219 | 514 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
515 | #define CPU_HAS_MIPS16(cpu) \ |
516 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
517 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 518 | |
2309ddf2 | 519 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
520 | #define CPU_HAS_MICROMIPS(cpu) 0 |
521 | ||
60b63b72 RS |
522 | /* True if CPU has a dror instruction. */ |
523 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
524 | ||
525 | /* True if CPU has a ror instruction. */ | |
526 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
527 | ||
6f2117ba | 528 | /* True if CPU is in the Octeon family. */ |
2c629856 N |
529 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
530 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 531 | |
dd3cbb7e | 532 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 533 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 534 | |
0aa27725 RS |
535 | /* True, if CPU has support for ldc1 and sdc1. */ |
536 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
537 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
538 | ||
c8978940 CD |
539 | /* True if mflo and mfhi can be immediately followed by instructions |
540 | which write to the HI and LO registers. | |
541 | ||
542 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
543 | (at least) two instructions between the reads of HI/LO and | |
544 | instructions which write them, and later ISAs do not. Contradicting | |
545 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
546 | the UM for the NEC Vr5000) document needing the instructions between | |
547 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
548 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
549 | earlier-ISA CPUs for which CPU documentation declares that the | |
550 | instructions are really interlocked. */ | |
551 | #define hilo_interlocks \ | |
552 | (mips_opts.isa == ISA_MIPS32 \ | |
553 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
554 | || mips_opts.isa == ISA_MIPS32R3 \ |
555 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 556 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
557 | || mips_opts.isa == ISA_MIPS64 \ |
558 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
559 | || mips_opts.isa == ISA_MIPS64R3 \ |
560 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 561 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 562 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 563 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
564 | || mips_opts.arch == CPU_R10000 \ |
565 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
566 | || mips_opts.arch == CPU_R14000 \ |
567 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 568 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 569 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 570 | || mips_opts.micromips \ |
c8978940 | 571 | ) |
252b5132 RH |
572 | |
573 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
574 | from the GPRs after they are loaded from memory, and thus does not |
575 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 576 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
577 | level I and microMIPS mode instructions are always interlocked. */ |
578 | #define gpr_interlocks \ | |
579 | (mips_opts.isa != ISA_MIPS1 \ | |
580 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 581 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
582 | || mips_opts.micromips \ |
583 | ) | |
252b5132 | 584 | |
81912461 ILT |
585 | /* Whether the processor uses hardware interlocks to avoid delays |
586 | required by coprocessor instructions, and thus does not require | |
587 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
588 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
589 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 590 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
591 | levels I, II, and III and microMIPS mode instructions are always |
592 | interlocked. */ | |
bdaaa2e1 | 593 | /* Itbl support may require additional care here. */ |
81912461 ILT |
594 | #define cop_interlocks \ |
595 | ((mips_opts.isa != ISA_MIPS1 \ | |
596 | && mips_opts.isa != ISA_MIPS2 \ | |
597 | && mips_opts.isa != ISA_MIPS3) \ | |
598 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 599 | || mips_opts.micromips \ |
81912461 ILT |
600 | ) |
601 | ||
602 | /* Whether the processor uses hardware interlocks to protect reads | |
603 | from coprocessor registers after they are loaded from memory, and | |
604 | thus does not require nops to be inserted. This applies to | |
605 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
606 | requires at MIPS ISA level I and microMIPS mode instructions are |
607 | always interlocked. */ | |
608 | #define cop_mem_interlocks \ | |
609 | (mips_opts.isa != ISA_MIPS1 \ | |
610 | || mips_opts.micromips \ | |
611 | ) | |
252b5132 | 612 | |
6b76fefe CM |
613 | /* Is this a mfhi or mflo instruction? */ |
614 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
615 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
616 | ||
df58fc94 RS |
617 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
618 | has been selected. This implies, in particular, that addresses of text | |
619 | labels have their LSB set. */ | |
620 | #define HAVE_CODE_COMPRESSION \ | |
621 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
622 | ||
42429eac | 623 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 624 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
625 | #define GPR_SMIN (-GPR_SMAX - 1) |
626 | ||
252b5132 RH |
627 | /* MIPS PIC level. */ |
628 | ||
a161fe53 | 629 | enum mips_pic_level mips_pic; |
252b5132 | 630 | |
c9914766 | 631 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 632 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 633 | static int mips_big_got = 0; |
252b5132 RH |
634 | |
635 | /* 1 if trap instructions should used for overflow rather than break | |
636 | instructions. */ | |
c9914766 | 637 | static int mips_trap = 0; |
252b5132 | 638 | |
119d663a | 639 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 640 | by assembling two single width halves into two single width floating |
119d663a NC |
641 | point registers which just happen to alias the double width destination |
642 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 643 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
644 | automatically at assemble time. */ |
645 | static int mips_disable_float_construction; | |
646 | ||
252b5132 RH |
647 | /* Non-zero if any .set noreorder directives were used. */ |
648 | ||
649 | static int mips_any_noreorder; | |
650 | ||
6b76fefe CM |
651 | /* Non-zero if nops should be inserted when the register referenced in |
652 | an mfhi/mflo instruction is read in the next two instructions. */ | |
653 | static int mips_7000_hilo_fix; | |
654 | ||
02ffd3e4 | 655 | /* The size of objects in the small data section. */ |
156c2f8b | 656 | static unsigned int g_switch_value = 8; |
252b5132 RH |
657 | /* Whether the -G option was used. */ |
658 | static int g_switch_seen = 0; | |
659 | ||
660 | #define N_RMASK 0xc4 | |
661 | #define N_VFP 0xd4 | |
662 | ||
663 | /* If we can determine in advance that GP optimization won't be | |
664 | possible, we can skip the relaxation stuff that tries to produce | |
665 | GP-relative references. This makes delay slot optimization work | |
666 | better. | |
667 | ||
668 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
669 | gcc output. It needs to guess right for gcc, otherwise gcc |
670 | will put what it thinks is a GP-relative instruction in a branch | |
671 | delay slot. | |
252b5132 RH |
672 | |
673 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
674 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 675 | static int nopic_need_relax (symbolS *, int); |
252b5132 | 676 | |
6f2117ba | 677 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
678 | static struct hash_control *op_hash = NULL; |
679 | ||
680 | /* The opcode hash table we use for the mips16. */ | |
681 | static struct hash_control *mips16_op_hash = NULL; | |
682 | ||
df58fc94 RS |
683 | /* The opcode hash table we use for the microMIPS ASE. */ |
684 | static struct hash_control *micromips_op_hash = NULL; | |
685 | ||
252b5132 | 686 | /* This array holds the chars that always start a comment. If the |
6f2117ba | 687 | pre-processor is disabled, these aren't very useful. */ |
252b5132 RH |
688 | const char comment_chars[] = "#"; |
689 | ||
690 | /* This array holds the chars that only start a comment at the beginning of | |
691 | a line. If the line seems to have the form '# 123 filename' | |
6f2117ba | 692 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
693 | /* Note that input_file.c hand checks for '#' at the beginning of the |
694 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 695 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
696 | /* Also note that C style comments are always supported. */ |
697 | const char line_comment_chars[] = "#"; | |
698 | ||
bdaaa2e1 | 699 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 700 | const char line_separator_chars[] = ";"; |
252b5132 | 701 | |
6f2117ba | 702 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
252b5132 RH |
703 | const char EXP_CHARS[] = "eE"; |
704 | ||
6f2117ba PH |
705 | /* Chars that mean this number is a floating point constant. |
706 | As in 0f12.456 | |
707 | or 0d1.2345e12. */ | |
252b5132 RH |
708 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
709 | ||
710 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
711 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
6f2117ba | 712 | but nothing is ideal around here. */ |
252b5132 | 713 | |
e3de51ce | 714 | /* Types of printf format used for instruction-related error messages. |
6f2117ba PH |
715 | "I" means int ("%d") and "S" means string ("%s"). */ |
716 | enum mips_insn_error_format | |
717 | { | |
e3de51ce RS |
718 | ERR_FMT_PLAIN, |
719 | ERR_FMT_I, | |
720 | ERR_FMT_SS, | |
721 | }; | |
722 | ||
723 | /* Information about an error that was found while assembling the current | |
724 | instruction. */ | |
6f2117ba PH |
725 | struct mips_insn_error |
726 | { | |
e3de51ce RS |
727 | /* We sometimes need to match an instruction against more than one |
728 | opcode table entry. Errors found during this matching are reported | |
729 | against a particular syntactic argument rather than against the | |
730 | instruction as a whole. We grade these messages so that errors | |
731 | against argument N have a greater priority than an error against | |
732 | any argument < N, since the former implies that arguments up to N | |
733 | were acceptable and that the opcode entry was therefore a closer match. | |
734 | If several matches report an error against the same argument, | |
735 | we only use that error if it is the same in all cases. | |
736 | ||
737 | min_argnum is the minimum argument number for which an error message | |
738 | should be accepted. It is 0 if MSG is against the instruction as | |
739 | a whole. */ | |
740 | int min_argnum; | |
741 | ||
742 | /* The printf()-style message, including its format and arguments. */ | |
743 | enum mips_insn_error_format format; | |
744 | const char *msg; | |
6f2117ba PH |
745 | union |
746 | { | |
e3de51ce RS |
747 | int i; |
748 | const char *ss[2]; | |
749 | } u; | |
750 | }; | |
751 | ||
752 | /* The error that should be reported for the current instruction. */ | |
753 | static struct mips_insn_error insn_error; | |
252b5132 RH |
754 | |
755 | static int auto_align = 1; | |
756 | ||
757 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
758 | offset in the stack frame from which to restore the $gp register. | |
759 | This is set by the .cprestore pseudo-op, and saved in this | |
760 | variable. */ | |
761 | static offsetT mips_cprestore_offset = -1; | |
762 | ||
67c1ffbe | 763 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 764 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 765 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
766 | static offsetT mips_cpreturn_offset = -1; |
767 | static int mips_cpreturn_register = -1; | |
768 | static int mips_gp_register = GP; | |
def2e0dd | 769 | static int mips_gprel_offset = 0; |
6478892d | 770 | |
7a621144 DJ |
771 | /* Whether mips_cprestore_offset has been set in the current function |
772 | (or whether it has already been warned about, if not). */ | |
773 | static int mips_cprestore_valid = 0; | |
774 | ||
252b5132 RH |
775 | /* This is the register which holds the stack frame, as set by the |
776 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
777 | static int mips_frame_reg = SP; | |
778 | ||
7a621144 DJ |
779 | /* Whether mips_frame_reg has been set in the current function |
780 | (or whether it has already been warned about, if not). */ | |
781 | static int mips_frame_reg_valid = 0; | |
782 | ||
252b5132 RH |
783 | /* To output NOP instructions correctly, we need to keep information |
784 | about the previous two instructions. */ | |
785 | ||
786 | /* Whether we are optimizing. The default value of 2 means to remove | |
787 | unneeded NOPs and swap branch instructions when possible. A value | |
788 | of 1 means to not swap branches. A value of 0 means to always | |
789 | insert NOPs. */ | |
790 | static int mips_optimize = 2; | |
791 | ||
792 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
793 | equivalent to seeing no -g option at all. */ | |
794 | static int mips_debug = 0; | |
795 | ||
7d8e00cf RS |
796 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
797 | #define MAX_VR4130_NOPS 4 | |
798 | ||
799 | /* The maximum number of NOPs needed to fill delay slots. */ | |
800 | #define MAX_DELAY_NOPS 2 | |
801 | ||
802 | /* The maximum number of NOPs needed for any purpose. */ | |
803 | #define MAX_NOPS 4 | |
71400594 | 804 | |
6f2117ba PH |
805 | /* The maximum range of context length of ll/sc. */ |
806 | #define MAX_LLSC_RANGE 20 | |
807 | ||
71400594 RS |
808 | /* A list of previous instructions, with index 0 being the most recent. |
809 | We need to look back MAX_NOPS instructions when filling delay slots | |
810 | or working around processor errata. We need to look back one | |
811 | instruction further if we're thinking about using history[0] to | |
812 | fill a branch delay slot. */ | |
6f2117ba | 813 | static struct mips_cl_insn history[1 + MAX_NOPS + MAX_LLSC_RANGE]; |
252b5132 | 814 | |
fc76e730 | 815 | /* Arrays of operands for each instruction. */ |
14daeee3 | 816 | #define MAX_OPERANDS 6 |
6f2117ba PH |
817 | struct mips_operand_array |
818 | { | |
fc76e730 RS |
819 | const struct mips_operand *operand[MAX_OPERANDS]; |
820 | }; | |
821 | static struct mips_operand_array *mips_operands; | |
822 | static struct mips_operand_array *mips16_operands; | |
823 | static struct mips_operand_array *micromips_operands; | |
824 | ||
1e915849 | 825 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
826 | static struct mips_cl_insn nop_insn; |
827 | static struct mips_cl_insn mips16_nop_insn; | |
828 | static struct mips_cl_insn micromips_nop16_insn; | |
829 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 | 830 | |
6f2117ba PH |
831 | /* Sync instructions used by insert sync. */ |
832 | static struct mips_cl_insn sync_insn; | |
833 | ||
1e915849 | 834 | /* The appropriate nop for the current mode. */ |
833794fc MR |
835 | #define NOP_INSN (mips_opts.mips16 \ |
836 | ? &mips16_nop_insn \ | |
837 | : (mips_opts.micromips \ | |
838 | ? (mips_opts.insn32 \ | |
839 | ? µmips_nop32_insn \ | |
840 | : µmips_nop16_insn) \ | |
841 | : &nop_insn)) | |
df58fc94 RS |
842 | |
843 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
844 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
845 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
846 | ? 2 : 4) | |
252b5132 | 847 | |
252b5132 RH |
848 | /* If this is set, it points to a frag holding nop instructions which |
849 | were inserted before the start of a noreorder section. If those | |
850 | nops turn out to be unnecessary, the size of the frag can be | |
851 | decreased. */ | |
852 | static fragS *prev_nop_frag; | |
853 | ||
854 | /* The number of nop instructions we created in prev_nop_frag. */ | |
855 | static int prev_nop_frag_holds; | |
856 | ||
857 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 858 | prev_nop_frag. */ |
252b5132 RH |
859 | static int prev_nop_frag_required; |
860 | ||
861 | /* The number of instructions we've seen since prev_nop_frag. */ | |
862 | static int prev_nop_frag_since; | |
863 | ||
e8044f35 RS |
864 | /* Relocations against symbols are sometimes done in two parts, with a HI |
865 | relocation and a LO relocation. Each relocation has only 16 bits of | |
866 | space to store an addend. This means that in order for the linker to | |
867 | handle carries correctly, it must be able to locate both the HI and | |
868 | the LO relocation. This means that the relocations must appear in | |
869 | order in the relocation table. | |
252b5132 RH |
870 | |
871 | In order to implement this, we keep track of each unmatched HI | |
872 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 873 | corresponding LO relocation. */ |
252b5132 | 874 | |
e972090a NC |
875 | struct mips_hi_fixup |
876 | { | |
252b5132 RH |
877 | /* Next HI fixup. */ |
878 | struct mips_hi_fixup *next; | |
879 | /* This fixup. */ | |
880 | fixS *fixp; | |
881 | /* The section this fixup is in. */ | |
882 | segT seg; | |
883 | }; | |
884 | ||
885 | /* The list of unmatched HI relocs. */ | |
886 | ||
887 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
888 | ||
64bdfcaf RS |
889 | /* The frag containing the last explicit relocation operator. |
890 | Null if explicit relocations have not been used. */ | |
891 | ||
892 | static fragS *prev_reloc_op_frag; | |
893 | ||
252b5132 RH |
894 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
895 | ||
e972090a NC |
896 | static const unsigned int mips16_to_32_reg_map[] = |
897 | { | |
252b5132 RH |
898 | 16, 17, 2, 3, 4, 5, 6, 7 |
899 | }; | |
60b63b72 | 900 | |
df58fc94 RS |
901 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
902 | ||
df58fc94 | 903 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
904 | |
905 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 906 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
907 | { |
908 | 5, 5, 6, 4, 4, 4, 4, 4 | |
909 | }; | |
e76ff5ab | 910 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
911 | { |
912 | 6, 7, 7, 21, 22, 5, 6, 7 | |
913 | }; | |
914 | ||
df58fc94 RS |
915 | /* The microMIPS registers with type m. */ |
916 | static const unsigned int micromips_to_32_reg_m_map[] = | |
917 | { | |
918 | 0, 17, 2, 3, 16, 18, 19, 20 | |
919 | }; | |
920 | ||
921 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
922 | ||
71400594 RS |
923 | /* Classifies the kind of instructions we're interested in when |
924 | implementing -mfix-vr4120. */ | |
c67a084a NC |
925 | enum fix_vr4120_class |
926 | { | |
71400594 RS |
927 | FIX_VR4120_MACC, |
928 | FIX_VR4120_DMACC, | |
929 | FIX_VR4120_MULT, | |
930 | FIX_VR4120_DMULT, | |
931 | FIX_VR4120_DIV, | |
932 | FIX_VR4120_MTHILO, | |
933 | NUM_FIX_VR4120_CLASSES | |
934 | }; | |
935 | ||
c67a084a NC |
936 | /* ...likewise -mfix-loongson2f-jump. */ |
937 | static bfd_boolean mips_fix_loongson2f_jump; | |
938 | ||
939 | /* ...likewise -mfix-loongson2f-nop. */ | |
940 | static bfd_boolean mips_fix_loongson2f_nop; | |
941 | ||
942 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
943 | static bfd_boolean mips_fix_loongson2f; | |
944 | ||
71400594 RS |
945 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
946 | there must be at least one other instruction between an instruction | |
947 | of type X and an instruction of type Y. */ | |
948 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
949 | ||
950 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 951 | static int mips_fix_vr4120; |
4a6a3df4 | 952 | |
7d8e00cf RS |
953 | /* ...likewise -mfix-vr4130. */ |
954 | static int mips_fix_vr4130; | |
955 | ||
6a32d874 CM |
956 | /* ...likewise -mfix-24k. */ |
957 | static int mips_fix_24k; | |
958 | ||
a8d14a88 CM |
959 | /* ...likewise -mfix-rm7000 */ |
960 | static int mips_fix_rm7000; | |
961 | ||
d954098f DD |
962 | /* ...likewise -mfix-cn63xxp1 */ |
963 | static bfd_boolean mips_fix_cn63xxp1; | |
964 | ||
27c634e0 FN |
965 | /* ...likewise -mfix-r5900 */ |
966 | static bfd_boolean mips_fix_r5900; | |
967 | static bfd_boolean mips_fix_r5900_explicit; | |
968 | ||
6f2117ba PH |
969 | /* ...likewise -mfix-loongson3-llsc. */ |
970 | static bfd_boolean mips_fix_loongson3_llsc = DEFAULT_MIPS_FIX_LOONGSON3_LLSC; | |
971 | ||
4a6a3df4 AO |
972 | /* We don't relax branches by default, since this causes us to expand |
973 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
974 | fail to compute the offset before expanding the macro to the most | |
975 | efficient expansion. */ | |
976 | ||
977 | static int mips_relax_branch; | |
8b10b0b3 MR |
978 | |
979 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
980 | Needed for broken assembly produced by some GCC versions and some | |
981 | sloppy code out there, where branches to data labels are present. */ | |
982 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 983 | \f |
4d7206a2 RS |
984 | /* The expansion of many macros depends on the type of symbol that |
985 | they refer to. For example, when generating position-dependent code, | |
986 | a macro that refers to a symbol may have two different expansions, | |
987 | one which uses GP-relative addresses and one which uses absolute | |
988 | addresses. When generating SVR4-style PIC, a macro may have | |
989 | different expansions for local and global symbols. | |
990 | ||
991 | We handle these situations by generating both sequences and putting | |
992 | them in variant frags. In position-dependent code, the first sequence | |
993 | will be the GP-relative one and the second sequence will be the | |
994 | absolute one. In SVR4 PIC, the first sequence will be for global | |
995 | symbols and the second will be for local symbols. | |
996 | ||
584892a6 RS |
997 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
998 | SECOND are the lengths of the two sequences in bytes. These fields | |
999 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
1000 | the subtype has the following flags: | |
4d7206a2 | 1001 | |
ce8ad872 MR |
1002 | RELAX_PIC |
1003 | Set if generating PIC code. | |
1004 | ||
584892a6 RS |
1005 | RELAX_USE_SECOND |
1006 | Set if it has been decided that we should use the second | |
1007 | sequence instead of the first. | |
1008 | ||
1009 | RELAX_SECOND_LONGER | |
1010 | Set in the first variant frag if the macro's second implementation | |
1011 | is longer than its first. This refers to the macro as a whole, | |
1012 | not an individual relaxation. | |
1013 | ||
1014 | RELAX_NOMACRO | |
1015 | Set in the first variant frag if the macro appeared in a .set nomacro | |
1016 | block and if one alternative requires a warning but the other does not. | |
1017 | ||
1018 | RELAX_DELAY_SLOT | |
1019 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
1020 | delay slot. | |
4d7206a2 | 1021 | |
df58fc94 RS |
1022 | RELAX_DELAY_SLOT_16BIT |
1023 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
1024 | 16-bit instruction. | |
1025 | ||
1026 | RELAX_DELAY_SLOT_SIZE_FIRST | |
1027 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
1028 | the macro is of the wrong size for the branch delay slot. | |
1029 | ||
1030 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1031 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1032 | the macro is of the wrong size for the branch delay slot. | |
1033 | ||
4d7206a2 RS |
1034 | The frag's "opcode" points to the first fixup for relaxable code. |
1035 | ||
1036 | Relaxable macros are generated using a sequence such as: | |
1037 | ||
1038 | relax_start (SYMBOL); | |
1039 | ... generate first expansion ... | |
1040 | relax_switch (); | |
1041 | ... generate second expansion ... | |
1042 | relax_end (); | |
1043 | ||
1044 | The code and fixups for the unwanted alternative are discarded | |
1045 | by md_convert_frag. */ | |
ce8ad872 MR |
1046 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1047 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1048 | |
584892a6 RS |
1049 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1050 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1051 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1052 | #define RELAX_USE_SECOND 0x20000 | |
1053 | #define RELAX_SECOND_LONGER 0x40000 | |
1054 | #define RELAX_NOMACRO 0x80000 | |
1055 | #define RELAX_DELAY_SLOT 0x100000 | |
1056 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1057 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1058 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1059 | |
4a6a3df4 AO |
1060 | /* Branch without likely bit. If label is out of range, we turn: |
1061 | ||
134c0c8b | 1062 | beq reg1, reg2, label |
4a6a3df4 AO |
1063 | delay slot |
1064 | ||
1065 | into | |
1066 | ||
1067 | bne reg1, reg2, 0f | |
1068 | nop | |
1069 | j label | |
1070 | 0: delay slot | |
1071 | ||
1072 | with the following opcode replacements: | |
1073 | ||
1074 | beq <-> bne | |
1075 | blez <-> bgtz | |
1076 | bltz <-> bgez | |
1077 | bc1f <-> bc1t | |
1078 | ||
1079 | bltzal <-> bgezal (with jal label instead of j label) | |
1080 | ||
1081 | Even though keeping the delay slot instruction in the delay slot of | |
1082 | the branch would be more efficient, it would be very tricky to do | |
1083 | correctly, because we'd have to introduce a variable frag *after* | |
1084 | the delay slot instruction, and expand that instead. Let's do it | |
1085 | the easy way for now, even if the branch-not-taken case now costs | |
1086 | one additional instruction. Out-of-range branches are not supposed | |
1087 | to be common, anyway. | |
1088 | ||
1089 | Branch likely. If label is out of range, we turn: | |
1090 | ||
1091 | beql reg1, reg2, label | |
1092 | delay slot (annulled if branch not taken) | |
1093 | ||
1094 | into | |
1095 | ||
1096 | beql reg1, reg2, 1f | |
1097 | nop | |
1098 | beql $0, $0, 2f | |
1099 | nop | |
1100 | 1: j[al] label | |
1101 | delay slot (executed only if branch taken) | |
1102 | 2: | |
1103 | ||
1104 | It would be possible to generate a shorter sequence by losing the | |
1105 | likely bit, generating something like: | |
b34976b6 | 1106 | |
4a6a3df4 AO |
1107 | bne reg1, reg2, 0f |
1108 | nop | |
1109 | j[al] label | |
1110 | delay slot (executed only if branch taken) | |
1111 | 0: | |
1112 | ||
1113 | beql -> bne | |
1114 | bnel -> beq | |
1115 | blezl -> bgtz | |
1116 | bgtzl -> blez | |
1117 | bltzl -> bgez | |
1118 | bgezl -> bltz | |
1119 | bc1fl -> bc1t | |
1120 | bc1tl -> bc1f | |
1121 | ||
1122 | bltzall -> bgezal (with jal label instead of j label) | |
1123 | bgezall -> bltzal (ditto) | |
1124 | ||
1125 | ||
1126 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1127 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1128 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1129 | ((relax_substateT) \ |
1130 | (0xc0000000 \ | |
1131 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1132 | | ((pic) ? 0x20 : 0) \ |
1133 | | ((toofar) ? 0x40 : 0) \ | |
1134 | | ((link) ? 0x80 : 0) \ | |
1135 | | ((likely) ? 0x100 : 0) \ | |
1136 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1137 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1138 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1139 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1140 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1141 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1142 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1143 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1144 | |
252b5132 RH |
1145 | /* For mips16 code, we use an entirely different form of relaxation. |
1146 | mips16 supports two versions of most instructions which take | |
1147 | immediate values: a small one which takes some small value, and a | |
1148 | larger one which takes a 16 bit value. Since branches also follow | |
1149 | this pattern, relaxing these values is required. | |
1150 | ||
1151 | We can assemble both mips16 and normal MIPS code in a single | |
1152 | object. Therefore, we need to support this type of relaxation at | |
1153 | the same time that we support the relaxation described above. We | |
1154 | use the high bit of the subtype field to distinguish these cases. | |
1155 | ||
1156 | The information we store for this type of relaxation is the | |
1157 | argument code found in the opcode file for this relocation, whether | |
1158 | the user explicitly requested a small or extended form, and whether | |
1159 | the relocation is in a jump or jal delay slot. That tells us the | |
1160 | size of the value, and how it should be stored. We also store | |
1161 | whether the fragment is considered to be extended or not. We also | |
1162 | store whether this is known to be a branch to a different section, | |
1163 | whether we have tried to relax this frag yet, and whether we have | |
1164 | ever extended a PC relative fragment because of a shift count. */ | |
25499ac7 | 1165 | #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ |
8507b6e7 MR |
1166 | small, ext, \ |
1167 | dslot, jal_dslot) \ | |
252b5132 RH |
1168 | (0x80000000 \ |
1169 | | ((type) & 0xff) \ | |
25499ac7 MR |
1170 | | ((e2) ? 0x100 : 0) \ |
1171 | | ((pic) ? 0x200 : 0) \ | |
1172 | | ((sym32) ? 0x400 : 0) \ | |
1173 | | ((nomacro) ? 0x800 : 0) \ | |
1174 | | ((small) ? 0x1000 : 0) \ | |
1175 | | ((ext) ? 0x2000 : 0) \ | |
1176 | | ((dslot) ? 0x4000 : 0) \ | |
1177 | | ((jal_dslot) ? 0x8000 : 0)) | |
8507b6e7 | 1178 | |
4a6a3df4 | 1179 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1180 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
25499ac7 MR |
1181 | #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) |
1182 | #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) | |
1183 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) | |
1184 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) | |
1185 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) | |
1186 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) | |
1187 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) | |
1188 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) | |
1189 | ||
1190 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) | |
1191 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) | |
1192 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) | |
1193 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) | |
1194 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) | |
1195 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) | |
1196 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) | |
1197 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) | |
1198 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) | |
885add95 | 1199 | |
df58fc94 RS |
1200 | /* For microMIPS code, we use relaxation similar to one we use for |
1201 | MIPS16 code. Some instructions that take immediate values support | |
1202 | two encodings: a small one which takes some small value, and a | |
1203 | larger one which takes a 16 bit value. As some branches also follow | |
1204 | this pattern, relaxing these values is required. | |
1205 | ||
1206 | We can assemble both microMIPS and normal MIPS code in a single | |
1207 | object. Therefore, we need to support this type of relaxation at | |
1208 | the same time that we support the relaxation described above. We | |
1209 | use one of the high bits of the subtype field to distinguish these | |
1210 | cases. | |
1211 | ||
1212 | The information we store for this type of relaxation is the argument | |
1213 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1214 | selected as the assembler temporary, whether in the 32-bit |
1215 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1216 | compact, whether there is no delay-slot instruction available to fill |
1217 | in, whether it stores the link address implicitly in $ra, whether | |
1218 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1219 | instructions is enabled, and whether the displacement of a branch is |
1220 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1221 | branch, respectively. */ | |
ce8ad872 | 1222 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1223 | uncond, compact, link, nods, \ |
40209cad MR |
1224 | relax32, toofar16, toofar32) \ |
1225 | (0x40000000 \ | |
1226 | | ((type) & 0xff) \ | |
1227 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1228 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1229 | | ((pic) ? 0x4000 : 0) \ |
1230 | | ((uncond) ? 0x8000 : 0) \ | |
1231 | | ((compact) ? 0x10000 : 0) \ | |
1232 | | ((link) ? 0x20000 : 0) \ | |
1233 | | ((nods) ? 0x40000 : 0) \ | |
1234 | | ((relax32) ? 0x80000 : 0) \ | |
1235 | | ((toofar16) ? 0x100000 : 0) \ | |
1236 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1237 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1238 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1239 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1240 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1241 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1242 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1243 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1244 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1245 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1246 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1247 | ||
1248 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1249 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1250 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1251 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1252 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1253 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1254 | |
43c0598f RS |
1255 | /* Sign-extend 16-bit value X. */ |
1256 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1257 | ||
885add95 CD |
1258 | /* Is the given value a sign-extended 32-bit value? */ |
1259 | #define IS_SEXT_32BIT_NUM(x) \ | |
1260 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1261 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1262 | ||
1263 | /* Is the given value a sign-extended 16-bit value? */ | |
1264 | #define IS_SEXT_16BIT_NUM(x) \ | |
1265 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1266 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1267 | ||
df58fc94 RS |
1268 | /* Is the given value a sign-extended 12-bit value? */ |
1269 | #define IS_SEXT_12BIT_NUM(x) \ | |
1270 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1271 | ||
7f3c4072 CM |
1272 | /* Is the given value a sign-extended 9-bit value? */ |
1273 | #define IS_SEXT_9BIT_NUM(x) \ | |
1274 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1275 | ||
2051e8c4 MR |
1276 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1277 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1278 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1279 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1280 | ||
bf12938e RS |
1281 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1282 | SHIFT places. */ | |
1283 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1284 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1285 | ||
bf12938e | 1286 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1287 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1288 | (!(MICROMIPS) \ | |
1289 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1290 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1291 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1292 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1293 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1294 | MIPS16OP_MASK_##FIELD, \ | |
1295 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1296 | |
1297 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1298 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1299 | \f |
df58fc94 RS |
1300 | /* Whether or not we are emitting a branch-likely macro. */ |
1301 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1302 | ||
4d7206a2 RS |
1303 | /* Global variables used when generating relaxable macros. See the |
1304 | comment above RELAX_ENCODE for more details about how relaxation | |
1305 | is used. */ | |
1306 | static struct { | |
1307 | /* 0 if we're not emitting a relaxable macro. | |
1308 | 1 if we're emitting the first of the two relaxation alternatives. | |
1309 | 2 if we're emitting the second alternative. */ | |
1310 | int sequence; | |
1311 | ||
1312 | /* The first relaxable fixup in the current frag. (In other words, | |
1313 | the first fixup that refers to relaxable code.) */ | |
1314 | fixS *first_fixup; | |
1315 | ||
1316 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1317 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1318 | unsigned int sizes[2]; | |
1319 | ||
1320 | /* The symbol on which the choice of sequence depends. */ | |
1321 | symbolS *symbol; | |
1322 | } mips_relax; | |
252b5132 | 1323 | \f |
584892a6 RS |
1324 | /* Global variables used to decide whether a macro needs a warning. */ |
1325 | static struct { | |
1326 | /* True if the macro is in a branch delay slot. */ | |
1327 | bfd_boolean delay_slot_p; | |
1328 | ||
df58fc94 RS |
1329 | /* Set to the length in bytes required if the macro is in a delay slot |
1330 | that requires a specific length of instruction, otherwise zero. */ | |
1331 | unsigned int delay_slot_length; | |
1332 | ||
584892a6 RS |
1333 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1334 | in bytes and sizes[1] is the length of the second alternative. | |
1335 | For non-relaxable macros, both elements give the length of the | |
1336 | macro in bytes. */ | |
1337 | unsigned int sizes[2]; | |
1338 | ||
df58fc94 RS |
1339 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1340 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1341 | is the length of the first instruction of the second alternative. | |
1342 | For non-relaxable macros, both elements give the length of the first | |
1343 | instruction in bytes. | |
1344 | ||
1345 | Set to zero if we haven't yet seen the first instruction. */ | |
1346 | unsigned int first_insn_sizes[2]; | |
1347 | ||
1348 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1349 | first alternative and insns[1] is the number of instructions for the | |
1350 | second alternative. | |
1351 | ||
1352 | For non-relaxable macros, both elements give the number of | |
1353 | instructions for the macro. */ | |
1354 | unsigned int insns[2]; | |
1355 | ||
584892a6 RS |
1356 | /* The first variant frag for this macro. */ |
1357 | fragS *first_frag; | |
1358 | } mips_macro_warning; | |
1359 | \f | |
252b5132 RH |
1360 | /* Prototypes for static functions. */ |
1361 | ||
252b5132 RH |
1362 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1363 | ||
b34976b6 | 1364 | static void append_insn |
df58fc94 RS |
1365 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1366 | bfd_boolean expansionp); | |
7d10b47d | 1367 | static void mips_no_prev_insn (void); |
c67a084a | 1368 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1369 | static void mips16_macro_build |
03ea81db | 1370 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1371 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1372 | static void macro_start (void); |
1373 | static void macro_end (void); | |
833794fc | 1374 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1375 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1376 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1377 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
25499ac7 | 1378 | static unsigned long mips16_immed_extend (offsetT, unsigned int); |
b34976b6 | 1379 | static void mips16_immed |
3b4dbbbf | 1380 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1381 | unsigned int, unsigned long *); |
5e0116d5 | 1382 | static size_t my_getSmallExpression |
17a2f251 TS |
1383 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1384 | static void my_getExpression (expressionS *, char *); | |
1385 | static void s_align (int); | |
1386 | static void s_change_sec (int); | |
1387 | static void s_change_section (int); | |
1388 | static void s_cons (int); | |
1389 | static void s_float_cons (int); | |
1390 | static void s_mips_globl (int); | |
1391 | static void s_option (int); | |
1392 | static void s_mipsset (int); | |
1393 | static void s_abicalls (int); | |
1394 | static void s_cpload (int); | |
1395 | static void s_cpsetup (int); | |
1396 | static void s_cplocal (int); | |
1397 | static void s_cprestore (int); | |
1398 | static void s_cpreturn (int); | |
741d6ea8 JM |
1399 | static void s_dtprelword (int); |
1400 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1401 | static void s_tprelword (int); |
1402 | static void s_tpreldword (int); | |
17a2f251 TS |
1403 | static void s_gpvalue (int); |
1404 | static void s_gpword (int); | |
1405 | static void s_gpdword (int); | |
a3f278e2 | 1406 | static void s_ehword (int); |
17a2f251 TS |
1407 | static void s_cpadd (int); |
1408 | static void s_insn (int); | |
ba92f887 | 1409 | static void s_nan (int); |
919731af | 1410 | static void s_module (int); |
17a2f251 TS |
1411 | static void s_mips_ent (int); |
1412 | static void s_mips_end (int); | |
1413 | static void s_mips_frame (int); | |
1414 | static void s_mips_mask (int reg_type); | |
1415 | static void s_mips_stab (int); | |
1416 | static void s_mips_weakext (int); | |
1417 | static void s_mips_file (int); | |
1418 | static void s_mips_loc (int); | |
9e009953 | 1419 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1420 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1421 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1422 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1423 | static void file_mips_check_options (void); |
e7af610e NC |
1424 | |
1425 | /* Table and functions used to map between CPU/ISA names, and | |
1426 | ISA levels, and CPU numbers. */ | |
1427 | ||
e972090a NC |
1428 | struct mips_cpu_info |
1429 | { | |
e7af610e | 1430 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1431 | int flags; /* MIPS_CPU_* flags. */ |
1432 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1433 | int isa; /* ISA level. */ |
1434 | int cpu; /* CPU number (default CPU if ISA). */ | |
1435 | }; | |
1436 | ||
ad3fea08 | 1437 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1438 | |
17a2f251 TS |
1439 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1440 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1441 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1442 | \f |
c31f3936 RS |
1443 | /* Command-line options. */ |
1444 | const char *md_shortopts = "O::g::G:"; | |
1445 | ||
1446 | enum options | |
1447 | { | |
1448 | OPTION_MARCH = OPTION_MD_BASE, | |
1449 | OPTION_MTUNE, | |
1450 | OPTION_MIPS1, | |
1451 | OPTION_MIPS2, | |
1452 | OPTION_MIPS3, | |
1453 | OPTION_MIPS4, | |
1454 | OPTION_MIPS5, | |
1455 | OPTION_MIPS32, | |
1456 | OPTION_MIPS64, | |
1457 | OPTION_MIPS32R2, | |
ae52f483 AB |
1458 | OPTION_MIPS32R3, |
1459 | OPTION_MIPS32R5, | |
7361da2c | 1460 | OPTION_MIPS32R6, |
c31f3936 | 1461 | OPTION_MIPS64R2, |
ae52f483 AB |
1462 | OPTION_MIPS64R3, |
1463 | OPTION_MIPS64R5, | |
7361da2c | 1464 | OPTION_MIPS64R6, |
c31f3936 RS |
1465 | OPTION_MIPS16, |
1466 | OPTION_NO_MIPS16, | |
1467 | OPTION_MIPS3D, | |
1468 | OPTION_NO_MIPS3D, | |
1469 | OPTION_MDMX, | |
1470 | OPTION_NO_MDMX, | |
1471 | OPTION_DSP, | |
1472 | OPTION_NO_DSP, | |
1473 | OPTION_MT, | |
1474 | OPTION_NO_MT, | |
1475 | OPTION_VIRT, | |
1476 | OPTION_NO_VIRT, | |
56d438b1 CF |
1477 | OPTION_MSA, |
1478 | OPTION_NO_MSA, | |
c31f3936 RS |
1479 | OPTION_SMARTMIPS, |
1480 | OPTION_NO_SMARTMIPS, | |
1481 | OPTION_DSPR2, | |
1482 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1483 | OPTION_DSPR3, |
1484 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1485 | OPTION_EVA, |
1486 | OPTION_NO_EVA, | |
7d64c587 AB |
1487 | OPTION_XPA, |
1488 | OPTION_NO_XPA, | |
c31f3936 RS |
1489 | OPTION_MICROMIPS, |
1490 | OPTION_NO_MICROMIPS, | |
1491 | OPTION_MCU, | |
1492 | OPTION_NO_MCU, | |
25499ac7 MR |
1493 | OPTION_MIPS16E2, |
1494 | OPTION_NO_MIPS16E2, | |
730c3174 SE |
1495 | OPTION_CRC, |
1496 | OPTION_NO_CRC, | |
c31f3936 RS |
1497 | OPTION_M4650, |
1498 | OPTION_NO_M4650, | |
1499 | OPTION_M4010, | |
1500 | OPTION_NO_M4010, | |
1501 | OPTION_M4100, | |
1502 | OPTION_NO_M4100, | |
1503 | OPTION_M3900, | |
1504 | OPTION_NO_M3900, | |
1505 | OPTION_M7000_HILO_FIX, | |
1506 | OPTION_MNO_7000_HILO_FIX, | |
1507 | OPTION_FIX_24K, | |
1508 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1509 | OPTION_FIX_RM7000, |
1510 | OPTION_NO_FIX_RM7000, | |
6f2117ba PH |
1511 | OPTION_FIX_LOONGSON3_LLSC, |
1512 | OPTION_NO_FIX_LOONGSON3_LLSC, | |
c31f3936 RS |
1513 | OPTION_FIX_LOONGSON2F_JUMP, |
1514 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1515 | OPTION_FIX_LOONGSON2F_NOP, | |
1516 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1517 | OPTION_FIX_VR4120, | |
1518 | OPTION_NO_FIX_VR4120, | |
1519 | OPTION_FIX_VR4130, | |
1520 | OPTION_NO_FIX_VR4130, | |
1521 | OPTION_FIX_CN63XXP1, | |
1522 | OPTION_NO_FIX_CN63XXP1, | |
27c634e0 FN |
1523 | OPTION_FIX_R5900, |
1524 | OPTION_NO_FIX_R5900, | |
c31f3936 RS |
1525 | OPTION_TRAP, |
1526 | OPTION_BREAK, | |
1527 | OPTION_EB, | |
1528 | OPTION_EL, | |
1529 | OPTION_FP32, | |
1530 | OPTION_GP32, | |
1531 | OPTION_CONSTRUCT_FLOATS, | |
1532 | OPTION_NO_CONSTRUCT_FLOATS, | |
1533 | OPTION_FP64, | |
351cdf24 | 1534 | OPTION_FPXX, |
c31f3936 RS |
1535 | OPTION_GP64, |
1536 | OPTION_RELAX_BRANCH, | |
1537 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1538 | OPTION_IGNORE_BRANCH_ISA, |
1539 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1540 | OPTION_INSN32, |
1541 | OPTION_NO_INSN32, | |
c31f3936 RS |
1542 | OPTION_MSHARED, |
1543 | OPTION_MNO_SHARED, | |
1544 | OPTION_MSYM32, | |
1545 | OPTION_MNO_SYM32, | |
1546 | OPTION_SOFT_FLOAT, | |
1547 | OPTION_HARD_FLOAT, | |
1548 | OPTION_SINGLE_FLOAT, | |
1549 | OPTION_DOUBLE_FLOAT, | |
1550 | OPTION_32, | |
c31f3936 RS |
1551 | OPTION_CALL_SHARED, |
1552 | OPTION_CALL_NONPIC, | |
1553 | OPTION_NON_SHARED, | |
1554 | OPTION_XGOT, | |
1555 | OPTION_MABI, | |
1556 | OPTION_N32, | |
1557 | OPTION_64, | |
1558 | OPTION_MDEBUG, | |
1559 | OPTION_NO_MDEBUG, | |
1560 | OPTION_PDR, | |
1561 | OPTION_NO_PDR, | |
1562 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1563 | OPTION_NAN, |
351cdf24 MF |
1564 | OPTION_ODD_SPREG, |
1565 | OPTION_NO_ODD_SPREG, | |
6f20c942 FS |
1566 | OPTION_GINV, |
1567 | OPTION_NO_GINV, | |
8095d2f7 CX |
1568 | OPTION_LOONGSON_MMI, |
1569 | OPTION_NO_LOONGSON_MMI, | |
716c08de CX |
1570 | OPTION_LOONGSON_CAM, |
1571 | OPTION_NO_LOONGSON_CAM, | |
bdc6c06e CX |
1572 | OPTION_LOONGSON_EXT, |
1573 | OPTION_NO_LOONGSON_EXT, | |
a693765e CX |
1574 | OPTION_LOONGSON_EXT2, |
1575 | OPTION_NO_LOONGSON_EXT2, | |
c31f3936 RS |
1576 | OPTION_END_OF_ENUM |
1577 | }; | |
1578 | ||
1579 | struct option md_longopts[] = | |
1580 | { | |
1581 | /* Options which specify architecture. */ | |
1582 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1583 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1584 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1585 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1586 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1587 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1588 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1589 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1590 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1591 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1592 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1593 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1594 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1595 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1596 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1597 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1598 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1599 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1600 | |
1601 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1602 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1603 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1604 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1605 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1606 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1607 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1608 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1609 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1610 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1611 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1612 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1613 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1614 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1615 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1616 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1617 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1618 | {"meva", no_argument, NULL, OPTION_EVA}, |
1619 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1620 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1621 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1622 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1623 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1624 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1625 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1626 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1627 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1628 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1629 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
25499ac7 MR |
1630 | {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, |
1631 | {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, | |
730c3174 SE |
1632 | {"mcrc", no_argument, NULL, OPTION_CRC}, |
1633 | {"mno-crc", no_argument, NULL, OPTION_NO_CRC}, | |
6f20c942 FS |
1634 | {"mginv", no_argument, NULL, OPTION_GINV}, |
1635 | {"mno-ginv", no_argument, NULL, OPTION_NO_GINV}, | |
8095d2f7 CX |
1636 | {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI}, |
1637 | {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI}, | |
716c08de CX |
1638 | {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM}, |
1639 | {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM}, | |
bdc6c06e CX |
1640 | {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT}, |
1641 | {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT}, | |
a693765e CX |
1642 | {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2}, |
1643 | {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2}, | |
c31f3936 RS |
1644 | |
1645 | /* Old-style architecture options. Don't add more of these. */ | |
1646 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1647 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1648 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1649 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1650 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1651 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1652 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1653 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1654 | ||
1655 | /* Options which enable bug fixes. */ | |
1656 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1657 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1658 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
6f2117ba PH |
1659 | {"mfix-loongson3-llsc", no_argument, NULL, OPTION_FIX_LOONGSON3_LLSC}, |
1660 | {"mno-fix-loongson3-llsc", no_argument, NULL, OPTION_NO_FIX_LOONGSON3_LLSC}, | |
c31f3936 RS |
1661 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
1662 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1663 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1664 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1665 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1666 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1667 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1668 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1669 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1670 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1671 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1672 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1673 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1674 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
27c634e0 FN |
1675 | {"mfix-r5900", no_argument, NULL, OPTION_FIX_R5900}, |
1676 | {"mno-fix-r5900", no_argument, NULL, OPTION_NO_FIX_R5900}, | |
c31f3936 RS |
1677 | |
1678 | /* Miscellaneous options. */ | |
1679 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1680 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1681 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1682 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1683 | {"EB", no_argument, NULL, OPTION_EB}, | |
1684 | {"EL", no_argument, NULL, OPTION_EL}, | |
1685 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1686 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1687 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1688 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1689 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1690 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1691 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1692 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1693 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1694 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1695 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1696 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1697 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1698 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1699 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1700 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1701 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1702 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1703 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1704 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1705 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1706 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1707 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1708 | |
1709 | /* Strictly speaking this next option is ELF specific, | |
1710 | but we allow it for other ports as well in order to | |
1711 | make testing easier. */ | |
1712 | {"32", no_argument, NULL, OPTION_32}, | |
1713 | ||
1714 | /* ELF-specific options. */ | |
c31f3936 RS |
1715 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1716 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1717 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1718 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1719 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1720 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1721 | {"n32", no_argument, NULL, OPTION_N32}, | |
1722 | {"64", no_argument, NULL, OPTION_64}, | |
1723 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1724 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1725 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1726 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1727 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1728 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1729 | |
1730 | {NULL, no_argument, NULL, 0} | |
1731 | }; | |
1732 | size_t md_longopts_size = sizeof (md_longopts); | |
1733 | \f | |
c6278170 RS |
1734 | /* Information about either an Application Specific Extension or an |
1735 | optional architecture feature that, for simplicity, we treat in the | |
1736 | same way as an ASE. */ | |
1737 | struct mips_ase | |
1738 | { | |
1739 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1740 | const char *name; | |
1741 | ||
1742 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1743 | and 64-bit architectures, the flags here refer to the subset that | |
1744 | is available on both. */ | |
1745 | unsigned int flags; | |
1746 | ||
1747 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1748 | architectures but that are not included in FLAGS. */ | |
1749 | unsigned int flags64; | |
1750 | ||
1751 | /* The command-line options that turn the ASE on and off. */ | |
1752 | int option_on; | |
1753 | int option_off; | |
1754 | ||
1755 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1756 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1757 | int mips32_rev; | |
1758 | int mips64_rev; | |
1759 | int micromips32_rev; | |
1760 | int micromips64_rev; | |
7361da2c AB |
1761 | |
1762 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1763 | been removed. */ | |
1764 | int rem_rev; | |
c6278170 RS |
1765 | }; |
1766 | ||
1767 | /* A table of all supported ASEs. */ | |
1768 | static const struct mips_ase mips_ases[] = { | |
1769 | { "dsp", ASE_DSP, ASE_DSP64, | |
1770 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1771 | 2, 2, 2, 2, |
1772 | -1 }, | |
c6278170 RS |
1773 | |
1774 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1775 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1776 | 2, 2, 2, 2, |
1777 | -1 }, | |
c6278170 | 1778 | |
8f4f9071 MF |
1779 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1780 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1781 | 6, 6, -1, -1, | |
1782 | -1 }, | |
1783 | ||
c6278170 RS |
1784 | { "eva", ASE_EVA, 0, |
1785 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1786 | 2, 2, 2, 2, |
1787 | -1 }, | |
c6278170 RS |
1788 | |
1789 | { "mcu", ASE_MCU, 0, | |
1790 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1791 | 2, 2, 2, 2, |
1792 | -1 }, | |
c6278170 RS |
1793 | |
1794 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1795 | { "mdmx", ASE_MDMX, 0, | |
1796 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1797 | -1, 1, -1, -1, |
1798 | 6 }, | |
c6278170 RS |
1799 | |
1800 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1801 | { "mips3d", ASE_MIPS3D, 0, | |
1802 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1803 | 2, 1, -1, -1, |
1804 | 6 }, | |
c6278170 RS |
1805 | |
1806 | { "mt", ASE_MT, 0, | |
1807 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1808 | 2, 2, -1, -1, |
1809 | -1 }, | |
c6278170 RS |
1810 | |
1811 | { "smartmips", ASE_SMARTMIPS, 0, | |
1812 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1813 | 1, -1, -1, -1, |
1814 | 6 }, | |
c6278170 RS |
1815 | |
1816 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1817 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1818 | 2, 2, 2, 2, |
1819 | -1 }, | |
56d438b1 CF |
1820 | |
1821 | { "msa", ASE_MSA, ASE_MSA64, | |
1822 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1823 | 2, 2, 2, 2, |
1824 | -1 }, | |
7d64c587 AB |
1825 | |
1826 | { "xpa", ASE_XPA, 0, | |
1827 | OPTION_XPA, OPTION_NO_XPA, | |
909b4e3d | 1828 | 2, 2, 2, 2, |
7361da2c | 1829 | -1 }, |
25499ac7 MR |
1830 | |
1831 | { "mips16e2", ASE_MIPS16E2, 0, | |
1832 | OPTION_MIPS16E2, OPTION_NO_MIPS16E2, | |
1833 | 2, 2, -1, -1, | |
1834 | 6 }, | |
730c3174 SE |
1835 | |
1836 | { "crc", ASE_CRC, ASE_CRC64, | |
1837 | OPTION_CRC, OPTION_NO_CRC, | |
1838 | 6, 6, -1, -1, | |
1839 | -1 }, | |
6f20c942 FS |
1840 | |
1841 | { "ginv", ASE_GINV, 0, | |
1842 | OPTION_GINV, OPTION_NO_GINV, | |
1843 | 6, 6, 6, 6, | |
1844 | -1 }, | |
8095d2f7 CX |
1845 | |
1846 | { "loongson-mmi", ASE_LOONGSON_MMI, 0, | |
1847 | OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI, | |
1848 | 0, 0, -1, -1, | |
1849 | -1 }, | |
716c08de CX |
1850 | |
1851 | { "loongson-cam", ASE_LOONGSON_CAM, 0, | |
1852 | OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM, | |
1853 | 0, 0, -1, -1, | |
1854 | -1 }, | |
bdc6c06e CX |
1855 | |
1856 | { "loongson-ext", ASE_LOONGSON_EXT, 0, | |
1857 | OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT, | |
1858 | 0, 0, -1, -1, | |
1859 | -1 }, | |
a693765e CX |
1860 | |
1861 | { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0, | |
1862 | OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2, | |
1863 | 0, 0, -1, -1, | |
1864 | -1 }, | |
c6278170 RS |
1865 | }; |
1866 | ||
1867 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1868 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1869 | |
1870 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1871 | static const unsigned int mips_ase_groups[] = { | |
a693765e CX |
1872 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3, |
1873 | ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2 | |
c6278170 RS |
1874 | }; |
1875 | \f | |
252b5132 RH |
1876 | /* Pseudo-op table. |
1877 | ||
1878 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1879 | should be defined here, but are currently unsupported: .alias, | |
1880 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1881 | ||
1882 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1883 | specific to the type of debugging information being generated, and | |
1884 | should be defined by the object format: .aent, .begin, .bend, | |
1885 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1886 | .vreg. | |
1887 | ||
1888 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1889 | not MIPS CPU specific, but are also not specific to the object file | |
1890 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1891 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1892 | |
e972090a NC |
1893 | static const pseudo_typeS mips_pseudo_table[] = |
1894 | { | |
beae10d5 | 1895 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1896 | {"option", s_option, 0}, |
1897 | {"set", s_mipsset, 0}, | |
1898 | {"rdata", s_change_sec, 'r'}, | |
1899 | {"sdata", s_change_sec, 's'}, | |
1900 | {"livereg", s_ignore, 0}, | |
1901 | {"abicalls", s_abicalls, 0}, | |
1902 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1903 | {"cpsetup", s_cpsetup, 0}, |
1904 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1905 | {"cprestore", s_cprestore, 0}, |
6478892d | 1906 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1907 | {"dtprelword", s_dtprelword, 0}, |
1908 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1909 | {"tprelword", s_tprelword, 0}, |
1910 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1911 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1912 | {"gpword", s_gpword, 0}, |
10181a0d | 1913 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1914 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1915 | {"cpadd", s_cpadd, 0}, |
1916 | {"insn", s_insn, 0}, | |
ba92f887 | 1917 | {"nan", s_nan, 0}, |
919731af | 1918 | {"module", s_module, 0}, |
252b5132 | 1919 | |
beae10d5 | 1920 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1921 | chips. */ |
38a57ae7 | 1922 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1923 | {"bss", s_change_sec, 'b'}, |
1924 | {"err", s_err, 0}, | |
1925 | {"half", s_cons, 1}, | |
1926 | {"dword", s_cons, 3}, | |
1927 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1928 | {"origin", s_org, 0}, |
1929 | {"repeat", s_rept, 0}, | |
252b5132 | 1930 | |
998b3c36 MR |
1931 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1932 | {"sbss", s_change_sec, 'B'}, | |
1933 | ||
beae10d5 | 1934 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1935 | here for one reason or another. */ |
1936 | {"align", s_align, 0}, | |
1937 | {"byte", s_cons, 0}, | |
1938 | {"data", s_change_sec, 'd'}, | |
1939 | {"double", s_float_cons, 'd'}, | |
1940 | {"float", s_float_cons, 'f'}, | |
1941 | {"globl", s_mips_globl, 0}, | |
1942 | {"global", s_mips_globl, 0}, | |
1943 | {"hword", s_cons, 1}, | |
1944 | {"int", s_cons, 2}, | |
1945 | {"long", s_cons, 2}, | |
1946 | {"octa", s_cons, 4}, | |
1947 | {"quad", s_cons, 3}, | |
cca86cc8 | 1948 | {"section", s_change_section, 0}, |
252b5132 RH |
1949 | {"short", s_cons, 1}, |
1950 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1951 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1952 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1953 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1954 | {"text", s_change_sec, 't'}, |
1955 | {"word", s_cons, 2}, | |
add56521 | 1956 | |
add56521 | 1957 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1958 | |
43841e91 | 1959 | { NULL, NULL, 0 }, |
252b5132 RH |
1960 | }; |
1961 | ||
e972090a NC |
1962 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1963 | { | |
beae10d5 KH |
1964 | /* These pseudo-ops should be defined by the object file format. |
1965 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1966 | {"aent", s_mips_ent, 1}, |
1967 | {"bgnb", s_ignore, 0}, | |
1968 | {"end", s_mips_end, 0}, | |
1969 | {"endb", s_ignore, 0}, | |
1970 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1971 | {"file", s_mips_file, 0}, |
252b5132 RH |
1972 | {"fmask", s_mips_mask, 'F'}, |
1973 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1974 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1975 | {"mask", s_mips_mask, 'R'}, |
1976 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1977 | { NULL, NULL, 0 }, |
252b5132 RH |
1978 | }; |
1979 | ||
3ae8dd8d MR |
1980 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1981 | purpose of the `.dc.a' internal pseudo-op. */ | |
1982 | ||
1983 | int | |
1984 | mips_address_bytes (void) | |
1985 | { | |
919731af | 1986 | file_mips_check_options (); |
3ae8dd8d MR |
1987 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1988 | } | |
1989 | ||
17a2f251 | 1990 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1991 | |
1992 | void | |
17a2f251 | 1993 | mips_pop_insert (void) |
252b5132 RH |
1994 | { |
1995 | pop_insert (mips_pseudo_table); | |
1996 | if (! ECOFF_DEBUGGING) | |
1997 | pop_insert (mips_nonecoff_pseudo_table); | |
1998 | } | |
1999 | \f | |
2000 | /* Symbols labelling the current insn. */ | |
2001 | ||
e972090a NC |
2002 | struct insn_label_list |
2003 | { | |
252b5132 RH |
2004 | struct insn_label_list *next; |
2005 | symbolS *label; | |
2006 | }; | |
2007 | ||
252b5132 | 2008 | static struct insn_label_list *free_insn_labels; |
742a56fe | 2009 | #define label_list tc_segment_info_data.labels |
252b5132 | 2010 | |
17a2f251 | 2011 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
2012 | static void mips_mark_labels (void); |
2013 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
2014 | |
2015 | static inline void | |
17a2f251 | 2016 | mips_clear_insn_labels (void) |
252b5132 | 2017 | { |
ed9e98c2 | 2018 | struct insn_label_list **pl; |
a8dbcb85 | 2019 | segment_info_type *si; |
252b5132 | 2020 | |
a8dbcb85 TS |
2021 | if (now_seg) |
2022 | { | |
2023 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
2024 | ; | |
3739860c | 2025 | |
a8dbcb85 TS |
2026 | si = seg_info (now_seg); |
2027 | *pl = si->label_list; | |
2028 | si->label_list = NULL; | |
2029 | } | |
252b5132 | 2030 | } |
a8dbcb85 | 2031 | |
df58fc94 RS |
2032 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
2033 | ||
2034 | static inline void | |
2035 | mips_mark_labels (void) | |
2036 | { | |
2037 | if (HAVE_CODE_COMPRESSION) | |
2038 | mips_compressed_mark_labels (); | |
2039 | } | |
252b5132 RH |
2040 | \f |
2041 | static char *expr_end; | |
2042 | ||
e423441d | 2043 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 2044 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
2045 | |
2046 | static expressionS imm_expr; | |
252b5132 | 2047 | |
77bd4346 RS |
2048 | /* The relocatable field in an instruction and the relocs associated |
2049 | with it. These variables are used for instructions like LUI and | |
2050 | JAL as well as true offsets. They are also used for address | |
2051 | operands in macros. */ | |
252b5132 | 2052 | |
77bd4346 | 2053 | static expressionS offset_expr; |
f6688943 TS |
2054 | static bfd_reloc_code_real_type offset_reloc[3] |
2055 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 2056 | |
df58fc94 RS |
2057 | /* This is set to the resulting size of the instruction to be produced |
2058 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
2059 | explicit size is supplied. */ | |
252b5132 | 2060 | |
df58fc94 | 2061 | static unsigned int forced_insn_length; |
252b5132 | 2062 | |
e1b47bd5 RS |
2063 | /* True if we are assembling an instruction. All dot symbols defined during |
2064 | this time should be treated as code labels. */ | |
2065 | ||
2066 | static bfd_boolean mips_assembling_insn; | |
2067 | ||
ecb4347a DJ |
2068 | /* The pdr segment for per procedure frame/regmask info. Not used for |
2069 | ECOFF debugging. */ | |
252b5132 RH |
2070 | |
2071 | static segT pdr_seg; | |
252b5132 | 2072 | |
e013f690 TS |
2073 | /* The default target format to use. */ |
2074 | ||
aeffff67 RS |
2075 | #if defined (TE_FreeBSD) |
2076 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
2077 | #elif defined (TE_TMIPS) | |
2078 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
2079 | #else | |
2080 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
2081 | #endif | |
2082 | ||
e013f690 | 2083 | const char * |
17a2f251 | 2084 | mips_target_format (void) |
e013f690 TS |
2085 | { |
2086 | switch (OUTPUT_FLAVOR) | |
2087 | { | |
e013f690 | 2088 | case bfd_target_elf_flavour: |
0a44bf69 RS |
2089 | #ifdef TE_VXWORKS |
2090 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
2091 | return (target_big_endian | |
2092 | ? "elf32-bigmips-vxworks" | |
2093 | : "elf32-littlemips-vxworks"); | |
2094 | #endif | |
e013f690 | 2095 | return (target_big_endian |
cfe86eaa | 2096 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 2097 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 2098 | : (HAVE_NEWABI |
aeffff67 RS |
2099 | ? ELF_TARGET ("elf32-n", "big") |
2100 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 2101 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 2102 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 2103 | : (HAVE_NEWABI |
aeffff67 RS |
2104 | ? ELF_TARGET ("elf32-n", "little") |
2105 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2106 | default: |
2107 | abort (); | |
2108 | return NULL; | |
2109 | } | |
2110 | } | |
2111 | ||
c6278170 RS |
2112 | /* Return the ISA revision that is currently in use, or 0 if we are |
2113 | generating code for MIPS V or below. */ | |
2114 | ||
2115 | static int | |
2116 | mips_isa_rev (void) | |
2117 | { | |
2118 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2119 | return 2; | |
2120 | ||
ae52f483 AB |
2121 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2122 | return 3; | |
2123 | ||
2124 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2125 | return 5; | |
2126 | ||
7361da2c AB |
2127 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2128 | return 6; | |
2129 | ||
c6278170 RS |
2130 | /* microMIPS implies revision 2 or above. */ |
2131 | if (mips_opts.micromips) | |
2132 | return 2; | |
2133 | ||
2134 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2135 | return 1; | |
2136 | ||
2137 | return 0; | |
2138 | } | |
2139 | ||
2140 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2141 | ||
2142 | static unsigned int | |
2143 | mips_ase_mask (unsigned int flags) | |
2144 | { | |
2145 | unsigned int i; | |
2146 | ||
2147 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2148 | if (flags & mips_ase_groups[i]) | |
2149 | flags |= mips_ase_groups[i]; | |
2150 | return flags; | |
2151 | } | |
2152 | ||
2153 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2154 | appropriate. */ | |
2155 | ||
2156 | static void | |
2157 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2158 | { | |
2159 | const char *base; | |
2160 | int min_rev, size; | |
2161 | static unsigned int warned_isa; | |
2162 | static unsigned int warned_fp32; | |
2163 | ||
2164 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2165 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2166 | else | |
2167 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2168 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2169 | && (warned_isa & ase->flags) != ase->flags) | |
2170 | { | |
2171 | warned_isa |= ase->flags; | |
2172 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2173 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2174 | if (min_rev < 0) | |
1661c76c | 2175 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2176 | " `%s' extension"), size, base, ase->name); |
2177 | else | |
1661c76c | 2178 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2179 | ase->name, base, size, min_rev); |
2180 | } | |
7361da2c AB |
2181 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2182 | && (warned_isa & ase->flags) != ase->flags) | |
2183 | { | |
2184 | warned_isa |= ase->flags; | |
2185 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2186 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2187 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2188 | ase->name, base, size, ase->rem_rev); | |
2189 | } | |
2190 | ||
c6278170 | 2191 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2192 | && mips_opts.fp != 64 |
c6278170 RS |
2193 | && (warned_fp32 & ase->flags) != ase->flags) |
2194 | { | |
2195 | warned_fp32 |= ase->flags; | |
1661c76c | 2196 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2197 | } |
2198 | } | |
2199 | ||
2200 | /* Check all enabled ASEs to see whether they are supported by the | |
2201 | chosen architecture. */ | |
2202 | ||
2203 | static void | |
2204 | mips_check_isa_supports_ases (void) | |
2205 | { | |
2206 | unsigned int i, mask; | |
2207 | ||
2208 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2209 | { | |
2210 | mask = mips_ase_mask (mips_ases[i].flags); | |
2211 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2212 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2217 | that were affected. */ | |
2218 | ||
2219 | static unsigned int | |
919731af | 2220 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2221 | bfd_boolean enabled_p) | |
c6278170 RS |
2222 | { |
2223 | unsigned int mask; | |
2224 | ||
2225 | mask = mips_ase_mask (ase->flags); | |
919731af | 2226 | opts->ase &= ~mask; |
92cebb3d MR |
2227 | |
2228 | /* Clear combination ASE flags, which need to be recalculated based on | |
2229 | updated regular ASE settings. */ | |
41cee089 | 2230 | opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6); |
92cebb3d | 2231 | |
c6278170 | 2232 | if (enabled_p) |
919731af | 2233 | opts->ase |= ase->flags; |
25499ac7 | 2234 | |
9785fc2a MR |
2235 | /* The Virtualization ASE has eXtended Physical Addressing (XPA) |
2236 | instructions which are only valid when both ASEs are enabled. | |
2237 | This sets the ASE_XPA_VIRT flag when both ASEs are present. */ | |
2238 | if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) | |
2239 | { | |
2240 | opts->ase |= ASE_XPA_VIRT; | |
2241 | mask |= ASE_XPA_VIRT; | |
2242 | } | |
25499ac7 MR |
2243 | if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) |
2244 | { | |
2245 | opts->ase |= ASE_MIPS16E2_MT; | |
2246 | mask |= ASE_MIPS16E2_MT; | |
2247 | } | |
2248 | ||
41cee089 FS |
2249 | /* The EVA Extension has instructions which are only valid when the R6 ISA |
2250 | is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are | |
2251 | present. */ | |
2252 | if (((opts->ase & ASE_EVA) != 0) && ISA_IS_R6 (opts->isa)) | |
2253 | { | |
2254 | opts->ase |= ASE_EVA_R6; | |
2255 | mask |= ASE_EVA_R6; | |
2256 | } | |
2257 | ||
c6278170 RS |
2258 | return mask; |
2259 | } | |
2260 | ||
2261 | /* Return the ASE called NAME, or null if none. */ | |
2262 | ||
2263 | static const struct mips_ase * | |
2264 | mips_lookup_ase (const char *name) | |
2265 | { | |
2266 | unsigned int i; | |
2267 | ||
2268 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2269 | if (strcmp (name, mips_ases[i].name) == 0) | |
2270 | return &mips_ases[i]; | |
2271 | return NULL; | |
2272 | } | |
2273 | ||
df58fc94 | 2274 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2275 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2276 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2277 | |
2278 | static inline unsigned int | |
2279 | micromips_insn_length (const struct mips_opcode *mo) | |
2280 | { | |
7fd53920 | 2281 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2282 | } |
2283 | ||
5c04167a RS |
2284 | /* Return the length of MIPS16 instruction OPCODE. */ |
2285 | ||
2286 | static inline unsigned int | |
2287 | mips16_opcode_length (unsigned long opcode) | |
2288 | { | |
2289 | return (opcode >> 16) == 0 ? 2 : 4; | |
2290 | } | |
2291 | ||
1e915849 RS |
2292 | /* Return the length of instruction INSN. */ |
2293 | ||
2294 | static inline unsigned int | |
2295 | insn_length (const struct mips_cl_insn *insn) | |
2296 | { | |
df58fc94 RS |
2297 | if (mips_opts.micromips) |
2298 | return micromips_insn_length (insn->insn_mo); | |
2299 | else if (mips_opts.mips16) | |
5c04167a | 2300 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2301 | else |
1e915849 | 2302 | return 4; |
1e915849 RS |
2303 | } |
2304 | ||
2305 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2306 | ||
2307 | static void | |
2308 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2309 | { | |
2310 | size_t i; | |
2311 | ||
2312 | insn->insn_mo = mo; | |
1e915849 RS |
2313 | insn->insn_opcode = mo->match; |
2314 | insn->frag = NULL; | |
2315 | insn->where = 0; | |
2316 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2317 | insn->fixp[i] = NULL; | |
2318 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2319 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2320 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2321 | insn->complete_p = 0; |
e407c74b | 2322 | insn->cleared_p = 0; |
1e915849 RS |
2323 | } |
2324 | ||
fc76e730 RS |
2325 | /* Get a list of all the operands in INSN. */ |
2326 | ||
2327 | static const struct mips_operand_array * | |
2328 | insn_operands (const struct mips_cl_insn *insn) | |
2329 | { | |
2330 | if (insn->insn_mo >= &mips_opcodes[0] | |
2331 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2332 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2333 | ||
2334 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2335 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2336 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2337 | ||
2338 | if (insn->insn_mo >= µmips_opcodes[0] | |
2339 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2340 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2341 | ||
2342 | abort (); | |
2343 | } | |
2344 | ||
2345 | /* Get a description of operand OPNO of INSN. */ | |
2346 | ||
2347 | static const struct mips_operand * | |
2348 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2349 | { | |
2350 | const struct mips_operand_array *operands; | |
2351 | ||
2352 | operands = insn_operands (insn); | |
2353 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2354 | abort (); | |
2355 | return operands->operand[opno]; | |
2356 | } | |
2357 | ||
e077a1c8 RS |
2358 | /* Install UVAL as the value of OPERAND in INSN. */ |
2359 | ||
2360 | static inline void | |
2361 | insn_insert_operand (struct mips_cl_insn *insn, | |
2362 | const struct mips_operand *operand, unsigned int uval) | |
2363 | { | |
25499ac7 MR |
2364 | if (mips_opts.mips16 |
2365 | && operand->type == OP_INT && operand->lsb == 0 | |
2366 | && mips_opcode_32bit_p (insn->insn_mo)) | |
2367 | insn->insn_opcode |= mips16_immed_extend (uval, operand->size); | |
2368 | else | |
2369 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
e077a1c8 RS |
2370 | } |
2371 | ||
fc76e730 RS |
2372 | /* Extract the value of OPERAND from INSN. */ |
2373 | ||
2374 | static inline unsigned | |
2375 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2376 | const struct mips_operand *operand) | |
2377 | { | |
2378 | return mips_extract_operand (operand, insn->insn_opcode); | |
2379 | } | |
2380 | ||
df58fc94 | 2381 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2382 | |
2383 | static void | |
df58fc94 | 2384 | mips_record_compressed_mode (void) |
742a56fe RS |
2385 | { |
2386 | segment_info_type *si; | |
2387 | ||
2388 | si = seg_info (now_seg); | |
2389 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2390 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2391 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2392 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2393 | } |
2394 | ||
4d68580a RS |
2395 | /* Read a standard MIPS instruction from BUF. */ |
2396 | ||
2397 | static unsigned long | |
2398 | read_insn (char *buf) | |
2399 | { | |
2400 | if (target_big_endian) | |
2401 | return bfd_getb32 ((bfd_byte *) buf); | |
2402 | else | |
2403 | return bfd_getl32 ((bfd_byte *) buf); | |
2404 | } | |
2405 | ||
2406 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2407 | the next byte. */ | |
2408 | ||
2409 | static char * | |
2410 | write_insn (char *buf, unsigned int insn) | |
2411 | { | |
2412 | md_number_to_chars (buf, insn, 4); | |
2413 | return buf + 4; | |
2414 | } | |
2415 | ||
2416 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2417 | has length LENGTH. */ | |
2418 | ||
2419 | static unsigned long | |
2420 | read_compressed_insn (char *buf, unsigned int length) | |
2421 | { | |
2422 | unsigned long insn; | |
2423 | unsigned int i; | |
2424 | ||
2425 | insn = 0; | |
2426 | for (i = 0; i < length; i += 2) | |
2427 | { | |
2428 | insn <<= 16; | |
2429 | if (target_big_endian) | |
2430 | insn |= bfd_getb16 ((char *) buf); | |
2431 | else | |
2432 | insn |= bfd_getl16 ((char *) buf); | |
2433 | buf += 2; | |
2434 | } | |
2435 | return insn; | |
2436 | } | |
2437 | ||
5c04167a RS |
2438 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2439 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2440 | ||
2441 | static char * | |
2442 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2443 | { | |
2444 | unsigned int i; | |
2445 | ||
2446 | for (i = 0; i < length; i += 2) | |
2447 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2448 | return buf + length; | |
2449 | } | |
2450 | ||
1e915849 RS |
2451 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2452 | ||
2453 | static void | |
2454 | install_insn (const struct mips_cl_insn *insn) | |
2455 | { | |
2456 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2457 | if (HAVE_CODE_COMPRESSION) |
2458 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2459 | else |
4d68580a | 2460 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2461 | mips_record_compressed_mode (); |
1e915849 RS |
2462 | } |
2463 | ||
2464 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2465 | and install the opcode in the new location. */ | |
2466 | ||
2467 | static void | |
2468 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2469 | { | |
2470 | size_t i; | |
2471 | ||
2472 | insn->frag = frag; | |
2473 | insn->where = where; | |
2474 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2475 | if (insn->fixp[i] != NULL) | |
2476 | { | |
2477 | insn->fixp[i]->fx_frag = frag; | |
2478 | insn->fixp[i]->fx_where = where; | |
2479 | } | |
2480 | install_insn (insn); | |
2481 | } | |
2482 | ||
2483 | /* Add INSN to the end of the output. */ | |
2484 | ||
2485 | static void | |
2486 | add_fixed_insn (struct mips_cl_insn *insn) | |
2487 | { | |
2488 | char *f = frag_more (insn_length (insn)); | |
2489 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2490 | } | |
2491 | ||
2492 | /* Start a variant frag and move INSN to the start of the variant part, | |
2493 | marking it as fixed. The other arguments are as for frag_var. */ | |
2494 | ||
2495 | static void | |
2496 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2497 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2498 | { | |
2499 | frag_grow (max_chars); | |
2500 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2501 | insn->fixed_p = 1; | |
2502 | frag_var (rs_machine_dependent, max_chars, var, | |
2503 | subtype, symbol, offset, NULL); | |
2504 | } | |
2505 | ||
2506 | /* Insert N copies of INSN into the history buffer, starting at | |
2507 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2508 | ||
2509 | static void | |
2510 | insert_into_history (unsigned int first, unsigned int n, | |
2511 | const struct mips_cl_insn *insn) | |
2512 | { | |
2513 | if (mips_relax.sequence != 2) | |
2514 | { | |
2515 | unsigned int i; | |
2516 | ||
2517 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2518 | if (i >= first + n) | |
2519 | history[i] = history[i - n]; | |
2520 | else | |
2521 | history[i] = *insn; | |
2522 | } | |
2523 | } | |
2524 | ||
e3de51ce RS |
2525 | /* Clear the error in insn_error. */ |
2526 | ||
2527 | static void | |
2528 | clear_insn_error (void) | |
2529 | { | |
2530 | memset (&insn_error, 0, sizeof (insn_error)); | |
2531 | } | |
2532 | ||
2533 | /* Possibly record error message MSG for the current instruction. | |
2534 | If the error is about a particular argument, ARGNUM is the 1-based | |
2535 | number of that argument, otherwise it is 0. FORMAT is the format | |
2536 | of MSG. Return true if MSG was used, false if the current message | |
2537 | was kept. */ | |
2538 | ||
2539 | static bfd_boolean | |
2540 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2541 | const char *msg) | |
2542 | { | |
2543 | if (argnum == 0) | |
2544 | { | |
2545 | /* Give priority to errors against specific arguments, and to | |
2546 | the first whole-instruction message. */ | |
2547 | if (insn_error.msg) | |
2548 | return FALSE; | |
2549 | } | |
2550 | else | |
2551 | { | |
2552 | /* Keep insn_error if it is against a later argument. */ | |
2553 | if (argnum < insn_error.min_argnum) | |
2554 | return FALSE; | |
2555 | ||
2556 | /* If both errors are against the same argument but are different, | |
2557 | give up on reporting a specific error for this argument. | |
2558 | See the comment about mips_insn_error for details. */ | |
2559 | if (argnum == insn_error.min_argnum | |
2560 | && insn_error.msg | |
2561 | && strcmp (insn_error.msg, msg) != 0) | |
2562 | { | |
2563 | insn_error.msg = 0; | |
2564 | insn_error.min_argnum += 1; | |
2565 | return FALSE; | |
2566 | } | |
2567 | } | |
2568 | insn_error.min_argnum = argnum; | |
2569 | insn_error.format = format; | |
2570 | insn_error.msg = msg; | |
2571 | return TRUE; | |
2572 | } | |
2573 | ||
2574 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2575 | as for set_insn_error_format. */ | |
2576 | ||
2577 | static void | |
2578 | set_insn_error (int argnum, const char *msg) | |
2579 | { | |
2580 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2581 | } | |
2582 | ||
2583 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2584 | as for set_insn_error_format. */ | |
2585 | ||
2586 | static void | |
2587 | set_insn_error_i (int argnum, const char *msg, int i) | |
2588 | { | |
2589 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2590 | insn_error.u.i = i; | |
2591 | } | |
2592 | ||
2593 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2594 | are as for set_insn_error_format. */ | |
2595 | ||
2596 | static void | |
2597 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2598 | { | |
2599 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2600 | { | |
2601 | insn_error.u.ss[0] = s1; | |
2602 | insn_error.u.ss[1] = s2; | |
2603 | } | |
2604 | } | |
2605 | ||
2606 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2607 | ||
2608 | static void | |
2609 | report_insn_error (const char *str) | |
2610 | { | |
e1fa0163 | 2611 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2612 | |
e3de51ce RS |
2613 | switch (insn_error.format) |
2614 | { | |
2615 | case ERR_FMT_PLAIN: | |
2616 | as_bad (msg, str); | |
2617 | break; | |
2618 | ||
2619 | case ERR_FMT_I: | |
2620 | as_bad (msg, insn_error.u.i, str); | |
2621 | break; | |
2622 | ||
2623 | case ERR_FMT_SS: | |
2624 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2625 | break; | |
2626 | } | |
e1fa0163 NC |
2627 | |
2628 | free ((char *) msg); | |
e3de51ce RS |
2629 | } |
2630 | ||
71400594 RS |
2631 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2632 | the idea is to make it obvious at a glance that each errata is | |
2633 | included. */ | |
2634 | ||
2635 | static void | |
2636 | init_vr4120_conflicts (void) | |
2637 | { | |
2638 | #define CONFLICT(FIRST, SECOND) \ | |
2639 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2640 | ||
2641 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2642 | CONFLICT (MACC, DIV); | |
2643 | CONFLICT (DMACC, DIV); | |
2644 | ||
2645 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2646 | CONFLICT (DMULT, DMULT); | |
2647 | CONFLICT (DMULT, DMACC); | |
2648 | CONFLICT (DMACC, DMULT); | |
2649 | CONFLICT (DMACC, DMACC); | |
2650 | ||
2651 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2652 | CONFLICT (MACC, MTHILO); | |
2653 | CONFLICT (DMACC, MTHILO); | |
2654 | ||
2655 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2656 | instruction is executed immediately after a MACC or DMACC | |
2657 | instruction, the result of [either instruction] is incorrect." */ | |
2658 | CONFLICT (MACC, MULT); | |
2659 | CONFLICT (MACC, DMULT); | |
2660 | CONFLICT (DMACC, MULT); | |
2661 | CONFLICT (DMACC, DMULT); | |
2662 | ||
2663 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2664 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2665 | DDIV or DDIVU instruction, the result of the MACC or | |
2666 | DMACC instruction is incorrect.". */ | |
2667 | CONFLICT (DMULT, MACC); | |
2668 | CONFLICT (DMULT, DMACC); | |
2669 | CONFLICT (DIV, MACC); | |
2670 | CONFLICT (DIV, DMACC); | |
2671 | ||
2672 | #undef CONFLICT | |
2673 | } | |
2674 | ||
707bfff6 TS |
2675 | struct regname { |
2676 | const char *name; | |
2677 | unsigned int num; | |
2678 | }; | |
2679 | ||
14daeee3 | 2680 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2681 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2682 | #define RTYPE_NUM 0x0000100 |
2683 | #define RTYPE_FPU 0x0000200 | |
2684 | #define RTYPE_FCC 0x0000400 | |
2685 | #define RTYPE_VEC 0x0000800 | |
2686 | #define RTYPE_GP 0x0001000 | |
2687 | #define RTYPE_CP0 0x0002000 | |
2688 | #define RTYPE_PC 0x0004000 | |
2689 | #define RTYPE_ACC 0x0008000 | |
2690 | #define RTYPE_CCC 0x0010000 | |
2691 | #define RTYPE_VI 0x0020000 | |
2692 | #define RTYPE_VF 0x0040000 | |
2693 | #define RTYPE_R5900_I 0x0080000 | |
2694 | #define RTYPE_R5900_Q 0x0100000 | |
2695 | #define RTYPE_R5900_R 0x0200000 | |
2696 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2697 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2698 | #define RWARN 0x8000000 |
707bfff6 TS |
2699 | |
2700 | #define GENERIC_REGISTER_NUMBERS \ | |
2701 | {"$0", RTYPE_NUM | 0}, \ | |
2702 | {"$1", RTYPE_NUM | 1}, \ | |
2703 | {"$2", RTYPE_NUM | 2}, \ | |
2704 | {"$3", RTYPE_NUM | 3}, \ | |
2705 | {"$4", RTYPE_NUM | 4}, \ | |
2706 | {"$5", RTYPE_NUM | 5}, \ | |
2707 | {"$6", RTYPE_NUM | 6}, \ | |
2708 | {"$7", RTYPE_NUM | 7}, \ | |
2709 | {"$8", RTYPE_NUM | 8}, \ | |
2710 | {"$9", RTYPE_NUM | 9}, \ | |
2711 | {"$10", RTYPE_NUM | 10}, \ | |
2712 | {"$11", RTYPE_NUM | 11}, \ | |
2713 | {"$12", RTYPE_NUM | 12}, \ | |
2714 | {"$13", RTYPE_NUM | 13}, \ | |
2715 | {"$14", RTYPE_NUM | 14}, \ | |
2716 | {"$15", RTYPE_NUM | 15}, \ | |
2717 | {"$16", RTYPE_NUM | 16}, \ | |
2718 | {"$17", RTYPE_NUM | 17}, \ | |
2719 | {"$18", RTYPE_NUM | 18}, \ | |
2720 | {"$19", RTYPE_NUM | 19}, \ | |
2721 | {"$20", RTYPE_NUM | 20}, \ | |
2722 | {"$21", RTYPE_NUM | 21}, \ | |
2723 | {"$22", RTYPE_NUM | 22}, \ | |
2724 | {"$23", RTYPE_NUM | 23}, \ | |
2725 | {"$24", RTYPE_NUM | 24}, \ | |
2726 | {"$25", RTYPE_NUM | 25}, \ | |
2727 | {"$26", RTYPE_NUM | 26}, \ | |
2728 | {"$27", RTYPE_NUM | 27}, \ | |
2729 | {"$28", RTYPE_NUM | 28}, \ | |
2730 | {"$29", RTYPE_NUM | 29}, \ | |
2731 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2732 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2733 | |
2734 | #define FPU_REGISTER_NAMES \ | |
2735 | {"$f0", RTYPE_FPU | 0}, \ | |
2736 | {"$f1", RTYPE_FPU | 1}, \ | |
2737 | {"$f2", RTYPE_FPU | 2}, \ | |
2738 | {"$f3", RTYPE_FPU | 3}, \ | |
2739 | {"$f4", RTYPE_FPU | 4}, \ | |
2740 | {"$f5", RTYPE_FPU | 5}, \ | |
2741 | {"$f6", RTYPE_FPU | 6}, \ | |
2742 | {"$f7", RTYPE_FPU | 7}, \ | |
2743 | {"$f8", RTYPE_FPU | 8}, \ | |
2744 | {"$f9", RTYPE_FPU | 9}, \ | |
2745 | {"$f10", RTYPE_FPU | 10}, \ | |
2746 | {"$f11", RTYPE_FPU | 11}, \ | |
2747 | {"$f12", RTYPE_FPU | 12}, \ | |
2748 | {"$f13", RTYPE_FPU | 13}, \ | |
2749 | {"$f14", RTYPE_FPU | 14}, \ | |
2750 | {"$f15", RTYPE_FPU | 15}, \ | |
2751 | {"$f16", RTYPE_FPU | 16}, \ | |
2752 | {"$f17", RTYPE_FPU | 17}, \ | |
2753 | {"$f18", RTYPE_FPU | 18}, \ | |
2754 | {"$f19", RTYPE_FPU | 19}, \ | |
2755 | {"$f20", RTYPE_FPU | 20}, \ | |
2756 | {"$f21", RTYPE_FPU | 21}, \ | |
2757 | {"$f22", RTYPE_FPU | 22}, \ | |
2758 | {"$f23", RTYPE_FPU | 23}, \ | |
2759 | {"$f24", RTYPE_FPU | 24}, \ | |
2760 | {"$f25", RTYPE_FPU | 25}, \ | |
2761 | {"$f26", RTYPE_FPU | 26}, \ | |
2762 | {"$f27", RTYPE_FPU | 27}, \ | |
2763 | {"$f28", RTYPE_FPU | 28}, \ | |
2764 | {"$f29", RTYPE_FPU | 29}, \ | |
2765 | {"$f30", RTYPE_FPU | 30}, \ | |
2766 | {"$f31", RTYPE_FPU | 31} | |
2767 | ||
2768 | #define FPU_CONDITION_CODE_NAMES \ | |
2769 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2770 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2771 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2772 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2773 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2774 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2775 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2776 | {"$fcc7", RTYPE_FCC | 7} | |
2777 | ||
2778 | #define COPROC_CONDITION_CODE_NAMES \ | |
2779 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2780 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2781 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2782 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2783 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2784 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2785 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2786 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2787 | ||
2788 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2789 | {"$a4", RTYPE_GP | 8}, \ | |
2790 | {"$a5", RTYPE_GP | 9}, \ | |
2791 | {"$a6", RTYPE_GP | 10}, \ | |
2792 | {"$a7", RTYPE_GP | 11}, \ | |
2793 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2794 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2795 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2796 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2797 | {"$t0", RTYPE_GP | 12}, \ | |
2798 | {"$t1", RTYPE_GP | 13}, \ | |
2799 | {"$t2", RTYPE_GP | 14}, \ | |
2800 | {"$t3", RTYPE_GP | 15} | |
2801 | ||
2802 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2803 | {"$t0", RTYPE_GP | 8}, \ | |
2804 | {"$t1", RTYPE_GP | 9}, \ | |
2805 | {"$t2", RTYPE_GP | 10}, \ | |
2806 | {"$t3", RTYPE_GP | 11}, \ | |
2807 | {"$t4", RTYPE_GP | 12}, \ | |
2808 | {"$t5", RTYPE_GP | 13}, \ | |
2809 | {"$t6", RTYPE_GP | 14}, \ | |
2810 | {"$t7", RTYPE_GP | 15}, \ | |
2811 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2812 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2813 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2814 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 | 2815 | |
6f2117ba | 2816 | /* Remaining symbolic register names. */ |
707bfff6 TS |
2817 | #define SYMBOLIC_REGISTER_NAMES \ |
2818 | {"$zero", RTYPE_GP | 0}, \ | |
2819 | {"$at", RTYPE_GP | 1}, \ | |
2820 | {"$AT", RTYPE_GP | 1}, \ | |
2821 | {"$v0", RTYPE_GP | 2}, \ | |
2822 | {"$v1", RTYPE_GP | 3}, \ | |
2823 | {"$a0", RTYPE_GP | 4}, \ | |
2824 | {"$a1", RTYPE_GP | 5}, \ | |
2825 | {"$a2", RTYPE_GP | 6}, \ | |
2826 | {"$a3", RTYPE_GP | 7}, \ | |
2827 | {"$s0", RTYPE_GP | 16}, \ | |
2828 | {"$s1", RTYPE_GP | 17}, \ | |
2829 | {"$s2", RTYPE_GP | 18}, \ | |
2830 | {"$s3", RTYPE_GP | 19}, \ | |
2831 | {"$s4", RTYPE_GP | 20}, \ | |
2832 | {"$s5", RTYPE_GP | 21}, \ | |
2833 | {"$s6", RTYPE_GP | 22}, \ | |
2834 | {"$s7", RTYPE_GP | 23}, \ | |
2835 | {"$t8", RTYPE_GP | 24}, \ | |
2836 | {"$t9", RTYPE_GP | 25}, \ | |
2837 | {"$k0", RTYPE_GP | 26}, \ | |
2838 | {"$kt0", RTYPE_GP | 26}, \ | |
2839 | {"$k1", RTYPE_GP | 27}, \ | |
2840 | {"$kt1", RTYPE_GP | 27}, \ | |
2841 | {"$gp", RTYPE_GP | 28}, \ | |
2842 | {"$sp", RTYPE_GP | 29}, \ | |
2843 | {"$s8", RTYPE_GP | 30}, \ | |
2844 | {"$fp", RTYPE_GP | 30}, \ | |
2845 | {"$ra", RTYPE_GP | 31} | |
2846 | ||
2847 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2848 | {"$pc", RTYPE_PC | 0} | |
2849 | ||
2850 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
6f2117ba PH |
2851 | /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \ |
2852 | /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \ | |
707bfff6 TS |
2853 | {"$v2", RTYPE_VEC | 2}, \ |
2854 | {"$v3", RTYPE_VEC | 3}, \ | |
2855 | {"$v4", RTYPE_VEC | 4}, \ | |
2856 | {"$v5", RTYPE_VEC | 5}, \ | |
2857 | {"$v6", RTYPE_VEC | 6}, \ | |
2858 | {"$v7", RTYPE_VEC | 7}, \ | |
2859 | {"$v8", RTYPE_VEC | 8}, \ | |
2860 | {"$v9", RTYPE_VEC | 9}, \ | |
2861 | {"$v10", RTYPE_VEC | 10}, \ | |
2862 | {"$v11", RTYPE_VEC | 11}, \ | |
2863 | {"$v12", RTYPE_VEC | 12}, \ | |
2864 | {"$v13", RTYPE_VEC | 13}, \ | |
2865 | {"$v14", RTYPE_VEC | 14}, \ | |
2866 | {"$v15", RTYPE_VEC | 15}, \ | |
2867 | {"$v16", RTYPE_VEC | 16}, \ | |
2868 | {"$v17", RTYPE_VEC | 17}, \ | |
2869 | {"$v18", RTYPE_VEC | 18}, \ | |
2870 | {"$v19", RTYPE_VEC | 19}, \ | |
2871 | {"$v20", RTYPE_VEC | 20}, \ | |
2872 | {"$v21", RTYPE_VEC | 21}, \ | |
2873 | {"$v22", RTYPE_VEC | 22}, \ | |
2874 | {"$v23", RTYPE_VEC | 23}, \ | |
2875 | {"$v24", RTYPE_VEC | 24}, \ | |
2876 | {"$v25", RTYPE_VEC | 25}, \ | |
2877 | {"$v26", RTYPE_VEC | 26}, \ | |
2878 | {"$v27", RTYPE_VEC | 27}, \ | |
2879 | {"$v28", RTYPE_VEC | 28}, \ | |
2880 | {"$v29", RTYPE_VEC | 29}, \ | |
2881 | {"$v30", RTYPE_VEC | 30}, \ | |
2882 | {"$v31", RTYPE_VEC | 31} | |
2883 | ||
14daeee3 RS |
2884 | #define R5900_I_NAMES \ |
2885 | {"$I", RTYPE_R5900_I | 0} | |
2886 | ||
2887 | #define R5900_Q_NAMES \ | |
2888 | {"$Q", RTYPE_R5900_Q | 0} | |
2889 | ||
2890 | #define R5900_R_NAMES \ | |
2891 | {"$R", RTYPE_R5900_R | 0} | |
2892 | ||
2893 | #define R5900_ACC_NAMES \ | |
2894 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2895 | ||
707bfff6 TS |
2896 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2897 | {"$ac0", RTYPE_ACC | 0}, \ | |
2898 | {"$ac1", RTYPE_ACC | 1}, \ | |
2899 | {"$ac2", RTYPE_ACC | 2}, \ | |
2900 | {"$ac3", RTYPE_ACC | 3} | |
2901 | ||
2902 | static const struct regname reg_names[] = { | |
2903 | GENERIC_REGISTER_NUMBERS, | |
2904 | FPU_REGISTER_NAMES, | |
2905 | FPU_CONDITION_CODE_NAMES, | |
2906 | COPROC_CONDITION_CODE_NAMES, | |
2907 | ||
2908 | /* The $txx registers depends on the abi, | |
2909 | these will be added later into the symbol table from | |
3739860c | 2910 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2911 | parsing of arguments from the command line. */ |
2912 | SYMBOLIC_REGISTER_NAMES, | |
2913 | ||
2914 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2915 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2916 | R5900_I_NAMES, |
2917 | R5900_Q_NAMES, | |
2918 | R5900_R_NAMES, | |
2919 | R5900_ACC_NAMES, | |
707bfff6 TS |
2920 | MIPS_DSP_ACCUMULATOR_NAMES, |
2921 | {0, 0} | |
2922 | }; | |
2923 | ||
2924 | static const struct regname reg_names_o32[] = { | |
2925 | O32_SYMBOLIC_REGISTER_NAMES, | |
2926 | {0, 0} | |
2927 | }; | |
2928 | ||
2929 | static const struct regname reg_names_n32n64[] = { | |
2930 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2931 | {0, 0} | |
2932 | }; | |
2933 | ||
a92713e6 RS |
2934 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2935 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2936 | of these register symbols, return the associated vector register, | |
2937 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2938 | |
a92713e6 RS |
2939 | static unsigned int |
2940 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2941 | { |
a92713e6 RS |
2942 | if ((symval & -2) == (RTYPE_GP | 2)) |
2943 | return RTYPE_VEC | (symval & 1); | |
2944 | return symval; | |
2945 | } | |
2946 | ||
14daeee3 RS |
2947 | /* Return true if string [S, E) is a valid register name, storing its |
2948 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2949 | |
2950 | static bfd_boolean | |
14daeee3 | 2951 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2952 | { |
707bfff6 | 2953 | char save_c; |
14daeee3 | 2954 | symbolS *symbol; |
707bfff6 TS |
2955 | |
2956 | /* Terminate name. */ | |
2957 | save_c = *e; | |
2958 | *e = '\0'; | |
2959 | ||
a92713e6 RS |
2960 | /* Look up the name. */ |
2961 | symbol = symbol_find (s); | |
2962 | *e = save_c; | |
2963 | ||
2964 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2965 | return FALSE; | |
2966 | ||
14daeee3 RS |
2967 | *symval_ptr = S_GET_VALUE (symbol); |
2968 | return TRUE; | |
2969 | } | |
2970 | ||
2971 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2972 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2973 | is nonnull. | |
2974 | ||
2975 | When returning true, move *SPTR past the register, store the | |
2976 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2977 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2978 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2979 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2980 | ||
2981 | static bfd_boolean | |
2982 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2983 | unsigned int *channels_ptr) | |
2984 | { | |
2985 | char *s, *e, *m; | |
2986 | const char *q; | |
2987 | unsigned int channels, symval, bit; | |
2988 | ||
2989 | /* Find end of name. */ | |
2990 | s = e = *sptr; | |
2991 | if (is_name_beginner (*e)) | |
2992 | ++e; | |
2993 | while (is_part_of_name (*e)) | |
2994 | ++e; | |
2995 | ||
2996 | channels = 0; | |
2997 | if (!mips_parse_register_1 (s, e, &symval)) | |
2998 | { | |
2999 | if (!channels_ptr) | |
3000 | return FALSE; | |
3001 | ||
3002 | /* Eat characters from the end of the string that are valid | |
3003 | channel suffixes. The preceding register must be $ACC or | |
3004 | end with a digit, so there is no ambiguity. */ | |
3005 | bit = 1; | |
3006 | m = e; | |
3007 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
3008 | if (m > s && m[-1] == *q) | |
3009 | { | |
3010 | --m; | |
3011 | channels |= bit; | |
3012 | } | |
3013 | ||
3014 | if (channels == 0 | |
3015 | || !mips_parse_register_1 (s, m, &symval) | |
3016 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
3017 | return FALSE; | |
3018 | } | |
3019 | ||
a92713e6 | 3020 | *sptr = e; |
14daeee3 RS |
3021 | *symval_ptr = symval; |
3022 | if (channels_ptr) | |
3023 | *channels_ptr = channels; | |
a92713e6 RS |
3024 | return TRUE; |
3025 | } | |
3026 | ||
3027 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
3028 | If so, then return 1, advance S to consume the specifier and store | |
3029 | the register's number in REGNOP, otherwise return 0. */ | |
3030 | ||
3031 | static int | |
3032 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
3033 | { | |
3034 | unsigned int regno; | |
3035 | ||
14daeee3 | 3036 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 3037 | { |
a92713e6 RS |
3038 | if (types & RTYPE_VEC) |
3039 | regno = mips_prefer_vec_regno (regno); | |
3040 | if (regno & types) | |
3041 | regno &= RNUM_MASK; | |
3042 | else | |
3043 | regno = ~0; | |
707bfff6 | 3044 | } |
a92713e6 | 3045 | else |
707bfff6 | 3046 | { |
a92713e6 | 3047 | if (types & RWARN) |
1661c76c | 3048 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 3049 | regno = ~0; |
707bfff6 | 3050 | } |
707bfff6 | 3051 | if (regnop) |
a92713e6 RS |
3052 | *regnop = regno; |
3053 | return regno <= RNUM_MASK; | |
707bfff6 TS |
3054 | } |
3055 | ||
14daeee3 RS |
3056 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
3057 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
3058 | ||
3059 | static char * | |
3060 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
3061 | { | |
3062 | unsigned int i; | |
3063 | ||
3064 | *channels = 0; | |
3065 | for (i = 0; i < 4; i++) | |
3066 | if (*s == "xyzw"[i]) | |
3067 | { | |
3068 | *channels |= 1 << (3 - i); | |
3069 | ++s; | |
3070 | } | |
3071 | return s; | |
3072 | } | |
3073 | ||
a92713e6 RS |
3074 | /* Token types for parsed operand lists. */ |
3075 | enum mips_operand_token_type { | |
3076 | /* A plain register, e.g. $f2. */ | |
3077 | OT_REG, | |
df58fc94 | 3078 | |
14daeee3 RS |
3079 | /* A 4-bit XYZW channel mask. */ |
3080 | OT_CHANNELS, | |
3081 | ||
56d438b1 CF |
3082 | /* A constant vector index, e.g. [1]. */ |
3083 | OT_INTEGER_INDEX, | |
3084 | ||
3085 | /* A register vector index, e.g. [$2]. */ | |
3086 | OT_REG_INDEX, | |
df58fc94 | 3087 | |
a92713e6 RS |
3088 | /* A continuous range of registers, e.g. $s0-$s4. */ |
3089 | OT_REG_RANGE, | |
3090 | ||
3091 | /* A (possibly relocated) expression. */ | |
3092 | OT_INTEGER, | |
3093 | ||
3094 | /* A floating-point value. */ | |
3095 | OT_FLOAT, | |
3096 | ||
3097 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
3098 | before OT_REGs. */ | |
3099 | OT_CHAR, | |
3100 | ||
14daeee3 RS |
3101 | /* A doubled character, either "--" or "++". */ |
3102 | OT_DOUBLE_CHAR, | |
3103 | ||
a92713e6 RS |
3104 | /* The end of the operand list. */ |
3105 | OT_END | |
3106 | }; | |
3107 | ||
3108 | /* A parsed operand token. */ | |
3109 | struct mips_operand_token | |
3110 | { | |
3111 | /* The type of token. */ | |
3112 | enum mips_operand_token_type type; | |
3113 | union | |
3114 | { | |
56d438b1 | 3115 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
3116 | unsigned int regno; |
3117 | ||
14daeee3 RS |
3118 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
3119 | unsigned int channels; | |
3120 | ||
56d438b1 CF |
3121 | /* The integer value of an OT_INTEGER_INDEX. */ |
3122 | addressT index; | |
a92713e6 RS |
3123 | |
3124 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
3125 | struct { | |
3126 | unsigned int regno1; | |
3127 | unsigned int regno2; | |
3128 | } reg_range; | |
3129 | ||
3130 | /* The value of an OT_INTEGER. The value is represented as an | |
3131 | expression and the relocation operators that were applied to | |
3132 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
3133 | relocation operators were used. */ | |
3134 | struct { | |
3135 | expressionS value; | |
3136 | bfd_reloc_code_real_type relocs[3]; | |
3137 | } integer; | |
3138 | ||
3139 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3140 | in the constant. */ | |
3141 | struct { | |
3142 | unsigned char data[8]; | |
3143 | int length; | |
3144 | } flt; | |
3145 | ||
14daeee3 | 3146 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3147 | char ch; |
3148 | } u; | |
3149 | }; | |
3150 | ||
3151 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3152 | static struct obstack mips_operand_tokens; | |
3153 | ||
3154 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3155 | ||
3156 | static void | |
3157 | mips_add_token (struct mips_operand_token *token, | |
3158 | enum mips_operand_token_type type) | |
3159 | { | |
3160 | token->type = type; | |
3161 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3162 | } | |
3163 | ||
3164 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3165 | and OT_REG tokens for them if so, and return a pointer to the first | |
3166 | unconsumed character. Return null otherwise. */ | |
3167 | ||
3168 | static char * | |
3169 | mips_parse_base_start (char *s) | |
3170 | { | |
3171 | struct mips_operand_token token; | |
14daeee3 RS |
3172 | unsigned int regno, channels; |
3173 | bfd_boolean decrement_p; | |
df58fc94 | 3174 | |
a92713e6 RS |
3175 | if (*s != '(') |
3176 | return 0; | |
3177 | ||
3178 | ++s; | |
3179 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3180 | |
3181 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3182 | is a double negative. */ | |
3183 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3184 | if (decrement_p) | |
3185 | { | |
3186 | s += 2; | |
3187 | SKIP_SPACE_TABS (s); | |
3188 | } | |
3189 | ||
3190 | /* Allow a channel specifier because that leads to better error messages | |
3191 | than treating something like "$vf0x++" as an expression. */ | |
3192 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3193 | return 0; |
3194 | ||
3195 | token.u.ch = '('; | |
3196 | mips_add_token (&token, OT_CHAR); | |
3197 | ||
14daeee3 RS |
3198 | if (decrement_p) |
3199 | { | |
3200 | token.u.ch = '-'; | |
3201 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3202 | } | |
3203 | ||
a92713e6 RS |
3204 | token.u.regno = regno; |
3205 | mips_add_token (&token, OT_REG); | |
3206 | ||
14daeee3 RS |
3207 | if (channels) |
3208 | { | |
3209 | token.u.channels = channels; | |
3210 | mips_add_token (&token, OT_CHANNELS); | |
3211 | } | |
3212 | ||
3213 | /* For consistency, only match "++" as part of base expressions too. */ | |
3214 | SKIP_SPACE_TABS (s); | |
3215 | if (s[0] == '+' && s[1] == '+') | |
3216 | { | |
3217 | s += 2; | |
3218 | token.u.ch = '+'; | |
3219 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3220 | } | |
3221 | ||
a92713e6 RS |
3222 | return s; |
3223 | } | |
3224 | ||
3225 | /* Parse one or more tokens from S. Return a pointer to the first | |
3226 | unconsumed character on success. Return null if an error was found | |
3227 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3228 | mips_parse_arguments. */ | |
3229 | ||
3230 | static char * | |
3231 | mips_parse_argument_token (char *s, char float_format) | |
3232 | { | |
6d4af3c2 AM |
3233 | char *end, *save_in; |
3234 | const char *err; | |
14daeee3 | 3235 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3236 | struct mips_operand_token token; |
3237 | ||
3238 | /* First look for "($reg", since we want to treat that as an | |
3239 | OT_CHAR and OT_REG rather than an expression. */ | |
3240 | end = mips_parse_base_start (s); | |
3241 | if (end) | |
3242 | return end; | |
3243 | ||
3244 | /* Handle other characters that end up as OT_CHARs. */ | |
3245 | if (*s == ')' || *s == ',') | |
3246 | { | |
3247 | token.u.ch = *s; | |
3248 | mips_add_token (&token, OT_CHAR); | |
3249 | ++s; | |
3250 | return s; | |
3251 | } | |
3252 | ||
3253 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3254 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3255 | { |
14daeee3 RS |
3256 | if (channels) |
3257 | { | |
3258 | /* A register and a VU0 channel suffix. */ | |
3259 | token.u.regno = regno1; | |
3260 | mips_add_token (&token, OT_REG); | |
3261 | ||
3262 | token.u.channels = channels; | |
3263 | mips_add_token (&token, OT_CHANNELS); | |
3264 | return s; | |
3265 | } | |
3266 | ||
a92713e6 RS |
3267 | SKIP_SPACE_TABS (s); |
3268 | if (*s == '-') | |
df58fc94 | 3269 | { |
a92713e6 RS |
3270 | /* A register range. */ |
3271 | ++s; | |
3272 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3273 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3274 | { |
1661c76c | 3275 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3276 | return 0; |
3277 | } | |
df58fc94 | 3278 | |
a92713e6 RS |
3279 | token.u.reg_range.regno1 = regno1; |
3280 | token.u.reg_range.regno2 = regno2; | |
3281 | mips_add_token (&token, OT_REG_RANGE); | |
3282 | return s; | |
3283 | } | |
a92713e6 | 3284 | |
56d438b1 CF |
3285 | /* Add the register itself. */ |
3286 | token.u.regno = regno1; | |
3287 | mips_add_token (&token, OT_REG); | |
3288 | ||
3289 | /* Check for a vector index. */ | |
3290 | if (*s == '[') | |
3291 | { | |
a92713e6 RS |
3292 | ++s; |
3293 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3294 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3295 | mips_add_token (&token, OT_REG_INDEX); | |
3296 | else | |
a92713e6 | 3297 | { |
56d438b1 CF |
3298 | expressionS element; |
3299 | ||
3300 | my_getExpression (&element, s); | |
3301 | if (element.X_op != O_constant) | |
3302 | { | |
3303 | set_insn_error (0, _("vector element must be constant")); | |
3304 | return 0; | |
3305 | } | |
3306 | s = expr_end; | |
3307 | token.u.index = element.X_add_number; | |
3308 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3309 | } |
a92713e6 RS |
3310 | SKIP_SPACE_TABS (s); |
3311 | if (*s != ']') | |
3312 | { | |
1661c76c | 3313 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3314 | return 0; |
3315 | } | |
3316 | ++s; | |
df58fc94 | 3317 | } |
a92713e6 | 3318 | return s; |
df58fc94 RS |
3319 | } |
3320 | ||
a92713e6 RS |
3321 | if (float_format) |
3322 | { | |
3323 | /* First try to treat expressions as floats. */ | |
3324 | save_in = input_line_pointer; | |
3325 | input_line_pointer = s; | |
3326 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3327 | &token.u.flt.length); | |
3328 | end = input_line_pointer; | |
3329 | input_line_pointer = save_in; | |
3330 | if (err && *err) | |
3331 | { | |
e3de51ce | 3332 | set_insn_error (0, err); |
a92713e6 RS |
3333 | return 0; |
3334 | } | |
3335 | if (s != end) | |
3336 | { | |
3337 | mips_add_token (&token, OT_FLOAT); | |
3338 | return end; | |
3339 | } | |
3340 | } | |
3341 | ||
3342 | /* Treat everything else as an integer expression. */ | |
3343 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3344 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3345 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3346 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3347 | s = expr_end; | |
3348 | mips_add_token (&token, OT_INTEGER); | |
3349 | return s; | |
3350 | } | |
3351 | ||
3352 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3353 | if expressions should be treated as 32-bit floating-point constants, | |
3354 | 'd' if they should be treated as 64-bit floating-point constants, | |
3355 | or 0 if they should be treated as integer expressions (the usual case). | |
3356 | ||
3357 | Return a list of tokens on success, otherwise return 0. The caller | |
3358 | must obstack_free the list after use. */ | |
3359 | ||
3360 | static struct mips_operand_token * | |
3361 | mips_parse_arguments (char *s, char float_format) | |
3362 | { | |
3363 | struct mips_operand_token token; | |
3364 | ||
3365 | SKIP_SPACE_TABS (s); | |
3366 | while (*s) | |
3367 | { | |
3368 | s = mips_parse_argument_token (s, float_format); | |
3369 | if (!s) | |
3370 | { | |
3371 | obstack_free (&mips_operand_tokens, | |
3372 | obstack_finish (&mips_operand_tokens)); | |
3373 | return 0; | |
3374 | } | |
3375 | SKIP_SPACE_TABS (s); | |
3376 | } | |
3377 | mips_add_token (&token, OT_END); | |
3378 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3379 | } |
3380 | ||
d301a56b RS |
3381 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3382 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3383 | |
3384 | static bfd_boolean | |
f79e2745 | 3385 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3386 | { |
3387 | int isa = mips_opts.isa; | |
846ef2d0 | 3388 | int ase = mips_opts.ase; |
037b32b9 | 3389 | int fp_s, fp_d; |
c6278170 | 3390 | unsigned int i; |
037b32b9 | 3391 | |
be0fcbee | 3392 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3393 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3394 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3395 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3396 | |
d301a56b | 3397 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3398 | return FALSE; |
3399 | ||
3400 | /* Check whether the instruction or macro requires single-precision or | |
3401 | double-precision floating-point support. Note that this information is | |
3402 | stored differently in the opcode table for insns and macros. */ | |
3403 | if (mo->pinfo == INSN_MACRO) | |
3404 | { | |
3405 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3406 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3407 | } | |
3408 | else | |
3409 | { | |
3410 | fp_s = mo->pinfo & FP_S; | |
3411 | fp_d = mo->pinfo & FP_D; | |
3412 | } | |
3413 | ||
3414 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3415 | return FALSE; | |
3416 | ||
3417 | if (fp_s && mips_opts.soft_float) | |
3418 | return FALSE; | |
3419 | ||
3420 | return TRUE; | |
3421 | } | |
3422 | ||
3423 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3424 | selected ISA and architecture. */ | |
3425 | ||
3426 | static bfd_boolean | |
3427 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3428 | { | |
25499ac7 MR |
3429 | int isa = mips_opts.isa; |
3430 | int ase = mips_opts.ase; | |
3431 | unsigned int i; | |
3432 | ||
3433 | if (ISA_HAS_64BIT_REGS (isa)) | |
3434 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3435 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3436 | ase |= mips_ases[i].flags64; | |
3437 | ||
3438 | return opcode_is_member (mo, isa, ase, mips_opts.arch); | |
037b32b9 AN |
3439 | } |
3440 | ||
df58fc94 | 3441 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3442 | explicitly requested. Always TRUE in the standard MIPS mode. |
3443 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3444 | |
3445 | static bfd_boolean | |
3446 | is_size_valid (const struct mips_opcode *mo) | |
3447 | { | |
3448 | if (!mips_opts.micromips) | |
3449 | return TRUE; | |
3450 | ||
833794fc MR |
3451 | if (mips_opts.insn32) |
3452 | { | |
3453 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3454 | return FALSE; | |
3455 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3456 | return FALSE; | |
3457 | } | |
df58fc94 RS |
3458 | if (!forced_insn_length) |
3459 | return TRUE; | |
3460 | if (mo->pinfo == INSN_MACRO) | |
3461 | return FALSE; | |
3462 | return forced_insn_length == micromips_insn_length (mo); | |
3463 | } | |
3464 | ||
7fd53920 MR |
3465 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3466 | explicitly requested. */ | |
3467 | ||
3468 | static bfd_boolean | |
3469 | is_size_valid_16 (const struct mips_opcode *mo) | |
3470 | { | |
3471 | if (!forced_insn_length) | |
3472 | return TRUE; | |
3473 | if (mo->pinfo == INSN_MACRO) | |
3474 | return FALSE; | |
3475 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3476 | return FALSE; | |
0674ee5d MR |
3477 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3478 | return FALSE; | |
7fd53920 MR |
3479 | return TRUE; |
3480 | } | |
3481 | ||
df58fc94 | 3482 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3483 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3484 | ||
3485 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3486 | a macro expansion fails because it relies on a preceding 32-bit real | |
3487 | instruction to have matched and does not handle the operands correctly. | |
3488 | The only macros that may expand to 16-bit instructions are JAL that | |
3489 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3490 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3491 | a NOP. In all these cases the macros precede any corresponding real | |
3492 | instruction definitions in the opcode table, so they will match in the | |
3493 | second pass where the size of the delay slot is ignored and therefore | |
3494 | produce correct code. */ | |
df58fc94 RS |
3495 | |
3496 | static bfd_boolean | |
3497 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3498 | { | |
3499 | if (!mips_opts.micromips) | |
3500 | return TRUE; | |
3501 | ||
3502 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3503 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3504 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3505 | && micromips_insn_length (mo) != 4) | |
3506 | return FALSE; | |
3507 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3508 | && micromips_insn_length (mo) != 2) | |
3509 | return FALSE; | |
3510 | ||
3511 | return TRUE; | |
3512 | } | |
3513 | ||
fc76e730 RS |
3514 | /* For consistency checking, verify that all bits of OPCODE are specified |
3515 | either by the match/mask part of the instruction definition, or by the | |
3516 | operand list. Also build up a list of operands in OPERANDS. | |
3517 | ||
3518 | INSN_BITS says which bits of the instruction are significant. | |
3519 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3520 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3521 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3522 | |
3523 | static int | |
3524 | validate_mips_insn (const struct mips_opcode *opcode, | |
3525 | unsigned long insn_bits, | |
fc76e730 RS |
3526 | const struct mips_operand *(*decode_operand) (const char *), |
3527 | struct mips_operand_array *operands) | |
ab902481 RS |
3528 | { |
3529 | const char *s; | |
fc76e730 | 3530 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3531 | const struct mips_operand *operand; |
3532 | ||
fc76e730 RS |
3533 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3534 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3535 | { |
3536 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3537 | opcode->name, opcode->args); | |
3538 | return 0; | |
3539 | } | |
3540 | used_bits = 0; | |
fc76e730 | 3541 | opno = 0; |
14daeee3 RS |
3542 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3543 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3544 | for (s = opcode->args; *s; ++s) |
3545 | switch (*s) | |
3546 | { | |
3547 | case ',': | |
3548 | case '(': | |
3549 | case ')': | |
3550 | break; | |
3551 | ||
14daeee3 RS |
3552 | case '#': |
3553 | s++; | |
3554 | break; | |
3555 | ||
ab902481 | 3556 | default: |
fc76e730 | 3557 | if (!decode_operand) |
7fd53920 | 3558 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3559 | else |
3560 | operand = decode_operand (s); | |
3561 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3562 | { |
3563 | as_bad (_("internal: unknown operand type: %s %s"), | |
3564 | opcode->name, opcode->args); | |
3565 | return 0; | |
3566 | } | |
fc76e730 RS |
3567 | gas_assert (opno < MAX_OPERANDS); |
3568 | operands->operand[opno] = operand; | |
25499ac7 MR |
3569 | if (!decode_operand && operand |
3570 | && operand->type == OP_INT && operand->lsb == 0 | |
3571 | && mips_opcode_32bit_p (opcode)) | |
3572 | used_bits |= mips16_immed_extend (-1, operand->size); | |
3573 | else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) | |
fc76e730 | 3574 | { |
14daeee3 | 3575 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3576 | if (operand->type == OP_MDMX_IMM_REG) |
3577 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3578 | has separate entries for each format. */ | |
3579 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3580 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3581 | used_bits &= ~(mask & 0x700); | |
38bf472a MR |
3582 | /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous |
3583 | operand field that cannot be fully described with LSB/SIZE. */ | |
3584 | if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6) | |
3585 | used_bits &= ~0x6000; | |
fc76e730 | 3586 | } |
ab902481 | 3587 | /* Skip prefix characters. */ |
7361da2c | 3588 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3589 | ++s; |
fc76e730 | 3590 | opno += 1; |
ab902481 RS |
3591 | break; |
3592 | } | |
fc76e730 | 3593 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3594 | if (doubled) |
3595 | { | |
3596 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3597 | " %s %s"), doubled, opcode->name, opcode->args); | |
3598 | return 0; | |
3599 | } | |
fc76e730 | 3600 | used_bits |= mask; |
ab902481 | 3601 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3602 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3603 | { |
3604 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3605 | undefined, opcode->name, opcode->args); | |
3606 | return 0; | |
3607 | } | |
3608 | used_bits &= ~insn_bits; | |
3609 | if (used_bits) | |
3610 | { | |
3611 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3612 | used_bits, opcode->name, opcode->args); | |
3613 | return 0; | |
3614 | } | |
3615 | return 1; | |
3616 | } | |
3617 | ||
fc76e730 RS |
3618 | /* The MIPS16 version of validate_mips_insn. */ |
3619 | ||
3620 | static int | |
3621 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3622 | struct mips_operand_array *operands) | |
3623 | { | |
7fd53920 | 3624 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3625 | |
7fd53920 | 3626 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3627 | } |
3628 | ||
ab902481 RS |
3629 | /* The microMIPS version of validate_mips_insn. */ |
3630 | ||
3631 | static int | |
fc76e730 RS |
3632 | validate_micromips_insn (const struct mips_opcode *opc, |
3633 | struct mips_operand_array *operands) | |
ab902481 RS |
3634 | { |
3635 | unsigned long insn_bits; | |
3636 | unsigned long major; | |
3637 | unsigned int length; | |
3638 | ||
fc76e730 RS |
3639 | if (opc->pinfo == INSN_MACRO) |
3640 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3641 | operands); | |
3642 | ||
ab902481 RS |
3643 | length = micromips_insn_length (opc); |
3644 | if (length != 2 && length != 4) | |
3645 | { | |
1661c76c | 3646 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3647 | "%s %s"), length, opc->name, opc->args); |
3648 | return 0; | |
3649 | } | |
3650 | major = opc->match >> (10 + 8 * (length - 2)); | |
3651 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3652 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3653 | { | |
1661c76c | 3654 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3655 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3656 | return 0; | |
3657 | } | |
3658 | ||
3659 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3660 | insn_bits = 1 << 4 * length; | |
3661 | insn_bits <<= 4 * length; | |
3662 | insn_bits -= 1; | |
fc76e730 RS |
3663 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3664 | operands); | |
ab902481 RS |
3665 | } |
3666 | ||
707bfff6 TS |
3667 | /* This function is called once, at assembler startup time. It should set up |
3668 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3669 | |
252b5132 | 3670 | void |
17a2f251 | 3671 | md_begin (void) |
252b5132 | 3672 | { |
3994f87e | 3673 | const char *retval = NULL; |
156c2f8b | 3674 | int i = 0; |
252b5132 | 3675 | int broken = 0; |
1f25f5d3 | 3676 | |
0a44bf69 RS |
3677 | if (mips_pic != NO_PIC) |
3678 | { | |
3679 | if (g_switch_seen && g_switch_value != 0) | |
3680 | as_bad (_("-G may not be used in position-independent code")); | |
3681 | g_switch_value = 0; | |
3682 | } | |
00acd688 CM |
3683 | else if (mips_abicalls) |
3684 | { | |
3685 | if (g_switch_seen && g_switch_value != 0) | |
3686 | as_bad (_("-G may not be used with abicalls")); | |
3687 | g_switch_value = 0; | |
3688 | } | |
0a44bf69 | 3689 | |
0b35dfee | 3690 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3691 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3692 | |
252b5132 RH |
3693 | op_hash = hash_new (); |
3694 | ||
fc76e730 | 3695 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3696 | for (i = 0; i < NUMOPCODES;) |
3697 | { | |
3698 | const char *name = mips_opcodes[i].name; | |
3699 | ||
17a2f251 | 3700 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3701 | if (retval != NULL) |
3702 | { | |
3703 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3704 | mips_opcodes[i].name, retval); | |
3705 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3706 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3707 | } |
3708 | do | |
3709 | { | |
fc76e730 RS |
3710 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3711 | decode_mips_operand, &mips_operands[i])) | |
3712 | broken = 1; | |
6f2117ba | 3713 | |
fc76e730 | 3714 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
252b5132 | 3715 | { |
fc76e730 RS |
3716 | create_insn (&nop_insn, mips_opcodes + i); |
3717 | if (mips_fix_loongson2f_nop) | |
3718 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3719 | nop_insn.fixed_p = 1; | |
252b5132 | 3720 | } |
6f2117ba PH |
3721 | |
3722 | if (sync_insn.insn_mo == NULL && strcmp (name, "sync") == 0) | |
3723 | create_insn (&sync_insn, mips_opcodes + i); | |
3724 | ||
252b5132 RH |
3725 | ++i; |
3726 | } | |
3727 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3728 | } | |
3729 | ||
3730 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3731 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3732 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3733 | |
3734 | i = 0; | |
3735 | while (i < bfd_mips16_num_opcodes) | |
3736 | { | |
3737 | const char *name = mips16_opcodes[i].name; | |
3738 | ||
17a2f251 | 3739 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3740 | if (retval != NULL) |
3741 | as_fatal (_("internal: can't hash `%s': %s"), | |
3742 | mips16_opcodes[i].name, retval); | |
3743 | do | |
3744 | { | |
fc76e730 RS |
3745 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3746 | broken = 1; | |
1e915849 RS |
3747 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3748 | { | |
3749 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3750 | mips16_nop_insn.fixed_p = 1; | |
3751 | } | |
252b5132 RH |
3752 | ++i; |
3753 | } | |
3754 | while (i < bfd_mips16_num_opcodes | |
3755 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3756 | } | |
3757 | ||
df58fc94 | 3758 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3759 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3760 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3761 | |
3762 | i = 0; | |
3763 | while (i < bfd_micromips_num_opcodes) | |
3764 | { | |
3765 | const char *name = micromips_opcodes[i].name; | |
3766 | ||
3767 | retval = hash_insert (micromips_op_hash, name, | |
3768 | (void *) µmips_opcodes[i]); | |
3769 | if (retval != NULL) | |
3770 | as_fatal (_("internal: can't hash `%s': %s"), | |
3771 | micromips_opcodes[i].name, retval); | |
3772 | do | |
fc76e730 RS |
3773 | { |
3774 | struct mips_cl_insn *micromips_nop_insn; | |
3775 | ||
3776 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3777 | µmips_operands[i])) | |
3778 | broken = 1; | |
3779 | ||
3780 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3781 | { | |
3782 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3783 | micromips_nop_insn = µmips_nop16_insn; | |
3784 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3785 | micromips_nop_insn = µmips_nop32_insn; | |
3786 | else | |
3787 | continue; | |
3788 | ||
3789 | if (micromips_nop_insn->insn_mo == NULL | |
3790 | && strcmp (name, "nop") == 0) | |
3791 | { | |
3792 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3793 | micromips_nop_insn->fixed_p = 1; | |
3794 | } | |
3795 | } | |
3796 | } | |
df58fc94 RS |
3797 | while (++i < bfd_micromips_num_opcodes |
3798 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3799 | } | |
3800 | ||
252b5132 | 3801 | if (broken) |
1661c76c | 3802 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3803 | |
3804 | /* We add all the general register names to the symbol table. This | |
3805 | helps us detect invalid uses of them. */ | |
3739860c | 3806 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3807 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3808 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3809 | &zero_address_frag)); |
3810 | if (HAVE_NEWABI) | |
3739860c | 3811 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3812 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3813 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3814 | &zero_address_frag)); |
707bfff6 | 3815 | else |
3739860c | 3816 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3817 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3818 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3819 | &zero_address_frag)); |
6047c971 | 3820 | |
14daeee3 RS |
3821 | for (i = 0; i < 32; i++) |
3822 | { | |
92fce9bd | 3823 | char regname[6]; |
14daeee3 RS |
3824 | |
3825 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3826 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3827 | symbol_table_insert (symbol_new (regname, reg_section, |
3828 | RTYPE_VF | i, &zero_address_frag)); | |
3829 | ||
3830 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3831 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3832 | symbol_table_insert (symbol_new (regname, reg_section, |
3833 | RTYPE_VI | i, &zero_address_frag)); | |
3834 | ||
56d438b1 | 3835 | /* MSA register. */ |
92fce9bd | 3836 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3837 | symbol_table_insert (symbol_new (regname, reg_section, |
3838 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3839 | } |
3840 | ||
a92713e6 RS |
3841 | obstack_init (&mips_operand_tokens); |
3842 | ||
7d10b47d | 3843 | mips_no_prev_insn (); |
252b5132 RH |
3844 | |
3845 | mips_gprmask = 0; | |
3846 | mips_cprmask[0] = 0; | |
3847 | mips_cprmask[1] = 0; | |
3848 | mips_cprmask[2] = 0; | |
3849 | mips_cprmask[3] = 0; | |
3850 | ||
3851 | /* set the default alignment for the text section (2**2) */ | |
3852 | record_alignment (text_section, 2); | |
3853 | ||
4d0d148d | 3854 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3855 | |
f3ded42a RS |
3856 | /* On a native system other than VxWorks, sections must be aligned |
3857 | to 16 byte boundaries. When configured for an embedded ELF | |
3858 | target, we don't bother. */ | |
3859 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3860 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3861 | { |
f3ded42a RS |
3862 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3863 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3864 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3865 | } | |
252b5132 | 3866 | |
f3ded42a RS |
3867 | /* Create a .reginfo section for register masks and a .mdebug |
3868 | section for debugging information. */ | |
3869 | { | |
3870 | segT seg; | |
3871 | subsegT subseg; | |
3872 | flagword flags; | |
3873 | segT sec; | |
3874 | ||
3875 | seg = now_seg; | |
3876 | subseg = now_subseg; | |
3877 | ||
3878 | /* The ABI says this section should be loaded so that the | |
3879 | running program can access it. However, we don't load it | |
6f2117ba | 3880 | if we are configured for an embedded target. */ |
f3ded42a RS |
3881 | flags = SEC_READONLY | SEC_DATA; |
3882 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3883 | flags |= SEC_ALLOC | SEC_LOAD; | |
3884 | ||
3885 | if (mips_abi != N64_ABI) | |
252b5132 | 3886 | { |
f3ded42a | 3887 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3888 | |
f3ded42a RS |
3889 | bfd_set_section_flags (stdoutput, sec, flags); |
3890 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3891 | |
f3ded42a RS |
3892 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3893 | } | |
3894 | else | |
3895 | { | |
3896 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3897 | .reginfo section. */ | |
3898 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3899 | bfd_set_section_flags (stdoutput, sec, flags); | |
3900 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3901 | |
f3ded42a RS |
3902 | /* Set up the option header. */ |
3903 | { | |
3904 | Elf_Internal_Options opthdr; | |
3905 | char *f; | |
3906 | ||
3907 | opthdr.kind = ODK_REGINFO; | |
3908 | opthdr.size = (sizeof (Elf_External_Options) | |
3909 | + sizeof (Elf64_External_RegInfo)); | |
3910 | opthdr.section = 0; | |
3911 | opthdr.info = 0; | |
3912 | f = frag_more (sizeof (Elf_External_Options)); | |
3913 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3914 | (Elf_External_Options *) f); | |
3915 | ||
3916 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3917 | } | |
3918 | } | |
252b5132 | 3919 | |
351cdf24 MF |
3920 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
3921 | bfd_set_section_flags (stdoutput, sec, | |
3922 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); | |
3923 | bfd_set_section_alignment (stdoutput, sec, 3); | |
3924 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); | |
3925 | ||
f3ded42a RS |
3926 | if (ECOFF_DEBUGGING) |
3927 | { | |
3928 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3929 | (void) bfd_set_section_flags (stdoutput, sec, | |
3930 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3931 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3932 | } |
f3ded42a RS |
3933 | else if (mips_flag_pdr) |
3934 | { | |
3935 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3936 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3937 | SEC_READONLY | SEC_RELOC | |
3938 | | SEC_DEBUGGING); | |
3939 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3940 | } | |
3941 | ||
3942 | subseg_set (seg, subseg); | |
3943 | } | |
252b5132 | 3944 | |
71400594 RS |
3945 | if (mips_fix_vr4120) |
3946 | init_vr4120_conflicts (); | |
252b5132 RH |
3947 | } |
3948 | ||
351cdf24 MF |
3949 | static inline void |
3950 | fpabi_incompatible_with (int fpabi, const char *what) | |
3951 | { | |
3952 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3953 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3954 | } | |
3955 | ||
3956 | static inline void | |
3957 | fpabi_requires (int fpabi, const char *what) | |
3958 | { | |
3959 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3960 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3961 | } | |
3962 | ||
3963 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3964 | static void | |
3965 | check_fpabi (int fpabi) | |
3966 | { | |
351cdf24 MF |
3967 | switch (fpabi) |
3968 | { | |
3969 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3970 | if (file_mips_opts.soft_float) |
3971 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3972 | else if (file_mips_opts.single_float) | |
3973 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3974 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3975 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3976 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3977 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3978 | break; |
3979 | ||
3980 | case Val_GNU_MIPS_ABI_FP_XX: | |
3981 | if (mips_abi != O32_ABI) | |
3982 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3983 | else if (file_mips_opts.soft_float) |
3984 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3985 | else if (file_mips_opts.single_float) | |
3986 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3987 | else if (file_mips_opts.fp != 0) |
3988 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3989 | break; |
3990 | ||
3991 | case Val_GNU_MIPS_ABI_FP_64A: | |
3992 | case Val_GNU_MIPS_ABI_FP_64: | |
3993 | if (mips_abi != O32_ABI) | |
3994 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3995 | else if (file_mips_opts.soft_float) |
3996 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3997 | else if (file_mips_opts.single_float) | |
3998 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3999 | else if (file_mips_opts.fp != 64) |
4000 | fpabi_requires (fpabi, "fp=64"); | |
4001 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
4002 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
4003 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
4004 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
4005 | break; |
4006 | ||
4007 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
4008 | if (file_mips_opts.soft_float) | |
4009 | fpabi_incompatible_with (fpabi, "softfloat"); | |
4010 | else if (!file_mips_opts.single_float) | |
4011 | fpabi_requires (fpabi, "singlefloat"); | |
4012 | break; | |
4013 | ||
4014 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
4015 | if (!file_mips_opts.soft_float) | |
4016 | fpabi_requires (fpabi, "softfloat"); | |
4017 | break; | |
4018 | ||
4019 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
4020 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
4021 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
4022 | break; | |
4023 | ||
3350cc01 CM |
4024 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
4025 | /* Silently ignore compatibility value. */ | |
4026 | break; | |
4027 | ||
351cdf24 MF |
4028 | default: |
4029 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
4030 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
4031 | break; | |
4032 | } | |
351cdf24 MF |
4033 | } |
4034 | ||
919731af | 4035 | /* Perform consistency checks on the current options. */ |
4036 | ||
4037 | static void | |
4038 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
4039 | { | |
4040 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
4041 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
4042 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
4043 | else if (abi_checks | |
4044 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4045 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
4046 | else if (abi_checks | |
4047 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
4048 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
4049 | ||
4050 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
4051 | switch (opts->fp) | |
4052 | { | |
351cdf24 MF |
4053 | case 0: |
4054 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
4055 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
4056 | else if (opts->single_float == 1) | |
4057 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
4058 | break; | |
919731af | 4059 | case 64: |
4060 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
4061 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
4062 | else if (abi_checks | |
4063 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
4064 | && !ISA_HAS_MXHC1 (opts->isa)) | |
4065 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
4066 | break; | |
4067 | case 32: | |
4068 | if (abi_checks | |
4069 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4070 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 4071 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 4072 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 4073 | break; |
4074 | default: | |
4075 | as_bad (_("Unknown size of floating point registers")); | |
4076 | break; | |
4077 | } | |
4078 | ||
351cdf24 MF |
4079 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
4080 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
4081 | ||
919731af | 4082 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 4083 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 4084 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
4085 | && (opts->micromips == 1 |
4086 | || opts->mips16 == 1)) | |
1357373c | 4087 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 4088 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 4089 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
4090 | |
4091 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
4092 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
4093 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 4094 | } |
4095 | ||
4096 | /* Perform consistency checks on the module level options exactly once. | |
4097 | This is a deferred check that happens: | |
4098 | at the first .set directive | |
4099 | or, at the first pseudo op that generates code (inc .dc.a) | |
4100 | or, at the first instruction | |
4101 | or, at the end. */ | |
4102 | ||
4103 | static void | |
4104 | file_mips_check_options (void) | |
4105 | { | |
919731af | 4106 | if (file_mips_opts_checked) |
4107 | return; | |
4108 | ||
4109 | /* The following code determines the register size. | |
4110 | Similar code was added to GCC 3.3 (see override_options() in | |
4111 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
4112 | as much as possible. */ | |
4113 | ||
4114 | if (file_mips_opts.gp < 0) | |
4115 | { | |
4116 | /* Infer the integer register size from the ABI and processor. | |
4117 | Restrict ourselves to 32-bit registers if that's all the | |
4118 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
4119 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
4120 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
4121 | ? 32 : 64; | |
4122 | } | |
4123 | ||
4124 | if (file_mips_opts.fp < 0) | |
4125 | { | |
4126 | /* No user specified float register size. | |
4127 | ??? GAS treats single-float processors as though they had 64-bit | |
4128 | float registers (although it complains when double-precision | |
4129 | instructions are used). As things stand, saying they have 32-bit | |
4130 | registers would lead to spurious "register must be even" messages. | |
4131 | So here we assume float registers are never smaller than the | |
4132 | integer ones. */ | |
4133 | if (file_mips_opts.gp == 64) | |
4134 | /* 64-bit integer registers implies 64-bit float registers. */ | |
4135 | file_mips_opts.fp = 64; | |
4136 | else if ((file_mips_opts.ase & FP64_ASES) | |
4137 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
4138 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
4139 | file_mips_opts.fp = 64; | |
7361da2c AB |
4140 | else if (ISA_IS_R6 (mips_opts.isa)) |
4141 | /* R6 implies 64-bit float registers. */ | |
4142 | file_mips_opts.fp = 64; | |
919731af | 4143 | else |
4144 | /* 32-bit float registers. */ | |
4145 | file_mips_opts.fp = 32; | |
4146 | } | |
4147 | ||
351cdf24 MF |
4148 | /* Disable operations on odd-numbered floating-point registers by default |
4149 | when using the FPXX ABI. */ | |
4150 | if (file_mips_opts.oddspreg < 0) | |
4151 | { | |
4152 | if (file_mips_opts.fp == 0) | |
4153 | file_mips_opts.oddspreg = 0; | |
4154 | else | |
4155 | file_mips_opts.oddspreg = 1; | |
4156 | } | |
4157 | ||
919731af | 4158 | /* End of GCC-shared inference code. */ |
4159 | ||
4160 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4161 | 32-bit wide registers. Note that EABI does not use it. */ | |
4162 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4163 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4164 | || mips_abi == O32_ABI)) | |
4165 | mips_32bitmode = 1; | |
4166 | ||
4167 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4168 | as_bad (_("trap exception not supported at ISA 1")); | |
4169 | ||
4170 | /* If the selected architecture includes support for ASEs, enable | |
4171 | generation of code for them. */ | |
4172 | if (file_mips_opts.mips16 == -1) | |
4173 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4174 | if (file_mips_opts.micromips == -1) | |
4175 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4176 | ? 1 : 0; | |
4177 | ||
7361da2c AB |
4178 | if (mips_nan2008 == -1) |
4179 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4180 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4181 | as_fatal (_("`%s' does not support legacy NaN"), | |
4182 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4183 | ||
919731af | 4184 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4185 | being selected implicitly. */ | |
4186 | if (file_mips_opts.fp != 64) | |
4187 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4188 | ||
4189 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4190 | use the default setting for the CPU. */ | |
3315614d | 4191 | file_mips_opts.ase |= (file_mips_opts.init_ase & ~file_ase_explicit); |
919731af | 4192 | |
4193 | /* Set up the current options. These may change throughout assembly. */ | |
4194 | mips_opts = file_mips_opts; | |
4195 | ||
4196 | mips_check_isa_supports_ases (); | |
4197 | mips_check_options (&file_mips_opts, TRUE); | |
4198 | file_mips_opts_checked = TRUE; | |
4199 | ||
4200 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4201 | as_warn (_("could not set architecture and machine")); | |
4202 | } | |
4203 | ||
252b5132 | 4204 | void |
17a2f251 | 4205 | md_assemble (char *str) |
252b5132 RH |
4206 | { |
4207 | struct mips_cl_insn insn; | |
f6688943 TS |
4208 | bfd_reloc_code_real_type unused_reloc[3] |
4209 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4210 | |
919731af | 4211 | file_mips_check_options (); |
4212 | ||
252b5132 | 4213 | imm_expr.X_op = O_absent; |
252b5132 | 4214 | offset_expr.X_op = O_absent; |
f6688943 TS |
4215 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4216 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4217 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4218 | |
e1b47bd5 RS |
4219 | mips_mark_labels (); |
4220 | mips_assembling_insn = TRUE; | |
e3de51ce | 4221 | clear_insn_error (); |
e1b47bd5 | 4222 | |
252b5132 RH |
4223 | if (mips_opts.mips16) |
4224 | mips16_ip (str, &insn); | |
4225 | else | |
4226 | { | |
4227 | mips_ip (str, &insn); | |
beae10d5 KH |
4228 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4229 | str, insn.insn_opcode)); | |
252b5132 RH |
4230 | } |
4231 | ||
e3de51ce RS |
4232 | if (insn_error.msg) |
4233 | report_insn_error (str); | |
e1b47bd5 | 4234 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4235 | { |
584892a6 | 4236 | macro_start (); |
252b5132 RH |
4237 | if (mips_opts.mips16) |
4238 | mips16_macro (&insn); | |
4239 | else | |
833794fc | 4240 | macro (&insn, str); |
584892a6 | 4241 | macro_end (); |
252b5132 RH |
4242 | } |
4243 | else | |
4244 | { | |
77bd4346 | 4245 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4246 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4247 | else |
df58fc94 | 4248 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4249 | } |
e1b47bd5 RS |
4250 | |
4251 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4252 | } |
4253 | ||
738e5348 RS |
4254 | /* Convenience functions for abstracting away the differences between |
4255 | MIPS16 and non-MIPS16 relocations. */ | |
4256 | ||
4257 | static inline bfd_boolean | |
4258 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4259 | { | |
4260 | switch (reloc) | |
4261 | { | |
4262 | case BFD_RELOC_MIPS16_JMP: | |
4263 | case BFD_RELOC_MIPS16_GPREL: | |
4264 | case BFD_RELOC_MIPS16_GOT16: | |
4265 | case BFD_RELOC_MIPS16_CALL16: | |
4266 | case BFD_RELOC_MIPS16_HI16_S: | |
4267 | case BFD_RELOC_MIPS16_HI16: | |
4268 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4269 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4270 | return TRUE; |
4271 | ||
4272 | default: | |
4273 | return FALSE; | |
4274 | } | |
4275 | } | |
4276 | ||
df58fc94 RS |
4277 | static inline bfd_boolean |
4278 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4279 | { | |
4280 | switch (reloc) | |
4281 | { | |
4282 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4283 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4284 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4285 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4286 | case BFD_RELOC_MICROMIPS_JMP: | |
4287 | case BFD_RELOC_MICROMIPS_HI16: | |
4288 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4289 | case BFD_RELOC_MICROMIPS_LO16: | |
4290 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4291 | case BFD_RELOC_MICROMIPS_GOT16: | |
4292 | case BFD_RELOC_MICROMIPS_CALL16: | |
4293 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4294 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4295 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4296 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4297 | case BFD_RELOC_MICROMIPS_SUB: | |
4298 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4299 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4300 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4301 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4302 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4303 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4304 | case BFD_RELOC_MICROMIPS_JALR: | |
4305 | return TRUE; | |
4306 | ||
4307 | default: | |
4308 | return FALSE; | |
4309 | } | |
4310 | } | |
4311 | ||
2309ddf2 MR |
4312 | static inline bfd_boolean |
4313 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4314 | { | |
4315 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4316 | } | |
4317 | ||
0e9c5a5c MR |
4318 | static inline bfd_boolean |
4319 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4320 | { | |
4321 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4322 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4323 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4324 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4325 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4326 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4327 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4328 | } | |
4329 | ||
738e5348 RS |
4330 | static inline bfd_boolean |
4331 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4332 | { | |
2309ddf2 | 4333 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4334 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4335 | } |
4336 | ||
4337 | static inline bfd_boolean | |
4338 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4339 | { | |
2309ddf2 | 4340 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4341 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4342 | } |
4343 | ||
4344 | static inline bfd_boolean | |
4345 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4346 | { | |
2309ddf2 | 4347 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4348 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4349 | } | |
4350 | ||
df58fc94 RS |
4351 | static inline bfd_boolean |
4352 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4353 | { | |
2309ddf2 | 4354 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4355 | } |
4356 | ||
f2ae14a1 RS |
4357 | static inline bfd_boolean |
4358 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4359 | { | |
4360 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4361 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4362 | } | |
4363 | ||
2de39019 CM |
4364 | /* Return true if RELOC is a PC-relative relocation that does not have |
4365 | full address range. */ | |
4366 | ||
4367 | static inline bfd_boolean | |
4368 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4369 | { | |
4370 | switch (reloc) | |
4371 | { | |
4372 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4373 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4374 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4375 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4376 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4377 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4378 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4379 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4380 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4381 | return TRUE; |
4382 | ||
b47468a6 | 4383 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4384 | case BFD_RELOC_HI16_S_PCREL: |
4385 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4386 | return HAVE_64BIT_ADDRESSES; |
4387 | ||
2de39019 CM |
4388 | default: |
4389 | return FALSE; | |
4390 | } | |
4391 | } | |
b47468a6 | 4392 | |
5919d012 | 4393 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4394 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4395 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4396 | |
4397 | static inline bfd_boolean | |
17a2f251 | 4398 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4399 | { |
3b91255e | 4400 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4401 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4402 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4403 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4404 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4405 | } | |
4406 | ||
4407 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4408 | reloc_needs_lo_p. */ | |
4409 | ||
4410 | static inline bfd_reloc_code_real_type | |
4411 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4412 | { | |
df58fc94 RS |
4413 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4414 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4415 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4416 | } |
4417 | ||
4418 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4419 | relocation. */ | |
4420 | ||
4421 | static inline bfd_boolean | |
17a2f251 | 4422 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4423 | { |
4424 | return (fixp->fx_next != NULL | |
738e5348 | 4425 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4426 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4427 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4428 | } | |
4429 | ||
462427c4 RS |
4430 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4431 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4432 | |
4433 | static void | |
462427c4 | 4434 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4435 | { |
4436 | struct insn_label_list *l; | |
4437 | valueT val; | |
4438 | ||
462427c4 | 4439 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4440 | { |
9c2799c2 | 4441 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4442 | symbol_set_frag (l->label, frag_now); |
4443 | val = (valueT) frag_now_fix (); | |
df58fc94 | 4444 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 4445 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
4446 | ++val; |
4447 | S_SET_VALUE (l->label, val); | |
4448 | } | |
4449 | } | |
4450 | ||
462427c4 RS |
4451 | /* Move all labels in insn_labels to the current insertion point |
4452 | and treat them as text labels. */ | |
4453 | ||
4454 | static void | |
4455 | mips_move_text_labels (void) | |
4456 | { | |
4457 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4458 | } | |
4459 | ||
9e009953 MR |
4460 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4461 | ||
5f0fe04b TS |
4462 | static bfd_boolean |
4463 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4464 | { | |
4465 | bfd_boolean linkonce = FALSE; | |
4466 | segT symseg = S_GET_SEGMENT (sym); | |
4467 | ||
4468 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4469 | { | |
4470 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
4471 | linkonce = TRUE; | |
5f0fe04b TS |
4472 | /* The GNU toolchain uses an extension for ELF: a section |
4473 | beginning with the magic string .gnu.linkonce is a | |
4474 | linkonce section. */ | |
4475 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4476 | sizeof ".gnu.linkonce" - 1) == 0) | |
4477 | linkonce = TRUE; | |
5f0fe04b TS |
4478 | } |
4479 | return linkonce; | |
4480 | } | |
4481 | ||
e1b47bd5 | 4482 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4483 | linker to handle them specially, such as generating jalx instructions |
4484 | when needed. We also make them odd for the duration of the assembly, | |
4485 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4486 | in the adjust_symtab routine, while leaving them marked. This is |
4487 | convenient for the debugger and the disassembler. The linker knows | |
4488 | to make them odd again. */ | |
4489 | ||
4490 | static void | |
e1b47bd5 | 4491 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4492 | { |
df58fc94 | 4493 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4494 | |
f3ded42a RS |
4495 | if (mips_opts.mips16) |
4496 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4497 | else | |
4498 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4499 | if ((S_GET_VALUE (label) & 1) == 0 |
4500 | /* Don't adjust the address if the label is global or weak, or | |
4501 | in a link-once section, since we'll be emitting symbol reloc | |
4502 | references to it which will be patched up by the linker, and | |
4503 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4504 | && !S_IS_WEAK (label) | |
4505 | && !S_IS_EXTERNAL (label) | |
4506 | && !s_is_linkonce (label, now_seg)) | |
4507 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4508 | } | |
4509 | ||
4510 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4511 | ||
4512 | static void | |
4513 | mips_compressed_mark_labels (void) | |
4514 | { | |
4515 | struct insn_label_list *l; | |
4516 | ||
4517 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4518 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4519 | } |
4520 | ||
4d7206a2 RS |
4521 | /* End the current frag. Make it a variant frag and record the |
4522 | relaxation info. */ | |
4523 | ||
4524 | static void | |
4525 | relax_close_frag (void) | |
4526 | { | |
584892a6 | 4527 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4528 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4529 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4530 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4531 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4532 | ||
4533 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4534 | mips_relax.first_fixup = 0; | |
4535 | } | |
4536 | ||
4537 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4538 | See the comment above RELAX_ENCODE for more details. */ | |
4539 | ||
4540 | static void | |
4541 | relax_start (symbolS *symbol) | |
4542 | { | |
9c2799c2 | 4543 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4544 | mips_relax.sequence = 1; |
4545 | mips_relax.symbol = symbol; | |
4546 | } | |
4547 | ||
4548 | /* Start generating the second version of a relaxable sequence. | |
4549 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4550 | |
4551 | static void | |
4d7206a2 RS |
4552 | relax_switch (void) |
4553 | { | |
9c2799c2 | 4554 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4555 | mips_relax.sequence = 2; |
4556 | } | |
4557 | ||
4558 | /* End the current relaxable sequence. */ | |
4559 | ||
4560 | static void | |
4561 | relax_end (void) | |
4562 | { | |
9c2799c2 | 4563 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4564 | relax_close_frag (); |
4565 | mips_relax.sequence = 0; | |
4566 | } | |
4567 | ||
11625dd8 RS |
4568 | /* Return true if IP is a delayed branch or jump. */ |
4569 | ||
4570 | static inline bfd_boolean | |
4571 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4572 | { | |
4573 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4574 | | INSN_COND_BRANCH_DELAY | |
4575 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4576 | } | |
4577 | ||
4578 | /* Return true if IP is a compact branch or jump. */ | |
4579 | ||
4580 | static inline bfd_boolean | |
4581 | compact_branch_p (const struct mips_cl_insn *ip) | |
4582 | { | |
26545944 RS |
4583 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4584 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4585 | } |
4586 | ||
4587 | /* Return true if IP is an unconditional branch or jump. */ | |
4588 | ||
4589 | static inline bfd_boolean | |
4590 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4591 | { | |
4592 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4593 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4594 | } |
4595 | ||
4596 | /* Return true if IP is a branch-likely instruction. */ | |
4597 | ||
4598 | static inline bfd_boolean | |
4599 | branch_likely_p (const struct mips_cl_insn *ip) | |
4600 | { | |
4601 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4602 | } | |
4603 | ||
14fe068b RS |
4604 | /* Return the type of nop that should be used to fill the delay slot |
4605 | of delayed branch IP. */ | |
4606 | ||
4607 | static struct mips_cl_insn * | |
4608 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4609 | { | |
4610 | if (mips_opts.micromips | |
4611 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4612 | return µmips_nop32_insn; | |
4613 | return NOP_INSN; | |
4614 | } | |
4615 | ||
fc76e730 RS |
4616 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4617 | in operand N. */ | |
df58fc94 RS |
4618 | |
4619 | static unsigned int | |
fc76e730 | 4620 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4621 | { |
fc76e730 RS |
4622 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4623 | } | |
df58fc94 | 4624 | |
fc76e730 RS |
4625 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4626 | in operand N. */ | |
4627 | ||
4628 | static unsigned int | |
4629 | insn_write_mask (const struct mips_opcode *opcode) | |
4630 | { | |
4631 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4632 | } | |
4633 | ||
4634 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4635 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4636 | is set. */ | |
4637 | ||
4638 | static unsigned int | |
4639 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4640 | const struct mips_operand *operand, | |
4641 | unsigned int type_mask) | |
4642 | { | |
4643 | unsigned int uval, vsel; | |
4644 | ||
4645 | switch (operand->type) | |
df58fc94 | 4646 | { |
fc76e730 RS |
4647 | case OP_INT: |
4648 | case OP_MAPPED_INT: | |
4649 | case OP_MSB: | |
4650 | case OP_PCREL: | |
4651 | case OP_PERF_REG: | |
4652 | case OP_ADDIUSP_INT: | |
4653 | case OP_ENTRY_EXIT_LIST: | |
4654 | case OP_REPEAT_DEST_REG: | |
4655 | case OP_REPEAT_PREV_REG: | |
4656 | case OP_PC: | |
14daeee3 RS |
4657 | case OP_VU0_SUFFIX: |
4658 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4659 | case OP_IMM_INDEX: |
fc76e730 RS |
4660 | abort (); |
4661 | ||
25499ac7 MR |
4662 | case OP_REG28: |
4663 | return 1 << 28; | |
4664 | ||
fc76e730 | 4665 | case OP_REG: |
0f35dbc4 | 4666 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4667 | { |
4668 | const struct mips_reg_operand *reg_op; | |
4669 | ||
4670 | reg_op = (const struct mips_reg_operand *) operand; | |
4671 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4672 | return 0; | |
4673 | uval = insn_extract_operand (insn, operand); | |
4674 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4675 | } | |
4676 | ||
4677 | case OP_REG_PAIR: | |
4678 | { | |
4679 | const struct mips_reg_pair_operand *pair_op; | |
4680 | ||
4681 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4682 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4683 | return 0; | |
4684 | uval = insn_extract_operand (insn, operand); | |
4685 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4686 | } | |
4687 | ||
4688 | case OP_CLO_CLZ_DEST: | |
4689 | if (!(type_mask & (1 << OP_REG_GP))) | |
4690 | return 0; | |
4691 | uval = insn_extract_operand (insn, operand); | |
4692 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4693 | ||
7361da2c AB |
4694 | case OP_SAME_RS_RT: |
4695 | if (!(type_mask & (1 << OP_REG_GP))) | |
4696 | return 0; | |
4697 | uval = insn_extract_operand (insn, operand); | |
4698 | gas_assert ((uval & 31) == (uval >> 5)); | |
4699 | return 1 << (uval & 31); | |
4700 | ||
4701 | case OP_CHECK_PREV: | |
4702 | case OP_NON_ZERO_REG: | |
4703 | if (!(type_mask & (1 << OP_REG_GP))) | |
4704 | return 0; | |
4705 | uval = insn_extract_operand (insn, operand); | |
4706 | return 1 << (uval & 31); | |
4707 | ||
fc76e730 RS |
4708 | case OP_LWM_SWM_LIST: |
4709 | abort (); | |
4710 | ||
4711 | case OP_SAVE_RESTORE_LIST: | |
4712 | abort (); | |
4713 | ||
4714 | case OP_MDMX_IMM_REG: | |
4715 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4716 | return 0; | |
4717 | uval = insn_extract_operand (insn, operand); | |
4718 | vsel = uval >> 5; | |
4719 | if ((vsel & 0x18) == 0x18) | |
4720 | return 0; | |
4721 | return 1 << (uval & 31); | |
56d438b1 CF |
4722 | |
4723 | case OP_REG_INDEX: | |
4724 | if (!(type_mask & (1 << OP_REG_GP))) | |
4725 | return 0; | |
4726 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4727 | } |
fc76e730 RS |
4728 | abort (); |
4729 | } | |
4730 | ||
4731 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4732 | where bit N of OPNO_MASK is set if operand N should be included. | |
4733 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4734 | is set. */ | |
4735 | ||
4736 | static unsigned int | |
4737 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4738 | unsigned int type_mask, unsigned int opno_mask) | |
4739 | { | |
4740 | unsigned int opno, reg_mask; | |
4741 | ||
4742 | opno = 0; | |
4743 | reg_mask = 0; | |
4744 | while (opno_mask != 0) | |
4745 | { | |
4746 | if (opno_mask & 1) | |
4747 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4748 | opno_mask >>= 1; | |
4749 | opno += 1; | |
4750 | } | |
4751 | return reg_mask; | |
df58fc94 RS |
4752 | } |
4753 | ||
4c260379 RS |
4754 | /* Return the mask of core registers that IP reads. */ |
4755 | ||
4756 | static unsigned int | |
4757 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4758 | { | |
4759 | unsigned long pinfo, pinfo2; | |
4760 | unsigned int mask; | |
4761 | ||
fc76e730 | 4762 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4763 | pinfo = ip->insn_mo->pinfo; |
4764 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4765 | if (pinfo & INSN_UDI) |
4c260379 | 4766 | { |
fc76e730 RS |
4767 | /* UDI instructions have traditionally been assumed to read RS |
4768 | and RT. */ | |
4769 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4770 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4771 | } |
fc76e730 RS |
4772 | if (pinfo & INSN_READ_GPR_24) |
4773 | mask |= 1 << 24; | |
4774 | if (pinfo2 & INSN2_READ_GPR_16) | |
4775 | mask |= 1 << 16; | |
4776 | if (pinfo2 & INSN2_READ_SP) | |
4777 | mask |= 1 << SP; | |
26545944 | 4778 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4779 | mask |= 1 << 31; |
fe35f09f RS |
4780 | /* Don't include register 0. */ |
4781 | return mask & ~1; | |
4c260379 RS |
4782 | } |
4783 | ||
4784 | /* Return the mask of core registers that IP writes. */ | |
4785 | ||
4786 | static unsigned int | |
4787 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4788 | { | |
4789 | unsigned long pinfo, pinfo2; | |
4790 | unsigned int mask; | |
4791 | ||
fc76e730 | 4792 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4793 | pinfo = ip->insn_mo->pinfo; |
4794 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4795 | if (pinfo & INSN_WRITE_GPR_24) |
4796 | mask |= 1 << 24; | |
4797 | if (pinfo & INSN_WRITE_GPR_31) | |
4798 | mask |= 1 << 31; | |
4799 | if (pinfo & INSN_UDI) | |
4800 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4801 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4802 | if (pinfo2 & INSN2_WRITE_SP) | |
4803 | mask |= 1 << SP; | |
fe35f09f RS |
4804 | /* Don't include register 0. */ |
4805 | return mask & ~1; | |
4c260379 RS |
4806 | } |
4807 | ||
4808 | /* Return the mask of floating-point registers that IP reads. */ | |
4809 | ||
4810 | static unsigned int | |
4811 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4812 | { | |
fc76e730 | 4813 | unsigned long pinfo; |
4c260379 RS |
4814 | unsigned int mask; |
4815 | ||
9d5de888 CF |
4816 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4817 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4818 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4819 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4820 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4821 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4822 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4823 | mask |= mask << 1; |
4824 | return mask; | |
4825 | } | |
4826 | ||
4827 | /* Return the mask of floating-point registers that IP writes. */ | |
4828 | ||
4829 | static unsigned int | |
4830 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4831 | { | |
fc76e730 | 4832 | unsigned long pinfo; |
4c260379 RS |
4833 | unsigned int mask; |
4834 | ||
9d5de888 CF |
4835 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4836 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4837 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4838 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4839 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4840 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4841 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4842 | mask |= mask << 1; |
4843 | return mask; | |
4844 | } | |
4845 | ||
a1d78564 RS |
4846 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4847 | Check whether that is allowed. */ | |
4848 | ||
4849 | static bfd_boolean | |
4850 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4851 | { | |
4852 | const char *s = insn->name; | |
351cdf24 MF |
4853 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4854 | || FPR_SIZE == 64) | |
4855 | && mips_opts.oddspreg; | |
a1d78564 RS |
4856 | |
4857 | if (insn->pinfo == INSN_MACRO) | |
4858 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4859 | return TRUE; | |
4860 | ||
351cdf24 MF |
4861 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4862 | otherwise it depends on oddspreg. */ | |
4863 | if ((insn->pinfo & FP_S) | |
4864 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4865 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4866 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4867 | |
351cdf24 MF |
4868 | /* Allow odd registers for single-precision ops and double-precision if the |
4869 | floating-point registers are 64-bit wide. */ | |
4870 | switch (insn->pinfo & (FP_S | FP_D)) | |
4871 | { | |
4872 | case FP_S: | |
4873 | case 0: | |
4874 | return oddspreg; | |
4875 | case FP_D: | |
4876 | return FPR_SIZE == 64; | |
4877 | default: | |
4878 | break; | |
a1d78564 RS |
4879 | } |
4880 | ||
351cdf24 MF |
4881 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4882 | s = strchr (insn->name, '.'); | |
4883 | if (s != NULL && opnum == 2) | |
4884 | s = strchr (s + 1, '.'); | |
4885 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4886 | return oddspreg; | |
a1d78564 | 4887 | |
351cdf24 | 4888 | return FPR_SIZE == 64; |
a1d78564 RS |
4889 | } |
4890 | ||
a1d78564 RS |
4891 | /* Information about an instruction argument that we're trying to match. */ |
4892 | struct mips_arg_info | |
4893 | { | |
4894 | /* The instruction so far. */ | |
4895 | struct mips_cl_insn *insn; | |
4896 | ||
a92713e6 RS |
4897 | /* The first unconsumed operand token. */ |
4898 | struct mips_operand_token *token; | |
4899 | ||
a1d78564 RS |
4900 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4901 | int opnum; | |
4902 | ||
4903 | /* The 1-based argument number, for error reporting. This does not | |
4904 | count elided optional registers, etc.. */ | |
4905 | int argnum; | |
4906 | ||
4907 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4908 | unsigned int last_regno; | |
4909 | ||
4910 | /* If the first operand was an OP_REG, this is the register that it | |
4911 | specified, otherwise it is ILLEGAL_REG. */ | |
4912 | unsigned int dest_regno; | |
4913 | ||
4914 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4915 | where it gives the lsb position. */ | |
4916 | unsigned int last_op_int; | |
4917 | ||
60f20e8b | 4918 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4919 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4920 | possible. Match routines should not report errors if something |
4921 | is only invalid for !LAX_MATCH. */ | |
4922 | bfd_boolean lax_match; | |
a1d78564 | 4923 | |
a1d78564 RS |
4924 | /* True if a reference to the current AT register was seen. */ |
4925 | bfd_boolean seen_at; | |
4926 | }; | |
4927 | ||
1a00e612 RS |
4928 | /* Record that the argument is out of range. */ |
4929 | ||
4930 | static void | |
4931 | match_out_of_range (struct mips_arg_info *arg) | |
4932 | { | |
4933 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4934 | } | |
4935 | ||
4936 | /* Record that the argument isn't constant but needs to be. */ | |
4937 | ||
4938 | static void | |
4939 | match_not_constant (struct mips_arg_info *arg) | |
4940 | { | |
4941 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4942 | arg->argnum); | |
4943 | } | |
4944 | ||
a92713e6 RS |
4945 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4946 | and return true on success, otherwise return false. */ | |
a1d78564 | 4947 | |
a92713e6 RS |
4948 | static bfd_boolean |
4949 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4950 | { |
a92713e6 RS |
4951 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4952 | { | |
4953 | ++arg->token; | |
4954 | if (ch == ',') | |
4955 | arg->argnum += 1; | |
4956 | return TRUE; | |
4957 | } | |
4958 | return FALSE; | |
4959 | } | |
a1d78564 | 4960 | |
a92713e6 RS |
4961 | /* Try to get an expression from the next tokens in ARG. Consume the |
4962 | tokens and return true on success, storing the expression value in | |
4963 | VALUE and relocation types in R. */ | |
4964 | ||
4965 | static bfd_boolean | |
4966 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4967 | bfd_reloc_code_real_type *r) | |
4968 | { | |
d436c1c2 RS |
4969 | /* If the next token is a '(' that was parsed as being part of a base |
4970 | expression, assume we have an elided offset. The later match will fail | |
4971 | if this turns out to be wrong. */ | |
4972 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4973 | { |
d436c1c2 RS |
4974 | value->X_op = O_constant; |
4975 | value->X_add_number = 0; | |
4976 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4977 | return TRUE; |
4978 | } | |
4979 | ||
d436c1c2 RS |
4980 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4981 | For plain registers the default error seems more appropriate. */ | |
4982 | if (arg->token->type == OT_INTEGER | |
4983 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4984 | { |
d436c1c2 RS |
4985 | set_insn_error (arg->argnum, _("register value used as expression")); |
4986 | return FALSE; | |
a1d78564 | 4987 | } |
d436c1c2 RS |
4988 | |
4989 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4990 | { |
d436c1c2 RS |
4991 | *value = arg->token->u.integer.value; |
4992 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4993 | ++arg->token; | |
4994 | return TRUE; | |
a92713e6 | 4995 | } |
a92713e6 | 4996 | |
d436c1c2 RS |
4997 | set_insn_error_i |
4998 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4999 | arg->argnum); | |
5000 | return FALSE; | |
a92713e6 RS |
5001 | } |
5002 | ||
5003 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
de194d85 | 5004 | the tokens and return true on success, storing the constant value |
a54d5f8b | 5005 | in *VALUE. */ |
a92713e6 RS |
5006 | |
5007 | static bfd_boolean | |
1a00e612 | 5008 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
5009 | { |
5010 | expressionS ex; | |
5011 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 5012 | |
a92713e6 RS |
5013 | if (!match_expression (arg, &ex, r)) |
5014 | return FALSE; | |
5015 | ||
5016 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
5017 | *value = ex.X_add_number; |
5018 | else | |
5019 | { | |
c96425c5 MR |
5020 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
5021 | match_out_of_range (arg); | |
5022 | else | |
5023 | match_not_constant (arg); | |
1a00e612 | 5024 | return FALSE; |
a1d78564 | 5025 | } |
a92713e6 | 5026 | return TRUE; |
a1d78564 RS |
5027 | } |
5028 | ||
5029 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
5030 | appears in instruction OPCODE. */ | |
5031 | ||
5032 | static unsigned int | |
5033 | convert_reg_type (const struct mips_opcode *opcode, | |
5034 | enum mips_reg_operand_type type) | |
5035 | { | |
5036 | switch (type) | |
5037 | { | |
5038 | case OP_REG_GP: | |
5039 | return RTYPE_NUM | RTYPE_GP; | |
5040 | ||
5041 | case OP_REG_FP: | |
5042 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
5043 | FPR load, store or move (including moves to and from GPRs). */ | |
5044 | if ((mips_opts.ase & ASE_MDMX) | |
5045 | && (opcode->pinfo & FP_D) | |
43885403 | 5046 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 5047 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 5048 | | INSN_LOAD_COPROC |
67dc82bc | 5049 | | INSN_LOAD_MEMORY |
a1d78564 RS |
5050 | | INSN_STORE_MEMORY))) |
5051 | return RTYPE_FPU | RTYPE_VEC; | |
5052 | return RTYPE_FPU; | |
5053 | ||
5054 | case OP_REG_CCC: | |
5055 | if (opcode->pinfo & (FP_D | FP_S)) | |
5056 | return RTYPE_CCC | RTYPE_FCC; | |
5057 | return RTYPE_CCC; | |
5058 | ||
5059 | case OP_REG_VEC: | |
5060 | if (opcode->membership & INSN_5400) | |
5061 | return RTYPE_FPU; | |
5062 | return RTYPE_FPU | RTYPE_VEC; | |
5063 | ||
5064 | case OP_REG_ACC: | |
5065 | return RTYPE_ACC; | |
5066 | ||
5067 | case OP_REG_COPRO: | |
5068 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
5069 | return RTYPE_NUM | RTYPE_CP0; | |
5070 | return RTYPE_NUM; | |
5071 | ||
5072 | case OP_REG_HW: | |
5073 | return RTYPE_NUM; | |
14daeee3 RS |
5074 | |
5075 | case OP_REG_VI: | |
5076 | return RTYPE_NUM | RTYPE_VI; | |
5077 | ||
5078 | case OP_REG_VF: | |
5079 | return RTYPE_NUM | RTYPE_VF; | |
5080 | ||
5081 | case OP_REG_R5900_I: | |
5082 | return RTYPE_R5900_I; | |
5083 | ||
5084 | case OP_REG_R5900_Q: | |
5085 | return RTYPE_R5900_Q; | |
5086 | ||
5087 | case OP_REG_R5900_R: | |
5088 | return RTYPE_R5900_R; | |
5089 | ||
5090 | case OP_REG_R5900_ACC: | |
5091 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
5092 | |
5093 | case OP_REG_MSA: | |
5094 | return RTYPE_MSA; | |
5095 | ||
5096 | case OP_REG_MSA_CTRL: | |
5097 | return RTYPE_NUM; | |
a1d78564 RS |
5098 | } |
5099 | abort (); | |
5100 | } | |
5101 | ||
5102 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
5103 | ||
5104 | static void | |
5105 | check_regno (struct mips_arg_info *arg, | |
5106 | enum mips_reg_operand_type type, unsigned int regno) | |
5107 | { | |
5108 | if (AT && type == OP_REG_GP && regno == AT) | |
5109 | arg->seen_at = TRUE; | |
5110 | ||
5111 | if (type == OP_REG_FP | |
5112 | && (regno & 1) != 0 | |
a1d78564 | 5113 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
5114 | { |
5115 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
5116 | so maintain a warning for FP32 but raise an error for the new | |
5117 | cases. */ | |
5118 | if (FPR_SIZE == 32) | |
5119 | as_warn (_("float register should be even, was %d"), regno); | |
5120 | else | |
5121 | as_bad (_("float register should be even, was %d"), regno); | |
5122 | } | |
a1d78564 RS |
5123 | |
5124 | if (type == OP_REG_CCC) | |
5125 | { | |
5126 | const char *name; | |
5127 | size_t length; | |
5128 | ||
5129 | name = arg->insn->insn_mo->name; | |
5130 | length = strlen (name); | |
5131 | if ((regno & 1) != 0 | |
5132 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
5133 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 5134 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
5135 | name, regno); |
5136 | ||
5137 | if ((regno & 3) != 0 | |
5138 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 5139 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
5140 | name, regno); |
5141 | } | |
5142 | } | |
5143 | ||
a92713e6 RS |
5144 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
5145 | a register of type TYPE. Return true on success, storing the register | |
5146 | number in *REGNO and warning about any dubious uses. */ | |
5147 | ||
5148 | static bfd_boolean | |
5149 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5150 | unsigned int symval, unsigned int *regno) | |
5151 | { | |
5152 | if (type == OP_REG_VEC) | |
5153 | symval = mips_prefer_vec_regno (symval); | |
5154 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
5155 | return FALSE; | |
5156 | ||
5157 | *regno = symval & RNUM_MASK; | |
5158 | check_regno (arg, type, *regno); | |
5159 | return TRUE; | |
5160 | } | |
5161 | ||
5162 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
5163 | Consume the token and return true on success, storing the register | |
5164 | number in *REGNO. Return false on failure. */ | |
5165 | ||
5166 | static bfd_boolean | |
5167 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5168 | unsigned int *regno) | |
5169 | { | |
5170 | if (arg->token->type == OT_REG | |
5171 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5172 | { | |
5173 | ++arg->token; | |
5174 | return TRUE; | |
5175 | } | |
5176 | return FALSE; | |
5177 | } | |
5178 | ||
5179 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5180 | Consume the token and return true on success, storing the register numbers | |
5181 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5182 | ||
5183 | static bfd_boolean | |
5184 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5185 | unsigned int *regno1, unsigned int *regno2) | |
5186 | { | |
5187 | if (match_reg (arg, type, regno1)) | |
5188 | { | |
5189 | *regno2 = *regno1; | |
5190 | return TRUE; | |
5191 | } | |
5192 | if (arg->token->type == OT_REG_RANGE | |
5193 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5194 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5195 | && *regno1 <= *regno2) | |
5196 | { | |
5197 | ++arg->token; | |
5198 | return TRUE; | |
5199 | } | |
5200 | return FALSE; | |
5201 | } | |
5202 | ||
a1d78564 RS |
5203 | /* OP_INT matcher. */ |
5204 | ||
a92713e6 | 5205 | static bfd_boolean |
a1d78564 | 5206 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5207 | const struct mips_operand *operand_base) |
a1d78564 RS |
5208 | { |
5209 | const struct mips_int_operand *operand; | |
3ccad066 | 5210 | unsigned int uval; |
a1d78564 RS |
5211 | int min_val, max_val, factor; |
5212 | offsetT sval; | |
a1d78564 RS |
5213 | |
5214 | operand = (const struct mips_int_operand *) operand_base; | |
5215 | factor = 1 << operand->shift; | |
3ccad066 RS |
5216 | min_val = mips_int_operand_min (operand); |
5217 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5218 | |
d436c1c2 RS |
5219 | if (operand_base->lsb == 0 |
5220 | && operand_base->size == 16 | |
5221 | && operand->shift == 0 | |
5222 | && operand->bias == 0 | |
5223 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5224 | { |
5225 | /* The operand can be relocated. */ | |
a92713e6 RS |
5226 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5227 | return FALSE; | |
5228 | ||
c96425c5 MR |
5229 | if (offset_expr.X_op == O_big) |
5230 | { | |
5231 | match_out_of_range (arg); | |
5232 | return FALSE; | |
5233 | } | |
5234 | ||
a92713e6 | 5235 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
33eaf5de | 5236 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5237 | leave the relocation value in offset_expr and offset_relocs |
5238 | for the caller to process. */ | |
a92713e6 RS |
5239 | return TRUE; |
5240 | ||
5241 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5242 | { |
60f20e8b RS |
5243 | /* Accept non-constant operands if no later alternative matches, |
5244 | leaving it for the caller to process. */ | |
5245 | if (!arg->lax_match) | |
602b88e3 MR |
5246 | { |
5247 | match_not_constant (arg); | |
5248 | return FALSE; | |
5249 | } | |
a92713e6 RS |
5250 | offset_reloc[0] = BFD_RELOC_LO16; |
5251 | return TRUE; | |
a1d78564 | 5252 | } |
a92713e6 | 5253 | |
a1d78564 RS |
5254 | /* Clear the global state; we're going to install the operand |
5255 | ourselves. */ | |
a92713e6 | 5256 | sval = offset_expr.X_add_number; |
a1d78564 | 5257 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5258 | |
5259 | /* For compatibility with older assemblers, we accept | |
5260 | 0x8000-0xffff as signed 16-bit numbers when only | |
5261 | signed numbers are allowed. */ | |
5262 | if (sval > max_val) | |
5263 | { | |
5264 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5265 | if (!arg->lax_match && sval <= max_val) | |
20c59b84 MR |
5266 | { |
5267 | match_out_of_range (arg); | |
5268 | return FALSE; | |
5269 | } | |
60f20e8b | 5270 | } |
a1d78564 RS |
5271 | } |
5272 | else | |
5273 | { | |
1a00e612 | 5274 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5275 | return FALSE; |
a1d78564 RS |
5276 | } |
5277 | ||
5278 | arg->last_op_int = sval; | |
5279 | ||
1a00e612 | 5280 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5281 | { |
1a00e612 RS |
5282 | match_out_of_range (arg); |
5283 | return FALSE; | |
a1d78564 RS |
5284 | } |
5285 | ||
5286 | uval = (unsigned int) sval >> operand->shift; | |
5287 | uval -= operand->bias; | |
5288 | ||
5289 | /* Handle -mfix-cn63xxp1. */ | |
5290 | if (arg->opnum == 1 | |
5291 | && mips_fix_cn63xxp1 | |
5292 | && !mips_opts.micromips | |
5293 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5294 | switch (uval) | |
5295 | { | |
5296 | case 5: | |
5297 | case 25: | |
5298 | case 26: | |
5299 | case 27: | |
5300 | case 28: | |
5301 | case 29: | |
5302 | case 30: | |
5303 | case 31: | |
5304 | /* These are ok. */ | |
5305 | break; | |
5306 | ||
5307 | default: | |
5308 | /* The rest must be changed to 28. */ | |
5309 | uval = 28; | |
5310 | break; | |
5311 | } | |
5312 | ||
5313 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5314 | return TRUE; |
a1d78564 RS |
5315 | } |
5316 | ||
5317 | /* OP_MAPPED_INT matcher. */ | |
5318 | ||
a92713e6 | 5319 | static bfd_boolean |
a1d78564 | 5320 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5321 | const struct mips_operand *operand_base) |
a1d78564 RS |
5322 | { |
5323 | const struct mips_mapped_int_operand *operand; | |
5324 | unsigned int uval, num_vals; | |
5325 | offsetT sval; | |
5326 | ||
5327 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5328 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5329 | return FALSE; |
a1d78564 RS |
5330 | |
5331 | num_vals = 1 << operand_base->size; | |
5332 | for (uval = 0; uval < num_vals; uval++) | |
5333 | if (operand->int_map[uval] == sval) | |
5334 | break; | |
5335 | if (uval == num_vals) | |
1a00e612 RS |
5336 | { |
5337 | match_out_of_range (arg); | |
5338 | return FALSE; | |
5339 | } | |
a1d78564 RS |
5340 | |
5341 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5342 | return TRUE; |
a1d78564 RS |
5343 | } |
5344 | ||
5345 | /* OP_MSB matcher. */ | |
5346 | ||
a92713e6 | 5347 | static bfd_boolean |
a1d78564 | 5348 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5349 | const struct mips_operand *operand_base) |
a1d78564 RS |
5350 | { |
5351 | const struct mips_msb_operand *operand; | |
5352 | int min_val, max_val, max_high; | |
5353 | offsetT size, sval, high; | |
5354 | ||
5355 | operand = (const struct mips_msb_operand *) operand_base; | |
5356 | min_val = operand->bias; | |
5357 | max_val = min_val + (1 << operand_base->size) - 1; | |
5358 | max_high = operand->opsize; | |
5359 | ||
1a00e612 | 5360 | if (!match_const_int (arg, &size)) |
a92713e6 | 5361 | return FALSE; |
a1d78564 RS |
5362 | |
5363 | high = size + arg->last_op_int; | |
5364 | sval = operand->add_lsb ? high : size; | |
5365 | ||
5366 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5367 | { | |
1a00e612 RS |
5368 | match_out_of_range (arg); |
5369 | return FALSE; | |
a1d78564 RS |
5370 | } |
5371 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5372 | return TRUE; |
a1d78564 RS |
5373 | } |
5374 | ||
5375 | /* OP_REG matcher. */ | |
5376 | ||
a92713e6 | 5377 | static bfd_boolean |
a1d78564 | 5378 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5379 | const struct mips_operand *operand_base) |
a1d78564 RS |
5380 | { |
5381 | const struct mips_reg_operand *operand; | |
a92713e6 | 5382 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5383 | |
5384 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5385 | if (!match_reg (arg, operand->reg_type, ®no)) |
5386 | return FALSE; | |
a1d78564 RS |
5387 | |
5388 | if (operand->reg_map) | |
5389 | { | |
5390 | num_vals = 1 << operand->root.size; | |
5391 | for (uval = 0; uval < num_vals; uval++) | |
5392 | if (operand->reg_map[uval] == regno) | |
5393 | break; | |
5394 | if (num_vals == uval) | |
a92713e6 | 5395 | return FALSE; |
a1d78564 RS |
5396 | } |
5397 | else | |
5398 | uval = regno; | |
5399 | ||
a1d78564 RS |
5400 | arg->last_regno = regno; |
5401 | if (arg->opnum == 1) | |
5402 | arg->dest_regno = regno; | |
5403 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5404 | return TRUE; |
a1d78564 RS |
5405 | } |
5406 | ||
5407 | /* OP_REG_PAIR matcher. */ | |
5408 | ||
a92713e6 | 5409 | static bfd_boolean |
a1d78564 | 5410 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5411 | const struct mips_operand *operand_base) |
a1d78564 RS |
5412 | { |
5413 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5414 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5415 | |
5416 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5417 | if (!match_reg (arg, operand->reg_type, ®no1) |
5418 | || !match_char (arg, ',') | |
5419 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5420 | return FALSE; | |
a1d78564 RS |
5421 | |
5422 | num_vals = 1 << operand_base->size; | |
5423 | for (uval = 0; uval < num_vals; uval++) | |
5424 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5425 | break; | |
5426 | if (uval == num_vals) | |
a92713e6 | 5427 | return FALSE; |
a1d78564 | 5428 | |
a1d78564 | 5429 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5430 | return TRUE; |
a1d78564 RS |
5431 | } |
5432 | ||
5433 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5434 | ||
a92713e6 RS |
5435 | static bfd_boolean |
5436 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5437 | { |
a92713e6 RS |
5438 | bfd_reloc_code_real_type r[3]; |
5439 | ||
5440 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5441 | } |
5442 | ||
5443 | /* OP_PERF_REG matcher. */ | |
5444 | ||
a92713e6 | 5445 | static bfd_boolean |
a1d78564 | 5446 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5447 | const struct mips_operand *operand) |
a1d78564 RS |
5448 | { |
5449 | offsetT sval; | |
5450 | ||
1a00e612 | 5451 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5452 | return FALSE; |
a1d78564 RS |
5453 | |
5454 | if (sval != 0 | |
5455 | && (sval != 1 | |
5456 | || (mips_opts.arch == CPU_R5900 | |
5457 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5458 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5459 | { | |
1a00e612 RS |
5460 | set_insn_error (arg->argnum, _("invalid performance register")); |
5461 | return FALSE; | |
a1d78564 RS |
5462 | } |
5463 | ||
5464 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5465 | return TRUE; |
a1d78564 RS |
5466 | } |
5467 | ||
5468 | /* OP_ADDIUSP matcher. */ | |
5469 | ||
a92713e6 | 5470 | static bfd_boolean |
a1d78564 | 5471 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5472 | const struct mips_operand *operand) |
a1d78564 RS |
5473 | { |
5474 | offsetT sval; | |
5475 | unsigned int uval; | |
5476 | ||
1a00e612 | 5477 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5478 | return FALSE; |
a1d78564 RS |
5479 | |
5480 | if (sval % 4) | |
1a00e612 RS |
5481 | { |
5482 | match_out_of_range (arg); | |
5483 | return FALSE; | |
5484 | } | |
a1d78564 RS |
5485 | |
5486 | sval /= 4; | |
5487 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5488 | { |
5489 | match_out_of_range (arg); | |
5490 | return FALSE; | |
5491 | } | |
a1d78564 RS |
5492 | |
5493 | uval = (unsigned int) sval; | |
5494 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5495 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5496 | return TRUE; |
a1d78564 RS |
5497 | } |
5498 | ||
5499 | /* OP_CLO_CLZ_DEST matcher. */ | |
5500 | ||
a92713e6 | 5501 | static bfd_boolean |
a1d78564 | 5502 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5503 | const struct mips_operand *operand) |
a1d78564 RS |
5504 | { |
5505 | unsigned int regno; | |
5506 | ||
a92713e6 RS |
5507 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5508 | return FALSE; | |
a1d78564 | 5509 | |
a1d78564 | 5510 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5511 | return TRUE; |
a1d78564 RS |
5512 | } |
5513 | ||
7361da2c AB |
5514 | /* OP_CHECK_PREV matcher. */ |
5515 | ||
5516 | static bfd_boolean | |
5517 | match_check_prev_operand (struct mips_arg_info *arg, | |
5518 | const struct mips_operand *operand_base) | |
5519 | { | |
5520 | const struct mips_check_prev_operand *operand; | |
5521 | unsigned int regno; | |
5522 | ||
5523 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5524 | ||
5525 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5526 | return FALSE; | |
5527 | ||
5528 | if (!operand->zero_ok && regno == 0) | |
5529 | return FALSE; | |
5530 | ||
5531 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5532 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5533 | || (operand->equal_ok && regno == arg->last_regno)) | |
5534 | { | |
5535 | arg->last_regno = regno; | |
5536 | insn_insert_operand (arg->insn, operand_base, regno); | |
5537 | return TRUE; | |
5538 | } | |
5539 | ||
5540 | return FALSE; | |
5541 | } | |
5542 | ||
5543 | /* OP_SAME_RS_RT matcher. */ | |
5544 | ||
5545 | static bfd_boolean | |
5546 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5547 | const struct mips_operand *operand) | |
5548 | { | |
5549 | unsigned int regno; | |
5550 | ||
5551 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5552 | return FALSE; | |
5553 | ||
5554 | if (regno == 0) | |
5555 | { | |
5556 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5557 | return FALSE; | |
5558 | } | |
5559 | ||
5560 | arg->last_regno = regno; | |
5561 | ||
5562 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5563 | return TRUE; | |
5564 | } | |
5565 | ||
a1d78564 RS |
5566 | /* OP_LWM_SWM_LIST matcher. */ |
5567 | ||
a92713e6 | 5568 | static bfd_boolean |
a1d78564 | 5569 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5570 | const struct mips_operand *operand) |
a1d78564 | 5571 | { |
a92713e6 RS |
5572 | unsigned int reglist, sregs, ra, regno1, regno2; |
5573 | struct mips_arg_info reset; | |
a1d78564 | 5574 | |
a92713e6 RS |
5575 | reglist = 0; |
5576 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5577 | return FALSE; | |
5578 | do | |
5579 | { | |
5580 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5581 | { | |
5582 | reglist |= 1 << FP; | |
5583 | regno2 = S7; | |
5584 | } | |
5585 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5586 | reset = *arg; | |
5587 | } | |
5588 | while (match_char (arg, ',') | |
5589 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5590 | *arg = reset; | |
a1d78564 RS |
5591 | |
5592 | if (operand->size == 2) | |
5593 | { | |
5594 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5595 | ||
5596 | s0, ra | |
5597 | s0, s1, ra, s2, s3 | |
5598 | s0-s2, ra | |
5599 | ||
5600 | and any permutations of these. */ | |
5601 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5602 | return FALSE; |
a1d78564 RS |
5603 | |
5604 | sregs = (reglist >> 17) & 7; | |
5605 | ra = 0; | |
5606 | } | |
5607 | else | |
5608 | { | |
5609 | /* The list must include at least one of ra and s0-sN, | |
5610 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5611 | which are $23 and $30 respectively.) E.g.: | |
5612 | ||
5613 | ra | |
5614 | s0 | |
5615 | ra, s0, s1, s2 | |
5616 | s0-s8 | |
5617 | s0-s5, ra | |
5618 | ||
5619 | and any permutations of these. */ | |
5620 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5621 | return FALSE; |
a1d78564 RS |
5622 | |
5623 | ra = (reglist >> 27) & 0x10; | |
5624 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5625 | } | |
5626 | sregs += 1; | |
5627 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5628 | return FALSE; |
a1d78564 RS |
5629 | |
5630 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5631 | return TRUE; |
a1d78564 RS |
5632 | } |
5633 | ||
364215c8 RS |
5634 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5635 | ||
a92713e6 | 5636 | static unsigned int |
364215c8 | 5637 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5638 | const struct mips_operand *operand) |
364215c8 RS |
5639 | { |
5640 | unsigned int mask; | |
5641 | bfd_boolean is_exit; | |
5642 | ||
5643 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5644 | are different. */ | |
5645 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5646 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5647 | do |
364215c8 RS |
5648 | { |
5649 | unsigned int regno1, regno2; | |
5650 | bfd_boolean is_freg; | |
5651 | ||
a92713e6 | 5652 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5653 | is_freg = FALSE; |
a92713e6 | 5654 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5655 | is_freg = TRUE; |
5656 | else | |
a92713e6 | 5657 | return FALSE; |
364215c8 RS |
5658 | |
5659 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5660 | { | |
5661 | mask &= ~(7 << 3); | |
5662 | mask |= (5 + regno2) << 3; | |
5663 | } | |
5664 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5665 | mask |= (regno2 - 3) << 3; | |
5666 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5667 | mask |= (regno2 - 15) << 1; | |
5668 | else if (regno1 == RA && regno2 == RA) | |
5669 | mask |= 1; | |
5670 | else | |
a92713e6 | 5671 | return FALSE; |
364215c8 | 5672 | } |
a92713e6 RS |
5673 | while (match_char (arg, ',')); |
5674 | ||
364215c8 | 5675 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5676 | return TRUE; |
364215c8 RS |
5677 | } |
5678 | ||
38bf472a MR |
5679 | /* Encode regular MIPS SAVE/RESTORE instruction operands according to |
5680 | the argument register mask AMASK, the number of static registers | |
5681 | saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5682 | respectively, and the frame size FRAME_SIZE. */ | |
5683 | ||
5684 | static unsigned int | |
5685 | mips_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5686 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5687 | unsigned int frame_size) | |
5688 | { | |
5689 | return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15) | |
5690 | | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6)); | |
5691 | } | |
5692 | ||
5693 | /* Encode MIPS16 SAVE/RESTORE instruction operands according to the | |
5694 | argument register mask AMASK, the number of static registers saved | |
5695 | NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5696 | respectively, and the frame size FRAME_SIZE. */ | |
5697 | ||
5698 | static unsigned int | |
5699 | mips16_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5700 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5701 | unsigned int frame_size) | |
5702 | { | |
5703 | unsigned int args; | |
5704 | ||
5705 | args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf); | |
5706 | if (nsreg || amask || frame_size == 0 || frame_size > 16) | |
5707 | args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16) | |
5708 | | ((frame_size & 0xf0) << 16)); | |
5709 | return args; | |
5710 | } | |
5711 | ||
364215c8 RS |
5712 | /* OP_SAVE_RESTORE_LIST matcher. */ |
5713 | ||
a92713e6 RS |
5714 | static bfd_boolean |
5715 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5716 | { |
5717 | unsigned int opcode, args, statics, sregs; | |
5718 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
38bf472a | 5719 | unsigned int arg_mask, ra, s0, s1; |
364215c8 | 5720 | offsetT frame_size; |
364215c8 | 5721 | |
364215c8 RS |
5722 | opcode = arg->insn->insn_opcode; |
5723 | frame_size = 0; | |
5724 | num_frame_sizes = 0; | |
5725 | args = 0; | |
5726 | statics = 0; | |
5727 | sregs = 0; | |
38bf472a MR |
5728 | ra = 0; |
5729 | s0 = 0; | |
5730 | s1 = 0; | |
a92713e6 | 5731 | do |
364215c8 RS |
5732 | { |
5733 | unsigned int regno1, regno2; | |
5734 | ||
a92713e6 | 5735 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5736 | { |
5737 | /* Handle the frame size. */ | |
1a00e612 | 5738 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5739 | return FALSE; |
364215c8 | 5740 | num_frame_sizes += 1; |
364215c8 RS |
5741 | } |
5742 | else | |
5743 | { | |
a92713e6 RS |
5744 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5745 | return FALSE; | |
364215c8 RS |
5746 | |
5747 | while (regno1 <= regno2) | |
5748 | { | |
5749 | if (regno1 >= 4 && regno1 <= 7) | |
5750 | { | |
5751 | if (num_frame_sizes == 0) | |
5752 | /* args $a0-$a3 */ | |
5753 | args |= 1 << (regno1 - 4); | |
5754 | else | |
5755 | /* statics $a0-$a3 */ | |
5756 | statics |= 1 << (regno1 - 4); | |
5757 | } | |
5758 | else if (regno1 >= 16 && regno1 <= 23) | |
5759 | /* $s0-$s7 */ | |
5760 | sregs |= 1 << (regno1 - 16); | |
5761 | else if (regno1 == 30) | |
5762 | /* $s8 */ | |
5763 | sregs |= 1 << 8; | |
5764 | else if (regno1 == 31) | |
5765 | /* Add $ra to insn. */ | |
38bf472a | 5766 | ra = 1; |
364215c8 | 5767 | else |
a92713e6 | 5768 | return FALSE; |
364215c8 RS |
5769 | regno1 += 1; |
5770 | if (regno1 == 24) | |
5771 | regno1 = 30; | |
5772 | } | |
5773 | } | |
364215c8 | 5774 | } |
a92713e6 | 5775 | while (match_char (arg, ',')); |
364215c8 RS |
5776 | |
5777 | /* Encode args/statics combination. */ | |
5778 | if (args & statics) | |
a92713e6 | 5779 | return FALSE; |
364215c8 RS |
5780 | else if (args == 0xf) |
5781 | /* All $a0-$a3 are args. */ | |
38bf472a | 5782 | arg_mask = MIPS_SVRS_ALL_ARGS; |
364215c8 RS |
5783 | else if (statics == 0xf) |
5784 | /* All $a0-$a3 are statics. */ | |
38bf472a | 5785 | arg_mask = MIPS_SVRS_ALL_STATICS; |
364215c8 RS |
5786 | else |
5787 | { | |
5788 | /* Count arg registers. */ | |
5789 | num_args = 0; | |
5790 | while (args & 0x1) | |
5791 | { | |
5792 | args >>= 1; | |
5793 | num_args += 1; | |
5794 | } | |
5795 | if (args != 0) | |
a92713e6 | 5796 | return FALSE; |
364215c8 RS |
5797 | |
5798 | /* Count static registers. */ | |
5799 | num_statics = 0; | |
5800 | while (statics & 0x8) | |
5801 | { | |
5802 | statics = (statics << 1) & 0xf; | |
5803 | num_statics += 1; | |
5804 | } | |
5805 | if (statics != 0) | |
a92713e6 | 5806 | return FALSE; |
364215c8 RS |
5807 | |
5808 | /* Encode args/statics. */ | |
38bf472a | 5809 | arg_mask = (num_args << 2) | num_statics; |
364215c8 RS |
5810 | } |
5811 | ||
5812 | /* Encode $s0/$s1. */ | |
5813 | if (sregs & (1 << 0)) /* $s0 */ | |
38bf472a | 5814 | s0 = 1; |
364215c8 | 5815 | if (sregs & (1 << 1)) /* $s1 */ |
38bf472a | 5816 | s1 = 1; |
364215c8 RS |
5817 | sregs >>= 2; |
5818 | ||
5819 | /* Encode $s2-$s8. */ | |
5820 | num_sregs = 0; | |
5821 | while (sregs & 1) | |
5822 | { | |
5823 | sregs >>= 1; | |
5824 | num_sregs += 1; | |
5825 | } | |
5826 | if (sregs != 0) | |
a92713e6 | 5827 | return FALSE; |
364215c8 RS |
5828 | |
5829 | /* Encode frame size. */ | |
5830 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5831 | { |
5832 | set_insn_error (arg->argnum, _("missing frame size")); | |
5833 | return FALSE; | |
5834 | } | |
5835 | if (num_frame_sizes > 1) | |
5836 | { | |
5837 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5838 | return FALSE; | |
5839 | } | |
5840 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5841 | { | |
5842 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5843 | return FALSE; | |
5844 | } | |
38bf472a | 5845 | frame_size /= 8; |
364215c8 | 5846 | |
364215c8 | 5847 | /* Finally build the instruction. */ |
38bf472a MR |
5848 | if (mips_opts.mips16) |
5849 | opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5850 | frame_size); | |
5851 | else if (!mips_opts.micromips) | |
5852 | opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5853 | frame_size); | |
5854 | else | |
5855 | abort (); | |
5856 | ||
364215c8 | 5857 | arg->insn->insn_opcode = opcode; |
a92713e6 | 5858 | return TRUE; |
364215c8 RS |
5859 | } |
5860 | ||
a1d78564 RS |
5861 | /* OP_MDMX_IMM_REG matcher. */ |
5862 | ||
a92713e6 | 5863 | static bfd_boolean |
a1d78564 | 5864 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5865 | const struct mips_operand *operand) |
a1d78564 | 5866 | { |
a92713e6 | 5867 | unsigned int regno, uval; |
a1d78564 RS |
5868 | bfd_boolean is_qh; |
5869 | const struct mips_opcode *opcode; | |
5870 | ||
5871 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5872 | instruction. Start out with that bit in place. */ | |
5873 | opcode = arg->insn->insn_mo; | |
5874 | uval = mips_extract_operand (operand, opcode->match); | |
5875 | is_qh = (uval != 0); | |
5876 | ||
56d438b1 | 5877 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5878 | { |
5879 | if ((opcode->membership & INSN_5400) | |
5880 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5881 | { | |
1a00e612 RS |
5882 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5883 | arg->argnum); | |
5884 | return FALSE; | |
a1d78564 RS |
5885 | } |
5886 | ||
56d438b1 CF |
5887 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5888 | return FALSE; | |
5889 | ++arg->token; | |
5890 | ||
a1d78564 RS |
5891 | /* Check whether this is a vector register or a broadcast of |
5892 | a single element. */ | |
56d438b1 | 5893 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5894 | { |
56d438b1 | 5895 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5896 | { |
1a00e612 RS |
5897 | set_insn_error (arg->argnum, _("invalid element selector")); |
5898 | return FALSE; | |
a1d78564 | 5899 | } |
56d438b1 CF |
5900 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5901 | ++arg->token; | |
a1d78564 RS |
5902 | } |
5903 | else | |
5904 | { | |
5905 | /* A full vector. */ | |
5906 | if ((opcode->membership & INSN_5400) | |
5907 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5908 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5909 | { | |
1a00e612 RS |
5910 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5911 | arg->argnum); | |
5912 | return FALSE; | |
a1d78564 RS |
5913 | } |
5914 | ||
5915 | if (is_qh) | |
5916 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5917 | else | |
5918 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5919 | } | |
a1d78564 RS |
5920 | uval |= regno; |
5921 | } | |
5922 | else | |
5923 | { | |
5924 | offsetT sval; | |
5925 | ||
1a00e612 | 5926 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5927 | return FALSE; |
a1d78564 RS |
5928 | if (sval < 0 || sval > 31) |
5929 | { | |
1a00e612 RS |
5930 | match_out_of_range (arg); |
5931 | return FALSE; | |
a1d78564 RS |
5932 | } |
5933 | uval |= (sval & 31); | |
5934 | if (is_qh) | |
5935 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5936 | else | |
5937 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5938 | } | |
5939 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5940 | return TRUE; |
a1d78564 RS |
5941 | } |
5942 | ||
56d438b1 CF |
5943 | /* OP_IMM_INDEX matcher. */ |
5944 | ||
5945 | static bfd_boolean | |
5946 | match_imm_index_operand (struct mips_arg_info *arg, | |
5947 | const struct mips_operand *operand) | |
5948 | { | |
5949 | unsigned int max_val; | |
5950 | ||
5951 | if (arg->token->type != OT_INTEGER_INDEX) | |
5952 | return FALSE; | |
5953 | ||
5954 | max_val = (1 << operand->size) - 1; | |
5955 | if (arg->token->u.index > max_val) | |
5956 | { | |
5957 | match_out_of_range (arg); | |
5958 | return FALSE; | |
5959 | } | |
5960 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5961 | ++arg->token; | |
5962 | return TRUE; | |
5963 | } | |
5964 | ||
5965 | /* OP_REG_INDEX matcher. */ | |
5966 | ||
5967 | static bfd_boolean | |
5968 | match_reg_index_operand (struct mips_arg_info *arg, | |
5969 | const struct mips_operand *operand) | |
5970 | { | |
5971 | unsigned int regno; | |
5972 | ||
5973 | if (arg->token->type != OT_REG_INDEX) | |
5974 | return FALSE; | |
5975 | ||
5976 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5977 | return FALSE; | |
5978 | ||
5979 | insn_insert_operand (arg->insn, operand, regno); | |
5980 | ++arg->token; | |
5981 | return TRUE; | |
5982 | } | |
5983 | ||
a1d78564 RS |
5984 | /* OP_PC matcher. */ |
5985 | ||
a92713e6 RS |
5986 | static bfd_boolean |
5987 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5988 | { |
a92713e6 RS |
5989 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5990 | { | |
5991 | ++arg->token; | |
5992 | return TRUE; | |
5993 | } | |
5994 | return FALSE; | |
a1d78564 RS |
5995 | } |
5996 | ||
25499ac7 MR |
5997 | /* OP_REG28 matcher. */ |
5998 | ||
5999 | static bfd_boolean | |
6000 | match_reg28_operand (struct mips_arg_info *arg) | |
6001 | { | |
6002 | unsigned int regno; | |
6003 | ||
6004 | if (arg->token->type == OT_REG | |
6005 | && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) | |
6006 | && regno == GP) | |
6007 | { | |
6008 | ++arg->token; | |
6009 | return TRUE; | |
6010 | } | |
6011 | return FALSE; | |
6012 | } | |
6013 | ||
7361da2c AB |
6014 | /* OP_NON_ZERO_REG matcher. */ |
6015 | ||
6016 | static bfd_boolean | |
6017 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
6018 | const struct mips_operand *operand) | |
6019 | { | |
6020 | unsigned int regno; | |
6021 | ||
6022 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
6023 | return FALSE; | |
6024 | ||
6025 | if (regno == 0) | |
85bec12d MF |
6026 | { |
6027 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
6028 | return FALSE; | |
6029 | } | |
7361da2c AB |
6030 | |
6031 | arg->last_regno = regno; | |
6032 | insn_insert_operand (arg->insn, operand, regno); | |
6033 | return TRUE; | |
6034 | } | |
6035 | ||
a1d78564 RS |
6036 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
6037 | register that we need to match. */ | |
6038 | ||
a92713e6 RS |
6039 | static bfd_boolean |
6040 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
6041 | { |
6042 | unsigned int regno; | |
6043 | ||
a92713e6 | 6044 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
6045 | } |
6046 | ||
33f46696 MR |
6047 | /* Try to match a floating-point constant from ARG for LI.S or LI.D. |
6048 | LENGTH is the length of the value in bytes (4 for float, 8 for double) | |
6049 | and USING_GPRS says whether the destination is a GPR rather than an FPR. | |
89565f1b RS |
6050 | |
6051 | Return the constant in IMM and OFFSET as follows: | |
6052 | ||
6053 | - If the constant should be loaded via memory, set IMM to O_absent and | |
6054 | OFFSET to the memory address. | |
6055 | ||
6056 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
6057 | set IMM to the O_constant to load into the high register and OFFSET | |
6058 | to the corresponding value for the low register. | |
6059 | ||
6060 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
6061 | ||
6062 | These constants only appear as the last operand in an instruction, | |
6063 | and every instruction that accepts them in any variant accepts them | |
6064 | in all variants. This means we don't have to worry about backing out | |
6065 | any changes if the instruction does not match. We just match | |
6066 | unconditionally and report an error if the constant is invalid. */ | |
6067 | ||
a92713e6 RS |
6068 | static bfd_boolean |
6069 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
6070 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 6071 | { |
a92713e6 | 6072 | char *p; |
89565f1b RS |
6073 | segT seg, new_seg; |
6074 | subsegT subseg; | |
6075 | const char *newname; | |
a92713e6 | 6076 | unsigned char *data; |
89565f1b RS |
6077 | |
6078 | /* Where the constant is placed is based on how the MIPS assembler | |
6079 | does things: | |
6080 | ||
6081 | length == 4 && using_gprs -- immediate value only | |
6082 | length == 8 && using_gprs -- .rdata or immediate value | |
6083 | length == 4 && !using_gprs -- .lit4 or immediate value | |
6084 | length == 8 && !using_gprs -- .lit8 or immediate value | |
6085 | ||
6086 | The .lit4 and .lit8 sections are only used if permitted by the | |
6087 | -G argument. */ | |
a92713e6 | 6088 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
6089 | { |
6090 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
6091 | return FALSE; | |
6092 | } | |
a92713e6 RS |
6093 | |
6094 | gas_assert (arg->token->u.flt.length == length); | |
6095 | data = arg->token->u.flt.data; | |
6096 | ++arg->token; | |
89565f1b RS |
6097 | |
6098 | /* Handle 32-bit constants for which an immediate value is best. */ | |
6099 | if (length == 4 | |
6100 | && (using_gprs | |
6101 | || g_switch_value < 4 | |
6102 | || (data[0] == 0 && data[1] == 0) | |
6103 | || (data[2] == 0 && data[3] == 0))) | |
6104 | { | |
6105 | imm->X_op = O_constant; | |
6106 | if (!target_big_endian) | |
6107 | imm->X_add_number = bfd_getl32 (data); | |
6108 | else | |
6109 | imm->X_add_number = bfd_getb32 (data); | |
6110 | offset->X_op = O_absent; | |
a92713e6 | 6111 | return TRUE; |
89565f1b RS |
6112 | } |
6113 | ||
6114 | /* Handle 64-bit constants for which an immediate value is best. */ | |
6115 | if (length == 8 | |
6116 | && !mips_disable_float_construction | |
351cdf24 MF |
6117 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
6118 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
6119 | Unlike most tests for 32-bit floating-point registers this check | |
6120 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
6121 | permit 64-bit moves without MXHC1. | |
6122 | Force the constant into memory otherwise. */ | |
6123 | && (using_gprs | |
6124 | || GPR_SIZE == 64 | |
6125 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
6126 | || FPR_SIZE == 32) | |
89565f1b RS |
6127 | && ((data[0] == 0 && data[1] == 0) |
6128 | || (data[2] == 0 && data[3] == 0)) | |
6129 | && ((data[4] == 0 && data[5] == 0) | |
6130 | || (data[6] == 0 && data[7] == 0))) | |
6131 | { | |
6132 | /* The value is simple enough to load with a couple of instructions. | |
6133 | If using 32-bit registers, set IMM to the high order 32 bits and | |
6134 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
6135 | 64 bit constant. */ | |
351cdf24 | 6136 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
6137 | { |
6138 | imm->X_op = O_constant; | |
6139 | offset->X_op = O_constant; | |
6140 | if (!target_big_endian) | |
6141 | { | |
6142 | imm->X_add_number = bfd_getl32 (data + 4); | |
6143 | offset->X_add_number = bfd_getl32 (data); | |
6144 | } | |
6145 | else | |
6146 | { | |
6147 | imm->X_add_number = bfd_getb32 (data); | |
6148 | offset->X_add_number = bfd_getb32 (data + 4); | |
6149 | } | |
6150 | if (offset->X_add_number == 0) | |
6151 | offset->X_op = O_absent; | |
6152 | } | |
6153 | else | |
6154 | { | |
6155 | imm->X_op = O_constant; | |
6156 | if (!target_big_endian) | |
6157 | imm->X_add_number = bfd_getl64 (data); | |
6158 | else | |
6159 | imm->X_add_number = bfd_getb64 (data); | |
6160 | offset->X_op = O_absent; | |
6161 | } | |
a92713e6 | 6162 | return TRUE; |
89565f1b RS |
6163 | } |
6164 | ||
6165 | /* Switch to the right section. */ | |
6166 | seg = now_seg; | |
6167 | subseg = now_subseg; | |
6168 | if (length == 4) | |
6169 | { | |
6170 | gas_assert (!using_gprs && g_switch_value >= 4); | |
6171 | newname = ".lit4"; | |
6172 | } | |
6173 | else | |
6174 | { | |
6175 | if (using_gprs || g_switch_value < 8) | |
6176 | newname = RDATA_SECTION_NAME; | |
6177 | else | |
6178 | newname = ".lit8"; | |
6179 | } | |
6180 | ||
6181 | new_seg = subseg_new (newname, (subsegT) 0); | |
6182 | bfd_set_section_flags (stdoutput, new_seg, | |
6183 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
6184 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
6185 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
6186 | record_alignment (new_seg, 4); | |
6187 | else | |
6188 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
6189 | if (seg == now_seg) | |
1661c76c | 6190 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
6191 | |
6192 | /* Set the argument to the current address in the section. */ | |
6193 | imm->X_op = O_absent; | |
6194 | offset->X_op = O_symbol; | |
6195 | offset->X_add_symbol = symbol_temp_new_now (); | |
6196 | offset->X_add_number = 0; | |
6197 | ||
6198 | /* Put the floating point number into the section. */ | |
6199 | p = frag_more (length); | |
6200 | memcpy (p, data, length); | |
6201 | ||
6202 | /* Switch back to the original section. */ | |
6203 | subseg_set (seg, subseg); | |
a92713e6 | 6204 | return TRUE; |
89565f1b RS |
6205 | } |
6206 | ||
14daeee3 RS |
6207 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
6208 | them. */ | |
6209 | ||
6210 | static bfd_boolean | |
6211 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
6212 | const struct mips_operand *operand, | |
6213 | bfd_boolean match_p) | |
6214 | { | |
6215 | unsigned int uval; | |
6216 | ||
6217 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
6218 | (with X being 0). */ | |
6219 | gas_assert (operand->size == 2 || operand->size == 4); | |
6220 | ||
ee5734f0 | 6221 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 6222 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 6223 | return match_p; |
14daeee3 RS |
6224 | |
6225 | uval = arg->token->u.channels; | |
6226 | if (operand->size == 2) | |
6227 | { | |
6228 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
6229 | if ((uval & -uval) != uval) | |
6230 | return FALSE; | |
6231 | uval = 4 - ffs (uval); | |
6232 | } | |
6233 | ||
6234 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6235 | return FALSE; | |
6236 | ||
6237 | ++arg->token; | |
6238 | if (!match_p) | |
6239 | insn_insert_operand (arg->insn, operand, uval); | |
6240 | return TRUE; | |
6241 | } | |
6242 | ||
33f46696 MR |
6243 | /* Try to match a token from ARG against OPERAND. Consume the token |
6244 | and return true on success, otherwise return false. */ | |
a1d78564 | 6245 | |
a92713e6 | 6246 | static bfd_boolean |
a1d78564 | 6247 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6248 | const struct mips_operand *operand) |
a1d78564 RS |
6249 | { |
6250 | switch (operand->type) | |
6251 | { | |
6252 | case OP_INT: | |
a92713e6 | 6253 | return match_int_operand (arg, operand); |
a1d78564 RS |
6254 | |
6255 | case OP_MAPPED_INT: | |
a92713e6 | 6256 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6257 | |
6258 | case OP_MSB: | |
a92713e6 | 6259 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6260 | |
6261 | case OP_REG: | |
0f35dbc4 | 6262 | case OP_OPTIONAL_REG: |
a92713e6 | 6263 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6264 | |
6265 | case OP_REG_PAIR: | |
a92713e6 | 6266 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6267 | |
6268 | case OP_PCREL: | |
a92713e6 | 6269 | return match_pcrel_operand (arg); |
a1d78564 RS |
6270 | |
6271 | case OP_PERF_REG: | |
a92713e6 | 6272 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6273 | |
6274 | case OP_ADDIUSP_INT: | |
a92713e6 | 6275 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6276 | |
6277 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6278 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6279 | |
6280 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6281 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6282 | |
6283 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6284 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6285 | |
a1d78564 | 6286 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6287 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6288 | |
6289 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6290 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6291 | |
6292 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6293 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6294 | |
6295 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6296 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6297 | |
6298 | case OP_PC: | |
a92713e6 | 6299 | return match_pc_operand (arg); |
14daeee3 | 6300 | |
25499ac7 MR |
6301 | case OP_REG28: |
6302 | return match_reg28_operand (arg); | |
6303 | ||
14daeee3 RS |
6304 | case OP_VU0_SUFFIX: |
6305 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6306 | ||
6307 | case OP_VU0_MATCH_SUFFIX: | |
6308 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6309 | |
6310 | case OP_IMM_INDEX: | |
6311 | return match_imm_index_operand (arg, operand); | |
6312 | ||
6313 | case OP_REG_INDEX: | |
6314 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6315 | |
6316 | case OP_SAME_RS_RT: | |
6317 | return match_same_rs_rt_operand (arg, operand); | |
6318 | ||
6319 | case OP_CHECK_PREV: | |
6320 | return match_check_prev_operand (arg, operand); | |
6321 | ||
6322 | case OP_NON_ZERO_REG: | |
6323 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6324 | } |
6325 | abort (); | |
6326 | } | |
6327 | ||
6328 | /* ARG is the state after successfully matching an instruction. | |
6329 | Issue any queued-up warnings. */ | |
6330 | ||
6331 | static void | |
6332 | check_completed_insn (struct mips_arg_info *arg) | |
6333 | { | |
6334 | if (arg->seen_at) | |
6335 | { | |
6336 | if (AT == ATREG) | |
1661c76c | 6337 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6338 | else |
1661c76c | 6339 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6340 | } |
6341 | } | |
a1d78564 | 6342 | |
85fcb30f RS |
6343 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6344 | ||
6345 | static bfd_boolean | |
6346 | reg_needs_delay (unsigned int reg) | |
6347 | { | |
6348 | unsigned long prev_pinfo; | |
6349 | ||
6350 | prev_pinfo = history[0].insn_mo->pinfo; | |
6351 | if (!mips_opts.noreorder | |
67dc82bc | 6352 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6353 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6354 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6355 | return TRUE; | |
6356 | ||
6357 | return FALSE; | |
6358 | } | |
6359 | ||
71400594 RS |
6360 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6361 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6362 | by VR4120 errata. */ | |
4d7206a2 | 6363 | |
71400594 RS |
6364 | static unsigned int |
6365 | classify_vr4120_insn (const char *name) | |
252b5132 | 6366 | { |
71400594 RS |
6367 | if (strncmp (name, "macc", 4) == 0) |
6368 | return FIX_VR4120_MACC; | |
6369 | if (strncmp (name, "dmacc", 5) == 0) | |
6370 | return FIX_VR4120_DMACC; | |
6371 | if (strncmp (name, "mult", 4) == 0) | |
6372 | return FIX_VR4120_MULT; | |
6373 | if (strncmp (name, "dmult", 5) == 0) | |
6374 | return FIX_VR4120_DMULT; | |
6375 | if (strstr (name, "div")) | |
6376 | return FIX_VR4120_DIV; | |
6377 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6378 | return FIX_VR4120_MTHILO; | |
6379 | return NUM_FIX_VR4120_CLASSES; | |
6380 | } | |
252b5132 | 6381 | |
a8d14a88 CM |
6382 | #define INSN_ERET 0x42000018 |
6383 | #define INSN_DERET 0x4200001f | |
6384 | #define INSN_DMULT 0x1c | |
6385 | #define INSN_DMULTU 0x1d | |
ff239038 | 6386 | |
71400594 RS |
6387 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6388 | where INSN1 is the earlier instruction. Return the worst-case value | |
6389 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6390 | |
71400594 RS |
6391 | static unsigned int |
6392 | insns_between (const struct mips_cl_insn *insn1, | |
6393 | const struct mips_cl_insn *insn2) | |
6394 | { | |
6395 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6396 | unsigned int mask; |
71400594 | 6397 | |
85fcb30f RS |
6398 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6399 | the second instruction. */ | |
71400594 RS |
6400 | pinfo1 = insn1->insn_mo->pinfo; |
6401 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6402 | |
71400594 RS |
6403 | /* For most targets, write-after-read dependencies on the HI and LO |
6404 | registers must be separated by at least two instructions. */ | |
6405 | if (!hilo_interlocks) | |
252b5132 | 6406 | { |
71400594 RS |
6407 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6408 | return 2; | |
6409 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6410 | return 2; | |
6411 | } | |
6412 | ||
6413 | /* If we're working around r7000 errata, there must be two instructions | |
6414 | between an mfhi or mflo and any instruction that uses the result. */ | |
6415 | if (mips_7000_hilo_fix | |
df58fc94 | 6416 | && !mips_opts.micromips |
71400594 | 6417 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6418 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6419 | return 2; |
6420 | ||
ff239038 CM |
6421 | /* If we're working around 24K errata, one instruction is required |
6422 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6423 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6424 | { |
6425 | if (insn1->insn_opcode == INSN_ERET | |
6426 | || insn1->insn_opcode == INSN_DERET) | |
6427 | { | |
6428 | if (insn2 == NULL | |
6429 | || insn2->insn_opcode == INSN_ERET | |
6430 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6431 | || delayed_branch_p (insn2)) |
ff239038 CM |
6432 | return 1; |
6433 | } | |
6434 | } | |
6435 | ||
a8d14a88 CM |
6436 | /* If we're working around PMC RM7000 errata, there must be three |
6437 | nops between a dmult and a load instruction. */ | |
6438 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6439 | { | |
6440 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6441 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6442 | { | |
6443 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6444 | return 3; | |
6445 | } | |
6446 | } | |
6447 | ||
71400594 RS |
6448 | /* If working around VR4120 errata, check for combinations that need |
6449 | a single intervening instruction. */ | |
df58fc94 | 6450 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6451 | { |
6452 | unsigned int class1, class2; | |
252b5132 | 6453 | |
71400594 RS |
6454 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6455 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6456 | { |
71400594 RS |
6457 | if (insn2 == NULL) |
6458 | return 1; | |
6459 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6460 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6461 | return 1; | |
252b5132 | 6462 | } |
71400594 RS |
6463 | } |
6464 | ||
df58fc94 | 6465 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6466 | { |
6467 | /* Check for GPR or coprocessor load delays. All such delays | |
6468 | are on the RT register. */ | |
6469 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6470 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6471 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6472 | { |
85fcb30f | 6473 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6474 | return 1; |
6475 | } | |
6476 | ||
6477 | /* Check for generic coprocessor hazards. | |
6478 | ||
6479 | This case is not handled very well. There is no special | |
6480 | knowledge of CP0 handling, and the coprocessors other than | |
6481 | the floating point unit are not distinguished at all. */ | |
6482 | /* Itbl support may require additional care here. FIXME! | |
6483 | Need to modify this to include knowledge about | |
6484 | user specified delays! */ | |
43885403 | 6485 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6486 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6487 | { | |
6488 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6489 | register. There must be a one instruction delay before INSN2 | |
6490 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6491 | mask = fpr_write_mask (insn1); |
6492 | if (mask != 0) | |
252b5132 | 6493 | { |
4c260379 | 6494 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6495 | return 1; |
252b5132 RH |
6496 | } |
6497 | else | |
6498 | { | |
71400594 RS |
6499 | /* Read-after-write dependencies on the control registers |
6500 | require a two-instruction gap. */ | |
6501 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6502 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6503 | return 2; | |
6504 | ||
6505 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6506 | also a coprocessor instruction, assume there must be | |
6507 | a one instruction gap. */ | |
6508 | if (pinfo2 & INSN_COP) | |
6509 | return 1; | |
252b5132 RH |
6510 | } |
6511 | } | |
6b76fefe | 6512 | |
71400594 RS |
6513 | /* Check for read-after-write dependencies on the coprocessor |
6514 | control registers in cases where INSN1 does not need a general | |
6515 | coprocessor delay. This means that INSN1 is a floating point | |
6516 | comparison instruction. */ | |
6517 | /* Itbl support may require additional care here. */ | |
6518 | else if (!cop_interlocks | |
6519 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6520 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6521 | return 1; | |
6522 | } | |
6b76fefe | 6523 | |
7361da2c AB |
6524 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6525 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6526 | and pause. */ | |
6527 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6528 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6529 | || (insn2 && delayed_branch_p (insn2)))) | |
6530 | return 1; | |
6531 | ||
71400594 RS |
6532 | return 0; |
6533 | } | |
6b76fefe | 6534 | |
7d8e00cf RS |
6535 | /* Return the number of nops that would be needed to work around the |
6536 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6537 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6538 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6539 | |
6540 | static int | |
932d1a1b | 6541 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6542 | const struct mips_cl_insn *insn) |
6543 | { | |
4c260379 RS |
6544 | int i, j; |
6545 | unsigned int mask; | |
7d8e00cf RS |
6546 | |
6547 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6548 | are not affected by the errata. */ | |
6549 | if (insn != 0 | |
6550 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6551 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6552 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6553 | return 0; | |
6554 | ||
6555 | /* Search for the first MFLO or MFHI. */ | |
6556 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6557 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6558 | { |
6559 | /* Extract the destination register. */ | |
4c260379 | 6560 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6561 | |
6562 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6563 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6564 | return 0; |
6565 | ||
6566 | /* ...or if any of the intervening instructions do. */ | |
6567 | for (j = 0; j < i; j++) | |
4c260379 | 6568 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6569 | return 0; |
6570 | ||
932d1a1b RS |
6571 | if (i >= ignore) |
6572 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6573 | } |
6574 | return 0; | |
6575 | } | |
6576 | ||
134c0c8b MR |
6577 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6578 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6579 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6580 | ||
6581 | /* Return the minimum alignment for this store instruction. */ | |
6582 | ||
6583 | static int | |
6584 | fix_24k_align_to (const struct mips_opcode *mo) | |
6585 | { | |
6586 | if (strcmp (mo->name, "sh") == 0) | |
6587 | return 2; | |
6588 | ||
6589 | if (strcmp (mo->name, "swc1") == 0 | |
6590 | || strcmp (mo->name, "swc2") == 0 | |
6591 | || strcmp (mo->name, "sw") == 0 | |
6592 | || strcmp (mo->name, "sc") == 0 | |
6593 | || strcmp (mo->name, "s.s") == 0) | |
6594 | return 4; | |
6595 | ||
6596 | if (strcmp (mo->name, "sdc1") == 0 | |
6597 | || strcmp (mo->name, "sdc2") == 0 | |
6598 | || strcmp (mo->name, "s.d") == 0) | |
6599 | return 8; | |
6600 | ||
6601 | /* sb, swl, swr */ | |
6602 | return 1; | |
6603 | } | |
6604 | ||
6605 | struct fix_24k_store_info | |
6606 | { | |
6607 | /* Immediate offset, if any, for this store instruction. */ | |
6608 | short off; | |
6609 | /* Alignment required by this store instruction. */ | |
6610 | int align_to; | |
6611 | /* True for register offsets. */ | |
6612 | int register_offset; | |
6613 | }; | |
6614 | ||
6615 | /* Comparison function used by qsort. */ | |
6616 | ||
6617 | static int | |
6618 | fix_24k_sort (const void *a, const void *b) | |
6619 | { | |
6620 | const struct fix_24k_store_info *pos1 = a; | |
6621 | const struct fix_24k_store_info *pos2 = b; | |
6622 | ||
6623 | return (pos1->off - pos2->off); | |
6624 | } | |
6625 | ||
6626 | /* INSN is a store instruction. Try to record the store information | |
6627 | in STINFO. Return false if the information isn't known. */ | |
6628 | ||
6629 | static bfd_boolean | |
6630 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6631 | const struct mips_cl_insn *insn) |
15be625d CM |
6632 | { |
6633 | /* The instruction must have a known offset. */ | |
6634 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6635 | return FALSE; | |
6636 | ||
6637 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6638 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6639 | return TRUE; | |
6640 | } | |
6641 | ||
932d1a1b RS |
6642 | /* Return the number of nops that would be needed to work around the 24k |
6643 | "lost data on stores during refill" errata if instruction INSN | |
6644 | immediately followed the 2 instructions described by HIST. | |
6645 | Ignore hazards that are contained within the first IGNORE | |
6646 | instructions of HIST. | |
6647 | ||
6648 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6649 | for the data cache refills and store data. The following describes | |
6650 | the scenario where the store data could be lost. | |
6651 | ||
6652 | * A data cache miss, due to either a load or a store, causing fill | |
6653 | data to be supplied by the memory subsystem | |
6654 | * The first three doublewords of fill data are returned and written | |
6655 | into the cache | |
6656 | * A sequence of four stores occurs in consecutive cycles around the | |
6657 | final doubleword of the fill: | |
6658 | * Store A | |
6659 | * Store B | |
6660 | * Store C | |
6661 | * Zero, One or more instructions | |
6662 | * Store D | |
6663 | ||
6664 | The four stores A-D must be to different doublewords of the line that | |
6665 | is being filled. The fourth instruction in the sequence above permits | |
6666 | the fill of the final doubleword to be transferred from the FSB into | |
6667 | the cache. In the sequence above, the stores may be either integer | |
6668 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6669 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6670 | different doublewords on the line. If the floating point unit is | |
6671 | running in 1:2 mode, it is not possible to create the sequence above | |
6672 | using only floating point store instructions. | |
15be625d CM |
6673 | |
6674 | In this case, the cache line being filled is incorrectly marked | |
6675 | invalid, thereby losing the data from any store to the line that | |
6676 | occurs between the original miss and the completion of the five | |
6677 | cycle sequence shown above. | |
6678 | ||
932d1a1b | 6679 | The workarounds are: |
15be625d | 6680 | |
932d1a1b RS |
6681 | * Run the data cache in write-through mode. |
6682 | * Insert a non-store instruction between | |
6683 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6684 | |
15be625d | 6685 | static int |
932d1a1b | 6686 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6687 | const struct mips_cl_insn *insn) |
6688 | { | |
6689 | struct fix_24k_store_info pos[3]; | |
6690 | int align, i, base_offset; | |
6691 | ||
932d1a1b RS |
6692 | if (ignore >= 2) |
6693 | return 0; | |
6694 | ||
ab9794cf RS |
6695 | /* If the previous instruction wasn't a store, there's nothing to |
6696 | worry about. */ | |
15be625d CM |
6697 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6698 | return 0; | |
6699 | ||
ab9794cf RS |
6700 | /* If the instructions after the previous one are unknown, we have |
6701 | to assume the worst. */ | |
6702 | if (!insn) | |
15be625d CM |
6703 | return 1; |
6704 | ||
ab9794cf RS |
6705 | /* Check whether we are dealing with three consecutive stores. */ |
6706 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6707 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6708 | return 0; |
6709 | ||
6710 | /* If we don't know the relationship between the store addresses, | |
6711 | assume the worst. */ | |
ab9794cf | 6712 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6713 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6714 | return 1; | |
6715 | ||
6716 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6717 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6718 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6719 | return 1; | |
6720 | ||
6721 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6722 | ||
6723 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6724 | X bytes and such that the base register + X is known to be aligned | |
6725 | to align bytes. */ | |
6726 | ||
6727 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6728 | align = 8; | |
6729 | else | |
6730 | { | |
6731 | align = pos[0].align_to; | |
6732 | base_offset = pos[0].off; | |
6733 | for (i = 1; i < 3; i++) | |
6734 | if (align < pos[i].align_to) | |
6735 | { | |
6736 | align = pos[i].align_to; | |
6737 | base_offset = pos[i].off; | |
6738 | } | |
6739 | for (i = 0; i < 3; i++) | |
6740 | pos[i].off -= base_offset; | |
6741 | } | |
6742 | ||
6743 | pos[0].off &= ~align + 1; | |
6744 | pos[1].off &= ~align + 1; | |
6745 | pos[2].off &= ~align + 1; | |
6746 | ||
6747 | /* If any two stores write to the same chunk, they also write to the | |
6748 | same doubleword. The offsets are still sorted at this point. */ | |
6749 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6750 | return 0; | |
6751 | ||
6752 | /* A range of at least 9 bytes is needed for the stores to be in | |
6753 | non-overlapping doublewords. */ | |
6754 | if (pos[2].off - pos[0].off <= 8) | |
6755 | return 0; | |
6756 | ||
6757 | if (pos[2].off - pos[1].off >= 24 | |
6758 | || pos[1].off - pos[0].off >= 24 | |
6759 | || pos[2].off - pos[0].off >= 32) | |
6760 | return 0; | |
6761 | ||
6762 | return 1; | |
6763 | } | |
6764 | ||
71400594 | 6765 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6766 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6767 | where HIST[0] is the most recent instruction. Ignore hazards |
6768 | between INSN and the first IGNORE instructions in HIST. | |
6769 | ||
6770 | If INSN is null, return the worse-case number of nops for any | |
6771 | instruction. */ | |
bdaaa2e1 | 6772 | |
71400594 | 6773 | static int |
932d1a1b | 6774 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6775 | const struct mips_cl_insn *insn) |
6776 | { | |
6777 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6778 | |
71400594 | 6779 | nops = 0; |
932d1a1b | 6780 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6781 | { |
91d6fa6a | 6782 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6783 | if (tmp_nops > nops) |
6784 | nops = tmp_nops; | |
6785 | } | |
7d8e00cf | 6786 | |
df58fc94 | 6787 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6788 | { |
932d1a1b | 6789 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6790 | if (tmp_nops > nops) |
6791 | nops = tmp_nops; | |
6792 | } | |
6793 | ||
df58fc94 | 6794 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6795 | { |
932d1a1b | 6796 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6797 | if (tmp_nops > nops) |
6798 | nops = tmp_nops; | |
6799 | } | |
6800 | ||
71400594 RS |
6801 | return nops; |
6802 | } | |
252b5132 | 6803 | |
71400594 | 6804 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6805 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6806 | would be needed after the extended sequence, ignoring hazards |
6807 | in the first IGNORE instructions. */ | |
252b5132 | 6808 | |
71400594 | 6809 | static int |
932d1a1b RS |
6810 | nops_for_sequence (int num_insns, int ignore, |
6811 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6812 | { |
6813 | va_list args; | |
6814 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6815 | struct mips_cl_insn *cursor; | |
6816 | int nops; | |
6817 | ||
91d6fa6a | 6818 | va_start (args, hist); |
71400594 | 6819 | cursor = buffer + num_insns; |
91d6fa6a | 6820 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6821 | while (cursor > buffer) |
6822 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6823 | ||
932d1a1b | 6824 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6825 | va_end (args); |
6826 | return nops; | |
6827 | } | |
252b5132 | 6828 | |
71400594 RS |
6829 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6830 | worst-case delay for the branch target. */ | |
252b5132 | 6831 | |
71400594 | 6832 | static int |
932d1a1b | 6833 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6834 | const struct mips_cl_insn *insn) |
6835 | { | |
6836 | int nops, tmp_nops; | |
60b63b72 | 6837 | |
932d1a1b | 6838 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6839 | if (delayed_branch_p (insn)) |
71400594 | 6840 | { |
932d1a1b | 6841 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6842 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6843 | if (tmp_nops > nops) |
6844 | nops = tmp_nops; | |
6845 | } | |
11625dd8 | 6846 | else if (compact_branch_p (insn)) |
71400594 | 6847 | { |
932d1a1b | 6848 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6849 | if (tmp_nops > nops) |
6850 | nops = tmp_nops; | |
6851 | } | |
6852 | return nops; | |
6853 | } | |
6854 | ||
c67a084a NC |
6855 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6856 | ||
6857 | static void | |
6858 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6859 | { | |
df58fc94 | 6860 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6861 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6862 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6863 | } | |
6864 | ||
6865 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6866 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6867 | ||
6868 | static void | |
6869 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6870 | { | |
df58fc94 | 6871 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6872 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6873 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6874 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6875 | { | |
6876 | int sreg; | |
6877 | expressionS ep; | |
6878 | ||
6879 | if (! mips_opts.at) | |
6880 | return; | |
6881 | ||
df58fc94 | 6882 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6883 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6884 | return; | |
6885 | ||
6886 | ep.X_op = O_constant; | |
6887 | ep.X_add_number = 0xcfff0000; | |
6888 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6889 | ep.X_add_number = 0xffff; | |
6890 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6891 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6892 | } | |
6893 | } | |
6894 | ||
6895 | static void | |
6896 | fix_loongson2f (struct mips_cl_insn * ip) | |
6897 | { | |
6898 | if (mips_fix_loongson2f_nop) | |
6899 | fix_loongson2f_nop (ip); | |
6900 | ||
6901 | if (mips_fix_loongson2f_jump) | |
6902 | fix_loongson2f_jump (ip); | |
6903 | } | |
6904 | ||
6f2117ba PH |
6905 | /* Fix loongson3 llsc errata: Insert sync before ll/lld. */ |
6906 | ||
6907 | static void | |
6908 | fix_loongson3_llsc (struct mips_cl_insn * ip) | |
6909 | { | |
6910 | gas_assert (!HAVE_CODE_COMPRESSION); | |
6911 | ||
6912 | /* If is an local label and the insn is not sync, | |
6913 | look forward that whether an branch between ll/sc jump to here | |
6914 | if so, insert a sync. */ | |
6915 | if (seg_info (now_seg)->label_list | |
6916 | && S_IS_LOCAL (seg_info (now_seg)->label_list->label) | |
6917 | && (strcmp (ip->insn_mo->name, "sync") != 0)) | |
6918 | { | |
6919 | const char *label_name = S_GET_NAME (seg_info (now_seg)->label_list->label); | |
6920 | unsigned long lookback = ARRAY_SIZE (history); | |
6921 | unsigned long i; | |
6922 | ||
6923 | for (i = 0; i < lookback; i++) | |
6924 | { | |
6925 | if (streq (history[i].insn_mo->name, "ll") | |
6926 | || streq (history[i].insn_mo->name, "lld")) | |
6927 | break; | |
6928 | ||
6929 | if (streq (history[i].insn_mo->name, "sc") | |
6930 | || streq (history[i].insn_mo->name, "scd")) | |
6931 | { | |
6932 | unsigned long j; | |
6933 | ||
6934 | for (j = i + 1; j < lookback; j++) | |
6935 | { | |
6936 | if (streq (history[i].insn_mo->name, "ll") | |
6937 | || streq (history[i].insn_mo->name, "lld")) | |
6938 | break; | |
6939 | ||
6940 | if (delayed_branch_p (&history[j])) | |
6941 | { | |
6942 | if (streq (history[j].target, label_name)) | |
6943 | { | |
6944 | add_fixed_insn (&sync_insn); | |
6945 | insert_into_history (0, 1, &sync_insn); | |
6946 | i = lookback; | |
6947 | break; | |
6948 | } | |
6949 | } | |
6950 | } | |
6951 | } | |
6952 | } | |
6953 | } | |
6954 | /* If we find a sc, we look forward to look for an branch insn, | |
6955 | and see whether it jump back and out of ll/sc. */ | |
6956 | else if (streq(ip->insn_mo->name, "sc") || streq(ip->insn_mo->name, "scd")) | |
6957 | { | |
6958 | unsigned long lookback = ARRAY_SIZE (history) - 1; | |
6959 | unsigned long i; | |
6960 | ||
6961 | for (i = 0; i < lookback; i++) | |
6962 | { | |
6963 | if (streq (history[i].insn_mo->name, "ll") | |
6964 | || streq (history[i].insn_mo->name, "lld")) | |
6965 | break; | |
6966 | ||
6967 | if (delayed_branch_p (&history[i])) | |
6968 | { | |
6969 | unsigned long j; | |
6970 | ||
6971 | for (j = i + 1; j < lookback; j++) | |
6972 | { | |
6973 | if (streq (history[j].insn_mo->name, "ll") | |
6974 | || streq (history[i].insn_mo->name, "lld")) | |
6975 | break; | |
6976 | } | |
6977 | ||
6978 | for (; j < lookback; j++) | |
6979 | { | |
6980 | if (history[j].label[0] != '\0' | |
6981 | && streq (history[j].label, history[i].target) | |
6982 | && strcmp (history[j+1].insn_mo->name, "sync") != 0) | |
6983 | { | |
6984 | add_fixed_insn (&sync_insn); | |
6985 | insert_into_history (++j, 1, &sync_insn); | |
6986 | } | |
6987 | } | |
6988 | } | |
6989 | } | |
6990 | } | |
6991 | ||
6992 | /* Skip if there is a sync before ll/lld. */ | |
6993 | if ((strcmp (ip->insn_mo->name, "ll") == 0 | |
6994 | || strcmp (ip->insn_mo->name, "lld") == 0) | |
6995 | && (strcmp (history[0].insn_mo->name, "sync") != 0)) | |
6996 | { | |
6997 | add_fixed_insn (&sync_insn); | |
6998 | insert_into_history (0, 1, &sync_insn); | |
6999 | } | |
7000 | } | |
7001 | ||
a4e06468 RS |
7002 | /* IP is a branch that has a delay slot, and we need to fill it |
7003 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
7004 | with the previous instruction. |
7005 | ADDRESS_EXPR is an operand of the instruction to be used with | |
7006 | RELOC_TYPE. */ | |
a4e06468 RS |
7007 | |
7008 | static bfd_boolean | |
e407c74b | 7009 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 7010 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 7011 | { |
2b0c8b40 | 7012 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 7013 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 7014 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
7015 | |
7016 | /* -O2 and above is required for this optimization. */ | |
7017 | if (mips_optimize < 2) | |
7018 | return FALSE; | |
7019 | ||
7020 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
7021 | if (mips_opts.nomove) | |
7022 | return FALSE; | |
7023 | ||
7024 | /* We can't swap if the previous instruction's position is fixed. */ | |
7025 | if (history[0].fixed_p) | |
7026 | return FALSE; | |
7027 | ||
7028 | /* If the previous previous insn was in a .set noreorder, we can't | |
7029 | swap. Actually, the MIPS assembler will swap in this situation. | |
7030 | However, gcc configured -with-gnu-as will generate code like | |
7031 | ||
7032 | .set noreorder | |
7033 | lw $4,XXX | |
7034 | .set reorder | |
7035 | INSN | |
7036 | bne $4,$0,foo | |
7037 | ||
7038 | in which we can not swap the bne and INSN. If gcc is not configured | |
7039 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
7040 | if (history[1].noreorder_p) | |
7041 | return FALSE; | |
7042 | ||
87333bb7 MR |
7043 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
7044 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
7045 | if (mips_opts.mips16 && history[0].fixp[0]) |
7046 | return FALSE; | |
7047 | ||
7048 | /* If the branch is itself the target of a branch, we can not swap. | |
7049 | We cheat on this; all we check for is whether there is a label on | |
7050 | this instruction. If there are any branches to anything other than | |
7051 | a label, users must use .set noreorder. */ | |
7052 | if (seg_info (now_seg)->label_list) | |
7053 | return FALSE; | |
7054 | ||
7055 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 7056 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
7057 | MIPS16 code, which uses variant frags for different purposes. */ |
7058 | if (!mips_opts.mips16 | |
a4e06468 RS |
7059 | && history[0].frag |
7060 | && history[0].frag->fr_type == rs_machine_dependent) | |
7061 | return FALSE; | |
7062 | ||
bcd530a7 RS |
7063 | /* We do not swap with instructions that cannot architecturally |
7064 | be placed in a branch delay slot, such as SYNC or ERET. We | |
7065 | also refrain from swapping with a trap instruction, since it | |
7066 | complicates trap handlers to have the trap instruction be in | |
7067 | a delay slot. */ | |
a4e06468 | 7068 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 7069 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
7070 | return FALSE; |
7071 | ||
7072 | /* Check for conflicts between the branch and the instructions | |
7073 | before the candidate delay slot. */ | |
7074 | if (nops_for_insn (0, history + 1, ip) > 0) | |
7075 | return FALSE; | |
7076 | ||
7077 | /* Check for conflicts between the swapped sequence and the | |
7078 | target of the branch. */ | |
7079 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
7080 | return FALSE; | |
7081 | ||
7082 | /* If the branch reads a register that the previous | |
7083 | instruction sets, we can not swap. */ | |
7084 | gpr_read = gpr_read_mask (ip); | |
7085 | prev_gpr_write = gpr_write_mask (&history[0]); | |
7086 | if (gpr_read & prev_gpr_write) | |
7087 | return FALSE; | |
7088 | ||
9d5de888 CF |
7089 | fpr_read = fpr_read_mask (ip); |
7090 | prev_fpr_write = fpr_write_mask (&history[0]); | |
7091 | if (fpr_read & prev_fpr_write) | |
7092 | return FALSE; | |
7093 | ||
a4e06468 RS |
7094 | /* If the branch writes a register that the previous |
7095 | instruction sets, we can not swap. */ | |
7096 | gpr_write = gpr_write_mask (ip); | |
7097 | if (gpr_write & prev_gpr_write) | |
7098 | return FALSE; | |
7099 | ||
7100 | /* If the branch writes a register that the previous | |
7101 | instruction reads, we can not swap. */ | |
7102 | prev_gpr_read = gpr_read_mask (&history[0]); | |
7103 | if (gpr_write & prev_gpr_read) | |
7104 | return FALSE; | |
7105 | ||
7106 | /* If one instruction sets a condition code and the | |
7107 | other one uses a condition code, we can not swap. */ | |
7108 | pinfo = ip->insn_mo->pinfo; | |
7109 | if ((pinfo & INSN_READ_COND_CODE) | |
7110 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
7111 | return FALSE; | |
7112 | if ((pinfo & INSN_WRITE_COND_CODE) | |
7113 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
7114 | return FALSE; | |
7115 | ||
7116 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 7117 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 7118 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 7119 | return FALSE; |
a4e06468 | 7120 | |
df58fc94 RS |
7121 | /* If the previous instruction has an incorrect size for a fixed |
7122 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
7123 | pinfo2 = ip->insn_mo->pinfo2; |
7124 | if (mips_opts.micromips | |
7125 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
7126 | && insn_length (history) != 2) | |
7127 | return FALSE; | |
7128 | if (mips_opts.micromips | |
7129 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
7130 | && insn_length (history) != 4) | |
7131 | return FALSE; | |
7132 | ||
33d64ca5 FN |
7133 | /* On the R5900 short loops need to be fixed by inserting a NOP in the |
7134 | branch delay slot. | |
7135 | ||
7136 | The short loop bug under certain conditions causes loops to execute | |
7137 | only once or twice. We must ensure that the assembler never | |
7138 | generates loops that satisfy all of the following conditions: | |
7139 | ||
7140 | - a loop consists of less than or equal to six instructions | |
7141 | (including the branch delay slot); | |
7142 | - a loop contains only one conditional branch instruction at the end | |
7143 | of the loop; | |
7144 | - a loop does not contain any other branch or jump instructions; | |
7145 | - a branch delay slot of the loop is not NOP (EE 2.9 or later). | |
7146 | ||
7147 | We need to do this because of a hardware bug in the R5900 chip. */ | |
27c634e0 | 7148 | if (mips_fix_r5900 |
e407c74b NC |
7149 | /* Check if instruction has a parameter, ignore "j $31". */ |
7150 | && (address_expr != NULL) | |
7151 | /* Parameter must be 16 bit. */ | |
7152 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
7153 | /* Branch to same segment. */ | |
41065f5e | 7154 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 7155 | /* Branch to same code fragment. */ |
41065f5e | 7156 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 7157 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 7158 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
7159 | /* Check if branch is really conditional. */ |
7160 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
7161 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
7162 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
7163 | { | |
7164 | int distance; | |
33d64ca5 FN |
7165 | /* Check if loop is shorter than or equal to 6 instructions |
7166 | including branch and delay slot. */ | |
41065f5e | 7167 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
7168 | if (distance <= 20) |
7169 | { | |
7170 | int i; | |
7171 | int rv; | |
7172 | ||
7173 | rv = FALSE; | |
7174 | /* When the loop includes branches or jumps, | |
7175 | it is not a short loop. */ | |
7176 | for (i = 0; i < (distance / 4); i++) | |
7177 | { | |
7178 | if ((history[i].cleared_p) | |
41065f5e | 7179 | || delayed_branch_p (&history[i])) |
e407c74b NC |
7180 | { |
7181 | rv = TRUE; | |
7182 | break; | |
7183 | } | |
7184 | } | |
535b785f | 7185 | if (!rv) |
e407c74b NC |
7186 | { |
7187 | /* Insert nop after branch to fix short loop. */ | |
7188 | return FALSE; | |
7189 | } | |
7190 | } | |
7191 | } | |
7192 | ||
a4e06468 RS |
7193 | return TRUE; |
7194 | } | |
7195 | ||
e407c74b NC |
7196 | /* Decide how we should add IP to the instruction stream. |
7197 | ADDRESS_EXPR is an operand of the instruction to be used with | |
7198 | RELOC_TYPE. */ | |
a4e06468 RS |
7199 | |
7200 | static enum append_method | |
e407c74b | 7201 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 7202 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 7203 | { |
a4e06468 RS |
7204 | /* The relaxed version of a macro sequence must be inherently |
7205 | hazard-free. */ | |
7206 | if (mips_relax.sequence == 2) | |
7207 | return APPEND_ADD; | |
7208 | ||
3b821a28 | 7209 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
7210 | if (mips_opts.noreorder) |
7211 | return APPEND_ADD; | |
7212 | ||
7213 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 7214 | if (delayed_branch_p (ip)) |
a4e06468 | 7215 | { |
e407c74b NC |
7216 | if (!branch_likely_p (ip) |
7217 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
7218 | return APPEND_SWAP; |
7219 | ||
7220 | if (mips_opts.mips16 | |
7221 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 7222 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
7223 | return APPEND_ADD_COMPACT; |
7224 | ||
7bd374a4 MR |
7225 | if (mips_opts.micromips |
7226 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
7227 | || (!forced_insn_length | |
7228 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
7229 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
7230 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
7231 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
7232 | return APPEND_ADD_COMPACT; | |
7233 | ||
a4e06468 RS |
7234 | return APPEND_ADD_WITH_NOP; |
7235 | } | |
7236 | ||
a4e06468 RS |
7237 | return APPEND_ADD; |
7238 | } | |
7239 | ||
7bd374a4 MR |
7240 | /* IP is an instruction whose opcode we have just changed, END points |
7241 | to the end of the opcode table processed. Point IP->insn_mo to the | |
7242 | new opcode's definition. */ | |
ceb94aa5 RS |
7243 | |
7244 | static void | |
7bd374a4 | 7245 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 7246 | { |
7bd374a4 | 7247 | const struct mips_opcode *mo; |
ceb94aa5 | 7248 | |
ceb94aa5 | 7249 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
7250 | if (mo->pinfo != INSN_MACRO |
7251 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
7252 | { |
7253 | ip->insn_mo = mo; | |
7254 | return; | |
7255 | } | |
7256 | abort (); | |
7257 | } | |
7258 | ||
7bd374a4 MR |
7259 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
7260 | Point IP->insn_mo to the new opcode's definition. */ | |
7261 | ||
7262 | static void | |
7263 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
7264 | { | |
7265 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
7266 | } | |
7267 | ||
7268 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
7269 | Point IP->insn_mo to the new opcode's definition. */ | |
7270 | ||
7271 | static void | |
7272 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
7273 | { | |
7274 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
7275 | } | |
7276 | ||
df58fc94 RS |
7277 | /* For microMIPS macros, we need to generate a local number label |
7278 | as the target of branches. */ | |
7279 | #define MICROMIPS_LABEL_CHAR '\037' | |
7280 | static unsigned long micromips_target_label; | |
7281 | static char micromips_target_name[32]; | |
7282 | ||
7283 | static char * | |
7284 | micromips_label_name (void) | |
7285 | { | |
7286 | char *p = micromips_target_name; | |
7287 | char symbol_name_temporary[24]; | |
7288 | unsigned long l; | |
7289 | int i; | |
7290 | ||
7291 | if (*p) | |
7292 | return p; | |
7293 | ||
7294 | i = 0; | |
7295 | l = micromips_target_label; | |
7296 | #ifdef LOCAL_LABEL_PREFIX | |
7297 | *p++ = LOCAL_LABEL_PREFIX; | |
7298 | #endif | |
7299 | *p++ = 'L'; | |
7300 | *p++ = MICROMIPS_LABEL_CHAR; | |
7301 | do | |
7302 | { | |
7303 | symbol_name_temporary[i++] = l % 10 + '0'; | |
7304 | l /= 10; | |
7305 | } | |
7306 | while (l != 0); | |
7307 | while (i > 0) | |
7308 | *p++ = symbol_name_temporary[--i]; | |
7309 | *p = '\0'; | |
7310 | ||
7311 | return micromips_target_name; | |
7312 | } | |
7313 | ||
7314 | static void | |
7315 | micromips_label_expr (expressionS *label_expr) | |
7316 | { | |
7317 | label_expr->X_op = O_symbol; | |
7318 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
7319 | label_expr->X_add_number = 0; | |
7320 | } | |
7321 | ||
7322 | static void | |
7323 | micromips_label_inc (void) | |
7324 | { | |
7325 | micromips_target_label++; | |
7326 | *micromips_target_name = '\0'; | |
7327 | } | |
7328 | ||
7329 | static void | |
7330 | micromips_add_label (void) | |
7331 | { | |
7332 | symbolS *s; | |
7333 | ||
7334 | s = colon (micromips_label_name ()); | |
7335 | micromips_label_inc (); | |
f3ded42a | 7336 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
7337 | } |
7338 | ||
7339 | /* If assembling microMIPS code, then return the microMIPS reloc | |
7340 | corresponding to the requested one if any. Otherwise return | |
7341 | the reloc unchanged. */ | |
7342 | ||
7343 | static bfd_reloc_code_real_type | |
7344 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
7345 | { | |
7346 | static const bfd_reloc_code_real_type relocs[][2] = | |
7347 | { | |
7348 | /* Keep sorted incrementally by the left-hand key. */ | |
7349 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7350 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7351 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7352 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7353 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7354 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7355 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7356 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7357 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7358 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7359 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7360 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7361 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7362 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7363 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7364 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7365 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7366 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7367 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7368 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7369 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7370 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7371 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7372 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7373 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7374 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7375 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7376 | }; | |
7377 | bfd_reloc_code_real_type r; | |
7378 | size_t i; | |
7379 | ||
7380 | if (!mips_opts.micromips) | |
7381 | return reloc; | |
7382 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7383 | { | |
7384 | r = relocs[i][0]; | |
7385 | if (r > reloc) | |
7386 | return reloc; | |
7387 | if (r == reloc) | |
7388 | return relocs[i][1]; | |
7389 | } | |
7390 | return reloc; | |
7391 | } | |
7392 | ||
b886a2ab RS |
7393 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7394 | Return true on success, storing the resolved value in RESULT. */ | |
7395 | ||
7396 | static bfd_boolean | |
7397 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7398 | offsetT *result) | |
7399 | { | |
7400 | switch (reloc) | |
7401 | { | |
7402 | case BFD_RELOC_MIPS_HIGHEST: | |
7403 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7404 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7405 | return TRUE; | |
7406 | ||
7407 | case BFD_RELOC_MIPS_HIGHER: | |
7408 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7409 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7410 | return TRUE; | |
7411 | ||
7412 | case BFD_RELOC_HI16_S: | |
41947d9e | 7413 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7414 | case BFD_RELOC_MICROMIPS_HI16_S: |
7415 | case BFD_RELOC_MIPS16_HI16_S: | |
7416 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7417 | return TRUE; | |
7418 | ||
7419 | case BFD_RELOC_HI16: | |
7420 | case BFD_RELOC_MICROMIPS_HI16: | |
7421 | case BFD_RELOC_MIPS16_HI16: | |
7422 | *result = (operand >> 16) & 0xffff; | |
7423 | return TRUE; | |
7424 | ||
7425 | case BFD_RELOC_LO16: | |
41947d9e | 7426 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7427 | case BFD_RELOC_MICROMIPS_LO16: |
7428 | case BFD_RELOC_MIPS16_LO16: | |
7429 | *result = operand & 0xffff; | |
7430 | return TRUE; | |
7431 | ||
7432 | case BFD_RELOC_UNUSED: | |
7433 | *result = operand; | |
7434 | return TRUE; | |
7435 | ||
7436 | default: | |
7437 | return FALSE; | |
7438 | } | |
7439 | } | |
7440 | ||
71400594 RS |
7441 | /* Output an instruction. IP is the instruction information. |
7442 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7443 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7444 | a macro expansion. */ | |
71400594 RS |
7445 | |
7446 | static void | |
7447 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7448 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7449 | { |
14fe068b | 7450 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7451 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7452 | enum append_method method; |
2309ddf2 | 7453 | bfd_boolean relax32; |
2b0c8b40 | 7454 | int branch_disp; |
71400594 | 7455 | |
2309ddf2 | 7456 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7457 | fix_loongson2f (ip); |
7458 | ||
6f2117ba PH |
7459 | ip->target[0] = '\0'; |
7460 | if (offset_expr.X_op == O_symbol) | |
7461 | strncpy (ip->target, S_GET_NAME (offset_expr.X_add_symbol), 15); | |
7462 | ip->label[0] = '\0'; | |
7463 | if (seg_info (now_seg)->label_list) | |
7464 | strncpy (ip->label, S_GET_NAME (seg_info (now_seg)->label_list->label), 15); | |
7465 | if (mips_fix_loongson3_llsc && !HAVE_CODE_COMPRESSION) | |
7466 | fix_loongson3_llsc (ip); | |
7467 | ||
738f4d98 | 7468 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7469 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7470 | |
df58fc94 | 7471 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7472 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7473 | |
7bd374a4 MR |
7474 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7475 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7476 | if (mips_opts.micromips |
7477 | && !expansionp | |
7bd374a4 MR |
7478 | && !(history[0].frag |
7479 | && history[0].frag->fr_type == rs_machine_dependent | |
7480 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7481 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7482 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7483 | && micromips_insn_length (ip->insn_mo) != 2) | |
7484 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7485 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7486 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7487 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7488 | |
15be625d CM |
7489 | if (address_expr == NULL) |
7490 | ip->complete_p = 1; | |
b886a2ab RS |
7491 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7492 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7493 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7494 | && address_expr->X_op == O_constant) |
7495 | { | |
15be625d CM |
7496 | switch (*reloc_type) |
7497 | { | |
15be625d | 7498 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7499 | { |
7500 | int shift; | |
7501 | ||
17c6c9d9 MR |
7502 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7503 | shift = (mips_opts.micromips | |
7504 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7505 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7506 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7507 | (unsigned long) address_expr->X_add_number); | |
7508 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7509 | & 0x3ffffff); | |
335574df | 7510 | ip->complete_p = 1; |
df58fc94 | 7511 | } |
15be625d CM |
7512 | break; |
7513 | ||
7514 | case BFD_RELOC_MIPS16_JMP: | |
7515 | if ((address_expr->X_add_number & 3) != 0) | |
7516 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7517 | (unsigned long) address_expr->X_add_number); | |
7518 | ip->insn_opcode |= | |
7519 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7520 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7521 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7522 | ip->complete_p = 1; |
15be625d CM |
7523 | break; |
7524 | ||
7525 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7526 | { |
7527 | int shift; | |
7528 | ||
7529 | shift = mips_opts.micromips ? 1 : 2; | |
7530 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7531 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7532 | (unsigned long) address_expr->X_add_number); | |
7533 | if (!mips_relax_branch) | |
7534 | { | |
7535 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7536 | & ~((1 << (shift + 16)) - 1)) | |
7537 | as_bad (_("branch address range overflow (0x%lx)"), | |
7538 | (unsigned long) address_expr->X_add_number); | |
7539 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7540 | & 0xffff); | |
7541 | } | |
df58fc94 | 7542 | } |
15be625d CM |
7543 | break; |
7544 | ||
7361da2c AB |
7545 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7546 | { | |
7547 | int shift; | |
7548 | ||
7549 | shift = 2; | |
7550 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7551 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7552 | (unsigned long) address_expr->X_add_number); | |
7553 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7554 | & ~((1 << (shift + 21)) - 1)) | |
7555 | as_bad (_("branch address range overflow (0x%lx)"), | |
7556 | (unsigned long) address_expr->X_add_number); | |
7557 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7558 | & 0x1fffff); | |
7559 | } | |
7560 | break; | |
7561 | ||
7562 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7563 | { | |
7564 | int shift; | |
7565 | ||
7566 | shift = 2; | |
7567 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7568 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7569 | (unsigned long) address_expr->X_add_number); | |
7570 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7571 | & ~((1 << (shift + 26)) - 1)) | |
7572 | as_bad (_("branch address range overflow (0x%lx)"), | |
7573 | (unsigned long) address_expr->X_add_number); | |
7574 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7575 | & 0x3ffffff); | |
7576 | } | |
7577 | break; | |
7578 | ||
15be625d | 7579 | default: |
b886a2ab RS |
7580 | { |
7581 | offsetT value; | |
7582 | ||
7583 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7584 | &value)) | |
7585 | { | |
7586 | ip->insn_opcode |= value & 0xffff; | |
7587 | ip->complete_p = 1; | |
7588 | } | |
7589 | } | |
7590 | break; | |
7591 | } | |
15be625d CM |
7592 | } |
7593 | ||
71400594 RS |
7594 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7595 | { | |
7596 | /* There are a lot of optimizations we could do that we don't. | |
7597 | In particular, we do not, in general, reorder instructions. | |
7598 | If you use gcc with optimization, it will reorder | |
7599 | instructions and generally do much more optimization then we | |
7600 | do here; repeating all that work in the assembler would only | |
7601 | benefit hand written assembly code, and does not seem worth | |
7602 | it. */ | |
7603 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7604 | ? nops_for_insn (0, history, NULL) |
7605 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7606 | if (nops > 0) |
252b5132 RH |
7607 | { |
7608 | fragS *old_frag; | |
7609 | unsigned long old_frag_offset; | |
7610 | int i; | |
252b5132 RH |
7611 | |
7612 | old_frag = frag_now; | |
7613 | old_frag_offset = frag_now_fix (); | |
7614 | ||
7615 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7616 | add_fixed_insn (NOP_INSN); |
7617 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7618 | |
7619 | if (listing) | |
7620 | { | |
7621 | listing_prev_line (); | |
7622 | /* We may be at the start of a variant frag. In case we | |
7623 | are, make sure there is enough space for the frag | |
7624 | after the frags created by listing_prev_line. The | |
7625 | argument to frag_grow here must be at least as large | |
7626 | as the argument to all other calls to frag_grow in | |
7627 | this file. We don't have to worry about being in the | |
7628 | middle of a variant frag, because the variants insert | |
7629 | all needed nop instructions themselves. */ | |
7630 | frag_grow (40); | |
7631 | } | |
7632 | ||
462427c4 | 7633 | mips_move_text_labels (); |
252b5132 RH |
7634 | |
7635 | #ifndef NO_ECOFF_DEBUGGING | |
7636 | if (ECOFF_DEBUGGING) | |
7637 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7638 | #endif | |
7639 | } | |
71400594 RS |
7640 | } |
7641 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7642 | { | |
932d1a1b RS |
7643 | int nops; |
7644 | ||
7645 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7646 | ignoring hazards generated by the first prev_nop_frag_since | |
7647 | instructions. */ | |
7648 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7649 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7650 | |
71400594 RS |
7651 | /* Enforce NOPS as a minimum. */ |
7652 | if (nops > prev_nop_frag_required) | |
7653 | prev_nop_frag_required = nops; | |
252b5132 | 7654 | |
71400594 RS |
7655 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7656 | { | |
7657 | /* Settle for the current number of nops. Update the history | |
7658 | accordingly (for the benefit of any future .set reorder code). */ | |
7659 | prev_nop_frag = NULL; | |
7660 | insert_into_history (prev_nop_frag_since, | |
7661 | prev_nop_frag_holds, NOP_INSN); | |
7662 | } | |
7663 | else | |
7664 | { | |
7665 | /* Allow this instruction to replace one of the nops that was | |
7666 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7667 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7668 | prev_nop_frag_holds--; |
7669 | prev_nop_frag_since++; | |
252b5132 RH |
7670 | } |
7671 | } | |
7672 | ||
e407c74b | 7673 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7674 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7675 | |
e410add4 RS |
7676 | dwarf2_emit_insn (0); |
7677 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7678 | so "move" the instruction address accordingly. | |
7679 | ||
7680 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7681 | entries. If this instruction is a branch that we are going to swap | |
7682 | with the previous instruction, the two instructions should be | |
7683 | treated as a unit, and the debug information for both instructions | |
7684 | should refer to the start of the branch sequence. Using the | |
7685 | current position is certainly wrong when swapping a 32-bit branch | |
7686 | and a 16-bit delay slot, since the current position would then be | |
7687 | in the middle of a branch. */ | |
7688 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7689 | |
df58fc94 RS |
7690 | relax32 = (mips_relax_branch |
7691 | /* Don't try branch relaxation within .set nomacro, or within | |
7692 | .set noat if we use $at for PIC computations. If it turns | |
7693 | out that the branch was out-of-range, we'll get an error. */ | |
7694 | && !mips_opts.warn_about_macros | |
7695 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7696 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7697 | as they have no complementing branches. */ | |
7698 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7699 | |
7700 | if (!HAVE_CODE_COMPRESSION | |
7701 | && address_expr | |
7702 | && relax32 | |
0b25d3e6 | 7703 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7704 | && delayed_branch_p (ip)) |
4a6a3df4 | 7705 | { |
895921c9 | 7706 | relaxed_branch = TRUE; |
1e915849 RS |
7707 | add_relaxed_insn (ip, (relaxed_branch_length |
7708 | (NULL, NULL, | |
11625dd8 RS |
7709 | uncond_branch_p (ip) ? -1 |
7710 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7711 | : 0)), 4, |
7712 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7713 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7714 | uncond_branch_p (ip), |
7715 | branch_likely_p (ip), | |
1e915849 RS |
7716 | pinfo & INSN_WRITE_GPR_31, |
7717 | 0), | |
7718 | address_expr->X_add_symbol, | |
7719 | address_expr->X_add_number); | |
4a6a3df4 AO |
7720 | *reloc_type = BFD_RELOC_UNUSED; |
7721 | } | |
df58fc94 RS |
7722 | else if (mips_opts.micromips |
7723 | && address_expr | |
7724 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7725 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7726 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7727 | /* Don't try branch relaxation when users specify | |
7728 | 16-bit/32-bit instructions. */ | |
7729 | && !forced_insn_length) | |
df58fc94 | 7730 | { |
7bd374a4 MR |
7731 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7732 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7733 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7734 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7735 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7736 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7737 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7738 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7739 | |
7740 | gas_assert (address_expr != NULL); | |
7741 | gas_assert (!mips_relax.sequence); | |
7742 | ||
2b0c8b40 | 7743 | relaxed_branch = TRUE; |
7bd374a4 MR |
7744 | if (nods) |
7745 | method = APPEND_ADD; | |
7746 | if (relax32) | |
7747 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7748 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7749 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7750 | mips_pic != NO_PIC, |
7bd374a4 | 7751 | uncond, compact, al, nods, |
40209cad | 7752 | relax32, 0, 0), |
df58fc94 RS |
7753 | address_expr->X_add_symbol, |
7754 | address_expr->X_add_number); | |
7755 | *reloc_type = BFD_RELOC_UNUSED; | |
7756 | } | |
7757 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7758 | { |
7fd53920 MR |
7759 | bfd_boolean require_unextended; |
7760 | bfd_boolean require_extended; | |
88a7ef16 MR |
7761 | symbolS *symbol; |
7762 | offsetT offset; | |
7763 | ||
7fd53920 MR |
7764 | if (forced_insn_length != 0) |
7765 | { | |
7766 | require_unextended = forced_insn_length == 2; | |
7767 | require_extended = forced_insn_length == 4; | |
7768 | } | |
7769 | else | |
7770 | { | |
7771 | require_unextended = (mips_opts.noautoextend | |
7772 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7773 | require_extended = 0; | |
7774 | } | |
7775 | ||
252b5132 | 7776 | /* We need to set up a variant frag. */ |
df58fc94 | 7777 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7778 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7779 | symbol created by `make_expr_symbol' may not get a necessary | |
7780 | external relocation produced. */ | |
7781 | if (address_expr->X_op == O_symbol) | |
7782 | { | |
7783 | symbol = address_expr->X_add_symbol; | |
7784 | offset = address_expr->X_add_number; | |
7785 | } | |
7786 | else | |
7787 | { | |
7788 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7789 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7790 | offset = 0; |
7791 | } | |
8507b6e7 | 7792 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7793 | RELAX_MIPS16_ENCODE |
7794 | (*reloc_type - BFD_RELOC_UNUSED, | |
25499ac7 | 7795 | mips_opts.ase & ASE_MIPS16E2, |
8507b6e7 MR |
7796 | mips_pic != NO_PIC, |
7797 | HAVE_32BIT_SYMBOLS, | |
7798 | mips_opts.warn_about_macros, | |
7fd53920 | 7799 | require_unextended, require_extended, |
11625dd8 | 7800 | delayed_branch_p (&history[0]), |
1e915849 | 7801 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7802 | symbol, offset); |
252b5132 | 7803 | } |
5c04167a | 7804 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7805 | { |
11625dd8 | 7806 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7807 | /* Make sure there is enough room to swap this instruction with |
7808 | a following jump instruction. */ | |
7809 | frag_grow (6); | |
1e915849 | 7810 | add_fixed_insn (ip); |
252b5132 RH |
7811 | } |
7812 | else | |
7813 | { | |
7814 | if (mips_opts.mips16 | |
7815 | && mips_opts.noreorder | |
11625dd8 | 7816 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7817 | as_warn (_("extended instruction in delay slot")); |
7818 | ||
4d7206a2 RS |
7819 | if (mips_relax.sequence) |
7820 | { | |
7821 | /* If we've reached the end of this frag, turn it into a variant | |
7822 | frag and record the information for the instructions we've | |
7823 | written so far. */ | |
7824 | if (frag_room () < 4) | |
7825 | relax_close_frag (); | |
df58fc94 | 7826 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7827 | } |
7828 | ||
584892a6 | 7829 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7830 | { |
7831 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7832 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7833 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7834 | mips_macro_warning.insns[0]++; | |
7835 | } | |
584892a6 | 7836 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7837 | { |
7838 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7839 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7840 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7841 | mips_macro_warning.insns[1]++; | |
7842 | } | |
584892a6 | 7843 | |
1e915849 RS |
7844 | if (mips_opts.mips16) |
7845 | { | |
7846 | ip->fixed_p = 1; | |
7847 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7848 | } | |
7849 | add_fixed_insn (ip); | |
252b5132 RH |
7850 | } |
7851 | ||
9fe77896 | 7852 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7853 | { |
df58fc94 | 7854 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7855 | reloc_howto_type *howto0; |
9fe77896 RS |
7856 | reloc_howto_type *howto; |
7857 | int i; | |
34ce925e | 7858 | |
df58fc94 RS |
7859 | /* Perform any necessary conversion to microMIPS relocations |
7860 | and find out how many relocations there actually are. */ | |
7861 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7862 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7863 | ||
9fe77896 RS |
7864 | /* In a compound relocation, it is the final (outermost) |
7865 | operator that determines the relocated field. */ | |
2309ddf2 | 7866 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7867 | if (!howto) |
7868 | abort (); | |
2309ddf2 MR |
7869 | |
7870 | if (i > 1) | |
7871 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7872 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7873 | bfd_get_reloc_size (howto), | |
7874 | address_expr, | |
2309ddf2 MR |
7875 | howto0 && howto0->pc_relative, |
7876 | final_type[0]); | |
ce8ad872 MR |
7877 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7878 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7879 | |
7880 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7881 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7882 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7883 | ||
7884 | /* These relocations can have an addend that won't fit in | |
7885 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7886 | if (GPR_SIZE == 64 |
9fe77896 RS |
7887 | && ! howto->partial_inplace |
7888 | && (reloc_type[0] == BFD_RELOC_16 | |
7889 | || reloc_type[0] == BFD_RELOC_32 | |
7890 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7891 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7892 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7893 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7894 | || reloc_type[0] == BFD_RELOC_64 | |
7895 | || reloc_type[0] == BFD_RELOC_CTOR | |
7896 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7897 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7898 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7899 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7900 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7901 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7902 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7903 | || hi16_reloc_p (reloc_type[0]) | |
7904 | || lo16_reloc_p (reloc_type[0]))) | |
7905 | ip->fixp[0]->fx_no_overflow = 1; | |
7906 | ||
ddaf2c41 MR |
7907 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7908 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7909 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7910 | ip->fixp[0]->fx_no_overflow = 1; | |
7911 | ||
9fe77896 RS |
7912 | if (mips_relax.sequence) |
7913 | { | |
7914 | if (mips_relax.first_fixup == 0) | |
7915 | mips_relax.first_fixup = ip->fixp[0]; | |
7916 | } | |
7917 | else if (reloc_needs_lo_p (*reloc_type)) | |
7918 | { | |
7919 | struct mips_hi_fixup *hi_fixup; | |
7920 | ||
7921 | /* Reuse the last entry if it already has a matching %lo. */ | |
7922 | hi_fixup = mips_hi_fixup_list; | |
7923 | if (hi_fixup == 0 | |
7924 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7925 | { |
325801bd | 7926 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7927 | hi_fixup->next = mips_hi_fixup_list; |
7928 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7929 | } |
9fe77896 RS |
7930 | hi_fixup->fixp = ip->fixp[0]; |
7931 | hi_fixup->seg = now_seg; | |
7932 | } | |
252b5132 | 7933 | |
9fe77896 RS |
7934 | /* Add fixups for the second and third relocations, if given. |
7935 | Note that the ABI allows the second relocation to be | |
7936 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7937 | moment we only use RSS_UNDEF, but we could add support | |
7938 | for the others if it ever becomes necessary. */ | |
7939 | for (i = 1; i < 3; i++) | |
7940 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7941 | { | |
7942 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7943 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7944 | FALSE, final_type[i]); |
f6688943 | 7945 | |
9fe77896 RS |
7946 | /* Use fx_tcbit to mark compound relocs. */ |
7947 | ip->fixp[0]->fx_tcbit = 1; | |
7948 | ip->fixp[i]->fx_tcbit = 1; | |
7949 | } | |
252b5132 | 7950 | } |
252b5132 RH |
7951 | |
7952 | /* Update the register mask information. */ | |
4c260379 RS |
7953 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7954 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7955 | |
a4e06468 | 7956 | switch (method) |
252b5132 | 7957 | { |
a4e06468 RS |
7958 | case APPEND_ADD: |
7959 | insert_into_history (0, 1, ip); | |
7960 | break; | |
7961 | ||
7962 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7963 | { |
7964 | struct mips_cl_insn *nop; | |
7965 | ||
7966 | insert_into_history (0, 1, ip); | |
7967 | nop = get_delay_slot_nop (ip); | |
7968 | add_fixed_insn (nop); | |
7969 | insert_into_history (0, 1, nop); | |
7970 | if (mips_relax.sequence) | |
7971 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7972 | } | |
a4e06468 RS |
7973 | break; |
7974 | ||
7975 | case APPEND_ADD_COMPACT: | |
7976 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
7977 | if (mips_opts.mips16) |
7978 | { | |
7979 | ip->insn_opcode |= 0x0080; | |
7980 | find_altered_mips16_opcode (ip); | |
7981 | } | |
7982 | /* Convert microMIPS instructions. */ | |
7983 | else if (mips_opts.micromips) | |
7984 | { | |
7985 | /* jr16->jrc */ | |
7986 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
7987 | ip->insn_opcode |= 0x0020; | |
7988 | /* b16->bc */ | |
7989 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
7990 | ip->insn_opcode = 0x40e00000; | |
7991 | /* beqz16->beqzc, bnez16->bnezc */ | |
7992 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
7993 | { | |
7994 | unsigned long regno; | |
7995 | ||
7996 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
7997 | regno &= MICROMIPSOP_MASK_MD; | |
7998 | regno = micromips_to_32_reg_d_map[regno]; | |
7999 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
8000 | | (regno << MICROMIPSOP_SH_RS) | |
8001 | | 0x40a00000) ^ 0x00400000; | |
8002 | } | |
8003 | /* beqz->beqzc, bnez->bnezc */ | |
8004 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
8005 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
8006 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
8007 | | 0x40a00000) ^ 0x00400000; | |
8008 | /* beq $0->beqzc, bne $0->bnezc */ | |
8009 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
8010 | ip->insn_opcode = (((ip->insn_opcode >> | |
8011 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
8012 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
8013 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
8014 | | 0x40a00000) ^ 0x00400000; | |
8015 | else | |
8016 | abort (); | |
8017 | find_altered_micromips_opcode (ip); | |
8018 | } | |
8019 | else | |
8020 | abort (); | |
a4e06468 RS |
8021 | install_insn (ip); |
8022 | insert_into_history (0, 1, ip); | |
8023 | break; | |
8024 | ||
8025 | case APPEND_SWAP: | |
8026 | { | |
8027 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
8028 | |
8029 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
8030 | { |
8031 | /* Add the delay slot instruction to the end of the | |
8032 | current frag and shrink the fixed part of the | |
8033 | original frag. If the branch occupies the tail of | |
8034 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 8035 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 8036 | if (delay.frag == ip->frag) |
2b0c8b40 | 8037 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
8038 | add_fixed_insn (&delay); |
8039 | } | |
8040 | else | |
8041 | { | |
5e35670b MR |
8042 | /* If this is not a relaxed branch and we are in the |
8043 | same frag, then just swap the instructions. */ | |
8044 | move_insn (ip, delay.frag, delay.where); | |
8045 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
8046 | } |
8047 | history[0] = *ip; | |
8048 | delay.fixed_p = 1; | |
8049 | insert_into_history (0, 1, &delay); | |
8050 | } | |
8051 | break; | |
252b5132 RH |
8052 | } |
8053 | ||
13408f1e | 8054 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
8055 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
8056 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
8057 | { |
8058 | unsigned int i; | |
8059 | ||
79850f26 | 8060 | mips_no_prev_insn (); |
13408f1e | 8061 | |
e407c74b | 8062 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 8063 | history[i].cleared_p = 1; |
e407c74b NC |
8064 | } |
8065 | ||
df58fc94 RS |
8066 | /* We need to emit a label at the end of branch-likely macros. */ |
8067 | if (emit_branch_likely_macro) | |
8068 | { | |
8069 | emit_branch_likely_macro = FALSE; | |
8070 | micromips_add_label (); | |
8071 | } | |
8072 | ||
252b5132 RH |
8073 | /* We just output an insn, so the next one doesn't have a label. */ |
8074 | mips_clear_insn_labels (); | |
252b5132 RH |
8075 | } |
8076 | ||
e407c74b NC |
8077 | /* Forget that there was any previous instruction or label. |
8078 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
8079 | |
8080 | static void | |
7d10b47d | 8081 | mips_no_prev_insn (void) |
252b5132 | 8082 | { |
7d10b47d RS |
8083 | prev_nop_frag = NULL; |
8084 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
8085 | mips_clear_insn_labels (); |
8086 | } | |
8087 | ||
7d10b47d RS |
8088 | /* This function must be called before we emit something other than |
8089 | instructions. It is like mips_no_prev_insn except that it inserts | |
8090 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 8091 | |
7d10b47d RS |
8092 | void |
8093 | mips_emit_delays (void) | |
252b5132 RH |
8094 | { |
8095 | if (! mips_opts.noreorder) | |
8096 | { | |
932d1a1b | 8097 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
8098 | if (nops > 0) |
8099 | { | |
7d10b47d RS |
8100 | while (nops-- > 0) |
8101 | add_fixed_insn (NOP_INSN); | |
462427c4 | 8102 | mips_move_text_labels (); |
7d10b47d RS |
8103 | } |
8104 | } | |
8105 | mips_no_prev_insn (); | |
8106 | } | |
8107 | ||
8108 | /* Start a (possibly nested) noreorder block. */ | |
8109 | ||
8110 | static void | |
8111 | start_noreorder (void) | |
8112 | { | |
8113 | if (mips_opts.noreorder == 0) | |
8114 | { | |
8115 | unsigned int i; | |
8116 | int nops; | |
8117 | ||
8118 | /* None of the instructions before the .set noreorder can be moved. */ | |
8119 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
8120 | history[i].fixed_p = 1; | |
8121 | ||
8122 | /* Insert any nops that might be needed between the .set noreorder | |
8123 | block and the previous instructions. We will later remove any | |
8124 | nops that turn out not to be needed. */ | |
932d1a1b | 8125 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
8126 | if (nops > 0) |
8127 | { | |
8128 | if (mips_optimize != 0) | |
252b5132 RH |
8129 | { |
8130 | /* Record the frag which holds the nop instructions, so | |
8131 | that we can remove them if we don't need them. */ | |
df58fc94 | 8132 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
8133 | prev_nop_frag = frag_now; |
8134 | prev_nop_frag_holds = nops; | |
8135 | prev_nop_frag_required = 0; | |
8136 | prev_nop_frag_since = 0; | |
8137 | } | |
8138 | ||
8139 | for (; nops > 0; --nops) | |
1e915849 | 8140 | add_fixed_insn (NOP_INSN); |
252b5132 | 8141 | |
7d10b47d RS |
8142 | /* Move on to a new frag, so that it is safe to simply |
8143 | decrease the size of prev_nop_frag. */ | |
8144 | frag_wane (frag_now); | |
8145 | frag_new (0); | |
462427c4 | 8146 | mips_move_text_labels (); |
252b5132 | 8147 | } |
df58fc94 | 8148 | mips_mark_labels (); |
7d10b47d | 8149 | mips_clear_insn_labels (); |
252b5132 | 8150 | } |
7d10b47d RS |
8151 | mips_opts.noreorder++; |
8152 | mips_any_noreorder = 1; | |
8153 | } | |
252b5132 | 8154 | |
7d10b47d | 8155 | /* End a nested noreorder block. */ |
252b5132 | 8156 | |
7d10b47d RS |
8157 | static void |
8158 | end_noreorder (void) | |
8159 | { | |
8160 | mips_opts.noreorder--; | |
8161 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
8162 | { | |
8163 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
8164 | handling nop insertion the .set reorder way. */ | |
8165 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 8166 | * NOP_INSN_SIZE); |
7d10b47d RS |
8167 | insert_into_history (prev_nop_frag_since, |
8168 | prev_nop_frag_required, NOP_INSN); | |
8169 | prev_nop_frag = NULL; | |
8170 | } | |
252b5132 RH |
8171 | } |
8172 | ||
97d87491 RS |
8173 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
8174 | higher bits unset. */ | |
8175 | ||
8176 | static void | |
8177 | normalize_constant_expr (expressionS *ex) | |
8178 | { | |
8179 | if (ex->X_op == O_constant | |
8180 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8181 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8182 | - 0x80000000); | |
8183 | } | |
8184 | ||
8185 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
8186 | all higher bits unset. */ | |
8187 | ||
8188 | static void | |
8189 | normalize_address_expr (expressionS *ex) | |
8190 | { | |
8191 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
8192 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
8193 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8194 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8195 | - 0x80000000); | |
8196 | } | |
8197 | ||
8198 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
8199 | Return true if the match was successful. | |
8200 | ||
8201 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
8202 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
8203 | there are more alternatives after OPCODE and SOFT_MATCH is | |
8204 | as for mips_arg_info. */ | |
8205 | ||
8206 | static bfd_boolean | |
8207 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
8208 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 8209 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
8210 | { |
8211 | const char *args; | |
8212 | struct mips_arg_info arg; | |
8213 | const struct mips_operand *operand; | |
8214 | char c; | |
8215 | ||
8216 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8217 | offset_expr.X_op = O_absent; |
8218 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8219 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8220 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8221 | ||
8222 | create_insn (insn, opcode); | |
60f20e8b RS |
8223 | /* When no opcode suffix is specified, assume ".xyzw". */ |
8224 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
8225 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
8226 | else | |
8227 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
8228 | memset (&arg, 0, sizeof (arg)); |
8229 | arg.insn = insn; | |
8230 | arg.token = tokens; | |
8231 | arg.argnum = 1; | |
8232 | arg.last_regno = ILLEGAL_REG; | |
8233 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 8234 | arg.lax_match = lax_match; |
97d87491 RS |
8235 | for (args = opcode->args;; ++args) |
8236 | { | |
8237 | if (arg.token->type == OT_END) | |
8238 | { | |
8239 | /* Handle unary instructions in which only one operand is given. | |
8240 | The source is then the same as the destination. */ | |
8241 | if (arg.opnum == 1 && *args == ',') | |
8242 | { | |
8243 | operand = (mips_opts.micromips | |
8244 | ? decode_micromips_operand (args + 1) | |
8245 | : decode_mips_operand (args + 1)); | |
8246 | if (operand && mips_optional_operand_p (operand)) | |
8247 | { | |
8248 | arg.token = tokens; | |
8249 | arg.argnum = 1; | |
8250 | continue; | |
8251 | } | |
8252 | } | |
8253 | ||
8254 | /* Treat elided base registers as $0. */ | |
8255 | if (strcmp (args, "(b)") == 0) | |
8256 | args += 3; | |
8257 | ||
8258 | if (args[0] == '+') | |
8259 | switch (args[1]) | |
8260 | { | |
8261 | case 'K': | |
8262 | case 'N': | |
8263 | /* The register suffix is optional. */ | |
8264 | args += 2; | |
8265 | break; | |
8266 | } | |
8267 | ||
8268 | /* Fail the match if there were too few operands. */ | |
8269 | if (*args) | |
8270 | return FALSE; | |
8271 | ||
8272 | /* Successful match. */ | |
60f20e8b RS |
8273 | if (!complete_p) |
8274 | return TRUE; | |
e3de51ce | 8275 | clear_insn_error (); |
97d87491 RS |
8276 | if (arg.dest_regno == arg.last_regno |
8277 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
8278 | { | |
8279 | if (arg.opnum == 2) | |
e3de51ce | 8280 | set_insn_error |
1661c76c | 8281 | (0, _("source and destination must be different")); |
97d87491 | 8282 | else if (arg.last_regno == 31) |
e3de51ce | 8283 | set_insn_error |
1661c76c | 8284 | (0, _("a destination register must be supplied")); |
97d87491 | 8285 | } |
173d3447 CF |
8286 | else if (arg.last_regno == 31 |
8287 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
8288 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
8289 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
8290 | check_completed_insn (&arg); |
8291 | return TRUE; | |
8292 | } | |
8293 | ||
8294 | /* Fail the match if the line has too many operands. */ | |
8295 | if (*args == 0) | |
8296 | return FALSE; | |
8297 | ||
8298 | /* Handle characters that need to match exactly. */ | |
8299 | if (*args == '(' || *args == ')' || *args == ',') | |
8300 | { | |
8301 | if (match_char (&arg, *args)) | |
8302 | continue; | |
8303 | return FALSE; | |
8304 | } | |
8305 | if (*args == '#') | |
8306 | { | |
8307 | ++args; | |
8308 | if (arg.token->type == OT_DOUBLE_CHAR | |
8309 | && arg.token->u.ch == *args) | |
8310 | { | |
8311 | ++arg.token; | |
8312 | continue; | |
8313 | } | |
8314 | return FALSE; | |
8315 | } | |
8316 | ||
8317 | /* Handle special macro operands. Work out the properties of | |
8318 | other operands. */ | |
8319 | arg.opnum += 1; | |
97d87491 RS |
8320 | switch (*args) |
8321 | { | |
7361da2c AB |
8322 | case '-': |
8323 | switch (args[1]) | |
8324 | { | |
8325 | case 'A': | |
8326 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
8327 | break; | |
8328 | ||
8329 | case 'B': | |
8330 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
8331 | break; | |
8332 | } | |
8333 | break; | |
8334 | ||
97d87491 RS |
8335 | case '+': |
8336 | switch (args[1]) | |
8337 | { | |
97d87491 RS |
8338 | case 'i': |
8339 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8340 | break; | |
7361da2c AB |
8341 | |
8342 | case '\'': | |
8343 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
8344 | break; | |
8345 | ||
8346 | case '\"': | |
8347 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
8348 | break; | |
97d87491 RS |
8349 | } |
8350 | break; | |
8351 | ||
97d87491 | 8352 | case 'I': |
1a00e612 RS |
8353 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8354 | return FALSE; | |
8355 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8356 | if (GPR_SIZE == 32) |
97d87491 RS |
8357 | normalize_constant_expr (&imm_expr); |
8358 | continue; | |
8359 | ||
8360 | case 'A': | |
8361 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8362 | { | |
8363 | /* Assume that the offset has been elided and that what | |
8364 | we saw was a base register. The match will fail later | |
8365 | if that assumption turns out to be wrong. */ | |
8366 | offset_expr.X_op = O_constant; | |
8367 | offset_expr.X_add_number = 0; | |
8368 | } | |
97d87491 | 8369 | else |
1a00e612 RS |
8370 | { |
8371 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8372 | return FALSE; | |
8373 | normalize_address_expr (&offset_expr); | |
8374 | } | |
97d87491 RS |
8375 | continue; |
8376 | ||
8377 | case 'F': | |
8378 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8379 | 8, TRUE)) | |
1a00e612 | 8380 | return FALSE; |
97d87491 RS |
8381 | continue; |
8382 | ||
8383 | case 'L': | |
8384 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8385 | 8, FALSE)) | |
1a00e612 | 8386 | return FALSE; |
97d87491 RS |
8387 | continue; |
8388 | ||
8389 | case 'f': | |
8390 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8391 | 4, TRUE)) | |
1a00e612 | 8392 | return FALSE; |
97d87491 RS |
8393 | continue; |
8394 | ||
8395 | case 'l': | |
8396 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8397 | 4, FALSE)) | |
1a00e612 | 8398 | return FALSE; |
97d87491 RS |
8399 | continue; |
8400 | ||
97d87491 RS |
8401 | case 'p': |
8402 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8403 | break; | |
8404 | ||
8405 | case 'a': | |
8406 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8407 | break; | |
8408 | ||
8409 | case 'm': | |
8410 | gas_assert (mips_opts.micromips); | |
8411 | c = args[1]; | |
8412 | switch (c) | |
8413 | { | |
8414 | case 'D': | |
8415 | case 'E': | |
8416 | if (!forced_insn_length) | |
8417 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8418 | else if (c == 'D') | |
8419 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8420 | else | |
8421 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8422 | break; | |
8423 | } | |
8424 | break; | |
8425 | } | |
8426 | ||
8427 | operand = (mips_opts.micromips | |
8428 | ? decode_micromips_operand (args) | |
8429 | : decode_mips_operand (args)); | |
8430 | if (!operand) | |
8431 | abort (); | |
8432 | ||
8433 | /* Skip prefixes. */ | |
7361da2c | 8434 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8435 | args++; |
8436 | ||
8437 | if (mips_optional_operand_p (operand) | |
8438 | && args[1] == ',' | |
8439 | && (arg.token[0].type != OT_REG | |
8440 | || arg.token[1].type == OT_END)) | |
8441 | { | |
8442 | /* Assume that the register has been elided and is the | |
8443 | same as the first operand. */ | |
8444 | arg.token = tokens; | |
8445 | arg.argnum = 1; | |
8446 | } | |
8447 | ||
8448 | if (!match_operand (&arg, operand)) | |
8449 | return FALSE; | |
8450 | } | |
8451 | } | |
8452 | ||
8453 | /* Like match_insn, but for MIPS16. */ | |
8454 | ||
8455 | static bfd_boolean | |
8456 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8457 | struct mips_operand_token *tokens) |
97d87491 RS |
8458 | { |
8459 | const char *args; | |
8460 | const struct mips_operand *operand; | |
8461 | const struct mips_operand *ext_operand; | |
82d808ed | 8462 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8463 | int required_insn_length; |
97d87491 RS |
8464 | struct mips_arg_info arg; |
8465 | int relax_char; | |
8466 | ||
7fd53920 MR |
8467 | if (forced_insn_length) |
8468 | required_insn_length = forced_insn_length; | |
8469 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8470 | required_insn_length = 2; | |
8471 | else | |
8472 | required_insn_length = 0; | |
8473 | ||
97d87491 RS |
8474 | create_insn (insn, opcode); |
8475 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8476 | offset_expr.X_op = O_absent; |
8477 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8478 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8479 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8480 | relax_char = 0; | |
8481 | ||
8482 | memset (&arg, 0, sizeof (arg)); | |
8483 | arg.insn = insn; | |
8484 | arg.token = tokens; | |
8485 | arg.argnum = 1; | |
8486 | arg.last_regno = ILLEGAL_REG; | |
8487 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8488 | relax_char = 0; |
8489 | for (args = opcode->args;; ++args) | |
8490 | { | |
8491 | int c; | |
8492 | ||
8493 | if (arg.token->type == OT_END) | |
8494 | { | |
8495 | offsetT value; | |
8496 | ||
8497 | /* Handle unary instructions in which only one operand is given. | |
8498 | The source is then the same as the destination. */ | |
8499 | if (arg.opnum == 1 && *args == ',') | |
8500 | { | |
8501 | operand = decode_mips16_operand (args[1], FALSE); | |
8502 | if (operand && mips_optional_operand_p (operand)) | |
8503 | { | |
8504 | arg.token = tokens; | |
8505 | arg.argnum = 1; | |
8506 | continue; | |
8507 | } | |
8508 | } | |
8509 | ||
8510 | /* Fail the match if there were too few operands. */ | |
8511 | if (*args) | |
8512 | return FALSE; | |
8513 | ||
8514 | /* Successful match. Stuff the immediate value in now, if | |
8515 | we can. */ | |
e3de51ce | 8516 | clear_insn_error (); |
97d87491 RS |
8517 | if (opcode->pinfo == INSN_MACRO) |
8518 | { | |
8519 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8520 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8521 | } | |
8522 | else if (relax_char | |
8523 | && offset_expr.X_op == O_constant | |
82d808ed | 8524 | && !pcrel |
97d87491 RS |
8525 | && calculate_reloc (*offset_reloc, |
8526 | offset_expr.X_add_number, | |
8527 | &value)) | |
8528 | { | |
8529 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8530 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8531 | offset_expr.X_op = O_absent; |
8532 | *offset_reloc = BFD_RELOC_UNUSED; | |
8533 | } | |
8534 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8535 | { | |
7fd53920 | 8536 | if (required_insn_length == 2) |
e3de51ce | 8537 | set_insn_error (0, _("invalid unextended operand value")); |
25499ac7 | 8538 | else if (!mips_opcode_32bit_p (opcode)) |
1da43acc MR |
8539 | { |
8540 | forced_insn_length = 4; | |
8541 | insn->insn_opcode |= MIPS16_EXTEND; | |
8542 | } | |
97d87491 RS |
8543 | } |
8544 | else if (relax_char) | |
8545 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8546 | ||
8547 | check_completed_insn (&arg); | |
8548 | return TRUE; | |
8549 | } | |
8550 | ||
8551 | /* Fail the match if the line has too many operands. */ | |
8552 | if (*args == 0) | |
8553 | return FALSE; | |
8554 | ||
8555 | /* Handle characters that need to match exactly. */ | |
8556 | if (*args == '(' || *args == ')' || *args == ',') | |
8557 | { | |
8558 | if (match_char (&arg, *args)) | |
8559 | continue; | |
8560 | return FALSE; | |
8561 | } | |
8562 | ||
8563 | arg.opnum += 1; | |
8564 | c = *args; | |
8565 | switch (c) | |
8566 | { | |
8567 | case 'p': | |
8568 | case 'q': | |
8569 | case 'A': | |
8570 | case 'B': | |
8571 | case 'E': | |
25499ac7 MR |
8572 | case 'V': |
8573 | case 'u': | |
97d87491 RS |
8574 | relax_char = c; |
8575 | break; | |
8576 | ||
8577 | case 'I': | |
1a00e612 RS |
8578 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8579 | return FALSE; | |
8580 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8581 | if (GPR_SIZE == 32) |
97d87491 RS |
8582 | normalize_constant_expr (&imm_expr); |
8583 | continue; | |
8584 | ||
8585 | case 'a': | |
8586 | case 'i': | |
8587 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8588 | break; |
8589 | } | |
8590 | ||
7fd53920 | 8591 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8592 | if (!operand) |
8593 | abort (); | |
8594 | ||
82d808ed MR |
8595 | if (operand->type == OP_PCREL) |
8596 | pcrel = TRUE; | |
8597 | else | |
97d87491 RS |
8598 | { |
8599 | ext_operand = decode_mips16_operand (c, TRUE); | |
8600 | if (operand != ext_operand) | |
8601 | { | |
8602 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8603 | { | |
8604 | offset_expr.X_op = O_constant; | |
8605 | offset_expr.X_add_number = 0; | |
8606 | relax_char = c; | |
8607 | continue; | |
8608 | } | |
8609 | ||
1a7bf198 | 8610 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
97d87491 RS |
8611 | return FALSE; |
8612 | ||
8613 | /* '8' is used for SLTI(U) and has traditionally not | |
8614 | been allowed to take relocation operators. */ | |
8615 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8616 | && (ext_operand->size != 16 || c == '8')) | |
e295202f MR |
8617 | { |
8618 | match_not_constant (&arg); | |
8619 | return FALSE; | |
8620 | } | |
97d87491 | 8621 | |
c96425c5 MR |
8622 | if (offset_expr.X_op == O_big) |
8623 | { | |
8624 | match_out_of_range (&arg); | |
8625 | return FALSE; | |
8626 | } | |
8627 | ||
97d87491 RS |
8628 | relax_char = c; |
8629 | continue; | |
8630 | } | |
8631 | } | |
8632 | ||
8633 | if (mips_optional_operand_p (operand) | |
8634 | && args[1] == ',' | |
8635 | && (arg.token[0].type != OT_REG | |
8636 | || arg.token[1].type == OT_END)) | |
8637 | { | |
8638 | /* Assume that the register has been elided and is the | |
8639 | same as the first operand. */ | |
8640 | arg.token = tokens; | |
8641 | arg.argnum = 1; | |
8642 | } | |
8643 | ||
8644 | if (!match_operand (&arg, operand)) | |
8645 | return FALSE; | |
8646 | } | |
8647 | } | |
8648 | ||
60f20e8b RS |
8649 | /* Record that the current instruction is invalid for the current ISA. */ |
8650 | ||
8651 | static void | |
8652 | match_invalid_for_isa (void) | |
8653 | { | |
8654 | set_insn_error_ss | |
1661c76c | 8655 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8656 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8657 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8658 | } | |
8659 | ||
8660 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8661 | Return true if a definite match or failure was found, storing any match | |
8662 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8663 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8664 | tried and failed to match under normal conditions and now want to try a | |
8665 | more relaxed match. */ | |
8666 | ||
8667 | static bfd_boolean | |
8668 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8669 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8670 | int opcode_extra, bfd_boolean lax_match) | |
8671 | { | |
8672 | const struct mips_opcode *opcode; | |
8673 | const struct mips_opcode *invalid_delay_slot; | |
8674 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8675 | ||
8676 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8677 | current ISA or forced_length. */ | |
8678 | invalid_delay_slot = 0; | |
8679 | seen_valid_for_isa = FALSE; | |
8680 | seen_valid_for_size = FALSE; | |
8681 | opcode = first; | |
8682 | do | |
8683 | { | |
8684 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8685 | if (is_opcode_valid (opcode)) | |
8686 | { | |
8687 | seen_valid_for_isa = TRUE; | |
8688 | if (is_size_valid (opcode)) | |
8689 | { | |
8690 | bfd_boolean delay_slot_ok; | |
8691 | ||
8692 | seen_valid_for_size = TRUE; | |
8693 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8694 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8695 | lax_match, delay_slot_ok)) | |
8696 | { | |
8697 | if (!delay_slot_ok) | |
8698 | { | |
8699 | if (!invalid_delay_slot) | |
8700 | invalid_delay_slot = opcode; | |
8701 | } | |
8702 | else | |
8703 | return TRUE; | |
8704 | } | |
8705 | } | |
8706 | } | |
8707 | ++opcode; | |
8708 | } | |
8709 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8710 | ||
8711 | /* If the only matches we found had the wrong length for the delay slot, | |
8712 | pick the first such match. We'll issue an appropriate warning later. */ | |
8713 | if (invalid_delay_slot) | |
8714 | { | |
8715 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8716 | lax_match, TRUE)) | |
8717 | return TRUE; | |
8718 | abort (); | |
8719 | } | |
8720 | ||
8721 | /* Handle the case where we didn't try to match an instruction because | |
8722 | all the alternatives were incompatible with the current ISA. */ | |
8723 | if (!seen_valid_for_isa) | |
8724 | { | |
8725 | match_invalid_for_isa (); | |
8726 | return TRUE; | |
8727 | } | |
8728 | ||
8729 | /* Handle the case where we didn't try to match an instruction because | |
8730 | all the alternatives were of the wrong size. */ | |
8731 | if (!seen_valid_for_size) | |
8732 | { | |
8733 | if (mips_opts.insn32) | |
1661c76c | 8734 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8735 | else |
8736 | set_insn_error_i | |
1661c76c | 8737 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8738 | 8 * forced_insn_length); |
8739 | return TRUE; | |
8740 | } | |
8741 | ||
8742 | return FALSE; | |
8743 | } | |
8744 | ||
8745 | /* Like match_insns, but for MIPS16. */ | |
8746 | ||
8747 | static bfd_boolean | |
8748 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8749 | struct mips_operand_token *tokens) | |
8750 | { | |
8751 | const struct mips_opcode *opcode; | |
8752 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8753 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8754 | |
8755 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8756 | current ISA. There are no separate entries for extended forms so | |
8757 | we deal with forced_length later. */ | |
8758 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8759 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8760 | opcode = first; |
8761 | do | |
8762 | { | |
8763 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8764 | if (is_opcode_valid_16 (opcode)) | |
8765 | { | |
8766 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8767 | if (is_size_valid_16 (opcode)) |
8768 | { | |
8769 | seen_valid_for_size = TRUE; | |
8770 | if (match_mips16_insn (insn, opcode, tokens)) | |
8771 | return TRUE; | |
8772 | } | |
60f20e8b RS |
8773 | } |
8774 | ++opcode; | |
8775 | } | |
8776 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8777 | && strcmp (opcode->name, first->name) == 0); | |
8778 | ||
8779 | /* Handle the case where we didn't try to match an instruction because | |
8780 | all the alternatives were incompatible with the current ISA. */ | |
8781 | if (!seen_valid_for_isa) | |
8782 | { | |
8783 | match_invalid_for_isa (); | |
8784 | return TRUE; | |
8785 | } | |
8786 | ||
7fd53920 MR |
8787 | /* Handle the case where we didn't try to match an instruction because |
8788 | all the alternatives were of the wrong size. */ | |
8789 | if (!seen_valid_for_size) | |
8790 | { | |
8791 | if (forced_insn_length == 2) | |
8792 | set_insn_error | |
8793 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8794 | else | |
8795 | set_insn_error | |
8796 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8797 | return TRUE; | |
8798 | } | |
8799 | ||
60f20e8b RS |
8800 | return FALSE; |
8801 | } | |
8802 | ||
584892a6 RS |
8803 | /* Set up global variables for the start of a new macro. */ |
8804 | ||
8805 | static void | |
8806 | macro_start (void) | |
8807 | { | |
8808 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8809 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8810 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8811 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8812 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8813 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8814 | if (history[0].frag |
8815 | && history[0].frag->fr_type == rs_machine_dependent | |
8816 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8817 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8818 | mips_macro_warning.delay_slot_length = 0; | |
8819 | else | |
8820 | switch (history[0].insn_mo->pinfo2 | |
8821 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8822 | { | |
8823 | case INSN2_BRANCH_DELAY_32BIT: | |
8824 | mips_macro_warning.delay_slot_length = 4; | |
8825 | break; | |
8826 | case INSN2_BRANCH_DELAY_16BIT: | |
8827 | mips_macro_warning.delay_slot_length = 2; | |
8828 | break; | |
8829 | default: | |
8830 | mips_macro_warning.delay_slot_length = 0; | |
8831 | break; | |
8832 | } | |
df58fc94 | 8833 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8834 | } |
8835 | ||
df58fc94 RS |
8836 | /* Given that a macro is longer than one instruction or of the wrong size, |
8837 | return the appropriate warning for it. Return null if no warning is | |
8838 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8839 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8840 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8841 | |
8842 | static const char * | |
8843 | macro_warning (relax_substateT subtype) | |
8844 | { | |
8845 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8846 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8847 | " in a branch delay slot"); |
8848 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8849 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8850 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8851 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8852 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8853 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8854 | " in a 16-bit branch delay slot") |
1661c76c | 8855 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8856 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8857 | else |
8858 | return 0; | |
8859 | } | |
8860 | ||
8861 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8862 | ||
8863 | static void | |
8864 | macro_end (void) | |
8865 | { | |
df58fc94 RS |
8866 | /* Relaxation warning flags. */ |
8867 | relax_substateT subtype = 0; | |
8868 | ||
8869 | /* Check delay slot size requirements. */ | |
8870 | if (mips_macro_warning.delay_slot_length == 2) | |
8871 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8872 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8873 | { |
df58fc94 RS |
8874 | if (mips_macro_warning.delay_slot_length |
8875 | != mips_macro_warning.first_insn_sizes[0]) | |
8876 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8877 | if (mips_macro_warning.delay_slot_length | |
8878 | != mips_macro_warning.first_insn_sizes[1]) | |
8879 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8880 | } | |
584892a6 | 8881 | |
df58fc94 RS |
8882 | /* Check instruction count requirements. */ |
8883 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8884 | { | |
8885 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8886 | subtype |= RELAX_SECOND_LONGER; |
8887 | if (mips_opts.warn_about_macros) | |
8888 | subtype |= RELAX_NOMACRO; | |
8889 | if (mips_macro_warning.delay_slot_p) | |
8890 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8891 | } |
584892a6 | 8892 | |
df58fc94 RS |
8893 | /* If both alternatives fail to fill a delay slot correctly, |
8894 | emit the warning now. */ | |
8895 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8896 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8897 | { | |
8898 | relax_substateT s; | |
8899 | const char *msg; | |
8900 | ||
8901 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8902 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8903 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8904 | msg = macro_warning (s); | |
8905 | if (msg != NULL) | |
8906 | as_warn ("%s", msg); | |
8907 | subtype &= ~s; | |
8908 | } | |
8909 | ||
8910 | /* If both implementations are longer than 1 instruction, then emit the | |
8911 | warning now. */ | |
8912 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8913 | { | |
8914 | relax_substateT s; | |
8915 | const char *msg; | |
8916 | ||
8917 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8918 | msg = macro_warning (s); | |
8919 | if (msg != NULL) | |
8920 | as_warn ("%s", msg); | |
8921 | subtype &= ~s; | |
584892a6 | 8922 | } |
df58fc94 RS |
8923 | |
8924 | /* If any flags still set, then one implementation might need a warning | |
8925 | and the other either will need one of a different kind or none at all. | |
8926 | Pass any remaining flags over to relaxation. */ | |
8927 | if (mips_macro_warning.first_frag != NULL) | |
8928 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8929 | } |
8930 | ||
df58fc94 RS |
8931 | /* Instruction operand formats used in macros that vary between |
8932 | standard MIPS and microMIPS code. */ | |
8933 | ||
833794fc | 8934 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8935 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8936 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8937 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8938 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8939 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8940 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8941 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8942 | ||
833794fc | 8943 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8944 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8945 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8946 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8947 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8948 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8949 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8950 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8951 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8952 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8953 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8954 | ||
6e1304d8 RS |
8955 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8956 | The first argument in *ARGS will be either the code for a single | |
8957 | relocation or -1 followed by the three codes that make up a | |
8958 | composite relocation. */ | |
8959 | ||
8960 | static void | |
8961 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8962 | { | |
8963 | int i, next; | |
8964 | ||
8965 | next = va_arg (*args, int); | |
8966 | if (next >= 0) | |
8967 | r[0] = (bfd_reloc_code_real_type) next; | |
8968 | else | |
f2ae14a1 RS |
8969 | { |
8970 | for (i = 0; i < 3; i++) | |
8971 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8972 | /* This function is only used for 16-bit relocation fields. | |
8973 | To make the macro code simpler, treat an unrelocated value | |
8974 | in the same way as BFD_RELOC_LO16. */ | |
8975 | if (r[0] == BFD_RELOC_UNUSED) | |
8976 | r[0] = BFD_RELOC_LO16; | |
8977 | } | |
6e1304d8 RS |
8978 | } |
8979 | ||
252b5132 RH |
8980 | /* Build an instruction created by a macro expansion. This is passed |
8981 | a pointer to the count of instructions created so far, an | |
8982 | expression, the name of the instruction to build, an operand format | |
8983 | string, and corresponding arguments. */ | |
8984 | ||
252b5132 | 8985 | static void |
67c0d1eb | 8986 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8987 | { |
df58fc94 | 8988 | const struct mips_opcode *mo = NULL; |
f6688943 | 8989 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8990 | const struct mips_opcode *amo; |
e077a1c8 | 8991 | const struct mips_operand *operand; |
df58fc94 RS |
8992 | struct hash_control *hash; |
8993 | struct mips_cl_insn insn; | |
252b5132 | 8994 | va_list args; |
e077a1c8 | 8995 | unsigned int uval; |
252b5132 | 8996 | |
252b5132 | 8997 | va_start (args, fmt); |
252b5132 | 8998 | |
252b5132 RH |
8999 | if (mips_opts.mips16) |
9000 | { | |
03ea81db | 9001 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
9002 | va_end (args); |
9003 | return; | |
9004 | } | |
9005 | ||
f6688943 TS |
9006 | r[0] = BFD_RELOC_UNUSED; |
9007 | r[1] = BFD_RELOC_UNUSED; | |
9008 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
9009 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
9010 | amo = (struct mips_opcode *) hash_find (hash, name); | |
9011 | gas_assert (amo); | |
9012 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 9013 | |
df58fc94 | 9014 | do |
8b082fb1 TS |
9015 | { |
9016 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 9017 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 9018 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
9019 | slot instruction length requirement (if any) of the previous |
9020 | instruction. While doing this we record the first instruction | |
9021 | seen that matches all the other conditions and use it anyway | |
9022 | if the requirement cannot be met; we will issue an appropriate | |
9023 | warning later on. */ | |
9024 | if (strcmp (fmt, amo->args) == 0 | |
9025 | && amo->pinfo != INSN_MACRO | |
9026 | && is_opcode_valid (amo) | |
9027 | && is_size_valid (amo)) | |
9028 | { | |
9029 | if (is_delay_slot_valid (amo)) | |
9030 | { | |
9031 | mo = amo; | |
9032 | break; | |
9033 | } | |
9034 | else if (!mo) | |
9035 | mo = amo; | |
9036 | } | |
8b082fb1 | 9037 | |
df58fc94 RS |
9038 | ++amo; |
9039 | gas_assert (amo->name); | |
252b5132 | 9040 | } |
df58fc94 | 9041 | while (strcmp (name, amo->name) == 0); |
252b5132 | 9042 | |
df58fc94 | 9043 | gas_assert (mo); |
1e915849 | 9044 | create_insn (&insn, mo); |
e077a1c8 | 9045 | for (; *fmt; ++fmt) |
252b5132 | 9046 | { |
e077a1c8 | 9047 | switch (*fmt) |
252b5132 | 9048 | { |
252b5132 RH |
9049 | case ',': |
9050 | case '(': | |
9051 | case ')': | |
252b5132 | 9052 | case 'z': |
e077a1c8 | 9053 | break; |
252b5132 RH |
9054 | |
9055 | case 'i': | |
9056 | case 'j': | |
6e1304d8 | 9057 | macro_read_relocs (&args, r); |
9c2799c2 | 9058 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
9059 | || *r == BFD_RELOC_MIPS_HIGHER |
9060 | || *r == BFD_RELOC_HI16_S | |
9061 | || *r == BFD_RELOC_LO16 | |
14c80123 MR |
9062 | || *r == BFD_RELOC_MIPS_GOT_OFST |
9063 | || (mips_opts.micromips | |
9064 | && (*r == BFD_RELOC_16 | |
9065 | || *r == BFD_RELOC_MIPS_GOT16 | |
9066 | || *r == BFD_RELOC_MIPS_CALL16 | |
9067 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
9068 | || *r == BFD_RELOC_MIPS_GOT_LO16 | |
9069 | || *r == BFD_RELOC_MIPS_CALL_HI16 | |
9070 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
9071 | || *r == BFD_RELOC_MIPS_SUB | |
9072 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
9073 | || *r == BFD_RELOC_MIPS_HIGHEST | |
9074 | || *r == BFD_RELOC_MIPS_GOT_DISP | |
9075 | || *r == BFD_RELOC_MIPS_TLS_GD | |
9076 | || *r == BFD_RELOC_MIPS_TLS_LDM | |
9077 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16 | |
9078 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16 | |
9079 | || *r == BFD_RELOC_MIPS_TLS_GOTTPREL | |
9080 | || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16 | |
9081 | || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16))); | |
e077a1c8 | 9082 | break; |
e391c024 RS |
9083 | |
9084 | case 'o': | |
9085 | macro_read_relocs (&args, r); | |
e077a1c8 | 9086 | break; |
252b5132 RH |
9087 | |
9088 | case 'u': | |
6e1304d8 | 9089 | macro_read_relocs (&args, r); |
9c2799c2 | 9090 | gas_assert (ep != NULL |
90ecf173 MR |
9091 | && (ep->X_op == O_constant |
9092 | || (ep->X_op == O_symbol | |
9093 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
9094 | || *r == BFD_RELOC_HI16_S | |
9095 | || *r == BFD_RELOC_HI16 | |
9096 | || *r == BFD_RELOC_GPREL16 | |
9097 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
9098 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 9099 | break; |
252b5132 RH |
9100 | |
9101 | case 'p': | |
9c2799c2 | 9102 | gas_assert (ep != NULL); |
bad36eac | 9103 | |
252b5132 RH |
9104 | /* |
9105 | * This allows macro() to pass an immediate expression for | |
9106 | * creating short branches without creating a symbol. | |
bad36eac DJ |
9107 | * |
9108 | * We don't allow branch relaxation for these branches, as | |
9109 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
9110 | */ |
9111 | if (ep->X_op == O_constant) | |
9112 | { | |
df58fc94 RS |
9113 | /* For microMIPS we always use relocations for branches. |
9114 | So we should not resolve immediate values. */ | |
9115 | gas_assert (!mips_opts.micromips); | |
9116 | ||
bad36eac DJ |
9117 | if ((ep->X_add_number & 3) != 0) |
9118 | as_bad (_("branch to misaligned address (0x%lx)"), | |
9119 | (unsigned long) ep->X_add_number); | |
9120 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
9121 | as_bad (_("branch address range overflow (0x%lx)"), | |
9122 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
9123 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
9124 | ep = NULL; | |
9125 | } | |
9126 | else | |
0b25d3e6 | 9127 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 9128 | break; |
252b5132 RH |
9129 | |
9130 | case 'a': | |
9c2799c2 | 9131 | gas_assert (ep != NULL); |
f6688943 | 9132 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 9133 | break; |
d43b4baf | 9134 | |
252b5132 | 9135 | default: |
e077a1c8 RS |
9136 | operand = (mips_opts.micromips |
9137 | ? decode_micromips_operand (fmt) | |
9138 | : decode_mips_operand (fmt)); | |
9139 | if (!operand) | |
9140 | abort (); | |
9141 | ||
9142 | uval = va_arg (args, int); | |
9143 | if (operand->type == OP_CLO_CLZ_DEST) | |
9144 | uval |= (uval << 5); | |
9145 | insn_insert_operand (&insn, operand, uval); | |
9146 | ||
7361da2c | 9147 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
9148 | ++fmt; |
9149 | break; | |
252b5132 | 9150 | } |
252b5132 RH |
9151 | } |
9152 | va_end (args); | |
9c2799c2 | 9153 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9154 | |
df58fc94 | 9155 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9156 | } |
9157 | ||
9158 | static void | |
67c0d1eb | 9159 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 9160 | va_list *args) |
252b5132 | 9161 | { |
1e915849 | 9162 | struct mips_opcode *mo; |
252b5132 | 9163 | struct mips_cl_insn insn; |
e077a1c8 | 9164 | const struct mips_operand *operand; |
f6688943 TS |
9165 | bfd_reloc_code_real_type r[3] |
9166 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 9167 | |
1e915849 | 9168 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
9169 | gas_assert (mo); |
9170 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 9171 | |
1e915849 | 9172 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 9173 | { |
1e915849 | 9174 | ++mo; |
9c2799c2 NC |
9175 | gas_assert (mo->name); |
9176 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
9177 | } |
9178 | ||
1e915849 | 9179 | create_insn (&insn, mo); |
e077a1c8 | 9180 | for (; *fmt; ++fmt) |
252b5132 RH |
9181 | { |
9182 | int c; | |
9183 | ||
e077a1c8 | 9184 | c = *fmt; |
252b5132 RH |
9185 | switch (c) |
9186 | { | |
252b5132 RH |
9187 | case ',': |
9188 | case '(': | |
9189 | case ')': | |
e077a1c8 | 9190 | break; |
252b5132 | 9191 | |
d8722d76 | 9192 | case '.': |
252b5132 RH |
9193 | case 'S': |
9194 | case 'P': | |
9195 | case 'R': | |
e077a1c8 | 9196 | break; |
252b5132 RH |
9197 | |
9198 | case '<': | |
252b5132 | 9199 | case '5': |
d8722d76 | 9200 | case 'F': |
252b5132 RH |
9201 | case 'H': |
9202 | case 'W': | |
9203 | case 'D': | |
9204 | case 'j': | |
9205 | case '8': | |
9206 | case 'V': | |
9207 | case 'C': | |
9208 | case 'U': | |
9209 | case 'k': | |
9210 | case 'K': | |
9211 | case 'p': | |
9212 | case 'q': | |
9213 | { | |
b886a2ab RS |
9214 | offsetT value; |
9215 | ||
9c2799c2 | 9216 | gas_assert (ep != NULL); |
252b5132 RH |
9217 | |
9218 | if (ep->X_op != O_constant) | |
874e8986 | 9219 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 9220 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 9221 | { |
b886a2ab | 9222 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 9223 | ep = NULL; |
f6688943 | 9224 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
9225 | } |
9226 | } | |
e077a1c8 | 9227 | break; |
252b5132 | 9228 | |
e077a1c8 RS |
9229 | default: |
9230 | operand = decode_mips16_operand (c, FALSE); | |
9231 | if (!operand) | |
9232 | abort (); | |
252b5132 | 9233 | |
4a06e5a2 | 9234 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
9235 | break; |
9236 | } | |
252b5132 RH |
9237 | } |
9238 | ||
9c2799c2 | 9239 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9240 | |
df58fc94 | 9241 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9242 | } |
9243 | ||
438c16b8 TS |
9244 | /* |
9245 | * Generate a "jalr" instruction with a relocation hint to the called | |
9246 | * function. This occurs in NewABI PIC code. | |
9247 | */ | |
9248 | static void | |
df58fc94 | 9249 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 9250 | { |
df58fc94 RS |
9251 | static const bfd_reloc_code_real_type jalr_relocs[2] |
9252 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
9253 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
9254 | const char *jalr; | |
685736be | 9255 | char *f = NULL; |
b34976b6 | 9256 | |
1180b5a4 | 9257 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 9258 | { |
cc3d92a5 | 9259 | frag_grow (8); |
f21f8242 AO |
9260 | f = frag_more (0); |
9261 | } | |
2906b037 | 9262 | if (mips_opts.micromips) |
df58fc94 | 9263 | { |
833794fc MR |
9264 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
9265 | ? "jalr" : "jalrs"); | |
e64af278 | 9266 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 9267 | || mips_opts.insn32 |
e64af278 | 9268 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
9269 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
9270 | else | |
9271 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
9272 | } | |
2906b037 MR |
9273 | else |
9274 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 9275 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 9276 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
9277 | } |
9278 | ||
252b5132 RH |
9279 | /* |
9280 | * Generate a "lui" instruction. | |
9281 | */ | |
9282 | static void | |
67c0d1eb | 9283 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 9284 | { |
9c2799c2 | 9285 | gas_assert (! mips_opts.mips16); |
252b5132 | 9286 | |
df58fc94 | 9287 | if (ep->X_op != O_constant) |
252b5132 | 9288 | { |
9c2799c2 | 9289 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
9290 | /* _gp_disp is a special case, used from s_cpload. |
9291 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 9292 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 9293 | || (! HAVE_NEWABI |
aa6975fb ILT |
9294 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
9295 | || (! mips_in_shared | |
bbe506e8 TS |
9296 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
9297 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
9298 | } |
9299 | ||
df58fc94 | 9300 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
9301 | } |
9302 | ||
885add95 CD |
9303 | /* Generate a sequence of instructions to do a load or store from a constant |
9304 | offset off of a base register (breg) into/from a target register (treg), | |
9305 | using AT if necessary. */ | |
9306 | static void | |
67c0d1eb RS |
9307 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
9308 | int treg, int breg, int dbl) | |
885add95 | 9309 | { |
9c2799c2 | 9310 | gas_assert (ep->X_op == O_constant); |
885add95 | 9311 | |
256ab948 | 9312 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
9313 | if (!dbl) |
9314 | normalize_constant_expr (ep); | |
256ab948 | 9315 | |
67c1ffbe | 9316 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 9317 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
9318 | as_warn (_("operand overflow")); |
9319 | ||
9320 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
9321 | { | |
9322 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 9323 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
9324 | } |
9325 | else | |
9326 | { | |
9327 | /* 32-bit offset, need multiple instructions and AT, like: | |
9328 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
9329 | addu $tempreg,$tempreg,$breg | |
9330 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
9331 | to handle the complete offset. */ | |
67c0d1eb RS |
9332 | macro_build_lui (ep, AT); |
9333 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
9334 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 9335 | |
741fe287 | 9336 | if (!mips_opts.at) |
1661c76c | 9337 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
9338 | } |
9339 | } | |
9340 | ||
252b5132 RH |
9341 | /* set_at() |
9342 | * Generates code to set the $at register to true (one) | |
9343 | * if reg is less than the immediate expression. | |
9344 | */ | |
9345 | static void | |
67c0d1eb | 9346 | set_at (int reg, int unsignedp) |
252b5132 | 9347 | { |
b0e6f033 | 9348 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 9349 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
9350 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
9351 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
9352 | else |
9353 | { | |
bad1aba3 | 9354 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 9355 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
9356 | } |
9357 | } | |
9358 | ||
252b5132 RH |
9359 | /* Count the leading zeroes by performing a binary chop. This is a |
9360 | bulky bit of source, but performance is a LOT better for the | |
9361 | majority of values than a simple loop to count the bits: | |
9362 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
9363 | if ((v) & (1 << (31 - lcnt))) | |
9364 | break; | |
9365 | However it is not code size friendly, and the gain will drop a bit | |
9366 | on certain cached systems. | |
9367 | */ | |
9368 | #define COUNT_TOP_ZEROES(v) \ | |
9369 | (((v) & ~0xffff) == 0 \ | |
9370 | ? ((v) & ~0xff) == 0 \ | |
9371 | ? ((v) & ~0xf) == 0 \ | |
9372 | ? ((v) & ~0x3) == 0 \ | |
9373 | ? ((v) & ~0x1) == 0 \ | |
9374 | ? !(v) \ | |
9375 | ? 32 \ | |
9376 | : 31 \ | |
9377 | : 30 \ | |
9378 | : ((v) & ~0x7) == 0 \ | |
9379 | ? 29 \ | |
9380 | : 28 \ | |
9381 | : ((v) & ~0x3f) == 0 \ | |
9382 | ? ((v) & ~0x1f) == 0 \ | |
9383 | ? 27 \ | |
9384 | : 26 \ | |
9385 | : ((v) & ~0x7f) == 0 \ | |
9386 | ? 25 \ | |
9387 | : 24 \ | |
9388 | : ((v) & ~0xfff) == 0 \ | |
9389 | ? ((v) & ~0x3ff) == 0 \ | |
9390 | ? ((v) & ~0x1ff) == 0 \ | |
9391 | ? 23 \ | |
9392 | : 22 \ | |
9393 | : ((v) & ~0x7ff) == 0 \ | |
9394 | ? 21 \ | |
9395 | : 20 \ | |
9396 | : ((v) & ~0x3fff) == 0 \ | |
9397 | ? ((v) & ~0x1fff) == 0 \ | |
9398 | ? 19 \ | |
9399 | : 18 \ | |
9400 | : ((v) & ~0x7fff) == 0 \ | |
9401 | ? 17 \ | |
9402 | : 16 \ | |
9403 | : ((v) & ~0xffffff) == 0 \ | |
9404 | ? ((v) & ~0xfffff) == 0 \ | |
9405 | ? ((v) & ~0x3ffff) == 0 \ | |
9406 | ? ((v) & ~0x1ffff) == 0 \ | |
9407 | ? 15 \ | |
9408 | : 14 \ | |
9409 | : ((v) & ~0x7ffff) == 0 \ | |
9410 | ? 13 \ | |
9411 | : 12 \ | |
9412 | : ((v) & ~0x3fffff) == 0 \ | |
9413 | ? ((v) & ~0x1fffff) == 0 \ | |
9414 | ? 11 \ | |
9415 | : 10 \ | |
9416 | : ((v) & ~0x7fffff) == 0 \ | |
9417 | ? 9 \ | |
9418 | : 8 \ | |
9419 | : ((v) & ~0xfffffff) == 0 \ | |
9420 | ? ((v) & ~0x3ffffff) == 0 \ | |
9421 | ? ((v) & ~0x1ffffff) == 0 \ | |
9422 | ? 7 \ | |
9423 | : 6 \ | |
9424 | : ((v) & ~0x7ffffff) == 0 \ | |
9425 | ? 5 \ | |
9426 | : 4 \ | |
9427 | : ((v) & ~0x3fffffff) == 0 \ | |
9428 | ? ((v) & ~0x1fffffff) == 0 \ | |
9429 | ? 3 \ | |
9430 | : 2 \ | |
9431 | : ((v) & ~0x7fffffff) == 0 \ | |
9432 | ? 1 \ | |
9433 | : 0) | |
9434 | ||
9435 | /* load_register() | |
67c1ffbe | 9436 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9437 | * an absolute expression value into a register. |
9438 | */ | |
9439 | static void | |
67c0d1eb | 9440 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9441 | { |
9442 | int freg; | |
9443 | expressionS hi32, lo32; | |
9444 | ||
9445 | if (ep->X_op != O_big) | |
9446 | { | |
9c2799c2 | 9447 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9448 | |
9449 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9450 | if (!dbl) |
9451 | normalize_constant_expr (ep); | |
256ab948 TS |
9452 | |
9453 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9454 | { |
9455 | /* We can handle 16 bit signed values with an addiu to | |
9456 | $zero. No need to ever use daddiu here, since $zero and | |
9457 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9458 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9459 | return; |
9460 | } | |
9461 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9462 | { | |
9463 | /* We can handle 16 bit unsigned values with an ori to | |
9464 | $zero. */ | |
67c0d1eb | 9465 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9466 | return; |
9467 | } | |
256ab948 | 9468 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9469 | { |
9470 | /* 32 bit values require an lui. */ | |
df58fc94 | 9471 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9472 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9473 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9474 | return; |
9475 | } | |
9476 | } | |
9477 | ||
9478 | /* The value is larger than 32 bits. */ | |
9479 | ||
bad1aba3 | 9480 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9481 | { |
55e08f71 NC |
9482 | char value[32]; |
9483 | ||
9484 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9485 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9486 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9487 | return; |
9488 | } | |
9489 | ||
9490 | if (ep->X_op != O_big) | |
9491 | { | |
9492 | hi32 = *ep; | |
9493 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9494 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9495 | hi32.X_add_number &= 0xffffffff; | |
9496 | lo32 = *ep; | |
9497 | lo32.X_add_number &= 0xffffffff; | |
9498 | } | |
9499 | else | |
9500 | { | |
9c2799c2 | 9501 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9502 | if (ep->X_add_number == 3) |
9503 | generic_bignum[3] = 0; | |
9504 | else if (ep->X_add_number > 4) | |
1661c76c | 9505 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9506 | lo32.X_op = O_constant; |
9507 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9508 | hi32.X_op = O_constant; | |
9509 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9510 | } | |
9511 | ||
9512 | if (hi32.X_add_number == 0) | |
9513 | freg = 0; | |
9514 | else | |
9515 | { | |
9516 | int shift, bit; | |
9517 | unsigned long hi, lo; | |
9518 | ||
956cd1d6 | 9519 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9520 | { |
9521 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9522 | { | |
67c0d1eb | 9523 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9524 | return; |
9525 | } | |
9526 | if (lo32.X_add_number & 0x80000000) | |
9527 | { | |
df58fc94 | 9528 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9529 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9530 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9531 | return; |
9532 | } | |
9533 | } | |
252b5132 RH |
9534 | |
9535 | /* Check for 16bit shifted constant. We know that hi32 is | |
9536 | non-zero, so start the mask on the first bit of the hi32 | |
9537 | value. */ | |
9538 | shift = 17; | |
9539 | do | |
beae10d5 KH |
9540 | { |
9541 | unsigned long himask, lomask; | |
9542 | ||
9543 | if (shift < 32) | |
9544 | { | |
9545 | himask = 0xffff >> (32 - shift); | |
9546 | lomask = (0xffff << shift) & 0xffffffff; | |
9547 | } | |
9548 | else | |
9549 | { | |
9550 | himask = 0xffff << (shift - 32); | |
9551 | lomask = 0; | |
9552 | } | |
9553 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9554 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9555 | { | |
9556 | expressionS tmp; | |
9557 | ||
9558 | tmp.X_op = O_constant; | |
9559 | if (shift < 32) | |
9560 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9561 | | (lo32.X_add_number >> shift)); | |
9562 | else | |
9563 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9564 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9565 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9566 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9567 | return; |
9568 | } | |
f9419b05 | 9569 | ++shift; |
beae10d5 KH |
9570 | } |
9571 | while (shift <= (64 - 16)); | |
252b5132 RH |
9572 | |
9573 | /* Find the bit number of the lowest one bit, and store the | |
9574 | shifted value in hi/lo. */ | |
9575 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9576 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9577 | if (lo != 0) | |
9578 | { | |
9579 | bit = 0; | |
9580 | while ((lo & 1) == 0) | |
9581 | { | |
9582 | lo >>= 1; | |
9583 | ++bit; | |
9584 | } | |
9585 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9586 | hi >>= bit; | |
9587 | } | |
9588 | else | |
9589 | { | |
9590 | bit = 32; | |
9591 | while ((hi & 1) == 0) | |
9592 | { | |
9593 | hi >>= 1; | |
9594 | ++bit; | |
9595 | } | |
9596 | lo = hi; | |
9597 | hi = 0; | |
9598 | } | |
9599 | ||
9600 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9601 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9602 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9603 | { |
9604 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9605 | if (shift != 0) |
beae10d5 | 9606 | { |
252b5132 RH |
9607 | expressionS tmp; |
9608 | ||
9609 | /* This instruction will set the register to be all | |
9610 | ones. */ | |
beae10d5 KH |
9611 | tmp.X_op = O_constant; |
9612 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9613 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9614 | if (bit != 0) |
9615 | { | |
9616 | bit += shift; | |
df58fc94 | 9617 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9618 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9619 | } |
df58fc94 | 9620 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9621 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9622 | return; |
9623 | } | |
9624 | } | |
252b5132 RH |
9625 | |
9626 | /* Sign extend hi32 before calling load_register, because we can | |
9627 | generally get better code when we load a sign extended value. */ | |
9628 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9629 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9630 | load_register (reg, &hi32, 0); |
252b5132 RH |
9631 | freg = reg; |
9632 | } | |
9633 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9634 | { | |
9635 | if (freg != 0) | |
9636 | { | |
df58fc94 | 9637 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9638 | freg = reg; |
9639 | } | |
9640 | } | |
9641 | else | |
9642 | { | |
9643 | expressionS mid16; | |
9644 | ||
956cd1d6 | 9645 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9646 | { |
df58fc94 RS |
9647 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9648 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9649 | return; |
9650 | } | |
252b5132 RH |
9651 | |
9652 | if (freg != 0) | |
9653 | { | |
df58fc94 | 9654 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9655 | freg = reg; |
9656 | } | |
9657 | mid16 = lo32; | |
9658 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9659 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9660 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9661 | freg = reg; |
9662 | } | |
9663 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9664 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9665 | } |
9666 | ||
269137b2 TS |
9667 | static inline void |
9668 | load_delay_nop (void) | |
9669 | { | |
9670 | if (!gpr_interlocks) | |
9671 | macro_build (NULL, "nop", ""); | |
9672 | } | |
9673 | ||
252b5132 RH |
9674 | /* Load an address into a register. */ |
9675 | ||
9676 | static void | |
67c0d1eb | 9677 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9678 | { |
252b5132 RH |
9679 | if (ep->X_op != O_constant |
9680 | && ep->X_op != O_symbol) | |
9681 | { | |
9682 | as_bad (_("expression too complex")); | |
9683 | ep->X_op = O_constant; | |
9684 | } | |
9685 | ||
9686 | if (ep->X_op == O_constant) | |
9687 | { | |
67c0d1eb | 9688 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9689 | return; |
9690 | } | |
9691 | ||
9692 | if (mips_pic == NO_PIC) | |
9693 | { | |
9694 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9695 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9696 | Otherwise we want |
9697 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9698 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9699 | If we have an addend, we always use the latter form. |
76b3015f | 9700 | |
d6bc6245 TS |
9701 | With 64bit address space and a usable $at we want |
9702 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9703 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9704 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9705 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9706 | dsll32 $reg,0 | |
3a482fd5 | 9707 | daddu $reg,$reg,$at |
76b3015f | 9708 | |
c03099e6 | 9709 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9710 | on superscalar processors. |
9711 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9712 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9713 | dsll $reg,16 | |
9714 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9715 | dsll $reg,16 | |
9716 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9717 | |
9718 | For GP relative symbols in 64bit address space we can use | |
9719 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9720 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9721 | { |
6caf9ef4 TS |
9722 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9723 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9724 | { | |
9725 | relax_start (ep->X_add_symbol); | |
9726 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9727 | mips_gp_register, BFD_RELOC_GPREL16); | |
9728 | relax_switch (); | |
9729 | } | |
d6bc6245 | 9730 | |
741fe287 | 9731 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9732 | { |
df58fc94 RS |
9733 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9734 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9735 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9736 | BFD_RELOC_MIPS_HIGHER); | |
9737 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9738 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9739 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9740 | *used_at = 1; |
9741 | } | |
9742 | else | |
9743 | { | |
df58fc94 | 9744 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9745 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9746 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9747 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9748 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9749 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9750 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9751 | } |
6caf9ef4 TS |
9752 | |
9753 | if (mips_relax.sequence) | |
9754 | relax_end (); | |
d6bc6245 | 9755 | } |
252b5132 RH |
9756 | else |
9757 | { | |
d6bc6245 | 9758 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9759 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9760 | { |
4d7206a2 | 9761 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9762 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9763 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9764 | relax_switch (); |
d6bc6245 | 9765 | } |
67c0d1eb RS |
9766 | macro_build_lui (ep, reg); |
9767 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9768 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9769 | if (mips_relax.sequence) |
9770 | relax_end (); | |
d6bc6245 | 9771 | } |
252b5132 | 9772 | } |
0a44bf69 | 9773 | else if (!mips_big_got) |
252b5132 RH |
9774 | { |
9775 | expressionS ex; | |
9776 | ||
9777 | /* If this is a reference to an external symbol, we want | |
9778 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9779 | Otherwise we want | |
9780 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9781 | nop | |
9782 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9783 | If there is a constant, it must be added in after. |
9784 | ||
ed6fb7bd | 9785 | If we have NewABI, we want |
f5040a92 AO |
9786 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9787 | unless we're referencing a global symbol with a non-zero | |
9788 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9789 | if (HAVE_NEWABI) |
9790 | { | |
f5040a92 AO |
9791 | if (ep->X_add_number) |
9792 | { | |
4d7206a2 | 9793 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9794 | ep->X_add_number = 0; |
4d7206a2 | 9795 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9796 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9797 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9798 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9799 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9800 | ex.X_op = O_constant; | |
67c0d1eb | 9801 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9802 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9803 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9804 | relax_switch (); |
f5040a92 | 9805 | } |
67c0d1eb | 9806 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9807 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9808 | if (mips_relax.sequence) |
9809 | relax_end (); | |
ed6fb7bd SC |
9810 | } |
9811 | else | |
9812 | { | |
f5040a92 AO |
9813 | ex.X_add_number = ep->X_add_number; |
9814 | ep->X_add_number = 0; | |
67c0d1eb RS |
9815 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9816 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9817 | load_delay_nop (); |
4d7206a2 RS |
9818 | relax_start (ep->X_add_symbol); |
9819 | relax_switch (); | |
67c0d1eb | 9820 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9821 | BFD_RELOC_LO16); |
4d7206a2 | 9822 | relax_end (); |
ed6fb7bd | 9823 | |
f5040a92 AO |
9824 | if (ex.X_add_number != 0) |
9825 | { | |
9826 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9827 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9828 | ex.X_op = O_constant; | |
67c0d1eb | 9829 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9830 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9831 | } |
252b5132 RH |
9832 | } |
9833 | } | |
0a44bf69 | 9834 | else if (mips_big_got) |
252b5132 RH |
9835 | { |
9836 | expressionS ex; | |
252b5132 RH |
9837 | |
9838 | /* This is the large GOT case. If this is a reference to an | |
9839 | external symbol, we want | |
9840 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9841 | addu $reg,$reg,$gp | |
9842 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9843 | |
9844 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9845 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9846 | nop | |
9847 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9848 | If there is a constant, it must be added in after. |
f5040a92 AO |
9849 | |
9850 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9851 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9852 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9853 | */ |
438c16b8 TS |
9854 | if (HAVE_NEWABI) |
9855 | { | |
4d7206a2 | 9856 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9857 | ep->X_add_number = 0; |
4d7206a2 | 9858 | relax_start (ep->X_add_symbol); |
df58fc94 | 9859 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9860 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9861 | reg, reg, mips_gp_register); | |
9862 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9863 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9864 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9865 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9866 | else if (ex.X_add_number) | |
9867 | { | |
9868 | ex.X_op = O_constant; | |
67c0d1eb RS |
9869 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9870 | BFD_RELOC_LO16); | |
f5040a92 AO |
9871 | } |
9872 | ||
9873 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9874 | relax_switch (); |
67c0d1eb | 9875 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9876 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9877 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9878 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9879 | relax_end (); |
438c16b8 | 9880 | } |
252b5132 | 9881 | else |
438c16b8 | 9882 | { |
f5040a92 AO |
9883 | ex.X_add_number = ep->X_add_number; |
9884 | ep->X_add_number = 0; | |
4d7206a2 | 9885 | relax_start (ep->X_add_symbol); |
df58fc94 | 9886 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9887 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9888 | reg, reg, mips_gp_register); | |
9889 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9890 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9891 | relax_switch (); |
9892 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9893 | { |
9894 | /* We need a nop before loading from $gp. This special | |
9895 | check is required because the lui which starts the main | |
9896 | instruction stream does not refer to $gp, and so will not | |
9897 | insert the nop which may be required. */ | |
67c0d1eb | 9898 | macro_build (NULL, "nop", ""); |
438c16b8 | 9899 | } |
67c0d1eb | 9900 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9901 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9902 | load_delay_nop (); |
67c0d1eb | 9903 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9904 | BFD_RELOC_LO16); |
4d7206a2 | 9905 | relax_end (); |
438c16b8 | 9906 | |
f5040a92 AO |
9907 | if (ex.X_add_number != 0) |
9908 | { | |
9909 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9910 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9911 | ex.X_op = O_constant; | |
67c0d1eb RS |
9912 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9913 | BFD_RELOC_LO16); | |
f5040a92 | 9914 | } |
252b5132 RH |
9915 | } |
9916 | } | |
252b5132 RH |
9917 | else |
9918 | abort (); | |
8fc2e39e | 9919 | |
741fe287 | 9920 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9921 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9922 | } |
9923 | ||
ea1fb5dc RS |
9924 | /* Move the contents of register SOURCE into register DEST. */ |
9925 | ||
9926 | static void | |
67c0d1eb | 9927 | move_register (int dest, int source) |
ea1fb5dc | 9928 | { |
df58fc94 RS |
9929 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9930 | instruction specifically requires a 32-bit one. */ | |
9931 | if (mips_opts.micromips | |
833794fc | 9932 | && !mips_opts.insn32 |
df58fc94 | 9933 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9934 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9935 | else |
40fc1451 | 9936 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9937 | } |
9938 | ||
4d7206a2 | 9939 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9940 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9941 | The two alternatives are: | |
4d7206a2 | 9942 | |
33eaf5de | 9943 | Global symbol Local symbol |
4d7206a2 RS |
9944 | ------------- ------------ |
9945 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9946 | ... ... | |
9947 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9948 | ||
9949 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9950 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9951 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9952 | |
9953 | static void | |
67c0d1eb | 9954 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9955 | { |
9956 | expressionS global; | |
9957 | ||
9958 | global = *local; | |
9959 | global.X_add_number = 0; | |
9960 | ||
9961 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9962 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9963 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9964 | relax_switch (); |
67c0d1eb RS |
9965 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9966 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9967 | relax_end (); |
9968 | } | |
9969 | ||
9970 | static void | |
67c0d1eb | 9971 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9972 | { |
9973 | expressionS global; | |
9974 | ||
9975 | global.X_op = O_constant; | |
9976 | global.X_op_symbol = NULL; | |
9977 | global.X_add_symbol = NULL; | |
9978 | global.X_add_number = local->X_add_number; | |
9979 | ||
9980 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9981 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9982 | dest, dest, BFD_RELOC_LO16); |
9983 | relax_switch (); | |
67c0d1eb | 9984 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9985 | relax_end (); |
9986 | } | |
9987 | ||
f6a22291 MR |
9988 | static void |
9989 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9990 | { | |
9991 | expressionS global; | |
9992 | int hold_mips_optimize; | |
9993 | ||
9994 | global.X_op = O_constant; | |
9995 | global.X_op_symbol = NULL; | |
9996 | global.X_add_symbol = NULL; | |
9997 | global.X_add_number = local->X_add_number; | |
9998 | ||
9999 | relax_start (local->X_add_symbol); | |
10000 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
10001 | relax_switch (); | |
10002 | /* Set mips_optimize around the lui instruction to avoid | |
10003 | inserting an unnecessary nop after the lw. */ | |
10004 | hold_mips_optimize = mips_optimize; | |
10005 | mips_optimize = 2; | |
10006 | macro_build_lui (&global, tmp); | |
10007 | mips_optimize = hold_mips_optimize; | |
10008 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
10009 | relax_end (); | |
10010 | ||
10011 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
10012 | } | |
10013 | ||
df58fc94 RS |
10014 | /* Emit a sequence of instructions to emulate a branch likely operation. |
10015 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
10016 | is its complementing branch with the original condition negated. | |
10017 | CALL is set if the original branch specified the link operation. | |
10018 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
10019 | ||
10020 | Code like this is produced in the noreorder mode: | |
10021 | ||
10022 | BRNEG <args>, 1f | |
10023 | nop | |
10024 | b <sym> | |
10025 | delay slot (executed only if branch taken) | |
10026 | 1: | |
10027 | ||
10028 | or, if CALL is set: | |
10029 | ||
10030 | BRNEG <args>, 1f | |
10031 | nop | |
10032 | bal <sym> | |
10033 | delay slot (executed only if branch taken) | |
10034 | 1: | |
10035 | ||
10036 | In the reorder mode the delay slot would be filled with a nop anyway, | |
10037 | so code produced is simply: | |
10038 | ||
10039 | BR <args>, <sym> | |
10040 | nop | |
10041 | ||
10042 | This function is used when producing code for the microMIPS ASE that | |
10043 | does not implement branch likely instructions in hardware. */ | |
10044 | ||
10045 | static void | |
10046 | macro_build_branch_likely (const char *br, const char *brneg, | |
10047 | int call, expressionS *ep, const char *fmt, | |
10048 | unsigned int sreg, unsigned int treg) | |
10049 | { | |
10050 | int noreorder = mips_opts.noreorder; | |
10051 | expressionS expr1; | |
10052 | ||
10053 | gas_assert (mips_opts.micromips); | |
10054 | start_noreorder (); | |
10055 | if (noreorder) | |
10056 | { | |
10057 | micromips_label_expr (&expr1); | |
10058 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
10059 | macro_build (NULL, "nop", ""); | |
10060 | macro_build (ep, call ? "bal" : "b", "p"); | |
10061 | ||
10062 | /* Set to true so that append_insn adds a label. */ | |
10063 | emit_branch_likely_macro = TRUE; | |
10064 | } | |
10065 | else | |
10066 | { | |
10067 | macro_build (ep, br, fmt, sreg, treg); | |
10068 | macro_build (NULL, "nop", ""); | |
10069 | } | |
10070 | end_noreorder (); | |
10071 | } | |
10072 | ||
10073 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
10074 | the condition code tested. EP specifies the branch target. */ | |
10075 | ||
10076 | static void | |
10077 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
10078 | { | |
10079 | const int call = 0; | |
10080 | const char *brneg; | |
10081 | const char *br; | |
10082 | ||
10083 | switch (type) | |
10084 | { | |
10085 | case M_BC1FL: | |
10086 | br = "bc1f"; | |
10087 | brneg = "bc1t"; | |
10088 | break; | |
10089 | case M_BC1TL: | |
10090 | br = "bc1t"; | |
10091 | brneg = "bc1f"; | |
10092 | break; | |
10093 | case M_BC2FL: | |
10094 | br = "bc2f"; | |
10095 | brneg = "bc2t"; | |
10096 | break; | |
10097 | case M_BC2TL: | |
10098 | br = "bc2t"; | |
10099 | brneg = "bc2f"; | |
10100 | break; | |
10101 | default: | |
10102 | abort (); | |
10103 | } | |
10104 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
10105 | } | |
10106 | ||
10107 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
10108 | the register tested. EP specifies the branch target. */ | |
10109 | ||
10110 | static void | |
10111 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
10112 | { | |
10113 | const char *brneg = NULL; | |
10114 | const char *br; | |
10115 | int call = 0; | |
10116 | ||
10117 | switch (type) | |
10118 | { | |
10119 | case M_BGEZ: | |
10120 | br = "bgez"; | |
10121 | break; | |
10122 | case M_BGEZL: | |
10123 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
10124 | brneg = "bltz"; | |
10125 | break; | |
10126 | case M_BGEZALL: | |
10127 | gas_assert (mips_opts.micromips); | |
833794fc | 10128 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
10129 | brneg = "bltz"; |
10130 | call = 1; | |
10131 | break; | |
10132 | case M_BGTZ: | |
10133 | br = "bgtz"; | |
10134 | break; | |
10135 | case M_BGTZL: | |
10136 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
10137 | brneg = "blez"; | |
10138 | break; | |
10139 | case M_BLEZ: | |
10140 | br = "blez"; | |
10141 | break; | |
10142 | case M_BLEZL: | |
10143 | br = mips_opts.micromips ? "blez" : "blezl"; | |
10144 | brneg = "bgtz"; | |
10145 | break; | |
10146 | case M_BLTZ: | |
10147 | br = "bltz"; | |
10148 | break; | |
10149 | case M_BLTZL: | |
10150 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
10151 | brneg = "bgez"; | |
10152 | break; | |
10153 | case M_BLTZALL: | |
10154 | gas_assert (mips_opts.micromips); | |
833794fc | 10155 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
10156 | brneg = "bgez"; |
10157 | call = 1; | |
10158 | break; | |
10159 | default: | |
10160 | abort (); | |
10161 | } | |
10162 | if (mips_opts.micromips && brneg) | |
10163 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
10164 | else | |
10165 | macro_build (ep, br, "s,p", sreg); | |
10166 | } | |
10167 | ||
10168 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
10169 | TREG as the registers tested. EP specifies the branch target. */ | |
10170 | ||
10171 | static void | |
10172 | macro_build_branch_rsrt (int type, expressionS *ep, | |
10173 | unsigned int sreg, unsigned int treg) | |
10174 | { | |
10175 | const char *brneg = NULL; | |
10176 | const int call = 0; | |
10177 | const char *br; | |
10178 | ||
10179 | switch (type) | |
10180 | { | |
10181 | case M_BEQ: | |
10182 | case M_BEQ_I: | |
10183 | br = "beq"; | |
10184 | break; | |
10185 | case M_BEQL: | |
10186 | case M_BEQL_I: | |
10187 | br = mips_opts.micromips ? "beq" : "beql"; | |
10188 | brneg = "bne"; | |
10189 | break; | |
10190 | case M_BNE: | |
10191 | case M_BNE_I: | |
10192 | br = "bne"; | |
10193 | break; | |
10194 | case M_BNEL: | |
10195 | case M_BNEL_I: | |
10196 | br = mips_opts.micromips ? "bne" : "bnel"; | |
10197 | brneg = "beq"; | |
10198 | break; | |
10199 | default: | |
10200 | abort (); | |
10201 | } | |
10202 | if (mips_opts.micromips && brneg) | |
10203 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
10204 | else | |
10205 | macro_build (ep, br, "s,t,p", sreg, treg); | |
10206 | } | |
10207 | ||
f2ae14a1 RS |
10208 | /* Return the high part that should be loaded in order to make the low |
10209 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
10210 | ||
10211 | static offsetT | |
10212 | offset_high_part (offsetT value, unsigned int offbits) | |
10213 | { | |
10214 | offsetT bias; | |
10215 | addressT low_mask; | |
10216 | ||
10217 | if (offbits == 0) | |
10218 | return value; | |
10219 | bias = 1 << (offbits - 1); | |
10220 | low_mask = bias * 2 - 1; | |
10221 | return (value + bias) & ~low_mask; | |
10222 | } | |
10223 | ||
10224 | /* Return true if the value stored in offset_expr and offset_reloc | |
10225 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
10226 | amount that the caller wants to add without inducing overflow | |
10227 | and ALIGN is the known alignment of the value in bytes. */ | |
10228 | ||
10229 | static bfd_boolean | |
10230 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
10231 | { | |
10232 | if (offbits == 16) | |
10233 | { | |
10234 | /* Accept any relocation operator if overflow isn't a concern. */ | |
10235 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
10236 | return TRUE; | |
10237 | ||
10238 | /* These relocations are guaranteed not to overflow in correct links. */ | |
10239 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
10240 | || gprel16_reloc_p (*offset_reloc)) | |
10241 | return TRUE; | |
10242 | } | |
10243 | if (offset_expr.X_op == O_constant | |
10244 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
10245 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
10246 | return TRUE; | |
10247 | return FALSE; | |
10248 | } | |
10249 | ||
252b5132 RH |
10250 | /* |
10251 | * Build macros | |
10252 | * This routine implements the seemingly endless macro or synthesized | |
10253 | * instructions and addressing modes in the mips assembly language. Many | |
10254 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 10255 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
10256 | * this verbose method. Others are not simple macros but are more like |
10257 | * optimizing code generation. | |
10258 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 10259 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 10260 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
10261 | * of global optimization. We currently only optimize within a single macro. |
10262 | * For many of the load and store macros if the address is specified as a | |
10263 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
10264 | * first load register 'at' with zero and use it as the base register. The | |
10265 | * mips assembler simply uses register $zero. Just one tiny optimization | |
10266 | * we're missing. | |
10267 | */ | |
10268 | static void | |
833794fc | 10269 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 10270 | { |
c0ebe874 RS |
10271 | const struct mips_operand_array *operands; |
10272 | unsigned int breg, i; | |
741fe287 | 10273 | unsigned int tempreg; |
252b5132 | 10274 | int mask; |
43841e91 | 10275 | int used_at = 0; |
df58fc94 | 10276 | expressionS label_expr; |
252b5132 | 10277 | expressionS expr1; |
df58fc94 | 10278 | expressionS *ep; |
252b5132 RH |
10279 | const char *s; |
10280 | const char *s2; | |
10281 | const char *fmt; | |
10282 | int likely = 0; | |
252b5132 | 10283 | int coproc = 0; |
7f3c4072 | 10284 | int offbits = 16; |
1abe91b1 | 10285 | int call = 0; |
df58fc94 RS |
10286 | int jals = 0; |
10287 | int dbl = 0; | |
10288 | int imm = 0; | |
10289 | int ust = 0; | |
10290 | int lp = 0; | |
a45328b9 | 10291 | int ll_sc_paired = 0; |
f2ae14a1 | 10292 | bfd_boolean large_offset; |
252b5132 | 10293 | int off; |
252b5132 | 10294 | int hold_mips_optimize; |
f2ae14a1 | 10295 | unsigned int align; |
c0ebe874 | 10296 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 10297 | |
9c2799c2 | 10298 | gas_assert (! mips_opts.mips16); |
252b5132 | 10299 | |
c0ebe874 RS |
10300 | operands = insn_operands (ip); |
10301 | for (i = 0; i < MAX_OPERANDS; i++) | |
10302 | if (operands->operand[i]) | |
10303 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
10304 | else | |
10305 | op[i] = -1; | |
10306 | ||
252b5132 RH |
10307 | mask = ip->insn_mo->mask; |
10308 | ||
df58fc94 RS |
10309 | label_expr.X_op = O_constant; |
10310 | label_expr.X_op_symbol = NULL; | |
10311 | label_expr.X_add_symbol = NULL; | |
10312 | label_expr.X_add_number = 0; | |
10313 | ||
252b5132 RH |
10314 | expr1.X_op = O_constant; |
10315 | expr1.X_op_symbol = NULL; | |
10316 | expr1.X_add_symbol = NULL; | |
10317 | expr1.X_add_number = 1; | |
f2ae14a1 | 10318 | align = 1; |
252b5132 RH |
10319 | |
10320 | switch (mask) | |
10321 | { | |
10322 | case M_DABS: | |
10323 | dbl = 1; | |
1a0670f3 | 10324 | /* Fall through. */ |
252b5132 | 10325 | case M_ABS: |
df58fc94 RS |
10326 | /* bgez $a0,1f |
10327 | move v0,$a0 | |
10328 | sub v0,$zero,$a0 | |
10329 | 1: | |
10330 | */ | |
252b5132 | 10331 | |
7d10b47d | 10332 | start_noreorder (); |
252b5132 | 10333 | |
df58fc94 RS |
10334 | if (mips_opts.micromips) |
10335 | micromips_label_expr (&label_expr); | |
10336 | else | |
10337 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10338 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
10339 | if (op[0] == op[1]) | |
a605d2b3 | 10340 | macro_build (NULL, "nop", ""); |
252b5132 | 10341 | else |
c0ebe874 RS |
10342 | move_register (op[0], op[1]); |
10343 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
10344 | if (mips_opts.micromips) |
10345 | micromips_add_label (); | |
252b5132 | 10346 | |
7d10b47d | 10347 | end_noreorder (); |
8fc2e39e | 10348 | break; |
252b5132 RH |
10349 | |
10350 | case M_ADD_I: | |
10351 | s = "addi"; | |
10352 | s2 = "add"; | |
387e7624 FS |
10353 | if (ISA_IS_R6 (mips_opts.isa)) |
10354 | goto do_addi_i; | |
10355 | else | |
10356 | goto do_addi; | |
252b5132 RH |
10357 | case M_ADDU_I: |
10358 | s = "addiu"; | |
10359 | s2 = "addu"; | |
10360 | goto do_addi; | |
10361 | case M_DADD_I: | |
10362 | dbl = 1; | |
10363 | s = "daddi"; | |
10364 | s2 = "dadd"; | |
387e7624 | 10365 | if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa)) |
df58fc94 | 10366 | goto do_addi; |
b0e6f033 | 10367 | if (imm_expr.X_add_number >= -0x200 |
387e7624 FS |
10368 | && imm_expr.X_add_number < 0x200 |
10369 | && !ISA_IS_R6 (mips_opts.isa)) | |
df58fc94 | 10370 | { |
b0e6f033 RS |
10371 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
10372 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
10373 | break; |
10374 | } | |
10375 | goto do_addi_i; | |
252b5132 RH |
10376 | case M_DADDU_I: |
10377 | dbl = 1; | |
10378 | s = "daddiu"; | |
10379 | s2 = "daddu"; | |
10380 | do_addi: | |
b0e6f033 | 10381 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
10382 | && imm_expr.X_add_number < 0x8000) |
10383 | { | |
c0ebe874 | 10384 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 10385 | break; |
252b5132 | 10386 | } |
df58fc94 | 10387 | do_addi_i: |
8fc2e39e | 10388 | used_at = 1; |
67c0d1eb | 10389 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10390 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10391 | break; |
10392 | ||
10393 | case M_AND_I: | |
10394 | s = "andi"; | |
10395 | s2 = "and"; | |
10396 | goto do_bit; | |
10397 | case M_OR_I: | |
10398 | s = "ori"; | |
10399 | s2 = "or"; | |
10400 | goto do_bit; | |
10401 | case M_NOR_I: | |
10402 | s = ""; | |
10403 | s2 = "nor"; | |
10404 | goto do_bit; | |
10405 | case M_XOR_I: | |
10406 | s = "xori"; | |
10407 | s2 = "xor"; | |
10408 | do_bit: | |
b0e6f033 | 10409 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10410 | && imm_expr.X_add_number < 0x10000) |
10411 | { | |
10412 | if (mask != M_NOR_I) | |
c0ebe874 | 10413 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10414 | else |
10415 | { | |
67c0d1eb | 10416 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10417 | op[0], op[1], BFD_RELOC_LO16); |
10418 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10419 | } |
8fc2e39e | 10420 | break; |
252b5132 RH |
10421 | } |
10422 | ||
8fc2e39e | 10423 | used_at = 1; |
bad1aba3 | 10424 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10425 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10426 | break; |
10427 | ||
8b082fb1 TS |
10428 | case M_BALIGN: |
10429 | switch (imm_expr.X_add_number) | |
10430 | { | |
10431 | case 0: | |
10432 | macro_build (NULL, "nop", ""); | |
10433 | break; | |
10434 | case 2: | |
c0ebe874 | 10435 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10436 | break; |
03f66e8a MR |
10437 | case 1: |
10438 | case 3: | |
c0ebe874 | 10439 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10440 | (int) imm_expr.X_add_number); |
8b082fb1 | 10441 | break; |
03f66e8a MR |
10442 | default: |
10443 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10444 | (unsigned long) imm_expr.X_add_number); | |
10445 | break; | |
8b082fb1 TS |
10446 | } |
10447 | break; | |
10448 | ||
df58fc94 RS |
10449 | case M_BC1FL: |
10450 | case M_BC1TL: | |
10451 | case M_BC2FL: | |
10452 | case M_BC2TL: | |
10453 | gas_assert (mips_opts.micromips); | |
10454 | macro_build_branch_ccl (mask, &offset_expr, | |
10455 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10456 | break; | |
10457 | ||
252b5132 | 10458 | case M_BEQ_I: |
252b5132 | 10459 | case M_BEQL_I: |
252b5132 | 10460 | case M_BNE_I: |
252b5132 | 10461 | case M_BNEL_I: |
b0e6f033 | 10462 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10463 | op[1] = 0; |
df58fc94 | 10464 | else |
252b5132 | 10465 | { |
c0ebe874 | 10466 | op[1] = AT; |
df58fc94 | 10467 | used_at = 1; |
bad1aba3 | 10468 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10469 | } |
df58fc94 RS |
10470 | /* Fall through. */ |
10471 | case M_BEQL: | |
10472 | case M_BNEL: | |
c0ebe874 | 10473 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10474 | break; |
10475 | ||
10476 | case M_BGEL: | |
10477 | likely = 1; | |
1a0670f3 | 10478 | /* Fall through. */ |
252b5132 | 10479 | case M_BGE: |
c0ebe874 RS |
10480 | if (op[1] == 0) |
10481 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10482 | else if (op[0] == 0) | |
10483 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10484 | else |
252b5132 | 10485 | { |
df58fc94 | 10486 | used_at = 1; |
c0ebe874 | 10487 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10488 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10489 | &offset_expr, AT, ZERO); | |
252b5132 | 10490 | } |
df58fc94 RS |
10491 | break; |
10492 | ||
10493 | case M_BGEZL: | |
10494 | case M_BGEZALL: | |
10495 | case M_BGTZL: | |
10496 | case M_BLEZL: | |
10497 | case M_BLTZL: | |
10498 | case M_BLTZALL: | |
c0ebe874 | 10499 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10500 | break; |
10501 | ||
10502 | case M_BGTL_I: | |
10503 | likely = 1; | |
1a0670f3 | 10504 | /* Fall through. */ |
252b5132 | 10505 | case M_BGT_I: |
90ecf173 | 10506 | /* Check for > max integer. */ |
b0e6f033 | 10507 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10508 | { |
10509 | do_false: | |
90ecf173 | 10510 | /* Result is always false. */ |
252b5132 | 10511 | if (! likely) |
a605d2b3 | 10512 | macro_build (NULL, "nop", ""); |
252b5132 | 10513 | else |
df58fc94 | 10514 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10515 | break; |
252b5132 | 10516 | } |
f9419b05 | 10517 | ++imm_expr.X_add_number; |
6f2117ba | 10518 | /* Fall through. */ |
252b5132 RH |
10519 | case M_BGE_I: |
10520 | case M_BGEL_I: | |
10521 | if (mask == M_BGEL_I) | |
10522 | likely = 1; | |
b0e6f033 | 10523 | if (imm_expr.X_add_number == 0) |
252b5132 | 10524 | { |
df58fc94 | 10525 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10526 | &offset_expr, op[0]); |
8fc2e39e | 10527 | break; |
252b5132 | 10528 | } |
b0e6f033 | 10529 | if (imm_expr.X_add_number == 1) |
252b5132 | 10530 | { |
df58fc94 | 10531 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10532 | &offset_expr, op[0]); |
8fc2e39e | 10533 | break; |
252b5132 | 10534 | } |
b0e6f033 | 10535 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10536 | { |
10537 | do_true: | |
6f2117ba | 10538 | /* Result is always true. */ |
1661c76c | 10539 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10540 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10541 | break; |
252b5132 | 10542 | } |
8fc2e39e | 10543 | used_at = 1; |
c0ebe874 | 10544 | set_at (op[0], 0); |
df58fc94 RS |
10545 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10546 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10547 | break; |
10548 | ||
10549 | case M_BGEUL: | |
10550 | likely = 1; | |
1a0670f3 | 10551 | /* Fall through. */ |
252b5132 | 10552 | case M_BGEU: |
c0ebe874 | 10553 | if (op[1] == 0) |
252b5132 | 10554 | goto do_true; |
c0ebe874 | 10555 | else if (op[0] == 0) |
df58fc94 | 10556 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10557 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10558 | else |
252b5132 | 10559 | { |
df58fc94 | 10560 | used_at = 1; |
c0ebe874 | 10561 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10562 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10563 | &offset_expr, AT, ZERO); | |
252b5132 | 10564 | } |
252b5132 RH |
10565 | break; |
10566 | ||
10567 | case M_BGTUL_I: | |
10568 | likely = 1; | |
1a0670f3 | 10569 | /* Fall through. */ |
252b5132 | 10570 | case M_BGTU_I: |
c0ebe874 | 10571 | if (op[0] == 0 |
bad1aba3 | 10572 | || (GPR_SIZE == 32 |
f01dc953 | 10573 | && imm_expr.X_add_number == -1)) |
252b5132 | 10574 | goto do_false; |
f9419b05 | 10575 | ++imm_expr.X_add_number; |
6f2117ba | 10576 | /* Fall through. */ |
252b5132 RH |
10577 | case M_BGEU_I: |
10578 | case M_BGEUL_I: | |
10579 | if (mask == M_BGEUL_I) | |
10580 | likely = 1; | |
b0e6f033 | 10581 | if (imm_expr.X_add_number == 0) |
252b5132 | 10582 | goto do_true; |
b0e6f033 | 10583 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10584 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10585 | &offset_expr, op[0], ZERO); |
df58fc94 | 10586 | else |
252b5132 | 10587 | { |
df58fc94 | 10588 | used_at = 1; |
c0ebe874 | 10589 | set_at (op[0], 1); |
df58fc94 RS |
10590 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10591 | &offset_expr, AT, ZERO); | |
252b5132 | 10592 | } |
252b5132 RH |
10593 | break; |
10594 | ||
10595 | case M_BGTL: | |
10596 | likely = 1; | |
1a0670f3 | 10597 | /* Fall through. */ |
252b5132 | 10598 | case M_BGT: |
c0ebe874 RS |
10599 | if (op[1] == 0) |
10600 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10601 | else if (op[0] == 0) | |
10602 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10603 | else |
252b5132 | 10604 | { |
df58fc94 | 10605 | used_at = 1; |
c0ebe874 | 10606 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10607 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10608 | &offset_expr, AT, ZERO); | |
252b5132 | 10609 | } |
252b5132 RH |
10610 | break; |
10611 | ||
10612 | case M_BGTUL: | |
10613 | likely = 1; | |
1a0670f3 | 10614 | /* Fall through. */ |
252b5132 | 10615 | case M_BGTU: |
c0ebe874 | 10616 | if (op[1] == 0) |
df58fc94 | 10617 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10618 | &offset_expr, op[0], ZERO); |
10619 | else if (op[0] == 0) | |
df58fc94 RS |
10620 | goto do_false; |
10621 | else | |
252b5132 | 10622 | { |
df58fc94 | 10623 | used_at = 1; |
c0ebe874 | 10624 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10625 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10626 | &offset_expr, AT, ZERO); | |
252b5132 | 10627 | } |
252b5132 RH |
10628 | break; |
10629 | ||
10630 | case M_BLEL: | |
10631 | likely = 1; | |
1a0670f3 | 10632 | /* Fall through. */ |
252b5132 | 10633 | case M_BLE: |
c0ebe874 RS |
10634 | if (op[1] == 0) |
10635 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10636 | else if (op[0] == 0) | |
10637 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10638 | else |
252b5132 | 10639 | { |
df58fc94 | 10640 | used_at = 1; |
c0ebe874 | 10641 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10642 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10643 | &offset_expr, AT, ZERO); | |
252b5132 | 10644 | } |
252b5132 RH |
10645 | break; |
10646 | ||
10647 | case M_BLEL_I: | |
10648 | likely = 1; | |
1a0670f3 | 10649 | /* Fall through. */ |
252b5132 | 10650 | case M_BLE_I: |
b0e6f033 | 10651 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10652 | goto do_true; |
f9419b05 | 10653 | ++imm_expr.X_add_number; |
6f2117ba | 10654 | /* Fall through. */ |
252b5132 RH |
10655 | case M_BLT_I: |
10656 | case M_BLTL_I: | |
10657 | if (mask == M_BLTL_I) | |
10658 | likely = 1; | |
b0e6f033 | 10659 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10660 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10661 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10662 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10663 | else |
252b5132 | 10664 | { |
df58fc94 | 10665 | used_at = 1; |
c0ebe874 | 10666 | set_at (op[0], 0); |
df58fc94 RS |
10667 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10668 | &offset_expr, AT, ZERO); | |
252b5132 | 10669 | } |
252b5132 RH |
10670 | break; |
10671 | ||
10672 | case M_BLEUL: | |
10673 | likely = 1; | |
1a0670f3 | 10674 | /* Fall through. */ |
252b5132 | 10675 | case M_BLEU: |
c0ebe874 | 10676 | if (op[1] == 0) |
df58fc94 | 10677 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10678 | &offset_expr, op[0], ZERO); |
10679 | else if (op[0] == 0) | |
df58fc94 RS |
10680 | goto do_true; |
10681 | else | |
252b5132 | 10682 | { |
df58fc94 | 10683 | used_at = 1; |
c0ebe874 | 10684 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10685 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10686 | &offset_expr, AT, ZERO); | |
252b5132 | 10687 | } |
252b5132 RH |
10688 | break; |
10689 | ||
10690 | case M_BLEUL_I: | |
10691 | likely = 1; | |
1a0670f3 | 10692 | /* Fall through. */ |
252b5132 | 10693 | case M_BLEU_I: |
c0ebe874 | 10694 | if (op[0] == 0 |
bad1aba3 | 10695 | || (GPR_SIZE == 32 |
f01dc953 | 10696 | && imm_expr.X_add_number == -1)) |
252b5132 | 10697 | goto do_true; |
f9419b05 | 10698 | ++imm_expr.X_add_number; |
6f2117ba | 10699 | /* Fall through. */ |
252b5132 RH |
10700 | case M_BLTU_I: |
10701 | case M_BLTUL_I: | |
10702 | if (mask == M_BLTUL_I) | |
10703 | likely = 1; | |
b0e6f033 | 10704 | if (imm_expr.X_add_number == 0) |
252b5132 | 10705 | goto do_false; |
b0e6f033 | 10706 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10707 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10708 | &offset_expr, op[0], ZERO); |
df58fc94 | 10709 | else |
252b5132 | 10710 | { |
df58fc94 | 10711 | used_at = 1; |
c0ebe874 | 10712 | set_at (op[0], 1); |
df58fc94 RS |
10713 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10714 | &offset_expr, AT, ZERO); | |
252b5132 | 10715 | } |
252b5132 RH |
10716 | break; |
10717 | ||
10718 | case M_BLTL: | |
10719 | likely = 1; | |
1a0670f3 | 10720 | /* Fall through. */ |
252b5132 | 10721 | case M_BLT: |
c0ebe874 RS |
10722 | if (op[1] == 0) |
10723 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10724 | else if (op[0] == 0) | |
10725 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10726 | else |
252b5132 | 10727 | { |
df58fc94 | 10728 | used_at = 1; |
c0ebe874 | 10729 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10730 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10731 | &offset_expr, AT, ZERO); | |
252b5132 | 10732 | } |
252b5132 RH |
10733 | break; |
10734 | ||
10735 | case M_BLTUL: | |
10736 | likely = 1; | |
1a0670f3 | 10737 | /* Fall through. */ |
252b5132 | 10738 | case M_BLTU: |
c0ebe874 | 10739 | if (op[1] == 0) |
252b5132 | 10740 | goto do_false; |
c0ebe874 | 10741 | else if (op[0] == 0) |
df58fc94 | 10742 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10743 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10744 | else |
252b5132 | 10745 | { |
df58fc94 | 10746 | used_at = 1; |
c0ebe874 | 10747 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10748 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10749 | &offset_expr, AT, ZERO); | |
252b5132 | 10750 | } |
252b5132 RH |
10751 | break; |
10752 | ||
10753 | case M_DDIV_3: | |
10754 | dbl = 1; | |
1a0670f3 | 10755 | /* Fall through. */ |
252b5132 RH |
10756 | case M_DIV_3: |
10757 | s = "mflo"; | |
10758 | goto do_div3; | |
10759 | case M_DREM_3: | |
10760 | dbl = 1; | |
1a0670f3 | 10761 | /* Fall through. */ |
252b5132 RH |
10762 | case M_REM_3: |
10763 | s = "mfhi"; | |
10764 | do_div3: | |
c0ebe874 | 10765 | if (op[2] == 0) |
252b5132 | 10766 | { |
1661c76c | 10767 | as_warn (_("divide by zero")); |
252b5132 | 10768 | if (mips_trap) |
df58fc94 | 10769 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10770 | else |
df58fc94 | 10771 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10772 | break; |
252b5132 RH |
10773 | } |
10774 | ||
7d10b47d | 10775 | start_noreorder (); |
252b5132 RH |
10776 | if (mips_trap) |
10777 | { | |
c0ebe874 RS |
10778 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10779 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10780 | } |
10781 | else | |
10782 | { | |
df58fc94 RS |
10783 | if (mips_opts.micromips) |
10784 | micromips_label_expr (&label_expr); | |
10785 | else | |
10786 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10787 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10788 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10789 | macro_build (NULL, "break", BRK_FMT, 7); |
10790 | if (mips_opts.micromips) | |
10791 | micromips_add_label (); | |
252b5132 RH |
10792 | } |
10793 | expr1.X_add_number = -1; | |
8fc2e39e | 10794 | used_at = 1; |
f6a22291 | 10795 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10796 | if (mips_opts.micromips) |
10797 | micromips_label_expr (&label_expr); | |
10798 | else | |
10799 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10800 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10801 | if (dbl) |
10802 | { | |
10803 | expr1.X_add_number = 1; | |
f6a22291 | 10804 | load_register (AT, &expr1, dbl); |
df58fc94 | 10805 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10806 | } |
10807 | else | |
10808 | { | |
10809 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10810 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10811 | } |
10812 | if (mips_trap) | |
10813 | { | |
c0ebe874 | 10814 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10815 | /* We want to close the noreorder block as soon as possible, so |
10816 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10817 | end_noreorder (); |
252b5132 RH |
10818 | } |
10819 | else | |
10820 | { | |
df58fc94 RS |
10821 | if (mips_opts.micromips) |
10822 | micromips_label_expr (&label_expr); | |
10823 | else | |
10824 | label_expr.X_add_number = 8; | |
c0ebe874 | 10825 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10826 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10827 | |
10828 | /* We want to close the noreorder block as soon as possible, so | |
10829 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10830 | end_noreorder (); |
252b5132 | 10831 | |
df58fc94 | 10832 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10833 | } |
df58fc94 RS |
10834 | if (mips_opts.micromips) |
10835 | micromips_add_label (); | |
c0ebe874 | 10836 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10837 | break; |
10838 | ||
10839 | case M_DIV_3I: | |
10840 | s = "div"; | |
10841 | s2 = "mflo"; | |
10842 | goto do_divi; | |
10843 | case M_DIVU_3I: | |
10844 | s = "divu"; | |
10845 | s2 = "mflo"; | |
10846 | goto do_divi; | |
10847 | case M_REM_3I: | |
10848 | s = "div"; | |
10849 | s2 = "mfhi"; | |
10850 | goto do_divi; | |
10851 | case M_REMU_3I: | |
10852 | s = "divu"; | |
10853 | s2 = "mfhi"; | |
10854 | goto do_divi; | |
10855 | case M_DDIV_3I: | |
10856 | dbl = 1; | |
10857 | s = "ddiv"; | |
10858 | s2 = "mflo"; | |
10859 | goto do_divi; | |
10860 | case M_DDIVU_3I: | |
10861 | dbl = 1; | |
10862 | s = "ddivu"; | |
10863 | s2 = "mflo"; | |
10864 | goto do_divi; | |
10865 | case M_DREM_3I: | |
10866 | dbl = 1; | |
10867 | s = "ddiv"; | |
10868 | s2 = "mfhi"; | |
10869 | goto do_divi; | |
10870 | case M_DREMU_3I: | |
10871 | dbl = 1; | |
10872 | s = "ddivu"; | |
10873 | s2 = "mfhi"; | |
10874 | do_divi: | |
b0e6f033 | 10875 | if (imm_expr.X_add_number == 0) |
252b5132 | 10876 | { |
1661c76c | 10877 | as_warn (_("divide by zero")); |
252b5132 | 10878 | if (mips_trap) |
df58fc94 | 10879 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10880 | else |
df58fc94 | 10881 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10882 | break; |
252b5132 | 10883 | } |
b0e6f033 | 10884 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10885 | { |
10886 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10887 | move_register (op[0], op[1]); |
252b5132 | 10888 | else |
c0ebe874 | 10889 | move_register (op[0], ZERO); |
8fc2e39e | 10890 | break; |
252b5132 | 10891 | } |
b0e6f033 | 10892 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10893 | { |
10894 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10895 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10896 | else |
c0ebe874 | 10897 | move_register (op[0], ZERO); |
8fc2e39e | 10898 | break; |
252b5132 RH |
10899 | } |
10900 | ||
8fc2e39e | 10901 | used_at = 1; |
67c0d1eb | 10902 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10903 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10904 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10905 | break; |
10906 | ||
10907 | case M_DIVU_3: | |
10908 | s = "divu"; | |
10909 | s2 = "mflo"; | |
10910 | goto do_divu3; | |
10911 | case M_REMU_3: | |
10912 | s = "divu"; | |
10913 | s2 = "mfhi"; | |
10914 | goto do_divu3; | |
10915 | case M_DDIVU_3: | |
10916 | s = "ddivu"; | |
10917 | s2 = "mflo"; | |
10918 | goto do_divu3; | |
10919 | case M_DREMU_3: | |
10920 | s = "ddivu"; | |
10921 | s2 = "mfhi"; | |
10922 | do_divu3: | |
7d10b47d | 10923 | start_noreorder (); |
252b5132 RH |
10924 | if (mips_trap) |
10925 | { | |
c0ebe874 RS |
10926 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10927 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10928 | /* We want to close the noreorder block as soon as possible, so |
10929 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10930 | end_noreorder (); |
252b5132 RH |
10931 | } |
10932 | else | |
10933 | { | |
df58fc94 RS |
10934 | if (mips_opts.micromips) |
10935 | micromips_label_expr (&label_expr); | |
10936 | else | |
10937 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10938 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10939 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10940 | |
10941 | /* We want to close the noreorder block as soon as possible, so | |
10942 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10943 | end_noreorder (); |
df58fc94 RS |
10944 | macro_build (NULL, "break", BRK_FMT, 7); |
10945 | if (mips_opts.micromips) | |
10946 | micromips_add_label (); | |
252b5132 | 10947 | } |
c0ebe874 | 10948 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10949 | break; |
252b5132 | 10950 | |
1abe91b1 MR |
10951 | case M_DLCA_AB: |
10952 | dbl = 1; | |
1a0670f3 | 10953 | /* Fall through. */ |
1abe91b1 MR |
10954 | case M_LCA_AB: |
10955 | call = 1; | |
10956 | goto do_la; | |
252b5132 RH |
10957 | case M_DLA_AB: |
10958 | dbl = 1; | |
1a0670f3 | 10959 | /* Fall through. */ |
252b5132 | 10960 | case M_LA_AB: |
1abe91b1 | 10961 | do_la: |
252b5132 RH |
10962 | /* Load the address of a symbol into a register. If breg is not |
10963 | zero, we then add a base register to it. */ | |
10964 | ||
c0ebe874 | 10965 | breg = op[2]; |
bad1aba3 | 10966 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10967 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10968 | "instead")); | |
3bec30a8 | 10969 | |
90ecf173 | 10970 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10971 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10972 | "instead")); | |
3bec30a8 | 10973 | |
f2ae14a1 | 10974 | if (small_offset_p (0, align, 16)) |
0c11417f | 10975 | { |
c0ebe874 | 10976 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10977 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10978 | break; |
0c11417f MR |
10979 | } |
10980 | ||
c0ebe874 | 10981 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10982 | { |
10983 | tempreg = AT; | |
10984 | used_at = 1; | |
10985 | } | |
10986 | else | |
c0ebe874 | 10987 | tempreg = op[0]; |
afdbd6d0 | 10988 | |
252b5132 RH |
10989 | if (offset_expr.X_op != O_symbol |
10990 | && offset_expr.X_op != O_constant) | |
10991 | { | |
1661c76c | 10992 | as_bad (_("expression too complex")); |
252b5132 RH |
10993 | offset_expr.X_op = O_constant; |
10994 | } | |
10995 | ||
252b5132 | 10996 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10997 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10998 | else if (mips_pic == NO_PIC) |
10999 | { | |
d6bc6245 | 11000 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 11001 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
11002 | Otherwise we want |
11003 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11004 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11005 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 11006 | so we may as well always use the latter form. |
76b3015f | 11007 | |
6caf9ef4 TS |
11008 | With 64bit address space and a usable $at we want |
11009 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11010 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11011 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11012 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
11013 | dsll32 $tempreg,0 | |
11014 | daddu $tempreg,$tempreg,$at | |
11015 | ||
11016 | If $at is already in use, we use a path which is suboptimal | |
11017 | on superscalar processors. | |
11018 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11019 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11020 | dsll $tempreg,16 | |
11021 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11022 | dsll $tempreg,16 | |
11023 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
11024 | ||
11025 | For GP relative symbols in 64bit address space we can use | |
11026 | the same sequence as in 32bit address space. */ | |
aed1a261 | 11027 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 11028 | { |
6caf9ef4 TS |
11029 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
11030 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
11031 | { | |
11032 | relax_start (offset_expr.X_add_symbol); | |
11033 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11034 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
11035 | relax_switch (); | |
11036 | } | |
d6bc6245 | 11037 | |
741fe287 | 11038 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 11039 | { |
df58fc94 | 11040 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11041 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 11042 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11043 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 11044 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11045 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 11046 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11047 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 11048 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 11049 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
11050 | used_at = 1; |
11051 | } | |
11052 | else | |
11053 | { | |
df58fc94 | 11054 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11055 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 11056 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11057 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 11058 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 11059 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11060 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 11061 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 11062 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11063 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 11064 | } |
6caf9ef4 TS |
11065 | |
11066 | if (mips_relax.sequence) | |
11067 | relax_end (); | |
98d3f06f KH |
11068 | } |
11069 | else | |
11070 | { | |
11071 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 11072 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 11073 | { |
4d7206a2 | 11074 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11075 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11076 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 11077 | relax_switch (); |
98d3f06f | 11078 | } |
6943caf0 | 11079 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 11080 | as_bad (_("offset too large")); |
67c0d1eb RS |
11081 | macro_build_lui (&offset_expr, tempreg); |
11082 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11083 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
11084 | if (mips_relax.sequence) |
11085 | relax_end (); | |
98d3f06f | 11086 | } |
252b5132 | 11087 | } |
0a44bf69 | 11088 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 11089 | { |
9117d219 NC |
11090 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
11091 | ||
252b5132 RH |
11092 | /* If this is a reference to an external symbol, and there |
11093 | is no constant, we want | |
11094 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 11095 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 11096 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
11097 | For a local symbol, we want |
11098 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11099 | nop | |
11100 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11101 | ||
11102 | If we have a small constant, and this is a reference to | |
11103 | an external symbol, we want | |
11104 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11105 | nop | |
11106 | addiu $tempreg,$tempreg,<constant> | |
11107 | For a local symbol, we want the same instruction | |
11108 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
11109 | addiu instruction. | |
11110 | ||
11111 | If we have a large constant, and this is a reference to | |
11112 | an external symbol, we want | |
11113 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11114 | lui $at,<hiconstant> | |
11115 | addiu $at,$at,<loconstant> | |
11116 | addu $tempreg,$tempreg,$at | |
11117 | For a local symbol, we want the same instruction | |
11118 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 11119 | addiu instruction. |
ed6fb7bd SC |
11120 | */ |
11121 | ||
4d7206a2 | 11122 | if (offset_expr.X_add_number == 0) |
252b5132 | 11123 | { |
0a44bf69 RS |
11124 | if (mips_pic == SVR4_PIC |
11125 | && breg == 0 | |
11126 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
11127 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
11128 | ||
11129 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
11130 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11131 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 11132 | if (breg != 0) |
252b5132 RH |
11133 | { |
11134 | /* We're going to put in an addu instruction using | |
11135 | tempreg, so we may as well insert the nop right | |
11136 | now. */ | |
269137b2 | 11137 | load_delay_nop (); |
252b5132 | 11138 | } |
4d7206a2 | 11139 | relax_switch (); |
67c0d1eb RS |
11140 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11141 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 11142 | load_delay_nop (); |
67c0d1eb RS |
11143 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11144 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 11145 | relax_end (); |
252b5132 RH |
11146 | /* FIXME: If breg == 0, and the next instruction uses |
11147 | $tempreg, then if this variant case is used an extra | |
11148 | nop will be generated. */ | |
11149 | } | |
4d7206a2 RS |
11150 | else if (offset_expr.X_add_number >= -0x8000 |
11151 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 11152 | { |
67c0d1eb | 11153 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 11154 | load_delay_nop (); |
67c0d1eb | 11155 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
11156 | } |
11157 | else | |
11158 | { | |
4d7206a2 RS |
11159 | expr1.X_add_number = offset_expr.X_add_number; |
11160 | offset_expr.X_add_number = | |
43c0598f | 11161 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 11162 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 11163 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
11164 | /* If we are going to add in a base register, and the |
11165 | target register and the base register are the same, | |
11166 | then we are using AT as a temporary register. Since | |
11167 | we want to load the constant into AT, we add our | |
11168 | current AT (from the global offset table) and the | |
11169 | register into the register now, and pretend we were | |
11170 | not using a base register. */ | |
c0ebe874 | 11171 | if (breg == op[0]) |
252b5132 | 11172 | { |
269137b2 | 11173 | load_delay_nop (); |
67c0d1eb | 11174 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11175 | op[0], AT, breg); |
252b5132 | 11176 | breg = 0; |
c0ebe874 | 11177 | tempreg = op[0]; |
252b5132 | 11178 | } |
f6a22291 | 11179 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
11180 | used_at = 1; |
11181 | } | |
11182 | } | |
0a44bf69 | 11183 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 11184 | { |
67c0d1eb | 11185 | int add_breg_early = 0; |
f5040a92 AO |
11186 | |
11187 | /* If this is a reference to an external, and there is no | |
11188 | constant, or local symbol (*), with or without a | |
11189 | constant, we want | |
11190 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 11191 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11192 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
11193 | ||
11194 | If we have a small constant, and this is a reference to | |
11195 | an external symbol, we want | |
11196 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11197 | addiu $tempreg,$tempreg,<constant> | |
11198 | ||
11199 | If we have a large constant, and this is a reference to | |
11200 | an external symbol, we want | |
11201 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11202 | lui $at,<hiconstant> | |
11203 | addiu $at,$at,<loconstant> | |
11204 | addu $tempreg,$tempreg,$at | |
11205 | ||
11206 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
11207 | local symbols, even though it introduces an additional | |
11208 | instruction. */ | |
11209 | ||
f5040a92 AO |
11210 | if (offset_expr.X_add_number) |
11211 | { | |
4d7206a2 | 11212 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11213 | offset_expr.X_add_number = 0; |
11214 | ||
4d7206a2 | 11215 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11216 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11217 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11218 | |
11219 | if (expr1.X_add_number >= -0x8000 | |
11220 | && expr1.X_add_number < 0x8000) | |
11221 | { | |
67c0d1eb RS |
11222 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
11223 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 11224 | } |
ecd13cd3 | 11225 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11226 | { |
c0ebe874 RS |
11227 | unsigned int dreg; |
11228 | ||
f5040a92 AO |
11229 | /* If we are going to add in a base register, and the |
11230 | target register and the base register are the same, | |
11231 | then we are using AT as a temporary register. Since | |
11232 | we want to load the constant into AT, we add our | |
11233 | current AT (from the global offset table) and the | |
11234 | register into the register now, and pretend we were | |
11235 | not using a base register. */ | |
c0ebe874 | 11236 | if (breg != op[0]) |
f5040a92 AO |
11237 | dreg = tempreg; |
11238 | else | |
11239 | { | |
9c2799c2 | 11240 | gas_assert (tempreg == AT); |
67c0d1eb | 11241 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11242 | op[0], AT, breg); |
11243 | dreg = op[0]; | |
67c0d1eb | 11244 | add_breg_early = 1; |
f5040a92 AO |
11245 | } |
11246 | ||
f6a22291 | 11247 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11248 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11249 | dreg, dreg, AT); |
f5040a92 | 11250 | |
f5040a92 AO |
11251 | used_at = 1; |
11252 | } | |
11253 | else | |
11254 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11255 | ||
4d7206a2 | 11256 | relax_switch (); |
f5040a92 AO |
11257 | offset_expr.X_add_number = expr1.X_add_number; |
11258 | ||
67c0d1eb RS |
11259 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11260 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
11261 | if (add_breg_early) | |
f5040a92 | 11262 | { |
67c0d1eb | 11263 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11264 | op[0], tempreg, breg); |
f5040a92 | 11265 | breg = 0; |
c0ebe874 | 11266 | tempreg = op[0]; |
f5040a92 | 11267 | } |
4d7206a2 | 11268 | relax_end (); |
f5040a92 | 11269 | } |
4d7206a2 | 11270 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 11271 | { |
4d7206a2 | 11272 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11273 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11274 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 11275 | relax_switch (); |
67c0d1eb RS |
11276 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11277 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 11278 | relax_end (); |
f5040a92 | 11279 | } |
4d7206a2 | 11280 | else |
f5040a92 | 11281 | { |
67c0d1eb RS |
11282 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11283 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11284 | } |
11285 | } | |
0a44bf69 | 11286 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11287 | { |
67c0d1eb | 11288 | int gpdelay; |
9117d219 NC |
11289 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11290 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 11291 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
11292 | |
11293 | /* This is the large GOT case. If this is a reference to an | |
11294 | external symbol, and there is no constant, we want | |
11295 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11296 | addu $tempreg,$tempreg,$gp | |
11297 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11298 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
11299 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11300 | addu $tempreg,$tempreg,$gp | |
11301 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
11302 | For a local symbol, we want |
11303 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11304 | nop | |
11305 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11306 | ||
11307 | If we have a small constant, and this is a reference to | |
11308 | an external symbol, we want | |
11309 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11310 | addu $tempreg,$tempreg,$gp | |
11311 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11312 | nop | |
11313 | addiu $tempreg,$tempreg,<constant> | |
11314 | For a local symbol, we want | |
11315 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11316 | nop | |
11317 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
11318 | ||
11319 | If we have a large constant, and this is a reference to | |
11320 | an external symbol, we want | |
11321 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11322 | addu $tempreg,$tempreg,$gp | |
11323 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11324 | lui $at,<hiconstant> | |
11325 | addiu $at,$at,<loconstant> | |
11326 | addu $tempreg,$tempreg,$at | |
11327 | For a local symbol, we want | |
11328 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11329 | lui $at,<hiconstant> | |
11330 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
11331 | addu $tempreg,$tempreg,$at | |
f5040a92 | 11332 | */ |
438c16b8 | 11333 | |
252b5132 RH |
11334 | expr1.X_add_number = offset_expr.X_add_number; |
11335 | offset_expr.X_add_number = 0; | |
4d7206a2 | 11336 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11337 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
11338 | if (expr1.X_add_number == 0 && breg == 0 |
11339 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
11340 | { |
11341 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11342 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11343 | } | |
df58fc94 | 11344 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11345 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11346 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 11347 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 11348 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
11349 | if (expr1.X_add_number == 0) |
11350 | { | |
67c0d1eb | 11351 | if (breg != 0) |
252b5132 RH |
11352 | { |
11353 | /* We're going to put in an addu instruction using | |
11354 | tempreg, so we may as well insert the nop right | |
11355 | now. */ | |
269137b2 | 11356 | load_delay_nop (); |
252b5132 | 11357 | } |
252b5132 RH |
11358 | } |
11359 | else if (expr1.X_add_number >= -0x8000 | |
11360 | && expr1.X_add_number < 0x8000) | |
11361 | { | |
269137b2 | 11362 | load_delay_nop (); |
67c0d1eb | 11363 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11364 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
11365 | } |
11366 | else | |
11367 | { | |
c0ebe874 RS |
11368 | unsigned int dreg; |
11369 | ||
252b5132 RH |
11370 | /* If we are going to add in a base register, and the |
11371 | target register and the base register are the same, | |
11372 | then we are using AT as a temporary register. Since | |
11373 | we want to load the constant into AT, we add our | |
11374 | current AT (from the global offset table) and the | |
11375 | register into the register now, and pretend we were | |
11376 | not using a base register. */ | |
c0ebe874 | 11377 | if (breg != op[0]) |
67c0d1eb | 11378 | dreg = tempreg; |
252b5132 RH |
11379 | else |
11380 | { | |
9c2799c2 | 11381 | gas_assert (tempreg == AT); |
269137b2 | 11382 | load_delay_nop (); |
67c0d1eb | 11383 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11384 | op[0], AT, breg); |
11385 | dreg = op[0]; | |
252b5132 RH |
11386 | } |
11387 | ||
f6a22291 | 11388 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11389 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11390 | |
252b5132 RH |
11391 | used_at = 1; |
11392 | } | |
43c0598f | 11393 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11394 | relax_switch (); |
252b5132 | 11395 | |
67c0d1eb | 11396 | if (gpdelay) |
252b5132 RH |
11397 | { |
11398 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11399 | the first instruction on the main stream does not. */ |
67c0d1eb | 11400 | macro_build (NULL, "nop", ""); |
252b5132 | 11401 | } |
ed6fb7bd | 11402 | |
67c0d1eb RS |
11403 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11404 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11405 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11406 | && expr1.X_add_number < 0x8000) |
11407 | { | |
269137b2 | 11408 | load_delay_nop (); |
67c0d1eb RS |
11409 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11410 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11411 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11412 | register, the external symbol case ended with a load, |
11413 | so if the symbol turns out to not be external, and | |
11414 | the next instruction uses tempreg, an unnecessary nop | |
11415 | will be inserted. */ | |
252b5132 RH |
11416 | } |
11417 | else | |
11418 | { | |
c0ebe874 | 11419 | if (breg == op[0]) |
252b5132 RH |
11420 | { |
11421 | /* We must add in the base register now, as in the | |
f5040a92 | 11422 | external symbol case. */ |
9c2799c2 | 11423 | gas_assert (tempreg == AT); |
269137b2 | 11424 | load_delay_nop (); |
67c0d1eb | 11425 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11426 | op[0], AT, breg); |
11427 | tempreg = op[0]; | |
252b5132 | 11428 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11429 | it in in both cases. */ |
252b5132 RH |
11430 | breg = 0; |
11431 | } | |
11432 | ||
67c0d1eb RS |
11433 | macro_build_lui (&expr1, AT); |
11434 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11435 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11436 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11437 | tempreg, tempreg, AT); |
8fc2e39e | 11438 | used_at = 1; |
252b5132 | 11439 | } |
4d7206a2 | 11440 | relax_end (); |
252b5132 | 11441 | } |
0a44bf69 | 11442 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11443 | { |
f5040a92 AO |
11444 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11445 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11446 | int add_breg_early = 0; |
f5040a92 AO |
11447 | |
11448 | /* This is the large GOT case. If this is a reference to an | |
11449 | external symbol, and there is no constant, we want | |
11450 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11451 | add $tempreg,$tempreg,$gp | |
11452 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11453 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11454 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11455 | add $tempreg,$tempreg,$gp | |
11456 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11457 | ||
11458 | If we have a small constant, and this is a reference to | |
11459 | an external symbol, we want | |
11460 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11461 | add $tempreg,$tempreg,$gp | |
11462 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11463 | addi $tempreg,$tempreg,<constant> | |
11464 | ||
11465 | If we have a large constant, and this is a reference to | |
11466 | an external symbol, we want | |
11467 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11468 | addu $tempreg,$tempreg,$gp | |
11469 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11470 | lui $at,<hiconstant> | |
11471 | addi $at,$at,<loconstant> | |
11472 | add $tempreg,$tempreg,$at | |
11473 | ||
11474 | If we have NewABI, and we know it's a local symbol, we want | |
11475 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11476 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11477 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11478 | ||
4d7206a2 | 11479 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11480 | |
4d7206a2 | 11481 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11482 | offset_expr.X_add_number = 0; |
11483 | ||
1abe91b1 MR |
11484 | if (expr1.X_add_number == 0 && breg == 0 |
11485 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11486 | { |
11487 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11488 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11489 | } | |
df58fc94 | 11490 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11491 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11492 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11493 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11494 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11495 | |
11496 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11497 | ; |
f5040a92 AO |
11498 | else if (expr1.X_add_number >= -0x8000 |
11499 | && expr1.X_add_number < 0x8000) | |
11500 | { | |
67c0d1eb | 11501 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11502 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11503 | } |
ecd13cd3 | 11504 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11505 | { |
c0ebe874 RS |
11506 | unsigned int dreg; |
11507 | ||
f5040a92 AO |
11508 | /* If we are going to add in a base register, and the |
11509 | target register and the base register are the same, | |
11510 | then we are using AT as a temporary register. Since | |
11511 | we want to load the constant into AT, we add our | |
11512 | current AT (from the global offset table) and the | |
11513 | register into the register now, and pretend we were | |
11514 | not using a base register. */ | |
c0ebe874 | 11515 | if (breg != op[0]) |
f5040a92 AO |
11516 | dreg = tempreg; |
11517 | else | |
11518 | { | |
9c2799c2 | 11519 | gas_assert (tempreg == AT); |
67c0d1eb | 11520 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11521 | op[0], AT, breg); |
11522 | dreg = op[0]; | |
67c0d1eb | 11523 | add_breg_early = 1; |
f5040a92 AO |
11524 | } |
11525 | ||
f6a22291 | 11526 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11527 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11528 | |
f5040a92 AO |
11529 | used_at = 1; |
11530 | } | |
11531 | else | |
11532 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11533 | ||
4d7206a2 | 11534 | relax_switch (); |
f5040a92 | 11535 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11536 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11537 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11538 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11539 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11540 | if (add_breg_early) | |
f5040a92 | 11541 | { |
67c0d1eb | 11542 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11543 | op[0], tempreg, breg); |
f5040a92 | 11544 | breg = 0; |
c0ebe874 | 11545 | tempreg = op[0]; |
f5040a92 | 11546 | } |
4d7206a2 | 11547 | relax_end (); |
f5040a92 | 11548 | } |
252b5132 RH |
11549 | else |
11550 | abort (); | |
11551 | ||
11552 | if (breg != 0) | |
c0ebe874 | 11553 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11554 | break; |
11555 | ||
52b6b6b9 | 11556 | case M_MSGSND: |
df58fc94 | 11557 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11558 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11559 | break; |
52b6b6b9 JM |
11560 | |
11561 | case M_MSGLD: | |
df58fc94 | 11562 | gas_assert (!mips_opts.micromips); |
c8276761 | 11563 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11564 | break; |
52b6b6b9 JM |
11565 | |
11566 | case M_MSGLD_T: | |
df58fc94 | 11567 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11568 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11569 | break; |
52b6b6b9 JM |
11570 | |
11571 | case M_MSGWAIT: | |
df58fc94 | 11572 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11573 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11574 | break; |
52b6b6b9 JM |
11575 | |
11576 | case M_MSGWAIT_T: | |
df58fc94 | 11577 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11578 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11579 | break; |
52b6b6b9 | 11580 | |
252b5132 RH |
11581 | case M_J_A: |
11582 | /* The j instruction may not be used in PIC code, since it | |
11583 | requires an absolute address. We convert it to a b | |
11584 | instruction. */ | |
11585 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11586 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11587 | else |
67c0d1eb | 11588 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11589 | break; |
252b5132 RH |
11590 | |
11591 | /* The jal instructions must be handled as macros because when | |
11592 | generating PIC code they expand to multi-instruction | |
11593 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11594 | case M_JALS_1: |
c0ebe874 RS |
11595 | op[1] = op[0]; |
11596 | op[0] = RA; | |
df58fc94 RS |
11597 | /* Fall through. */ |
11598 | case M_JALS_2: | |
11599 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11600 | if (mips_opts.insn32) |
11601 | { | |
1661c76c | 11602 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11603 | break; |
11604 | } | |
df58fc94 RS |
11605 | jals = 1; |
11606 | goto jal; | |
252b5132 | 11607 | case M_JAL_1: |
c0ebe874 RS |
11608 | op[1] = op[0]; |
11609 | op[0] = RA; | |
252b5132 RH |
11610 | /* Fall through. */ |
11611 | case M_JAL_2: | |
df58fc94 | 11612 | jal: |
3e722fb5 | 11613 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11614 | { |
11615 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11616 | if (mips_opts.micromips |
833794fc | 11617 | && !mips_opts.insn32 |
c0ebe874 | 11618 | && op[0] == RA |
e64af278 | 11619 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11620 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11621 | else |
c0ebe874 | 11622 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11623 | } |
0a44bf69 | 11624 | else |
252b5132 | 11625 | { |
df58fc94 RS |
11626 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11627 | && mips_cprestore_offset >= 0); | |
11628 | ||
c0ebe874 | 11629 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11630 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11631 | |
833794fc MR |
11632 | s = ((mips_opts.micromips |
11633 | && !mips_opts.insn32 | |
11634 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11635 | ? "jalrs" : "jalr"); |
e64af278 | 11636 | if (mips_opts.micromips |
833794fc | 11637 | && !mips_opts.insn32 |
c0ebe874 | 11638 | && op[0] == RA |
e64af278 | 11639 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11640 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11641 | else |
c0ebe874 | 11642 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11643 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11644 | { |
6478892d | 11645 | if (mips_cprestore_offset < 0) |
1661c76c | 11646 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11647 | else |
11648 | { | |
90ecf173 | 11649 | if (!mips_frame_reg_valid) |
7a621144 | 11650 | { |
1661c76c | 11651 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11652 | /* Quiet this warning. */ |
11653 | mips_frame_reg_valid = 1; | |
11654 | } | |
90ecf173 | 11655 | if (!mips_cprestore_valid) |
7a621144 | 11656 | { |
1661c76c | 11657 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11658 | /* Quiet this warning. */ |
11659 | mips_cprestore_valid = 1; | |
11660 | } | |
d3fca0b5 MR |
11661 | if (mips_opts.noreorder) |
11662 | macro_build (NULL, "nop", ""); | |
6478892d | 11663 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11664 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11665 | mips_gp_register, |
256ab948 TS |
11666 | mips_frame_reg, |
11667 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11668 | } |
252b5132 RH |
11669 | } |
11670 | } | |
252b5132 | 11671 | |
8fc2e39e | 11672 | break; |
252b5132 | 11673 | |
df58fc94 RS |
11674 | case M_JALS_A: |
11675 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11676 | if (mips_opts.insn32) |
11677 | { | |
1661c76c | 11678 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11679 | break; |
11680 | } | |
df58fc94 RS |
11681 | jals = 1; |
11682 | /* Fall through. */ | |
252b5132 RH |
11683 | case M_JAL_A: |
11684 | if (mips_pic == NO_PIC) | |
df58fc94 | 11685 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11686 | else if (mips_pic == SVR4_PIC) |
11687 | { | |
11688 | /* If this is a reference to an external symbol, and we are | |
11689 | using a small GOT, we want | |
11690 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11691 | nop | |
f9419b05 | 11692 | jalr $ra,$25 |
252b5132 RH |
11693 | nop |
11694 | lw $gp,cprestore($sp) | |
11695 | The cprestore value is set using the .cprestore | |
11696 | pseudo-op. If we are using a big GOT, we want | |
11697 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11698 | addu $25,$25,$gp | |
11699 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11700 | nop | |
f9419b05 | 11701 | jalr $ra,$25 |
252b5132 RH |
11702 | nop |
11703 | lw $gp,cprestore($sp) | |
11704 | If the symbol is not external, we want | |
11705 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11706 | nop | |
11707 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11708 | jalr $ra,$25 |
252b5132 | 11709 | nop |
438c16b8 | 11710 | lw $gp,cprestore($sp) |
f5040a92 AO |
11711 | |
11712 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11713 | sequences above, minus nops, unless the symbol is local, | |
11714 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11715 | GOT_DISP. */ | |
438c16b8 | 11716 | if (HAVE_NEWABI) |
252b5132 | 11717 | { |
90ecf173 | 11718 | if (!mips_big_got) |
f5040a92 | 11719 | { |
4d7206a2 | 11720 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11721 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11722 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11723 | mips_gp_register); |
4d7206a2 | 11724 | relax_switch (); |
67c0d1eb RS |
11725 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11726 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11727 | mips_gp_register); |
11728 | relax_end (); | |
f5040a92 AO |
11729 | } |
11730 | else | |
11731 | { | |
4d7206a2 | 11732 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11733 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11734 | BFD_RELOC_MIPS_CALL_HI16); |
11735 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11736 | PIC_CALL_REG, mips_gp_register); | |
11737 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11738 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11739 | PIC_CALL_REG); | |
4d7206a2 | 11740 | relax_switch (); |
67c0d1eb RS |
11741 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11742 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11743 | mips_gp_register); | |
11744 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11745 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11746 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11747 | relax_end (); |
f5040a92 | 11748 | } |
684022ea | 11749 | |
df58fc94 | 11750 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11751 | } |
11752 | else | |
11753 | { | |
4d7206a2 | 11754 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11755 | if (!mips_big_got) |
438c16b8 | 11756 | { |
67c0d1eb RS |
11757 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11758 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11759 | mips_gp_register); |
269137b2 | 11760 | load_delay_nop (); |
4d7206a2 | 11761 | relax_switch (); |
438c16b8 | 11762 | } |
252b5132 | 11763 | else |
252b5132 | 11764 | { |
67c0d1eb RS |
11765 | int gpdelay; |
11766 | ||
11767 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11768 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11769 | BFD_RELOC_MIPS_CALL_HI16); |
11770 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11771 | PIC_CALL_REG, mips_gp_register); | |
11772 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11773 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11774 | PIC_CALL_REG); | |
269137b2 | 11775 | load_delay_nop (); |
4d7206a2 | 11776 | relax_switch (); |
67c0d1eb RS |
11777 | if (gpdelay) |
11778 | macro_build (NULL, "nop", ""); | |
252b5132 | 11779 | } |
67c0d1eb RS |
11780 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11781 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11782 | mips_gp_register); |
269137b2 | 11783 | load_delay_nop (); |
67c0d1eb RS |
11784 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11785 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11786 | relax_end (); |
df58fc94 | 11787 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11788 | |
6478892d | 11789 | if (mips_cprestore_offset < 0) |
1661c76c | 11790 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11791 | else |
11792 | { | |
90ecf173 | 11793 | if (!mips_frame_reg_valid) |
7a621144 | 11794 | { |
1661c76c | 11795 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11796 | /* Quiet this warning. */ |
11797 | mips_frame_reg_valid = 1; | |
11798 | } | |
90ecf173 | 11799 | if (!mips_cprestore_valid) |
7a621144 | 11800 | { |
1661c76c | 11801 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11802 | /* Quiet this warning. */ |
11803 | mips_cprestore_valid = 1; | |
11804 | } | |
6478892d | 11805 | if (mips_opts.noreorder) |
67c0d1eb | 11806 | macro_build (NULL, "nop", ""); |
6478892d | 11807 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11808 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11809 | mips_gp_register, |
256ab948 TS |
11810 | mips_frame_reg, |
11811 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11812 | } |
252b5132 RH |
11813 | } |
11814 | } | |
0a44bf69 | 11815 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11816 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11817 | else |
11818 | abort (); | |
11819 | ||
8fc2e39e | 11820 | break; |
252b5132 | 11821 | |
7f3c4072 | 11822 | case M_LBUE_AB: |
7f3c4072 CM |
11823 | s = "lbue"; |
11824 | fmt = "t,+j(b)"; | |
11825 | offbits = 9; | |
11826 | goto ld_st; | |
11827 | case M_LHUE_AB: | |
7f3c4072 CM |
11828 | s = "lhue"; |
11829 | fmt = "t,+j(b)"; | |
11830 | offbits = 9; | |
11831 | goto ld_st; | |
11832 | case M_LBE_AB: | |
7f3c4072 CM |
11833 | s = "lbe"; |
11834 | fmt = "t,+j(b)"; | |
11835 | offbits = 9; | |
11836 | goto ld_st; | |
11837 | case M_LHE_AB: | |
7f3c4072 CM |
11838 | s = "lhe"; |
11839 | fmt = "t,+j(b)"; | |
11840 | offbits = 9; | |
11841 | goto ld_st; | |
11842 | case M_LLE_AB: | |
7f3c4072 CM |
11843 | s = "lle"; |
11844 | fmt = "t,+j(b)"; | |
11845 | offbits = 9; | |
11846 | goto ld_st; | |
11847 | case M_LWE_AB: | |
7f3c4072 CM |
11848 | s = "lwe"; |
11849 | fmt = "t,+j(b)"; | |
11850 | offbits = 9; | |
11851 | goto ld_st; | |
11852 | case M_LWLE_AB: | |
7f3c4072 CM |
11853 | s = "lwle"; |
11854 | fmt = "t,+j(b)"; | |
11855 | offbits = 9; | |
11856 | goto ld_st; | |
11857 | case M_LWRE_AB: | |
7f3c4072 CM |
11858 | s = "lwre"; |
11859 | fmt = "t,+j(b)"; | |
11860 | offbits = 9; | |
11861 | goto ld_st; | |
11862 | case M_SBE_AB: | |
7f3c4072 CM |
11863 | s = "sbe"; |
11864 | fmt = "t,+j(b)"; | |
11865 | offbits = 9; | |
11866 | goto ld_st; | |
11867 | case M_SCE_AB: | |
7f3c4072 CM |
11868 | s = "sce"; |
11869 | fmt = "t,+j(b)"; | |
11870 | offbits = 9; | |
11871 | goto ld_st; | |
11872 | case M_SHE_AB: | |
7f3c4072 CM |
11873 | s = "she"; |
11874 | fmt = "t,+j(b)"; | |
11875 | offbits = 9; | |
11876 | goto ld_st; | |
11877 | case M_SWE_AB: | |
7f3c4072 CM |
11878 | s = "swe"; |
11879 | fmt = "t,+j(b)"; | |
11880 | offbits = 9; | |
11881 | goto ld_st; | |
11882 | case M_SWLE_AB: | |
7f3c4072 CM |
11883 | s = "swle"; |
11884 | fmt = "t,+j(b)"; | |
11885 | offbits = 9; | |
11886 | goto ld_st; | |
11887 | case M_SWRE_AB: | |
7f3c4072 CM |
11888 | s = "swre"; |
11889 | fmt = "t,+j(b)"; | |
11890 | offbits = 9; | |
11891 | goto ld_st; | |
dec0624d | 11892 | case M_ACLR_AB: |
dec0624d | 11893 | s = "aclr"; |
dec0624d | 11894 | fmt = "\\,~(b)"; |
7f3c4072 | 11895 | offbits = 12; |
dec0624d MR |
11896 | goto ld_st; |
11897 | case M_ASET_AB: | |
dec0624d | 11898 | s = "aset"; |
dec0624d | 11899 | fmt = "\\,~(b)"; |
7f3c4072 | 11900 | offbits = 12; |
dec0624d | 11901 | goto ld_st; |
252b5132 RH |
11902 | case M_LB_AB: |
11903 | s = "lb"; | |
df58fc94 | 11904 | fmt = "t,o(b)"; |
252b5132 RH |
11905 | goto ld; |
11906 | case M_LBU_AB: | |
11907 | s = "lbu"; | |
df58fc94 | 11908 | fmt = "t,o(b)"; |
252b5132 RH |
11909 | goto ld; |
11910 | case M_LH_AB: | |
11911 | s = "lh"; | |
df58fc94 | 11912 | fmt = "t,o(b)"; |
252b5132 RH |
11913 | goto ld; |
11914 | case M_LHU_AB: | |
11915 | s = "lhu"; | |
df58fc94 | 11916 | fmt = "t,o(b)"; |
252b5132 RH |
11917 | goto ld; |
11918 | case M_LW_AB: | |
11919 | s = "lw"; | |
df58fc94 | 11920 | fmt = "t,o(b)"; |
252b5132 RH |
11921 | goto ld; |
11922 | case M_LWC0_AB: | |
df58fc94 | 11923 | gas_assert (!mips_opts.micromips); |
252b5132 | 11924 | s = "lwc0"; |
df58fc94 | 11925 | fmt = "E,o(b)"; |
bdaaa2e1 | 11926 | /* Itbl support may require additional care here. */ |
252b5132 | 11927 | coproc = 1; |
df58fc94 | 11928 | goto ld_st; |
252b5132 RH |
11929 | case M_LWC1_AB: |
11930 | s = "lwc1"; | |
df58fc94 | 11931 | fmt = "T,o(b)"; |
bdaaa2e1 | 11932 | /* Itbl support may require additional care here. */ |
252b5132 | 11933 | coproc = 1; |
df58fc94 | 11934 | goto ld_st; |
252b5132 RH |
11935 | case M_LWC2_AB: |
11936 | s = "lwc2"; | |
df58fc94 | 11937 | fmt = COP12_FMT; |
7361da2c AB |
11938 | offbits = (mips_opts.micromips ? 12 |
11939 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11940 | : 16); | |
bdaaa2e1 | 11941 | /* Itbl support may require additional care here. */ |
252b5132 | 11942 | coproc = 1; |
df58fc94 | 11943 | goto ld_st; |
252b5132 | 11944 | case M_LWC3_AB: |
df58fc94 | 11945 | gas_assert (!mips_opts.micromips); |
252b5132 | 11946 | s = "lwc3"; |
df58fc94 | 11947 | fmt = "E,o(b)"; |
bdaaa2e1 | 11948 | /* Itbl support may require additional care here. */ |
252b5132 | 11949 | coproc = 1; |
df58fc94 | 11950 | goto ld_st; |
252b5132 RH |
11951 | case M_LWL_AB: |
11952 | s = "lwl"; | |
df58fc94 | 11953 | fmt = MEM12_FMT; |
7f3c4072 | 11954 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11955 | goto ld_st; |
252b5132 RH |
11956 | case M_LWR_AB: |
11957 | s = "lwr"; | |
df58fc94 | 11958 | fmt = MEM12_FMT; |
7f3c4072 | 11959 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11960 | goto ld_st; |
252b5132 | 11961 | case M_LDC1_AB: |
252b5132 | 11962 | s = "ldc1"; |
df58fc94 | 11963 | fmt = "T,o(b)"; |
bdaaa2e1 | 11964 | /* Itbl support may require additional care here. */ |
252b5132 | 11965 | coproc = 1; |
df58fc94 | 11966 | goto ld_st; |
252b5132 RH |
11967 | case M_LDC2_AB: |
11968 | s = "ldc2"; | |
df58fc94 | 11969 | fmt = COP12_FMT; |
7361da2c AB |
11970 | offbits = (mips_opts.micromips ? 12 |
11971 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11972 | : 16); | |
bdaaa2e1 | 11973 | /* Itbl support may require additional care here. */ |
252b5132 | 11974 | coproc = 1; |
df58fc94 | 11975 | goto ld_st; |
c77c0862 | 11976 | case M_LQC2_AB: |
c77c0862 | 11977 | s = "lqc2"; |
14daeee3 | 11978 | fmt = "+7,o(b)"; |
c77c0862 RS |
11979 | /* Itbl support may require additional care here. */ |
11980 | coproc = 1; | |
11981 | goto ld_st; | |
252b5132 RH |
11982 | case M_LDC3_AB: |
11983 | s = "ldc3"; | |
df58fc94 | 11984 | fmt = "E,o(b)"; |
bdaaa2e1 | 11985 | /* Itbl support may require additional care here. */ |
252b5132 | 11986 | coproc = 1; |
df58fc94 | 11987 | goto ld_st; |
252b5132 RH |
11988 | case M_LDL_AB: |
11989 | s = "ldl"; | |
df58fc94 | 11990 | fmt = MEM12_FMT; |
7f3c4072 | 11991 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11992 | goto ld_st; |
252b5132 RH |
11993 | case M_LDR_AB: |
11994 | s = "ldr"; | |
df58fc94 | 11995 | fmt = MEM12_FMT; |
7f3c4072 | 11996 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11997 | goto ld_st; |
252b5132 RH |
11998 | case M_LL_AB: |
11999 | s = "ll"; | |
7361da2c AB |
12000 | fmt = LL_SC_FMT; |
12001 | offbits = (mips_opts.micromips ? 12 | |
12002 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12003 | : 16); | |
252b5132 RH |
12004 | goto ld; |
12005 | case M_LLD_AB: | |
12006 | s = "lld"; | |
7361da2c AB |
12007 | fmt = LL_SC_FMT; |
12008 | offbits = (mips_opts.micromips ? 12 | |
12009 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12010 | : 16); | |
252b5132 RH |
12011 | goto ld; |
12012 | case M_LWU_AB: | |
12013 | s = "lwu"; | |
df58fc94 | 12014 | fmt = MEM12_FMT; |
7f3c4072 | 12015 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12016 | goto ld; |
12017 | case M_LWP_AB: | |
df58fc94 RS |
12018 | gas_assert (mips_opts.micromips); |
12019 | s = "lwp"; | |
12020 | fmt = "t,~(b)"; | |
7f3c4072 | 12021 | offbits = 12; |
df58fc94 RS |
12022 | lp = 1; |
12023 | goto ld; | |
12024 | case M_LDP_AB: | |
df58fc94 RS |
12025 | gas_assert (mips_opts.micromips); |
12026 | s = "ldp"; | |
12027 | fmt = "t,~(b)"; | |
7f3c4072 | 12028 | offbits = 12; |
df58fc94 RS |
12029 | lp = 1; |
12030 | goto ld; | |
a45328b9 AB |
12031 | case M_LLDP_AB: |
12032 | case M_LLWP_AB: | |
41cee089 | 12033 | case M_LLWPE_AB: |
a45328b9 AB |
12034 | s = ip->insn_mo->name; |
12035 | fmt = "t,d,s"; | |
12036 | ll_sc_paired = 1; | |
12037 | offbits = 0; | |
12038 | goto ld; | |
df58fc94 | 12039 | case M_LWM_AB: |
df58fc94 RS |
12040 | gas_assert (mips_opts.micromips); |
12041 | s = "lwm"; | |
12042 | fmt = "n,~(b)"; | |
7f3c4072 | 12043 | offbits = 12; |
df58fc94 RS |
12044 | goto ld_st; |
12045 | case M_LDM_AB: | |
df58fc94 RS |
12046 | gas_assert (mips_opts.micromips); |
12047 | s = "ldm"; | |
12048 | fmt = "n,~(b)"; | |
7f3c4072 | 12049 | offbits = 12; |
df58fc94 RS |
12050 | goto ld_st; |
12051 | ||
252b5132 | 12052 | ld: |
a45328b9 AB |
12053 | /* Try to use one the the load registers to compute the base address. |
12054 | We don't want to use $0 as tempreg. */ | |
12055 | if (ll_sc_paired) | |
12056 | { | |
12057 | if ((op[0] == ZERO && op[3] == op[1]) | |
12058 | || (op[1] == ZERO && op[3] == op[0]) | |
12059 | || (op[0] == ZERO && op[1] == ZERO)) | |
12060 | goto ld_st; | |
12061 | else if (op[0] != op[3] && op[0] != ZERO) | |
12062 | tempreg = op[0]; | |
12063 | else | |
12064 | tempreg = op[1]; | |
12065 | } | |
252b5132 | 12066 | else |
a45328b9 AB |
12067 | { |
12068 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) | |
12069 | goto ld_st; | |
12070 | else | |
12071 | tempreg = op[0] + lp; | |
12072 | } | |
df58fc94 RS |
12073 | goto ld_noat; |
12074 | ||
252b5132 RH |
12075 | case M_SB_AB: |
12076 | s = "sb"; | |
df58fc94 RS |
12077 | fmt = "t,o(b)"; |
12078 | goto ld_st; | |
252b5132 RH |
12079 | case M_SH_AB: |
12080 | s = "sh"; | |
df58fc94 RS |
12081 | fmt = "t,o(b)"; |
12082 | goto ld_st; | |
252b5132 RH |
12083 | case M_SW_AB: |
12084 | s = "sw"; | |
df58fc94 RS |
12085 | fmt = "t,o(b)"; |
12086 | goto ld_st; | |
252b5132 | 12087 | case M_SWC0_AB: |
df58fc94 | 12088 | gas_assert (!mips_opts.micromips); |
252b5132 | 12089 | s = "swc0"; |
df58fc94 | 12090 | fmt = "E,o(b)"; |
bdaaa2e1 | 12091 | /* Itbl support may require additional care here. */ |
252b5132 | 12092 | coproc = 1; |
df58fc94 | 12093 | goto ld_st; |
252b5132 RH |
12094 | case M_SWC1_AB: |
12095 | s = "swc1"; | |
df58fc94 | 12096 | fmt = "T,o(b)"; |
bdaaa2e1 | 12097 | /* Itbl support may require additional care here. */ |
252b5132 | 12098 | coproc = 1; |
df58fc94 | 12099 | goto ld_st; |
252b5132 RH |
12100 | case M_SWC2_AB: |
12101 | s = "swc2"; | |
df58fc94 | 12102 | fmt = COP12_FMT; |
7361da2c AB |
12103 | offbits = (mips_opts.micromips ? 12 |
12104 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12105 | : 16); | |
bdaaa2e1 | 12106 | /* Itbl support may require additional care here. */ |
252b5132 | 12107 | coproc = 1; |
df58fc94 | 12108 | goto ld_st; |
252b5132 | 12109 | case M_SWC3_AB: |
df58fc94 | 12110 | gas_assert (!mips_opts.micromips); |
252b5132 | 12111 | s = "swc3"; |
df58fc94 | 12112 | fmt = "E,o(b)"; |
bdaaa2e1 | 12113 | /* Itbl support may require additional care here. */ |
252b5132 | 12114 | coproc = 1; |
df58fc94 | 12115 | goto ld_st; |
252b5132 RH |
12116 | case M_SWL_AB: |
12117 | s = "swl"; | |
df58fc94 | 12118 | fmt = MEM12_FMT; |
7f3c4072 | 12119 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12120 | goto ld_st; |
252b5132 RH |
12121 | case M_SWR_AB: |
12122 | s = "swr"; | |
df58fc94 | 12123 | fmt = MEM12_FMT; |
7f3c4072 | 12124 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12125 | goto ld_st; |
252b5132 RH |
12126 | case M_SC_AB: |
12127 | s = "sc"; | |
7361da2c AB |
12128 | fmt = LL_SC_FMT; |
12129 | offbits = (mips_opts.micromips ? 12 | |
12130 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12131 | : 16); | |
df58fc94 | 12132 | goto ld_st; |
252b5132 RH |
12133 | case M_SCD_AB: |
12134 | s = "scd"; | |
7361da2c AB |
12135 | fmt = LL_SC_FMT; |
12136 | offbits = (mips_opts.micromips ? 12 | |
12137 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12138 | : 16); | |
df58fc94 | 12139 | goto ld_st; |
a45328b9 AB |
12140 | case M_SCDP_AB: |
12141 | case M_SCWP_AB: | |
41cee089 | 12142 | case M_SCWPE_AB: |
a45328b9 AB |
12143 | s = ip->insn_mo->name; |
12144 | fmt = "t,d,s"; | |
12145 | ll_sc_paired = 1; | |
12146 | offbits = 0; | |
12147 | goto ld_st; | |
d43b4baf TS |
12148 | case M_CACHE_AB: |
12149 | s = "cache"; | |
7361da2c AB |
12150 | fmt = (mips_opts.micromips ? "k,~(b)" |
12151 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
12152 | : "k,o(b)"); | |
12153 | offbits = (mips_opts.micromips ? 12 | |
12154 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12155 | : 16); | |
7f3c4072 CM |
12156 | goto ld_st; |
12157 | case M_CACHEE_AB: | |
7f3c4072 CM |
12158 | s = "cachee"; |
12159 | fmt = "k,+j(b)"; | |
12160 | offbits = 9; | |
df58fc94 | 12161 | goto ld_st; |
3eebd5eb MR |
12162 | case M_PREF_AB: |
12163 | s = "pref"; | |
7361da2c AB |
12164 | fmt = (mips_opts.micromips ? "k,~(b)" |
12165 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
12166 | : "k,o(b)"); | |
12167 | offbits = (mips_opts.micromips ? 12 | |
12168 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12169 | : 16); | |
7f3c4072 CM |
12170 | goto ld_st; |
12171 | case M_PREFE_AB: | |
7f3c4072 CM |
12172 | s = "prefe"; |
12173 | fmt = "k,+j(b)"; | |
12174 | offbits = 9; | |
df58fc94 | 12175 | goto ld_st; |
252b5132 | 12176 | case M_SDC1_AB: |
252b5132 | 12177 | s = "sdc1"; |
df58fc94 | 12178 | fmt = "T,o(b)"; |
252b5132 | 12179 | coproc = 1; |
bdaaa2e1 | 12180 | /* Itbl support may require additional care here. */ |
df58fc94 | 12181 | goto ld_st; |
252b5132 RH |
12182 | case M_SDC2_AB: |
12183 | s = "sdc2"; | |
df58fc94 | 12184 | fmt = COP12_FMT; |
7361da2c AB |
12185 | offbits = (mips_opts.micromips ? 12 |
12186 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12187 | : 16); | |
c77c0862 RS |
12188 | /* Itbl support may require additional care here. */ |
12189 | coproc = 1; | |
12190 | goto ld_st; | |
12191 | case M_SQC2_AB: | |
c77c0862 | 12192 | s = "sqc2"; |
14daeee3 | 12193 | fmt = "+7,o(b)"; |
bdaaa2e1 | 12194 | /* Itbl support may require additional care here. */ |
252b5132 | 12195 | coproc = 1; |
df58fc94 | 12196 | goto ld_st; |
252b5132 | 12197 | case M_SDC3_AB: |
df58fc94 | 12198 | gas_assert (!mips_opts.micromips); |
252b5132 | 12199 | s = "sdc3"; |
df58fc94 | 12200 | fmt = "E,o(b)"; |
bdaaa2e1 | 12201 | /* Itbl support may require additional care here. */ |
252b5132 | 12202 | coproc = 1; |
df58fc94 | 12203 | goto ld_st; |
252b5132 RH |
12204 | case M_SDL_AB: |
12205 | s = "sdl"; | |
df58fc94 | 12206 | fmt = MEM12_FMT; |
7f3c4072 | 12207 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12208 | goto ld_st; |
252b5132 RH |
12209 | case M_SDR_AB: |
12210 | s = "sdr"; | |
df58fc94 | 12211 | fmt = MEM12_FMT; |
7f3c4072 | 12212 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12213 | goto ld_st; |
12214 | case M_SWP_AB: | |
df58fc94 RS |
12215 | gas_assert (mips_opts.micromips); |
12216 | s = "swp"; | |
12217 | fmt = "t,~(b)"; | |
7f3c4072 | 12218 | offbits = 12; |
df58fc94 RS |
12219 | goto ld_st; |
12220 | case M_SDP_AB: | |
df58fc94 RS |
12221 | gas_assert (mips_opts.micromips); |
12222 | s = "sdp"; | |
12223 | fmt = "t,~(b)"; | |
7f3c4072 | 12224 | offbits = 12; |
df58fc94 RS |
12225 | goto ld_st; |
12226 | case M_SWM_AB: | |
df58fc94 RS |
12227 | gas_assert (mips_opts.micromips); |
12228 | s = "swm"; | |
12229 | fmt = "n,~(b)"; | |
7f3c4072 | 12230 | offbits = 12; |
df58fc94 RS |
12231 | goto ld_st; |
12232 | case M_SDM_AB: | |
df58fc94 RS |
12233 | gas_assert (mips_opts.micromips); |
12234 | s = "sdm"; | |
12235 | fmt = "n,~(b)"; | |
7f3c4072 | 12236 | offbits = 12; |
df58fc94 RS |
12237 | |
12238 | ld_st: | |
8fc2e39e | 12239 | tempreg = AT; |
df58fc94 | 12240 | ld_noat: |
a45328b9 | 12241 | breg = ll_sc_paired ? op[3] : op[2]; |
f2ae14a1 RS |
12242 | if (small_offset_p (0, align, 16)) |
12243 | { | |
12244 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
12245 | macros for o32 but which should act like normal instructions | |
12246 | otherwise. */ | |
12247 | if (offbits == 16) | |
c0ebe874 | 12248 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12249 | offset_reloc[1], offset_reloc[2], breg); |
12250 | else if (small_offset_p (0, align, offbits)) | |
12251 | { | |
12252 | if (offbits == 0) | |
a45328b9 AB |
12253 | { |
12254 | if (ll_sc_paired) | |
12255 | macro_build (NULL, s, fmt, op[0], op[1], breg); | |
12256 | else | |
12257 | macro_build (NULL, s, fmt, op[0], breg); | |
12258 | } | |
f2ae14a1 | 12259 | else |
c0ebe874 | 12260 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12261 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
12262 | } |
12263 | else | |
12264 | { | |
12265 | if (tempreg == AT) | |
12266 | used_at = 1; | |
12267 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
12268 | tempreg, breg, -1, offset_reloc[0], | |
12269 | offset_reloc[1], offset_reloc[2]); | |
12270 | if (offbits == 0) | |
a45328b9 AB |
12271 | { |
12272 | if (ll_sc_paired) | |
12273 | macro_build (NULL, s, fmt, op[0], op[1], tempreg); | |
12274 | else | |
12275 | macro_build (NULL, s, fmt, op[0], tempreg); | |
12276 | } | |
f2ae14a1 | 12277 | else |
c0ebe874 | 12278 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
12279 | } |
12280 | break; | |
12281 | } | |
12282 | ||
12283 | if (tempreg == AT) | |
12284 | used_at = 1; | |
12285 | ||
252b5132 RH |
12286 | if (offset_expr.X_op != O_constant |
12287 | && offset_expr.X_op != O_symbol) | |
12288 | { | |
1661c76c | 12289 | as_bad (_("expression too complex")); |
252b5132 RH |
12290 | offset_expr.X_op = O_constant; |
12291 | } | |
12292 | ||
2051e8c4 MR |
12293 | if (HAVE_32BIT_ADDRESSES |
12294 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12295 | { |
12296 | char value [32]; | |
12297 | ||
12298 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12299 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12300 | } |
2051e8c4 | 12301 | |
252b5132 RH |
12302 | /* A constant expression in PIC code can be handled just as it |
12303 | is in non PIC code. */ | |
aed1a261 RS |
12304 | if (offset_expr.X_op == O_constant) |
12305 | { | |
f2ae14a1 RS |
12306 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
12307 | offbits == 0 ? 16 : offbits); | |
12308 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 12309 | |
f2ae14a1 RS |
12310 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
12311 | if (breg != 0) | |
12312 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12313 | tempreg, tempreg, breg); | |
7f3c4072 | 12314 | if (offbits == 0) |
dd6a37e7 | 12315 | { |
f2ae14a1 | 12316 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 12317 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 12318 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
a45328b9 AB |
12319 | if (ll_sc_paired) |
12320 | macro_build (NULL, s, fmt, op[0], op[1], tempreg); | |
12321 | else | |
12322 | macro_build (NULL, s, fmt, op[0], tempreg); | |
dd6a37e7 | 12323 | } |
7f3c4072 | 12324 | else if (offbits == 16) |
c0ebe874 | 12325 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 12326 | else |
c0ebe874 | 12327 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12328 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 12329 | } |
7f3c4072 | 12330 | else if (offbits != 16) |
df58fc94 | 12331 | { |
7f3c4072 | 12332 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 12333 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
12334 | register. */ |
12335 | load_address (tempreg, &offset_expr, &used_at); | |
12336 | if (breg != 0) | |
12337 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12338 | tempreg, tempreg, breg); | |
7f3c4072 | 12339 | if (offbits == 0) |
a45328b9 AB |
12340 | { |
12341 | if (ll_sc_paired) | |
12342 | macro_build (NULL, s, fmt, op[0], op[1], tempreg); | |
12343 | else | |
12344 | macro_build (NULL, s, fmt, op[0], tempreg); | |
12345 | } | |
dd6a37e7 | 12346 | else |
c0ebe874 | 12347 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
12348 | } |
12349 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
12350 | { |
12351 | /* If this is a reference to a GP relative symbol, and there | |
12352 | is no base register, we want | |
c0ebe874 | 12353 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
12354 | Otherwise, if there is no base register, we want |
12355 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 12356 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
12357 | If we have a constant, we need two instructions anyhow, |
12358 | so we always use the latter form. | |
12359 | ||
12360 | If we have a base register, and this is a reference to a | |
12361 | GP relative symbol, we want | |
12362 | addu $tempreg,$breg,$gp | |
c0ebe874 | 12363 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
12364 | Otherwise we want |
12365 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12366 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 12367 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 12368 | With a constant we always use the latter case. |
76b3015f | 12369 | |
d6bc6245 TS |
12370 | With 64bit address space and no base register and $at usable, |
12371 | we want | |
12372 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12373 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12374 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12375 | dsll32 $tempreg,0 | |
12376 | daddu $tempreg,$at | |
c0ebe874 | 12377 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12378 | If we have a base register, we want |
12379 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12380 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12381 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12382 | daddu $at,$breg | |
12383 | dsll32 $tempreg,0 | |
12384 | daddu $tempreg,$at | |
c0ebe874 | 12385 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12386 | |
12387 | Without $at we can't generate the optimal path for superscalar | |
12388 | processors here since this would require two temporary registers. | |
12389 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12390 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12391 | dsll $tempreg,16 | |
12392 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12393 | dsll $tempreg,16 | |
c0ebe874 | 12394 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12395 | If we have a base register, we want |
12396 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12397 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12398 | dsll $tempreg,16 | |
12399 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12400 | dsll $tempreg,16 | |
12401 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 12402 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 12403 | |
6caf9ef4 | 12404 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
12405 | the same sequence as in 32bit address space. */ |
12406 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 12407 | { |
aed1a261 | 12408 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
12409 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
12410 | { | |
12411 | relax_start (offset_expr.X_add_symbol); | |
12412 | if (breg == 0) | |
12413 | { | |
c0ebe874 | 12414 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12415 | BFD_RELOC_GPREL16, mips_gp_register); |
12416 | } | |
12417 | else | |
12418 | { | |
12419 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12420 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 12421 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12422 | BFD_RELOC_GPREL16, tempreg); |
12423 | } | |
12424 | relax_switch (); | |
12425 | } | |
d6bc6245 | 12426 | |
741fe287 | 12427 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 12428 | { |
df58fc94 | 12429 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 12430 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 12431 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
12432 | BFD_RELOC_HI16_S); |
12433 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12434 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 12435 | if (breg != 0) |
67c0d1eb | 12436 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12437 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12438 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12439 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12440 | tempreg); |
d6bc6245 TS |
12441 | used_at = 1; |
12442 | } | |
12443 | else | |
12444 | { | |
df58fc94 | 12445 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12446 | BFD_RELOC_MIPS_HIGHEST); |
12447 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12448 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12449 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12450 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12451 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12452 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12453 | if (breg != 0) |
67c0d1eb | 12454 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12455 | tempreg, tempreg, breg); |
c0ebe874 | 12456 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12457 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12458 | } |
6caf9ef4 TS |
12459 | |
12460 | if (mips_relax.sequence) | |
12461 | relax_end (); | |
8fc2e39e | 12462 | break; |
d6bc6245 | 12463 | } |
256ab948 | 12464 | |
252b5132 RH |
12465 | if (breg == 0) |
12466 | { | |
67c0d1eb | 12467 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12468 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12469 | { |
4d7206a2 | 12470 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12471 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12472 | mips_gp_register); |
4d7206a2 | 12473 | relax_switch (); |
252b5132 | 12474 | } |
67c0d1eb | 12475 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12476 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12477 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12478 | if (mips_relax.sequence) |
12479 | relax_end (); | |
252b5132 RH |
12480 | } |
12481 | else | |
12482 | { | |
67c0d1eb | 12483 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12484 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12485 | { |
4d7206a2 | 12486 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12487 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12488 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12489 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12490 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12491 | relax_switch (); |
252b5132 | 12492 | } |
67c0d1eb RS |
12493 | macro_build_lui (&offset_expr, tempreg); |
12494 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12495 | tempreg, tempreg, breg); |
c0ebe874 | 12496 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12497 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12498 | if (mips_relax.sequence) |
12499 | relax_end (); | |
252b5132 RH |
12500 | } |
12501 | } | |
0a44bf69 | 12502 | else if (!mips_big_got) |
252b5132 | 12503 | { |
ed6fb7bd | 12504 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12505 | |
252b5132 RH |
12506 | /* If this is a reference to an external symbol, we want |
12507 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12508 | nop | |
c0ebe874 | 12509 | <op> op[0],0($tempreg) |
252b5132 RH |
12510 | Otherwise we want |
12511 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12512 | nop | |
12513 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12514 | <op> op[0],0($tempreg) |
f5040a92 AO |
12515 | |
12516 | For NewABI, we want | |
12517 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12518 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12519 | |
252b5132 RH |
12520 | If there is a base register, we add it to $tempreg before |
12521 | the <op>. If there is a constant, we stick it in the | |
12522 | <op> instruction. We don't handle constants larger than | |
12523 | 16 bits, because we have no way to load the upper 16 bits | |
12524 | (actually, we could handle them for the subset of cases | |
12525 | in which we are not using $at). */ | |
9c2799c2 | 12526 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12527 | if (HAVE_NEWABI) |
12528 | { | |
67c0d1eb RS |
12529 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12530 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12531 | if (breg != 0) |
67c0d1eb | 12532 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12533 | tempreg, tempreg, breg); |
c0ebe874 | 12534 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12535 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12536 | break; |
12537 | } | |
252b5132 RH |
12538 | expr1.X_add_number = offset_expr.X_add_number; |
12539 | offset_expr.X_add_number = 0; | |
12540 | if (expr1.X_add_number < -0x8000 | |
12541 | || expr1.X_add_number >= 0x8000) | |
12542 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12543 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12544 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12545 | load_delay_nop (); |
4d7206a2 RS |
12546 | relax_start (offset_expr.X_add_symbol); |
12547 | relax_switch (); | |
67c0d1eb RS |
12548 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12549 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12550 | relax_end (); |
252b5132 | 12551 | if (breg != 0) |
67c0d1eb | 12552 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12553 | tempreg, tempreg, breg); |
c0ebe874 | 12554 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12555 | } |
0a44bf69 | 12556 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12557 | { |
67c0d1eb | 12558 | int gpdelay; |
252b5132 RH |
12559 | |
12560 | /* If this is a reference to an external symbol, we want | |
12561 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12562 | addu $tempreg,$tempreg,$gp | |
12563 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12564 | <op> op[0],0($tempreg) |
252b5132 RH |
12565 | Otherwise we want |
12566 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12567 | nop | |
12568 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12569 | <op> op[0],0($tempreg) |
252b5132 RH |
12570 | If there is a base register, we add it to $tempreg before |
12571 | the <op>. If there is a constant, we stick it in the | |
12572 | <op> instruction. We don't handle constants larger than | |
12573 | 16 bits, because we have no way to load the upper 16 bits | |
12574 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12575 | in which we are not using $at). */ |
9c2799c2 | 12576 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12577 | expr1.X_add_number = offset_expr.X_add_number; |
12578 | offset_expr.X_add_number = 0; | |
12579 | if (expr1.X_add_number < -0x8000 | |
12580 | || expr1.X_add_number >= 0x8000) | |
12581 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12582 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12583 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12584 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12585 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12586 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12587 | mips_gp_register); | |
12588 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12589 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12590 | relax_switch (); |
67c0d1eb RS |
12591 | if (gpdelay) |
12592 | macro_build (NULL, "nop", ""); | |
12593 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12594 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12595 | load_delay_nop (); |
67c0d1eb RS |
12596 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12597 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12598 | relax_end (); |
12599 | ||
252b5132 | 12600 | if (breg != 0) |
67c0d1eb | 12601 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12602 | tempreg, tempreg, breg); |
c0ebe874 | 12603 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12604 | } |
0a44bf69 | 12605 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12606 | { |
f5040a92 AO |
12607 | /* If this is a reference to an external symbol, we want |
12608 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12609 | add $tempreg,$tempreg,$gp | |
12610 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12611 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12612 | Otherwise, for local symbols, we want: |
12613 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12614 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12615 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12616 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12617 | offset_expr.X_add_number = 0; |
12618 | if (expr1.X_add_number < -0x8000 | |
12619 | || expr1.X_add_number >= 0x8000) | |
12620 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12621 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12622 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12623 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12624 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12625 | mips_gp_register); | |
12626 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12627 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12628 | if (breg != 0) |
67c0d1eb | 12629 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12630 | tempreg, tempreg, breg); |
c0ebe874 | 12631 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12632 | |
4d7206a2 | 12633 | relax_switch (); |
f5040a92 | 12634 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12635 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12636 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12637 | if (breg != 0) |
67c0d1eb | 12638 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12639 | tempreg, tempreg, breg); |
c0ebe874 | 12640 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12641 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12642 | relax_end (); |
f5040a92 | 12643 | } |
252b5132 RH |
12644 | else |
12645 | abort (); | |
12646 | ||
252b5132 RH |
12647 | break; |
12648 | ||
833794fc MR |
12649 | case M_JRADDIUSP: |
12650 | gas_assert (mips_opts.micromips); | |
12651 | gas_assert (mips_opts.insn32); | |
12652 | start_noreorder (); | |
12653 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12654 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12655 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12656 | end_noreorder (); | |
12657 | break; | |
12658 | ||
12659 | case M_JRC: | |
12660 | gas_assert (mips_opts.micromips); | |
12661 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12662 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12663 | if (mips_opts.noreorder) |
12664 | macro_build (NULL, "nop", ""); | |
12665 | break; | |
12666 | ||
252b5132 RH |
12667 | case M_LI: |
12668 | case M_LI_S: | |
c0ebe874 | 12669 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12670 | break; |
252b5132 RH |
12671 | |
12672 | case M_DLI: | |
c0ebe874 | 12673 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12674 | break; |
252b5132 RH |
12675 | |
12676 | case M_LI_SS: | |
12677 | if (imm_expr.X_op == O_constant) | |
12678 | { | |
8fc2e39e | 12679 | used_at = 1; |
67c0d1eb | 12680 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12681 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12682 | break; |
12683 | } | |
12684 | else | |
12685 | { | |
b0e6f033 RS |
12686 | gas_assert (imm_expr.X_op == O_absent |
12687 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12688 | && strcmp (segment_name (S_GET_SEGMENT |
12689 | (offset_expr.X_add_symbol)), | |
12690 | ".lit4") == 0 | |
12691 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12692 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12693 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12694 | break; |
252b5132 RH |
12695 | } |
12696 | ||
12697 | case M_LI_D: | |
ca4e0257 RS |
12698 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12699 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12700 | order 32 bits of the value and the low order 32 bits are either | |
12701 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12702 | if (imm_expr.X_op == O_constant) |
252b5132 | 12703 | { |
bad1aba3 | 12704 | if (GPR_SIZE == 64) |
c0ebe874 | 12705 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12706 | else |
12707 | { | |
12708 | int hreg, lreg; | |
12709 | ||
12710 | if (target_big_endian) | |
12711 | { | |
c0ebe874 RS |
12712 | hreg = op[0]; |
12713 | lreg = op[0] + 1; | |
252b5132 RH |
12714 | } |
12715 | else | |
12716 | { | |
c0ebe874 RS |
12717 | hreg = op[0] + 1; |
12718 | lreg = op[0]; | |
252b5132 RH |
12719 | } |
12720 | ||
12721 | if (hreg <= 31) | |
67c0d1eb | 12722 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12723 | if (lreg <= 31) |
12724 | { | |
12725 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12726 | move_register (lreg, 0); |
252b5132 RH |
12727 | else |
12728 | { | |
9c2799c2 | 12729 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12730 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12731 | } |
12732 | } | |
12733 | } | |
8fc2e39e | 12734 | break; |
252b5132 | 12735 | } |
b0e6f033 | 12736 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12737 | |
12738 | /* We know that sym is in the .rdata section. First we get the | |
12739 | upper 16 bits of the address. */ | |
12740 | if (mips_pic == NO_PIC) | |
12741 | { | |
67c0d1eb | 12742 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12743 | used_at = 1; |
252b5132 | 12744 | } |
0a44bf69 | 12745 | else |
252b5132 | 12746 | { |
67c0d1eb RS |
12747 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12748 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12749 | used_at = 1; |
252b5132 | 12750 | } |
bdaaa2e1 | 12751 | |
252b5132 | 12752 | /* Now we load the register(s). */ |
bad1aba3 | 12753 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12754 | { |
12755 | used_at = 1; | |
c0ebe874 RS |
12756 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12757 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12758 | } |
252b5132 RH |
12759 | else |
12760 | { | |
8fc2e39e | 12761 | used_at = 1; |
c0ebe874 RS |
12762 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12763 | BFD_RELOC_LO16, AT); | |
12764 | if (op[0] != RA) | |
252b5132 RH |
12765 | { |
12766 | /* FIXME: How in the world do we deal with the possible | |
12767 | overflow here? */ | |
12768 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12769 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12770 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12771 | } |
12772 | } | |
252b5132 RH |
12773 | break; |
12774 | ||
12775 | case M_LI_DD: | |
ca4e0257 RS |
12776 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12777 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12778 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12779 | the value and the low order 32 bits are either zero or in | |
12780 | OFFSET_EXPR. */ | |
b0e6f033 | 12781 | if (imm_expr.X_op == O_constant) |
252b5132 | 12782 | { |
9b444f95 FS |
12783 | tempreg = ZERO; |
12784 | if (((FPR_SIZE == 64 && GPR_SIZE == 64) | |
12785 | || !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12786 | && imm_expr.X_add_number != 0) | |
12787 | { | |
12788 | used_at = 1; | |
12789 | tempreg = AT; | |
12790 | load_register (AT, &imm_expr, FPR_SIZE == 64); | |
12791 | } | |
351cdf24 | 12792 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
9b444f95 | 12793 | macro_build (NULL, "dmtc1", "t,S", tempreg, op[0]); |
252b5132 RH |
12794 | else |
12795 | { | |
9b444f95 FS |
12796 | if (!ISA_HAS_MXHC1 (mips_opts.isa)) |
12797 | { | |
12798 | if (FPR_SIZE != 32) | |
12799 | as_bad (_("Unable to generate `%s' compliant code " | |
12800 | "without mthc1"), | |
12801 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12802 | else | |
12803 | macro_build (NULL, "mtc1", "t,G", tempreg, op[0] + 1); | |
12804 | } | |
252b5132 | 12805 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12806 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12807 | else |
12808 | { | |
9c2799c2 | 12809 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12810 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12811 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 | 12812 | } |
9b444f95 FS |
12813 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12814 | { | |
12815 | if (imm_expr.X_add_number != 0) | |
12816 | { | |
12817 | used_at = 1; | |
12818 | tempreg = AT; | |
12819 | load_register (AT, &imm_expr, 0); | |
12820 | } | |
12821 | macro_build (NULL, "mthc1", "t,G", tempreg, op[0]); | |
12822 | } | |
252b5132 RH |
12823 | } |
12824 | break; | |
12825 | } | |
12826 | ||
b0e6f033 RS |
12827 | gas_assert (imm_expr.X_op == O_absent |
12828 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12829 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12830 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12831 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12832 | { |
12833 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12834 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12835 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12836 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12837 | } |
12838 | else | |
12839 | { | |
9c2799c2 | 12840 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12841 | used_at = 1; |
0a44bf69 | 12842 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12843 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12844 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12845 | else |
12846 | { | |
12847 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12848 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12849 | } |
bdaaa2e1 | 12850 | |
c0ebe874 | 12851 | op[2] = AT; |
f2ae14a1 RS |
12852 | offset_reloc[0] = BFD_RELOC_LO16; |
12853 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12854 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12855 | } |
f2ae14a1 | 12856 | align = 8; |
6f2117ba | 12857 | /* Fall through. */ |
c4a68bea | 12858 | |
252b5132 | 12859 | case M_L_DAB: |
6f2117ba PH |
12860 | /* The MIPS assembler seems to check for X_add_number not |
12861 | being double aligned and generating: | |
12862 | lui at,%hi(foo+1) | |
12863 | addu at,at,v1 | |
12864 | addiu at,at,%lo(foo+1) | |
12865 | lwc1 f2,0(at) | |
12866 | lwc1 f3,4(at) | |
12867 | But, the resulting address is the same after relocation so why | |
12868 | generate the extra instruction? */ | |
bdaaa2e1 | 12869 | /* Itbl support may require additional care here. */ |
252b5132 | 12870 | coproc = 1; |
df58fc94 | 12871 | fmt = "T,o(b)"; |
0aa27725 | 12872 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12873 | { |
12874 | s = "ldc1"; | |
df58fc94 | 12875 | goto ld_st; |
252b5132 | 12876 | } |
252b5132 | 12877 | s = "lwc1"; |
252b5132 RH |
12878 | goto ldd_std; |
12879 | ||
12880 | case M_S_DAB: | |
df58fc94 RS |
12881 | gas_assert (!mips_opts.micromips); |
12882 | /* Itbl support may require additional care here. */ | |
12883 | coproc = 1; | |
12884 | fmt = "T,o(b)"; | |
0aa27725 | 12885 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12886 | { |
12887 | s = "sdc1"; | |
df58fc94 | 12888 | goto ld_st; |
252b5132 | 12889 | } |
252b5132 | 12890 | s = "swc1"; |
252b5132 RH |
12891 | goto ldd_std; |
12892 | ||
e407c74b NC |
12893 | case M_LQ_AB: |
12894 | fmt = "t,o(b)"; | |
12895 | s = "lq"; | |
12896 | goto ld; | |
12897 | ||
12898 | case M_SQ_AB: | |
12899 | fmt = "t,o(b)"; | |
12900 | s = "sq"; | |
12901 | goto ld_st; | |
12902 | ||
252b5132 | 12903 | case M_LD_AB: |
df58fc94 | 12904 | fmt = "t,o(b)"; |
bad1aba3 | 12905 | if (GPR_SIZE == 64) |
252b5132 RH |
12906 | { |
12907 | s = "ld"; | |
12908 | goto ld; | |
12909 | } | |
252b5132 | 12910 | s = "lw"; |
252b5132 RH |
12911 | goto ldd_std; |
12912 | ||
12913 | case M_SD_AB: | |
df58fc94 | 12914 | fmt = "t,o(b)"; |
bad1aba3 | 12915 | if (GPR_SIZE == 64) |
252b5132 RH |
12916 | { |
12917 | s = "sd"; | |
df58fc94 | 12918 | goto ld_st; |
252b5132 | 12919 | } |
252b5132 | 12920 | s = "sw"; |
252b5132 RH |
12921 | |
12922 | ldd_std: | |
f2ae14a1 RS |
12923 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12924 | to adjust when loading from memory. We set coproc if we must | |
12925 | load $fn+1 first. */ | |
12926 | /* Itbl support may require additional care here. */ | |
12927 | if (!target_big_endian) | |
12928 | coproc = 0; | |
12929 | ||
c0ebe874 | 12930 | breg = op[2]; |
f2ae14a1 RS |
12931 | if (small_offset_p (0, align, 16)) |
12932 | { | |
12933 | ep = &offset_expr; | |
12934 | if (!small_offset_p (4, align, 16)) | |
12935 | { | |
12936 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12937 | -1, offset_reloc[0], offset_reloc[1], | |
12938 | offset_reloc[2]); | |
12939 | expr1.X_add_number = 0; | |
12940 | ep = &expr1; | |
12941 | breg = AT; | |
12942 | used_at = 1; | |
12943 | offset_reloc[0] = BFD_RELOC_LO16; | |
12944 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12945 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12946 | } | |
c0ebe874 | 12947 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12948 | { |
12949 | ep->X_add_number += 4; | |
c0ebe874 | 12950 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12951 | offset_reloc[1], offset_reloc[2], breg); |
12952 | ep->X_add_number -= 4; | |
c0ebe874 | 12953 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12954 | offset_reloc[1], offset_reloc[2], breg); |
12955 | } | |
12956 | else | |
12957 | { | |
c0ebe874 | 12958 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12959 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12960 | breg); | |
12961 | ep->X_add_number += 4; | |
c0ebe874 | 12962 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12963 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12964 | breg); | |
12965 | } | |
12966 | break; | |
12967 | } | |
12968 | ||
252b5132 RH |
12969 | if (offset_expr.X_op != O_symbol |
12970 | && offset_expr.X_op != O_constant) | |
12971 | { | |
1661c76c | 12972 | as_bad (_("expression too complex")); |
252b5132 RH |
12973 | offset_expr.X_op = O_constant; |
12974 | } | |
12975 | ||
2051e8c4 MR |
12976 | if (HAVE_32BIT_ADDRESSES |
12977 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12978 | { |
12979 | char value [32]; | |
12980 | ||
12981 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12982 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12983 | } |
2051e8c4 | 12984 | |
90ecf173 | 12985 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12986 | { |
12987 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12988 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12989 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12990 | If we have a base register, we use this |
12991 | addu $at,$breg,$gp | |
c0ebe874 RS |
12992 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12993 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12994 | If this is not a GP relative symbol, we want |
12995 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12996 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12997 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12998 | If there is a base register, we add it to $at after the |
12999 | lui instruction. If there is a constant, we always use | |
13000 | the last case. */ | |
39a59cf8 MR |
13001 | if (offset_expr.X_op == O_symbol |
13002 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 13003 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 13004 | { |
4d7206a2 | 13005 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
13006 | if (breg == 0) |
13007 | { | |
c9914766 | 13008 | tempreg = mips_gp_register; |
252b5132 RH |
13009 | } |
13010 | else | |
13011 | { | |
67c0d1eb | 13012 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 13013 | AT, breg, mips_gp_register); |
252b5132 | 13014 | tempreg = AT; |
252b5132 RH |
13015 | used_at = 1; |
13016 | } | |
13017 | ||
beae10d5 | 13018 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13019 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13020 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
13021 | offset_expr.X_add_number += 4; |
13022 | ||
13023 | /* Set mips_optimize to 2 to avoid inserting an | |
13024 | undesired nop. */ | |
13025 | hold_mips_optimize = mips_optimize; | |
13026 | mips_optimize = 2; | |
beae10d5 | 13027 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13028 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13029 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
13030 | mips_optimize = hold_mips_optimize; |
13031 | ||
4d7206a2 | 13032 | relax_switch (); |
252b5132 | 13033 | |
0970e49e | 13034 | offset_expr.X_add_number -= 4; |
252b5132 | 13035 | } |
8fc2e39e | 13036 | used_at = 1; |
f2ae14a1 RS |
13037 | if (offset_high_part (offset_expr.X_add_number, 16) |
13038 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
13039 | { | |
13040 | load_address (AT, &offset_expr, &used_at); | |
13041 | offset_expr.X_op = O_constant; | |
13042 | offset_expr.X_add_number = 0; | |
13043 | } | |
13044 | else | |
13045 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 13046 | if (breg != 0) |
67c0d1eb | 13047 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13048 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13049 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13050 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13051 | /* FIXME: How do we handle overflow here? */ |
13052 | offset_expr.X_add_number += 4; | |
beae10d5 | 13053 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13054 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13055 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
13056 | if (mips_relax.sequence) |
13057 | relax_end (); | |
bdaaa2e1 | 13058 | } |
0a44bf69 | 13059 | else if (!mips_big_got) |
252b5132 | 13060 | { |
252b5132 RH |
13061 | /* If this is a reference to an external symbol, we want |
13062 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13063 | nop | |
c0ebe874 RS |
13064 | <op> op[0],0($at) |
13065 | <op> op[0]+1,4($at) | |
252b5132 RH |
13066 | Otherwise we want |
13067 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13068 | nop | |
c0ebe874 RS |
13069 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
13070 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
13071 | If there is a base register we add it to $at before the |
13072 | lwc1 instructions. If there is a constant we include it | |
13073 | in the lwc1 instructions. */ | |
13074 | used_at = 1; | |
13075 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
13076 | if (expr1.X_add_number < -0x8000 |
13077 | || expr1.X_add_number >= 0x8000 - 4) | |
13078 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 13079 | load_got_offset (AT, &offset_expr); |
269137b2 | 13080 | load_delay_nop (); |
252b5132 | 13081 | if (breg != 0) |
67c0d1eb | 13082 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
13083 | |
13084 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13085 | nop. */ | |
13086 | hold_mips_optimize = mips_optimize; | |
13087 | mips_optimize = 2; | |
4d7206a2 | 13088 | |
beae10d5 | 13089 | /* Itbl support may require additional care here. */ |
4d7206a2 | 13090 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 13091 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13092 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13093 | expr1.X_add_number += 4; |
c0ebe874 | 13094 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13095 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13096 | relax_switch (); |
c0ebe874 | 13097 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13098 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13099 | offset_expr.X_add_number += 4; |
c0ebe874 | 13100 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13101 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13102 | relax_end (); |
252b5132 | 13103 | |
4d7206a2 | 13104 | mips_optimize = hold_mips_optimize; |
252b5132 | 13105 | } |
0a44bf69 | 13106 | else if (mips_big_got) |
252b5132 | 13107 | { |
67c0d1eb | 13108 | int gpdelay; |
252b5132 RH |
13109 | |
13110 | /* If this is a reference to an external symbol, we want | |
13111 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
13112 | addu $at,$at,$gp | |
13113 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
13114 | nop | |
c0ebe874 RS |
13115 | <op> op[0],0($at) |
13116 | <op> op[0]+1,4($at) | |
252b5132 RH |
13117 | Otherwise we want |
13118 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13119 | nop | |
c0ebe874 RS |
13120 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
13121 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
13122 | If there is a base register we add it to $at before the |
13123 | lwc1 instructions. If there is a constant we include it | |
13124 | in the lwc1 instructions. */ | |
13125 | used_at = 1; | |
13126 | expr1.X_add_number = offset_expr.X_add_number; | |
13127 | offset_expr.X_add_number = 0; | |
13128 | if (expr1.X_add_number < -0x8000 | |
13129 | || expr1.X_add_number >= 0x8000 - 4) | |
13130 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 13131 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 13132 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 13133 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
13134 | AT, BFD_RELOC_MIPS_GOT_HI16); |
13135 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 13136 | AT, AT, mips_gp_register); |
67c0d1eb | 13137 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 13138 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 13139 | load_delay_nop (); |
252b5132 | 13140 | if (breg != 0) |
67c0d1eb | 13141 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13142 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13143 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13144 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13145 | expr1.X_add_number += 4; |
13146 | ||
13147 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13148 | nop. */ | |
13149 | hold_mips_optimize = mips_optimize; | |
13150 | mips_optimize = 2; | |
beae10d5 | 13151 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13152 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13153 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13154 | mips_optimize = hold_mips_optimize; |
13155 | expr1.X_add_number -= 4; | |
13156 | ||
4d7206a2 RS |
13157 | relax_switch (); |
13158 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
13159 | if (gpdelay) |
13160 | macro_build (NULL, "nop", ""); | |
13161 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
13162 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 13163 | load_delay_nop (); |
252b5132 | 13164 | if (breg != 0) |
67c0d1eb | 13165 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13166 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13167 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13168 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13169 | offset_expr.X_add_number += 4; |
252b5132 RH |
13170 | |
13171 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13172 | nop. */ | |
13173 | hold_mips_optimize = mips_optimize; | |
13174 | mips_optimize = 2; | |
beae10d5 | 13175 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13176 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13177 | BFD_RELOC_LO16, AT); |
252b5132 | 13178 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 13179 | relax_end (); |
252b5132 | 13180 | } |
252b5132 RH |
13181 | else |
13182 | abort (); | |
13183 | ||
252b5132 | 13184 | break; |
3739860c | 13185 | |
dd6a37e7 | 13186 | case M_SAA_AB: |
dd6a37e7 | 13187 | s = "saa"; |
0db377d0 | 13188 | goto saa_saad; |
dd6a37e7 | 13189 | case M_SAAD_AB: |
dd6a37e7 | 13190 | s = "saad"; |
0db377d0 MR |
13191 | saa_saad: |
13192 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 13193 | offbits = 0; |
dd6a37e7 AP |
13194 | fmt = "t,(b)"; |
13195 | goto ld_st; | |
13196 | ||
252b5132 RH |
13197 | /* New code added to support COPZ instructions. |
13198 | This code builds table entries out of the macros in mip_opcodes. | |
13199 | R4000 uses interlocks to handle coproc delays. | |
13200 | Other chips (like the R3000) require nops to be inserted for delays. | |
13201 | ||
f72c8c98 | 13202 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
13203 | In order to fill delay slots for non-interlocked chips, |
13204 | we must have a way to specify delays based on the coprocessor. | |
13205 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
13206 | What are the side-effects of the cop instruction? | |
13207 | What cache support might we have and what are its effects? | |
13208 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 13209 | What registers are read/set/modified? |
252b5132 RH |
13210 | |
13211 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 13212 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
13213 | |
13214 | case M_COP0: | |
13215 | s = "c0"; | |
13216 | goto copz; | |
13217 | case M_COP1: | |
13218 | s = "c1"; | |
13219 | goto copz; | |
13220 | case M_COP2: | |
13221 | s = "c2"; | |
13222 | goto copz; | |
13223 | case M_COP3: | |
13224 | s = "c3"; | |
13225 | copz: | |
df58fc94 | 13226 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
13227 | /* For now we just do C (same as Cz). The parameter will be |
13228 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 13229 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 13230 | break; |
252b5132 | 13231 | |
ea1fb5dc | 13232 | case M_MOVE: |
c0ebe874 | 13233 | move_register (op[0], op[1]); |
8fc2e39e | 13234 | break; |
ea1fb5dc | 13235 | |
833794fc MR |
13236 | case M_MOVEP: |
13237 | gas_assert (mips_opts.micromips); | |
13238 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
13239 | move_register (micromips_to_32_reg_h_map1[op[0]], |
13240 | micromips_to_32_reg_m_map[op[1]]); | |
13241 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
13242 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
13243 | break; |
13244 | ||
252b5132 RH |
13245 | case M_DMUL: |
13246 | dbl = 1; | |
1a0670f3 | 13247 | /* Fall through. */ |
252b5132 | 13248 | case M_MUL: |
e407c74b | 13249 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
13250 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
13251 | op[2]); | |
e407c74b NC |
13252 | else |
13253 | { | |
c0ebe874 RS |
13254 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
13255 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 13256 | } |
8fc2e39e | 13257 | break; |
252b5132 RH |
13258 | |
13259 | case M_DMUL_I: | |
13260 | dbl = 1; | |
1a0670f3 | 13261 | /* Fall through. */ |
252b5132 RH |
13262 | case M_MUL_I: |
13263 | /* The MIPS assembler some times generates shifts and adds. I'm | |
13264 | not trying to be that fancy. GCC should do this for us | |
13265 | anyway. */ | |
8fc2e39e | 13266 | used_at = 1; |
67c0d1eb | 13267 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13268 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
13269 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
13270 | break; |
13271 | ||
13272 | case M_DMULO_I: | |
13273 | dbl = 1; | |
1a0670f3 | 13274 | /* Fall through. */ |
252b5132 RH |
13275 | case M_MULO_I: |
13276 | imm = 1; | |
13277 | goto do_mulo; | |
13278 | ||
13279 | case M_DMULO: | |
13280 | dbl = 1; | |
1a0670f3 | 13281 | /* Fall through. */ |
252b5132 RH |
13282 | case M_MULO: |
13283 | do_mulo: | |
7d10b47d | 13284 | start_noreorder (); |
8fc2e39e | 13285 | used_at = 1; |
252b5132 | 13286 | if (imm) |
67c0d1eb | 13287 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13288 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
13289 | op[1], imm ? AT : op[2]); | |
13290 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
13291 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 13292 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 13293 | if (mips_trap) |
c0ebe874 | 13294 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
13295 | else |
13296 | { | |
df58fc94 RS |
13297 | if (mips_opts.micromips) |
13298 | micromips_label_expr (&label_expr); | |
13299 | else | |
13300 | label_expr.X_add_number = 8; | |
c0ebe874 | 13301 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 13302 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13303 | macro_build (NULL, "break", BRK_FMT, 6); |
13304 | if (mips_opts.micromips) | |
13305 | micromips_add_label (); | |
252b5132 | 13306 | } |
7d10b47d | 13307 | end_noreorder (); |
c0ebe874 | 13308 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
13309 | break; |
13310 | ||
13311 | case M_DMULOU_I: | |
13312 | dbl = 1; | |
1a0670f3 | 13313 | /* Fall through. */ |
252b5132 RH |
13314 | case M_MULOU_I: |
13315 | imm = 1; | |
13316 | goto do_mulou; | |
13317 | ||
13318 | case M_DMULOU: | |
13319 | dbl = 1; | |
1a0670f3 | 13320 | /* Fall through. */ |
252b5132 RH |
13321 | case M_MULOU: |
13322 | do_mulou: | |
7d10b47d | 13323 | start_noreorder (); |
8fc2e39e | 13324 | used_at = 1; |
252b5132 | 13325 | if (imm) |
67c0d1eb RS |
13326 | load_register (AT, &imm_expr, dbl); |
13327 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 13328 | op[1], imm ? AT : op[2]); |
df58fc94 | 13329 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 13330 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 13331 | if (mips_trap) |
df58fc94 | 13332 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
13333 | else |
13334 | { | |
df58fc94 RS |
13335 | if (mips_opts.micromips) |
13336 | micromips_label_expr (&label_expr); | |
13337 | else | |
13338 | label_expr.X_add_number = 8; | |
13339 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 13340 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13341 | macro_build (NULL, "break", BRK_FMT, 6); |
13342 | if (mips_opts.micromips) | |
13343 | micromips_add_label (); | |
252b5132 | 13344 | } |
7d10b47d | 13345 | end_noreorder (); |
252b5132 RH |
13346 | break; |
13347 | ||
771c7ce4 | 13348 | case M_DROL: |
fef14a42 | 13349 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13350 | { |
c0ebe874 | 13351 | if (op[0] == op[1]) |
82dd0097 CD |
13352 | { |
13353 | tempreg = AT; | |
13354 | used_at = 1; | |
13355 | } | |
13356 | else | |
c0ebe874 RS |
13357 | tempreg = op[0]; |
13358 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
13359 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13360 | break; |
82dd0097 | 13361 | } |
8fc2e39e | 13362 | used_at = 1; |
c0ebe874 RS |
13363 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13364 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
13365 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
13366 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13367 | break; |
13368 | ||
252b5132 | 13369 | case M_ROL: |
fef14a42 | 13370 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13371 | { |
c0ebe874 | 13372 | if (op[0] == op[1]) |
82dd0097 CD |
13373 | { |
13374 | tempreg = AT; | |
13375 | used_at = 1; | |
13376 | } | |
13377 | else | |
c0ebe874 RS |
13378 | tempreg = op[0]; |
13379 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
13380 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13381 | break; |
82dd0097 | 13382 | } |
8fc2e39e | 13383 | used_at = 1; |
c0ebe874 RS |
13384 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13385 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
13386 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
13387 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13388 | break; |
13389 | ||
771c7ce4 TS |
13390 | case M_DROL_I: |
13391 | { | |
13392 | unsigned int rot; | |
e0471c16 TS |
13393 | const char *l; |
13394 | const char *rr; | |
771c7ce4 | 13395 | |
771c7ce4 | 13396 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13397 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
13398 | { |
13399 | rot = (64 - rot) & 0x3f; | |
13400 | if (rot >= 32) | |
c0ebe874 | 13401 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 13402 | else |
c0ebe874 | 13403 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13404 | break; |
60b63b72 | 13405 | } |
483fc7cd | 13406 | if (rot == 0) |
483fc7cd | 13407 | { |
c0ebe874 | 13408 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13409 | break; |
483fc7cd | 13410 | } |
82dd0097 | 13411 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 13412 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 13413 | rot &= 0x1f; |
8fc2e39e | 13414 | used_at = 1; |
c0ebe874 RS |
13415 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
13416 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13417 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13418 | } |
13419 | break; | |
13420 | ||
252b5132 | 13421 | case M_ROL_I: |
771c7ce4 TS |
13422 | { |
13423 | unsigned int rot; | |
13424 | ||
771c7ce4 | 13425 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13426 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 13427 | { |
c0ebe874 RS |
13428 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
13429 | (32 - rot) & 0x1f); | |
8fc2e39e | 13430 | break; |
60b63b72 | 13431 | } |
483fc7cd | 13432 | if (rot == 0) |
483fc7cd | 13433 | { |
c0ebe874 | 13434 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13435 | break; |
483fc7cd | 13436 | } |
8fc2e39e | 13437 | used_at = 1; |
c0ebe874 RS |
13438 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
13439 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13440 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13441 | } |
13442 | break; | |
13443 | ||
13444 | case M_DROR: | |
fef14a42 | 13445 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13446 | { |
c0ebe874 | 13447 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13448 | break; |
82dd0097 | 13449 | } |
8fc2e39e | 13450 | used_at = 1; |
c0ebe874 RS |
13451 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13452 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13453 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13454 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13455 | break; |
13456 | ||
13457 | case M_ROR: | |
fef14a42 | 13458 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13459 | { |
c0ebe874 | 13460 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13461 | break; |
82dd0097 | 13462 | } |
8fc2e39e | 13463 | used_at = 1; |
c0ebe874 RS |
13464 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13465 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13466 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13467 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13468 | break; |
13469 | ||
771c7ce4 TS |
13470 | case M_DROR_I: |
13471 | { | |
13472 | unsigned int rot; | |
e0471c16 TS |
13473 | const char *l; |
13474 | const char *rr; | |
771c7ce4 | 13475 | |
771c7ce4 | 13476 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13477 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13478 | { |
13479 | if (rot >= 32) | |
c0ebe874 | 13480 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13481 | else |
c0ebe874 | 13482 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13483 | break; |
82dd0097 | 13484 | } |
483fc7cd | 13485 | if (rot == 0) |
483fc7cd | 13486 | { |
c0ebe874 | 13487 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13488 | break; |
483fc7cd | 13489 | } |
91d6fa6a | 13490 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13491 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13492 | rot &= 0x1f; | |
8fc2e39e | 13493 | used_at = 1; |
c0ebe874 RS |
13494 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13495 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13496 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13497 | } |
13498 | break; | |
13499 | ||
252b5132 | 13500 | case M_ROR_I: |
771c7ce4 TS |
13501 | { |
13502 | unsigned int rot; | |
13503 | ||
771c7ce4 | 13504 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13505 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13506 | { |
c0ebe874 | 13507 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13508 | break; |
82dd0097 | 13509 | } |
483fc7cd | 13510 | if (rot == 0) |
483fc7cd | 13511 | { |
c0ebe874 | 13512 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13513 | break; |
483fc7cd | 13514 | } |
8fc2e39e | 13515 | used_at = 1; |
c0ebe874 RS |
13516 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13517 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13518 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13519 | } |
252b5132 RH |
13520 | break; |
13521 | ||
252b5132 | 13522 | case M_SEQ: |
c0ebe874 RS |
13523 | if (op[1] == 0) |
13524 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13525 | else if (op[2] == 0) | |
13526 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13527 | else |
13528 | { | |
c0ebe874 RS |
13529 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13530 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13531 | } |
8fc2e39e | 13532 | break; |
252b5132 RH |
13533 | |
13534 | case M_SEQ_I: | |
b0e6f033 | 13535 | if (imm_expr.X_add_number == 0) |
252b5132 | 13536 | { |
c0ebe874 | 13537 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13538 | break; |
252b5132 | 13539 | } |
c0ebe874 | 13540 | if (op[1] == 0) |
252b5132 | 13541 | { |
1661c76c | 13542 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13543 | ip->insn_mo->name); |
c0ebe874 | 13544 | move_register (op[0], 0); |
8fc2e39e | 13545 | break; |
252b5132 | 13546 | } |
dd3cbb7e NC |
13547 | if (CPU_HAS_SEQ (mips_opts.arch) |
13548 | && -512 <= imm_expr.X_add_number | |
13549 | && imm_expr.X_add_number < 512) | |
13550 | { | |
c0ebe874 | 13551 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13552 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13553 | break; |
13554 | } | |
b0e6f033 | 13555 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13556 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13557 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13558 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13559 | && imm_expr.X_add_number < 0) |
13560 | { | |
13561 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13562 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13563 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13564 | } |
dd3cbb7e NC |
13565 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13566 | { | |
13567 | used_at = 1; | |
bad1aba3 | 13568 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13569 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13570 | break; |
13571 | } | |
252b5132 RH |
13572 | else |
13573 | { | |
bad1aba3 | 13574 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13575 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13576 | used_at = 1; |
13577 | } | |
c0ebe874 | 13578 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13579 | break; |
252b5132 | 13580 | |
c0ebe874 | 13581 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13582 | s = "slt"; |
13583 | goto sge; | |
13584 | case M_SGEU: | |
13585 | s = "sltu"; | |
13586 | sge: | |
c0ebe874 RS |
13587 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13588 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13589 | break; |
252b5132 | 13590 | |
6f2117ba | 13591 | case M_SGE_I: /* X >= I <==> not (X < I). */ |
252b5132 | 13592 | case M_SGEU_I: |
b0e6f033 | 13593 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13594 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13595 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13596 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13597 | else |
13598 | { | |
bad1aba3 | 13599 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13600 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13601 | op[0], op[1], AT); |
252b5132 RH |
13602 | used_at = 1; |
13603 | } | |
c0ebe874 | 13604 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13605 | break; |
252b5132 | 13606 | |
6f2117ba | 13607 | case M_SGT: /* X > Y <==> Y < X. */ |
252b5132 RH |
13608 | s = "slt"; |
13609 | goto sgt; | |
13610 | case M_SGTU: | |
13611 | s = "sltu"; | |
13612 | sgt: | |
c0ebe874 | 13613 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13614 | break; |
252b5132 | 13615 | |
6f2117ba | 13616 | case M_SGT_I: /* X > I <==> I < X. */ |
252b5132 RH |
13617 | s = "slt"; |
13618 | goto sgti; | |
13619 | case M_SGTU_I: | |
13620 | s = "sltu"; | |
13621 | sgti: | |
8fc2e39e | 13622 | used_at = 1; |
bad1aba3 | 13623 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13624 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13625 | break; |
13626 | ||
6f2117ba | 13627 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X). */ |
252b5132 RH |
13628 | s = "slt"; |
13629 | goto sle; | |
13630 | case M_SLEU: | |
13631 | s = "sltu"; | |
13632 | sle: | |
c0ebe874 RS |
13633 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13634 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13635 | break; |
252b5132 | 13636 | |
c0ebe874 | 13637 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13638 | s = "slt"; |
13639 | goto slei; | |
13640 | case M_SLEU_I: | |
13641 | s = "sltu"; | |
13642 | slei: | |
8fc2e39e | 13643 | used_at = 1; |
bad1aba3 | 13644 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13645 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13646 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13647 | break; |
13648 | ||
13649 | case M_SLT_I: | |
b0e6f033 | 13650 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13651 | && imm_expr.X_add_number < 0x8000) |
13652 | { | |
c0ebe874 RS |
13653 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13654 | BFD_RELOC_LO16); | |
8fc2e39e | 13655 | break; |
252b5132 | 13656 | } |
8fc2e39e | 13657 | used_at = 1; |
bad1aba3 | 13658 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13659 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13660 | break; |
13661 | ||
13662 | case M_SLTU_I: | |
b0e6f033 | 13663 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13664 | && imm_expr.X_add_number < 0x8000) |
13665 | { | |
c0ebe874 | 13666 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13667 | BFD_RELOC_LO16); |
8fc2e39e | 13668 | break; |
252b5132 | 13669 | } |
8fc2e39e | 13670 | used_at = 1; |
bad1aba3 | 13671 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13672 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13673 | break; |
13674 | ||
13675 | case M_SNE: | |
c0ebe874 RS |
13676 | if (op[1] == 0) |
13677 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13678 | else if (op[2] == 0) | |
13679 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13680 | else |
13681 | { | |
c0ebe874 RS |
13682 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13683 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13684 | } |
8fc2e39e | 13685 | break; |
252b5132 RH |
13686 | |
13687 | case M_SNE_I: | |
b0e6f033 | 13688 | if (imm_expr.X_add_number == 0) |
252b5132 | 13689 | { |
c0ebe874 | 13690 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13691 | break; |
252b5132 | 13692 | } |
c0ebe874 | 13693 | if (op[1] == 0) |
252b5132 | 13694 | { |
1661c76c | 13695 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13696 | ip->insn_mo->name); |
bad1aba3 | 13697 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13698 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13699 | break; |
252b5132 | 13700 | } |
dd3cbb7e NC |
13701 | if (CPU_HAS_SEQ (mips_opts.arch) |
13702 | && -512 <= imm_expr.X_add_number | |
13703 | && imm_expr.X_add_number < 512) | |
13704 | { | |
c0ebe874 | 13705 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13706 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13707 | break; |
13708 | } | |
b0e6f033 | 13709 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13710 | && imm_expr.X_add_number < 0x10000) |
13711 | { | |
c0ebe874 RS |
13712 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13713 | BFD_RELOC_LO16); | |
252b5132 | 13714 | } |
b0e6f033 | 13715 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13716 | && imm_expr.X_add_number < 0) |
13717 | { | |
13718 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13719 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13720 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13721 | } |
dd3cbb7e NC |
13722 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13723 | { | |
13724 | used_at = 1; | |
bad1aba3 | 13725 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13726 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13727 | break; |
13728 | } | |
252b5132 RH |
13729 | else |
13730 | { | |
bad1aba3 | 13731 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13732 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13733 | used_at = 1; |
13734 | } | |
c0ebe874 | 13735 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13736 | break; |
252b5132 | 13737 | |
df58fc94 RS |
13738 | case M_SUB_I: |
13739 | s = "addi"; | |
13740 | s2 = "sub"; | |
387e7624 FS |
13741 | if (ISA_IS_R6 (mips_opts.isa)) |
13742 | goto do_subi_i; | |
13743 | else | |
13744 | goto do_subi; | |
df58fc94 RS |
13745 | case M_SUBU_I: |
13746 | s = "addiu"; | |
13747 | s2 = "subu"; | |
13748 | goto do_subi; | |
252b5132 RH |
13749 | case M_DSUB_I: |
13750 | dbl = 1; | |
df58fc94 RS |
13751 | s = "daddi"; |
13752 | s2 = "dsub"; | |
387e7624 | 13753 | if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa)) |
df58fc94 | 13754 | goto do_subi; |
b0e6f033 | 13755 | if (imm_expr.X_add_number > -0x200 |
387e7624 FS |
13756 | && imm_expr.X_add_number <= 0x200 |
13757 | && !ISA_IS_R6 (mips_opts.isa)) | |
252b5132 | 13758 | { |
b0e6f033 RS |
13759 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13760 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13761 | break; |
252b5132 | 13762 | } |
df58fc94 | 13763 | goto do_subi_i; |
252b5132 RH |
13764 | case M_DSUBU_I: |
13765 | dbl = 1; | |
df58fc94 RS |
13766 | s = "daddiu"; |
13767 | s2 = "dsubu"; | |
13768 | do_subi: | |
b0e6f033 | 13769 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13770 | && imm_expr.X_add_number <= 0x8000) |
13771 | { | |
13772 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13773 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13774 | break; |
252b5132 | 13775 | } |
df58fc94 | 13776 | do_subi_i: |
8fc2e39e | 13777 | used_at = 1; |
67c0d1eb | 13778 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13779 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13780 | break; |
13781 | ||
13782 | case M_TEQ_I: | |
13783 | s = "teq"; | |
13784 | goto trap; | |
13785 | case M_TGE_I: | |
13786 | s = "tge"; | |
13787 | goto trap; | |
13788 | case M_TGEU_I: | |
13789 | s = "tgeu"; | |
13790 | goto trap; | |
13791 | case M_TLT_I: | |
13792 | s = "tlt"; | |
13793 | goto trap; | |
13794 | case M_TLTU_I: | |
13795 | s = "tltu"; | |
13796 | goto trap; | |
13797 | case M_TNE_I: | |
13798 | s = "tne"; | |
13799 | trap: | |
8fc2e39e | 13800 | used_at = 1; |
bad1aba3 | 13801 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13802 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13803 | break; |
13804 | ||
252b5132 | 13805 | case M_TRUNCWS: |
43841e91 | 13806 | case M_TRUNCWD: |
df58fc94 | 13807 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13808 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13809 | used_at = 1; |
252b5132 RH |
13810 | |
13811 | /* | |
13812 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13813 | * or is there a reason for it? | |
13814 | */ | |
7d10b47d | 13815 | start_noreorder (); |
c0ebe874 RS |
13816 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13817 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13818 | macro_build (NULL, "nop", ""); |
252b5132 | 13819 | expr1.X_add_number = 3; |
c0ebe874 | 13820 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13821 | expr1.X_add_number = 2; |
67c0d1eb RS |
13822 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13823 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13824 | macro_build (NULL, "nop", ""); | |
13825 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13826 | op[0], op[1]); |
13827 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13828 | macro_build (NULL, "nop", ""); |
7d10b47d | 13829 | end_noreorder (); |
252b5132 RH |
13830 | break; |
13831 | ||
f2ae14a1 | 13832 | case M_ULH_AB: |
252b5132 | 13833 | s = "lb"; |
df58fc94 RS |
13834 | s2 = "lbu"; |
13835 | off = 1; | |
13836 | goto uld_st; | |
f2ae14a1 | 13837 | case M_ULHU_AB: |
252b5132 | 13838 | s = "lbu"; |
df58fc94 RS |
13839 | s2 = "lbu"; |
13840 | off = 1; | |
13841 | goto uld_st; | |
f2ae14a1 | 13842 | case M_ULW_AB: |
df58fc94 RS |
13843 | s = "lwl"; |
13844 | s2 = "lwr"; | |
7f3c4072 | 13845 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13846 | off = 3; |
13847 | goto uld_st; | |
f2ae14a1 | 13848 | case M_ULD_AB: |
252b5132 RH |
13849 | s = "ldl"; |
13850 | s2 = "ldr"; | |
7f3c4072 | 13851 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13852 | off = 7; |
df58fc94 | 13853 | goto uld_st; |
f2ae14a1 | 13854 | case M_USH_AB: |
df58fc94 RS |
13855 | s = "sb"; |
13856 | s2 = "sb"; | |
13857 | off = 1; | |
13858 | ust = 1; | |
13859 | goto uld_st; | |
f2ae14a1 | 13860 | case M_USW_AB: |
df58fc94 RS |
13861 | s = "swl"; |
13862 | s2 = "swr"; | |
7f3c4072 | 13863 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13864 | off = 3; |
df58fc94 RS |
13865 | ust = 1; |
13866 | goto uld_st; | |
f2ae14a1 | 13867 | case M_USD_AB: |
df58fc94 RS |
13868 | s = "sdl"; |
13869 | s2 = "sdr"; | |
7f3c4072 | 13870 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13871 | off = 7; |
13872 | ust = 1; | |
13873 | ||
13874 | uld_st: | |
c0ebe874 | 13875 | breg = op[2]; |
f2ae14a1 | 13876 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13877 | ep = &offset_expr; |
13878 | expr1.X_add_number = 0; | |
f2ae14a1 | 13879 | if (large_offset) |
df58fc94 RS |
13880 | { |
13881 | used_at = 1; | |
13882 | tempreg = AT; | |
f2ae14a1 RS |
13883 | if (small_offset_p (0, align, 16)) |
13884 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13885 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13886 | else | |
13887 | { | |
13888 | load_address (tempreg, ep, &used_at); | |
13889 | if (breg != 0) | |
13890 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13891 | tempreg, tempreg, breg); | |
13892 | } | |
13893 | offset_reloc[0] = BFD_RELOC_LO16; | |
13894 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13895 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13896 | breg = tempreg; |
c0ebe874 | 13897 | tempreg = op[0]; |
df58fc94 RS |
13898 | ep = &expr1; |
13899 | } | |
c0ebe874 | 13900 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13901 | { |
13902 | used_at = 1; | |
13903 | tempreg = AT; | |
13904 | } | |
252b5132 | 13905 | else |
c0ebe874 | 13906 | tempreg = op[0]; |
af22f5b2 | 13907 | |
df58fc94 RS |
13908 | if (off == 1) |
13909 | goto ulh_sh; | |
252b5132 | 13910 | |
90ecf173 | 13911 | if (!target_big_endian) |
df58fc94 | 13912 | ep->X_add_number += off; |
f2ae14a1 | 13913 | if (offbits == 12) |
c8276761 | 13914 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13915 | else |
13916 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13917 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13918 | |
90ecf173 | 13919 | if (!target_big_endian) |
df58fc94 | 13920 | ep->X_add_number -= off; |
252b5132 | 13921 | else |
df58fc94 | 13922 | ep->X_add_number += off; |
f2ae14a1 | 13923 | if (offbits == 12) |
df58fc94 | 13924 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13925 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13926 | else |
13927 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13928 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13929 | |
df58fc94 | 13930 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13931 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13932 | { |
13933 | /* Protect second load's delay slot. */ | |
13934 | load_delay_nop (); | |
c0ebe874 | 13935 | move_register (op[0], tempreg); |
df58fc94 | 13936 | } |
8fc2e39e | 13937 | break; |
252b5132 | 13938 | |
df58fc94 | 13939 | ulh_sh: |
d6bc6245 | 13940 | used_at = 1; |
df58fc94 RS |
13941 | if (target_big_endian == ust) |
13942 | ep->X_add_number += off; | |
c0ebe874 | 13943 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13944 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13945 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13946 | |
13947 | /* For halfword transfers we need a temporary register to shuffle | |
13948 | bytes. Unfortunately for M_USH_A we have none available before | |
13949 | the next store as AT holds the base address. We deal with this | |
13950 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13951 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13952 | if (ust) |
c0ebe874 | 13953 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13954 | |
13955 | if (target_big_endian == ust) | |
13956 | ep->X_add_number -= off; | |
252b5132 | 13957 | else |
df58fc94 | 13958 | ep->X_add_number += off; |
f2ae14a1 RS |
13959 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13960 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13961 | |
df58fc94 | 13962 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13963 | if (ust && large_offset) |
df58fc94 RS |
13964 | { |
13965 | if (target_big_endian) | |
13966 | ep->X_add_number += off; | |
13967 | else | |
13968 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13969 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13970 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13971 | } |
13972 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13973 | if (!ust || large_offset) |
df58fc94 | 13974 | { |
c0ebe874 | 13975 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13976 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13977 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13978 | } |
252b5132 RH |
13979 | break; |
13980 | ||
13981 | default: | |
13982 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13983 | are added dynamically. */ |
1661c76c | 13984 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13985 | break; |
13986 | } | |
741fe287 | 13987 | if (!mips_opts.at && used_at) |
1661c76c | 13988 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13989 | } |
13990 | ||
13991 | /* Implement macros in mips16 mode. */ | |
13992 | ||
13993 | static void | |
17a2f251 | 13994 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13995 | { |
c0ebe874 | 13996 | const struct mips_operand_array *operands; |
252b5132 | 13997 | int mask; |
c0ebe874 | 13998 | int tmp; |
252b5132 RH |
13999 | expressionS expr1; |
14000 | int dbl; | |
14001 | const char *s, *s2, *s3; | |
c0ebe874 RS |
14002 | unsigned int op[MAX_OPERANDS]; |
14003 | unsigned int i; | |
252b5132 RH |
14004 | |
14005 | mask = ip->insn_mo->mask; | |
14006 | ||
c0ebe874 RS |
14007 | operands = insn_operands (ip); |
14008 | for (i = 0; i < MAX_OPERANDS; i++) | |
14009 | if (operands->operand[i]) | |
14010 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
14011 | else | |
14012 | op[i] = -1; | |
252b5132 | 14013 | |
252b5132 RH |
14014 | expr1.X_op = O_constant; |
14015 | expr1.X_op_symbol = NULL; | |
14016 | expr1.X_add_symbol = NULL; | |
14017 | expr1.X_add_number = 1; | |
14018 | ||
14019 | dbl = 0; | |
14020 | ||
14021 | switch (mask) | |
14022 | { | |
14023 | default: | |
b37df7c4 | 14024 | abort (); |
252b5132 RH |
14025 | |
14026 | case M_DDIV_3: | |
14027 | dbl = 1; | |
1a0670f3 | 14028 | /* Fall through. */ |
252b5132 RH |
14029 | case M_DIV_3: |
14030 | s = "mflo"; | |
14031 | goto do_div3; | |
14032 | case M_DREM_3: | |
14033 | dbl = 1; | |
1a0670f3 | 14034 | /* Fall through. */ |
252b5132 RH |
14035 | case M_REM_3: |
14036 | s = "mfhi"; | |
14037 | do_div3: | |
7d10b47d | 14038 | start_noreorder (); |
d8722d76 | 14039 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 14040 | expr1.X_add_number = 2; |
c0ebe874 | 14041 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 14042 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 14043 | |
252b5132 RH |
14044 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
14045 | since that causes an overflow. We should do that as well, | |
14046 | but I don't see how to do the comparisons without a temporary | |
14047 | register. */ | |
7d10b47d | 14048 | end_noreorder (); |
c0ebe874 | 14049 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
14050 | break; |
14051 | ||
14052 | case M_DIVU_3: | |
14053 | s = "divu"; | |
14054 | s2 = "mflo"; | |
14055 | goto do_divu3; | |
14056 | case M_REMU_3: | |
14057 | s = "divu"; | |
14058 | s2 = "mfhi"; | |
14059 | goto do_divu3; | |
14060 | case M_DDIVU_3: | |
14061 | s = "ddivu"; | |
14062 | s2 = "mflo"; | |
14063 | goto do_divu3; | |
14064 | case M_DREMU_3: | |
14065 | s = "ddivu"; | |
14066 | s2 = "mfhi"; | |
14067 | do_divu3: | |
7d10b47d | 14068 | start_noreorder (); |
d8722d76 | 14069 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 14070 | expr1.X_add_number = 2; |
c0ebe874 | 14071 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 14072 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 14073 | end_noreorder (); |
c0ebe874 | 14074 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
14075 | break; |
14076 | ||
14077 | case M_DMUL: | |
14078 | dbl = 1; | |
1a0670f3 | 14079 | /* Fall through. */ |
252b5132 | 14080 | case M_MUL: |
c0ebe874 RS |
14081 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
14082 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 14083 | break; |
252b5132 RH |
14084 | |
14085 | case M_DSUBU_I: | |
14086 | dbl = 1; | |
14087 | goto do_subu; | |
14088 | case M_SUBU_I: | |
14089 | do_subu: | |
252b5132 | 14090 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 14091 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
14092 | break; |
14093 | ||
14094 | case M_SUBU_I_2: | |
252b5132 | 14095 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 14096 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
14097 | break; |
14098 | ||
14099 | case M_DSUBU_I_2: | |
252b5132 | 14100 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 14101 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
14102 | break; |
14103 | ||
14104 | case M_BEQ: | |
14105 | s = "cmp"; | |
14106 | s2 = "bteqz"; | |
14107 | goto do_branch; | |
14108 | case M_BNE: | |
14109 | s = "cmp"; | |
14110 | s2 = "btnez"; | |
14111 | goto do_branch; | |
14112 | case M_BLT: | |
14113 | s = "slt"; | |
14114 | s2 = "btnez"; | |
14115 | goto do_branch; | |
14116 | case M_BLTU: | |
14117 | s = "sltu"; | |
14118 | s2 = "btnez"; | |
14119 | goto do_branch; | |
14120 | case M_BLE: | |
14121 | s = "slt"; | |
14122 | s2 = "bteqz"; | |
14123 | goto do_reverse_branch; | |
14124 | case M_BLEU: | |
14125 | s = "sltu"; | |
14126 | s2 = "bteqz"; | |
14127 | goto do_reverse_branch; | |
14128 | case M_BGE: | |
14129 | s = "slt"; | |
14130 | s2 = "bteqz"; | |
14131 | goto do_branch; | |
14132 | case M_BGEU: | |
14133 | s = "sltu"; | |
14134 | s2 = "bteqz"; | |
14135 | goto do_branch; | |
14136 | case M_BGT: | |
14137 | s = "slt"; | |
14138 | s2 = "btnez"; | |
14139 | goto do_reverse_branch; | |
14140 | case M_BGTU: | |
14141 | s = "sltu"; | |
14142 | s2 = "btnez"; | |
14143 | ||
14144 | do_reverse_branch: | |
c0ebe874 RS |
14145 | tmp = op[1]; |
14146 | op[1] = op[0]; | |
14147 | op[0] = tmp; | |
252b5132 RH |
14148 | |
14149 | do_branch: | |
c0ebe874 | 14150 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 14151 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
14152 | break; |
14153 | ||
14154 | case M_BEQ_I: | |
14155 | s = "cmpi"; | |
14156 | s2 = "bteqz"; | |
14157 | s3 = "x,U"; | |
14158 | goto do_branch_i; | |
14159 | case M_BNE_I: | |
14160 | s = "cmpi"; | |
14161 | s2 = "btnez"; | |
14162 | s3 = "x,U"; | |
14163 | goto do_branch_i; | |
14164 | case M_BLT_I: | |
14165 | s = "slti"; | |
14166 | s2 = "btnez"; | |
14167 | s3 = "x,8"; | |
14168 | goto do_branch_i; | |
14169 | case M_BLTU_I: | |
14170 | s = "sltiu"; | |
14171 | s2 = "btnez"; | |
14172 | s3 = "x,8"; | |
14173 | goto do_branch_i; | |
14174 | case M_BLE_I: | |
14175 | s = "slti"; | |
14176 | s2 = "btnez"; | |
14177 | s3 = "x,8"; | |
14178 | goto do_addone_branch_i; | |
14179 | case M_BLEU_I: | |
14180 | s = "sltiu"; | |
14181 | s2 = "btnez"; | |
14182 | s3 = "x,8"; | |
14183 | goto do_addone_branch_i; | |
14184 | case M_BGE_I: | |
14185 | s = "slti"; | |
14186 | s2 = "bteqz"; | |
14187 | s3 = "x,8"; | |
14188 | goto do_branch_i; | |
14189 | case M_BGEU_I: | |
14190 | s = "sltiu"; | |
14191 | s2 = "bteqz"; | |
14192 | s3 = "x,8"; | |
14193 | goto do_branch_i; | |
14194 | case M_BGT_I: | |
14195 | s = "slti"; | |
14196 | s2 = "bteqz"; | |
14197 | s3 = "x,8"; | |
14198 | goto do_addone_branch_i; | |
14199 | case M_BGTU_I: | |
14200 | s = "sltiu"; | |
14201 | s2 = "bteqz"; | |
14202 | s3 = "x,8"; | |
14203 | ||
14204 | do_addone_branch_i: | |
252b5132 RH |
14205 | ++imm_expr.X_add_number; |
14206 | ||
14207 | do_branch_i: | |
c0ebe874 | 14208 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 14209 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
14210 | break; |
14211 | ||
14212 | case M_ABS: | |
14213 | expr1.X_add_number = 0; | |
c0ebe874 RS |
14214 | macro_build (&expr1, "slti", "x,8", op[1]); |
14215 | if (op[0] != op[1]) | |
14216 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 14217 | expr1.X_add_number = 2; |
67c0d1eb | 14218 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 14219 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 14220 | break; |
252b5132 RH |
14221 | } |
14222 | } | |
14223 | ||
14daeee3 RS |
14224 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
14225 | opcode bits in *OPCODE_EXTRA. */ | |
14226 | ||
14227 | static struct mips_opcode * | |
14228 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 14229 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
14230 | { |
14231 | char *name, *dot, *p; | |
14232 | unsigned int mask, suffix; | |
da8bca91 | 14233 | ssize_t opend; |
14daeee3 RS |
14234 | struct mips_opcode *insn; |
14235 | ||
14236 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 14237 | name = xstrndup (start, length); |
14daeee3 RS |
14238 | |
14239 | /* Look up the instruction as-is. */ | |
14240 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 14241 | if (insn) |
e1fa0163 | 14242 | goto end; |
14daeee3 RS |
14243 | |
14244 | dot = strchr (name, '.'); | |
14245 | if (dot && dot[1]) | |
14246 | { | |
14247 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
14248 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
14249 | if (*p == 0 && mask != 0) | |
14250 | { | |
14251 | *dot = 0; | |
14252 | insn = (struct mips_opcode *) hash_find (hash, name); | |
14253 | *dot = '.'; | |
14254 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
14255 | { | |
14256 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 14257 | goto end; |
14daeee3 RS |
14258 | } |
14259 | } | |
14260 | } | |
14261 | ||
14262 | if (mips_opts.micromips) | |
14263 | { | |
14264 | /* See if there's an instruction size override suffix, | |
14265 | either `16' or `32', at the end of the mnemonic proper, | |
14266 | that defines the operation, i.e. before the first `.' | |
14267 | character if any. Strip it and retry. */ | |
14268 | opend = dot != NULL ? dot - name : length; | |
14269 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
14270 | suffix = 2; | |
3076e594 | 14271 | else if (opend >= 2 && name[opend - 2] == '3' && name[opend - 1] == '2') |
14daeee3 RS |
14272 | suffix = 4; |
14273 | else | |
14274 | suffix = 0; | |
14275 | if (suffix) | |
14276 | { | |
39334a61 | 14277 | memmove (name + opend - 2, name + opend, length - opend + 1); |
14daeee3 | 14278 | insn = (struct mips_opcode *) hash_find (hash, name); |
ee5734f0 | 14279 | if (insn) |
14daeee3 RS |
14280 | { |
14281 | forced_insn_length = suffix; | |
e1fa0163 | 14282 | goto end; |
14daeee3 RS |
14283 | } |
14284 | } | |
14285 | } | |
14286 | ||
e1fa0163 NC |
14287 | insn = NULL; |
14288 | end: | |
14289 | free (name); | |
14290 | return insn; | |
14daeee3 RS |
14291 | } |
14292 | ||
77bd4346 | 14293 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
14294 | is a macro, set imm_expr and offset_expr to the values associated |
14295 | with "I" and "A" operands respectively. Otherwise store the value | |
14296 | of the relocatable field (if any) in offset_expr. In both cases | |
14297 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
14298 | |
14299 | static void | |
60f20e8b | 14300 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14301 | { |
60f20e8b | 14302 | const struct mips_opcode *first, *past; |
df58fc94 | 14303 | struct hash_control *hash; |
a92713e6 | 14304 | char format; |
14daeee3 | 14305 | size_t end; |
a92713e6 | 14306 | struct mips_operand_token *tokens; |
14daeee3 | 14307 | unsigned int opcode_extra; |
252b5132 | 14308 | |
df58fc94 RS |
14309 | if (mips_opts.micromips) |
14310 | { | |
14311 | hash = micromips_op_hash; | |
14312 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
14313 | } | |
14314 | else | |
14315 | { | |
14316 | hash = op_hash; | |
14317 | past = &mips_opcodes[NUMOPCODES]; | |
14318 | } | |
14319 | forced_insn_length = 0; | |
14daeee3 | 14320 | opcode_extra = 0; |
252b5132 | 14321 | |
df58fc94 | 14322 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
14323 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
14324 | continue; | |
bdaaa2e1 | 14325 | |
60f20e8b RS |
14326 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
14327 | if (first == NULL) | |
252b5132 | 14328 | { |
1661c76c | 14329 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 14330 | return; |
252b5132 RH |
14331 | } |
14332 | ||
60f20e8b | 14333 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 14334 | format = 'f'; |
60f20e8b | 14335 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
14336 | format = 'd'; |
14337 | else | |
14338 | format = 0; | |
14339 | tokens = mips_parse_arguments (str + end, format); | |
14340 | if (!tokens) | |
14341 | return; | |
14342 | ||
60f20e8b RS |
14343 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
14344 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 14345 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 14346 | |
e3de51ce | 14347 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14348 | } |
14349 | ||
77bd4346 RS |
14350 | /* As for mips_ip, but used when assembling MIPS16 code. |
14351 | Also set forced_insn_length to the resulting instruction size in | |
14352 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
14353 | |
14354 | static void | |
60f20e8b | 14355 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14356 | { |
1a00e612 | 14357 | char *end, *s, c; |
60f20e8b | 14358 | struct mips_opcode *first; |
a92713e6 | 14359 | struct mips_operand_token *tokens; |
3fb49709 | 14360 | unsigned int l; |
252b5132 | 14361 | |
25499ac7 | 14362 | for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) |
252b5132 | 14363 | ; |
1a00e612 RS |
14364 | end = s; |
14365 | c = *end; | |
3fb49709 MR |
14366 | |
14367 | l = 0; | |
1a00e612 | 14368 | switch (c) |
252b5132 RH |
14369 | { |
14370 | case '\0': | |
14371 | break; | |
14372 | ||
14373 | case ' ': | |
1a00e612 | 14374 | s++; |
252b5132 RH |
14375 | break; |
14376 | ||
14377 | case '.': | |
3fb49709 MR |
14378 | s++; |
14379 | if (*s == 't') | |
252b5132 | 14380 | { |
3fb49709 MR |
14381 | l = 2; |
14382 | s++; | |
252b5132 | 14383 | } |
3fb49709 | 14384 | else if (*s == 'e') |
252b5132 | 14385 | { |
3fb49709 MR |
14386 | l = 4; |
14387 | s++; | |
252b5132 | 14388 | } |
3fb49709 MR |
14389 | if (*s == '\0') |
14390 | break; | |
14391 | else if (*s++ == ' ') | |
14392 | break; | |
1661c76c | 14393 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14394 | return; |
14395 | } | |
3fb49709 | 14396 | forced_insn_length = l; |
252b5132 | 14397 | |
1a00e612 | 14398 | *end = 0; |
60f20e8b | 14399 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
14400 | *end = c; |
14401 | ||
60f20e8b | 14402 | if (!first) |
252b5132 | 14403 | { |
1661c76c | 14404 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14405 | return; |
14406 | } | |
14407 | ||
a92713e6 RS |
14408 | tokens = mips_parse_arguments (s, 0); |
14409 | if (!tokens) | |
14410 | return; | |
14411 | ||
60f20e8b | 14412 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 14413 | set_insn_error (0, _("invalid operands")); |
252b5132 | 14414 | |
e3de51ce | 14415 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14416 | } |
14417 | ||
b886a2ab RS |
14418 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14419 | NBITS is the number of significant bits in VAL. */ | |
14420 | ||
14421 | static unsigned long | |
14422 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14423 | { | |
14424 | int extval; | |
25499ac7 MR |
14425 | |
14426 | extval = 0; | |
14427 | val &= (1U << nbits) - 1; | |
14428 | if (nbits == 16 || nbits == 9) | |
b886a2ab RS |
14429 | { |
14430 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14431 | val &= 0x1f; | |
14432 | } | |
14433 | else if (nbits == 15) | |
14434 | { | |
14435 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14436 | val &= 0xf; | |
14437 | } | |
25499ac7 | 14438 | else if (nbits == 6) |
b886a2ab RS |
14439 | { |
14440 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14441 | val = 0; | |
14442 | } | |
14443 | return (extval << 16) | val; | |
14444 | } | |
14445 | ||
3ccad066 RS |
14446 | /* Like decode_mips16_operand, but require the operand to be defined and |
14447 | require it to be an integer. */ | |
14448 | ||
14449 | static const struct mips_int_operand * | |
14450 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
14451 | { | |
14452 | const struct mips_operand *operand; | |
14453 | ||
14454 | operand = decode_mips16_operand (type, extended_p); | |
14455 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
14456 | abort (); | |
14457 | return (const struct mips_int_operand *) operand; | |
14458 | } | |
14459 | ||
14460 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14461 | ||
14462 | static bfd_boolean | |
14463 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14464 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14465 | { | |
14466 | int min_val, max_val; | |
14467 | ||
14468 | min_val = mips_int_operand_min (operand); | |
14469 | max_val = mips_int_operand_max (operand); | |
14470 | if (reloc != BFD_RELOC_UNUSED) | |
14471 | { | |
14472 | if (min_val < 0) | |
14473 | sval = SEXT_16BIT (sval); | |
14474 | else | |
14475 | sval &= 0xffff; | |
14476 | } | |
14477 | ||
14478 | return (sval >= min_val | |
14479 | && sval <= max_val | |
14480 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14481 | } | |
14482 | ||
5c04167a RS |
14483 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14484 | extending it if necessary. The instruction in *INSN may | |
14485 | already be extended. | |
14486 | ||
43c0598f RS |
14487 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14488 | if none. In the former case, VAL is a 16-bit number with no | |
14489 | defined signedness. | |
14490 | ||
14491 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14492 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14493 | |
14494 | static void | |
3b4dbbbf | 14495 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14496 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14497 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14498 | { |
3ccad066 RS |
14499 | const struct mips_int_operand *operand; |
14500 | unsigned int uval, length; | |
252b5132 | 14501 | |
3ccad066 RS |
14502 | operand = mips16_immed_operand (type, FALSE); |
14503 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14504 | { |
14505 | /* We need an extended instruction. */ | |
14506 | if (user_insn_length == 2) | |
14507 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14508 | else | |
14509 | *insn |= MIPS16_EXTEND; | |
14510 | } | |
14511 | else if (user_insn_length == 4) | |
14512 | { | |
14513 | /* The operand doesn't force an unextended instruction to be extended. | |
14514 | Warn if the user wanted an extended instruction anyway. */ | |
14515 | *insn |= MIPS16_EXTEND; | |
14516 | as_warn_where (file, line, | |
14517 | _("extended operand requested but not required")); | |
14518 | } | |
252b5132 | 14519 | |
3ccad066 RS |
14520 | length = mips16_opcode_length (*insn); |
14521 | if (length == 4) | |
252b5132 | 14522 | { |
3ccad066 RS |
14523 | operand = mips16_immed_operand (type, TRUE); |
14524 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14525 | as_bad_where (file, line, | |
14526 | _("operand value out of range for instruction")); | |
252b5132 | 14527 | } |
3ccad066 | 14528 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14529 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14530 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14531 | else |
3ccad066 | 14532 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14533 | } |
14534 | \f | |
d6f16593 | 14535 | struct percent_op_match |
ad8d3bb3 | 14536 | { |
5e0116d5 RS |
14537 | const char *str; |
14538 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14539 | }; |
14540 | ||
14541 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14542 | { |
5e0116d5 | 14543 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14544 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14545 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14546 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14547 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14548 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14549 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14550 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14551 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14552 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14553 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14554 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14555 | {"%half", BFD_RELOC_16}, |
14556 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14557 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14558 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14559 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14560 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14561 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14562 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14563 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14564 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14565 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14566 | {"%hi", BFD_RELOC_HI16_S}, |
14567 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14568 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14569 | }; |
14570 | ||
d6f16593 MR |
14571 | static const struct percent_op_match mips16_percent_op[] = |
14572 | { | |
14573 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14574 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14575 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14576 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14577 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14578 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14579 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14580 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14581 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14582 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14583 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14584 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14585 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14586 | }; |
14587 | ||
252b5132 | 14588 | |
5e0116d5 RS |
14589 | /* Return true if *STR points to a relocation operator. When returning true, |
14590 | move *STR over the operator and store its relocation code in *RELOC. | |
14591 | Leave both *STR and *RELOC alone when returning false. */ | |
14592 | ||
14593 | static bfd_boolean | |
17a2f251 | 14594 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14595 | { |
d6f16593 MR |
14596 | const struct percent_op_match *percent_op; |
14597 | size_t limit, i; | |
14598 | ||
14599 | if (mips_opts.mips16) | |
14600 | { | |
14601 | percent_op = mips16_percent_op; | |
14602 | limit = ARRAY_SIZE (mips16_percent_op); | |
14603 | } | |
14604 | else | |
14605 | { | |
14606 | percent_op = mips_percent_op; | |
14607 | limit = ARRAY_SIZE (mips_percent_op); | |
14608 | } | |
76b3015f | 14609 | |
d6f16593 | 14610 | for (i = 0; i < limit; i++) |
5e0116d5 | 14611 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14612 | { |
3f98094e DJ |
14613 | int len = strlen (percent_op[i].str); |
14614 | ||
14615 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14616 | continue; | |
14617 | ||
5e0116d5 RS |
14618 | *str += strlen (percent_op[i].str); |
14619 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14620 | |
5e0116d5 RS |
14621 | /* Check whether the output BFD supports this relocation. |
14622 | If not, issue an error and fall back on something safe. */ | |
14623 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14624 | { |
20203fb9 | 14625 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14626 | percent_op[i].str); |
01a3f561 | 14627 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14628 | } |
5e0116d5 | 14629 | return TRUE; |
394f9b3a | 14630 | } |
5e0116d5 | 14631 | return FALSE; |
394f9b3a | 14632 | } |
ad8d3bb3 | 14633 | |
ad8d3bb3 | 14634 | |
5e0116d5 RS |
14635 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14636 | expression in *EP and the relocations in the array starting | |
14637 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14638 | |
01a3f561 | 14639 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14640 | |
5e0116d5 | 14641 | static size_t |
17a2f251 TS |
14642 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14643 | char *str) | |
ad8d3bb3 | 14644 | { |
5e0116d5 RS |
14645 | bfd_reloc_code_real_type reversed_reloc[3]; |
14646 | size_t reloc_index, i; | |
09b8f35a RS |
14647 | int crux_depth, str_depth; |
14648 | char *crux; | |
5e0116d5 RS |
14649 | |
14650 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14651 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14652 | of the main expression and with CRUX_DEPTH containing the number | |
14653 | of open brackets at that point. */ | |
14654 | reloc_index = -1; | |
14655 | str_depth = 0; | |
14656 | do | |
fb1b3232 | 14657 | { |
09b8f35a RS |
14658 | reloc_index++; |
14659 | crux = str; | |
14660 | crux_depth = str_depth; | |
14661 | ||
14662 | /* Skip over whitespace and brackets, keeping count of the number | |
14663 | of brackets. */ | |
14664 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14665 | if (*str++ == '(') | |
14666 | str_depth++; | |
5e0116d5 | 14667 | } |
09b8f35a RS |
14668 | while (*str == '%' |
14669 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14670 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14671 | |
09b8f35a | 14672 | my_getExpression (ep, crux); |
5e0116d5 | 14673 | str = expr_end; |
394f9b3a | 14674 | |
5e0116d5 | 14675 | /* Match every open bracket. */ |
09b8f35a | 14676 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14677 | if (*str++ == ')') |
09b8f35a | 14678 | crux_depth--; |
394f9b3a | 14679 | |
09b8f35a | 14680 | if (crux_depth > 0) |
20203fb9 | 14681 | as_bad (_("unclosed '('")); |
394f9b3a | 14682 | |
5e0116d5 | 14683 | expr_end = str; |
252b5132 | 14684 | |
01a3f561 | 14685 | if (reloc_index != 0) |
64bdfcaf RS |
14686 | { |
14687 | prev_reloc_op_frag = frag_now; | |
14688 | for (i = 0; i < reloc_index; i++) | |
14689 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14690 | } | |
fb1b3232 | 14691 | |
5e0116d5 | 14692 | return reloc_index; |
252b5132 RH |
14693 | } |
14694 | ||
14695 | static void | |
17a2f251 | 14696 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14697 | { |
14698 | char *save_in; | |
14699 | ||
14700 | save_in = input_line_pointer; | |
14701 | input_line_pointer = str; | |
14702 | expression (ep); | |
14703 | expr_end = input_line_pointer; | |
14704 | input_line_pointer = save_in; | |
252b5132 RH |
14705 | } |
14706 | ||
6d4af3c2 | 14707 | const char * |
17a2f251 | 14708 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14709 | { |
499ac353 | 14710 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14711 | } |
14712 | ||
14713 | void | |
17a2f251 | 14714 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14715 | { |
14716 | if (target_big_endian) | |
14717 | number_to_chars_bigendian (buf, val, n); | |
14718 | else | |
14719 | number_to_chars_littleendian (buf, val, n); | |
14720 | } | |
14721 | \f | |
e013f690 TS |
14722 | static int support_64bit_objects(void) |
14723 | { | |
14724 | const char **list, **l; | |
aa3d8fdf | 14725 | int yes; |
e013f690 TS |
14726 | |
14727 | list = bfd_target_list (); | |
14728 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14729 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14730 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14731 | break; |
aa3d8fdf | 14732 | yes = (*l != NULL); |
e013f690 | 14733 | free (list); |
aa3d8fdf | 14734 | return yes; |
e013f690 TS |
14735 | } |
14736 | ||
316f5878 RS |
14737 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14738 | NEW_VALUE. Warn if another value was already specified. Note: | |
14739 | we have to defer parsing the -march and -mtune arguments in order | |
14740 | to handle 'from-abi' correctly, since the ABI might be specified | |
14741 | in a later argument. */ | |
14742 | ||
14743 | static void | |
17a2f251 | 14744 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14745 | { |
14746 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14747 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14748 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14749 | new_value); | |
14750 | ||
14751 | *string_ptr = new_value; | |
14752 | } | |
14753 | ||
252b5132 | 14754 | int |
17b9d67d | 14755 | md_parse_option (int c, const char *arg) |
252b5132 | 14756 | { |
c6278170 RS |
14757 | unsigned int i; |
14758 | ||
14759 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14760 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14761 | { | |
919731af | 14762 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14763 | c == mips_ases[i].option_on); |
14764 | return 1; | |
14765 | } | |
14766 | ||
252b5132 RH |
14767 | switch (c) |
14768 | { | |
119d663a NC |
14769 | case OPTION_CONSTRUCT_FLOATS: |
14770 | mips_disable_float_construction = 0; | |
14771 | break; | |
bdaaa2e1 | 14772 | |
119d663a NC |
14773 | case OPTION_NO_CONSTRUCT_FLOATS: |
14774 | mips_disable_float_construction = 1; | |
14775 | break; | |
bdaaa2e1 | 14776 | |
252b5132 RH |
14777 | case OPTION_TRAP: |
14778 | mips_trap = 1; | |
14779 | break; | |
14780 | ||
14781 | case OPTION_BREAK: | |
14782 | mips_trap = 0; | |
14783 | break; | |
14784 | ||
14785 | case OPTION_EB: | |
14786 | target_big_endian = 1; | |
14787 | break; | |
14788 | ||
14789 | case OPTION_EL: | |
14790 | target_big_endian = 0; | |
14791 | break; | |
14792 | ||
14793 | case 'O': | |
4ffff32f TS |
14794 | if (arg == NULL) |
14795 | mips_optimize = 1; | |
14796 | else if (arg[0] == '0') | |
14797 | mips_optimize = 0; | |
14798 | else if (arg[0] == '1') | |
252b5132 RH |
14799 | mips_optimize = 1; |
14800 | else | |
14801 | mips_optimize = 2; | |
14802 | break; | |
14803 | ||
14804 | case 'g': | |
14805 | if (arg == NULL) | |
14806 | mips_debug = 2; | |
14807 | else | |
14808 | mips_debug = atoi (arg); | |
252b5132 RH |
14809 | break; |
14810 | ||
14811 | case OPTION_MIPS1: | |
0b35dfee | 14812 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14813 | break; |
14814 | ||
14815 | case OPTION_MIPS2: | |
0b35dfee | 14816 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14817 | break; |
14818 | ||
14819 | case OPTION_MIPS3: | |
0b35dfee | 14820 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14821 | break; |
14822 | ||
14823 | case OPTION_MIPS4: | |
0b35dfee | 14824 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14825 | break; |
14826 | ||
84ea6cf2 | 14827 | case OPTION_MIPS5: |
0b35dfee | 14828 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14829 | break; |
14830 | ||
e7af610e | 14831 | case OPTION_MIPS32: |
0b35dfee | 14832 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14833 | break; |
14834 | ||
af7ee8bf | 14835 | case OPTION_MIPS32R2: |
0b35dfee | 14836 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14837 | break; |
14838 | ||
ae52f483 | 14839 | case OPTION_MIPS32R3: |
0ae19f05 | 14840 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14841 | break; |
14842 | ||
14843 | case OPTION_MIPS32R5: | |
0ae19f05 | 14844 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14845 | break; |
14846 | ||
7361da2c AB |
14847 | case OPTION_MIPS32R6: |
14848 | file_mips_opts.isa = ISA_MIPS32R6; | |
14849 | break; | |
14850 | ||
5f74bc13 | 14851 | case OPTION_MIPS64R2: |
0b35dfee | 14852 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14853 | break; |
14854 | ||
ae52f483 | 14855 | case OPTION_MIPS64R3: |
0ae19f05 | 14856 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14857 | break; |
14858 | ||
14859 | case OPTION_MIPS64R5: | |
0ae19f05 | 14860 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14861 | break; |
14862 | ||
7361da2c AB |
14863 | case OPTION_MIPS64R6: |
14864 | file_mips_opts.isa = ISA_MIPS64R6; | |
14865 | break; | |
14866 | ||
84ea6cf2 | 14867 | case OPTION_MIPS64: |
0b35dfee | 14868 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14869 | break; |
14870 | ||
ec68c924 | 14871 | case OPTION_MTUNE: |
316f5878 RS |
14872 | mips_set_option_string (&mips_tune_string, arg); |
14873 | break; | |
ec68c924 | 14874 | |
316f5878 RS |
14875 | case OPTION_MARCH: |
14876 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14877 | break; |
14878 | ||
14879 | case OPTION_M4650: | |
316f5878 RS |
14880 | mips_set_option_string (&mips_arch_string, "4650"); |
14881 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14882 | break; |
14883 | ||
14884 | case OPTION_NO_M4650: | |
14885 | break; | |
14886 | ||
14887 | case OPTION_M4010: | |
316f5878 RS |
14888 | mips_set_option_string (&mips_arch_string, "4010"); |
14889 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14890 | break; |
14891 | ||
14892 | case OPTION_NO_M4010: | |
14893 | break; | |
14894 | ||
14895 | case OPTION_M4100: | |
316f5878 RS |
14896 | mips_set_option_string (&mips_arch_string, "4100"); |
14897 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14898 | break; |
14899 | ||
14900 | case OPTION_NO_M4100: | |
14901 | break; | |
14902 | ||
252b5132 | 14903 | case OPTION_M3900: |
316f5878 RS |
14904 | mips_set_option_string (&mips_arch_string, "3900"); |
14905 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14906 | break; |
bdaaa2e1 | 14907 | |
252b5132 RH |
14908 | case OPTION_NO_M3900: |
14909 | break; | |
14910 | ||
df58fc94 | 14911 | case OPTION_MICROMIPS: |
919731af | 14912 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14913 | { |
14914 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14915 | return 0; | |
14916 | } | |
919731af | 14917 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14918 | mips_no_prev_insn (); |
14919 | break; | |
14920 | ||
14921 | case OPTION_NO_MICROMIPS: | |
919731af | 14922 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14923 | mips_no_prev_insn (); |
14924 | break; | |
14925 | ||
252b5132 | 14926 | case OPTION_MIPS16: |
919731af | 14927 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14928 | { |
14929 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14930 | return 0; | |
14931 | } | |
919731af | 14932 | file_mips_opts.mips16 = 1; |
7d10b47d | 14933 | mips_no_prev_insn (); |
252b5132 RH |
14934 | break; |
14935 | ||
14936 | case OPTION_NO_MIPS16: | |
919731af | 14937 | file_mips_opts.mips16 = 0; |
7d10b47d | 14938 | mips_no_prev_insn (); |
252b5132 RH |
14939 | break; |
14940 | ||
6a32d874 CM |
14941 | case OPTION_FIX_24K: |
14942 | mips_fix_24k = 1; | |
14943 | break; | |
14944 | ||
14945 | case OPTION_NO_FIX_24K: | |
14946 | mips_fix_24k = 0; | |
14947 | break; | |
14948 | ||
a8d14a88 CM |
14949 | case OPTION_FIX_RM7000: |
14950 | mips_fix_rm7000 = 1; | |
14951 | break; | |
14952 | ||
14953 | case OPTION_NO_FIX_RM7000: | |
14954 | mips_fix_rm7000 = 0; | |
14955 | break; | |
14956 | ||
6f2117ba PH |
14957 | case OPTION_FIX_LOONGSON3_LLSC: |
14958 | mips_fix_loongson3_llsc = TRUE; | |
14959 | break; | |
14960 | ||
14961 | case OPTION_NO_FIX_LOONGSON3_LLSC: | |
14962 | mips_fix_loongson3_llsc = FALSE; | |
14963 | break; | |
14964 | ||
c67a084a NC |
14965 | case OPTION_FIX_LOONGSON2F_JUMP: |
14966 | mips_fix_loongson2f_jump = TRUE; | |
14967 | break; | |
14968 | ||
14969 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14970 | mips_fix_loongson2f_jump = FALSE; | |
14971 | break; | |
14972 | ||
14973 | case OPTION_FIX_LOONGSON2F_NOP: | |
14974 | mips_fix_loongson2f_nop = TRUE; | |
14975 | break; | |
14976 | ||
14977 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14978 | mips_fix_loongson2f_nop = FALSE; | |
14979 | break; | |
14980 | ||
d766e8ec RS |
14981 | case OPTION_FIX_VR4120: |
14982 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14983 | break; |
14984 | ||
d766e8ec RS |
14985 | case OPTION_NO_FIX_VR4120: |
14986 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14987 | break; |
14988 | ||
7d8e00cf RS |
14989 | case OPTION_FIX_VR4130: |
14990 | mips_fix_vr4130 = 1; | |
14991 | break; | |
14992 | ||
14993 | case OPTION_NO_FIX_VR4130: | |
14994 | mips_fix_vr4130 = 0; | |
14995 | break; | |
14996 | ||
d954098f DD |
14997 | case OPTION_FIX_CN63XXP1: |
14998 | mips_fix_cn63xxp1 = TRUE; | |
14999 | break; | |
15000 | ||
15001 | case OPTION_NO_FIX_CN63XXP1: | |
15002 | mips_fix_cn63xxp1 = FALSE; | |
15003 | break; | |
15004 | ||
27c634e0 FN |
15005 | case OPTION_FIX_R5900: |
15006 | mips_fix_r5900 = TRUE; | |
15007 | mips_fix_r5900_explicit = TRUE; | |
15008 | break; | |
15009 | ||
15010 | case OPTION_NO_FIX_R5900: | |
15011 | mips_fix_r5900 = FALSE; | |
15012 | mips_fix_r5900_explicit = TRUE; | |
15013 | break; | |
15014 | ||
4a6a3df4 AO |
15015 | case OPTION_RELAX_BRANCH: |
15016 | mips_relax_branch = 1; | |
15017 | break; | |
15018 | ||
15019 | case OPTION_NO_RELAX_BRANCH: | |
15020 | mips_relax_branch = 0; | |
15021 | break; | |
15022 | ||
8b10b0b3 MR |
15023 | case OPTION_IGNORE_BRANCH_ISA: |
15024 | mips_ignore_branch_isa = TRUE; | |
15025 | break; | |
15026 | ||
15027 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
15028 | mips_ignore_branch_isa = FALSE; | |
15029 | break; | |
15030 | ||
833794fc | 15031 | case OPTION_INSN32: |
919731af | 15032 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
15033 | break; |
15034 | ||
15035 | case OPTION_NO_INSN32: | |
919731af | 15036 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
15037 | break; |
15038 | ||
aa6975fb ILT |
15039 | case OPTION_MSHARED: |
15040 | mips_in_shared = TRUE; | |
15041 | break; | |
15042 | ||
15043 | case OPTION_MNO_SHARED: | |
15044 | mips_in_shared = FALSE; | |
15045 | break; | |
15046 | ||
aed1a261 | 15047 | case OPTION_MSYM32: |
919731af | 15048 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
15049 | break; |
15050 | ||
15051 | case OPTION_MNO_SYM32: | |
919731af | 15052 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
15053 | break; |
15054 | ||
252b5132 RH |
15055 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15056 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15057 | intended to be compatible with Irix 5. */ | |
15058 | case OPTION_CALL_SHARED: | |
252b5132 | 15059 | mips_pic = SVR4_PIC; |
143d77c5 | 15060 | mips_abicalls = TRUE; |
252b5132 RH |
15061 | break; |
15062 | ||
861fb55a | 15063 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
15064 | mips_pic = NO_PIC; |
15065 | mips_abicalls = TRUE; | |
15066 | break; | |
15067 | ||
252b5132 | 15068 | case OPTION_NON_SHARED: |
252b5132 | 15069 | mips_pic = NO_PIC; |
143d77c5 | 15070 | mips_abicalls = FALSE; |
252b5132 RH |
15071 | break; |
15072 | ||
44075ae2 TS |
15073 | /* The -xgot option tells the assembler to use 32 bit offsets |
15074 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15075 | compatibility. */ |
15076 | case OPTION_XGOT: | |
15077 | mips_big_got = 1; | |
15078 | break; | |
15079 | ||
15080 | case 'G': | |
6caf9ef4 TS |
15081 | g_switch_value = atoi (arg); |
15082 | g_switch_seen = 1; | |
252b5132 RH |
15083 | break; |
15084 | ||
34ba82a8 TS |
15085 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15086 | and -mabi=64. */ | |
252b5132 | 15087 | case OPTION_32: |
f3ded42a | 15088 | mips_abi = O32_ABI; |
252b5132 RH |
15089 | break; |
15090 | ||
e013f690 | 15091 | case OPTION_N32: |
316f5878 | 15092 | mips_abi = N32_ABI; |
e013f690 | 15093 | break; |
252b5132 | 15094 | |
e013f690 | 15095 | case OPTION_64: |
316f5878 | 15096 | mips_abi = N64_ABI; |
f43abd2b | 15097 | if (!support_64bit_objects()) |
1661c76c | 15098 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
15099 | break; |
15100 | ||
c97ef257 | 15101 | case OPTION_GP32: |
bad1aba3 | 15102 | file_mips_opts.gp = 32; |
c97ef257 AH |
15103 | break; |
15104 | ||
15105 | case OPTION_GP64: | |
bad1aba3 | 15106 | file_mips_opts.gp = 64; |
c97ef257 | 15107 | break; |
252b5132 | 15108 | |
ca4e0257 | 15109 | case OPTION_FP32: |
0b35dfee | 15110 | file_mips_opts.fp = 32; |
316f5878 RS |
15111 | break; |
15112 | ||
351cdf24 MF |
15113 | case OPTION_FPXX: |
15114 | file_mips_opts.fp = 0; | |
15115 | break; | |
15116 | ||
316f5878 | 15117 | case OPTION_FP64: |
0b35dfee | 15118 | file_mips_opts.fp = 64; |
ca4e0257 RS |
15119 | break; |
15120 | ||
351cdf24 MF |
15121 | case OPTION_ODD_SPREG: |
15122 | file_mips_opts.oddspreg = 1; | |
15123 | break; | |
15124 | ||
15125 | case OPTION_NO_ODD_SPREG: | |
15126 | file_mips_opts.oddspreg = 0; | |
15127 | break; | |
15128 | ||
037b32b9 | 15129 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 15130 | file_mips_opts.single_float = 1; |
037b32b9 AN |
15131 | break; |
15132 | ||
15133 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 15134 | file_mips_opts.single_float = 0; |
037b32b9 AN |
15135 | break; |
15136 | ||
15137 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 15138 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
15139 | break; |
15140 | ||
15141 | case OPTION_HARD_FLOAT: | |
0b35dfee | 15142 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
15143 | break; |
15144 | ||
252b5132 | 15145 | case OPTION_MABI: |
e013f690 | 15146 | if (strcmp (arg, "32") == 0) |
316f5878 | 15147 | mips_abi = O32_ABI; |
e013f690 | 15148 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15149 | mips_abi = O64_ABI; |
e013f690 | 15150 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15151 | mips_abi = N32_ABI; |
e013f690 TS |
15152 | else if (strcmp (arg, "64") == 0) |
15153 | { | |
316f5878 | 15154 | mips_abi = N64_ABI; |
e013f690 | 15155 | if (! support_64bit_objects()) |
1661c76c | 15156 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
15157 | "format")); |
15158 | } | |
15159 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15160 | mips_abi = EABI_ABI; |
e013f690 | 15161 | else |
da0e507f TS |
15162 | { |
15163 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15164 | return 0; | |
15165 | } | |
252b5132 RH |
15166 | break; |
15167 | ||
6b76fefe | 15168 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15169 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15170 | break; |
15171 | ||
9ee72ff1 | 15172 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15173 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15174 | break; |
15175 | ||
ecb4347a | 15176 | case OPTION_MDEBUG: |
b34976b6 | 15177 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15178 | break; |
15179 | ||
15180 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15181 | mips_flag_mdebug = FALSE; |
ecb4347a | 15182 | break; |
dcd410fe RO |
15183 | |
15184 | case OPTION_PDR: | |
15185 | mips_flag_pdr = TRUE; | |
15186 | break; | |
15187 | ||
15188 | case OPTION_NO_PDR: | |
15189 | mips_flag_pdr = FALSE; | |
15190 | break; | |
0a44bf69 RS |
15191 | |
15192 | case OPTION_MVXWORKS_PIC: | |
15193 | mips_pic = VXWORKS_PIC; | |
15194 | break; | |
ecb4347a | 15195 | |
ba92f887 MR |
15196 | case OPTION_NAN: |
15197 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 15198 | mips_nan2008 = 1; |
ba92f887 | 15199 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 15200 | mips_nan2008 = 0; |
ba92f887 MR |
15201 | else |
15202 | { | |
1661c76c | 15203 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
15204 | return 0; |
15205 | } | |
15206 | break; | |
15207 | ||
252b5132 RH |
15208 | default: |
15209 | return 0; | |
15210 | } | |
15211 | ||
c67a084a NC |
15212 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15213 | ||
252b5132 RH |
15214 | return 1; |
15215 | } | |
316f5878 | 15216 | \f |
919731af | 15217 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 15218 | |
316f5878 | 15219 | static void |
17a2f251 | 15220 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15221 | { |
15222 | if (info != 0) | |
fef14a42 | 15223 | mips_tune = info->cpu; |
316f5878 | 15224 | } |
80cc45a5 | 15225 | |
34ba82a8 | 15226 | |
252b5132 | 15227 | void |
17a2f251 | 15228 | mips_after_parse_args (void) |
e9670677 | 15229 | { |
fef14a42 TS |
15230 | const struct mips_cpu_info *arch_info = 0; |
15231 | const struct mips_cpu_info *tune_info = 0; | |
15232 | ||
6f2117ba | 15233 | /* GP relative stuff not working for PE. */ |
6caf9ef4 | 15234 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15235 | { |
6caf9ef4 | 15236 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 15237 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
15238 | g_switch_value = 0; |
15239 | } | |
15240 | ||
cac012d6 AO |
15241 | if (mips_abi == NO_ABI) |
15242 | mips_abi = MIPS_DEFAULT_ABI; | |
15243 | ||
919731af | 15244 | /* The following code determines the architecture. |
22923709 RS |
15245 | Similar code was added to GCC 3.3 (see override_options() in |
15246 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15247 | as much as possible. */ | |
e9670677 | 15248 | |
316f5878 | 15249 | if (mips_arch_string != 0) |
fef14a42 | 15250 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15251 | |
0b35dfee | 15252 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 15253 | { |
0b35dfee | 15254 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 15255 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15256 | the -march selection (if any). */ |
fef14a42 | 15257 | if (arch_info != 0) |
e9670677 | 15258 | { |
316f5878 RS |
15259 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15260 | There's no harm in specifying both as long as the ISA levels | |
15261 | are the same. */ | |
0b35dfee | 15262 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
15263 | as_bad (_("-%s conflicts with the other architecture options," |
15264 | " which imply -%s"), | |
0b35dfee | 15265 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 15266 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15267 | } |
316f5878 | 15268 | else |
0b35dfee | 15269 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
15270 | } |
15271 | ||
fef14a42 | 15272 | if (arch_info == 0) |
95bfe26e MF |
15273 | { |
15274 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15275 | gas_assert (arch_info); | |
15276 | } | |
e9670677 | 15277 | |
fef14a42 | 15278 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15279 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15280 | arch_info->name); |
15281 | ||
919731af | 15282 | file_mips_opts.arch = arch_info->cpu; |
15283 | file_mips_opts.isa = arch_info->isa; | |
3315614d | 15284 | file_mips_opts.init_ase = arch_info->ase; |
919731af | 15285 | |
41cee089 FS |
15286 | /* The EVA Extension has instructions which are only valid when the R6 ISA |
15287 | is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are | |
15288 | present. */ | |
15289 | if (((file_mips_opts.ase & ASE_EVA) != 0) && ISA_IS_R6 (file_mips_opts.isa)) | |
15290 | file_mips_opts.ase |= ASE_EVA_R6; | |
15291 | ||
919731af | 15292 | /* Set up initial mips_opts state. */ |
15293 | mips_opts = file_mips_opts; | |
15294 | ||
27c634e0 FN |
15295 | /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */ |
15296 | if (!mips_fix_r5900_explicit) | |
15297 | mips_fix_r5900 = file_mips_opts.arch == CPU_R5900; | |
15298 | ||
919731af | 15299 | /* The register size inference code is now placed in |
15300 | file_mips_check_options. */ | |
fef14a42 | 15301 | |
0b35dfee | 15302 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
15303 | processor. */ | |
fef14a42 TS |
15304 | if (mips_tune_string != 0) |
15305 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15306 | |
fef14a42 TS |
15307 | if (tune_info == 0) |
15308 | mips_set_tune (arch_info); | |
15309 | else | |
15310 | mips_set_tune (tune_info); | |
e9670677 | 15311 | |
ecb4347a | 15312 | if (mips_flag_mdebug < 0) |
e8044f35 | 15313 | mips_flag_mdebug = 0; |
e9670677 MR |
15314 | } |
15315 | \f | |
15316 | void | |
17a2f251 | 15317 | mips_init_after_args (void) |
252b5132 | 15318 | { |
6f2117ba | 15319 | /* Initialize opcodes. */ |
252b5132 | 15320 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; |
beae10d5 | 15321 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15322 | } |
15323 | ||
15324 | long | |
17a2f251 | 15325 | md_pcrel_from (fixS *fixP) |
252b5132 | 15326 | { |
a7ebbfdf | 15327 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
6f2117ba | 15328 | |
a7ebbfdf TS |
15329 | switch (fixP->fx_r_type) |
15330 | { | |
df58fc94 RS |
15331 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15332 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15333 | /* Return the address of the delay slot. */ | |
15334 | return addr + 2; | |
15335 | ||
15336 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15337 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 15338 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 15339 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
15340 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15341 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
15342 | case BFD_RELOC_MIPS_JMP: |
15343 | /* Return the address of the delay slot. */ | |
15344 | return addr + 4; | |
df58fc94 | 15345 | |
51f6035b MR |
15346 | case BFD_RELOC_MIPS_18_PCREL_S3: |
15347 | /* Return the aligned address of the doubleword containing | |
15348 | the instruction. */ | |
15349 | return addr & ~7; | |
15350 | ||
a7ebbfdf TS |
15351 | default: |
15352 | return addr; | |
15353 | } | |
252b5132 RH |
15354 | } |
15355 | ||
252b5132 RH |
15356 | /* This is called before the symbol table is processed. In order to |
15357 | work with gcc when using mips-tfile, we must keep all local labels. | |
15358 | However, in other cases, we want to discard them. If we were | |
15359 | called with -g, but we didn't see any debugging information, it may | |
15360 | mean that gcc is smuggling debugging information through to | |
15361 | mips-tfile, in which case we must generate all local labels. */ | |
15362 | ||
15363 | void | |
17a2f251 | 15364 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15365 | { |
15366 | #ifndef NO_ECOFF_DEBUGGING | |
15367 | if (ECOFF_DEBUGGING | |
15368 | && mips_debug != 0 | |
15369 | && ! ecoff_debugging_seen) | |
15370 | flag_keep_locals = 1; | |
15371 | #endif | |
15372 | } | |
15373 | ||
3b91255e | 15374 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15375 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15376 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15377 | relocation operators. | |
15378 | ||
15379 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15380 | expression if: | |
15381 | ||
15382 | (a) it refers to the same symbol; and | |
15383 | (b) the offset applied in the %lo() expression is no lower than | |
15384 | the offset applied in the %got() or %hi(). | |
15385 | ||
15386 | (b) allows us to cope with code like: | |
15387 | ||
15388 | lui $4,%hi(foo) | |
15389 | lh $4,%lo(foo+2)($4) | |
15390 | ||
15391 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15392 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15393 | the high 16 bits. | |
15394 | ||
15395 | When several %lo()s match a particular %got() or %hi(), we use the | |
15396 | following rules to distinguish them: | |
15397 | ||
15398 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15399 | higher offsets. | |
15400 | ||
15401 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15402 | that already have a matching %got() or %hi(). | |
15403 | ||
15404 | (3) later %lo()s are better than earlier %lo()s. | |
15405 | ||
15406 | These rules are applied in order. | |
15407 | ||
15408 | (1) means, among other things, that %lo()s with identical offsets are | |
15409 | chosen if they exist. | |
15410 | ||
15411 | (2) means that we won't associate several high-part relocations with | |
15412 | the same low-part relocation unless there's no alternative. Having | |
15413 | several high parts for the same low part is a GNU extension; this rule | |
15414 | allows careful users to avoid it. | |
15415 | ||
15416 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15417 | with the last high-part relocation being at the front of the list. | |
15418 | It therefore makes sense to choose the last matching low-part | |
15419 | relocation, all other things being equal. It's also easier | |
15420 | to code that way. */ | |
252b5132 RH |
15421 | |
15422 | void | |
17a2f251 | 15423 | mips_frob_file (void) |
252b5132 RH |
15424 | { |
15425 | struct mips_hi_fixup *l; | |
35903be0 | 15426 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15427 | |
15428 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15429 | { | |
15430 | segment_info_type *seginfo; | |
3b91255e RS |
15431 | bfd_boolean matched_lo_p; |
15432 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15433 | |
9c2799c2 | 15434 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15435 | |
5919d012 | 15436 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15437 | there isn't supposed to be a matching LO. Ignore %gots against |
15438 | constants; we'll report an error for those later. */ | |
738e5348 | 15439 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 15440 | && !(l->fixp->fx_addsy |
9e009953 | 15441 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
15442 | continue; |
15443 | ||
15444 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15445 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15446 | continue; |
15447 | ||
252b5132 | 15448 | seginfo = seg_info (l->seg); |
252b5132 | 15449 | |
3b91255e RS |
15450 | /* Set HI_POS to the position of this relocation in the chain. |
15451 | Set LO_POS to the position of the chosen low-part relocation. | |
15452 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15453 | relocation that matches an immediately-preceding high-part | |
15454 | relocation. */ | |
15455 | hi_pos = NULL; | |
15456 | lo_pos = NULL; | |
15457 | matched_lo_p = FALSE; | |
738e5348 | 15458 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15459 | |
3b91255e RS |
15460 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15461 | { | |
15462 | if (*pos == l->fixp) | |
15463 | hi_pos = pos; | |
15464 | ||
35903be0 | 15465 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15466 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15467 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15468 | && (lo_pos == NULL | |
15469 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15470 | || (!matched_lo_p | |
15471 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15472 | lo_pos = pos; | |
15473 | ||
15474 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15475 | && fixup_has_matching_lo_p (*pos)); | |
15476 | } | |
15477 | ||
15478 | /* If we found a match, remove the high-part relocation from its | |
15479 | current position and insert it before the low-part relocation. | |
15480 | Make the offsets match so that fixup_has_matching_lo_p() | |
15481 | will return true. | |
15482 | ||
15483 | We don't warn about unmatched high-part relocations since some | |
15484 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15485 | instructions. */ | |
15486 | if (lo_pos != NULL) | |
15487 | { | |
15488 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15489 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15490 | { |
3b91255e RS |
15491 | *hi_pos = l->fixp->fx_next; |
15492 | l->fixp->fx_next = *lo_pos; | |
15493 | *lo_pos = l->fixp; | |
252b5132 | 15494 | } |
252b5132 RH |
15495 | } |
15496 | } | |
15497 | } | |
15498 | ||
252b5132 | 15499 | int |
17a2f251 | 15500 | mips_force_relocation (fixS *fixp) |
252b5132 | 15501 | { |
ae6063d4 | 15502 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15503 | return 1; |
15504 | ||
df58fc94 RS |
15505 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15506 | so that the linker relaxation can update targets. */ | |
15507 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15508 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15509 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15510 | return 1; | |
15511 | ||
5caa2b07 MR |
15512 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15513 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15514 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15515 | and BAL to JALX conversion by the linker. */ | |
15516 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15517 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15518 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15519 | && fixp->fx_addsy | |
15520 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15521 | return 1; | |
15522 | ||
7361da2c | 15523 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15524 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15525 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15526 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15527 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15528 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15529 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15530 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15531 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15532 | return 1; | |
15533 | ||
3e722fb5 | 15534 | return 0; |
252b5132 RH |
15535 | } |
15536 | ||
b416ba9b MR |
15537 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15538 | ||
15539 | bfd_boolean | |
15540 | mips_force_relocation_abs (fixS *fixp) | |
15541 | { | |
15542 | if (generic_force_reloc (fixp)) | |
15543 | return TRUE; | |
15544 | ||
15545 | /* These relocations do not have enough bits in the in-place addend | |
15546 | to hold an arbitrary absolute section's offset. */ | |
15547 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15548 | return TRUE; | |
15549 | ||
15550 | return FALSE; | |
15551 | } | |
15552 | ||
b886a2ab RS |
15553 | /* Read the instruction associated with RELOC from BUF. */ |
15554 | ||
15555 | static unsigned int | |
15556 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15557 | { | |
15558 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15559 | return read_compressed_insn (buf, 4); | |
15560 | else | |
15561 | return read_insn (buf); | |
15562 | } | |
15563 | ||
15564 | /* Write instruction INSN to BUF, given that it has been relocated | |
15565 | by RELOC. */ | |
15566 | ||
15567 | static void | |
15568 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15569 | unsigned long insn) | |
15570 | { | |
15571 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15572 | write_compressed_insn (buf, insn, 4); | |
15573 | else | |
15574 | write_insn (buf, insn); | |
15575 | } | |
15576 | ||
9d862524 MR |
15577 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15578 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15579 | ||
15580 | static bfd_boolean | |
15581 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15582 | { | |
15583 | unsigned long opcode; | |
15584 | int other; | |
15585 | char *buf; | |
15586 | ||
15587 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15588 | return FALSE; | |
15589 | ||
15590 | other = S_GET_OTHER (fixP->fx_addsy); | |
15591 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15592 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15593 | switch (fixP->fx_r_type) | |
15594 | { | |
15595 | case BFD_RELOC_MIPS_JMP: | |
15596 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15597 | case BFD_RELOC_MICROMIPS_JMP: | |
15598 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15599 | default: | |
15600 | return FALSE; | |
15601 | } | |
15602 | } | |
15603 | ||
15604 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15605 | jump to a symbol in the same ISA mode. */ | |
15606 | ||
15607 | static bfd_boolean | |
15608 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15609 | { | |
15610 | unsigned long opcode; | |
15611 | int other; | |
15612 | char *buf; | |
15613 | ||
15614 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15615 | return FALSE; | |
15616 | ||
15617 | other = S_GET_OTHER (fixP->fx_addsy); | |
15618 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15619 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15620 | switch (fixP->fx_r_type) | |
15621 | { | |
15622 | case BFD_RELOC_MIPS_JMP: | |
15623 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15624 | case BFD_RELOC_MIPS16_JMP: | |
15625 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15626 | case BFD_RELOC_MICROMIPS_JMP: | |
15627 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15628 | default: | |
15629 | return FALSE; | |
15630 | } | |
15631 | } | |
15632 | ||
15633 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15634 | to a symbol whose value plus addend is not aligned according to the | |
15635 | ultimate (after linker relaxation) jump instruction's immediate field | |
15636 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15637 | regular MIPS code, to (1 << 2). */ | |
15638 | ||
15639 | static bfd_boolean | |
15640 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15641 | { | |
15642 | bfd_boolean micro_to_mips_p; | |
15643 | valueT val; | |
15644 | int other; | |
15645 | ||
15646 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15647 | return FALSE; | |
15648 | ||
15649 | other = S_GET_OTHER (fixP->fx_addsy); | |
15650 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15651 | val += fixP->fx_offset; | |
15652 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15653 | && !ELF_ST_IS_MICROMIPS (other)); | |
15654 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15655 | != ELF_ST_IS_COMPRESSED (other)); | |
15656 | } | |
15657 | ||
15658 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15659 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15660 | symbols check the ISA bit instead. |
15661 | ||
15662 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15663 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15664 | MIPS symbols and associated with BAL instructions as these instructions | |
de194d85 | 15665 | may be converted to JALX by the linker. */ |
9d862524 MR |
15666 | |
15667 | static bfd_boolean | |
15668 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15669 | { | |
15670 | bfd_boolean absolute_p; | |
15671 | unsigned long opcode; | |
15672 | asection *symsec; | |
15673 | valueT val; | |
15674 | int other; | |
15675 | char *buf; | |
15676 | ||
8b10b0b3 MR |
15677 | if (mips_ignore_branch_isa) |
15678 | return FALSE; | |
15679 | ||
9d862524 MR |
15680 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15681 | return FALSE; | |
15682 | ||
15683 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15684 | absolute_p = bfd_is_abs_section (symsec); | |
15685 | ||
15686 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15687 | other = S_GET_OTHER (fixP->fx_addsy); | |
15688 | ||
15689 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15690 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15691 | switch (fixP->fx_r_type) | |
15692 | { | |
15693 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15694 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15695 | && opcode != 0x0411); | |
15696 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15697 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15698 | && opcode != 0x4060); | |
9d862524 MR |
15699 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15700 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15701 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15702 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15703 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15704 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15705 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15706 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15707 | default: | |
15708 | abort (); | |
15709 | } | |
15710 | } | |
15711 | ||
15712 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15713 | branch instruction pointed to by FIXP is not aligned according to the | |
15714 | branch instruction's immediate field requirement. We need the addend | |
15715 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15716 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15717 | won't be set in the symbol's value then. */ | |
15718 | ||
15719 | static bfd_boolean | |
15720 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15721 | { | |
15722 | bfd_boolean absolute_p; | |
15723 | asection *symsec; | |
15724 | valueT isa_bit; | |
15725 | valueT val; | |
15726 | valueT off; | |
15727 | int other; | |
15728 | ||
15729 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15730 | return FALSE; | |
15731 | ||
15732 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15733 | absolute_p = bfd_is_abs_section (symsec); | |
15734 | ||
15735 | val = S_GET_VALUE (fixP->fx_addsy); | |
15736 | other = S_GET_OTHER (fixP->fx_addsy); | |
15737 | off = fixP->fx_offset; | |
15738 | ||
15739 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15740 | val |= ELF_ST_IS_COMPRESSED (other); | |
15741 | val += off; | |
15742 | return (val & 0x3) != isa_bit; | |
15743 | } | |
15744 | ||
15745 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP | |
15746 | and its calculated value VAL. */ | |
15747 | ||
15748 | static void | |
15749 | fix_validate_branch (fixS *fixP, valueT val) | |
15750 | { | |
15751 | if (fixP->fx_done && (val & 0x3) != 0) | |
15752 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15753 | _("branch to misaligned address (0x%lx)"), | |
15754 | (long) (val + md_pcrel_from (fixP))); | |
15755 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15756 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15757 | _("branch to a symbol in another ISA mode")); | |
15758 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15759 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15760 | _("branch to misaligned address (0x%lx)"), | |
15761 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15762 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) | |
15763 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15764 | _("cannot encode misaligned addend " | |
15765 | "in the relocatable field (0x%lx)"), | |
15766 | (long) fixP->fx_offset); | |
15767 | } | |
15768 | ||
252b5132 RH |
15769 | /* Apply a fixup to the object file. */ |
15770 | ||
94f592af | 15771 | void |
55cf6793 | 15772 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15773 | { |
4d68580a | 15774 | char *buf; |
b886a2ab | 15775 | unsigned long insn; |
a7ebbfdf | 15776 | reloc_howto_type *howto; |
252b5132 | 15777 | |
d56a8dda RS |
15778 | if (fixP->fx_pcrel) |
15779 | switch (fixP->fx_r_type) | |
15780 | { | |
15781 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15782 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15783 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15784 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15785 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15786 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15787 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15788 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15789 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15790 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15791 | case BFD_RELOC_HI16_S_PCREL: | |
15792 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15793 | break; |
15794 | ||
15795 | case BFD_RELOC_32: | |
15796 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15797 | break; | |
15798 | ||
15799 | default: | |
15800 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15801 | _("PC-relative reference to a different section")); | |
15802 | break; | |
15803 | } | |
15804 | ||
15805 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15806 | that have no MIPS ELF equivalent. */ | |
15807 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15808 | { | |
15809 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15810 | if (!howto) | |
15811 | return; | |
15812 | } | |
65551fa4 | 15813 | |
df58fc94 RS |
15814 | gas_assert (fixP->fx_size == 2 |
15815 | || fixP->fx_size == 4 | |
d56a8dda | 15816 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15817 | || fixP->fx_r_type == BFD_RELOC_16 |
15818 | || fixP->fx_r_type == BFD_RELOC_64 | |
15819 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15820 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15821 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15822 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15823 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15824 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15825 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15826 | |
4d68580a | 15827 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15828 | |
b1dca8ee RS |
15829 | /* Don't treat parts of a composite relocation as done. There are two |
15830 | reasons for this: | |
15831 | ||
15832 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15833 | should nevertheless be emitted if the first part is. | |
15834 | ||
15835 | (2) In normal usage, composite relocations are never assembly-time | |
15836 | constants. The easiest way of dealing with the pathological | |
15837 | exceptions is to generate a relocation against STN_UNDEF and | |
15838 | leave everything up to the linker. */ | |
3994f87e | 15839 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15840 | fixP->fx_done = 1; |
15841 | ||
15842 | switch (fixP->fx_r_type) | |
15843 | { | |
3f98094e DJ |
15844 | case BFD_RELOC_MIPS_TLS_GD: |
15845 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15846 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15847 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15848 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15849 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15850 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15851 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15852 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15853 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15854 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15855 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15856 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15857 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15858 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15859 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15860 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15861 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15862 | case BFD_RELOC_MIPS16_TLS_GD: |
15863 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15864 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15865 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15866 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15867 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15868 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15869 | if (fixP->fx_addsy) |
15870 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15871 | else | |
15872 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15873 | _("TLS relocation against a constant")); | |
15874 | break; | |
3f98094e | 15875 | |
252b5132 | 15876 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15877 | case BFD_RELOC_MIPS16_JMP: |
15878 | case BFD_RELOC_MICROMIPS_JMP: | |
15879 | { | |
15880 | int shift; | |
15881 | ||
15882 | gas_assert (!fixP->fx_done); | |
15883 | ||
15884 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15885 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15886 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15887 | shift = 1; | |
15888 | else | |
15889 | shift = 2; | |
15890 | ||
15891 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15892 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15893 | _("jump to a symbol in another ISA mode")); | |
15894 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15895 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15896 | _("JALX to a symbol in the same ISA mode")); | |
15897 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15898 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15899 | _("jump to misaligned address (0x%lx)"), | |
15900 | (long) (S_GET_VALUE (fixP->fx_addsy) | |
15901 | + fixP->fx_offset)); | |
15902 | else if (HAVE_IN_PLACE_ADDENDS | |
15903 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15904 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15905 | _("cannot encode misaligned addend " | |
15906 | "in the relocatable field (0x%lx)"), | |
15907 | (long) fixP->fx_offset); | |
15908 | } | |
15909 | /* Fall through. */ | |
15910 | ||
e369bcce TS |
15911 | case BFD_RELOC_MIPS_SHIFT5: |
15912 | case BFD_RELOC_MIPS_SHIFT6: | |
15913 | case BFD_RELOC_MIPS_GOT_DISP: | |
15914 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15915 | case BFD_RELOC_MIPS_GOT_OFST: | |
15916 | case BFD_RELOC_MIPS_SUB: | |
15917 | case BFD_RELOC_MIPS_INSERT_A: | |
15918 | case BFD_RELOC_MIPS_INSERT_B: | |
15919 | case BFD_RELOC_MIPS_DELETE: | |
15920 | case BFD_RELOC_MIPS_HIGHEST: | |
15921 | case BFD_RELOC_MIPS_HIGHER: | |
15922 | case BFD_RELOC_MIPS_SCN_DISP: | |
15923 | case BFD_RELOC_MIPS_REL16: | |
15924 | case BFD_RELOC_MIPS_RELGOT: | |
15925 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15926 | case BFD_RELOC_HI16: |
15927 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15928 | case BFD_RELOC_LO16: |
cdf6fd85 | 15929 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15930 | case BFD_RELOC_MIPS_LITERAL: |
15931 | case BFD_RELOC_MIPS_CALL16: | |
15932 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15933 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15934 | case BFD_RELOC_MIPS_GOT_HI16: |
15935 | case BFD_RELOC_MIPS_GOT_LO16: | |
15936 | case BFD_RELOC_MIPS_CALL_HI16: | |
15937 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15938 | case BFD_RELOC_HI16_S_PCREL: |
15939 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15940 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15941 | case BFD_RELOC_MIPS16_GOT16: |
15942 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15943 | case BFD_RELOC_MIPS16_HI16: |
15944 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15945 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15946 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15947 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15948 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15949 | case BFD_RELOC_MICROMIPS_SUB: | |
15950 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15951 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15952 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15953 | case BFD_RELOC_MICROMIPS_JALR: | |
15954 | case BFD_RELOC_MICROMIPS_HI16: | |
15955 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15956 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15957 | case BFD_RELOC_MICROMIPS_GPREL16: |
15958 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15959 | case BFD_RELOC_MICROMIPS_CALL16: | |
15960 | case BFD_RELOC_MICROMIPS_GOT16: | |
15961 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15962 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15963 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15964 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15965 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15966 | if (fixP->fx_done) |
15967 | { | |
15968 | offsetT value; | |
15969 | ||
15970 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15971 | { | |
15972 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15973 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15974 | insn |= mips16_immed_extend (value, 16); | |
15975 | else | |
15976 | insn |= (value & 0xffff); | |
15977 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15978 | } | |
15979 | else | |
15980 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15981 | _("unsupported constant in relocation")); |
b886a2ab | 15982 | } |
252b5132 RH |
15983 | break; |
15984 | ||
252b5132 RH |
15985 | case BFD_RELOC_64: |
15986 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15987 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15988 | if (fixP->fx_done) |
252b5132 RH |
15989 | { |
15990 | if (8 <= sizeof (valueT)) | |
4d68580a | 15991 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15992 | else |
15993 | { | |
a7ebbfdf | 15994 | valueT hiv; |
252b5132 | 15995 | |
a7ebbfdf | 15996 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15997 | hiv = 0xffffffff; |
15998 | else | |
15999 | hiv = 0; | |
4d68580a RS |
16000 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
16001 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
16002 | } |
16003 | } | |
16004 | break; | |
16005 | ||
056350c6 | 16006 | case BFD_RELOC_RVA: |
252b5132 | 16007 | case BFD_RELOC_32: |
b47468a6 | 16008 | case BFD_RELOC_32_PCREL: |
252b5132 | 16009 | case BFD_RELOC_16: |
d56a8dda | 16010 | case BFD_RELOC_8: |
252b5132 | 16011 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
16012 | value now. This can happen if we have a .word which is not |
16013 | resolved when it appears but is later defined. */ | |
252b5132 | 16014 | if (fixP->fx_done) |
4d68580a | 16015 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
16016 | break; |
16017 | ||
7361da2c | 16018 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 16019 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
16020 | if (!fixP->fx_done) |
16021 | break; | |
16022 | ||
16023 | if (*valP + 0x400000 <= 0x7fffff) | |
16024 | { | |
16025 | insn = read_insn (buf); | |
16026 | insn |= (*valP >> 2) & 0x1fffff; | |
16027 | write_insn (buf, insn); | |
16028 | } | |
16029 | else | |
16030 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16031 | _("branch out of range")); | |
16032 | break; | |
16033 | ||
7361da2c | 16034 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 16035 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
16036 | if (!fixP->fx_done) |
16037 | break; | |
7361da2c | 16038 | |
41947d9e MR |
16039 | if (*valP + 0x8000000 <= 0xfffffff) |
16040 | { | |
16041 | insn = read_insn (buf); | |
16042 | insn |= (*valP >> 2) & 0x3ffffff; | |
16043 | write_insn (buf, insn); | |
16044 | } | |
16045 | else | |
16046 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16047 | _("branch out of range")); | |
7361da2c AB |
16048 | break; |
16049 | ||
16050 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 16051 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 16052 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
16053 | _("PC-relative access using misaligned symbol (%lx)"), |
16054 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
16055 | if ((fixP->fx_offset & 0x7) != 0) | |
16056 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16057 | _("PC-relative access using misaligned offset (%lx)"), | |
16058 | (long) fixP->fx_offset); | |
41947d9e MR |
16059 | if (!fixP->fx_done) |
16060 | break; | |
7361da2c | 16061 | |
41947d9e MR |
16062 | if (*valP + 0x100000 <= 0x1fffff) |
16063 | { | |
16064 | insn = read_insn (buf); | |
16065 | insn |= (*valP >> 3) & 0x3ffff; | |
16066 | write_insn (buf, insn); | |
16067 | } | |
16068 | else | |
16069 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16070 | _("PC-relative access out of range")); | |
7361da2c AB |
16071 | break; |
16072 | ||
16073 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
16074 | if ((*valP & 0x3) != 0) | |
16075 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16076 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 16077 | (long) *valP); |
41947d9e MR |
16078 | if (!fixP->fx_done) |
16079 | break; | |
7361da2c | 16080 | |
41947d9e MR |
16081 | if (*valP + 0x100000 <= 0x1fffff) |
16082 | { | |
16083 | insn = read_insn (buf); | |
16084 | insn |= (*valP >> 2) & 0x7ffff; | |
16085 | write_insn (buf, insn); | |
16086 | } | |
16087 | else | |
16088 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16089 | _("PC-relative access out of range")); | |
7361da2c AB |
16090 | break; |
16091 | ||
252b5132 | 16092 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 16093 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 16094 | |
54f4ddb3 TS |
16095 | /* We need to save the bits in the instruction since fixup_segment() |
16096 | might be deleting the relocation entry (i.e., a branch within | |
16097 | the current segment). */ | |
a7ebbfdf | 16098 | if (! fixP->fx_done) |
bb2d6cd7 | 16099 | break; |
252b5132 | 16100 | |
54f4ddb3 | 16101 | /* Update old instruction data. */ |
4d68580a | 16102 | insn = read_insn (buf); |
252b5132 | 16103 | |
a7ebbfdf TS |
16104 | if (*valP + 0x20000 <= 0x3ffff) |
16105 | { | |
16106 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 16107 | write_insn (buf, insn); |
a7ebbfdf | 16108 | } |
ce8ad872 | 16109 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
16110 | && fixP->fx_done |
16111 | && fixP->fx_frag->fr_address >= text_section->vma | |
16112 | && (fixP->fx_frag->fr_address | |
587aac4e | 16113 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
16114 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
16115 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
16116 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
16117 | { |
16118 | /* The branch offset is too large. If this is an | |
16119 | unconditional branch, and we are not generating PIC code, | |
16120 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
16121 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
16122 | insn = 0x0c000000; /* jal */ | |
252b5132 | 16123 | else |
a7ebbfdf TS |
16124 | insn = 0x08000000; /* j */ |
16125 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
16126 | fixP->fx_done = 0; | |
16127 | fixP->fx_addsy = section_symbol (text_section); | |
16128 | *valP += md_pcrel_from (fixP); | |
4d68580a | 16129 | write_insn (buf, insn); |
a7ebbfdf TS |
16130 | } |
16131 | else | |
16132 | { | |
16133 | /* If we got here, we have branch-relaxation disabled, | |
16134 | and there's nothing we can do to fix this instruction | |
16135 | without turning it into a longer sequence. */ | |
16136 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 16137 | _("branch out of range")); |
252b5132 | 16138 | } |
252b5132 RH |
16139 | break; |
16140 | ||
c9775dde | 16141 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
16142 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
16143 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
16144 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 16145 | gas_assert (!fixP->fx_done); |
9d862524 MR |
16146 | if (fix_bad_cross_mode_branch_p (fixP)) |
16147 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16148 | _("branch to a symbol in another ISA mode")); | |
16149 | else if (fixP->fx_addsy | |
16150 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
16151 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
16152 | && (fixP->fx_offset & 0x1) != 0) | |
16153 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16154 | _("branch to misaligned address (0x%lx)"), | |
16155 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
16156 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) | |
16157 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16158 | _("cannot encode misaligned addend " | |
16159 | "in the relocatable field (0x%lx)"), | |
16160 | (long) fixP->fx_offset); | |
df58fc94 RS |
16161 | break; |
16162 | ||
252b5132 RH |
16163 | case BFD_RELOC_VTABLE_INHERIT: |
16164 | fixP->fx_done = 0; | |
16165 | if (fixP->fx_addsy | |
16166 | && !S_IS_DEFINED (fixP->fx_addsy) | |
16167 | && !S_IS_WEAK (fixP->fx_addsy)) | |
16168 | S_SET_WEAK (fixP->fx_addsy); | |
16169 | break; | |
16170 | ||
2f0c68f2 | 16171 | case BFD_RELOC_NONE: |
252b5132 RH |
16172 | case BFD_RELOC_VTABLE_ENTRY: |
16173 | fixP->fx_done = 0; | |
16174 | break; | |
16175 | ||
16176 | default: | |
b37df7c4 | 16177 | abort (); |
252b5132 | 16178 | } |
a7ebbfdf TS |
16179 | |
16180 | /* Remember value for tc_gen_reloc. */ | |
16181 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
16182 | } |
16183 | ||
252b5132 | 16184 | static symbolS * |
17a2f251 | 16185 | get_symbol (void) |
252b5132 RH |
16186 | { |
16187 | int c; | |
16188 | char *name; | |
16189 | symbolS *p; | |
16190 | ||
d02603dc | 16191 | c = get_symbol_name (&name); |
252b5132 | 16192 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 16193 | (void) restore_line_pointer (c); |
252b5132 RH |
16194 | return p; |
16195 | } | |
16196 | ||
742a56fe RS |
16197 | /* Align the current frag to a given power of two. If a particular |
16198 | fill byte should be used, FILL points to an integer that contains | |
16199 | that byte, otherwise FILL is null. | |
16200 | ||
462427c4 RS |
16201 | This function used to have the comment: |
16202 | ||
16203 | The MIPS assembler also automatically adjusts any preceding label. | |
16204 | ||
16205 | The implementation therefore applied the adjustment to a maximum of | |
16206 | one label. However, other label adjustments are applied to batches | |
16207 | of labels, and adjusting just one caused problems when new labels | |
16208 | were added for the sake of debugging or unwind information. | |
16209 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
16210 | |
16211 | static void | |
462427c4 | 16212 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16213 | { |
7d10b47d | 16214 | mips_emit_delays (); |
df58fc94 | 16215 | mips_record_compressed_mode (); |
742a56fe RS |
16216 | if (fill == NULL && subseg_text_p (now_seg)) |
16217 | frag_align_code (to, 0); | |
16218 | else | |
16219 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16220 | record_alignment (now_seg, to); |
462427c4 | 16221 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16222 | } |
16223 | ||
16224 | /* Align to a given power of two. .align 0 turns off the automatic | |
16225 | alignment used by the data creating pseudo-ops. */ | |
16226 | ||
16227 | static void | |
17a2f251 | 16228 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16229 | { |
742a56fe | 16230 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16231 | long max_alignment = 28; |
252b5132 | 16232 | |
54f4ddb3 | 16233 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16234 | to the aligned address. |
54f4ddb3 | 16235 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16236 | a .align pseudo instruction. |
54f4ddb3 | 16237 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16238 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16239 | We don't. */ |
252b5132 RH |
16240 | |
16241 | temp = get_absolute_expression (); | |
16242 | if (temp > max_alignment) | |
1661c76c | 16243 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
16244 | else if (temp < 0) |
16245 | { | |
1661c76c | 16246 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
16247 | temp = 0; |
16248 | } | |
16249 | if (*input_line_pointer == ',') | |
16250 | { | |
f9419b05 | 16251 | ++input_line_pointer; |
742a56fe RS |
16252 | fill_value = get_absolute_expression (); |
16253 | fill_ptr = &fill_value; | |
252b5132 RH |
16254 | } |
16255 | else | |
742a56fe | 16256 | fill_ptr = 0; |
252b5132 RH |
16257 | if (temp) |
16258 | { | |
a8dbcb85 TS |
16259 | segment_info_type *si = seg_info (now_seg); |
16260 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16261 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16262 | auto_align = 1; |
462427c4 | 16263 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16264 | } |
16265 | else | |
16266 | { | |
16267 | auto_align = 0; | |
16268 | } | |
16269 | ||
16270 | demand_empty_rest_of_line (); | |
16271 | } | |
16272 | ||
252b5132 | 16273 | static void |
17a2f251 | 16274 | s_change_sec (int sec) |
252b5132 RH |
16275 | { |
16276 | segT seg; | |
16277 | ||
252b5132 RH |
16278 | /* The ELF backend needs to know that we are changing sections, so |
16279 | that .previous works correctly. We could do something like check | |
b6ff326e | 16280 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16281 | as it would not be appropriate to use it in the section changing |
16282 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16283 | This should be cleaner, somehow. */ | |
f3ded42a | 16284 | obj_elf_section_change_hook (); |
252b5132 | 16285 | |
7d10b47d | 16286 | mips_emit_delays (); |
6a32d874 | 16287 | |
252b5132 RH |
16288 | switch (sec) |
16289 | { | |
16290 | case 't': | |
16291 | s_text (0); | |
16292 | break; | |
16293 | case 'd': | |
16294 | s_data (0); | |
16295 | break; | |
16296 | case 'b': | |
16297 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16298 | demand_empty_rest_of_line (); | |
16299 | break; | |
16300 | ||
16301 | case 'r': | |
4d0d148d TS |
16302 | seg = subseg_new (RDATA_SECTION_NAME, |
16303 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16304 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16305 | | SEC_READONLY | SEC_RELOC | |
16306 | | SEC_DATA)); | |
16307 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16308 | record_alignment (seg, 4); | |
4d0d148d | 16309 | demand_empty_rest_of_line (); |
252b5132 RH |
16310 | break; |
16311 | ||
16312 | case 's': | |
4d0d148d | 16313 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
16314 | bfd_set_section_flags (stdoutput, seg, |
16315 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
16316 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16317 | record_alignment (seg, 4); | |
4d0d148d TS |
16318 | demand_empty_rest_of_line (); |
16319 | break; | |
998b3c36 MR |
16320 | |
16321 | case 'B': | |
16322 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16323 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
16324 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16325 | record_alignment (seg, 4); | |
998b3c36 MR |
16326 | demand_empty_rest_of_line (); |
16327 | break; | |
252b5132 RH |
16328 | } |
16329 | ||
16330 | auto_align = 1; | |
16331 | } | |
b34976b6 | 16332 | |
cca86cc8 | 16333 | void |
17a2f251 | 16334 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16335 | { |
d02603dc | 16336 | char *saved_ilp; |
cca86cc8 | 16337 | char *section_name; |
d02603dc | 16338 | char c, endc; |
684022ea | 16339 | char next_c = 0; |
cca86cc8 SC |
16340 | int section_type; |
16341 | int section_flag; | |
16342 | int section_entry_size; | |
16343 | int section_alignment; | |
b34976b6 | 16344 | |
d02603dc NC |
16345 | saved_ilp = input_line_pointer; |
16346 | endc = get_symbol_name (§ion_name); | |
16347 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 16348 | if (c) |
d02603dc | 16349 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 16350 | |
4cf0dd0d TS |
16351 | /* Do we have .section Name<,"flags">? */ |
16352 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16353 | { |
d02603dc NC |
16354 | /* Just after name is now '\0'. */ |
16355 | (void) restore_line_pointer (endc); | |
16356 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
16357 | obj_elf_section (ignore); |
16358 | return; | |
16359 | } | |
d02603dc NC |
16360 | |
16361 | section_name = xstrdup (section_name); | |
16362 | c = restore_line_pointer (endc); | |
16363 | ||
cca86cc8 SC |
16364 | input_line_pointer++; |
16365 | ||
16366 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16367 | if (c == ',') | |
16368 | section_type = get_absolute_expression (); | |
16369 | else | |
16370 | section_type = 0; | |
d02603dc | 16371 | |
cca86cc8 SC |
16372 | if (*input_line_pointer++ == ',') |
16373 | section_flag = get_absolute_expression (); | |
16374 | else | |
16375 | section_flag = 0; | |
d02603dc | 16376 | |
cca86cc8 SC |
16377 | if (*input_line_pointer++ == ',') |
16378 | section_entry_size = get_absolute_expression (); | |
16379 | else | |
16380 | section_entry_size = 0; | |
d02603dc | 16381 | |
cca86cc8 SC |
16382 | if (*input_line_pointer++ == ',') |
16383 | section_alignment = get_absolute_expression (); | |
16384 | else | |
16385 | section_alignment = 0; | |
d02603dc | 16386 | |
87975d2a AM |
16387 | /* FIXME: really ignore? */ |
16388 | (void) section_alignment; | |
cca86cc8 | 16389 | |
8ab8a5c8 RS |
16390 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16391 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16392 | traditionally had to fall back on the more common @progbits instead. | |
16393 | ||
16394 | There's nothing really harmful in this, since bfd will correct | |
16395 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16396 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16397 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16398 | ||
16399 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16400 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16401 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16402 | generic type-checking code. */ | |
16403 | if (section_type == SHT_MIPS_DWARF) | |
16404 | section_type = SHT_PROGBITS; | |
16405 | ||
a91e1603 | 16406 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
cca86cc8 | 16407 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
16408 | |
16409 | if (now_seg->name != section_name) | |
16410 | free (section_name); | |
cca86cc8 | 16411 | } |
252b5132 RH |
16412 | |
16413 | void | |
17a2f251 | 16414 | mips_enable_auto_align (void) |
252b5132 RH |
16415 | { |
16416 | auto_align = 1; | |
16417 | } | |
16418 | ||
16419 | static void | |
17a2f251 | 16420 | s_cons (int log_size) |
252b5132 | 16421 | { |
a8dbcb85 TS |
16422 | segment_info_type *si = seg_info (now_seg); |
16423 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16424 | |
7d10b47d | 16425 | mips_emit_delays (); |
252b5132 | 16426 | if (log_size > 0 && auto_align) |
462427c4 | 16427 | mips_align (log_size, 0, l); |
252b5132 | 16428 | cons (1 << log_size); |
a1facbec | 16429 | mips_clear_insn_labels (); |
252b5132 RH |
16430 | } |
16431 | ||
16432 | static void | |
17a2f251 | 16433 | s_float_cons (int type) |
252b5132 | 16434 | { |
a8dbcb85 TS |
16435 | segment_info_type *si = seg_info (now_seg); |
16436 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16437 | |
7d10b47d | 16438 | mips_emit_delays (); |
252b5132 RH |
16439 | |
16440 | if (auto_align) | |
49309057 ILT |
16441 | { |
16442 | if (type == 'd') | |
462427c4 | 16443 | mips_align (3, 0, l); |
49309057 | 16444 | else |
462427c4 | 16445 | mips_align (2, 0, l); |
49309057 | 16446 | } |
252b5132 | 16447 | |
252b5132 | 16448 | float_cons (type); |
a1facbec | 16449 | mips_clear_insn_labels (); |
252b5132 RH |
16450 | } |
16451 | ||
16452 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16453 | permitted to say | |
16454 | .globl foo .text | |
16455 | where foo is an undefined symbol, to mean that foo should be | |
16456 | considered to be the address of a function. */ | |
16457 | ||
16458 | static void | |
17a2f251 | 16459 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16460 | { |
16461 | char *name; | |
16462 | int c; | |
16463 | symbolS *symbolP; | |
252b5132 | 16464 | |
8a06b769 | 16465 | do |
252b5132 | 16466 | { |
d02603dc | 16467 | c = get_symbol_name (&name); |
8a06b769 TS |
16468 | symbolP = symbol_find_or_make (name); |
16469 | S_SET_EXTERNAL (symbolP); | |
16470 | ||
252b5132 | 16471 | *input_line_pointer = c; |
d02603dc | 16472 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 16473 | |
8a06b769 TS |
16474 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16475 | && (*input_line_pointer != ',')) | |
16476 | { | |
16477 | char *secname; | |
16478 | asection *sec; | |
16479 | ||
d02603dc | 16480 | c = get_symbol_name (&secname); |
8a06b769 TS |
16481 | sec = bfd_get_section_by_name (stdoutput, secname); |
16482 | if (sec == NULL) | |
16483 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16484 | (void) restore_line_pointer (c); |
8a06b769 TS |
16485 | |
16486 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
d69cd47e | 16487 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
8a06b769 TS |
16488 | } |
16489 | ||
8a06b769 TS |
16490 | c = *input_line_pointer; |
16491 | if (c == ',') | |
16492 | { | |
16493 | input_line_pointer++; | |
16494 | SKIP_WHITESPACE (); | |
16495 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16496 | c = '\n'; | |
16497 | } | |
16498 | } | |
16499 | while (c == ','); | |
252b5132 | 16500 | |
252b5132 RH |
16501 | demand_empty_rest_of_line (); |
16502 | } | |
16503 | ||
d69cd47e AM |
16504 | #ifdef TE_IRIX |
16505 | /* The Irix 5 and 6 assemblers set the type of any common symbol and | |
16506 | any undefined non-function symbol to STT_OBJECT. We try to be | |
16507 | compatible, since newer Irix 5 and 6 linkers care. */ | |
16508 | ||
16509 | void | |
16510 | mips_frob_symbol (symbolS *symp ATTRIBUTE_UNUSED) | |
16511 | { | |
16512 | /* This late in assembly we can set BSF_OBJECT indiscriminately | |
16513 | and let elf.c:swap_out_syms sort out the symbol type. */ | |
16514 | flagword *flags = &symbol_get_bfdsym (symp)->flags; | |
16515 | if ((*flags & (BSF_GLOBAL | BSF_WEAK)) != 0 | |
16516 | || !S_IS_DEFINED (symp)) | |
16517 | *flags |= BSF_OBJECT; | |
16518 | } | |
16519 | #endif | |
16520 | ||
252b5132 | 16521 | static void |
17a2f251 | 16522 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16523 | { |
16524 | char *opt; | |
16525 | char c; | |
16526 | ||
d02603dc | 16527 | c = get_symbol_name (&opt); |
252b5132 RH |
16528 | |
16529 | if (*opt == 'O') | |
16530 | { | |
16531 | /* FIXME: What does this mean? */ | |
16532 | } | |
41a1578e | 16533 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16534 | { |
16535 | int i; | |
16536 | ||
16537 | i = atoi (opt + 3); | |
668c5ebc MR |
16538 | if (i != 0 && i != 2) |
16539 | as_bad (_(".option pic%d not supported"), i); | |
16540 | else if (mips_pic == VXWORKS_PIC) | |
16541 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16542 | else if (i == 0) | |
252b5132 RH |
16543 | mips_pic = NO_PIC; |
16544 | else if (i == 2) | |
143d77c5 | 16545 | { |
8b828383 | 16546 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16547 | mips_abicalls = TRUE; |
16548 | } | |
252b5132 | 16549 | |
4d0d148d | 16550 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16551 | { |
16552 | if (g_switch_seen && g_switch_value != 0) | |
16553 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16554 | g_switch_value = 0; | |
16555 | bfd_set_gp_size (stdoutput, 0); | |
16556 | } | |
16557 | } | |
16558 | else | |
1661c76c | 16559 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16560 | |
d02603dc | 16561 | (void) restore_line_pointer (c); |
252b5132 RH |
16562 | demand_empty_rest_of_line (); |
16563 | } | |
16564 | ||
16565 | /* This structure is used to hold a stack of .set values. */ | |
16566 | ||
e972090a NC |
16567 | struct mips_option_stack |
16568 | { | |
252b5132 RH |
16569 | struct mips_option_stack *next; |
16570 | struct mips_set_options options; | |
16571 | }; | |
16572 | ||
16573 | static struct mips_option_stack *mips_opts_stack; | |
16574 | ||
22522f88 MR |
16575 | /* Return status for .set/.module option handling. */ |
16576 | ||
16577 | enum code_option_type | |
16578 | { | |
16579 | /* Unrecognized option. */ | |
16580 | OPTION_TYPE_BAD = -1, | |
16581 | ||
16582 | /* Ordinary option. */ | |
16583 | OPTION_TYPE_NORMAL, | |
16584 | ||
16585 | /* ISA changing option. */ | |
16586 | OPTION_TYPE_ISA | |
16587 | }; | |
16588 | ||
16589 | /* Handle common .set/.module options. Return status indicating option | |
16590 | type. */ | |
16591 | ||
16592 | static enum code_option_type | |
919731af | 16593 | parse_code_option (char * name) |
252b5132 | 16594 | { |
22522f88 | 16595 | bfd_boolean isa_set = FALSE; |
c6278170 | 16596 | const struct mips_ase *ase; |
22522f88 | 16597 | |
919731af | 16598 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16599 | { |
16600 | char *s = name + 3; | |
16601 | ||
16602 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16603 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16604 | } |
252b5132 | 16605 | else if (strcmp (name, "at") == 0) |
919731af | 16606 | mips_opts.at = ATREG; |
252b5132 | 16607 | else if (strcmp (name, "noat") == 0) |
919731af | 16608 | mips_opts.at = ZERO; |
252b5132 | 16609 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16610 | mips_opts.nomove = 0; |
252b5132 | 16611 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16612 | mips_opts.nomove = 1; |
252b5132 | 16613 | else if (strcmp (name, "bopt") == 0) |
919731af | 16614 | mips_opts.nobopt = 0; |
252b5132 | 16615 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16616 | mips_opts.nobopt = 1; |
ad3fea08 | 16617 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16618 | mips_opts.gp = 32; |
ad3fea08 | 16619 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16620 | mips_opts.gp = 64; |
ad3fea08 | 16621 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16622 | mips_opts.fp = 32; |
351cdf24 MF |
16623 | else if (strcmp (name, "fp=xx") == 0) |
16624 | mips_opts.fp = 0; | |
ad3fea08 | 16625 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16626 | mips_opts.fp = 64; |
037b32b9 AN |
16627 | else if (strcmp (name, "softfloat") == 0) |
16628 | mips_opts.soft_float = 1; | |
16629 | else if (strcmp (name, "hardfloat") == 0) | |
16630 | mips_opts.soft_float = 0; | |
16631 | else if (strcmp (name, "singlefloat") == 0) | |
16632 | mips_opts.single_float = 1; | |
16633 | else if (strcmp (name, "doublefloat") == 0) | |
16634 | mips_opts.single_float = 0; | |
351cdf24 MF |
16635 | else if (strcmp (name, "nooddspreg") == 0) |
16636 | mips_opts.oddspreg = 0; | |
16637 | else if (strcmp (name, "oddspreg") == 0) | |
16638 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16639 | else if (strcmp (name, "mips16") == 0 |
16640 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16641 | mips_opts.mips16 = 1; |
252b5132 RH |
16642 | else if (strcmp (name, "nomips16") == 0 |
16643 | || strcmp (name, "noMIPS-16") == 0) | |
16644 | mips_opts.mips16 = 0; | |
df58fc94 | 16645 | else if (strcmp (name, "micromips") == 0) |
919731af | 16646 | mips_opts.micromips = 1; |
df58fc94 RS |
16647 | else if (strcmp (name, "nomicromips") == 0) |
16648 | mips_opts.micromips = 0; | |
c6278170 RS |
16649 | else if (name[0] == 'n' |
16650 | && name[1] == 'o' | |
16651 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16652 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16653 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16654 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16655 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16656 | { |
1a2c1fad CD |
16657 | /* Permit the user to change the ISA and architecture on the fly. |
16658 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16659 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16660 | { |
16661 | const struct mips_cpu_info *p; | |
16662 | ||
919731af | 16663 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16664 | if (!p) |
16665 | as_bad (_("unknown architecture %s"), name + 5); | |
16666 | else | |
16667 | { | |
16668 | mips_opts.arch = p->cpu; | |
16669 | mips_opts.isa = p->isa; | |
22522f88 | 16670 | isa_set = TRUE; |
3315614d | 16671 | mips_opts.init_ase = p->ase; |
1a2c1fad CD |
16672 | } |
16673 | } | |
81a21e38 TS |
16674 | else if (strncmp (name, "mips", 4) == 0) |
16675 | { | |
16676 | const struct mips_cpu_info *p; | |
16677 | ||
919731af | 16678 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16679 | if (!p) |
16680 | as_bad (_("unknown ISA level %s"), name + 4); | |
16681 | else | |
16682 | { | |
16683 | mips_opts.arch = p->cpu; | |
16684 | mips_opts.isa = p->isa; | |
22522f88 | 16685 | isa_set = TRUE; |
3315614d | 16686 | mips_opts.init_ase = p->ase; |
81a21e38 TS |
16687 | } |
16688 | } | |
af7ee8bf | 16689 | else |
81a21e38 | 16690 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16691 | } |
16692 | else if (strcmp (name, "autoextend") == 0) | |
16693 | mips_opts.noautoextend = 0; | |
16694 | else if (strcmp (name, "noautoextend") == 0) | |
16695 | mips_opts.noautoextend = 1; | |
833794fc MR |
16696 | else if (strcmp (name, "insn32") == 0) |
16697 | mips_opts.insn32 = TRUE; | |
16698 | else if (strcmp (name, "noinsn32") == 0) | |
16699 | mips_opts.insn32 = FALSE; | |
919731af | 16700 | else if (strcmp (name, "sym32") == 0) |
16701 | mips_opts.sym32 = TRUE; | |
16702 | else if (strcmp (name, "nosym32") == 0) | |
16703 | mips_opts.sym32 = FALSE; | |
16704 | else | |
22522f88 MR |
16705 | return OPTION_TYPE_BAD; |
16706 | ||
16707 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16708 | } |
16709 | ||
16710 | /* Handle the .set pseudo-op. */ | |
16711 | ||
16712 | static void | |
16713 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16714 | { | |
22522f88 | 16715 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16716 | char *name = input_line_pointer, ch; |
919731af | 16717 | |
16718 | file_mips_check_options (); | |
16719 | ||
16720 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16721 | ++input_line_pointer; | |
16722 | ch = *input_line_pointer; | |
16723 | *input_line_pointer = '\0'; | |
16724 | ||
16725 | if (strchr (name, ',')) | |
16726 | { | |
16727 | /* Generic ".set" directive; use the generic handler. */ | |
16728 | *input_line_pointer = ch; | |
16729 | input_line_pointer = name; | |
16730 | s_set (0); | |
16731 | return; | |
16732 | } | |
16733 | ||
16734 | if (strcmp (name, "reorder") == 0) | |
16735 | { | |
16736 | if (mips_opts.noreorder) | |
16737 | end_noreorder (); | |
16738 | } | |
16739 | else if (strcmp (name, "noreorder") == 0) | |
16740 | { | |
16741 | if (!mips_opts.noreorder) | |
16742 | start_noreorder (); | |
16743 | } | |
16744 | else if (strcmp (name, "macro") == 0) | |
16745 | mips_opts.warn_about_macros = 0; | |
16746 | else if (strcmp (name, "nomacro") == 0) | |
16747 | { | |
16748 | if (mips_opts.noreorder == 0) | |
16749 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16750 | mips_opts.warn_about_macros = 1; | |
16751 | } | |
16752 | else if (strcmp (name, "gp=default") == 0) | |
16753 | mips_opts.gp = file_mips_opts.gp; | |
16754 | else if (strcmp (name, "fp=default") == 0) | |
16755 | mips_opts.fp = file_mips_opts.fp; | |
16756 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16757 | { | |
16758 | mips_opts.isa = file_mips_opts.isa; | |
16759 | mips_opts.arch = file_mips_opts.arch; | |
3315614d | 16760 | mips_opts.init_ase = file_mips_opts.init_ase; |
919731af | 16761 | mips_opts.gp = file_mips_opts.gp; |
16762 | mips_opts.fp = file_mips_opts.fp; | |
16763 | } | |
252b5132 RH |
16764 | else if (strcmp (name, "push") == 0) |
16765 | { | |
16766 | struct mips_option_stack *s; | |
16767 | ||
325801bd | 16768 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16769 | s->next = mips_opts_stack; |
16770 | s->options = mips_opts; | |
16771 | mips_opts_stack = s; | |
16772 | } | |
16773 | else if (strcmp (name, "pop") == 0) | |
16774 | { | |
16775 | struct mips_option_stack *s; | |
16776 | ||
16777 | s = mips_opts_stack; | |
16778 | if (s == NULL) | |
16779 | as_bad (_(".set pop with no .set push")); | |
16780 | else | |
16781 | { | |
16782 | /* If we're changing the reorder mode we need to handle | |
16783 | delay slots correctly. */ | |
16784 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16785 | start_noreorder (); |
252b5132 | 16786 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16787 | end_noreorder (); |
252b5132 RH |
16788 | |
16789 | mips_opts = s->options; | |
16790 | mips_opts_stack = s->next; | |
16791 | free (s); | |
16792 | } | |
16793 | } | |
22522f88 MR |
16794 | else |
16795 | { | |
16796 | type = parse_code_option (name); | |
16797 | if (type == OPTION_TYPE_BAD) | |
16798 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16799 | } | |
919731af | 16800 | |
16801 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16802 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16803 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16804 | { |
919731af | 16805 | switch (mips_opts.isa) |
16806 | { | |
16807 | case 0: | |
16808 | break; | |
16809 | case ISA_MIPS1: | |
351cdf24 MF |
16810 | /* MIPS I cannot support FPXX. */ |
16811 | mips_opts.fp = 32; | |
16812 | /* fall-through. */ | |
919731af | 16813 | case ISA_MIPS2: |
16814 | case ISA_MIPS32: | |
16815 | case ISA_MIPS32R2: | |
16816 | case ISA_MIPS32R3: | |
16817 | case ISA_MIPS32R5: | |
16818 | mips_opts.gp = 32; | |
351cdf24 MF |
16819 | if (mips_opts.fp != 0) |
16820 | mips_opts.fp = 32; | |
919731af | 16821 | break; |
7361da2c AB |
16822 | case ISA_MIPS32R6: |
16823 | mips_opts.gp = 32; | |
16824 | mips_opts.fp = 64; | |
16825 | break; | |
919731af | 16826 | case ISA_MIPS3: |
16827 | case ISA_MIPS4: | |
16828 | case ISA_MIPS5: | |
16829 | case ISA_MIPS64: | |
16830 | case ISA_MIPS64R2: | |
16831 | case ISA_MIPS64R3: | |
16832 | case ISA_MIPS64R5: | |
7361da2c | 16833 | case ISA_MIPS64R6: |
919731af | 16834 | mips_opts.gp = 64; |
351cdf24 MF |
16835 | if (mips_opts.fp != 0) |
16836 | { | |
16837 | if (mips_opts.arch == CPU_R5900) | |
16838 | mips_opts.fp = 32; | |
16839 | else | |
16840 | mips_opts.fp = 64; | |
16841 | } | |
919731af | 16842 | break; |
16843 | default: | |
16844 | as_bad (_("unknown ISA level %s"), name + 4); | |
16845 | break; | |
16846 | } | |
e6559e01 | 16847 | } |
919731af | 16848 | |
16849 | mips_check_options (&mips_opts, FALSE); | |
16850 | ||
16851 | mips_check_isa_supports_ases (); | |
16852 | *input_line_pointer = ch; | |
16853 | demand_empty_rest_of_line (); | |
16854 | } | |
16855 | ||
16856 | /* Handle the .module pseudo-op. */ | |
16857 | ||
16858 | static void | |
16859 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16860 | { | |
16861 | char *name = input_line_pointer, ch; | |
16862 | ||
16863 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16864 | ++input_line_pointer; | |
16865 | ch = *input_line_pointer; | |
16866 | *input_line_pointer = '\0'; | |
16867 | ||
16868 | if (!file_mips_opts_checked) | |
252b5132 | 16869 | { |
22522f88 | 16870 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16871 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16872 | ||
16873 | /* Update module level settings from mips_opts. */ | |
16874 | file_mips_opts = mips_opts; | |
252b5132 | 16875 | } |
919731af | 16876 | else |
16877 | as_bad (_(".module is not permitted after generating code")); | |
16878 | ||
252b5132 RH |
16879 | *input_line_pointer = ch; |
16880 | demand_empty_rest_of_line (); | |
16881 | } | |
16882 | ||
16883 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16884 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16885 | ||
16886 | static void | |
17a2f251 | 16887 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16888 | { |
16889 | mips_pic = SVR4_PIC; | |
143d77c5 | 16890 | mips_abicalls = TRUE; |
4d0d148d TS |
16891 | |
16892 | if (g_switch_seen && g_switch_value != 0) | |
16893 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16894 | g_switch_value = 0; | |
16895 | ||
252b5132 RH |
16896 | bfd_set_gp_size (stdoutput, 0); |
16897 | demand_empty_rest_of_line (); | |
16898 | } | |
16899 | ||
16900 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16901 | PIC code. It sets the $gp register for the function based on the | |
16902 | function address, which is in the register named in the argument. | |
16903 | This uses a relocation against _gp_disp, which is handled specially | |
16904 | by the linker. The result is: | |
16905 | lui $gp,%hi(_gp_disp) | |
16906 | addiu $gp,$gp,%lo(_gp_disp) | |
16907 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16908 | The .cpload argument is normally $25 == $t9. |
16909 | ||
16910 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16911 | lui $gp,%hi(__gnu_local_gp) |
16912 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16913 | and the argument is ignored. This saves an instruction, but the |
16914 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16915 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16916 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16917 | |
16918 | static void | |
17a2f251 | 16919 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16920 | { |
16921 | expressionS ex; | |
aa6975fb ILT |
16922 | int reg; |
16923 | int in_shared; | |
252b5132 | 16924 | |
919731af | 16925 | file_mips_check_options (); |
16926 | ||
6478892d TS |
16927 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16928 | .cpload is ignored. */ | |
16929 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16930 | { |
16931 | s_ignore (0); | |
16932 | return; | |
16933 | } | |
16934 | ||
a276b80c MR |
16935 | if (mips_opts.mips16) |
16936 | { | |
16937 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16938 | ignore_rest_of_line (); | |
16939 | return; | |
16940 | } | |
16941 | ||
d3ecfc59 | 16942 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16943 | if (mips_opts.noreorder == 0) |
16944 | as_warn (_(".cpload not in noreorder section")); | |
16945 | ||
aa6975fb ILT |
16946 | reg = tc_get_register (0); |
16947 | ||
16948 | /* If we need to produce a 64-bit address, we are better off using | |
16949 | the default instruction sequence. */ | |
aed1a261 | 16950 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16951 | |
252b5132 | 16952 | ex.X_op = O_symbol; |
bbe506e8 TS |
16953 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16954 | "__gnu_local_gp"); | |
252b5132 RH |
16955 | ex.X_op_symbol = NULL; |
16956 | ex.X_add_number = 0; | |
16957 | ||
16958 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16959 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16960 | |
8a75745d MR |
16961 | mips_mark_labels (); |
16962 | mips_assembling_insn = TRUE; | |
16963 | ||
584892a6 | 16964 | macro_start (); |
67c0d1eb RS |
16965 | macro_build_lui (&ex, mips_gp_register); |
16966 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16967 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16968 | if (in_shared) |
16969 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16970 | mips_gp_register, reg); | |
584892a6 | 16971 | macro_end (); |
252b5132 | 16972 | |
8a75745d | 16973 | mips_assembling_insn = FALSE; |
252b5132 RH |
16974 | demand_empty_rest_of_line (); |
16975 | } | |
16976 | ||
6478892d TS |
16977 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16978 | .cpsetup $reg1, offset|$reg2, label | |
16979 | ||
16980 | If offset is given, this results in: | |
16981 | sd $gp, offset($sp) | |
956cd1d6 | 16982 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16983 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16984 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16985 | |
16986 | If $reg2 is given, this results in: | |
40fc1451 | 16987 | or $reg2, $gp, $0 |
956cd1d6 | 16988 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16989 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16990 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16991 | $reg1 is normally $25 == $t9. |
16992 | ||
16993 | The -mno-shared option replaces the last three instructions with | |
16994 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16995 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16996 | |
6478892d | 16997 | static void |
17a2f251 | 16998 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16999 | { |
17000 | expressionS ex_off; | |
17001 | expressionS ex_sym; | |
17002 | int reg1; | |
6478892d | 17003 | |
919731af | 17004 | file_mips_check_options (); |
17005 | ||
8586fc66 | 17006 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
17007 | We also need NewABI support. */ |
17008 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17009 | { | |
17010 | s_ignore (0); | |
17011 | return; | |
17012 | } | |
17013 | ||
a276b80c MR |
17014 | if (mips_opts.mips16) |
17015 | { | |
17016 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
17017 | ignore_rest_of_line (); | |
17018 | return; | |
17019 | } | |
17020 | ||
6478892d TS |
17021 | reg1 = tc_get_register (0); |
17022 | SKIP_WHITESPACE (); | |
17023 | if (*input_line_pointer != ',') | |
17024 | { | |
17025 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
17026 | return; | |
17027 | } | |
17028 | else | |
80245285 | 17029 | ++input_line_pointer; |
6478892d TS |
17030 | SKIP_WHITESPACE (); |
17031 | if (*input_line_pointer == '$') | |
80245285 TS |
17032 | { |
17033 | mips_cpreturn_register = tc_get_register (0); | |
17034 | mips_cpreturn_offset = -1; | |
17035 | } | |
6478892d | 17036 | else |
80245285 TS |
17037 | { |
17038 | mips_cpreturn_offset = get_absolute_expression (); | |
17039 | mips_cpreturn_register = -1; | |
17040 | } | |
6478892d TS |
17041 | SKIP_WHITESPACE (); |
17042 | if (*input_line_pointer != ',') | |
17043 | { | |
17044 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
17045 | return; | |
17046 | } | |
17047 | else | |
f9419b05 | 17048 | ++input_line_pointer; |
6478892d | 17049 | SKIP_WHITESPACE (); |
f21f8242 | 17050 | expression (&ex_sym); |
6478892d | 17051 | |
8a75745d MR |
17052 | mips_mark_labels (); |
17053 | mips_assembling_insn = TRUE; | |
17054 | ||
584892a6 | 17055 | macro_start (); |
6478892d TS |
17056 | if (mips_cpreturn_register == -1) |
17057 | { | |
17058 | ex_off.X_op = O_constant; | |
17059 | ex_off.X_add_symbol = NULL; | |
17060 | ex_off.X_op_symbol = NULL; | |
17061 | ex_off.X_add_number = mips_cpreturn_offset; | |
17062 | ||
67c0d1eb | 17063 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 17064 | BFD_RELOC_LO16, SP); |
6478892d TS |
17065 | } |
17066 | else | |
40fc1451 | 17067 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 17068 | |
aed1a261 | 17069 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 17070 | { |
df58fc94 | 17071 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
17072 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
17073 | BFD_RELOC_HI16_S); | |
17074 | ||
17075 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
17076 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
17077 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
17078 | ||
17079 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
17080 | mips_gp_register, reg1); | |
17081 | } | |
17082 | else | |
17083 | { | |
17084 | expressionS ex; | |
17085 | ||
17086 | ex.X_op = O_symbol; | |
4184909a | 17087 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
17088 | ex.X_op_symbol = NULL; |
17089 | ex.X_add_number = 0; | |
6e1304d8 | 17090 | |
aa6975fb ILT |
17091 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
17092 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
17093 | ||
17094 | macro_build_lui (&ex, mips_gp_register); | |
17095 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17096 | mips_gp_register, BFD_RELOC_LO16); | |
17097 | } | |
f21f8242 | 17098 | |
584892a6 | 17099 | macro_end (); |
6478892d | 17100 | |
8a75745d | 17101 | mips_assembling_insn = FALSE; |
6478892d TS |
17102 | demand_empty_rest_of_line (); |
17103 | } | |
17104 | ||
17105 | static void | |
17a2f251 | 17106 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 17107 | { |
919731af | 17108 | file_mips_check_options (); |
17109 | ||
6478892d | 17110 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 17111 | .cplocal is ignored. */ |
6478892d TS |
17112 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
17113 | { | |
17114 | s_ignore (0); | |
17115 | return; | |
17116 | } | |
17117 | ||
a276b80c MR |
17118 | if (mips_opts.mips16) |
17119 | { | |
17120 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
17121 | ignore_rest_of_line (); | |
17122 | return; | |
17123 | } | |
17124 | ||
6478892d | 17125 | mips_gp_register = tc_get_register (0); |
85b51719 | 17126 | demand_empty_rest_of_line (); |
6478892d TS |
17127 | } |
17128 | ||
252b5132 RH |
17129 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
17130 | offset from $sp. The offset is remembered, and after making a PIC | |
17131 | call $gp is restored from that location. */ | |
17132 | ||
17133 | static void | |
17a2f251 | 17134 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17135 | { |
17136 | expressionS ex; | |
252b5132 | 17137 | |
919731af | 17138 | file_mips_check_options (); |
17139 | ||
6478892d | 17140 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 17141 | .cprestore is ignored. */ |
6478892d | 17142 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
17143 | { |
17144 | s_ignore (0); | |
17145 | return; | |
17146 | } | |
17147 | ||
a276b80c MR |
17148 | if (mips_opts.mips16) |
17149 | { | |
17150 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
17151 | ignore_rest_of_line (); | |
17152 | return; | |
17153 | } | |
17154 | ||
252b5132 | 17155 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 17156 | mips_cprestore_valid = 1; |
252b5132 RH |
17157 | |
17158 | ex.X_op = O_constant; | |
17159 | ex.X_add_symbol = NULL; | |
17160 | ex.X_op_symbol = NULL; | |
17161 | ex.X_add_number = mips_cprestore_offset; | |
17162 | ||
8a75745d MR |
17163 | mips_mark_labels (); |
17164 | mips_assembling_insn = TRUE; | |
17165 | ||
584892a6 | 17166 | macro_start (); |
67c0d1eb RS |
17167 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
17168 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 17169 | macro_end (); |
252b5132 | 17170 | |
8a75745d | 17171 | mips_assembling_insn = FALSE; |
252b5132 RH |
17172 | demand_empty_rest_of_line (); |
17173 | } | |
17174 | ||
6478892d | 17175 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 17176 | was given in the preceding .cpsetup, it results in: |
6478892d | 17177 | ld $gp, offset($sp) |
76b3015f | 17178 | |
6478892d | 17179 | If a register $reg2 was given there, it results in: |
40fc1451 | 17180 | or $gp, $reg2, $0 */ |
54f4ddb3 | 17181 | |
6478892d | 17182 | static void |
17a2f251 | 17183 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17184 | { |
17185 | expressionS ex; | |
6478892d | 17186 | |
919731af | 17187 | file_mips_check_options (); |
17188 | ||
6478892d TS |
17189 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
17190 | We also need NewABI support. */ | |
17191 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17192 | { | |
17193 | s_ignore (0); | |
17194 | return; | |
17195 | } | |
17196 | ||
a276b80c MR |
17197 | if (mips_opts.mips16) |
17198 | { | |
17199 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
17200 | ignore_rest_of_line (); | |
17201 | return; | |
17202 | } | |
17203 | ||
8a75745d MR |
17204 | mips_mark_labels (); |
17205 | mips_assembling_insn = TRUE; | |
17206 | ||
584892a6 | 17207 | macro_start (); |
6478892d TS |
17208 | if (mips_cpreturn_register == -1) |
17209 | { | |
17210 | ex.X_op = O_constant; | |
17211 | ex.X_add_symbol = NULL; | |
17212 | ex.X_op_symbol = NULL; | |
17213 | ex.X_add_number = mips_cpreturn_offset; | |
17214 | ||
67c0d1eb | 17215 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
17216 | } |
17217 | else | |
40fc1451 SD |
17218 | move_register (mips_gp_register, mips_cpreturn_register); |
17219 | ||
584892a6 | 17220 | macro_end (); |
6478892d | 17221 | |
8a75745d | 17222 | mips_assembling_insn = FALSE; |
6478892d TS |
17223 | demand_empty_rest_of_line (); |
17224 | } | |
17225 | ||
d0f13682 CLT |
17226 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
17227 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
17228 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
17229 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
17230 | |
17231 | static void | |
d0f13682 CLT |
17232 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
17233 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
17234 | { |
17235 | expressionS ex; | |
17236 | char *p; | |
17237 | ||
17238 | expression (&ex); | |
17239 | ||
17240 | if (ex.X_op != O_symbol) | |
17241 | { | |
1661c76c | 17242 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
17243 | ignore_rest_of_line (); |
17244 | } | |
17245 | ||
17246 | p = frag_more (bytes); | |
17247 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17248 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17249 | demand_empty_rest_of_line (); |
de64cffd | 17250 | mips_clear_insn_labels (); |
741d6ea8 JM |
17251 | } |
17252 | ||
17253 | /* Handle .dtprelword. */ | |
17254 | ||
17255 | static void | |
17256 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17257 | { | |
d0f13682 | 17258 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17259 | } |
17260 | ||
17261 | /* Handle .dtpreldword. */ | |
17262 | ||
17263 | static void | |
17264 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17265 | { | |
d0f13682 CLT |
17266 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17267 | } | |
17268 | ||
17269 | /* Handle .tprelword. */ | |
17270 | ||
17271 | static void | |
17272 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17273 | { | |
17274 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17275 | } | |
17276 | ||
17277 | /* Handle .tpreldword. */ | |
17278 | ||
17279 | static void | |
17280 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17281 | { | |
17282 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17283 | } |
17284 | ||
6478892d TS |
17285 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17286 | code. It sets the offset to use in gp_rel relocations. */ | |
17287 | ||
17288 | static void | |
17a2f251 | 17289 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17290 | { |
17291 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17292 | We also need NewABI support. */ | |
17293 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17294 | { | |
17295 | s_ignore (0); | |
17296 | return; | |
17297 | } | |
17298 | ||
def2e0dd | 17299 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17300 | |
17301 | demand_empty_rest_of_line (); | |
17302 | } | |
17303 | ||
252b5132 RH |
17304 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17305 | code. It generates a 32 bit GP relative reloc. */ | |
17306 | ||
17307 | static void | |
17a2f251 | 17308 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17309 | { |
a8dbcb85 TS |
17310 | segment_info_type *si; |
17311 | struct insn_label_list *l; | |
252b5132 RH |
17312 | expressionS ex; |
17313 | char *p; | |
17314 | ||
17315 | /* When not generating PIC code, this is treated as .word. */ | |
17316 | if (mips_pic != SVR4_PIC) | |
17317 | { | |
17318 | s_cons (2); | |
17319 | return; | |
17320 | } | |
17321 | ||
a8dbcb85 TS |
17322 | si = seg_info (now_seg); |
17323 | l = si->label_list; | |
7d10b47d | 17324 | mips_emit_delays (); |
252b5132 | 17325 | if (auto_align) |
462427c4 | 17326 | mips_align (2, 0, l); |
252b5132 RH |
17327 | |
17328 | expression (&ex); | |
a1facbec | 17329 | mips_clear_insn_labels (); |
252b5132 RH |
17330 | |
17331 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17332 | { | |
1661c76c | 17333 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
17334 | ignore_rest_of_line (); |
17335 | } | |
17336 | ||
17337 | p = frag_more (4); | |
17a2f251 | 17338 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17339 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17340 | BFD_RELOC_GPREL32); |
252b5132 RH |
17341 | |
17342 | demand_empty_rest_of_line (); | |
17343 | } | |
17344 | ||
10181a0d | 17345 | static void |
17a2f251 | 17346 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17347 | { |
a8dbcb85 TS |
17348 | segment_info_type *si; |
17349 | struct insn_label_list *l; | |
10181a0d AO |
17350 | expressionS ex; |
17351 | char *p; | |
17352 | ||
17353 | /* When not generating PIC code, this is treated as .dword. */ | |
17354 | if (mips_pic != SVR4_PIC) | |
17355 | { | |
17356 | s_cons (3); | |
17357 | return; | |
17358 | } | |
17359 | ||
a8dbcb85 TS |
17360 | si = seg_info (now_seg); |
17361 | l = si->label_list; | |
7d10b47d | 17362 | mips_emit_delays (); |
10181a0d | 17363 | if (auto_align) |
462427c4 | 17364 | mips_align (3, 0, l); |
10181a0d AO |
17365 | |
17366 | expression (&ex); | |
a1facbec | 17367 | mips_clear_insn_labels (); |
10181a0d AO |
17368 | |
17369 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17370 | { | |
1661c76c | 17371 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
17372 | ignore_rest_of_line (); |
17373 | } | |
17374 | ||
17375 | p = frag_more (8); | |
17a2f251 | 17376 | md_number_to_chars (p, 0, 8); |
a105a300 | 17377 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17378 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17379 | |
17380 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17381 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17382 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17383 | |
17384 | demand_empty_rest_of_line (); | |
17385 | } | |
17386 | ||
a3f278e2 CM |
17387 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17388 | tables. It generates a R_MIPS_EH reloc. */ | |
17389 | ||
17390 | static void | |
17391 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17392 | { | |
17393 | expressionS ex; | |
17394 | char *p; | |
17395 | ||
17396 | mips_emit_delays (); | |
17397 | ||
17398 | expression (&ex); | |
17399 | mips_clear_insn_labels (); | |
17400 | ||
17401 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17402 | { | |
1661c76c | 17403 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
17404 | ignore_rest_of_line (); |
17405 | } | |
17406 | ||
17407 | p = frag_more (4); | |
17408 | md_number_to_chars (p, 0, 4); | |
17409 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 17410 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
17411 | |
17412 | demand_empty_rest_of_line (); | |
17413 | } | |
17414 | ||
252b5132 RH |
17415 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17416 | tables in SVR4 PIC code. */ | |
17417 | ||
17418 | static void | |
17a2f251 | 17419 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17420 | { |
252b5132 RH |
17421 | int reg; |
17422 | ||
919731af | 17423 | file_mips_check_options (); |
17424 | ||
10181a0d AO |
17425 | /* This is ignored when not generating SVR4 PIC code. */ |
17426 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17427 | { |
17428 | s_ignore (0); | |
17429 | return; | |
17430 | } | |
17431 | ||
8a75745d MR |
17432 | mips_mark_labels (); |
17433 | mips_assembling_insn = TRUE; | |
17434 | ||
252b5132 | 17435 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17436 | macro_start (); |
252b5132 | 17437 | reg = tc_get_register (0); |
67c0d1eb | 17438 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17439 | macro_end (); |
252b5132 | 17440 | |
8a75745d | 17441 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17442 | demand_empty_rest_of_line (); |
252b5132 RH |
17443 | } |
17444 | ||
17445 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17446 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17447 | such as generating jalx instructions when needed. We also make |
17448 | them odd for the duration of the assembly, in order to generate the | |
17449 | right sort of code. We will make them even in the adjust_symtab | |
17450 | routine, while leaving them marked. This is convenient for the | |
17451 | debugger and the disassembler. The linker knows to make them odd | |
17452 | again. */ | |
17453 | ||
17454 | static void | |
17a2f251 | 17455 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17456 | { |
7bb01e2d MR |
17457 | file_mips_check_options (); |
17458 | file_ase_mips16 |= mips_opts.mips16; | |
17459 | file_ase_micromips |= mips_opts.micromips; | |
17460 | ||
df58fc94 | 17461 | mips_mark_labels (); |
252b5132 RH |
17462 | |
17463 | demand_empty_rest_of_line (); | |
17464 | } | |
17465 | ||
ba92f887 MR |
17466 | /* Handle the .nan pseudo-op. */ |
17467 | ||
17468 | static void | |
17469 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17470 | { | |
17471 | static const char str_legacy[] = "legacy"; | |
17472 | static const char str_2008[] = "2008"; | |
17473 | size_t i; | |
17474 | ||
17475 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17476 | ||
17477 | if (i == sizeof (str_2008) - 1 | |
17478 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 17479 | mips_nan2008 = 1; |
ba92f887 MR |
17480 | else if (i == sizeof (str_legacy) - 1 |
17481 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
17482 | { |
17483 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
17484 | mips_nan2008 = 0; | |
17485 | else | |
17486 | as_bad (_("`%s' does not support legacy NaN"), | |
17487 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
17488 | } | |
ba92f887 | 17489 | else |
1661c76c | 17490 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
17491 | |
17492 | input_line_pointer += i; | |
17493 | demand_empty_rest_of_line (); | |
17494 | } | |
17495 | ||
754e2bb9 RS |
17496 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17497 | implemented in a transparent way, so that removing them would not | |
17498 | have any effect on the generated instructions. However, s_stab | |
17499 | internally changes the section, so in practice we need to decide | |
17500 | now whether the preceding label marks compressed code. We do not | |
17501 | support changing the compression mode of a label after a .stab* | |
17502 | directive, such as in: | |
17503 | ||
17504 | foo: | |
134c0c8b | 17505 | .stabs ... |
754e2bb9 RS |
17506 | .set mips16 |
17507 | ||
17508 | so the current mode wins. */ | |
252b5132 RH |
17509 | |
17510 | static void | |
17a2f251 | 17511 | s_mips_stab (int type) |
252b5132 | 17512 | { |
42c0794e | 17513 | file_mips_check_options (); |
754e2bb9 | 17514 | mips_mark_labels (); |
252b5132 RH |
17515 | s_stab (type); |
17516 | } | |
17517 | ||
54f4ddb3 | 17518 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17519 | |
17520 | static void | |
17a2f251 | 17521 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17522 | { |
17523 | char *name; | |
17524 | int c; | |
17525 | symbolS *symbolP; | |
17526 | expressionS exp; | |
17527 | ||
d02603dc | 17528 | c = get_symbol_name (&name); |
252b5132 RH |
17529 | symbolP = symbol_find_or_make (name); |
17530 | S_SET_WEAK (symbolP); | |
17531 | *input_line_pointer = c; | |
17532 | ||
d02603dc | 17533 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17534 | |
17535 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17536 | { | |
17537 | if (S_IS_DEFINED (symbolP)) | |
17538 | { | |
20203fb9 | 17539 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17540 | S_GET_NAME (symbolP)); |
17541 | ignore_rest_of_line (); | |
17542 | return; | |
17543 | } | |
bdaaa2e1 | 17544 | |
252b5132 RH |
17545 | if (*input_line_pointer == ',') |
17546 | { | |
17547 | ++input_line_pointer; | |
17548 | SKIP_WHITESPACE (); | |
17549 | } | |
bdaaa2e1 | 17550 | |
252b5132 RH |
17551 | expression (&exp); |
17552 | if (exp.X_op != O_symbol) | |
17553 | { | |
20203fb9 | 17554 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17555 | ignore_rest_of_line (); |
252b5132 RH |
17556 | return; |
17557 | } | |
49309057 | 17558 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17559 | } |
17560 | ||
17561 | demand_empty_rest_of_line (); | |
17562 | } | |
17563 | ||
17564 | /* Parse a register string into a number. Called from the ECOFF code | |
17565 | to parse .frame. The argument is non-zero if this is the frame | |
17566 | register, so that we can record it in mips_frame_reg. */ | |
17567 | ||
17568 | int | |
17a2f251 | 17569 | tc_get_register (int frame) |
252b5132 | 17570 | { |
707bfff6 | 17571 | unsigned int reg; |
252b5132 RH |
17572 | |
17573 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17574 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17575 | reg = 0; | |
252b5132 | 17576 | if (frame) |
7a621144 DJ |
17577 | { |
17578 | mips_frame_reg = reg != 0 ? reg : SP; | |
17579 | mips_frame_reg_valid = 1; | |
17580 | mips_cprestore_valid = 0; | |
17581 | } | |
252b5132 RH |
17582 | return reg; |
17583 | } | |
17584 | ||
17585 | valueT | |
17a2f251 | 17586 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17587 | { |
17588 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17589 | ||
f3ded42a RS |
17590 | /* We don't need to align ELF sections to the full alignment. |
17591 | However, Irix 5 may prefer that we align them at least to a 16 | |
17592 | byte boundary. We don't bother to align the sections if we | |
17593 | are targeted for an embedded system. */ | |
17594 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17595 | return addr; | |
17596 | if (align > 4) | |
17597 | align = 4; | |
252b5132 | 17598 | |
8d3842cd | 17599 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17600 | } |
17601 | ||
17602 | /* Utility routine, called from above as well. If called while the | |
17603 | input file is still being read, it's only an approximation. (For | |
17604 | example, a symbol may later become defined which appeared to be | |
17605 | undefined earlier.) */ | |
17606 | ||
17607 | static int | |
17a2f251 | 17608 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17609 | { |
17610 | if (sym == 0) | |
17611 | return 0; | |
17612 | ||
4d0d148d | 17613 | if (g_switch_value > 0) |
252b5132 RH |
17614 | { |
17615 | const char *symname; | |
17616 | int change; | |
17617 | ||
c9914766 | 17618 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17619 | register. It can be if it is smaller than the -G size or if |
17620 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17621 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17622 | they can. */ |
17623 | symname = S_GET_NAME (sym); | |
17624 | if (symname != (const char *) NULL | |
17625 | && (strcmp (symname, "eprol") == 0 | |
17626 | || strcmp (symname, "etext") == 0 | |
17627 | || strcmp (symname, "_gp") == 0 | |
17628 | || strcmp (symname, "edata") == 0 | |
17629 | || strcmp (symname, "_fbss") == 0 | |
17630 | || strcmp (symname, "_fdata") == 0 | |
17631 | || strcmp (symname, "_ftext") == 0 | |
17632 | || strcmp (symname, "end") == 0 | |
17633 | || strcmp (symname, "_gp_disp") == 0)) | |
17634 | change = 1; | |
17635 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17636 | && (0 | |
17637 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17638 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17639 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17640 | <= g_switch_value)) | |
252b5132 RH |
17641 | #endif |
17642 | /* We must defer this decision until after the whole | |
17643 | file has been read, since there might be a .extern | |
17644 | after the first use of this symbol. */ | |
17645 | || (before_relaxing | |
17646 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17647 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17648 | #endif |
17649 | && S_GET_VALUE (sym) == 0) | |
17650 | || (S_GET_VALUE (sym) != 0 | |
17651 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17652 | change = 0; | |
17653 | else | |
17654 | { | |
17655 | const char *segname; | |
17656 | ||
17657 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17658 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17659 | && strcmp (segname, ".lit4") != 0); |
17660 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17661 | && strcmp (segname, ".sbss") != 0 |
17662 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17663 | && strncmp (segname, ".sbss.", 6) != 0 |
17664 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17665 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17666 | } |
17667 | return change; | |
17668 | } | |
17669 | else | |
c9914766 | 17670 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17671 | return 1; |
17672 | } | |
17673 | ||
5919d012 RS |
17674 | |
17675 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17676 | ||
17677 | static bfd_boolean | |
9e009953 | 17678 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17679 | { |
17680 | asection *symsec; | |
5919d012 RS |
17681 | |
17682 | /* Handle the case of a symbol equated to another symbol. */ | |
17683 | while (symbol_equated_reloc_p (sym)) | |
17684 | { | |
17685 | symbolS *n; | |
17686 | ||
5f0fe04b | 17687 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17688 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17689 | if (n == sym) | |
17690 | break; | |
17691 | sym = n; | |
17692 | } | |
17693 | ||
df1f3cda DD |
17694 | if (symbol_section_p (sym)) |
17695 | return TRUE; | |
17696 | ||
5919d012 RS |
17697 | symsec = S_GET_SEGMENT (sym); |
17698 | ||
5919d012 | 17699 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17700 | return (!bfd_is_und_section (symsec) |
17701 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17702 | && !bfd_is_com_section (symsec) |
5919d012 | 17703 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17704 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17705 | } |
14f72d45 MR |
17706 | \f |
17707 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17708 | convert a section-relative value VAL to the equivalent PC-relative | |
17709 | value. */ | |
17710 | ||
17711 | static offsetT | |
17712 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17713 | offsetT val, long stretch) | |
17714 | { | |
17715 | fragS *sym_frag; | |
17716 | addressT addr; | |
17717 | ||
17718 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17719 | ||
17720 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17721 | ||
17722 | /* If the relax_marker of the symbol fragment differs from the | |
17723 | relax_marker of this fragment, we have not yet adjusted the | |
17724 | symbol fragment fr_address. We want to add in STRETCH in | |
17725 | order to get a better estimate of the address. This | |
17726 | particularly matters because of the shift bits. */ | |
17727 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17728 | { | |
17729 | fragS *f; | |
17730 | ||
17731 | /* Adjust stretch for any alignment frag. Note that if have | |
17732 | been expanding the earlier code, the symbol may be | |
17733 | defined in what appears to be an earlier frag. FIXME: | |
17734 | This doesn't handle the fr_subtype field, which specifies | |
17735 | a maximum number of bytes to skip when doing an | |
17736 | alignment. */ | |
17737 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17738 | { | |
17739 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17740 | { | |
17741 | if (stretch < 0) | |
17742 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17743 | else | |
17744 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17745 | if (stretch == 0) | |
17746 | break; | |
17747 | } | |
17748 | } | |
17749 | if (f != NULL) | |
17750 | val += stretch; | |
17751 | } | |
17752 | ||
17753 | addr = fragp->fr_address + fragp->fr_fix; | |
17754 | ||
17755 | /* The base address rules are complicated. The base address of | |
17756 | a branch is the following instruction. The base address of a | |
17757 | PC relative load or add is the instruction itself, but if it | |
17758 | is in a delay slot (in which case it can not be extended) use | |
17759 | the address of the instruction whose delay slot it is in. */ | |
17760 | if (pcrel_op->include_isa_bit) | |
17761 | { | |
17762 | addr += 2; | |
17763 | ||
17764 | /* If we are currently assuming that this frag should be | |
17765 | extended, then the current address is two bytes higher. */ | |
17766 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17767 | addr += 2; | |
17768 | ||
17769 | /* Ignore the low bit in the target, since it will be set | |
17770 | for a text label. */ | |
17771 | val &= -2; | |
17772 | } | |
17773 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17774 | addr -= 4; | |
17775 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17776 | addr -= 2; | |
5919d012 | 17777 | |
14f72d45 MR |
17778 | val -= addr & -(1 << pcrel_op->align_log2); |
17779 | ||
17780 | return val; | |
17781 | } | |
5919d012 | 17782 | |
252b5132 RH |
17783 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17784 | extended opcode. SEC is the section the frag is in. */ | |
17785 | ||
17786 | static int | |
17a2f251 | 17787 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17788 | { |
3ccad066 | 17789 | const struct mips_int_operand *operand; |
252b5132 | 17790 | offsetT val; |
252b5132 | 17791 | segT symsec; |
14f72d45 | 17792 | int type; |
252b5132 RH |
17793 | |
17794 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17795 | return 0; | |
17796 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17797 | return 1; | |
17798 | ||
88a7ef16 | 17799 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17800 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17801 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17802 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17803 | || (operand->root.type == OP_PCREL | |
17804 | ? sec != symsec | |
17805 | : !bfd_is_abs_section (symsec))) | |
17806 | return 1; | |
252b5132 | 17807 | |
88a7ef16 | 17808 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17809 | |
3ccad066 | 17810 | if (operand->root.type == OP_PCREL) |
252b5132 | 17811 | { |
3ccad066 | 17812 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17813 | offsetT maxtiny; |
252b5132 | 17814 | |
1425c41d | 17815 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17816 | return 1; |
252b5132 | 17817 | |
88a7ef16 | 17818 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17819 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17820 | |
17821 | /* If any of the shifted bits are set, we must use an extended | |
17822 | opcode. If the address depends on the size of this | |
17823 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17824 | use an extended opcode. */ |
17825 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17826 | { |
17827 | fragp->fr_subtype = | |
1425c41d | 17828 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17829 | return 1; |
17830 | } | |
17831 | ||
17832 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17833 | is precisely the next value above maxtiny, then there is a |
17834 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17835 | la $4,foo |
17836 | .skip 1020 | |
17837 | .align 2 | |
17838 | foo: | |
17839 | In this case when the la is extended, foo is 0x3fc bytes | |
17840 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17841 | the la must be extended. To avoid this loop, we mark the | |
17842 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17843 | extended with the next value above maxtiny. */ |
17844 | maxtiny = mips_int_operand_max (operand); | |
17845 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17846 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17847 | { |
17848 | fragp->fr_subtype = | |
1425c41d | 17849 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17850 | return 1; |
17851 | } | |
17852 | } | |
252b5132 | 17853 | |
3ccad066 | 17854 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17855 | } |
17856 | ||
8507b6e7 MR |
17857 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17858 | macro expansion. SEC is the section the frag is in. We only | |
17859 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17860 | non-PIC code using 32-bit addressing. */ | |
17861 | ||
17862 | static int | |
17863 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17864 | { | |
17865 | const struct mips_pcrel_operand *pcrel_op; | |
17866 | const struct mips_int_operand *operand; | |
17867 | offsetT val; | |
17868 | segT symsec; | |
17869 | int type; | |
17870 | ||
17871 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17872 | ||
17873 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17874 | return 0; | |
17875 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17876 | return 0; | |
17877 | ||
17878 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17879 | switch (type) | |
17880 | { | |
17881 | case 'A': | |
17882 | case 'B': | |
17883 | case 'E': | |
17884 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17885 | if (bfd_is_abs_section (symsec)) | |
17886 | return 1; | |
17887 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17888 | return 0; | |
17889 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17890 | return 1; | |
17891 | ||
17892 | operand = mips16_immed_operand (type, TRUE); | |
17893 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17894 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17895 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17896 | ||
17897 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17898 | ||
17899 | default: | |
17900 | return 0; | |
17901 | } | |
17902 | } | |
17903 | ||
4a6a3df4 AO |
17904 | /* Compute the length of a branch sequence, and adjust the |
17905 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17906 | worst-case length is computed, with UPDATE being used to indicate | |
17907 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17908 | branch is to be computed. */ | |
17909 | static int | |
17a2f251 | 17910 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17911 | { |
b34976b6 | 17912 | bfd_boolean toofar; |
4a6a3df4 AO |
17913 | int length; |
17914 | ||
17915 | if (fragp | |
17916 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17917 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17918 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17919 | { | |
17920 | addressT addr; | |
17921 | offsetT val; | |
17922 | ||
17923 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17924 | ||
17925 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17926 | ||
17927 | val -= addr; | |
17928 | ||
17929 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17930 | } | |
4a6a3df4 | 17931 | else |
c1f61bd2 MR |
17932 | /* If the symbol is not defined or it's in a different segment, |
17933 | we emit the long sequence. */ | |
b34976b6 | 17934 | toofar = TRUE; |
4a6a3df4 AO |
17935 | |
17936 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17937 | fragp->fr_subtype | |
66b3e8da | 17938 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17939 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17940 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17941 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17942 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17943 | toofar); | |
17944 | ||
17945 | length = 4; | |
17946 | if (toofar) | |
17947 | { | |
17948 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17949 | length += 8; | |
17950 | ||
ce8ad872 | 17951 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17952 | { |
17953 | /* Additional space for PIC loading of target address. */ | |
17954 | length += 8; | |
17955 | if (mips_opts.isa == ISA_MIPS1) | |
17956 | /* Additional space for $at-stabilizing nop. */ | |
17957 | length += 4; | |
17958 | } | |
17959 | ||
17960 | /* If branch is conditional. */ | |
17961 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17962 | length += 8; | |
17963 | } | |
b34976b6 | 17964 | |
4a6a3df4 AO |
17965 | return length; |
17966 | } | |
17967 | ||
7bd374a4 MR |
17968 | /* Get a FRAG's branch instruction delay slot size, either from the |
17969 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
17970 | or SHORT_INSN_SIZE otherwise. */ | |
17971 | ||
17972 | static int | |
17973 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
17974 | { | |
17975 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
17976 | ||
17977 | if (al) | |
17978 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
17979 | else | |
17980 | return short_insn_size; | |
17981 | } | |
17982 | ||
df58fc94 RS |
17983 | /* Compute the length of a branch sequence, and adjust the |
17984 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17985 | worst-case length is computed, with UPDATE being used to indicate | |
17986 | whether an unconditional (-1), or regular (0) branch is to be | |
17987 | computed. */ | |
17988 | ||
17989 | static int | |
17990 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17991 | { | |
7bd374a4 MR |
17992 | bfd_boolean insn32 = TRUE; |
17993 | bfd_boolean nods = TRUE; | |
ce8ad872 | 17994 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
17995 | bfd_boolean al = TRUE; |
17996 | int short_insn_size; | |
df58fc94 RS |
17997 | bfd_boolean toofar; |
17998 | int length; | |
17999 | ||
7bd374a4 MR |
18000 | if (fragp) |
18001 | { | |
18002 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
18003 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 18004 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
18005 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18006 | } | |
18007 | short_insn_size = insn32 ? 4 : 2; | |
18008 | ||
df58fc94 RS |
18009 | if (fragp |
18010 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 18011 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
18012 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
18013 | { | |
18014 | addressT addr; | |
18015 | offsetT val; | |
18016 | ||
18017 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
18018 | /* Ignore the low bit in the target, since it will be set | |
18019 | for a text label. */ | |
18020 | if ((val & 1) != 0) | |
18021 | --val; | |
18022 | ||
18023 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
18024 | ||
18025 | val -= addr; | |
18026 | ||
18027 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
18028 | } | |
df58fc94 | 18029 | else |
c1f61bd2 MR |
18030 | /* If the symbol is not defined or it's in a different segment, |
18031 | we emit the long sequence. */ | |
df58fc94 RS |
18032 | toofar = TRUE; |
18033 | ||
18034 | if (fragp && update | |
18035 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18036 | fragp->fr_subtype = (toofar | |
18037 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
18038 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
18039 | ||
18040 | length = 4; | |
18041 | if (toofar) | |
18042 | { | |
18043 | bfd_boolean compact_known = fragp != NULL; | |
18044 | bfd_boolean compact = FALSE; | |
18045 | bfd_boolean uncond; | |
18046 | ||
df58fc94 | 18047 | if (fragp) |
8484fb75 MR |
18048 | { |
18049 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
18050 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 18051 | } |
df58fc94 RS |
18052 | else |
18053 | uncond = update < 0; | |
18054 | ||
18055 | /* If label is out of range, we turn branch <br>: | |
18056 | ||
18057 | <br> label # 4 bytes | |
18058 | 0: | |
18059 | ||
18060 | into: | |
18061 | ||
18062 | j label # 4 bytes | |
8484fb75 MR |
18063 | nop # 2/4 bytes if |
18064 | # compact && (!PIC || insn32) | |
df58fc94 RS |
18065 | 0: |
18066 | */ | |
ce8ad872 | 18067 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 18068 | length += short_insn_size; |
df58fc94 RS |
18069 | |
18070 | /* If assembling PIC code, we further turn: | |
18071 | ||
18072 | j label # 4 bytes | |
18073 | ||
18074 | into: | |
18075 | ||
18076 | lw/ld at, %got(label)(gp) # 4 bytes | |
18077 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 18078 | jr/c at # 2/4 bytes |
df58fc94 | 18079 | */ |
ce8ad872 | 18080 | if (pic) |
8484fb75 | 18081 | length += 4 + short_insn_size; |
df58fc94 | 18082 | |
7bd374a4 MR |
18083 | /* Add an extra nop if the jump has no compact form and we need |
18084 | to fill the delay slot. */ | |
ce8ad872 | 18085 | if ((!pic || al) && nods) |
7bd374a4 MR |
18086 | length += (fragp |
18087 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
18088 | : short_insn_size); | |
18089 | ||
df58fc94 RS |
18090 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
18091 | ||
18092 | <brneg> 0f # 4 bytes | |
8484fb75 | 18093 | nop # 2/4 bytes if !compact |
df58fc94 RS |
18094 | */ |
18095 | if (!uncond) | |
8484fb75 | 18096 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 18097 | } |
7bd374a4 MR |
18098 | else if (nods) |
18099 | { | |
18100 | /* Add an extra nop to fill the delay slot. */ | |
18101 | gas_assert (fragp); | |
18102 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
18103 | } | |
df58fc94 RS |
18104 | |
18105 | return length; | |
18106 | } | |
18107 | ||
18108 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
18109 | bit accordingly. */ | |
18110 | ||
18111 | static int | |
18112 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
18113 | { | |
18114 | bfd_boolean toofar; | |
18115 | ||
df58fc94 RS |
18116 | if (fragp |
18117 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 18118 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
18119 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
18120 | { | |
18121 | addressT addr; | |
18122 | offsetT val; | |
18123 | int type; | |
18124 | ||
18125 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
18126 | /* Ignore the low bit in the target, since it will be set | |
18127 | for a text label. */ | |
18128 | if ((val & 1) != 0) | |
18129 | --val; | |
18130 | ||
18131 | /* Assume this is a 2-byte branch. */ | |
18132 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
18133 | ||
18134 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
18135 | long branches. */ | |
18136 | ||
18137 | val -= addr; | |
18138 | ||
18139 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
18140 | if (type == 'D') | |
18141 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
18142 | else if (type == 'E') | |
18143 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
18144 | else | |
18145 | abort (); | |
18146 | } | |
18147 | else | |
18148 | /* If the symbol is not defined or it's in a different segment, | |
18149 | we emit a normal 32-bit branch. */ | |
18150 | toofar = TRUE; | |
18151 | ||
18152 | if (fragp && update | |
18153 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18154 | fragp->fr_subtype | |
18155 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
18156 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
18157 | ||
18158 | if (toofar) | |
18159 | return 4; | |
18160 | ||
18161 | return 2; | |
18162 | } | |
18163 | ||
252b5132 RH |
18164 | /* Estimate the size of a frag before relaxing. Unless this is the |
18165 | mips16, we are not really relaxing here, and the final size is | |
18166 | encoded in the subtype information. For the mips16, we have to | |
18167 | decide whether we are using an extended opcode or not. */ | |
18168 | ||
252b5132 | 18169 | int |
17a2f251 | 18170 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 18171 | { |
5919d012 | 18172 | int change; |
252b5132 | 18173 | |
4a6a3df4 AO |
18174 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18175 | { | |
18176 | ||
b34976b6 AM |
18177 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
18178 | ||
4a6a3df4 AO |
18179 | return fragp->fr_var; |
18180 | } | |
18181 | ||
252b5132 | 18182 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
18183 | { |
18184 | /* We don't want to modify the EXTENDED bit here; it might get us | |
18185 | into infinite loops. We change it only in mips_relax_frag(). */ | |
18186 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
25499ac7 | 18187 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; |
8507b6e7 MR |
18188 | else |
18189 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
18190 | } | |
252b5132 | 18191 | |
df58fc94 RS |
18192 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18193 | { | |
18194 | int length = 4; | |
18195 | ||
18196 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18197 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
18198 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18199 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
18200 | fragp->fr_var = length; | |
18201 | ||
18202 | return length; | |
18203 | } | |
18204 | ||
ce8ad872 | 18205 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
18206 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
18207 | change = 0; | |
ce8ad872 MR |
18208 | else if (RELAX_PIC (fragp->fr_subtype)) |
18209 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 18210 | else |
ce8ad872 | 18211 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
18212 | |
18213 | if (change) | |
18214 | { | |
4d7206a2 | 18215 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 18216 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 18217 | } |
4d7206a2 RS |
18218 | else |
18219 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
18220 | } |
18221 | ||
18222 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 18223 | should be converted into a reloc against a section. */ |
252b5132 RH |
18224 | |
18225 | int | |
17a2f251 | 18226 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 18227 | { |
252b5132 RH |
18228 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
18229 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
18230 | return 0; | |
a161fe53 | 18231 | |
252b5132 RH |
18232 | if (fixp->fx_addsy == NULL) |
18233 | return 1; | |
a161fe53 | 18234 | |
2f0c68f2 CM |
18235 | /* Allow relocs used for EH tables. */ |
18236 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
18237 | return 1; | |
18238 | ||
de7e6852 RS |
18239 | /* If symbol SYM is in a mergeable section, relocations of the form |
18240 | SYM + 0 can usually be made section-relative. The mergeable data | |
18241 | is then identified by the section offset rather than by the symbol. | |
18242 | ||
18243 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 18244 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
18245 | need to recalculate the complete offset in order to correctly identify |
18246 | the merge data. | |
18247 | ||
33eaf5de | 18248 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
18249 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
18250 | placed anywhere. Rather than break backwards compatibility by changing | |
18251 | this, it seems better not to force the issue, and instead keep the | |
18252 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 18253 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 18254 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
18255 | && HAVE_IN_PLACE_ADDENDS |
18256 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
18257 | return 0; | |
18258 | ||
97f50151 MR |
18259 | /* There is no place to store an in-place offset for JALR relocations. */ |
18260 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
18261 | return 0; | |
18262 | ||
18263 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 18264 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
18265 | start address of the symbol's containing section. |
18266 | ||
18267 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
18268 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 18269 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 18270 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
18271 | return 0; |
18272 | ||
b314ec0e RS |
18273 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
18274 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
18275 | relocations against MIPS16 functions; in this case, the stub becomes | |
18276 | the function's canonical address. | |
18277 | ||
18278 | Floating-point stubs are stored in unique .mips16.call.* or | |
18279 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
18280 | the first relocation in section S must be against F; this is how the | |
18281 | linker determines the target function. All relocations that might | |
18282 | resolve to T must also be against F. We therefore have the following | |
18283 | restrictions, which are given in an intentionally-redundant way: | |
18284 | ||
18285 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
18286 | symbols. | |
18287 | ||
18288 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
18289 | if that stub might be used. | |
18290 | ||
18291 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
18292 | symbols. | |
18293 | ||
18294 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
18295 | that stub might be used. | |
18296 | ||
18297 | There is a further restriction: | |
18298 | ||
df58fc94 | 18299 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 18300 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
18301 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
18302 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
18303 | against MIPS16 or microMIPS symbols because we need to keep the | |
18304 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
18305 | detection and JAL or BAL to JALX instruction conversion in the |
18306 | linker. | |
b314ec0e | 18307 | |
df58fc94 | 18308 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 18309 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 18310 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
18311 | |
18312 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18313 | relocation against some symbol R, no relocation against R may be | |
18314 | reduced. (Note that this deals with (2) as well as (1) because | |
18315 | relocations against global symbols will never be reduced on ELF | |
18316 | targets.) This approach is a little simpler than trying to detect | |
18317 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18318 | that we have for MIPS16 symbols. */ | |
f3ded42a | 18319 | if (fixp->fx_subsy == NULL |
30c09090 | 18320 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 18321 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
18322 | && (jmp_reloc_p (fixp->fx_r_type) |
18323 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 18324 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 18325 | return 0; |
a161fe53 | 18326 | |
252b5132 RH |
18327 | return 1; |
18328 | } | |
18329 | ||
18330 | /* Translate internal representation of relocation info to BFD target | |
18331 | format. */ | |
18332 | ||
18333 | arelent ** | |
17a2f251 | 18334 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18335 | { |
18336 | static arelent *retval[4]; | |
18337 | arelent *reloc; | |
18338 | bfd_reloc_code_real_type code; | |
18339 | ||
4b0cff4e | 18340 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
18341 | reloc = retval[0] = XCNEW (arelent); |
18342 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 18343 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
18344 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18345 | ||
bad36eac DJ |
18346 | if (fixp->fx_pcrel) |
18347 | { | |
df58fc94 | 18348 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 18349 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
18350 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
18351 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 18352 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
18353 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
18354 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
18355 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
18356 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
18357 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
18358 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
18359 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
18360 | |
18361 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18362 | Relocations want only the symbol offset. */ | |
51f6035b MR |
18363 | switch (fixp->fx_r_type) |
18364 | { | |
18365 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
18366 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
18367 | break; | |
18368 | default: | |
18369 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
18370 | break; | |
18371 | } | |
bad36eac | 18372 | } |
17c6c9d9 MR |
18373 | else if (HAVE_IN_PLACE_ADDENDS |
18374 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
18375 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
18376 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
18377 | { | |
18378 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
18379 | addend accordingly. */ | |
18380 | reloc->addend = fixp->fx_addnumber >> 1; | |
18381 | } | |
bad36eac DJ |
18382 | else |
18383 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18384 | |
438c16b8 TS |
18385 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18386 | entry to be used in the relocation's section offset. */ | |
18387 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18388 | { |
18389 | reloc->address = reloc->addend; | |
18390 | reloc->addend = 0; | |
18391 | } | |
18392 | ||
252b5132 | 18393 | code = fixp->fx_r_type; |
252b5132 | 18394 | |
bad36eac | 18395 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18396 | if (reloc->howto == NULL) |
18397 | { | |
18398 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
18399 | _("cannot represent %s relocation in this object file" |
18400 | " format"), | |
252b5132 RH |
18401 | bfd_get_reloc_code_name (code)); |
18402 | retval[0] = NULL; | |
18403 | } | |
18404 | ||
18405 | return retval; | |
18406 | } | |
18407 | ||
18408 | /* Relax a machine dependent frag. This returns the amount by which | |
18409 | the current size of the frag should change. */ | |
18410 | ||
18411 | int | |
17a2f251 | 18412 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18413 | { |
4a6a3df4 AO |
18414 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18415 | { | |
18416 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18417 | |
18418 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18419 | |
18420 | return fragp->fr_var - old_var; | |
18421 | } | |
18422 | ||
df58fc94 RS |
18423 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18424 | { | |
18425 | offsetT old_var = fragp->fr_var; | |
18426 | offsetT new_var = 4; | |
18427 | ||
18428 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18429 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18430 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18431 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18432 | fragp->fr_var = new_var; | |
18433 | ||
18434 | return new_var - old_var; | |
18435 | } | |
18436 | ||
252b5132 RH |
18437 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18438 | return 0; | |
18439 | ||
8507b6e7 | 18440 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 18441 | { |
8507b6e7 MR |
18442 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
18443 | { | |
18444 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
25499ac7 | 18445 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; |
8507b6e7 MR |
18446 | } |
18447 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18448 | { | |
18449 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18450 | return -2; | |
18451 | } | |
18452 | else | |
18453 | return 0; | |
18454 | } | |
18455 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
18456 | { | |
18457 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
18458 | { | |
18459 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
18460 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
25499ac7 | 18461 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; |
8507b6e7 MR |
18462 | } |
18463 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18464 | { | |
18465 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18466 | return 2; | |
18467 | } | |
18468 | else | |
252b5132 | 18469 | return 0; |
252b5132 RH |
18470 | } |
18471 | else | |
18472 | { | |
8507b6e7 | 18473 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 18474 | return 0; |
8507b6e7 MR |
18475 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
18476 | { | |
18477 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18478 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18479 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; |
8507b6e7 MR |
18480 | } |
18481 | else | |
18482 | { | |
18483 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18484 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; |
8507b6e7 | 18485 | } |
252b5132 RH |
18486 | } |
18487 | ||
18488 | return 0; | |
18489 | } | |
18490 | ||
18491 | /* Convert a machine dependent frag. */ | |
18492 | ||
18493 | void | |
17a2f251 | 18494 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18495 | { |
4a6a3df4 AO |
18496 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18497 | { | |
4d68580a | 18498 | char *buf; |
4a6a3df4 | 18499 | unsigned long insn; |
4a6a3df4 | 18500 | fixS *fixp; |
b34976b6 | 18501 | |
4d68580a RS |
18502 | buf = fragp->fr_literal + fragp->fr_fix; |
18503 | insn = read_insn (buf); | |
b34976b6 | 18504 | |
4a6a3df4 AO |
18505 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18506 | { | |
18507 | /* We generate a fixup instead of applying it right now | |
18508 | because, if there are linker relaxations, we're going to | |
18509 | need the relocations. */ | |
bbd27b76 MR |
18510 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18511 | fragp->fr_symbol, fragp->fr_offset, | |
18512 | TRUE, BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18513 | fixp->fx_file = fragp->fr_file; |
18514 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18515 | |
4d68580a | 18516 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18517 | } |
18518 | else | |
18519 | { | |
18520 | int i; | |
18521 | ||
18522 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18523 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18524 | |
18525 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18526 | goto uncond; | |
18527 | ||
18528 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18529 | { | |
18530 | /* Reverse the branch. */ | |
18531 | switch ((insn >> 28) & 0xf) | |
18532 | { | |
18533 | case 4: | |
56d438b1 CF |
18534 | if ((insn & 0xff000000) == 0x47000000 |
18535 | || (insn & 0xff600000) == 0x45600000) | |
18536 | { | |
18537 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18538 | reversed by tweaking bit 23. */ | |
18539 | insn ^= 0x00800000; | |
18540 | } | |
18541 | else | |
18542 | { | |
18543 | /* bc[0-3][tf]l? instructions can have the condition | |
18544 | reversed by tweaking a single TF bit, and their | |
18545 | opcodes all have 0x4???????. */ | |
18546 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18547 | insn ^= 0x00010000; | |
18548 | } | |
4a6a3df4 AO |
18549 | break; |
18550 | ||
18551 | case 0: | |
18552 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18553 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18554 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18555 | insn ^= 0x00010000; |
18556 | break; | |
b34976b6 | 18557 | |
4a6a3df4 AO |
18558 | case 1: |
18559 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18560 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18561 | insn ^= 0x04000000; |
18562 | break; | |
18563 | ||
18564 | default: | |
18565 | abort (); | |
18566 | } | |
18567 | } | |
18568 | ||
18569 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18570 | { | |
18571 | /* Clear the and-link bit. */ | |
9c2799c2 | 18572 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18573 | |
54f4ddb3 TS |
18574 | /* bltzal 0x04100000 bgezal 0x04110000 |
18575 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18576 | insn &= ~0x00100000; |
18577 | } | |
18578 | ||
18579 | /* Branch over the branch (if the branch was likely) or the | |
18580 | full jump (not likely case). Compute the offset from the | |
18581 | current instruction to branch to. */ | |
18582 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18583 | i = 16; | |
18584 | else | |
18585 | { | |
18586 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18587 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18588 | /* How many bytes in instructions from here to the end? */ |
18589 | i = fragp->fr_var - i; | |
18590 | } | |
18591 | /* Convert to instruction count. */ | |
18592 | i >>= 2; | |
18593 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18594 | i--; |
4a6a3df4 AO |
18595 | insn |= i; |
18596 | /* Branch over the jump. */ | |
4d68580a | 18597 | buf = write_insn (buf, insn); |
4a6a3df4 | 18598 | |
54f4ddb3 | 18599 | /* nop */ |
4d68580a | 18600 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18601 | |
18602 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18603 | { | |
18604 | /* beql $0, $0, 2f */ | |
18605 | insn = 0x50000000; | |
18606 | /* Compute the PC offset from the current instruction to | |
18607 | the end of the variable frag. */ | |
18608 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18609 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18610 | /* How many bytes in instructions from here to the end? */ |
18611 | i = fragp->fr_var - i; | |
18612 | /* Convert to instruction count. */ | |
18613 | i >>= 2; | |
18614 | /* Don't decrement i, because we want to branch over the | |
18615 | delay slot. */ | |
4a6a3df4 | 18616 | insn |= i; |
4a6a3df4 | 18617 | |
4d68580a RS |
18618 | buf = write_insn (buf, insn); |
18619 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18620 | } |
18621 | ||
18622 | uncond: | |
ce8ad872 | 18623 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18624 | { |
18625 | /* j or jal. */ | |
18626 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18627 | ? 0x0c000000 : 0x08000000); | |
4a6a3df4 | 18628 | |
bbd27b76 MR |
18629 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18630 | fragp->fr_symbol, fragp->fr_offset, | |
18631 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18632 | fixp->fx_file = fragp->fr_file; |
18633 | fixp->fx_line = fragp->fr_line; | |
18634 | ||
4d68580a | 18635 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18636 | } |
18637 | else | |
18638 | { | |
66b3e8da MR |
18639 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18640 | ||
4a6a3df4 | 18641 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18642 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18643 | insn |= at << OP_SH_RT; | |
4a6a3df4 | 18644 | |
bbd27b76 MR |
18645 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18646 | fragp->fr_symbol, fragp->fr_offset, | |
18647 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18648 | fixp->fx_file = fragp->fr_file; |
18649 | fixp->fx_line = fragp->fr_line; | |
18650 | ||
4d68580a | 18651 | buf = write_insn (buf, insn); |
b34976b6 | 18652 | |
4a6a3df4 | 18653 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18654 | /* nop */ |
18655 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18656 | |
18657 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18658 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18659 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18660 | |
bbd27b76 MR |
18661 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18662 | fragp->fr_symbol, fragp->fr_offset, | |
18663 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18664 | fixp->fx_file = fragp->fr_file; |
18665 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18666 | |
4d68580a | 18667 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18668 | |
18669 | /* j(al)r $at. */ | |
18670 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18671 | insn = 0x0000f809; |
4a6a3df4 | 18672 | else |
66b3e8da MR |
18673 | insn = 0x00000008; |
18674 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18675 | |
4d68580a | 18676 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18677 | } |
18678 | } | |
18679 | ||
4a6a3df4 | 18680 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18681 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18682 | return; |
18683 | } | |
18684 | ||
df58fc94 RS |
18685 | /* Relax microMIPS branches. */ |
18686 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18687 | { | |
4d68580a | 18688 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18689 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18690 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18691 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18692 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18693 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18694 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18695 | bfd_boolean short_ds; |
df58fc94 | 18696 | unsigned long insn; |
df58fc94 RS |
18697 | fixS *fixp; |
18698 | ||
df58fc94 RS |
18699 | fragp->fr_fix += fragp->fr_var; |
18700 | ||
18701 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18702 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18703 | { | |
18704 | /* We generate a fixup instead of applying it right now, | |
18705 | because if there is linker relaxation, we're going to | |
18706 | need the relocations. */ | |
834a65aa MR |
18707 | switch (type) |
18708 | { | |
18709 | case 'D': | |
18710 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18711 | fragp->fr_symbol, fragp->fr_offset, | |
18712 | TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
18713 | break; | |
18714 | case 'E': | |
18715 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18716 | fragp->fr_symbol, fragp->fr_offset, | |
18717 | TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
18718 | break; | |
18719 | default: | |
18720 | abort (); | |
18721 | } | |
df58fc94 RS |
18722 | |
18723 | fixp->fx_file = fragp->fr_file; | |
18724 | fixp->fx_line = fragp->fr_line; | |
18725 | ||
18726 | /* These relocations can have an addend that won't fit in | |
18727 | 2 octets. */ | |
18728 | fixp->fx_no_overflow = 1; | |
18729 | ||
18730 | return; | |
18731 | } | |
18732 | ||
2309ddf2 | 18733 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18734 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18735 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18736 | { | |
18737 | /* We generate a fixup instead of applying it right now, | |
18738 | because if there is linker relaxation, we're going to | |
18739 | need the relocations. */ | |
bbd27b76 MR |
18740 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18741 | fragp->fr_symbol, fragp->fr_offset, | |
18742 | TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18743 | fixp->fx_file = fragp->fr_file; |
18744 | fixp->fx_line = fragp->fr_line; | |
18745 | ||
18746 | if (type == 0) | |
7bd374a4 MR |
18747 | { |
18748 | insn = read_compressed_insn (buf, 4); | |
18749 | buf += 4; | |
18750 | ||
18751 | if (nods) | |
18752 | { | |
18753 | /* Check the short-delay-slot bit. */ | |
18754 | if (!al || (insn & 0x02000000) != 0) | |
18755 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18756 | else | |
18757 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18758 | } | |
18759 | ||
18760 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18761 | return; | |
18762 | } | |
df58fc94 RS |
18763 | } |
18764 | ||
18765 | /* Relax 16-bit branches to 32-bit branches. */ | |
18766 | if (type != 0) | |
18767 | { | |
4d68580a | 18768 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18769 | |
18770 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18771 | insn = 0x94000000; /* beq */ | |
18772 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18773 | { | |
18774 | unsigned long regno; | |
18775 | ||
18776 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18777 | regno = micromips_to_32_reg_d_map [regno]; | |
18778 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18779 | insn |= regno << MICROMIPSOP_SH_RS; | |
18780 | } | |
18781 | else | |
18782 | abort (); | |
18783 | ||
18784 | /* Nothing else to do, just write it out. */ | |
18785 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18786 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18787 | { | |
4d68580a | 18788 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18789 | if (nods) |
18790 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18791 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18792 | return; |
18793 | } | |
18794 | } | |
18795 | else | |
4d68580a | 18796 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18797 | |
18798 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18799 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18800 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18801 | |
2309ddf2 | 18802 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18803 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18804 | |
18805 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18806 | { | |
18807 | symbolS *l; | |
18808 | ||
18809 | /* Reverse the branch. */ | |
18810 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18811 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18812 | insn ^= 0x20000000; | |
18813 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18814 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18815 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18816 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18817 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18818 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18819 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18820 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18821 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18822 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18823 | insn ^= 0x00400000; | |
18824 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18825 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18826 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18827 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18828 | insn ^= 0x00200000; | |
56d438b1 CF |
18829 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18830 | BNZ.df */ | |
18831 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18832 | BNZ.V */ | |
18833 | insn ^= 0x00800000; | |
df58fc94 RS |
18834 | else |
18835 | abort (); | |
18836 | ||
18837 | if (al) | |
18838 | { | |
18839 | /* Clear the and-link and short-delay-slot bits. */ | |
18840 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18841 | ||
18842 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18843 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18844 | insn &= ~0x02200000; | |
18845 | } | |
18846 | ||
18847 | /* Make a label at the end for use with the branch. */ | |
18848 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18849 | micromips_label_inc (); | |
f3ded42a | 18850 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18851 | |
18852 | /* Refer to it. */ | |
4d68580a RS |
18853 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18854 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18855 | fixp->fx_file = fragp->fr_file; |
18856 | fixp->fx_line = fragp->fr_line; | |
18857 | ||
18858 | /* Branch over the jump. */ | |
4d68580a | 18859 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18860 | |
df58fc94 | 18861 | if (!compact) |
8484fb75 MR |
18862 | { |
18863 | /* nop */ | |
18864 | if (insn32) | |
18865 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18866 | else | |
18867 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18868 | } | |
df58fc94 RS |
18869 | } |
18870 | ||
ce8ad872 | 18871 | if (!pic) |
df58fc94 | 18872 | { |
7bd374a4 MR |
18873 | unsigned long jal = (short_ds || nods |
18874 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18875 | |
df58fc94 RS |
18876 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18877 | insn = al ? jal : 0xd4000000; | |
18878 | ||
bbd27b76 MR |
18879 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18880 | fragp->fr_symbol, fragp->fr_offset, | |
18881 | FALSE, BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18882 | fixp->fx_file = fragp->fr_file; |
18883 | fixp->fx_line = fragp->fr_line; | |
18884 | ||
4d68580a | 18885 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18886 | |
7bd374a4 | 18887 | if (compact || nods) |
8484fb75 MR |
18888 | { |
18889 | /* nop */ | |
18890 | if (insn32) | |
18891 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18892 | else | |
18893 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18894 | } | |
df58fc94 RS |
18895 | } |
18896 | else | |
18897 | { | |
18898 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18899 | ||
18900 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18901 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18902 | insn |= at << MICROMIPSOP_SH_RT; | |
18903 | ||
bbd27b76 MR |
18904 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18905 | fragp->fr_symbol, fragp->fr_offset, | |
18906 | FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18907 | fixp->fx_file = fragp->fr_file; |
18908 | fixp->fx_line = fragp->fr_line; | |
18909 | ||
4d68580a | 18910 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18911 | |
18912 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18913 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18914 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18915 | ||
bbd27b76 MR |
18916 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18917 | fragp->fr_symbol, fragp->fr_offset, | |
18918 | FALSE, BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18919 | fixp->fx_file = fragp->fr_file; |
18920 | fixp->fx_line = fragp->fr_line; | |
18921 | ||
4d68580a | 18922 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18923 | |
8484fb75 MR |
18924 | if (insn32) |
18925 | { | |
18926 | /* jr/jalr $at */ | |
18927 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18928 | insn |= at << MICROMIPSOP_SH_RS; | |
18929 | ||
18930 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18931 | |
7bd374a4 | 18932 | if (compact || nods) |
8484fb75 MR |
18933 | /* nop */ |
18934 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18935 | } | |
18936 | else | |
18937 | { | |
18938 | /* jr/jrc/jalr/jalrs $at */ | |
18939 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18940 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18941 | |
18942 | insn = al ? jalr : jr; | |
18943 | insn |= at << MICROMIPSOP_SH_MJ; | |
18944 | ||
18945 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18946 | if (al && nods) |
18947 | { | |
18948 | /* nop */ | |
18949 | if (short_ds) | |
18950 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18951 | else | |
18952 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18953 | } | |
8484fb75 | 18954 | } |
df58fc94 RS |
18955 | } |
18956 | ||
4d68580a | 18957 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18958 | return; |
18959 | } | |
18960 | ||
252b5132 RH |
18961 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18962 | { | |
18963 | int type; | |
3ccad066 | 18964 | const struct mips_int_operand *operand; |
252b5132 | 18965 | offsetT val; |
5c04167a | 18966 | char *buf; |
8507b6e7 | 18967 | unsigned int user_length; |
9d862524 | 18968 | bfd_boolean need_reloc; |
252b5132 | 18969 | unsigned long insn; |
8507b6e7 | 18970 | bfd_boolean mac; |
5c04167a | 18971 | bfd_boolean ext; |
88a7ef16 | 18972 | segT symsec; |
252b5132 RH |
18973 | |
18974 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 18975 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 18976 | |
8507b6e7 | 18977 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 18978 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 18979 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
18980 | |
18981 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
18982 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 18983 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
18984 | ? asec != symsec |
18985 | : !bfd_is_abs_section (symsec))); | |
18986 | ||
8507b6e7 | 18987 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 18988 | { |
3ccad066 | 18989 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 18990 | |
3ccad066 | 18991 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 18992 | |
14f72d45 | 18993 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 18994 | { |
37b2d327 MR |
18995 | if (!mips_ignore_branch_isa |
18996 | && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) | |
14f72d45 MR |
18997 | as_bad_where (fragp->fr_file, fragp->fr_line, |
18998 | _("branch to a symbol in another ISA mode")); | |
18999 | else if ((fragp->fr_offset & 0x1) != 0) | |
19000 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19001 | _("branch to misaligned address (0x%lx)"), | |
19002 | (long) val); | |
252b5132 | 19003 | } |
252b5132 | 19004 | |
14f72d45 | 19005 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
19006 | |
19007 | /* Make sure the section winds up with the alignment we have | |
19008 | assumed. */ | |
3ccad066 RS |
19009 | if (operand->shift > 0) |
19010 | record_alignment (asec, operand->shift); | |
252b5132 RH |
19011 | } |
19012 | ||
8507b6e7 MR |
19013 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
19014 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
19015 | { | |
19016 | if (mac) | |
19017 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
19018 | _("macro instruction expanded into multiple " | |
19019 | "instructions in a branch delay slot")); | |
19020 | else if (ext) | |
19021 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
19022 | _("extended instruction in a branch delay slot")); | |
19023 | } | |
19024 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 19025 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
19026 | _("macro instruction expanded into multiple " |
19027 | "instructions")); | |
252b5132 | 19028 | |
5c04167a | 19029 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 19030 | |
4d68580a | 19031 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
19032 | if (ext) |
19033 | insn |= MIPS16_EXTEND; | |
252b5132 | 19034 | |
5c04167a RS |
19035 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
19036 | user_length = 4; | |
19037 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
19038 | user_length = 2; | |
19039 | else | |
19040 | user_length = 0; | |
19041 | ||
8507b6e7 | 19042 | if (mac) |
c9775dde | 19043 | { |
8507b6e7 MR |
19044 | unsigned long reg; |
19045 | unsigned long new; | |
19046 | unsigned long op; | |
25499ac7 | 19047 | bfd_boolean e2; |
8507b6e7 MR |
19048 | |
19049 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
19050 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 19051 | |
25499ac7 MR |
19052 | e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); |
19053 | ||
8507b6e7 | 19054 | if (need_reloc) |
c9775dde | 19055 | { |
8507b6e7 MR |
19056 | fixS *fixp; |
19057 | ||
19058 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
19059 | ||
19060 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
19061 | fragp->fr_symbol, fragp->fr_offset, | |
19062 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
19063 | fixp->fx_file = fragp->fr_file; | |
19064 | fixp->fx_line = fragp->fr_line; | |
19065 | ||
25499ac7 | 19066 | fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, |
8507b6e7 MR |
19067 | fragp->fr_symbol, fragp->fr_offset, |
19068 | FALSE, BFD_RELOC_MIPS16_LO16); | |
19069 | fixp->fx_file = fragp->fr_file; | |
19070 | fixp->fx_line = fragp->fr_line; | |
19071 | ||
19072 | val = 0; | |
19073 | } | |
19074 | ||
19075 | switch (insn & 0xf800) | |
19076 | { | |
19077 | case 0x0800: /* ADDIU */ | |
19078 | reg = (insn >> 8) & 0x7; | |
19079 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 19080 | break; |
8507b6e7 MR |
19081 | case 0xb000: /* LW */ |
19082 | reg = (insn >> 8) & 0x7; | |
19083 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 19084 | break; |
8507b6e7 MR |
19085 | case 0xf800: /* I64 */ |
19086 | reg = (insn >> 5) & 0x7; | |
19087 | switch (insn & 0x0700) | |
19088 | { | |
19089 | case 0x0400: /* LD */ | |
19090 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
19091 | break; | |
19092 | case 0x0600: /* DADDIU */ | |
19093 | op = 0xf000fd00 | (reg << 5); | |
19094 | break; | |
19095 | default: | |
19096 | abort (); | |
19097 | } | |
19098 | break; | |
19099 | default: | |
19100 | abort (); | |
c9775dde | 19101 | } |
8507b6e7 | 19102 | |
25499ac7 | 19103 | new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ |
8507b6e7 MR |
19104 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); |
19105 | buf = write_compressed_insn (buf, new, 4); | |
25499ac7 MR |
19106 | if (!e2) |
19107 | { | |
19108 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
19109 | buf = write_compressed_insn (buf, new, 4); | |
19110 | } | |
8507b6e7 MR |
19111 | op |= mips16_immed_extend (val, 16); |
19112 | buf = write_compressed_insn (buf, op, 4); | |
19113 | ||
25499ac7 | 19114 | fragp->fr_fix += e2 ? 8 : 12; |
8507b6e7 MR |
19115 | } |
19116 | else | |
19117 | { | |
19118 | unsigned int length = ext ? 4 : 2; | |
19119 | ||
19120 | if (need_reloc) | |
c9775dde | 19121 | { |
8507b6e7 | 19122 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
8507b6e7 | 19123 | fixS *fixp; |
c9775dde | 19124 | |
8507b6e7 MR |
19125 | switch (type) |
19126 | { | |
19127 | case 'p': | |
19128 | case 'q': | |
19129 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
19130 | break; | |
19131 | default: | |
19132 | break; | |
19133 | } | |
19134 | if (mac || reloc == BFD_RELOC_NONE) | |
19135 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19136 | _("unsupported relocation")); | |
19137 | else if (ext) | |
19138 | { | |
bbd27b76 MR |
19139 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
19140 | fragp->fr_symbol, fragp->fr_offset, | |
19141 | TRUE, reloc); | |
8507b6e7 MR |
19142 | fixp->fx_file = fragp->fr_file; |
19143 | fixp->fx_line = fragp->fr_line; | |
19144 | } | |
19145 | else | |
19146 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19147 | _("invalid unextended operand value")); | |
c9775dde | 19148 | } |
eefc3365 | 19149 | else |
8507b6e7 MR |
19150 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
19151 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 19152 | |
8507b6e7 MR |
19153 | gas_assert (mips16_opcode_length (insn) == length); |
19154 | write_compressed_insn (buf, insn, length); | |
19155 | fragp->fr_fix += length; | |
19156 | } | |
252b5132 RH |
19157 | } |
19158 | else | |
19159 | { | |
df58fc94 RS |
19160 | relax_substateT subtype = fragp->fr_subtype; |
19161 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
19162 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
871a6bd2 | 19163 | unsigned int first, second; |
4d7206a2 | 19164 | fixS *fixp; |
252b5132 | 19165 | |
df58fc94 RS |
19166 | first = RELAX_FIRST (subtype); |
19167 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 19168 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 19169 | |
df58fc94 RS |
19170 | /* If the delay slot chosen does not match the size of the instruction, |
19171 | then emit a warning. */ | |
19172 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
19173 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
19174 | { | |
19175 | relax_substateT s; | |
19176 | const char *msg; | |
19177 | ||
19178 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
19179 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
19180 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
19181 | msg = macro_warning (s); | |
19182 | if (msg != NULL) | |
db9b2be4 | 19183 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
19184 | subtype &= ~s; |
19185 | } | |
19186 | ||
584892a6 | 19187 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 19188 | if (use_second == second_longer) |
584892a6 | 19189 | { |
df58fc94 RS |
19190 | relax_substateT s; |
19191 | const char *msg; | |
19192 | ||
19193 | s = (subtype | |
19194 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
19195 | msg = macro_warning (s); | |
19196 | if (msg != NULL) | |
db9b2be4 | 19197 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 19198 | subtype &= ~s; |
584892a6 RS |
19199 | } |
19200 | ||
4d7206a2 RS |
19201 | /* Go through all the fixups for the first sequence. Disable them |
19202 | (by marking them as done) if we're going to use the second | |
19203 | sequence instead. */ | |
19204 | while (fixp | |
19205 | && fixp->fx_frag == fragp | |
90bd3c90 | 19206 | && fixp->fx_where + second < fragp->fr_fix) |
4d7206a2 | 19207 | { |
df58fc94 | 19208 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19209 | fixp->fx_done = 1; |
19210 | fixp = fixp->fx_next; | |
19211 | } | |
252b5132 | 19212 | |
4d7206a2 RS |
19213 | /* Go through the fixups for the second sequence. Disable them if |
19214 | we're going to use the first sequence, otherwise adjust their | |
19215 | addresses to account for the relaxation. */ | |
19216 | while (fixp && fixp->fx_frag == fragp) | |
19217 | { | |
df58fc94 | 19218 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19219 | fixp->fx_where -= first; |
19220 | else | |
19221 | fixp->fx_done = 1; | |
19222 | fixp = fixp->fx_next; | |
19223 | } | |
19224 | ||
19225 | /* Now modify the frag contents. */ | |
df58fc94 | 19226 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19227 | { |
19228 | char *start; | |
19229 | ||
19230 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
19231 | memmove (start, start + first, second); | |
19232 | fragp->fr_fix -= first; | |
19233 | } | |
19234 | else | |
19235 | fragp->fr_fix -= second; | |
252b5132 RH |
19236 | } |
19237 | } | |
19238 | ||
252b5132 RH |
19239 | /* This function is called after the relocs have been generated. |
19240 | We've been storing mips16 text labels as odd. Here we convert them | |
19241 | back to even for the convenience of the debugger. */ | |
19242 | ||
19243 | void | |
17a2f251 | 19244 | mips_frob_file_after_relocs (void) |
252b5132 RH |
19245 | { |
19246 | asymbol **syms; | |
19247 | unsigned int count, i; | |
19248 | ||
252b5132 RH |
19249 | syms = bfd_get_outsymbols (stdoutput); |
19250 | count = bfd_get_symcount (stdoutput); | |
19251 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
19252 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
19253 | && ((*syms)->value & 1) != 0) | |
19254 | { | |
19255 | (*syms)->value &= ~1; | |
19256 | /* If the symbol has an odd size, it was probably computed | |
19257 | incorrectly, so adjust that as well. */ | |
19258 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
19259 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
19260 | } | |
252b5132 RH |
19261 | } |
19262 | ||
a1facbec MR |
19263 | /* This function is called whenever a label is defined, including fake |
19264 | labels instantiated off the dot special symbol. It is used when | |
19265 | handling branch delays; if a branch has a label, we assume we cannot | |
19266 | move it. This also bumps the value of the symbol by 1 in compressed | |
19267 | code. */ | |
252b5132 | 19268 | |
e1b47bd5 | 19269 | static void |
a1facbec | 19270 | mips_record_label (symbolS *sym) |
252b5132 | 19271 | { |
a8dbcb85 | 19272 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
19273 | struct insn_label_list *l; |
19274 | ||
19275 | if (free_insn_labels == NULL) | |
325801bd | 19276 | l = XNEW (struct insn_label_list); |
252b5132 RH |
19277 | else |
19278 | { | |
19279 | l = free_insn_labels; | |
19280 | free_insn_labels = l->next; | |
19281 | } | |
19282 | ||
19283 | l->label = sym; | |
a8dbcb85 TS |
19284 | l->next = si->label_list; |
19285 | si->label_list = l; | |
a1facbec | 19286 | } |
07a53e5c | 19287 | |
a1facbec MR |
19288 | /* This function is called as tc_frob_label() whenever a label is defined |
19289 | and adds a DWARF-2 record we only want for true labels. */ | |
19290 | ||
19291 | void | |
19292 | mips_define_label (symbolS *sym) | |
19293 | { | |
19294 | mips_record_label (sym); | |
07a53e5c | 19295 | dwarf2_emit_label (sym); |
252b5132 | 19296 | } |
e1b47bd5 RS |
19297 | |
19298 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
19299 | is defined. */ | |
19300 | ||
19301 | void | |
19302 | mips_add_dot_label (symbolS *sym) | |
19303 | { | |
19304 | mips_record_label (sym); | |
19305 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
19306 | mips_compressed_mark_label (sym); | |
19307 | } | |
252b5132 | 19308 | \f |
351cdf24 MF |
19309 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
19310 | static unsigned int | |
19311 | mips_convert_ase_flags (int ase) | |
19312 | { | |
19313 | unsigned int ext_ases = 0; | |
19314 | ||
19315 | if (ase & ASE_DSP) | |
19316 | ext_ases |= AFL_ASE_DSP; | |
19317 | if (ase & ASE_DSPR2) | |
19318 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
19319 | if (ase & ASE_DSPR3) |
19320 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
19321 | if (ase & ASE_EVA) |
19322 | ext_ases |= AFL_ASE_EVA; | |
19323 | if (ase & ASE_MCU) | |
19324 | ext_ases |= AFL_ASE_MCU; | |
19325 | if (ase & ASE_MDMX) | |
19326 | ext_ases |= AFL_ASE_MDMX; | |
19327 | if (ase & ASE_MIPS3D) | |
19328 | ext_ases |= AFL_ASE_MIPS3D; | |
19329 | if (ase & ASE_MT) | |
19330 | ext_ases |= AFL_ASE_MT; | |
19331 | if (ase & ASE_SMARTMIPS) | |
19332 | ext_ases |= AFL_ASE_SMARTMIPS; | |
19333 | if (ase & ASE_VIRT) | |
19334 | ext_ases |= AFL_ASE_VIRT; | |
19335 | if (ase & ASE_MSA) | |
19336 | ext_ases |= AFL_ASE_MSA; | |
19337 | if (ase & ASE_XPA) | |
19338 | ext_ases |= AFL_ASE_XPA; | |
25499ac7 MR |
19339 | if (ase & ASE_MIPS16E2) |
19340 | ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; | |
730c3174 SE |
19341 | if (ase & ASE_CRC) |
19342 | ext_ases |= AFL_ASE_CRC; | |
6f20c942 FS |
19343 | if (ase & ASE_GINV) |
19344 | ext_ases |= AFL_ASE_GINV; | |
8095d2f7 CX |
19345 | if (ase & ASE_LOONGSON_MMI) |
19346 | ext_ases |= AFL_ASE_LOONGSON_MMI; | |
716c08de CX |
19347 | if (ase & ASE_LOONGSON_CAM) |
19348 | ext_ases |= AFL_ASE_LOONGSON_CAM; | |
bdc6c06e CX |
19349 | if (ase & ASE_LOONGSON_EXT) |
19350 | ext_ases |= AFL_ASE_LOONGSON_EXT; | |
a693765e CX |
19351 | if (ase & ASE_LOONGSON_EXT2) |
19352 | ext_ases |= AFL_ASE_LOONGSON_EXT2; | |
351cdf24 MF |
19353 | |
19354 | return ext_ases; | |
19355 | } | |
252b5132 RH |
19356 | /* Some special processing for a MIPS ELF file. */ |
19357 | ||
19358 | void | |
17a2f251 | 19359 | mips_elf_final_processing (void) |
252b5132 | 19360 | { |
351cdf24 MF |
19361 | int fpabi; |
19362 | Elf_Internal_ABIFlags_v0 flags; | |
19363 | ||
19364 | flags.version = 0; | |
19365 | flags.isa_rev = 0; | |
19366 | switch (file_mips_opts.isa) | |
19367 | { | |
19368 | case INSN_ISA1: | |
19369 | flags.isa_level = 1; | |
19370 | break; | |
19371 | case INSN_ISA2: | |
19372 | flags.isa_level = 2; | |
19373 | break; | |
19374 | case INSN_ISA3: | |
19375 | flags.isa_level = 3; | |
19376 | break; | |
19377 | case INSN_ISA4: | |
19378 | flags.isa_level = 4; | |
19379 | break; | |
19380 | case INSN_ISA5: | |
19381 | flags.isa_level = 5; | |
19382 | break; | |
19383 | case INSN_ISA32: | |
19384 | flags.isa_level = 32; | |
19385 | flags.isa_rev = 1; | |
19386 | break; | |
19387 | case INSN_ISA32R2: | |
19388 | flags.isa_level = 32; | |
19389 | flags.isa_rev = 2; | |
19390 | break; | |
19391 | case INSN_ISA32R3: | |
19392 | flags.isa_level = 32; | |
19393 | flags.isa_rev = 3; | |
19394 | break; | |
19395 | case INSN_ISA32R5: | |
19396 | flags.isa_level = 32; | |
19397 | flags.isa_rev = 5; | |
19398 | break; | |
09c14161 MF |
19399 | case INSN_ISA32R6: |
19400 | flags.isa_level = 32; | |
19401 | flags.isa_rev = 6; | |
19402 | break; | |
351cdf24 MF |
19403 | case INSN_ISA64: |
19404 | flags.isa_level = 64; | |
19405 | flags.isa_rev = 1; | |
19406 | break; | |
19407 | case INSN_ISA64R2: | |
19408 | flags.isa_level = 64; | |
19409 | flags.isa_rev = 2; | |
19410 | break; | |
19411 | case INSN_ISA64R3: | |
19412 | flags.isa_level = 64; | |
19413 | flags.isa_rev = 3; | |
19414 | break; | |
19415 | case INSN_ISA64R5: | |
19416 | flags.isa_level = 64; | |
19417 | flags.isa_rev = 5; | |
19418 | break; | |
09c14161 MF |
19419 | case INSN_ISA64R6: |
19420 | flags.isa_level = 64; | |
19421 | flags.isa_rev = 6; | |
19422 | break; | |
351cdf24 MF |
19423 | } |
19424 | ||
19425 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
19426 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
19427 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
19428 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
19429 | : AFL_REG_32; | |
19430 | flags.cpr2_size = AFL_REG_NONE; | |
19431 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19432 | Tag_GNU_MIPS_ABI_FP); | |
19433 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
19434 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
19435 | if (file_ase_mips16) | |
19436 | flags.ases |= AFL_ASE_MIPS16; | |
19437 | if (file_ase_micromips) | |
19438 | flags.ases |= AFL_ASE_MICROMIPS; | |
19439 | flags.flags1 = 0; | |
19440 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
19441 | || file_mips_opts.fp == 64) | |
19442 | && file_mips_opts.oddspreg) | |
19443 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
19444 | flags.flags2 = 0; | |
19445 | ||
19446 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
19447 | ((Elf_External_ABIFlags_v0 *) | |
19448 | mips_flags_frag)); | |
19449 | ||
252b5132 | 19450 | /* Write out the register information. */ |
316f5878 | 19451 | if (mips_abi != N64_ABI) |
252b5132 RH |
19452 | { |
19453 | Elf32_RegInfo s; | |
19454 | ||
19455 | s.ri_gprmask = mips_gprmask; | |
19456 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19457 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19458 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19459 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19460 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19461 | ||
19462 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
19463 | ((Elf32_External_RegInfo *) | |
19464 | mips_regmask_frag)); | |
19465 | } | |
19466 | else | |
19467 | { | |
19468 | Elf64_Internal_RegInfo s; | |
19469 | ||
19470 | s.ri_gprmask = mips_gprmask; | |
19471 | s.ri_pad = 0; | |
19472 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19473 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19474 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19475 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19476 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19477 | ||
19478 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
19479 | ((Elf64_External_RegInfo *) | |
19480 | mips_regmask_frag)); | |
19481 | } | |
19482 | ||
19483 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
19484 | sort of BFD interface for this. */ | |
19485 | if (mips_any_noreorder) | |
19486 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19487 | if (mips_pic != NO_PIC) | |
143d77c5 | 19488 | { |
8b828383 | 19489 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19490 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19491 | } | |
19492 | if (mips_abicalls) | |
19493 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19494 | |
b015e599 AP |
19495 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19496 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19497 | if (file_ase_mips16) |
19498 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19499 | if (file_ase_micromips) |
19500 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 19501 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 19502 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 19503 | |
bdaaa2e1 | 19504 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19505 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19506 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19507 | else if (mips_abi == O64_ABI) |
252b5132 | 19508 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19509 | else if (mips_abi == EABI_ABI) |
252b5132 | 19510 | { |
bad1aba3 | 19511 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19512 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19513 | else | |
19514 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19515 | } | |
be00bddd | 19516 | |
defc8e2b | 19517 | /* Nothing to do for N32_ABI or N64_ABI. */ |
252b5132 RH |
19518 | |
19519 | if (mips_32bitmode) | |
19520 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19521 | |
7361da2c | 19522 | if (mips_nan2008 == 1) |
ba92f887 MR |
19523 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19524 | ||
ad3fea08 | 19525 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19526 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19527 | Tag_GNU_MIPS_ABI_FP); | |
19528 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19529 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19530 | } |
252b5132 | 19531 | \f |
beae10d5 | 19532 | typedef struct proc { |
9b2f1d35 EC |
19533 | symbolS *func_sym; |
19534 | symbolS *func_end_sym; | |
beae10d5 KH |
19535 | unsigned long reg_mask; |
19536 | unsigned long reg_offset; | |
19537 | unsigned long fpreg_mask; | |
19538 | unsigned long fpreg_offset; | |
19539 | unsigned long frame_offset; | |
19540 | unsigned long frame_reg; | |
19541 | unsigned long pc_reg; | |
19542 | } procS; | |
252b5132 RH |
19543 | |
19544 | static procS cur_proc; | |
19545 | static procS *cur_proc_ptr; | |
19546 | static int numprocs; | |
19547 | ||
df58fc94 RS |
19548 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19549 | as "2", and a normal nop as "0". */ | |
19550 | ||
19551 | #define NOP_OPCODE_MIPS 0 | |
19552 | #define NOP_OPCODE_MIPS16 1 | |
19553 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19554 | |
19555 | char | |
19556 | mips_nop_opcode (void) | |
19557 | { | |
df58fc94 RS |
19558 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19559 | return NOP_OPCODE_MICROMIPS; | |
19560 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19561 | return NOP_OPCODE_MIPS16; | |
19562 | else | |
19563 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19564 | } |
19565 | ||
df58fc94 RS |
19566 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19567 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19568 | |
0a9ef439 | 19569 | void |
17a2f251 | 19570 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19571 | { |
df58fc94 | 19572 | char nop_opcode; |
742a56fe | 19573 | char *p; |
c67a084a NC |
19574 | int bytes, size, excess; |
19575 | valueT opcode; | |
742a56fe | 19576 | |
0a9ef439 RH |
19577 | if (fragp->fr_type != rs_align_code) |
19578 | return; | |
19579 | ||
742a56fe | 19580 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19581 | nop_opcode = *p; |
19582 | switch (nop_opcode) | |
a19d8eb0 | 19583 | { |
df58fc94 RS |
19584 | case NOP_OPCODE_MICROMIPS: |
19585 | opcode = micromips_nop32_insn.insn_opcode; | |
19586 | size = 4; | |
19587 | break; | |
19588 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19589 | opcode = mips16_nop_insn.insn_opcode; |
19590 | size = 2; | |
df58fc94 RS |
19591 | break; |
19592 | case NOP_OPCODE_MIPS: | |
19593 | default: | |
c67a084a NC |
19594 | opcode = nop_insn.insn_opcode; |
19595 | size = 4; | |
df58fc94 | 19596 | break; |
c67a084a | 19597 | } |
a19d8eb0 | 19598 | |
c67a084a NC |
19599 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19600 | excess = bytes % size; | |
df58fc94 RS |
19601 | |
19602 | /* Handle the leading part if we're not inserting a whole number of | |
19603 | instructions, and make it the end of the fixed part of the frag. | |
19604 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19605 | and use zeroes otherwise. */ | |
19606 | gas_assert (excess < 4); | |
19607 | fragp->fr_fix += excess; | |
19608 | switch (excess) | |
c67a084a | 19609 | { |
df58fc94 RS |
19610 | case 3: |
19611 | *p++ = '\0'; | |
19612 | /* Fall through. */ | |
19613 | case 2: | |
833794fc | 19614 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19615 | { |
4d68580a | 19616 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19617 | break; |
19618 | } | |
19619 | *p++ = '\0'; | |
19620 | /* Fall through. */ | |
19621 | case 1: | |
19622 | *p++ = '\0'; | |
19623 | /* Fall through. */ | |
19624 | case 0: | |
19625 | break; | |
a19d8eb0 | 19626 | } |
c67a084a NC |
19627 | |
19628 | md_number_to_chars (p, opcode, size); | |
19629 | fragp->fr_var = size; | |
a19d8eb0 CP |
19630 | } |
19631 | ||
252b5132 | 19632 | static long |
17a2f251 | 19633 | get_number (void) |
252b5132 RH |
19634 | { |
19635 | int negative = 0; | |
19636 | long val = 0; | |
19637 | ||
19638 | if (*input_line_pointer == '-') | |
19639 | { | |
19640 | ++input_line_pointer; | |
19641 | negative = 1; | |
19642 | } | |
3882b010 | 19643 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19644 | as_bad (_("expected simple number")); |
252b5132 RH |
19645 | if (input_line_pointer[0] == '0') |
19646 | { | |
19647 | if (input_line_pointer[1] == 'x') | |
19648 | { | |
19649 | input_line_pointer += 2; | |
3882b010 | 19650 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19651 | { |
19652 | val <<= 4; | |
19653 | val |= hex_value (*input_line_pointer++); | |
19654 | } | |
19655 | return negative ? -val : val; | |
19656 | } | |
19657 | else | |
19658 | { | |
19659 | ++input_line_pointer; | |
3882b010 | 19660 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19661 | { |
19662 | val <<= 3; | |
19663 | val |= *input_line_pointer++ - '0'; | |
19664 | } | |
19665 | return negative ? -val : val; | |
19666 | } | |
19667 | } | |
3882b010 | 19668 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19669 | { |
19670 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19671 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19672 | as_warn (_("invalid number")); |
252b5132 RH |
19673 | return -1; |
19674 | } | |
3882b010 | 19675 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19676 | { |
19677 | val *= 10; | |
19678 | val += *input_line_pointer++ - '0'; | |
19679 | } | |
19680 | return negative ? -val : val; | |
19681 | } | |
19682 | ||
19683 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19684 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19685 | case .file implies DWARF-2. */ | |
19686 | ||
19687 | static void | |
17a2f251 | 19688 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19689 | { |
ecb4347a DJ |
19690 | static int first_file_directive = 0; |
19691 | ||
c5dd6aab DJ |
19692 | if (ECOFF_DEBUGGING) |
19693 | { | |
19694 | get_number (); | |
19695 | s_app_file (0); | |
19696 | } | |
19697 | else | |
ecb4347a DJ |
19698 | { |
19699 | char *filename; | |
19700 | ||
68d20676 | 19701 | filename = dwarf2_directive_filename (); |
ecb4347a DJ |
19702 | |
19703 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19704 | directive even for stabs output. Make sure that this | |
19705 | ".file" is handled. Note that you need a version of GCC | |
19706 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19707 | if (filename != NULL && ! first_file_directive) | |
19708 | { | |
19709 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19710 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19711 | } |
19712 | first_file_directive = 1; | |
19713 | } | |
c5dd6aab DJ |
19714 | } |
19715 | ||
19716 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19717 | |
19718 | static void | |
17a2f251 | 19719 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19720 | { |
c5dd6aab DJ |
19721 | if (!ECOFF_DEBUGGING) |
19722 | dwarf2_directive_loc (0); | |
252b5132 RH |
19723 | } |
19724 | ||
252b5132 RH |
19725 | /* The .end directive. */ |
19726 | ||
19727 | static void | |
17a2f251 | 19728 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19729 | { |
19730 | symbolS *p; | |
252b5132 | 19731 | |
7a621144 DJ |
19732 | /* Following functions need their own .frame and .cprestore directives. */ |
19733 | mips_frame_reg_valid = 0; | |
19734 | mips_cprestore_valid = 0; | |
19735 | ||
252b5132 RH |
19736 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19737 | { | |
19738 | p = get_symbol (); | |
19739 | demand_empty_rest_of_line (); | |
19740 | } | |
19741 | else | |
19742 | p = NULL; | |
19743 | ||
14949570 | 19744 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19745 | as_warn (_(".end not in text section")); |
19746 | ||
19747 | if (!cur_proc_ptr) | |
19748 | { | |
1661c76c | 19749 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19750 | demand_empty_rest_of_line (); |
19751 | return; | |
19752 | } | |
19753 | ||
19754 | if (p != NULL) | |
19755 | { | |
9c2799c2 | 19756 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19757 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19758 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19759 | |
19760 | if (debug_type == DEBUG_STABS) | |
19761 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19762 | S_GET_NAME (p)); | |
252b5132 RH |
19763 | } |
19764 | else | |
19765 | as_warn (_(".end directive missing or unknown symbol")); | |
19766 | ||
9b2f1d35 EC |
19767 | /* Create an expression to calculate the size of the function. */ |
19768 | if (p && cur_proc_ptr) | |
19769 | { | |
19770 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19771 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19772 | |
19773 | obj->size = exp; | |
19774 | exp->X_op = O_subtract; | |
19775 | exp->X_add_symbol = symbol_temp_new_now (); | |
19776 | exp->X_op_symbol = p; | |
19777 | exp->X_add_number = 0; | |
19778 | ||
19779 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19780 | } | |
19781 | ||
5ff6a06c MR |
19782 | #ifdef md_flush_pending_output |
19783 | md_flush_pending_output (); | |
19784 | #endif | |
19785 | ||
ecb4347a | 19786 | /* Generate a .pdr section. */ |
f3ded42a | 19787 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19788 | { |
19789 | segT saved_seg = now_seg; | |
19790 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19791 | expressionS exp; |
19792 | char *fragp; | |
252b5132 | 19793 | |
9c2799c2 | 19794 | gas_assert (pdr_seg); |
ecb4347a | 19795 | subseg_set (pdr_seg, 0); |
252b5132 | 19796 | |
ecb4347a DJ |
19797 | /* Write the symbol. */ |
19798 | exp.X_op = O_symbol; | |
19799 | exp.X_add_symbol = p; | |
19800 | exp.X_add_number = 0; | |
19801 | emit_expr (&exp, 4); | |
252b5132 | 19802 | |
ecb4347a | 19803 | fragp = frag_more (7 * 4); |
252b5132 | 19804 | |
17a2f251 TS |
19805 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19806 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19807 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19808 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19809 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19810 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19811 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19812 | |
ecb4347a DJ |
19813 | subseg_set (saved_seg, saved_subseg); |
19814 | } | |
252b5132 RH |
19815 | |
19816 | cur_proc_ptr = NULL; | |
19817 | } | |
19818 | ||
19819 | /* The .aent and .ent directives. */ | |
19820 | ||
19821 | static void | |
17a2f251 | 19822 | s_mips_ent (int aent) |
252b5132 | 19823 | { |
252b5132 | 19824 | symbolS *symbolP; |
252b5132 RH |
19825 | |
19826 | symbolP = get_symbol (); | |
19827 | if (*input_line_pointer == ',') | |
f9419b05 | 19828 | ++input_line_pointer; |
252b5132 | 19829 | SKIP_WHITESPACE (); |
3882b010 | 19830 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19831 | || *input_line_pointer == '-') |
874e8986 | 19832 | get_number (); |
252b5132 | 19833 | |
14949570 | 19834 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 19835 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19836 | |
19837 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19838 | as_warn (_("missing .end")); |
252b5132 RH |
19839 | |
19840 | if (!aent) | |
19841 | { | |
7a621144 DJ |
19842 | /* This function needs its own .frame and .cprestore directives. */ |
19843 | mips_frame_reg_valid = 0; | |
19844 | mips_cprestore_valid = 0; | |
19845 | ||
252b5132 RH |
19846 | cur_proc_ptr = &cur_proc; |
19847 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19848 | ||
9b2f1d35 | 19849 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19850 | |
f9419b05 | 19851 | ++numprocs; |
ecb4347a DJ |
19852 | |
19853 | if (debug_type == DEBUG_STABS) | |
19854 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19855 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19856 | } |
19857 | ||
7c0fc524 MR |
19858 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19859 | ||
252b5132 RH |
19860 | demand_empty_rest_of_line (); |
19861 | } | |
19862 | ||
19863 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19864 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19865 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19866 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19867 | symbol table (in the mdebug section). */ |
19868 | ||
19869 | static void | |
17a2f251 | 19870 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19871 | { |
f3ded42a RS |
19872 | if (ECOFF_DEBUGGING) |
19873 | s_ignore (ignore); | |
19874 | else | |
ecb4347a DJ |
19875 | { |
19876 | long val; | |
252b5132 | 19877 | |
ecb4347a DJ |
19878 | if (cur_proc_ptr == (procS *) NULL) |
19879 | { | |
19880 | as_warn (_(".frame outside of .ent")); | |
19881 | demand_empty_rest_of_line (); | |
19882 | return; | |
19883 | } | |
252b5132 | 19884 | |
ecb4347a DJ |
19885 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19886 | ||
19887 | SKIP_WHITESPACE (); | |
19888 | if (*input_line_pointer++ != ',' | |
19889 | || get_absolute_expression_and_terminator (&val) != ',') | |
19890 | { | |
1661c76c | 19891 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19892 | --input_line_pointer; |
19893 | demand_empty_rest_of_line (); | |
19894 | return; | |
19895 | } | |
252b5132 | 19896 | |
ecb4347a DJ |
19897 | cur_proc_ptr->frame_offset = val; |
19898 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19899 | |
252b5132 | 19900 | demand_empty_rest_of_line (); |
252b5132 | 19901 | } |
252b5132 RH |
19902 | } |
19903 | ||
bdaaa2e1 KH |
19904 | /* The .fmask and .mask directives. If the mdebug section is present |
19905 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19906 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19907 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19908 | make reference to the ecoff symbol table (in the mdebug section). */ |
19909 | ||
19910 | static void | |
17a2f251 | 19911 | s_mips_mask (int reg_type) |
252b5132 | 19912 | { |
f3ded42a RS |
19913 | if (ECOFF_DEBUGGING) |
19914 | s_ignore (reg_type); | |
19915 | else | |
252b5132 | 19916 | { |
ecb4347a | 19917 | long mask, off; |
252b5132 | 19918 | |
ecb4347a DJ |
19919 | if (cur_proc_ptr == (procS *) NULL) |
19920 | { | |
19921 | as_warn (_(".mask/.fmask outside of .ent")); | |
19922 | demand_empty_rest_of_line (); | |
19923 | return; | |
19924 | } | |
252b5132 | 19925 | |
ecb4347a DJ |
19926 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19927 | { | |
1661c76c | 19928 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19929 | --input_line_pointer; |
19930 | demand_empty_rest_of_line (); | |
19931 | return; | |
19932 | } | |
252b5132 | 19933 | |
ecb4347a DJ |
19934 | off = get_absolute_expression (); |
19935 | ||
19936 | if (reg_type == 'F') | |
19937 | { | |
19938 | cur_proc_ptr->fpreg_mask = mask; | |
19939 | cur_proc_ptr->fpreg_offset = off; | |
19940 | } | |
19941 | else | |
19942 | { | |
19943 | cur_proc_ptr->reg_mask = mask; | |
19944 | cur_proc_ptr->reg_offset = off; | |
19945 | } | |
19946 | ||
19947 | demand_empty_rest_of_line (); | |
252b5132 | 19948 | } |
252b5132 RH |
19949 | } |
19950 | ||
316f5878 RS |
19951 | /* A table describing all the processors gas knows about. Names are |
19952 | matched in the order listed. | |
e7af610e | 19953 | |
316f5878 RS |
19954 | To ease comparison, please keep this table in the same order as |
19955 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19956 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19957 | { | |
6f2117ba | 19958 | /* Entries for generic ISAs. */ |
d16afab6 RS |
19959 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19960 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19961 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19962 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19963 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19964 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19965 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
19966 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
19967 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 19968 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
19969 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
19970 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
19971 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
19972 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 19973 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
19974 | |
19975 | /* MIPS I */ | |
d16afab6 RS |
19976 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19977 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19978 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19979 | |
19980 | /* MIPS II */ | |
d16afab6 | 19981 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19982 | |
19983 | /* MIPS III */ | |
d16afab6 RS |
19984 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19985 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19986 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19987 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19988 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19989 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19990 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19991 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19992 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19993 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19994 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19995 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19996 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
6f2117ba | 19997 | /* ST Microelectronics Loongson 2E and 2F cores. */ |
d16afab6 | 19998 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
8095d2f7 | 19999 | { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F }, |
316f5878 RS |
20000 | |
20001 | /* MIPS IV */ | |
d16afab6 RS |
20002 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
20003 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
20004 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
20005 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
20006 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
20007 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20008 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
20009 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
20010 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20011 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20012 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20013 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20014 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20015 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
20016 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
20017 | |
20018 | /* MIPS 32 */ | |
d16afab6 RS |
20019 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
20020 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
20021 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
20022 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
20023 | |
20024 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
20025 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20026 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20027 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20028 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20029 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20030 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20031 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20032 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20033 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
20034 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20035 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
20036 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20037 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20038 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20039 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20040 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20041 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20042 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20043 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 20044 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
20045 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20046 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20047 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20048 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20049 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20050 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20051 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 20052 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
20053 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20054 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20055 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20056 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20057 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20058 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20059 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 20060 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 20061 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 20062 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
20063 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20064 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20065 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20066 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20067 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20068 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20069 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20070 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 20071 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
20072 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20073 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20074 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20075 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
6f2117ba | 20076 | /* interaptiv is the new name for 1004kf. */ |
77403ce9 | 20077 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
38bf472a MR |
20078 | { "interaptiv-mr2", 0, |
20079 | ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT, | |
20080 | ISA_MIPS32R3, CPU_INTERAPTIV_MR2 }, | |
6f2117ba | 20081 | /* M5100 family. */ |
c6e5c03a RS |
20082 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, |
20083 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 20084 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 20085 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 20086 | |
316f5878 | 20087 | /* MIPS 64 */ |
d16afab6 RS |
20088 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
20089 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
20090 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
20091 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 20092 | |
6f2117ba | 20093 | /* Broadcom SB-1 CPU core. */ |
d16afab6 | 20094 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
6f2117ba | 20095 | /* Broadcom SB-1A CPU core. */ |
d16afab6 | 20096 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 20097 | |
6f2117ba PH |
20098 | /* MIPS 64 Release 2. */ |
20099 | /* Loongson CPU core. */ | |
20100 | /* -march=loongson3a is an alias of -march=gs464 for compatibility. */ | |
bdc6c06e | 20101 | { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, |
ac8cb70f CX |
20102 | ISA_MIPS64R2, CPU_GS464 }, |
20103 | { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, | |
20104 | ISA_MIPS64R2, CPU_GS464 }, | |
bd782c07 CX |
20105 | { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
20106 | | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E }, | |
9108bc33 CX |
20107 | { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
20108 | | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E }, | |
ed163775 | 20109 | |
6f2117ba | 20110 | /* Cavium Networks Octeon CPU core. */ |
d16afab6 RS |
20111 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
20112 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
20113 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 20114 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 20115 | |
52b6b6b9 | 20116 | /* RMI Xlr */ |
d16afab6 | 20117 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 20118 | |
55a36193 MK |
20119 | /* Broadcom XLP. |
20120 | XLP is mostly like XLR, with the prominent exception that it is | |
20121 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 20122 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 20123 | |
6f2117ba | 20124 | /* MIPS 64 Release 6. */ |
bdc8beb4 MF |
20125 | { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
20126 | { "i6500", 0, ASE_VIRT | ASE_MSA | ASE_CRC | ASE_GINV, | |
20127 | ISA_MIPS64R6, CPU_MIPS64R6}, | |
a4968f42 | 20128 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 20129 | |
6f2117ba | 20130 | /* End marker. */ |
d16afab6 | 20131 | { NULL, 0, 0, 0, 0 } |
316f5878 | 20132 | }; |
e7af610e | 20133 | |
84ea6cf2 | 20134 | |
316f5878 RS |
20135 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
20136 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 20137 | |
316f5878 | 20138 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 20139 | |
b34976b6 | 20140 | static bfd_boolean |
17a2f251 | 20141 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
20142 | { |
20143 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
20144 | given++, canonical++; | |
20145 | ||
20146 | return ((*given == 0 && *canonical == 0) | |
20147 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
20148 | } | |
20149 | ||
20150 | ||
20151 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
20152 | CPU name. We've traditionally allowed a lot of variation here. | |
20153 | ||
20154 | Note: this function is shared between GCC and GAS. */ | |
20155 | ||
b34976b6 | 20156 | static bfd_boolean |
17a2f251 | 20157 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
20158 | { |
20159 | /* First see if the name matches exactly, or with a final "000" | |
20160 | turned into "k". */ | |
20161 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 20162 | return TRUE; |
316f5878 RS |
20163 | |
20164 | /* If not, try comparing based on numerical designation alone. | |
20165 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
20166 | if (TOLOWER (*given) == 'r') | |
20167 | given++; | |
20168 | if (!ISDIGIT (*given)) | |
b34976b6 | 20169 | return FALSE; |
316f5878 RS |
20170 | |
20171 | /* Skip over some well-known prefixes in the canonical name, | |
20172 | hoping to find a number there too. */ | |
20173 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
20174 | canonical += 2; | |
20175 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
20176 | canonical += 2; | |
20177 | else if (TOLOWER (canonical[0]) == 'r') | |
20178 | canonical += 1; | |
20179 | ||
20180 | return mips_strict_matching_cpu_name_p (canonical, given); | |
20181 | } | |
20182 | ||
20183 | ||
20184 | /* Parse an option that takes the name of a processor as its argument. | |
20185 | OPTION is the name of the option and CPU_STRING is the argument. | |
20186 | Return the corresponding processor enumeration if the CPU_STRING is | |
20187 | recognized, otherwise report an error and return null. | |
20188 | ||
20189 | A similar function exists in GCC. */ | |
e7af610e NC |
20190 | |
20191 | static const struct mips_cpu_info * | |
17a2f251 | 20192 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 20193 | { |
316f5878 | 20194 | const struct mips_cpu_info *p; |
e7af610e | 20195 | |
316f5878 RS |
20196 | /* 'from-abi' selects the most compatible architecture for the given |
20197 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
20198 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
20199 | version. Look first at the -mgp options, if given, otherwise base | |
20200 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 20201 | |
316f5878 RS |
20202 | Treat NO_ABI like the EABIs. One reason to do this is that the |
20203 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
20204 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
20205 | 'mips64', just as we did in the days before 'from-abi'. */ | |
20206 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
20207 | { | |
20208 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
20209 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
20210 | ||
20211 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
20212 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
20213 | ||
bad1aba3 | 20214 | if (file_mips_opts.gp >= 0) |
20215 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 20216 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
20217 | |
20218 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
20219 | ? ISA_MIPS3 | |
20220 | : ISA_MIPS1); | |
20221 | } | |
20222 | ||
20223 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
20224 | if (strcasecmp (cpu_string, "default") == 0) | |
20225 | return 0; | |
20226 | ||
20227 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
20228 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
20229 | return p; | |
20230 | ||
1661c76c | 20231 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 20232 | return 0; |
e7af610e NC |
20233 | } |
20234 | ||
316f5878 RS |
20235 | /* Return the canonical processor information for ISA (a member of the |
20236 | ISA_MIPS* enumeration). */ | |
20237 | ||
e7af610e | 20238 | static const struct mips_cpu_info * |
17a2f251 | 20239 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
20240 | { |
20241 | int i; | |
20242 | ||
20243 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 20244 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 20245 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
20246 | return (&mips_cpu_info_table[i]); |
20247 | ||
e972090a | 20248 | return NULL; |
e7af610e | 20249 | } |
fef14a42 TS |
20250 | |
20251 | static const struct mips_cpu_info * | |
17a2f251 | 20252 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
20253 | { |
20254 | int i; | |
20255 | ||
20256 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
20257 | if (arch == mips_cpu_info_table[i].cpu) | |
20258 | return (&mips_cpu_info_table[i]); | |
20259 | ||
20260 | return NULL; | |
20261 | } | |
316f5878 RS |
20262 | \f |
20263 | static void | |
17a2f251 | 20264 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
20265 | { |
20266 | if (*first_p) | |
20267 | { | |
20268 | fprintf (stream, "%24s", ""); | |
20269 | *col_p = 24; | |
20270 | } | |
20271 | else | |
20272 | { | |
20273 | fprintf (stream, ", "); | |
20274 | *col_p += 2; | |
20275 | } | |
e7af610e | 20276 | |
316f5878 RS |
20277 | if (*col_p + strlen (string) > 72) |
20278 | { | |
20279 | fprintf (stream, "\n%24s", ""); | |
20280 | *col_p = 24; | |
20281 | } | |
20282 | ||
20283 | fprintf (stream, "%s", string); | |
20284 | *col_p += strlen (string); | |
20285 | ||
20286 | *first_p = 0; | |
20287 | } | |
20288 | ||
20289 | void | |
17a2f251 | 20290 | md_show_usage (FILE *stream) |
e7af610e | 20291 | { |
316f5878 RS |
20292 | int column, first; |
20293 | size_t i; | |
20294 | ||
20295 | fprintf (stream, _("\ | |
20296 | MIPS options:\n\ | |
316f5878 RS |
20297 | -EB generate big endian output\n\ |
20298 | -EL generate little endian output\n\ | |
20299 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
20300 | -G NUM allow referencing objects up to NUM bytes\n\ | |
20301 | implicitly with the gp register [default 8]\n")); | |
20302 | fprintf (stream, _("\ | |
20303 | -mips1 generate MIPS ISA I instructions\n\ | |
20304 | -mips2 generate MIPS ISA II instructions\n\ | |
20305 | -mips3 generate MIPS ISA III instructions\n\ | |
20306 | -mips4 generate MIPS ISA IV instructions\n\ | |
20307 | -mips5 generate MIPS ISA V instructions\n\ | |
20308 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 20309 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
20310 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
20311 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 20312 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 20313 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 20314 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
20315 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
20316 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 20317 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
20318 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
20319 | ||
20320 | first = 1; | |
e7af610e NC |
20321 | |
20322 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
20323 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
20324 | show (stream, "from-abi", &column, &first); | |
20325 | fputc ('\n', stream); | |
e7af610e | 20326 | |
316f5878 RS |
20327 | fprintf (stream, _("\ |
20328 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
20329 | -no-mCPU don't generate code specific to CPU.\n\ | |
20330 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
20331 | ||
20332 | first = 1; | |
20333 | ||
20334 | show (stream, "3900", &column, &first); | |
20335 | show (stream, "4010", &column, &first); | |
20336 | show (stream, "4100", &column, &first); | |
20337 | show (stream, "4650", &column, &first); | |
20338 | fputc ('\n', stream); | |
20339 | ||
20340 | fprintf (stream, _("\ | |
20341 | -mips16 generate mips16 instructions\n\ | |
20342 | -no-mips16 do not generate mips16 instructions\n")); | |
20343 | fprintf (stream, _("\ | |
f866b262 MR |
20344 | -mmips16e2 generate MIPS16e2 instructions\n\ |
20345 | -mno-mips16e2 do not generate MIPS16e2 instructions\n")); | |
20346 | fprintf (stream, _("\ | |
df58fc94 RS |
20347 | -mmicromips generate microMIPS instructions\n\ |
20348 | -mno-micromips do not generate microMIPS instructions\n")); | |
20349 | fprintf (stream, _("\ | |
e16bfa71 | 20350 | -msmartmips generate smartmips instructions\n\ |
3739860c | 20351 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 20352 | fprintf (stream, _("\ |
74cd071d CF |
20353 | -mdsp generate DSP instructions\n\ |
20354 | -mno-dsp do not generate DSP instructions\n")); | |
20355 | fprintf (stream, _("\ | |
8b082fb1 TS |
20356 | -mdspr2 generate DSP R2 instructions\n\ |
20357 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
20358 | fprintf (stream, _("\ | |
8f4f9071 MF |
20359 | -mdspr3 generate DSP R3 instructions\n\ |
20360 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
20361 | fprintf (stream, _("\ | |
ef2e4d86 CF |
20362 | -mmt generate MT instructions\n\ |
20363 | -mno-mt do not generate MT instructions\n")); | |
20364 | fprintf (stream, _("\ | |
dec0624d MR |
20365 | -mmcu generate MCU instructions\n\ |
20366 | -mno-mcu do not generate MCU instructions\n")); | |
20367 | fprintf (stream, _("\ | |
56d438b1 CF |
20368 | -mmsa generate MSA instructions\n\ |
20369 | -mno-msa do not generate MSA instructions\n")); | |
20370 | fprintf (stream, _("\ | |
7d64c587 AB |
20371 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
20372 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
20373 | fprintf (stream, _("\ | |
b015e599 AP |
20374 | -mvirt generate Virtualization instructions\n\ |
20375 | -mno-virt do not generate Virtualization instructions\n")); | |
20376 | fprintf (stream, _("\ | |
730c3174 SE |
20377 | -mcrc generate CRC instructions\n\ |
20378 | -mno-crc do not generate CRC instructions\n")); | |
20379 | fprintf (stream, _("\ | |
6f20c942 FS |
20380 | -mginv generate Global INValidate (GINV) instructions\n\ |
20381 | -mno-ginv do not generate Global INValidate instructions\n")); | |
20382 | fprintf (stream, _("\ | |
8095d2f7 CX |
20383 | -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\ |
20384 | -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n")); | |
20385 | fprintf (stream, _("\ | |
716c08de CX |
20386 | -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\ |
20387 | -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n")); | |
20388 | fprintf (stream, _("\ | |
bdc6c06e CX |
20389 | -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\ |
20390 | -mno-loongson-ext do not generate Loongson EXTensions Instructions\n")); | |
20391 | fprintf (stream, _("\ | |
a693765e CX |
20392 | -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\ |
20393 | -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n")); | |
20394 | fprintf (stream, _("\ | |
833794fc MR |
20395 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
20396 | -mno-insn32 generate all microMIPS instructions\n")); | |
6f2117ba PH |
20397 | #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC |
20398 | fprintf (stream, _("\ | |
20399 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\ | |
20400 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n")); | |
20401 | #else | |
20402 | fprintf (stream, _("\ | |
20403 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ | |
20404 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n")); | |
20405 | #endif | |
833794fc | 20406 | fprintf (stream, _("\ |
c67a084a NC |
20407 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
20408 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
6f2117ba PH |
20409 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ |
20410 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\ | |
d766e8ec | 20411 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 20412 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 20413 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 20414 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
27c634e0 | 20415 | -mfix-r5900 work around R5900 short loop errata\n\ |
316f5878 RS |
20416 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
20417 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 20418 | -msym32 assume all symbols have 32-bit values\n\ |
092a534f MR |
20419 | -O0 do not remove unneeded NOPs, do not swap branches\n\ |
20420 | -O, -O1 remove unneeded NOPs, do not swap branches\n\ | |
20421 | -O2 remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
20422 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
20423 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
20424 | fprintf (stream, _("\ |
20425 | -mhard-float allow floating-point instructions\n\ | |
20426 | -msoft-float do not allow floating-point instructions\n\ | |
20427 | -msingle-float only allow 32-bit floating-point operations\n\ | |
20428 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 20429 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 20430 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
20431 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
20432 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
20433 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
20434 | ||
20435 | first = 1; | |
20436 | ||
20437 | show (stream, "legacy", &column, &first); | |
20438 | show (stream, "2008", &column, &first); | |
20439 | ||
20440 | fputc ('\n', stream); | |
20441 | ||
316f5878 RS |
20442 | fprintf (stream, _("\ |
20443 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 20444 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 20445 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 20446 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 20447 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 20448 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 20449 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 20450 | position dependent (non shared) code\n\ |
316f5878 RS |
20451 | -mabi=ABI create ABI conformant object file for:\n")); |
20452 | ||
20453 | first = 1; | |
20454 | ||
20455 | show (stream, "32", &column, &first); | |
20456 | show (stream, "o64", &column, &first); | |
20457 | show (stream, "n32", &column, &first); | |
20458 | show (stream, "64", &column, &first); | |
20459 | show (stream, "eabi", &column, &first); | |
20460 | ||
20461 | fputc ('\n', stream); | |
20462 | ||
20463 | fprintf (stream, _("\ | |
b4f6242e MR |
20464 | -32 create o32 ABI object file%s\n"), |
20465 | MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : ""); | |
20466 | fprintf (stream, _("\ | |
20467 | -n32 create n32 ABI object file%s\n"), | |
20468 | MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : ""); | |
20469 | fprintf (stream, _("\ | |
20470 | -64 create 64 ABI object file%s\n"), | |
20471 | MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : ""); | |
e7af610e | 20472 | } |
14e777e0 | 20473 | |
1575952e | 20474 | #ifdef TE_IRIX |
14e777e0 | 20475 | enum dwarf2_format |
413a266c | 20476 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 20477 | { |
369943fe | 20478 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 20479 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
20480 | else |
20481 | return dwarf2_format_32bit; | |
20482 | } | |
1575952e | 20483 | #endif |
73369e65 EC |
20484 | |
20485 | int | |
20486 | mips_dwarf2_addr_size (void) | |
20487 | { | |
6b6b3450 | 20488 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 20489 | return 8; |
73369e65 EC |
20490 | else |
20491 | return 4; | |
20492 | } | |
5862107c EC |
20493 | |
20494 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
20495 | void | |
20496 | mips_cfi_frame_initial_instructions (void) | |
20497 | { | |
20498 | cfi_add_CFA_def_cfa_register (SP); | |
20499 | } | |
20500 | ||
707bfff6 TS |
20501 | int |
20502 | tc_mips_regname_to_dw2regnum (char *regname) | |
20503 | { | |
20504 | unsigned int regnum = -1; | |
20505 | unsigned int reg; | |
20506 | ||
20507 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
20508 | regnum = reg; | |
20509 | ||
20510 | return regnum; | |
20511 | } | |
263b2574 | 20512 | |
20513 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
20514 | Given a symbolic attribute NAME, return the proper integer value. | |
20515 | Returns -1 if the attribute is not known. */ | |
20516 | ||
20517 | int | |
20518 | mips_convert_symbolic_attribute (const char *name) | |
20519 | { | |
20520 | static const struct | |
20521 | { | |
20522 | const char * name; | |
20523 | const int tag; | |
20524 | } | |
20525 | attribute_table[] = | |
20526 | { | |
20527 | #define T(tag) {#tag, tag} | |
20528 | T (Tag_GNU_MIPS_ABI_FP), | |
20529 | T (Tag_GNU_MIPS_ABI_MSA), | |
20530 | #undef T | |
20531 | }; | |
20532 | unsigned int i; | |
20533 | ||
20534 | if (name == NULL) | |
20535 | return -1; | |
20536 | ||
20537 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
20538 | if (streq (name, attribute_table[i].name)) | |
20539 | return attribute_table[i].tag; | |
20540 | ||
20541 | return -1; | |
20542 | } | |
fd5c94ab RS |
20543 | |
20544 | void | |
20545 | md_mips_end (void) | |
20546 | { | |
351cdf24 MF |
20547 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
20548 | ||
fd5c94ab RS |
20549 | mips_emit_delays (); |
20550 | if (cur_proc_ptr) | |
20551 | as_warn (_("missing .end at end of assembly")); | |
919731af | 20552 | |
20553 | /* Just in case no code was emitted, do the consistency check. */ | |
20554 | file_mips_check_options (); | |
351cdf24 MF |
20555 | |
20556 | /* Set a floating-point ABI if the user did not. */ | |
20557 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20558 | { | |
20559 | /* Perform consistency checks on the floating-point ABI. */ | |
20560 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20561 | Tag_GNU_MIPS_ABI_FP); | |
20562 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20563 | check_fpabi (fpabi); | |
20564 | } | |
20565 | else | |
20566 | { | |
20567 | /* Soft-float gets precedence over single-float, the two options should | |
20568 | not be used together so this should not matter. */ | |
20569 | if (file_mips_opts.soft_float == 1) | |
20570 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20571 | /* Single-float gets precedence over all double_float cases. */ | |
20572 | else if (file_mips_opts.single_float == 1) | |
20573 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20574 | else | |
20575 | { | |
20576 | switch (file_mips_opts.fp) | |
20577 | { | |
20578 | case 32: | |
20579 | if (file_mips_opts.gp == 32) | |
20580 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20581 | break; | |
20582 | case 0: | |
20583 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20584 | break; | |
20585 | case 64: | |
20586 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20587 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20588 | else if (file_mips_opts.gp == 32) | |
20589 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20590 | else | |
20591 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20592 | break; | |
20593 | } | |
20594 | } | |
20595 | ||
20596 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20597 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20598 | } | |
fd5c94ab | 20599 | } |
2f0c68f2 CM |
20600 | |
20601 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20602 | ||
20603 | bfd_reloc_code_real_type | |
20604 | mips_cfi_reloc_for_encoding (int encoding) | |
20605 | { | |
20606 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20607 | return BFD_RELOC_32_PCREL; | |
20608 | else return BFD_RELOC_NONE; | |
20609 | } |