Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
f7e42eb4 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
47 | #ifdef OBJ_MAYBE_ELF | |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
49 | static int mips_output_flavor PARAMS ((void)); | |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
252b5132 RH |
57 | #undef obj_frob_file |
58 | #undef obj_frob_file_after_relocs | |
59 | #undef obj_frob_symbol | |
60 | #undef obj_pop_insert | |
61 | #undef obj_sec_sym_ok_for_reloc | |
62 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
71 | #include "elf/mips.h" | |
72 | #endif | |
73 | ||
74 | #ifndef ECOFF_DEBUGGING | |
75 | #define NO_ECOFF_DEBUGGING | |
76 | #define ECOFF_DEBUGGING 0 | |
77 | #endif | |
78 | ||
79 | #include "ecoff.h" | |
80 | ||
81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
82 | static char *mips_regmask_frag; | |
83 | #endif | |
84 | ||
85 | #define AT 1 | |
86 | #define TREG 24 | |
87 | #define PIC_CALL_REG 25 | |
88 | #define KT0 26 | |
89 | #define KT1 27 | |
90 | #define GP 28 | |
91 | #define SP 29 | |
92 | #define FP 30 | |
93 | #define RA 31 | |
94 | ||
95 | #define ILLEGAL_REG (32) | |
96 | ||
97 | /* Allow override of standard little-endian ECOFF format. */ | |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
103 | extern int target_big_endian; | |
104 | ||
252b5132 RH |
105 | /* The name of the readonly data section. */ |
106 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
107 | ? ".data" \ | |
108 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
109 | ? ".rdata" \ | |
056350c6 NC |
110 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
111 | ? ".rdata" \ | |
252b5132 RH |
112 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
113 | ? ".rodata" \ | |
114 | : (abort (), "")) | |
115 | ||
a325df1d TS |
116 | /* The ABI to use. */ |
117 | enum mips_abi_level | |
118 | { | |
119 | NO_ABI = 0, | |
120 | O32_ABI, | |
121 | O64_ABI, | |
122 | N32_ABI, | |
123 | N64_ABI, | |
124 | EABI_ABI | |
125 | }; | |
126 | ||
127 | /* MIPS ABI we are using for this output file. */ | |
128 | static enum mips_abi_level file_mips_abi = NO_ABI; | |
129 | ||
252b5132 RH |
130 | /* This is the set of options which may be modified by the .set |
131 | pseudo-op. We use a struct so that .set push and .set pop are more | |
132 | reliable. */ | |
133 | ||
e972090a NC |
134 | struct mips_set_options |
135 | { | |
252b5132 RH |
136 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
137 | if it has not been initialized. Changed by `.set mipsN', and the | |
138 | -mipsN command line option, and the default CPU. */ | |
139 | int isa; | |
140 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
141 | not, 1 if we are, and -1 if the value has not been initialized. | |
142 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
143 | -nomips16 command line options, and the default CPU. */ | |
144 | int mips16; | |
145 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
146 | reorder' and `.set noreorder'. */ | |
147 | int noreorder; | |
148 | /* Non-zero if we should not permit the $at ($1) register to be used | |
149 | in instructions. Changed by `.set at' and `.set noat'. */ | |
150 | int noat; | |
151 | /* Non-zero if we should warn when a macro instruction expands into | |
152 | more than one machine instruction. Changed by `.set nomacro' and | |
153 | `.set macro'. */ | |
154 | int warn_about_macros; | |
155 | /* Non-zero if we should not move instructions. Changed by `.set | |
156 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
157 | int nomove; | |
158 | /* Non-zero if we should not optimize branches by moving the target | |
159 | of the branch into the delay slot. Actually, we don't perform | |
160 | this optimization anyhow. Changed by `.set bopt' and `.set | |
161 | nobopt'. */ | |
162 | int nobopt; | |
163 | /* Non-zero if we should not autoextend mips16 instructions. | |
164 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
165 | int noautoextend; | |
a325df1d TS |
166 | /* Restrict general purpose registers and floating point registers |
167 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
168 | is passed but can changed if the assembler code uses .set mipsN. */ | |
169 | int gp32; | |
170 | int fp32; | |
171 | /* The ABI currently in use. This is changed by .set mipsN to loosen | |
172 | restrictions and doesn't affect the whole file. */ | |
173 | enum mips_abi_level abi; | |
252b5132 RH |
174 | }; |
175 | ||
a325df1d TS |
176 | /* True if -mgp32 was passed. */ |
177 | static int file_mips_gp32 = 0; | |
178 | ||
179 | /* True if -mfp32 was passed. */ | |
180 | static int file_mips_fp32 = 0; | |
181 | ||
252b5132 | 182 | /* This is the struct we use to hold the current set of options. Note |
e7af610e NC |
183 | that we must set the isa field to ISA_UNKNOWN and the mips16 field to |
184 | -1 to indicate that they have not been initialized. */ | |
252b5132 | 185 | |
e972090a NC |
186 | static struct mips_set_options mips_opts = |
187 | { | |
a325df1d | 188 | ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI |
e7af610e | 189 | }; |
252b5132 RH |
190 | |
191 | /* These variables are filled in with the masks of registers used. | |
192 | The object format code reads them and puts them in the appropriate | |
193 | place. */ | |
194 | unsigned long mips_gprmask; | |
195 | unsigned long mips_cprmask[4]; | |
196 | ||
197 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 198 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 199 | |
ec68c924 | 200 | /* The argument of the -mcpu= flag. Historical for code generation. */ |
e7af610e | 201 | static int mips_cpu = CPU_UNKNOWN; |
252b5132 | 202 | |
ec68c924 EC |
203 | /* The argument of the -march= flag. The architecture we are assembling. */ |
204 | static int mips_arch = CPU_UNKNOWN; | |
205 | ||
206 | /* The argument of the -mtune= flag. The architecture for which we | |
207 | are optimizing. */ | |
208 | static int mips_tune = CPU_UNKNOWN; | |
209 | ||
2f4dcb11 | 210 | /* Whether we should mark the file EABI64 or EABI32. */ |
252b5132 RH |
211 | static int mips_eabi64 = 0; |
212 | ||
213 | /* If they asked for mips1 or mips2 and a cpu that is | |
bdaaa2e1 | 214 | mips3 or greater, then mark the object file 32BITMODE. */ |
252b5132 RH |
215 | static int mips_32bitmode = 0; |
216 | ||
9ce8a5dd GRK |
217 | /* Some ISA's have delay slots for instructions which read or write |
218 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 219 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
220 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
221 | delay slot in this ISA. The uses of this macro assume that any | |
222 | ISA that has delay slots for one of these, has them for all. They | |
223 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 224 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 225 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
226 | (ISA) == ISA_MIPS1 \ |
227 | || (ISA) == ISA_MIPS2 \ | |
228 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
229 | ) |
230 | ||
bdaaa2e1 | 231 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 232 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
233 | (ISA) == ISA_MIPS3 \ |
234 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 235 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 236 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
237 | ) |
238 | ||
e013f690 | 239 | #define HAVE_32BIT_GPRS \ |
a325df1d TS |
240 | (mips_opts.gp32 \ |
241 | || mips_opts.abi == O32_ABI \ | |
e013f690 | 242 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 243 | |
e013f690 | 244 | #define HAVE_32BIT_FPRS \ |
a325df1d TS |
245 | (mips_opts.fp32 \ |
246 | || mips_opts.abi == O32_ABI \ | |
e013f690 | 247 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
248 | |
249 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
250 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
251 | ||
a325df1d | 252 | #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI) |
e013f690 | 253 | |
a325df1d | 254 | #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI) |
e013f690 TS |
255 | |
256 | /* We can only have 64bit addresses if the object file format | |
257 | supports it. */ | |
afdbd6d0 CD |
258 | #define HAVE_32BIT_ADDRESSES \ |
259 | (HAVE_32BIT_GPRS \ | |
260 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
261 | || ! HAVE_64BIT_OBJECTS) \ | |
262 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
263 | |
264 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 265 | |
bdaaa2e1 | 266 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 267 | reads from the HI and LO registers, and thus does not |
ec68c924 | 268 | require nops to be inserted. */ |
252b5132 | 269 | |
ec68c924 | 270 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
0a758a12 | 271 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
272 | ) |
273 | ||
274 | /* Whether the processor uses hardware interlocks to protect reads | |
275 | from the GPRs, and thus does not require nops to be inserted. */ | |
276 | #define gpr_interlocks \ | |
e7af610e | 277 | (mips_opts.isa != ISA_MIPS1 \ |
ec68c924 | 278 | || mips_arch == CPU_R3900) |
252b5132 RH |
279 | |
280 | /* As with other "interlocks" this is used by hardware that has FP | |
281 | (co-processor) interlocks. */ | |
bdaaa2e1 | 282 | /* Itbl support may require additional care here. */ |
ec68c924 | 283 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
0a758a12 | 284 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
285 | ) |
286 | ||
6b76fefe CM |
287 | /* Is this a mfhi or mflo instruction? */ |
288 | #define MF_HILO_INSN(PINFO) \ | |
289 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
290 | ||
252b5132 RH |
291 | /* MIPS PIC level. */ |
292 | ||
e972090a NC |
293 | enum mips_pic_level |
294 | { | |
252b5132 RH |
295 | /* Do not generate PIC code. */ |
296 | NO_PIC, | |
297 | ||
298 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
299 | not sure what it is supposed to do. */ | |
300 | IRIX4_PIC, | |
301 | ||
302 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
303 | SVR4_PIC, | |
304 | ||
305 | /* Generate PIC code without using a global offset table: the data | |
306 | segment has a maximum size of 64K, all data references are off | |
307 | the $gp register, and all text references are PC relative. This | |
308 | is used on some embedded systems. */ | |
309 | EMBEDDED_PIC | |
310 | }; | |
311 | ||
312 | static enum mips_pic_level mips_pic; | |
313 | ||
39c0a331 L |
314 | /* Warn about all NOPS that the assembler generates. */ |
315 | static int warn_nops = 0; | |
316 | ||
252b5132 RH |
317 | /* 1 if we should generate 32 bit offsets from the GP register in |
318 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
319 | static int mips_big_got; | |
320 | ||
321 | /* 1 if trap instructions should used for overflow rather than break | |
322 | instructions. */ | |
323 | static int mips_trap; | |
324 | ||
119d663a | 325 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 326 | by assembling two single width halves into two single width floating |
119d663a NC |
327 | point registers which just happen to alias the double width destination |
328 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 329 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
330 | automatically at assemble time. */ |
331 | static int mips_disable_float_construction; | |
332 | ||
252b5132 RH |
333 | /* Non-zero if any .set noreorder directives were used. */ |
334 | ||
335 | static int mips_any_noreorder; | |
336 | ||
6b76fefe CM |
337 | /* Non-zero if nops should be inserted when the register referenced in |
338 | an mfhi/mflo instruction is read in the next two instructions. */ | |
339 | static int mips_7000_hilo_fix; | |
340 | ||
252b5132 | 341 | /* The size of the small data section. */ |
156c2f8b | 342 | static unsigned int g_switch_value = 8; |
252b5132 RH |
343 | /* Whether the -G option was used. */ |
344 | static int g_switch_seen = 0; | |
345 | ||
346 | #define N_RMASK 0xc4 | |
347 | #define N_VFP 0xd4 | |
348 | ||
349 | /* If we can determine in advance that GP optimization won't be | |
350 | possible, we can skip the relaxation stuff that tries to produce | |
351 | GP-relative references. This makes delay slot optimization work | |
352 | better. | |
353 | ||
354 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
355 | gcc output. It needs to guess right for gcc, otherwise gcc |
356 | will put what it thinks is a GP-relative instruction in a branch | |
357 | delay slot. | |
252b5132 RH |
358 | |
359 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
360 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
361 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
362 | ||
363 | /* handle of the OPCODE hash table */ | |
364 | static struct hash_control *op_hash = NULL; | |
365 | ||
366 | /* The opcode hash table we use for the mips16. */ | |
367 | static struct hash_control *mips16_op_hash = NULL; | |
368 | ||
369 | /* This array holds the chars that always start a comment. If the | |
370 | pre-processor is disabled, these aren't very useful */ | |
371 | const char comment_chars[] = "#"; | |
372 | ||
373 | /* This array holds the chars that only start a comment at the beginning of | |
374 | a line. If the line seems to have the form '# 123 filename' | |
375 | .line and .file directives will appear in the pre-processed output */ | |
376 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
377 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 378 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
379 | /* Also note that C style comments are always supported. */ |
380 | const char line_comment_chars[] = "#"; | |
381 | ||
bdaaa2e1 | 382 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 383 | const char line_separator_chars[] = ";"; |
252b5132 RH |
384 | |
385 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
386 | const char EXP_CHARS[] = "eE"; | |
387 | ||
388 | /* Chars that mean this number is a floating point constant */ | |
389 | /* As in 0f12.456 */ | |
390 | /* or 0d1.2345e12 */ | |
391 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
392 | ||
393 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
394 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
395 | but nothing is ideal around here. | |
396 | */ | |
397 | ||
398 | static char *insn_error; | |
399 | ||
400 | static int auto_align = 1; | |
401 | ||
402 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
403 | offset in the stack frame from which to restore the $gp register. | |
404 | This is set by the .cprestore pseudo-op, and saved in this | |
405 | variable. */ | |
406 | static offsetT mips_cprestore_offset = -1; | |
407 | ||
6478892d TS |
408 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
409 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 410 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
411 | static offsetT mips_cpreturn_offset = -1; |
412 | static int mips_cpreturn_register = -1; | |
413 | static int mips_gp_register = GP; | |
414 | ||
252b5132 RH |
415 | /* This is the register which holds the stack frame, as set by the |
416 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
417 | static int mips_frame_reg = SP; | |
418 | ||
419 | /* To output NOP instructions correctly, we need to keep information | |
420 | about the previous two instructions. */ | |
421 | ||
422 | /* Whether we are optimizing. The default value of 2 means to remove | |
423 | unneeded NOPs and swap branch instructions when possible. A value | |
424 | of 1 means to not swap branches. A value of 0 means to always | |
425 | insert NOPs. */ | |
426 | static int mips_optimize = 2; | |
427 | ||
428 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
429 | equivalent to seeing no -g option at all. */ | |
430 | static int mips_debug = 0; | |
431 | ||
432 | /* The previous instruction. */ | |
433 | static struct mips_cl_insn prev_insn; | |
434 | ||
435 | /* The instruction before prev_insn. */ | |
436 | static struct mips_cl_insn prev_prev_insn; | |
437 | ||
438 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
439 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 440 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
441 | |
442 | /* Non-zero if prev_insn is valid. */ | |
443 | static int prev_insn_valid; | |
444 | ||
445 | /* The frag for the previous instruction. */ | |
446 | static struct frag *prev_insn_frag; | |
447 | ||
448 | /* The offset into prev_insn_frag for the previous instruction. */ | |
449 | static long prev_insn_where; | |
450 | ||
451 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 452 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
453 | |
454 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 455 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
456 | |
457 | /* Non-zero if the previous instruction was in a delay slot. */ | |
458 | static int prev_insn_is_delay_slot; | |
459 | ||
460 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
461 | static int prev_insn_unreordered; | |
462 | ||
463 | /* Non-zero if the previous instruction uses an extend opcode (if | |
464 | mips16). */ | |
465 | static int prev_insn_extended; | |
466 | ||
467 | /* Non-zero if the previous previous instruction was in a .set | |
468 | noreorder. */ | |
469 | static int prev_prev_insn_unreordered; | |
470 | ||
471 | /* If this is set, it points to a frag holding nop instructions which | |
472 | were inserted before the start of a noreorder section. If those | |
473 | nops turn out to be unnecessary, the size of the frag can be | |
474 | decreased. */ | |
475 | static fragS *prev_nop_frag; | |
476 | ||
477 | /* The number of nop instructions we created in prev_nop_frag. */ | |
478 | static int prev_nop_frag_holds; | |
479 | ||
480 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 481 | prev_nop_frag. */ |
252b5132 RH |
482 | static int prev_nop_frag_required; |
483 | ||
484 | /* The number of instructions we've seen since prev_nop_frag. */ | |
485 | static int prev_nop_frag_since; | |
486 | ||
487 | /* For ECOFF and ELF, relocations against symbols are done in two | |
488 | parts, with a HI relocation and a LO relocation. Each relocation | |
489 | has only 16 bits of space to store an addend. This means that in | |
490 | order for the linker to handle carries correctly, it must be able | |
491 | to locate both the HI and the LO relocation. This means that the | |
492 | relocations must appear in order in the relocation table. | |
493 | ||
494 | In order to implement this, we keep track of each unmatched HI | |
495 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 496 | corresponding LO relocation. */ |
252b5132 | 497 | |
e972090a NC |
498 | struct mips_hi_fixup |
499 | { | |
252b5132 RH |
500 | /* Next HI fixup. */ |
501 | struct mips_hi_fixup *next; | |
502 | /* This fixup. */ | |
503 | fixS *fixp; | |
504 | /* The section this fixup is in. */ | |
505 | segT seg; | |
506 | }; | |
507 | ||
508 | /* The list of unmatched HI relocs. */ | |
509 | ||
510 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
511 | ||
512 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
513 | ||
514 | #define X ILLEGAL_REG | |
e972090a NC |
515 | static const int mips32_to_16_reg_map[] = |
516 | { | |
252b5132 RH |
517 | X, X, 2, 3, 4, 5, 6, 7, |
518 | X, X, X, X, X, X, X, X, | |
519 | 0, 1, X, X, X, X, X, X, | |
520 | X, X, X, X, X, X, X, X | |
521 | }; | |
522 | #undef X | |
523 | ||
524 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
525 | ||
e972090a NC |
526 | static const unsigned int mips16_to_32_reg_map[] = |
527 | { | |
252b5132 RH |
528 | 16, 17, 2, 3, 4, 5, 6, 7 |
529 | }; | |
530 | \f | |
531 | /* Since the MIPS does not have multiple forms of PC relative | |
532 | instructions, we do not have to do relaxing as is done on other | |
533 | platforms. However, we do have to handle GP relative addressing | |
534 | correctly, which turns out to be a similar problem. | |
535 | ||
536 | Every macro that refers to a symbol can occur in (at least) two | |
537 | forms, one with GP relative addressing and one without. For | |
538 | example, loading a global variable into a register generally uses | |
539 | a macro instruction like this: | |
540 | lw $4,i | |
541 | If i can be addressed off the GP register (this is true if it is in | |
542 | the .sbss or .sdata section, or if it is known to be smaller than | |
543 | the -G argument) this will generate the following instruction: | |
544 | lw $4,i($gp) | |
545 | This instruction will use a GPREL reloc. If i can not be addressed | |
546 | off the GP register, the following instruction sequence will be used: | |
547 | lui $at,i | |
548 | lw $4,i($at) | |
549 | In this case the first instruction will have a HI16 reloc, and the | |
550 | second reloc will have a LO16 reloc. Both relocs will be against | |
551 | the symbol i. | |
552 | ||
553 | The issue here is that we may not know whether i is GP addressable | |
554 | until after we see the instruction that uses it. Therefore, we | |
555 | want to be able to choose the final instruction sequence only at | |
556 | the end of the assembly. This is similar to the way other | |
557 | platforms choose the size of a PC relative instruction only at the | |
558 | end of assembly. | |
559 | ||
560 | When generating position independent code we do not use GP | |
561 | addressing in quite the same way, but the issue still arises as | |
562 | external symbols and local symbols must be handled differently. | |
563 | ||
564 | We handle these issues by actually generating both possible | |
565 | instruction sequences. The longer one is put in a frag_var with | |
566 | type rs_machine_dependent. We encode what to do with the frag in | |
567 | the subtype field. We encode (1) the number of existing bytes to | |
568 | replace, (2) the number of new bytes to use, (3) the offset from | |
569 | the start of the existing bytes to the first reloc we must generate | |
570 | (that is, the offset is applied from the start of the existing | |
571 | bytes after they are replaced by the new bytes, if any), (4) the | |
572 | offset from the start of the existing bytes to the second reloc, | |
573 | (5) whether a third reloc is needed (the third reloc is always four | |
574 | bytes after the second reloc), and (6) whether to warn if this | |
575 | variant is used (this is sometimes needed if .set nomacro or .set | |
576 | noat is in effect). All these numbers are reasonably small. | |
577 | ||
578 | Generating two instruction sequences must be handled carefully to | |
579 | ensure that delay slots are handled correctly. Fortunately, there | |
580 | are a limited number of cases. When the second instruction | |
581 | sequence is generated, append_insn is directed to maintain the | |
582 | existing delay slot information, so it continues to apply to any | |
583 | code after the second instruction sequence. This means that the | |
584 | second instruction sequence must not impose any requirements not | |
585 | required by the first instruction sequence. | |
586 | ||
587 | These variant frags are then handled in functions called by the | |
588 | machine independent code. md_estimate_size_before_relax returns | |
589 | the final size of the frag. md_convert_frag sets up the final form | |
590 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
591 | one if needed. */ | |
592 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
593 | ((relax_substateT) \ | |
594 | (((old) << 23) \ | |
595 | | ((new) << 16) \ | |
596 | | (((reloc1) + 64) << 9) \ | |
597 | | (((reloc2) + 64) << 2) \ | |
598 | | ((reloc3) ? (1 << 1) : 0) \ | |
599 | | ((warn) ? 1 : 0))) | |
600 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
601 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
602 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
603 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
604 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
605 | #define RELAX_WARN(i) ((i) & 1) | |
606 | ||
607 | /* For mips16 code, we use an entirely different form of relaxation. | |
608 | mips16 supports two versions of most instructions which take | |
609 | immediate values: a small one which takes some small value, and a | |
610 | larger one which takes a 16 bit value. Since branches also follow | |
611 | this pattern, relaxing these values is required. | |
612 | ||
613 | We can assemble both mips16 and normal MIPS code in a single | |
614 | object. Therefore, we need to support this type of relaxation at | |
615 | the same time that we support the relaxation described above. We | |
616 | use the high bit of the subtype field to distinguish these cases. | |
617 | ||
618 | The information we store for this type of relaxation is the | |
619 | argument code found in the opcode file for this relocation, whether | |
620 | the user explicitly requested a small or extended form, and whether | |
621 | the relocation is in a jump or jal delay slot. That tells us the | |
622 | size of the value, and how it should be stored. We also store | |
623 | whether the fragment is considered to be extended or not. We also | |
624 | store whether this is known to be a branch to a different section, | |
625 | whether we have tried to relax this frag yet, and whether we have | |
626 | ever extended a PC relative fragment because of a shift count. */ | |
627 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
628 | (0x80000000 \ | |
629 | | ((type) & 0xff) \ | |
630 | | ((small) ? 0x100 : 0) \ | |
631 | | ((ext) ? 0x200 : 0) \ | |
632 | | ((dslot) ? 0x400 : 0) \ | |
633 | | ((jal_dslot) ? 0x800 : 0)) | |
634 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
635 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
636 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
637 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
638 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
639 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
640 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
641 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
642 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
643 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
644 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
645 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
646 | \f | |
647 | /* Prototypes for static functions. */ | |
648 | ||
649 | #ifdef __STDC__ | |
650 | #define internalError() \ | |
651 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
652 | #else | |
653 | #define internalError() as_fatal (_("MIPS internal Error")); | |
654 | #endif | |
655 | ||
656 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
657 | ||
658 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
659 | unsigned int reg, enum mips_regclass class)); | |
156c2f8b | 660 | static int reg_needs_delay PARAMS ((unsigned int)); |
252b5132 RH |
661 | static void mips16_mark_labels PARAMS ((void)); |
662 | static void append_insn PARAMS ((char *place, | |
663 | struct mips_cl_insn * ip, | |
664 | expressionS * p, | |
f6688943 | 665 | bfd_reloc_code_real_type *r, |
252b5132 RH |
666 | boolean)); |
667 | static void mips_no_prev_insn PARAMS ((int)); | |
668 | static void mips_emit_delays PARAMS ((boolean)); | |
669 | #ifdef USE_STDARG | |
670 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
671 | const char *name, const char *fmt, | |
672 | ...)); | |
673 | #else | |
674 | static void macro_build (); | |
675 | #endif | |
676 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
677 | const char *, const char *, | |
678 | va_list)); | |
679 | static void macro_build_lui PARAMS ((char *place, int *counter, | |
680 | expressionS * ep, int regnum)); | |
681 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
682 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
683 | expressionS *)); | |
684 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
d6bc6245 | 685 | static void load_address PARAMS ((int *, int, expressionS *, int, int *)); |
ea1fb5dc | 686 | static void move_register PARAMS ((int *, int, int)); |
252b5132 RH |
687 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
688 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
689 | #ifdef LOSING_COMPILER | |
690 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
691 | #endif | |
692 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
693 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
694 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
695 | boolean, boolean, unsigned long *, | |
696 | boolean *, unsigned short *)); | |
ad8d3bb3 TS |
697 | static int my_getSmallParser PARAMS ((char **, unsigned int *, int *)); |
698 | static int my_getSmallExpression PARAMS ((expressionS *, char *)); | |
699 | static void my_getExpression PARAMS ((expressionS *, char *)); | |
ae948b86 | 700 | #ifdef OBJ_ELF |
e013f690 | 701 | static int support_64bit_objects PARAMS((void)); |
ae948b86 | 702 | #endif |
252b5132 RH |
703 | static symbolS *get_symbol PARAMS ((void)); |
704 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
705 | static void s_align PARAMS ((int)); | |
706 | static void s_change_sec PARAMS ((int)); | |
707 | static void s_cons PARAMS ((int)); | |
708 | static void s_float_cons PARAMS ((int)); | |
709 | static void s_mips_globl PARAMS ((int)); | |
710 | static void s_option PARAMS ((int)); | |
711 | static void s_mipsset PARAMS ((int)); | |
712 | static void s_abicalls PARAMS ((int)); | |
713 | static void s_cpload PARAMS ((int)); | |
6478892d TS |
714 | static void s_cpsetup PARAMS ((int)); |
715 | static void s_cplocal PARAMS ((int)); | |
252b5132 | 716 | static void s_cprestore PARAMS ((int)); |
6478892d TS |
717 | static void s_cpreturn PARAMS ((int)); |
718 | static void s_gpvalue PARAMS ((int)); | |
252b5132 RH |
719 | static void s_gpword PARAMS ((int)); |
720 | static void s_cpadd PARAMS ((int)); | |
721 | static void s_insn PARAMS ((int)); | |
722 | static void md_obj_begin PARAMS ((void)); | |
723 | static void md_obj_end PARAMS ((void)); | |
724 | static long get_number PARAMS ((void)); | |
725 | static void s_mips_ent PARAMS ((int)); | |
726 | static void s_mips_end PARAMS ((int)); | |
727 | static void s_mips_frame PARAMS ((int)); | |
728 | static void s_mips_mask PARAMS ((int)); | |
729 | static void s_mips_stab PARAMS ((int)); | |
730 | static void s_mips_weakext PARAMS ((int)); | |
731 | static void s_file PARAMS ((int)); | |
732 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
e7af610e NC |
733 | static const char *mips_isa_to_str PARAMS ((int)); |
734 | static const char *mips_cpu_to_str PARAMS ((int)); | |
252b5132 | 735 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
e87a0284 | 736 | static void show PARAMS ((FILE *, char *, int *, int *)); |
add55e1f RS |
737 | #ifdef OBJ_ELF |
738 | static int mips_need_elf_addend_fixup PARAMS ((fixS *)); | |
739 | #endif | |
e7af610e | 740 | |
ad8d3bb3 | 741 | /* Return values of my_getSmallExpression(). */ |
fb1b3232 | 742 | |
ad8d3bb3 | 743 | enum small_ex_type |
fb1b3232 TS |
744 | { |
745 | S_EX_NONE = 0, | |
ad8d3bb3 TS |
746 | S_EX_REGISTER, |
747 | ||
748 | /* Direct relocation creation by %percent_op(). */ | |
749 | S_EX_HALF, | |
fb1b3232 | 750 | S_EX_HI, |
ad8d3bb3 TS |
751 | S_EX_LO, |
752 | S_EX_GP_REL, | |
753 | S_EX_GOT, | |
754 | S_EX_CALL16, | |
755 | S_EX_GOT_DISP, | |
756 | S_EX_GOT_PAGE, | |
757 | S_EX_GOT_OFST, | |
758 | S_EX_GOT_HI, | |
759 | S_EX_GOT_LO, | |
760 | S_EX_NEG, | |
fb1b3232 TS |
761 | S_EX_HIGHER, |
762 | S_EX_HIGHEST, | |
ad8d3bb3 TS |
763 | S_EX_CALL_HI, |
764 | S_EX_CALL_LO | |
fb1b3232 TS |
765 | }; |
766 | ||
e7af610e NC |
767 | /* Table and functions used to map between CPU/ISA names, and |
768 | ISA levels, and CPU numbers. */ | |
769 | ||
e972090a NC |
770 | struct mips_cpu_info |
771 | { | |
e7af610e NC |
772 | const char *name; /* CPU or ISA name. */ |
773 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
774 | int isa; /* ISA level. */ | |
775 | int cpu; /* CPU number (default CPU if ISA). */ | |
776 | }; | |
777 | ||
778 | static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); | |
779 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); | |
780 | static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); | |
252b5132 RH |
781 | \f |
782 | /* Pseudo-op table. | |
783 | ||
784 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
785 | should be defined here, but are currently unsupported: .alias, | |
786 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
787 | ||
788 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
789 | specific to the type of debugging information being generated, and | |
790 | should be defined by the object format: .aent, .begin, .bend, | |
791 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
792 | .vreg. | |
793 | ||
794 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
795 | not MIPS CPU specific, but are also not specific to the object file | |
796 | format. This file is probably the best place to define them, but | |
797 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
798 | .struct. */ | |
799 | ||
e972090a NC |
800 | static const pseudo_typeS mips_pseudo_table[] = |
801 | { | |
beae10d5 | 802 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
803 | {"option", s_option, 0}, |
804 | {"set", s_mipsset, 0}, | |
805 | {"rdata", s_change_sec, 'r'}, | |
806 | {"sdata", s_change_sec, 's'}, | |
807 | {"livereg", s_ignore, 0}, | |
808 | {"abicalls", s_abicalls, 0}, | |
809 | {"cpload", s_cpload, 0}, | |
6478892d TS |
810 | {"cpsetup", s_cpsetup, 0}, |
811 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 812 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
813 | {"cpreturn", s_cpreturn, 0}, |
814 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 RH |
815 | {"gpword", s_gpword, 0}, |
816 | {"cpadd", s_cpadd, 0}, | |
817 | {"insn", s_insn, 0}, | |
818 | ||
beae10d5 | 819 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
820 | chips. */ |
821 | {"asciiz", stringer, 1}, | |
822 | {"bss", s_change_sec, 'b'}, | |
823 | {"err", s_err, 0}, | |
824 | {"half", s_cons, 1}, | |
825 | {"dword", s_cons, 3}, | |
826 | {"weakext", s_mips_weakext, 0}, | |
827 | ||
beae10d5 | 828 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
829 | here for one reason or another. */ |
830 | {"align", s_align, 0}, | |
831 | {"byte", s_cons, 0}, | |
832 | {"data", s_change_sec, 'd'}, | |
833 | {"double", s_float_cons, 'd'}, | |
834 | {"float", s_float_cons, 'f'}, | |
835 | {"globl", s_mips_globl, 0}, | |
836 | {"global", s_mips_globl, 0}, | |
837 | {"hword", s_cons, 1}, | |
838 | {"int", s_cons, 2}, | |
839 | {"long", s_cons, 2}, | |
840 | {"octa", s_cons, 4}, | |
841 | {"quad", s_cons, 3}, | |
842 | {"short", s_cons, 1}, | |
843 | {"single", s_float_cons, 'f'}, | |
844 | {"stabn", s_mips_stab, 'n'}, | |
845 | {"text", s_change_sec, 't'}, | |
846 | {"word", s_cons, 2}, | |
add56521 L |
847 | |
848 | #ifdef MIPS_STABS_ELF | |
849 | { "extern", ecoff_directive_extern, 0}, | |
850 | #endif | |
851 | ||
43841e91 | 852 | { NULL, NULL, 0 }, |
252b5132 RH |
853 | }; |
854 | ||
e972090a NC |
855 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
856 | { | |
beae10d5 KH |
857 | /* These pseudo-ops should be defined by the object file format. |
858 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
859 | {"aent", s_mips_ent, 1}, |
860 | {"bgnb", s_ignore, 0}, | |
861 | {"end", s_mips_end, 0}, | |
862 | {"endb", s_ignore, 0}, | |
863 | {"ent", s_mips_ent, 0}, | |
864 | {"file", s_file, 0}, | |
865 | {"fmask", s_mips_mask, 'F'}, | |
866 | {"frame", s_mips_frame, 0}, | |
867 | {"loc", s_ignore, 0}, | |
868 | {"mask", s_mips_mask, 'R'}, | |
869 | {"verstamp", s_ignore, 0}, | |
43841e91 | 870 | { NULL, NULL, 0 }, |
252b5132 RH |
871 | }; |
872 | ||
873 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
874 | ||
875 | void | |
876 | mips_pop_insert () | |
877 | { | |
878 | pop_insert (mips_pseudo_table); | |
879 | if (! ECOFF_DEBUGGING) | |
880 | pop_insert (mips_nonecoff_pseudo_table); | |
881 | } | |
882 | \f | |
883 | /* Symbols labelling the current insn. */ | |
884 | ||
e972090a NC |
885 | struct insn_label_list |
886 | { | |
252b5132 RH |
887 | struct insn_label_list *next; |
888 | symbolS *label; | |
889 | }; | |
890 | ||
891 | static struct insn_label_list *insn_labels; | |
892 | static struct insn_label_list *free_insn_labels; | |
893 | ||
894 | static void mips_clear_insn_labels PARAMS ((void)); | |
895 | ||
896 | static inline void | |
897 | mips_clear_insn_labels () | |
898 | { | |
899 | register struct insn_label_list **pl; | |
900 | ||
901 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
902 | ; | |
903 | *pl = insn_labels; | |
904 | insn_labels = NULL; | |
905 | } | |
906 | \f | |
907 | static char *expr_end; | |
908 | ||
909 | /* Expressions which appear in instructions. These are set by | |
910 | mips_ip. */ | |
911 | ||
912 | static expressionS imm_expr; | |
913 | static expressionS offset_expr; | |
914 | ||
915 | /* Relocs associated with imm_expr and offset_expr. */ | |
916 | ||
f6688943 TS |
917 | static bfd_reloc_code_real_type imm_reloc[3] |
918 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
919 | static bfd_reloc_code_real_type offset_reloc[3] | |
920 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
921 | |
922 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
923 | ||
924 | static boolean imm_unmatched_hi; | |
925 | ||
926 | /* These are set by mips16_ip if an explicit extension is used. */ | |
927 | ||
928 | static boolean mips16_small, mips16_ext; | |
929 | ||
930 | #ifdef MIPS_STABS_ELF | |
931 | /* The pdr segment for per procedure frame/regmask info */ | |
932 | ||
933 | static segT pdr_seg; | |
934 | #endif | |
935 | ||
e7af610e NC |
936 | static const char * |
937 | mips_isa_to_str (isa) | |
938 | int isa; | |
939 | { | |
940 | const struct mips_cpu_info *ci; | |
941 | static char s[20]; | |
942 | ||
943 | ci = mips_cpu_info_from_isa (isa); | |
944 | if (ci != NULL) | |
945 | return (ci->name); | |
946 | ||
947 | sprintf (s, "ISA#%d", isa); | |
948 | return s; | |
949 | } | |
950 | ||
951 | static const char * | |
156c2f8b NC |
952 | mips_cpu_to_str (cpu) |
953 | int cpu; | |
954 | { | |
e7af610e | 955 | const struct mips_cpu_info *ci; |
156c2f8b | 956 | static char s[16]; |
e7af610e NC |
957 | |
958 | ci = mips_cpu_info_from_cpu (cpu); | |
959 | if (ci != NULL) | |
960 | return (ci->name); | |
961 | ||
962 | sprintf (s, "CPU#%d", cpu); | |
963 | return s; | |
156c2f8b NC |
964 | } |
965 | ||
e013f690 TS |
966 | /* The default target format to use. */ |
967 | ||
968 | const char * | |
969 | mips_target_format () | |
970 | { | |
971 | switch (OUTPUT_FLAVOR) | |
972 | { | |
973 | case bfd_target_aout_flavour: | |
974 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
975 | case bfd_target_ecoff_flavour: | |
976 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
977 | case bfd_target_coff_flavour: | |
978 | return "pe-mips"; | |
979 | case bfd_target_elf_flavour: | |
980 | #ifdef TE_TMIPS | |
981 | /* This is traditional mips */ | |
982 | return (target_big_endian | |
983 | ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips" | |
984 | : "elf32-tradbigmips") | |
985 | : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips" | |
986 | : "elf32-tradlittlemips")); | |
987 | #else | |
988 | return (target_big_endian | |
989 | ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips") | |
990 | : (HAVE_64BIT_OBJECTS ? "elf64-littlemips" | |
991 | : "elf32-littlemips")); | |
992 | #endif | |
993 | default: | |
994 | abort (); | |
995 | return NULL; | |
996 | } | |
997 | } | |
998 | ||
156c2f8b NC |
999 | /* This function is called once, at assembler startup time. It should |
1000 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1001 | ||
252b5132 RH |
1002 | void |
1003 | md_begin () | |
1004 | { | |
252b5132 | 1005 | register const char *retval = NULL; |
156c2f8b | 1006 | int i = 0; |
252b5132 RH |
1007 | const char *cpu; |
1008 | char *a = NULL; | |
1009 | int broken = 0; | |
1010 | int mips_isa_from_cpu; | |
e7af610e NC |
1011 | int target_cpu_had_mips16 = 0; |
1012 | const struct mips_cpu_info *ci; | |
252b5132 | 1013 | |
056350c6 NC |
1014 | /* GP relative stuff not working for PE */ |
1015 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
1016 | && g_switch_value != 0) | |
1017 | { | |
1018 | if (g_switch_seen) | |
1019 | as_bad (_("-G not supported in this configuration.")); | |
1020 | g_switch_value = 0; | |
1021 | } | |
1022 | ||
252b5132 RH |
1023 | cpu = TARGET_CPU; |
1024 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
1025 | { | |
1026 | a = xmalloc (sizeof TARGET_CPU); | |
1027 | strcpy (a, TARGET_CPU); | |
1028 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
1029 | cpu = a; | |
1030 | } | |
1031 | ||
e7af610e | 1032 | if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) |
252b5132 | 1033 | { |
e7af610e NC |
1034 | target_cpu_had_mips16 = 1; |
1035 | cpu += sizeof "mips16" - 1; | |
252b5132 RH |
1036 | } |
1037 | ||
e7af610e NC |
1038 | if (mips_opts.mips16 < 0) |
1039 | mips_opts.mips16 = target_cpu_had_mips16; | |
252b5132 | 1040 | |
6dce9e24 TS |
1041 | /* Backward compatibility for historic -mcpu= option. Check for |
1042 | incompatible options, warn if -mcpu is used. */ | |
1043 | if (mips_cpu != CPU_UNKNOWN | |
1044 | && mips_arch != CPU_UNKNOWN | |
1045 | && mips_cpu != mips_arch) | |
1046 | { | |
1047 | as_fatal (_("The -mcpu option can't be used together with -march. " | |
1048 | "Use -mtune instead of -mcpu.")); | |
1049 | } | |
1050 | ||
1051 | if (mips_cpu != CPU_UNKNOWN | |
1052 | && mips_tune != CPU_UNKNOWN | |
1053 | && mips_cpu != mips_tune) | |
1054 | { | |
1055 | as_fatal (_("The -mcpu option can't be used together with -mtune. " | |
1056 | "Use -march instead of -mcpu.")); | |
1057 | } | |
1058 | ||
1059 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) | |
1060 | { | |
1061 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1062 | assert (ci != NULL); | |
1063 | mips_arch = ci->cpu; | |
1064 | as_warn (_("The -mcpu option is deprecated. Please use -march and " | |
1065 | "-mtune instead.")); | |
1066 | } | |
1067 | ||
ec68c924 | 1068 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was |
e7af610e NC |
1069 | specified on the command line, or some other value if one was. |
1070 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
1071 | the command line, or will be set otherwise if one was. */ | |
ec68c924 | 1072 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
252b5132 | 1073 | { |
1ff54a84 TS |
1074 | /* We have to check if the isa is the default isa of arch. Otherwise |
1075 | we'll get invalid object file headers. */ | |
1076 | ci = mips_cpu_info_from_cpu (mips_arch); | |
1077 | assert (ci != NULL); | |
1078 | if (mips_opts.isa != ci->isa) | |
1079 | { | |
1080 | /* This really should be an error instead of a warning, but old | |
1081 | compilers only have -mcpu which sets both arch and tune. For | |
1082 | now, we discard arch and preserve tune. */ | |
1083 | as_warn (_("The -march option is incompatible to -mipsN and " | |
1084 | "therefore ignored.")); | |
1085 | if (mips_tune == CPU_UNKNOWN) | |
1086 | mips_tune = mips_arch; | |
1087 | ci = mips_cpu_info_from_isa (mips_opts.isa); | |
1088 | assert (ci != NULL); | |
1089 | mips_arch = ci->cpu; | |
1090 | } | |
252b5132 | 1091 | } |
ec68c924 | 1092 | else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) |
252b5132 | 1093 | { |
ec68c924 EC |
1094 | /* We have ARCH, we need ISA. */ |
1095 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1096 | assert (ci != NULL); |
1097 | mips_opts.isa = ci->isa; | |
1098 | } | |
ec68c924 | 1099 | else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
e7af610e | 1100 | { |
ec68c924 | 1101 | /* We have ISA, we need default ARCH. */ |
e7af610e NC |
1102 | ci = mips_cpu_info_from_isa (mips_opts.isa); |
1103 | assert (ci != NULL); | |
ec68c924 EC |
1104 | mips_arch = ci->cpu; |
1105 | } | |
e7af610e NC |
1106 | else |
1107 | { | |
ec68c924 | 1108 | /* We need to set both ISA and ARCH from target cpu. */ |
e7af610e NC |
1109 | ci = mips_cpu_info_from_name (cpu); |
1110 | if (ci == NULL) | |
beae10d5 | 1111 | ci = mips_cpu_info_from_cpu (CPU_R3000); |
e7af610e NC |
1112 | assert (ci != NULL); |
1113 | mips_opts.isa = ci->isa; | |
ec68c924 | 1114 | mips_arch = ci->cpu; |
252b5132 RH |
1115 | } |
1116 | ||
ec68c924 EC |
1117 | if (mips_tune == CPU_UNKNOWN) |
1118 | mips_tune = mips_arch; | |
1119 | ||
1120 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1121 | assert (ci != NULL); |
1122 | mips_isa_from_cpu = ci->isa; | |
1123 | ||
252b5132 | 1124 | /* End of TARGET_CPU processing, get rid of malloced memory |
bdaaa2e1 | 1125 | if necessary. */ |
252b5132 RH |
1126 | cpu = NULL; |
1127 | if (a != NULL) | |
1128 | { | |
156c2f8b NC |
1129 | free (a); |
1130 | a = NULL; | |
252b5132 RH |
1131 | } |
1132 | ||
e7af610e | 1133 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
252b5132 RH |
1134 | as_bad (_("trap exception not supported at ISA 1")); |
1135 | ||
1136 | /* Set the EABI kind based on the ISA before the user gets | |
1137 | to change the ISA with directives. This isn't really | |
bdaaa2e1 | 1138 | the best, but then neither is basing the abi on the isa. */ |
9ce8a5dd | 1139 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
a325df1d | 1140 | && mips_opts.abi == EABI_ABI) |
252b5132 RH |
1141 | mips_eabi64 = 1; |
1142 | ||
e7af610e NC |
1143 | /* If they asked for mips1 or mips2 and a cpu that is |
1144 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1145 | if (mips_isa_from_cpu != ISA_UNKNOWN | |
1146 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) | |
1147 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
1148 | mips_32bitmode = 1; | |
252b5132 | 1149 | |
ec68c924 | 1150 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1151 | as_warn (_("Could not set architecture and machine")); |
1152 | ||
1153 | file_mips_isa = mips_opts.isa; | |
a325df1d TS |
1154 | file_mips_abi = mips_opts.abi; |
1155 | mips_opts.gp32 = file_mips_gp32; | |
1156 | mips_opts.fp32 = file_mips_fp32; | |
252b5132 RH |
1157 | |
1158 | op_hash = hash_new (); | |
1159 | ||
1160 | for (i = 0; i < NUMOPCODES;) | |
1161 | { | |
1162 | const char *name = mips_opcodes[i].name; | |
1163 | ||
1164 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1165 | if (retval != NULL) | |
1166 | { | |
1167 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1168 | mips_opcodes[i].name, retval); | |
1169 | /* Probably a memory allocation problem? Give up now. */ | |
1170 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1171 | } | |
1172 | do | |
1173 | { | |
1174 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1175 | { | |
1176 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1177 | broken = 1; | |
1178 | } | |
1179 | ++i; | |
1180 | } | |
1181 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1182 | } | |
1183 | ||
1184 | mips16_op_hash = hash_new (); | |
1185 | ||
1186 | i = 0; | |
1187 | while (i < bfd_mips16_num_opcodes) | |
1188 | { | |
1189 | const char *name = mips16_opcodes[i].name; | |
1190 | ||
1191 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1192 | if (retval != NULL) | |
1193 | as_fatal (_("internal: can't hash `%s': %s"), | |
1194 | mips16_opcodes[i].name, retval); | |
1195 | do | |
1196 | { | |
1197 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1198 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1199 | != mips16_opcodes[i].match)) | |
1200 | { | |
1201 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1202 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1203 | broken = 1; | |
1204 | } | |
1205 | ++i; | |
1206 | } | |
1207 | while (i < bfd_mips16_num_opcodes | |
1208 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1209 | } | |
1210 | ||
1211 | if (broken) | |
1212 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1213 | ||
1214 | /* We add all the general register names to the symbol table. This | |
1215 | helps us detect invalid uses of them. */ | |
1216 | for (i = 0; i < 32; i++) | |
1217 | { | |
1218 | char buf[5]; | |
1219 | ||
1220 | sprintf (buf, "$%d", i); | |
1221 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1222 | &zero_address_frag)); | |
1223 | } | |
1224 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1225 | &zero_address_frag)); | |
1226 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1227 | &zero_address_frag)); | |
1228 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1229 | &zero_address_frag)); | |
1230 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1231 | &zero_address_frag)); | |
1232 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1233 | &zero_address_frag)); | |
1234 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1235 | &zero_address_frag)); | |
1236 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1237 | &zero_address_frag)); | |
1238 | ||
1239 | mips_no_prev_insn (false); | |
1240 | ||
1241 | mips_gprmask = 0; | |
1242 | mips_cprmask[0] = 0; | |
1243 | mips_cprmask[1] = 0; | |
1244 | mips_cprmask[2] = 0; | |
1245 | mips_cprmask[3] = 0; | |
1246 | ||
1247 | /* set the default alignment for the text section (2**2) */ | |
1248 | record_alignment (text_section, 2); | |
1249 | ||
1250 | if (USE_GLOBAL_POINTER_OPT) | |
1251 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1252 | ||
1253 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1254 | { | |
1255 | /* On a native system, sections must be aligned to 16 byte | |
1256 | boundaries. When configured for an embedded ELF target, we | |
1257 | don't bother. */ | |
1258 | if (strcmp (TARGET_OS, "elf") != 0) | |
1259 | { | |
1260 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1261 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1262 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1263 | } | |
1264 | ||
1265 | /* Create a .reginfo section for register masks and a .mdebug | |
1266 | section for debugging information. */ | |
1267 | { | |
1268 | segT seg; | |
1269 | subsegT subseg; | |
1270 | flagword flags; | |
1271 | segT sec; | |
1272 | ||
1273 | seg = now_seg; | |
1274 | subseg = now_subseg; | |
1275 | ||
1276 | /* The ABI says this section should be loaded so that the | |
1277 | running program can access it. However, we don't load it | |
1278 | if we are configured for an embedded target */ | |
1279 | flags = SEC_READONLY | SEC_DATA; | |
1280 | if (strcmp (TARGET_OS, "elf") != 0) | |
1281 | flags |= SEC_ALLOC | SEC_LOAD; | |
1282 | ||
e013f690 | 1283 | if (! HAVE_NEWABI) |
252b5132 RH |
1284 | { |
1285 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1286 | ||
252b5132 RH |
1287 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
1288 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
bdaaa2e1 | 1289 | |
252b5132 RH |
1290 | #ifdef OBJ_ELF |
1291 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1292 | #endif | |
1293 | } | |
1294 | else | |
1295 | { | |
1296 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1297 | .reginfo section. */ | |
1298 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
1299 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
1300 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
1301 | ||
1302 | #ifdef OBJ_ELF | |
1303 | /* Set up the option header. */ | |
1304 | { | |
1305 | Elf_Internal_Options opthdr; | |
1306 | char *f; | |
1307 | ||
1308 | opthdr.kind = ODK_REGINFO; | |
1309 | opthdr.size = (sizeof (Elf_External_Options) | |
1310 | + sizeof (Elf64_External_RegInfo)); | |
1311 | opthdr.section = 0; | |
1312 | opthdr.info = 0; | |
1313 | f = frag_more (sizeof (Elf_External_Options)); | |
1314 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1315 | (Elf_External_Options *) f); | |
1316 | ||
1317 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1318 | } | |
1319 | #endif | |
1320 | } | |
1321 | ||
1322 | if (ECOFF_DEBUGGING) | |
1323 | { | |
1324 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1325 | (void) bfd_set_section_flags (stdoutput, sec, | |
1326 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1327 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1328 | } | |
1329 | ||
1330 | #ifdef MIPS_STABS_ELF | |
1331 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1332 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1333 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1334 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1335 | #endif | |
1336 | ||
1337 | subseg_set (seg, subseg); | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | if (! ECOFF_DEBUGGING) | |
1342 | md_obj_begin (); | |
1343 | } | |
1344 | ||
1345 | void | |
1346 | md_mips_end () | |
1347 | { | |
1348 | if (! ECOFF_DEBUGGING) | |
1349 | md_obj_end (); | |
1350 | } | |
1351 | ||
1352 | void | |
1353 | md_assemble (str) | |
1354 | char *str; | |
1355 | { | |
1356 | struct mips_cl_insn insn; | |
f6688943 TS |
1357 | bfd_reloc_code_real_type unused_reloc[3] |
1358 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1359 | |
1360 | imm_expr.X_op = O_absent; | |
252b5132 RH |
1361 | imm_unmatched_hi = false; |
1362 | offset_expr.X_op = O_absent; | |
f6688943 TS |
1363 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1364 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1365 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1366 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1367 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1368 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1369 | |
1370 | if (mips_opts.mips16) | |
1371 | mips16_ip (str, &insn); | |
1372 | else | |
1373 | { | |
1374 | mips_ip (str, &insn); | |
beae10d5 KH |
1375 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1376 | str, insn.insn_opcode)); | |
252b5132 RH |
1377 | } |
1378 | ||
1379 | if (insn_error) | |
1380 | { | |
1381 | as_bad ("%s `%s'", insn_error, str); | |
1382 | return; | |
1383 | } | |
1384 | ||
1385 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1386 | { | |
1387 | if (mips_opts.mips16) | |
1388 | mips16_macro (&insn); | |
1389 | else | |
1390 | macro (&insn); | |
1391 | } | |
1392 | else | |
1393 | { | |
1394 | if (imm_expr.X_op != O_absent) | |
c4e7957c | 1395 | append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi); |
252b5132 | 1396 | else if (offset_expr.X_op != O_absent) |
c4e7957c | 1397 | append_insn (NULL, &insn, &offset_expr, offset_reloc, false); |
252b5132 | 1398 | else |
c4e7957c | 1399 | append_insn (NULL, &insn, NULL, unused_reloc, false); |
252b5132 RH |
1400 | } |
1401 | } | |
1402 | ||
1403 | /* See whether instruction IP reads register REG. CLASS is the type | |
1404 | of register. */ | |
1405 | ||
1406 | static int | |
1407 | insn_uses_reg (ip, reg, class) | |
1408 | struct mips_cl_insn *ip; | |
1409 | unsigned int reg; | |
1410 | enum mips_regclass class; | |
1411 | { | |
1412 | if (class == MIPS16_REG) | |
1413 | { | |
1414 | assert (mips_opts.mips16); | |
1415 | reg = mips16_to_32_reg_map[reg]; | |
1416 | class = MIPS_GR_REG; | |
1417 | } | |
1418 | ||
1419 | /* Don't report on general register 0, since it never changes. */ | |
1420 | if (class == MIPS_GR_REG && reg == 0) | |
1421 | return 0; | |
1422 | ||
1423 | if (class == MIPS_FP_REG) | |
1424 | { | |
1425 | assert (! mips_opts.mips16); | |
1426 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1427 | This is not optimal, because it will introduce an unnecessary | |
1428 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1429 | need to distinguish reading both $f0 and $f1 or just one of | |
1430 | them. Note that we don't have to check the other way, | |
1431 | because there is no instruction that sets both $f0 and $f1 | |
1432 | and requires a delay. */ | |
1433 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1434 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1435 | == (reg &~ (unsigned) 1))) | |
1436 | return 1; | |
1437 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1438 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1439 | == (reg &~ (unsigned) 1))) | |
1440 | return 1; | |
1441 | } | |
1442 | else if (! mips_opts.mips16) | |
1443 | { | |
1444 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1445 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1446 | return 1; | |
1447 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1448 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1449 | return 1; | |
1450 | } | |
1451 | else | |
1452 | { | |
1453 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1454 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1455 | & MIPS16OP_MASK_RX)] | |
1456 | == reg)) | |
1457 | return 1; | |
1458 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1459 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1460 | & MIPS16OP_MASK_RY)] | |
1461 | == reg)) | |
1462 | return 1; | |
1463 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1464 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1465 | & MIPS16OP_MASK_MOVE32Z)] | |
1466 | == reg)) | |
1467 | return 1; | |
1468 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1469 | return 1; | |
1470 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1471 | return 1; | |
1472 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1473 | return 1; | |
1474 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1475 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1476 | & MIPS16OP_MASK_REGR32) == reg) | |
1477 | return 1; | |
1478 | } | |
1479 | ||
1480 | return 0; | |
1481 | } | |
1482 | ||
1483 | /* This function returns true if modifying a register requires a | |
1484 | delay. */ | |
1485 | ||
1486 | static int | |
1487 | reg_needs_delay (reg) | |
156c2f8b | 1488 | unsigned int reg; |
252b5132 RH |
1489 | { |
1490 | unsigned long prev_pinfo; | |
1491 | ||
1492 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1493 | if (! mips_opts.noreorder | |
9ce8a5dd | 1494 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1495 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1496 | || (! gpr_interlocks | |
1497 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1498 | { | |
1499 | /* A load from a coprocessor or from memory. All load | |
1500 | delays delay the use of general register rt for one | |
1501 | instruction on the r3000. The r6000 and r4000 use | |
1502 | interlocks. */ | |
bdaaa2e1 | 1503 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1504 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1505 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1506 | return 1; | |
1507 | } | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
1512 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1513 | handle them specially, such as generating jalx instructions when | |
1514 | needed. We also make them odd for the duration of the assembly, in | |
1515 | order to generate the right sort of code. We will make them even | |
1516 | in the adjust_symtab routine, while leaving them marked. This is | |
1517 | convenient for the debugger and the disassembler. The linker knows | |
1518 | to make them odd again. */ | |
1519 | ||
1520 | static void | |
1521 | mips16_mark_labels () | |
1522 | { | |
1523 | if (mips_opts.mips16) | |
1524 | { | |
1525 | struct insn_label_list *l; | |
98aa84af | 1526 | valueT val; |
252b5132 RH |
1527 | |
1528 | for (l = insn_labels; l != NULL; l = l->next) | |
1529 | { | |
1530 | #ifdef OBJ_ELF | |
1531 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1532 | S_SET_OTHER (l->label, STO_MIPS16); | |
1533 | #endif | |
98aa84af AM |
1534 | val = S_GET_VALUE (l->label); |
1535 | if ((val & 1) == 0) | |
1536 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1537 | } |
1538 | } | |
1539 | } | |
1540 | ||
1541 | /* Output an instruction. PLACE is where to put the instruction; if | |
1542 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1543 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1544 | used with RELOC_TYPE. */ | |
1545 | ||
1546 | static void | |
1547 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1548 | char *place; | |
1549 | struct mips_cl_insn *ip; | |
1550 | expressionS *address_expr; | |
f6688943 | 1551 | bfd_reloc_code_real_type *reloc_type; |
252b5132 RH |
1552 | boolean unmatched_hi; |
1553 | { | |
1554 | register unsigned long prev_pinfo, pinfo; | |
1555 | char *f; | |
f6688943 | 1556 | fixS *fixp[3]; |
252b5132 RH |
1557 | int nops = 0; |
1558 | ||
1559 | /* Mark instruction labels in mips16 mode. */ | |
1560 | if (mips_opts.mips16) | |
1561 | mips16_mark_labels (); | |
1562 | ||
1563 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1564 | pinfo = ip->insn_mo->pinfo; | |
1565 | ||
1566 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1567 | { | |
1568 | int prev_prev_nop; | |
1569 | ||
1570 | /* If the previous insn required any delay slots, see if we need | |
1571 | to insert a NOP or two. There are eight kinds of possible | |
1572 | hazards, of which an instruction can have at most one type. | |
1573 | (1) a load from memory delay | |
1574 | (2) a load from a coprocessor delay | |
1575 | (3) an unconditional branch delay | |
1576 | (4) a conditional branch delay | |
1577 | (5) a move to coprocessor register delay | |
1578 | (6) a load coprocessor register from memory delay | |
1579 | (7) a coprocessor condition code delay | |
1580 | (8) a HI/LO special register delay | |
1581 | ||
1582 | There are a lot of optimizations we could do that we don't. | |
1583 | In particular, we do not, in general, reorder instructions. | |
1584 | If you use gcc with optimization, it will reorder | |
1585 | instructions and generally do much more optimization then we | |
1586 | do here; repeating all that work in the assembler would only | |
1587 | benefit hand written assembly code, and does not seem worth | |
1588 | it. */ | |
1589 | ||
1590 | /* This is how a NOP is emitted. */ | |
1591 | #define emit_nop() \ | |
1592 | (mips_opts.mips16 \ | |
1593 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1594 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1595 | ||
1596 | /* The previous insn might require a delay slot, depending upon | |
1597 | the contents of the current insn. */ | |
1598 | if (! mips_opts.mips16 | |
9ce8a5dd | 1599 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1600 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1601 | && ! cop_interlocks) | |
1602 | || (! gpr_interlocks | |
1603 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1604 | { | |
1605 | /* A load from a coprocessor or from memory. All load | |
1606 | delays delay the use of general register rt for one | |
1607 | instruction on the r3000. The r6000 and r4000 use | |
1608 | interlocks. */ | |
beae10d5 | 1609 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1610 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1611 | if (mips_optimize == 0 | |
1612 | || insn_uses_reg (ip, | |
1613 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1614 | & OP_MASK_RT), | |
1615 | MIPS_GR_REG)) | |
1616 | ++nops; | |
1617 | } | |
1618 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1619 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1620 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1621 | && ! cop_interlocks) |
e7af610e | 1622 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1623 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1624 | { | |
1625 | /* A generic coprocessor delay. The previous instruction | |
1626 | modified a coprocessor general or control register. If | |
1627 | it modified a control register, we need to avoid any | |
1628 | coprocessor instruction (this is probably not always | |
1629 | required, but it sometimes is). If it modified a general | |
1630 | register, we avoid using that register. | |
1631 | ||
1632 | On the r6000 and r4000 loading a coprocessor register | |
1633 | from memory is interlocked, and does not require a delay. | |
1634 | ||
1635 | This case is not handled very well. There is no special | |
1636 | knowledge of CP0 handling, and the coprocessors other | |
1637 | than the floating point unit are not distinguished at | |
1638 | all. */ | |
1639 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1640 | Need to modify this to include knowledge about |
252b5132 RH |
1641 | user specified delays! */ |
1642 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1643 | { | |
1644 | if (mips_optimize == 0 | |
1645 | || insn_uses_reg (ip, | |
1646 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1647 | & OP_MASK_FT), | |
1648 | MIPS_FP_REG)) | |
1649 | ++nops; | |
1650 | } | |
1651 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1652 | { | |
1653 | if (mips_optimize == 0 | |
1654 | || insn_uses_reg (ip, | |
1655 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1656 | & OP_MASK_FS), | |
1657 | MIPS_FP_REG)) | |
1658 | ++nops; | |
1659 | } | |
1660 | else | |
1661 | { | |
1662 | /* We don't know exactly what the previous instruction | |
1663 | does. If the current instruction uses a coprocessor | |
1664 | register, we must insert a NOP. If previous | |
1665 | instruction may set the condition codes, and the | |
1666 | current instruction uses them, we must insert two | |
1667 | NOPS. */ | |
bdaaa2e1 | 1668 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1669 | if (mips_optimize == 0 |
1670 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1671 | && (pinfo & INSN_READ_COND_CODE))) | |
1672 | nops += 2; | |
1673 | else if (pinfo & INSN_COP) | |
1674 | ++nops; | |
1675 | } | |
1676 | } | |
1677 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1678 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1679 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1680 | && ! cop_interlocks) | |
1681 | { | |
1682 | /* The previous instruction sets the coprocessor condition | |
1683 | codes, but does not require a general coprocessor delay | |
1684 | (this means it is a floating point comparison | |
1685 | instruction). If this instruction uses the condition | |
1686 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1687 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1688 | if (mips_optimize == 0 |
1689 | || (pinfo & INSN_READ_COND_CODE)) | |
1690 | ++nops; | |
1691 | } | |
6b76fefe CM |
1692 | |
1693 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1694 | previous insn was an mfhi/mflo and the current insn | |
1695 | reads the register that the mfhi/mflo wrote to, then | |
1696 | insert two nops. */ | |
1697 | ||
1698 | else if (mips_7000_hilo_fix | |
1699 | && MF_HILO_INSN (prev_pinfo) | |
1700 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1701 | & OP_MASK_RD), |
1702 | MIPS_GR_REG)) | |
6b76fefe CM |
1703 | { |
1704 | nops += 2; | |
1705 | } | |
1706 | ||
1707 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1708 | 2nd previous insn was an mfhi/mflo and the current insn | |
1709 | reads the register that the mfhi/mflo wrote to, then | |
1710 | insert one nop. */ | |
1711 | ||
1712 | else if (mips_7000_hilo_fix | |
1713 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1714 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1715 | & OP_MASK_RD), | |
1716 | MIPS_GR_REG)) | |
bdaaa2e1 | 1717 | |
6b76fefe CM |
1718 | { |
1719 | nops += 1; | |
1720 | } | |
bdaaa2e1 | 1721 | |
252b5132 RH |
1722 | else if (prev_pinfo & INSN_READ_LO) |
1723 | { | |
1724 | /* The previous instruction reads the LO register; if the | |
1725 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1726 | insert two NOPS. Some newer processors have interlocks. |
1727 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1728 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1729 | though the tx39's divide insns still do require the |
1730 | delay. */ | |
252b5132 | 1731 | if (! (hilo_interlocks |
ec68c924 | 1732 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1733 | && (mips_optimize == 0 |
1734 | || (pinfo & INSN_WRITE_LO))) | |
1735 | nops += 2; | |
1736 | /* Most mips16 branch insns don't have a delay slot. | |
1737 | If a read from LO is immediately followed by a branch | |
1738 | to a write to LO we have a read followed by a write | |
1739 | less than 2 insns away. We assume the target of | |
1740 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1741 | between a read and an immediately following branch. */ |
252b5132 RH |
1742 | else if (mips_opts.mips16 |
1743 | && (mips_optimize == 0 | |
1744 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1745 | nops += 1; | |
1746 | } | |
1747 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1748 | { | |
1749 | /* The previous instruction reads the HI register; if the | |
1750 | current instruction writes to the HI register, we must | |
1751 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1752 | Also the note tx39's multiply above. */ |
252b5132 | 1753 | if (! (hilo_interlocks |
ec68c924 | 1754 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1755 | && (mips_optimize == 0 |
1756 | || (pinfo & INSN_WRITE_HI))) | |
1757 | nops += 2; | |
1758 | /* Most mips16 branch insns don't have a delay slot. | |
1759 | If a read from HI is immediately followed by a branch | |
1760 | to a write to HI we have a read followed by a write | |
1761 | less than 2 insns away. We assume the target of | |
1762 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1763 | between a read and an immediately following branch. */ |
252b5132 RH |
1764 | else if (mips_opts.mips16 |
1765 | && (mips_optimize == 0 | |
1766 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1767 | nops += 1; | |
1768 | } | |
1769 | ||
1770 | /* If the previous instruction was in a noreorder section, then | |
1771 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1772 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1773 | if (prev_insn_unreordered) |
1774 | nops = 0; | |
1775 | ||
1776 | /* There are two cases which require two intervening | |
1777 | instructions: 1) setting the condition codes using a move to | |
1778 | coprocessor instruction which requires a general coprocessor | |
1779 | delay and then reading the condition codes 2) reading the HI | |
1780 | or LO register and then writing to it (except on processors | |
1781 | which have interlocks). If we are not already emitting a NOP | |
1782 | instruction, we must check for these cases compared to the | |
1783 | instruction previous to the previous instruction. */ | |
1784 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1785 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1786 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1787 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1788 | && (pinfo & INSN_READ_COND_CODE) | |
1789 | && ! cop_interlocks) | |
1790 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1791 | && (pinfo & INSN_WRITE_LO) | |
1792 | && ! (hilo_interlocks | |
ec68c924 | 1793 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1794 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1795 | && (pinfo & INSN_WRITE_HI) | |
1796 | && ! (hilo_interlocks | |
ec68c924 | 1797 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1798 | prev_prev_nop = 1; |
1799 | else | |
1800 | prev_prev_nop = 0; | |
1801 | ||
1802 | if (prev_prev_insn_unreordered) | |
1803 | prev_prev_nop = 0; | |
1804 | ||
1805 | if (prev_prev_nop && nops == 0) | |
1806 | ++nops; | |
1807 | ||
1808 | /* If we are being given a nop instruction, don't bother with | |
1809 | one of the nops we would otherwise output. This will only | |
1810 | happen when a nop instruction is used with mips_optimize set | |
1811 | to 0. */ | |
1812 | if (nops > 0 | |
1813 | && ! mips_opts.noreorder | |
156c2f8b | 1814 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1815 | --nops; |
1816 | ||
1817 | /* Now emit the right number of NOP instructions. */ | |
1818 | if (nops > 0 && ! mips_opts.noreorder) | |
1819 | { | |
1820 | fragS *old_frag; | |
1821 | unsigned long old_frag_offset; | |
1822 | int i; | |
1823 | struct insn_label_list *l; | |
1824 | ||
1825 | old_frag = frag_now; | |
1826 | old_frag_offset = frag_now_fix (); | |
1827 | ||
1828 | for (i = 0; i < nops; i++) | |
1829 | emit_nop (); | |
1830 | ||
1831 | if (listing) | |
1832 | { | |
1833 | listing_prev_line (); | |
1834 | /* We may be at the start of a variant frag. In case we | |
1835 | are, make sure there is enough space for the frag | |
1836 | after the frags created by listing_prev_line. The | |
1837 | argument to frag_grow here must be at least as large | |
1838 | as the argument to all other calls to frag_grow in | |
1839 | this file. We don't have to worry about being in the | |
1840 | middle of a variant frag, because the variants insert | |
1841 | all needed nop instructions themselves. */ | |
1842 | frag_grow (40); | |
1843 | } | |
1844 | ||
1845 | for (l = insn_labels; l != NULL; l = l->next) | |
1846 | { | |
98aa84af AM |
1847 | valueT val; |
1848 | ||
252b5132 | 1849 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1850 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1851 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1852 | /* mips16 text labels are stored as odd. */ |
1853 | if (mips_opts.mips16) | |
98aa84af AM |
1854 | val += 1; |
1855 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
1856 | } |
1857 | ||
1858 | #ifndef NO_ECOFF_DEBUGGING | |
1859 | if (ECOFF_DEBUGGING) | |
1860 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1861 | #endif | |
1862 | } | |
1863 | else if (prev_nop_frag != NULL) | |
1864 | { | |
1865 | /* We have a frag holding nops we may be able to remove. If | |
1866 | we don't need any nops, we can decrease the size of | |
1867 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1868 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1869 | if (prev_nop_frag_since == 0) |
1870 | { | |
1871 | if (nops == 0) | |
1872 | { | |
1873 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1874 | --prev_nop_frag_holds; | |
1875 | } | |
1876 | else | |
1877 | prev_nop_frag_required += nops; | |
1878 | } | |
1879 | else | |
1880 | { | |
1881 | if (prev_prev_nop == 0) | |
1882 | { | |
1883 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1884 | --prev_nop_frag_holds; | |
1885 | } | |
1886 | else | |
1887 | ++prev_nop_frag_required; | |
1888 | } | |
1889 | ||
1890 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1891 | prev_nop_frag = NULL; | |
1892 | ||
1893 | ++prev_nop_frag_since; | |
1894 | ||
1895 | /* Sanity check: by the time we reach the second instruction | |
1896 | after prev_nop_frag, we should have used up all the nops | |
1897 | one way or another. */ | |
1898 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1899 | } | |
1900 | } | |
1901 | ||
f6688943 | 1902 | if (*reloc_type > BFD_RELOC_UNUSED) |
252b5132 RH |
1903 | { |
1904 | /* We need to set up a variant frag. */ | |
1905 | assert (mips_opts.mips16 && address_expr != NULL); | |
1906 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 1907 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
1908 | mips16_small, mips16_ext, |
1909 | (prev_pinfo | |
1910 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 1911 | (*prev_insn_reloc_type |
252b5132 | 1912 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 1913 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
1914 | } |
1915 | else if (place != NULL) | |
1916 | f = place; | |
1917 | else if (mips_opts.mips16 | |
1918 | && ! ip->use_extend | |
f6688943 | 1919 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
1920 | { |
1921 | /* Make sure there is enough room to swap this instruction with | |
1922 | a following jump instruction. */ | |
1923 | frag_grow (6); | |
1924 | f = frag_more (2); | |
1925 | } | |
1926 | else | |
1927 | { | |
1928 | if (mips_opts.mips16 | |
1929 | && mips_opts.noreorder | |
1930 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1931 | as_warn (_("extended instruction in delay slot")); | |
1932 | ||
1933 | f = frag_more (4); | |
1934 | } | |
1935 | ||
f6688943 TS |
1936 | fixp[0] = fixp[1] = fixp[2] = NULL; |
1937 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
1938 | { |
1939 | if (address_expr->X_op == O_constant) | |
1940 | { | |
f6688943 TS |
1941 | unsigned long tmp; |
1942 | ||
1943 | switch (*reloc_type) | |
252b5132 RH |
1944 | { |
1945 | case BFD_RELOC_32: | |
1946 | ip->insn_opcode |= address_expr->X_add_number; | |
1947 | break; | |
1948 | ||
f6688943 TS |
1949 | case BFD_RELOC_MIPS_HIGHEST: |
1950 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
1951 | tmp >>= 16; | |
1952 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
1953 | break; | |
1954 | ||
1955 | case BFD_RELOC_MIPS_HIGHER: | |
1956 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
1957 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
1958 | break; | |
1959 | ||
1960 | case BFD_RELOC_HI16_S: | |
1961 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
1962 | >> 16) & 0xffff; | |
1963 | break; | |
1964 | ||
1965 | case BFD_RELOC_HI16: | |
1966 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
1967 | break; | |
1968 | ||
252b5132 RH |
1969 | case BFD_RELOC_LO16: |
1970 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
1971 | break; | |
1972 | ||
1973 | case BFD_RELOC_MIPS_JMP: | |
1974 | if ((address_expr->X_add_number & 3) != 0) | |
1975 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1976 | (unsigned long) address_expr->X_add_number); | |
7496292d TS |
1977 | if (address_expr->X_add_number & ~0xfffffff |
1978 | || address_expr->X_add_number > 0x7fffffc) | |
1979 | as_bad (_("jump address range overflow (0x%lx)"), | |
1980 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
1981 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1982 | break; | |
1983 | ||
1984 | case BFD_RELOC_MIPS16_JMP: | |
1985 | if ((address_expr->X_add_number & 3) != 0) | |
1986 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1987 | (unsigned long) address_expr->X_add_number); | |
7496292d TS |
1988 | if (address_expr->X_add_number & ~0xfffffff |
1989 | || address_expr->X_add_number > 0x7fffffc) | |
1990 | as_bad (_("jump address range overflow (0x%lx)"), | |
1991 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
1992 | ip->insn_opcode |= |
1993 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1994 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1995 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1996 | break; | |
1997 | ||
cb56d3d3 | 1998 | case BFD_RELOC_16_PCREL: |
233b8738 | 1999 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
cb56d3d3 TS |
2000 | break; |
2001 | ||
252b5132 RH |
2002 | case BFD_RELOC_16_PCREL_S2: |
2003 | goto need_reloc; | |
2004 | ||
2005 | default: | |
2006 | internalError (); | |
2007 | } | |
2008 | } | |
2009 | else | |
2010 | { | |
2011 | need_reloc: | |
f6688943 | 2012 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2013 | if (place == NULL) |
2014 | { | |
f6688943 TS |
2015 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
2016 | address_expr, | |
2017 | (*reloc_type == BFD_RELOC_16_PCREL | |
2018 | || *reloc_type == BFD_RELOC_16_PCREL_S2), | |
2019 | reloc_type[0]); | |
2020 | ||
b6ff326e | 2021 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2022 | 4 octets for 64bit assembly. */ |
2023 | if (HAVE_64BIT_GPRS && | |
2024 | (*reloc_type == BFD_RELOC_16 | |
2025 | || *reloc_type == BFD_RELOC_32 | |
2026 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2027 | || *reloc_type == BFD_RELOC_HI16_S | |
2028 | || *reloc_type == BFD_RELOC_LO16 | |
2029 | || *reloc_type == BFD_RELOC_GPREL16 | |
2030 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2031 | || *reloc_type == BFD_RELOC_GPREL32 | |
2032 | || *reloc_type == BFD_RELOC_64 | |
2033 | || *reloc_type == BFD_RELOC_CTOR | |
2034 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2035 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2036 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2037 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2038 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2039 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
2040 | fixp[0]->fx_no_overflow = 1; | |
2041 | ||
252b5132 RH |
2042 | if (unmatched_hi) |
2043 | { | |
2044 | struct mips_hi_fixup *hi_fixup; | |
2045 | ||
f6688943 | 2046 | assert (*reloc_type == BFD_RELOC_HI16_S); |
252b5132 RH |
2047 | hi_fixup = ((struct mips_hi_fixup *) |
2048 | xmalloc (sizeof (struct mips_hi_fixup))); | |
f6688943 | 2049 | hi_fixup->fixp = fixp[0]; |
252b5132 RH |
2050 | hi_fixup->seg = now_seg; |
2051 | hi_fixup->next = mips_hi_fixup_list; | |
2052 | mips_hi_fixup_list = hi_fixup; | |
2053 | } | |
f6688943 TS |
2054 | |
2055 | if (reloc_type[1] != BFD_RELOC_UNUSED) | |
2056 | { | |
2057 | /* FIXME: This symbol can be one of | |
2058 | RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */ | |
2059 | address_expr->X_op = O_absent; | |
2060 | address_expr->X_add_symbol = 0; | |
2061 | address_expr->X_add_number = 0; | |
2062 | ||
2063 | fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2064 | 4, address_expr, false, | |
2065 | reloc_type[1]); | |
2066 | ||
b6ff326e | 2067 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2068 | 4 octets for 64bit assembly. */ |
2069 | if (HAVE_64BIT_GPRS && | |
2070 | (*reloc_type == BFD_RELOC_16 | |
2071 | || *reloc_type == BFD_RELOC_32 | |
2072 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2073 | || *reloc_type == BFD_RELOC_HI16_S | |
2074 | || *reloc_type == BFD_RELOC_LO16 | |
2075 | || *reloc_type == BFD_RELOC_GPREL16 | |
2076 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2077 | || *reloc_type == BFD_RELOC_GPREL32 | |
2078 | || *reloc_type == BFD_RELOC_64 | |
2079 | || *reloc_type == BFD_RELOC_CTOR | |
2080 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2081 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2082 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2083 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2084 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2085 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
2086 | fixp[1]->fx_no_overflow = 1; | |
2087 | ||
2088 | if (reloc_type[2] != BFD_RELOC_UNUSED) | |
2089 | { | |
2090 | address_expr->X_op = O_absent; | |
2091 | address_expr->X_add_symbol = 0; | |
2092 | address_expr->X_add_number = 0; | |
2093 | ||
2094 | fixp[2] = fix_new_exp (frag_now, | |
2095 | f - frag_now->fr_literal, 4, | |
2096 | address_expr, false, | |
2097 | reloc_type[2]); | |
2098 | ||
b6ff326e | 2099 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2100 | 4 octets for 64bit assembly. */ |
2101 | if (HAVE_64BIT_GPRS && | |
2102 | (*reloc_type == BFD_RELOC_16 | |
2103 | || *reloc_type == BFD_RELOC_32 | |
2104 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2105 | || *reloc_type == BFD_RELOC_HI16_S | |
2106 | || *reloc_type == BFD_RELOC_LO16 | |
2107 | || *reloc_type == BFD_RELOC_GPREL16 | |
2108 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2109 | || *reloc_type == BFD_RELOC_GPREL32 | |
2110 | || *reloc_type == BFD_RELOC_64 | |
2111 | || *reloc_type == BFD_RELOC_CTOR | |
2112 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2113 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2114 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2115 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2116 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2117 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
2118 | fixp[2]->fx_no_overflow = 1; | |
2119 | } | |
2120 | } | |
252b5132 RH |
2121 | } |
2122 | } | |
2123 | } | |
2124 | ||
2125 | if (! mips_opts.mips16) | |
2126 | md_number_to_chars (f, ip->insn_opcode, 4); | |
f6688943 | 2127 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2128 | { |
2129 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2130 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
2131 | } | |
2132 | else | |
2133 | { | |
2134 | if (ip->use_extend) | |
2135 | { | |
2136 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2137 | f += 2; | |
2138 | } | |
2139 | md_number_to_chars (f, ip->insn_opcode, 2); | |
2140 | } | |
2141 | ||
2142 | /* Update the register mask information. */ | |
2143 | if (! mips_opts.mips16) | |
2144 | { | |
2145 | if (pinfo & INSN_WRITE_GPR_D) | |
2146 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2147 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2148 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2149 | if (pinfo & INSN_READ_GPR_S) | |
2150 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2151 | if (pinfo & INSN_WRITE_GPR_31) | |
2152 | mips_gprmask |= 1 << 31; | |
2153 | if (pinfo & INSN_WRITE_FPR_D) | |
2154 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2155 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2156 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2157 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2158 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2159 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2160 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2161 | if (pinfo & INSN_COP) | |
2162 | { | |
bdaaa2e1 KH |
2163 | /* We don't keep enough information to sort these cases out. |
2164 | The itbl support does keep this information however, although | |
2165 | we currently don't support itbl fprmats as part of the cop | |
2166 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2167 | } |
2168 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2169 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2170 | } |
2171 | else | |
2172 | { | |
2173 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2174 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2175 | & MIPS16OP_MASK_RX); | |
2176 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2177 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2178 | & MIPS16OP_MASK_RY); | |
2179 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2180 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2181 | & MIPS16OP_MASK_RZ); | |
2182 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2183 | mips_gprmask |= 1 << TREG; | |
2184 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2185 | mips_gprmask |= 1 << SP; | |
2186 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2187 | mips_gprmask |= 1 << RA; | |
2188 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2189 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2190 | if (pinfo & MIPS16_INSN_READ_Z) | |
2191 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2192 | & MIPS16OP_MASK_MOVE32Z); | |
2193 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2194 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2195 | & MIPS16OP_MASK_REGR32); | |
2196 | } | |
2197 | ||
2198 | if (place == NULL && ! mips_opts.noreorder) | |
2199 | { | |
2200 | /* Filling the branch delay slot is more complex. We try to | |
2201 | switch the branch with the previous instruction, which we can | |
2202 | do if the previous instruction does not set up a condition | |
2203 | that the branch tests and if the branch is not itself the | |
2204 | target of any branch. */ | |
2205 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2206 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2207 | { | |
2208 | if (mips_optimize < 2 | |
2209 | /* If we have seen .set volatile or .set nomove, don't | |
2210 | optimize. */ | |
2211 | || mips_opts.nomove != 0 | |
2212 | /* If we had to emit any NOP instructions, then we | |
2213 | already know we can not swap. */ | |
2214 | || nops != 0 | |
2215 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2216 | swap. */ |
252b5132 RH |
2217 | || ! prev_insn_valid |
2218 | /* If the previous insn is already in a branch delay | |
2219 | slot, then we can not swap. */ | |
2220 | || prev_insn_is_delay_slot | |
2221 | /* If the previous previous insn was in a .set | |
2222 | noreorder, we can't swap. Actually, the MIPS | |
2223 | assembler will swap in this situation. However, gcc | |
2224 | configured -with-gnu-as will generate code like | |
2225 | .set noreorder | |
2226 | lw $4,XXX | |
2227 | .set reorder | |
2228 | INSN | |
2229 | bne $4,$0,foo | |
2230 | in which we can not swap the bne and INSN. If gcc is | |
2231 | not configured -with-gnu-as, it does not output the | |
2232 | .set pseudo-ops. We don't have to check | |
2233 | prev_insn_unreordered, because prev_insn_valid will | |
2234 | be 0 in that case. We don't want to use | |
2235 | prev_prev_insn_valid, because we do want to be able | |
2236 | to swap at the start of a function. */ | |
2237 | || prev_prev_insn_unreordered | |
2238 | /* If the branch is itself the target of a branch, we | |
2239 | can not swap. We cheat on this; all we check for is | |
2240 | whether there is a label on this instruction. If | |
2241 | there are any branches to anything other than a | |
2242 | label, users must use .set noreorder. */ | |
2243 | || insn_labels != NULL | |
2244 | /* If the previous instruction is in a variant frag, we | |
2245 | can not do the swap. This does not apply to the | |
2246 | mips16, which uses variant frags for different | |
2247 | purposes. */ | |
2248 | || (! mips_opts.mips16 | |
2249 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2250 | /* If the branch reads the condition codes, we don't | |
2251 | even try to swap, because in the sequence | |
2252 | ctc1 $X,$31 | |
2253 | INSN | |
2254 | INSN | |
2255 | bc1t LABEL | |
2256 | we can not swap, and I don't feel like handling that | |
2257 | case. */ | |
2258 | || (! mips_opts.mips16 | |
9ce8a5dd | 2259 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2260 | && (pinfo & INSN_READ_COND_CODE)) |
2261 | /* We can not swap with an instruction that requires a | |
2262 | delay slot, becase the target of the branch might | |
2263 | interfere with that instruction. */ | |
2264 | || (! mips_opts.mips16 | |
9ce8a5dd | 2265 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2266 | && (prev_pinfo |
bdaaa2e1 | 2267 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2268 | & (INSN_LOAD_COPROC_DELAY |
2269 | | INSN_COPROC_MOVE_DELAY | |
2270 | | INSN_WRITE_COND_CODE))) | |
2271 | || (! (hilo_interlocks | |
ec68c924 | 2272 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2273 | && (prev_pinfo |
2274 | & (INSN_READ_LO | |
2275 | | INSN_READ_HI))) | |
2276 | || (! mips_opts.mips16 | |
2277 | && ! gpr_interlocks | |
2278 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2279 | || (! mips_opts.mips16 | |
e7af610e | 2280 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2281 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2282 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2283 | /* We can not swap with a branch instruction. */ | |
2284 | || (prev_pinfo | |
2285 | & (INSN_UNCOND_BRANCH_DELAY | |
2286 | | INSN_COND_BRANCH_DELAY | |
2287 | | INSN_COND_BRANCH_LIKELY)) | |
2288 | /* We do not swap with a trap instruction, since it | |
2289 | complicates trap handlers to have the trap | |
2290 | instruction be in a delay slot. */ | |
2291 | || (prev_pinfo & INSN_TRAP) | |
2292 | /* If the branch reads a register that the previous | |
2293 | instruction sets, we can not swap. */ | |
2294 | || (! mips_opts.mips16 | |
2295 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2296 | && insn_uses_reg (ip, | |
2297 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2298 | & OP_MASK_RT), | |
2299 | MIPS_GR_REG)) | |
2300 | || (! mips_opts.mips16 | |
2301 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2302 | && insn_uses_reg (ip, | |
2303 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2304 | & OP_MASK_RD), | |
2305 | MIPS_GR_REG)) | |
2306 | || (mips_opts.mips16 | |
2307 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2308 | && insn_uses_reg (ip, | |
2309 | ((prev_insn.insn_opcode | |
2310 | >> MIPS16OP_SH_RX) | |
2311 | & MIPS16OP_MASK_RX), | |
2312 | MIPS16_REG)) | |
2313 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2314 | && insn_uses_reg (ip, | |
2315 | ((prev_insn.insn_opcode | |
2316 | >> MIPS16OP_SH_RY) | |
2317 | & MIPS16OP_MASK_RY), | |
2318 | MIPS16_REG)) | |
2319 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2320 | && insn_uses_reg (ip, | |
2321 | ((prev_insn.insn_opcode | |
2322 | >> MIPS16OP_SH_RZ) | |
2323 | & MIPS16OP_MASK_RZ), | |
2324 | MIPS16_REG)) | |
2325 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2326 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2327 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2328 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2329 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2330 | && insn_uses_reg (ip, | |
2331 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2332 | insn_opcode), | |
2333 | MIPS_GR_REG)))) | |
2334 | /* If the branch writes a register that the previous | |
2335 | instruction sets, we can not swap (we know that | |
2336 | branches write only to RD or to $31). */ | |
2337 | || (! mips_opts.mips16 | |
2338 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2339 | && (((pinfo & INSN_WRITE_GPR_D) | |
2340 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2341 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2342 | || ((pinfo & INSN_WRITE_GPR_31) | |
2343 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2344 | & OP_MASK_RT) | |
2345 | == 31)))) | |
2346 | || (! mips_opts.mips16 | |
2347 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2348 | && (((pinfo & INSN_WRITE_GPR_D) | |
2349 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2350 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2351 | || ((pinfo & INSN_WRITE_GPR_31) | |
2352 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2353 | & OP_MASK_RD) | |
2354 | == 31)))) | |
2355 | || (mips_opts.mips16 | |
2356 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2357 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2358 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2359 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2360 | == RA)))) | |
2361 | /* If the branch writes a register that the previous | |
2362 | instruction reads, we can not swap (we know that | |
2363 | branches only write to RD or to $31). */ | |
2364 | || (! mips_opts.mips16 | |
2365 | && (pinfo & INSN_WRITE_GPR_D) | |
2366 | && insn_uses_reg (&prev_insn, | |
2367 | ((ip->insn_opcode >> OP_SH_RD) | |
2368 | & OP_MASK_RD), | |
2369 | MIPS_GR_REG)) | |
2370 | || (! mips_opts.mips16 | |
2371 | && (pinfo & INSN_WRITE_GPR_31) | |
2372 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
2373 | || (mips_opts.mips16 | |
2374 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2375 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2376 | /* If we are generating embedded PIC code, the branch | |
2377 | might be expanded into a sequence which uses $at, so | |
2378 | we can't swap with an instruction which reads it. */ | |
2379 | || (mips_pic == EMBEDDED_PIC | |
2380 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2381 | /* If the previous previous instruction has a load | |
2382 | delay, and sets a register that the branch reads, we | |
2383 | can not swap. */ | |
2384 | || (! mips_opts.mips16 | |
9ce8a5dd | 2385 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2386 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2387 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2388 | || (! gpr_interlocks | |
2389 | && (prev_prev_insn.insn_mo->pinfo | |
2390 | & INSN_LOAD_MEMORY_DELAY))) | |
2391 | && insn_uses_reg (ip, | |
2392 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2393 | & OP_MASK_RT), | |
2394 | MIPS_GR_REG)) | |
2395 | /* If one instruction sets a condition code and the | |
2396 | other one uses a condition code, we can not swap. */ | |
2397 | || ((pinfo & INSN_READ_COND_CODE) | |
2398 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2399 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2400 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2401 | /* If the previous instruction uses the PC, we can not | |
2402 | swap. */ | |
2403 | || (mips_opts.mips16 | |
2404 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2405 | /* If the previous instruction was extended, we can not | |
2406 | swap. */ | |
2407 | || (mips_opts.mips16 && prev_insn_extended) | |
2408 | /* If the previous instruction had a fixup in mips16 | |
2409 | mode, we can not swap. This normally means that the | |
2410 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2411 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2412 | /* If the previous instruction is a sync, sync.l, or |
2413 | sync.p, we can not swap. */ | |
f173e82e | 2414 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2415 | { |
2416 | /* We could do even better for unconditional branches to | |
2417 | portions of this object file; we could pick up the | |
2418 | instruction at the destination, put it in the delay | |
2419 | slot, and bump the destination address. */ | |
2420 | emit_nop (); | |
2421 | /* Update the previous insn information. */ | |
2422 | prev_prev_insn = *ip; | |
2423 | prev_insn.insn_mo = &dummy_opcode; | |
2424 | } | |
2425 | else | |
2426 | { | |
2427 | /* It looks like we can actually do the swap. */ | |
2428 | if (! mips_opts.mips16) | |
2429 | { | |
2430 | char *prev_f; | |
2431 | char temp[4]; | |
2432 | ||
2433 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2434 | memcpy (temp, prev_f, 4); | |
2435 | memcpy (prev_f, f, 4); | |
2436 | memcpy (f, temp, 4); | |
f6688943 TS |
2437 | if (prev_insn_fixp[0]) |
2438 | { | |
2439 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2440 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2441 | } | |
2442 | if (prev_insn_fixp[1]) | |
2443 | { | |
2444 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2445 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2446 | } | |
2447 | if (prev_insn_fixp[2]) | |
252b5132 | 2448 | { |
f6688943 TS |
2449 | prev_insn_fixp[2]->fx_frag = frag_now; |
2450 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2451 | } |
f6688943 | 2452 | if (fixp[0]) |
252b5132 | 2453 | { |
f6688943 TS |
2454 | fixp[0]->fx_frag = prev_insn_frag; |
2455 | fixp[0]->fx_where = prev_insn_where; | |
2456 | } | |
2457 | if (fixp[1]) | |
2458 | { | |
2459 | fixp[1]->fx_frag = prev_insn_frag; | |
2460 | fixp[1]->fx_where = prev_insn_where; | |
2461 | } | |
2462 | if (fixp[2]) | |
2463 | { | |
2464 | fixp[2]->fx_frag = prev_insn_frag; | |
2465 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2466 | } |
2467 | } | |
2468 | else | |
2469 | { | |
2470 | char *prev_f; | |
2471 | char temp[2]; | |
2472 | ||
f6688943 TS |
2473 | assert (prev_insn_fixp[0] == NULL); |
2474 | assert (prev_insn_fixp[1] == NULL); | |
2475 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2476 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2477 | memcpy (temp, prev_f, 2); | |
2478 | memcpy (prev_f, f, 2); | |
f6688943 | 2479 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2480 | { |
f6688943 | 2481 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2482 | memcpy (f, temp, 2); |
2483 | } | |
2484 | else | |
2485 | { | |
2486 | memcpy (f, f + 2, 2); | |
2487 | memcpy (f + 2, temp, 2); | |
2488 | } | |
f6688943 TS |
2489 | if (fixp[0]) |
2490 | { | |
2491 | fixp[0]->fx_frag = prev_insn_frag; | |
2492 | fixp[0]->fx_where = prev_insn_where; | |
2493 | } | |
2494 | if (fixp[1]) | |
2495 | { | |
2496 | fixp[1]->fx_frag = prev_insn_frag; | |
2497 | fixp[1]->fx_where = prev_insn_where; | |
2498 | } | |
2499 | if (fixp[2]) | |
252b5132 | 2500 | { |
f6688943 TS |
2501 | fixp[2]->fx_frag = prev_insn_frag; |
2502 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2503 | } |
2504 | } | |
2505 | ||
2506 | /* Update the previous insn information; leave prev_insn | |
2507 | unchanged. */ | |
2508 | prev_prev_insn = *ip; | |
2509 | } | |
2510 | prev_insn_is_delay_slot = 1; | |
2511 | ||
2512 | /* If that was an unconditional branch, forget the previous | |
2513 | insn information. */ | |
2514 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2515 | { | |
2516 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2517 | prev_insn.insn_mo = &dummy_opcode; | |
2518 | } | |
2519 | ||
f6688943 TS |
2520 | prev_insn_fixp[0] = NULL; |
2521 | prev_insn_fixp[1] = NULL; | |
2522 | prev_insn_fixp[2] = NULL; | |
2523 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2524 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2525 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2526 | prev_insn_extended = 0; |
2527 | } | |
2528 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2529 | { | |
2530 | /* We don't yet optimize a branch likely. What we should do | |
2531 | is look at the target, copy the instruction found there | |
2532 | into the delay slot, and increment the branch to jump to | |
2533 | the next instruction. */ | |
2534 | emit_nop (); | |
2535 | /* Update the previous insn information. */ | |
2536 | prev_prev_insn = *ip; | |
2537 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2538 | prev_insn_fixp[0] = NULL; |
2539 | prev_insn_fixp[1] = NULL; | |
2540 | prev_insn_fixp[2] = NULL; | |
2541 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2542 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2543 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2544 | prev_insn_extended = 0; |
2545 | } | |
2546 | else | |
2547 | { | |
2548 | /* Update the previous insn information. */ | |
2549 | if (nops > 0) | |
2550 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2551 | else | |
2552 | prev_prev_insn = prev_insn; | |
2553 | prev_insn = *ip; | |
2554 | ||
2555 | /* Any time we see a branch, we always fill the delay slot | |
2556 | immediately; since this insn is not a branch, we know it | |
2557 | is not in a delay slot. */ | |
2558 | prev_insn_is_delay_slot = 0; | |
2559 | ||
f6688943 TS |
2560 | prev_insn_fixp[0] = fixp[0]; |
2561 | prev_insn_fixp[1] = fixp[1]; | |
2562 | prev_insn_fixp[2] = fixp[2]; | |
2563 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2564 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2565 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2566 | if (mips_opts.mips16) |
2567 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2568 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2569 | } |
2570 | ||
2571 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2572 | prev_insn_unreordered = 0; | |
2573 | prev_insn_frag = frag_now; | |
2574 | prev_insn_where = f - frag_now->fr_literal; | |
2575 | prev_insn_valid = 1; | |
2576 | } | |
2577 | else if (place == NULL) | |
2578 | { | |
2579 | /* We need to record a bit of information even when we are not | |
2580 | reordering, in order to determine the base address for mips16 | |
2581 | PC relative relocs. */ | |
2582 | prev_prev_insn = prev_insn; | |
2583 | prev_insn = *ip; | |
f6688943 TS |
2584 | prev_insn_reloc_type[0] = reloc_type[0]; |
2585 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2586 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2587 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2588 | prev_insn_unreordered = 1; | |
2589 | } | |
2590 | ||
2591 | /* We just output an insn, so the next one doesn't have a label. */ | |
2592 | mips_clear_insn_labels (); | |
2593 | ||
2594 | /* We must ensure that a fixup associated with an unmatched %hi | |
2595 | reloc does not become a variant frag. Otherwise, the | |
2596 | rearrangement of %hi relocs in frob_file may confuse | |
2597 | tc_gen_reloc. */ | |
2598 | if (unmatched_hi) | |
2599 | { | |
2600 | frag_wane (frag_now); | |
2601 | frag_new (0); | |
2602 | } | |
2603 | } | |
2604 | ||
2605 | /* This function forgets that there was any previous instruction or | |
2606 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2607 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2608 | |
2609 | static void | |
2610 | mips_no_prev_insn (preserve) | |
2611 | int preserve; | |
2612 | { | |
2613 | if (! preserve) | |
2614 | { | |
2615 | prev_insn.insn_mo = &dummy_opcode; | |
2616 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2617 | prev_nop_frag = NULL; | |
2618 | prev_nop_frag_holds = 0; | |
2619 | prev_nop_frag_required = 0; | |
2620 | prev_nop_frag_since = 0; | |
2621 | } | |
2622 | prev_insn_valid = 0; | |
2623 | prev_insn_is_delay_slot = 0; | |
2624 | prev_insn_unreordered = 0; | |
2625 | prev_insn_extended = 0; | |
f6688943 TS |
2626 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2627 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2628 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2629 | prev_prev_insn_unreordered = 0; |
2630 | mips_clear_insn_labels (); | |
2631 | } | |
2632 | ||
2633 | /* This function must be called whenever we turn on noreorder or emit | |
2634 | something other than instructions. It inserts any NOPS which might | |
2635 | be needed by the previous instruction, and clears the information | |
2636 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2637 | instructions are to follow. */ |
252b5132 RH |
2638 | |
2639 | static void | |
2640 | mips_emit_delays (insns) | |
2641 | boolean insns; | |
2642 | { | |
2643 | if (! mips_opts.noreorder) | |
2644 | { | |
2645 | int nops; | |
2646 | ||
2647 | nops = 0; | |
2648 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2649 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2650 | && (! cop_interlocks |
2651 | && (prev_insn.insn_mo->pinfo | |
2652 | & (INSN_LOAD_COPROC_DELAY | |
2653 | | INSN_COPROC_MOVE_DELAY | |
2654 | | INSN_WRITE_COND_CODE)))) | |
2655 | || (! hilo_interlocks | |
2656 | && (prev_insn.insn_mo->pinfo | |
2657 | & (INSN_READ_LO | |
2658 | | INSN_READ_HI))) | |
2659 | || (! mips_opts.mips16 | |
2660 | && ! gpr_interlocks | |
bdaaa2e1 | 2661 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2662 | & INSN_LOAD_MEMORY_DELAY)) |
2663 | || (! mips_opts.mips16 | |
e7af610e | 2664 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2665 | && (prev_insn.insn_mo->pinfo |
2666 | & INSN_COPROC_MEMORY_DELAY))) | |
2667 | { | |
beae10d5 | 2668 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2669 | ++nops; |
2670 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2671 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2672 | && (! cop_interlocks |
2673 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2674 | || (! hilo_interlocks | |
2675 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2676 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2677 | ++nops; | |
2678 | ||
2679 | if (prev_insn_unreordered) | |
2680 | nops = 0; | |
2681 | } | |
2682 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2683 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2684 | && (! cop_interlocks |
2685 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2686 | || (! hilo_interlocks | |
2687 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2688 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2689 | { | |
beae10d5 | 2690 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2691 | if (! prev_prev_insn_unreordered) |
2692 | ++nops; | |
2693 | } | |
2694 | ||
2695 | if (nops > 0) | |
2696 | { | |
2697 | struct insn_label_list *l; | |
2698 | ||
2699 | if (insns) | |
2700 | { | |
2701 | /* Record the frag which holds the nop instructions, so | |
2702 | that we can remove them if we don't need them. */ | |
2703 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2704 | prev_nop_frag = frag_now; | |
2705 | prev_nop_frag_holds = nops; | |
2706 | prev_nop_frag_required = 0; | |
2707 | prev_nop_frag_since = 0; | |
2708 | } | |
2709 | ||
2710 | for (; nops > 0; --nops) | |
2711 | emit_nop (); | |
2712 | ||
2713 | if (insns) | |
2714 | { | |
2715 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2716 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2717 | frag_wane (frag_now); |
2718 | frag_new (0); | |
2719 | } | |
2720 | ||
2721 | for (l = insn_labels; l != NULL; l = l->next) | |
2722 | { | |
98aa84af AM |
2723 | valueT val; |
2724 | ||
252b5132 | 2725 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2726 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2727 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2728 | /* mips16 text labels are stored as odd. */ |
2729 | if (mips_opts.mips16) | |
98aa84af AM |
2730 | val += 1; |
2731 | S_SET_VALUE (l->label, val); | |
252b5132 RH |
2732 | } |
2733 | } | |
2734 | } | |
2735 | ||
2736 | /* Mark instruction labels in mips16 mode. */ | |
2737 | if (mips_opts.mips16 && insns) | |
2738 | mips16_mark_labels (); | |
2739 | ||
2740 | mips_no_prev_insn (insns); | |
2741 | } | |
2742 | ||
2743 | /* Build an instruction created by a macro expansion. This is passed | |
2744 | a pointer to the count of instructions created so far, an | |
2745 | expression, the name of the instruction to build, an operand format | |
2746 | string, and corresponding arguments. */ | |
2747 | ||
2748 | #ifdef USE_STDARG | |
2749 | static void | |
2750 | macro_build (char *place, | |
2751 | int *counter, | |
2752 | expressionS * ep, | |
2753 | const char *name, | |
2754 | const char *fmt, | |
2755 | ...) | |
2756 | #else | |
2757 | static void | |
2758 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2759 | char *place; | |
2760 | int *counter; | |
2761 | expressionS *ep; | |
2762 | const char *name; | |
2763 | const char *fmt; | |
2764 | va_dcl | |
2765 | #endif | |
2766 | { | |
2767 | struct mips_cl_insn insn; | |
f6688943 | 2768 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2769 | va_list args; |
252b5132 RH |
2770 | |
2771 | #ifdef USE_STDARG | |
2772 | va_start (args, fmt); | |
2773 | #else | |
2774 | va_start (args); | |
2775 | #endif | |
2776 | ||
2777 | /* | |
2778 | * If the macro is about to expand into a second instruction, | |
2779 | * print a warning if needed. We need to pass ip as a parameter | |
2780 | * to generate a better warning message here... | |
2781 | */ | |
2782 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2783 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2784 | ||
2785 | if (place == NULL) | |
2786 | *counter += 1; /* bump instruction counter */ | |
2787 | ||
2788 | if (mips_opts.mips16) | |
2789 | { | |
2790 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2791 | va_end (args); | |
2792 | return; | |
2793 | } | |
2794 | ||
f6688943 TS |
2795 | r[0] = BFD_RELOC_UNUSED; |
2796 | r[1] = BFD_RELOC_UNUSED; | |
2797 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2798 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2799 | assert (insn.insn_mo); | |
2800 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2801 | ||
2802 | /* Search until we get a match for NAME. */ | |
2803 | while (1) | |
2804 | { | |
252b5132 RH |
2805 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2806 | && insn.insn_mo->pinfo != INSN_MACRO | |
ea1fb5dc | 2807 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch) |
ec68c924 | 2808 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2809 | break; |
2810 | ||
2811 | ++insn.insn_mo; | |
2812 | assert (insn.insn_mo->name); | |
2813 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2814 | } | |
2815 | ||
2816 | insn.insn_opcode = insn.insn_mo->match; | |
2817 | for (;;) | |
2818 | { | |
2819 | switch (*fmt++) | |
2820 | { | |
2821 | case '\0': | |
2822 | break; | |
2823 | ||
2824 | case ',': | |
2825 | case '(': | |
2826 | case ')': | |
2827 | continue; | |
2828 | ||
2829 | case 't': | |
2830 | case 'w': | |
2831 | case 'E': | |
38487616 | 2832 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2833 | continue; |
2834 | ||
2835 | case 'c': | |
38487616 TS |
2836 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2837 | continue; | |
2838 | ||
252b5132 RH |
2839 | case 'T': |
2840 | case 'W': | |
38487616 | 2841 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2842 | continue; |
2843 | ||
2844 | case 'd': | |
2845 | case 'G': | |
38487616 | 2846 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2847 | continue; |
2848 | ||
4372b673 NC |
2849 | case 'U': |
2850 | { | |
2851 | int tmp = va_arg (args, int); | |
2852 | ||
38487616 TS |
2853 | insn.insn_opcode |= tmp << OP_SH_RT; |
2854 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2855 | continue; |
4372b673 NC |
2856 | } |
2857 | ||
252b5132 RH |
2858 | case 'V': |
2859 | case 'S': | |
38487616 | 2860 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2861 | continue; |
2862 | ||
2863 | case 'z': | |
2864 | continue; | |
2865 | ||
2866 | case '<': | |
38487616 | 2867 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2868 | continue; |
2869 | ||
2870 | case 'D': | |
38487616 | 2871 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
2872 | continue; |
2873 | ||
2874 | case 'B': | |
38487616 | 2875 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
2876 | continue; |
2877 | ||
4372b673 | 2878 | case 'J': |
38487616 | 2879 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
2880 | continue; |
2881 | ||
252b5132 | 2882 | case 'q': |
38487616 | 2883 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
2884 | continue; |
2885 | ||
2886 | case 'b': | |
2887 | case 's': | |
2888 | case 'r': | |
2889 | case 'v': | |
38487616 | 2890 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
2891 | continue; |
2892 | ||
2893 | case 'i': | |
2894 | case 'j': | |
2895 | case 'o': | |
f6688943 | 2896 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 2897 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
2898 | || *r == BFD_RELOC_MIPS_LITERAL |
2899 | || *r == BFD_RELOC_MIPS_HIGHER | |
2900 | || *r == BFD_RELOC_HI16_S | |
2901 | || *r == BFD_RELOC_LO16 | |
2902 | || *r == BFD_RELOC_MIPS_GOT16 | |
2903 | || *r == BFD_RELOC_MIPS_CALL16 | |
2904 | || *r == BFD_RELOC_MIPS_GOT_LO16 | |
2905 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 2906 | || (ep->X_op == O_subtract |
f6688943 | 2907 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
2908 | continue; |
2909 | ||
2910 | case 'u': | |
f6688943 | 2911 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
2912 | assert (ep != NULL |
2913 | && (ep->X_op == O_constant | |
2914 | || (ep->X_op == O_symbol | |
f6688943 TS |
2915 | && (*r == BFD_RELOC_MIPS_HIGHEST |
2916 | || *r == BFD_RELOC_HI16_S | |
2917 | || *r == BFD_RELOC_HI16 | |
2918 | || *r == BFD_RELOC_GPREL16 | |
2919 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
2920 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 2921 | || (ep->X_op == O_subtract |
f6688943 | 2922 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
2923 | continue; |
2924 | ||
2925 | case 'p': | |
2926 | assert (ep != NULL); | |
2927 | /* | |
2928 | * This allows macro() to pass an immediate expression for | |
2929 | * creating short branches without creating a symbol. | |
2930 | * Note that the expression still might come from the assembly | |
2931 | * input, in which case the value is not checked for range nor | |
2932 | * is a relocation entry generated (yuck). | |
2933 | */ | |
2934 | if (ep->X_op == O_constant) | |
2935 | { | |
2936 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2937 | ep = NULL; | |
2938 | } | |
2939 | else | |
cb56d3d3 | 2940 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 2941 | *r = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 2942 | else |
f6688943 | 2943 | *r = BFD_RELOC_16_PCREL; |
252b5132 RH |
2944 | continue; |
2945 | ||
2946 | case 'a': | |
2947 | assert (ep != NULL); | |
f6688943 | 2948 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
2949 | continue; |
2950 | ||
2951 | case 'C': | |
2952 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2953 | continue; | |
2954 | ||
2955 | default: | |
2956 | internalError (); | |
2957 | } | |
2958 | break; | |
2959 | } | |
2960 | va_end (args); | |
f6688943 | 2961 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
2962 | |
2963 | append_insn (place, &insn, ep, r, false); | |
2964 | } | |
2965 | ||
2966 | static void | |
2967 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2968 | char *place; | |
43841e91 | 2969 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
2970 | expressionS *ep; |
2971 | const char *name; | |
2972 | const char *fmt; | |
2973 | va_list args; | |
2974 | { | |
2975 | struct mips_cl_insn insn; | |
f6688943 TS |
2976 | bfd_reloc_code_real_type r[3] |
2977 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 2978 | |
252b5132 RH |
2979 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
2980 | assert (insn.insn_mo); | |
2981 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2982 | ||
2983 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2984 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2985 | { | |
2986 | ++insn.insn_mo; | |
2987 | assert (insn.insn_mo->name); | |
2988 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2989 | } | |
2990 | ||
2991 | insn.insn_opcode = insn.insn_mo->match; | |
2992 | insn.use_extend = false; | |
2993 | ||
2994 | for (;;) | |
2995 | { | |
2996 | int c; | |
2997 | ||
2998 | c = *fmt++; | |
2999 | switch (c) | |
3000 | { | |
3001 | case '\0': | |
3002 | break; | |
3003 | ||
3004 | case ',': | |
3005 | case '(': | |
3006 | case ')': | |
3007 | continue; | |
3008 | ||
3009 | case 'y': | |
3010 | case 'w': | |
3011 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3012 | continue; | |
3013 | ||
3014 | case 'x': | |
3015 | case 'v': | |
3016 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3017 | continue; | |
3018 | ||
3019 | case 'z': | |
3020 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3021 | continue; | |
3022 | ||
3023 | case 'Z': | |
3024 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3025 | continue; | |
3026 | ||
3027 | case '0': | |
3028 | case 'S': | |
3029 | case 'P': | |
3030 | case 'R': | |
3031 | continue; | |
3032 | ||
3033 | case 'X': | |
3034 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3035 | continue; | |
3036 | ||
3037 | case 'Y': | |
3038 | { | |
3039 | int regno; | |
3040 | ||
3041 | regno = va_arg (args, int); | |
3042 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3043 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3044 | } | |
3045 | continue; | |
3046 | ||
3047 | case '<': | |
3048 | case '>': | |
3049 | case '4': | |
3050 | case '5': | |
3051 | case 'H': | |
3052 | case 'W': | |
3053 | case 'D': | |
3054 | case 'j': | |
3055 | case '8': | |
3056 | case 'V': | |
3057 | case 'C': | |
3058 | case 'U': | |
3059 | case 'k': | |
3060 | case 'K': | |
3061 | case 'p': | |
3062 | case 'q': | |
3063 | { | |
3064 | assert (ep != NULL); | |
3065 | ||
3066 | if (ep->X_op != O_constant) | |
f6688943 | 3067 | *r = BFD_RELOC_UNUSED + c; |
252b5132 RH |
3068 | else |
3069 | { | |
c4e7957c TS |
3070 | mips16_immed (NULL, 0, c, ep->X_add_number, false, false, |
3071 | false, &insn.insn_opcode, &insn.use_extend, | |
3072 | &insn.extend); | |
252b5132 | 3073 | ep = NULL; |
f6688943 | 3074 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3075 | } |
3076 | } | |
3077 | continue; | |
3078 | ||
3079 | case '6': | |
3080 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3081 | continue; | |
3082 | } | |
3083 | ||
3084 | break; | |
3085 | } | |
3086 | ||
f6688943 | 3087 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
3088 | |
3089 | append_insn (place, &insn, ep, r, false); | |
3090 | } | |
3091 | ||
3092 | /* | |
3093 | * Generate a "lui" instruction. | |
3094 | */ | |
3095 | static void | |
3096 | macro_build_lui (place, counter, ep, regnum) | |
3097 | char *place; | |
3098 | int *counter; | |
3099 | expressionS *ep; | |
3100 | int regnum; | |
3101 | { | |
3102 | expressionS high_expr; | |
3103 | struct mips_cl_insn insn; | |
f6688943 TS |
3104 | bfd_reloc_code_real_type r[3] |
3105 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
3106 | CONST char *name = "lui"; |
3107 | CONST char *fmt = "t,u"; | |
3108 | ||
3109 | assert (! mips_opts.mips16); | |
3110 | ||
3111 | if (place == NULL) | |
3112 | high_expr = *ep; | |
3113 | else | |
3114 | { | |
3115 | high_expr.X_op = O_constant; | |
3116 | high_expr.X_add_number = ep->X_add_number; | |
3117 | } | |
3118 | ||
3119 | if (high_expr.X_op == O_constant) | |
3120 | { | |
3121 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3122 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3123 | >> 16) & 0xffff; | |
f6688943 | 3124 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3125 | } |
f6688943 | 3126 | else if (! HAVE_NEWABI) |
252b5132 RH |
3127 | { |
3128 | assert (ep->X_op == O_symbol); | |
3129 | /* _gp_disp is a special case, used from s_cpload. */ | |
3130 | assert (mips_pic == NO_PIC | |
3131 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
f6688943 | 3132 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3133 | } |
3134 | ||
3135 | /* | |
3136 | * If the macro is about to expand into a second instruction, | |
3137 | * print a warning if needed. We need to pass ip as a parameter | |
3138 | * to generate a better warning message here... | |
3139 | */ | |
3140 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3141 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3142 | ||
3143 | if (place == NULL) | |
3144 | *counter += 1; /* bump instruction counter */ | |
3145 | ||
3146 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3147 | assert (insn.insn_mo); | |
3148 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3149 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3150 | ||
3151 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3152 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3153 | { |
3154 | insn.insn_opcode |= high_expr.X_add_number; | |
3155 | append_insn (place, &insn, NULL, r, false); | |
3156 | } | |
3157 | else | |
3158 | append_insn (place, &insn, &high_expr, r, false); | |
3159 | } | |
3160 | ||
3161 | /* set_at() | |
3162 | * Generates code to set the $at register to true (one) | |
3163 | * if reg is less than the immediate expression. | |
3164 | */ | |
3165 | static void | |
3166 | set_at (counter, reg, unsignedp) | |
3167 | int *counter; | |
3168 | int reg; | |
3169 | int unsignedp; | |
3170 | { | |
3171 | if (imm_expr.X_op == O_constant | |
3172 | && imm_expr.X_add_number >= -0x8000 | |
3173 | && imm_expr.X_add_number < 0x8000) | |
3174 | macro_build ((char *) NULL, counter, &imm_expr, | |
3175 | unsignedp ? "sltiu" : "slti", | |
3176 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3177 | else | |
3178 | { | |
3179 | load_register (counter, AT, &imm_expr, 0); | |
2396cfb9 | 3180 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 RH |
3181 | unsignedp ? "sltu" : "slt", |
3182 | "d,v,t", AT, reg, AT); | |
3183 | } | |
3184 | } | |
3185 | ||
3186 | /* Warn if an expression is not a constant. */ | |
3187 | ||
3188 | static void | |
3189 | check_absolute_expr (ip, ex) | |
3190 | struct mips_cl_insn *ip; | |
3191 | expressionS *ex; | |
3192 | { | |
3193 | if (ex->X_op == O_big) | |
3194 | as_bad (_("unsupported large constant")); | |
3195 | else if (ex->X_op != O_constant) | |
3196 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3197 | } | |
3198 | ||
3199 | /* Count the leading zeroes by performing a binary chop. This is a | |
3200 | bulky bit of source, but performance is a LOT better for the | |
3201 | majority of values than a simple loop to count the bits: | |
3202 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3203 | if ((v) & (1 << (31 - lcnt))) | |
3204 | break; | |
3205 | However it is not code size friendly, and the gain will drop a bit | |
3206 | on certain cached systems. | |
3207 | */ | |
3208 | #define COUNT_TOP_ZEROES(v) \ | |
3209 | (((v) & ~0xffff) == 0 \ | |
3210 | ? ((v) & ~0xff) == 0 \ | |
3211 | ? ((v) & ~0xf) == 0 \ | |
3212 | ? ((v) & ~0x3) == 0 \ | |
3213 | ? ((v) & ~0x1) == 0 \ | |
3214 | ? !(v) \ | |
3215 | ? 32 \ | |
3216 | : 31 \ | |
3217 | : 30 \ | |
3218 | : ((v) & ~0x7) == 0 \ | |
3219 | ? 29 \ | |
3220 | : 28 \ | |
3221 | : ((v) & ~0x3f) == 0 \ | |
3222 | ? ((v) & ~0x1f) == 0 \ | |
3223 | ? 27 \ | |
3224 | : 26 \ | |
3225 | : ((v) & ~0x7f) == 0 \ | |
3226 | ? 25 \ | |
3227 | : 24 \ | |
3228 | : ((v) & ~0xfff) == 0 \ | |
3229 | ? ((v) & ~0x3ff) == 0 \ | |
3230 | ? ((v) & ~0x1ff) == 0 \ | |
3231 | ? 23 \ | |
3232 | : 22 \ | |
3233 | : ((v) & ~0x7ff) == 0 \ | |
3234 | ? 21 \ | |
3235 | : 20 \ | |
3236 | : ((v) & ~0x3fff) == 0 \ | |
3237 | ? ((v) & ~0x1fff) == 0 \ | |
3238 | ? 19 \ | |
3239 | : 18 \ | |
3240 | : ((v) & ~0x7fff) == 0 \ | |
3241 | ? 17 \ | |
3242 | : 16 \ | |
3243 | : ((v) & ~0xffffff) == 0 \ | |
3244 | ? ((v) & ~0xfffff) == 0 \ | |
3245 | ? ((v) & ~0x3ffff) == 0 \ | |
3246 | ? ((v) & ~0x1ffff) == 0 \ | |
3247 | ? 15 \ | |
3248 | : 14 \ | |
3249 | : ((v) & ~0x7ffff) == 0 \ | |
3250 | ? 13 \ | |
3251 | : 12 \ | |
3252 | : ((v) & ~0x3fffff) == 0 \ | |
3253 | ? ((v) & ~0x1fffff) == 0 \ | |
3254 | ? 11 \ | |
3255 | : 10 \ | |
3256 | : ((v) & ~0x7fffff) == 0 \ | |
3257 | ? 9 \ | |
3258 | : 8 \ | |
3259 | : ((v) & ~0xfffffff) == 0 \ | |
3260 | ? ((v) & ~0x3ffffff) == 0 \ | |
3261 | ? ((v) & ~0x1ffffff) == 0 \ | |
3262 | ? 7 \ | |
3263 | : 6 \ | |
3264 | : ((v) & ~0x7ffffff) == 0 \ | |
3265 | ? 5 \ | |
3266 | : 4 \ | |
3267 | : ((v) & ~0x3fffffff) == 0 \ | |
3268 | ? ((v) & ~0x1fffffff) == 0 \ | |
3269 | ? 3 \ | |
3270 | : 2 \ | |
3271 | : ((v) & ~0x7fffffff) == 0 \ | |
3272 | ? 1 \ | |
3273 | : 0) | |
3274 | ||
3275 | /* load_register() | |
3276 | * This routine generates the least number of instructions neccessary to load | |
3277 | * an absolute expression value into a register. | |
3278 | */ | |
3279 | static void | |
3280 | load_register (counter, reg, ep, dbl) | |
3281 | int *counter; | |
3282 | int reg; | |
3283 | expressionS *ep; | |
3284 | int dbl; | |
3285 | { | |
3286 | int freg; | |
3287 | expressionS hi32, lo32; | |
3288 | ||
3289 | if (ep->X_op != O_big) | |
3290 | { | |
3291 | assert (ep->X_op == O_constant); | |
3292 | if (ep->X_add_number < 0x8000 | |
3293 | && (ep->X_add_number >= 0 | |
3294 | || (ep->X_add_number >= -0x8000 | |
3295 | && (! dbl | |
3296 | || ! ep->X_unsigned | |
3297 | || sizeof (ep->X_add_number) > 4)))) | |
3298 | { | |
3299 | /* We can handle 16 bit signed values with an addiu to | |
3300 | $zero. No need to ever use daddiu here, since $zero and | |
3301 | the result are always correct in 32 bit mode. */ | |
3302 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3303 | (int) BFD_RELOC_LO16); | |
3304 | return; | |
3305 | } | |
3306 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3307 | { | |
3308 | /* We can handle 16 bit unsigned values with an ori to | |
3309 | $zero. */ | |
3310 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3311 | (int) BFD_RELOC_LO16); | |
3312 | return; | |
3313 | } | |
3314 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 | |
3315 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
3316 | == ~ (offsetT) 0x7fffffff)) | |
3317 | && (! dbl | |
3318 | || ! ep->X_unsigned | |
3319 | || sizeof (ep->X_add_number) > 4 | |
3320 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3321 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3322 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3323 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3324 | && ! dbl |
3325 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3326 | == ~ (offsetT) 0xffffffff))) | |
3327 | { | |
3328 | /* 32 bit values require an lui. */ | |
3329 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3330 | (int) BFD_RELOC_HI16); | |
3331 | if ((ep->X_add_number & 0xffff) != 0) | |
3332 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3333 | (int) BFD_RELOC_LO16); | |
3334 | return; | |
3335 | } | |
3336 | } | |
3337 | ||
3338 | /* The value is larger than 32 bits. */ | |
3339 | ||
ca4e0257 | 3340 | if (HAVE_32BIT_GPRS) |
252b5132 | 3341 | { |
956cd1d6 TS |
3342 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3343 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3344 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3345 | (int) BFD_RELOC_LO16); | |
3346 | return; | |
3347 | } | |
3348 | ||
3349 | if (ep->X_op != O_big) | |
3350 | { | |
3351 | hi32 = *ep; | |
3352 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3353 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3354 | hi32.X_add_number &= 0xffffffff; | |
3355 | lo32 = *ep; | |
3356 | lo32.X_add_number &= 0xffffffff; | |
3357 | } | |
3358 | else | |
3359 | { | |
3360 | assert (ep->X_add_number > 2); | |
3361 | if (ep->X_add_number == 3) | |
3362 | generic_bignum[3] = 0; | |
3363 | else if (ep->X_add_number > 4) | |
3364 | as_bad (_("Number larger than 64 bits")); | |
3365 | lo32.X_op = O_constant; | |
3366 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3367 | hi32.X_op = O_constant; | |
3368 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3369 | } | |
3370 | ||
3371 | if (hi32.X_add_number == 0) | |
3372 | freg = 0; | |
3373 | else | |
3374 | { | |
3375 | int shift, bit; | |
3376 | unsigned long hi, lo; | |
3377 | ||
956cd1d6 | 3378 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3379 | { |
3380 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3381 | { | |
3382 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3383 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3384 | return; |
3385 | } | |
3386 | if (lo32.X_add_number & 0x80000000) | |
3387 | { | |
3388 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3389 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3390 | if (lo32.X_add_number & 0xffff) |
3391 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3392 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3393 | return; |
3394 | } | |
3395 | } | |
252b5132 RH |
3396 | |
3397 | /* Check for 16bit shifted constant. We know that hi32 is | |
3398 | non-zero, so start the mask on the first bit of the hi32 | |
3399 | value. */ | |
3400 | shift = 17; | |
3401 | do | |
beae10d5 KH |
3402 | { |
3403 | unsigned long himask, lomask; | |
3404 | ||
3405 | if (shift < 32) | |
3406 | { | |
3407 | himask = 0xffff >> (32 - shift); | |
3408 | lomask = (0xffff << shift) & 0xffffffff; | |
3409 | } | |
3410 | else | |
3411 | { | |
3412 | himask = 0xffff << (shift - 32); | |
3413 | lomask = 0; | |
3414 | } | |
3415 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3416 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3417 | { | |
3418 | expressionS tmp; | |
3419 | ||
3420 | tmp.X_op = O_constant; | |
3421 | if (shift < 32) | |
3422 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3423 | | (lo32.X_add_number >> shift)); | |
3424 | else | |
3425 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3426 | macro_build ((char *) NULL, counter, &tmp, | |
3427 | "ori", "t,r,i", reg, 0, | |
3428 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 3429 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3430 | (shift >= 32) ? "dsll32" : "dsll", |
3431 | "d,w,<", reg, reg, | |
3432 | (shift >= 32) ? shift - 32 : shift); | |
3433 | return; | |
3434 | } | |
3435 | shift++; | |
3436 | } | |
3437 | while (shift <= (64 - 16)); | |
252b5132 RH |
3438 | |
3439 | /* Find the bit number of the lowest one bit, and store the | |
3440 | shifted value in hi/lo. */ | |
3441 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3442 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3443 | if (lo != 0) | |
3444 | { | |
3445 | bit = 0; | |
3446 | while ((lo & 1) == 0) | |
3447 | { | |
3448 | lo >>= 1; | |
3449 | ++bit; | |
3450 | } | |
3451 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3452 | hi >>= bit; | |
3453 | } | |
3454 | else | |
3455 | { | |
3456 | bit = 32; | |
3457 | while ((hi & 1) == 0) | |
3458 | { | |
3459 | hi >>= 1; | |
3460 | ++bit; | |
3461 | } | |
3462 | lo = hi; | |
3463 | hi = 0; | |
3464 | } | |
3465 | ||
3466 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3467 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3468 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3469 | { |
3470 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3471 | if (shift != 0) |
beae10d5 | 3472 | { |
252b5132 RH |
3473 | expressionS tmp; |
3474 | ||
3475 | /* This instruction will set the register to be all | |
3476 | ones. */ | |
beae10d5 KH |
3477 | tmp.X_op = O_constant; |
3478 | tmp.X_add_number = (offsetT) -1; | |
3479 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3480 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3481 | if (bit != 0) |
3482 | { | |
3483 | bit += shift; | |
2396cfb9 | 3484 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3485 | (bit >= 32) ? "dsll32" : "dsll", |
3486 | "d,w,<", reg, reg, | |
3487 | (bit >= 32) ? bit - 32 : bit); | |
3488 | } | |
2396cfb9 | 3489 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 | 3490 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3491 | "d,w,<", reg, reg, |
252b5132 | 3492 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3493 | return; |
3494 | } | |
3495 | } | |
252b5132 RH |
3496 | |
3497 | /* Sign extend hi32 before calling load_register, because we can | |
3498 | generally get better code when we load a sign extended value. */ | |
3499 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3500 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3501 | load_register (counter, reg, &hi32, 0); |
3502 | freg = reg; | |
3503 | } | |
3504 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3505 | { | |
3506 | if (freg != 0) | |
3507 | { | |
2396cfb9 TS |
3508 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3509 | "dsll32", "d,w,<", reg, freg, 0); | |
252b5132 RH |
3510 | freg = reg; |
3511 | } | |
3512 | } | |
3513 | else | |
3514 | { | |
3515 | expressionS mid16; | |
3516 | ||
956cd1d6 | 3517 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3518 | { |
252b5132 RH |
3519 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3520 | (int) BFD_RELOC_HI16); | |
956cd1d6 TS |
3521 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3522 | "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3523 | return; |
3524 | } | |
252b5132 RH |
3525 | |
3526 | if (freg != 0) | |
3527 | { | |
956cd1d6 TS |
3528 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3529 | "d,w,<", reg, freg, 16); | |
252b5132 RH |
3530 | freg = reg; |
3531 | } | |
3532 | mid16 = lo32; | |
3533 | mid16.X_add_number >>= 16; | |
3534 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3535 | freg, (int) BFD_RELOC_LO16); | |
956cd1d6 TS |
3536 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3537 | "d,w,<", reg, reg, 16); | |
252b5132 RH |
3538 | freg = reg; |
3539 | } | |
3540 | if ((lo32.X_add_number & 0xffff) != 0) | |
3541 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3542 | (int) BFD_RELOC_LO16); | |
3543 | } | |
3544 | ||
3545 | /* Load an address into a register. */ | |
3546 | ||
3547 | static void | |
d6bc6245 | 3548 | load_address (counter, reg, ep, dbl, used_at) |
252b5132 RH |
3549 | int *counter; |
3550 | int reg; | |
3551 | expressionS *ep; | |
d6bc6245 TS |
3552 | int dbl; |
3553 | int *used_at; | |
252b5132 RH |
3554 | { |
3555 | char *p; | |
3556 | ||
3557 | if (ep->X_op != O_constant | |
3558 | && ep->X_op != O_symbol) | |
3559 | { | |
3560 | as_bad (_("expression too complex")); | |
3561 | ep->X_op = O_constant; | |
3562 | } | |
3563 | ||
3564 | if (ep->X_op == O_constant) | |
3565 | { | |
d6bc6245 | 3566 | load_register (counter, reg, ep, dbl); |
252b5132 RH |
3567 | return; |
3568 | } | |
3569 | ||
3570 | if (mips_pic == NO_PIC) | |
3571 | { | |
3572 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3573 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3574 | Otherwise we want |
3575 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3576 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3577 | If we have an addend, we always use the latter form. |
76b3015f | 3578 | |
d6bc6245 TS |
3579 | With 64bit address space and a usable $at we want |
3580 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3581 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3582 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3583 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3584 | dsll32 $reg,0 | |
3585 | dadd $reg,$reg,$at | |
76b3015f | 3586 | |
d6bc6245 TS |
3587 | If $at is already in use, we use an path which is suboptimal |
3588 | on superscalar processors. | |
3589 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3590 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3591 | dsll $reg,16 | |
3592 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3593 | dsll $reg,16 | |
3594 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3595 | */ | |
956cd1d6 | 3596 | if (dbl) |
d6bc6245 TS |
3597 | { |
3598 | p = NULL; | |
3599 | ||
3600 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
3601 | hold the data for such large chunks. */ | |
3602 | ||
3603 | if (*used_at == 0) | |
3604 | { | |
3605 | macro_build (p, counter, ep, "lui", "t,u", | |
3606 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3607 | macro_build (p, counter, ep, "lui", "t,u", | |
3608 | AT, (int) BFD_RELOC_HI16_S); | |
3609 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3610 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3611 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3612 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3613 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
3614 | "d,w,<", reg, reg, 0); | |
3615 | macro_build (p, counter, (expressionS *) NULL, "dadd", | |
3616 | "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3617 | *used_at = 1; |
3618 | } | |
3619 | else | |
3620 | { | |
3621 | macro_build (p, counter, ep, "lui", "t,u", | |
3622 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3623 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3624 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
3625 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3626 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3627 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3628 | reg, reg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
3629 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3630 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3631 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3632 | reg, reg, (int) BFD_RELOC_LO16); | |
3633 | } | |
3634 | } | |
252b5132 RH |
3635 | else |
3636 | { | |
d6bc6245 TS |
3637 | p = NULL; |
3638 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET | |
3639 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3640 | { | |
3641 | frag_grow (20); | |
3642 | macro_build ((char *) NULL, counter, ep, | |
cdf6fd85 TS |
3643 | dbl ? "daddiu" : "addiu", "t,r,j", reg, GP, |
3644 | (int) BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3645 | p = frag_var (rs_machine_dependent, 8, 0, |
3646 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3647 | mips_opts.warn_about_macros), | |
956cd1d6 | 3648 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3649 | } |
3650 | macro_build_lui (p, counter, ep, reg); | |
3651 | if (p != NULL) | |
3652 | p += 4; | |
956cd1d6 | 3653 | macro_build (p, counter, ep, dbl ? "daddiu" : "addiu", |
d6bc6245 TS |
3654 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3655 | } | |
252b5132 RH |
3656 | } |
3657 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3658 | { | |
3659 | expressionS ex; | |
3660 | ||
3661 | /* If this is a reference to an external symbol, we want | |
3662 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3663 | Otherwise we want | |
3664 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3665 | nop | |
3666 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3667 | If there is a constant, it must be added in after. */ | |
3668 | ex.X_add_number = ep->X_add_number; | |
3669 | ep->X_add_number = 0; | |
3670 | frag_grow (20); | |
3671 | macro_build ((char *) NULL, counter, ep, | |
ca4e0257 | 3672 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
3673 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3674 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3675 | p = frag_var (rs_machine_dependent, 4, 0, | |
3676 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3677 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3678 | macro_build (p, counter, ep, | |
ca4e0257 | 3679 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3680 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3681 | if (ex.X_add_number != 0) | |
3682 | { | |
3683 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3684 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3685 | ex.X_op = O_constant; | |
3686 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3687 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3688 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3689 | } | |
3690 | } | |
3691 | else if (mips_pic == SVR4_PIC) | |
3692 | { | |
3693 | expressionS ex; | |
3694 | int off; | |
3695 | ||
3696 | /* This is the large GOT case. If this is a reference to an | |
3697 | external symbol, we want | |
3698 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3699 | addu $reg,$reg,$gp | |
3700 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3701 | Otherwise, for a reference to a local symbol, we want | |
3702 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3703 | nop | |
3704 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3705 | If there is a constant, it must be added in after. */ | |
3706 | ex.X_add_number = ep->X_add_number; | |
3707 | ep->X_add_number = 0; | |
3708 | if (reg_needs_delay (GP)) | |
3709 | off = 4; | |
3710 | else | |
3711 | off = 0; | |
3712 | frag_grow (32); | |
3713 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3714 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3715 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
956cd1d6 TS |
3716 | dbl ? "daddu" : "addu", "d,v,t", reg, reg, GP); |
3717 | macro_build ((char *) NULL, counter, ep, dbl ? "ld" : "lw", | |
252b5132 RH |
3718 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3719 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3720 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3721 | mips_opts.warn_about_macros), | |
956cd1d6 | 3722 | ep->X_add_symbol, 0, NULL); |
252b5132 RH |
3723 | if (off > 0) |
3724 | { | |
3725 | /* We need a nop before loading from $gp. This special | |
3726 | check is required because the lui which starts the main | |
3727 | instruction stream does not refer to $gp, and so will not | |
3728 | insert the nop which may be required. */ | |
3729 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3730 | p += 4; | |
3731 | } | |
956cd1d6 | 3732 | macro_build (p, counter, ep, dbl ? "ld" : "lw", |
252b5132 RH |
3733 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3734 | p += 4; | |
3735 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3736 | p += 4; | |
956cd1d6 | 3737 | macro_build (p, counter, ep, dbl ? "daddiu" : "addiu", |
252b5132 RH |
3738 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3739 | if (ex.X_add_number != 0) | |
3740 | { | |
3741 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3742 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3743 | ex.X_op = O_constant; | |
956cd1d6 | 3744 | macro_build ((char *) NULL, counter, &ex, dbl ? "daddiu" : "addiu", |
252b5132 RH |
3745 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3746 | } | |
3747 | } | |
3748 | else if (mips_pic == EMBEDDED_PIC) | |
3749 | { | |
3750 | /* We always do | |
cdf6fd85 | 3751 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 | 3752 | */ |
cdf6fd85 TS |
3753 | macro_build ((char *) NULL, counter, ep, dbl ? "daddiu" : "addiu", |
3754 | "t,r,j", reg, GP, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
3755 | } |
3756 | else | |
3757 | abort (); | |
3758 | } | |
3759 | ||
ea1fb5dc RS |
3760 | /* Move the contents of register SOURCE into register DEST. */ |
3761 | ||
3762 | static void | |
3763 | move_register (counter, dest, source) | |
3764 | int *counter; | |
3765 | int dest; | |
3766 | int source; | |
3767 | { | |
3768 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3769 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
3770 | "d,v,t", dest, source, 0); | |
3771 | } | |
3772 | ||
252b5132 RH |
3773 | /* |
3774 | * Build macros | |
3775 | * This routine implements the seemingly endless macro or synthesized | |
3776 | * instructions and addressing modes in the mips assembly language. Many | |
3777 | * of these macros are simple and are similar to each other. These could | |
3778 | * probably be handled by some kind of table or grammer aproach instead of | |
3779 | * this verbose method. Others are not simple macros but are more like | |
3780 | * optimizing code generation. | |
3781 | * One interesting optimization is when several store macros appear | |
3782 | * consecutivly that would load AT with the upper half of the same address. | |
3783 | * The ensuing load upper instructions are ommited. This implies some kind | |
3784 | * of global optimization. We currently only optimize within a single macro. | |
3785 | * For many of the load and store macros if the address is specified as a | |
3786 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3787 | * first load register 'at' with zero and use it as the base register. The | |
3788 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3789 | * we're missing. | |
3790 | */ | |
3791 | static void | |
3792 | macro (ip) | |
3793 | struct mips_cl_insn *ip; | |
3794 | { | |
3795 | register int treg, sreg, dreg, breg; | |
3796 | int tempreg; | |
3797 | int mask; | |
3798 | int icnt = 0; | |
43841e91 | 3799 | int used_at = 0; |
252b5132 RH |
3800 | expressionS expr1; |
3801 | const char *s; | |
3802 | const char *s2; | |
3803 | const char *fmt; | |
3804 | int likely = 0; | |
3805 | int dbl = 0; | |
3806 | int coproc = 0; | |
3807 | int lr = 0; | |
3808 | int imm = 0; | |
3809 | offsetT maxnum; | |
3810 | int off; | |
3811 | bfd_reloc_code_real_type r; | |
3812 | char *p; | |
3813 | int hold_mips_optimize; | |
3814 | ||
3815 | assert (! mips_opts.mips16); | |
3816 | ||
3817 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3818 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3819 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3820 | mask = ip->insn_mo->mask; | |
3821 | ||
3822 | expr1.X_op = O_constant; | |
3823 | expr1.X_op_symbol = NULL; | |
3824 | expr1.X_add_symbol = NULL; | |
3825 | expr1.X_add_number = 1; | |
3826 | ||
3827 | switch (mask) | |
3828 | { | |
3829 | case M_DABS: | |
3830 | dbl = 1; | |
3831 | case M_ABS: | |
3832 | /* bgez $a0,.+12 | |
3833 | move v0,$a0 | |
3834 | sub v0,$zero,$a0 | |
3835 | */ | |
3836 | ||
3837 | mips_emit_delays (true); | |
3838 | ++mips_opts.noreorder; | |
3839 | mips_any_noreorder = 1; | |
3840 | ||
3841 | expr1.X_add_number = 8; | |
3842 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
3843 | if (dreg == sreg) | |
2396cfb9 TS |
3844 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
3845 | 0); | |
252b5132 | 3846 | else |
ea1fb5dc | 3847 | move_register (&icnt, dreg, sreg); |
2396cfb9 | 3848 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 3849 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
3850 | |
3851 | --mips_opts.noreorder; | |
3852 | return; | |
3853 | ||
3854 | case M_ADD_I: | |
3855 | s = "addi"; | |
3856 | s2 = "add"; | |
3857 | goto do_addi; | |
3858 | case M_ADDU_I: | |
3859 | s = "addiu"; | |
3860 | s2 = "addu"; | |
3861 | goto do_addi; | |
3862 | case M_DADD_I: | |
3863 | dbl = 1; | |
3864 | s = "daddi"; | |
3865 | s2 = "dadd"; | |
3866 | goto do_addi; | |
3867 | case M_DADDU_I: | |
3868 | dbl = 1; | |
3869 | s = "daddiu"; | |
3870 | s2 = "daddu"; | |
3871 | do_addi: | |
3872 | if (imm_expr.X_op == O_constant | |
3873 | && imm_expr.X_add_number >= -0x8000 | |
3874 | && imm_expr.X_add_number < 0x8000) | |
3875 | { | |
3876 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
3877 | (int) BFD_RELOC_LO16); | |
3878 | return; | |
3879 | } | |
3880 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
3881 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
3882 | treg, sreg, AT); | |
252b5132 RH |
3883 | break; |
3884 | ||
3885 | case M_AND_I: | |
3886 | s = "andi"; | |
3887 | s2 = "and"; | |
3888 | goto do_bit; | |
3889 | case M_OR_I: | |
3890 | s = "ori"; | |
3891 | s2 = "or"; | |
3892 | goto do_bit; | |
3893 | case M_NOR_I: | |
3894 | s = ""; | |
3895 | s2 = "nor"; | |
3896 | goto do_bit; | |
3897 | case M_XOR_I: | |
3898 | s = "xori"; | |
3899 | s2 = "xor"; | |
3900 | do_bit: | |
3901 | if (imm_expr.X_op == O_constant | |
3902 | && imm_expr.X_add_number >= 0 | |
3903 | && imm_expr.X_add_number < 0x10000) | |
3904 | { | |
3905 | if (mask != M_NOR_I) | |
3906 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
3907 | sreg, (int) BFD_RELOC_LO16); | |
3908 | else | |
3909 | { | |
3910 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
3911 | treg, sreg, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3912 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
3913 | "d,v,t", treg, treg, 0); | |
252b5132 RH |
3914 | } |
3915 | return; | |
3916 | } | |
3917 | ||
d6bc6245 | 3918 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
3919 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
3920 | treg, sreg, AT); | |
252b5132 RH |
3921 | break; |
3922 | ||
3923 | case M_BEQ_I: | |
3924 | s = "beq"; | |
3925 | goto beq_i; | |
3926 | case M_BEQL_I: | |
3927 | s = "beql"; | |
3928 | likely = 1; | |
3929 | goto beq_i; | |
3930 | case M_BNE_I: | |
3931 | s = "bne"; | |
3932 | goto beq_i; | |
3933 | case M_BNEL_I: | |
3934 | s = "bnel"; | |
3935 | likely = 1; | |
3936 | beq_i: | |
3937 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3938 | { | |
3939 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
3940 | 0); | |
3941 | return; | |
3942 | } | |
3943 | load_register (&icnt, AT, &imm_expr, 0); | |
3944 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); | |
3945 | break; | |
3946 | ||
3947 | case M_BGEL: | |
3948 | likely = 1; | |
3949 | case M_BGE: | |
3950 | if (treg == 0) | |
3951 | { | |
3952 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 3953 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
3954 | return; |
3955 | } | |
3956 | if (sreg == 0) | |
3957 | { | |
3958 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 3959 | likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
3960 | return; |
3961 | } | |
2396cfb9 TS |
3962 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
3963 | AT, sreg, treg); | |
252b5132 | 3964 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 3965 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
3966 | break; |
3967 | ||
3968 | case M_BGTL_I: | |
3969 | likely = 1; | |
3970 | case M_BGT_I: | |
3971 | /* check for > max integer */ | |
3972 | maxnum = 0x7fffffff; | |
ca4e0257 | 3973 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
3974 | { |
3975 | maxnum <<= 16; | |
3976 | maxnum |= 0xffff; | |
3977 | maxnum <<= 16; | |
3978 | maxnum |= 0xffff; | |
3979 | } | |
3980 | if (imm_expr.X_op == O_constant | |
3981 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 3982 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
3983 | { |
3984 | do_false: | |
3985 | /* result is always false */ | |
3986 | if (! likely) | |
3987 | { | |
39c0a331 L |
3988 | if (warn_nops) |
3989 | as_warn (_("Branch %s is always false (nop)"), | |
3990 | ip->insn_mo->name); | |
2396cfb9 TS |
3991 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
3992 | "", 0); | |
252b5132 RH |
3993 | } |
3994 | else | |
3995 | { | |
39c0a331 L |
3996 | if (warn_nops) |
3997 | as_warn (_("Branch likely %s is always false"), | |
3998 | ip->insn_mo->name); | |
252b5132 RH |
3999 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
4000 | "s,t,p", 0, 0); | |
4001 | } | |
4002 | return; | |
4003 | } | |
4004 | if (imm_expr.X_op != O_constant) | |
4005 | as_bad (_("Unsupported large constant")); | |
4006 | imm_expr.X_add_number++; | |
4007 | /* FALLTHROUGH */ | |
4008 | case M_BGE_I: | |
4009 | case M_BGEL_I: | |
4010 | if (mask == M_BGEL_I) | |
4011 | likely = 1; | |
4012 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4013 | { | |
4014 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4015 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4016 | return; |
4017 | } | |
4018 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4019 | { | |
4020 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4021 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4022 | return; |
4023 | } | |
4024 | maxnum = 0x7fffffff; | |
ca4e0257 | 4025 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4026 | { |
4027 | maxnum <<= 16; | |
4028 | maxnum |= 0xffff; | |
4029 | maxnum <<= 16; | |
4030 | maxnum |= 0xffff; | |
4031 | } | |
4032 | maxnum = - maxnum - 1; | |
4033 | if (imm_expr.X_op == O_constant | |
4034 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4035 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4036 | { |
4037 | do_true: | |
4038 | /* result is always true */ | |
4039 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4040 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4041 | return; | |
4042 | } | |
4043 | set_at (&icnt, sreg, 0); | |
4044 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4045 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4046 | break; |
4047 | ||
4048 | case M_BGEUL: | |
4049 | likely = 1; | |
4050 | case M_BGEU: | |
4051 | if (treg == 0) | |
4052 | goto do_true; | |
4053 | if (sreg == 0) | |
4054 | { | |
4055 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4056 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4057 | return; |
4058 | } | |
2396cfb9 TS |
4059 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4060 | "d,v,t", AT, sreg, treg); | |
252b5132 | 4061 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4062 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4063 | break; |
4064 | ||
4065 | case M_BGTUL_I: | |
4066 | likely = 1; | |
4067 | case M_BGTU_I: | |
4068 | if (sreg == 0 | |
ca4e0257 | 4069 | || (HAVE_32BIT_GPRS |
252b5132 | 4070 | && imm_expr.X_op == O_constant |
956cd1d6 | 4071 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4072 | goto do_false; |
4073 | if (imm_expr.X_op != O_constant) | |
4074 | as_bad (_("Unsupported large constant")); | |
4075 | imm_expr.X_add_number++; | |
4076 | /* FALLTHROUGH */ | |
4077 | case M_BGEU_I: | |
4078 | case M_BGEUL_I: | |
4079 | if (mask == M_BGEUL_I) | |
4080 | likely = 1; | |
4081 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4082 | goto do_true; | |
4083 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4084 | { | |
4085 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4086 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4087 | return; |
4088 | } | |
4089 | set_at (&icnt, sreg, 1); | |
4090 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4091 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4092 | break; |
4093 | ||
4094 | case M_BGTL: | |
4095 | likely = 1; | |
4096 | case M_BGT: | |
4097 | if (treg == 0) | |
4098 | { | |
4099 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4100 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4101 | return; |
4102 | } | |
4103 | if (sreg == 0) | |
4104 | { | |
4105 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4106 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4107 | return; |
4108 | } | |
2396cfb9 TS |
4109 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4110 | AT, treg, sreg); | |
252b5132 | 4111 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4112 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4113 | break; |
4114 | ||
4115 | case M_BGTUL: | |
4116 | likely = 1; | |
4117 | case M_BGTU: | |
4118 | if (treg == 0) | |
4119 | { | |
4120 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4121 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4122 | return; |
4123 | } | |
4124 | if (sreg == 0) | |
4125 | goto do_false; | |
2396cfb9 TS |
4126 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4127 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4128 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4129 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4130 | break; |
4131 | ||
4132 | case M_BLEL: | |
4133 | likely = 1; | |
4134 | case M_BLE: | |
4135 | if (treg == 0) | |
4136 | { | |
4137 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4138 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4139 | return; |
4140 | } | |
4141 | if (sreg == 0) | |
4142 | { | |
4143 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4144 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4145 | return; |
4146 | } | |
2396cfb9 TS |
4147 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4148 | AT, treg, sreg); | |
252b5132 | 4149 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4150 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4151 | break; |
4152 | ||
4153 | case M_BLEL_I: | |
4154 | likely = 1; | |
4155 | case M_BLE_I: | |
4156 | maxnum = 0x7fffffff; | |
ca4e0257 | 4157 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4158 | { |
4159 | maxnum <<= 16; | |
4160 | maxnum |= 0xffff; | |
4161 | maxnum <<= 16; | |
4162 | maxnum |= 0xffff; | |
4163 | } | |
4164 | if (imm_expr.X_op == O_constant | |
4165 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4166 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4167 | goto do_true; |
4168 | if (imm_expr.X_op != O_constant) | |
4169 | as_bad (_("Unsupported large constant")); | |
4170 | imm_expr.X_add_number++; | |
4171 | /* FALLTHROUGH */ | |
4172 | case M_BLT_I: | |
4173 | case M_BLTL_I: | |
4174 | if (mask == M_BLTL_I) | |
4175 | likely = 1; | |
4176 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4177 | { | |
4178 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4179 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4180 | return; |
4181 | } | |
4182 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4183 | { | |
4184 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4185 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4186 | return; |
4187 | } | |
4188 | set_at (&icnt, sreg, 0); | |
4189 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4190 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4191 | break; |
4192 | ||
4193 | case M_BLEUL: | |
4194 | likely = 1; | |
4195 | case M_BLEU: | |
4196 | if (treg == 0) | |
4197 | { | |
4198 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4199 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4200 | return; |
4201 | } | |
4202 | if (sreg == 0) | |
4203 | goto do_true; | |
2396cfb9 TS |
4204 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4205 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4206 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4207 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4208 | break; |
4209 | ||
4210 | case M_BLEUL_I: | |
4211 | likely = 1; | |
4212 | case M_BLEU_I: | |
4213 | if (sreg == 0 | |
ca4e0257 | 4214 | || (HAVE_32BIT_GPRS |
252b5132 | 4215 | && imm_expr.X_op == O_constant |
956cd1d6 | 4216 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4217 | goto do_true; |
4218 | if (imm_expr.X_op != O_constant) | |
4219 | as_bad (_("Unsupported large constant")); | |
4220 | imm_expr.X_add_number++; | |
4221 | /* FALLTHROUGH */ | |
4222 | case M_BLTU_I: | |
4223 | case M_BLTUL_I: | |
4224 | if (mask == M_BLTUL_I) | |
4225 | likely = 1; | |
4226 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4227 | goto do_false; | |
4228 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4229 | { | |
4230 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4231 | likely ? "beql" : "beq", | |
4232 | "s,t,p", sreg, 0); | |
4233 | return; | |
4234 | } | |
4235 | set_at (&icnt, sreg, 1); | |
4236 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4237 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4238 | break; |
4239 | ||
4240 | case M_BLTL: | |
4241 | likely = 1; | |
4242 | case M_BLT: | |
4243 | if (treg == 0) | |
4244 | { | |
4245 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4246 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4247 | return; |
4248 | } | |
4249 | if (sreg == 0) | |
4250 | { | |
4251 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4252 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4253 | return; |
4254 | } | |
2396cfb9 TS |
4255 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4256 | AT, sreg, treg); | |
252b5132 | 4257 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4258 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4259 | break; |
4260 | ||
4261 | case M_BLTUL: | |
4262 | likely = 1; | |
4263 | case M_BLTU: | |
4264 | if (treg == 0) | |
4265 | goto do_false; | |
4266 | if (sreg == 0) | |
4267 | { | |
4268 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4269 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4270 | return; |
4271 | } | |
2396cfb9 TS |
4272 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4273 | "d,v,t", AT, sreg, | |
252b5132 RH |
4274 | treg); |
4275 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4276 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4277 | break; |
4278 | ||
4279 | case M_DDIV_3: | |
4280 | dbl = 1; | |
4281 | case M_DIV_3: | |
4282 | s = "mflo"; | |
4283 | goto do_div3; | |
4284 | case M_DREM_3: | |
4285 | dbl = 1; | |
4286 | case M_REM_3: | |
4287 | s = "mfhi"; | |
4288 | do_div3: | |
4289 | if (treg == 0) | |
4290 | { | |
4291 | as_warn (_("Divide by zero.")); | |
4292 | if (mips_trap) | |
2396cfb9 TS |
4293 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4294 | "s,t", 0, 0); | |
252b5132 | 4295 | else |
2396cfb9 TS |
4296 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4297 | "c", 7); | |
252b5132 RH |
4298 | return; |
4299 | } | |
4300 | ||
4301 | mips_emit_delays (true); | |
4302 | ++mips_opts.noreorder; | |
4303 | mips_any_noreorder = 1; | |
4304 | if (mips_trap) | |
4305 | { | |
2396cfb9 TS |
4306 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4307 | "s,t", treg, 0); | |
4308 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a41af64 | 4309 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4310 | } |
4311 | else | |
4312 | { | |
4313 | expr1.X_add_number = 8; | |
4314 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 | 4315 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4316 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
2396cfb9 TS |
4317 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4318 | "c", 7); | |
252b5132 RH |
4319 | } |
4320 | expr1.X_add_number = -1; | |
4321 | macro_build ((char *) NULL, &icnt, &expr1, | |
4322 | dbl ? "daddiu" : "addiu", | |
4323 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4324 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4325 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4326 | if (dbl) | |
4327 | { | |
4328 | expr1.X_add_number = 1; | |
4329 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4330 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4331 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
4332 | "d,w,<", AT, AT, 31); | |
252b5132 RH |
4333 | } |
4334 | else | |
4335 | { | |
4336 | expr1.X_add_number = 0x80000000; | |
4337 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4338 | (int) BFD_RELOC_HI16); | |
4339 | } | |
4340 | if (mips_trap) | |
4341 | { | |
2396cfb9 TS |
4342 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4343 | "s,t", sreg, AT); | |
252b5132 RH |
4344 | /* We want to close the noreorder block as soon as possible, so |
4345 | that later insns are available for delay slot filling. */ | |
4346 | --mips_opts.noreorder; | |
4347 | } | |
4348 | else | |
4349 | { | |
4350 | expr1.X_add_number = 8; | |
4351 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2396cfb9 TS |
4352 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4353 | 0); | |
252b5132 RH |
4354 | |
4355 | /* We want to close the noreorder block as soon as possible, so | |
4356 | that later insns are available for delay slot filling. */ | |
4357 | --mips_opts.noreorder; | |
4358 | ||
2396cfb9 TS |
4359 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4360 | "c", 6); | |
252b5132 | 4361 | } |
2396cfb9 | 4362 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
252b5132 RH |
4363 | break; |
4364 | ||
4365 | case M_DIV_3I: | |
4366 | s = "div"; | |
4367 | s2 = "mflo"; | |
4368 | goto do_divi; | |
4369 | case M_DIVU_3I: | |
4370 | s = "divu"; | |
4371 | s2 = "mflo"; | |
4372 | goto do_divi; | |
4373 | case M_REM_3I: | |
4374 | s = "div"; | |
4375 | s2 = "mfhi"; | |
4376 | goto do_divi; | |
4377 | case M_REMU_3I: | |
4378 | s = "divu"; | |
4379 | s2 = "mfhi"; | |
4380 | goto do_divi; | |
4381 | case M_DDIV_3I: | |
4382 | dbl = 1; | |
4383 | s = "ddiv"; | |
4384 | s2 = "mflo"; | |
4385 | goto do_divi; | |
4386 | case M_DDIVU_3I: | |
4387 | dbl = 1; | |
4388 | s = "ddivu"; | |
4389 | s2 = "mflo"; | |
4390 | goto do_divi; | |
4391 | case M_DREM_3I: | |
4392 | dbl = 1; | |
4393 | s = "ddiv"; | |
4394 | s2 = "mfhi"; | |
4395 | goto do_divi; | |
4396 | case M_DREMU_3I: | |
4397 | dbl = 1; | |
4398 | s = "ddivu"; | |
4399 | s2 = "mfhi"; | |
4400 | do_divi: | |
4401 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4402 | { | |
4403 | as_warn (_("Divide by zero.")); | |
4404 | if (mips_trap) | |
2396cfb9 TS |
4405 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4406 | "s,t", 0, 0); | |
252b5132 | 4407 | else |
2396cfb9 TS |
4408 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4409 | "c", 7); | |
252b5132 RH |
4410 | return; |
4411 | } | |
4412 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4413 | { | |
4414 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4415 | move_register (&icnt, dreg, sreg); |
252b5132 | 4416 | else |
ea1fb5dc | 4417 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4418 | return; |
4419 | } | |
4420 | if (imm_expr.X_op == O_constant | |
4421 | && imm_expr.X_add_number == -1 | |
4422 | && s[strlen (s) - 1] != 'u') | |
4423 | { | |
4424 | if (strcmp (s2, "mflo") == 0) | |
4425 | { | |
2396cfb9 TS |
4426 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4427 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); | |
252b5132 RH |
4428 | } |
4429 | else | |
ea1fb5dc | 4430 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4431 | return; |
4432 | } | |
4433 | ||
4434 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4435 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4436 | sreg, AT); | |
4437 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); | |
252b5132 RH |
4438 | break; |
4439 | ||
4440 | case M_DIVU_3: | |
4441 | s = "divu"; | |
4442 | s2 = "mflo"; | |
4443 | goto do_divu3; | |
4444 | case M_REMU_3: | |
4445 | s = "divu"; | |
4446 | s2 = "mfhi"; | |
4447 | goto do_divu3; | |
4448 | case M_DDIVU_3: | |
4449 | s = "ddivu"; | |
4450 | s2 = "mflo"; | |
4451 | goto do_divu3; | |
4452 | case M_DREMU_3: | |
4453 | s = "ddivu"; | |
4454 | s2 = "mfhi"; | |
4455 | do_divu3: | |
4456 | mips_emit_delays (true); | |
4457 | ++mips_opts.noreorder; | |
4458 | mips_any_noreorder = 1; | |
4459 | if (mips_trap) | |
4460 | { | |
2396cfb9 TS |
4461 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4462 | "s,t", treg, 0); | |
4463 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", | |
4464 | sreg, treg); | |
252b5132 RH |
4465 | /* We want to close the noreorder block as soon as possible, so |
4466 | that later insns are available for delay slot filling. */ | |
4467 | --mips_opts.noreorder; | |
4468 | } | |
4469 | else | |
4470 | { | |
4471 | expr1.X_add_number = 8; | |
4472 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 TS |
4473 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4474 | sreg, treg); | |
252b5132 RH |
4475 | |
4476 | /* We want to close the noreorder block as soon as possible, so | |
4477 | that later insns are available for delay slot filling. */ | |
4478 | --mips_opts.noreorder; | |
2396cfb9 TS |
4479 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4480 | "c", 7); | |
252b5132 | 4481 | } |
2396cfb9 | 4482 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
252b5132 RH |
4483 | return; |
4484 | ||
4485 | case M_DLA_AB: | |
4486 | dbl = 1; | |
4487 | case M_LA_AB: | |
4488 | /* Load the address of a symbol into a register. If breg is not | |
4489 | zero, we then add a base register to it. */ | |
4490 | ||
afdbd6d0 CD |
4491 | if (treg == breg) |
4492 | { | |
4493 | tempreg = AT; | |
4494 | used_at = 1; | |
4495 | } | |
4496 | else | |
4497 | { | |
4498 | tempreg = treg; | |
4499 | used_at = 0; | |
4500 | } | |
4501 | ||
252b5132 RH |
4502 | /* When generating embedded PIC code, we permit expressions of |
4503 | the form | |
afdbd6d0 CD |
4504 | la $treg,foo-bar |
4505 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4506 | where bar is an address in the current section. These are used |
252b5132 RH |
4507 | when getting the addresses of functions. We don't permit |
4508 | X_add_number to be non-zero, because if the symbol is | |
4509 | external the relaxing code needs to know that any addend is | |
4510 | purely the offset to X_op_symbol. */ | |
4511 | if (mips_pic == EMBEDDED_PIC | |
4512 | && offset_expr.X_op == O_subtract | |
49309057 | 4513 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4514 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4515 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4516 | && (S_GET_SEGMENT | |
4517 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4518 | ->X_add_symbol) | |
bb2d6cd7 | 4519 | == now_seg))) |
bb2d6cd7 GK |
4520 | && (offset_expr.X_add_number == 0 |
4521 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4522 | { |
afdbd6d0 CD |
4523 | if (breg == 0) |
4524 | { | |
4525 | tempreg = treg; | |
4526 | used_at = 0; | |
4527 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4528 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4529 | } | |
4530 | else | |
4531 | { | |
4532 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4533 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4534 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4535 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
4536 | "d,v,t", tempreg, tempreg, breg); | |
4537 | } | |
252b5132 | 4538 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 4539 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
afdbd6d0 CD |
4540 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
4541 | if (! used_at) | |
4542 | return; | |
4543 | break; | |
252b5132 RH |
4544 | } |
4545 | ||
4546 | if (offset_expr.X_op != O_symbol | |
4547 | && offset_expr.X_op != O_constant) | |
4548 | { | |
4549 | as_bad (_("expression too complex")); | |
4550 | offset_expr.X_op = O_constant; | |
4551 | } | |
4552 | ||
252b5132 RH |
4553 | if (offset_expr.X_op == O_constant) |
4554 | load_register (&icnt, tempreg, &offset_expr, dbl); | |
4555 | else if (mips_pic == NO_PIC) | |
4556 | { | |
d6bc6245 | 4557 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4558 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4559 | Otherwise we want |
4560 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4561 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4562 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4563 | so we may as well always use the latter form. |
76b3015f | 4564 | |
d6bc6245 TS |
4565 | With 64bit address space and a usable $at we want |
4566 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4567 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4568 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4569 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4570 | dsll32 $tempreg,0 | |
4571 | dadd $tempreg,$tempreg,$at | |
76b3015f | 4572 | |
d6bc6245 TS |
4573 | If $at is already in use, we use an path which is suboptimal |
4574 | on superscalar processors. | |
4575 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4576 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4577 | dsll $tempreg,16 | |
4578 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4579 | dsll $tempreg,16 | |
4580 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4581 | */ | |
4582 | p = NULL; | |
4583 | if (HAVE_64BIT_ADDRESSES) | |
252b5132 | 4584 | { |
d6bc6245 TS |
4585 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4586 | hold the data for such large chunks. */ | |
4587 | ||
4588 | if (used_at == 0) | |
4589 | { | |
4590 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4591 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4592 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4593 | AT, (int) BFD_RELOC_HI16_S); | |
4594 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4595 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4596 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4597 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4598 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", |
4599 | "d,w,<", tempreg, tempreg, 0); | |
4600 | macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t", | |
d6bc6245 TS |
4601 | tempreg, tempreg, AT); |
4602 | used_at = 1; | |
4603 | } | |
4604 | else | |
4605 | { | |
4606 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4607 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4608 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4609 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 | 4610 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", |
d6bc6245 TS |
4611 | tempreg, tempreg, 16); |
4612 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4613 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 | 4614 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", |
d6bc6245 TS |
4615 | tempreg, tempreg, 16); |
4616 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4617 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4618 | } | |
4619 | } | |
4620 | else | |
4621 | { | |
4622 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4623 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4624 | { | |
4625 | frag_grow (20); | |
4626 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4627 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
cdf6fd85 | 4628 | "t,r,j", tempreg, GP, (int) BFD_RELOC_GPREL16); |
d6bc6245 TS |
4629 | p = frag_var (rs_machine_dependent, 8, 0, |
4630 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4631 | mips_opts.warn_about_macros), | |
956cd1d6 | 4632 | offset_expr.X_add_symbol, 0, NULL); |
d6bc6245 TS |
4633 | } |
4634 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4635 | if (p != NULL) | |
4636 | p += 4; | |
4637 | macro_build (p, &icnt, &offset_expr, | |
4638 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
4639 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4640 | } | |
252b5132 RH |
4641 | } |
4642 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4643 | { | |
9117d219 NC |
4644 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4645 | ||
252b5132 RH |
4646 | /* If this is a reference to an external symbol, and there |
4647 | is no constant, we want | |
4648 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4649 | or if tempreg is PIC_CALL_REG |
4650 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4651 | For a local symbol, we want |
4652 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4653 | nop | |
4654 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4655 | ||
4656 | If we have a small constant, and this is a reference to | |
4657 | an external symbol, we want | |
4658 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4659 | nop | |
4660 | addiu $tempreg,$tempreg,<constant> | |
4661 | For a local symbol, we want the same instruction | |
4662 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4663 | addiu instruction. | |
4664 | ||
4665 | If we have a large constant, and this is a reference to | |
4666 | an external symbol, we want | |
4667 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4668 | lui $at,<hiconstant> | |
4669 | addiu $at,$at,<loconstant> | |
4670 | addu $tempreg,$tempreg,$at | |
4671 | For a local symbol, we want the same instruction | |
4672 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4673 | addiu instruction. */ | |
4674 | expr1.X_add_number = offset_expr.X_add_number; | |
4675 | offset_expr.X_add_number = 0; | |
4676 | frag_grow (32); | |
9117d219 NC |
4677 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4678 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
2396cfb9 | 4679 | macro_build ((char *) NULL, &icnt, &offset_expr, dbl ? "ld" : "lw", |
9117d219 | 4680 | "t,o(b)", tempreg, lw_reloc_type, GP); |
252b5132 RH |
4681 | if (expr1.X_add_number == 0) |
4682 | { | |
4683 | int off; | |
4684 | ||
4685 | if (breg == 0) | |
4686 | off = 0; | |
4687 | else | |
4688 | { | |
4689 | /* We're going to put in an addu instruction using | |
4690 | tempreg, so we may as well insert the nop right | |
4691 | now. */ | |
4692 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4693 | "nop", ""); | |
4694 | off = 4; | |
4695 | } | |
4696 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4697 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4698 | (breg == 0 | |
4699 | ? mips_opts.warn_about_macros | |
4700 | : 0)), | |
c4e7957c | 4701 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4702 | if (breg == 0) |
4703 | { | |
4704 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4705 | p += 4; | |
4706 | } | |
4707 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4708 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4709 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4710 | /* FIXME: If breg == 0, and the next instruction uses | |
4711 | $tempreg, then if this variant case is used an extra | |
4712 | nop will be generated. */ | |
4713 | } | |
4714 | else if (expr1.X_add_number >= -0x8000 | |
4715 | && expr1.X_add_number < 0x8000) | |
4716 | { | |
4717 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4718 | "nop", ""); | |
4719 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4720 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 | 4721 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
c4e7957c TS |
4722 | frag_var (rs_machine_dependent, 0, 0, |
4723 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4724 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4725 | } |
4726 | else | |
4727 | { | |
4728 | int off1; | |
4729 | ||
4730 | /* If we are going to add in a base register, and the | |
4731 | target register and the base register are the same, | |
4732 | then we are using AT as a temporary register. Since | |
4733 | we want to load the constant into AT, we add our | |
4734 | current AT (from the global offset table) and the | |
4735 | register into the register now, and pretend we were | |
4736 | not using a base register. */ | |
4737 | if (breg != treg) | |
4738 | off1 = 0; | |
4739 | else | |
4740 | { | |
4741 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4742 | "nop", ""); | |
4743 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4744 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4745 | "d,v,t", treg, AT, breg); |
4746 | breg = 0; | |
4747 | tempreg = treg; | |
4748 | off1 = -8; | |
4749 | } | |
4750 | ||
4751 | /* Set mips_optimize around the lui instruction to avoid | |
4752 | inserting an unnecessary nop after the lw. */ | |
4753 | hold_mips_optimize = mips_optimize; | |
4754 | mips_optimize = 2; | |
c4e7957c | 4755 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
4756 | mips_optimize = hold_mips_optimize; |
4757 | ||
4758 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4759 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4760 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4761 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4762 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 4763 | "d,v,t", tempreg, tempreg, AT); |
c4e7957c TS |
4764 | frag_var (rs_machine_dependent, 0, 0, |
4765 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4766 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4767 | used_at = 1; |
4768 | } | |
4769 | } | |
4770 | else if (mips_pic == SVR4_PIC) | |
4771 | { | |
4772 | int gpdel; | |
9117d219 NC |
4773 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
4774 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
252b5132 RH |
4775 | |
4776 | /* This is the large GOT case. If this is a reference to an | |
4777 | external symbol, and there is no constant, we want | |
4778 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4779 | addu $tempreg,$tempreg,$gp | |
4780 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
4781 | or if tempreg is PIC_CALL_REG |
4782 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4783 | addu $tempreg,$tempreg,$gp | |
4784 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
4785 | For a local symbol, we want |
4786 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4787 | nop | |
4788 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4789 | ||
4790 | If we have a small constant, and this is a reference to | |
4791 | an external symbol, we want | |
4792 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4793 | addu $tempreg,$tempreg,$gp | |
4794 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4795 | nop | |
4796 | addiu $tempreg,$tempreg,<constant> | |
4797 | For a local symbol, we want | |
4798 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4799 | nop | |
4800 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4801 | ||
4802 | If we have a large constant, and this is a reference to | |
4803 | an external symbol, we want | |
4804 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4805 | addu $tempreg,$tempreg,$gp | |
4806 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4807 | lui $at,<hiconstant> | |
4808 | addiu $at,$at,<loconstant> | |
4809 | addu $tempreg,$tempreg,$at | |
4810 | For a local symbol, we want | |
4811 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4812 | lui $at,<hiconstant> | |
4813 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4814 | addu $tempreg,$tempreg,$at | |
4815 | */ | |
4816 | expr1.X_add_number = offset_expr.X_add_number; | |
4817 | offset_expr.X_add_number = 0; | |
4818 | frag_grow (52); | |
4819 | if (reg_needs_delay (GP)) | |
4820 | gpdel = 4; | |
4821 | else | |
4822 | gpdel = 0; | |
9117d219 NC |
4823 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4824 | { | |
4825 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
4826 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
4827 | } | |
252b5132 | 4828 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 4829 | tempreg, lui_reloc_type); |
252b5132 | 4830 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
ca4e0257 | 4831 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4832 | "d,v,t", tempreg, tempreg, GP); |
4833 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4834 | dbl ? "ld" : "lw", | |
9117d219 | 4835 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
4836 | if (expr1.X_add_number == 0) |
4837 | { | |
4838 | int off; | |
4839 | ||
4840 | if (breg == 0) | |
4841 | off = 0; | |
4842 | else | |
4843 | { | |
4844 | /* We're going to put in an addu instruction using | |
4845 | tempreg, so we may as well insert the nop right | |
4846 | now. */ | |
4847 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4848 | "nop", ""); | |
4849 | off = 4; | |
4850 | } | |
4851 | ||
4852 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4853 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4854 | 8 + gpdel, 0, | |
4855 | (breg == 0 | |
4856 | ? mips_opts.warn_about_macros | |
4857 | : 0)), | |
c4e7957c | 4858 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4859 | } |
4860 | else if (expr1.X_add_number >= -0x8000 | |
4861 | && expr1.X_add_number < 0x8000) | |
4862 | { | |
4863 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4864 | "nop", ""); | |
4865 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4866 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4867 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4868 | ||
4869 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4870 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4871 | (breg == 0 | |
4872 | ? mips_opts.warn_about_macros | |
4873 | : 0)), | |
c4e7957c | 4874 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4875 | } |
4876 | else | |
4877 | { | |
4878 | int adj, dreg; | |
4879 | ||
4880 | /* If we are going to add in a base register, and the | |
4881 | target register and the base register are the same, | |
4882 | then we are using AT as a temporary register. Since | |
4883 | we want to load the constant into AT, we add our | |
4884 | current AT (from the global offset table) and the | |
4885 | register into the register now, and pretend we were | |
4886 | not using a base register. */ | |
4887 | if (breg != treg) | |
4888 | { | |
4889 | adj = 0; | |
4890 | dreg = tempreg; | |
4891 | } | |
4892 | else | |
4893 | { | |
4894 | assert (tempreg == AT); | |
4895 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4896 | "nop", ""); | |
4897 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4898 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4899 | "d,v,t", treg, AT, breg); |
4900 | dreg = treg; | |
4901 | adj = 8; | |
4902 | } | |
4903 | ||
4904 | /* Set mips_optimize around the lui instruction to avoid | |
4905 | inserting an unnecessary nop after the lw. */ | |
4906 | hold_mips_optimize = mips_optimize; | |
4907 | mips_optimize = 2; | |
c4e7957c | 4908 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
4909 | mips_optimize = hold_mips_optimize; |
4910 | ||
4911 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4912 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4913 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4914 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4915 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4916 | "d,v,t", dreg, dreg, AT); |
4917 | ||
4918 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4919 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4920 | 8 + gpdel, 0, | |
4921 | (breg == 0 | |
4922 | ? mips_opts.warn_about_macros | |
4923 | : 0)), | |
c4e7957c | 4924 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4925 | |
4926 | used_at = 1; | |
4927 | } | |
4928 | ||
4929 | if (gpdel > 0) | |
4930 | { | |
4931 | /* This is needed because this instruction uses $gp, but | |
4932 | the first instruction on the main stream does not. */ | |
4933 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4934 | p += 4; | |
4935 | } | |
4936 | macro_build (p, &icnt, &offset_expr, | |
4937 | dbl ? "ld" : "lw", | |
4938 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4939 | p += 4; | |
4940 | if (expr1.X_add_number >= -0x8000 | |
4941 | && expr1.X_add_number < 0x8000) | |
4942 | { | |
4943 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4944 | p += 4; | |
4945 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4946 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4947 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4948 | /* FIXME: If add_number is 0, and there was no base | |
4949 | register, the external symbol case ended with a load, | |
4950 | so if the symbol turns out to not be external, and | |
4951 | the next instruction uses tempreg, an unnecessary nop | |
4952 | will be inserted. */ | |
4953 | } | |
4954 | else | |
4955 | { | |
4956 | if (breg == treg) | |
4957 | { | |
4958 | /* We must add in the base register now, as in the | |
4959 | external symbol case. */ | |
4960 | assert (tempreg == AT); | |
4961 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4962 | p += 4; | |
4963 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4964 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4965 | "d,v,t", treg, AT, breg); |
4966 | p += 4; | |
4967 | tempreg = treg; | |
4968 | /* We set breg to 0 because we have arranged to add | |
4969 | it in in both cases. */ | |
4970 | breg = 0; | |
4971 | } | |
4972 | ||
4973 | macro_build_lui (p, &icnt, &expr1, AT); | |
4974 | p += 4; | |
4975 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4976 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4977 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4978 | p += 4; | |
4979 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4980 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4981 | "d,v,t", tempreg, tempreg, AT); |
4982 | p += 4; | |
4983 | } | |
4984 | } | |
4985 | else if (mips_pic == EMBEDDED_PIC) | |
4986 | { | |
4987 | /* We use | |
cdf6fd85 | 4988 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4989 | */ |
4990 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 4991 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
cdf6fd85 | 4992 | "t,r,j", tempreg, GP, (int) BFD_RELOC_GPREL16); |
252b5132 RH |
4993 | } |
4994 | else | |
4995 | abort (); | |
4996 | ||
4997 | if (breg != 0) | |
4998 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4999 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5000 | "d,v,t", treg, tempreg, breg); |
5001 | ||
5002 | if (! used_at) | |
5003 | return; | |
5004 | ||
5005 | break; | |
5006 | ||
5007 | case M_J_A: | |
5008 | /* The j instruction may not be used in PIC code, since it | |
5009 | requires an absolute address. We convert it to a b | |
5010 | instruction. */ | |
5011 | if (mips_pic == NO_PIC) | |
5012 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
5013 | else | |
5014 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
5015 | return; | |
5016 | ||
5017 | /* The jal instructions must be handled as macros because when | |
5018 | generating PIC code they expand to multi-instruction | |
5019 | sequences. Normally they are simple instructions. */ | |
5020 | case M_JAL_1: | |
5021 | dreg = RA; | |
5022 | /* Fall through. */ | |
5023 | case M_JAL_2: | |
5024 | if (mips_pic == NO_PIC | |
5025 | || mips_pic == EMBEDDED_PIC) | |
5026 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
5027 | "d,s", dreg, sreg); | |
5028 | else if (mips_pic == SVR4_PIC) | |
5029 | { | |
5030 | if (sreg != PIC_CALL_REG) | |
5031 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5032 | |
252b5132 RH |
5033 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
5034 | "d,s", dreg, sreg); | |
6478892d | 5035 | if (! HAVE_NEWABI) |
252b5132 | 5036 | { |
6478892d TS |
5037 | if (mips_cprestore_offset < 0) |
5038 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5039 | else | |
5040 | { | |
5041 | expr1.X_add_number = mips_cprestore_offset; | |
5042 | macro_build ((char *) NULL, &icnt, &expr1, | |
5043 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
5044 | GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
5045 | } | |
252b5132 RH |
5046 | } |
5047 | } | |
5048 | else | |
5049 | abort (); | |
5050 | ||
5051 | return; | |
5052 | ||
5053 | case M_JAL_A: | |
5054 | if (mips_pic == NO_PIC) | |
5055 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5056 | else if (mips_pic == SVR4_PIC) | |
5057 | { | |
5058 | /* If this is a reference to an external symbol, and we are | |
5059 | using a small GOT, we want | |
5060 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5061 | nop | |
5062 | jalr $25 | |
5063 | nop | |
5064 | lw $gp,cprestore($sp) | |
5065 | The cprestore value is set using the .cprestore | |
5066 | pseudo-op. If we are using a big GOT, we want | |
5067 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5068 | addu $25,$25,$gp | |
5069 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5070 | nop | |
5071 | jalr $25 | |
5072 | nop | |
5073 | lw $gp,cprestore($sp) | |
5074 | If the symbol is not external, we want | |
5075 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5076 | nop | |
5077 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
5078 | jalr $25 | |
5079 | nop | |
5080 | lw $gp,cprestore($sp) */ | |
5081 | frag_grow (40); | |
5082 | if (! mips_big_got) | |
5083 | { | |
5084 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5085 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5086 | "t,o(b)", PIC_CALL_REG, |
5087 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
5088 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5089 | "nop", ""); | |
5090 | p = frag_var (rs_machine_dependent, 4, 0, | |
5091 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
c4e7957c | 5092 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5093 | } |
5094 | else | |
5095 | { | |
5096 | int gpdel; | |
5097 | ||
5098 | if (reg_needs_delay (GP)) | |
5099 | gpdel = 4; | |
5100 | else | |
5101 | gpdel = 0; | |
5102 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5103 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
5104 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5105 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5106 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
5107 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5108 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5109 | "t,o(b)", PIC_CALL_REG, |
5110 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5111 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5112 | "nop", ""); | |
5113 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5114 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
5115 | 0, 0), | |
c4e7957c | 5116 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5117 | if (gpdel > 0) |
5118 | { | |
5119 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5120 | p += 4; | |
5121 | } | |
5122 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5123 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5124 | "t,o(b)", PIC_CALL_REG, |
5125 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
5126 | p += 4; | |
5127 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5128 | p += 4; | |
bdaaa2e1 | 5129 | } |
252b5132 | 5130 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5131 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5132 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
5133 | (int) BFD_RELOC_LO16); | |
5134 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5135 | "jalr", "s", PIC_CALL_REG); | |
6478892d | 5136 | if (! HAVE_NEWABI) |
252b5132 | 5137 | { |
6478892d TS |
5138 | if (mips_cprestore_offset < 0) |
5139 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5140 | else | |
5141 | { | |
5142 | if (mips_opts.noreorder) | |
5143 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 5144 | "nop", ""); |
6478892d TS |
5145 | expr1.X_add_number = mips_cprestore_offset; |
5146 | macro_build ((char *) NULL, &icnt, &expr1, | |
5147 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
5148 | GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
5149 | } | |
252b5132 RH |
5150 | } |
5151 | } | |
5152 | else if (mips_pic == EMBEDDED_PIC) | |
5153 | { | |
5154 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5155 | /* The linker may expand the call to a longer sequence which | |
5156 | uses $at, so we must break rather than return. */ | |
5157 | break; | |
5158 | } | |
5159 | else | |
5160 | abort (); | |
5161 | ||
5162 | return; | |
5163 | ||
5164 | case M_LB_AB: | |
5165 | s = "lb"; | |
5166 | goto ld; | |
5167 | case M_LBU_AB: | |
5168 | s = "lbu"; | |
5169 | goto ld; | |
5170 | case M_LH_AB: | |
5171 | s = "lh"; | |
5172 | goto ld; | |
5173 | case M_LHU_AB: | |
5174 | s = "lhu"; | |
5175 | goto ld; | |
5176 | case M_LW_AB: | |
5177 | s = "lw"; | |
5178 | goto ld; | |
5179 | case M_LWC0_AB: | |
5180 | s = "lwc0"; | |
bdaaa2e1 | 5181 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5182 | coproc = 1; |
5183 | goto ld; | |
5184 | case M_LWC1_AB: | |
5185 | s = "lwc1"; | |
bdaaa2e1 | 5186 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5187 | coproc = 1; |
5188 | goto ld; | |
5189 | case M_LWC2_AB: | |
5190 | s = "lwc2"; | |
bdaaa2e1 | 5191 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5192 | coproc = 1; |
5193 | goto ld; | |
5194 | case M_LWC3_AB: | |
5195 | s = "lwc3"; | |
bdaaa2e1 | 5196 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5197 | coproc = 1; |
5198 | goto ld; | |
5199 | case M_LWL_AB: | |
5200 | s = "lwl"; | |
5201 | lr = 1; | |
5202 | goto ld; | |
5203 | case M_LWR_AB: | |
5204 | s = "lwr"; | |
5205 | lr = 1; | |
5206 | goto ld; | |
5207 | case M_LDC1_AB: | |
ec68c924 | 5208 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5209 | { |
5210 | as_bad (_("opcode not supported on this processor")); | |
5211 | return; | |
5212 | } | |
5213 | s = "ldc1"; | |
bdaaa2e1 | 5214 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5215 | coproc = 1; |
5216 | goto ld; | |
5217 | case M_LDC2_AB: | |
5218 | s = "ldc2"; | |
bdaaa2e1 | 5219 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5220 | coproc = 1; |
5221 | goto ld; | |
5222 | case M_LDC3_AB: | |
5223 | s = "ldc3"; | |
bdaaa2e1 | 5224 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5225 | coproc = 1; |
5226 | goto ld; | |
5227 | case M_LDL_AB: | |
5228 | s = "ldl"; | |
5229 | lr = 1; | |
5230 | goto ld; | |
5231 | case M_LDR_AB: | |
5232 | s = "ldr"; | |
5233 | lr = 1; | |
5234 | goto ld; | |
5235 | case M_LL_AB: | |
5236 | s = "ll"; | |
5237 | goto ld; | |
5238 | case M_LLD_AB: | |
5239 | s = "lld"; | |
5240 | goto ld; | |
5241 | case M_LWU_AB: | |
5242 | s = "lwu"; | |
5243 | ld: | |
5244 | if (breg == treg || coproc || lr) | |
5245 | { | |
5246 | tempreg = AT; | |
5247 | used_at = 1; | |
5248 | } | |
5249 | else | |
5250 | { | |
5251 | tempreg = treg; | |
5252 | used_at = 0; | |
5253 | } | |
5254 | goto ld_st; | |
5255 | case M_SB_AB: | |
5256 | s = "sb"; | |
5257 | goto st; | |
5258 | case M_SH_AB: | |
5259 | s = "sh"; | |
5260 | goto st; | |
5261 | case M_SW_AB: | |
5262 | s = "sw"; | |
5263 | goto st; | |
5264 | case M_SWC0_AB: | |
5265 | s = "swc0"; | |
bdaaa2e1 | 5266 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5267 | coproc = 1; |
5268 | goto st; | |
5269 | case M_SWC1_AB: | |
5270 | s = "swc1"; | |
bdaaa2e1 | 5271 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5272 | coproc = 1; |
5273 | goto st; | |
5274 | case M_SWC2_AB: | |
5275 | s = "swc2"; | |
bdaaa2e1 | 5276 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5277 | coproc = 1; |
5278 | goto st; | |
5279 | case M_SWC3_AB: | |
5280 | s = "swc3"; | |
bdaaa2e1 | 5281 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5282 | coproc = 1; |
5283 | goto st; | |
5284 | case M_SWL_AB: | |
5285 | s = "swl"; | |
5286 | goto st; | |
5287 | case M_SWR_AB: | |
5288 | s = "swr"; | |
5289 | goto st; | |
5290 | case M_SC_AB: | |
5291 | s = "sc"; | |
5292 | goto st; | |
5293 | case M_SCD_AB: | |
5294 | s = "scd"; | |
5295 | goto st; | |
5296 | case M_SDC1_AB: | |
ec68c924 | 5297 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5298 | { |
5299 | as_bad (_("opcode not supported on this processor")); | |
5300 | return; | |
5301 | } | |
5302 | s = "sdc1"; | |
5303 | coproc = 1; | |
bdaaa2e1 | 5304 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5305 | goto st; |
5306 | case M_SDC2_AB: | |
5307 | s = "sdc2"; | |
bdaaa2e1 | 5308 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5309 | coproc = 1; |
5310 | goto st; | |
5311 | case M_SDC3_AB: | |
5312 | s = "sdc3"; | |
bdaaa2e1 | 5313 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5314 | coproc = 1; |
5315 | goto st; | |
5316 | case M_SDL_AB: | |
5317 | s = "sdl"; | |
5318 | goto st; | |
5319 | case M_SDR_AB: | |
5320 | s = "sdr"; | |
5321 | st: | |
5322 | tempreg = AT; | |
5323 | used_at = 1; | |
5324 | ld_st: | |
bdaaa2e1 | 5325 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5326 | if (mask == M_LWC1_AB |
5327 | || mask == M_SWC1_AB | |
5328 | || mask == M_LDC1_AB | |
5329 | || mask == M_SDC1_AB | |
5330 | || mask == M_L_DAB | |
5331 | || mask == M_S_DAB) | |
5332 | fmt = "T,o(b)"; | |
5333 | else if (coproc) | |
5334 | fmt = "E,o(b)"; | |
5335 | else | |
5336 | fmt = "t,o(b)"; | |
5337 | ||
afdbd6d0 CD |
5338 | /* For embedded PIC, we allow loads where the offset is calculated |
5339 | by subtracting a symbol in the current segment from an unknown | |
5340 | symbol, relative to a base register, e.g.: | |
5341 | <op> $treg, <sym>-<localsym>($breg) | |
5342 | This is used by the compiler for switch statements. */ | |
76b3015f | 5343 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5344 | && offset_expr.X_op == O_subtract |
5345 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5346 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5347 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5348 | && (S_GET_SEGMENT | |
5349 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5350 | ->X_add_symbol) | |
5351 | == now_seg))) | |
5352 | && breg != 0 | |
5353 | && (offset_expr.X_add_number == 0 | |
5354 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5355 | { | |
5356 | /* For this case, we output the instructions: | |
5357 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5358 | addiu $tempreg,$tempreg,$breg | |
5359 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5360 | If the relocation would fit entirely in 16 bits, it would be | |
5361 | nice to emit: | |
5362 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5363 | instead, but that seems quite difficult. */ | |
5364 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5365 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
5366 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5367 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
5368 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
5369 | ? "addu" : "daddu"), | |
5370 | "d,v,t", tempreg, tempreg, breg); | |
5371 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, | |
5372 | (int) BFD_RELOC_PCREL_LO16, tempreg); | |
5373 | if (! used_at) | |
5374 | return; | |
5375 | break; | |
5376 | } | |
5377 | ||
252b5132 RH |
5378 | if (offset_expr.X_op != O_constant |
5379 | && offset_expr.X_op != O_symbol) | |
5380 | { | |
5381 | as_bad (_("expression too complex")); | |
5382 | offset_expr.X_op = O_constant; | |
5383 | } | |
5384 | ||
5385 | /* A constant expression in PIC code can be handled just as it | |
5386 | is in non PIC code. */ | |
5387 | if (mips_pic == NO_PIC | |
5388 | || offset_expr.X_op == O_constant) | |
5389 | { | |
5390 | /* If this is a reference to a GP relative symbol, and there | |
5391 | is no base register, we want | |
cdf6fd85 | 5392 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5393 | Otherwise, if there is no base register, we want |
5394 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5395 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5396 | If we have a constant, we need two instructions anyhow, | |
5397 | so we always use the latter form. | |
5398 | ||
5399 | If we have a base register, and this is a reference to a | |
5400 | GP relative symbol, we want | |
5401 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5402 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5403 | Otherwise we want |
5404 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5405 | addu $tempreg,$tempreg,$breg | |
5406 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5407 | With a constant we always use the latter case. |
76b3015f | 5408 | |
d6bc6245 TS |
5409 | With 64bit address space and no base register and $at usable, |
5410 | we want | |
5411 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5412 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5413 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5414 | dsll32 $tempreg,0 | |
5415 | daddu $tempreg,$at | |
5416 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5417 | If we have a base register, we want | |
5418 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5419 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5420 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5421 | daddu $at,$breg | |
5422 | dsll32 $tempreg,0 | |
5423 | daddu $tempreg,$at | |
5424 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5425 | ||
5426 | Without $at we can't generate the optimal path for superscalar | |
5427 | processors here since this would require two temporary registers. | |
5428 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5429 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5430 | dsll $tempreg,16 | |
5431 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5432 | dsll $tempreg,16 | |
5433 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5434 | If we have a base register, we want | |
5435 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5436 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5437 | dsll $tempreg,16 | |
5438 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5439 | dsll $tempreg,16 | |
5440 | daddu $tempreg,$tempreg,$breg | |
5441 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5442 | */ | |
5443 | if (HAVE_64BIT_ADDRESSES) | |
5444 | { | |
5445 | p = NULL; | |
5446 | ||
5447 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5448 | hold the data for such large chunks. */ | |
5449 | ||
5450 | if (used_at == 0) | |
5451 | { | |
5452 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5453 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5454 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5455 | AT, (int) BFD_RELOC_HI16_S); | |
5456 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5457 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
5458 | if (breg != 0) | |
2396cfb9 TS |
5459 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5460 | "d,v,t", AT, AT, breg); | |
5461 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
5462 | "d,w,<", tempreg, tempreg, 0); | |
5463 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", | |
5464 | "d,v,t", tempreg, tempreg, AT); | |
d6bc6245 TS |
5465 | macro_build (p, &icnt, &offset_expr, s, |
5466 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5467 | used_at = 1; | |
5468 | } | |
5469 | else | |
5470 | { | |
5471 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5472 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5473 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5474 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
5475 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5476 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 TS |
5477 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
5478 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
5479 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5480 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5481 | if (breg != 0) |
2396cfb9 TS |
5482 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5483 | "d,v,t", tempreg, tempreg, breg); | |
d6bc6245 TS |
5484 | macro_build (p, &icnt, &offset_expr, s, |
5485 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5486 | } | |
5487 | ||
5488 | return; | |
5489 | } | |
76b3015f | 5490 | |
252b5132 RH |
5491 | if (breg == 0) |
5492 | { | |
e7d556df | 5493 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5494 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5495 | p = NULL; | |
5496 | else | |
5497 | { | |
5498 | frag_grow (20); | |
5499 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
cdf6fd85 | 5500 | treg, (int) BFD_RELOC_GPREL16, GP); |
252b5132 RH |
5501 | p = frag_var (rs_machine_dependent, 8, 0, |
5502 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5503 | (mips_opts.warn_about_macros | |
5504 | || (used_at | |
5505 | && mips_opts.noat))), | |
956cd1d6 | 5506 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5507 | used_at = 0; |
5508 | } | |
5509 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5510 | if (p != NULL) | |
5511 | p += 4; | |
5512 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5513 | (int) BFD_RELOC_LO16, tempreg); | |
5514 | } | |
5515 | else | |
5516 | { | |
e7d556df | 5517 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5518 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5519 | p = NULL; | |
5520 | else | |
5521 | { | |
5522 | frag_grow (28); | |
5523 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5524 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5525 | "d,v,t", tempreg, breg, GP); |
5526 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
cdf6fd85 | 5527 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5528 | p = frag_var (rs_machine_dependent, 12, 0, |
5529 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 5530 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5531 | } |
5532 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5533 | if (p != NULL) | |
5534 | p += 4; | |
5535 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5536 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5537 | "d,v,t", tempreg, tempreg, breg); |
5538 | if (p != NULL) | |
5539 | p += 4; | |
5540 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5541 | (int) BFD_RELOC_LO16, tempreg); | |
5542 | } | |
5543 | } | |
5544 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5545 | { | |
5546 | /* If this is a reference to an external symbol, we want | |
5547 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5548 | nop | |
5549 | <op> $treg,0($tempreg) | |
5550 | Otherwise we want | |
5551 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5552 | nop | |
5553 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5554 | <op> $treg,0($tempreg) | |
5555 | If there is a base register, we add it to $tempreg before | |
5556 | the <op>. If there is a constant, we stick it in the | |
5557 | <op> instruction. We don't handle constants larger than | |
5558 | 16 bits, because we have no way to load the upper 16 bits | |
5559 | (actually, we could handle them for the subset of cases | |
5560 | in which we are not using $at). */ | |
5561 | assert (offset_expr.X_op == O_symbol); | |
5562 | expr1.X_add_number = offset_expr.X_add_number; | |
5563 | offset_expr.X_add_number = 0; | |
5564 | if (expr1.X_add_number < -0x8000 | |
5565 | || expr1.X_add_number >= 0x8000) | |
5566 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5567 | frag_grow (20); | |
5568 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5569 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5570 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5571 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
bdaaa2e1 | 5572 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 5573 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 5574 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 | 5575 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5576 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5577 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5578 | if (breg != 0) | |
5579 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5580 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5581 | "d,v,t", tempreg, tempreg, breg); |
5582 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5583 | (int) BFD_RELOC_LO16, tempreg); | |
5584 | } | |
5585 | else if (mips_pic == SVR4_PIC) | |
5586 | { | |
5587 | int gpdel; | |
5588 | ||
5589 | /* If this is a reference to an external symbol, we want | |
5590 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5591 | addu $tempreg,$tempreg,$gp | |
5592 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5593 | <op> $treg,0($tempreg) | |
5594 | Otherwise we want | |
5595 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5596 | nop | |
5597 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5598 | <op> $treg,0($tempreg) | |
5599 | If there is a base register, we add it to $tempreg before | |
5600 | the <op>. If there is a constant, we stick it in the | |
5601 | <op> instruction. We don't handle constants larger than | |
5602 | 16 bits, because we have no way to load the upper 16 bits | |
5603 | (actually, we could handle them for the subset of cases | |
5604 | in which we are not using $at). */ | |
5605 | assert (offset_expr.X_op == O_symbol); | |
5606 | expr1.X_add_number = offset_expr.X_add_number; | |
5607 | offset_expr.X_add_number = 0; | |
5608 | if (expr1.X_add_number < -0x8000 | |
5609 | || expr1.X_add_number >= 0x8000) | |
5610 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5611 | if (reg_needs_delay (GP)) | |
5612 | gpdel = 4; | |
5613 | else | |
5614 | gpdel = 0; | |
5615 | frag_grow (36); | |
5616 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5617 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5618 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5619 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5620 | "d,v,t", tempreg, tempreg, GP); |
5621 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5622 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5623 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5624 | tempreg); | |
5625 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5626 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 5627 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5628 | if (gpdel > 0) |
5629 | { | |
5630 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5631 | p += 4; | |
5632 | } | |
5633 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5634 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5635 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5636 | p += 4; | |
5637 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5638 | p += 4; | |
5639 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5640 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5641 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5642 | if (breg != 0) | |
5643 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5644 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5645 | "d,v,t", tempreg, tempreg, breg); |
5646 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5647 | (int) BFD_RELOC_LO16, tempreg); | |
5648 | } | |
5649 | else if (mips_pic == EMBEDDED_PIC) | |
5650 | { | |
5651 | /* If there is no base register, we want | |
cdf6fd85 | 5652 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5653 | If there is a base register, we want |
5654 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5655 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5656 | */ |
5657 | assert (offset_expr.X_op == O_symbol); | |
5658 | if (breg == 0) | |
5659 | { | |
5660 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
cdf6fd85 | 5661 | treg, (int) BFD_RELOC_GPREL16, GP); |
252b5132 RH |
5662 | used_at = 0; |
5663 | } | |
5664 | else | |
5665 | { | |
5666 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5667 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5668 | "d,v,t", tempreg, breg, GP); |
5669 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
cdf6fd85 | 5670 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5671 | } |
5672 | } | |
5673 | else | |
5674 | abort (); | |
5675 | ||
5676 | if (! used_at) | |
5677 | return; | |
5678 | ||
5679 | break; | |
5680 | ||
5681 | case M_LI: | |
5682 | case M_LI_S: | |
5683 | load_register (&icnt, treg, &imm_expr, 0); | |
5684 | return; | |
5685 | ||
5686 | case M_DLI: | |
5687 | load_register (&icnt, treg, &imm_expr, 1); | |
5688 | return; | |
5689 | ||
5690 | case M_LI_SS: | |
5691 | if (imm_expr.X_op == O_constant) | |
5692 | { | |
5693 | load_register (&icnt, AT, &imm_expr, 0); | |
5694 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5695 | "mtc1", "t,G", AT, treg); | |
5696 | break; | |
5697 | } | |
5698 | else | |
5699 | { | |
5700 | assert (offset_expr.X_op == O_symbol | |
5701 | && strcmp (segment_name (S_GET_SEGMENT | |
5702 | (offset_expr.X_add_symbol)), | |
5703 | ".lit4") == 0 | |
5704 | && offset_expr.X_add_number == 0); | |
5705 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5706 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5707 | return; | |
5708 | } | |
5709 | ||
5710 | case M_LI_D: | |
ca4e0257 RS |
5711 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
5712 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
5713 | order 32 bits of the value and the low order 32 bits are either | |
5714 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
5715 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5716 | { | |
ca4e0257 | 5717 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5718 | load_register (&icnt, treg, &imm_expr, 1); |
5719 | else | |
5720 | { | |
5721 | int hreg, lreg; | |
5722 | ||
5723 | if (target_big_endian) | |
5724 | { | |
5725 | hreg = treg; | |
5726 | lreg = treg + 1; | |
5727 | } | |
5728 | else | |
5729 | { | |
5730 | hreg = treg + 1; | |
5731 | lreg = treg; | |
5732 | } | |
5733 | ||
5734 | if (hreg <= 31) | |
5735 | load_register (&icnt, hreg, &imm_expr, 0); | |
5736 | if (lreg <= 31) | |
5737 | { | |
5738 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 5739 | move_register (&icnt, lreg, 0); |
252b5132 RH |
5740 | else |
5741 | { | |
5742 | assert (offset_expr.X_op == O_constant); | |
5743 | load_register (&icnt, lreg, &offset_expr, 0); | |
5744 | } | |
5745 | } | |
5746 | } | |
5747 | return; | |
5748 | } | |
5749 | ||
5750 | /* We know that sym is in the .rdata section. First we get the | |
5751 | upper 16 bits of the address. */ | |
5752 | if (mips_pic == NO_PIC) | |
5753 | { | |
956cd1d6 | 5754 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
5755 | } |
5756 | else if (mips_pic == SVR4_PIC) | |
5757 | { | |
5758 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5759 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5760 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5761 | } | |
5762 | else if (mips_pic == EMBEDDED_PIC) | |
5763 | { | |
5764 | /* For embedded PIC we pick up the entire address off $gp in | |
5765 | a single instruction. */ | |
5766 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5767 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
cdf6fd85 | 5768 | "t,r,j", AT, GP, (int) BFD_RELOC_GPREL16); |
252b5132 RH |
5769 | offset_expr.X_op = O_constant; |
5770 | offset_expr.X_add_number = 0; | |
5771 | } | |
5772 | else | |
5773 | abort (); | |
bdaaa2e1 | 5774 | |
252b5132 | 5775 | /* Now we load the register(s). */ |
ca4e0257 | 5776 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5777 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5778 | treg, (int) BFD_RELOC_LO16, AT); | |
5779 | else | |
5780 | { | |
5781 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5782 | treg, (int) BFD_RELOC_LO16, AT); | |
5783 | if (treg != 31) | |
5784 | { | |
5785 | /* FIXME: How in the world do we deal with the possible | |
5786 | overflow here? */ | |
5787 | offset_expr.X_add_number += 4; | |
5788 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5789 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5790 | } | |
5791 | } | |
5792 | ||
5793 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5794 | does not become a variant frag. */ | |
5795 | frag_wane (frag_now); | |
5796 | frag_new (0); | |
5797 | ||
5798 | break; | |
5799 | ||
5800 | case M_LI_DD: | |
ca4e0257 RS |
5801 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
5802 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
5803 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
5804 | the value and the low order 32 bits are either zero or in | |
5805 | OFFSET_EXPR. */ | |
252b5132 RH |
5806 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5807 | { | |
ca4e0257 RS |
5808 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
5809 | if (HAVE_64BIT_FPRS) | |
5810 | { | |
5811 | assert (HAVE_64BIT_GPRS); | |
5812 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5813 | "dmtc1", "t,S", AT, treg); | |
5814 | } | |
252b5132 RH |
5815 | else |
5816 | { | |
5817 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5818 | "mtc1", "t,G", AT, treg + 1); | |
5819 | if (offset_expr.X_op == O_absent) | |
5820 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5821 | "mtc1", "t,G", 0, treg); | |
5822 | else | |
5823 | { | |
5824 | assert (offset_expr.X_op == O_constant); | |
5825 | load_register (&icnt, AT, &offset_expr, 0); | |
5826 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5827 | "mtc1", "t,G", AT, treg); | |
5828 | } | |
5829 | } | |
5830 | break; | |
5831 | } | |
5832 | ||
5833 | assert (offset_expr.X_op == O_symbol | |
5834 | && offset_expr.X_add_number == 0); | |
5835 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5836 | if (strcmp (s, ".lit8") == 0) | |
5837 | { | |
e7af610e | 5838 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5839 | { |
5840 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5841 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5842 | return; | |
5843 | } | |
5844 | breg = GP; | |
5845 | r = BFD_RELOC_MIPS_LITERAL; | |
5846 | goto dob; | |
5847 | } | |
5848 | else | |
5849 | { | |
5850 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
5851 | if (mips_pic == SVR4_PIC) | |
5852 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5853 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5854 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5855 | else | |
5856 | { | |
5857 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 5858 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 5859 | } |
bdaaa2e1 | 5860 | |
e7af610e | 5861 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5862 | { |
5863 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5864 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
5865 | ||
5866 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5867 | that this does not become a variant frag. */ | |
5868 | frag_wane (frag_now); | |
5869 | frag_new (0); | |
5870 | ||
5871 | break; | |
5872 | } | |
5873 | breg = AT; | |
5874 | r = BFD_RELOC_LO16; | |
5875 | goto dob; | |
5876 | } | |
5877 | ||
5878 | case M_L_DOB: | |
ec68c924 | 5879 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5880 | { |
5881 | as_bad (_("opcode not supported on this processor")); | |
5882 | return; | |
5883 | } | |
5884 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5885 | to adjust when loading from memory. */ | |
5886 | r = BFD_RELOC_LO16; | |
5887 | dob: | |
e7af610e | 5888 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
5889 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
5890 | target_big_endian ? treg + 1 : treg, | |
5891 | (int) r, breg); | |
5892 | /* FIXME: A possible overflow which I don't know how to deal | |
5893 | with. */ | |
5894 | offset_expr.X_add_number += 4; | |
5895 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5896 | target_big_endian ? treg : treg + 1, | |
5897 | (int) r, breg); | |
5898 | ||
5899 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5900 | does not become a variant frag. */ | |
5901 | frag_wane (frag_now); | |
5902 | frag_new (0); | |
5903 | ||
5904 | if (breg != AT) | |
5905 | return; | |
5906 | break; | |
5907 | ||
5908 | case M_L_DAB: | |
5909 | /* | |
5910 | * The MIPS assembler seems to check for X_add_number not | |
5911 | * being double aligned and generating: | |
5912 | * lui at,%hi(foo+1) | |
5913 | * addu at,at,v1 | |
5914 | * addiu at,at,%lo(foo+1) | |
5915 | * lwc1 f2,0(at) | |
5916 | * lwc1 f3,4(at) | |
5917 | * But, the resulting address is the same after relocation so why | |
5918 | * generate the extra instruction? | |
5919 | */ | |
ec68c924 | 5920 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5921 | { |
5922 | as_bad (_("opcode not supported on this processor")); | |
5923 | return; | |
5924 | } | |
bdaaa2e1 | 5925 | /* Itbl support may require additional care here. */ |
252b5132 | 5926 | coproc = 1; |
e7af610e | 5927 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5928 | { |
5929 | s = "ldc1"; | |
5930 | goto ld; | |
5931 | } | |
5932 | ||
5933 | s = "lwc1"; | |
5934 | fmt = "T,o(b)"; | |
5935 | goto ldd_std; | |
5936 | ||
5937 | case M_S_DAB: | |
ec68c924 | 5938 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5939 | { |
5940 | as_bad (_("opcode not supported on this processor")); | |
5941 | return; | |
5942 | } | |
5943 | ||
e7af610e | 5944 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5945 | { |
5946 | s = "sdc1"; | |
5947 | goto st; | |
5948 | } | |
5949 | ||
5950 | s = "swc1"; | |
5951 | fmt = "T,o(b)"; | |
bdaaa2e1 | 5952 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5953 | coproc = 1; |
5954 | goto ldd_std; | |
5955 | ||
5956 | case M_LD_AB: | |
ca4e0257 | 5957 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5958 | { |
5959 | s = "ld"; | |
5960 | goto ld; | |
5961 | } | |
5962 | ||
5963 | s = "lw"; | |
5964 | fmt = "t,o(b)"; | |
5965 | goto ldd_std; | |
5966 | ||
5967 | case M_SD_AB: | |
ca4e0257 | 5968 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5969 | { |
5970 | s = "sd"; | |
5971 | goto st; | |
5972 | } | |
5973 | ||
5974 | s = "sw"; | |
5975 | fmt = "t,o(b)"; | |
5976 | ||
5977 | ldd_std: | |
afdbd6d0 CD |
5978 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
5979 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
5980 | This is not currently done by the compiler, and assembly coders | |
5981 | writing embedded-pic code can cope. */ | |
5982 | ||
252b5132 RH |
5983 | if (offset_expr.X_op != O_symbol |
5984 | && offset_expr.X_op != O_constant) | |
5985 | { | |
5986 | as_bad (_("expression too complex")); | |
5987 | offset_expr.X_op = O_constant; | |
5988 | } | |
5989 | ||
5990 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5991 | to adjust when loading from memory. We set coproc if we must | |
5992 | load $fn+1 first. */ | |
bdaaa2e1 | 5993 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5994 | if (! target_big_endian) |
5995 | coproc = 0; | |
5996 | ||
5997 | if (mips_pic == NO_PIC | |
5998 | || offset_expr.X_op == O_constant) | |
5999 | { | |
6000 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6001 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6002 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6003 | If we have a base register, we use this |
6004 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6005 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6006 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6007 | If this is not a GP relative symbol, we want |
6008 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6009 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6010 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6011 | If there is a base register, we add it to $at after the | |
6012 | lui instruction. If there is a constant, we always use | |
6013 | the last case. */ | |
e7d556df | 6014 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6015 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6016 | { | |
6017 | p = NULL; | |
6018 | used_at = 1; | |
6019 | } | |
6020 | else | |
6021 | { | |
6022 | int off; | |
6023 | ||
6024 | if (breg == 0) | |
6025 | { | |
6026 | frag_grow (28); | |
6027 | tempreg = GP; | |
6028 | off = 0; | |
6029 | used_at = 0; | |
6030 | } | |
6031 | else | |
6032 | { | |
6033 | frag_grow (36); | |
6034 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6035 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6036 | "d,v,t", AT, breg, GP); |
6037 | tempreg = AT; | |
6038 | off = 4; | |
6039 | used_at = 1; | |
6040 | } | |
6041 | ||
beae10d5 | 6042 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6043 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6044 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6045 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6046 | offset_expr.X_add_number += 4; |
6047 | ||
6048 | /* Set mips_optimize to 2 to avoid inserting an | |
6049 | undesired nop. */ | |
6050 | hold_mips_optimize = mips_optimize; | |
6051 | mips_optimize = 2; | |
beae10d5 | 6052 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6053 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6054 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6055 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6056 | mips_optimize = hold_mips_optimize; |
6057 | ||
6058 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6059 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6060 | used_at && mips_opts.noat), | |
956cd1d6 | 6061 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6062 | |
6063 | /* We just generated two relocs. When tc_gen_reloc | |
6064 | handles this case, it will skip the first reloc and | |
6065 | handle the second. The second reloc already has an | |
6066 | extra addend of 4, which we added above. We must | |
6067 | subtract it out, and then subtract another 4 to make | |
6068 | the first reloc come out right. The second reloc | |
6069 | will come out right because we are going to add 4 to | |
6070 | offset_expr when we build its instruction below. | |
6071 | ||
6072 | If we have a symbol, then we don't want to include | |
6073 | the offset, because it will wind up being included | |
6074 | when we generate the reloc. */ | |
6075 | ||
6076 | if (offset_expr.X_op == O_constant) | |
6077 | offset_expr.X_add_number -= 8; | |
6078 | else | |
6079 | { | |
6080 | offset_expr.X_add_number = -4; | |
6081 | offset_expr.X_op = O_constant; | |
6082 | } | |
6083 | } | |
6084 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6085 | if (p != NULL) | |
6086 | p += 4; | |
6087 | if (breg != 0) | |
6088 | { | |
6089 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6090 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6091 | "d,v,t", AT, breg, AT); |
6092 | if (p != NULL) | |
6093 | p += 4; | |
6094 | } | |
beae10d5 | 6095 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6096 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6097 | coproc ? treg + 1 : treg, | |
6098 | (int) BFD_RELOC_LO16, AT); | |
6099 | if (p != NULL) | |
6100 | p += 4; | |
6101 | /* FIXME: How do we handle overflow here? */ | |
6102 | offset_expr.X_add_number += 4; | |
beae10d5 | 6103 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6104 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6105 | coproc ? treg : treg + 1, | |
6106 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6107 | } |
252b5132 RH |
6108 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6109 | { | |
6110 | int off; | |
6111 | ||
6112 | /* If this is a reference to an external symbol, we want | |
6113 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6114 | nop | |
6115 | <op> $treg,0($at) | |
6116 | <op> $treg+1,4($at) | |
6117 | Otherwise we want | |
6118 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6119 | nop | |
6120 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6121 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6122 | If there is a base register we add it to $at before the | |
6123 | lwc1 instructions. If there is a constant we include it | |
6124 | in the lwc1 instructions. */ | |
6125 | used_at = 1; | |
6126 | expr1.X_add_number = offset_expr.X_add_number; | |
6127 | offset_expr.X_add_number = 0; | |
6128 | if (expr1.X_add_number < -0x8000 | |
6129 | || expr1.X_add_number >= 0x8000 - 4) | |
6130 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6131 | if (breg == 0) | |
6132 | off = 0; | |
6133 | else | |
6134 | off = 4; | |
6135 | frag_grow (24 + off); | |
6136 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6137 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6138 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
6139 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6140 | if (breg != 0) | |
6141 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6142 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6143 | "d,v,t", AT, breg, AT); |
beae10d5 | 6144 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6145 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6146 | coproc ? treg + 1 : treg, | |
6147 | (int) BFD_RELOC_LO16, AT); | |
6148 | expr1.X_add_number += 4; | |
6149 | ||
6150 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6151 | nop. */ | |
6152 | hold_mips_optimize = mips_optimize; | |
6153 | mips_optimize = 2; | |
beae10d5 | 6154 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6155 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6156 | coproc ? treg : treg + 1, | |
6157 | (int) BFD_RELOC_LO16, AT); | |
6158 | mips_optimize = hold_mips_optimize; | |
6159 | ||
6160 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6161 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6162 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6163 | } |
6164 | else if (mips_pic == SVR4_PIC) | |
6165 | { | |
6166 | int gpdel, off; | |
6167 | ||
6168 | /* If this is a reference to an external symbol, we want | |
6169 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6170 | addu $at,$at,$gp | |
6171 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6172 | nop | |
6173 | <op> $treg,0($at) | |
6174 | <op> $treg+1,4($at) | |
6175 | Otherwise we want | |
6176 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6177 | nop | |
6178 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6179 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6180 | If there is a base register we add it to $at before the | |
6181 | lwc1 instructions. If there is a constant we include it | |
6182 | in the lwc1 instructions. */ | |
6183 | used_at = 1; | |
6184 | expr1.X_add_number = offset_expr.X_add_number; | |
6185 | offset_expr.X_add_number = 0; | |
6186 | if (expr1.X_add_number < -0x8000 | |
6187 | || expr1.X_add_number >= 0x8000 - 4) | |
6188 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6189 | if (reg_needs_delay (GP)) | |
6190 | gpdel = 4; | |
6191 | else | |
6192 | gpdel = 0; | |
6193 | if (breg == 0) | |
6194 | off = 0; | |
6195 | else | |
6196 | off = 4; | |
6197 | frag_grow (56); | |
6198 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6199 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6200 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6201 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6202 | "d,v,t", AT, AT, GP); |
6203 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6204 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6205 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
6206 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6207 | if (breg != 0) | |
6208 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6209 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6210 | "d,v,t", AT, breg, AT); |
beae10d5 | 6211 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6212 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6213 | coproc ? treg + 1 : treg, | |
6214 | (int) BFD_RELOC_LO16, AT); | |
6215 | expr1.X_add_number += 4; | |
6216 | ||
6217 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6218 | nop. */ | |
6219 | hold_mips_optimize = mips_optimize; | |
6220 | mips_optimize = 2; | |
beae10d5 | 6221 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6222 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6223 | coproc ? treg : treg + 1, | |
6224 | (int) BFD_RELOC_LO16, AT); | |
6225 | mips_optimize = hold_mips_optimize; | |
6226 | expr1.X_add_number -= 4; | |
6227 | ||
6228 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6229 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6230 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6231 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6232 | if (gpdel > 0) |
6233 | { | |
6234 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6235 | p += 4; | |
6236 | } | |
6237 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6238 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6239 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
6240 | p += 4; | |
6241 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6242 | p += 4; | |
6243 | if (breg != 0) | |
6244 | { | |
6245 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6246 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6247 | "d,v,t", AT, breg, AT); |
6248 | p += 4; | |
6249 | } | |
beae10d5 | 6250 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6251 | macro_build (p, &icnt, &expr1, s, fmt, |
6252 | coproc ? treg + 1 : treg, | |
6253 | (int) BFD_RELOC_LO16, AT); | |
6254 | p += 4; | |
6255 | expr1.X_add_number += 4; | |
6256 | ||
6257 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6258 | nop. */ | |
6259 | hold_mips_optimize = mips_optimize; | |
6260 | mips_optimize = 2; | |
beae10d5 | 6261 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6262 | macro_build (p, &icnt, &expr1, s, fmt, |
6263 | coproc ? treg : treg + 1, | |
6264 | (int) BFD_RELOC_LO16, AT); | |
6265 | mips_optimize = hold_mips_optimize; | |
6266 | } | |
6267 | else if (mips_pic == EMBEDDED_PIC) | |
6268 | { | |
6269 | /* If there is no base register, we use | |
cdf6fd85 TS |
6270 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6271 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6272 | If we have a base register, we use |
6273 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6274 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6275 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6276 | */ |
6277 | if (breg == 0) | |
6278 | { | |
6279 | tempreg = GP; | |
6280 | used_at = 0; | |
6281 | } | |
6282 | else | |
6283 | { | |
6284 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6285 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6286 | "d,v,t", AT, breg, GP); |
6287 | tempreg = AT; | |
6288 | used_at = 1; | |
6289 | } | |
6290 | ||
beae10d5 | 6291 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6292 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6293 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6294 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6295 | offset_expr.X_add_number += 4; |
beae10d5 | 6296 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6297 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6298 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6299 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6300 | } |
6301 | else | |
6302 | abort (); | |
6303 | ||
6304 | if (! used_at) | |
6305 | return; | |
6306 | ||
6307 | break; | |
6308 | ||
6309 | case M_LD_OB: | |
6310 | s = "lw"; | |
6311 | goto sd_ob; | |
6312 | case M_SD_OB: | |
6313 | s = "sw"; | |
6314 | sd_ob: | |
ca4e0257 | 6315 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
6316 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6317 | (int) BFD_RELOC_LO16, breg); | |
6318 | offset_expr.X_add_number += 4; | |
6319 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
6320 | (int) BFD_RELOC_LO16, breg); | |
6321 | return; | |
6322 | ||
6323 | /* New code added to support COPZ instructions. | |
6324 | This code builds table entries out of the macros in mip_opcodes. | |
6325 | R4000 uses interlocks to handle coproc delays. | |
6326 | Other chips (like the R3000) require nops to be inserted for delays. | |
6327 | ||
f72c8c98 | 6328 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6329 | In order to fill delay slots for non-interlocked chips, |
6330 | we must have a way to specify delays based on the coprocessor. | |
6331 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6332 | What are the side-effects of the cop instruction? | |
6333 | What cache support might we have and what are its effects? | |
6334 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6335 | What registers are read/set/modified? |
252b5132 RH |
6336 | |
6337 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6338 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6339 | |
6340 | case M_COP0: | |
6341 | s = "c0"; | |
6342 | goto copz; | |
6343 | case M_COP1: | |
6344 | s = "c1"; | |
6345 | goto copz; | |
6346 | case M_COP2: | |
6347 | s = "c2"; | |
6348 | goto copz; | |
6349 | case M_COP3: | |
6350 | s = "c3"; | |
6351 | copz: | |
6352 | /* For now we just do C (same as Cz). The parameter will be | |
6353 | stored in insn_opcode by mips_ip. */ | |
6354 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6355 | ip->insn_opcode); | |
6356 | return; | |
6357 | ||
ea1fb5dc RS |
6358 | case M_MOVE: |
6359 | move_register (&icnt, dreg, sreg); | |
6360 | return; | |
6361 | ||
252b5132 RH |
6362 | #ifdef LOSING_COMPILER |
6363 | default: | |
6364 | /* Try and see if this is a new itbl instruction. | |
6365 | This code builds table entries out of the macros in mip_opcodes. | |
6366 | FIXME: For now we just assemble the expression and pass it's | |
6367 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6368 | We may want to have the assembler assemble this value, |
252b5132 RH |
6369 | so that we gain the assembler's knowledge of delay slots, |
6370 | symbols, etc. | |
6371 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6372 | if (itbl_have_entries |
252b5132 | 6373 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6374 | { |
252b5132 RH |
6375 | s = ip->insn_mo->name; |
6376 | s2 = "cop3"; | |
6377 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
6378 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
6379 | return; | |
beae10d5 | 6380 | } |
252b5132 RH |
6381 | macro2 (ip); |
6382 | return; | |
6383 | } | |
6384 | if (mips_opts.noat) | |
6385 | as_warn (_("Macro used $at after \".set noat\"")); | |
6386 | } | |
bdaaa2e1 | 6387 | |
252b5132 RH |
6388 | static void |
6389 | macro2 (ip) | |
6390 | struct mips_cl_insn *ip; | |
6391 | { | |
6392 | register int treg, sreg, dreg, breg; | |
6393 | int tempreg; | |
6394 | int mask; | |
6395 | int icnt = 0; | |
6396 | int used_at; | |
6397 | expressionS expr1; | |
6398 | const char *s; | |
6399 | const char *s2; | |
6400 | const char *fmt; | |
6401 | int likely = 0; | |
6402 | int dbl = 0; | |
6403 | int coproc = 0; | |
6404 | int lr = 0; | |
6405 | int imm = 0; | |
6406 | int off; | |
6407 | offsetT maxnum; | |
6408 | bfd_reloc_code_real_type r; | |
6409 | char *p; | |
bdaaa2e1 | 6410 | |
252b5132 RH |
6411 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6412 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6413 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6414 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6415 | |
252b5132 RH |
6416 | expr1.X_op = O_constant; |
6417 | expr1.X_op_symbol = NULL; | |
6418 | expr1.X_add_symbol = NULL; | |
6419 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6420 | |
252b5132 RH |
6421 | switch (mask) |
6422 | { | |
6423 | #endif /* LOSING_COMPILER */ | |
6424 | ||
6425 | case M_DMUL: | |
6426 | dbl = 1; | |
6427 | case M_MUL: | |
2396cfb9 TS |
6428 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6429 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); | |
6430 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6431 | dreg); | |
252b5132 RH |
6432 | return; |
6433 | ||
6434 | case M_DMUL_I: | |
6435 | dbl = 1; | |
6436 | case M_MUL_I: | |
6437 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6438 | not trying to be that fancy. GCC should do this for us | |
6439 | anyway. */ | |
6440 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6441 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6442 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
2396cfb9 TS |
6443 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6444 | dreg); | |
252b5132 RH |
6445 | break; |
6446 | ||
6447 | case M_DMULO_I: | |
6448 | dbl = 1; | |
6449 | case M_MULO_I: | |
6450 | imm = 1; | |
6451 | goto do_mulo; | |
6452 | ||
6453 | case M_DMULO: | |
6454 | dbl = 1; | |
6455 | case M_MULO: | |
6456 | do_mulo: | |
6457 | mips_emit_delays (true); | |
6458 | ++mips_opts.noreorder; | |
6459 | mips_any_noreorder = 1; | |
6460 | if (imm) | |
6461 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6462 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6463 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
2396cfb9 TS |
6464 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6465 | dreg); | |
6466 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a41af64 | 6467 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, 31); |
2396cfb9 TS |
6468 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6469 | AT); | |
252b5132 | 6470 | if (mips_trap) |
2396cfb9 TS |
6471 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t", |
6472 | dreg, AT); | |
252b5132 RH |
6473 | else |
6474 | { | |
6475 | expr1.X_add_number = 8; | |
2396cfb9 TS |
6476 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
6477 | AT); | |
6478 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", | |
6479 | 0); | |
6480 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6481 | "c", 6); | |
252b5132 RH |
6482 | } |
6483 | --mips_opts.noreorder; | |
2396cfb9 | 6484 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
252b5132 RH |
6485 | break; |
6486 | ||
6487 | case M_DMULOU_I: | |
6488 | dbl = 1; | |
6489 | case M_MULOU_I: | |
6490 | imm = 1; | |
6491 | goto do_mulou; | |
6492 | ||
6493 | case M_DMULOU: | |
6494 | dbl = 1; | |
6495 | case M_MULOU: | |
6496 | do_mulou: | |
6497 | mips_emit_delays (true); | |
6498 | ++mips_opts.noreorder; | |
6499 | mips_any_noreorder = 1; | |
6500 | if (imm) | |
6501 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6502 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
6503 | dbl ? "dmultu" : "multu", |
6504 | "s,t", sreg, imm ? AT : treg); | |
2396cfb9 TS |
6505 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6506 | AT); | |
6507 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6508 | dreg); | |
252b5132 | 6509 | if (mips_trap) |
2396cfb9 TS |
6510 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t", |
6511 | AT, 0); | |
252b5132 RH |
6512 | else |
6513 | { | |
6514 | expr1.X_add_number = 8; | |
6515 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
2396cfb9 TS |
6516 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
6517 | 0); | |
6518 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6519 | "c", 6); | |
252b5132 RH |
6520 | } |
6521 | --mips_opts.noreorder; | |
6522 | break; | |
6523 | ||
6524 | case M_ROL: | |
2396cfb9 TS |
6525 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6526 | "d,v,t", AT, 0, treg); | |
6527 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6528 | "d,t,s", AT, sreg, AT); | |
6529 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6530 | "d,t,s", dreg, sreg, treg); | |
6531 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6532 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6533 | break; |
6534 | ||
6535 | case M_ROL_I: | |
6536 | if (imm_expr.X_op != O_constant) | |
6537 | as_bad (_("rotate count too large")); | |
2396cfb9 TS |
6538 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
6539 | AT, sreg, (int) (imm_expr.X_add_number & 0x1f)); | |
6540 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", | |
6541 | dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6542 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
6543 | dreg, dreg, AT); | |
252b5132 RH |
6544 | break; |
6545 | ||
6546 | case M_ROR: | |
2396cfb9 TS |
6547 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6548 | "d,v,t", AT, 0, treg); | |
6549 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6550 | "d,t,s", AT, sreg, AT); | |
6551 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6552 | "d,t,s", dreg, sreg, treg); | |
6553 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6554 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6555 | break; |
6556 | ||
6557 | case M_ROR_I: | |
6558 | if (imm_expr.X_op != O_constant) | |
6559 | as_bad (_("rotate count too large")); | |
2396cfb9 TS |
6560 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
6561 | AT, sreg, (int) (imm_expr.X_add_number & 0x1f)); | |
6562 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", | |
6563 | dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6564 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
6565 | dreg, dreg, AT); | |
252b5132 RH |
6566 | break; |
6567 | ||
6568 | case M_S_DOB: | |
ec68c924 | 6569 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6570 | { |
6571 | as_bad (_("opcode not supported on this processor")); | |
6572 | return; | |
6573 | } | |
e7af610e | 6574 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6575 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6576 | to adjust when storing to memory. */ | |
6577 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6578 | target_big_endian ? treg + 1 : treg, | |
6579 | (int) BFD_RELOC_LO16, breg); | |
6580 | offset_expr.X_add_number += 4; | |
6581 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6582 | target_big_endian ? treg : treg + 1, | |
6583 | (int) BFD_RELOC_LO16, breg); | |
6584 | return; | |
6585 | ||
6586 | case M_SEQ: | |
6587 | if (sreg == 0) | |
6588 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6589 | treg, (int) BFD_RELOC_LO16); | |
6590 | else if (treg == 0) | |
6591 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6592 | sreg, (int) BFD_RELOC_LO16); | |
6593 | else | |
6594 | { | |
2396cfb9 TS |
6595 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6596 | "d,v,t", dreg, sreg, treg); | |
252b5132 RH |
6597 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6598 | dreg, (int) BFD_RELOC_LO16); | |
6599 | } | |
6600 | return; | |
6601 | ||
6602 | case M_SEQ_I: | |
6603 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6604 | { | |
6605 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6606 | sreg, (int) BFD_RELOC_LO16); | |
6607 | return; | |
6608 | } | |
6609 | if (sreg == 0) | |
6610 | { | |
6611 | as_warn (_("Instruction %s: result is always false"), | |
6612 | ip->insn_mo->name); | |
ea1fb5dc | 6613 | move_register (&icnt, dreg, 0); |
252b5132 RH |
6614 | return; |
6615 | } | |
6616 | if (imm_expr.X_op == O_constant | |
6617 | && imm_expr.X_add_number >= 0 | |
6618 | && imm_expr.X_add_number < 0x10000) | |
6619 | { | |
6620 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6621 | sreg, (int) BFD_RELOC_LO16); | |
6622 | used_at = 0; | |
6623 | } | |
6624 | else if (imm_expr.X_op == O_constant | |
6625 | && imm_expr.X_add_number > -0x8000 | |
6626 | && imm_expr.X_add_number < 0) | |
6627 | { | |
6628 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6629 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 6630 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6631 | "t,r,j", dreg, sreg, |
6632 | (int) BFD_RELOC_LO16); | |
6633 | used_at = 0; | |
6634 | } | |
6635 | else | |
6636 | { | |
6637 | load_register (&icnt, AT, &imm_expr, 0); | |
2396cfb9 TS |
6638 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6639 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
6640 | used_at = 1; |
6641 | } | |
6642 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
6643 | (int) BFD_RELOC_LO16); | |
6644 | if (used_at) | |
6645 | break; | |
6646 | return; | |
6647 | ||
6648 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6649 | s = "slt"; | |
6650 | goto sge; | |
6651 | case M_SGEU: | |
6652 | s = "sltu"; | |
6653 | sge: | |
2396cfb9 TS |
6654 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6655 | dreg, sreg, treg); | |
252b5132 RH |
6656 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
6657 | (int) BFD_RELOC_LO16); | |
6658 | return; | |
6659 | ||
6660 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6661 | case M_SGEU_I: | |
6662 | if (imm_expr.X_op == O_constant | |
6663 | && imm_expr.X_add_number >= -0x8000 | |
6664 | && imm_expr.X_add_number < 0x8000) | |
6665 | { | |
6666 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6667 | mask == M_SGE_I ? "slti" : "sltiu", | |
6668 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6669 | used_at = 0; | |
6670 | } | |
6671 | else | |
6672 | { | |
6673 | load_register (&icnt, AT, &imm_expr, 0); | |
2396cfb9 TS |
6674 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6675 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, | |
6676 | AT); | |
252b5132 RH |
6677 | used_at = 1; |
6678 | } | |
6679 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6680 | (int) BFD_RELOC_LO16); | |
6681 | if (used_at) | |
6682 | break; | |
6683 | return; | |
6684 | ||
6685 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
6686 | s = "slt"; | |
6687 | goto sgt; | |
6688 | case M_SGTU: | |
6689 | s = "sltu"; | |
6690 | sgt: | |
2396cfb9 TS |
6691 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6692 | dreg, treg, sreg); | |
252b5132 RH |
6693 | return; |
6694 | ||
6695 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
6696 | s = "slt"; | |
6697 | goto sgti; | |
6698 | case M_SGTU_I: | |
6699 | s = "sltu"; | |
6700 | sgti: | |
6701 | load_register (&icnt, AT, &imm_expr, 0); | |
2396cfb9 TS |
6702 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6703 | dreg, AT, sreg); | |
252b5132 RH |
6704 | break; |
6705 | ||
2396cfb9 | 6706 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
6707 | s = "slt"; |
6708 | goto sle; | |
6709 | case M_SLEU: | |
6710 | s = "sltu"; | |
6711 | sle: | |
2396cfb9 TS |
6712 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6713 | dreg, treg, sreg); | |
252b5132 RH |
6714 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
6715 | (int) BFD_RELOC_LO16); | |
6716 | return; | |
6717 | ||
2396cfb9 | 6718 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
6719 | s = "slt"; |
6720 | goto slei; | |
6721 | case M_SLEU_I: | |
6722 | s = "sltu"; | |
6723 | slei: | |
6724 | load_register (&icnt, AT, &imm_expr, 0); | |
2396cfb9 TS |
6725 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6726 | dreg, AT, sreg); | |
252b5132 RH |
6727 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
6728 | (int) BFD_RELOC_LO16); | |
6729 | break; | |
6730 | ||
6731 | case M_SLT_I: | |
6732 | if (imm_expr.X_op == O_constant | |
6733 | && imm_expr.X_add_number >= -0x8000 | |
6734 | && imm_expr.X_add_number < 0x8000) | |
6735 | { | |
6736 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
6737 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6738 | return; | |
6739 | } | |
6740 | load_register (&icnt, AT, &imm_expr, 0); | |
2396cfb9 TS |
6741 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
6742 | dreg, sreg, AT); | |
252b5132 RH |
6743 | break; |
6744 | ||
6745 | case M_SLTU_I: | |
6746 | if (imm_expr.X_op == O_constant | |
6747 | && imm_expr.X_add_number >= -0x8000 | |
6748 | && imm_expr.X_add_number < 0x8000) | |
6749 | { | |
6750 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
6751 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6752 | return; | |
6753 | } | |
6754 | load_register (&icnt, AT, &imm_expr, 0); | |
2396cfb9 TS |
6755 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
6756 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
6757 | break; |
6758 | ||
6759 | case M_SNE: | |
6760 | if (sreg == 0) | |
2396cfb9 TS |
6761 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
6762 | "d,v,t", dreg, 0, treg); | |
252b5132 | 6763 | else if (treg == 0) |
2396cfb9 TS |
6764 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
6765 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
6766 | else |
6767 | { | |
2396cfb9 TS |
6768 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6769 | "d,v,t", dreg, sreg, treg); | |
6770 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", | |
6771 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
6772 | } |
6773 | return; | |
6774 | ||
6775 | case M_SNE_I: | |
6776 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6777 | { | |
2396cfb9 TS |
6778 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
6779 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
6780 | return; |
6781 | } | |
6782 | if (sreg == 0) | |
6783 | { | |
6784 | as_warn (_("Instruction %s: result is always true"), | |
6785 | ip->insn_mo->name); | |
6786 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 6787 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6788 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
6789 | return; | |
6790 | } | |
6791 | if (imm_expr.X_op == O_constant | |
6792 | && imm_expr.X_add_number >= 0 | |
6793 | && imm_expr.X_add_number < 0x10000) | |
6794 | { | |
6795 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
6796 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6797 | used_at = 0; | |
6798 | } | |
6799 | else if (imm_expr.X_op == O_constant | |
6800 | && imm_expr.X_add_number > -0x8000 | |
6801 | && imm_expr.X_add_number < 0) | |
6802 | { | |
6803 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6804 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 6805 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6806 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6807 | used_at = 0; | |
6808 | } | |
6809 | else | |
6810 | { | |
6811 | load_register (&icnt, AT, &imm_expr, 0); | |
2396cfb9 TS |
6812 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6813 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
6814 | used_at = 1; |
6815 | } | |
2396cfb9 TS |
6816 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
6817 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
6818 | if (used_at) |
6819 | break; | |
6820 | return; | |
6821 | ||
6822 | case M_DSUB_I: | |
6823 | dbl = 1; | |
6824 | case M_SUB_I: | |
6825 | if (imm_expr.X_op == O_constant | |
6826 | && imm_expr.X_add_number > -0x8000 | |
6827 | && imm_expr.X_add_number <= 0x8000) | |
6828 | { | |
6829 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6830 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6831 | dbl ? "daddi" : "addi", | |
6832 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6833 | return; | |
6834 | } | |
6835 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6836 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6837 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
6838 | break; |
6839 | ||
6840 | case M_DSUBU_I: | |
6841 | dbl = 1; | |
6842 | case M_SUBU_I: | |
6843 | if (imm_expr.X_op == O_constant | |
6844 | && imm_expr.X_add_number > -0x8000 | |
6845 | && imm_expr.X_add_number <= 0x8000) | |
6846 | { | |
6847 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6848 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6849 | dbl ? "daddiu" : "addiu", | |
6850 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6851 | return; | |
6852 | } | |
6853 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6854 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6855 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
6856 | break; |
6857 | ||
6858 | case M_TEQ_I: | |
6859 | s = "teq"; | |
6860 | goto trap; | |
6861 | case M_TGE_I: | |
6862 | s = "tge"; | |
6863 | goto trap; | |
6864 | case M_TGEU_I: | |
6865 | s = "tgeu"; | |
6866 | goto trap; | |
6867 | case M_TLT_I: | |
6868 | s = "tlt"; | |
6869 | goto trap; | |
6870 | case M_TLTU_I: | |
6871 | s = "tltu"; | |
6872 | goto trap; | |
6873 | case M_TNE_I: | |
6874 | s = "tne"; | |
6875 | trap: | |
6876 | load_register (&icnt, AT, &imm_expr, 0); | |
2396cfb9 TS |
6877 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
6878 | AT); | |
252b5132 RH |
6879 | break; |
6880 | ||
252b5132 | 6881 | case M_TRUNCWS: |
43841e91 | 6882 | case M_TRUNCWD: |
e7af610e | 6883 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6884 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6885 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6886 | ||
6887 | /* | |
6888 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6889 | * or is there a reason for it? | |
6890 | */ | |
6891 | mips_emit_delays (true); | |
6892 | ++mips_opts.noreorder; | |
6893 | mips_any_noreorder = 1; | |
2396cfb9 TS |
6894 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
6895 | treg, 31); | |
6896 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", | |
6897 | treg, 31); | |
6898 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
252b5132 RH |
6899 | expr1.X_add_number = 3; |
6900 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
6901 | (int) BFD_RELOC_LO16); | |
6902 | expr1.X_add_number = 2; | |
6903 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
6904 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
6905 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
6906 | AT, 31); | |
6907 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6908 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 6909 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
2396cfb9 TS |
6910 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
6911 | treg, 31); | |
6912 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
252b5132 RH |
6913 | --mips_opts.noreorder; |
6914 | break; | |
6915 | ||
6916 | case M_ULH: | |
6917 | s = "lb"; | |
6918 | goto ulh; | |
6919 | case M_ULHU: | |
6920 | s = "lbu"; | |
6921 | ulh: | |
6922 | if (offset_expr.X_add_number >= 0x7fff) | |
6923 | as_bad (_("operand overflow")); | |
6924 | /* avoid load delay */ | |
6925 | if (! target_big_endian) | |
6926 | offset_expr.X_add_number += 1; | |
6927 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6928 | (int) BFD_RELOC_LO16, breg); | |
6929 | if (! target_big_endian) | |
6930 | offset_expr.X_add_number -= 1; | |
6931 | else | |
6932 | offset_expr.X_add_number += 1; | |
6933 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, | |
6934 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
6935 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
6936 | treg, treg, 8); | |
6937 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
6938 | treg, treg, AT); | |
252b5132 RH |
6939 | break; |
6940 | ||
6941 | case M_ULD: | |
6942 | s = "ldl"; | |
6943 | s2 = "ldr"; | |
6944 | off = 7; | |
6945 | goto ulw; | |
6946 | case M_ULW: | |
6947 | s = "lwl"; | |
6948 | s2 = "lwr"; | |
6949 | off = 3; | |
6950 | ulw: | |
6951 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6952 | as_bad (_("operand overflow")); | |
6953 | if (! target_big_endian) | |
6954 | offset_expr.X_add_number += off; | |
6955 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6956 | (int) BFD_RELOC_LO16, breg); | |
6957 | if (! target_big_endian) | |
6958 | offset_expr.X_add_number -= off; | |
6959 | else | |
6960 | offset_expr.X_add_number += off; | |
6961 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6962 | (int) BFD_RELOC_LO16, breg); | |
6963 | return; | |
6964 | ||
6965 | case M_ULD_A: | |
6966 | s = "ldl"; | |
6967 | s2 = "ldr"; | |
6968 | off = 7; | |
6969 | goto ulwa; | |
6970 | case M_ULW_A: | |
6971 | s = "lwl"; | |
6972 | s2 = "lwr"; | |
6973 | off = 3; | |
6974 | ulwa: | |
d6bc6245 TS |
6975 | used_at = 1; |
6976 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
6977 | if (breg != 0) |
6978 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6979 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6980 | "d,v,t", AT, AT, breg); |
6981 | if (! target_big_endian) | |
6982 | expr1.X_add_number = off; | |
6983 | else | |
6984 | expr1.X_add_number = 0; | |
6985 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6986 | (int) BFD_RELOC_LO16, AT); | |
6987 | if (! target_big_endian) | |
6988 | expr1.X_add_number = 0; | |
6989 | else | |
6990 | expr1.X_add_number = off; | |
6991 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6992 | (int) BFD_RELOC_LO16, AT); | |
6993 | break; | |
6994 | ||
6995 | case M_ULH_A: | |
6996 | case M_ULHU_A: | |
d6bc6245 TS |
6997 | used_at = 1; |
6998 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
6999 | if (breg != 0) |
7000 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7001 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7002 | "d,v,t", AT, AT, breg); |
7003 | if (target_big_endian) | |
7004 | expr1.X_add_number = 0; | |
7005 | macro_build ((char *) NULL, &icnt, &expr1, | |
7006 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
7007 | (int) BFD_RELOC_LO16, AT); | |
7008 | if (target_big_endian) | |
7009 | expr1.X_add_number = 1; | |
7010 | else | |
7011 | expr1.X_add_number = 0; | |
7012 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7013 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7014 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7015 | treg, treg, 8); | |
7016 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7017 | treg, treg, AT); | |
252b5132 RH |
7018 | break; |
7019 | ||
7020 | case M_USH: | |
7021 | if (offset_expr.X_add_number >= 0x7fff) | |
7022 | as_bad (_("operand overflow")); | |
7023 | if (target_big_endian) | |
7024 | offset_expr.X_add_number += 1; | |
7025 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, | |
7026 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7027 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7028 | AT, treg, 8); | |
252b5132 RH |
7029 | if (target_big_endian) |
7030 | offset_expr.X_add_number -= 1; | |
7031 | else | |
7032 | offset_expr.X_add_number += 1; | |
7033 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, | |
7034 | (int) BFD_RELOC_LO16, breg); | |
7035 | break; | |
7036 | ||
7037 | case M_USD: | |
7038 | s = "sdl"; | |
7039 | s2 = "sdr"; | |
7040 | off = 7; | |
7041 | goto usw; | |
7042 | case M_USW: | |
7043 | s = "swl"; | |
7044 | s2 = "swr"; | |
7045 | off = 3; | |
7046 | usw: | |
7047 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7048 | as_bad (_("operand overflow")); | |
7049 | if (! target_big_endian) | |
7050 | offset_expr.X_add_number += off; | |
7051 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7052 | (int) BFD_RELOC_LO16, breg); | |
7053 | if (! target_big_endian) | |
7054 | offset_expr.X_add_number -= off; | |
7055 | else | |
7056 | offset_expr.X_add_number += off; | |
7057 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7058 | (int) BFD_RELOC_LO16, breg); | |
7059 | return; | |
7060 | ||
7061 | case M_USD_A: | |
7062 | s = "sdl"; | |
7063 | s2 = "sdr"; | |
7064 | off = 7; | |
7065 | goto uswa; | |
7066 | case M_USW_A: | |
7067 | s = "swl"; | |
7068 | s2 = "swr"; | |
7069 | off = 3; | |
7070 | uswa: | |
d6bc6245 TS |
7071 | used_at = 1; |
7072 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
7073 | if (breg != 0) |
7074 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7075 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7076 | "d,v,t", AT, AT, breg); |
7077 | if (! target_big_endian) | |
7078 | expr1.X_add_number = off; | |
7079 | else | |
7080 | expr1.X_add_number = 0; | |
7081 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7082 | (int) BFD_RELOC_LO16, AT); | |
7083 | if (! target_big_endian) | |
7084 | expr1.X_add_number = 0; | |
7085 | else | |
7086 | expr1.X_add_number = off; | |
7087 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7088 | (int) BFD_RELOC_LO16, AT); | |
7089 | break; | |
7090 | ||
7091 | case M_USH_A: | |
d6bc6245 TS |
7092 | used_at = 1; |
7093 | load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at); | |
252b5132 RH |
7094 | if (breg != 0) |
7095 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7096 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7097 | "d,v,t", AT, AT, breg); |
7098 | if (! target_big_endian) | |
7099 | expr1.X_add_number = 0; | |
7100 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7101 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7102 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7103 | treg, treg, 8); | |
252b5132 RH |
7104 | if (! target_big_endian) |
7105 | expr1.X_add_number = 1; | |
7106 | else | |
7107 | expr1.X_add_number = 0; | |
7108 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7109 | (int) BFD_RELOC_LO16, AT); | |
7110 | if (! target_big_endian) | |
7111 | expr1.X_add_number = 0; | |
7112 | else | |
7113 | expr1.X_add_number = 1; | |
7114 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7115 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7116 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7117 | treg, treg, 8); | |
7118 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7119 | treg, treg, AT); | |
252b5132 RH |
7120 | break; |
7121 | ||
7122 | default: | |
7123 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7124 | are added dynamically. */ |
252b5132 RH |
7125 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7126 | break; | |
7127 | } | |
7128 | if (mips_opts.noat) | |
7129 | as_warn (_("Macro used $at after \".set noat\"")); | |
7130 | } | |
7131 | ||
7132 | /* Implement macros in mips16 mode. */ | |
7133 | ||
7134 | static void | |
7135 | mips16_macro (ip) | |
7136 | struct mips_cl_insn *ip; | |
7137 | { | |
7138 | int mask; | |
7139 | int xreg, yreg, zreg, tmp; | |
7140 | int icnt; | |
7141 | expressionS expr1; | |
7142 | int dbl; | |
7143 | const char *s, *s2, *s3; | |
7144 | ||
7145 | mask = ip->insn_mo->mask; | |
7146 | ||
7147 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7148 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7149 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7150 | ||
7151 | icnt = 0; | |
7152 | ||
7153 | expr1.X_op = O_constant; | |
7154 | expr1.X_op_symbol = NULL; | |
7155 | expr1.X_add_symbol = NULL; | |
7156 | expr1.X_add_number = 1; | |
7157 | ||
7158 | dbl = 0; | |
7159 | ||
7160 | switch (mask) | |
7161 | { | |
7162 | default: | |
7163 | internalError (); | |
7164 | ||
7165 | case M_DDIV_3: | |
7166 | dbl = 1; | |
7167 | case M_DIV_3: | |
7168 | s = "mflo"; | |
7169 | goto do_div3; | |
7170 | case M_DREM_3: | |
7171 | dbl = 1; | |
7172 | case M_REM_3: | |
7173 | s = "mfhi"; | |
7174 | do_div3: | |
7175 | mips_emit_delays (true); | |
7176 | ++mips_opts.noreorder; | |
7177 | mips_any_noreorder = 1; | |
2396cfb9 | 7178 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
7179 | dbl ? "ddiv" : "div", |
7180 | "0,x,y", xreg, yreg); | |
7181 | expr1.X_add_number = 2; | |
7182 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
7183 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
7184 | 7); | |
bdaaa2e1 | 7185 | |
252b5132 RH |
7186 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7187 | since that causes an overflow. We should do that as well, | |
7188 | but I don't see how to do the comparisons without a temporary | |
7189 | register. */ | |
7190 | --mips_opts.noreorder; | |
2396cfb9 | 7191 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
252b5132 RH |
7192 | break; |
7193 | ||
7194 | case M_DIVU_3: | |
7195 | s = "divu"; | |
7196 | s2 = "mflo"; | |
7197 | goto do_divu3; | |
7198 | case M_REMU_3: | |
7199 | s = "divu"; | |
7200 | s2 = "mfhi"; | |
7201 | goto do_divu3; | |
7202 | case M_DDIVU_3: | |
7203 | s = "ddivu"; | |
7204 | s2 = "mflo"; | |
7205 | goto do_divu3; | |
7206 | case M_DREMU_3: | |
7207 | s = "ddivu"; | |
7208 | s2 = "mfhi"; | |
7209 | do_divu3: | |
7210 | mips_emit_delays (true); | |
7211 | ++mips_opts.noreorder; | |
7212 | mips_any_noreorder = 1; | |
2396cfb9 TS |
7213 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
7214 | xreg, yreg); | |
252b5132 RH |
7215 | expr1.X_add_number = 2; |
7216 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
7217 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
7218 | "6", 7); | |
252b5132 | 7219 | --mips_opts.noreorder; |
2396cfb9 | 7220 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
252b5132 RH |
7221 | break; |
7222 | ||
7223 | case M_DMUL: | |
7224 | dbl = 1; | |
7225 | case M_MUL: | |
2396cfb9 | 7226 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7227 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
2396cfb9 TS |
7228 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
7229 | zreg); | |
252b5132 RH |
7230 | return; |
7231 | ||
7232 | case M_DSUBU_I: | |
7233 | dbl = 1; | |
7234 | goto do_subu; | |
7235 | case M_SUBU_I: | |
7236 | do_subu: | |
7237 | if (imm_expr.X_op != O_constant) | |
7238 | as_bad (_("Unsupported large constant")); | |
7239 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7240 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 7241 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7242 | break; |
7243 | ||
7244 | case M_SUBU_I_2: | |
7245 | if (imm_expr.X_op != O_constant) | |
7246 | as_bad (_("Unsupported large constant")); | |
7247 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7248 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
7249 | "x,k", xreg); | |
7250 | break; | |
7251 | ||
7252 | case M_DSUBU_I_2: | |
7253 | if (imm_expr.X_op != O_constant) | |
7254 | as_bad (_("Unsupported large constant")); | |
7255 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7256 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
7257 | "y,j", yreg); | |
7258 | break; | |
7259 | ||
7260 | case M_BEQ: | |
7261 | s = "cmp"; | |
7262 | s2 = "bteqz"; | |
7263 | goto do_branch; | |
7264 | case M_BNE: | |
7265 | s = "cmp"; | |
7266 | s2 = "btnez"; | |
7267 | goto do_branch; | |
7268 | case M_BLT: | |
7269 | s = "slt"; | |
7270 | s2 = "btnez"; | |
7271 | goto do_branch; | |
7272 | case M_BLTU: | |
7273 | s = "sltu"; | |
7274 | s2 = "btnez"; | |
7275 | goto do_branch; | |
7276 | case M_BLE: | |
7277 | s = "slt"; | |
7278 | s2 = "bteqz"; | |
7279 | goto do_reverse_branch; | |
7280 | case M_BLEU: | |
7281 | s = "sltu"; | |
7282 | s2 = "bteqz"; | |
7283 | goto do_reverse_branch; | |
7284 | case M_BGE: | |
7285 | s = "slt"; | |
7286 | s2 = "bteqz"; | |
7287 | goto do_branch; | |
7288 | case M_BGEU: | |
7289 | s = "sltu"; | |
7290 | s2 = "bteqz"; | |
7291 | goto do_branch; | |
7292 | case M_BGT: | |
7293 | s = "slt"; | |
7294 | s2 = "btnez"; | |
7295 | goto do_reverse_branch; | |
7296 | case M_BGTU: | |
7297 | s = "sltu"; | |
7298 | s2 = "btnez"; | |
7299 | ||
7300 | do_reverse_branch: | |
7301 | tmp = xreg; | |
7302 | xreg = yreg; | |
7303 | yreg = tmp; | |
7304 | ||
7305 | do_branch: | |
7306 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
7307 | xreg, yreg); | |
7308 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7309 | break; | |
7310 | ||
7311 | case M_BEQ_I: | |
7312 | s = "cmpi"; | |
7313 | s2 = "bteqz"; | |
7314 | s3 = "x,U"; | |
7315 | goto do_branch_i; | |
7316 | case M_BNE_I: | |
7317 | s = "cmpi"; | |
7318 | s2 = "btnez"; | |
7319 | s3 = "x,U"; | |
7320 | goto do_branch_i; | |
7321 | case M_BLT_I: | |
7322 | s = "slti"; | |
7323 | s2 = "btnez"; | |
7324 | s3 = "x,8"; | |
7325 | goto do_branch_i; | |
7326 | case M_BLTU_I: | |
7327 | s = "sltiu"; | |
7328 | s2 = "btnez"; | |
7329 | s3 = "x,8"; | |
7330 | goto do_branch_i; | |
7331 | case M_BLE_I: | |
7332 | s = "slti"; | |
7333 | s2 = "btnez"; | |
7334 | s3 = "x,8"; | |
7335 | goto do_addone_branch_i; | |
7336 | case M_BLEU_I: | |
7337 | s = "sltiu"; | |
7338 | s2 = "btnez"; | |
7339 | s3 = "x,8"; | |
7340 | goto do_addone_branch_i; | |
7341 | case M_BGE_I: | |
7342 | s = "slti"; | |
7343 | s2 = "bteqz"; | |
7344 | s3 = "x,8"; | |
7345 | goto do_branch_i; | |
7346 | case M_BGEU_I: | |
7347 | s = "sltiu"; | |
7348 | s2 = "bteqz"; | |
7349 | s3 = "x,8"; | |
7350 | goto do_branch_i; | |
7351 | case M_BGT_I: | |
7352 | s = "slti"; | |
7353 | s2 = "bteqz"; | |
7354 | s3 = "x,8"; | |
7355 | goto do_addone_branch_i; | |
7356 | case M_BGTU_I: | |
7357 | s = "sltiu"; | |
7358 | s2 = "bteqz"; | |
7359 | s3 = "x,8"; | |
7360 | ||
7361 | do_addone_branch_i: | |
7362 | if (imm_expr.X_op != O_constant) | |
7363 | as_bad (_("Unsupported large constant")); | |
7364 | ++imm_expr.X_add_number; | |
7365 | ||
7366 | do_branch_i: | |
7367 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7368 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7369 | break; | |
7370 | ||
7371 | case M_ABS: | |
7372 | expr1.X_add_number = 0; | |
7373 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
7374 | if (xreg != yreg) | |
ea1fb5dc | 7375 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
7376 | expr1.X_add_number = 2; |
7377 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7378 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7379 | "neg", "x,w", xreg, xreg); | |
7380 | } | |
7381 | } | |
7382 | ||
7383 | /* For consistency checking, verify that all bits are specified either | |
7384 | by the match/mask part of the instruction definition, or by the | |
7385 | operand list. */ | |
7386 | static int | |
7387 | validate_mips_insn (opc) | |
7388 | const struct mips_opcode *opc; | |
7389 | { | |
7390 | const char *p = opc->args; | |
7391 | char c; | |
7392 | unsigned long used_bits = opc->mask; | |
7393 | ||
7394 | if ((used_bits & opc->match) != opc->match) | |
7395 | { | |
7396 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7397 | opc->name, opc->args); | |
7398 | return 0; | |
7399 | } | |
7400 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7401 | while (*p) | |
7402 | switch (c = *p++) | |
7403 | { | |
7404 | case ',': break; | |
7405 | case '(': break; | |
7406 | case ')': break; | |
7407 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7408 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7409 | case 'A': break; | |
4372b673 | 7410 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7411 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7412 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7413 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7414 | case 'F': break; | |
7415 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7416 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7417 | case 'I': break; |
e972090a | 7418 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
7419 | case 'L': break; |
7420 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7421 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
7422 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
7423 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7424 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7425 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7426 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7427 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
7428 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7429 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7430 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7431 | case 'f': break; | |
7432 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7433 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7434 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7435 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7436 | case 'l': break; | |
7437 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7438 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7439 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7440 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7441 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7442 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7443 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7444 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7445 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7446 | case 'x': break; | |
7447 | case 'z': break; | |
7448 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7449 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7450 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
252b5132 RH |
7451 | default: |
7452 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7453 | c, opc->name, opc->args); | |
7454 | return 0; | |
7455 | } | |
7456 | #undef USE_BITS | |
7457 | if (used_bits != 0xffffffff) | |
7458 | { | |
7459 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7460 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7461 | return 0; | |
7462 | } | |
7463 | return 1; | |
7464 | } | |
7465 | ||
7466 | /* This routine assembles an instruction into its binary format. As a | |
7467 | side effect, it sets one of the global variables imm_reloc or | |
7468 | offset_reloc to the type of relocation to do if one of the operands | |
7469 | is an address expression. */ | |
7470 | ||
7471 | static void | |
7472 | mips_ip (str, ip) | |
7473 | char *str; | |
7474 | struct mips_cl_insn *ip; | |
7475 | { | |
7476 | char *s; | |
7477 | const char *args; | |
43841e91 | 7478 | char c = 0; |
252b5132 RH |
7479 | struct mips_opcode *insn; |
7480 | char *argsStart; | |
7481 | unsigned int regno; | |
7482 | unsigned int lastregno = 0; | |
7483 | char *s_reset; | |
7484 | char save_c = 0; | |
7485 | int full_opcode_match = 1; | |
7486 | ||
7487 | insn_error = NULL; | |
7488 | ||
7489 | /* If the instruction contains a '.', we first try to match an instruction | |
7490 | including the '.'. Then we try again without the '.'. */ | |
7491 | insn = NULL; | |
3882b010 | 7492 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7493 | continue; |
7494 | ||
7495 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7496 | the call to hash_find. Save the character we replaced just in case we | |
7497 | have to re-parse the instruction. */ | |
3882b010 | 7498 | if (ISSPACE (*s)) |
252b5132 RH |
7499 | { |
7500 | save_c = *s; | |
7501 | *s++ = '\0'; | |
7502 | } | |
bdaaa2e1 | 7503 | |
252b5132 RH |
7504 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7505 | ||
7506 | /* If we didn't find the instruction in the opcode table, try again, but | |
7507 | this time with just the instruction up to, but not including the | |
7508 | first '.'. */ | |
7509 | if (insn == NULL) | |
7510 | { | |
bdaaa2e1 | 7511 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7512 | if (save_c) |
7513 | *(--s) = save_c; | |
7514 | ||
7515 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7516 | for (s = str; |
7517 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7518 | ++s) | |
252b5132 RH |
7519 | continue; |
7520 | ||
7521 | /* If we did not find a '.', then we can quit now. */ | |
7522 | if (*s != '.') | |
7523 | { | |
7524 | insn_error = "unrecognized opcode"; | |
7525 | return; | |
7526 | } | |
7527 | ||
7528 | /* Lookup the instruction in the hash table. */ | |
7529 | *s++ = '\0'; | |
7530 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7531 | { | |
7532 | insn_error = "unrecognized opcode"; | |
7533 | return; | |
7534 | } | |
7535 | ||
7536 | full_opcode_match = 0; | |
7537 | } | |
7538 | ||
7539 | argsStart = s; | |
7540 | for (;;) | |
7541 | { | |
252b5132 RH |
7542 | boolean ok; |
7543 | ||
7544 | assert (strcmp (insn->name, str) == 0); | |
7545 | ||
ea1fb5dc | 7546 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch)) |
252b5132 | 7547 | ok = true; |
bdaaa2e1 | 7548 | else |
252b5132 | 7549 | ok = false; |
bdaaa2e1 | 7550 | |
252b5132 RH |
7551 | if (insn->pinfo != INSN_MACRO) |
7552 | { | |
ec68c924 | 7553 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
252b5132 RH |
7554 | ok = false; |
7555 | } | |
7556 | ||
7557 | if (! ok) | |
7558 | { | |
7559 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7560 | && strcmp (insn->name, insn[1].name) == 0) | |
7561 | { | |
7562 | ++insn; | |
7563 | continue; | |
7564 | } | |
252b5132 | 7565 | else |
beae10d5 | 7566 | { |
268f6bed L |
7567 | if (!insn_error) |
7568 | { | |
7569 | static char buf[100]; | |
7570 | sprintf (buf, | |
7571 | _("opcode not supported on this processor: %s (%s)"), | |
ec68c924 | 7572 | mips_cpu_to_str (mips_arch), |
268f6bed | 7573 | mips_isa_to_str (mips_opts.isa)); |
bdaaa2e1 | 7574 | |
268f6bed L |
7575 | insn_error = buf; |
7576 | } | |
7577 | if (save_c) | |
7578 | *(--s) = save_c; | |
2bd7f1f3 | 7579 | return; |
252b5132 | 7580 | } |
252b5132 RH |
7581 | } |
7582 | ||
7583 | ip->insn_mo = insn; | |
7584 | ip->insn_opcode = insn->match; | |
268f6bed | 7585 | insn_error = NULL; |
252b5132 RH |
7586 | for (args = insn->args;; ++args) |
7587 | { | |
ad8d3bb3 | 7588 | s += strspn (s, " \t"); |
252b5132 RH |
7589 | switch (*args) |
7590 | { | |
7591 | case '\0': /* end of args */ | |
7592 | if (*s == '\0') | |
7593 | return; | |
7594 | break; | |
7595 | ||
7596 | case ',': | |
7597 | if (*s++ == *args) | |
7598 | continue; | |
7599 | s--; | |
7600 | switch (*++args) | |
7601 | { | |
7602 | case 'r': | |
7603 | case 'v': | |
38487616 | 7604 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
7605 | continue; |
7606 | ||
7607 | case 'w': | |
38487616 TS |
7608 | ip->insn_opcode |= lastregno << OP_SH_RT; |
7609 | continue; | |
7610 | ||
252b5132 | 7611 | case 'W': |
38487616 | 7612 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
7613 | continue; |
7614 | ||
7615 | case 'V': | |
38487616 | 7616 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
7617 | continue; |
7618 | } | |
7619 | break; | |
7620 | ||
7621 | case '(': | |
7622 | /* Handle optional base register. | |
7623 | Either the base register is omitted or | |
bdaaa2e1 | 7624 | we must have a left paren. */ |
252b5132 RH |
7625 | /* This is dependent on the next operand specifier |
7626 | is a base register specification. */ | |
7627 | assert (args[1] == 'b' || args[1] == '5' | |
7628 | || args[1] == '-' || args[1] == '4'); | |
7629 | if (*s == '\0') | |
7630 | return; | |
7631 | ||
7632 | case ')': /* these must match exactly */ | |
7633 | if (*s++ == *args) | |
7634 | continue; | |
7635 | break; | |
7636 | ||
7637 | case '<': /* must be at least one digit */ | |
7638 | /* | |
7639 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
7640 | * than 31 or less than 0, then the shift amount should be |
7641 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
7642 | * We issue a warning and mask out all but the low 5 bits. |
7643 | */ | |
7644 | my_getExpression (&imm_expr, s); | |
7645 | check_absolute_expr (ip, &imm_expr); | |
7646 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7647 | { | |
7648 | as_warn (_("Improper shift amount (%ld)"), | |
7649 | (long) imm_expr.X_add_number); | |
38487616 | 7650 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 7651 | } |
38487616 | 7652 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
7653 | imm_expr.X_op = O_absent; |
7654 | s = expr_end; | |
7655 | continue; | |
7656 | ||
7657 | case '>': /* shift amount minus 32 */ | |
7658 | my_getExpression (&imm_expr, s); | |
7659 | check_absolute_expr (ip, &imm_expr); | |
7660 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7661 | || (unsigned long) imm_expr.X_add_number > 63) | |
7662 | break; | |
38487616 | 7663 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
7664 | imm_expr.X_op = O_absent; |
7665 | s = expr_end; | |
7666 | continue; | |
7667 | ||
252b5132 RH |
7668 | case 'k': /* cache code */ |
7669 | case 'h': /* prefx code */ | |
7670 | my_getExpression (&imm_expr, s); | |
7671 | check_absolute_expr (ip, &imm_expr); | |
7672 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7673 | { | |
7674 | as_warn (_("Invalid value for `%s' (%lu)"), | |
7675 | ip->insn_mo->name, | |
7676 | (unsigned long) imm_expr.X_add_number); | |
7677 | imm_expr.X_add_number &= 0x1f; | |
7678 | } | |
7679 | if (*args == 'k') | |
7680 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7681 | else | |
7682 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
7683 | imm_expr.X_op = O_absent; | |
7684 | s = expr_end; | |
7685 | continue; | |
7686 | ||
7687 | case 'c': /* break code */ | |
7688 | my_getExpression (&imm_expr, s); | |
7689 | check_absolute_expr (ip, &imm_expr); | |
7690 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7691 | { | |
7692 | as_warn (_("Illegal break code (%ld)"), | |
7693 | (long) imm_expr.X_add_number); | |
38487616 | 7694 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 7695 | } |
38487616 | 7696 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
7697 | imm_expr.X_op = O_absent; |
7698 | s = expr_end; | |
7699 | continue; | |
7700 | ||
7701 | case 'q': /* lower break code */ | |
7702 | my_getExpression (&imm_expr, s); | |
7703 | check_absolute_expr (ip, &imm_expr); | |
7704 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7705 | { | |
7706 | as_warn (_("Illegal lower break code (%ld)"), | |
7707 | (long) imm_expr.X_add_number); | |
38487616 | 7708 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 7709 | } |
38487616 | 7710 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
7711 | imm_expr.X_op = O_absent; |
7712 | s = expr_end; | |
7713 | continue; | |
7714 | ||
4372b673 | 7715 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 7716 | my_getExpression (&imm_expr, s); |
156c2f8b | 7717 | check_absolute_expr (ip, &imm_expr); |
38487616 | 7718 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20) |
4372b673 | 7719 | as_warn (_("Illegal 20-bit code (%ld)"), |
252b5132 | 7720 | (long) imm_expr.X_add_number); |
38487616 | 7721 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
7722 | imm_expr.X_op = O_absent; |
7723 | s = expr_end; | |
7724 | continue; | |
7725 | ||
7726 | case 'C': /* Coprocessor code */ | |
beae10d5 | 7727 | my_getExpression (&imm_expr, s); |
252b5132 | 7728 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7729 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) |
252b5132 | 7730 | { |
beae10d5 | 7731 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
252b5132 | 7732 | (long) imm_expr.X_add_number); |
beae10d5 | 7733 | imm_expr.X_add_number &= ((1<<25) - 1); |
252b5132 | 7734 | } |
beae10d5 KH |
7735 | ip->insn_opcode |= imm_expr.X_add_number; |
7736 | imm_expr.X_op = O_absent; | |
7737 | s = expr_end; | |
7738 | continue; | |
252b5132 | 7739 | |
4372b673 NC |
7740 | case 'J': /* 19-bit wait code. */ |
7741 | my_getExpression (&imm_expr, s); | |
7742 | check_absolute_expr (ip, &imm_expr); | |
38487616 | 7743 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19) |
4372b673 NC |
7744 | as_warn (_("Illegal 19-bit code (%ld)"), |
7745 | (long) imm_expr.X_add_number); | |
38487616 | 7746 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
7747 | imm_expr.X_op = O_absent; |
7748 | s = expr_end; | |
7749 | continue; | |
7750 | ||
252b5132 | 7751 | case 'P': /* Performance register */ |
beae10d5 | 7752 | my_getExpression (&imm_expr, s); |
252b5132 | 7753 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 7754 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 7755 | { |
38487616 | 7756 | as_warn (_("Invalid performance register (%ld)"), |
252b5132 | 7757 | (long) imm_expr.X_add_number); |
38487616 | 7758 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 7759 | } |
38487616 | 7760 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
7761 | imm_expr.X_op = O_absent; |
7762 | s = expr_end; | |
7763 | continue; | |
252b5132 RH |
7764 | |
7765 | case 'b': /* base register */ | |
7766 | case 'd': /* destination register */ | |
7767 | case 's': /* source register */ | |
7768 | case 't': /* target register */ | |
7769 | case 'r': /* both target and source */ | |
7770 | case 'v': /* both dest and source */ | |
7771 | case 'w': /* both dest and target */ | |
7772 | case 'E': /* coprocessor target register */ | |
7773 | case 'G': /* coprocessor destination register */ | |
7774 | case 'x': /* ignore register name */ | |
7775 | case 'z': /* must be zero register */ | |
4372b673 | 7776 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
7777 | s_reset = s; |
7778 | if (s[0] == '$') | |
7779 | { | |
7780 | ||
3882b010 | 7781 | if (ISDIGIT (s[1])) |
252b5132 RH |
7782 | { |
7783 | ++s; | |
7784 | regno = 0; | |
7785 | do | |
7786 | { | |
7787 | regno *= 10; | |
7788 | regno += *s - '0'; | |
7789 | ++s; | |
7790 | } | |
3882b010 | 7791 | while (ISDIGIT (*s)); |
252b5132 RH |
7792 | if (regno > 31) |
7793 | as_bad (_("Invalid register number (%d)"), regno); | |
7794 | } | |
7795 | else if (*args == 'E' || *args == 'G') | |
7796 | goto notreg; | |
7797 | else | |
7798 | { | |
7799 | if (s[1] == 'f' && s[2] == 'p') | |
7800 | { | |
7801 | s += 3; | |
7802 | regno = FP; | |
7803 | } | |
7804 | else if (s[1] == 's' && s[2] == 'p') | |
7805 | { | |
7806 | s += 3; | |
7807 | regno = SP; | |
7808 | } | |
7809 | else if (s[1] == 'g' && s[2] == 'p') | |
7810 | { | |
7811 | s += 3; | |
7812 | regno = GP; | |
7813 | } | |
7814 | else if (s[1] == 'a' && s[2] == 't') | |
7815 | { | |
7816 | s += 3; | |
7817 | regno = AT; | |
7818 | } | |
7819 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7820 | { | |
7821 | s += 4; | |
7822 | regno = KT0; | |
7823 | } | |
7824 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7825 | { | |
7826 | s += 4; | |
7827 | regno = KT1; | |
7828 | } | |
7829 | else if (itbl_have_entries) | |
7830 | { | |
7831 | char *p, *n; | |
d7ba4a77 | 7832 | unsigned long r; |
252b5132 | 7833 | |
d7ba4a77 | 7834 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
7835 | n = itbl_get_field (&p); /* n is name */ |
7836 | ||
d7ba4a77 ILT |
7837 | /* See if this is a register defined in an |
7838 | itbl entry. */ | |
7839 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
7840 | { |
7841 | /* Get_field advances to the start of | |
7842 | the next field, so we need to back | |
d7ba4a77 | 7843 | rack to the end of the last field. */ |
bdaaa2e1 | 7844 | if (p) |
252b5132 | 7845 | s = p - 1; |
bdaaa2e1 | 7846 | else |
d7ba4a77 | 7847 | s = strchr (s, '\0'); |
252b5132 RH |
7848 | regno = r; |
7849 | } | |
7850 | else | |
7851 | goto notreg; | |
beae10d5 | 7852 | } |
252b5132 RH |
7853 | else |
7854 | goto notreg; | |
7855 | } | |
7856 | if (regno == AT | |
7857 | && ! mips_opts.noat | |
7858 | && *args != 'E' | |
7859 | && *args != 'G') | |
7860 | as_warn (_("Used $at without \".set noat\"")); | |
7861 | c = *args; | |
7862 | if (*s == ' ') | |
7863 | s++; | |
7864 | if (args[1] != *s) | |
7865 | { | |
7866 | if (c == 'r' || c == 'v' || c == 'w') | |
7867 | { | |
7868 | regno = lastregno; | |
7869 | s = s_reset; | |
7870 | args++; | |
7871 | } | |
7872 | } | |
7873 | /* 'z' only matches $0. */ | |
7874 | if (c == 'z' && regno != 0) | |
7875 | break; | |
7876 | ||
bdaaa2e1 KH |
7877 | /* Now that we have assembled one operand, we use the args string |
7878 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
7879 | switch (c) |
7880 | { | |
7881 | case 'r': | |
7882 | case 's': | |
7883 | case 'v': | |
7884 | case 'b': | |
38487616 | 7885 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
7886 | break; |
7887 | case 'd': | |
7888 | case 'G': | |
38487616 | 7889 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 7890 | break; |
4372b673 | 7891 | case 'U': |
38487616 TS |
7892 | ip->insn_opcode |= regno << OP_SH_RD; |
7893 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 7894 | break; |
252b5132 RH |
7895 | case 'w': |
7896 | case 't': | |
7897 | case 'E': | |
38487616 | 7898 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
7899 | break; |
7900 | case 'x': | |
7901 | /* This case exists because on the r3000 trunc | |
7902 | expands into a macro which requires a gp | |
7903 | register. On the r6000 or r4000 it is | |
7904 | assembled into a single instruction which | |
7905 | ignores the register. Thus the insn version | |
7906 | is MIPS_ISA2 and uses 'x', and the macro | |
7907 | version is MIPS_ISA1 and uses 't'. */ | |
7908 | break; | |
7909 | case 'z': | |
7910 | /* This case is for the div instruction, which | |
7911 | acts differently if the destination argument | |
7912 | is $0. This only matches $0, and is checked | |
7913 | outside the switch. */ | |
7914 | break; | |
7915 | case 'D': | |
7916 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7917 | break; | |
7918 | /* What about all other operands like 'i', which | |
7919 | can be specified in the opcode table? */ | |
7920 | } | |
7921 | lastregno = regno; | |
7922 | continue; | |
7923 | } | |
7924 | notreg: | |
7925 | switch (*args++) | |
7926 | { | |
7927 | case 'r': | |
7928 | case 'v': | |
38487616 | 7929 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
7930 | continue; |
7931 | case 'w': | |
38487616 | 7932 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
7933 | continue; |
7934 | } | |
7935 | break; | |
7936 | ||
7937 | case 'D': /* floating point destination register */ | |
7938 | case 'S': /* floating point source register */ | |
7939 | case 'T': /* floating point target register */ | |
7940 | case 'R': /* floating point source register */ | |
7941 | case 'V': | |
7942 | case 'W': | |
7943 | s_reset = s; | |
3882b010 L |
7944 | if (s[0] == '$' && s[1] == 'f' |
7945 | && ISDIGIT (s[2])) | |
252b5132 RH |
7946 | { |
7947 | s += 2; | |
7948 | regno = 0; | |
7949 | do | |
7950 | { | |
7951 | regno *= 10; | |
7952 | regno += *s - '0'; | |
7953 | ++s; | |
7954 | } | |
3882b010 | 7955 | while (ISDIGIT (*s)); |
252b5132 RH |
7956 | |
7957 | if (regno > 31) | |
7958 | as_bad (_("Invalid float register number (%d)"), regno); | |
7959 | ||
7960 | if ((regno & 1) != 0 | |
ca4e0257 | 7961 | && HAVE_32BIT_FPRS |
252b5132 RH |
7962 | && ! (strcmp (str, "mtc1") == 0 |
7963 | || strcmp (str, "mfc1") == 0 | |
7964 | || strcmp (str, "lwc1") == 0 | |
7965 | || strcmp (str, "swc1") == 0 | |
7966 | || strcmp (str, "l.s") == 0 | |
7967 | || strcmp (str, "s.s") == 0)) | |
7968 | as_warn (_("Float register should be even, was %d"), | |
7969 | regno); | |
7970 | ||
7971 | c = *args; | |
7972 | if (*s == ' ') | |
7973 | s++; | |
7974 | if (args[1] != *s) | |
7975 | { | |
7976 | if (c == 'V' || c == 'W') | |
7977 | { | |
7978 | regno = lastregno; | |
7979 | s = s_reset; | |
7980 | args++; | |
7981 | } | |
7982 | } | |
7983 | switch (c) | |
7984 | { | |
7985 | case 'D': | |
38487616 | 7986 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
7987 | break; |
7988 | case 'V': | |
7989 | case 'S': | |
38487616 | 7990 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 RH |
7991 | break; |
7992 | case 'W': | |
7993 | case 'T': | |
38487616 | 7994 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
7995 | break; |
7996 | case 'R': | |
38487616 | 7997 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
7998 | break; |
7999 | } | |
8000 | lastregno = regno; | |
8001 | continue; | |
8002 | } | |
8003 | ||
252b5132 RH |
8004 | switch (*args++) |
8005 | { | |
8006 | case 'V': | |
38487616 | 8007 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8008 | continue; |
8009 | case 'W': | |
38487616 | 8010 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8011 | continue; |
8012 | } | |
8013 | break; | |
8014 | ||
8015 | case 'I': | |
8016 | my_getExpression (&imm_expr, s); | |
8017 | if (imm_expr.X_op != O_big | |
8018 | && imm_expr.X_op != O_constant) | |
8019 | insn_error = _("absolute expression required"); | |
8020 | s = expr_end; | |
8021 | continue; | |
8022 | ||
8023 | case 'A': | |
8024 | my_getExpression (&offset_expr, s); | |
f6688943 | 8025 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8026 | s = expr_end; |
8027 | continue; | |
8028 | ||
8029 | case 'F': | |
8030 | case 'L': | |
8031 | case 'f': | |
8032 | case 'l': | |
8033 | { | |
8034 | int f64; | |
ca4e0257 | 8035 | int using_gprs; |
252b5132 RH |
8036 | char *save_in; |
8037 | char *err; | |
8038 | unsigned char temp[8]; | |
8039 | int len; | |
8040 | unsigned int length; | |
8041 | segT seg; | |
8042 | subsegT subseg; | |
8043 | char *p; | |
8044 | ||
8045 | /* These only appear as the last operand in an | |
8046 | instruction, and every instruction that accepts | |
8047 | them in any variant accepts them in all variants. | |
8048 | This means we don't have to worry about backing out | |
8049 | any changes if the instruction does not match. | |
8050 | ||
8051 | The difference between them is the size of the | |
8052 | floating point constant and where it goes. For 'F' | |
8053 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8054 | is 32 bits. Where the constant is placed is based | |
8055 | on how the MIPS assembler does things: | |
8056 | F -- .rdata | |
8057 | L -- .lit8 | |
8058 | f -- immediate value | |
8059 | l -- .lit4 | |
8060 | ||
8061 | The .lit4 and .lit8 sections are only used if | |
8062 | permitted by the -G argument. | |
8063 | ||
8064 | When generating embedded PIC code, we use the | |
8065 | .lit8 section but not the .lit4 section (we can do | |
8066 | .lit4 inline easily; we need to put .lit8 | |
8067 | somewhere in the data segment, and using .lit8 | |
8068 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8069 | .lit8 entries). |
8070 | ||
8071 | The code below needs to know whether the target register | |
8072 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8073 | 'F' are used with GPR-based instructions and 'l' and | |
8074 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8075 | |
8076 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8077 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8078 | |
8079 | save_in = input_line_pointer; | |
8080 | input_line_pointer = s; | |
8081 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8082 | length = len; | |
8083 | s = input_line_pointer; | |
8084 | input_line_pointer = save_in; | |
8085 | if (err != NULL && *err != '\0') | |
8086 | { | |
8087 | as_bad (_("Bad floating point constant: %s"), err); | |
8088 | memset (temp, '\0', sizeof temp); | |
8089 | length = f64 ? 8 : 4; | |
8090 | } | |
8091 | ||
156c2f8b | 8092 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8093 | |
8094 | if (*args == 'f' | |
8095 | || (*args == 'l' | |
8096 | && (! USE_GLOBAL_POINTER_OPT | |
8097 | || mips_pic == EMBEDDED_PIC | |
8098 | || g_switch_value < 4 | |
8099 | || (temp[0] == 0 && temp[1] == 0) | |
8100 | || (temp[2] == 0 && temp[3] == 0)))) | |
8101 | { | |
8102 | imm_expr.X_op = O_constant; | |
8103 | if (! target_big_endian) | |
8104 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8105 | else | |
8106 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8107 | } | |
8108 | else if (length > 4 | |
119d663a | 8109 | && ! mips_disable_float_construction |
ca4e0257 RS |
8110 | /* Constants can only be constructed in GPRs and |
8111 | copied to FPRs if the GPRs are at least as wide | |
8112 | as the FPRs. Force the constant into memory if | |
8113 | we are using 64-bit FPRs but the GPRs are only | |
8114 | 32 bits wide. */ | |
8115 | && (using_gprs | |
8116 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8117 | && ((temp[0] == 0 && temp[1] == 0) |
8118 | || (temp[2] == 0 && temp[3] == 0)) | |
8119 | && ((temp[4] == 0 && temp[5] == 0) | |
8120 | || (temp[6] == 0 && temp[7] == 0))) | |
8121 | { | |
ca4e0257 RS |
8122 | /* The value is simple enough to load with a couple of |
8123 | instructions. If using 32-bit registers, set | |
8124 | imm_expr to the high order 32 bits and offset_expr to | |
8125 | the low order 32 bits. Otherwise, set imm_expr to | |
8126 | the entire 64 bit constant. */ | |
8127 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8128 | { |
8129 | imm_expr.X_op = O_constant; | |
8130 | offset_expr.X_op = O_constant; | |
8131 | if (! target_big_endian) | |
8132 | { | |
8133 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8134 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8135 | } | |
8136 | else | |
8137 | { | |
8138 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8139 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8140 | } | |
8141 | if (offset_expr.X_add_number == 0) | |
8142 | offset_expr.X_op = O_absent; | |
8143 | } | |
8144 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8145 | { | |
8146 | imm_expr.X_op = O_constant; | |
8147 | if (! target_big_endian) | |
8148 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8149 | else | |
8150 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8151 | } | |
8152 | else | |
8153 | { | |
8154 | imm_expr.X_op = O_big; | |
8155 | imm_expr.X_add_number = 4; | |
8156 | if (! target_big_endian) | |
8157 | { | |
8158 | generic_bignum[0] = bfd_getl16 (temp); | |
8159 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8160 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8161 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8162 | } | |
8163 | else | |
8164 | { | |
8165 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8166 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8167 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8168 | generic_bignum[3] = bfd_getb16 (temp); | |
8169 | } | |
8170 | } | |
8171 | } | |
8172 | else | |
8173 | { | |
8174 | const char *newname; | |
8175 | segT new_seg; | |
8176 | ||
8177 | /* Switch to the right section. */ | |
8178 | seg = now_seg; | |
8179 | subseg = now_subseg; | |
8180 | switch (*args) | |
8181 | { | |
8182 | default: /* unused default case avoids warnings. */ | |
8183 | case 'L': | |
8184 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
8185 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
8186 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
8187 | newname = ".lit8"; |
8188 | break; | |
8189 | case 'F': | |
bb2d6cd7 GK |
8190 | if (mips_pic == EMBEDDED_PIC) |
8191 | newname = ".lit8"; | |
8192 | else | |
8193 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
8194 | break; |
8195 | case 'l': | |
8196 | assert (!USE_GLOBAL_POINTER_OPT | |
8197 | || g_switch_value >= 4); | |
8198 | newname = ".lit4"; | |
8199 | break; | |
8200 | } | |
8201 | new_seg = subseg_new (newname, (subsegT) 0); | |
8202 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8203 | bfd_set_section_flags (stdoutput, new_seg, | |
8204 | (SEC_ALLOC | |
8205 | | SEC_LOAD | |
8206 | | SEC_READONLY | |
8207 | | SEC_DATA)); | |
8208 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8209 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8210 | && strcmp (TARGET_OS, "elf") != 0) | |
8211 | record_alignment (new_seg, 4); | |
8212 | else | |
8213 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8214 | if (seg == now_seg) | |
8215 | as_bad (_("Can't use floating point insn in this section")); | |
8216 | ||
8217 | /* Set the argument to the current address in the | |
8218 | section. */ | |
8219 | offset_expr.X_op = O_symbol; | |
8220 | offset_expr.X_add_symbol = | |
8221 | symbol_new ("L0\001", now_seg, | |
8222 | (valueT) frag_now_fix (), frag_now); | |
8223 | offset_expr.X_add_number = 0; | |
8224 | ||
8225 | /* Put the floating point number into the section. */ | |
8226 | p = frag_more ((int) length); | |
8227 | memcpy (p, temp, length); | |
8228 | ||
8229 | /* Switch back to the original section. */ | |
8230 | subseg_set (seg, subseg); | |
8231 | } | |
8232 | } | |
8233 | continue; | |
8234 | ||
8235 | case 'i': /* 16 bit unsigned immediate */ | |
8236 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8237 | *imm_reloc = BFD_RELOC_LO16; |
252b5132 | 8238 | c = my_getSmallExpression (&imm_expr, s); |
fb1b3232 | 8239 | if (c != S_EX_NONE) |
252b5132 | 8240 | { |
fb1b3232 | 8241 | if (c != S_EX_LO) |
252b5132 RH |
8242 | { |
8243 | if (imm_expr.X_op == O_constant) | |
8244 | imm_expr.X_add_number = | |
8245 | (imm_expr.X_add_number >> 16) & 0xffff; | |
ad8d3bb3 | 8246 | #ifdef OBJ_ELF |
fb1b3232 | 8247 | else if (c == S_EX_HIGHEST) |
f6688943 | 8248 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
fb1b3232 | 8249 | else if (c == S_EX_HIGHER) |
f6688943 | 8250 | *imm_reloc = BFD_RELOC_MIPS_HIGHER; |
ad8d3bb3 TS |
8251 | else if (c == S_EX_GP_REL) |
8252 | { | |
8253 | /* This occurs in NewABI only. */ | |
8254 | c = my_getSmallExpression (&imm_expr, s); | |
8255 | if (c != S_EX_NEG) | |
8256 | as_bad (_("bad composition of relocations")); | |
8257 | else | |
8258 | { | |
8259 | c = my_getSmallExpression (&imm_expr, s); | |
8260 | if (c != S_EX_LO) | |
8261 | as_bad (_("bad composition of relocations")); | |
8262 | else | |
8263 | { | |
8264 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8265 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8266 | imm_reloc[2] = BFD_RELOC_LO16; | |
8267 | } | |
8268 | } | |
8269 | } | |
8270 | #endif | |
fb1b3232 | 8271 | else if (c == S_EX_HI) |
252b5132 | 8272 | { |
f6688943 | 8273 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8274 | imm_unmatched_hi = true; |
8275 | } | |
8276 | else | |
f6688943 | 8277 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8278 | } |
8279 | else if (imm_expr.X_op == O_constant) | |
8280 | imm_expr.X_add_number &= 0xffff; | |
8281 | } | |
8282 | if (*args == 'i') | |
8283 | { | |
fb1b3232 | 8284 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8285 | || ((imm_expr.X_add_number < 0 |
beae10d5 KH |
8286 | || imm_expr.X_add_number >= 0x10000) |
8287 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
8288 | { |
8289 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8290 | !strcmp (insn->name, insn[1].name)) | |
8291 | break; | |
2ae7e77b AH |
8292 | if (imm_expr.X_op == O_constant |
8293 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8294 | as_bad (_("16 bit expression not in range 0..65535")); |
8295 | } | |
8296 | } | |
8297 | else | |
8298 | { | |
8299 | int more; | |
8300 | offsetT max; | |
8301 | ||
8302 | /* The upper bound should be 0x8000, but | |
8303 | unfortunately the MIPS assembler accepts numbers | |
8304 | from 0x8000 to 0xffff and sign extends them, and | |
8305 | we want to be compatible. We only permit this | |
8306 | extended range for an instruction which does not | |
8307 | provide any further alternates, since those | |
8308 | alternates may handle other cases. People should | |
8309 | use the numbers they mean, rather than relying on | |
8310 | a mysterious sign extension. */ | |
8311 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8312 | strcmp (insn->name, insn[1].name) == 0); | |
8313 | if (more) | |
8314 | max = 0x8000; | |
8315 | else | |
8316 | max = 0x10000; | |
fb1b3232 | 8317 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8318 | || ((imm_expr.X_add_number < -0x8000 |
beae10d5 KH |
8319 | || imm_expr.X_add_number >= max) |
8320 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
8321 | || (more |
8322 | && imm_expr.X_add_number < 0 | |
ca4e0257 | 8323 | && HAVE_64BIT_GPRS |
252b5132 RH |
8324 | && imm_expr.X_unsigned |
8325 | && sizeof (imm_expr.X_add_number) <= 4)) | |
8326 | { | |
8327 | if (more) | |
8328 | break; | |
2ae7e77b AH |
8329 | if (imm_expr.X_op == O_constant |
8330 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8331 | as_bad (_("16 bit expression not in range -32768..32767")); |
8332 | } | |
8333 | } | |
8334 | s = expr_end; | |
8335 | continue; | |
8336 | ||
8337 | case 'o': /* 16 bit offset */ | |
8338 | c = my_getSmallExpression (&offset_expr, s); | |
8339 | ||
8340 | /* If this value won't fit into a 16 bit offset, then go | |
8341 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8342 | code pattern. */ |
fb1b3232 | 8343 | if (c == S_EX_NONE |
252b5132 RH |
8344 | && (offset_expr.X_op != O_constant |
8345 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8346 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8347 | break; |
8348 | ||
fb1b3232 | 8349 | if (c == S_EX_HI) |
252b5132 RH |
8350 | { |
8351 | if (offset_expr.X_op != O_constant) | |
8352 | break; | |
8353 | offset_expr.X_add_number = | |
8354 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8355 | } | |
f6688943 | 8356 | *offset_reloc = BFD_RELOC_LO16; |
252b5132 RH |
8357 | s = expr_end; |
8358 | continue; | |
8359 | ||
8360 | case 'p': /* pc relative offset */ | |
cb56d3d3 | 8361 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 8362 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 8363 | else |
f6688943 | 8364 | *offset_reloc = BFD_RELOC_16_PCREL; |
252b5132 RH |
8365 | my_getExpression (&offset_expr, s); |
8366 | s = expr_end; | |
8367 | continue; | |
8368 | ||
8369 | case 'u': /* upper 16 bits */ | |
8370 | c = my_getSmallExpression (&imm_expr, s); | |
f6688943 | 8371 | *imm_reloc = BFD_RELOC_LO16; |
e7d556df | 8372 | if (c != S_EX_NONE) |
252b5132 | 8373 | { |
fb1b3232 | 8374 | if (c != S_EX_LO) |
252b5132 RH |
8375 | { |
8376 | if (imm_expr.X_op == O_constant) | |
8377 | imm_expr.X_add_number = | |
8378 | (imm_expr.X_add_number >> 16) & 0xffff; | |
fb1b3232 | 8379 | else if (c == S_EX_HI) |
252b5132 | 8380 | { |
f6688943 | 8381 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8382 | imm_unmatched_hi = true; |
8383 | } | |
645dc66c TS |
8384 | #ifdef OBJ_ELF |
8385 | else if (c == S_EX_HIGHEST) | |
8386 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; | |
ad8d3bb3 TS |
8387 | else if (c == S_EX_GP_REL) |
8388 | { | |
8389 | /* This occurs in NewABI only. */ | |
8390 | c = my_getSmallExpression (&imm_expr, s); | |
8391 | if (c != S_EX_NEG) | |
8392 | as_bad (_("bad composition of relocations")); | |
8393 | else | |
8394 | { | |
8395 | c = my_getSmallExpression (&imm_expr, s); | |
8396 | if (c != S_EX_HI) | |
8397 | as_bad (_("bad composition of relocations")); | |
8398 | else | |
8399 | { | |
8400 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8401 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8402 | imm_reloc[2] = BFD_RELOC_HI16_S; | |
8403 | } | |
8404 | } | |
8405 | } | |
8406 | #endif | |
252b5132 | 8407 | else |
f6688943 | 8408 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8409 | } |
8410 | else if (imm_expr.X_op == O_constant) | |
8411 | imm_expr.X_add_number &= 0xffff; | |
8412 | } | |
8413 | if (imm_expr.X_op == O_constant | |
8414 | && (imm_expr.X_add_number < 0 | |
8415 | || imm_expr.X_add_number >= 0x10000)) | |
8416 | as_bad (_("lui expression not in range 0..65535")); | |
8417 | s = expr_end; | |
8418 | continue; | |
8419 | ||
8420 | case 'a': /* 26 bit address */ | |
8421 | my_getExpression (&offset_expr, s); | |
8422 | s = expr_end; | |
f6688943 | 8423 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8424 | continue; |
8425 | ||
8426 | case 'N': /* 3 bit branch condition code */ | |
8427 | case 'M': /* 3 bit compare condition code */ | |
8428 | if (strncmp (s, "$fcc", 4) != 0) | |
8429 | break; | |
8430 | s += 4; | |
8431 | regno = 0; | |
8432 | do | |
8433 | { | |
8434 | regno *= 10; | |
8435 | regno += *s - '0'; | |
8436 | ++s; | |
8437 | } | |
3882b010 | 8438 | while (ISDIGIT (*s)); |
252b5132 RH |
8439 | if (regno > 7) |
8440 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
8441 | if (*args == 'N') | |
8442 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8443 | else | |
8444 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 8445 | continue; |
252b5132 | 8446 | |
156c2f8b NC |
8447 | case 'H': |
8448 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8449 | s += 2; | |
3882b010 | 8450 | if (ISDIGIT (*s)) |
156c2f8b NC |
8451 | { |
8452 | c = 0; | |
8453 | do | |
8454 | { | |
8455 | c *= 10; | |
8456 | c += *s - '0'; | |
8457 | ++s; | |
8458 | } | |
3882b010 | 8459 | while (ISDIGIT (*s)); |
156c2f8b NC |
8460 | } |
8461 | else | |
8462 | c = 8; /* Invalid sel value. */ | |
8463 | ||
8464 | if (c > 7) | |
8465 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8466 | ip->insn_opcode |= c; | |
8467 | continue; | |
8468 | ||
252b5132 RH |
8469 | default: |
8470 | as_bad (_("bad char = '%c'\n"), *args); | |
8471 | internalError (); | |
8472 | } | |
8473 | break; | |
8474 | } | |
8475 | /* Args don't match. */ | |
8476 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8477 | !strcmp (insn->name, insn[1].name)) | |
8478 | { | |
8479 | ++insn; | |
8480 | s = argsStart; | |
268f6bed | 8481 | insn_error = _("illegal operands"); |
252b5132 RH |
8482 | continue; |
8483 | } | |
268f6bed L |
8484 | if (save_c) |
8485 | *(--s) = save_c; | |
252b5132 RH |
8486 | insn_error = _("illegal operands"); |
8487 | return; | |
8488 | } | |
8489 | } | |
8490 | ||
8491 | /* This routine assembles an instruction into its binary format when | |
8492 | assembling for the mips16. As a side effect, it sets one of the | |
8493 | global variables imm_reloc or offset_reloc to the type of | |
8494 | relocation to do if one of the operands is an address expression. | |
8495 | It also sets mips16_small and mips16_ext if the user explicitly | |
8496 | requested a small or extended instruction. */ | |
8497 | ||
8498 | static void | |
8499 | mips16_ip (str, ip) | |
8500 | char *str; | |
8501 | struct mips_cl_insn *ip; | |
8502 | { | |
8503 | char *s; | |
8504 | const char *args; | |
8505 | struct mips_opcode *insn; | |
8506 | char *argsstart; | |
8507 | unsigned int regno; | |
8508 | unsigned int lastregno = 0; | |
8509 | char *s_reset; | |
8510 | ||
8511 | insn_error = NULL; | |
8512 | ||
8513 | mips16_small = false; | |
8514 | mips16_ext = false; | |
8515 | ||
3882b010 | 8516 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
8517 | ; |
8518 | switch (*s) | |
8519 | { | |
8520 | case '\0': | |
8521 | break; | |
8522 | ||
8523 | case ' ': | |
8524 | *s++ = '\0'; | |
8525 | break; | |
8526 | ||
8527 | case '.': | |
8528 | if (s[1] == 't' && s[2] == ' ') | |
8529 | { | |
8530 | *s = '\0'; | |
8531 | mips16_small = true; | |
8532 | s += 3; | |
8533 | break; | |
8534 | } | |
8535 | else if (s[1] == 'e' && s[2] == ' ') | |
8536 | { | |
8537 | *s = '\0'; | |
8538 | mips16_ext = true; | |
8539 | s += 3; | |
8540 | break; | |
8541 | } | |
8542 | /* Fall through. */ | |
8543 | default: | |
8544 | insn_error = _("unknown opcode"); | |
8545 | return; | |
8546 | } | |
8547 | ||
8548 | if (mips_opts.noautoextend && ! mips16_ext) | |
8549 | mips16_small = true; | |
8550 | ||
8551 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
8552 | { | |
8553 | insn_error = _("unrecognized opcode"); | |
8554 | return; | |
8555 | } | |
8556 | ||
8557 | argsstart = s; | |
8558 | for (;;) | |
8559 | { | |
8560 | assert (strcmp (insn->name, str) == 0); | |
8561 | ||
8562 | ip->insn_mo = insn; | |
8563 | ip->insn_opcode = insn->match; | |
8564 | ip->use_extend = false; | |
8565 | imm_expr.X_op = O_absent; | |
f6688943 TS |
8566 | imm_reloc[0] = BFD_RELOC_UNUSED; |
8567 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
8568 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 8569 | offset_expr.X_op = O_absent; |
f6688943 TS |
8570 | offset_reloc[0] = BFD_RELOC_UNUSED; |
8571 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8572 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
8573 | for (args = insn->args; 1; ++args) |
8574 | { | |
8575 | int c; | |
8576 | ||
8577 | if (*s == ' ') | |
8578 | ++s; | |
8579 | ||
8580 | /* In this switch statement we call break if we did not find | |
8581 | a match, continue if we did find a match, or return if we | |
8582 | are done. */ | |
8583 | ||
8584 | c = *args; | |
8585 | switch (c) | |
8586 | { | |
8587 | case '\0': | |
8588 | if (*s == '\0') | |
8589 | { | |
8590 | /* Stuff the immediate value in now, if we can. */ | |
8591 | if (imm_expr.X_op == O_constant | |
f6688943 | 8592 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
8593 | && insn->pinfo != INSN_MACRO) |
8594 | { | |
c4e7957c | 8595 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
252b5132 RH |
8596 | imm_expr.X_add_number, true, mips16_small, |
8597 | mips16_ext, &ip->insn_opcode, | |
8598 | &ip->use_extend, &ip->extend); | |
8599 | imm_expr.X_op = O_absent; | |
f6688943 | 8600 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
8601 | } |
8602 | ||
8603 | return; | |
8604 | } | |
8605 | break; | |
8606 | ||
8607 | case ',': | |
8608 | if (*s++ == c) | |
8609 | continue; | |
8610 | s--; | |
8611 | switch (*++args) | |
8612 | { | |
8613 | case 'v': | |
8614 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8615 | continue; | |
8616 | case 'w': | |
8617 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8618 | continue; | |
8619 | } | |
8620 | break; | |
8621 | ||
8622 | case '(': | |
8623 | case ')': | |
8624 | if (*s++ == c) | |
8625 | continue; | |
8626 | break; | |
8627 | ||
8628 | case 'v': | |
8629 | case 'w': | |
8630 | if (s[0] != '$') | |
8631 | { | |
8632 | if (c == 'v') | |
8633 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8634 | else | |
8635 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8636 | ++args; | |
8637 | continue; | |
8638 | } | |
8639 | /* Fall through. */ | |
8640 | case 'x': | |
8641 | case 'y': | |
8642 | case 'z': | |
8643 | case 'Z': | |
8644 | case '0': | |
8645 | case 'S': | |
8646 | case 'R': | |
8647 | case 'X': | |
8648 | case 'Y': | |
8649 | if (s[0] != '$') | |
8650 | break; | |
8651 | s_reset = s; | |
3882b010 | 8652 | if (ISDIGIT (s[1])) |
252b5132 RH |
8653 | { |
8654 | ++s; | |
8655 | regno = 0; | |
8656 | do | |
8657 | { | |
8658 | regno *= 10; | |
8659 | regno += *s - '0'; | |
8660 | ++s; | |
8661 | } | |
3882b010 | 8662 | while (ISDIGIT (*s)); |
252b5132 RH |
8663 | if (regno > 31) |
8664 | { | |
8665 | as_bad (_("invalid register number (%d)"), regno); | |
8666 | regno = 2; | |
8667 | } | |
8668 | } | |
8669 | else | |
8670 | { | |
8671 | if (s[1] == 'f' && s[2] == 'p') | |
8672 | { | |
8673 | s += 3; | |
8674 | regno = FP; | |
8675 | } | |
8676 | else if (s[1] == 's' && s[2] == 'p') | |
8677 | { | |
8678 | s += 3; | |
8679 | regno = SP; | |
8680 | } | |
8681 | else if (s[1] == 'g' && s[2] == 'p') | |
8682 | { | |
8683 | s += 3; | |
8684 | regno = GP; | |
8685 | } | |
8686 | else if (s[1] == 'a' && s[2] == 't') | |
8687 | { | |
8688 | s += 3; | |
8689 | regno = AT; | |
8690 | } | |
8691 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8692 | { | |
8693 | s += 4; | |
8694 | regno = KT0; | |
8695 | } | |
8696 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8697 | { | |
8698 | s += 4; | |
8699 | regno = KT1; | |
8700 | } | |
8701 | else | |
8702 | break; | |
8703 | } | |
8704 | ||
8705 | if (*s == ' ') | |
8706 | ++s; | |
8707 | if (args[1] != *s) | |
8708 | { | |
8709 | if (c == 'v' || c == 'w') | |
8710 | { | |
8711 | regno = mips16_to_32_reg_map[lastregno]; | |
8712 | s = s_reset; | |
8713 | args++; | |
8714 | } | |
8715 | } | |
8716 | ||
8717 | switch (c) | |
8718 | { | |
8719 | case 'x': | |
8720 | case 'y': | |
8721 | case 'z': | |
8722 | case 'v': | |
8723 | case 'w': | |
8724 | case 'Z': | |
8725 | regno = mips32_to_16_reg_map[regno]; | |
8726 | break; | |
8727 | ||
8728 | case '0': | |
8729 | if (regno != 0) | |
8730 | regno = ILLEGAL_REG; | |
8731 | break; | |
8732 | ||
8733 | case 'S': | |
8734 | if (regno != SP) | |
8735 | regno = ILLEGAL_REG; | |
8736 | break; | |
8737 | ||
8738 | case 'R': | |
8739 | if (regno != RA) | |
8740 | regno = ILLEGAL_REG; | |
8741 | break; | |
8742 | ||
8743 | case 'X': | |
8744 | case 'Y': | |
8745 | if (regno == AT && ! mips_opts.noat) | |
8746 | as_warn (_("used $at without \".set noat\"")); | |
8747 | break; | |
8748 | ||
8749 | default: | |
8750 | internalError (); | |
8751 | } | |
8752 | ||
8753 | if (regno == ILLEGAL_REG) | |
8754 | break; | |
8755 | ||
8756 | switch (c) | |
8757 | { | |
8758 | case 'x': | |
8759 | case 'v': | |
8760 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8761 | break; | |
8762 | case 'y': | |
8763 | case 'w': | |
8764 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8765 | break; | |
8766 | case 'z': | |
8767 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8768 | break; | |
8769 | case 'Z': | |
8770 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8771 | case '0': | |
8772 | case 'S': | |
8773 | case 'R': | |
8774 | break; | |
8775 | case 'X': | |
8776 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8777 | break; | |
8778 | case 'Y': | |
8779 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8780 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8781 | break; | |
8782 | default: | |
8783 | internalError (); | |
8784 | } | |
8785 | ||
8786 | lastregno = regno; | |
8787 | continue; | |
8788 | ||
8789 | case 'P': | |
8790 | if (strncmp (s, "$pc", 3) == 0) | |
8791 | { | |
8792 | s += 3; | |
8793 | continue; | |
8794 | } | |
8795 | break; | |
8796 | ||
8797 | case '<': | |
8798 | case '>': | |
8799 | case '[': | |
8800 | case ']': | |
8801 | case '4': | |
8802 | case '5': | |
8803 | case 'H': | |
8804 | case 'W': | |
8805 | case 'D': | |
8806 | case 'j': | |
8807 | case '8': | |
8808 | case 'V': | |
8809 | case 'C': | |
8810 | case 'U': | |
8811 | case 'k': | |
8812 | case 'K': | |
8813 | if (s[0] == '%' | |
8814 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8815 | { | |
8816 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8817 | and generate the appropriate reloc. If the text | |
8818 | inside %gprel is not a symbol name with an | |
8819 | optional offset, then we generate a normal reloc | |
8820 | and will probably fail later. */ | |
8821 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8822 | if (imm_expr.X_op == O_symbol) | |
8823 | { | |
8824 | mips16_ext = true; | |
f6688943 | 8825 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 RH |
8826 | s = expr_end; |
8827 | ip->use_extend = true; | |
8828 | ip->extend = 0; | |
8829 | continue; | |
8830 | } | |
8831 | } | |
8832 | else | |
8833 | { | |
8834 | /* Just pick up a normal expression. */ | |
8835 | my_getExpression (&imm_expr, s); | |
8836 | } | |
8837 | ||
8838 | if (imm_expr.X_op == O_register) | |
8839 | { | |
8840 | /* What we thought was an expression turned out to | |
8841 | be a register. */ | |
8842 | ||
8843 | if (s[0] == '(' && args[1] == '(') | |
8844 | { | |
8845 | /* It looks like the expression was omitted | |
8846 | before a register indirection, which means | |
8847 | that the expression is implicitly zero. We | |
8848 | still set up imm_expr, so that we handle | |
8849 | explicit extensions correctly. */ | |
8850 | imm_expr.X_op = O_constant; | |
8851 | imm_expr.X_add_number = 0; | |
f6688943 | 8852 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
8853 | continue; |
8854 | } | |
8855 | ||
8856 | break; | |
8857 | } | |
8858 | ||
8859 | /* We need to relax this instruction. */ | |
f6688943 | 8860 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
8861 | s = expr_end; |
8862 | continue; | |
8863 | ||
8864 | case 'p': | |
8865 | case 'q': | |
8866 | case 'A': | |
8867 | case 'B': | |
8868 | case 'E': | |
8869 | /* We use offset_reloc rather than imm_reloc for the PC | |
8870 | relative operands. This lets macros with both | |
8871 | immediate and address operands work correctly. */ | |
8872 | my_getExpression (&offset_expr, s); | |
8873 | ||
8874 | if (offset_expr.X_op == O_register) | |
8875 | break; | |
8876 | ||
8877 | /* We need to relax this instruction. */ | |
f6688943 | 8878 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
8879 | s = expr_end; |
8880 | continue; | |
8881 | ||
8882 | case '6': /* break code */ | |
8883 | my_getExpression (&imm_expr, s); | |
8884 | check_absolute_expr (ip, &imm_expr); | |
8885 | if ((unsigned long) imm_expr.X_add_number > 63) | |
8886 | { | |
8887 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8888 | ip->insn_mo->name, | |
8889 | (unsigned long) imm_expr.X_add_number); | |
8890 | imm_expr.X_add_number &= 0x3f; | |
8891 | } | |
8892 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
8893 | imm_expr.X_op = O_absent; | |
8894 | s = expr_end; | |
8895 | continue; | |
8896 | ||
8897 | case 'a': /* 26 bit address */ | |
8898 | my_getExpression (&offset_expr, s); | |
8899 | s = expr_end; | |
f6688943 | 8900 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
8901 | ip->insn_opcode <<= 16; |
8902 | continue; | |
8903 | ||
8904 | case 'l': /* register list for entry macro */ | |
8905 | case 'L': /* register list for exit macro */ | |
8906 | { | |
8907 | int mask; | |
8908 | ||
8909 | if (c == 'l') | |
8910 | mask = 0; | |
8911 | else | |
8912 | mask = 7 << 3; | |
8913 | while (*s != '\0') | |
8914 | { | |
8915 | int freg, reg1, reg2; | |
8916 | ||
8917 | while (*s == ' ' || *s == ',') | |
8918 | ++s; | |
8919 | if (*s != '$') | |
8920 | { | |
8921 | as_bad (_("can't parse register list")); | |
8922 | break; | |
8923 | } | |
8924 | ++s; | |
8925 | if (*s != 'f') | |
8926 | freg = 0; | |
8927 | else | |
8928 | { | |
8929 | freg = 1; | |
8930 | ++s; | |
8931 | } | |
8932 | reg1 = 0; | |
3882b010 | 8933 | while (ISDIGIT (*s)) |
252b5132 RH |
8934 | { |
8935 | reg1 *= 10; | |
8936 | reg1 += *s - '0'; | |
8937 | ++s; | |
8938 | } | |
8939 | if (*s == ' ') | |
8940 | ++s; | |
8941 | if (*s != '-') | |
8942 | reg2 = reg1; | |
8943 | else | |
8944 | { | |
8945 | ++s; | |
8946 | if (*s != '$') | |
8947 | break; | |
8948 | ++s; | |
8949 | if (freg) | |
8950 | { | |
8951 | if (*s == 'f') | |
8952 | ++s; | |
8953 | else | |
8954 | { | |
8955 | as_bad (_("invalid register list")); | |
8956 | break; | |
8957 | } | |
8958 | } | |
8959 | reg2 = 0; | |
3882b010 | 8960 | while (ISDIGIT (*s)) |
252b5132 RH |
8961 | { |
8962 | reg2 *= 10; | |
8963 | reg2 += *s - '0'; | |
8964 | ++s; | |
8965 | } | |
8966 | } | |
8967 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
8968 | { | |
8969 | mask &= ~ (7 << 3); | |
8970 | mask |= 5 << 3; | |
8971 | } | |
8972 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8973 | { | |
8974 | mask &= ~ (7 << 3); | |
8975 | mask |= 6 << 3; | |
8976 | } | |
8977 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
8978 | mask |= (reg2 - 3) << 3; | |
8979 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8980 | mask |= (reg2 - 15) << 1; | |
8981 | else if (reg1 == 31 && reg2 == 31) | |
8982 | mask |= 1; | |
8983 | else | |
8984 | { | |
8985 | as_bad (_("invalid register list")); | |
8986 | break; | |
8987 | } | |
8988 | } | |
8989 | /* The mask is filled in in the opcode table for the | |
8990 | benefit of the disassembler. We remove it before | |
8991 | applying the actual mask. */ | |
8992 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
8993 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
8994 | } | |
8995 | continue; | |
8996 | ||
8997 | case 'e': /* extend code */ | |
8998 | my_getExpression (&imm_expr, s); | |
8999 | check_absolute_expr (ip, &imm_expr); | |
9000 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9001 | { | |
9002 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9003 | ip->insn_mo->name, | |
9004 | (unsigned long) imm_expr.X_add_number); | |
9005 | imm_expr.X_add_number &= 0x7ff; | |
9006 | } | |
9007 | ip->insn_opcode |= imm_expr.X_add_number; | |
9008 | imm_expr.X_op = O_absent; | |
9009 | s = expr_end; | |
9010 | continue; | |
9011 | ||
9012 | default: | |
9013 | internalError (); | |
9014 | } | |
9015 | break; | |
9016 | } | |
9017 | ||
9018 | /* Args don't match. */ | |
9019 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9020 | strcmp (insn->name, insn[1].name) == 0) | |
9021 | { | |
9022 | ++insn; | |
9023 | s = argsstart; | |
9024 | continue; | |
9025 | } | |
9026 | ||
9027 | insn_error = _("illegal operands"); | |
9028 | ||
9029 | return; | |
9030 | } | |
9031 | } | |
9032 | ||
9033 | /* This structure holds information we know about a mips16 immediate | |
9034 | argument type. */ | |
9035 | ||
e972090a NC |
9036 | struct mips16_immed_operand |
9037 | { | |
252b5132 RH |
9038 | /* The type code used in the argument string in the opcode table. */ |
9039 | int type; | |
9040 | /* The number of bits in the short form of the opcode. */ | |
9041 | int nbits; | |
9042 | /* The number of bits in the extended form of the opcode. */ | |
9043 | int extbits; | |
9044 | /* The amount by which the short form is shifted when it is used; | |
9045 | for example, the sw instruction has a shift count of 2. */ | |
9046 | int shift; | |
9047 | /* The amount by which the short form is shifted when it is stored | |
9048 | into the instruction code. */ | |
9049 | int op_shift; | |
9050 | /* Non-zero if the short form is unsigned. */ | |
9051 | int unsp; | |
9052 | /* Non-zero if the extended form is unsigned. */ | |
9053 | int extu; | |
9054 | /* Non-zero if the value is PC relative. */ | |
9055 | int pcrel; | |
9056 | }; | |
9057 | ||
9058 | /* The mips16 immediate operand types. */ | |
9059 | ||
9060 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9061 | { | |
9062 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9063 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9064 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9065 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9066 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9067 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9068 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9069 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9070 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9071 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9072 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9073 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9074 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9075 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9076 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9077 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9078 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9079 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9080 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9081 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9082 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9083 | }; | |
9084 | ||
9085 | #define MIPS16_NUM_IMMED \ | |
9086 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9087 | ||
9088 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9089 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9090 | whether an extended value is needed; if one is needed, it sets | |
9091 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9092 | If SMALL is true, an unextended opcode was explicitly requested. | |
9093 | If EXT is true, an extended opcode was explicitly requested. If | |
9094 | WARN is true, warn if EXT does not match reality. */ | |
9095 | ||
9096 | static void | |
9097 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
9098 | extend) | |
9099 | char *file; | |
9100 | unsigned int line; | |
9101 | int type; | |
9102 | offsetT val; | |
9103 | boolean warn; | |
9104 | boolean small; | |
9105 | boolean ext; | |
9106 | unsigned long *insn; | |
9107 | boolean *use_extend; | |
9108 | unsigned short *extend; | |
9109 | { | |
9110 | register const struct mips16_immed_operand *op; | |
9111 | int mintiny, maxtiny; | |
9112 | boolean needext; | |
9113 | ||
9114 | op = mips16_immed_operands; | |
9115 | while (op->type != type) | |
9116 | { | |
9117 | ++op; | |
9118 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9119 | } | |
9120 | ||
9121 | if (op->unsp) | |
9122 | { | |
9123 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9124 | { | |
9125 | mintiny = 1; | |
9126 | maxtiny = 1 << op->nbits; | |
9127 | } | |
9128 | else | |
9129 | { | |
9130 | mintiny = 0; | |
9131 | maxtiny = (1 << op->nbits) - 1; | |
9132 | } | |
9133 | } | |
9134 | else | |
9135 | { | |
9136 | mintiny = - (1 << (op->nbits - 1)); | |
9137 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9138 | } | |
9139 | ||
9140 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9141 | if (type == 'p' || type == 'q') | |
9142 | val /= 2; | |
9143 | ||
9144 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9145 | || val < (mintiny << op->shift) | |
9146 | || val > (maxtiny << op->shift)) | |
9147 | needext = true; | |
9148 | else | |
9149 | needext = false; | |
9150 | ||
9151 | if (warn && ext && ! needext) | |
beae10d5 KH |
9152 | as_warn_where (file, line, |
9153 | _("extended operand requested but not required")); | |
252b5132 RH |
9154 | if (small && needext) |
9155 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9156 | ||
9157 | if (small || (! ext && ! needext)) | |
9158 | { | |
9159 | int insnval; | |
9160 | ||
9161 | *use_extend = false; | |
9162 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
9163 | insnval <<= op->op_shift; | |
9164 | *insn |= insnval; | |
9165 | } | |
9166 | else | |
9167 | { | |
9168 | long minext, maxext; | |
9169 | int extval; | |
9170 | ||
9171 | if (op->extu) | |
9172 | { | |
9173 | minext = 0; | |
9174 | maxext = (1 << op->extbits) - 1; | |
9175 | } | |
9176 | else | |
9177 | { | |
9178 | minext = - (1 << (op->extbits - 1)); | |
9179 | maxext = (1 << (op->extbits - 1)) - 1; | |
9180 | } | |
9181 | if (val < minext || val > maxext) | |
9182 | as_bad_where (file, line, | |
9183 | _("operand value out of range for instruction")); | |
9184 | ||
9185 | *use_extend = true; | |
9186 | if (op->extbits == 16) | |
9187 | { | |
9188 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9189 | val &= 0x1f; | |
9190 | } | |
9191 | else if (op->extbits == 15) | |
9192 | { | |
9193 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9194 | val &= 0xf; | |
9195 | } | |
9196 | else | |
9197 | { | |
9198 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9199 | val = 0; | |
9200 | } | |
9201 | ||
9202 | *extend = (unsigned short) extval; | |
9203 | *insn |= val; | |
9204 | } | |
9205 | } | |
9206 | \f | |
ad8d3bb3 TS |
9207 | static struct percent_op_match |
9208 | { | |
9209 | const char *str; | |
9210 | const enum small_ex_type type; | |
9211 | } percent_op[] = | |
9212 | { | |
9213 | #ifdef OBJ_ELF | |
9214 | {"%half", S_EX_HALF}, | |
9215 | #endif | |
9216 | {"%hi", S_EX_HI}, | |
9217 | {"%lo", S_EX_LO}, | |
9218 | #ifdef OBJ_ELF | |
9219 | {"%gp_rel", S_EX_GP_REL}, | |
9220 | {"%got", S_EX_GOT}, | |
9221 | {"%call16", S_EX_CALL16}, | |
9222 | {"%got_disp", S_EX_GOT_DISP}, | |
9223 | {"%got_page", S_EX_GOT_PAGE}, | |
9224 | {"%got_ofst", S_EX_GOT_OFST}, | |
9225 | {"%got_hi", S_EX_GOT_HI}, | |
9226 | {"%got_lo", S_EX_GOT_LO}, | |
9227 | {"%neg", S_EX_NEG}, | |
9228 | {"%higher", S_EX_HIGHER}, | |
9229 | {"%highest", S_EX_HIGHEST}, | |
9230 | {"%call_hi", S_EX_CALL_HI}, | |
9231 | {"%call_lo", S_EX_CALL_LO} | |
9232 | #endif | |
9233 | }; | |
9234 | ||
9235 | /* Parse small expression input. STR gets adjusted to eat up whitespace. | |
9236 | It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's | |
9237 | can be nested, this is handled by blanking the innermost, parsing the | |
9238 | rest by subsequent calls. */ | |
252b5132 RH |
9239 | |
9240 | static int | |
ad8d3bb3 TS |
9241 | my_getSmallParser (str, len, nestlevel) |
9242 | char **str; | |
9243 | unsigned int *len; | |
9244 | int *nestlevel; | |
252b5132 | 9245 | { |
ad8d3bb3 | 9246 | int type = S_EX_NONE; |
252b5132 | 9247 | |
ad8d3bb3 TS |
9248 | *len = 0; |
9249 | *str += strspn (*str, " \t"); | |
9250 | if (**str == '(') | |
252b5132 | 9251 | { |
ad8d3bb3 TS |
9252 | char *b = *str + 1 + strspn (*str + 1, " \t"); |
9253 | char *e; | |
9254 | ||
9255 | /* Check for base register. */ | |
9256 | if (b[0] == '$') | |
9257 | { | |
9258 | if (strchr (b, ')') | |
9259 | && (e = b + strcspn (b, ") \t")) | |
9260 | && e - b > 1 && e - b < 4) | |
9261 | { | |
9262 | if ((e - b == 3 | |
9263 | && ((b[1] == 'f' && b[2] == 'p') | |
9264 | || (b[1] == 's' && b[2] == 'p') | |
9265 | || (b[1] == 'g' && b[2] == 'p') | |
9266 | || (b[1] == 'a' && b[2] == 't') | |
9267 | || (ISDIGIT (b[1]) | |
9268 | && ISDIGIT (b[2])))) | |
9269 | || (ISDIGIT (b[1]))) | |
9270 | { | |
9271 | *len = strcspn (*str, ")") + 1; | |
9272 | return S_EX_REGISTER; | |
9273 | } | |
9274 | } | |
9275 | } | |
9276 | else if (b[0] == '%') | |
9277 | { | |
9278 | *str = b; | |
9279 | goto percent_op; | |
9280 | } | |
76b3015f EC |
9281 | |
9282 | /* Some other expression in the braces. */ | |
9283 | *len = strcspn (*str, ")") + 1; | |
fb1b3232 | 9284 | } |
ad8d3bb3 TS |
9285 | /* Check for percent_op. */ |
9286 | else if (*str[0] == '%') | |
fb1b3232 | 9287 | { |
ad8d3bb3 TS |
9288 | char *tmp; |
9289 | unsigned int i; | |
9290 | ||
9291 | percent_op: | |
9292 | tmp = *str + 1; | |
9293 | i = 0; | |
9294 | ||
9295 | while (ISALPHA (*tmp) || *tmp == '_') | |
9296 | { | |
9297 | *tmp = TOLOWER (*tmp); | |
9298 | tmp++; | |
9299 | } | |
9300 | while (i < (sizeof (percent_op) / sizeof (struct percent_op_match))) | |
9301 | { | |
9302 | if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str))) | |
9303 | i++; | |
9304 | else | |
9305 | { | |
9306 | type = percent_op[i].type; | |
9307 | ||
9308 | /* Only %hi and %lo are allowed for OldABI. */ | |
9309 | if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO) | |
9310 | return S_EX_NONE; | |
9311 | ||
9312 | *len = strlen (percent_op[i].str); | |
9313 | (*nestlevel)++; | |
9314 | return type; | |
9315 | } | |
9316 | } | |
fb1b3232 | 9317 | } |
ad8d3bb3 TS |
9318 | |
9319 | /* Any other expression. */ | |
9320 | return S_EX_NONE; | |
9321 | } | |
9322 | ||
9323 | static int | |
9324 | my_getSmallExpression (ep, str) | |
9325 | expressionS *ep; | |
9326 | char *str; | |
9327 | { | |
9328 | static char *oldstr = NULL; | |
9329 | int c = S_EX_NONE; | |
9330 | int oldc; | |
9331 | int nest_level = 0; | |
9332 | unsigned int len; | |
9333 | ||
9334 | /* Don't update oldstr if the last call had nested percent_op's. */ | |
9335 | if (! oldstr) | |
9336 | oldstr = str; | |
76b3015f | 9337 | |
ad8d3bb3 | 9338 | do |
fb1b3232 | 9339 | { |
ad8d3bb3 TS |
9340 | oldc = c; |
9341 | c = my_getSmallParser (&str, &len, &nest_level); | |
9342 | if (c != S_EX_NONE && c != S_EX_REGISTER) | |
9343 | str += len; | |
fb1b3232 | 9344 | } |
ad8d3bb3 TS |
9345 | while (c != S_EX_NONE && c != S_EX_REGISTER); |
9346 | ||
9347 | /* A percent_op was encountered. */ | |
9348 | if (nest_level) | |
fb1b3232 | 9349 | { |
b6ff326e | 9350 | /* Don't try to get an expression if it is already blanked out. */ |
ad8d3bb3 TS |
9351 | if (*(str + strspn (str + 1, " )")) != ')') |
9352 | { | |
9353 | char save; | |
9354 | ||
9355 | save = *(str + len); | |
9356 | *(str + len) = '\0'; | |
9357 | my_getExpression (ep, str); | |
9358 | *(str + len) = save; | |
9359 | } | |
9360 | if (nest_level > 1) | |
9361 | { | |
9362 | /* blank out including the % sign. */ | |
9363 | char *p = strrchr (oldstr, '%'); | |
9364 | memset (p, ' ', str - p + len); | |
9365 | str = oldstr; | |
9366 | } | |
9367 | else | |
9368 | { | |
9369 | expr_end = strchr (str, ')') + 1; | |
9370 | } | |
9371 | c = oldc; | |
fb1b3232 | 9372 | } |
ad8d3bb3 | 9373 | else if (c == S_EX_NONE) |
fb1b3232 | 9374 | { |
ad8d3bb3 | 9375 | my_getExpression (ep, str); |
fb1b3232 | 9376 | } |
ad8d3bb3 | 9377 | else if (c == S_EX_REGISTER) |
fb1b3232 | 9378 | { |
ad8d3bb3 TS |
9379 | ep->X_op = O_constant; |
9380 | expr_end = str; | |
9381 | ep->X_add_symbol = NULL; | |
9382 | ep->X_op_symbol = NULL; | |
9383 | ep->X_add_number = 0; | |
fb1b3232 | 9384 | } |
fb1b3232 TS |
9385 | else |
9386 | { | |
ad8d3bb3 | 9387 | as_fatal(_("internal error")); |
fb1b3232 | 9388 | } |
252b5132 | 9389 | |
ad8d3bb3 TS |
9390 | if (nest_level <= 1) |
9391 | oldstr = NULL; | |
fb1b3232 | 9392 | |
fb1b3232 | 9393 | return c; |
252b5132 RH |
9394 | } |
9395 | ||
9396 | static void | |
9397 | my_getExpression (ep, str) | |
9398 | expressionS *ep; | |
9399 | char *str; | |
9400 | { | |
9401 | char *save_in; | |
98aa84af | 9402 | valueT val; |
252b5132 RH |
9403 | |
9404 | save_in = input_line_pointer; | |
9405 | input_line_pointer = str; | |
9406 | expression (ep); | |
9407 | expr_end = input_line_pointer; | |
9408 | input_line_pointer = save_in; | |
9409 | ||
9410 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9411 | then we bump the value of the symbol by 1 since that is how other | |
9412 | text symbols are handled. We don't bother to handle complex | |
9413 | expressions, just `.' plus or minus a constant. */ | |
9414 | if (mips_opts.mips16 | |
9415 | && ep->X_op == O_symbol | |
9416 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9417 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9418 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9419 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9420 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9421 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9422 | } |
9423 | ||
9424 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9425 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9426 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9427 | returned, or NULL on OK. */ |
9428 | ||
9429 | char * | |
9430 | md_atof (type, litP, sizeP) | |
9431 | int type; | |
9432 | char *litP; | |
9433 | int *sizeP; | |
9434 | { | |
9435 | int prec; | |
9436 | LITTLENUM_TYPE words[4]; | |
9437 | char *t; | |
9438 | int i; | |
9439 | ||
9440 | switch (type) | |
9441 | { | |
9442 | case 'f': | |
9443 | prec = 2; | |
9444 | break; | |
9445 | ||
9446 | case 'd': | |
9447 | prec = 4; | |
9448 | break; | |
9449 | ||
9450 | default: | |
9451 | *sizeP = 0; | |
9452 | return _("bad call to md_atof"); | |
9453 | } | |
9454 | ||
9455 | t = atof_ieee (input_line_pointer, type, words); | |
9456 | if (t) | |
9457 | input_line_pointer = t; | |
9458 | ||
9459 | *sizeP = prec * 2; | |
9460 | ||
9461 | if (! target_big_endian) | |
9462 | { | |
9463 | for (i = prec - 1; i >= 0; i--) | |
9464 | { | |
9465 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9466 | litP += 2; | |
9467 | } | |
9468 | } | |
9469 | else | |
9470 | { | |
9471 | for (i = 0; i < prec; i++) | |
9472 | { | |
9473 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9474 | litP += 2; | |
9475 | } | |
9476 | } | |
bdaaa2e1 | 9477 | |
252b5132 RH |
9478 | return NULL; |
9479 | } | |
9480 | ||
9481 | void | |
9482 | md_number_to_chars (buf, val, n) | |
9483 | char *buf; | |
9484 | valueT val; | |
9485 | int n; | |
9486 | { | |
9487 | if (target_big_endian) | |
9488 | number_to_chars_bigendian (buf, val, n); | |
9489 | else | |
9490 | number_to_chars_littleendian (buf, val, n); | |
9491 | } | |
9492 | \f | |
ae948b86 | 9493 | #ifdef OBJ_ELF |
e013f690 TS |
9494 | static int support_64bit_objects(void) |
9495 | { | |
9496 | const char **list, **l; | |
9497 | ||
9498 | list = bfd_target_list (); | |
9499 | for (l = list; *l != NULL; l++) | |
9500 | #ifdef TE_TMIPS | |
9501 | /* This is traditional mips */ | |
9502 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9503 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9504 | #else | |
9505 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9506 | || strcmp (*l, "elf64-littlemips") == 0) | |
9507 | #endif | |
9508 | break; | |
9509 | free (list); | |
9510 | return (*l != NULL); | |
9511 | } | |
ae948b86 | 9512 | #endif /* OBJ_ELF */ |
e013f690 | 9513 | |
39c0a331 | 9514 | CONST char *md_shortopts = "nO::g::G:"; |
252b5132 | 9515 | |
e972090a NC |
9516 | struct option md_longopts[] = |
9517 | { | |
252b5132 RH |
9518 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
9519 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
9520 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
9521 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
9522 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
9523 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
9524 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
9525 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
9526 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
ae948b86 TS |
9527 | #define OPTION_MIPS5 (OPTION_MD_BASE + 5) |
9528 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
9529 | #define OPTION_MIPS32 (OPTION_MD_BASE + 6) | |
9530 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
9531 | #define OPTION_MIPS64 (OPTION_MD_BASE + 7) | |
9532 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
9533 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8) | |
252b5132 | 9534 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
ae948b86 | 9535 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
252b5132 RH |
9536 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9537 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
ae948b86 | 9538 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
252b5132 RH |
9539 | {"break", no_argument, NULL, OPTION_BREAK}, |
9540 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
ae948b86 | 9541 | #define OPTION_EB (OPTION_MD_BASE + 11) |
252b5132 | 9542 | {"EB", no_argument, NULL, OPTION_EB}, |
ae948b86 | 9543 | #define OPTION_EL (OPTION_MD_BASE + 12) |
252b5132 | 9544 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 9545 | #define OPTION_MIPS16 (OPTION_MD_BASE + 13) |
252b5132 | 9546 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
ae948b86 | 9547 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14) |
252b5132 | 9548 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
ae948b86 | 9549 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15) |
6b76fefe | 9550 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
ae948b86 | 9551 | #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 16) |
6b76fefe | 9552 | {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX}, |
ae948b86 TS |
9553 | #define OPTION_FP32 (OPTION_MD_BASE + 17) |
9554 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
9555 | #define OPTION_GP32 (OPTION_MD_BASE + 18) | |
c97ef257 | 9556 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
ae948b86 | 9557 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19) |
119d663a | 9558 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
ae948b86 | 9559 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20) |
119d663a | 9560 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
ae948b86 | 9561 | #define OPTION_MARCH (OPTION_MD_BASE + 21) |
ec68c924 | 9562 | {"march", required_argument, NULL, OPTION_MARCH}, |
ae948b86 | 9563 | #define OPTION_MTUNE (OPTION_MD_BASE + 22) |
ec68c924 | 9564 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
ae948b86 TS |
9565 | #define OPTION_MCPU (OPTION_MD_BASE + 23) |
9566 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
9567 | #define OPTION_M4650 (OPTION_MD_BASE + 24) | |
9568 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
9569 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 25) | |
9570 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
9571 | #define OPTION_M4010 (OPTION_MD_BASE + 26) | |
9572 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
9573 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 27) | |
9574 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
9575 | #define OPTION_M4100 (OPTION_MD_BASE + 28) | |
9576 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
9577 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 29) | |
9578 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
9579 | #define OPTION_M3900 (OPTION_MD_BASE + 30) | |
9580 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
9581 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 31) | |
9582 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
9583 | #define OPTION_GP64 (OPTION_MD_BASE + 32) | |
9584 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
156c2f8b | 9585 | #ifdef OBJ_ELF |
ae948b86 | 9586 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 33) |
156c2f8b | 9587 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
9588 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
9589 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 9590 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 9591 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 9592 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 9593 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
9594 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
9595 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
9596 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 9597 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 9598 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 9599 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 9600 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 9601 | {"64", no_argument, NULL, OPTION_64}, |
ae948b86 | 9602 | #endif /* OBJ_ELF */ |
252b5132 RH |
9603 | {NULL, no_argument, NULL, 0} |
9604 | }; | |
156c2f8b | 9605 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
9606 | |
9607 | int | |
9608 | md_parse_option (c, arg) | |
9609 | int c; | |
9610 | char *arg; | |
9611 | { | |
9612 | switch (c) | |
9613 | { | |
119d663a NC |
9614 | case OPTION_CONSTRUCT_FLOATS: |
9615 | mips_disable_float_construction = 0; | |
9616 | break; | |
bdaaa2e1 | 9617 | |
119d663a NC |
9618 | case OPTION_NO_CONSTRUCT_FLOATS: |
9619 | mips_disable_float_construction = 1; | |
9620 | break; | |
bdaaa2e1 | 9621 | |
252b5132 RH |
9622 | case OPTION_TRAP: |
9623 | mips_trap = 1; | |
9624 | break; | |
9625 | ||
9626 | case OPTION_BREAK: | |
9627 | mips_trap = 0; | |
9628 | break; | |
9629 | ||
9630 | case OPTION_EB: | |
9631 | target_big_endian = 1; | |
9632 | break; | |
9633 | ||
9634 | case OPTION_EL: | |
9635 | target_big_endian = 0; | |
9636 | break; | |
9637 | ||
39c0a331 L |
9638 | case 'n': |
9639 | warn_nops = 1; | |
9640 | break; | |
9641 | ||
252b5132 RH |
9642 | case 'O': |
9643 | if (arg && arg[1] == '0') | |
9644 | mips_optimize = 1; | |
9645 | else | |
9646 | mips_optimize = 2; | |
9647 | break; | |
9648 | ||
9649 | case 'g': | |
9650 | if (arg == NULL) | |
9651 | mips_debug = 2; | |
9652 | else | |
9653 | mips_debug = atoi (arg); | |
9654 | /* When the MIPS assembler sees -g or -g2, it does not do | |
9655 | optimizations which limit full symbolic debugging. We take | |
9656 | that to be equivalent to -O0. */ | |
9657 | if (mips_debug == 2) | |
9658 | mips_optimize = 1; | |
9659 | break; | |
9660 | ||
9661 | case OPTION_MIPS1: | |
e7af610e | 9662 | mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
9663 | break; |
9664 | ||
9665 | case OPTION_MIPS2: | |
e7af610e | 9666 | mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
9667 | break; |
9668 | ||
9669 | case OPTION_MIPS3: | |
e7af610e | 9670 | mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
9671 | break; |
9672 | ||
9673 | case OPTION_MIPS4: | |
e7af610e NC |
9674 | mips_opts.isa = ISA_MIPS4; |
9675 | break; | |
9676 | ||
84ea6cf2 NC |
9677 | case OPTION_MIPS5: |
9678 | mips_opts.isa = ISA_MIPS5; | |
9679 | break; | |
9680 | ||
e7af610e NC |
9681 | case OPTION_MIPS32: |
9682 | mips_opts.isa = ISA_MIPS32; | |
252b5132 RH |
9683 | break; |
9684 | ||
84ea6cf2 NC |
9685 | case OPTION_MIPS64: |
9686 | mips_opts.isa = ISA_MIPS64; | |
9687 | break; | |
9688 | ||
ec68c924 EC |
9689 | case OPTION_MTUNE: |
9690 | case OPTION_MARCH: | |
252b5132 RH |
9691 | case OPTION_MCPU: |
9692 | { | |
ec68c924 EC |
9693 | int cpu = CPU_UNKNOWN; |
9694 | ||
e7af610e | 9695 | /* Identify the processor type. */ |
ec68c924 | 9696 | if (strcasecmp (arg, "default") != 0) |
252b5132 | 9697 | { |
e7af610e | 9698 | const struct mips_cpu_info *ci; |
252b5132 | 9699 | |
e7af610e NC |
9700 | ci = mips_cpu_info_from_name (arg); |
9701 | if (ci == NULL || ci->is_isa) | |
ec68c924 EC |
9702 | { |
9703 | switch (c) | |
9704 | { | |
9705 | case OPTION_MTUNE: | |
9706 | as_fatal (_("invalid architecture -mtune=%s"), arg); | |
9707 | break; | |
9708 | case OPTION_MARCH: | |
9709 | as_fatal (_("invalid architecture -march=%s"), arg); | |
9710 | break; | |
9711 | case OPTION_MCPU: | |
9712 | as_fatal (_("invalid architecture -mcpu=%s"), arg); | |
9713 | break; | |
9714 | } | |
9715 | } | |
e7af610e | 9716 | else |
ec68c924 EC |
9717 | cpu = ci->cpu; |
9718 | } | |
9719 | ||
9720 | switch (c) | |
9721 | { | |
9722 | case OPTION_MTUNE: | |
6dce9e24 TS |
9723 | if (mips_tune != CPU_UNKNOWN && mips_tune != cpu) |
9724 | as_warn(_("A different -mtune= was already specified, is now " | |
9725 | "-mtune=%s"), arg); | |
ec68c924 EC |
9726 | mips_tune = cpu; |
9727 | break; | |
9728 | case OPTION_MARCH: | |
6dce9e24 TS |
9729 | if (mips_arch != CPU_UNKNOWN && mips_arch != cpu) |
9730 | as_warn(_("A different -march= was already specified, is now " | |
9731 | "-march=%s"), arg); | |
ec68c924 EC |
9732 | mips_arch = cpu; |
9733 | break; | |
9734 | case OPTION_MCPU: | |
6dce9e24 TS |
9735 | if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu) |
9736 | as_warn(_("A different -mcpu= was already specified, is now " | |
9737 | "-mcpu=%s"), arg); | |
ec68c924 | 9738 | mips_cpu = cpu; |
252b5132 RH |
9739 | } |
9740 | } | |
9741 | break; | |
9742 | ||
9743 | case OPTION_M4650: | |
6dce9e24 TS |
9744 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650) |
9745 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650)) | |
9746 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9747 | "is now -m4650")); | |
ec68c924 EC |
9748 | mips_arch = CPU_R4650; |
9749 | mips_tune = CPU_R4650; | |
252b5132 RH |
9750 | break; |
9751 | ||
9752 | case OPTION_NO_M4650: | |
9753 | break; | |
9754 | ||
9755 | case OPTION_M4010: | |
6dce9e24 TS |
9756 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010) |
9757 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010)) | |
9758 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9759 | "is now -m4010")); | |
ec68c924 EC |
9760 | mips_arch = CPU_R4010; |
9761 | mips_tune = CPU_R4010; | |
252b5132 RH |
9762 | break; |
9763 | ||
9764 | case OPTION_NO_M4010: | |
9765 | break; | |
9766 | ||
9767 | case OPTION_M4100: | |
6dce9e24 TS |
9768 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100) |
9769 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100)) | |
9770 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9771 | "is now -m4100")); | |
ec68c924 EC |
9772 | mips_arch = CPU_VR4100; |
9773 | mips_tune = CPU_VR4100; | |
252b5132 RH |
9774 | break; |
9775 | ||
9776 | case OPTION_NO_M4100: | |
9777 | break; | |
9778 | ||
252b5132 | 9779 | case OPTION_M3900: |
6dce9e24 TS |
9780 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900) |
9781 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900)) | |
9782 | as_warn(_("A different -march= or -mtune= was already specified, " | |
9783 | "is now -m3900")); | |
ec68c924 EC |
9784 | mips_arch = CPU_R3900; |
9785 | mips_tune = CPU_R3900; | |
252b5132 | 9786 | break; |
bdaaa2e1 | 9787 | |
252b5132 RH |
9788 | case OPTION_NO_M3900: |
9789 | break; | |
9790 | ||
9791 | case OPTION_MIPS16: | |
9792 | mips_opts.mips16 = 1; | |
9793 | mips_no_prev_insn (false); | |
9794 | break; | |
9795 | ||
9796 | case OPTION_NO_MIPS16: | |
9797 | mips_opts.mips16 = 0; | |
9798 | mips_no_prev_insn (false); | |
9799 | break; | |
9800 | ||
9801 | case OPTION_MEMBEDDED_PIC: | |
9802 | mips_pic = EMBEDDED_PIC; | |
9803 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
9804 | { | |
9805 | as_bad (_("-G may not be used with embedded PIC code")); | |
9806 | return 0; | |
9807 | } | |
9808 | g_switch_value = 0x7fffffff; | |
9809 | break; | |
9810 | ||
0f074f60 | 9811 | #ifdef OBJ_ELF |
252b5132 RH |
9812 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9813 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9814 | intended to be compatible with Irix 5. */ | |
9815 | case OPTION_CALL_SHARED: | |
9816 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9817 | { | |
9818 | as_bad (_("-call_shared is supported only for ELF format")); | |
9819 | return 0; | |
9820 | } | |
9821 | mips_pic = SVR4_PIC; | |
9822 | if (g_switch_seen && g_switch_value != 0) | |
9823 | { | |
9824 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
9825 | return 0; | |
9826 | } | |
9827 | g_switch_value = 0; | |
9828 | break; | |
9829 | ||
9830 | case OPTION_NON_SHARED: | |
9831 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9832 | { | |
9833 | as_bad (_("-non_shared is supported only for ELF format")); | |
9834 | return 0; | |
9835 | } | |
9836 | mips_pic = NO_PIC; | |
9837 | break; | |
9838 | ||
9839 | /* The -xgot option tells the assembler to use 32 offsets when | |
9840 | accessing the got in SVR4_PIC mode. It is for Irix | |
9841 | compatibility. */ | |
9842 | case OPTION_XGOT: | |
9843 | mips_big_got = 1; | |
9844 | break; | |
0f074f60 | 9845 | #endif /* OBJ_ELF */ |
252b5132 RH |
9846 | |
9847 | case 'G': | |
9848 | if (! USE_GLOBAL_POINTER_OPT) | |
9849 | { | |
9850 | as_bad (_("-G is not supported for this configuration")); | |
9851 | return 0; | |
9852 | } | |
9853 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
9854 | { | |
9855 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
9856 | return 0; | |
9857 | } | |
9858 | else | |
9859 | g_switch_value = atoi (arg); | |
9860 | g_switch_seen = 1; | |
9861 | break; | |
9862 | ||
0f074f60 | 9863 | #ifdef OBJ_ELF |
34ba82a8 TS |
9864 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
9865 | and -mabi=64. */ | |
252b5132 | 9866 | case OPTION_32: |
34ba82a8 TS |
9867 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9868 | { | |
9869 | as_bad (_("-32 is supported for ELF format only")); | |
9870 | return 0; | |
9871 | } | |
a325df1d | 9872 | mips_opts.abi = O32_ABI; |
252b5132 RH |
9873 | break; |
9874 | ||
e013f690 | 9875 | case OPTION_N32: |
34ba82a8 TS |
9876 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9877 | { | |
9878 | as_bad (_("-n32 is supported for ELF format only")); | |
9879 | return 0; | |
9880 | } | |
a325df1d | 9881 | mips_opts.abi = N32_ABI; |
e013f690 | 9882 | break; |
252b5132 | 9883 | |
e013f690 | 9884 | case OPTION_64: |
34ba82a8 TS |
9885 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9886 | { | |
9887 | as_bad (_("-64 is supported for ELF format only")); | |
9888 | return 0; | |
9889 | } | |
a325df1d | 9890 | mips_opts.abi = N64_ABI; |
e013f690 TS |
9891 | if (! support_64bit_objects()) |
9892 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 9893 | break; |
ae948b86 | 9894 | #endif /* OBJ_ELF */ |
252b5132 | 9895 | |
c97ef257 | 9896 | case OPTION_GP32: |
a325df1d TS |
9897 | file_mips_gp32 = 1; |
9898 | if (mips_opts.abi != O32_ABI) | |
9899 | mips_opts.abi = NO_ABI; | |
c97ef257 AH |
9900 | break; |
9901 | ||
9902 | case OPTION_GP64: | |
a325df1d TS |
9903 | file_mips_gp32 = 0; |
9904 | if (mips_opts.abi == O32_ABI) | |
9905 | mips_opts.abi = NO_ABI; | |
c97ef257 | 9906 | break; |
252b5132 | 9907 | |
ca4e0257 | 9908 | case OPTION_FP32: |
a325df1d TS |
9909 | file_mips_fp32 = 1; |
9910 | if (mips_opts.abi != O32_ABI) | |
9911 | mips_opts.abi = NO_ABI; | |
ca4e0257 RS |
9912 | break; |
9913 | ||
ae948b86 | 9914 | #ifdef OBJ_ELF |
252b5132 | 9915 | case OPTION_MABI: |
34ba82a8 TS |
9916 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9917 | { | |
9918 | as_bad (_("-mabi is supported for ELF format only")); | |
9919 | return 0; | |
9920 | } | |
e013f690 | 9921 | if (strcmp (arg, "32") == 0) |
a325df1d | 9922 | mips_opts.abi = O32_ABI; |
e013f690 | 9923 | else if (strcmp (arg, "o64") == 0) |
a325df1d | 9924 | mips_opts.abi = O64_ABI; |
e013f690 | 9925 | else if (strcmp (arg, "n32") == 0) |
a325df1d | 9926 | mips_opts.abi = N32_ABI; |
e013f690 TS |
9927 | else if (strcmp (arg, "64") == 0) |
9928 | { | |
a325df1d | 9929 | mips_opts.abi = N64_ABI; |
e013f690 TS |
9930 | if (! support_64bit_objects()) |
9931 | as_fatal (_("No compiled in support for 64 bit object file " | |
9932 | "format")); | |
9933 | } | |
9934 | else if (strcmp (arg, "eabi") == 0) | |
a325df1d | 9935 | mips_opts.abi = EABI_ABI; |
e013f690 | 9936 | else |
a325df1d | 9937 | mips_opts.abi = NO_ABI; |
252b5132 | 9938 | break; |
e013f690 | 9939 | #endif /* OBJ_ELF */ |
252b5132 | 9940 | |
6b76fefe CM |
9941 | case OPTION_M7000_HILO_FIX: |
9942 | mips_7000_hilo_fix = true; | |
9943 | break; | |
9944 | ||
9945 | case OPTION_NO_M7000_HILO_FIX: | |
9946 | mips_7000_hilo_fix = false; | |
9947 | break; | |
9948 | ||
252b5132 RH |
9949 | default: |
9950 | return 0; | |
9951 | } | |
9952 | ||
9953 | return 1; | |
9954 | } | |
9955 | ||
252b5132 RH |
9956 | static void |
9957 | show (stream, string, col_p, first_p) | |
9958 | FILE *stream; | |
9959 | char *string; | |
9960 | int *col_p; | |
9961 | int *first_p; | |
9962 | { | |
9963 | if (*first_p) | |
9964 | { | |
9965 | fprintf (stream, "%24s", ""); | |
9966 | *col_p = 24; | |
9967 | } | |
9968 | else | |
9969 | { | |
9970 | fprintf (stream, ", "); | |
9971 | *col_p += 2; | |
9972 | } | |
9973 | ||
9974 | if (*col_p + strlen (string) > 72) | |
9975 | { | |
9976 | fprintf (stream, "\n%24s", ""); | |
9977 | *col_p = 24; | |
9978 | } | |
9979 | ||
9980 | fprintf (stream, "%s", string); | |
9981 | *col_p += strlen (string); | |
9982 | ||
9983 | *first_p = 0; | |
9984 | } | |
9985 | ||
252b5132 RH |
9986 | void |
9987 | md_show_usage (stream) | |
9988 | FILE *stream; | |
9989 | { | |
9990 | int column, first; | |
9991 | ||
beae10d5 | 9992 | fprintf (stream, _("\ |
252b5132 RH |
9993 | MIPS options:\n\ |
9994 | -membedded-pic generate embedded position independent code\n\ | |
9995 | -EB generate big endian output\n\ | |
9996 | -EL generate little endian output\n\ | |
9a41af64 | 9997 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ |
252b5132 RH |
9998 | -G NUM allow referencing objects up to NUM bytes\n\ |
9999 | implicitly with the gp register [default 8]\n")); | |
beae10d5 | 10000 | fprintf (stream, _("\ |
252b5132 RH |
10001 | -mips1 generate MIPS ISA I instructions\n\ |
10002 | -mips2 generate MIPS ISA II instructions\n\ | |
10003 | -mips3 generate MIPS ISA III instructions\n\ | |
10004 | -mips4 generate MIPS ISA IV instructions\n\ | |
84ea6cf2 | 10005 | -mips5 generate MIPS ISA V instructions\n\ |
e7af610e | 10006 | -mips32 generate MIPS32 ISA instructions\n\ |
84ea6cf2 | 10007 | -mips64 generate MIPS64 ISA instructions\n\ |
ec68c924 | 10008 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
252b5132 RH |
10009 | |
10010 | first = 1; | |
10011 | ||
10012 | show (stream, "2000", &column, &first); | |
10013 | show (stream, "3000", &column, &first); | |
10014 | show (stream, "3900", &column, &first); | |
10015 | show (stream, "4000", &column, &first); | |
10016 | show (stream, "4010", &column, &first); | |
10017 | show (stream, "4100", &column, &first); | |
10018 | show (stream, "4111", &column, &first); | |
10019 | show (stream, "4300", &column, &first); | |
10020 | show (stream, "4400", &column, &first); | |
10021 | show (stream, "4600", &column, &first); | |
10022 | show (stream, "4650", &column, &first); | |
10023 | show (stream, "5000", &column, &first); | |
18ae5d72 EC |
10024 | show (stream, "5200", &column, &first); |
10025 | show (stream, "5230", &column, &first); | |
10026 | show (stream, "5231", &column, &first); | |
10027 | show (stream, "5261", &column, &first); | |
10028 | show (stream, "5721", &column, &first); | |
252b5132 RH |
10029 | show (stream, "6000", &column, &first); |
10030 | show (stream, "8000", &column, &first); | |
10031 | show (stream, "10000", &column, &first); | |
d1cf510e | 10032 | show (stream, "12000", &column, &first); |
2e4acd24 | 10033 | show (stream, "sb1", &column, &first); |
252b5132 RH |
10034 | fputc ('\n', stream); |
10035 | ||
10036 | fprintf (stream, _("\ | |
ec68c924 | 10037 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
252b5132 RH |
10038 | -no-mCPU don't generate code specific to CPU.\n\ |
10039 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
10040 | ||
10041 | first = 1; | |
10042 | ||
10043 | show (stream, "3900", &column, &first); | |
10044 | show (stream, "4010", &column, &first); | |
10045 | show (stream, "4100", &column, &first); | |
10046 | show (stream, "4650", &column, &first); | |
10047 | fputc ('\n', stream); | |
10048 | ||
beae10d5 | 10049 | fprintf (stream, _("\ |
252b5132 RH |
10050 | -mips16 generate mips16 instructions\n\ |
10051 | -no-mips16 do not generate mips16 instructions\n")); | |
beae10d5 | 10052 | fprintf (stream, _("\ |
ca4e0257 RS |
10053 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
10054 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
252b5132 RH |
10055 | -O0 remove unneeded NOPs, do not swap branches\n\ |
10056 | -O remove unneeded NOPs and swap branches\n\ | |
63486801 | 10057 | -n warn about NOPs generated from macros\n\ |
119d663a | 10058 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
252b5132 RH |
10059 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
10060 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
10061 | #ifdef OBJ_ELF | |
beae10d5 | 10062 | fprintf (stream, _("\ |
252b5132 RH |
10063 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
10064 | -non_shared do not generate position independent code\n\ | |
10065 | -xgot assume a 32 bit GOT\n\ | |
34ba82a8 TS |
10066 | -mabi=ABI create ABI conformant object file for:\n")); |
10067 | ||
10068 | first = 1; | |
10069 | ||
10070 | show (stream, "32", &column, &first); | |
10071 | show (stream, "o64", &column, &first); | |
10072 | show (stream, "n32", &column, &first); | |
10073 | show (stream, "64", &column, &first); | |
10074 | show (stream, "eabi", &column, &first); | |
10075 | ||
10076 | fputc ('\n', stream); | |
10077 | ||
10078 | fprintf (stream, _("\ | |
e013f690 TS |
10079 | -32 create o32 ABI object file (default)\n\ |
10080 | -n32 create n32 ABI object file\n\ | |
10081 | -64 create 64 ABI object file\n")); | |
252b5132 RH |
10082 | #endif |
10083 | } | |
10084 | \f | |
10085 | void | |
10086 | mips_init_after_args () | |
10087 | { | |
10088 | /* initialize opcodes */ | |
10089 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10090 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10091 | } |
10092 | ||
10093 | long | |
10094 | md_pcrel_from (fixP) | |
10095 | fixS *fixP; | |
10096 | { | |
10097 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
10098 | && fixP->fx_addsy != (symbolS *) NULL | |
10099 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
10100 | { | |
6478892d TS |
10101 | /* This makes a branch to an undefined symbol be a branch to the |
10102 | current location. */ | |
cb56d3d3 | 10103 | if (mips_pic == EMBEDDED_PIC) |
6478892d | 10104 | return 4; |
cb56d3d3 | 10105 | else |
6478892d | 10106 | return 1; |
252b5132 RH |
10107 | } |
10108 | ||
10109 | /* return the address of the delay slot */ | |
10110 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
10111 | } | |
10112 | ||
252b5132 RH |
10113 | /* This is called before the symbol table is processed. In order to |
10114 | work with gcc when using mips-tfile, we must keep all local labels. | |
10115 | However, in other cases, we want to discard them. If we were | |
10116 | called with -g, but we didn't see any debugging information, it may | |
10117 | mean that gcc is smuggling debugging information through to | |
10118 | mips-tfile, in which case we must generate all local labels. */ | |
10119 | ||
10120 | void | |
10121 | mips_frob_file_before_adjust () | |
10122 | { | |
10123 | #ifndef NO_ECOFF_DEBUGGING | |
10124 | if (ECOFF_DEBUGGING | |
10125 | && mips_debug != 0 | |
10126 | && ! ecoff_debugging_seen) | |
10127 | flag_keep_locals = 1; | |
10128 | #endif | |
10129 | } | |
10130 | ||
10131 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10132 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10133 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10134 | explicit use of the %hi modifier. */ | |
10135 | ||
10136 | void | |
10137 | mips_frob_file () | |
10138 | { | |
10139 | struct mips_hi_fixup *l; | |
10140 | ||
10141 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10142 | { | |
10143 | segment_info_type *seginfo; | |
10144 | int pass; | |
10145 | ||
10146 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
10147 | ||
10148 | /* Check quickly whether the next fixup happens to be a matching | |
10149 | %lo. */ | |
10150 | if (l->fixp->fx_next != NULL | |
10151 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
10152 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
10153 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
10154 | continue; | |
10155 | ||
10156 | /* Look through the fixups for this segment for a matching %lo. | |
10157 | When we find one, move the %hi just in front of it. We do | |
10158 | this in two passes. In the first pass, we try to find a | |
10159 | unique %lo. In the second pass, we permit multiple %hi | |
10160 | relocs for a single %lo (this is a GNU extension). */ | |
10161 | seginfo = seg_info (l->seg); | |
10162 | for (pass = 0; pass < 2; pass++) | |
10163 | { | |
10164 | fixS *f, *prev; | |
10165 | ||
10166 | prev = NULL; | |
10167 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10168 | { | |
10169 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10170 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10171 | && f->fx_addsy == l->fixp->fx_addsy | |
10172 | && f->fx_offset == l->fixp->fx_offset | |
10173 | && (pass == 1 | |
10174 | || prev == NULL | |
10175 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
10176 | || prev->fx_addsy != f->fx_addsy | |
10177 | || prev->fx_offset != f->fx_offset)) | |
10178 | { | |
10179 | fixS **pf; | |
10180 | ||
10181 | /* Move l->fixp before f. */ | |
10182 | for (pf = &seginfo->fix_root; | |
10183 | *pf != l->fixp; | |
10184 | pf = &(*pf)->fx_next) | |
10185 | assert (*pf != NULL); | |
10186 | ||
10187 | *pf = l->fixp->fx_next; | |
10188 | ||
10189 | l->fixp->fx_next = f; | |
10190 | if (prev == NULL) | |
10191 | seginfo->fix_root = l->fixp; | |
10192 | else | |
10193 | prev->fx_next = l->fixp; | |
10194 | ||
10195 | break; | |
10196 | } | |
10197 | ||
10198 | prev = f; | |
10199 | } | |
10200 | ||
10201 | if (f != NULL) | |
10202 | break; | |
10203 | ||
10204 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10205 | can leave a %hi without a %lo. */ | |
10206 | if (pass == 1) | |
10207 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10208 | _("Unmatched %%hi reloc")); | |
10209 | #endif | |
10210 | } | |
10211 | } | |
10212 | } | |
10213 | ||
10214 | /* When generating embedded PIC code we need to use a special | |
10215 | relocation to represent the difference of two symbols in the .text | |
10216 | section (switch tables use a difference of this sort). See | |
10217 | include/coff/mips.h for details. This macro checks whether this | |
10218 | fixup requires the special reloc. */ | |
10219 | #define SWITCH_TABLE(fixp) \ | |
10220 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10221 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10222 | && (fixp)->fx_addsy != NULL \ |
10223 | && (fixp)->fx_subsy != NULL \ | |
10224 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10225 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10226 | ||
10227 | /* When generating embedded PIC code we must keep all PC relative | |
10228 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
10229 | to keep relocations for switch table entries. |
10230 | ||
10231 | We may have combined relocations without symbols in the N32/N64 ABI. | |
10232 | We have to prevent gas from dropping them. */ | |
252b5132 | 10233 | |
252b5132 RH |
10234 | int |
10235 | mips_force_relocation (fixp) | |
10236 | fixS *fixp; | |
10237 | { | |
10238 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
10239 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10240 | return 1; | |
10241 | ||
f6688943 TS |
10242 | if (HAVE_NEWABI |
10243 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10244 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10245 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10246 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10247 | return 1; | |
10248 | ||
252b5132 RH |
10249 | return (mips_pic == EMBEDDED_PIC |
10250 | && (fixp->fx_pcrel | |
10251 | || SWITCH_TABLE (fixp) | |
10252 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10253 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
10254 | } | |
10255 | ||
add55e1f RS |
10256 | #ifdef OBJ_ELF |
10257 | static int | |
10258 | mips_need_elf_addend_fixup (fixP) | |
10259 | fixS *fixP; | |
10260 | { | |
10261 | return (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 | |
10262 | || ((S_IS_WEAK (fixP->fx_addsy) | |
10263 | || S_IS_EXTERN (fixP->fx_addsy)) | |
10264 | && !S_IS_COMMON (fixP->fx_addsy)) | |
10265 | || (symbol_used_in_reloc_p (fixP->fx_addsy) | |
10266 | && (((bfd_get_section_flags (stdoutput, | |
10267 | S_GET_SEGMENT (fixP->fx_addsy)) | |
10268 | & SEC_LINK_ONCE) != 0) | |
10269 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
10270 | ".gnu.linkonce", | |
10271 | sizeof (".gnu.linkonce") - 1)))); | |
10272 | } | |
10273 | #endif | |
10274 | ||
252b5132 RH |
10275 | /* Apply a fixup to the object file. */ |
10276 | ||
94f592af NC |
10277 | void |
10278 | md_apply_fix3 (fixP, valP, seg) | |
252b5132 | 10279 | fixS *fixP; |
94f592af NC |
10280 | valueT * valP; |
10281 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 RH |
10282 | { |
10283 | unsigned char *buf; | |
98aa84af AM |
10284 | long insn; |
10285 | valueT value; | |
252b5132 RH |
10286 | |
10287 | assert (fixP->fx_size == 4 | |
10288 | || fixP->fx_r_type == BFD_RELOC_16 | |
f6688943 TS |
10289 | || fixP->fx_r_type == BFD_RELOC_32 |
10290 | || fixP->fx_r_type == BFD_RELOC_MIPS_JMP | |
10291 | || fixP->fx_r_type == BFD_RELOC_HI16_S | |
10292 | || fixP->fx_r_type == BFD_RELOC_LO16 | |
10293 | || fixP->fx_r_type == BFD_RELOC_GPREL16 | |
76b3015f | 10294 | || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL |
f6688943 | 10295 | || fixP->fx_r_type == BFD_RELOC_GPREL32 |
252b5132 | 10296 | || fixP->fx_r_type == BFD_RELOC_64 |
f6688943 TS |
10297 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10298 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10299 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST | |
10300 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER | |
10301 | || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP | |
10302 | || fixP->fx_r_type == BFD_RELOC_MIPS_REL16 | |
10303 | || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT | |
252b5132 RH |
10304 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
10305 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
10306 | ||
94f592af | 10307 | value = * valP; |
252b5132 RH |
10308 | |
10309 | /* If we aren't adjusting this fixup to be against the section | |
10310 | symbol, we need to adjust the value. */ | |
10311 | #ifdef OBJ_ELF | |
10312 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 10313 | { |
add55e1f | 10314 | if (mips_need_elf_addend_fixup (fixP)) |
98aa84af AM |
10315 | { |
10316 | valueT symval = S_GET_VALUE (fixP->fx_addsy); | |
94f592af | 10317 | |
98aa84af | 10318 | value -= symval; |
add55e1f | 10319 | if (value != 0 && ! fixP->fx_pcrel) |
98aa84af AM |
10320 | { |
10321 | /* In this case, the bfd_install_relocation routine will | |
10322 | incorrectly add the symbol value back in. We just want | |
7461da6e | 10323 | the addend to appear in the object file. */ |
98aa84af | 10324 | value -= symval; |
7461da6e RS |
10325 | |
10326 | /* Make sure the addend is still non-zero. If it became zero | |
10327 | after the last operation, set it to a spurious value and | |
10328 | subtract the same value from the object file's contents. */ | |
10329 | if (value == 0) | |
10330 | { | |
10331 | value = 8; | |
10332 | ||
10333 | /* The in-place addends for LO16 relocations are signed; | |
10334 | leave the matching HI16 in-place addends as zero. */ | |
10335 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
10336 | { | |
10337 | reloc_howto_type *howto; | |
10338 | bfd_vma contents, mask, field; | |
10339 | ||
10340 | howto = bfd_reloc_type_lookup (stdoutput, | |
10341 | fixP->fx_r_type); | |
10342 | ||
10343 | contents = bfd_get_bits (fixP->fx_frag->fr_literal | |
10344 | + fixP->fx_where, | |
10345 | fixP->fx_size * 8, | |
10346 | target_big_endian); | |
10347 | ||
10348 | /* MASK has bits set where the relocation should go. | |
10349 | FIELD is -value, shifted into the appropriate place | |
10350 | for this relocation. */ | |
10351 | mask = 1 << (howto->bitsize - 1); | |
10352 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
10353 | field = (-value >> howto->rightshift) << howto->bitpos; | |
10354 | ||
10355 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
10356 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
10357 | fixP->fx_size * 8, | |
10358 | target_big_endian); | |
10359 | } | |
10360 | } | |
98aa84af AM |
10361 | } |
10362 | } | |
252b5132 | 10363 | |
bb2d6cd7 GK |
10364 | /* This code was generated using trial and error and so is |
10365 | fragile and not trustworthy. If you change it, you should | |
10366 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
10367 | they still pass. */ | |
10368 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
10369 | { | |
10370 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10371 | ||
10372 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
10373 | This gives the right results, but it can't possibly | |
10374 | be the way things are supposed to work. */ | |
cb56d3d3 TS |
10375 | if ((fixP->fx_r_type != BFD_RELOC_16_PCREL |
10376 | && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2) | |
bb2d6cd7 GK |
10377 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
10378 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10379 | } | |
10380 | } | |
10381 | #endif | |
252b5132 | 10382 | |
94f592af | 10383 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */ |
252b5132 RH |
10384 | |
10385 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
10386 | fixP->fx_done = 1; | |
10387 | ||
10388 | switch (fixP->fx_r_type) | |
10389 | { | |
10390 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
10391 | case BFD_RELOC_MIPS_SHIFT5: |
10392 | case BFD_RELOC_MIPS_SHIFT6: | |
10393 | case BFD_RELOC_MIPS_GOT_DISP: | |
10394 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10395 | case BFD_RELOC_MIPS_GOT_OFST: | |
10396 | case BFD_RELOC_MIPS_SUB: | |
10397 | case BFD_RELOC_MIPS_INSERT_A: | |
10398 | case BFD_RELOC_MIPS_INSERT_B: | |
10399 | case BFD_RELOC_MIPS_DELETE: | |
10400 | case BFD_RELOC_MIPS_HIGHEST: | |
10401 | case BFD_RELOC_MIPS_HIGHER: | |
10402 | case BFD_RELOC_MIPS_SCN_DISP: | |
10403 | case BFD_RELOC_MIPS_REL16: | |
10404 | case BFD_RELOC_MIPS_RELGOT: | |
10405 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10406 | case BFD_RELOC_HI16: |
10407 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10408 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10409 | case BFD_RELOC_MIPS_LITERAL: |
10410 | case BFD_RELOC_MIPS_CALL16: | |
10411 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10412 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10413 | case BFD_RELOC_MIPS_GOT_HI16: |
10414 | case BFD_RELOC_MIPS_GOT_LO16: | |
10415 | case BFD_RELOC_MIPS_CALL_HI16: | |
10416 | case BFD_RELOC_MIPS_CALL_LO16: | |
10417 | case BFD_RELOC_MIPS16_GPREL: | |
10418 | if (fixP->fx_pcrel) | |
10419 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10420 | _("Invalid PC relative reloc")); | |
10421 | /* Nothing needed to do. The value comes from the reloc entry */ | |
10422 | break; | |
10423 | ||
10424 | case BFD_RELOC_MIPS16_JMP: | |
10425 | /* We currently always generate a reloc against a symbol, which | |
10426 | means that we don't want an addend even if the symbol is | |
10427 | defined. */ | |
10428 | fixP->fx_addnumber = 0; | |
10429 | break; | |
10430 | ||
10431 | case BFD_RELOC_PCREL_HI16_S: | |
10432 | /* The addend for this is tricky if it is internal, so we just | |
10433 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10434 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10435 | && !fixP->fx_done |
10436 | && value != 0) | |
10437 | break; | |
10438 | if (fixP->fx_addsy | |
10439 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
10440 | { |
10441 | /* For an external symbol adjust by the address to make it | |
10442 | pcrel_offset. We use the address of the RELLO reloc | |
10443 | which follows this one. */ | |
10444 | value += (fixP->fx_next->fx_frag->fr_address | |
10445 | + fixP->fx_next->fx_where); | |
10446 | } | |
e7d556df | 10447 | value = ((value + 0x8000) >> 16) & 0xffff; |
252b5132 RH |
10448 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
10449 | if (target_big_endian) | |
10450 | buf += 2; | |
10451 | md_number_to_chars (buf, value, 2); | |
10452 | break; | |
10453 | ||
10454 | case BFD_RELOC_PCREL_LO16: | |
10455 | /* The addend for this is tricky if it is internal, so we just | |
10456 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10457 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10458 | && !fixP->fx_done |
10459 | && value != 0) | |
10460 | break; | |
10461 | if (fixP->fx_addsy | |
10462 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
10463 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
10464 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
10465 | if (target_big_endian) | |
10466 | buf += 2; | |
10467 | md_number_to_chars (buf, value, 2); | |
10468 | break; | |
10469 | ||
10470 | case BFD_RELOC_64: | |
10471 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10472 | extended value if we are only 32 bits. */ | |
10473 | if (fixP->fx_done | |
10474 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10475 | { | |
10476 | if (8 <= sizeof (valueT)) | |
10477 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10478 | value, 8); | |
10479 | else | |
10480 | { | |
10481 | long w1, w2; | |
10482 | long hiv; | |
10483 | ||
10484 | w1 = w2 = fixP->fx_where; | |
10485 | if (target_big_endian) | |
10486 | w1 += 4; | |
10487 | else | |
10488 | w2 += 4; | |
10489 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
10490 | if ((value & 0x80000000) != 0) | |
10491 | hiv = 0xffffffff; | |
10492 | else | |
10493 | hiv = 0; | |
10494 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
10495 | } | |
10496 | } | |
10497 | break; | |
10498 | ||
056350c6 | 10499 | case BFD_RELOC_RVA: |
252b5132 RH |
10500 | case BFD_RELOC_32: |
10501 | /* If we are deleting this reloc entry, we must fill in the | |
10502 | value now. This can happen if we have a .word which is not | |
10503 | resolved when it appears but is later defined. We also need | |
10504 | to fill in the value if this is an embedded PIC switch table | |
10505 | entry. */ | |
10506 | if (fixP->fx_done | |
10507 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10508 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10509 | value, 4); | |
10510 | break; | |
10511 | ||
10512 | case BFD_RELOC_16: | |
10513 | /* If we are deleting this reloc entry, we must fill in the | |
10514 | value now. */ | |
10515 | assert (fixP->fx_size == 2); | |
10516 | if (fixP->fx_done) | |
10517 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10518 | value, 2); | |
10519 | break; | |
10520 | ||
10521 | case BFD_RELOC_LO16: | |
10522 | /* When handling an embedded PIC switch statement, we can wind | |
10523 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10524 | if (fixP->fx_done) | |
10525 | { | |
98aa84af | 10526 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
10527 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10528 | _("relocation overflow")); | |
10529 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
10530 | if (target_big_endian) | |
10531 | buf += 2; | |
10532 | md_number_to_chars (buf, value, 2); | |
10533 | } | |
10534 | break; | |
10535 | ||
10536 | case BFD_RELOC_16_PCREL_S2: | |
cb56d3d3 TS |
10537 | if ((value & 0x3) != 0) |
10538 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10539 | _("Branch to odd address (%lx)"), (long) value); | |
10540 | ||
10541 | /* Fall through. */ | |
10542 | ||
10543 | case BFD_RELOC_16_PCREL: | |
252b5132 RH |
10544 | /* |
10545 | * We need to save the bits in the instruction since fixup_segment() | |
10546 | * might be deleting the relocation entry (i.e., a branch within | |
10547 | * the current segment). | |
10548 | */ | |
bb2d6cd7 GK |
10549 | if (!fixP->fx_done && value != 0) |
10550 | break; | |
10551 | /* If 'value' is zero, the remaining reloc code won't actually | |
10552 | do the store, so it must be done here. This is probably | |
10553 | a bug somewhere. */ | |
10554 | if (!fixP->fx_done) | |
10555 | value -= fixP->fx_frag->fr_address + fixP->fx_where; | |
bdaaa2e1 | 10556 | |
98aa84af | 10557 | value = (offsetT) value >> 2; |
252b5132 RH |
10558 | |
10559 | /* update old instruction data */ | |
10560 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
10561 | if (target_big_endian) | |
10562 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
10563 | else | |
10564 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
10565 | ||
98aa84af | 10566 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
10567 | insn |= value & 0xffff; |
10568 | else | |
10569 | { | |
10570 | /* The branch offset is too large. If this is an | |
10571 | unconditional branch, and we are not generating PIC code, | |
10572 | we can convert it to an absolute jump instruction. */ | |
10573 | if (mips_pic == NO_PIC | |
10574 | && fixP->fx_done | |
10575 | && fixP->fx_frag->fr_address >= text_section->vma | |
10576 | && (fixP->fx_frag->fr_address | |
10577 | < text_section->vma + text_section->_raw_size) | |
10578 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
10579 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
10580 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
10581 | { | |
10582 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
10583 | insn = 0x0c000000; /* jal */ | |
10584 | else | |
10585 | insn = 0x08000000; /* j */ | |
10586 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
10587 | fixP->fx_done = 0; | |
10588 | fixP->fx_addsy = section_symbol (text_section); | |
10589 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
10590 | } | |
10591 | else | |
10592 | { | |
10593 | /* FIXME. It would be possible in principle to handle | |
10594 | conditional branches which overflow. They could be | |
10595 | transformed into a branch around a jump. This would | |
10596 | require setting up variant frags for each different | |
10597 | branch type. The native MIPS assembler attempts to | |
10598 | handle these cases, but it appears to do it | |
10599 | incorrectly. */ | |
10600 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10601 | _("Branch out of range")); | |
10602 | } | |
10603 | } | |
10604 | ||
10605 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
10606 | break; | |
10607 | ||
10608 | case BFD_RELOC_VTABLE_INHERIT: | |
10609 | fixP->fx_done = 0; | |
10610 | if (fixP->fx_addsy | |
10611 | && !S_IS_DEFINED (fixP->fx_addsy) | |
10612 | && !S_IS_WEAK (fixP->fx_addsy)) | |
10613 | S_SET_WEAK (fixP->fx_addsy); | |
10614 | break; | |
10615 | ||
10616 | case BFD_RELOC_VTABLE_ENTRY: | |
10617 | fixP->fx_done = 0; | |
10618 | break; | |
10619 | ||
10620 | default: | |
10621 | internalError (); | |
10622 | } | |
252b5132 RH |
10623 | } |
10624 | ||
10625 | #if 0 | |
10626 | void | |
10627 | printInsn (oc) | |
10628 | unsigned long oc; | |
10629 | { | |
10630 | const struct mips_opcode *p; | |
10631 | int treg, sreg, dreg, shamt; | |
10632 | short imm; | |
10633 | const char *args; | |
10634 | int i; | |
10635 | ||
10636 | for (i = 0; i < NUMOPCODES; ++i) | |
10637 | { | |
10638 | p = &mips_opcodes[i]; | |
10639 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
10640 | { | |
10641 | printf ("%08lx %s\t", oc, p->name); | |
10642 | treg = (oc >> 16) & 0x1f; | |
10643 | sreg = (oc >> 21) & 0x1f; | |
10644 | dreg = (oc >> 11) & 0x1f; | |
10645 | shamt = (oc >> 6) & 0x1f; | |
10646 | imm = oc; | |
10647 | for (args = p->args;; ++args) | |
10648 | { | |
10649 | switch (*args) | |
10650 | { | |
10651 | case '\0': | |
10652 | printf ("\n"); | |
10653 | break; | |
10654 | ||
10655 | case ',': | |
10656 | case '(': | |
10657 | case ')': | |
10658 | printf ("%c", *args); | |
10659 | continue; | |
10660 | ||
10661 | case 'r': | |
10662 | assert (treg == sreg); | |
10663 | printf ("$%d,$%d", treg, sreg); | |
10664 | continue; | |
10665 | ||
10666 | case 'd': | |
10667 | case 'G': | |
10668 | printf ("$%d", dreg); | |
10669 | continue; | |
10670 | ||
10671 | case 't': | |
10672 | case 'E': | |
10673 | printf ("$%d", treg); | |
10674 | continue; | |
10675 | ||
10676 | case 'k': | |
10677 | printf ("0x%x", treg); | |
10678 | continue; | |
10679 | ||
10680 | case 'b': | |
10681 | case 's': | |
10682 | printf ("$%d", sreg); | |
10683 | continue; | |
10684 | ||
10685 | case 'a': | |
10686 | printf ("0x%08lx", oc & 0x1ffffff); | |
10687 | continue; | |
10688 | ||
10689 | case 'i': | |
10690 | case 'j': | |
10691 | case 'o': | |
10692 | case 'u': | |
10693 | printf ("%d", imm); | |
10694 | continue; | |
10695 | ||
10696 | case '<': | |
10697 | case '>': | |
10698 | printf ("$%d", shamt); | |
10699 | continue; | |
10700 | ||
10701 | default: | |
10702 | internalError (); | |
10703 | } | |
10704 | break; | |
10705 | } | |
10706 | return; | |
10707 | } | |
10708 | } | |
10709 | printf (_("%08lx UNDEFINED\n"), oc); | |
10710 | } | |
10711 | #endif | |
10712 | ||
10713 | static symbolS * | |
10714 | get_symbol () | |
10715 | { | |
10716 | int c; | |
10717 | char *name; | |
10718 | symbolS *p; | |
10719 | ||
10720 | name = input_line_pointer; | |
10721 | c = get_symbol_end (); | |
10722 | p = (symbolS *) symbol_find_or_make (name); | |
10723 | *input_line_pointer = c; | |
10724 | return p; | |
10725 | } | |
10726 | ||
10727 | /* Align the current frag to a given power of two. The MIPS assembler | |
10728 | also automatically adjusts any preceding label. */ | |
10729 | ||
10730 | static void | |
10731 | mips_align (to, fill, label) | |
10732 | int to; | |
10733 | int fill; | |
10734 | symbolS *label; | |
10735 | { | |
10736 | mips_emit_delays (false); | |
10737 | frag_align (to, fill, 0); | |
10738 | record_alignment (now_seg, to); | |
10739 | if (label != NULL) | |
10740 | { | |
10741 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 10742 | symbol_set_frag (label, frag_now); |
252b5132 RH |
10743 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
10744 | } | |
10745 | } | |
10746 | ||
10747 | /* Align to a given power of two. .align 0 turns off the automatic | |
10748 | alignment used by the data creating pseudo-ops. */ | |
10749 | ||
10750 | static void | |
10751 | s_align (x) | |
43841e91 | 10752 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10753 | { |
10754 | register int temp; | |
10755 | register long temp_fill; | |
10756 | long max_alignment = 15; | |
10757 | ||
10758 | /* | |
10759 | ||
10760 | o Note that the assembler pulls down any immediately preceeding label | |
10761 | to the aligned address. | |
10762 | o It's not documented but auto alignment is reinstated by | |
10763 | a .align pseudo instruction. | |
10764 | o Note also that after auto alignment is turned off the mips assembler | |
10765 | issues an error on attempt to assemble an improperly aligned data item. | |
10766 | We don't. | |
10767 | ||
10768 | */ | |
10769 | ||
10770 | temp = get_absolute_expression (); | |
10771 | if (temp > max_alignment) | |
10772 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
10773 | else if (temp < 0) | |
10774 | { | |
10775 | as_warn (_("Alignment negative: 0 assumed.")); | |
10776 | temp = 0; | |
10777 | } | |
10778 | if (*input_line_pointer == ',') | |
10779 | { | |
10780 | input_line_pointer++; | |
10781 | temp_fill = get_absolute_expression (); | |
10782 | } | |
10783 | else | |
10784 | temp_fill = 0; | |
10785 | if (temp) | |
10786 | { | |
10787 | auto_align = 1; | |
10788 | mips_align (temp, (int) temp_fill, | |
10789 | insn_labels != NULL ? insn_labels->label : NULL); | |
10790 | } | |
10791 | else | |
10792 | { | |
10793 | auto_align = 0; | |
10794 | } | |
10795 | ||
10796 | demand_empty_rest_of_line (); | |
10797 | } | |
10798 | ||
10799 | void | |
10800 | mips_flush_pending_output () | |
10801 | { | |
10802 | mips_emit_delays (false); | |
10803 | mips_clear_insn_labels (); | |
10804 | } | |
10805 | ||
10806 | static void | |
10807 | s_change_sec (sec) | |
10808 | int sec; | |
10809 | { | |
10810 | segT seg; | |
10811 | ||
10812 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
10813 | .sdata and .sbss sections. We change the .data and .rdata | |
10814 | pseudo-ops to use .sdata. */ | |
10815 | if (mips_pic == EMBEDDED_PIC | |
10816 | && (sec == 'd' || sec == 'r')) | |
10817 | sec = 's'; | |
10818 | ||
10819 | #ifdef OBJ_ELF | |
10820 | /* The ELF backend needs to know that we are changing sections, so | |
10821 | that .previous works correctly. We could do something like check | |
b6ff326e | 10822 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
10823 | as it would not be appropriate to use it in the section changing |
10824 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
10825 | This should be cleaner, somehow. */ | |
10826 | obj_elf_section_change_hook (); | |
10827 | #endif | |
10828 | ||
10829 | mips_emit_delays (false); | |
10830 | switch (sec) | |
10831 | { | |
10832 | case 't': | |
10833 | s_text (0); | |
10834 | break; | |
10835 | case 'd': | |
10836 | s_data (0); | |
10837 | break; | |
10838 | case 'b': | |
10839 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
10840 | demand_empty_rest_of_line (); | |
10841 | break; | |
10842 | ||
10843 | case 'r': | |
10844 | if (USE_GLOBAL_POINTER_OPT) | |
10845 | { | |
10846 | seg = subseg_new (RDATA_SECTION_NAME, | |
10847 | (subsegT) get_absolute_expression ()); | |
10848 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10849 | { | |
10850 | bfd_set_section_flags (stdoutput, seg, | |
10851 | (SEC_ALLOC | |
10852 | | SEC_LOAD | |
10853 | | SEC_READONLY | |
10854 | | SEC_RELOC | |
10855 | | SEC_DATA)); | |
10856 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10857 | record_alignment (seg, 4); |
252b5132 RH |
10858 | } |
10859 | demand_empty_rest_of_line (); | |
10860 | } | |
10861 | else | |
10862 | { | |
10863 | as_bad (_("No read only data section in this object file format")); | |
10864 | demand_empty_rest_of_line (); | |
10865 | return; | |
10866 | } | |
10867 | break; | |
10868 | ||
10869 | case 's': | |
10870 | if (USE_GLOBAL_POINTER_OPT) | |
10871 | { | |
10872 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
10873 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
10874 | { | |
10875 | bfd_set_section_flags (stdoutput, seg, | |
10876 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
10877 | | SEC_DATA); | |
10878 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 10879 | record_alignment (seg, 4); |
252b5132 RH |
10880 | } |
10881 | demand_empty_rest_of_line (); | |
10882 | break; | |
10883 | } | |
10884 | else | |
10885 | { | |
10886 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
10887 | demand_empty_rest_of_line (); | |
10888 | return; | |
10889 | } | |
10890 | } | |
10891 | ||
10892 | auto_align = 1; | |
10893 | } | |
10894 | ||
10895 | void | |
10896 | mips_enable_auto_align () | |
10897 | { | |
10898 | auto_align = 1; | |
10899 | } | |
10900 | ||
10901 | static void | |
10902 | s_cons (log_size) | |
10903 | int log_size; | |
10904 | { | |
10905 | symbolS *label; | |
10906 | ||
10907 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10908 | mips_emit_delays (false); | |
10909 | if (log_size > 0 && auto_align) | |
10910 | mips_align (log_size, 0, label); | |
10911 | mips_clear_insn_labels (); | |
10912 | cons (1 << log_size); | |
10913 | } | |
10914 | ||
10915 | static void | |
10916 | s_float_cons (type) | |
10917 | int type; | |
10918 | { | |
10919 | symbolS *label; | |
10920 | ||
10921 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10922 | ||
10923 | mips_emit_delays (false); | |
10924 | ||
10925 | if (auto_align) | |
49309057 ILT |
10926 | { |
10927 | if (type == 'd') | |
10928 | mips_align (3, 0, label); | |
10929 | else | |
10930 | mips_align (2, 0, label); | |
10931 | } | |
252b5132 RH |
10932 | |
10933 | mips_clear_insn_labels (); | |
10934 | ||
10935 | float_cons (type); | |
10936 | } | |
10937 | ||
10938 | /* Handle .globl. We need to override it because on Irix 5 you are | |
10939 | permitted to say | |
10940 | .globl foo .text | |
10941 | where foo is an undefined symbol, to mean that foo should be | |
10942 | considered to be the address of a function. */ | |
10943 | ||
10944 | static void | |
10945 | s_mips_globl (x) | |
43841e91 | 10946 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10947 | { |
10948 | char *name; | |
10949 | int c; | |
10950 | symbolS *symbolP; | |
10951 | flagword flag; | |
10952 | ||
10953 | name = input_line_pointer; | |
10954 | c = get_symbol_end (); | |
10955 | symbolP = symbol_find_or_make (name); | |
10956 | *input_line_pointer = c; | |
10957 | SKIP_WHITESPACE (); | |
10958 | ||
10959 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10960 | being a function is apparently labelled as being an object. */ | |
10961 | flag = BSF_OBJECT; | |
10962 | ||
10963 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10964 | { | |
10965 | char *secname; | |
10966 | asection *sec; | |
10967 | ||
10968 | secname = input_line_pointer; | |
10969 | c = get_symbol_end (); | |
10970 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10971 | if (sec == NULL) | |
10972 | as_bad (_("%s: no such section"), secname); | |
10973 | *input_line_pointer = c; | |
10974 | ||
10975 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
10976 | flag = BSF_FUNCTION; | |
10977 | } | |
10978 | ||
49309057 | 10979 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
10980 | |
10981 | S_SET_EXTERNAL (symbolP); | |
10982 | demand_empty_rest_of_line (); | |
10983 | } | |
10984 | ||
10985 | static void | |
10986 | s_option (x) | |
43841e91 | 10987 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
10988 | { |
10989 | char *opt; | |
10990 | char c; | |
10991 | ||
10992 | opt = input_line_pointer; | |
10993 | c = get_symbol_end (); | |
10994 | ||
10995 | if (*opt == 'O') | |
10996 | { | |
10997 | /* FIXME: What does this mean? */ | |
10998 | } | |
10999 | else if (strncmp (opt, "pic", 3) == 0) | |
11000 | { | |
11001 | int i; | |
11002 | ||
11003 | i = atoi (opt + 3); | |
11004 | if (i == 0) | |
11005 | mips_pic = NO_PIC; | |
11006 | else if (i == 2) | |
11007 | mips_pic = SVR4_PIC; | |
11008 | else | |
11009 | as_bad (_(".option pic%d not supported"), i); | |
11010 | ||
11011 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11012 | { | |
11013 | if (g_switch_seen && g_switch_value != 0) | |
11014 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11015 | g_switch_value = 0; | |
11016 | bfd_set_gp_size (stdoutput, 0); | |
11017 | } | |
11018 | } | |
11019 | else | |
11020 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11021 | ||
11022 | *input_line_pointer = c; | |
11023 | demand_empty_rest_of_line (); | |
11024 | } | |
11025 | ||
11026 | /* This structure is used to hold a stack of .set values. */ | |
11027 | ||
e972090a NC |
11028 | struct mips_option_stack |
11029 | { | |
252b5132 RH |
11030 | struct mips_option_stack *next; |
11031 | struct mips_set_options options; | |
11032 | }; | |
11033 | ||
11034 | static struct mips_option_stack *mips_opts_stack; | |
11035 | ||
11036 | /* Handle the .set pseudo-op. */ | |
11037 | ||
11038 | static void | |
11039 | s_mipsset (x) | |
43841e91 | 11040 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11041 | { |
11042 | char *name = input_line_pointer, ch; | |
11043 | ||
11044 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11045 | input_line_pointer++; | |
11046 | ch = *input_line_pointer; | |
11047 | *input_line_pointer = '\0'; | |
11048 | ||
11049 | if (strcmp (name, "reorder") == 0) | |
11050 | { | |
11051 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11052 | { | |
11053 | /* If we still have pending nops, we can discard them. The | |
11054 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11055 | needed. */ |
252b5132 RH |
11056 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11057 | * (mips_opts.mips16 ? 2 : 4)); | |
11058 | prev_nop_frag = NULL; | |
11059 | } | |
11060 | mips_opts.noreorder = 0; | |
11061 | } | |
11062 | else if (strcmp (name, "noreorder") == 0) | |
11063 | { | |
11064 | mips_emit_delays (true); | |
11065 | mips_opts.noreorder = 1; | |
11066 | mips_any_noreorder = 1; | |
11067 | } | |
11068 | else if (strcmp (name, "at") == 0) | |
11069 | { | |
11070 | mips_opts.noat = 0; | |
11071 | } | |
11072 | else if (strcmp (name, "noat") == 0) | |
11073 | { | |
11074 | mips_opts.noat = 1; | |
11075 | } | |
11076 | else if (strcmp (name, "macro") == 0) | |
11077 | { | |
11078 | mips_opts.warn_about_macros = 0; | |
11079 | } | |
11080 | else if (strcmp (name, "nomacro") == 0) | |
11081 | { | |
11082 | if (mips_opts.noreorder == 0) | |
11083 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11084 | mips_opts.warn_about_macros = 1; | |
11085 | } | |
11086 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11087 | { | |
11088 | mips_opts.nomove = 0; | |
11089 | } | |
11090 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11091 | { | |
11092 | mips_opts.nomove = 1; | |
11093 | } | |
11094 | else if (strcmp (name, "bopt") == 0) | |
11095 | { | |
11096 | mips_opts.nobopt = 0; | |
11097 | } | |
11098 | else if (strcmp (name, "nobopt") == 0) | |
11099 | { | |
11100 | mips_opts.nobopt = 1; | |
11101 | } | |
11102 | else if (strcmp (name, "mips16") == 0 | |
11103 | || strcmp (name, "MIPS-16") == 0) | |
11104 | mips_opts.mips16 = 1; | |
11105 | else if (strcmp (name, "nomips16") == 0 | |
11106 | || strcmp (name, "noMIPS-16") == 0) | |
11107 | mips_opts.mips16 = 0; | |
11108 | else if (strncmp (name, "mips", 4) == 0) | |
11109 | { | |
11110 | int isa; | |
11111 | ||
11112 | /* Permit the user to change the ISA on the fly. Needless to | |
11113 | say, misuse can cause serious problems. */ | |
11114 | isa = atoi (name + 4); | |
553178e4 TS |
11115 | switch (isa) |
11116 | { | |
11117 | case 0: | |
a325df1d TS |
11118 | mips_opts.gp32 = file_mips_gp32; |
11119 | mips_opts.fp32 = file_mips_fp32; | |
11120 | mips_opts.abi = file_mips_abi; | |
553178e4 TS |
11121 | break; |
11122 | case 1: | |
11123 | case 2: | |
11124 | case 32: | |
a325df1d TS |
11125 | mips_opts.gp32 = 1; |
11126 | mips_opts.fp32 = 1; | |
553178e4 TS |
11127 | break; |
11128 | case 3: | |
11129 | case 4: | |
11130 | case 5: | |
11131 | case 64: | |
a325df1d TS |
11132 | /* Loosen ABI register width restriction. */ |
11133 | if (mips_opts.abi == O32_ABI) | |
11134 | mips_opts.abi = NO_ABI; | |
11135 | mips_opts.gp32 = 0; | |
11136 | mips_opts.fp32 = 0; | |
553178e4 TS |
11137 | break; |
11138 | default: | |
a325df1d | 11139 | as_bad (_("unknown ISA level %s"), name + 4); |
553178e4 TS |
11140 | break; |
11141 | } | |
11142 | ||
e7af610e NC |
11143 | switch (isa) |
11144 | { | |
84ea6cf2 NC |
11145 | case 0: mips_opts.isa = file_mips_isa; break; |
11146 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
11147 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
11148 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
84ea6cf2 | 11149 | case 4: mips_opts.isa = ISA_MIPS4; break; |
9a41af64 | 11150 | case 5: mips_opts.isa = ISA_MIPS5; break; |
84ea6cf2 NC |
11151 | case 32: mips_opts.isa = ISA_MIPS32; break; |
11152 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
a325df1d | 11153 | default: as_bad (_("unknown ISA level %s"), name + 4); break; |
e7af610e | 11154 | } |
252b5132 RH |
11155 | } |
11156 | else if (strcmp (name, "autoextend") == 0) | |
11157 | mips_opts.noautoextend = 0; | |
11158 | else if (strcmp (name, "noautoextend") == 0) | |
11159 | mips_opts.noautoextend = 1; | |
11160 | else if (strcmp (name, "push") == 0) | |
11161 | { | |
11162 | struct mips_option_stack *s; | |
11163 | ||
11164 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11165 | s->next = mips_opts_stack; | |
11166 | s->options = mips_opts; | |
11167 | mips_opts_stack = s; | |
11168 | } | |
11169 | else if (strcmp (name, "pop") == 0) | |
11170 | { | |
11171 | struct mips_option_stack *s; | |
11172 | ||
11173 | s = mips_opts_stack; | |
11174 | if (s == NULL) | |
11175 | as_bad (_(".set pop with no .set push")); | |
11176 | else | |
11177 | { | |
11178 | /* If we're changing the reorder mode we need to handle | |
11179 | delay slots correctly. */ | |
11180 | if (s->options.noreorder && ! mips_opts.noreorder) | |
11181 | mips_emit_delays (true); | |
11182 | else if (! s->options.noreorder && mips_opts.noreorder) | |
11183 | { | |
11184 | if (prev_nop_frag != NULL) | |
11185 | { | |
11186 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11187 | * (mips_opts.mips16 ? 2 : 4)); | |
11188 | prev_nop_frag = NULL; | |
11189 | } | |
11190 | } | |
11191 | ||
11192 | mips_opts = s->options; | |
11193 | mips_opts_stack = s->next; | |
11194 | free (s); | |
11195 | } | |
11196 | } | |
11197 | else | |
11198 | { | |
11199 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11200 | } | |
11201 | *input_line_pointer = ch; | |
11202 | demand_empty_rest_of_line (); | |
11203 | } | |
11204 | ||
11205 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11206 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11207 | ||
11208 | static void | |
11209 | s_abicalls (ignore) | |
43841e91 | 11210 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11211 | { |
11212 | mips_pic = SVR4_PIC; | |
11213 | if (USE_GLOBAL_POINTER_OPT) | |
11214 | { | |
11215 | if (g_switch_seen && g_switch_value != 0) | |
11216 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11217 | g_switch_value = 0; | |
11218 | } | |
11219 | bfd_set_gp_size (stdoutput, 0); | |
11220 | demand_empty_rest_of_line (); | |
11221 | } | |
11222 | ||
11223 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11224 | PIC code. It sets the $gp register for the function based on the | |
11225 | function address, which is in the register named in the argument. | |
11226 | This uses a relocation against _gp_disp, which is handled specially | |
11227 | by the linker. The result is: | |
11228 | lui $gp,%hi(_gp_disp) | |
11229 | addiu $gp,$gp,%lo(_gp_disp) | |
11230 | addu $gp,$gp,.cpload argument | |
11231 | The .cpload argument is normally $25 == $t9. */ | |
11232 | ||
11233 | static void | |
11234 | s_cpload (ignore) | |
43841e91 | 11235 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11236 | { |
11237 | expressionS ex; | |
11238 | int icnt = 0; | |
11239 | ||
6478892d TS |
11240 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11241 | .cpload is ignored. */ | |
11242 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11243 | { |
11244 | s_ignore (0); | |
11245 | return; | |
11246 | } | |
11247 | ||
d3ecfc59 | 11248 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11249 | if (mips_opts.noreorder == 0) |
11250 | as_warn (_(".cpload not in noreorder section")); | |
11251 | ||
11252 | ex.X_op = O_symbol; | |
11253 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11254 | ex.X_op_symbol = NULL; | |
11255 | ex.X_add_number = 0; | |
11256 | ||
11257 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11258 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11259 | |
c4e7957c | 11260 | macro_build_lui (NULL, &icnt, &ex, GP); |
252b5132 RH |
11261 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, |
11262 | (int) BFD_RELOC_LO16); | |
11263 | ||
11264 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
11265 | GP, GP, tc_get_register (0)); | |
11266 | ||
11267 | demand_empty_rest_of_line (); | |
11268 | } | |
11269 | ||
6478892d TS |
11270 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11271 | .cpsetup $reg1, offset|$reg2, label | |
11272 | ||
11273 | If offset is given, this results in: | |
11274 | sd $gp, offset($sp) | |
956cd1d6 TS |
11275 | lui $gp, %hi(%neg(%gp_rel(label))) |
11276 | daddiu $gp, $gp, %lo(%neg(%gp_rel(label))) | |
6478892d TS |
11277 | addu $gp, $gp, $reg1 |
11278 | ||
11279 | If $reg2 is given, this results in: | |
11280 | daddu $reg2, $gp, $0 | |
956cd1d6 TS |
11281 | lui $gp, %hi(%neg(%gp_rel(label))) |
11282 | daddiu $gp, $gp, %lo(%neg(%gp_rel(label))) | |
6478892d TS |
11283 | addu $gp, $gp, $reg1 |
11284 | */ | |
11285 | static void | |
11286 | s_cpsetup (ignore) | |
11287 | int ignore ATTRIBUTE_UNUSED; | |
11288 | { | |
11289 | expressionS ex_off; | |
11290 | expressionS ex_sym; | |
11291 | int reg1; | |
11292 | int icnt = 0; | |
11293 | char *sym; | |
11294 | ||
11295 | /* If we are not generating SVR4 PIC code, .cpload is ignored. | |
11296 | We also need NewABI support. */ | |
11297 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11298 | { | |
11299 | s_ignore (0); | |
11300 | return; | |
11301 | } | |
11302 | ||
11303 | reg1 = tc_get_register (0); | |
11304 | SKIP_WHITESPACE (); | |
11305 | if (*input_line_pointer != ',') | |
11306 | { | |
11307 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11308 | return; | |
11309 | } | |
11310 | else | |
11311 | input_line_pointer++; | |
11312 | SKIP_WHITESPACE (); | |
11313 | if (*input_line_pointer == '$') | |
11314 | mips_cpreturn_register = tc_get_register (0); | |
11315 | else | |
11316 | mips_cpreturn_offset = get_absolute_expression (); | |
11317 | SKIP_WHITESPACE (); | |
11318 | if (*input_line_pointer != ',') | |
11319 | { | |
11320 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11321 | return; | |
11322 | } | |
11323 | else | |
11324 | input_line_pointer++; | |
11325 | SKIP_WHITESPACE (); | |
11326 | sym = input_line_pointer; | |
11327 | while (ISALNUM (*input_line_pointer)) | |
11328 | input_line_pointer++; | |
11329 | *input_line_pointer = 0; | |
11330 | ||
11331 | ex_sym.X_op = O_symbol; | |
11332 | ex_sym.X_add_symbol = symbol_find_or_make (sym); | |
11333 | ex_sym.X_op_symbol = NULL; | |
11334 | ex_sym.X_add_number = 0; | |
11335 | ||
11336 | if (mips_cpreturn_register == -1) | |
11337 | { | |
11338 | ex_off.X_op = O_constant; | |
11339 | ex_off.X_add_symbol = NULL; | |
11340 | ex_off.X_op_symbol = NULL; | |
11341 | ex_off.X_add_number = mips_cpreturn_offset; | |
11342 | ||
11343 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
11344 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11345 | } | |
11346 | else | |
11347 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11348 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
11349 | ||
11350 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, | |
11351 | (int) BFD_RELOC_GPREL16); | |
11352 | fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0, | |
11353 | NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
11354 | fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0, | |
11355 | NULL, 0, 0, BFD_RELOC_HI16_S); | |
11356 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", | |
11357 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
11358 | fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0, | |
11359 | NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
11360 | fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0, | |
11361 | NULL, 0, 0, BFD_RELOC_LO16); | |
11362 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11363 | "d,v,t", mips_gp_register, mips_gp_register, reg1); | |
11364 | ||
11365 | demand_empty_rest_of_line (); | |
11366 | } | |
11367 | ||
11368 | static void | |
11369 | s_cplocal (ignore) | |
11370 | int ignore ATTRIBUTE_UNUSED; | |
11371 | { | |
11372 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11373 | .cplocal is ignored. */ | |
11374 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11375 | { | |
11376 | s_ignore (0); | |
11377 | return; | |
11378 | } | |
11379 | ||
11380 | mips_gp_register = tc_get_register (0); | |
11381 | } | |
11382 | ||
252b5132 RH |
11383 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11384 | offset from $sp. The offset is remembered, and after making a PIC | |
11385 | call $gp is restored from that location. */ | |
11386 | ||
11387 | static void | |
11388 | s_cprestore (ignore) | |
43841e91 | 11389 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11390 | { |
11391 | expressionS ex; | |
11392 | int icnt = 0; | |
11393 | ||
6478892d TS |
11394 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11395 | .cprestore is ignored. */ | |
11396 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11397 | { |
11398 | s_ignore (0); | |
11399 | return; | |
11400 | } | |
11401 | ||
11402 | mips_cprestore_offset = get_absolute_expression (); | |
11403 | ||
11404 | ex.X_op = O_constant; | |
11405 | ex.X_add_symbol = NULL; | |
11406 | ex.X_op_symbol = NULL; | |
11407 | ex.X_add_number = mips_cprestore_offset; | |
11408 | ||
11409 | macro_build ((char *) NULL, &icnt, &ex, | |
ca4e0257 | 11410 | HAVE_32BIT_ADDRESSES ? "sw" : "sd", |
252b5132 RH |
11411 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
11412 | ||
11413 | demand_empty_rest_of_line (); | |
11414 | } | |
11415 | ||
6478892d TS |
11416 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
11417 | was given in the preceeding .gpsetup, it results in: | |
11418 | ld $gp, offset($sp) | |
76b3015f | 11419 | |
6478892d TS |
11420 | If a register $reg2 was given there, it results in: |
11421 | daddiu $gp, $gp, $reg2 | |
11422 | */ | |
11423 | static void | |
11424 | s_cpreturn (ignore) | |
11425 | int ignore ATTRIBUTE_UNUSED; | |
11426 | { | |
11427 | expressionS ex; | |
11428 | int icnt = 0; | |
11429 | ||
11430 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11431 | We also need NewABI support. */ | |
11432 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11433 | { | |
11434 | s_ignore (0); | |
11435 | return; | |
11436 | } | |
11437 | ||
11438 | if (mips_cpreturn_register == -1) | |
11439 | { | |
11440 | ex.X_op = O_constant; | |
11441 | ex.X_add_symbol = NULL; | |
11442 | ex.X_op_symbol = NULL; | |
11443 | ex.X_add_number = mips_cpreturn_offset; | |
11444 | ||
11445 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
11446 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11447 | } | |
11448 | else | |
11449 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11450 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
11451 | ||
11452 | demand_empty_rest_of_line (); | |
11453 | } | |
11454 | ||
11455 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11456 | code. It sets the offset to use in gp_rel relocations. */ | |
11457 | ||
11458 | static void | |
11459 | s_gpvalue (ignore) | |
11460 | int ignore ATTRIBUTE_UNUSED; | |
11461 | { | |
11462 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11463 | We also need NewABI support. */ | |
11464 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11465 | { | |
11466 | s_ignore (0); | |
11467 | return; | |
11468 | } | |
11469 | ||
11470 | mips_cpreturn_offset = get_absolute_expression (); | |
11471 | ||
11472 | demand_empty_rest_of_line (); | |
11473 | } | |
11474 | ||
252b5132 RH |
11475 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11476 | code. It generates a 32 bit GP relative reloc. */ | |
11477 | ||
11478 | static void | |
11479 | s_gpword (ignore) | |
43841e91 | 11480 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11481 | { |
11482 | symbolS *label; | |
11483 | expressionS ex; | |
11484 | char *p; | |
11485 | ||
11486 | /* When not generating PIC code, this is treated as .word. */ | |
11487 | if (mips_pic != SVR4_PIC) | |
11488 | { | |
11489 | s_cons (2); | |
11490 | return; | |
11491 | } | |
11492 | ||
11493 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11494 | mips_emit_delays (true); | |
11495 | if (auto_align) | |
11496 | mips_align (2, 0, label); | |
11497 | mips_clear_insn_labels (); | |
11498 | ||
11499 | expression (&ex); | |
11500 | ||
11501 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
11502 | { | |
11503 | as_bad (_("Unsupported use of .gpword")); | |
11504 | ignore_rest_of_line (); | |
11505 | } | |
11506 | ||
11507 | p = frag_more (4); | |
11508 | md_number_to_chars (p, (valueT) 0, 4); | |
11509 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
cdf6fd85 | 11510 | BFD_RELOC_GPREL32); |
252b5132 RH |
11511 | |
11512 | demand_empty_rest_of_line (); | |
11513 | } | |
11514 | ||
11515 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
11516 | tables in SVR4 PIC code. */ | |
11517 | ||
11518 | static void | |
11519 | s_cpadd (ignore) | |
43841e91 | 11520 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11521 | { |
11522 | int icnt = 0; | |
11523 | int reg; | |
11524 | ||
6478892d TS |
11525 | /* This is ignored when not generating SVR4 PIC code or if this is NewABI |
11526 | code. */ | |
11527 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11528 | { |
11529 | s_ignore (0); | |
11530 | return; | |
11531 | } | |
11532 | ||
11533 | /* Add $gp to the register named as an argument. */ | |
11534 | reg = tc_get_register (0); | |
11535 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 11536 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
11537 | "d,v,t", reg, reg, GP); |
11538 | ||
bdaaa2e1 | 11539 | demand_empty_rest_of_line (); |
252b5132 RH |
11540 | } |
11541 | ||
11542 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
11543 | mips16 mode. This permits the linker to handle them specially, | |
11544 | such as generating jalx instructions when needed. We also make | |
11545 | them odd for the duration of the assembly, in order to generate the | |
11546 | right sort of code. We will make them even in the adjust_symtab | |
11547 | routine, while leaving them marked. This is convenient for the | |
11548 | debugger and the disassembler. The linker knows to make them odd | |
11549 | again. */ | |
11550 | ||
11551 | static void | |
11552 | s_insn (ignore) | |
43841e91 | 11553 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11554 | { |
11555 | if (mips_opts.mips16) | |
11556 | mips16_mark_labels (); | |
11557 | ||
11558 | demand_empty_rest_of_line (); | |
11559 | } | |
11560 | ||
11561 | /* Handle a .stabn directive. We need these in order to mark a label | |
11562 | as being a mips16 text label correctly. Sometimes the compiler | |
11563 | will emit a label, followed by a .stabn, and then switch sections. | |
11564 | If the label and .stabn are in mips16 mode, then the label is | |
11565 | really a mips16 text label. */ | |
11566 | ||
11567 | static void | |
11568 | s_mips_stab (type) | |
11569 | int type; | |
11570 | { | |
11571 | if (type == 'n' && mips_opts.mips16) | |
11572 | mips16_mark_labels (); | |
11573 | ||
11574 | s_stab (type); | |
11575 | } | |
11576 | ||
11577 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
11578 | */ | |
11579 | ||
11580 | static void | |
11581 | s_mips_weakext (ignore) | |
43841e91 | 11582 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11583 | { |
11584 | char *name; | |
11585 | int c; | |
11586 | symbolS *symbolP; | |
11587 | expressionS exp; | |
11588 | ||
11589 | name = input_line_pointer; | |
11590 | c = get_symbol_end (); | |
11591 | symbolP = symbol_find_or_make (name); | |
11592 | S_SET_WEAK (symbolP); | |
11593 | *input_line_pointer = c; | |
11594 | ||
11595 | SKIP_WHITESPACE (); | |
11596 | ||
11597 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11598 | { | |
11599 | if (S_IS_DEFINED (symbolP)) | |
11600 | { | |
956cd1d6 | 11601 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
11602 | S_GET_NAME (symbolP)); |
11603 | ignore_rest_of_line (); | |
11604 | return; | |
11605 | } | |
bdaaa2e1 | 11606 | |
252b5132 RH |
11607 | if (*input_line_pointer == ',') |
11608 | { | |
11609 | ++input_line_pointer; | |
11610 | SKIP_WHITESPACE (); | |
11611 | } | |
bdaaa2e1 | 11612 | |
252b5132 RH |
11613 | expression (&exp); |
11614 | if (exp.X_op != O_symbol) | |
11615 | { | |
11616 | as_bad ("bad .weakext directive"); | |
11617 | ignore_rest_of_line(); | |
11618 | return; | |
11619 | } | |
49309057 | 11620 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
11621 | } |
11622 | ||
11623 | demand_empty_rest_of_line (); | |
11624 | } | |
11625 | ||
11626 | /* Parse a register string into a number. Called from the ECOFF code | |
11627 | to parse .frame. The argument is non-zero if this is the frame | |
11628 | register, so that we can record it in mips_frame_reg. */ | |
11629 | ||
11630 | int | |
11631 | tc_get_register (frame) | |
11632 | int frame; | |
11633 | { | |
11634 | int reg; | |
11635 | ||
11636 | SKIP_WHITESPACE (); | |
11637 | if (*input_line_pointer++ != '$') | |
11638 | { | |
11639 | as_warn (_("expected `$'")); | |
11640 | reg = 0; | |
11641 | } | |
3882b010 | 11642 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
11643 | { |
11644 | reg = get_absolute_expression (); | |
11645 | if (reg < 0 || reg >= 32) | |
11646 | { | |
11647 | as_warn (_("Bad register number")); | |
11648 | reg = 0; | |
11649 | } | |
11650 | } | |
11651 | else | |
11652 | { | |
11653 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
11654 | reg = FP; | |
11655 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
11656 | reg = SP; | |
11657 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
11658 | reg = GP; | |
11659 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
11660 | reg = AT; | |
11661 | else | |
11662 | { | |
11663 | as_warn (_("Unrecognized register name")); | |
11664 | reg = 0; | |
11665 | } | |
11666 | input_line_pointer += 2; | |
11667 | } | |
11668 | if (frame) | |
11669 | mips_frame_reg = reg != 0 ? reg : SP; | |
11670 | return reg; | |
11671 | } | |
11672 | ||
11673 | valueT | |
11674 | md_section_align (seg, addr) | |
11675 | asection *seg; | |
11676 | valueT addr; | |
11677 | { | |
11678 | int align = bfd_get_section_alignment (stdoutput, seg); | |
11679 | ||
11680 | #ifdef OBJ_ELF | |
11681 | /* We don't need to align ELF sections to the full alignment. | |
11682 | However, Irix 5 may prefer that we align them at least to a 16 | |
11683 | byte boundary. We don't bother to align the sections if we are | |
11684 | targeted for an embedded system. */ | |
11685 | if (strcmp (TARGET_OS, "elf") == 0) | |
11686 | return addr; | |
11687 | if (align > 4) | |
11688 | align = 4; | |
11689 | #endif | |
11690 | ||
11691 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
11692 | } | |
11693 | ||
11694 | /* Utility routine, called from above as well. If called while the | |
11695 | input file is still being read, it's only an approximation. (For | |
11696 | example, a symbol may later become defined which appeared to be | |
11697 | undefined earlier.) */ | |
11698 | ||
11699 | static int | |
11700 | nopic_need_relax (sym, before_relaxing) | |
11701 | symbolS *sym; | |
11702 | int before_relaxing; | |
11703 | { | |
11704 | if (sym == 0) | |
11705 | return 0; | |
11706 | ||
6478892d | 11707 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
11708 | { |
11709 | const char *symname; | |
11710 | int change; | |
11711 | ||
11712 | /* Find out whether this symbol can be referenced off the GP | |
11713 | register. It can be if it is smaller than the -G size or if | |
11714 | it is in the .sdata or .sbss section. Certain symbols can | |
11715 | not be referenced off the GP, although it appears as though | |
11716 | they can. */ | |
11717 | symname = S_GET_NAME (sym); | |
11718 | if (symname != (const char *) NULL | |
11719 | && (strcmp (symname, "eprol") == 0 | |
11720 | || strcmp (symname, "etext") == 0 | |
11721 | || strcmp (symname, "_gp") == 0 | |
11722 | || strcmp (symname, "edata") == 0 | |
11723 | || strcmp (symname, "_fbss") == 0 | |
11724 | || strcmp (symname, "_fdata") == 0 | |
11725 | || strcmp (symname, "_ftext") == 0 | |
11726 | || strcmp (symname, "end") == 0 | |
11727 | || strcmp (symname, "_gp_disp") == 0)) | |
11728 | change = 1; | |
11729 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
11730 | && (0 | |
11731 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
11732 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
11733 | && (symbol_get_obj (sym)->ecoff_extern_size | |
11734 | <= g_switch_value)) | |
252b5132 RH |
11735 | #endif |
11736 | /* We must defer this decision until after the whole | |
11737 | file has been read, since there might be a .extern | |
11738 | after the first use of this symbol. */ | |
11739 | || (before_relaxing | |
11740 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 11741 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
11742 | #endif |
11743 | && S_GET_VALUE (sym) == 0) | |
11744 | || (S_GET_VALUE (sym) != 0 | |
11745 | && S_GET_VALUE (sym) <= g_switch_value))) | |
11746 | change = 0; | |
11747 | else | |
11748 | { | |
11749 | const char *segname; | |
11750 | ||
11751 | segname = segment_name (S_GET_SEGMENT (sym)); | |
11752 | assert (strcmp (segname, ".lit8") != 0 | |
11753 | && strcmp (segname, ".lit4") != 0); | |
11754 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
11755 | && strcmp (segname, ".sbss") != 0 |
11756 | && strncmp (segname, ".sdata.", 7) != 0 | |
11757 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
11758 | } |
11759 | return change; | |
11760 | } | |
11761 | else | |
11762 | /* We are not optimizing for the GP register. */ | |
11763 | return 1; | |
11764 | } | |
11765 | ||
11766 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
11767 | extended opcode. SEC is the section the frag is in. */ | |
11768 | ||
11769 | static int | |
11770 | mips16_extended_frag (fragp, sec, stretch) | |
11771 | fragS *fragp; | |
11772 | asection *sec; | |
11773 | long stretch; | |
11774 | { | |
11775 | int type; | |
11776 | register const struct mips16_immed_operand *op; | |
11777 | offsetT val; | |
11778 | int mintiny, maxtiny; | |
11779 | segT symsec; | |
98aa84af | 11780 | fragS *sym_frag; |
252b5132 RH |
11781 | |
11782 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
11783 | return 0; | |
11784 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
11785 | return 1; | |
11786 | ||
11787 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11788 | op = mips16_immed_operands; | |
11789 | while (op->type != type) | |
11790 | { | |
11791 | ++op; | |
11792 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
11793 | } | |
11794 | ||
11795 | if (op->unsp) | |
11796 | { | |
11797 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
11798 | { | |
11799 | mintiny = 1; | |
11800 | maxtiny = 1 << op->nbits; | |
11801 | } | |
11802 | else | |
11803 | { | |
11804 | mintiny = 0; | |
11805 | maxtiny = (1 << op->nbits) - 1; | |
11806 | } | |
11807 | } | |
11808 | else | |
11809 | { | |
11810 | mintiny = - (1 << (op->nbits - 1)); | |
11811 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
11812 | } | |
11813 | ||
98aa84af | 11814 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 11815 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 11816 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
11817 | |
11818 | if (op->pcrel) | |
11819 | { | |
11820 | addressT addr; | |
11821 | ||
11822 | /* We won't have the section when we are called from | |
11823 | mips_relax_frag. However, we will always have been called | |
11824 | from md_estimate_size_before_relax first. If this is a | |
11825 | branch to a different section, we mark it as such. If SEC is | |
11826 | NULL, and the frag is not marked, then it must be a branch to | |
11827 | the same section. */ | |
11828 | if (sec == NULL) | |
11829 | { | |
11830 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
11831 | return 1; | |
11832 | } | |
11833 | else | |
11834 | { | |
98aa84af | 11835 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
11836 | if (symsec != sec) |
11837 | { | |
11838 | fragp->fr_subtype = | |
11839 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11840 | ||
11841 | /* FIXME: We should support this, and let the linker | |
11842 | catch branches and loads that are out of range. */ | |
11843 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
11844 | _("unsupported PC relative reference to different section")); | |
11845 | ||
11846 | return 1; | |
11847 | } | |
98aa84af AM |
11848 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
11849 | /* Assume non-extended on the first relaxation pass. | |
11850 | The address we have calculated will be bogus if this is | |
11851 | a forward branch to another frag, as the forward frag | |
11852 | will have fr_address == 0. */ | |
11853 | return 0; | |
252b5132 RH |
11854 | } |
11855 | ||
11856 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
11857 | the same section. If the relax_marker of the symbol fragment |
11858 | differs from the relax_marker of this fragment, we have not | |
11859 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
11860 | in STRETCH in order to get a better estimate of the address. |
11861 | This particularly matters because of the shift bits. */ | |
11862 | if (stretch != 0 | |
98aa84af | 11863 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
11864 | { |
11865 | fragS *f; | |
11866 | ||
11867 | /* Adjust stretch for any alignment frag. Note that if have | |
11868 | been expanding the earlier code, the symbol may be | |
11869 | defined in what appears to be an earlier frag. FIXME: | |
11870 | This doesn't handle the fr_subtype field, which specifies | |
11871 | a maximum number of bytes to skip when doing an | |
11872 | alignment. */ | |
98aa84af | 11873 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
11874 | { |
11875 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
11876 | { | |
11877 | if (stretch < 0) | |
11878 | stretch = - ((- stretch) | |
11879 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
11880 | else | |
11881 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
11882 | if (stretch == 0) | |
11883 | break; | |
11884 | } | |
11885 | } | |
11886 | if (f != NULL) | |
11887 | val += stretch; | |
11888 | } | |
11889 | ||
11890 | addr = fragp->fr_address + fragp->fr_fix; | |
11891 | ||
11892 | /* The base address rules are complicated. The base address of | |
11893 | a branch is the following instruction. The base address of a | |
11894 | PC relative load or add is the instruction itself, but if it | |
11895 | is in a delay slot (in which case it can not be extended) use | |
11896 | the address of the instruction whose delay slot it is in. */ | |
11897 | if (type == 'p' || type == 'q') | |
11898 | { | |
11899 | addr += 2; | |
11900 | ||
11901 | /* If we are currently assuming that this frag should be | |
11902 | extended, then, the current address is two bytes | |
bdaaa2e1 | 11903 | higher. */ |
252b5132 RH |
11904 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
11905 | addr += 2; | |
11906 | ||
11907 | /* Ignore the low bit in the target, since it will be set | |
11908 | for a text label. */ | |
11909 | if ((val & 1) != 0) | |
11910 | --val; | |
11911 | } | |
11912 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
11913 | addr -= 4; | |
11914 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11915 | addr -= 2; | |
11916 | ||
11917 | val -= addr & ~ ((1 << op->shift) - 1); | |
11918 | ||
11919 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
11920 | if (type == 'p' || type == 'q') | |
11921 | val /= 2; | |
11922 | ||
11923 | /* If any of the shifted bits are set, we must use an extended | |
11924 | opcode. If the address depends on the size of this | |
11925 | instruction, this can lead to a loop, so we arrange to always | |
11926 | use an extended opcode. We only check this when we are in | |
11927 | the main relaxation loop, when SEC is NULL. */ | |
11928 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
11929 | { | |
11930 | fragp->fr_subtype = | |
11931 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11932 | return 1; | |
11933 | } | |
11934 | ||
11935 | /* If we are about to mark a frag as extended because the value | |
11936 | is precisely maxtiny + 1, then there is a chance of an | |
11937 | infinite loop as in the following code: | |
11938 | la $4,foo | |
11939 | .skip 1020 | |
11940 | .align 2 | |
11941 | foo: | |
11942 | In this case when the la is extended, foo is 0x3fc bytes | |
11943 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
11944 | the la must be extended. To avoid this loop, we mark the | |
11945 | frag as extended if it was small, and is about to become | |
11946 | extended with a value of maxtiny + 1. */ | |
11947 | if (val == ((maxtiny + 1) << op->shift) | |
11948 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
11949 | && sec == NULL) | |
11950 | { | |
11951 | fragp->fr_subtype = | |
11952 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
11953 | return 1; | |
11954 | } | |
11955 | } | |
11956 | else if (symsec != absolute_section && sec != NULL) | |
11957 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
11958 | ||
11959 | if ((val & ((1 << op->shift) - 1)) != 0 | |
11960 | || val < (mintiny << op->shift) | |
11961 | || val > (maxtiny << op->shift)) | |
11962 | return 1; | |
11963 | else | |
11964 | return 0; | |
11965 | } | |
11966 | ||
11967 | /* Estimate the size of a frag before relaxing. Unless this is the | |
11968 | mips16, we are not really relaxing here, and the final size is | |
11969 | encoded in the subtype information. For the mips16, we have to | |
11970 | decide whether we are using an extended opcode or not. */ | |
11971 | ||
252b5132 RH |
11972 | int |
11973 | md_estimate_size_before_relax (fragp, segtype) | |
11974 | fragS *fragp; | |
11975 | asection *segtype; | |
11976 | { | |
43841e91 | 11977 | int change = 0; |
8614eeee | 11978 | boolean linkonce = false; |
252b5132 RH |
11979 | |
11980 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
11981 | { | |
11982 | if (mips16_extended_frag (fragp, segtype, 0)) | |
11983 | { | |
11984 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11985 | return 4; | |
11986 | } | |
11987 | else | |
11988 | { | |
11989 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11990 | return 2; | |
11991 | } | |
11992 | } | |
11993 | ||
11994 | if (mips_pic == NO_PIC) | |
11995 | { | |
11996 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
11997 | } | |
11998 | else if (mips_pic == SVR4_PIC) | |
11999 | { | |
12000 | symbolS *sym; | |
12001 | asection *symsec; | |
12002 | ||
12003 | sym = fragp->fr_symbol; | |
12004 | ||
12005 | /* Handle the case of a symbol equated to another symbol. */ | |
e0890092 | 12006 | while (symbol_equated_reloc_p (sym)) |
252b5132 RH |
12007 | { |
12008 | symbolS *n; | |
12009 | ||
12010 | /* It's possible to get a loop here in a badly written | |
12011 | program. */ | |
49309057 | 12012 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
12013 | if (n == sym) |
12014 | break; | |
12015 | sym = n; | |
12016 | } | |
12017 | ||
12018 | symsec = S_GET_SEGMENT (sym); | |
12019 | ||
8614eeee UC |
12020 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
12021 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
12022 | { |
12023 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12024 | != 0) | |
12025 | linkonce = true; | |
12026 | ||
12027 | /* The GNU toolchain uses an extension for ELF: a section | |
12028 | beginning with the magic string .gnu.linkonce is a linkonce | |
12029 | section. */ | |
12030 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12031 | sizeof ".gnu.linkonce" - 1) == 0) | |
12032 | linkonce = true; | |
12033 | } | |
8614eeee | 12034 | |
252b5132 RH |
12035 | /* This must duplicate the test in adjust_reloc_syms. */ |
12036 | change = (symsec != &bfd_und_section | |
12037 | && symsec != &bfd_abs_section | |
426b0403 | 12038 | && ! bfd_is_com_section (symsec) |
8614eeee | 12039 | && !linkonce |
426b0403 | 12040 | #ifdef OBJ_ELF |
ea4ff978 | 12041 | /* A global or weak symbol is treated as external. */ |
46bac6de L |
12042 | && (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12043 | && ! (S_IS_EXTERN (sym) || S_IS_WEAK (sym))) | |
426b0403 AM |
12044 | #endif |
12045 | ); | |
252b5132 RH |
12046 | } |
12047 | else | |
12048 | abort (); | |
12049 | ||
12050 | if (change) | |
12051 | { | |
12052 | /* Record the offset to the first reloc in the fr_opcode field. | |
12053 | This lets md_convert_frag and tc_gen_reloc know that the code | |
12054 | must be expanded. */ | |
12055 | fragp->fr_opcode = (fragp->fr_literal | |
12056 | + fragp->fr_fix | |
12057 | - RELAX_OLD (fragp->fr_subtype) | |
12058 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
12059 | /* FIXME: This really needs as_warn_where. */ | |
12060 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
12061 | as_warn (_("AT used after \".set noat\" or macro used after " |
12062 | "\".set nomacro\"")); | |
12063 | ||
12064 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
12065 | } |
12066 | ||
9a41af64 | 12067 | return 0; |
252b5132 RH |
12068 | } |
12069 | ||
12070 | /* This is called to see whether a reloc against a defined symbol | |
12071 | should be converted into a reloc against a section. Don't adjust | |
12072 | MIPS16 jump relocations, so we don't have to worry about the format | |
12073 | of the offset in the .o file. Don't adjust relocations against | |
12074 | mips16 symbols, so that the linker can find them if it needs to set | |
12075 | up a stub. */ | |
12076 | ||
12077 | int | |
12078 | mips_fix_adjustable (fixp) | |
12079 | fixS *fixp; | |
12080 | { | |
ea4ff978 L |
12081 | #ifdef OBJ_ELF |
12082 | /* Prevent all adjustments to global symbols. */ | |
46bac6de L |
12083 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12084 | && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))) | |
ea4ff978 L |
12085 | return 0; |
12086 | #endif | |
252b5132 RH |
12087 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12088 | return 0; | |
12089 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12090 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12091 | return 0; | |
12092 | if (fixp->fx_addsy == NULL) | |
12093 | return 1; | |
12094 | #ifdef OBJ_ELF | |
12095 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
12096 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12097 | && fixp->fx_subsy == NULL) | |
12098 | return 0; | |
12099 | #endif | |
12100 | return 1; | |
12101 | } | |
12102 | ||
12103 | /* Translate internal representation of relocation info to BFD target | |
12104 | format. */ | |
12105 | ||
12106 | arelent ** | |
12107 | tc_gen_reloc (section, fixp) | |
43841e91 | 12108 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
12109 | fixS *fixp; |
12110 | { | |
12111 | static arelent *retval[4]; | |
12112 | arelent *reloc; | |
12113 | bfd_reloc_code_real_type code; | |
12114 | ||
12115 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
12116 | retval[1] = NULL; | |
12117 | ||
49309057 ILT |
12118 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12119 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12120 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12121 | ||
12122 | if (mips_pic == EMBEDDED_PIC | |
12123 | && SWITCH_TABLE (fixp)) | |
12124 | { | |
12125 | /* For a switch table entry we use a special reloc. The addend | |
12126 | is actually the difference between the reloc address and the | |
12127 | subtrahend. */ | |
12128 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
12129 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
12130 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
12131 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
12132 | } | |
bb2d6cd7 GK |
12133 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12134 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
12135 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
12136 | { | |
12137 | /* We use a special addend for an internal RELLO reloc. */ | |
49309057 | 12138 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
12139 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
12140 | else | |
12141 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
12142 | } | |
12143 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
12144 | { | |
12145 | assert (fixp->fx_next != NULL | |
12146 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
12147 | /* We use a special addend for an internal RELHI reloc. The | |
12148 | reloc is relative to the RELLO; adjust the addend | |
12149 | accordingly. */ | |
49309057 | 12150 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
12151 | reloc->addend = (fixp->fx_next->fx_frag->fr_address |
12152 | + fixp->fx_next->fx_where | |
12153 | - S_GET_VALUE (fixp->fx_subsy)); | |
12154 | else | |
12155 | reloc->addend = (fixp->fx_addnumber | |
12156 | + fixp->fx_next->fx_frag->fr_address | |
12157 | + fixp->fx_next->fx_where); | |
12158 | } | |
252b5132 RH |
12159 | else |
12160 | { | |
12161 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
12162 | /* A gruesome hack which is a result of the gruesome gas reloc | |
12163 | handling. */ | |
12164 | reloc->addend = reloc->address; | |
12165 | else | |
12166 | reloc->addend = -reloc->address; | |
12167 | } | |
12168 | ||
12169 | /* If this is a variant frag, we may need to adjust the existing | |
12170 | reloc and generate a new one. */ | |
12171 | if (fixp->fx_frag->fr_opcode != NULL | |
cdf6fd85 | 12172 | && (fixp->fx_r_type == BFD_RELOC_GPREL16 |
252b5132 RH |
12173 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
12174 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
12175 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
12176 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
12177 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d TS |
12178 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
12179 | && ! HAVE_NEWABI) | |
252b5132 RH |
12180 | { |
12181 | arelent *reloc2; | |
12182 | ||
12183 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
12184 | ||
12185 | /* If this is not the last reloc in this frag, then we have two | |
12186 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
12187 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
12188 | the second one handle all of them. */ | |
12189 | if (fixp->fx_next != NULL | |
12190 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
12191 | { | |
cdf6fd85 TS |
12192 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
12193 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
12194 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
12195 | && (fixp->fx_next->fx_r_type | |
12196 | == BFD_RELOC_MIPS_GOT_LO16)) | |
12197 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
12198 | && (fixp->fx_next->fx_r_type | |
12199 | == BFD_RELOC_MIPS_CALL_LO16))); | |
12200 | retval[0] = NULL; | |
12201 | return retval; | |
12202 | } | |
12203 | ||
12204 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
12205 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
12206 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
12207 | retval[2] = NULL; | |
49309057 ILT |
12208 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12209 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12210 | reloc2->address = (reloc->address |
12211 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
12212 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
12213 | reloc2->addend = fixp->fx_addnumber; | |
12214 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
12215 | assert (reloc2->howto != NULL); | |
12216 | ||
12217 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
12218 | { | |
12219 | arelent *reloc3; | |
12220 | ||
12221 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
12222 | retval[3] = NULL; | |
12223 | *reloc3 = *reloc2; | |
12224 | reloc3->address += 4; | |
12225 | } | |
12226 | ||
12227 | if (mips_pic == NO_PIC) | |
12228 | { | |
cdf6fd85 | 12229 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
12230 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
12231 | } | |
12232 | else if (mips_pic == SVR4_PIC) | |
12233 | { | |
12234 | switch (fixp->fx_r_type) | |
12235 | { | |
12236 | default: | |
12237 | abort (); | |
12238 | case BFD_RELOC_MIPS_GOT16: | |
12239 | break; | |
12240 | case BFD_RELOC_MIPS_CALL16: | |
12241 | case BFD_RELOC_MIPS_GOT_LO16: | |
12242 | case BFD_RELOC_MIPS_CALL_LO16: | |
12243 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
12244 | break; | |
12245 | } | |
12246 | } | |
12247 | else | |
12248 | abort (); | |
12249 | } | |
12250 | ||
12251 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry | |
12252 | to be used in the relocation's section offset. */ | |
12253 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12254 | { | |
12255 | reloc->address = reloc->addend; | |
12256 | reloc->addend = 0; | |
12257 | } | |
12258 | ||
12259 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
12260 | fixup_segment converted a non-PC relative reloc into a PC | |
12261 | relative reloc. In such a case, we need to convert the reloc | |
12262 | code. */ | |
12263 | code = fixp->fx_r_type; | |
12264 | if (fixp->fx_pcrel) | |
12265 | { | |
12266 | switch (code) | |
12267 | { | |
12268 | case BFD_RELOC_8: | |
12269 | code = BFD_RELOC_8_PCREL; | |
12270 | break; | |
12271 | case BFD_RELOC_16: | |
12272 | code = BFD_RELOC_16_PCREL; | |
12273 | break; | |
12274 | case BFD_RELOC_32: | |
12275 | code = BFD_RELOC_32_PCREL; | |
12276 | break; | |
12277 | case BFD_RELOC_64: | |
12278 | code = BFD_RELOC_64_PCREL; | |
12279 | break; | |
12280 | case BFD_RELOC_8_PCREL: | |
12281 | case BFD_RELOC_16_PCREL: | |
12282 | case BFD_RELOC_32_PCREL: | |
12283 | case BFD_RELOC_64_PCREL: | |
12284 | case BFD_RELOC_16_PCREL_S2: | |
12285 | case BFD_RELOC_PCREL_HI16_S: | |
12286 | case BFD_RELOC_PCREL_LO16: | |
12287 | break; | |
12288 | default: | |
12289 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12290 | _("Cannot make %s relocation PC relative"), | |
12291 | bfd_get_reloc_code_name (code)); | |
12292 | } | |
12293 | } | |
12294 | ||
add55e1f RS |
12295 | #ifdef OBJ_ELF |
12296 | /* md_apply_fix3 has a double-subtraction hack to get | |
12297 | bfd_install_relocation to behave nicely. GPREL relocations are | |
12298 | handled correctly without this hack, so undo it here. We can't | |
12299 | stop md_apply_fix3 from subtracting twice in the first place since | |
12300 | the fake addend is required for variant frags above. */ | |
12301 | if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour | |
d11008e1 | 12302 | && code == BFD_RELOC_GPREL16 |
add55e1f RS |
12303 | && reloc->addend != 0 |
12304 | && mips_need_elf_addend_fixup (fixp)) | |
12305 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); | |
12306 | #endif | |
12307 | ||
252b5132 RH |
12308 | /* To support a PC relative reloc when generating embedded PIC code |
12309 | for ECOFF, we use a Cygnus extension. We check for that here to | |
12310 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
12311 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12312 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
12313 | && code == BFD_RELOC_16_PCREL_S2 |
12314 | && mips_pic != EMBEDDED_PIC) | |
12315 | reloc->howto = NULL; | |
12316 | else | |
12317 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12318 | ||
12319 | if (reloc->howto == NULL) | |
12320 | { | |
12321 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12322 | _("Can not represent %s relocation in this object file format"), | |
12323 | bfd_get_reloc_code_name (code)); | |
12324 | retval[0] = NULL; | |
12325 | } | |
12326 | ||
12327 | return retval; | |
12328 | } | |
12329 | ||
12330 | /* Relax a machine dependent frag. This returns the amount by which | |
12331 | the current size of the frag should change. */ | |
12332 | ||
12333 | int | |
12334 | mips_relax_frag (fragp, stretch) | |
12335 | fragS *fragp; | |
12336 | long stretch; | |
12337 | { | |
12338 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
12339 | return 0; | |
12340 | ||
c4e7957c | 12341 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12342 | { |
12343 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12344 | return 0; | |
12345 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12346 | return 2; | |
12347 | } | |
12348 | else | |
12349 | { | |
12350 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12351 | return 0; | |
12352 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12353 | return -2; | |
12354 | } | |
12355 | ||
12356 | return 0; | |
12357 | } | |
12358 | ||
12359 | /* Convert a machine dependent frag. */ | |
12360 | ||
12361 | void | |
12362 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 12363 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
12364 | segT asec; |
12365 | fragS *fragp; | |
12366 | { | |
12367 | int old, new; | |
12368 | char *fixptr; | |
12369 | ||
12370 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
12371 | { | |
12372 | int type; | |
12373 | register const struct mips16_immed_operand *op; | |
12374 | boolean small, ext; | |
12375 | offsetT val; | |
12376 | bfd_byte *buf; | |
12377 | unsigned long insn; | |
12378 | boolean use_extend; | |
12379 | unsigned short extend; | |
12380 | ||
12381 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12382 | op = mips16_immed_operands; | |
12383 | while (op->type != type) | |
12384 | ++op; | |
12385 | ||
12386 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12387 | { | |
12388 | small = false; | |
12389 | ext = true; | |
12390 | } | |
12391 | else | |
12392 | { | |
12393 | small = true; | |
12394 | ext = false; | |
12395 | } | |
12396 | ||
6386f3a7 | 12397 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
12398 | val = S_GET_VALUE (fragp->fr_symbol); |
12399 | if (op->pcrel) | |
12400 | { | |
12401 | addressT addr; | |
12402 | ||
12403 | addr = fragp->fr_address + fragp->fr_fix; | |
12404 | ||
12405 | /* The rules for the base address of a PC relative reloc are | |
12406 | complicated; see mips16_extended_frag. */ | |
12407 | if (type == 'p' || type == 'q') | |
12408 | { | |
12409 | addr += 2; | |
12410 | if (ext) | |
12411 | addr += 2; | |
12412 | /* Ignore the low bit in the target, since it will be | |
12413 | set for a text label. */ | |
12414 | if ((val & 1) != 0) | |
12415 | --val; | |
12416 | } | |
12417 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12418 | addr -= 4; | |
12419 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12420 | addr -= 2; | |
12421 | ||
12422 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
12423 | val -= addr; | |
12424 | ||
12425 | /* Make sure the section winds up with the alignment we have | |
12426 | assumed. */ | |
12427 | if (op->shift > 0) | |
12428 | record_alignment (asec, op->shift); | |
12429 | } | |
12430 | ||
12431 | if (ext | |
12432 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
12433 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
12434 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12435 | _("extended instruction in delay slot")); | |
12436 | ||
12437 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
12438 | ||
12439 | if (target_big_endian) | |
12440 | insn = bfd_getb16 (buf); | |
12441 | else | |
12442 | insn = bfd_getl16 (buf); | |
12443 | ||
12444 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
12445 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
12446 | small, ext, &insn, &use_extend, &extend); | |
12447 | ||
12448 | if (use_extend) | |
12449 | { | |
12450 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
12451 | fragp->fr_fix += 2; | |
12452 | buf += 2; | |
12453 | } | |
12454 | ||
12455 | md_number_to_chars (buf, insn, 2); | |
12456 | fragp->fr_fix += 2; | |
12457 | buf += 2; | |
12458 | } | |
12459 | else | |
12460 | { | |
12461 | if (fragp->fr_opcode == NULL) | |
12462 | return; | |
12463 | ||
12464 | old = RELAX_OLD (fragp->fr_subtype); | |
12465 | new = RELAX_NEW (fragp->fr_subtype); | |
12466 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
12467 | ||
12468 | if (new > 0) | |
12469 | memcpy (fixptr - old, fixptr, new); | |
12470 | ||
12471 | fragp->fr_fix += new - old; | |
12472 | } | |
12473 | } | |
12474 | ||
12475 | #ifdef OBJ_ELF | |
12476 | ||
12477 | /* This function is called after the relocs have been generated. | |
12478 | We've been storing mips16 text labels as odd. Here we convert them | |
12479 | back to even for the convenience of the debugger. */ | |
12480 | ||
12481 | void | |
12482 | mips_frob_file_after_relocs () | |
12483 | { | |
12484 | asymbol **syms; | |
12485 | unsigned int count, i; | |
12486 | ||
12487 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
12488 | return; | |
12489 | ||
12490 | syms = bfd_get_outsymbols (stdoutput); | |
12491 | count = bfd_get_symcount (stdoutput); | |
12492 | for (i = 0; i < count; i++, syms++) | |
12493 | { | |
12494 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
12495 | && ((*syms)->value & 1) != 0) | |
12496 | { | |
12497 | (*syms)->value &= ~1; | |
12498 | /* If the symbol has an odd size, it was probably computed | |
12499 | incorrectly, so adjust that as well. */ | |
12500 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
12501 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
12502 | } | |
12503 | } | |
12504 | } | |
12505 | ||
12506 | #endif | |
12507 | ||
12508 | /* This function is called whenever a label is defined. It is used | |
12509 | when handling branch delays; if a branch has a label, we assume we | |
12510 | can not move it. */ | |
12511 | ||
12512 | void | |
12513 | mips_define_label (sym) | |
12514 | symbolS *sym; | |
12515 | { | |
12516 | struct insn_label_list *l; | |
12517 | ||
12518 | if (free_insn_labels == NULL) | |
12519 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
12520 | else | |
12521 | { | |
12522 | l = free_insn_labels; | |
12523 | free_insn_labels = l->next; | |
12524 | } | |
12525 | ||
12526 | l->label = sym; | |
12527 | l->next = insn_labels; | |
12528 | insn_labels = l; | |
12529 | } | |
12530 | \f | |
12531 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12532 | ||
12533 | /* Some special processing for a MIPS ELF file. */ | |
12534 | ||
12535 | void | |
12536 | mips_elf_final_processing () | |
12537 | { | |
12538 | /* Write out the register information. */ | |
e013f690 | 12539 | if (! HAVE_NEWABI) |
252b5132 RH |
12540 | { |
12541 | Elf32_RegInfo s; | |
12542 | ||
12543 | s.ri_gprmask = mips_gprmask; | |
12544 | s.ri_cprmask[0] = mips_cprmask[0]; | |
12545 | s.ri_cprmask[1] = mips_cprmask[1]; | |
12546 | s.ri_cprmask[2] = mips_cprmask[2]; | |
12547 | s.ri_cprmask[3] = mips_cprmask[3]; | |
12548 | /* The gp_value field is set by the MIPS ELF backend. */ | |
12549 | ||
12550 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
12551 | ((Elf32_External_RegInfo *) | |
12552 | mips_regmask_frag)); | |
12553 | } | |
12554 | else | |
12555 | { | |
12556 | Elf64_Internal_RegInfo s; | |
12557 | ||
12558 | s.ri_gprmask = mips_gprmask; | |
12559 | s.ri_pad = 0; | |
12560 | s.ri_cprmask[0] = mips_cprmask[0]; | |
12561 | s.ri_cprmask[1] = mips_cprmask[1]; | |
12562 | s.ri_cprmask[2] = mips_cprmask[2]; | |
12563 | s.ri_cprmask[3] = mips_cprmask[3]; | |
12564 | /* The gp_value field is set by the MIPS ELF backend. */ | |
12565 | ||
12566 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
12567 | ((Elf64_External_RegInfo *) | |
12568 | mips_regmask_frag)); | |
12569 | } | |
12570 | ||
12571 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
12572 | sort of BFD interface for this. */ | |
12573 | if (mips_any_noreorder) | |
12574 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
12575 | if (mips_pic != NO_PIC) | |
12576 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
12577 | ||
bdaaa2e1 | 12578 | /* Set the MIPS ELF ABI flags. */ |
a325df1d | 12579 | if (file_mips_abi == NO_ABI) |
252b5132 | 12580 | ; |
a325df1d | 12581 | else if (file_mips_abi == O32_ABI) |
252b5132 | 12582 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
a325df1d | 12583 | else if (file_mips_abi == O64_ABI) |
252b5132 | 12584 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
a325df1d | 12585 | else if (file_mips_abi == EABI_ABI) |
252b5132 RH |
12586 | { |
12587 | if (mips_eabi64) | |
12588 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
12589 | else | |
12590 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
12591 | } | |
a325df1d | 12592 | else if (file_mips_abi == N32_ABI) |
be00bddd TS |
12593 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
12594 | ||
12595 | /* Nothing to do for "64". */ | |
252b5132 RH |
12596 | |
12597 | if (mips_32bitmode) | |
12598 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
12599 | } | |
12600 | ||
12601 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
12602 | \f | |
beae10d5 KH |
12603 | typedef struct proc { |
12604 | symbolS *isym; | |
12605 | unsigned long reg_mask; | |
12606 | unsigned long reg_offset; | |
12607 | unsigned long fpreg_mask; | |
12608 | unsigned long fpreg_offset; | |
12609 | unsigned long frame_offset; | |
12610 | unsigned long frame_reg; | |
12611 | unsigned long pc_reg; | |
12612 | } procS; | |
252b5132 RH |
12613 | |
12614 | static procS cur_proc; | |
12615 | static procS *cur_proc_ptr; | |
12616 | static int numprocs; | |
12617 | ||
0a9ef439 | 12618 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 12619 | |
0a9ef439 RH |
12620 | void |
12621 | mips_handle_align (fragp) | |
12622 | fragS *fragp; | |
a19d8eb0 | 12623 | { |
0a9ef439 RH |
12624 | if (fragp->fr_type != rs_align_code) |
12625 | return; | |
12626 | ||
12627 | if (mips_opts.mips16) | |
a19d8eb0 CP |
12628 | { |
12629 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
12630 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
12631 | ||
0a9ef439 RH |
12632 | int bytes; |
12633 | char *p; | |
a19d8eb0 | 12634 | |
0a9ef439 RH |
12635 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
12636 | p = fragp->fr_literal + fragp->fr_fix; | |
12637 | ||
12638 | if (bytes & 1) | |
12639 | { | |
12640 | *p++ = 0; | |
12641 | fragp->fr_fix += 1; | |
12642 | } | |
12643 | ||
12644 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
12645 | fragp->fr_var = 2; | |
a19d8eb0 CP |
12646 | } |
12647 | ||
0a9ef439 | 12648 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
12649 | } |
12650 | ||
252b5132 RH |
12651 | static void |
12652 | md_obj_begin () | |
12653 | { | |
12654 | } | |
12655 | ||
12656 | static void | |
12657 | md_obj_end () | |
12658 | { | |
12659 | /* check for premature end, nesting errors, etc */ | |
12660 | if (cur_proc_ptr) | |
9a41af64 | 12661 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
12662 | } |
12663 | ||
12664 | static long | |
12665 | get_number () | |
12666 | { | |
12667 | int negative = 0; | |
12668 | long val = 0; | |
12669 | ||
12670 | if (*input_line_pointer == '-') | |
12671 | { | |
12672 | ++input_line_pointer; | |
12673 | negative = 1; | |
12674 | } | |
3882b010 | 12675 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 12676 | as_bad (_("expected simple number")); |
252b5132 RH |
12677 | if (input_line_pointer[0] == '0') |
12678 | { | |
12679 | if (input_line_pointer[1] == 'x') | |
12680 | { | |
12681 | input_line_pointer += 2; | |
3882b010 | 12682 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
12683 | { |
12684 | val <<= 4; | |
12685 | val |= hex_value (*input_line_pointer++); | |
12686 | } | |
12687 | return negative ? -val : val; | |
12688 | } | |
12689 | else | |
12690 | { | |
12691 | ++input_line_pointer; | |
3882b010 | 12692 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12693 | { |
12694 | val <<= 3; | |
12695 | val |= *input_line_pointer++ - '0'; | |
12696 | } | |
12697 | return negative ? -val : val; | |
12698 | } | |
12699 | } | |
3882b010 | 12700 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12701 | { |
12702 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
12703 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 12704 | as_warn (_("invalid number")); |
252b5132 RH |
12705 | return -1; |
12706 | } | |
3882b010 | 12707 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12708 | { |
12709 | val *= 10; | |
12710 | val += *input_line_pointer++ - '0'; | |
12711 | } | |
12712 | return negative ? -val : val; | |
12713 | } | |
12714 | ||
12715 | /* The .file directive; just like the usual .file directive, but there | |
12716 | is an initial number which is the ECOFF file index. */ | |
12717 | ||
12718 | static void | |
12719 | s_file (x) | |
43841e91 | 12720 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12721 | { |
12722 | int line; | |
12723 | ||
12724 | line = get_number (); | |
12725 | s_app_file (0); | |
12726 | } | |
12727 | ||
252b5132 RH |
12728 | /* The .end directive. */ |
12729 | ||
12730 | static void | |
12731 | s_mips_end (x) | |
43841e91 | 12732 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
12733 | { |
12734 | symbolS *p; | |
12735 | int maybe_text; | |
12736 | ||
12737 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
12738 | { | |
12739 | p = get_symbol (); | |
12740 | demand_empty_rest_of_line (); | |
12741 | } | |
12742 | else | |
12743 | p = NULL; | |
12744 | ||
12745 | #ifdef BFD_ASSEMBLER | |
12746 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
12747 | maybe_text = 1; | |
12748 | else | |
12749 | maybe_text = 0; | |
12750 | #else | |
12751 | if (now_seg != data_section && now_seg != bss_section) | |
12752 | maybe_text = 1; | |
12753 | else | |
12754 | maybe_text = 0; | |
12755 | #endif | |
12756 | ||
12757 | if (!maybe_text) | |
12758 | as_warn (_(".end not in text section")); | |
12759 | ||
12760 | if (!cur_proc_ptr) | |
12761 | { | |
12762 | as_warn (_(".end directive without a preceding .ent directive.")); | |
12763 | demand_empty_rest_of_line (); | |
12764 | return; | |
12765 | } | |
12766 | ||
12767 | if (p != NULL) | |
12768 | { | |
12769 | assert (S_GET_NAME (p)); | |
12770 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
12771 | as_warn (_(".end symbol does not match .ent symbol.")); | |
12772 | } | |
12773 | else | |
12774 | as_warn (_(".end directive missing or unknown symbol")); | |
12775 | ||
12776 | #ifdef MIPS_STABS_ELF | |
12777 | { | |
12778 | segT saved_seg = now_seg; | |
12779 | subsegT saved_subseg = now_subseg; | |
252b5132 | 12780 | valueT dot; |
252b5132 RH |
12781 | expressionS exp; |
12782 | char *fragp; | |
12783 | ||
12784 | dot = frag_now_fix (); | |
12785 | ||
12786 | #ifdef md_flush_pending_output | |
12787 | md_flush_pending_output (); | |
12788 | #endif | |
12789 | ||
12790 | assert (pdr_seg); | |
12791 | subseg_set (pdr_seg, 0); | |
12792 | ||
beae10d5 | 12793 | /* Write the symbol. */ |
252b5132 RH |
12794 | exp.X_op = O_symbol; |
12795 | exp.X_add_symbol = p; | |
12796 | exp.X_add_number = 0; | |
12797 | emit_expr (&exp, 4); | |
12798 | ||
beae10d5 | 12799 | fragp = frag_more (7 * 4); |
252b5132 | 12800 | |
beae10d5 KH |
12801 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
12802 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
12803 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
12804 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
12805 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
12806 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
12807 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 RH |
12808 | |
12809 | subseg_set (saved_seg, saved_subseg); | |
12810 | } | |
12811 | #endif | |
12812 | ||
12813 | cur_proc_ptr = NULL; | |
12814 | } | |
12815 | ||
12816 | /* The .aent and .ent directives. */ | |
12817 | ||
12818 | static void | |
12819 | s_mips_ent (aent) | |
12820 | int aent; | |
12821 | { | |
12822 | int number = 0; | |
12823 | symbolS *symbolP; | |
12824 | int maybe_text; | |
12825 | ||
12826 | symbolP = get_symbol (); | |
12827 | if (*input_line_pointer == ',') | |
12828 | input_line_pointer++; | |
12829 | SKIP_WHITESPACE (); | |
3882b010 | 12830 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 12831 | || *input_line_pointer == '-') |
252b5132 RH |
12832 | number = get_number (); |
12833 | ||
12834 | #ifdef BFD_ASSEMBLER | |
12835 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
12836 | maybe_text = 1; | |
12837 | else | |
12838 | maybe_text = 0; | |
12839 | #else | |
12840 | if (now_seg != data_section && now_seg != bss_section) | |
12841 | maybe_text = 1; | |
12842 | else | |
12843 | maybe_text = 0; | |
12844 | #endif | |
12845 | ||
12846 | if (!maybe_text) | |
12847 | as_warn (_(".ent or .aent not in text section.")); | |
12848 | ||
12849 | if (!aent && cur_proc_ptr) | |
9a41af64 | 12850 | as_warn (_("missing .end")); |
252b5132 RH |
12851 | |
12852 | if (!aent) | |
12853 | { | |
12854 | cur_proc_ptr = &cur_proc; | |
12855 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
12856 | ||
12857 | cur_proc_ptr->isym = symbolP; | |
12858 | ||
49309057 | 12859 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 RH |
12860 | |
12861 | numprocs++; | |
12862 | } | |
12863 | ||
12864 | demand_empty_rest_of_line (); | |
12865 | } | |
12866 | ||
12867 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 12868 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 12869 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 12870 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
12871 | symbol table (in the mdebug section). */ |
12872 | ||
12873 | static void | |
12874 | s_mips_frame (ignore) | |
2b3c5a5d | 12875 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12876 | { |
12877 | #ifdef MIPS_STABS_ELF | |
12878 | ||
12879 | long val; | |
12880 | ||
beae10d5 | 12881 | if (cur_proc_ptr == (procS *) NULL) |
252b5132 RH |
12882 | { |
12883 | as_warn (_(".frame outside of .ent")); | |
12884 | demand_empty_rest_of_line (); | |
12885 | return; | |
12886 | } | |
12887 | ||
12888 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
12889 | ||
12890 | SKIP_WHITESPACE (); | |
12891 | if (*input_line_pointer++ != ',' | |
12892 | || get_absolute_expression_and_terminator (&val) != ',') | |
12893 | { | |
12894 | as_warn (_("Bad .frame directive")); | |
12895 | --input_line_pointer; | |
12896 | demand_empty_rest_of_line (); | |
12897 | return; | |
12898 | } | |
12899 | ||
12900 | cur_proc_ptr->frame_offset = val; | |
12901 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
12902 | ||
12903 | demand_empty_rest_of_line (); | |
12904 | #else | |
12905 | s_ignore (ignore); | |
12906 | #endif /* MIPS_STABS_ELF */ | |
12907 | } | |
12908 | ||
bdaaa2e1 KH |
12909 | /* The .fmask and .mask directives. If the mdebug section is present |
12910 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 12911 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 12912 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
12913 | make reference to the ecoff symbol table (in the mdebug section). */ |
12914 | ||
12915 | static void | |
12916 | s_mips_mask (reg_type) | |
12917 | char reg_type; | |
12918 | { | |
12919 | #ifdef MIPS_STABS_ELF | |
12920 | long mask, off; | |
bdaaa2e1 | 12921 | |
252b5132 RH |
12922 | if (cur_proc_ptr == (procS *) NULL) |
12923 | { | |
12924 | as_warn (_(".mask/.fmask outside of .ent")); | |
12925 | demand_empty_rest_of_line (); | |
12926 | return; | |
12927 | } | |
12928 | ||
12929 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
12930 | { | |
12931 | as_warn (_("Bad .mask/.fmask directive")); | |
12932 | --input_line_pointer; | |
12933 | demand_empty_rest_of_line (); | |
12934 | return; | |
12935 | } | |
12936 | ||
12937 | off = get_absolute_expression (); | |
12938 | ||
12939 | if (reg_type == 'F') | |
12940 | { | |
12941 | cur_proc_ptr->fpreg_mask = mask; | |
12942 | cur_proc_ptr->fpreg_offset = off; | |
12943 | } | |
12944 | else | |
12945 | { | |
12946 | cur_proc_ptr->reg_mask = mask; | |
12947 | cur_proc_ptr->reg_offset = off; | |
12948 | } | |
12949 | ||
12950 | demand_empty_rest_of_line (); | |
12951 | #else | |
12952 | s_ignore (reg_type); | |
12953 | #endif /* MIPS_STABS_ELF */ | |
12954 | } | |
12955 | ||
12956 | /* The .loc directive. */ | |
12957 | ||
12958 | #if 0 | |
12959 | static void | |
12960 | s_loc (x) | |
12961 | int x; | |
12962 | { | |
12963 | symbolS *symbolP; | |
12964 | int lineno; | |
12965 | int addroff; | |
12966 | ||
12967 | assert (now_seg == text_section); | |
12968 | ||
12969 | lineno = get_number (); | |
12970 | addroff = frag_now_fix (); | |
12971 | ||
12972 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
12973 | S_SET_TYPE (symbolP, N_SLINE); | |
12974 | S_SET_OTHER (symbolP, 0); | |
12975 | S_SET_DESC (symbolP, lineno); | |
12976 | symbolP->sy_segment = now_seg; | |
12977 | } | |
12978 | #endif | |
e7af610e NC |
12979 | |
12980 | /* CPU name/ISA/number mapping table. | |
12981 | ||
12982 | Entries are grouped by type. The first matching CPU or ISA entry | |
12983 | gets chosen by CPU or ISA, so it should be the 'canonical' name | |
12984 | for that type. Entries after that within the type are sorted | |
12985 | alphabetically. | |
12986 | ||
12987 | Case is ignored in comparison, so put the canonical entry in the | |
12988 | appropriate case but everything else in lower case to ease eye pain. */ | |
e972090a NC |
12989 | static const struct mips_cpu_info mips_cpu_info_table[] = |
12990 | { | |
e7af610e NC |
12991 | /* MIPS1 ISA */ |
12992 | { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, | |
12993 | { "mips", 1, ISA_MIPS1, CPU_R3000, }, | |
12994 | ||
12995 | /* MIPS2 ISA */ | |
12996 | { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, | |
12997 | ||
12998 | /* MIPS3 ISA */ | |
12999 | { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, | |
13000 | ||
13001 | /* MIPS4 ISA */ | |
13002 | { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, | |
13003 | ||
84ea6cf2 NC |
13004 | /* MIPS5 ISA */ |
13005 | { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, }, | |
13006 | { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, }, | |
13007 | ||
e7af610e NC |
13008 | /* MIPS32 ISA */ |
13009 | { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, | |
3c02b2ab | 13010 | { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, }, |
e7af610e | 13011 | { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, |
3c02b2ab EC |
13012 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, |
13013 | { "4km", 0, ISA_MIPS32, CPU_MIPS32, }, | |
13014 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32, }, | |
13015 | ||
13016 | /* For historical reasons. */ | |
13017 | { "MIPS64", 1, ISA_MIPS3, CPU_R4000, }, | |
e7af610e | 13018 | |
84ea6cf2 | 13019 | /* MIPS64 ISA */ |
3c02b2ab | 13020 | { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, }, |
84ea6cf2 | 13021 | { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, }, |
3c02b2ab EC |
13022 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64, }, |
13023 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64, }, | |
e7af610e NC |
13024 | |
13025 | /* R2000 CPU */ | |
13026 | { "R2000", 0, ISA_MIPS1, CPU_R2000, }, | |
13027 | { "2000", 0, ISA_MIPS1, CPU_R2000, }, | |
13028 | { "2k", 0, ISA_MIPS1, CPU_R2000, }, | |
13029 | { "r2k", 0, ISA_MIPS1, CPU_R2000, }, | |
13030 | ||
13031 | /* R3000 CPU */ | |
13032 | { "R3000", 0, ISA_MIPS1, CPU_R3000, }, | |
13033 | { "3000", 0, ISA_MIPS1, CPU_R3000, }, | |
13034 | { "3k", 0, ISA_MIPS1, CPU_R3000, }, | |
13035 | { "r3k", 0, ISA_MIPS1, CPU_R3000, }, | |
13036 | ||
13037 | /* TX3900 CPU */ | |
13038 | { "R3900", 0, ISA_MIPS1, CPU_R3900, }, | |
13039 | { "3900", 0, ISA_MIPS1, CPU_R3900, }, | |
e972090a | 13040 | { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, |
e7af610e NC |
13041 | |
13042 | /* R4000 CPU */ | |
13043 | { "R4000", 0, ISA_MIPS3, CPU_R4000, }, | |
13044 | { "4000", 0, ISA_MIPS3, CPU_R4000, }, | |
13045 | { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ | |
13046 | { "r4k", 0, ISA_MIPS3, CPU_R4000, }, | |
13047 | ||
13048 | /* R4010 CPU */ | |
13049 | { "R4010", 0, ISA_MIPS2, CPU_R4010, }, | |
13050 | { "4010", 0, ISA_MIPS2, CPU_R4010, }, | |
13051 | ||
13052 | /* R4400 CPU */ | |
13053 | { "R4400", 0, ISA_MIPS3, CPU_R4400, }, | |
13054 | { "4400", 0, ISA_MIPS3, CPU_R4400, }, | |
13055 | ||
13056 | /* R4600 CPU */ | |
13057 | { "R4600", 0, ISA_MIPS3, CPU_R4600, }, | |
13058 | { "4600", 0, ISA_MIPS3, CPU_R4600, }, | |
13059 | { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, | |
13060 | { "orion", 0, ISA_MIPS3, CPU_R4600, }, | |
13061 | ||
13062 | /* R4650 CPU */ | |
13063 | { "R4650", 0, ISA_MIPS3, CPU_R4650, }, | |
13064 | { "4650", 0, ISA_MIPS3, CPU_R4650, }, | |
13065 | ||
13066 | /* R6000 CPU */ | |
13067 | { "R6000", 0, ISA_MIPS2, CPU_R6000, }, | |
13068 | { "6000", 0, ISA_MIPS2, CPU_R6000, }, | |
13069 | { "6k", 0, ISA_MIPS2, CPU_R6000, }, | |
13070 | { "r6k", 0, ISA_MIPS2, CPU_R6000, }, | |
13071 | ||
13072 | /* R8000 CPU */ | |
13073 | { "R8000", 0, ISA_MIPS4, CPU_R8000, }, | |
13074 | { "8000", 0, ISA_MIPS4, CPU_R8000, }, | |
13075 | { "8k", 0, ISA_MIPS4, CPU_R8000, }, | |
13076 | { "r8k", 0, ISA_MIPS4, CPU_R8000, }, | |
13077 | ||
13078 | /* R10000 CPU */ | |
13079 | { "R10000", 0, ISA_MIPS4, CPU_R10000, }, | |
13080 | { "10000", 0, ISA_MIPS4, CPU_R10000, }, | |
13081 | { "10k", 0, ISA_MIPS4, CPU_R10000, }, | |
13082 | { "r10k", 0, ISA_MIPS4, CPU_R10000, }, | |
13083 | ||
d1cf510e NC |
13084 | /* R12000 CPU */ |
13085 | { "R12000", 0, ISA_MIPS4, CPU_R12000, }, | |
13086 | { "12000", 0, ISA_MIPS4, CPU_R12000, }, | |
13087 | { "12k", 0, ISA_MIPS4, CPU_R12000, }, | |
13088 | { "r12k", 0, ISA_MIPS4, CPU_R12000, }, | |
13089 | ||
e7af610e NC |
13090 | /* VR4100 CPU */ |
13091 | { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13092 | { "4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13093 | { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13094 | { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13095 | ||
13096 | /* VR4111 CPU */ | |
13097 | { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13098 | { "4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13099 | { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13100 | { "r4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13101 | ||
13102 | /* VR4300 CPU */ | |
13103 | { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13104 | { "4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13105 | { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13106 | { "r4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13107 | ||
13108 | /* VR5000 CPU */ | |
13109 | { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13110 | { "5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13111 | { "5k", 0, ISA_MIPS4, CPU_R5000, }, | |
13112 | { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13113 | { "r5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13114 | { "r5200", 0, ISA_MIPS4, CPU_R5000, }, | |
18ae5d72 | 13115 | { "rm5200", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13116 | { "r5230", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13117 | { "rm5230", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13118 | { "r5231", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13119 | { "rm5231", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13120 | { "r5261", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13121 | { "rm5261", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13122 | { "r5721", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13123 | { "rm5721", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e NC |
13124 | { "r5k", 0, ISA_MIPS4, CPU_R5000, }, |
13125 | { "r7000", 0, ISA_MIPS4, CPU_R5000, }, | |
13126 | ||
2e4acd24 | 13127 | /* Broadcom SB-1 CPU */ |
c6c98b38 | 13128 | { "SB-1", 0, ISA_MIPS64, CPU_SB1, }, |
e972090a | 13129 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1, }, |
c6c98b38 NC |
13130 | { "sb1", 0, ISA_MIPS64, CPU_SB1, }, |
13131 | { "sb1250", 0, ISA_MIPS64, CPU_SB1, }, | |
13132 | ||
beae10d5 | 13133 | /* End marker. */ |
e7af610e NC |
13134 | { NULL, 0, 0, 0, }, |
13135 | }; | |
13136 | ||
13137 | static const struct mips_cpu_info * | |
13138 | mips_cpu_info_from_name (name) | |
13139 | const char *name; | |
13140 | { | |
13141 | int i; | |
13142 | ||
13143 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
beae10d5 | 13144 | if (strcasecmp (name, mips_cpu_info_table[i].name) == 0) |
e7af610e NC |
13145 | return (&mips_cpu_info_table[i]); |
13146 | ||
e972090a | 13147 | return NULL; |
e7af610e NC |
13148 | } |
13149 | ||
13150 | static const struct mips_cpu_info * | |
13151 | mips_cpu_info_from_isa (isa) | |
13152 | int isa; | |
13153 | { | |
13154 | int i; | |
13155 | ||
13156 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13157 | if (mips_cpu_info_table[i].is_isa | |
13158 | && isa == mips_cpu_info_table[i].isa) | |
13159 | return (&mips_cpu_info_table[i]); | |
13160 | ||
e972090a | 13161 | return NULL; |
e7af610e NC |
13162 | } |
13163 | ||
13164 | static const struct mips_cpu_info * | |
13165 | mips_cpu_info_from_cpu (cpu) | |
13166 | int cpu; | |
13167 | { | |
13168 | int i; | |
13169 | ||
13170 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13171 | if (!mips_cpu_info_table[i].is_isa | |
13172 | && cpu == mips_cpu_info_table[i].cpu) | |
13173 | return (&mips_cpu_info_table[i]); | |
13174 | ||
e972090a | 13175 | return NULL; |
e7af610e | 13176 | } |