Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
071742cf | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 RH |
113 | /* The name of the readonly data section. */ |
114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
115 | ? ".data" \ | |
116 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
117 | ? ".rdata" \ | |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
a325df1d TS |
124 | /* The ABI to use. */ |
125 | enum mips_abi_level | |
126 | { | |
127 | NO_ABI = 0, | |
128 | O32_ABI, | |
129 | O64_ABI, | |
130 | N32_ABI, | |
131 | N64_ABI, | |
132 | EABI_ABI | |
133 | }; | |
134 | ||
135 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 136 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 137 | |
143d77c5 EC |
138 | /* Whether or not we have code that can call pic code. */ |
139 | int mips_abicalls = FALSE; | |
140 | ||
252b5132 RH |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
143 | reliable. */ | |
144 | ||
e972090a NC |
145 | struct mips_set_options |
146 | { | |
252b5132 RH |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
1f25f5d3 CD |
151 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
152 | if they have not been initialized. Changed by `.set <asename>', by | |
153 | command line options, and based on the default architecture. */ | |
154 | int ase_mips3d; | |
deec1734 | 155 | int ase_mdmx; |
252b5132 RH |
156 | /* Whether we are assembling for the mips16 processor. 0 if we are |
157 | not, 1 if we are, and -1 if the value has not been initialized. | |
158 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
159 | -nomips16 command line options, and the default CPU. */ | |
160 | int mips16; | |
161 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
162 | reorder' and `.set noreorder'. */ | |
163 | int noreorder; | |
164 | /* Non-zero if we should not permit the $at ($1) register to be used | |
165 | in instructions. Changed by `.set at' and `.set noat'. */ | |
166 | int noat; | |
167 | /* Non-zero if we should warn when a macro instruction expands into | |
168 | more than one machine instruction. Changed by `.set nomacro' and | |
169 | `.set macro'. */ | |
170 | int warn_about_macros; | |
171 | /* Non-zero if we should not move instructions. Changed by `.set | |
172 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
173 | int nomove; | |
174 | /* Non-zero if we should not optimize branches by moving the target | |
175 | of the branch into the delay slot. Actually, we don't perform | |
176 | this optimization anyhow. Changed by `.set bopt' and `.set | |
177 | nobopt'. */ | |
178 | int nobopt; | |
179 | /* Non-zero if we should not autoextend mips16 instructions. | |
180 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
181 | int noautoextend; | |
a325df1d TS |
182 | /* Restrict general purpose registers and floating point registers |
183 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
184 | is passed but can changed if the assembler code uses .set mipsN. */ | |
185 | int gp32; | |
186 | int fp32; | |
fef14a42 TS |
187 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
188 | command line option, and the default CPU. */ | |
189 | int arch; | |
252b5132 RH |
190 | }; |
191 | ||
a325df1d | 192 | /* True if -mgp32 was passed. */ |
a8e8e863 | 193 | static int file_mips_gp32 = -1; |
a325df1d TS |
194 | |
195 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 196 | static int file_mips_fp32 = -1; |
a325df1d | 197 | |
252b5132 | 198 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 199 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 200 | -1 to indicate that they have not been initialized. */ |
252b5132 | 201 | |
e972090a NC |
202 | static struct mips_set_options mips_opts = |
203 | { | |
fef14a42 | 204 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 205 | }; |
252b5132 RH |
206 | |
207 | /* These variables are filled in with the masks of registers used. | |
208 | The object format code reads them and puts them in the appropriate | |
209 | place. */ | |
210 | unsigned long mips_gprmask; | |
211 | unsigned long mips_cprmask[4]; | |
212 | ||
213 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 214 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 215 | |
a4672219 TS |
216 | /* True if -mips16 was passed or implied by arguments passed on the |
217 | command line (e.g., by -march). */ | |
218 | static int file_ase_mips16; | |
219 | ||
1f25f5d3 CD |
220 | /* True if -mips3d was passed or implied by arguments passed on the |
221 | command line (e.g., by -march). */ | |
222 | static int file_ase_mips3d; | |
223 | ||
deec1734 CD |
224 | /* True if -mdmx was passed or implied by arguments passed on the |
225 | command line (e.g., by -march). */ | |
226 | static int file_ase_mdmx; | |
227 | ||
ec68c924 | 228 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 229 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 230 | static const char *mips_arch_string; |
ec68c924 EC |
231 | |
232 | /* The argument of the -mtune= flag. The architecture for which we | |
233 | are optimizing. */ | |
234 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 235 | static const char *mips_tune_string; |
ec68c924 | 236 | |
316f5878 | 237 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
238 | static int mips_32bitmode = 0; |
239 | ||
9ce8a5dd GRK |
240 | /* Some ISA's have delay slots for instructions which read or write |
241 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 242 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
243 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
244 | delay slot in this ISA. The uses of this macro assume that any | |
245 | ISA that has delay slots for one of these, has them for all. They | |
246 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 247 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 248 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
249 | (ISA) == ISA_MIPS1 \ |
250 | || (ISA) == ISA_MIPS2 \ | |
251 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
252 | ) |
253 | ||
316f5878 RS |
254 | /* True if the given ABI requires 32-bit registers. */ |
255 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
256 | ||
257 | /* Likewise 64-bit registers. */ | |
258 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
259 | ((ABI) == N32_ABI \ | |
260 | || (ABI) == N64_ABI \ | |
261 | || (ABI) == O64_ABI) | |
262 | ||
bdaaa2e1 | 263 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 264 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
265 | (ISA) == ISA_MIPS3 \ |
266 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 267 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 268 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
269 | ) |
270 | ||
af7ee8bf CD |
271 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
272 | instructions. */ | |
273 | #define ISA_HAS_DROR(ISA) ( \ | |
274 | 0 \ | |
275 | ) | |
276 | ||
277 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
278 | instructions. */ | |
279 | #define ISA_HAS_ROR(ISA) ( \ | |
280 | (ISA) == ISA_MIPS32R2 \ | |
281 | ) | |
282 | ||
e013f690 | 283 | #define HAVE_32BIT_GPRS \ |
316f5878 | 284 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 285 | |
e013f690 | 286 | #define HAVE_32BIT_FPRS \ |
316f5878 | 287 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
288 | |
289 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
290 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
291 | ||
316f5878 | 292 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 293 | |
316f5878 | 294 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
295 | |
296 | /* We can only have 64bit addresses if the object file format | |
297 | supports it. */ | |
afdbd6d0 CD |
298 | #define HAVE_32BIT_ADDRESSES \ |
299 | (HAVE_32BIT_GPRS \ | |
300 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
301 | || ! HAVE_64BIT_OBJECTS) \ | |
302 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
303 | |
304 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 305 | |
b7c7d6c1 TS |
306 | /* Addresses are loaded in different ways, depending on the address size |
307 | in use. The n32 ABI Documentation also mandates the use of additions | |
308 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 309 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 310 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
311 | |
312 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 313 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
314 | |
315 | #define ADDRESS_LOAD_INSN \ | |
316 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
317 | ||
318 | #define ADDRESS_STORE_INSN \ | |
319 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
320 | ||
a4672219 | 321 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
322 | #define CPU_HAS_MIPS16(cpu) \ |
323 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
324 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 325 | |
1f25f5d3 CD |
326 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
327 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
328 | ) | |
329 | ||
deec1734 | 330 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 331 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
332 | ) |
333 | ||
60b63b72 RS |
334 | /* True if CPU has a dror instruction. */ |
335 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
336 | ||
337 | /* True if CPU has a ror instruction. */ | |
338 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
339 | ||
bdaaa2e1 | 340 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 341 | reads from the HI and LO registers, and thus does not |
ec68c924 | 342 | require nops to be inserted. */ |
252b5132 | 343 | |
fef14a42 TS |
344 | #define hilo_interlocks (mips_opts.arch == CPU_R4010 \ |
345 | || mips_opts.arch == CPU_VR5500 \ | |
5a7ea749 | 346 | || mips_opts.arch == CPU_RM7000 \ |
fef14a42 | 347 | || mips_opts.arch == CPU_SB1 \ |
252b5132 RH |
348 | ) |
349 | ||
350 | /* Whether the processor uses hardware interlocks to protect reads | |
351 | from the GPRs, and thus does not require nops to be inserted. */ | |
352 | #define gpr_interlocks \ | |
e7af610e | 353 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 TS |
354 | || mips_opts.arch == CPU_VR5400 \ |
355 | || mips_opts.arch == CPU_VR5500 \ | |
356 | || mips_opts.arch == CPU_R3900) | |
252b5132 RH |
357 | |
358 | /* As with other "interlocks" this is used by hardware that has FP | |
359 | (co-processor) interlocks. */ | |
bdaaa2e1 | 360 | /* Itbl support may require additional care here. */ |
fef14a42 TS |
361 | #define cop_interlocks (mips_opts.arch == CPU_R4300 \ |
362 | || mips_opts.arch == CPU_VR5400 \ | |
363 | || mips_opts.arch == CPU_VR5500 \ | |
364 | || mips_opts.arch == CPU_SB1 \ | |
252b5132 RH |
365 | ) |
366 | ||
6b76fefe CM |
367 | /* Is this a mfhi or mflo instruction? */ |
368 | #define MF_HILO_INSN(PINFO) \ | |
369 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
370 | ||
252b5132 RH |
371 | /* MIPS PIC level. */ |
372 | ||
a161fe53 | 373 | enum mips_pic_level mips_pic; |
252b5132 | 374 | |
39c0a331 L |
375 | /* Warn about all NOPS that the assembler generates. */ |
376 | static int warn_nops = 0; | |
377 | ||
c9914766 | 378 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 379 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 380 | static int mips_big_got = 0; |
252b5132 RH |
381 | |
382 | /* 1 if trap instructions should used for overflow rather than break | |
383 | instructions. */ | |
c9914766 | 384 | static int mips_trap = 0; |
252b5132 | 385 | |
119d663a | 386 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 387 | by assembling two single width halves into two single width floating |
119d663a NC |
388 | point registers which just happen to alias the double width destination |
389 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 390 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
391 | automatically at assemble time. */ |
392 | static int mips_disable_float_construction; | |
393 | ||
252b5132 RH |
394 | /* Non-zero if any .set noreorder directives were used. */ |
395 | ||
396 | static int mips_any_noreorder; | |
397 | ||
6b76fefe CM |
398 | /* Non-zero if nops should be inserted when the register referenced in |
399 | an mfhi/mflo instruction is read in the next two instructions. */ | |
400 | static int mips_7000_hilo_fix; | |
401 | ||
252b5132 | 402 | /* The size of the small data section. */ |
156c2f8b | 403 | static unsigned int g_switch_value = 8; |
252b5132 RH |
404 | /* Whether the -G option was used. */ |
405 | static int g_switch_seen = 0; | |
406 | ||
407 | #define N_RMASK 0xc4 | |
408 | #define N_VFP 0xd4 | |
409 | ||
410 | /* If we can determine in advance that GP optimization won't be | |
411 | possible, we can skip the relaxation stuff that tries to produce | |
412 | GP-relative references. This makes delay slot optimization work | |
413 | better. | |
414 | ||
415 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
416 | gcc output. It needs to guess right for gcc, otherwise gcc |
417 | will put what it thinks is a GP-relative instruction in a branch | |
418 | delay slot. | |
252b5132 RH |
419 | |
420 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
421 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 422 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
423 | |
424 | /* handle of the OPCODE hash table */ | |
425 | static struct hash_control *op_hash = NULL; | |
426 | ||
427 | /* The opcode hash table we use for the mips16. */ | |
428 | static struct hash_control *mips16_op_hash = NULL; | |
429 | ||
430 | /* This array holds the chars that always start a comment. If the | |
431 | pre-processor is disabled, these aren't very useful */ | |
432 | const char comment_chars[] = "#"; | |
433 | ||
434 | /* This array holds the chars that only start a comment at the beginning of | |
435 | a line. If the line seems to have the form '# 123 filename' | |
436 | .line and .file directives will appear in the pre-processed output */ | |
437 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
438 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 439 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
440 | /* Also note that C style comments are always supported. */ |
441 | const char line_comment_chars[] = "#"; | |
442 | ||
bdaaa2e1 | 443 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 444 | const char line_separator_chars[] = ";"; |
252b5132 RH |
445 | |
446 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
447 | const char EXP_CHARS[] = "eE"; | |
448 | ||
449 | /* Chars that mean this number is a floating point constant */ | |
450 | /* As in 0f12.456 */ | |
451 | /* or 0d1.2345e12 */ | |
452 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
453 | ||
454 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
455 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
456 | but nothing is ideal around here. | |
457 | */ | |
458 | ||
459 | static char *insn_error; | |
460 | ||
461 | static int auto_align = 1; | |
462 | ||
463 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
464 | offset in the stack frame from which to restore the $gp register. | |
465 | This is set by the .cprestore pseudo-op, and saved in this | |
466 | variable. */ | |
467 | static offsetT mips_cprestore_offset = -1; | |
468 | ||
6478892d TS |
469 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
470 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 471 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
472 | static offsetT mips_cpreturn_offset = -1; |
473 | static int mips_cpreturn_register = -1; | |
474 | static int mips_gp_register = GP; | |
def2e0dd | 475 | static int mips_gprel_offset = 0; |
6478892d | 476 | |
7a621144 DJ |
477 | /* Whether mips_cprestore_offset has been set in the current function |
478 | (or whether it has already been warned about, if not). */ | |
479 | static int mips_cprestore_valid = 0; | |
480 | ||
252b5132 RH |
481 | /* This is the register which holds the stack frame, as set by the |
482 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
483 | static int mips_frame_reg = SP; | |
484 | ||
7a621144 DJ |
485 | /* Whether mips_frame_reg has been set in the current function |
486 | (or whether it has already been warned about, if not). */ | |
487 | static int mips_frame_reg_valid = 0; | |
488 | ||
252b5132 RH |
489 | /* To output NOP instructions correctly, we need to keep information |
490 | about the previous two instructions. */ | |
491 | ||
492 | /* Whether we are optimizing. The default value of 2 means to remove | |
493 | unneeded NOPs and swap branch instructions when possible. A value | |
494 | of 1 means to not swap branches. A value of 0 means to always | |
495 | insert NOPs. */ | |
496 | static int mips_optimize = 2; | |
497 | ||
498 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
499 | equivalent to seeing no -g option at all. */ | |
500 | static int mips_debug = 0; | |
501 | ||
502 | /* The previous instruction. */ | |
503 | static struct mips_cl_insn prev_insn; | |
504 | ||
505 | /* The instruction before prev_insn. */ | |
506 | static struct mips_cl_insn prev_prev_insn; | |
507 | ||
508 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
509 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 510 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
511 | |
512 | /* Non-zero if prev_insn is valid. */ | |
513 | static int prev_insn_valid; | |
514 | ||
515 | /* The frag for the previous instruction. */ | |
516 | static struct frag *prev_insn_frag; | |
517 | ||
518 | /* The offset into prev_insn_frag for the previous instruction. */ | |
519 | static long prev_insn_where; | |
520 | ||
521 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 522 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
523 | |
524 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 525 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
526 | |
527 | /* Non-zero if the previous instruction was in a delay slot. */ | |
528 | static int prev_insn_is_delay_slot; | |
529 | ||
530 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
531 | static int prev_insn_unreordered; | |
532 | ||
533 | /* Non-zero if the previous instruction uses an extend opcode (if | |
534 | mips16). */ | |
535 | static int prev_insn_extended; | |
536 | ||
537 | /* Non-zero if the previous previous instruction was in a .set | |
538 | noreorder. */ | |
539 | static int prev_prev_insn_unreordered; | |
540 | ||
541 | /* If this is set, it points to a frag holding nop instructions which | |
542 | were inserted before the start of a noreorder section. If those | |
543 | nops turn out to be unnecessary, the size of the frag can be | |
544 | decreased. */ | |
545 | static fragS *prev_nop_frag; | |
546 | ||
547 | /* The number of nop instructions we created in prev_nop_frag. */ | |
548 | static int prev_nop_frag_holds; | |
549 | ||
550 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 551 | prev_nop_frag. */ |
252b5132 RH |
552 | static int prev_nop_frag_required; |
553 | ||
554 | /* The number of instructions we've seen since prev_nop_frag. */ | |
555 | static int prev_nop_frag_since; | |
556 | ||
557 | /* For ECOFF and ELF, relocations against symbols are done in two | |
558 | parts, with a HI relocation and a LO relocation. Each relocation | |
559 | has only 16 bits of space to store an addend. This means that in | |
560 | order for the linker to handle carries correctly, it must be able | |
561 | to locate both the HI and the LO relocation. This means that the | |
562 | relocations must appear in order in the relocation table. | |
563 | ||
564 | In order to implement this, we keep track of each unmatched HI | |
565 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 566 | corresponding LO relocation. */ |
252b5132 | 567 | |
e972090a NC |
568 | struct mips_hi_fixup |
569 | { | |
252b5132 RH |
570 | /* Next HI fixup. */ |
571 | struct mips_hi_fixup *next; | |
572 | /* This fixup. */ | |
573 | fixS *fixp; | |
574 | /* The section this fixup is in. */ | |
575 | segT seg; | |
576 | }; | |
577 | ||
578 | /* The list of unmatched HI relocs. */ | |
579 | ||
580 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
581 | ||
64bdfcaf RS |
582 | /* The frag containing the last explicit relocation operator. |
583 | Null if explicit relocations have not been used. */ | |
584 | ||
585 | static fragS *prev_reloc_op_frag; | |
586 | ||
252b5132 RH |
587 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
588 | ||
589 | #define X ILLEGAL_REG | |
e972090a NC |
590 | static const int mips32_to_16_reg_map[] = |
591 | { | |
252b5132 RH |
592 | X, X, 2, 3, 4, 5, 6, 7, |
593 | X, X, X, X, X, X, X, X, | |
594 | 0, 1, X, X, X, X, X, X, | |
595 | X, X, X, X, X, X, X, X | |
596 | }; | |
597 | #undef X | |
598 | ||
599 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
600 | ||
e972090a NC |
601 | static const unsigned int mips16_to_32_reg_map[] = |
602 | { | |
252b5132 RH |
603 | 16, 17, 2, 3, 4, 5, 6, 7 |
604 | }; | |
60b63b72 RS |
605 | |
606 | static int mips_fix_4122_bugs; | |
4a6a3df4 AO |
607 | |
608 | /* We don't relax branches by default, since this causes us to expand | |
609 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
610 | fail to compute the offset before expanding the macro to the most | |
611 | efficient expansion. */ | |
612 | ||
613 | static int mips_relax_branch; | |
252b5132 RH |
614 | \f |
615 | /* Since the MIPS does not have multiple forms of PC relative | |
616 | instructions, we do not have to do relaxing as is done on other | |
617 | platforms. However, we do have to handle GP relative addressing | |
618 | correctly, which turns out to be a similar problem. | |
619 | ||
620 | Every macro that refers to a symbol can occur in (at least) two | |
621 | forms, one with GP relative addressing and one without. For | |
622 | example, loading a global variable into a register generally uses | |
623 | a macro instruction like this: | |
624 | lw $4,i | |
625 | If i can be addressed off the GP register (this is true if it is in | |
626 | the .sbss or .sdata section, or if it is known to be smaller than | |
627 | the -G argument) this will generate the following instruction: | |
628 | lw $4,i($gp) | |
629 | This instruction will use a GPREL reloc. If i can not be addressed | |
630 | off the GP register, the following instruction sequence will be used: | |
631 | lui $at,i | |
632 | lw $4,i($at) | |
633 | In this case the first instruction will have a HI16 reloc, and the | |
634 | second reloc will have a LO16 reloc. Both relocs will be against | |
635 | the symbol i. | |
636 | ||
637 | The issue here is that we may not know whether i is GP addressable | |
638 | until after we see the instruction that uses it. Therefore, we | |
639 | want to be able to choose the final instruction sequence only at | |
640 | the end of the assembly. This is similar to the way other | |
641 | platforms choose the size of a PC relative instruction only at the | |
642 | end of assembly. | |
643 | ||
644 | When generating position independent code we do not use GP | |
645 | addressing in quite the same way, but the issue still arises as | |
646 | external symbols and local symbols must be handled differently. | |
647 | ||
648 | We handle these issues by actually generating both possible | |
649 | instruction sequences. The longer one is put in a frag_var with | |
650 | type rs_machine_dependent. We encode what to do with the frag in | |
651 | the subtype field. We encode (1) the number of existing bytes to | |
652 | replace, (2) the number of new bytes to use, (3) the offset from | |
653 | the start of the existing bytes to the first reloc we must generate | |
654 | (that is, the offset is applied from the start of the existing | |
655 | bytes after they are replaced by the new bytes, if any), (4) the | |
656 | offset from the start of the existing bytes to the second reloc, | |
657 | (5) whether a third reloc is needed (the third reloc is always four | |
658 | bytes after the second reloc), and (6) whether to warn if this | |
659 | variant is used (this is sometimes needed if .set nomacro or .set | |
660 | noat is in effect). All these numbers are reasonably small. | |
661 | ||
662 | Generating two instruction sequences must be handled carefully to | |
663 | ensure that delay slots are handled correctly. Fortunately, there | |
664 | are a limited number of cases. When the second instruction | |
665 | sequence is generated, append_insn is directed to maintain the | |
666 | existing delay slot information, so it continues to apply to any | |
667 | code after the second instruction sequence. This means that the | |
668 | second instruction sequence must not impose any requirements not | |
669 | required by the first instruction sequence. | |
670 | ||
671 | These variant frags are then handled in functions called by the | |
672 | machine independent code. md_estimate_size_before_relax returns | |
673 | the final size of the frag. md_convert_frag sets up the final form | |
674 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
675 | one if needed. */ | |
676 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
677 | ((relax_substateT) \ | |
678 | (((old) << 23) \ | |
679 | | ((new) << 16) \ | |
680 | | (((reloc1) + 64) << 9) \ | |
681 | | (((reloc2) + 64) << 2) \ | |
682 | | ((reloc3) ? (1 << 1) : 0) \ | |
683 | | ((warn) ? 1 : 0))) | |
684 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
685 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
686 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
687 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
688 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
689 | #define RELAX_WARN(i) ((i) & 1) | |
690 | ||
4a6a3df4 AO |
691 | /* Branch without likely bit. If label is out of range, we turn: |
692 | ||
693 | beq reg1, reg2, label | |
694 | delay slot | |
695 | ||
696 | into | |
697 | ||
698 | bne reg1, reg2, 0f | |
699 | nop | |
700 | j label | |
701 | 0: delay slot | |
702 | ||
703 | with the following opcode replacements: | |
704 | ||
705 | beq <-> bne | |
706 | blez <-> bgtz | |
707 | bltz <-> bgez | |
708 | bc1f <-> bc1t | |
709 | ||
710 | bltzal <-> bgezal (with jal label instead of j label) | |
711 | ||
712 | Even though keeping the delay slot instruction in the delay slot of | |
713 | the branch would be more efficient, it would be very tricky to do | |
714 | correctly, because we'd have to introduce a variable frag *after* | |
715 | the delay slot instruction, and expand that instead. Let's do it | |
716 | the easy way for now, even if the branch-not-taken case now costs | |
717 | one additional instruction. Out-of-range branches are not supposed | |
718 | to be common, anyway. | |
719 | ||
720 | Branch likely. If label is out of range, we turn: | |
721 | ||
722 | beql reg1, reg2, label | |
723 | delay slot (annulled if branch not taken) | |
724 | ||
725 | into | |
726 | ||
727 | beql reg1, reg2, 1f | |
728 | nop | |
729 | beql $0, $0, 2f | |
730 | nop | |
731 | 1: j[al] label | |
732 | delay slot (executed only if branch taken) | |
733 | 2: | |
734 | ||
735 | It would be possible to generate a shorter sequence by losing the | |
736 | likely bit, generating something like: | |
b34976b6 | 737 | |
4a6a3df4 AO |
738 | bne reg1, reg2, 0f |
739 | nop | |
740 | j[al] label | |
741 | delay slot (executed only if branch taken) | |
742 | 0: | |
743 | ||
744 | beql -> bne | |
745 | bnel -> beq | |
746 | blezl -> bgtz | |
747 | bgtzl -> blez | |
748 | bltzl -> bgez | |
749 | bgezl -> bltz | |
750 | bc1fl -> bc1t | |
751 | bc1tl -> bc1f | |
752 | ||
753 | bltzall -> bgezal (with jal label instead of j label) | |
754 | bgezall -> bltzal (ditto) | |
755 | ||
756 | ||
757 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 758 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
759 | ((relax_substateT) \ |
760 | (0xc0000000 \ | |
761 | | ((toofar) ? 1 : 0) \ | |
762 | | ((link) ? 2 : 0) \ | |
763 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 764 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 765 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
766 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
767 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
768 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 769 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 770 | |
252b5132 RH |
771 | /* For mips16 code, we use an entirely different form of relaxation. |
772 | mips16 supports two versions of most instructions which take | |
773 | immediate values: a small one which takes some small value, and a | |
774 | larger one which takes a 16 bit value. Since branches also follow | |
775 | this pattern, relaxing these values is required. | |
776 | ||
777 | We can assemble both mips16 and normal MIPS code in a single | |
778 | object. Therefore, we need to support this type of relaxation at | |
779 | the same time that we support the relaxation described above. We | |
780 | use the high bit of the subtype field to distinguish these cases. | |
781 | ||
782 | The information we store for this type of relaxation is the | |
783 | argument code found in the opcode file for this relocation, whether | |
784 | the user explicitly requested a small or extended form, and whether | |
785 | the relocation is in a jump or jal delay slot. That tells us the | |
786 | size of the value, and how it should be stored. We also store | |
787 | whether the fragment is considered to be extended or not. We also | |
788 | store whether this is known to be a branch to a different section, | |
789 | whether we have tried to relax this frag yet, and whether we have | |
790 | ever extended a PC relative fragment because of a shift count. */ | |
791 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
792 | (0x80000000 \ | |
793 | | ((type) & 0xff) \ | |
794 | | ((small) ? 0x100 : 0) \ | |
795 | | ((ext) ? 0x200 : 0) \ | |
796 | | ((dslot) ? 0x400 : 0) \ | |
797 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 798 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
799 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
800 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
801 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
802 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
803 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
804 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
805 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
806 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
807 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
808 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
809 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
810 | |
811 | /* Is the given value a sign-extended 32-bit value? */ | |
812 | #define IS_SEXT_32BIT_NUM(x) \ | |
813 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
814 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
815 | ||
816 | /* Is the given value a sign-extended 16-bit value? */ | |
817 | #define IS_SEXT_16BIT_NUM(x) \ | |
818 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
819 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
820 | ||
252b5132 RH |
821 | \f |
822 | /* Prototypes for static functions. */ | |
823 | ||
17a2f251 | 824 | #define internalError() \ |
252b5132 | 825 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
826 | |
827 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
828 | ||
b34976b6 | 829 | static void append_insn |
17a2f251 TS |
830 | (char *place, struct mips_cl_insn *ip, expressionS *p, |
831 | bfd_reloc_code_real_type *r); | |
832 | static void mips_no_prev_insn (int); | |
b34976b6 | 833 | static void mips16_macro_build |
17a2f251 TS |
834 | (char *, int *, expressionS *, const char *, const char *, va_list); |
835 | static void load_register (int *, int, expressionS *, int); | |
836 | static void macro (struct mips_cl_insn * ip); | |
837 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 838 | #ifdef LOSING_COMPILER |
17a2f251 | 839 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 840 | #endif |
17a2f251 TS |
841 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
842 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 843 | static void mips16_immed |
17a2f251 TS |
844 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
845 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 846 | static size_t my_getSmallExpression |
17a2f251 TS |
847 | (expressionS *, bfd_reloc_code_real_type *, char *); |
848 | static void my_getExpression (expressionS *, char *); | |
849 | static void s_align (int); | |
850 | static void s_change_sec (int); | |
851 | static void s_change_section (int); | |
852 | static void s_cons (int); | |
853 | static void s_float_cons (int); | |
854 | static void s_mips_globl (int); | |
855 | static void s_option (int); | |
856 | static void s_mipsset (int); | |
857 | static void s_abicalls (int); | |
858 | static void s_cpload (int); | |
859 | static void s_cpsetup (int); | |
860 | static void s_cplocal (int); | |
861 | static void s_cprestore (int); | |
862 | static void s_cpreturn (int); | |
863 | static void s_gpvalue (int); | |
864 | static void s_gpword (int); | |
865 | static void s_gpdword (int); | |
866 | static void s_cpadd (int); | |
867 | static void s_insn (int); | |
868 | static void md_obj_begin (void); | |
869 | static void md_obj_end (void); | |
870 | static void s_mips_ent (int); | |
871 | static void s_mips_end (int); | |
872 | static void s_mips_frame (int); | |
873 | static void s_mips_mask (int reg_type); | |
874 | static void s_mips_stab (int); | |
875 | static void s_mips_weakext (int); | |
876 | static void s_mips_file (int); | |
877 | static void s_mips_loc (int); | |
878 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 879 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 880 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
881 | |
882 | /* Table and functions used to map between CPU/ISA names, and | |
883 | ISA levels, and CPU numbers. */ | |
884 | ||
e972090a NC |
885 | struct mips_cpu_info |
886 | { | |
e7af610e NC |
887 | const char *name; /* CPU or ISA name. */ |
888 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
889 | int isa; /* ISA level. */ | |
890 | int cpu; /* CPU number (default CPU if ISA). */ | |
891 | }; | |
892 | ||
17a2f251 TS |
893 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
894 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
895 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
896 | \f |
897 | /* Pseudo-op table. | |
898 | ||
899 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
900 | should be defined here, but are currently unsupported: .alias, | |
901 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
902 | ||
903 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
904 | specific to the type of debugging information being generated, and | |
905 | should be defined by the object format: .aent, .begin, .bend, | |
906 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
907 | .vreg. | |
908 | ||
909 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
910 | not MIPS CPU specific, but are also not specific to the object file | |
911 | format. This file is probably the best place to define them, but | |
912 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
913 | .struct. */ | |
914 | ||
e972090a NC |
915 | static const pseudo_typeS mips_pseudo_table[] = |
916 | { | |
beae10d5 | 917 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
918 | {"option", s_option, 0}, |
919 | {"set", s_mipsset, 0}, | |
920 | {"rdata", s_change_sec, 'r'}, | |
921 | {"sdata", s_change_sec, 's'}, | |
922 | {"livereg", s_ignore, 0}, | |
923 | {"abicalls", s_abicalls, 0}, | |
924 | {"cpload", s_cpload, 0}, | |
6478892d TS |
925 | {"cpsetup", s_cpsetup, 0}, |
926 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 927 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
928 | {"cpreturn", s_cpreturn, 0}, |
929 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 930 | {"gpword", s_gpword, 0}, |
10181a0d | 931 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
932 | {"cpadd", s_cpadd, 0}, |
933 | {"insn", s_insn, 0}, | |
934 | ||
beae10d5 | 935 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
936 | chips. */ |
937 | {"asciiz", stringer, 1}, | |
938 | {"bss", s_change_sec, 'b'}, | |
939 | {"err", s_err, 0}, | |
940 | {"half", s_cons, 1}, | |
941 | {"dword", s_cons, 3}, | |
942 | {"weakext", s_mips_weakext, 0}, | |
943 | ||
beae10d5 | 944 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
945 | here for one reason or another. */ |
946 | {"align", s_align, 0}, | |
947 | {"byte", s_cons, 0}, | |
948 | {"data", s_change_sec, 'd'}, | |
949 | {"double", s_float_cons, 'd'}, | |
950 | {"float", s_float_cons, 'f'}, | |
951 | {"globl", s_mips_globl, 0}, | |
952 | {"global", s_mips_globl, 0}, | |
953 | {"hword", s_cons, 1}, | |
954 | {"int", s_cons, 2}, | |
955 | {"long", s_cons, 2}, | |
956 | {"octa", s_cons, 4}, | |
957 | {"quad", s_cons, 3}, | |
cca86cc8 | 958 | {"section", s_change_section, 0}, |
252b5132 RH |
959 | {"short", s_cons, 1}, |
960 | {"single", s_float_cons, 'f'}, | |
961 | {"stabn", s_mips_stab, 'n'}, | |
962 | {"text", s_change_sec, 't'}, | |
963 | {"word", s_cons, 2}, | |
add56521 | 964 | |
add56521 | 965 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 966 | |
43841e91 | 967 | { NULL, NULL, 0 }, |
252b5132 RH |
968 | }; |
969 | ||
e972090a NC |
970 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
971 | { | |
beae10d5 KH |
972 | /* These pseudo-ops should be defined by the object file format. |
973 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
974 | {"aent", s_mips_ent, 1}, |
975 | {"bgnb", s_ignore, 0}, | |
976 | {"end", s_mips_end, 0}, | |
977 | {"endb", s_ignore, 0}, | |
978 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 979 | {"file", s_mips_file, 0}, |
252b5132 RH |
980 | {"fmask", s_mips_mask, 'F'}, |
981 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 982 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
983 | {"mask", s_mips_mask, 'R'}, |
984 | {"verstamp", s_ignore, 0}, | |
43841e91 | 985 | { NULL, NULL, 0 }, |
252b5132 RH |
986 | }; |
987 | ||
17a2f251 | 988 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
989 | |
990 | void | |
17a2f251 | 991 | mips_pop_insert (void) |
252b5132 RH |
992 | { |
993 | pop_insert (mips_pseudo_table); | |
994 | if (! ECOFF_DEBUGGING) | |
995 | pop_insert (mips_nonecoff_pseudo_table); | |
996 | } | |
997 | \f | |
998 | /* Symbols labelling the current insn. */ | |
999 | ||
e972090a NC |
1000 | struct insn_label_list |
1001 | { | |
252b5132 RH |
1002 | struct insn_label_list *next; |
1003 | symbolS *label; | |
1004 | }; | |
1005 | ||
1006 | static struct insn_label_list *insn_labels; | |
1007 | static struct insn_label_list *free_insn_labels; | |
1008 | ||
17a2f251 | 1009 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1010 | |
1011 | static inline void | |
17a2f251 | 1012 | mips_clear_insn_labels (void) |
252b5132 RH |
1013 | { |
1014 | register struct insn_label_list **pl; | |
1015 | ||
1016 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1017 | ; | |
1018 | *pl = insn_labels; | |
1019 | insn_labels = NULL; | |
1020 | } | |
1021 | \f | |
1022 | static char *expr_end; | |
1023 | ||
1024 | /* Expressions which appear in instructions. These are set by | |
1025 | mips_ip. */ | |
1026 | ||
1027 | static expressionS imm_expr; | |
1028 | static expressionS offset_expr; | |
1029 | ||
1030 | /* Relocs associated with imm_expr and offset_expr. */ | |
1031 | ||
f6688943 TS |
1032 | static bfd_reloc_code_real_type imm_reloc[3] |
1033 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1034 | static bfd_reloc_code_real_type offset_reloc[3] | |
1035 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1036 | |
252b5132 RH |
1037 | /* These are set by mips16_ip if an explicit extension is used. */ |
1038 | ||
b34976b6 | 1039 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1040 | |
7ed4a06a | 1041 | #ifdef OBJ_ELF |
ecb4347a DJ |
1042 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1043 | ECOFF debugging. */ | |
252b5132 RH |
1044 | |
1045 | static segT pdr_seg; | |
7ed4a06a | 1046 | #endif |
252b5132 | 1047 | |
e013f690 TS |
1048 | /* The default target format to use. */ |
1049 | ||
1050 | const char * | |
17a2f251 | 1051 | mips_target_format (void) |
e013f690 TS |
1052 | { |
1053 | switch (OUTPUT_FLAVOR) | |
1054 | { | |
1055 | case bfd_target_aout_flavour: | |
1056 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1057 | case bfd_target_ecoff_flavour: | |
1058 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1059 | case bfd_target_coff_flavour: | |
1060 | return "pe-mips"; | |
1061 | case bfd_target_elf_flavour: | |
1062 | #ifdef TE_TMIPS | |
cfe86eaa | 1063 | /* This is traditional mips. */ |
e013f690 | 1064 | return (target_big_endian |
cfe86eaa TS |
1065 | ? (HAVE_64BIT_OBJECTS |
1066 | ? "elf64-tradbigmips" | |
1067 | : (HAVE_NEWABI | |
1068 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1069 | : (HAVE_64BIT_OBJECTS | |
1070 | ? "elf64-tradlittlemips" | |
1071 | : (HAVE_NEWABI | |
1072 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1073 | #else |
1074 | return (target_big_endian | |
cfe86eaa TS |
1075 | ? (HAVE_64BIT_OBJECTS |
1076 | ? "elf64-bigmips" | |
1077 | : (HAVE_NEWABI | |
1078 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1079 | : (HAVE_64BIT_OBJECTS | |
1080 | ? "elf64-littlemips" | |
1081 | : (HAVE_NEWABI | |
1082 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1083 | #endif |
1084 | default: | |
1085 | abort (); | |
1086 | return NULL; | |
1087 | } | |
1088 | } | |
1089 | ||
156c2f8b NC |
1090 | /* This function is called once, at assembler startup time. It should |
1091 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1092 | ||
252b5132 | 1093 | void |
17a2f251 | 1094 | md_begin (void) |
252b5132 | 1095 | { |
252b5132 | 1096 | register const char *retval = NULL; |
156c2f8b | 1097 | int i = 0; |
252b5132 | 1098 | int broken = 0; |
1f25f5d3 | 1099 | |
fef14a42 | 1100 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1101 | as_warn (_("Could not set architecture and machine")); |
1102 | ||
252b5132 RH |
1103 | op_hash = hash_new (); |
1104 | ||
1105 | for (i = 0; i < NUMOPCODES;) | |
1106 | { | |
1107 | const char *name = mips_opcodes[i].name; | |
1108 | ||
17a2f251 | 1109 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1110 | if (retval != NULL) |
1111 | { | |
1112 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1113 | mips_opcodes[i].name, retval); | |
1114 | /* Probably a memory allocation problem? Give up now. */ | |
1115 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1116 | } | |
1117 | do | |
1118 | { | |
1119 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1120 | { | |
1121 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1122 | broken = 1; | |
1123 | } | |
1124 | ++i; | |
1125 | } | |
1126 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1127 | } | |
1128 | ||
1129 | mips16_op_hash = hash_new (); | |
1130 | ||
1131 | i = 0; | |
1132 | while (i < bfd_mips16_num_opcodes) | |
1133 | { | |
1134 | const char *name = mips16_opcodes[i].name; | |
1135 | ||
17a2f251 | 1136 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1137 | if (retval != NULL) |
1138 | as_fatal (_("internal: can't hash `%s': %s"), | |
1139 | mips16_opcodes[i].name, retval); | |
1140 | do | |
1141 | { | |
1142 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1143 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1144 | != mips16_opcodes[i].match)) | |
1145 | { | |
1146 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1147 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1148 | broken = 1; | |
1149 | } | |
1150 | ++i; | |
1151 | } | |
1152 | while (i < bfd_mips16_num_opcodes | |
1153 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1154 | } | |
1155 | ||
1156 | if (broken) | |
1157 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1158 | ||
1159 | /* We add all the general register names to the symbol table. This | |
1160 | helps us detect invalid uses of them. */ | |
1161 | for (i = 0; i < 32; i++) | |
1162 | { | |
1163 | char buf[5]; | |
1164 | ||
1165 | sprintf (buf, "$%d", i); | |
1166 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1167 | &zero_address_frag)); | |
1168 | } | |
76db943d TS |
1169 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1170 | &zero_address_frag)); | |
252b5132 RH |
1171 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1172 | &zero_address_frag)); | |
1173 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1174 | &zero_address_frag)); | |
1175 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1176 | &zero_address_frag)); | |
1177 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1178 | &zero_address_frag)); | |
1179 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1180 | &zero_address_frag)); | |
1181 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1182 | &zero_address_frag)); | |
85b51719 TS |
1183 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1184 | &zero_address_frag)); | |
252b5132 RH |
1185 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1186 | &zero_address_frag)); | |
1187 | ||
6047c971 AO |
1188 | /* If we don't add these register names to the symbol table, they |
1189 | may end up being added as regular symbols by operand(), and then | |
1190 | make it to the object file as undefined in case they're not | |
1191 | regarded as local symbols. They're local in o32, since `$' is a | |
1192 | local symbol prefix, but not in n32 or n64. */ | |
1193 | for (i = 0; i < 8; i++) | |
1194 | { | |
1195 | char buf[6]; | |
1196 | ||
1197 | sprintf (buf, "$fcc%i", i); | |
1198 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1199 | &zero_address_frag)); | |
1200 | } | |
1201 | ||
b34976b6 | 1202 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1203 | |
1204 | mips_gprmask = 0; | |
1205 | mips_cprmask[0] = 0; | |
1206 | mips_cprmask[1] = 0; | |
1207 | mips_cprmask[2] = 0; | |
1208 | mips_cprmask[3] = 0; | |
1209 | ||
1210 | /* set the default alignment for the text section (2**2) */ | |
1211 | record_alignment (text_section, 2); | |
1212 | ||
1213 | if (USE_GLOBAL_POINTER_OPT) | |
1214 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1215 | ||
1216 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1217 | { | |
1218 | /* On a native system, sections must be aligned to 16 byte | |
1219 | boundaries. When configured for an embedded ELF target, we | |
1220 | don't bother. */ | |
1221 | if (strcmp (TARGET_OS, "elf") != 0) | |
1222 | { | |
1223 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1224 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1225 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1226 | } | |
1227 | ||
1228 | /* Create a .reginfo section for register masks and a .mdebug | |
1229 | section for debugging information. */ | |
1230 | { | |
1231 | segT seg; | |
1232 | subsegT subseg; | |
1233 | flagword flags; | |
1234 | segT sec; | |
1235 | ||
1236 | seg = now_seg; | |
1237 | subseg = now_subseg; | |
1238 | ||
1239 | /* The ABI says this section should be loaded so that the | |
1240 | running program can access it. However, we don't load it | |
1241 | if we are configured for an embedded target */ | |
1242 | flags = SEC_READONLY | SEC_DATA; | |
1243 | if (strcmp (TARGET_OS, "elf") != 0) | |
1244 | flags |= SEC_ALLOC | SEC_LOAD; | |
1245 | ||
316f5878 | 1246 | if (mips_abi != N64_ABI) |
252b5132 RH |
1247 | { |
1248 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1249 | ||
195325d2 TS |
1250 | bfd_set_section_flags (stdoutput, sec, flags); |
1251 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1252 | |
252b5132 RH |
1253 | #ifdef OBJ_ELF |
1254 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1255 | #endif | |
1256 | } | |
1257 | else | |
1258 | { | |
1259 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1260 | .reginfo section. */ | |
1261 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1262 | bfd_set_section_flags (stdoutput, sec, flags); |
1263 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1264 | |
1265 | #ifdef OBJ_ELF | |
1266 | /* Set up the option header. */ | |
1267 | { | |
1268 | Elf_Internal_Options opthdr; | |
1269 | char *f; | |
1270 | ||
1271 | opthdr.kind = ODK_REGINFO; | |
1272 | opthdr.size = (sizeof (Elf_External_Options) | |
1273 | + sizeof (Elf64_External_RegInfo)); | |
1274 | opthdr.section = 0; | |
1275 | opthdr.info = 0; | |
1276 | f = frag_more (sizeof (Elf_External_Options)); | |
1277 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1278 | (Elf_External_Options *) f); | |
1279 | ||
1280 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1281 | } | |
1282 | #endif | |
1283 | } | |
1284 | ||
1285 | if (ECOFF_DEBUGGING) | |
1286 | { | |
1287 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1288 | (void) bfd_set_section_flags (stdoutput, sec, | |
1289 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1290 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1291 | } | |
ecb4347a | 1292 | #ifdef OBJ_ELF |
dcd410fe | 1293 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1294 | { |
1295 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1296 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1297 | SEC_READONLY | SEC_RELOC | |
1298 | | SEC_DEBUGGING); | |
1299 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1300 | } | |
252b5132 RH |
1301 | #endif |
1302 | ||
1303 | subseg_set (seg, subseg); | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | if (! ECOFF_DEBUGGING) | |
1308 | md_obj_begin (); | |
1309 | } | |
1310 | ||
1311 | void | |
17a2f251 | 1312 | md_mips_end (void) |
252b5132 RH |
1313 | { |
1314 | if (! ECOFF_DEBUGGING) | |
1315 | md_obj_end (); | |
1316 | } | |
1317 | ||
1318 | void | |
17a2f251 | 1319 | md_assemble (char *str) |
252b5132 RH |
1320 | { |
1321 | struct mips_cl_insn insn; | |
f6688943 TS |
1322 | bfd_reloc_code_real_type unused_reloc[3] |
1323 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1324 | |
1325 | imm_expr.X_op = O_absent; | |
252b5132 | 1326 | offset_expr.X_op = O_absent; |
f6688943 TS |
1327 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1328 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1329 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1330 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1331 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1332 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1333 | |
1334 | if (mips_opts.mips16) | |
1335 | mips16_ip (str, &insn); | |
1336 | else | |
1337 | { | |
1338 | mips_ip (str, &insn); | |
beae10d5 KH |
1339 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1340 | str, insn.insn_opcode)); | |
252b5132 RH |
1341 | } |
1342 | ||
1343 | if (insn_error) | |
1344 | { | |
1345 | as_bad ("%s `%s'", insn_error, str); | |
1346 | return; | |
1347 | } | |
1348 | ||
1349 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1350 | { | |
1351 | if (mips_opts.mips16) | |
1352 | mips16_macro (&insn); | |
1353 | else | |
1354 | macro (&insn); | |
1355 | } | |
1356 | else | |
1357 | { | |
1358 | if (imm_expr.X_op != O_absent) | |
5e0116d5 | 1359 | append_insn (NULL, &insn, &imm_expr, imm_reloc); |
252b5132 | 1360 | else if (offset_expr.X_op != O_absent) |
5e0116d5 | 1361 | append_insn (NULL, &insn, &offset_expr, offset_reloc); |
252b5132 | 1362 | else |
5e0116d5 | 1363 | append_insn (NULL, &insn, NULL, unused_reloc); |
252b5132 RH |
1364 | } |
1365 | } | |
1366 | ||
5919d012 RS |
1367 | /* Return true if the given relocation might need a matching %lo(). |
1368 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1369 | applied to local symbols. */ | |
1370 | ||
1371 | static inline bfd_boolean | |
17a2f251 | 1372 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 RS |
1373 | { |
1374 | return (reloc == BFD_RELOC_HI16_S | |
1375 | || reloc == BFD_RELOC_MIPS_GOT16); | |
1376 | } | |
1377 | ||
1378 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1379 | relocation. */ | |
1380 | ||
1381 | static inline bfd_boolean | |
17a2f251 | 1382 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1383 | { |
1384 | return (fixp->fx_next != NULL | |
1385 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1386 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1387 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1388 | } | |
1389 | ||
252b5132 RH |
1390 | /* See whether instruction IP reads register REG. CLASS is the type |
1391 | of register. */ | |
1392 | ||
1393 | static int | |
17a2f251 TS |
1394 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1395 | enum mips_regclass class) | |
252b5132 RH |
1396 | { |
1397 | if (class == MIPS16_REG) | |
1398 | { | |
1399 | assert (mips_opts.mips16); | |
1400 | reg = mips16_to_32_reg_map[reg]; | |
1401 | class = MIPS_GR_REG; | |
1402 | } | |
1403 | ||
85b51719 TS |
1404 | /* Don't report on general register ZERO, since it never changes. */ |
1405 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1406 | return 0; |
1407 | ||
1408 | if (class == MIPS_FP_REG) | |
1409 | { | |
1410 | assert (! mips_opts.mips16); | |
1411 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1412 | This is not optimal, because it will introduce an unnecessary | |
1413 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1414 | need to distinguish reading both $f0 and $f1 or just one of | |
1415 | them. Note that we don't have to check the other way, | |
1416 | because there is no instruction that sets both $f0 and $f1 | |
1417 | and requires a delay. */ | |
1418 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1419 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1420 | == (reg &~ (unsigned) 1))) | |
1421 | return 1; | |
1422 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1423 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1424 | == (reg &~ (unsigned) 1))) | |
1425 | return 1; | |
1426 | } | |
1427 | else if (! mips_opts.mips16) | |
1428 | { | |
1429 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1430 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1431 | return 1; | |
1432 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1433 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1434 | return 1; | |
1435 | } | |
1436 | else | |
1437 | { | |
1438 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1439 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1440 | & MIPS16OP_MASK_RX)] | |
1441 | == reg)) | |
1442 | return 1; | |
1443 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1444 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1445 | & MIPS16OP_MASK_RY)] | |
1446 | == reg)) | |
1447 | return 1; | |
1448 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1449 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1450 | & MIPS16OP_MASK_MOVE32Z)] | |
1451 | == reg)) | |
1452 | return 1; | |
1453 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1454 | return 1; | |
1455 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1456 | return 1; | |
1457 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1458 | return 1; | |
1459 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1460 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1461 | & MIPS16OP_MASK_REGR32) == reg) | |
1462 | return 1; | |
1463 | } | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | /* This function returns true if modifying a register requires a | |
1469 | delay. */ | |
1470 | ||
1471 | static int | |
17a2f251 | 1472 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1473 | { |
1474 | unsigned long prev_pinfo; | |
1475 | ||
1476 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1477 | if (! mips_opts.noreorder | |
9ce8a5dd | 1478 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1479 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1480 | || (! gpr_interlocks | |
1481 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1482 | { | |
1483 | /* A load from a coprocessor or from memory. All load | |
1484 | delays delay the use of general register rt for one | |
1485 | instruction on the r3000. The r6000 and r4000 use | |
1486 | interlocks. */ | |
bdaaa2e1 | 1487 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1488 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1489 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1490 | return 1; | |
1491 | } | |
1492 | ||
1493 | return 0; | |
1494 | } | |
1495 | ||
1496 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1497 | handle them specially, such as generating jalx instructions when | |
1498 | needed. We also make them odd for the duration of the assembly, in | |
1499 | order to generate the right sort of code. We will make them even | |
1500 | in the adjust_symtab routine, while leaving them marked. This is | |
1501 | convenient for the debugger and the disassembler. The linker knows | |
1502 | to make them odd again. */ | |
1503 | ||
1504 | static void | |
17a2f251 | 1505 | mips16_mark_labels (void) |
252b5132 RH |
1506 | { |
1507 | if (mips_opts.mips16) | |
1508 | { | |
1509 | struct insn_label_list *l; | |
98aa84af | 1510 | valueT val; |
252b5132 RH |
1511 | |
1512 | for (l = insn_labels; l != NULL; l = l->next) | |
1513 | { | |
1514 | #ifdef OBJ_ELF | |
1515 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1516 | S_SET_OTHER (l->label, STO_MIPS16); | |
1517 | #endif | |
98aa84af AM |
1518 | val = S_GET_VALUE (l->label); |
1519 | if ((val & 1) == 0) | |
1520 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1521 | } |
1522 | } | |
1523 | } | |
1524 | ||
1525 | /* Output an instruction. PLACE is where to put the instruction; if | |
1526 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1527 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1528 | used with RELOC_TYPE. */ | |
1529 | ||
1530 | static void | |
17a2f251 TS |
1531 | append_insn (char *place, struct mips_cl_insn *ip, expressionS *address_expr, |
1532 | bfd_reloc_code_real_type *reloc_type) | |
252b5132 RH |
1533 | { |
1534 | register unsigned long prev_pinfo, pinfo; | |
1535 | char *f; | |
f6688943 | 1536 | fixS *fixp[3]; |
252b5132 | 1537 | int nops = 0; |
f5040a92 | 1538 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1539 | |
1540 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1541 | mips16_mark_labels (); |
252b5132 RH |
1542 | |
1543 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1544 | pinfo = ip->insn_mo->pinfo; | |
1545 | ||
1546 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1547 | { | |
1548 | int prev_prev_nop; | |
1549 | ||
1550 | /* If the previous insn required any delay slots, see if we need | |
1551 | to insert a NOP or two. There are eight kinds of possible | |
1552 | hazards, of which an instruction can have at most one type. | |
1553 | (1) a load from memory delay | |
1554 | (2) a load from a coprocessor delay | |
1555 | (3) an unconditional branch delay | |
1556 | (4) a conditional branch delay | |
1557 | (5) a move to coprocessor register delay | |
1558 | (6) a load coprocessor register from memory delay | |
1559 | (7) a coprocessor condition code delay | |
1560 | (8) a HI/LO special register delay | |
1561 | ||
1562 | There are a lot of optimizations we could do that we don't. | |
1563 | In particular, we do not, in general, reorder instructions. | |
1564 | If you use gcc with optimization, it will reorder | |
1565 | instructions and generally do much more optimization then we | |
1566 | do here; repeating all that work in the assembler would only | |
1567 | benefit hand written assembly code, and does not seem worth | |
1568 | it. */ | |
1569 | ||
1570 | /* This is how a NOP is emitted. */ | |
1571 | #define emit_nop() \ | |
1572 | (mips_opts.mips16 \ | |
1573 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1574 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1575 | ||
1576 | /* The previous insn might require a delay slot, depending upon | |
1577 | the contents of the current insn. */ | |
1578 | if (! mips_opts.mips16 | |
9ce8a5dd | 1579 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1580 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1581 | && ! cop_interlocks) | |
1582 | || (! gpr_interlocks | |
1583 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1584 | { | |
1585 | /* A load from a coprocessor or from memory. All load | |
1586 | delays delay the use of general register rt for one | |
1587 | instruction on the r3000. The r6000 and r4000 use | |
1588 | interlocks. */ | |
beae10d5 | 1589 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1590 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1591 | if (mips_optimize == 0 | |
1592 | || insn_uses_reg (ip, | |
1593 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1594 | & OP_MASK_RT), | |
1595 | MIPS_GR_REG)) | |
1596 | ++nops; | |
1597 | } | |
1598 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1599 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1600 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1601 | && ! cop_interlocks) |
e7af610e | 1602 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1603 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1604 | { | |
1605 | /* A generic coprocessor delay. The previous instruction | |
1606 | modified a coprocessor general or control register. If | |
1607 | it modified a control register, we need to avoid any | |
1608 | coprocessor instruction (this is probably not always | |
1609 | required, but it sometimes is). If it modified a general | |
1610 | register, we avoid using that register. | |
1611 | ||
1612 | On the r6000 and r4000 loading a coprocessor register | |
1613 | from memory is interlocked, and does not require a delay. | |
1614 | ||
1615 | This case is not handled very well. There is no special | |
1616 | knowledge of CP0 handling, and the coprocessors other | |
1617 | than the floating point unit are not distinguished at | |
1618 | all. */ | |
1619 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1620 | Need to modify this to include knowledge about |
252b5132 RH |
1621 | user specified delays! */ |
1622 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1623 | { | |
1624 | if (mips_optimize == 0 | |
1625 | || insn_uses_reg (ip, | |
1626 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1627 | & OP_MASK_FT), | |
1628 | MIPS_FP_REG)) | |
1629 | ++nops; | |
1630 | } | |
1631 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1632 | { | |
1633 | if (mips_optimize == 0 | |
1634 | || insn_uses_reg (ip, | |
1635 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1636 | & OP_MASK_FS), | |
1637 | MIPS_FP_REG)) | |
1638 | ++nops; | |
1639 | } | |
1640 | else | |
1641 | { | |
1642 | /* We don't know exactly what the previous instruction | |
1643 | does. If the current instruction uses a coprocessor | |
1644 | register, we must insert a NOP. If previous | |
1645 | instruction may set the condition codes, and the | |
1646 | current instruction uses them, we must insert two | |
1647 | NOPS. */ | |
bdaaa2e1 | 1648 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1649 | if (mips_optimize == 0 |
1650 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1651 | && (pinfo & INSN_READ_COND_CODE))) | |
1652 | nops += 2; | |
1653 | else if (pinfo & INSN_COP) | |
1654 | ++nops; | |
1655 | } | |
1656 | } | |
1657 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1658 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1659 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1660 | && ! cop_interlocks) | |
1661 | { | |
1662 | /* The previous instruction sets the coprocessor condition | |
1663 | codes, but does not require a general coprocessor delay | |
1664 | (this means it is a floating point comparison | |
1665 | instruction). If this instruction uses the condition | |
1666 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1667 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1668 | if (mips_optimize == 0 |
1669 | || (pinfo & INSN_READ_COND_CODE)) | |
1670 | ++nops; | |
1671 | } | |
6b76fefe CM |
1672 | |
1673 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1674 | previous insn was an mfhi/mflo and the current insn | |
1675 | reads the register that the mfhi/mflo wrote to, then | |
1676 | insert two nops. */ | |
1677 | ||
1678 | else if (mips_7000_hilo_fix | |
1679 | && MF_HILO_INSN (prev_pinfo) | |
1680 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1681 | & OP_MASK_RD), |
1682 | MIPS_GR_REG)) | |
6b76fefe CM |
1683 | { |
1684 | nops += 2; | |
1685 | } | |
1686 | ||
1687 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1688 | 2nd previous insn was an mfhi/mflo and the current insn | |
1689 | reads the register that the mfhi/mflo wrote to, then | |
1690 | insert one nop. */ | |
1691 | ||
1692 | else if (mips_7000_hilo_fix | |
1693 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1694 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1695 | & OP_MASK_RD), | |
1696 | MIPS_GR_REG)) | |
bdaaa2e1 | 1697 | |
6b76fefe | 1698 | { |
f9419b05 | 1699 | ++nops; |
6b76fefe | 1700 | } |
bdaaa2e1 | 1701 | |
252b5132 RH |
1702 | else if (prev_pinfo & INSN_READ_LO) |
1703 | { | |
1704 | /* The previous instruction reads the LO register; if the | |
1705 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1706 | insert two NOPS. Some newer processors have interlocks. |
1707 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1708 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1709 | though the tx39's divide insns still do require the |
1710 | delay. */ | |
252b5132 | 1711 | if (! (hilo_interlocks |
ec68c924 | 1712 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1713 | && (mips_optimize == 0 |
1714 | || (pinfo & INSN_WRITE_LO))) | |
1715 | nops += 2; | |
1716 | /* Most mips16 branch insns don't have a delay slot. | |
1717 | If a read from LO is immediately followed by a branch | |
1718 | to a write to LO we have a read followed by a write | |
1719 | less than 2 insns away. We assume the target of | |
1720 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1721 | between a read and an immediately following branch. */ |
252b5132 RH |
1722 | else if (mips_opts.mips16 |
1723 | && (mips_optimize == 0 | |
1724 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1725 | ++nops; |
252b5132 RH |
1726 | } |
1727 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1728 | { | |
1729 | /* The previous instruction reads the HI register; if the | |
1730 | current instruction writes to the HI register, we must | |
1731 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1732 | Also the note tx39's multiply above. */ |
252b5132 | 1733 | if (! (hilo_interlocks |
ec68c924 | 1734 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1735 | && (mips_optimize == 0 |
1736 | || (pinfo & INSN_WRITE_HI))) | |
1737 | nops += 2; | |
1738 | /* Most mips16 branch insns don't have a delay slot. | |
1739 | If a read from HI is immediately followed by a branch | |
1740 | to a write to HI we have a read followed by a write | |
1741 | less than 2 insns away. We assume the target of | |
1742 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1743 | between a read and an immediately following branch. */ |
252b5132 RH |
1744 | else if (mips_opts.mips16 |
1745 | && (mips_optimize == 0 | |
1746 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1747 | ++nops; |
252b5132 RH |
1748 | } |
1749 | ||
1750 | /* If the previous instruction was in a noreorder section, then | |
1751 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1752 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1753 | if (prev_insn_unreordered) |
1754 | nops = 0; | |
1755 | ||
1756 | /* There are two cases which require two intervening | |
1757 | instructions: 1) setting the condition codes using a move to | |
1758 | coprocessor instruction which requires a general coprocessor | |
1759 | delay and then reading the condition codes 2) reading the HI | |
1760 | or LO register and then writing to it (except on processors | |
1761 | which have interlocks). If we are not already emitting a NOP | |
1762 | instruction, we must check for these cases compared to the | |
1763 | instruction previous to the previous instruction. */ | |
1764 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1765 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1766 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1767 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1768 | && (pinfo & INSN_READ_COND_CODE) | |
1769 | && ! cop_interlocks) | |
1770 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1771 | && (pinfo & INSN_WRITE_LO) | |
1772 | && ! (hilo_interlocks | |
ec68c924 | 1773 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1774 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1775 | && (pinfo & INSN_WRITE_HI) | |
1776 | && ! (hilo_interlocks | |
ec68c924 | 1777 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1778 | prev_prev_nop = 1; |
1779 | else | |
1780 | prev_prev_nop = 0; | |
1781 | ||
1782 | if (prev_prev_insn_unreordered) | |
1783 | prev_prev_nop = 0; | |
1784 | ||
1785 | if (prev_prev_nop && nops == 0) | |
1786 | ++nops; | |
1787 | ||
60b63b72 RS |
1788 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
1789 | { | |
1790 | /* We're out of bits in pinfo, so we must resort to string | |
1791 | ops here. Shortcuts are selected based on opcodes being | |
1792 | limited to the VR4122 instruction set. */ | |
1793 | int min_nops = 0; | |
1794 | const char *pn = prev_insn.insn_mo->name; | |
1795 | const char *tn = ip->insn_mo->name; | |
1796 | if (strncmp(pn, "macc", 4) == 0 | |
1797 | || strncmp(pn, "dmacc", 5) == 0) | |
1798 | { | |
1799 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1800 | if (strstr (tn, "div")) | |
1801 | { | |
1802 | min_nops = 1; | |
1803 | } | |
1804 | ||
1805 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ | |
1806 | if (pn[0] == 'd' /* dmacc */ | |
1807 | && (strncmp(tn, "dmult", 5) == 0 | |
1808 | || strncmp(tn, "dmacc", 5) == 0)) | |
1809 | { | |
1810 | min_nops = 1; | |
1811 | } | |
1812 | ||
1813 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1814 | if (strcmp (tn, "mtlo") == 0 | |
1815 | || strcmp (tn, "mthi") == 0) | |
1816 | { | |
1817 | min_nops = 1; | |
1818 | } | |
1819 | ||
1820 | } | |
1821 | else if (strncmp(pn, "dmult", 5) == 0 | |
1822 | && (strncmp(tn, "dmult", 5) == 0 | |
1823 | || strncmp(tn, "dmacc", 5) == 0)) | |
1824 | { | |
1825 | /* Here is the rest of errata 23. */ | |
1826 | min_nops = 1; | |
1827 | } | |
1828 | if (nops < min_nops) | |
1829 | nops = min_nops; | |
1830 | } | |
1831 | ||
252b5132 RH |
1832 | /* If we are being given a nop instruction, don't bother with |
1833 | one of the nops we would otherwise output. This will only | |
1834 | happen when a nop instruction is used with mips_optimize set | |
1835 | to 0. */ | |
1836 | if (nops > 0 | |
1837 | && ! mips_opts.noreorder | |
156c2f8b | 1838 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1839 | --nops; |
1840 | ||
1841 | /* Now emit the right number of NOP instructions. */ | |
1842 | if (nops > 0 && ! mips_opts.noreorder) | |
1843 | { | |
1844 | fragS *old_frag; | |
1845 | unsigned long old_frag_offset; | |
1846 | int i; | |
1847 | struct insn_label_list *l; | |
1848 | ||
1849 | old_frag = frag_now; | |
1850 | old_frag_offset = frag_now_fix (); | |
1851 | ||
1852 | for (i = 0; i < nops; i++) | |
1853 | emit_nop (); | |
1854 | ||
1855 | if (listing) | |
1856 | { | |
1857 | listing_prev_line (); | |
1858 | /* We may be at the start of a variant frag. In case we | |
1859 | are, make sure there is enough space for the frag | |
1860 | after the frags created by listing_prev_line. The | |
1861 | argument to frag_grow here must be at least as large | |
1862 | as the argument to all other calls to frag_grow in | |
1863 | this file. We don't have to worry about being in the | |
1864 | middle of a variant frag, because the variants insert | |
1865 | all needed nop instructions themselves. */ | |
1866 | frag_grow (40); | |
1867 | } | |
1868 | ||
1869 | for (l = insn_labels; l != NULL; l = l->next) | |
1870 | { | |
98aa84af AM |
1871 | valueT val; |
1872 | ||
252b5132 | 1873 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1874 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1875 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1876 | /* mips16 text labels are stored as odd. */ |
1877 | if (mips_opts.mips16) | |
f9419b05 | 1878 | ++val; |
98aa84af | 1879 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1880 | } |
1881 | ||
1882 | #ifndef NO_ECOFF_DEBUGGING | |
1883 | if (ECOFF_DEBUGGING) | |
1884 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1885 | #endif | |
1886 | } | |
1887 | else if (prev_nop_frag != NULL) | |
1888 | { | |
1889 | /* We have a frag holding nops we may be able to remove. If | |
1890 | we don't need any nops, we can decrease the size of | |
1891 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1892 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1893 | if (prev_nop_frag_since == 0) |
1894 | { | |
1895 | if (nops == 0) | |
1896 | { | |
1897 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1898 | --prev_nop_frag_holds; | |
1899 | } | |
1900 | else | |
1901 | prev_nop_frag_required += nops; | |
1902 | } | |
1903 | else | |
1904 | { | |
1905 | if (prev_prev_nop == 0) | |
1906 | { | |
1907 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1908 | --prev_nop_frag_holds; | |
1909 | } | |
1910 | else | |
1911 | ++prev_nop_frag_required; | |
1912 | } | |
1913 | ||
1914 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1915 | prev_nop_frag = NULL; | |
1916 | ||
1917 | ++prev_nop_frag_since; | |
1918 | ||
1919 | /* Sanity check: by the time we reach the second instruction | |
1920 | after prev_nop_frag, we should have used up all the nops | |
1921 | one way or another. */ | |
1922 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1923 | } | |
1924 | } | |
1925 | ||
4a6a3df4 AO |
1926 | if (place == NULL |
1927 | && address_expr | |
0b25d3e6 | 1928 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
1929 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
1930 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
1931 | && mips_relax_branch | |
1932 | /* Don't try branch relaxation within .set nomacro, or within | |
1933 | .set noat if we use $at for PIC computations. If it turns | |
1934 | out that the branch was out-of-range, we'll get an error. */ | |
1935 | && !mips_opts.warn_about_macros | |
1936 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
1937 | && !mips_opts.mips16) | |
1938 | { | |
1939 | f = frag_var (rs_machine_dependent, | |
1940 | relaxed_branch_length | |
1941 | (NULL, NULL, | |
1942 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
1943 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
1944 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 1945 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
1946 | pinfo & INSN_COND_BRANCH_LIKELY, |
1947 | pinfo & INSN_WRITE_GPR_31, | |
1948 | 0), | |
1949 | address_expr->X_add_symbol, | |
1950 | address_expr->X_add_number, | |
1951 | 0); | |
1952 | *reloc_type = BFD_RELOC_UNUSED; | |
1953 | } | |
1954 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
1955 | { |
1956 | /* We need to set up a variant frag. */ | |
1957 | assert (mips_opts.mips16 && address_expr != NULL); | |
1958 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 1959 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
1960 | mips16_small, mips16_ext, |
1961 | (prev_pinfo | |
1962 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 1963 | (*prev_insn_reloc_type |
252b5132 | 1964 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 1965 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
1966 | } |
1967 | else if (place != NULL) | |
1968 | f = place; | |
1969 | else if (mips_opts.mips16 | |
1970 | && ! ip->use_extend | |
f6688943 | 1971 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
1972 | { |
1973 | /* Make sure there is enough room to swap this instruction with | |
1974 | a following jump instruction. */ | |
1975 | frag_grow (6); | |
1976 | f = frag_more (2); | |
1977 | } | |
1978 | else | |
1979 | { | |
1980 | if (mips_opts.mips16 | |
1981 | && mips_opts.noreorder | |
1982 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1983 | as_warn (_("extended instruction in delay slot")); | |
1984 | ||
1985 | f = frag_more (4); | |
1986 | } | |
1987 | ||
f6688943 TS |
1988 | fixp[0] = fixp[1] = fixp[2] = NULL; |
1989 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
1990 | { |
1991 | if (address_expr->X_op == O_constant) | |
1992 | { | |
4db1a35d | 1993 | valueT tmp; |
f6688943 TS |
1994 | |
1995 | switch (*reloc_type) | |
252b5132 RH |
1996 | { |
1997 | case BFD_RELOC_32: | |
1998 | ip->insn_opcode |= address_expr->X_add_number; | |
1999 | break; | |
2000 | ||
f6688943 | 2001 | case BFD_RELOC_MIPS_HIGHEST: |
6344efa4 AM |
2002 | tmp = (address_expr->X_add_number |
2003 | + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; | |
f6688943 TS |
2004 | tmp >>= 16; |
2005 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2006 | break; | |
2007 | ||
2008 | case BFD_RELOC_MIPS_HIGHER: | |
2009 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2010 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2011 | break; | |
2012 | ||
2013 | case BFD_RELOC_HI16_S: | |
2014 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2015 | >> 16) & 0xffff; | |
2016 | break; | |
2017 | ||
2018 | case BFD_RELOC_HI16: | |
2019 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2020 | break; | |
2021 | ||
252b5132 | 2022 | case BFD_RELOC_LO16: |
ed6fb7bd | 2023 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2024 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2025 | break; | |
2026 | ||
2027 | case BFD_RELOC_MIPS_JMP: | |
2028 | if ((address_expr->X_add_number & 3) != 0) | |
2029 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2030 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2031 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2032 | as_bad (_("jump address range overflow (0x%lx)"), |
2033 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2034 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2035 | break; | |
2036 | ||
2037 | case BFD_RELOC_MIPS16_JMP: | |
2038 | if ((address_expr->X_add_number & 3) != 0) | |
2039 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2040 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2041 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2042 | as_bad (_("jump address range overflow (0x%lx)"), |
2043 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2044 | ip->insn_opcode |= |
2045 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2046 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2047 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2048 | break; | |
2049 | ||
252b5132 RH |
2050 | case BFD_RELOC_16_PCREL_S2: |
2051 | goto need_reloc; | |
2052 | ||
2053 | default: | |
2054 | internalError (); | |
2055 | } | |
2056 | } | |
2057 | else | |
2058 | { | |
2059 | need_reloc: | |
f6688943 | 2060 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2061 | if (place == NULL) |
2062 | { | |
34ce925e RS |
2063 | reloc_howto_type *howto; |
2064 | int i; | |
2065 | ||
2066 | /* In a compound relocation, it is the final (outermost) | |
2067 | operator that determines the relocated field. */ | |
2068 | for (i = 1; i < 3; i++) | |
2069 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2070 | break; | |
2071 | ||
2072 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); | |
a105a300 TS |
2073 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, |
2074 | bfd_get_reloc_size(howto), | |
f6688943 | 2075 | address_expr, |
a105a300 | 2076 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, |
f6688943 TS |
2077 | reloc_type[0]); |
2078 | ||
b6ff326e | 2079 | /* These relocations can have an addend that won't fit in |
f6688943 | 2080 | 4 octets for 64bit assembly. */ |
a105a300 TS |
2081 | if (HAVE_64BIT_GPRS |
2082 | && ! howto->partial_inplace | |
2083 | && (reloc_type[0] == BFD_RELOC_16 | |
2084 | || reloc_type[0] == BFD_RELOC_32 | |
2085 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2086 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2087 | || reloc_type[0] == BFD_RELOC_LO16 | |
2088 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2089 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2090 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2091 | || reloc_type[0] == BFD_RELOC_64 | |
2092 | || reloc_type[0] == BFD_RELOC_CTOR | |
2093 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2094 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2095 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2096 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2097 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2098 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2099 | fixp[0]->fx_no_overflow = 1; |
2100 | ||
5919d012 | 2101 | if (reloc_needs_lo_p (*reloc_type)) |
252b5132 RH |
2102 | { |
2103 | struct mips_hi_fixup *hi_fixup; | |
2104 | ||
5919d012 RS |
2105 | /* Reuse the last entry if it already has a matching %lo. */ |
2106 | hi_fixup = mips_hi_fixup_list; | |
2107 | if (hi_fixup == 0 | |
2108 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2109 | { | |
2110 | hi_fixup = ((struct mips_hi_fixup *) | |
2111 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2112 | hi_fixup->next = mips_hi_fixup_list; | |
2113 | mips_hi_fixup_list = hi_fixup; | |
2114 | } | |
f6688943 | 2115 | hi_fixup->fixp = fixp[0]; |
252b5132 | 2116 | hi_fixup->seg = now_seg; |
252b5132 | 2117 | } |
f6688943 | 2118 | |
34ce925e RS |
2119 | /* Add fixups for the second and third relocations, if given. |
2120 | Note that the ABI allows the second relocation to be | |
2121 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2122 | moment we only use RSS_UNDEF, but we could add support | |
2123 | for the others if it ever becomes necessary. */ | |
2124 | for (i = 1; i < 3; i++) | |
2125 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2126 | { | |
2127 | address_expr->X_op = O_absent; | |
2128 | address_expr->X_add_symbol = 0; | |
2129 | address_expr->X_add_number = 0; | |
2130 | ||
2131 | fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, | |
2132 | fixp[0]->fx_size, address_expr, | |
2133 | FALSE, reloc_type[i]); | |
2134 | } | |
252b5132 RH |
2135 | } |
2136 | } | |
2137 | } | |
2138 | ||
2139 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2140 | { |
2141 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2142 | #ifdef OBJ_ELF | |
2143 | dwarf2_emit_insn (4); | |
2144 | #endif | |
2145 | } | |
f6688943 | 2146 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2147 | { |
2148 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2149 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2150 | #ifdef OBJ_ELF |
2151 | dwarf2_emit_insn (4); | |
2152 | #endif | |
252b5132 RH |
2153 | } |
2154 | else | |
2155 | { | |
2156 | if (ip->use_extend) | |
2157 | { | |
2158 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2159 | f += 2; | |
2160 | } | |
2161 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2162 | #ifdef OBJ_ELF |
2163 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2164 | #endif | |
252b5132 RH |
2165 | } |
2166 | ||
2167 | /* Update the register mask information. */ | |
2168 | if (! mips_opts.mips16) | |
2169 | { | |
2170 | if (pinfo & INSN_WRITE_GPR_D) | |
2171 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2172 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2173 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2174 | if (pinfo & INSN_READ_GPR_S) | |
2175 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2176 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2177 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2178 | if (pinfo & INSN_WRITE_FPR_D) |
2179 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2180 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2181 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2182 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2183 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2184 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2185 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2186 | if (pinfo & INSN_COP) | |
2187 | { | |
bdaaa2e1 KH |
2188 | /* We don't keep enough information to sort these cases out. |
2189 | The itbl support does keep this information however, although | |
2190 | we currently don't support itbl fprmats as part of the cop | |
2191 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2192 | } |
2193 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2194 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2195 | } |
2196 | else | |
2197 | { | |
2198 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2199 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2200 | & MIPS16OP_MASK_RX); | |
2201 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2202 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2203 | & MIPS16OP_MASK_RY); | |
2204 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2205 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2206 | & MIPS16OP_MASK_RZ); | |
2207 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2208 | mips_gprmask |= 1 << TREG; | |
2209 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2210 | mips_gprmask |= 1 << SP; | |
2211 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2212 | mips_gprmask |= 1 << RA; | |
2213 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2214 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2215 | if (pinfo & MIPS16_INSN_READ_Z) | |
2216 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2217 | & MIPS16OP_MASK_MOVE32Z); | |
2218 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2219 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2220 | & MIPS16OP_MASK_REGR32); | |
2221 | } | |
2222 | ||
2223 | if (place == NULL && ! mips_opts.noreorder) | |
2224 | { | |
2225 | /* Filling the branch delay slot is more complex. We try to | |
2226 | switch the branch with the previous instruction, which we can | |
2227 | do if the previous instruction does not set up a condition | |
2228 | that the branch tests and if the branch is not itself the | |
2229 | target of any branch. */ | |
2230 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2231 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2232 | { | |
2233 | if (mips_optimize < 2 | |
2234 | /* If we have seen .set volatile or .set nomove, don't | |
2235 | optimize. */ | |
2236 | || mips_opts.nomove != 0 | |
2237 | /* If we had to emit any NOP instructions, then we | |
2238 | already know we can not swap. */ | |
2239 | || nops != 0 | |
2240 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2241 | swap. */ |
252b5132 RH |
2242 | || ! prev_insn_valid |
2243 | /* If the previous insn is already in a branch delay | |
2244 | slot, then we can not swap. */ | |
2245 | || prev_insn_is_delay_slot | |
2246 | /* If the previous previous insn was in a .set | |
2247 | noreorder, we can't swap. Actually, the MIPS | |
2248 | assembler will swap in this situation. However, gcc | |
2249 | configured -with-gnu-as will generate code like | |
2250 | .set noreorder | |
2251 | lw $4,XXX | |
2252 | .set reorder | |
2253 | INSN | |
2254 | bne $4,$0,foo | |
2255 | in which we can not swap the bne and INSN. If gcc is | |
2256 | not configured -with-gnu-as, it does not output the | |
2257 | .set pseudo-ops. We don't have to check | |
2258 | prev_insn_unreordered, because prev_insn_valid will | |
2259 | be 0 in that case. We don't want to use | |
2260 | prev_prev_insn_valid, because we do want to be able | |
2261 | to swap at the start of a function. */ | |
2262 | || prev_prev_insn_unreordered | |
2263 | /* If the branch is itself the target of a branch, we | |
2264 | can not swap. We cheat on this; all we check for is | |
2265 | whether there is a label on this instruction. If | |
2266 | there are any branches to anything other than a | |
2267 | label, users must use .set noreorder. */ | |
2268 | || insn_labels != NULL | |
2269 | /* If the previous instruction is in a variant frag, we | |
2270 | can not do the swap. This does not apply to the | |
2271 | mips16, which uses variant frags for different | |
2272 | purposes. */ | |
2273 | || (! mips_opts.mips16 | |
2274 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2275 | /* If the branch reads the condition codes, we don't | |
2276 | even try to swap, because in the sequence | |
2277 | ctc1 $X,$31 | |
2278 | INSN | |
2279 | INSN | |
2280 | bc1t LABEL | |
2281 | we can not swap, and I don't feel like handling that | |
2282 | case. */ | |
2283 | || (! mips_opts.mips16 | |
9ce8a5dd | 2284 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2285 | && (pinfo & INSN_READ_COND_CODE)) |
2286 | /* We can not swap with an instruction that requires a | |
2287 | delay slot, becase the target of the branch might | |
2288 | interfere with that instruction. */ | |
2289 | || (! mips_opts.mips16 | |
9ce8a5dd | 2290 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2291 | && (prev_pinfo |
bdaaa2e1 | 2292 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2293 | & (INSN_LOAD_COPROC_DELAY |
2294 | | INSN_COPROC_MOVE_DELAY | |
2295 | | INSN_WRITE_COND_CODE))) | |
2296 | || (! (hilo_interlocks | |
ec68c924 | 2297 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2298 | && (prev_pinfo |
2299 | & (INSN_READ_LO | |
2300 | | INSN_READ_HI))) | |
2301 | || (! mips_opts.mips16 | |
2302 | && ! gpr_interlocks | |
2303 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2304 | || (! mips_opts.mips16 | |
e7af610e | 2305 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2306 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2307 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2308 | /* We can not swap with a branch instruction. */ | |
2309 | || (prev_pinfo | |
2310 | & (INSN_UNCOND_BRANCH_DELAY | |
2311 | | INSN_COND_BRANCH_DELAY | |
2312 | | INSN_COND_BRANCH_LIKELY)) | |
2313 | /* We do not swap with a trap instruction, since it | |
2314 | complicates trap handlers to have the trap | |
2315 | instruction be in a delay slot. */ | |
2316 | || (prev_pinfo & INSN_TRAP) | |
2317 | /* If the branch reads a register that the previous | |
2318 | instruction sets, we can not swap. */ | |
2319 | || (! mips_opts.mips16 | |
2320 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2321 | && insn_uses_reg (ip, | |
2322 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2323 | & OP_MASK_RT), | |
2324 | MIPS_GR_REG)) | |
2325 | || (! mips_opts.mips16 | |
2326 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2327 | && insn_uses_reg (ip, | |
2328 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2329 | & OP_MASK_RD), | |
2330 | MIPS_GR_REG)) | |
2331 | || (mips_opts.mips16 | |
2332 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2333 | && insn_uses_reg (ip, | |
2334 | ((prev_insn.insn_opcode | |
2335 | >> MIPS16OP_SH_RX) | |
2336 | & MIPS16OP_MASK_RX), | |
2337 | MIPS16_REG)) | |
2338 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2339 | && insn_uses_reg (ip, | |
2340 | ((prev_insn.insn_opcode | |
2341 | >> MIPS16OP_SH_RY) | |
2342 | & MIPS16OP_MASK_RY), | |
2343 | MIPS16_REG)) | |
2344 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2345 | && insn_uses_reg (ip, | |
2346 | ((prev_insn.insn_opcode | |
2347 | >> MIPS16OP_SH_RZ) | |
2348 | & MIPS16OP_MASK_RZ), | |
2349 | MIPS16_REG)) | |
2350 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2351 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2352 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2353 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2354 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2355 | && insn_uses_reg (ip, | |
2356 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2357 | insn_opcode), | |
2358 | MIPS_GR_REG)))) | |
2359 | /* If the branch writes a register that the previous | |
2360 | instruction sets, we can not swap (we know that | |
2361 | branches write only to RD or to $31). */ | |
2362 | || (! mips_opts.mips16 | |
2363 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2364 | && (((pinfo & INSN_WRITE_GPR_D) | |
2365 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2366 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2367 | || ((pinfo & INSN_WRITE_GPR_31) | |
2368 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2369 | & OP_MASK_RT) | |
f9419b05 | 2370 | == RA)))) |
252b5132 RH |
2371 | || (! mips_opts.mips16 |
2372 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2373 | && (((pinfo & INSN_WRITE_GPR_D) | |
2374 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2375 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2376 | || ((pinfo & INSN_WRITE_GPR_31) | |
2377 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2378 | & OP_MASK_RD) | |
f9419b05 | 2379 | == RA)))) |
252b5132 RH |
2380 | || (mips_opts.mips16 |
2381 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2382 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2383 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2384 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2385 | == RA)))) | |
2386 | /* If the branch writes a register that the previous | |
2387 | instruction reads, we can not swap (we know that | |
2388 | branches only write to RD or to $31). */ | |
2389 | || (! mips_opts.mips16 | |
2390 | && (pinfo & INSN_WRITE_GPR_D) | |
2391 | && insn_uses_reg (&prev_insn, | |
2392 | ((ip->insn_opcode >> OP_SH_RD) | |
2393 | & OP_MASK_RD), | |
2394 | MIPS_GR_REG)) | |
2395 | || (! mips_opts.mips16 | |
2396 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2397 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2398 | || (mips_opts.mips16 |
2399 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2400 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2401 | /* If we are generating embedded PIC code, the branch | |
2402 | might be expanded into a sequence which uses $at, so | |
2403 | we can't swap with an instruction which reads it. */ | |
2404 | || (mips_pic == EMBEDDED_PIC | |
2405 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2406 | /* If the previous previous instruction has a load | |
2407 | delay, and sets a register that the branch reads, we | |
2408 | can not swap. */ | |
2409 | || (! mips_opts.mips16 | |
9ce8a5dd | 2410 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2411 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2412 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2413 | || (! gpr_interlocks | |
2414 | && (prev_prev_insn.insn_mo->pinfo | |
2415 | & INSN_LOAD_MEMORY_DELAY))) | |
2416 | && insn_uses_reg (ip, | |
2417 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2418 | & OP_MASK_RT), | |
2419 | MIPS_GR_REG)) | |
2420 | /* If one instruction sets a condition code and the | |
2421 | other one uses a condition code, we can not swap. */ | |
2422 | || ((pinfo & INSN_READ_COND_CODE) | |
2423 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2424 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2425 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2426 | /* If the previous instruction uses the PC, we can not | |
2427 | swap. */ | |
2428 | || (mips_opts.mips16 | |
2429 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2430 | /* If the previous instruction was extended, we can not | |
2431 | swap. */ | |
2432 | || (mips_opts.mips16 && prev_insn_extended) | |
2433 | /* If the previous instruction had a fixup in mips16 | |
2434 | mode, we can not swap. This normally means that the | |
2435 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2436 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2437 | /* If the previous instruction is a sync, sync.l, or |
2438 | sync.p, we can not swap. */ | |
f173e82e | 2439 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2440 | { |
2441 | /* We could do even better for unconditional branches to | |
2442 | portions of this object file; we could pick up the | |
2443 | instruction at the destination, put it in the delay | |
2444 | slot, and bump the destination address. */ | |
2445 | emit_nop (); | |
2446 | /* Update the previous insn information. */ | |
2447 | prev_prev_insn = *ip; | |
2448 | prev_insn.insn_mo = &dummy_opcode; | |
2449 | } | |
2450 | else | |
2451 | { | |
2452 | /* It looks like we can actually do the swap. */ | |
2453 | if (! mips_opts.mips16) | |
2454 | { | |
2455 | char *prev_f; | |
2456 | char temp[4]; | |
2457 | ||
2458 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2459 | memcpy (temp, prev_f, 4); | |
2460 | memcpy (prev_f, f, 4); | |
2461 | memcpy (f, temp, 4); | |
f6688943 TS |
2462 | if (prev_insn_fixp[0]) |
2463 | { | |
2464 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2465 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2466 | } | |
2467 | if (prev_insn_fixp[1]) | |
2468 | { | |
2469 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2470 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2471 | } | |
2472 | if (prev_insn_fixp[2]) | |
252b5132 | 2473 | { |
f6688943 TS |
2474 | prev_insn_fixp[2]->fx_frag = frag_now; |
2475 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2476 | } |
f5040a92 AO |
2477 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2478 | && prev_insn_frag != frag_now | |
2479 | && (prev_insn_fixp[0]->fx_r_type | |
2480 | == BFD_RELOC_MIPS_GOT_DISP | |
2481 | || (prev_insn_fixp[0]->fx_r_type | |
2482 | == BFD_RELOC_MIPS_CALL16))) | |
2483 | { | |
2484 | /* To avoid confusion in tc_gen_reloc, we must | |
2485 | ensure that this does not become a variant | |
2486 | frag. */ | |
2487 | force_new_frag = TRUE; | |
2488 | } | |
f6688943 | 2489 | if (fixp[0]) |
252b5132 | 2490 | { |
f6688943 TS |
2491 | fixp[0]->fx_frag = prev_insn_frag; |
2492 | fixp[0]->fx_where = prev_insn_where; | |
2493 | } | |
2494 | if (fixp[1]) | |
2495 | { | |
2496 | fixp[1]->fx_frag = prev_insn_frag; | |
2497 | fixp[1]->fx_where = prev_insn_where; | |
2498 | } | |
2499 | if (fixp[2]) | |
2500 | { | |
2501 | fixp[2]->fx_frag = prev_insn_frag; | |
2502 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2503 | } |
2504 | } | |
2505 | else | |
2506 | { | |
2507 | char *prev_f; | |
2508 | char temp[2]; | |
2509 | ||
f6688943 TS |
2510 | assert (prev_insn_fixp[0] == NULL); |
2511 | assert (prev_insn_fixp[1] == NULL); | |
2512 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2513 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2514 | memcpy (temp, prev_f, 2); | |
2515 | memcpy (prev_f, f, 2); | |
f6688943 | 2516 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2517 | { |
f6688943 | 2518 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2519 | memcpy (f, temp, 2); |
2520 | } | |
2521 | else | |
2522 | { | |
2523 | memcpy (f, f + 2, 2); | |
2524 | memcpy (f + 2, temp, 2); | |
2525 | } | |
f6688943 TS |
2526 | if (fixp[0]) |
2527 | { | |
2528 | fixp[0]->fx_frag = prev_insn_frag; | |
2529 | fixp[0]->fx_where = prev_insn_where; | |
2530 | } | |
2531 | if (fixp[1]) | |
2532 | { | |
2533 | fixp[1]->fx_frag = prev_insn_frag; | |
2534 | fixp[1]->fx_where = prev_insn_where; | |
2535 | } | |
2536 | if (fixp[2]) | |
252b5132 | 2537 | { |
f6688943 TS |
2538 | fixp[2]->fx_frag = prev_insn_frag; |
2539 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2540 | } |
2541 | } | |
2542 | ||
2543 | /* Update the previous insn information; leave prev_insn | |
2544 | unchanged. */ | |
2545 | prev_prev_insn = *ip; | |
2546 | } | |
2547 | prev_insn_is_delay_slot = 1; | |
2548 | ||
2549 | /* If that was an unconditional branch, forget the previous | |
2550 | insn information. */ | |
2551 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2552 | { | |
2553 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2554 | prev_insn.insn_mo = &dummy_opcode; | |
2555 | } | |
2556 | ||
f6688943 TS |
2557 | prev_insn_fixp[0] = NULL; |
2558 | prev_insn_fixp[1] = NULL; | |
2559 | prev_insn_fixp[2] = NULL; | |
2560 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2561 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2562 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2563 | prev_insn_extended = 0; |
2564 | } | |
2565 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2566 | { | |
2567 | /* We don't yet optimize a branch likely. What we should do | |
2568 | is look at the target, copy the instruction found there | |
2569 | into the delay slot, and increment the branch to jump to | |
2570 | the next instruction. */ | |
2571 | emit_nop (); | |
2572 | /* Update the previous insn information. */ | |
2573 | prev_prev_insn = *ip; | |
2574 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2575 | prev_insn_fixp[0] = NULL; |
2576 | prev_insn_fixp[1] = NULL; | |
2577 | prev_insn_fixp[2] = NULL; | |
2578 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2579 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2580 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2581 | prev_insn_extended = 0; |
2582 | } | |
2583 | else | |
2584 | { | |
2585 | /* Update the previous insn information. */ | |
2586 | if (nops > 0) | |
2587 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2588 | else | |
2589 | prev_prev_insn = prev_insn; | |
2590 | prev_insn = *ip; | |
2591 | ||
2592 | /* Any time we see a branch, we always fill the delay slot | |
2593 | immediately; since this insn is not a branch, we know it | |
2594 | is not in a delay slot. */ | |
2595 | prev_insn_is_delay_slot = 0; | |
2596 | ||
f6688943 TS |
2597 | prev_insn_fixp[0] = fixp[0]; |
2598 | prev_insn_fixp[1] = fixp[1]; | |
2599 | prev_insn_fixp[2] = fixp[2]; | |
2600 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2601 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2602 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2603 | if (mips_opts.mips16) |
2604 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2605 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2606 | } |
2607 | ||
2608 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2609 | prev_insn_unreordered = 0; | |
2610 | prev_insn_frag = frag_now; | |
2611 | prev_insn_where = f - frag_now->fr_literal; | |
2612 | prev_insn_valid = 1; | |
2613 | } | |
2614 | else if (place == NULL) | |
2615 | { | |
2616 | /* We need to record a bit of information even when we are not | |
2617 | reordering, in order to determine the base address for mips16 | |
2618 | PC relative relocs. */ | |
2619 | prev_prev_insn = prev_insn; | |
2620 | prev_insn = *ip; | |
f6688943 TS |
2621 | prev_insn_reloc_type[0] = reloc_type[0]; |
2622 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2623 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2624 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2625 | prev_insn_unreordered = 1; | |
2626 | } | |
2627 | ||
2628 | /* We just output an insn, so the next one doesn't have a label. */ | |
2629 | mips_clear_insn_labels (); | |
f5040a92 AO |
2630 | |
2631 | /* We must ensure that the frag to which an instruction that was | |
2632 | moved from a non-variant frag doesn't become a variant frag, | |
2633 | otherwise tc_gen_reloc may get confused. */ | |
2634 | if (force_new_frag) | |
2635 | { | |
2636 | frag_wane (frag_now); | |
2637 | frag_new (0); | |
2638 | } | |
252b5132 RH |
2639 | } |
2640 | ||
2641 | /* This function forgets that there was any previous instruction or | |
2642 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2643 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2644 | |
2645 | static void | |
17a2f251 | 2646 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2647 | { |
2648 | if (! preserve) | |
2649 | { | |
2650 | prev_insn.insn_mo = &dummy_opcode; | |
2651 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2652 | prev_nop_frag = NULL; | |
2653 | prev_nop_frag_holds = 0; | |
2654 | prev_nop_frag_required = 0; | |
2655 | prev_nop_frag_since = 0; | |
2656 | } | |
2657 | prev_insn_valid = 0; | |
2658 | prev_insn_is_delay_slot = 0; | |
2659 | prev_insn_unreordered = 0; | |
2660 | prev_insn_extended = 0; | |
f6688943 TS |
2661 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2662 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2663 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2664 | prev_prev_insn_unreordered = 0; |
2665 | mips_clear_insn_labels (); | |
2666 | } | |
2667 | ||
2668 | /* This function must be called whenever we turn on noreorder or emit | |
2669 | something other than instructions. It inserts any NOPS which might | |
2670 | be needed by the previous instruction, and clears the information | |
2671 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2672 | instructions are to follow. */ |
252b5132 RH |
2673 | |
2674 | static void | |
17a2f251 | 2675 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2676 | { |
2677 | if (! mips_opts.noreorder) | |
2678 | { | |
2679 | int nops; | |
2680 | ||
2681 | nops = 0; | |
2682 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2683 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2684 | && (! cop_interlocks |
2685 | && (prev_insn.insn_mo->pinfo | |
2686 | & (INSN_LOAD_COPROC_DELAY | |
2687 | | INSN_COPROC_MOVE_DELAY | |
2688 | | INSN_WRITE_COND_CODE)))) | |
2689 | || (! hilo_interlocks | |
2690 | && (prev_insn.insn_mo->pinfo | |
2691 | & (INSN_READ_LO | |
2692 | | INSN_READ_HI))) | |
2693 | || (! mips_opts.mips16 | |
2694 | && ! gpr_interlocks | |
bdaaa2e1 | 2695 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2696 | & INSN_LOAD_MEMORY_DELAY)) |
2697 | || (! mips_opts.mips16 | |
e7af610e | 2698 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2699 | && (prev_insn.insn_mo->pinfo |
2700 | & INSN_COPROC_MEMORY_DELAY))) | |
2701 | { | |
beae10d5 | 2702 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2703 | ++nops; |
2704 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2705 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2706 | && (! cop_interlocks |
2707 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2708 | || (! hilo_interlocks | |
2709 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2710 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2711 | ++nops; | |
2712 | ||
2713 | if (prev_insn_unreordered) | |
2714 | nops = 0; | |
2715 | } | |
2716 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2717 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2718 | && (! cop_interlocks |
2719 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2720 | || (! hilo_interlocks | |
2721 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2722 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2723 | { | |
beae10d5 | 2724 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2725 | if (! prev_prev_insn_unreordered) |
2726 | ++nops; | |
2727 | } | |
2728 | ||
60b63b72 RS |
2729 | if (mips_fix_4122_bugs && prev_insn.insn_mo->name) |
2730 | { | |
2731 | int min_nops = 0; | |
2732 | const char *pn = prev_insn.insn_mo->name; | |
2733 | if (strncmp(pn, "macc", 4) == 0 | |
2734 | || strncmp(pn, "dmacc", 5) == 0 | |
2735 | || strncmp(pn, "dmult", 5) == 0) | |
2736 | { | |
2737 | min_nops = 1; | |
2738 | } | |
2739 | if (nops < min_nops) | |
2740 | nops = min_nops; | |
2741 | } | |
2742 | ||
252b5132 RH |
2743 | if (nops > 0) |
2744 | { | |
2745 | struct insn_label_list *l; | |
2746 | ||
2747 | if (insns) | |
2748 | { | |
2749 | /* Record the frag which holds the nop instructions, so | |
2750 | that we can remove them if we don't need them. */ | |
2751 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2752 | prev_nop_frag = frag_now; | |
2753 | prev_nop_frag_holds = nops; | |
2754 | prev_nop_frag_required = 0; | |
2755 | prev_nop_frag_since = 0; | |
2756 | } | |
2757 | ||
2758 | for (; nops > 0; --nops) | |
2759 | emit_nop (); | |
2760 | ||
2761 | if (insns) | |
2762 | { | |
2763 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2764 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2765 | frag_wane (frag_now); |
2766 | frag_new (0); | |
2767 | } | |
2768 | ||
2769 | for (l = insn_labels; l != NULL; l = l->next) | |
2770 | { | |
98aa84af AM |
2771 | valueT val; |
2772 | ||
252b5132 | 2773 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2774 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2775 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2776 | /* mips16 text labels are stored as odd. */ |
2777 | if (mips_opts.mips16) | |
f9419b05 | 2778 | ++val; |
98aa84af | 2779 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2780 | } |
2781 | } | |
2782 | } | |
2783 | ||
2784 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2785 | if (insns) |
252b5132 RH |
2786 | mips16_mark_labels (); |
2787 | ||
2788 | mips_no_prev_insn (insns); | |
2789 | } | |
2790 | ||
2791 | /* Build an instruction created by a macro expansion. This is passed | |
2792 | a pointer to the count of instructions created so far, an | |
2793 | expression, the name of the instruction to build, an operand format | |
2794 | string, and corresponding arguments. */ | |
2795 | ||
252b5132 | 2796 | static void |
17a2f251 TS |
2797 | macro_build (char *place, int *counter, expressionS *ep, const char *name, |
2798 | const char *fmt, ...) | |
252b5132 RH |
2799 | { |
2800 | struct mips_cl_insn insn; | |
f6688943 | 2801 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2802 | va_list args; |
252b5132 | 2803 | |
252b5132 | 2804 | va_start (args, fmt); |
252b5132 RH |
2805 | |
2806 | /* | |
2807 | * If the macro is about to expand into a second instruction, | |
2808 | * print a warning if needed. We need to pass ip as a parameter | |
2809 | * to generate a better warning message here... | |
2810 | */ | |
2811 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2812 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2813 | ||
80cc45a5 EC |
2814 | /* |
2815 | * If the macro is about to expand into a second instruction, | |
2816 | * and it is in a delay slot, print a warning. | |
2817 | */ | |
2818 | if (place == NULL | |
2819 | && *counter == 1 | |
2820 | && mips_opts.noreorder | |
2821 | && (prev_prev_insn.insn_mo->pinfo | |
2822 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2823 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2824 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2825 | ||
252b5132 | 2826 | if (place == NULL) |
f9419b05 | 2827 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2828 | |
2829 | if (mips_opts.mips16) | |
2830 | { | |
2831 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2832 | va_end (args); | |
2833 | return; | |
2834 | } | |
2835 | ||
f6688943 TS |
2836 | r[0] = BFD_RELOC_UNUSED; |
2837 | r[1] = BFD_RELOC_UNUSED; | |
2838 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2839 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2840 | assert (insn.insn_mo); | |
2841 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2842 | ||
2843 | /* Search until we get a match for NAME. */ | |
2844 | while (1) | |
2845 | { | |
b34976b6 | 2846 | /* It is assumed here that macros will never generate |
deec1734 | 2847 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
2848 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2849 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
2850 | && OPCODE_IS_MEMBER (insn.insn_mo, |
2851 | (mips_opts.isa | |
3396de36 | 2852 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
2853 | mips_opts.arch) |
2854 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
2855 | break; |
2856 | ||
2857 | ++insn.insn_mo; | |
2858 | assert (insn.insn_mo->name); | |
2859 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2860 | } | |
2861 | ||
2862 | insn.insn_opcode = insn.insn_mo->match; | |
2863 | for (;;) | |
2864 | { | |
2865 | switch (*fmt++) | |
2866 | { | |
2867 | case '\0': | |
2868 | break; | |
2869 | ||
2870 | case ',': | |
2871 | case '(': | |
2872 | case ')': | |
2873 | continue; | |
2874 | ||
2875 | case 't': | |
2876 | case 'w': | |
2877 | case 'E': | |
38487616 | 2878 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2879 | continue; |
2880 | ||
2881 | case 'c': | |
38487616 TS |
2882 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2883 | continue; | |
2884 | ||
252b5132 RH |
2885 | case 'T': |
2886 | case 'W': | |
38487616 | 2887 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2888 | continue; |
2889 | ||
2890 | case 'd': | |
2891 | case 'G': | |
af7ee8bf | 2892 | case 'K': |
38487616 | 2893 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2894 | continue; |
2895 | ||
4372b673 NC |
2896 | case 'U': |
2897 | { | |
2898 | int tmp = va_arg (args, int); | |
2899 | ||
38487616 TS |
2900 | insn.insn_opcode |= tmp << OP_SH_RT; |
2901 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2902 | continue; |
4372b673 NC |
2903 | } |
2904 | ||
252b5132 RH |
2905 | case 'V': |
2906 | case 'S': | |
38487616 | 2907 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2908 | continue; |
2909 | ||
2910 | case 'z': | |
2911 | continue; | |
2912 | ||
2913 | case '<': | |
38487616 | 2914 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2915 | continue; |
2916 | ||
2917 | case 'D': | |
38487616 | 2918 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
2919 | continue; |
2920 | ||
2921 | case 'B': | |
38487616 | 2922 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
2923 | continue; |
2924 | ||
4372b673 | 2925 | case 'J': |
38487616 | 2926 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
2927 | continue; |
2928 | ||
252b5132 | 2929 | case 'q': |
38487616 | 2930 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
2931 | continue; |
2932 | ||
2933 | case 'b': | |
2934 | case 's': | |
2935 | case 'r': | |
2936 | case 'v': | |
38487616 | 2937 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
2938 | continue; |
2939 | ||
2940 | case 'i': | |
2941 | case 'j': | |
2942 | case 'o': | |
f6688943 | 2943 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 2944 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
2945 | || *r == BFD_RELOC_MIPS_LITERAL |
2946 | || *r == BFD_RELOC_MIPS_HIGHER | |
2947 | || *r == BFD_RELOC_HI16_S | |
2948 | || *r == BFD_RELOC_LO16 | |
2949 | || *r == BFD_RELOC_MIPS_GOT16 | |
2950 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
2951 | || *r == BFD_RELOC_MIPS_GOT_DISP |
2952 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
2953 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
2954 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
2955 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 2956 | || (ep->X_op == O_subtract |
f6688943 | 2957 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
2958 | continue; |
2959 | ||
2960 | case 'u': | |
f6688943 | 2961 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
2962 | assert (ep != NULL |
2963 | && (ep->X_op == O_constant | |
2964 | || (ep->X_op == O_symbol | |
f6688943 TS |
2965 | && (*r == BFD_RELOC_MIPS_HIGHEST |
2966 | || *r == BFD_RELOC_HI16_S | |
2967 | || *r == BFD_RELOC_HI16 | |
2968 | || *r == BFD_RELOC_GPREL16 | |
2969 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
2970 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 2971 | || (ep->X_op == O_subtract |
f6688943 | 2972 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
2973 | continue; |
2974 | ||
2975 | case 'p': | |
2976 | assert (ep != NULL); | |
2977 | /* | |
2978 | * This allows macro() to pass an immediate expression for | |
2979 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
2980 | * Note that the expression still might come from the assembly |
2981 | * input, in which case the value is not checked for range nor | |
2982 | * is a relocation entry generated (yuck). | |
252b5132 RH |
2983 | */ |
2984 | if (ep->X_op == O_constant) | |
2985 | { | |
2986 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2987 | ep = NULL; | |
2988 | } | |
2989 | else | |
0b25d3e6 | 2990 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
2991 | continue; |
2992 | ||
2993 | case 'a': | |
2994 | assert (ep != NULL); | |
f6688943 | 2995 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
2996 | continue; |
2997 | ||
2998 | case 'C': | |
2999 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3000 | continue; | |
3001 | ||
3002 | default: | |
3003 | internalError (); | |
3004 | } | |
3005 | break; | |
3006 | } | |
3007 | va_end (args); | |
f6688943 | 3008 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3009 | |
5e0116d5 | 3010 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3011 | } |
3012 | ||
3013 | static void | |
17a2f251 TS |
3014 | mips16_macro_build (char *place, int *counter ATTRIBUTE_UNUSED, |
3015 | expressionS *ep, const char *name, const char *fmt, | |
3016 | va_list args) | |
252b5132 RH |
3017 | { |
3018 | struct mips_cl_insn insn; | |
f6688943 TS |
3019 | bfd_reloc_code_real_type r[3] |
3020 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3021 | |
252b5132 RH |
3022 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3023 | assert (insn.insn_mo); | |
3024 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3025 | ||
3026 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3027 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3028 | { | |
3029 | ++insn.insn_mo; | |
3030 | assert (insn.insn_mo->name); | |
3031 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3032 | } | |
3033 | ||
3034 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3035 | insn.use_extend = FALSE; |
252b5132 RH |
3036 | |
3037 | for (;;) | |
3038 | { | |
3039 | int c; | |
3040 | ||
3041 | c = *fmt++; | |
3042 | switch (c) | |
3043 | { | |
3044 | case '\0': | |
3045 | break; | |
3046 | ||
3047 | case ',': | |
3048 | case '(': | |
3049 | case ')': | |
3050 | continue; | |
3051 | ||
3052 | case 'y': | |
3053 | case 'w': | |
3054 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3055 | continue; | |
3056 | ||
3057 | case 'x': | |
3058 | case 'v': | |
3059 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3060 | continue; | |
3061 | ||
3062 | case 'z': | |
3063 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3064 | continue; | |
3065 | ||
3066 | case 'Z': | |
3067 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3068 | continue; | |
3069 | ||
3070 | case '0': | |
3071 | case 'S': | |
3072 | case 'P': | |
3073 | case 'R': | |
3074 | continue; | |
3075 | ||
3076 | case 'X': | |
3077 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3078 | continue; | |
3079 | ||
3080 | case 'Y': | |
3081 | { | |
3082 | int regno; | |
3083 | ||
3084 | regno = va_arg (args, int); | |
3085 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3086 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3087 | } | |
3088 | continue; | |
3089 | ||
3090 | case '<': | |
3091 | case '>': | |
3092 | case '4': | |
3093 | case '5': | |
3094 | case 'H': | |
3095 | case 'W': | |
3096 | case 'D': | |
3097 | case 'j': | |
3098 | case '8': | |
3099 | case 'V': | |
3100 | case 'C': | |
3101 | case 'U': | |
3102 | case 'k': | |
3103 | case 'K': | |
3104 | case 'p': | |
3105 | case 'q': | |
3106 | { | |
3107 | assert (ep != NULL); | |
3108 | ||
3109 | if (ep->X_op != O_constant) | |
874e8986 | 3110 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3111 | else |
3112 | { | |
b34976b6 AM |
3113 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3114 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3115 | &insn.extend); |
252b5132 | 3116 | ep = NULL; |
f6688943 | 3117 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3118 | } |
3119 | } | |
3120 | continue; | |
3121 | ||
3122 | case '6': | |
3123 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3124 | continue; | |
3125 | } | |
3126 | ||
3127 | break; | |
3128 | } | |
3129 | ||
f6688943 | 3130 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3131 | |
5e0116d5 | 3132 | append_insn (place, &insn, ep, r); |
252b5132 RH |
3133 | } |
3134 | ||
438c16b8 TS |
3135 | /* |
3136 | * Generate a "jalr" instruction with a relocation hint to the called | |
3137 | * function. This occurs in NewABI PIC code. | |
3138 | */ | |
3139 | static void | |
17a2f251 | 3140 | macro_build_jalr (int icnt, expressionS *ep) |
438c16b8 | 3141 | { |
685736be | 3142 | char *f = NULL; |
b34976b6 | 3143 | |
438c16b8 | 3144 | if (HAVE_NEWABI) |
f21f8242 AO |
3145 | { |
3146 | frag_grow (4); | |
3147 | f = frag_more (0); | |
3148 | } | |
17a2f251 | 3149 | macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3150 | if (HAVE_NEWABI) |
f21f8242 | 3151 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3152 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3153 | } |
3154 | ||
252b5132 RH |
3155 | /* |
3156 | * Generate a "lui" instruction. | |
3157 | */ | |
3158 | static void | |
17a2f251 | 3159 | macro_build_lui (char *place, int *counter, expressionS *ep, int regnum) |
252b5132 RH |
3160 | { |
3161 | expressionS high_expr; | |
3162 | struct mips_cl_insn insn; | |
f6688943 TS |
3163 | bfd_reloc_code_real_type r[3] |
3164 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3165 | const char *name = "lui"; |
3166 | const char *fmt = "t,u"; | |
252b5132 RH |
3167 | |
3168 | assert (! mips_opts.mips16); | |
3169 | ||
3170 | if (place == NULL) | |
3171 | high_expr = *ep; | |
3172 | else | |
3173 | { | |
3174 | high_expr.X_op = O_constant; | |
3175 | high_expr.X_add_number = ep->X_add_number; | |
3176 | } | |
3177 | ||
3178 | if (high_expr.X_op == O_constant) | |
3179 | { | |
3180 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3181 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3182 | >> 16) & 0xffff; | |
f6688943 | 3183 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3184 | } |
78e1bb40 | 3185 | else |
252b5132 RH |
3186 | { |
3187 | assert (ep->X_op == O_symbol); | |
3188 | /* _gp_disp is a special case, used from s_cpload. */ | |
3189 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3190 | || (! HAVE_NEWABI |
3191 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3192 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3193 | } |
3194 | ||
3195 | /* | |
3196 | * If the macro is about to expand into a second instruction, | |
3197 | * print a warning if needed. We need to pass ip as a parameter | |
3198 | * to generate a better warning message here... | |
3199 | */ | |
3200 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3201 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3202 | ||
3203 | if (place == NULL) | |
f9419b05 | 3204 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3205 | |
3206 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3207 | assert (insn.insn_mo); | |
3208 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3209 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3210 | ||
3211 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3212 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3213 | { |
3214 | insn.insn_opcode |= high_expr.X_add_number; | |
5e0116d5 | 3215 | append_insn (place, &insn, NULL, r); |
252b5132 RH |
3216 | } |
3217 | else | |
5e0116d5 | 3218 | append_insn (place, &insn, &high_expr, r); |
252b5132 RH |
3219 | } |
3220 | ||
885add95 CD |
3221 | /* Generate a sequence of instructions to do a load or store from a constant |
3222 | offset off of a base register (breg) into/from a target register (treg), | |
3223 | using AT if necessary. */ | |
3224 | static void | |
17a2f251 | 3225 | macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep, |
256ab948 | 3226 | const char *op, int treg, int breg, int dbl) |
885add95 CD |
3227 | { |
3228 | assert (ep->X_op == O_constant); | |
3229 | ||
256ab948 TS |
3230 | /* Sign-extending 32-bit constants makes their handling easier. */ |
3231 | if (! dbl) | |
ae826530 TS |
3232 | { |
3233 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff) | |
3234 | && ~(ep->X_add_number | 0xffffffff)) | |
3235 | as_bad (_("too large constant specified")); | |
3236 | ||
256ab948 TS |
3237 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3238 | - 0x80000000); | |
ae826530 | 3239 | } |
256ab948 | 3240 | |
885add95 CD |
3241 | /* Right now, this routine can only handle signed 32-bit contants. */ |
3242 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number)) | |
3243 | as_warn (_("operand overflow")); | |
3244 | ||
3245 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3246 | { | |
3247 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
17a2f251 TS |
3248 | macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16, |
3249 | breg); | |
885add95 CD |
3250 | } |
3251 | else | |
3252 | { | |
3253 | /* 32-bit offset, need multiple instructions and AT, like: | |
3254 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3255 | addu $tempreg,$tempreg,$breg | |
3256 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3257 | to handle the complete offset. */ | |
3258 | macro_build_lui (place, counter, ep, AT); | |
3259 | if (place != NULL) | |
3260 | place += 4; | |
17a2f251 TS |
3261 | macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, |
3262 | breg); | |
885add95 CD |
3263 | if (place != NULL) |
3264 | place += 4; | |
17a2f251 TS |
3265 | macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16, |
3266 | AT); | |
885add95 CD |
3267 | |
3268 | if (mips_opts.noat) | |
3269 | as_warn (_("Macro used $at after \".set noat\"")); | |
3270 | } | |
3271 | } | |
3272 | ||
252b5132 RH |
3273 | /* set_at() |
3274 | * Generates code to set the $at register to true (one) | |
3275 | * if reg is less than the immediate expression. | |
3276 | */ | |
3277 | static void | |
17a2f251 | 3278 | set_at (int *counter, int reg, int unsignedp) |
252b5132 RH |
3279 | { |
3280 | if (imm_expr.X_op == O_constant | |
3281 | && imm_expr.X_add_number >= -0x8000 | |
3282 | && imm_expr.X_add_number < 0x8000) | |
17a2f251 TS |
3283 | macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti", |
3284 | "t,r,j", AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3285 | else |
3286 | { | |
4d34fb5f | 3287 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 3288 | macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt", |
252b5132 RH |
3289 | "d,v,t", AT, reg, AT); |
3290 | } | |
3291 | } | |
3292 | ||
3293 | /* Warn if an expression is not a constant. */ | |
3294 | ||
3295 | static void | |
17a2f251 | 3296 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3297 | { |
3298 | if (ex->X_op == O_big) | |
3299 | as_bad (_("unsupported large constant")); | |
3300 | else if (ex->X_op != O_constant) | |
3301 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3302 | } | |
3303 | ||
3304 | /* Count the leading zeroes by performing a binary chop. This is a | |
3305 | bulky bit of source, but performance is a LOT better for the | |
3306 | majority of values than a simple loop to count the bits: | |
3307 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3308 | if ((v) & (1 << (31 - lcnt))) | |
3309 | break; | |
3310 | However it is not code size friendly, and the gain will drop a bit | |
3311 | on certain cached systems. | |
3312 | */ | |
3313 | #define COUNT_TOP_ZEROES(v) \ | |
3314 | (((v) & ~0xffff) == 0 \ | |
3315 | ? ((v) & ~0xff) == 0 \ | |
3316 | ? ((v) & ~0xf) == 0 \ | |
3317 | ? ((v) & ~0x3) == 0 \ | |
3318 | ? ((v) & ~0x1) == 0 \ | |
3319 | ? !(v) \ | |
3320 | ? 32 \ | |
3321 | : 31 \ | |
3322 | : 30 \ | |
3323 | : ((v) & ~0x7) == 0 \ | |
3324 | ? 29 \ | |
3325 | : 28 \ | |
3326 | : ((v) & ~0x3f) == 0 \ | |
3327 | ? ((v) & ~0x1f) == 0 \ | |
3328 | ? 27 \ | |
3329 | : 26 \ | |
3330 | : ((v) & ~0x7f) == 0 \ | |
3331 | ? 25 \ | |
3332 | : 24 \ | |
3333 | : ((v) & ~0xfff) == 0 \ | |
3334 | ? ((v) & ~0x3ff) == 0 \ | |
3335 | ? ((v) & ~0x1ff) == 0 \ | |
3336 | ? 23 \ | |
3337 | : 22 \ | |
3338 | : ((v) & ~0x7ff) == 0 \ | |
3339 | ? 21 \ | |
3340 | : 20 \ | |
3341 | : ((v) & ~0x3fff) == 0 \ | |
3342 | ? ((v) & ~0x1fff) == 0 \ | |
3343 | ? 19 \ | |
3344 | : 18 \ | |
3345 | : ((v) & ~0x7fff) == 0 \ | |
3346 | ? 17 \ | |
3347 | : 16 \ | |
3348 | : ((v) & ~0xffffff) == 0 \ | |
3349 | ? ((v) & ~0xfffff) == 0 \ | |
3350 | ? ((v) & ~0x3ffff) == 0 \ | |
3351 | ? ((v) & ~0x1ffff) == 0 \ | |
3352 | ? 15 \ | |
3353 | : 14 \ | |
3354 | : ((v) & ~0x7ffff) == 0 \ | |
3355 | ? 13 \ | |
3356 | : 12 \ | |
3357 | : ((v) & ~0x3fffff) == 0 \ | |
3358 | ? ((v) & ~0x1fffff) == 0 \ | |
3359 | ? 11 \ | |
3360 | : 10 \ | |
3361 | : ((v) & ~0x7fffff) == 0 \ | |
3362 | ? 9 \ | |
3363 | : 8 \ | |
3364 | : ((v) & ~0xfffffff) == 0 \ | |
3365 | ? ((v) & ~0x3ffffff) == 0 \ | |
3366 | ? ((v) & ~0x1ffffff) == 0 \ | |
3367 | ? 7 \ | |
3368 | : 6 \ | |
3369 | : ((v) & ~0x7ffffff) == 0 \ | |
3370 | ? 5 \ | |
3371 | : 4 \ | |
3372 | : ((v) & ~0x3fffffff) == 0 \ | |
3373 | ? ((v) & ~0x1fffffff) == 0 \ | |
3374 | ? 3 \ | |
3375 | : 2 \ | |
3376 | : ((v) & ~0x7fffffff) == 0 \ | |
3377 | ? 1 \ | |
3378 | : 0) | |
3379 | ||
3380 | /* load_register() | |
3381 | * This routine generates the least number of instructions neccessary to load | |
3382 | * an absolute expression value into a register. | |
3383 | */ | |
3384 | static void | |
17a2f251 | 3385 | load_register (int *counter, int reg, expressionS *ep, int dbl) |
252b5132 RH |
3386 | { |
3387 | int freg; | |
3388 | expressionS hi32, lo32; | |
3389 | ||
3390 | if (ep->X_op != O_big) | |
3391 | { | |
3392 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3393 | |
3394 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
3395 | if (! dbl) | |
ae826530 TS |
3396 | { |
3397 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff) | |
3398 | && ~(ep->X_add_number | 0xffffffff)) | |
3399 | as_bad (_("too large constant specified")); | |
3400 | ||
256ab948 TS |
3401 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3402 | - 0x80000000); | |
ae826530 | 3403 | } |
256ab948 TS |
3404 | |
3405 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3406 | { |
3407 | /* We can handle 16 bit signed values with an addiu to | |
3408 | $zero. No need to ever use daddiu here, since $zero and | |
3409 | the result are always correct in 32 bit mode. */ | |
17a2f251 TS |
3410 | macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3411 | BFD_RELOC_LO16); | |
252b5132 RH |
3412 | return; |
3413 | } | |
3414 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3415 | { | |
3416 | /* We can handle 16 bit unsigned values with an ori to | |
3417 | $zero. */ | |
17a2f251 TS |
3418 | macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0, |
3419 | BFD_RELOC_LO16); | |
252b5132 RH |
3420 | return; |
3421 | } | |
256ab948 | 3422 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3423 | { |
3424 | /* 32 bit values require an lui. */ | |
17a2f251 | 3425 | macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3426 | if ((ep->X_add_number & 0xffff) != 0) |
17a2f251 TS |
3427 | macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg, |
3428 | BFD_RELOC_LO16); | |
252b5132 RH |
3429 | return; |
3430 | } | |
3431 | } | |
3432 | ||
3433 | /* The value is larger than 32 bits. */ | |
3434 | ||
ca4e0257 | 3435 | if (HAVE_32BIT_GPRS) |
252b5132 | 3436 | { |
956cd1d6 TS |
3437 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3438 | (unsigned long) ep->X_add_number); | |
17a2f251 TS |
3439 | macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3440 | BFD_RELOC_LO16); | |
252b5132 RH |
3441 | return; |
3442 | } | |
3443 | ||
3444 | if (ep->X_op != O_big) | |
3445 | { | |
3446 | hi32 = *ep; | |
3447 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3448 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3449 | hi32.X_add_number &= 0xffffffff; | |
3450 | lo32 = *ep; | |
3451 | lo32.X_add_number &= 0xffffffff; | |
3452 | } | |
3453 | else | |
3454 | { | |
3455 | assert (ep->X_add_number > 2); | |
3456 | if (ep->X_add_number == 3) | |
3457 | generic_bignum[3] = 0; | |
3458 | else if (ep->X_add_number > 4) | |
3459 | as_bad (_("Number larger than 64 bits")); | |
3460 | lo32.X_op = O_constant; | |
3461 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3462 | hi32.X_op = O_constant; | |
3463 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3464 | } | |
3465 | ||
3466 | if (hi32.X_add_number == 0) | |
3467 | freg = 0; | |
3468 | else | |
3469 | { | |
3470 | int shift, bit; | |
3471 | unsigned long hi, lo; | |
3472 | ||
956cd1d6 | 3473 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3474 | { |
3475 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3476 | { | |
17a2f251 TS |
3477 | macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0, |
3478 | BFD_RELOC_LO16); | |
beae10d5 KH |
3479 | return; |
3480 | } | |
3481 | if (lo32.X_add_number & 0x80000000) | |
3482 | { | |
17a2f251 TS |
3483 | macro_build (NULL, counter, &lo32, "lui", "t,u", reg, |
3484 | BFD_RELOC_HI16); | |
252b5132 | 3485 | if (lo32.X_add_number & 0xffff) |
17a2f251 TS |
3486 | macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg, |
3487 | BFD_RELOC_LO16); | |
beae10d5 KH |
3488 | return; |
3489 | } | |
3490 | } | |
252b5132 RH |
3491 | |
3492 | /* Check for 16bit shifted constant. We know that hi32 is | |
3493 | non-zero, so start the mask on the first bit of the hi32 | |
3494 | value. */ | |
3495 | shift = 17; | |
3496 | do | |
beae10d5 KH |
3497 | { |
3498 | unsigned long himask, lomask; | |
3499 | ||
3500 | if (shift < 32) | |
3501 | { | |
3502 | himask = 0xffff >> (32 - shift); | |
3503 | lomask = (0xffff << shift) & 0xffffffff; | |
3504 | } | |
3505 | else | |
3506 | { | |
3507 | himask = 0xffff << (shift - 32); | |
3508 | lomask = 0; | |
3509 | } | |
3510 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3511 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3512 | { | |
3513 | expressionS tmp; | |
3514 | ||
3515 | tmp.X_op = O_constant; | |
3516 | if (shift < 32) | |
3517 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3518 | | (lo32.X_add_number >> shift)); | |
3519 | else | |
3520 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
17a2f251 TS |
3521 | macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0, |
3522 | BFD_RELOC_LO16); | |
3523 | macro_build (NULL, counter, NULL, | |
beae10d5 KH |
3524 | (shift >= 32) ? "dsll32" : "dsll", |
3525 | "d,w,<", reg, reg, | |
3526 | (shift >= 32) ? shift - 32 : shift); | |
3527 | return; | |
3528 | } | |
f9419b05 | 3529 | ++shift; |
beae10d5 KH |
3530 | } |
3531 | while (shift <= (64 - 16)); | |
252b5132 RH |
3532 | |
3533 | /* Find the bit number of the lowest one bit, and store the | |
3534 | shifted value in hi/lo. */ | |
3535 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3536 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3537 | if (lo != 0) | |
3538 | { | |
3539 | bit = 0; | |
3540 | while ((lo & 1) == 0) | |
3541 | { | |
3542 | lo >>= 1; | |
3543 | ++bit; | |
3544 | } | |
3545 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3546 | hi >>= bit; | |
3547 | } | |
3548 | else | |
3549 | { | |
3550 | bit = 32; | |
3551 | while ((hi & 1) == 0) | |
3552 | { | |
3553 | hi >>= 1; | |
3554 | ++bit; | |
3555 | } | |
3556 | lo = hi; | |
3557 | hi = 0; | |
3558 | } | |
3559 | ||
3560 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3561 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3562 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3563 | { |
3564 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3565 | if (shift != 0) |
beae10d5 | 3566 | { |
252b5132 RH |
3567 | expressionS tmp; |
3568 | ||
3569 | /* This instruction will set the register to be all | |
3570 | ones. */ | |
beae10d5 KH |
3571 | tmp.X_op = O_constant; |
3572 | tmp.X_add_number = (offsetT) -1; | |
17a2f251 TS |
3573 | macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0, |
3574 | BFD_RELOC_LO16); | |
beae10d5 KH |
3575 | if (bit != 0) |
3576 | { | |
3577 | bit += shift; | |
17a2f251 | 3578 | macro_build (NULL, counter, NULL, |
beae10d5 KH |
3579 | (bit >= 32) ? "dsll32" : "dsll", |
3580 | "d,w,<", reg, reg, | |
3581 | (bit >= 32) ? bit - 32 : bit); | |
3582 | } | |
17a2f251 | 3583 | macro_build (NULL, counter, NULL, |
252b5132 | 3584 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3585 | "d,w,<", reg, reg, |
252b5132 | 3586 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3587 | return; |
3588 | } | |
3589 | } | |
252b5132 RH |
3590 | |
3591 | /* Sign extend hi32 before calling load_register, because we can | |
3592 | generally get better code when we load a sign extended value. */ | |
3593 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3594 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3595 | load_register (counter, reg, &hi32, 0); |
3596 | freg = reg; | |
3597 | } | |
3598 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3599 | { | |
3600 | if (freg != 0) | |
3601 | { | |
17a2f251 | 3602 | macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3603 | freg = reg; |
3604 | } | |
3605 | } | |
3606 | else | |
3607 | { | |
3608 | expressionS mid16; | |
3609 | ||
956cd1d6 | 3610 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3611 | { |
17a2f251 TS |
3612 | macro_build (NULL, counter, &lo32, "lui", "t,u", reg, |
3613 | BFD_RELOC_HI16); | |
3614 | macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3615 | return; |
3616 | } | |
252b5132 RH |
3617 | |
3618 | if (freg != 0) | |
3619 | { | |
17a2f251 | 3620 | macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3621 | freg = reg; |
3622 | } | |
3623 | mid16 = lo32; | |
3624 | mid16.X_add_number >>= 16; | |
17a2f251 TS |
3625 | macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg, |
3626 | BFD_RELOC_LO16); | |
3627 | macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3628 | freg = reg; |
3629 | } | |
3630 | if ((lo32.X_add_number & 0xffff) != 0) | |
17a2f251 TS |
3631 | macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
3632 | BFD_RELOC_LO16); | |
252b5132 RH |
3633 | } |
3634 | ||
3635 | /* Load an address into a register. */ | |
3636 | ||
3637 | static void | |
17a2f251 | 3638 | load_address (int *counter, int reg, expressionS *ep, int *used_at) |
252b5132 | 3639 | { |
f9419b05 | 3640 | char *p = NULL; |
252b5132 RH |
3641 | |
3642 | if (ep->X_op != O_constant | |
3643 | && ep->X_op != O_symbol) | |
3644 | { | |
3645 | as_bad (_("expression too complex")); | |
3646 | ep->X_op = O_constant; | |
3647 | } | |
3648 | ||
3649 | if (ep->X_op == O_constant) | |
3650 | { | |
c9914766 | 3651 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3652 | return; |
3653 | } | |
3654 | ||
3655 | if (mips_pic == NO_PIC) | |
3656 | { | |
3657 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3658 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3659 | Otherwise we want |
3660 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3661 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3662 | If we have an addend, we always use the latter form. |
76b3015f | 3663 | |
d6bc6245 TS |
3664 | With 64bit address space and a usable $at we want |
3665 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3666 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3667 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3668 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3669 | dsll32 $reg,0 | |
3a482fd5 | 3670 | daddu $reg,$reg,$at |
76b3015f | 3671 | |
c03099e6 | 3672 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3673 | on superscalar processors. |
3674 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3675 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3676 | dsll $reg,16 | |
3677 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3678 | dsll $reg,16 | |
3679 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3680 | */ | |
c9914766 | 3681 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3682 | { |
d6bc6245 TS |
3683 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3684 | hold the data for such large chunks. */ | |
3685 | ||
460597ba | 3686 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
3687 | { |
3688 | macro_build (p, counter, ep, "lui", "t,u", | |
17a2f251 | 3689 | reg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 3690 | macro_build (p, counter, ep, "lui", "t,u", |
17a2f251 | 3691 | AT, BFD_RELOC_HI16_S); |
d6bc6245 | 3692 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 | 3693 | reg, reg, BFD_RELOC_MIPS_HIGHER); |
d6bc6245 | 3694 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 TS |
3695 | AT, AT, BFD_RELOC_LO16); |
3696 | macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3697 | macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3698 | *used_at = 1; |
3699 | } | |
3700 | else | |
3701 | { | |
3702 | macro_build (p, counter, ep, "lui", "t,u", | |
17a2f251 | 3703 | reg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 3704 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 TS |
3705 | reg, reg, BFD_RELOC_MIPS_HIGHER); |
3706 | macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16); | |
d6bc6245 | 3707 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 TS |
3708 | reg, reg, BFD_RELOC_HI16_S); |
3709 | macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16); | |
d6bc6245 | 3710 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
17a2f251 | 3711 | reg, reg, BFD_RELOC_LO16); |
d6bc6245 TS |
3712 | } |
3713 | } | |
252b5132 RH |
3714 | else |
3715 | { | |
d6bc6245 TS |
3716 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3717 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3718 | { | |
3719 | frag_grow (20); | |
17a2f251 TS |
3720 | macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
3721 | mips_gp_register, BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3722 | p = frag_var (rs_machine_dependent, 8, 0, |
3723 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3724 | mips_opts.warn_about_macros), | |
956cd1d6 | 3725 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3726 | } |
3727 | macro_build_lui (p, counter, ep, reg); | |
3728 | if (p != NULL) | |
3729 | p += 4; | |
17a2f251 TS |
3730 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3731 | BFD_RELOC_LO16); | |
d6bc6245 | 3732 | } |
252b5132 RH |
3733 | } |
3734 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3735 | { | |
3736 | expressionS ex; | |
3737 | ||
3738 | /* If this is a reference to an external symbol, we want | |
3739 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3740 | Otherwise we want | |
3741 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3742 | nop | |
3743 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3744 | If there is a constant, it must be added in after. |
3745 | ||
ed6fb7bd | 3746 | If we have NewABI, we want |
f5040a92 AO |
3747 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3748 | unless we're referencing a global symbol with a non-zero | |
3749 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3750 | if (HAVE_NEWABI) |
3751 | { | |
f5040a92 | 3752 | frag_grow (12); |
684022ea | 3753 | |
f5040a92 AO |
3754 | if (ep->X_add_number) |
3755 | { | |
3756 | frag_now->tc_frag_data.tc_fr_offset = | |
3757 | ex.X_add_number = ep->X_add_number; | |
3758 | ep->X_add_number = 0; | |
17a2f251 TS |
3759 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", |
3760 | reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3761 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3762 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3763 | ex.X_op = O_constant; | |
17a2f251 TS |
3764 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3765 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 AO |
3766 | p = frag_var (rs_machine_dependent, 8, 0, |
3767 | RELAX_ENCODE (8, 4, 0, 0, 0, | |
3768 | mips_opts.warn_about_macros), | |
17a2f251 | 3769 | ep->X_add_symbol, 0, NULL); |
f5040a92 AO |
3770 | ep->X_add_number = ex.X_add_number; |
3771 | } | |
3772 | ||
f899b4b8 | 3773 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3774 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
f5040a92 AO |
3775 | |
3776 | if (! p) | |
3777 | { | |
3778 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
3779 | that this does not become a variant frag. */ | |
3780 | frag_wane (frag_now); | |
3781 | frag_new (0); | |
3782 | } | |
ed6fb7bd SC |
3783 | } |
3784 | else | |
3785 | { | |
f5040a92 AO |
3786 | ex.X_add_number = ep->X_add_number; |
3787 | ep->X_add_number = 0; | |
3788 | frag_grow (20); | |
17a2f251 TS |
3789 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3790 | BFD_RELOC_MIPS_GOT16, | |
f899b4b8 | 3791 | mips_gp_register); |
17a2f251 | 3792 | macro_build (NULL, counter, NULL, "nop", ""); |
ed6fb7bd SC |
3793 | p = frag_var (rs_machine_dependent, 4, 0, |
3794 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
17a2f251 TS |
3795 | ep->X_add_symbol, 0, NULL); |
3796 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, | |
3797 | BFD_RELOC_LO16); | |
ed6fb7bd | 3798 | |
f5040a92 AO |
3799 | if (ex.X_add_number != 0) |
3800 | { | |
3801 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3802 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3803 | ex.X_op = O_constant; | |
17a2f251 TS |
3804 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3805 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 | 3806 | } |
252b5132 RH |
3807 | } |
3808 | } | |
3809 | else if (mips_pic == SVR4_PIC) | |
3810 | { | |
3811 | expressionS ex; | |
3812 | int off; | |
3813 | ||
3814 | /* This is the large GOT case. If this is a reference to an | |
3815 | external symbol, we want | |
3816 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3817 | addu $reg,$reg,$gp | |
3818 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3819 | |
3820 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3821 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3822 | nop | |
3823 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3824 | If there is a constant, it must be added in after. |
f5040a92 AO |
3825 | |
3826 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3827 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3828 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3829 | */ |
438c16b8 TS |
3830 | if (HAVE_NEWABI) |
3831 | { | |
f5040a92 AO |
3832 | frag_grow (24); |
3833 | ||
3834 | frag_now->tc_frag_data.tc_fr_offset = | |
3835 | ex.X_add_number = ep->X_add_number; | |
3836 | ep->X_add_number = 0; | |
17a2f251 TS |
3837 | macro_build (NULL, counter, ep, "lui", "t,u", reg, |
3838 | BFD_RELOC_MIPS_GOT_HI16); | |
3839 | macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg, | |
3840 | reg, mips_gp_register); | |
3841 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, | |
3842 | BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3843 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3844 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3845 | else if (ex.X_add_number) | |
3846 | { | |
3847 | ex.X_op = O_constant; | |
17a2f251 TS |
3848 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3849 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 AO |
3850 | } |
3851 | ||
3852 | ep->X_add_number = ex.X_add_number; | |
3853 | p = frag_var (rs_machine_dependent, 8, 0, | |
3854 | RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0, | |
3855 | mips_opts.warn_about_macros), | |
17a2f251 | 3856 | ep->X_add_symbol, 0, NULL); |
f899b4b8 | 3857 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 TS |
3858 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
3859 | macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3860 | reg, BFD_RELOC_MIPS_GOT_OFST); | |
438c16b8 | 3861 | } |
252b5132 | 3862 | else |
438c16b8 | 3863 | { |
f5040a92 AO |
3864 | ex.X_add_number = ep->X_add_number; |
3865 | ep->X_add_number = 0; | |
438c16b8 TS |
3866 | if (reg_needs_delay (mips_gp_register)) |
3867 | off = 4; | |
3868 | else | |
3869 | off = 0; | |
3870 | frag_grow (32); | |
17a2f251 TS |
3871 | macro_build (NULL, counter, ep, "lui", "t,u", reg, |
3872 | BFD_RELOC_MIPS_GOT_HI16); | |
3873 | macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg, | |
3874 | reg, mips_gp_register); | |
3875 | macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, | |
3876 | BFD_RELOC_MIPS_GOT_LO16, reg); | |
438c16b8 TS |
3877 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
3878 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3879 | mips_opts.warn_about_macros), | |
3880 | ep->X_add_symbol, 0, NULL); | |
3881 | if (off > 0) | |
3882 | { | |
3883 | /* We need a nop before loading from $gp. This special | |
3884 | check is required because the lui which starts the main | |
3885 | instruction stream does not refer to $gp, and so will not | |
3886 | insert the nop which may be required. */ | |
17a2f251 | 3887 | macro_build (p, counter, NULL, "nop", ""); |
438c16b8 TS |
3888 | p += 4; |
3889 | } | |
f899b4b8 | 3890 | macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3891 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
438c16b8 | 3892 | p += 4; |
17a2f251 | 3893 | macro_build (p, counter, NULL, "nop", ""); |
252b5132 | 3894 | p += 4; |
17a2f251 TS |
3895 | macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3896 | BFD_RELOC_LO16); | |
438c16b8 | 3897 | |
f5040a92 AO |
3898 | if (ex.X_add_number != 0) |
3899 | { | |
3900 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3901 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3902 | ex.X_op = O_constant; | |
17a2f251 TS |
3903 | macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j", |
3904 | reg, reg, BFD_RELOC_LO16); | |
f5040a92 | 3905 | } |
252b5132 RH |
3906 | } |
3907 | } | |
3908 | else if (mips_pic == EMBEDDED_PIC) | |
3909 | { | |
3910 | /* We always do | |
cdf6fd85 | 3911 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 | 3912 | */ |
17a2f251 TS |
3913 | macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
3914 | mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
3915 | } |
3916 | else | |
3917 | abort (); | |
3918 | } | |
3919 | ||
ea1fb5dc RS |
3920 | /* Move the contents of register SOURCE into register DEST. */ |
3921 | ||
3922 | static void | |
17a2f251 | 3923 | move_register (int *counter, int dest, int source) |
ea1fb5dc | 3924 | { |
17a2f251 | 3925 | macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", |
ea1fb5dc RS |
3926 | "d,v,t", dest, source, 0); |
3927 | } | |
3928 | ||
252b5132 RH |
3929 | /* |
3930 | * Build macros | |
3931 | * This routine implements the seemingly endless macro or synthesized | |
3932 | * instructions and addressing modes in the mips assembly language. Many | |
3933 | * of these macros are simple and are similar to each other. These could | |
3934 | * probably be handled by some kind of table or grammer aproach instead of | |
3935 | * this verbose method. Others are not simple macros but are more like | |
3936 | * optimizing code generation. | |
3937 | * One interesting optimization is when several store macros appear | |
3938 | * consecutivly that would load AT with the upper half of the same address. | |
3939 | * The ensuing load upper instructions are ommited. This implies some kind | |
3940 | * of global optimization. We currently only optimize within a single macro. | |
3941 | * For many of the load and store macros if the address is specified as a | |
3942 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3943 | * first load register 'at' with zero and use it as the base register. The | |
3944 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3945 | * we're missing. | |
3946 | */ | |
3947 | static void | |
17a2f251 | 3948 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
3949 | { |
3950 | register int treg, sreg, dreg, breg; | |
3951 | int tempreg; | |
3952 | int mask; | |
3953 | int icnt = 0; | |
43841e91 | 3954 | int used_at = 0; |
252b5132 RH |
3955 | expressionS expr1; |
3956 | const char *s; | |
3957 | const char *s2; | |
3958 | const char *fmt; | |
3959 | int likely = 0; | |
3960 | int dbl = 0; | |
3961 | int coproc = 0; | |
3962 | int lr = 0; | |
3963 | int imm = 0; | |
3964 | offsetT maxnum; | |
3965 | int off; | |
3966 | bfd_reloc_code_real_type r; | |
252b5132 RH |
3967 | int hold_mips_optimize; |
3968 | ||
3969 | assert (! mips_opts.mips16); | |
3970 | ||
3971 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3972 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3973 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3974 | mask = ip->insn_mo->mask; | |
3975 | ||
3976 | expr1.X_op = O_constant; | |
3977 | expr1.X_op_symbol = NULL; | |
3978 | expr1.X_add_symbol = NULL; | |
3979 | expr1.X_add_number = 1; | |
3980 | ||
5919d012 RS |
3981 | /* Umatched fixups should not be put in the same frag as a relaxable |
3982 | macro. For example, suppose we have: | |
3983 | ||
3984 | lui $4,%hi(l1) # 1 | |
3985 | la $5,l2 # 2 | |
3986 | addiu $4,$4,%lo(l1) # 3 | |
3987 | ||
3988 | If instructions 1 and 2 were put in the same frag, md_frob_file would | |
3989 | move the fixup for #1 after the fixups for the "unrelaxed" version of | |
3990 | #2. This would confuse tc_gen_reloc, which expects the relocations | |
3991 | for #2 to be the last for that frag. | |
3992 | ||
64bdfcaf RS |
3993 | Also, if tc_gen_reloc sees certain relocations in a variant frag, |
3994 | it assumes that they belong to a relaxable macro. We mustn't put | |
3995 | other uses of such relocations into a variant frag. | |
3996 | ||
3997 | To avoid both problems, finish the current frag it contains a | |
3998 | %reloc() operator. The macro then goes into a new frag. */ | |
3999 | if (prev_reloc_op_frag == frag_now) | |
5919d012 RS |
4000 | { |
4001 | frag_wane (frag_now); | |
4002 | frag_new (0); | |
4003 | } | |
4004 | ||
252b5132 RH |
4005 | switch (mask) |
4006 | { | |
4007 | case M_DABS: | |
4008 | dbl = 1; | |
4009 | case M_ABS: | |
4010 | /* bgez $a0,.+12 | |
4011 | move v0,$a0 | |
4012 | sub v0,$zero,$a0 | |
4013 | */ | |
4014 | ||
b34976b6 | 4015 | mips_emit_delays (TRUE); |
252b5132 RH |
4016 | ++mips_opts.noreorder; |
4017 | mips_any_noreorder = 1; | |
4018 | ||
4019 | expr1.X_add_number = 8; | |
17a2f251 | 4020 | macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
252b5132 | 4021 | if (dreg == sreg) |
17a2f251 | 4022 | macro_build (NULL, &icnt, NULL, "nop", "", 0); |
252b5132 | 4023 | else |
ea1fb5dc | 4024 | move_register (&icnt, dreg, sreg); |
17a2f251 TS |
4025 | macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, |
4026 | sreg); | |
252b5132 RH |
4027 | |
4028 | --mips_opts.noreorder; | |
4029 | return; | |
4030 | ||
4031 | case M_ADD_I: | |
4032 | s = "addi"; | |
4033 | s2 = "add"; | |
4034 | goto do_addi; | |
4035 | case M_ADDU_I: | |
4036 | s = "addiu"; | |
4037 | s2 = "addu"; | |
4038 | goto do_addi; | |
4039 | case M_DADD_I: | |
4040 | dbl = 1; | |
4041 | s = "daddi"; | |
4042 | s2 = "dadd"; | |
4043 | goto do_addi; | |
4044 | case M_DADDU_I: | |
4045 | dbl = 1; | |
4046 | s = "daddiu"; | |
4047 | s2 = "daddu"; | |
4048 | do_addi: | |
4049 | if (imm_expr.X_op == O_constant | |
4050 | && imm_expr.X_add_number >= -0x8000 | |
4051 | && imm_expr.X_add_number < 0x8000) | |
4052 | { | |
17a2f251 TS |
4053 | macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
4054 | BFD_RELOC_LO16); | |
252b5132 RH |
4055 | return; |
4056 | } | |
4057 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 | 4058 | macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
252b5132 RH |
4059 | break; |
4060 | ||
4061 | case M_AND_I: | |
4062 | s = "andi"; | |
4063 | s2 = "and"; | |
4064 | goto do_bit; | |
4065 | case M_OR_I: | |
4066 | s = "ori"; | |
4067 | s2 = "or"; | |
4068 | goto do_bit; | |
4069 | case M_NOR_I: | |
4070 | s = ""; | |
4071 | s2 = "nor"; | |
4072 | goto do_bit; | |
4073 | case M_XOR_I: | |
4074 | s = "xori"; | |
4075 | s2 = "xor"; | |
4076 | do_bit: | |
4077 | if (imm_expr.X_op == O_constant | |
4078 | && imm_expr.X_add_number >= 0 | |
4079 | && imm_expr.X_add_number < 0x10000) | |
4080 | { | |
4081 | if (mask != M_NOR_I) | |
17a2f251 TS |
4082 | macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg, |
4083 | BFD_RELOC_LO16); | |
252b5132 RH |
4084 | else |
4085 | { | |
17a2f251 TS |
4086 | macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg, |
4087 | BFD_RELOC_LO16); | |
4088 | macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4089 | } |
4090 | return; | |
4091 | } | |
4092 | ||
d6bc6245 | 4093 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 4094 | macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
252b5132 RH |
4095 | break; |
4096 | ||
4097 | case M_BEQ_I: | |
4098 | s = "beq"; | |
4099 | goto beq_i; | |
4100 | case M_BEQL_I: | |
4101 | s = "beql"; | |
4102 | likely = 1; | |
4103 | goto beq_i; | |
4104 | case M_BNE_I: | |
4105 | s = "bne"; | |
4106 | goto beq_i; | |
4107 | case M_BNEL_I: | |
4108 | s = "bnel"; | |
4109 | likely = 1; | |
4110 | beq_i: | |
4111 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4112 | { | |
17a2f251 | 4113 | macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4114 | return; |
4115 | } | |
4d34fb5f | 4116 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 4117 | macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
252b5132 RH |
4118 | break; |
4119 | ||
4120 | case M_BGEL: | |
4121 | likely = 1; | |
4122 | case M_BGE: | |
4123 | if (treg == 0) | |
4124 | { | |
17a2f251 TS |
4125 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez", |
4126 | "s,p", sreg); | |
252b5132 RH |
4127 | return; |
4128 | } | |
4129 | if (sreg == 0) | |
4130 | { | |
17a2f251 TS |
4131 | macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez", |
4132 | "s,p", treg); | |
252b5132 RH |
4133 | return; |
4134 | } | |
17a2f251 TS |
4135 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
4136 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4137 | "s,t,p", AT, 0); | |
252b5132 RH |
4138 | break; |
4139 | ||
4140 | case M_BGTL_I: | |
4141 | likely = 1; | |
4142 | case M_BGT_I: | |
4143 | /* check for > max integer */ | |
4144 | maxnum = 0x7fffffff; | |
ca4e0257 | 4145 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4146 | { |
4147 | maxnum <<= 16; | |
4148 | maxnum |= 0xffff; | |
4149 | maxnum <<= 16; | |
4150 | maxnum |= 0xffff; | |
4151 | } | |
4152 | if (imm_expr.X_op == O_constant | |
4153 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4154 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4155 | { |
4156 | do_false: | |
4157 | /* result is always false */ | |
4158 | if (! likely) | |
4159 | { | |
39c0a331 L |
4160 | if (warn_nops) |
4161 | as_warn (_("Branch %s is always false (nop)"), | |
4162 | ip->insn_mo->name); | |
17a2f251 | 4163 | macro_build (NULL, &icnt, NULL, "nop", "", 0); |
252b5132 RH |
4164 | } |
4165 | else | |
4166 | { | |
39c0a331 L |
4167 | if (warn_nops) |
4168 | as_warn (_("Branch likely %s is always false"), | |
4169 | ip->insn_mo->name); | |
17a2f251 | 4170 | macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4171 | } |
4172 | return; | |
4173 | } | |
4174 | if (imm_expr.X_op != O_constant) | |
4175 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4176 | ++imm_expr.X_add_number; |
252b5132 RH |
4177 | /* FALLTHROUGH */ |
4178 | case M_BGE_I: | |
4179 | case M_BGEL_I: | |
4180 | if (mask == M_BGEL_I) | |
4181 | likely = 1; | |
4182 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4183 | { | |
17a2f251 TS |
4184 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez", |
4185 | "s,p", sreg); | |
252b5132 RH |
4186 | return; |
4187 | } | |
4188 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4189 | { | |
17a2f251 TS |
4190 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz", |
4191 | "s,p", sreg); | |
252b5132 RH |
4192 | return; |
4193 | } | |
4194 | maxnum = 0x7fffffff; | |
ca4e0257 | 4195 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4196 | { |
4197 | maxnum <<= 16; | |
4198 | maxnum |= 0xffff; | |
4199 | maxnum <<= 16; | |
4200 | maxnum |= 0xffff; | |
4201 | } | |
4202 | maxnum = - maxnum - 1; | |
4203 | if (imm_expr.X_op == O_constant | |
4204 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4205 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4206 | { |
4207 | do_true: | |
4208 | /* result is always true */ | |
4209 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
17a2f251 | 4210 | macro_build (NULL, &icnt, &offset_expr, "b", "p"); |
252b5132 RH |
4211 | return; |
4212 | } | |
4213 | set_at (&icnt, sreg, 0); | |
17a2f251 TS |
4214 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4215 | "s,t,p", AT, 0); | |
252b5132 RH |
4216 | break; |
4217 | ||
4218 | case M_BGEUL: | |
4219 | likely = 1; | |
4220 | case M_BGEU: | |
4221 | if (treg == 0) | |
4222 | goto do_true; | |
4223 | if (sreg == 0) | |
4224 | { | |
17a2f251 TS |
4225 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4226 | "s,t,p", 0, treg); | |
252b5132 RH |
4227 | return; |
4228 | } | |
17a2f251 TS |
4229 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg); |
4230 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4231 | "s,t,p", AT, 0); | |
252b5132 RH |
4232 | break; |
4233 | ||
4234 | case M_BGTUL_I: | |
4235 | likely = 1; | |
4236 | case M_BGTU_I: | |
4237 | if (sreg == 0 | |
ca4e0257 | 4238 | || (HAVE_32BIT_GPRS |
252b5132 | 4239 | && imm_expr.X_op == O_constant |
956cd1d6 | 4240 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4241 | goto do_false; |
4242 | if (imm_expr.X_op != O_constant) | |
4243 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4244 | ++imm_expr.X_add_number; |
252b5132 RH |
4245 | /* FALLTHROUGH */ |
4246 | case M_BGEU_I: | |
4247 | case M_BGEUL_I: | |
4248 | if (mask == M_BGEUL_I) | |
4249 | likely = 1; | |
4250 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4251 | goto do_true; | |
4252 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4253 | { | |
17a2f251 TS |
4254 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4255 | "s,t,p", sreg, 0); | |
252b5132 RH |
4256 | return; |
4257 | } | |
4258 | set_at (&icnt, sreg, 1); | |
17a2f251 TS |
4259 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4260 | "s,t,p", AT, 0); | |
252b5132 RH |
4261 | break; |
4262 | ||
4263 | case M_BGTL: | |
4264 | likely = 1; | |
4265 | case M_BGT: | |
4266 | if (treg == 0) | |
4267 | { | |
17a2f251 TS |
4268 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz", |
4269 | "s,p", sreg); | |
252b5132 RH |
4270 | return; |
4271 | } | |
4272 | if (sreg == 0) | |
4273 | { | |
17a2f251 TS |
4274 | macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz", |
4275 | "s,p", treg); | |
252b5132 RH |
4276 | return; |
4277 | } | |
17a2f251 TS |
4278 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
4279 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4280 | "s,t,p", AT, 0); | |
252b5132 RH |
4281 | break; |
4282 | ||
4283 | case M_BGTUL: | |
4284 | likely = 1; | |
4285 | case M_BGTU: | |
4286 | if (treg == 0) | |
4287 | { | |
17a2f251 TS |
4288 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4289 | "s,t,p", sreg, 0); | |
252b5132 RH |
4290 | return; |
4291 | } | |
4292 | if (sreg == 0) | |
4293 | goto do_false; | |
17a2f251 TS |
4294 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg); |
4295 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4296 | "s,t,p", AT, 0); | |
252b5132 RH |
4297 | break; |
4298 | ||
4299 | case M_BLEL: | |
4300 | likely = 1; | |
4301 | case M_BLE: | |
4302 | if (treg == 0) | |
4303 | { | |
17a2f251 TS |
4304 | macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez", |
4305 | "s,p", sreg); | |
252b5132 RH |
4306 | return; |
4307 | } | |
4308 | if (sreg == 0) | |
4309 | { | |
17a2f251 TS |
4310 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez", |
4311 | "s,p", treg); | |
252b5132 RH |
4312 | return; |
4313 | } | |
17a2f251 TS |
4314 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
4315 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4316 | "s,t,p", AT, 0); | |
252b5132 RH |
4317 | break; |
4318 | ||
4319 | case M_BLEL_I: | |
4320 | likely = 1; | |
4321 | case M_BLE_I: | |
4322 | maxnum = 0x7fffffff; | |
ca4e0257 | 4323 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4324 | { |
4325 | maxnum <<= 16; | |
4326 | maxnum |= 0xffff; | |
4327 | maxnum <<= 16; | |
4328 | maxnum |= 0xffff; | |
4329 | } | |
4330 | if (imm_expr.X_op == O_constant | |
4331 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4332 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4333 | goto do_true; |
4334 | if (imm_expr.X_op != O_constant) | |
4335 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4336 | ++imm_expr.X_add_number; |
252b5132 RH |
4337 | /* FALLTHROUGH */ |
4338 | case M_BLT_I: | |
4339 | case M_BLTL_I: | |
4340 | if (mask == M_BLTL_I) | |
4341 | likely = 1; | |
4342 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4343 | { | |
17a2f251 TS |
4344 | macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz", |
4345 | "s,p", sreg); | |
252b5132 RH |
4346 | return; |
4347 | } | |
4348 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4349 | { | |
17a2f251 TS |
4350 | macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez", |
4351 | "s,p", sreg); | |
252b5132 RH |
4352 | return; |
4353 | } | |
4354 | set_at (&icnt, sreg, 0); | |
17a2f251 TS |
4355 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4356 | "s,t,p", AT, 0); | |
252b5132 RH |
4357 | break; |
4358 | ||
4359 | case M_BLEUL: | |
4360 | likely = 1; | |
4361 | case M_BLEU: | |
4362 | if (treg == 0) | |
4363 | { | |
17a2f251 TS |
4364 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
4365 | "s,t,p", sreg, 0); | |
252b5132 RH |
4366 | return; |
4367 | } | |
4368 | if (sreg == 0) | |
4369 | goto do_true; | |
17a2f251 TS |
4370 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg); |
4371 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", | |
4372 | "s,t,p", AT, 0); | |
252b5132 RH |
4373 | break; |
4374 | ||
4375 | case M_BLEUL_I: | |
4376 | likely = 1; | |
4377 | case M_BLEU_I: | |
4378 | if (sreg == 0 | |
ca4e0257 | 4379 | || (HAVE_32BIT_GPRS |
252b5132 | 4380 | && imm_expr.X_op == O_constant |
956cd1d6 | 4381 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4382 | goto do_true; |
4383 | if (imm_expr.X_op != O_constant) | |
4384 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4385 | ++imm_expr.X_add_number; |
252b5132 RH |
4386 | /* FALLTHROUGH */ |
4387 | case M_BLTU_I: | |
4388 | case M_BLTUL_I: | |
4389 | if (mask == M_BLTUL_I) | |
4390 | likely = 1; | |
4391 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4392 | goto do_false; | |
4393 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4394 | { | |
17a2f251 | 4395 | macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4396 | "s,t,p", sreg, 0); |
4397 | return; | |
4398 | } | |
4399 | set_at (&icnt, sreg, 1); | |
17a2f251 TS |
4400 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4401 | "s,t,p", AT, 0); | |
252b5132 RH |
4402 | break; |
4403 | ||
4404 | case M_BLTL: | |
4405 | likely = 1; | |
4406 | case M_BLT: | |
4407 | if (treg == 0) | |
4408 | { | |
17a2f251 TS |
4409 | macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz", |
4410 | "s,p", sreg); | |
252b5132 RH |
4411 | return; |
4412 | } | |
4413 | if (sreg == 0) | |
4414 | { | |
17a2f251 TS |
4415 | macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz", |
4416 | "s,p", treg); | |
252b5132 RH |
4417 | return; |
4418 | } | |
17a2f251 TS |
4419 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
4420 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4421 | "s,t,p", AT, 0); | |
252b5132 RH |
4422 | break; |
4423 | ||
4424 | case M_BLTUL: | |
4425 | likely = 1; | |
4426 | case M_BLTU: | |
4427 | if (treg == 0) | |
4428 | goto do_false; | |
4429 | if (sreg == 0) | |
4430 | { | |
17a2f251 TS |
4431 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", |
4432 | "s,t,p", 0, treg); | |
252b5132 RH |
4433 | return; |
4434 | } | |
17a2f251 TS |
4435 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg); |
4436 | macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne", | |
4437 | "s,t,p", AT, 0); | |
252b5132 RH |
4438 | break; |
4439 | ||
4440 | case M_DDIV_3: | |
4441 | dbl = 1; | |
4442 | case M_DIV_3: | |
4443 | s = "mflo"; | |
4444 | goto do_div3; | |
4445 | case M_DREM_3: | |
4446 | dbl = 1; | |
4447 | case M_REM_3: | |
4448 | s = "mfhi"; | |
4449 | do_div3: | |
4450 | if (treg == 0) | |
4451 | { | |
4452 | as_warn (_("Divide by zero.")); | |
4453 | if (mips_trap) | |
17a2f251 | 4454 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4455 | else |
17a2f251 | 4456 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4457 | return; |
4458 | } | |
4459 | ||
b34976b6 | 4460 | mips_emit_delays (TRUE); |
252b5132 RH |
4461 | ++mips_opts.noreorder; |
4462 | mips_any_noreorder = 1; | |
4463 | if (mips_trap) | |
4464 | { | |
17a2f251 TS |
4465 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7); |
4466 | macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t", | |
4467 | sreg, treg); | |
252b5132 RH |
4468 | } |
4469 | else | |
4470 | { | |
4471 | expr1.X_add_number = 8; | |
17a2f251 TS |
4472 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
4473 | macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t", | |
4474 | sreg, treg); | |
4475 | macro_build (NULL, &icnt,NULL, "break", "c", 7); | |
252b5132 RH |
4476 | } |
4477 | expr1.X_add_number = -1; | |
17a2f251 TS |
4478 | macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j", |
4479 | AT, 0, BFD_RELOC_LO16); | |
252b5132 | 4480 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
17a2f251 | 4481 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4482 | if (dbl) |
4483 | { | |
4484 | expr1.X_add_number = 1; | |
17a2f251 TS |
4485 | macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
4486 | BFD_RELOC_LO16); | |
4487 | macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31); | |
252b5132 RH |
4488 | } |
4489 | else | |
4490 | { | |
4491 | expr1.X_add_number = 0x80000000; | |
17a2f251 TS |
4492 | macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT, |
4493 | BFD_RELOC_HI16); | |
252b5132 RH |
4494 | } |
4495 | if (mips_trap) | |
4496 | { | |
17a2f251 | 4497 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4498 | /* We want to close the noreorder block as soon as possible, so |
4499 | that later insns are available for delay slot filling. */ | |
4500 | --mips_opts.noreorder; | |
4501 | } | |
4502 | else | |
4503 | { | |
4504 | expr1.X_add_number = 8; | |
17a2f251 TS |
4505 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); |
4506 | macro_build (NULL, &icnt, NULL, "nop", "", 0); | |
252b5132 RH |
4507 | |
4508 | /* We want to close the noreorder block as soon as possible, so | |
4509 | that later insns are available for delay slot filling. */ | |
4510 | --mips_opts.noreorder; | |
4511 | ||
17a2f251 | 4512 | macro_build (NULL, &icnt, NULL, "break", "c", 6); |
252b5132 | 4513 | } |
17a2f251 | 4514 | macro_build (NULL, &icnt, NULL, s, "d", dreg); |
252b5132 RH |
4515 | break; |
4516 | ||
4517 | case M_DIV_3I: | |
4518 | s = "div"; | |
4519 | s2 = "mflo"; | |
4520 | goto do_divi; | |
4521 | case M_DIVU_3I: | |
4522 | s = "divu"; | |
4523 | s2 = "mflo"; | |
4524 | goto do_divi; | |
4525 | case M_REM_3I: | |
4526 | s = "div"; | |
4527 | s2 = "mfhi"; | |
4528 | goto do_divi; | |
4529 | case M_REMU_3I: | |
4530 | s = "divu"; | |
4531 | s2 = "mfhi"; | |
4532 | goto do_divi; | |
4533 | case M_DDIV_3I: | |
4534 | dbl = 1; | |
4535 | s = "ddiv"; | |
4536 | s2 = "mflo"; | |
4537 | goto do_divi; | |
4538 | case M_DDIVU_3I: | |
4539 | dbl = 1; | |
4540 | s = "ddivu"; | |
4541 | s2 = "mflo"; | |
4542 | goto do_divi; | |
4543 | case M_DREM_3I: | |
4544 | dbl = 1; | |
4545 | s = "ddiv"; | |
4546 | s2 = "mfhi"; | |
4547 | goto do_divi; | |
4548 | case M_DREMU_3I: | |
4549 | dbl = 1; | |
4550 | s = "ddivu"; | |
4551 | s2 = "mfhi"; | |
4552 | do_divi: | |
4553 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4554 | { | |
4555 | as_warn (_("Divide by zero.")); | |
4556 | if (mips_trap) | |
17a2f251 | 4557 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4558 | else |
17a2f251 | 4559 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 RH |
4560 | return; |
4561 | } | |
4562 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4563 | { | |
4564 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4565 | move_register (&icnt, dreg, sreg); |
252b5132 | 4566 | else |
ea1fb5dc | 4567 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4568 | return; |
4569 | } | |
4570 | if (imm_expr.X_op == O_constant | |
4571 | && imm_expr.X_add_number == -1 | |
4572 | && s[strlen (s) - 1] != 'u') | |
4573 | { | |
4574 | if (strcmp (s2, "mflo") == 0) | |
4575 | { | |
17a2f251 TS |
4576 | macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w", |
4577 | dreg, sreg); | |
252b5132 RH |
4578 | } |
4579 | else | |
ea1fb5dc | 4580 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4581 | return; |
4582 | } | |
4583 | ||
4584 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
4585 | macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
4586 | macro_build (NULL, &icnt, NULL, s2, "d", dreg); | |
252b5132 RH |
4587 | break; |
4588 | ||
4589 | case M_DIVU_3: | |
4590 | s = "divu"; | |
4591 | s2 = "mflo"; | |
4592 | goto do_divu3; | |
4593 | case M_REMU_3: | |
4594 | s = "divu"; | |
4595 | s2 = "mfhi"; | |
4596 | goto do_divu3; | |
4597 | case M_DDIVU_3: | |
4598 | s = "ddivu"; | |
4599 | s2 = "mflo"; | |
4600 | goto do_divu3; | |
4601 | case M_DREMU_3: | |
4602 | s = "ddivu"; | |
4603 | s2 = "mfhi"; | |
4604 | do_divu3: | |
b34976b6 | 4605 | mips_emit_delays (TRUE); |
252b5132 RH |
4606 | ++mips_opts.noreorder; |
4607 | mips_any_noreorder = 1; | |
4608 | if (mips_trap) | |
4609 | { | |
17a2f251 TS |
4610 | macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7); |
4611 | macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4612 | /* We want to close the noreorder block as soon as possible, so |
4613 | that later insns are available for delay slot filling. */ | |
4614 | --mips_opts.noreorder; | |
4615 | } | |
4616 | else | |
4617 | { | |
4618 | expr1.X_add_number = 8; | |
17a2f251 TS |
4619 | macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
4620 | macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4621 | |
4622 | /* We want to close the noreorder block as soon as possible, so | |
4623 | that later insns are available for delay slot filling. */ | |
4624 | --mips_opts.noreorder; | |
17a2f251 | 4625 | macro_build (NULL, &icnt, NULL, "break", "c", 7); |
252b5132 | 4626 | } |
17a2f251 | 4627 | macro_build (NULL, &icnt, NULL, s2, "d", dreg); |
252b5132 RH |
4628 | return; |
4629 | ||
4630 | case M_DLA_AB: | |
4631 | dbl = 1; | |
4632 | case M_LA_AB: | |
4633 | /* Load the address of a symbol into a register. If breg is not | |
4634 | zero, we then add a base register to it. */ | |
4635 | ||
3bec30a8 TS |
4636 | if (dbl && HAVE_32BIT_GPRS) |
4637 | as_warn (_("dla used to load 32-bit register")); | |
4638 | ||
c90bbe5b | 4639 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4640 | as_warn (_("la used to load 64-bit address")); |
4641 | ||
0c11417f MR |
4642 | if (offset_expr.X_op == O_constant |
4643 | && offset_expr.X_add_number >= -0x8000 | |
4644 | && offset_expr.X_add_number < 0x8000) | |
4645 | { | |
17a2f251 | 4646 | macro_build (NULL, &icnt, &offset_expr, |
b7c7d6c1 | 4647 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4648 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4649 | return; |
4650 | } | |
4651 | ||
afdbd6d0 CD |
4652 | if (treg == breg) |
4653 | { | |
4654 | tempreg = AT; | |
4655 | used_at = 1; | |
4656 | } | |
4657 | else | |
4658 | { | |
4659 | tempreg = treg; | |
4660 | used_at = 0; | |
4661 | } | |
4662 | ||
252b5132 RH |
4663 | /* When generating embedded PIC code, we permit expressions of |
4664 | the form | |
afdbd6d0 CD |
4665 | la $treg,foo-bar |
4666 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4667 | where bar is an address in the current section. These are used |
252b5132 RH |
4668 | when getting the addresses of functions. We don't permit |
4669 | X_add_number to be non-zero, because if the symbol is | |
4670 | external the relaxing code needs to know that any addend is | |
4671 | purely the offset to X_op_symbol. */ | |
4672 | if (mips_pic == EMBEDDED_PIC | |
4673 | && offset_expr.X_op == O_subtract | |
49309057 | 4674 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4675 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4676 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4677 | && (S_GET_SEGMENT | |
4678 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4679 | ->X_add_symbol) | |
bb2d6cd7 | 4680 | == now_seg))) |
bb2d6cd7 GK |
4681 | && (offset_expr.X_add_number == 0 |
4682 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4683 | { |
afdbd6d0 CD |
4684 | if (breg == 0) |
4685 | { | |
4686 | tempreg = treg; | |
4687 | used_at = 0; | |
17a2f251 TS |
4688 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
4689 | BFD_RELOC_PCREL_HI16_S); | |
afdbd6d0 CD |
4690 | } |
4691 | else | |
4692 | { | |
17a2f251 TS |
4693 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
4694 | BFD_RELOC_PCREL_HI16_S); | |
4695 | macro_build (NULL, &icnt, NULL, | |
4d34fb5f | 4696 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4697 | "d,v,t", tempreg, tempreg, breg); |
4698 | } | |
17a2f251 | 4699 | macro_build (NULL, &icnt, &offset_expr, |
4d34fb5f | 4700 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4701 | "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16); |
afdbd6d0 CD |
4702 | if (! used_at) |
4703 | return; | |
4704 | break; | |
252b5132 RH |
4705 | } |
4706 | ||
4707 | if (offset_expr.X_op != O_symbol | |
4708 | && offset_expr.X_op != O_constant) | |
4709 | { | |
4710 | as_bad (_("expression too complex")); | |
4711 | offset_expr.X_op = O_constant; | |
4712 | } | |
4713 | ||
252b5132 | 4714 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4715 | load_register (&icnt, tempreg, &offset_expr, |
4716 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4717 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4718 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4719 | else if (mips_pic == NO_PIC) |
4720 | { | |
d6bc6245 | 4721 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4722 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4723 | Otherwise we want |
4724 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4725 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4726 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4727 | so we may as well always use the latter form. |
76b3015f | 4728 | |
d6bc6245 TS |
4729 | With 64bit address space and a usable $at we want |
4730 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4731 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4732 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4733 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4734 | dsll32 $tempreg,0 | |
3a482fd5 | 4735 | daddu $tempreg,$tempreg,$at |
76b3015f | 4736 | |
c03099e6 | 4737 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4738 | on superscalar processors. |
4739 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4740 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4741 | dsll $tempreg,16 | |
4742 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4743 | dsll $tempreg,16 | |
4744 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4745 | */ | |
f9419b05 | 4746 | char *p = NULL; |
d6bc6245 | 4747 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4748 | { |
d6bc6245 TS |
4749 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4750 | hold the data for such large chunks. */ | |
4751 | ||
460597ba | 4752 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f KH |
4753 | { |
4754 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 4755 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
98d3f06f | 4756 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
17a2f251 | 4757 | AT, BFD_RELOC_HI16_S); |
98d3f06f | 4758 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4759 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
98d3f06f | 4760 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
4761 | AT, AT, BFD_RELOC_LO16); |
4762 | macro_build (p, &icnt, NULL, "dsll32", "d,w,<", | |
4763 | tempreg, tempreg, 0); | |
4764 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", | |
4765 | tempreg, tempreg, AT); | |
98d3f06f KH |
4766 | used_at = 1; |
4767 | } | |
4768 | else | |
4769 | { | |
4770 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 4771 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
98d3f06f | 4772 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
4773 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
4774 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
98d3f06f KH |
4775 | tempreg, tempreg, 16); |
4776 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
17a2f251 TS |
4777 | tempreg, tempreg, BFD_RELOC_HI16_S); |
4778 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
98d3f06f KH |
4779 | tempreg, tempreg, 16); |
4780 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4781 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
4782 | } |
4783 | } | |
4784 | else | |
4785 | { | |
4786 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4787 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4788 | { | |
4789 | frag_grow (20); | |
17a2f251 TS |
4790 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
4791 | "t,r,j", tempreg, mips_gp_register, | |
4792 | BFD_RELOC_GPREL16); | |
98d3f06f KH |
4793 | p = frag_var (rs_machine_dependent, 8, 0, |
4794 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4795 | mips_opts.warn_about_macros), | |
4796 | offset_expr.X_add_symbol, 0, NULL); | |
4797 | } | |
4798 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4799 | if (p != NULL) | |
4800 | p += 4; | |
f899b4b8 | 4801 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4802 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 4803 | } |
252b5132 | 4804 | } |
f5040a92 | 4805 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4806 | { |
9117d219 NC |
4807 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4808 | ||
252b5132 RH |
4809 | /* If this is a reference to an external symbol, and there |
4810 | is no constant, we want | |
4811 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4812 | or if tempreg is PIC_CALL_REG |
4813 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4814 | For a local symbol, we want |
4815 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4816 | nop | |
4817 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4818 | ||
4819 | If we have a small constant, and this is a reference to | |
4820 | an external symbol, we want | |
4821 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4822 | nop | |
4823 | addiu $tempreg,$tempreg,<constant> | |
4824 | For a local symbol, we want the same instruction | |
4825 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4826 | addiu instruction. | |
4827 | ||
4828 | If we have a large constant, and this is a reference to | |
4829 | an external symbol, we want | |
4830 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4831 | lui $at,<hiconstant> | |
4832 | addiu $at,$at,<loconstant> | |
4833 | addu $tempreg,$tempreg,$at | |
4834 | For a local symbol, we want the same instruction | |
4835 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 4836 | addiu instruction. |
ed6fb7bd SC |
4837 | */ |
4838 | ||
252b5132 RH |
4839 | expr1.X_add_number = offset_expr.X_add_number; |
4840 | offset_expr.X_add_number = 0; | |
4841 | frag_grow (32); | |
9117d219 NC |
4842 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4843 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
17a2f251 TS |
4844 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
4845 | tempreg, lw_reloc_type, mips_gp_register); | |
252b5132 RH |
4846 | if (expr1.X_add_number == 0) |
4847 | { | |
4848 | int off; | |
f9419b05 | 4849 | char *p; |
252b5132 RH |
4850 | |
4851 | if (breg == 0) | |
4852 | off = 0; | |
4853 | else | |
4854 | { | |
4855 | /* We're going to put in an addu instruction using | |
4856 | tempreg, so we may as well insert the nop right | |
4857 | now. */ | |
17a2f251 | 4858 | macro_build (NULL, &icnt, NULL, "nop", ""); |
252b5132 RH |
4859 | off = 4; |
4860 | } | |
4861 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4862 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4863 | (breg == 0 | |
4864 | ? mips_opts.warn_about_macros | |
4865 | : 0)), | |
c4e7957c | 4866 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4867 | if (breg == 0) |
4868 | { | |
17a2f251 | 4869 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
4870 | p += 4; |
4871 | } | |
f899b4b8 | 4872 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
17a2f251 | 4873 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
4874 | /* FIXME: If breg == 0, and the next instruction uses |
4875 | $tempreg, then if this variant case is used an extra | |
4876 | nop will be generated. */ | |
4877 | } | |
4878 | else if (expr1.X_add_number >= -0x8000 | |
4879 | && expr1.X_add_number < 0x8000) | |
4880 | { | |
17a2f251 TS |
4881 | macro_build (NULL, &icnt, NULL, "nop", ""); |
4882 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, | |
4883 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); | |
c4e7957c TS |
4884 | frag_var (rs_machine_dependent, 0, 0, |
4885 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4886 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4887 | } |
4888 | else | |
4889 | { | |
4890 | int off1; | |
4891 | ||
4892 | /* If we are going to add in a base register, and the | |
4893 | target register and the base register are the same, | |
4894 | then we are using AT as a temporary register. Since | |
4895 | we want to load the constant into AT, we add our | |
4896 | current AT (from the global offset table) and the | |
4897 | register into the register now, and pretend we were | |
4898 | not using a base register. */ | |
4899 | if (breg != treg) | |
4900 | off1 = 0; | |
4901 | else | |
4902 | { | |
17a2f251 TS |
4903 | macro_build (NULL, &icnt, NULL, "nop", ""); |
4904 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4905 | treg, AT, breg); | |
252b5132 RH |
4906 | breg = 0; |
4907 | tempreg = treg; | |
4908 | off1 = -8; | |
4909 | } | |
4910 | ||
4911 | /* Set mips_optimize around the lui instruction to avoid | |
4912 | inserting an unnecessary nop after the lw. */ | |
4913 | hold_mips_optimize = mips_optimize; | |
4914 | mips_optimize = 2; | |
c4e7957c | 4915 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
4916 | mips_optimize = hold_mips_optimize; |
4917 | ||
17a2f251 TS |
4918 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
4919 | AT, AT, BFD_RELOC_LO16); | |
4920 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4921 | tempreg, tempreg, AT); | |
c4e7957c TS |
4922 | frag_var (rs_machine_dependent, 0, 0, |
4923 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4924 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4925 | used_at = 1; |
4926 | } | |
4927 | } | |
f5040a92 AO |
4928 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
4929 | { | |
4930 | char *p = NULL; | |
4931 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
4932 | int adj = 0; | |
4933 | ||
4934 | /* If this is a reference to an external, and there is no | |
4935 | constant, or local symbol (*), with or without a | |
4936 | constant, we want | |
4937 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4938 | or if tempreg is PIC_CALL_REG | |
4939 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
4940 | ||
4941 | If we have a small constant, and this is a reference to | |
4942 | an external symbol, we want | |
4943 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4944 | addiu $tempreg,$tempreg,<constant> | |
4945 | ||
4946 | If we have a large constant, and this is a reference to | |
4947 | an external symbol, we want | |
4948 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4949 | lui $at,<hiconstant> | |
4950 | addiu $at,$at,<loconstant> | |
4951 | addu $tempreg,$tempreg,$at | |
4952 | ||
4953 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
4954 | local symbols, even though it introduces an additional | |
4955 | instruction. */ | |
4956 | ||
4957 | frag_grow (28); | |
4958 | if (offset_expr.X_add_number == 0 && tempreg == PIC_CALL_REG) | |
4959 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
4960 | if (offset_expr.X_add_number) | |
4961 | { | |
4962 | frag_now->tc_frag_data.tc_fr_offset = | |
4963 | expr1.X_add_number = offset_expr.X_add_number; | |
4964 | offset_expr.X_add_number = 0; | |
4965 | ||
17a2f251 TS |
4966 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
4967 | "t,o(b)", tempreg, lw_reloc_type, | |
4968 | mips_gp_register); | |
f5040a92 AO |
4969 | |
4970 | if (expr1.X_add_number >= -0x8000 | |
4971 | && expr1.X_add_number < 0x8000) | |
4972 | { | |
17a2f251 TS |
4973 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, |
4974 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 AO |
4975 | p = frag_var (rs_machine_dependent, 4, 0, |
4976 | RELAX_ENCODE (8, 4, 0, 0, 0, 0), | |
4977 | offset_expr.X_add_symbol, 0, NULL); | |
4978 | } | |
4979 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number)) | |
4980 | { | |
4981 | int dreg; | |
4982 | ||
4983 | /* If we are going to add in a base register, and the | |
4984 | target register and the base register are the same, | |
4985 | then we are using AT as a temporary register. Since | |
4986 | we want to load the constant into AT, we add our | |
4987 | current AT (from the global offset table) and the | |
4988 | register into the register now, and pretend we were | |
4989 | not using a base register. */ | |
4990 | if (breg != treg) | |
4991 | dreg = tempreg; | |
4992 | else | |
4993 | { | |
4994 | assert (tempreg == AT); | |
17a2f251 TS |
4995 | macro_build (NULL, &icnt,NULL, ADDRESS_ADD_INSN, |
4996 | "d,v,t", treg, AT, breg); | |
f5040a92 AO |
4997 | dreg = treg; |
4998 | adj = 4; | |
4999 | } | |
5000 | ||
17a2f251 TS |
5001 | macro_build_lui (NULL, &icnt, &expr1, AT); |
5002 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, | |
5003 | "t,r,j", AT, AT, BFD_RELOC_LO16); | |
5004 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5005 | dreg, dreg, AT); | |
f5040a92 AO |
5006 | |
5007 | p = frag_var (rs_machine_dependent, 4 + adj, 0, | |
5008 | RELAX_ENCODE (16 + adj, 4 + adj, | |
5009 | 0, 0, 0, 0), | |
5010 | offset_expr.X_add_symbol, 0, NULL); | |
5011 | ||
5012 | used_at = 1; | |
5013 | } | |
5014 | else | |
5015 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5016 | ||
5017 | offset_expr.X_add_number = expr1.X_add_number; | |
5018 | ||
f899b4b8 | 5019 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
17a2f251 | 5020 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP, |
f5040a92 AO |
5021 | mips_gp_register); |
5022 | if (adj) | |
5023 | { | |
17a2f251 | 5024 | macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5025 | treg, tempreg, breg); |
f5040a92 AO |
5026 | breg = 0; |
5027 | tempreg = treg; | |
5028 | } | |
5029 | } | |
5030 | else | |
5031 | { | |
17a2f251 TS |
5032 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5033 | "t,o(b)", tempreg, lw_reloc_type, | |
5034 | mips_gp_register); | |
f5040a92 AO |
5035 | if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP) |
5036 | p = frag_var (rs_machine_dependent, 0, 0, | |
5037 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5038 | offset_expr.X_add_symbol, 0, NULL); | |
5039 | } | |
5040 | ||
5041 | if (! p) | |
5042 | { | |
5043 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5044 | that this does not become a variant frag. */ | |
5045 | frag_wane (frag_now); | |
5046 | frag_new (0); | |
5047 | } | |
5048 | } | |
5049 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 RH |
5050 | { |
5051 | int gpdel; | |
f9419b05 | 5052 | char *p; |
9117d219 NC |
5053 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5054 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5055 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5056 | |
5057 | /* This is the large GOT case. If this is a reference to an | |
5058 | external symbol, and there is no constant, we want | |
5059 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5060 | addu $tempreg,$tempreg,$gp | |
5061 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
5062 | or if tempreg is PIC_CALL_REG |
5063 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5064 | addu $tempreg,$tempreg,$gp | |
5065 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5066 | For a local symbol, we want |
5067 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5068 | nop | |
5069 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5070 | ||
5071 | If we have a small constant, and this is a reference to | |
5072 | an external symbol, we want | |
5073 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5074 | addu $tempreg,$tempreg,$gp | |
5075 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5076 | nop | |
5077 | addiu $tempreg,$tempreg,<constant> | |
5078 | For a local symbol, we want | |
5079 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5080 | nop | |
5081 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5082 | ||
5083 | If we have a large constant, and this is a reference to | |
5084 | an external symbol, we want | |
5085 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5086 | addu $tempreg,$tempreg,$gp | |
5087 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5088 | lui $at,<hiconstant> | |
5089 | addiu $at,$at,<loconstant> | |
5090 | addu $tempreg,$tempreg,$at | |
5091 | For a local symbol, we want | |
5092 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5093 | lui $at,<hiconstant> | |
5094 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5095 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5096 | */ |
438c16b8 | 5097 | |
252b5132 RH |
5098 | expr1.X_add_number = offset_expr.X_add_number; |
5099 | offset_expr.X_add_number = 0; | |
5100 | frag_grow (52); | |
f7ea7ef2 | 5101 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5102 | gpdel = 4; |
5103 | else | |
5104 | gpdel = 0; | |
9117d219 NC |
5105 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5106 | { | |
5107 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5108 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5109 | } | |
17a2f251 | 5110 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 5111 | tempreg, lui_reloc_type); |
17a2f251 TS |
5112 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5113 | tempreg, tempreg, mips_gp_register); | |
5114 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5115 | tempreg, lw_reloc_type, tempreg); | |
252b5132 RH |
5116 | if (expr1.X_add_number == 0) |
5117 | { | |
5118 | int off; | |
5119 | ||
5120 | if (breg == 0) | |
5121 | off = 0; | |
5122 | else | |
5123 | { | |
5124 | /* We're going to put in an addu instruction using | |
5125 | tempreg, so we may as well insert the nop right | |
5126 | now. */ | |
17a2f251 | 5127 | macro_build (NULL, &icnt, NULL, "nop", ""); |
252b5132 RH |
5128 | off = 4; |
5129 | } | |
5130 | ||
5131 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5132 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
5133 | 8 + gpdel, 0, | |
5134 | (breg == 0 | |
5135 | ? mips_opts.warn_about_macros | |
5136 | : 0)), | |
c4e7957c | 5137 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5138 | } |
5139 | else if (expr1.X_add_number >= -0x8000 | |
5140 | && expr1.X_add_number < 0x8000) | |
5141 | { | |
17a2f251 TS |
5142 | macro_build (NULL, &icnt, NULL, "nop", ""); |
5143 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", | |
5144 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 RH |
5145 | |
5146 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5147 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
5148 | (breg == 0 | |
5149 | ? mips_opts.warn_about_macros | |
5150 | : 0)), | |
c4e7957c | 5151 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5152 | } |
5153 | else | |
5154 | { | |
5155 | int adj, dreg; | |
5156 | ||
5157 | /* If we are going to add in a base register, and the | |
5158 | target register and the base register are the same, | |
5159 | then we are using AT as a temporary register. Since | |
5160 | we want to load the constant into AT, we add our | |
5161 | current AT (from the global offset table) and the | |
5162 | register into the register now, and pretend we were | |
5163 | not using a base register. */ | |
5164 | if (breg != treg) | |
5165 | { | |
5166 | adj = 0; | |
5167 | dreg = tempreg; | |
5168 | } | |
5169 | else | |
5170 | { | |
5171 | assert (tempreg == AT); | |
17a2f251 TS |
5172 | macro_build (NULL, &icnt, NULL, "nop", ""); |
5173 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5174 | treg, AT, breg); | |
252b5132 RH |
5175 | dreg = treg; |
5176 | adj = 8; | |
5177 | } | |
5178 | ||
5179 | /* Set mips_optimize around the lui instruction to avoid | |
5180 | inserting an unnecessary nop after the lw. */ | |
5181 | hold_mips_optimize = mips_optimize; | |
5182 | mips_optimize = 2; | |
c4e7957c | 5183 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5184 | mips_optimize = hold_mips_optimize; |
5185 | ||
17a2f251 TS |
5186 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5187 | AT, AT, BFD_RELOC_LO16); | |
5188 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5189 | dreg, dreg, AT); | |
252b5132 RH |
5190 | |
5191 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5192 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5193 | 8 + gpdel, 0, | |
5194 | (breg == 0 | |
5195 | ? mips_opts.warn_about_macros | |
5196 | : 0)), | |
c4e7957c | 5197 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5198 | |
5199 | used_at = 1; | |
5200 | } | |
5201 | ||
5202 | if (gpdel > 0) | |
5203 | { | |
5204 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5205 | the first instruction on the main stream does not. */ |
17a2f251 | 5206 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
5207 | p += 4; |
5208 | } | |
ed6fb7bd | 5209 | |
f899b4b8 TS |
5210 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5211 | tempreg, local_reloc_type, mips_gp_register); | |
252b5132 | 5212 | p += 4; |
f5040a92 | 5213 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5214 | && expr1.X_add_number < 0x8000) |
5215 | { | |
17a2f251 | 5216 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 | 5217 | p += 4; |
f899b4b8 | 5218 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, |
17a2f251 | 5219 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 | 5220 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5221 | register, the external symbol case ended with a load, |
5222 | so if the symbol turns out to not be external, and | |
5223 | the next instruction uses tempreg, an unnecessary nop | |
5224 | will be inserted. */ | |
252b5132 RH |
5225 | } |
5226 | else | |
5227 | { | |
5228 | if (breg == treg) | |
5229 | { | |
5230 | /* We must add in the base register now, as in the | |
f5040a92 | 5231 | external symbol case. */ |
252b5132 | 5232 | assert (tempreg == AT); |
17a2f251 | 5233 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 | 5234 | p += 4; |
17a2f251 TS |
5235 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5236 | treg, AT, breg); | |
252b5132 RH |
5237 | p += 4; |
5238 | tempreg = treg; | |
5239 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5240 | it in in both cases. */ |
252b5132 RH |
5241 | breg = 0; |
5242 | } | |
5243 | ||
5244 | macro_build_lui (p, &icnt, &expr1, AT); | |
5245 | p += 4; | |
17a2f251 TS |
5246 | macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5247 | AT, AT, BFD_RELOC_LO16); | |
252b5132 | 5248 | p += 4; |
17a2f251 TS |
5249 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5250 | tempreg, tempreg, AT); | |
252b5132 RH |
5251 | p += 4; |
5252 | } | |
5253 | } | |
f5040a92 AO |
5254 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5255 | { | |
5256 | char *p = NULL; | |
5257 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; | |
5258 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
5259 | int adj = 0; | |
5260 | ||
5261 | /* This is the large GOT case. If this is a reference to an | |
5262 | external symbol, and there is no constant, we want | |
5263 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5264 | add $tempreg,$tempreg,$gp | |
5265 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5266 | or if tempreg is PIC_CALL_REG | |
5267 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5268 | add $tempreg,$tempreg,$gp | |
5269 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5270 | ||
5271 | If we have a small constant, and this is a reference to | |
5272 | an external symbol, we want | |
5273 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5274 | add $tempreg,$tempreg,$gp | |
5275 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5276 | addi $tempreg,$tempreg,<constant> | |
5277 | ||
5278 | If we have a large constant, and this is a reference to | |
5279 | an external symbol, we want | |
5280 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5281 | addu $tempreg,$tempreg,$gp | |
5282 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5283 | lui $at,<hiconstant> | |
5284 | addi $at,$at,<loconstant> | |
5285 | add $tempreg,$tempreg,$at | |
5286 | ||
5287 | If we have NewABI, and we know it's a local symbol, we want | |
5288 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5289 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5290 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5291 | ||
5292 | frag_grow (40); | |
5293 | ||
5294 | frag_now->tc_frag_data.tc_fr_offset = | |
5295 | expr1.X_add_number = offset_expr.X_add_number; | |
5296 | offset_expr.X_add_number = 0; | |
5297 | ||
5298 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) | |
5299 | { | |
5300 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5301 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5302 | } | |
17a2f251 | 5303 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
f5040a92 | 5304 | tempreg, lui_reloc_type); |
17a2f251 TS |
5305 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5306 | tempreg, tempreg, mips_gp_register); | |
5307 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
f5040a92 AO |
5308 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
5309 | ||
5310 | if (expr1.X_add_number == 0) | |
5311 | { | |
5312 | p = frag_var (rs_machine_dependent, 8, 0, | |
5313 | RELAX_ENCODE (12, 8, 0, 4, 0, | |
5314 | mips_opts.warn_about_macros), | |
5315 | offset_expr.X_add_symbol, 0, NULL); | |
684022ea | 5316 | } |
f5040a92 AO |
5317 | else if (expr1.X_add_number >= -0x8000 |
5318 | && expr1.X_add_number < 0x8000) | |
5319 | { | |
17a2f251 TS |
5320 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5321 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 AO |
5322 | p = frag_var (rs_machine_dependent, 8, 0, |
5323 | RELAX_ENCODE (16, 8, 0, 4, 0, | |
5324 | mips_opts.warn_about_macros), | |
5325 | offset_expr.X_add_symbol, 0, NULL); | |
5326 | } | |
5327 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number)) | |
5328 | { | |
5329 | int dreg; | |
5330 | ||
5331 | /* If we are going to add in a base register, and the | |
5332 | target register and the base register are the same, | |
5333 | then we are using AT as a temporary register. Since | |
5334 | we want to load the constant into AT, we add our | |
5335 | current AT (from the global offset table) and the | |
5336 | register into the register now, and pretend we were | |
5337 | not using a base register. */ | |
5338 | if (breg != treg) | |
5339 | dreg = tempreg; | |
5340 | else | |
5341 | { | |
5342 | assert (tempreg == AT); | |
17a2f251 TS |
5343 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5344 | treg, AT, breg); | |
f5040a92 AO |
5345 | dreg = treg; |
5346 | adj = 4; | |
5347 | } | |
5348 | ||
5349 | /* Set mips_optimize around the lui instruction to avoid | |
5350 | inserting an unnecessary nop after the lw. */ | |
17a2f251 TS |
5351 | macro_build_lui (NULL, &icnt, &expr1, AT); |
5352 | macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, | |
5353 | "t,r,j", AT, AT, BFD_RELOC_LO16); | |
5354 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5355 | dreg, dreg, AT); | |
f5040a92 AO |
5356 | |
5357 | p = frag_var (rs_machine_dependent, 8 + adj, 0, | |
5358 | RELAX_ENCODE (24 + adj, 8 + adj, | |
5359 | 0, 4, 0, | |
5360 | (breg == 0 | |
5361 | ? mips_opts.warn_about_macros | |
5362 | : 0)), | |
5363 | offset_expr.X_add_symbol, 0, NULL); | |
5364 | ||
5365 | used_at = 1; | |
5366 | } | |
5367 | else | |
5368 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5369 | ||
5370 | offset_expr.X_add_number = expr1.X_add_number; | |
f899b4b8 | 5371 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5372 | tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f899b4b8 | 5373 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5374 | tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST); |
f5040a92 AO |
5375 | if (adj) |
5376 | { | |
17a2f251 TS |
5377 | macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
5378 | treg, tempreg, breg); | |
f5040a92 AO |
5379 | breg = 0; |
5380 | tempreg = treg; | |
5381 | } | |
5382 | } | |
252b5132 RH |
5383 | else if (mips_pic == EMBEDDED_PIC) |
5384 | { | |
5385 | /* We use | |
cdf6fd85 | 5386 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 | 5387 | */ |
17a2f251 TS |
5388 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5389 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
5390 | } |
5391 | else | |
5392 | abort (); | |
5393 | ||
5394 | if (breg != 0) | |
4d34fb5f TS |
5395 | { |
5396 | char *s; | |
5397 | ||
5398 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
b7c7d6c1 | 5399 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5400 | else |
f899b4b8 | 5401 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5402 | |
17a2f251 | 5403 | macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5404 | } |
252b5132 RH |
5405 | |
5406 | if (! used_at) | |
5407 | return; | |
5408 | ||
5409 | break; | |
5410 | ||
5411 | case M_J_A: | |
5412 | /* The j instruction may not be used in PIC code, since it | |
5413 | requires an absolute address. We convert it to a b | |
5414 | instruction. */ | |
5415 | if (mips_pic == NO_PIC) | |
17a2f251 | 5416 | macro_build (NULL, &icnt, &offset_expr, "j", "a"); |
252b5132 | 5417 | else |
17a2f251 | 5418 | macro_build (NULL, &icnt, &offset_expr, "b", "p"); |
252b5132 RH |
5419 | return; |
5420 | ||
5421 | /* The jal instructions must be handled as macros because when | |
5422 | generating PIC code they expand to multi-instruction | |
5423 | sequences. Normally they are simple instructions. */ | |
5424 | case M_JAL_1: | |
5425 | dreg = RA; | |
5426 | /* Fall through. */ | |
5427 | case M_JAL_2: | |
5428 | if (mips_pic == NO_PIC | |
5429 | || mips_pic == EMBEDDED_PIC) | |
17a2f251 | 5430 | macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5431 | else if (mips_pic == SVR4_PIC) |
5432 | { | |
5433 | if (sreg != PIC_CALL_REG) | |
5434 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5435 | |
17a2f251 | 5436 | macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5437 | if (! HAVE_NEWABI) |
252b5132 | 5438 | { |
6478892d TS |
5439 | if (mips_cprestore_offset < 0) |
5440 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5441 | else | |
5442 | { | |
7a621144 DJ |
5443 | if (! mips_frame_reg_valid) |
5444 | { | |
5445 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5446 | /* Quiet this warning. */ | |
5447 | mips_frame_reg_valid = 1; | |
5448 | } | |
5449 | if (! mips_cprestore_valid) | |
5450 | { | |
5451 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5452 | /* Quiet this warning. */ | |
5453 | mips_cprestore_valid = 1; | |
5454 | } | |
6478892d | 5455 | expr1.X_add_number = mips_cprestore_offset; |
17a2f251 | 5456 | macro_build_ldst_constoffset (NULL, &icnt, &expr1, |
f899b4b8 TS |
5457 | ADDRESS_LOAD_INSN, |
5458 | mips_gp_register, | |
256ab948 TS |
5459 | mips_frame_reg, |
5460 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5461 | } |
252b5132 RH |
5462 | } |
5463 | } | |
5464 | else | |
5465 | abort (); | |
5466 | ||
5467 | return; | |
5468 | ||
5469 | case M_JAL_A: | |
5470 | if (mips_pic == NO_PIC) | |
17a2f251 | 5471 | macro_build (NULL, &icnt, &offset_expr, "jal", "a"); |
252b5132 RH |
5472 | else if (mips_pic == SVR4_PIC) |
5473 | { | |
f9419b05 TS |
5474 | char *p; |
5475 | ||
252b5132 RH |
5476 | /* If this is a reference to an external symbol, and we are |
5477 | using a small GOT, we want | |
5478 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5479 | nop | |
f9419b05 | 5480 | jalr $ra,$25 |
252b5132 RH |
5481 | nop |
5482 | lw $gp,cprestore($sp) | |
5483 | The cprestore value is set using the .cprestore | |
5484 | pseudo-op. If we are using a big GOT, we want | |
5485 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5486 | addu $25,$25,$gp | |
5487 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5488 | nop | |
f9419b05 | 5489 | jalr $ra,$25 |
252b5132 RH |
5490 | nop |
5491 | lw $gp,cprestore($sp) | |
5492 | If the symbol is not external, we want | |
5493 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5494 | nop | |
5495 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5496 | jalr $ra,$25 |
252b5132 | 5497 | nop |
438c16b8 | 5498 | lw $gp,cprestore($sp) |
f5040a92 AO |
5499 | |
5500 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5501 | sequences above, minus nops, unless the symbol is local, | |
5502 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5503 | GOT_DISP. */ | |
438c16b8 | 5504 | if (HAVE_NEWABI) |
252b5132 | 5505 | { |
f5040a92 AO |
5506 | if (! mips_big_got) |
5507 | { | |
5508 | frag_grow (4); | |
17a2f251 TS |
5509 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5510 | "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 AO |
5511 | mips_gp_register); |
5512 | frag_var (rs_machine_dependent, 0, 0, | |
5513 | RELAX_ENCODE (0, 0, -4, 0, 0, 0), | |
5514 | offset_expr.X_add_symbol, 0, NULL); | |
5515 | } | |
5516 | else | |
5517 | { | |
5518 | frag_grow (20); | |
17a2f251 TS |
5519 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
5520 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16); | |
5521 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5522 | PIC_CALL_REG, PIC_CALL_REG, mips_gp_register); | |
5523 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
5524 | "t,o(b)", PIC_CALL_REG, | |
5525 | BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
f5040a92 AO |
5526 | p = frag_var (rs_machine_dependent, 8, 0, |
5527 | RELAX_ENCODE (12, 8, 0, 4, 0, 0), | |
5528 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 TS |
5529 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5530 | "t,o(b)", PIC_CALL_REG, | |
17a2f251 | 5531 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f899b4b8 | 5532 | macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
dc9461f6 | 5533 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
17a2f251 | 5534 | BFD_RELOC_MIPS_GOT_OFST); |
f5040a92 | 5535 | } |
684022ea | 5536 | |
438c16b8 | 5537 | macro_build_jalr (icnt, &offset_expr); |
252b5132 RH |
5538 | } |
5539 | else | |
5540 | { | |
438c16b8 TS |
5541 | frag_grow (40); |
5542 | if (! mips_big_got) | |
5543 | { | |
17a2f251 TS |
5544 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
5545 | "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
5546 | mips_gp_register); | |
5547 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
438c16b8 TS |
5548 | p = frag_var (rs_machine_dependent, 4, 0, |
5549 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5550 | offset_expr.X_add_symbol, 0, NULL); | |
5551 | } | |
252b5132 | 5552 | else |
252b5132 | 5553 | { |
438c16b8 TS |
5554 | int gpdel; |
5555 | ||
5556 | if (reg_needs_delay (mips_gp_register)) | |
5557 | gpdel = 4; | |
5558 | else | |
5559 | gpdel = 0; | |
17a2f251 TS |
5560 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", |
5561 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16); | |
5562 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5563 | PIC_CALL_REG, PIC_CALL_REG, mips_gp_register); | |
5564 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, | |
5565 | "t,o(b)", PIC_CALL_REG, | |
5566 | BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5567 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
438c16b8 TS |
5568 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
5569 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5570 | 8 + gpdel, 0, 0), | |
5571 | offset_expr.X_add_symbol, 0, NULL); | |
5572 | if (gpdel > 0) | |
5573 | { | |
17a2f251 | 5574 | macro_build (p, &icnt, NULL, "nop", ""); |
438c16b8 TS |
5575 | p += 4; |
5576 | } | |
f899b4b8 | 5577 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
17a2f251 TS |
5578 | "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, |
5579 | mips_gp_register); | |
438c16b8 | 5580 | p += 4; |
17a2f251 | 5581 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
5582 | p += 4; |
5583 | } | |
f899b4b8 | 5584 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
438c16b8 | 5585 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
17a2f251 | 5586 | BFD_RELOC_LO16); |
438c16b8 TS |
5587 | macro_build_jalr (icnt, &offset_expr); |
5588 | ||
6478892d TS |
5589 | if (mips_cprestore_offset < 0) |
5590 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5591 | else | |
5592 | { | |
7a621144 DJ |
5593 | if (! mips_frame_reg_valid) |
5594 | { | |
5595 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5596 | /* Quiet this warning. */ | |
5597 | mips_frame_reg_valid = 1; | |
5598 | } | |
5599 | if (! mips_cprestore_valid) | |
5600 | { | |
5601 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5602 | /* Quiet this warning. */ | |
5603 | mips_cprestore_valid = 1; | |
5604 | } | |
6478892d | 5605 | if (mips_opts.noreorder) |
17a2f251 | 5606 | macro_build (NULL, &icnt, NULL, "nop", ""); |
6478892d | 5607 | expr1.X_add_number = mips_cprestore_offset; |
17a2f251 | 5608 | macro_build_ldst_constoffset (NULL, &icnt, &expr1, |
f899b4b8 TS |
5609 | ADDRESS_LOAD_INSN, |
5610 | mips_gp_register, | |
256ab948 TS |
5611 | mips_frame_reg, |
5612 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5613 | } |
252b5132 RH |
5614 | } |
5615 | } | |
5616 | else if (mips_pic == EMBEDDED_PIC) | |
5617 | { | |
17a2f251 | 5618 | macro_build (NULL, &icnt, &offset_expr, "bal", "p"); |
252b5132 RH |
5619 | /* The linker may expand the call to a longer sequence which |
5620 | uses $at, so we must break rather than return. */ | |
5621 | break; | |
5622 | } | |
5623 | else | |
5624 | abort (); | |
5625 | ||
5626 | return; | |
5627 | ||
5628 | case M_LB_AB: | |
5629 | s = "lb"; | |
5630 | goto ld; | |
5631 | case M_LBU_AB: | |
5632 | s = "lbu"; | |
5633 | goto ld; | |
5634 | case M_LH_AB: | |
5635 | s = "lh"; | |
5636 | goto ld; | |
5637 | case M_LHU_AB: | |
5638 | s = "lhu"; | |
5639 | goto ld; | |
5640 | case M_LW_AB: | |
5641 | s = "lw"; | |
5642 | goto ld; | |
5643 | case M_LWC0_AB: | |
5644 | s = "lwc0"; | |
bdaaa2e1 | 5645 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5646 | coproc = 1; |
5647 | goto ld; | |
5648 | case M_LWC1_AB: | |
5649 | s = "lwc1"; | |
bdaaa2e1 | 5650 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5651 | coproc = 1; |
5652 | goto ld; | |
5653 | case M_LWC2_AB: | |
5654 | s = "lwc2"; | |
bdaaa2e1 | 5655 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5656 | coproc = 1; |
5657 | goto ld; | |
5658 | case M_LWC3_AB: | |
5659 | s = "lwc3"; | |
bdaaa2e1 | 5660 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5661 | coproc = 1; |
5662 | goto ld; | |
5663 | case M_LWL_AB: | |
5664 | s = "lwl"; | |
5665 | lr = 1; | |
5666 | goto ld; | |
5667 | case M_LWR_AB: | |
5668 | s = "lwr"; | |
5669 | lr = 1; | |
5670 | goto ld; | |
5671 | case M_LDC1_AB: | |
fef14a42 | 5672 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5673 | { |
5674 | as_bad (_("opcode not supported on this processor")); | |
5675 | return; | |
5676 | } | |
5677 | s = "ldc1"; | |
bdaaa2e1 | 5678 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5679 | coproc = 1; |
5680 | goto ld; | |
5681 | case M_LDC2_AB: | |
5682 | s = "ldc2"; | |
bdaaa2e1 | 5683 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5684 | coproc = 1; |
5685 | goto ld; | |
5686 | case M_LDC3_AB: | |
5687 | s = "ldc3"; | |
bdaaa2e1 | 5688 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5689 | coproc = 1; |
5690 | goto ld; | |
5691 | case M_LDL_AB: | |
5692 | s = "ldl"; | |
5693 | lr = 1; | |
5694 | goto ld; | |
5695 | case M_LDR_AB: | |
5696 | s = "ldr"; | |
5697 | lr = 1; | |
5698 | goto ld; | |
5699 | case M_LL_AB: | |
5700 | s = "ll"; | |
5701 | goto ld; | |
5702 | case M_LLD_AB: | |
5703 | s = "lld"; | |
5704 | goto ld; | |
5705 | case M_LWU_AB: | |
5706 | s = "lwu"; | |
5707 | ld: | |
5708 | if (breg == treg || coproc || lr) | |
5709 | { | |
5710 | tempreg = AT; | |
5711 | used_at = 1; | |
5712 | } | |
5713 | else | |
5714 | { | |
5715 | tempreg = treg; | |
5716 | used_at = 0; | |
5717 | } | |
5718 | goto ld_st; | |
5719 | case M_SB_AB: | |
5720 | s = "sb"; | |
5721 | goto st; | |
5722 | case M_SH_AB: | |
5723 | s = "sh"; | |
5724 | goto st; | |
5725 | case M_SW_AB: | |
5726 | s = "sw"; | |
5727 | goto st; | |
5728 | case M_SWC0_AB: | |
5729 | s = "swc0"; | |
bdaaa2e1 | 5730 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5731 | coproc = 1; |
5732 | goto st; | |
5733 | case M_SWC1_AB: | |
5734 | s = "swc1"; | |
bdaaa2e1 | 5735 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5736 | coproc = 1; |
5737 | goto st; | |
5738 | case M_SWC2_AB: | |
5739 | s = "swc2"; | |
bdaaa2e1 | 5740 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5741 | coproc = 1; |
5742 | goto st; | |
5743 | case M_SWC3_AB: | |
5744 | s = "swc3"; | |
bdaaa2e1 | 5745 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5746 | coproc = 1; |
5747 | goto st; | |
5748 | case M_SWL_AB: | |
5749 | s = "swl"; | |
5750 | goto st; | |
5751 | case M_SWR_AB: | |
5752 | s = "swr"; | |
5753 | goto st; | |
5754 | case M_SC_AB: | |
5755 | s = "sc"; | |
5756 | goto st; | |
5757 | case M_SCD_AB: | |
5758 | s = "scd"; | |
5759 | goto st; | |
5760 | case M_SDC1_AB: | |
fef14a42 | 5761 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5762 | { |
5763 | as_bad (_("opcode not supported on this processor")); | |
5764 | return; | |
5765 | } | |
5766 | s = "sdc1"; | |
5767 | coproc = 1; | |
bdaaa2e1 | 5768 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5769 | goto st; |
5770 | case M_SDC2_AB: | |
5771 | s = "sdc2"; | |
bdaaa2e1 | 5772 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5773 | coproc = 1; |
5774 | goto st; | |
5775 | case M_SDC3_AB: | |
5776 | s = "sdc3"; | |
bdaaa2e1 | 5777 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5778 | coproc = 1; |
5779 | goto st; | |
5780 | case M_SDL_AB: | |
5781 | s = "sdl"; | |
5782 | goto st; | |
5783 | case M_SDR_AB: | |
5784 | s = "sdr"; | |
5785 | st: | |
5786 | tempreg = AT; | |
5787 | used_at = 1; | |
5788 | ld_st: | |
bdaaa2e1 | 5789 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5790 | if (mask == M_LWC1_AB |
5791 | || mask == M_SWC1_AB | |
5792 | || mask == M_LDC1_AB | |
5793 | || mask == M_SDC1_AB | |
5794 | || mask == M_L_DAB | |
5795 | || mask == M_S_DAB) | |
5796 | fmt = "T,o(b)"; | |
5797 | else if (coproc) | |
5798 | fmt = "E,o(b)"; | |
5799 | else | |
5800 | fmt = "t,o(b)"; | |
5801 | ||
256ab948 TS |
5802 | /* Sign-extending 32-bit constants makes their handling easier. |
5803 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5804 | described below. */ | |
5805 | if ((! HAVE_64BIT_ADDRESSES | |
5806 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
5807 | && (offset_expr.X_op == O_constant)) | |
ae826530 TS |
5808 | { |
5809 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff) | |
5810 | && ~(offset_expr.X_add_number | 0xffffffff)) | |
5811 | as_bad (_("too large constant specified")); | |
5812 | ||
256ab948 TS |
5813 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5814 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5815 | } |
256ab948 | 5816 | |
afdbd6d0 CD |
5817 | /* For embedded PIC, we allow loads where the offset is calculated |
5818 | by subtracting a symbol in the current segment from an unknown | |
5819 | symbol, relative to a base register, e.g.: | |
5820 | <op> $treg, <sym>-<localsym>($breg) | |
5821 | This is used by the compiler for switch statements. */ | |
76b3015f | 5822 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5823 | && offset_expr.X_op == O_subtract |
5824 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5825 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5826 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5827 | && (S_GET_SEGMENT | |
5828 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5829 | ->X_add_symbol) | |
5830 | == now_seg))) | |
5831 | && breg != 0 | |
5832 | && (offset_expr.X_add_number == 0 | |
5833 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5834 | { | |
5835 | /* For this case, we output the instructions: | |
5836 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5837 | addiu $tempreg,$tempreg,$breg | |
5838 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5839 | If the relocation would fit entirely in 16 bits, it would be | |
5840 | nice to emit: | |
5841 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5842 | instead, but that seems quite difficult. */ | |
17a2f251 TS |
5843 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
5844 | BFD_RELOC_PCREL_HI16_S); | |
5845 | macro_build (NULL, &icnt, NULL, | |
afdbd6d0 CD |
5846 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5847 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
b7c7d6c1 | 5848 | ? "addu" : "daddu"), |
afdbd6d0 | 5849 | "d,v,t", tempreg, tempreg, breg); |
17a2f251 TS |
5850 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, |
5851 | BFD_RELOC_PCREL_LO16, tempreg); | |
afdbd6d0 CD |
5852 | if (! used_at) |
5853 | return; | |
5854 | break; | |
5855 | } | |
5856 | ||
252b5132 RH |
5857 | if (offset_expr.X_op != O_constant |
5858 | && offset_expr.X_op != O_symbol) | |
5859 | { | |
5860 | as_bad (_("expression too complex")); | |
5861 | offset_expr.X_op = O_constant; | |
5862 | } | |
5863 | ||
5864 | /* A constant expression in PIC code can be handled just as it | |
5865 | is in non PIC code. */ | |
5866 | if (mips_pic == NO_PIC | |
5867 | || offset_expr.X_op == O_constant) | |
5868 | { | |
f9419b05 TS |
5869 | char *p; |
5870 | ||
252b5132 RH |
5871 | /* If this is a reference to a GP relative symbol, and there |
5872 | is no base register, we want | |
cdf6fd85 | 5873 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5874 | Otherwise, if there is no base register, we want |
5875 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5876 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5877 | If we have a constant, we need two instructions anyhow, | |
5878 | so we always use the latter form. | |
5879 | ||
5880 | If we have a base register, and this is a reference to a | |
5881 | GP relative symbol, we want | |
5882 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5883 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5884 | Otherwise we want |
5885 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5886 | addu $tempreg,$tempreg,$breg | |
5887 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5888 | With a constant we always use the latter case. |
76b3015f | 5889 | |
d6bc6245 TS |
5890 | With 64bit address space and no base register and $at usable, |
5891 | we want | |
5892 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5893 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5894 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5895 | dsll32 $tempreg,0 | |
5896 | daddu $tempreg,$at | |
5897 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5898 | If we have a base register, we want | |
5899 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5900 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5901 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5902 | daddu $at,$breg | |
5903 | dsll32 $tempreg,0 | |
5904 | daddu $tempreg,$at | |
5905 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5906 | ||
5907 | Without $at we can't generate the optimal path for superscalar | |
5908 | processors here since this would require two temporary registers. | |
5909 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5910 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5911 | dsll $tempreg,16 | |
5912 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5913 | dsll $tempreg,16 | |
5914 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5915 | If we have a base register, we want | |
5916 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5917 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5918 | dsll $tempreg,16 | |
5919 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5920 | dsll $tempreg,16 | |
5921 | daddu $tempreg,$tempreg,$breg | |
5922 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5923 | |
5924 | If we have 64-bit addresses, as an optimization, for | |
5925 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5926 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5927 | mechanism since it is more efficient. Note that due to |
5928 | the signed offset used by memory operations, the 32-bit | |
5929 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5930 | probably attempt to generate 64-bit constants more |
5931 | efficiently in general. | |
9214dd3b AO |
5932 | |
5933 | As an extension for architectures with 64-bit registers, | |
5934 | we don't truncate 64-bit addresses given as literal | |
5935 | constants down to 32 bits, to support existing practice | |
5936 | in the mips64 Linux (the kernel), that compiles source | |
5937 | files with -mabi=64, assembling them as o32 or n32 (with | |
5938 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
5939 | the whole kernel is loaded into a memory region that is | |
5940 | addressible with sign-extended 32-bit addresses, it is | |
5941 | wasteful to compute the upper 32 bits of every | |
5942 | non-literal address, that takes more space and time. | |
5943 | Some day this should probably be implemented as an | |
5944 | assembler option, such that the kernel doesn't have to | |
5945 | use such ugly hacks, even though it will still have to | |
5946 | end up converting the binary to ELF32 for a number of | |
5947 | platforms whose boot loaders don't support ELF64 | |
5948 | binaries. */ | |
256ab948 TS |
5949 | if ((HAVE_64BIT_ADDRESSES |
5950 | && ! (offset_expr.X_op == O_constant | |
5951 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
5952 | || (HAVE_64BIT_GPRS | |
5953 | && offset_expr.X_op == O_constant | |
5954 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 TS |
5955 | { |
5956 | p = NULL; | |
5957 | ||
5958 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5959 | hold the data for such large chunks. */ | |
5960 | ||
460597ba | 5961 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
5962 | { |
5963 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 5964 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 5965 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", |
17a2f251 | 5966 | AT, BFD_RELOC_HI16_S); |
d6bc6245 | 5967 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5968 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
d6bc6245 | 5969 | if (breg != 0) |
17a2f251 TS |
5970 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", |
5971 | AT, AT, breg); | |
5972 | macro_build (p, &icnt, NULL, "dsll32", "d,w,<", | |
5973 | tempreg, tempreg, 0); | |
5974 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", | |
5975 | tempreg, tempreg, AT); | |
5976 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5977 | BFD_RELOC_LO16, tempreg); | |
d6bc6245 TS |
5978 | used_at = 1; |
5979 | } | |
5980 | else | |
5981 | { | |
5982 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
17a2f251 | 5983 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
d6bc6245 | 5984 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
5985 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
5986 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
5987 | tempreg, tempreg, 16); | |
d6bc6245 | 5988 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
17a2f251 TS |
5989 | tempreg, tempreg, BFD_RELOC_HI16_S); |
5990 | macro_build (p, &icnt, NULL, "dsll", "d,w,<", | |
5991 | tempreg, tempreg, 16); | |
d6bc6245 | 5992 | if (breg != 0) |
17a2f251 TS |
5993 | macro_build (p, &icnt, NULL, "daddu", "d,v,t", |
5994 | tempreg, tempreg, breg); | |
5995 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5996 | BFD_RELOC_LO16, tempreg); | |
d6bc6245 TS |
5997 | } |
5998 | ||
5999 | return; | |
6000 | } | |
256ab948 TS |
6001 | |
6002 | if (offset_expr.X_op == O_constant | |
6003 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
5a7a0b7b | 6004 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 6005 | |
252b5132 RH |
6006 | if (breg == 0) |
6007 | { | |
e7d556df | 6008 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6009 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6010 | p = NULL; | |
6011 | else | |
6012 | { | |
6013 | frag_grow (20); | |
17a2f251 TS |
6014 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, |
6015 | BFD_RELOC_GPREL16, mips_gp_register); | |
252b5132 RH |
6016 | p = frag_var (rs_machine_dependent, 8, 0, |
6017 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
6018 | (mips_opts.warn_about_macros | |
6019 | || (used_at | |
6020 | && mips_opts.noat))), | |
956cd1d6 | 6021 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6022 | used_at = 0; |
6023 | } | |
6024 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6025 | if (p != NULL) | |
6026 | p += 4; | |
6027 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
17a2f251 | 6028 | BFD_RELOC_LO16, tempreg); |
252b5132 RH |
6029 | } |
6030 | else | |
6031 | { | |
e7d556df | 6032 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6033 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6034 | p = NULL; | |
6035 | else | |
6036 | { | |
6037 | frag_grow (28); | |
17a2f251 TS |
6038 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6039 | tempreg, breg, mips_gp_register); | |
6040 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, | |
6041 | BFD_RELOC_GPREL16, tempreg); | |
252b5132 RH |
6042 | p = frag_var (rs_machine_dependent, 12, 0, |
6043 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 6044 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6045 | } |
6046 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
6047 | if (p != NULL) | |
6048 | p += 4; | |
17a2f251 TS |
6049 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6050 | tempreg, tempreg, breg); | |
252b5132 RH |
6051 | if (p != NULL) |
6052 | p += 4; | |
6053 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
17a2f251 | 6054 | BFD_RELOC_LO16, tempreg); |
252b5132 RH |
6055 | } |
6056 | } | |
6057 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6058 | { | |
f9419b05 | 6059 | char *p; |
ed6fb7bd | 6060 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6061 | |
252b5132 RH |
6062 | /* If this is a reference to an external symbol, we want |
6063 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6064 | nop | |
6065 | <op> $treg,0($tempreg) | |
6066 | Otherwise we want | |
6067 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6068 | nop | |
6069 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6070 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6071 | |
6072 | For NewABI, we want | |
6073 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6074 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6075 | ||
252b5132 RH |
6076 | If there is a base register, we add it to $tempreg before |
6077 | the <op>. If there is a constant, we stick it in the | |
6078 | <op> instruction. We don't handle constants larger than | |
6079 | 16 bits, because we have no way to load the upper 16 bits | |
6080 | (actually, we could handle them for the subset of cases | |
6081 | in which we are not using $at). */ | |
6082 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6083 | if (HAVE_NEWABI) |
6084 | { | |
17a2f251 TS |
6085 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6086 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE, | |
6087 | mips_gp_register); | |
f5040a92 | 6088 | if (breg != 0) |
17a2f251 TS |
6089 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6090 | tempreg, tempreg, breg); | |
6091 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, | |
6092 | BFD_RELOC_MIPS_GOT_OFST, tempreg); | |
f5040a92 AO |
6093 | |
6094 | if (! used_at) | |
6095 | return; | |
6096 | ||
6097 | break; | |
6098 | } | |
252b5132 RH |
6099 | expr1.X_add_number = offset_expr.X_add_number; |
6100 | offset_expr.X_add_number = 0; | |
6101 | if (expr1.X_add_number < -0x8000 | |
6102 | || expr1.X_add_number >= 0x8000) | |
6103 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6104 | frag_grow (20); | |
17a2f251 TS |
6105 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6106 | tempreg, lw_reloc_type, mips_gp_register); | |
6107 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
bdaaa2e1 | 6108 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 6109 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 6110 | offset_expr.X_add_symbol, 0, NULL); |
f899b4b8 | 6111 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 6112 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 | 6113 | if (breg != 0) |
17a2f251 TS |
6114 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6115 | tempreg, tempreg, breg); | |
6116 | macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16, | |
6117 | tempreg); | |
252b5132 | 6118 | } |
f5040a92 | 6119 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 RH |
6120 | { |
6121 | int gpdel; | |
f9419b05 | 6122 | char *p; |
252b5132 RH |
6123 | |
6124 | /* If this is a reference to an external symbol, we want | |
6125 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6126 | addu $tempreg,$tempreg,$gp | |
6127 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6128 | <op> $treg,0($tempreg) | |
6129 | Otherwise we want | |
6130 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6131 | nop | |
6132 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6133 | <op> $treg,0($tempreg) | |
6134 | If there is a base register, we add it to $tempreg before | |
6135 | the <op>. If there is a constant, we stick it in the | |
6136 | <op> instruction. We don't handle constants larger than | |
6137 | 16 bits, because we have no way to load the upper 16 bits | |
6138 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6139 | in which we are not using $at). */ |
252b5132 RH |
6140 | assert (offset_expr.X_op == O_symbol); |
6141 | expr1.X_add_number = offset_expr.X_add_number; | |
6142 | offset_expr.X_add_number = 0; | |
6143 | if (expr1.X_add_number < -0x8000 | |
6144 | || expr1.X_add_number >= 0x8000) | |
6145 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
f7ea7ef2 | 6146 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6147 | gpdel = 4; |
6148 | else | |
6149 | gpdel = 0; | |
6150 | frag_grow (36); | |
17a2f251 TS |
6151 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
6152 | BFD_RELOC_MIPS_GOT_HI16); | |
6153 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6154 | tempreg, tempreg, mips_gp_register); | |
6155 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6156 | tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
252b5132 RH |
6157 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
6158 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 6159 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6160 | if (gpdel > 0) |
6161 | { | |
17a2f251 | 6162 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
6163 | p += 4; |
6164 | } | |
17a2f251 TS |
6165 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6166 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6167 | p += 4; |
17a2f251 | 6168 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 | 6169 | p += 4; |
17a2f251 TS |
6170 | macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6171 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 6172 | if (breg != 0) |
17a2f251 TS |
6173 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6174 | tempreg, tempreg, breg); | |
6175 | macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16, | |
6176 | tempreg); | |
252b5132 | 6177 | } |
f5040a92 AO |
6178 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6179 | { | |
6180 | char *p; | |
6181 | int bregsz = breg != 0 ? 4 : 0; | |
6182 | ||
6183 | /* If this is a reference to an external symbol, we want | |
6184 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6185 | add $tempreg,$tempreg,$gp | |
6186 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6187 | <op> $treg,<ofst>($tempreg) | |
6188 | Otherwise, for local symbols, we want: | |
6189 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6190 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6191 | assert (offset_expr.X_op == O_symbol); | |
6192 | frag_now->tc_frag_data.tc_fr_offset = | |
6193 | expr1.X_add_number = offset_expr.X_add_number; | |
6194 | offset_expr.X_add_number = 0; | |
6195 | if (expr1.X_add_number < -0x8000 | |
6196 | || expr1.X_add_number >= 0x8000) | |
6197 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6198 | frag_grow (36); | |
17a2f251 TS |
6199 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg, |
6200 | BFD_RELOC_MIPS_GOT_HI16); | |
6201 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6202 | tempreg, tempreg, mips_gp_register); | |
6203 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6204 | tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6205 | if (breg != 0) |
17a2f251 TS |
6206 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6207 | tempreg, tempreg, breg); | |
6208 | macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16, | |
6209 | tempreg); | |
684022ea | 6210 | |
f5040a92 AO |
6211 | offset_expr.X_add_number = expr1.X_add_number; |
6212 | p = frag_var (rs_machine_dependent, 12 + bregsz, 0, | |
6213 | RELAX_ENCODE (16 + bregsz, 8 + bregsz, | |
6214 | 0, 4 + bregsz, 0, 0), | |
6215 | offset_expr.X_add_symbol, 0, NULL); | |
f899b4b8 | 6216 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6217 | tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
f5040a92 | 6218 | if (breg != 0) |
17a2f251 TS |
6219 | macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6220 | tempreg, tempreg, breg); | |
f5040a92 | 6221 | macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg, |
17a2f251 | 6222 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 | 6223 | } |
252b5132 RH |
6224 | else if (mips_pic == EMBEDDED_PIC) |
6225 | { | |
6226 | /* If there is no base register, we want | |
cdf6fd85 | 6227 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6228 | If there is a base register, we want |
6229 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6230 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6231 | */ |
6232 | assert (offset_expr.X_op == O_symbol); | |
6233 | if (breg == 0) | |
6234 | { | |
17a2f251 TS |
6235 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, |
6236 | BFD_RELOC_GPREL16, mips_gp_register); | |
252b5132 RH |
6237 | used_at = 0; |
6238 | } | |
6239 | else | |
6240 | { | |
17a2f251 TS |
6241 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6242 | tempreg, breg, mips_gp_register); | |
6243 | macro_build (NULL, &icnt, &offset_expr, s, fmt, treg, | |
6244 | BFD_RELOC_GPREL16, tempreg); | |
252b5132 RH |
6245 | } |
6246 | } | |
6247 | else | |
6248 | abort (); | |
6249 | ||
6250 | if (! used_at) | |
6251 | return; | |
6252 | ||
6253 | break; | |
6254 | ||
6255 | case M_LI: | |
6256 | case M_LI_S: | |
6257 | load_register (&icnt, treg, &imm_expr, 0); | |
6258 | return; | |
6259 | ||
6260 | case M_DLI: | |
6261 | load_register (&icnt, treg, &imm_expr, 1); | |
6262 | return; | |
6263 | ||
6264 | case M_LI_SS: | |
6265 | if (imm_expr.X_op == O_constant) | |
6266 | { | |
6267 | load_register (&icnt, AT, &imm_expr, 0); | |
17a2f251 | 6268 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg); |
252b5132 RH |
6269 | break; |
6270 | } | |
6271 | else | |
6272 | { | |
6273 | assert (offset_expr.X_op == O_symbol | |
6274 | && strcmp (segment_name (S_GET_SEGMENT | |
6275 | (offset_expr.X_add_symbol)), | |
6276 | ".lit4") == 0 | |
6277 | && offset_expr.X_add_number == 0); | |
17a2f251 TS |
6278 | macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg, |
6279 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); | |
252b5132 RH |
6280 | return; |
6281 | } | |
6282 | ||
6283 | case M_LI_D: | |
ca4e0257 RS |
6284 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6285 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6286 | order 32 bits of the value and the low order 32 bits are either | |
6287 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6288 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6289 | { | |
ca4e0257 | 6290 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6291 | load_register (&icnt, treg, &imm_expr, 1); |
6292 | else | |
6293 | { | |
6294 | int hreg, lreg; | |
6295 | ||
6296 | if (target_big_endian) | |
6297 | { | |
6298 | hreg = treg; | |
6299 | lreg = treg + 1; | |
6300 | } | |
6301 | else | |
6302 | { | |
6303 | hreg = treg + 1; | |
6304 | lreg = treg; | |
6305 | } | |
6306 | ||
6307 | if (hreg <= 31) | |
6308 | load_register (&icnt, hreg, &imm_expr, 0); | |
6309 | if (lreg <= 31) | |
6310 | { | |
6311 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 6312 | move_register (&icnt, lreg, 0); |
252b5132 RH |
6313 | else |
6314 | { | |
6315 | assert (offset_expr.X_op == O_constant); | |
6316 | load_register (&icnt, lreg, &offset_expr, 0); | |
6317 | } | |
6318 | } | |
6319 | } | |
6320 | return; | |
6321 | } | |
6322 | ||
6323 | /* We know that sym is in the .rdata section. First we get the | |
6324 | upper 16 bits of the address. */ | |
6325 | if (mips_pic == NO_PIC) | |
6326 | { | |
956cd1d6 | 6327 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
6328 | } |
6329 | else if (mips_pic == SVR4_PIC) | |
6330 | { | |
17a2f251 TS |
6331 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6332 | AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6333 | } |
6334 | else if (mips_pic == EMBEDDED_PIC) | |
6335 | { | |
6336 | /* For embedded PIC we pick up the entire address off $gp in | |
6337 | a single instruction. */ | |
17a2f251 TS |
6338 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6339 | AT, mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
6340 | offset_expr.X_op = O_constant; |
6341 | offset_expr.X_add_number = 0; | |
6342 | } | |
6343 | else | |
6344 | abort (); | |
bdaaa2e1 | 6345 | |
252b5132 | 6346 | /* Now we load the register(s). */ |
ca4e0257 | 6347 | if (HAVE_64BIT_GPRS) |
17a2f251 TS |
6348 | macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg, |
6349 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6350 | else |
6351 | { | |
17a2f251 TS |
6352 | macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg, |
6353 | BFD_RELOC_LO16, AT); | |
f9419b05 | 6354 | if (treg != RA) |
252b5132 RH |
6355 | { |
6356 | /* FIXME: How in the world do we deal with the possible | |
6357 | overflow here? */ | |
6358 | offset_expr.X_add_number += 4; | |
17a2f251 TS |
6359 | macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
6360 | treg + 1, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6361 | } |
6362 | } | |
6363 | ||
6364 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6365 | does not become a variant frag. */ | |
6366 | frag_wane (frag_now); | |
6367 | frag_new (0); | |
6368 | ||
6369 | break; | |
6370 | ||
6371 | case M_LI_DD: | |
ca4e0257 RS |
6372 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6373 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6374 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6375 | the value and the low order 32 bits are either zero or in | |
6376 | OFFSET_EXPR. */ | |
252b5132 RH |
6377 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6378 | { | |
ca4e0257 RS |
6379 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
6380 | if (HAVE_64BIT_FPRS) | |
6381 | { | |
6382 | assert (HAVE_64BIT_GPRS); | |
17a2f251 | 6383 | macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6384 | } |
252b5132 RH |
6385 | else |
6386 | { | |
17a2f251 | 6387 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6388 | if (offset_expr.X_op == O_absent) |
17a2f251 | 6389 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6390 | else |
6391 | { | |
6392 | assert (offset_expr.X_op == O_constant); | |
6393 | load_register (&icnt, AT, &offset_expr, 0); | |
17a2f251 | 6394 | macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg); |
252b5132 RH |
6395 | } |
6396 | } | |
6397 | break; | |
6398 | } | |
6399 | ||
6400 | assert (offset_expr.X_op == O_symbol | |
6401 | && offset_expr.X_add_number == 0); | |
6402 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6403 | if (strcmp (s, ".lit8") == 0) | |
6404 | { | |
e7af610e | 6405 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6406 | { |
17a2f251 TS |
6407 | macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg, |
6408 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); | |
252b5132 RH |
6409 | return; |
6410 | } | |
c9914766 | 6411 | breg = mips_gp_register; |
252b5132 RH |
6412 | r = BFD_RELOC_MIPS_LITERAL; |
6413 | goto dob; | |
6414 | } | |
6415 | else | |
6416 | { | |
6417 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6418 | if (mips_pic == SVR4_PIC) | |
17a2f251 TS |
6419 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, |
6420 | "t,o(b)", AT, BFD_RELOC_MIPS_GOT16, | |
6421 | mips_gp_register); | |
252b5132 RH |
6422 | else |
6423 | { | |
6424 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6425 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6426 | } |
bdaaa2e1 | 6427 | |
e7af610e | 6428 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6429 | { |
17a2f251 TS |
6430 | macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg, |
6431 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6432 | |
6433 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6434 | that this does not become a variant frag. */ | |
6435 | frag_wane (frag_now); | |
6436 | frag_new (0); | |
6437 | ||
6438 | break; | |
6439 | } | |
6440 | breg = AT; | |
6441 | r = BFD_RELOC_LO16; | |
6442 | goto dob; | |
6443 | } | |
6444 | ||
6445 | case M_L_DOB: | |
fef14a42 | 6446 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6447 | { |
6448 | as_bad (_("opcode not supported on this processor")); | |
6449 | return; | |
6450 | } | |
6451 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6452 | to adjust when loading from memory. */ | |
6453 | r = BFD_RELOC_LO16; | |
6454 | dob: | |
e7af610e | 6455 | assert (mips_opts.isa == ISA_MIPS1); |
17a2f251 TS |
6456 | macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6457 | target_big_endian ? treg + 1 : treg, r, breg); | |
252b5132 RH |
6458 | /* FIXME: A possible overflow which I don't know how to deal |
6459 | with. */ | |
6460 | offset_expr.X_add_number += 4; | |
17a2f251 TS |
6461 | macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6462 | target_big_endian ? treg : treg + 1, r, breg); | |
252b5132 RH |
6463 | |
6464 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6465 | does not become a variant frag. */ | |
6466 | frag_wane (frag_now); | |
6467 | frag_new (0); | |
6468 | ||
6469 | if (breg != AT) | |
6470 | return; | |
6471 | break; | |
6472 | ||
6473 | case M_L_DAB: | |
6474 | /* | |
6475 | * The MIPS assembler seems to check for X_add_number not | |
6476 | * being double aligned and generating: | |
6477 | * lui at,%hi(foo+1) | |
6478 | * addu at,at,v1 | |
6479 | * addiu at,at,%lo(foo+1) | |
6480 | * lwc1 f2,0(at) | |
6481 | * lwc1 f3,4(at) | |
6482 | * But, the resulting address is the same after relocation so why | |
6483 | * generate the extra instruction? | |
6484 | */ | |
fef14a42 | 6485 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6486 | { |
6487 | as_bad (_("opcode not supported on this processor")); | |
6488 | return; | |
6489 | } | |
bdaaa2e1 | 6490 | /* Itbl support may require additional care here. */ |
252b5132 | 6491 | coproc = 1; |
e7af610e | 6492 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6493 | { |
6494 | s = "ldc1"; | |
6495 | goto ld; | |
6496 | } | |
6497 | ||
6498 | s = "lwc1"; | |
6499 | fmt = "T,o(b)"; | |
6500 | goto ldd_std; | |
6501 | ||
6502 | case M_S_DAB: | |
fef14a42 | 6503 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6504 | { |
6505 | as_bad (_("opcode not supported on this processor")); | |
6506 | return; | |
6507 | } | |
6508 | ||
e7af610e | 6509 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6510 | { |
6511 | s = "sdc1"; | |
6512 | goto st; | |
6513 | } | |
6514 | ||
6515 | s = "swc1"; | |
6516 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6517 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6518 | coproc = 1; |
6519 | goto ldd_std; | |
6520 | ||
6521 | case M_LD_AB: | |
ca4e0257 | 6522 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6523 | { |
6524 | s = "ld"; | |
6525 | goto ld; | |
6526 | } | |
6527 | ||
6528 | s = "lw"; | |
6529 | fmt = "t,o(b)"; | |
6530 | goto ldd_std; | |
6531 | ||
6532 | case M_SD_AB: | |
ca4e0257 | 6533 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6534 | { |
6535 | s = "sd"; | |
6536 | goto st; | |
6537 | } | |
6538 | ||
6539 | s = "sw"; | |
6540 | fmt = "t,o(b)"; | |
6541 | ||
6542 | ldd_std: | |
afdbd6d0 CD |
6543 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6544 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6545 | This is not currently done by the compiler, and assembly coders | |
6546 | writing embedded-pic code can cope. */ | |
6547 | ||
252b5132 RH |
6548 | if (offset_expr.X_op != O_symbol |
6549 | && offset_expr.X_op != O_constant) | |
6550 | { | |
6551 | as_bad (_("expression too complex")); | |
6552 | offset_expr.X_op = O_constant; | |
6553 | } | |
6554 | ||
6555 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6556 | to adjust when loading from memory. We set coproc if we must | |
6557 | load $fn+1 first. */ | |
bdaaa2e1 | 6558 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6559 | if (! target_big_endian) |
6560 | coproc = 0; | |
6561 | ||
6562 | if (mips_pic == NO_PIC | |
6563 | || offset_expr.X_op == O_constant) | |
6564 | { | |
f9419b05 TS |
6565 | char *p; |
6566 | ||
252b5132 | 6567 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6568 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6569 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6570 | If we have a base register, we use this |
6571 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6572 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6573 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6574 | If this is not a GP relative symbol, we want |
6575 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6576 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6577 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6578 | If there is a base register, we add it to $at after the | |
6579 | lui instruction. If there is a constant, we always use | |
6580 | the last case. */ | |
e7d556df | 6581 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6582 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6583 | { | |
6584 | p = NULL; | |
6585 | used_at = 1; | |
6586 | } | |
6587 | else | |
6588 | { | |
6589 | int off; | |
6590 | ||
6591 | if (breg == 0) | |
6592 | { | |
6593 | frag_grow (28); | |
c9914766 | 6594 | tempreg = mips_gp_register; |
252b5132 RH |
6595 | off = 0; |
6596 | used_at = 0; | |
6597 | } | |
6598 | else | |
6599 | { | |
6600 | frag_grow (36); | |
17a2f251 TS |
6601 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6602 | AT, breg, mips_gp_register); | |
252b5132 RH |
6603 | tempreg = AT; |
6604 | off = 4; | |
6605 | used_at = 1; | |
6606 | } | |
6607 | ||
beae10d5 | 6608 | /* Itbl support may require additional care here. */ |
17a2f251 | 6609 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6610 | coproc ? treg + 1 : treg, |
17a2f251 | 6611 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6612 | offset_expr.X_add_number += 4; |
6613 | ||
6614 | /* Set mips_optimize to 2 to avoid inserting an | |
6615 | undesired nop. */ | |
6616 | hold_mips_optimize = mips_optimize; | |
6617 | mips_optimize = 2; | |
beae10d5 | 6618 | /* Itbl support may require additional care here. */ |
17a2f251 | 6619 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6620 | coproc ? treg : treg + 1, |
17a2f251 | 6621 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6622 | mips_optimize = hold_mips_optimize; |
6623 | ||
6624 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6625 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6626 | used_at && mips_opts.noat), | |
956cd1d6 | 6627 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6628 | |
6629 | /* We just generated two relocs. When tc_gen_reloc | |
6630 | handles this case, it will skip the first reloc and | |
6631 | handle the second. The second reloc already has an | |
6632 | extra addend of 4, which we added above. We must | |
6633 | subtract it out, and then subtract another 4 to make | |
6634 | the first reloc come out right. The second reloc | |
6635 | will come out right because we are going to add 4 to | |
6636 | offset_expr when we build its instruction below. | |
6637 | ||
6638 | If we have a symbol, then we don't want to include | |
6639 | the offset, because it will wind up being included | |
6640 | when we generate the reloc. */ | |
6641 | ||
6642 | if (offset_expr.X_op == O_constant) | |
6643 | offset_expr.X_add_number -= 8; | |
6644 | else | |
6645 | { | |
6646 | offset_expr.X_add_number = -4; | |
6647 | offset_expr.X_op = O_constant; | |
6648 | } | |
6649 | } | |
6650 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6651 | if (p != NULL) | |
6652 | p += 4; | |
6653 | if (breg != 0) | |
6654 | { | |
17a2f251 TS |
6655 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6656 | AT, breg, AT); | |
252b5132 RH |
6657 | if (p != NULL) |
6658 | p += 4; | |
6659 | } | |
beae10d5 | 6660 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6661 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6662 | coproc ? treg + 1 : treg, | |
17a2f251 | 6663 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6664 | if (p != NULL) |
6665 | p += 4; | |
6666 | /* FIXME: How do we handle overflow here? */ | |
6667 | offset_expr.X_add_number += 4; | |
beae10d5 | 6668 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6669 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6670 | coproc ? treg : treg + 1, | |
17a2f251 | 6671 | BFD_RELOC_LO16, AT); |
bdaaa2e1 | 6672 | } |
252b5132 RH |
6673 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6674 | { | |
6675 | int off; | |
6676 | ||
6677 | /* If this is a reference to an external symbol, we want | |
6678 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6679 | nop | |
6680 | <op> $treg,0($at) | |
6681 | <op> $treg+1,4($at) | |
6682 | Otherwise we want | |
6683 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6684 | nop | |
6685 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6686 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6687 | If there is a base register we add it to $at before the | |
6688 | lwc1 instructions. If there is a constant we include it | |
6689 | in the lwc1 instructions. */ | |
6690 | used_at = 1; | |
6691 | expr1.X_add_number = offset_expr.X_add_number; | |
6692 | offset_expr.X_add_number = 0; | |
6693 | if (expr1.X_add_number < -0x8000 | |
6694 | || expr1.X_add_number >= 0x8000 - 4) | |
6695 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6696 | if (breg == 0) | |
6697 | off = 0; | |
6698 | else | |
6699 | off = 4; | |
6700 | frag_grow (24 + off); | |
17a2f251 TS |
6701 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6702 | AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
6703 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 | 6704 | if (breg != 0) |
17a2f251 TS |
6705 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6706 | AT, breg, AT); | |
beae10d5 | 6707 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6708 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg, |
6709 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6710 | expr1.X_add_number += 4; |
6711 | ||
6712 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6713 | nop. */ | |
6714 | hold_mips_optimize = mips_optimize; | |
6715 | mips_optimize = 2; | |
beae10d5 | 6716 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6717 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1, |
6718 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6719 | mips_optimize = hold_mips_optimize; |
6720 | ||
6721 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6722 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6723 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6724 | } |
6725 | else if (mips_pic == SVR4_PIC) | |
6726 | { | |
6727 | int gpdel, off; | |
f9419b05 | 6728 | char *p; |
252b5132 RH |
6729 | |
6730 | /* If this is a reference to an external symbol, we want | |
6731 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6732 | addu $at,$at,$gp | |
6733 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6734 | nop | |
6735 | <op> $treg,0($at) | |
6736 | <op> $treg+1,4($at) | |
6737 | Otherwise we want | |
6738 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6739 | nop | |
6740 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6741 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6742 | If there is a base register we add it to $at before the | |
6743 | lwc1 instructions. If there is a constant we include it | |
6744 | in the lwc1 instructions. */ | |
6745 | used_at = 1; | |
6746 | expr1.X_add_number = offset_expr.X_add_number; | |
6747 | offset_expr.X_add_number = 0; | |
6748 | if (expr1.X_add_number < -0x8000 | |
6749 | || expr1.X_add_number >= 0x8000 - 4) | |
6750 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6751 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6752 | gpdel = 4; |
6753 | else | |
6754 | gpdel = 0; | |
6755 | if (breg == 0) | |
6756 | off = 0; | |
6757 | else | |
6758 | off = 4; | |
6759 | frag_grow (56); | |
17a2f251 TS |
6760 | macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT, |
6761 | BFD_RELOC_MIPS_GOT_HI16); | |
6762 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6763 | AT, AT, mips_gp_register); | |
6764 | macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6765 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); | |
6766 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 | 6767 | if (breg != 0) |
17a2f251 TS |
6768 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6769 | AT, breg, AT); | |
beae10d5 | 6770 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6771 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg, |
6772 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6773 | expr1.X_add_number += 4; |
6774 | ||
6775 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6776 | nop. */ | |
6777 | hold_mips_optimize = mips_optimize; | |
6778 | mips_optimize = 2; | |
beae10d5 | 6779 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6780 | macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1, |
6781 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6782 | mips_optimize = hold_mips_optimize; |
6783 | expr1.X_add_number -= 4; | |
6784 | ||
6785 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6786 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6787 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6788 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6789 | if (gpdel > 0) |
6790 | { | |
17a2f251 | 6791 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
6792 | p += 4; |
6793 | } | |
17a2f251 TS |
6794 | macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6795 | AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 6796 | p += 4; |
17a2f251 | 6797 | macro_build (p, &icnt, NULL, "nop", ""); |
252b5132 RH |
6798 | p += 4; |
6799 | if (breg != 0) | |
6800 | { | |
17a2f251 TS |
6801 | macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6802 | AT, breg, AT); | |
252b5132 RH |
6803 | p += 4; |
6804 | } | |
beae10d5 | 6805 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6806 | macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg, |
6807 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6808 | p += 4; |
6809 | expr1.X_add_number += 4; | |
6810 | ||
6811 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6812 | nop. */ | |
6813 | hold_mips_optimize = mips_optimize; | |
6814 | mips_optimize = 2; | |
beae10d5 | 6815 | /* Itbl support may require additional care here. */ |
17a2f251 TS |
6816 | macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1, |
6817 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
6818 | mips_optimize = hold_mips_optimize; |
6819 | } | |
6820 | else if (mips_pic == EMBEDDED_PIC) | |
6821 | { | |
6822 | /* If there is no base register, we use | |
cdf6fd85 TS |
6823 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6824 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6825 | If we have a base register, we use |
6826 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6827 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6828 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6829 | */ |
6830 | if (breg == 0) | |
6831 | { | |
c9914766 | 6832 | tempreg = mips_gp_register; |
252b5132 RH |
6833 | used_at = 0; |
6834 | } | |
6835 | else | |
6836 | { | |
17a2f251 TS |
6837 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
6838 | AT, breg, mips_gp_register); | |
252b5132 RH |
6839 | tempreg = AT; |
6840 | used_at = 1; | |
6841 | } | |
6842 | ||
beae10d5 | 6843 | /* Itbl support may require additional care here. */ |
17a2f251 | 6844 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6845 | coproc ? treg + 1 : treg, |
17a2f251 | 6846 | BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6847 | offset_expr.X_add_number += 4; |
beae10d5 | 6848 | /* Itbl support may require additional care here. */ |
17a2f251 | 6849 | macro_build (NULL, &icnt, &offset_expr, s, fmt, |
252b5132 | 6850 | coproc ? treg : treg + 1, |
17a2f251 | 6851 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6852 | } |
6853 | else | |
6854 | abort (); | |
6855 | ||
6856 | if (! used_at) | |
6857 | return; | |
6858 | ||
6859 | break; | |
6860 | ||
6861 | case M_LD_OB: | |
6862 | s = "lw"; | |
6863 | goto sd_ob; | |
6864 | case M_SD_OB: | |
6865 | s = "sw"; | |
6866 | sd_ob: | |
ca4e0257 | 6867 | assert (HAVE_32BIT_ADDRESSES); |
17a2f251 TS |
6868 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6869 | BFD_RELOC_LO16, breg); | |
252b5132 | 6870 | offset_expr.X_add_number += 4; |
17a2f251 TS |
6871 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, |
6872 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
6873 | return; |
6874 | ||
6875 | /* New code added to support COPZ instructions. | |
6876 | This code builds table entries out of the macros in mip_opcodes. | |
6877 | R4000 uses interlocks to handle coproc delays. | |
6878 | Other chips (like the R3000) require nops to be inserted for delays. | |
6879 | ||
f72c8c98 | 6880 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6881 | In order to fill delay slots for non-interlocked chips, |
6882 | we must have a way to specify delays based on the coprocessor. | |
6883 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6884 | What are the side-effects of the cop instruction? | |
6885 | What cache support might we have and what are its effects? | |
6886 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6887 | What registers are read/set/modified? |
252b5132 RH |
6888 | |
6889 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6890 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6891 | |
6892 | case M_COP0: | |
6893 | s = "c0"; | |
6894 | goto copz; | |
6895 | case M_COP1: | |
6896 | s = "c1"; | |
6897 | goto copz; | |
6898 | case M_COP2: | |
6899 | s = "c2"; | |
6900 | goto copz; | |
6901 | case M_COP3: | |
6902 | s = "c3"; | |
6903 | copz: | |
6904 | /* For now we just do C (same as Cz). The parameter will be | |
6905 | stored in insn_opcode by mips_ip. */ | |
17a2f251 | 6906 | macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
6907 | return; |
6908 | ||
ea1fb5dc RS |
6909 | case M_MOVE: |
6910 | move_register (&icnt, dreg, sreg); | |
6911 | return; | |
6912 | ||
252b5132 RH |
6913 | #ifdef LOSING_COMPILER |
6914 | default: | |
6915 | /* Try and see if this is a new itbl instruction. | |
6916 | This code builds table entries out of the macros in mip_opcodes. | |
6917 | FIXME: For now we just assemble the expression and pass it's | |
6918 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6919 | We may want to have the assembler assemble this value, |
252b5132 RH |
6920 | so that we gain the assembler's knowledge of delay slots, |
6921 | symbols, etc. | |
6922 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6923 | if (itbl_have_entries |
252b5132 | 6924 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6925 | { |
252b5132 RH |
6926 | s = ip->insn_mo->name; |
6927 | s2 = "cop3"; | |
6928 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
17a2f251 | 6929 | macro_build (NULL, &icnt, &immed_expr, s, "C"); |
252b5132 | 6930 | return; |
beae10d5 | 6931 | } |
252b5132 RH |
6932 | macro2 (ip); |
6933 | return; | |
6934 | } | |
6935 | if (mips_opts.noat) | |
6936 | as_warn (_("Macro used $at after \".set noat\"")); | |
6937 | } | |
bdaaa2e1 | 6938 | |
252b5132 | 6939 | static void |
17a2f251 | 6940 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6941 | { |
6942 | register int treg, sreg, dreg, breg; | |
6943 | int tempreg; | |
6944 | int mask; | |
6945 | int icnt = 0; | |
6946 | int used_at; | |
6947 | expressionS expr1; | |
6948 | const char *s; | |
6949 | const char *s2; | |
6950 | const char *fmt; | |
6951 | int likely = 0; | |
6952 | int dbl = 0; | |
6953 | int coproc = 0; | |
6954 | int lr = 0; | |
6955 | int imm = 0; | |
6956 | int off; | |
6957 | offsetT maxnum; | |
6958 | bfd_reloc_code_real_type r; | |
6959 | char *p; | |
bdaaa2e1 | 6960 | |
252b5132 RH |
6961 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6962 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6963 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6964 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6965 | |
252b5132 RH |
6966 | expr1.X_op = O_constant; |
6967 | expr1.X_op_symbol = NULL; | |
6968 | expr1.X_add_symbol = NULL; | |
6969 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6970 | |
252b5132 RH |
6971 | switch (mask) |
6972 | { | |
6973 | #endif /* LOSING_COMPILER */ | |
6974 | ||
6975 | case M_DMUL: | |
6976 | dbl = 1; | |
6977 | case M_MUL: | |
17a2f251 TS |
6978 | macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t", |
6979 | sreg, treg); | |
6980 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
252b5132 RH |
6981 | return; |
6982 | ||
6983 | case M_DMUL_I: | |
6984 | dbl = 1; | |
6985 | case M_MUL_I: | |
6986 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6987 | not trying to be that fancy. GCC should do this for us | |
6988 | anyway. */ | |
6989 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
6990 | macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t", |
6991 | sreg, AT); | |
6992 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
252b5132 RH |
6993 | break; |
6994 | ||
6995 | case M_DMULO_I: | |
6996 | dbl = 1; | |
6997 | case M_MULO_I: | |
6998 | imm = 1; | |
6999 | goto do_mulo; | |
7000 | ||
7001 | case M_DMULO: | |
7002 | dbl = 1; | |
7003 | case M_MULO: | |
7004 | do_mulo: | |
b34976b6 | 7005 | mips_emit_delays (TRUE); |
252b5132 RH |
7006 | ++mips_opts.noreorder; |
7007 | mips_any_noreorder = 1; | |
7008 | if (imm) | |
7009 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7010 | macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t", |
7011 | sreg, imm ? AT : treg); | |
7012 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
7013 | macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<", | |
7014 | dreg, dreg, RA); | |
7015 | macro_build (NULL, &icnt, NULL, "mfhi", "d", AT); | |
252b5132 | 7016 | if (mips_trap) |
17a2f251 | 7017 | macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7018 | else |
7019 | { | |
7020 | expr1.X_add_number = 8; | |
17a2f251 TS |
7021 | macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); |
7022 | macro_build (NULL, &icnt, NULL, "nop", "", 0); | |
7023 | macro_build (NULL, &icnt, NULL, "break", "c", 6); | |
252b5132 RH |
7024 | } |
7025 | --mips_opts.noreorder; | |
17a2f251 | 7026 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); |
252b5132 RH |
7027 | break; |
7028 | ||
7029 | case M_DMULOU_I: | |
7030 | dbl = 1; | |
7031 | case M_MULOU_I: | |
7032 | imm = 1; | |
7033 | goto do_mulou; | |
7034 | ||
7035 | case M_DMULOU: | |
7036 | dbl = 1; | |
7037 | case M_MULOU: | |
7038 | do_mulou: | |
b34976b6 | 7039 | mips_emit_delays (TRUE); |
252b5132 RH |
7040 | ++mips_opts.noreorder; |
7041 | mips_any_noreorder = 1; | |
7042 | if (imm) | |
7043 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7044 | macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t", |
7045 | sreg, imm ? AT : treg); | |
7046 | macro_build (NULL, &icnt, NULL, "mfhi", "d", AT); | |
7047 | macro_build (NULL, &icnt, NULL, "mflo", "d", dreg); | |
252b5132 | 7048 | if (mips_trap) |
17a2f251 | 7049 | macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7050 | else |
7051 | { | |
7052 | expr1.X_add_number = 8; | |
17a2f251 TS |
7053 | macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); |
7054 | macro_build (NULL, &icnt, NULL, "nop", "", 0); | |
7055 | macro_build (NULL, &icnt, NULL, "break", "c", 6); | |
252b5132 RH |
7056 | } |
7057 | --mips_opts.noreorder; | |
7058 | break; | |
7059 | ||
771c7ce4 | 7060 | case M_DROL: |
fef14a42 | 7061 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7062 | { |
7063 | if (dreg == sreg) | |
7064 | { | |
7065 | tempreg = AT; | |
7066 | used_at = 1; | |
7067 | } | |
7068 | else | |
7069 | { | |
7070 | tempreg = dreg; | |
7071 | used_at = 0; | |
7072 | } | |
17a2f251 TS |
7073 | macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg); |
7074 | macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, | |
7075 | tempreg); | |
82dd0097 CD |
7076 | if (used_at) |
7077 | break; | |
7078 | return; | |
7079 | } | |
17a2f251 TS |
7080 | macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg); |
7081 | macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7082 | macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7083 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7084 | break; |
7085 | ||
252b5132 | 7086 | case M_ROL: |
fef14a42 | 7087 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7088 | { |
7089 | if (dreg == sreg) | |
7090 | { | |
7091 | tempreg = AT; | |
7092 | used_at = 1; | |
7093 | } | |
7094 | else | |
7095 | { | |
7096 | tempreg = dreg; | |
7097 | used_at = 0; | |
7098 | } | |
17a2f251 TS |
7099 | macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg); |
7100 | macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, | |
7101 | tempreg); | |
82dd0097 CD |
7102 | if (used_at) |
7103 | break; | |
7104 | return; | |
7105 | } | |
17a2f251 TS |
7106 | macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
7107 | macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7108 | macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7109 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7110 | break; |
7111 | ||
771c7ce4 TS |
7112 | case M_DROL_I: |
7113 | { | |
7114 | unsigned int rot; | |
82dd0097 | 7115 | char *l, *r; |
771c7ce4 TS |
7116 | |
7117 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7118 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7119 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7120 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7121 | { |
7122 | rot = (64 - rot) & 0x3f; | |
7123 | if (rot >= 32) | |
17a2f251 TS |
7124 | macro_build (NULL, &icnt, NULL, "dror32", "d,w,<", |
7125 | dreg, sreg, rot - 32); | |
60b63b72 | 7126 | else |
17a2f251 TS |
7127 | macro_build (NULL, &icnt, NULL, "dror", "d,w,<", |
7128 | dreg, sreg, rot); | |
82dd0097 | 7129 | return; |
60b63b72 | 7130 | } |
483fc7cd | 7131 | if (rot == 0) |
483fc7cd | 7132 | { |
17a2f251 | 7133 | macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7134 | return; |
483fc7cd | 7135 | } |
82dd0097 CD |
7136 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7137 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7138 | rot &= 0x1f; | |
17a2f251 TS |
7139 | macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot); |
7140 | macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg, | |
7141 | (0x20 - rot) & 0x1f); | |
7142 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7143 | } |
7144 | break; | |
7145 | ||
252b5132 | 7146 | case M_ROL_I: |
771c7ce4 TS |
7147 | { |
7148 | unsigned int rot; | |
7149 | ||
7150 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7151 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7152 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7153 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7154 | { |
17a2f251 TS |
7155 | macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, |
7156 | (32 - rot) & 0x1f); | |
82dd0097 | 7157 | return; |
60b63b72 | 7158 | } |
483fc7cd | 7159 | if (rot == 0) |
483fc7cd | 7160 | { |
17a2f251 | 7161 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7162 | return; |
483fc7cd | 7163 | } |
17a2f251 TS |
7164 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot); |
7165 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, | |
7166 | (0x20 - rot) & 0x1f); | |
7167 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7168 | } |
7169 | break; | |
7170 | ||
7171 | case M_DROR: | |
fef14a42 | 7172 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7173 | { |
17a2f251 | 7174 | macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7175 | return; |
7176 | } | |
17a2f251 TS |
7177 | macro_build (NULL, &icnt,NULL, "dsubu", "d,v,t", AT, 0, treg); |
7178 | macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7179 | macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7180 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7181 | break; |
7182 | ||
7183 | case M_ROR: | |
fef14a42 | 7184 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7185 | { |
17a2f251 | 7186 | macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7187 | return; |
7188 | } | |
17a2f251 TS |
7189 | macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
7190 | macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7191 | macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7192 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7193 | break; |
7194 | ||
771c7ce4 TS |
7195 | case M_DROR_I: |
7196 | { | |
7197 | unsigned int rot; | |
82dd0097 | 7198 | char *l, *r; |
771c7ce4 TS |
7199 | |
7200 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7201 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7202 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7203 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7204 | { |
7205 | if (rot >= 32) | |
17a2f251 TS |
7206 | macro_build (NULL, &icnt, NULL, "dror32", "d,w,<", |
7207 | dreg, sreg, rot - 32); | |
82dd0097 | 7208 | else |
17a2f251 TS |
7209 | macro_build (NULL, &icnt, NULL, "dror", "d,w,<", |
7210 | dreg, sreg, rot); | |
82dd0097 CD |
7211 | return; |
7212 | } | |
483fc7cd | 7213 | if (rot == 0) |
483fc7cd | 7214 | { |
17a2f251 | 7215 | macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7216 | return; |
483fc7cd | 7217 | } |
82dd0097 CD |
7218 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7219 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7220 | rot &= 0x1f; | |
17a2f251 TS |
7221 | macro_build ( NULL, &icnt,NULL, r, "d,w,<", AT, sreg, rot); |
7222 | macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg, | |
7223 | (0x20 - rot) & 0x1f); | |
7224 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7225 | } |
7226 | break; | |
7227 | ||
252b5132 | 7228 | case M_ROR_I: |
771c7ce4 TS |
7229 | { |
7230 | unsigned int rot; | |
7231 | ||
7232 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7233 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7234 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7235 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7236 | { |
17a2f251 | 7237 | macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7238 | return; |
7239 | } | |
483fc7cd | 7240 | if (rot == 0) |
483fc7cd | 7241 | { |
17a2f251 | 7242 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7243 | return; |
483fc7cd | 7244 | } |
17a2f251 TS |
7245 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot); |
7246 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, | |
7247 | (0x20 - rot) & 0x1f); | |
7248 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7249 | } |
252b5132 RH |
7250 | break; |
7251 | ||
7252 | case M_S_DOB: | |
fef14a42 | 7253 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7254 | { |
7255 | as_bad (_("opcode not supported on this processor")); | |
7256 | return; | |
7257 | } | |
e7af610e | 7258 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7259 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7260 | to adjust when storing to memory. */ | |
17a2f251 | 7261 | macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
252b5132 | 7262 | target_big_endian ? treg + 1 : treg, |
17a2f251 | 7263 | BFD_RELOC_LO16, breg); |
252b5132 | 7264 | offset_expr.X_add_number += 4; |
17a2f251 | 7265 | macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
252b5132 | 7266 | target_big_endian ? treg : treg + 1, |
17a2f251 | 7267 | BFD_RELOC_LO16, breg); |
252b5132 RH |
7268 | return; |
7269 | ||
7270 | case M_SEQ: | |
7271 | if (sreg == 0) | |
17a2f251 TS |
7272 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg, |
7273 | BFD_RELOC_LO16); | |
252b5132 | 7274 | else if (treg == 0) |
17a2f251 TS |
7275 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg, |
7276 | BFD_RELOC_LO16); | |
252b5132 RH |
7277 | else |
7278 | { | |
17a2f251 TS |
7279 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg); |
7280 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
7281 | BFD_RELOC_LO16); | |
252b5132 RH |
7282 | } |
7283 | return; | |
7284 | ||
7285 | case M_SEQ_I: | |
7286 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7287 | { | |
17a2f251 TS |
7288 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg, |
7289 | BFD_RELOC_LO16); | |
252b5132 RH |
7290 | return; |
7291 | } | |
7292 | if (sreg == 0) | |
7293 | { | |
7294 | as_warn (_("Instruction %s: result is always false"), | |
7295 | ip->insn_mo->name); | |
ea1fb5dc | 7296 | move_register (&icnt, dreg, 0); |
252b5132 RH |
7297 | return; |
7298 | } | |
7299 | if (imm_expr.X_op == O_constant | |
7300 | && imm_expr.X_add_number >= 0 | |
7301 | && imm_expr.X_add_number < 0x10000) | |
7302 | { | |
17a2f251 TS |
7303 | macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg, |
7304 | BFD_RELOC_LO16); | |
252b5132 RH |
7305 | used_at = 0; |
7306 | } | |
7307 | else if (imm_expr.X_op == O_constant | |
7308 | && imm_expr.X_add_number > -0x8000 | |
7309 | && imm_expr.X_add_number < 0) | |
7310 | { | |
7311 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7312 | macro_build (NULL, &icnt, &imm_expr, |
ca4e0257 | 7313 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7314 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7315 | used_at = 0; |
7316 | } | |
7317 | else | |
7318 | { | |
4d34fb5f | 7319 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7320 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7321 | used_at = 1; |
7322 | } | |
17a2f251 TS |
7323 | macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
7324 | BFD_RELOC_LO16); | |
252b5132 RH |
7325 | if (used_at) |
7326 | break; | |
7327 | return; | |
7328 | ||
7329 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7330 | s = "slt"; | |
7331 | goto sge; | |
7332 | case M_SGEU: | |
7333 | s = "sltu"; | |
7334 | sge: | |
17a2f251 TS |
7335 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
7336 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7337 | BFD_RELOC_LO16); | |
252b5132 RH |
7338 | return; |
7339 | ||
7340 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7341 | case M_SGEU_I: | |
7342 | if (imm_expr.X_op == O_constant | |
7343 | && imm_expr.X_add_number >= -0x8000 | |
7344 | && imm_expr.X_add_number < 0x8000) | |
7345 | { | |
17a2f251 | 7346 | macro_build (NULL, &icnt, &imm_expr, |
252b5132 | 7347 | mask == M_SGE_I ? "slti" : "sltiu", |
17a2f251 | 7348 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7349 | used_at = 0; |
7350 | } | |
7351 | else | |
7352 | { | |
4d34fb5f | 7353 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 TS |
7354 | macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu", |
7355 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7356 | used_at = 1; |
7357 | } | |
17a2f251 TS |
7358 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7359 | BFD_RELOC_LO16); | |
252b5132 RH |
7360 | if (used_at) |
7361 | break; | |
7362 | return; | |
7363 | ||
7364 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7365 | s = "slt"; | |
7366 | goto sgt; | |
7367 | case M_SGTU: | |
7368 | s = "sltu"; | |
7369 | sgt: | |
17a2f251 | 7370 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7371 | return; |
7372 | ||
7373 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7374 | s = "slt"; | |
7375 | goto sgti; | |
7376 | case M_SGTU_I: | |
7377 | s = "sltu"; | |
7378 | sgti: | |
4d34fb5f | 7379 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7380 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
252b5132 RH |
7381 | break; |
7382 | ||
2396cfb9 | 7383 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7384 | s = "slt"; |
7385 | goto sle; | |
7386 | case M_SLEU: | |
7387 | s = "sltu"; | |
7388 | sle: | |
17a2f251 TS |
7389 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
7390 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7391 | BFD_RELOC_LO16); | |
252b5132 RH |
7392 | return; |
7393 | ||
2396cfb9 | 7394 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7395 | s = "slt"; |
7396 | goto slei; | |
7397 | case M_SLEU_I: | |
7398 | s = "sltu"; | |
7399 | slei: | |
4d34fb5f | 7400 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 TS |
7401 | macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
7402 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7403 | BFD_RELOC_LO16); | |
252b5132 RH |
7404 | break; |
7405 | ||
7406 | case M_SLT_I: | |
7407 | if (imm_expr.X_op == O_constant | |
7408 | && imm_expr.X_add_number >= -0x8000 | |
7409 | && imm_expr.X_add_number < 0x8000) | |
7410 | { | |
17a2f251 TS |
7411 | macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg, |
7412 | BFD_RELOC_LO16); | |
252b5132 RH |
7413 | return; |
7414 | } | |
4d34fb5f | 7415 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7416 | macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7417 | break; |
7418 | ||
7419 | case M_SLTU_I: | |
7420 | if (imm_expr.X_op == O_constant | |
7421 | && imm_expr.X_add_number >= -0x8000 | |
7422 | && imm_expr.X_add_number < 0x8000) | |
7423 | { | |
17a2f251 TS |
7424 | macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg, |
7425 | BFD_RELOC_LO16); | |
252b5132 RH |
7426 | return; |
7427 | } | |
4d34fb5f | 7428 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7429 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7430 | break; |
7431 | ||
7432 | case M_SNE: | |
7433 | if (sreg == 0) | |
17a2f251 | 7434 | macro_build (NULL, &icnt,NULL, "sltu","d,v,t", dreg, 0, treg); |
252b5132 | 7435 | else if (treg == 0) |
17a2f251 | 7436 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7437 | else |
7438 | { | |
17a2f251 TS |
7439 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg); |
7440 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7441 | } |
7442 | return; | |
7443 | ||
7444 | case M_SNE_I: | |
7445 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7446 | { | |
17a2f251 | 7447 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7448 | return; |
7449 | } | |
7450 | if (sreg == 0) | |
7451 | { | |
7452 | as_warn (_("Instruction %s: result is always true"), | |
7453 | ip->insn_mo->name); | |
17a2f251 | 7454 | macro_build (NULL, &icnt, &expr1, |
ca4e0257 | 7455 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7456 | "t,r,j", dreg, 0, BFD_RELOC_LO16); |
252b5132 RH |
7457 | return; |
7458 | } | |
7459 | if (imm_expr.X_op == O_constant | |
7460 | && imm_expr.X_add_number >= 0 | |
7461 | && imm_expr.X_add_number < 0x10000) | |
7462 | { | |
17a2f251 TS |
7463 | macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg, |
7464 | BFD_RELOC_LO16); | |
252b5132 RH |
7465 | used_at = 0; |
7466 | } | |
7467 | else if (imm_expr.X_op == O_constant | |
7468 | && imm_expr.X_add_number > -0x8000 | |
7469 | && imm_expr.X_add_number < 0) | |
7470 | { | |
7471 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7472 | macro_build (NULL, &icnt, &imm_expr, |
ca4e0257 | 7473 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7474 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7475 | used_at = 0; |
7476 | } | |
7477 | else | |
7478 | { | |
4d34fb5f | 7479 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7480 | macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7481 | used_at = 1; |
7482 | } | |
17a2f251 | 7483 | macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7484 | if (used_at) |
7485 | break; | |
7486 | return; | |
7487 | ||
7488 | case M_DSUB_I: | |
7489 | dbl = 1; | |
7490 | case M_SUB_I: | |
7491 | if (imm_expr.X_op == O_constant | |
7492 | && imm_expr.X_add_number > -0x8000 | |
7493 | && imm_expr.X_add_number <= 0x8000) | |
7494 | { | |
7495 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 TS |
7496 | macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi", |
7497 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7498 | return; |
7499 | } | |
7500 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7501 | macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", |
7502 | dreg, sreg, AT); | |
252b5132 RH |
7503 | break; |
7504 | ||
7505 | case M_DSUBU_I: | |
7506 | dbl = 1; | |
7507 | case M_SUBU_I: | |
7508 | if (imm_expr.X_op == O_constant | |
7509 | && imm_expr.X_add_number > -0x8000 | |
7510 | && imm_expr.X_add_number <= 0x8000) | |
7511 | { | |
7512 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 TS |
7513 | macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", |
7514 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7515 | return; |
7516 | } | |
7517 | load_register (&icnt, AT, &imm_expr, dbl); | |
17a2f251 TS |
7518 | macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t", |
7519 | dreg, sreg, AT); | |
252b5132 RH |
7520 | break; |
7521 | ||
7522 | case M_TEQ_I: | |
7523 | s = "teq"; | |
7524 | goto trap; | |
7525 | case M_TGE_I: | |
7526 | s = "tge"; | |
7527 | goto trap; | |
7528 | case M_TGEU_I: | |
7529 | s = "tgeu"; | |
7530 | goto trap; | |
7531 | case M_TLT_I: | |
7532 | s = "tlt"; | |
7533 | goto trap; | |
7534 | case M_TLTU_I: | |
7535 | s = "tltu"; | |
7536 | goto trap; | |
7537 | case M_TNE_I: | |
7538 | s = "tne"; | |
7539 | trap: | |
4d34fb5f | 7540 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
17a2f251 | 7541 | macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT); |
252b5132 RH |
7542 | break; |
7543 | ||
252b5132 | 7544 | case M_TRUNCWS: |
43841e91 | 7545 | case M_TRUNCWD: |
e7af610e | 7546 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7547 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7548 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7549 | ||
7550 | /* | |
7551 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7552 | * or is there a reason for it? | |
7553 | */ | |
b34976b6 | 7554 | mips_emit_delays (TRUE); |
252b5132 RH |
7555 | ++mips_opts.noreorder; |
7556 | mips_any_noreorder = 1; | |
17a2f251 TS |
7557 | macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA); |
7558 | macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA); | |
7559 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 | 7560 | expr1.X_add_number = 3; |
17a2f251 TS |
7561 | macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
7562 | BFD_RELOC_LO16); | |
252b5132 | 7563 | expr1.X_add_number = 2; |
17a2f251 TS |
7564 | macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
7565 | BFD_RELOC_LO16); | |
7566 | macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA); | |
7567 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
7568 | macro_build (NULL, &icnt, NULL, | |
7569 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", | |
7570 | "D,S", dreg, sreg); | |
7571 | macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA); | |
7572 | macro_build (NULL, &icnt, NULL, "nop", ""); | |
252b5132 RH |
7573 | --mips_opts.noreorder; |
7574 | break; | |
7575 | ||
7576 | case M_ULH: | |
7577 | s = "lb"; | |
7578 | goto ulh; | |
7579 | case M_ULHU: | |
7580 | s = "lbu"; | |
7581 | ulh: | |
7582 | if (offset_expr.X_add_number >= 0x7fff) | |
7583 | as_bad (_("operand overflow")); | |
252b5132 | 7584 | if (! target_big_endian) |
f9419b05 | 7585 | ++offset_expr.X_add_number; |
17a2f251 TS |
7586 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT, |
7587 | BFD_RELOC_LO16, breg); | |
252b5132 | 7588 | if (! target_big_endian) |
f9419b05 | 7589 | --offset_expr.X_add_number; |
252b5132 | 7590 | else |
f9419b05 | 7591 | ++offset_expr.X_add_number; |
17a2f251 TS |
7592 | macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg, |
7593 | BFD_RELOC_LO16, breg); | |
7594 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8); | |
7595 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7596 | break; |
7597 | ||
7598 | case M_ULD: | |
7599 | s = "ldl"; | |
7600 | s2 = "ldr"; | |
7601 | off = 7; | |
7602 | goto ulw; | |
7603 | case M_ULW: | |
7604 | s = "lwl"; | |
7605 | s2 = "lwr"; | |
7606 | off = 3; | |
7607 | ulw: | |
7608 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7609 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7610 | if (treg != breg) |
7611 | tempreg = treg; | |
7612 | else | |
7613 | tempreg = AT; | |
252b5132 RH |
7614 | if (! target_big_endian) |
7615 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7616 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg, |
7617 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7618 | if (! target_big_endian) |
7619 | offset_expr.X_add_number -= off; | |
7620 | else | |
7621 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7622 | macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg, |
7623 | BFD_RELOC_LO16, breg); | |
af22f5b2 CD |
7624 | |
7625 | /* If necessary, move the result in tempreg the final destination. */ | |
7626 | if (treg == tempreg) | |
7627 | return; | |
7628 | /* Protect second load's delay slot. */ | |
7629 | if (!gpr_interlocks) | |
17a2f251 | 7630 | macro_build (NULL, &icnt, NULL, "nop", ""); |
af22f5b2 CD |
7631 | move_register (&icnt, treg, tempreg); |
7632 | break; | |
252b5132 RH |
7633 | |
7634 | case M_ULD_A: | |
7635 | s = "ldl"; | |
7636 | s2 = "ldr"; | |
7637 | off = 7; | |
7638 | goto ulwa; | |
7639 | case M_ULW_A: | |
7640 | s = "lwl"; | |
7641 | s2 = "lwr"; | |
7642 | off = 3; | |
7643 | ulwa: | |
d6bc6245 | 7644 | used_at = 1; |
c9914766 | 7645 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7646 | if (breg != 0) |
17a2f251 TS |
7647 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7648 | AT, AT, breg); | |
252b5132 RH |
7649 | if (! target_big_endian) |
7650 | expr1.X_add_number = off; | |
7651 | else | |
7652 | expr1.X_add_number = 0; | |
17a2f251 TS |
7653 | macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg, |
7654 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7655 | if (! target_big_endian) |
7656 | expr1.X_add_number = 0; | |
7657 | else | |
7658 | expr1.X_add_number = off; | |
17a2f251 TS |
7659 | macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
7660 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7661 | break; |
7662 | ||
7663 | case M_ULH_A: | |
7664 | case M_ULHU_A: | |
d6bc6245 | 7665 | used_at = 1; |
c9914766 | 7666 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7667 | if (breg != 0) |
17a2f251 TS |
7668 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7669 | AT, AT, breg); | |
252b5132 RH |
7670 | if (target_big_endian) |
7671 | expr1.X_add_number = 0; | |
17a2f251 TS |
7672 | macro_build (NULL, &icnt, &expr1, |
7673 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", | |
7674 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7675 | if (target_big_endian) |
7676 | expr1.X_add_number = 1; | |
7677 | else | |
7678 | expr1.X_add_number = 0; | |
17a2f251 TS |
7679 | macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", |
7680 | AT, BFD_RELOC_LO16, AT); | |
7681 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
7682 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7683 | break; |
7684 | ||
7685 | case M_USH: | |
7686 | if (offset_expr.X_add_number >= 0x7fff) | |
7687 | as_bad (_("operand overflow")); | |
7688 | if (target_big_endian) | |
f9419b05 | 7689 | ++offset_expr.X_add_number; |
17a2f251 TS |
7690 | macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
7691 | BFD_RELOC_LO16, breg); | |
7692 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7693 | if (target_big_endian) |
f9419b05 | 7694 | --offset_expr.X_add_number; |
252b5132 | 7695 | else |
f9419b05 | 7696 | ++offset_expr.X_add_number; |
17a2f251 TS |
7697 | macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
7698 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7699 | break; |
7700 | ||
7701 | case M_USD: | |
7702 | s = "sdl"; | |
7703 | s2 = "sdr"; | |
7704 | off = 7; | |
7705 | goto usw; | |
7706 | case M_USW: | |
7707 | s = "swl"; | |
7708 | s2 = "swr"; | |
7709 | off = 3; | |
7710 | usw: | |
7711 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7712 | as_bad (_("operand overflow")); | |
7713 | if (! target_big_endian) | |
7714 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7715 | macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7716 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7717 | if (! target_big_endian) |
7718 | offset_expr.X_add_number -= off; | |
7719 | else | |
7720 | offset_expr.X_add_number += off; | |
17a2f251 TS |
7721 | macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, |
7722 | BFD_RELOC_LO16, breg); | |
252b5132 RH |
7723 | return; |
7724 | ||
7725 | case M_USD_A: | |
7726 | s = "sdl"; | |
7727 | s2 = "sdr"; | |
7728 | off = 7; | |
7729 | goto uswa; | |
7730 | case M_USW_A: | |
7731 | s = "swl"; | |
7732 | s2 = "swr"; | |
7733 | off = 3; | |
7734 | uswa: | |
d6bc6245 | 7735 | used_at = 1; |
c9914766 | 7736 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7737 | if (breg != 0) |
17a2f251 TS |
7738 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7739 | AT, AT, breg); | |
252b5132 RH |
7740 | if (! target_big_endian) |
7741 | expr1.X_add_number = off; | |
7742 | else | |
7743 | expr1.X_add_number = 0; | |
17a2f251 TS |
7744 | macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg, |
7745 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7746 | if (! target_big_endian) |
7747 | expr1.X_add_number = 0; | |
7748 | else | |
7749 | expr1.X_add_number = off; | |
17a2f251 TS |
7750 | macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
7751 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7752 | break; |
7753 | ||
7754 | case M_USH_A: | |
d6bc6245 | 7755 | used_at = 1; |
c9914766 | 7756 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 | 7757 | if (breg != 0) |
17a2f251 TS |
7758 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
7759 | AT, AT, breg); | |
252b5132 RH |
7760 | if (! target_big_endian) |
7761 | expr1.X_add_number = 0; | |
17a2f251 TS |
7762 | macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
7763 | BFD_RELOC_LO16, AT); | |
7764 | macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7765 | if (! target_big_endian) |
7766 | expr1.X_add_number = 1; | |
7767 | else | |
7768 | expr1.X_add_number = 0; | |
17a2f251 TS |
7769 | macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
7770 | BFD_RELOC_LO16, AT); | |
252b5132 RH |
7771 | if (! target_big_endian) |
7772 | expr1.X_add_number = 0; | |
7773 | else | |
7774 | expr1.X_add_number = 1; | |
17a2f251 TS |
7775 | macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
7776 | BFD_RELOC_LO16, AT); | |
7777 | macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
7778 | macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7779 | break; |
7780 | ||
7781 | default: | |
7782 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7783 | are added dynamically. */ |
252b5132 RH |
7784 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7785 | break; | |
7786 | } | |
7787 | if (mips_opts.noat) | |
7788 | as_warn (_("Macro used $at after \".set noat\"")); | |
7789 | } | |
7790 | ||
7791 | /* Implement macros in mips16 mode. */ | |
7792 | ||
7793 | static void | |
17a2f251 | 7794 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7795 | { |
7796 | int mask; | |
7797 | int xreg, yreg, zreg, tmp; | |
7798 | int icnt; | |
7799 | expressionS expr1; | |
7800 | int dbl; | |
7801 | const char *s, *s2, *s3; | |
7802 | ||
7803 | mask = ip->insn_mo->mask; | |
7804 | ||
7805 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7806 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7807 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7808 | ||
7809 | icnt = 0; | |
7810 | ||
7811 | expr1.X_op = O_constant; | |
7812 | expr1.X_op_symbol = NULL; | |
7813 | expr1.X_add_symbol = NULL; | |
7814 | expr1.X_add_number = 1; | |
7815 | ||
7816 | dbl = 0; | |
7817 | ||
7818 | switch (mask) | |
7819 | { | |
7820 | default: | |
7821 | internalError (); | |
7822 | ||
7823 | case M_DDIV_3: | |
7824 | dbl = 1; | |
7825 | case M_DIV_3: | |
7826 | s = "mflo"; | |
7827 | goto do_div3; | |
7828 | case M_DREM_3: | |
7829 | dbl = 1; | |
7830 | case M_REM_3: | |
7831 | s = "mfhi"; | |
7832 | do_div3: | |
b34976b6 | 7833 | mips_emit_delays (TRUE); |
252b5132 RH |
7834 | ++mips_opts.noreorder; |
7835 | mips_any_noreorder = 1; | |
17a2f251 TS |
7836 | macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y", |
7837 | xreg, yreg); | |
252b5132 | 7838 | expr1.X_add_number = 2; |
17a2f251 TS |
7839 | macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
7840 | macro_build (NULL, &icnt, NULL, "break", "6", 7); | |
bdaaa2e1 | 7841 | |
252b5132 RH |
7842 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7843 | since that causes an overflow. We should do that as well, | |
7844 | but I don't see how to do the comparisons without a temporary | |
7845 | register. */ | |
7846 | --mips_opts.noreorder; | |
17a2f251 | 7847 | macro_build (NULL, &icnt, NULL, s, "x", zreg); |
252b5132 RH |
7848 | break; |
7849 | ||
7850 | case M_DIVU_3: | |
7851 | s = "divu"; | |
7852 | s2 = "mflo"; | |
7853 | goto do_divu3; | |
7854 | case M_REMU_3: | |
7855 | s = "divu"; | |
7856 | s2 = "mfhi"; | |
7857 | goto do_divu3; | |
7858 | case M_DDIVU_3: | |
7859 | s = "ddivu"; | |
7860 | s2 = "mflo"; | |
7861 | goto do_divu3; | |
7862 | case M_DREMU_3: | |
7863 | s = "ddivu"; | |
7864 | s2 = "mfhi"; | |
7865 | do_divu3: | |
b34976b6 | 7866 | mips_emit_delays (TRUE); |
252b5132 RH |
7867 | ++mips_opts.noreorder; |
7868 | mips_any_noreorder = 1; | |
17a2f251 | 7869 | macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7870 | expr1.X_add_number = 2; |
17a2f251 TS |
7871 | macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
7872 | macro_build (NULL, &icnt, NULL, "break", "6", 7); | |
252b5132 | 7873 | --mips_opts.noreorder; |
17a2f251 | 7874 | macro_build (NULL, &icnt, NULL, s2, "x", zreg); |
252b5132 RH |
7875 | break; |
7876 | ||
7877 | case M_DMUL: | |
7878 | dbl = 1; | |
7879 | case M_MUL: | |
17a2f251 TS |
7880 | macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y", |
7881 | xreg, yreg); | |
7882 | macro_build (NULL, &icnt, NULL, "mflo", "x", zreg); | |
252b5132 RH |
7883 | return; |
7884 | ||
7885 | case M_DSUBU_I: | |
7886 | dbl = 1; | |
7887 | goto do_subu; | |
7888 | case M_SUBU_I: | |
7889 | do_subu: | |
7890 | if (imm_expr.X_op != O_constant) | |
7891 | as_bad (_("Unsupported large constant")); | |
7892 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 TS |
7893 | macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", |
7894 | yreg, xreg); | |
252b5132 RH |
7895 | break; |
7896 | ||
7897 | case M_SUBU_I_2: | |
7898 | if (imm_expr.X_op != O_constant) | |
7899 | as_bad (_("Unsupported large constant")); | |
7900 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7901 | macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7902 | break; |
7903 | ||
7904 | case M_DSUBU_I_2: | |
7905 | if (imm_expr.X_op != O_constant) | |
7906 | as_bad (_("Unsupported large constant")); | |
7907 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
17a2f251 | 7908 | macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7909 | break; |
7910 | ||
7911 | case M_BEQ: | |
7912 | s = "cmp"; | |
7913 | s2 = "bteqz"; | |
7914 | goto do_branch; | |
7915 | case M_BNE: | |
7916 | s = "cmp"; | |
7917 | s2 = "btnez"; | |
7918 | goto do_branch; | |
7919 | case M_BLT: | |
7920 | s = "slt"; | |
7921 | s2 = "btnez"; | |
7922 | goto do_branch; | |
7923 | case M_BLTU: | |
7924 | s = "sltu"; | |
7925 | s2 = "btnez"; | |
7926 | goto do_branch; | |
7927 | case M_BLE: | |
7928 | s = "slt"; | |
7929 | s2 = "bteqz"; | |
7930 | goto do_reverse_branch; | |
7931 | case M_BLEU: | |
7932 | s = "sltu"; | |
7933 | s2 = "bteqz"; | |
7934 | goto do_reverse_branch; | |
7935 | case M_BGE: | |
7936 | s = "slt"; | |
7937 | s2 = "bteqz"; | |
7938 | goto do_branch; | |
7939 | case M_BGEU: | |
7940 | s = "sltu"; | |
7941 | s2 = "bteqz"; | |
7942 | goto do_branch; | |
7943 | case M_BGT: | |
7944 | s = "slt"; | |
7945 | s2 = "btnez"; | |
7946 | goto do_reverse_branch; | |
7947 | case M_BGTU: | |
7948 | s = "sltu"; | |
7949 | s2 = "btnez"; | |
7950 | ||
7951 | do_reverse_branch: | |
7952 | tmp = xreg; | |
7953 | xreg = yreg; | |
7954 | yreg = tmp; | |
7955 | ||
7956 | do_branch: | |
17a2f251 TS |
7957 | macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg); |
7958 | macro_build (NULL, &icnt, &offset_expr, s2, "p"); | |
252b5132 RH |
7959 | break; |
7960 | ||
7961 | case M_BEQ_I: | |
7962 | s = "cmpi"; | |
7963 | s2 = "bteqz"; | |
7964 | s3 = "x,U"; | |
7965 | goto do_branch_i; | |
7966 | case M_BNE_I: | |
7967 | s = "cmpi"; | |
7968 | s2 = "btnez"; | |
7969 | s3 = "x,U"; | |
7970 | goto do_branch_i; | |
7971 | case M_BLT_I: | |
7972 | s = "slti"; | |
7973 | s2 = "btnez"; | |
7974 | s3 = "x,8"; | |
7975 | goto do_branch_i; | |
7976 | case M_BLTU_I: | |
7977 | s = "sltiu"; | |
7978 | s2 = "btnez"; | |
7979 | s3 = "x,8"; | |
7980 | goto do_branch_i; | |
7981 | case M_BLE_I: | |
7982 | s = "slti"; | |
7983 | s2 = "btnez"; | |
7984 | s3 = "x,8"; | |
7985 | goto do_addone_branch_i; | |
7986 | case M_BLEU_I: | |
7987 | s = "sltiu"; | |
7988 | s2 = "btnez"; | |
7989 | s3 = "x,8"; | |
7990 | goto do_addone_branch_i; | |
7991 | case M_BGE_I: | |
7992 | s = "slti"; | |
7993 | s2 = "bteqz"; | |
7994 | s3 = "x,8"; | |
7995 | goto do_branch_i; | |
7996 | case M_BGEU_I: | |
7997 | s = "sltiu"; | |
7998 | s2 = "bteqz"; | |
7999 | s3 = "x,8"; | |
8000 | goto do_branch_i; | |
8001 | case M_BGT_I: | |
8002 | s = "slti"; | |
8003 | s2 = "bteqz"; | |
8004 | s3 = "x,8"; | |
8005 | goto do_addone_branch_i; | |
8006 | case M_BGTU_I: | |
8007 | s = "sltiu"; | |
8008 | s2 = "bteqz"; | |
8009 | s3 = "x,8"; | |
8010 | ||
8011 | do_addone_branch_i: | |
8012 | if (imm_expr.X_op != O_constant) | |
8013 | as_bad (_("Unsupported large constant")); | |
8014 | ++imm_expr.X_add_number; | |
8015 | ||
8016 | do_branch_i: | |
17a2f251 TS |
8017 | macro_build (NULL, &icnt, &imm_expr, s, s3, xreg); |
8018 | macro_build (NULL, &icnt, &offset_expr, s2, "p"); | |
252b5132 RH |
8019 | break; |
8020 | ||
8021 | case M_ABS: | |
8022 | expr1.X_add_number = 0; | |
17a2f251 | 8023 | macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 8024 | if (xreg != yreg) |
ea1fb5dc | 8025 | move_register (&icnt, xreg, yreg); |
252b5132 | 8026 | expr1.X_add_number = 2; |
17a2f251 TS |
8027 | macro_build (NULL, &icnt, &expr1, "bteqz", "p"); |
8028 | macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8029 | } |
8030 | } | |
8031 | ||
8032 | /* For consistency checking, verify that all bits are specified either | |
8033 | by the match/mask part of the instruction definition, or by the | |
8034 | operand list. */ | |
8035 | static int | |
17a2f251 | 8036 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8037 | { |
8038 | const char *p = opc->args; | |
8039 | char c; | |
8040 | unsigned long used_bits = opc->mask; | |
8041 | ||
8042 | if ((used_bits & opc->match) != opc->match) | |
8043 | { | |
8044 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8045 | opc->name, opc->args); | |
8046 | return 0; | |
8047 | } | |
8048 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8049 | while (*p) | |
8050 | switch (c = *p++) | |
8051 | { | |
8052 | case ',': break; | |
8053 | case '(': break; | |
8054 | case ')': break; | |
af7ee8bf CD |
8055 | case '+': |
8056 | switch (c = *p++) | |
8057 | { | |
8058 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8059 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8060 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8061 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8062 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8063 | default: |
8064 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8065 | c, opc->name, opc->args); | |
8066 | return 0; | |
8067 | } | |
8068 | break; | |
252b5132 RH |
8069 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8070 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8071 | case 'A': break; | |
4372b673 | 8072 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8073 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8074 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8075 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8076 | case 'F': break; | |
8077 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8078 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8079 | case 'I': break; |
e972090a | 8080 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8081 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8082 | case 'L': break; |
8083 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8084 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8085 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8086 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8087 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8088 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8089 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8090 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8091 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8092 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8093 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8094 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8095 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8096 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8097 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8098 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8099 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8100 | case 'f': break; | |
8101 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8102 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8103 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8104 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8105 | case 'l': break; | |
8106 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8107 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8108 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8109 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8110 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8111 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8112 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8113 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8114 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8115 | case 'x': break; | |
8116 | case 'z': break; | |
8117 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8118 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8119 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8120 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8121 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8122 | case '[': break; | |
8123 | case ']': break; | |
252b5132 RH |
8124 | default: |
8125 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8126 | c, opc->name, opc->args); | |
8127 | return 0; | |
8128 | } | |
8129 | #undef USE_BITS | |
8130 | if (used_bits != 0xffffffff) | |
8131 | { | |
8132 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8133 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8134 | return 0; | |
8135 | } | |
8136 | return 1; | |
8137 | } | |
8138 | ||
8139 | /* This routine assembles an instruction into its binary format. As a | |
8140 | side effect, it sets one of the global variables imm_reloc or | |
8141 | offset_reloc to the type of relocation to do if one of the operands | |
8142 | is an address expression. */ | |
8143 | ||
8144 | static void | |
17a2f251 | 8145 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8146 | { |
8147 | char *s; | |
8148 | const char *args; | |
43841e91 | 8149 | char c = 0; |
252b5132 RH |
8150 | struct mips_opcode *insn; |
8151 | char *argsStart; | |
8152 | unsigned int regno; | |
8153 | unsigned int lastregno = 0; | |
af7ee8bf | 8154 | unsigned int lastpos = 0; |
071742cf | 8155 | unsigned int limlo, limhi; |
252b5132 RH |
8156 | char *s_reset; |
8157 | char save_c = 0; | |
252b5132 RH |
8158 | |
8159 | insn_error = NULL; | |
8160 | ||
8161 | /* If the instruction contains a '.', we first try to match an instruction | |
8162 | including the '.'. Then we try again without the '.'. */ | |
8163 | insn = NULL; | |
3882b010 | 8164 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8165 | continue; |
8166 | ||
8167 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8168 | the call to hash_find. Save the character we replaced just in case we | |
8169 | have to re-parse the instruction. */ | |
3882b010 | 8170 | if (ISSPACE (*s)) |
252b5132 RH |
8171 | { |
8172 | save_c = *s; | |
8173 | *s++ = '\0'; | |
8174 | } | |
bdaaa2e1 | 8175 | |
252b5132 RH |
8176 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8177 | ||
8178 | /* If we didn't find the instruction in the opcode table, try again, but | |
8179 | this time with just the instruction up to, but not including the | |
8180 | first '.'. */ | |
8181 | if (insn == NULL) | |
8182 | { | |
bdaaa2e1 | 8183 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8184 | if (save_c) |
8185 | *(--s) = save_c; | |
8186 | ||
8187 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8188 | for (s = str; |
8189 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8190 | ++s) | |
252b5132 RH |
8191 | continue; |
8192 | ||
8193 | /* If we did not find a '.', then we can quit now. */ | |
8194 | if (*s != '.') | |
8195 | { | |
8196 | insn_error = "unrecognized opcode"; | |
8197 | return; | |
8198 | } | |
8199 | ||
8200 | /* Lookup the instruction in the hash table. */ | |
8201 | *s++ = '\0'; | |
8202 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8203 | { | |
8204 | insn_error = "unrecognized opcode"; | |
8205 | return; | |
8206 | } | |
252b5132 RH |
8207 | } |
8208 | ||
8209 | argsStart = s; | |
8210 | for (;;) | |
8211 | { | |
b34976b6 | 8212 | bfd_boolean ok; |
252b5132 RH |
8213 | |
8214 | assert (strcmp (insn->name, str) == 0); | |
8215 | ||
1f25f5d3 CD |
8216 | if (OPCODE_IS_MEMBER (insn, |
8217 | (mips_opts.isa | |
3396de36 | 8218 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8219 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8220 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 8221 | mips_opts.arch)) |
b34976b6 | 8222 | ok = TRUE; |
bdaaa2e1 | 8223 | else |
b34976b6 | 8224 | ok = FALSE; |
bdaaa2e1 | 8225 | |
252b5132 RH |
8226 | if (insn->pinfo != INSN_MACRO) |
8227 | { | |
fef14a42 | 8228 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8229 | ok = FALSE; |
252b5132 RH |
8230 | } |
8231 | ||
8232 | if (! ok) | |
8233 | { | |
8234 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8235 | && strcmp (insn->name, insn[1].name) == 0) | |
8236 | { | |
8237 | ++insn; | |
8238 | continue; | |
8239 | } | |
252b5132 | 8240 | else |
beae10d5 | 8241 | { |
268f6bed L |
8242 | if (!insn_error) |
8243 | { | |
8244 | static char buf[100]; | |
fef14a42 TS |
8245 | sprintf (buf, |
8246 | _("opcode not supported on this processor: %s (%s)"), | |
8247 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8248 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8249 | insn_error = buf; |
8250 | } | |
8251 | if (save_c) | |
8252 | *(--s) = save_c; | |
2bd7f1f3 | 8253 | return; |
252b5132 | 8254 | } |
252b5132 RH |
8255 | } |
8256 | ||
8257 | ip->insn_mo = insn; | |
8258 | ip->insn_opcode = insn->match; | |
268f6bed | 8259 | insn_error = NULL; |
252b5132 RH |
8260 | for (args = insn->args;; ++args) |
8261 | { | |
deec1734 CD |
8262 | int is_mdmx; |
8263 | ||
ad8d3bb3 | 8264 | s += strspn (s, " \t"); |
deec1734 | 8265 | is_mdmx = 0; |
252b5132 RH |
8266 | switch (*args) |
8267 | { | |
8268 | case '\0': /* end of args */ | |
8269 | if (*s == '\0') | |
8270 | return; | |
8271 | break; | |
8272 | ||
8273 | case ',': | |
8274 | if (*s++ == *args) | |
8275 | continue; | |
8276 | s--; | |
8277 | switch (*++args) | |
8278 | { | |
8279 | case 'r': | |
8280 | case 'v': | |
38487616 | 8281 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8282 | continue; |
8283 | ||
8284 | case 'w': | |
38487616 TS |
8285 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8286 | continue; | |
8287 | ||
252b5132 | 8288 | case 'W': |
38487616 | 8289 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8290 | continue; |
8291 | ||
8292 | case 'V': | |
38487616 | 8293 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8294 | continue; |
8295 | } | |
8296 | break; | |
8297 | ||
8298 | case '(': | |
8299 | /* Handle optional base register. | |
8300 | Either the base register is omitted or | |
bdaaa2e1 | 8301 | we must have a left paren. */ |
252b5132 RH |
8302 | /* This is dependent on the next operand specifier |
8303 | is a base register specification. */ | |
8304 | assert (args[1] == 'b' || args[1] == '5' | |
8305 | || args[1] == '-' || args[1] == '4'); | |
8306 | if (*s == '\0') | |
8307 | return; | |
8308 | ||
8309 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8310 | case '[': |
8311 | case ']': | |
252b5132 RH |
8312 | if (*s++ == *args) |
8313 | continue; | |
8314 | break; | |
8315 | ||
af7ee8bf CD |
8316 | case '+': /* Opcode extension character. */ |
8317 | switch (*++args) | |
8318 | { | |
071742cf CD |
8319 | case 'A': /* ins/ext position, becomes LSB. */ |
8320 | limlo = 0; | |
8321 | limhi = 31; | |
8322 | my_getExpression (&imm_expr, s); | |
8323 | check_absolute_expr (ip, &imm_expr); | |
8324 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8325 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8326 | { | |
8327 | as_bad (_("Improper position (%lu)"), | |
8328 | (unsigned long) imm_expr.X_add_number); | |
8329 | imm_expr.X_add_number = limlo; | |
8330 | } | |
8331 | lastpos = imm_expr.X_add_number; | |
8332 | ip->insn_opcode |= (imm_expr.X_add_number | |
8333 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8334 | imm_expr.X_op = O_absent; | |
8335 | s = expr_end; | |
8336 | continue; | |
8337 | ||
8338 | case 'B': /* ins size, becomes MSB. */ | |
8339 | limlo = 1; | |
8340 | limhi = 32; | |
8341 | my_getExpression (&imm_expr, s); | |
8342 | check_absolute_expr (ip, &imm_expr); | |
8343 | /* Check for negative input so that small negative numbers | |
8344 | will not succeed incorrectly. The checks against | |
8345 | (pos+size) transitively check "size" itself, | |
8346 | assuming that "pos" is reasonable. */ | |
8347 | if ((long) imm_expr.X_add_number < 0 | |
8348 | || ((unsigned long) imm_expr.X_add_number | |
8349 | + lastpos) < limlo | |
8350 | || ((unsigned long) imm_expr.X_add_number | |
8351 | + lastpos) > limhi) | |
8352 | { | |
8353 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8354 | (unsigned long) imm_expr.X_add_number, | |
8355 | (unsigned long) lastpos); | |
8356 | imm_expr.X_add_number = limlo - lastpos; | |
8357 | } | |
8358 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8359 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8360 | imm_expr.X_op = O_absent; | |
8361 | s = expr_end; | |
8362 | continue; | |
8363 | ||
8364 | case 'C': /* ext size, becomes MSBD. */ | |
8365 | limlo = 1; | |
8366 | limhi = 32; | |
8367 | my_getExpression (&imm_expr, s); | |
8368 | check_absolute_expr (ip, &imm_expr); | |
8369 | /* Check for negative input so that small negative numbers | |
8370 | will not succeed incorrectly. The checks against | |
8371 | (pos+size) transitively check "size" itself, | |
8372 | assuming that "pos" is reasonable. */ | |
8373 | if ((long) imm_expr.X_add_number < 0 | |
8374 | || ((unsigned long) imm_expr.X_add_number | |
8375 | + lastpos) < limlo | |
8376 | || ((unsigned long) imm_expr.X_add_number | |
8377 | + lastpos) > limhi) | |
8378 | { | |
8379 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8380 | (unsigned long) imm_expr.X_add_number, | |
8381 | (unsigned long) lastpos); | |
8382 | imm_expr.X_add_number = limlo - lastpos; | |
8383 | } | |
8384 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8385 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8386 | imm_expr.X_op = O_absent; | |
8387 | s = expr_end; | |
8388 | continue; | |
af7ee8bf | 8389 | |
bbcc0807 CD |
8390 | case 'D': |
8391 | /* +D is for disassembly only; never match. */ | |
8392 | break; | |
8393 | ||
af7ee8bf CD |
8394 | default: |
8395 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8396 | *args, insn->name, insn->args); | |
8397 | /* Further processing is fruitless. */ | |
8398 | return; | |
8399 | } | |
8400 | break; | |
8401 | ||
252b5132 RH |
8402 | case '<': /* must be at least one digit */ |
8403 | /* | |
8404 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8405 | * than 31 or less than 0, then the shift amount should be |
8406 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8407 | * We issue a warning and mask out all but the low 5 bits. |
8408 | */ | |
8409 | my_getExpression (&imm_expr, s); | |
8410 | check_absolute_expr (ip, &imm_expr); | |
8411 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8412 | { | |
793b27f4 TS |
8413 | as_warn (_("Improper shift amount (%lu)"), |
8414 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8415 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8416 | } |
38487616 | 8417 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8418 | imm_expr.X_op = O_absent; |
8419 | s = expr_end; | |
8420 | continue; | |
8421 | ||
8422 | case '>': /* shift amount minus 32 */ | |
8423 | my_getExpression (&imm_expr, s); | |
8424 | check_absolute_expr (ip, &imm_expr); | |
8425 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8426 | || (unsigned long) imm_expr.X_add_number > 63) | |
8427 | break; | |
38487616 | 8428 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8429 | imm_expr.X_op = O_absent; |
8430 | s = expr_end; | |
8431 | continue; | |
8432 | ||
252b5132 RH |
8433 | case 'k': /* cache code */ |
8434 | case 'h': /* prefx code */ | |
8435 | my_getExpression (&imm_expr, s); | |
8436 | check_absolute_expr (ip, &imm_expr); | |
8437 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8438 | { | |
8439 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8440 | ip->insn_mo->name, | |
8441 | (unsigned long) imm_expr.X_add_number); | |
8442 | imm_expr.X_add_number &= 0x1f; | |
8443 | } | |
8444 | if (*args == 'k') | |
8445 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8446 | else | |
8447 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8448 | imm_expr.X_op = O_absent; | |
8449 | s = expr_end; | |
8450 | continue; | |
8451 | ||
8452 | case 'c': /* break code */ | |
8453 | my_getExpression (&imm_expr, s); | |
8454 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8455 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8456 | { |
793b27f4 TS |
8457 | as_warn (_("Illegal break code (%lu)"), |
8458 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8459 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8460 | } |
38487616 | 8461 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8462 | imm_expr.X_op = O_absent; |
8463 | s = expr_end; | |
8464 | continue; | |
8465 | ||
8466 | case 'q': /* lower break code */ | |
8467 | my_getExpression (&imm_expr, s); | |
8468 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8469 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8470 | { |
793b27f4 TS |
8471 | as_warn (_("Illegal lower break code (%lu)"), |
8472 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8473 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8474 | } |
38487616 | 8475 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8476 | imm_expr.X_op = O_absent; |
8477 | s = expr_end; | |
8478 | continue; | |
8479 | ||
4372b673 | 8480 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8481 | my_getExpression (&imm_expr, s); |
156c2f8b | 8482 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8483 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8484 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8485 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8486 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8487 | imm_expr.X_op = O_absent; |
8488 | s = expr_end; | |
8489 | continue; | |
8490 | ||
98d3f06f | 8491 | case 'C': /* Coprocessor code */ |
beae10d5 | 8492 | my_getExpression (&imm_expr, s); |
252b5132 | 8493 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8494 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8495 | { |
793b27f4 TS |
8496 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8497 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8498 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8499 | } |
beae10d5 KH |
8500 | ip->insn_opcode |= imm_expr.X_add_number; |
8501 | imm_expr.X_op = O_absent; | |
8502 | s = expr_end; | |
8503 | continue; | |
252b5132 | 8504 | |
4372b673 NC |
8505 | case 'J': /* 19-bit wait code. */ |
8506 | my_getExpression (&imm_expr, s); | |
8507 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8508 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8509 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8510 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8511 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8512 | imm_expr.X_op = O_absent; |
8513 | s = expr_end; | |
8514 | continue; | |
8515 | ||
252b5132 | 8516 | case 'P': /* Performance register */ |
beae10d5 | 8517 | my_getExpression (&imm_expr, s); |
252b5132 | 8518 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8519 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8520 | { |
793b27f4 TS |
8521 | as_warn (_("Invalid performance register (%lu)"), |
8522 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8523 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8524 | } |
38487616 | 8525 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8526 | imm_expr.X_op = O_absent; |
8527 | s = expr_end; | |
8528 | continue; | |
252b5132 RH |
8529 | |
8530 | case 'b': /* base register */ | |
8531 | case 'd': /* destination register */ | |
8532 | case 's': /* source register */ | |
8533 | case 't': /* target register */ | |
8534 | case 'r': /* both target and source */ | |
8535 | case 'v': /* both dest and source */ | |
8536 | case 'w': /* both dest and target */ | |
8537 | case 'E': /* coprocessor target register */ | |
8538 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8539 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8540 | case 'x': /* ignore register name */ |
8541 | case 'z': /* must be zero register */ | |
4372b673 | 8542 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8543 | s_reset = s; |
8544 | if (s[0] == '$') | |
8545 | { | |
8546 | ||
3882b010 | 8547 | if (ISDIGIT (s[1])) |
252b5132 RH |
8548 | { |
8549 | ++s; | |
8550 | regno = 0; | |
8551 | do | |
8552 | { | |
8553 | regno *= 10; | |
8554 | regno += *s - '0'; | |
8555 | ++s; | |
8556 | } | |
3882b010 | 8557 | while (ISDIGIT (*s)); |
252b5132 RH |
8558 | if (regno > 31) |
8559 | as_bad (_("Invalid register number (%d)"), regno); | |
8560 | } | |
af7ee8bf | 8561 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8562 | goto notreg; |
8563 | else | |
8564 | { | |
76db943d TS |
8565 | if (s[1] == 'r' && s[2] == 'a') |
8566 | { | |
8567 | s += 3; | |
8568 | regno = RA; | |
8569 | } | |
8570 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8571 | { |
8572 | s += 3; | |
8573 | regno = FP; | |
8574 | } | |
8575 | else if (s[1] == 's' && s[2] == 'p') | |
8576 | { | |
8577 | s += 3; | |
8578 | regno = SP; | |
8579 | } | |
8580 | else if (s[1] == 'g' && s[2] == 'p') | |
8581 | { | |
8582 | s += 3; | |
8583 | regno = GP; | |
8584 | } | |
8585 | else if (s[1] == 'a' && s[2] == 't') | |
8586 | { | |
8587 | s += 3; | |
8588 | regno = AT; | |
8589 | } | |
8590 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8591 | { | |
8592 | s += 4; | |
8593 | regno = KT0; | |
8594 | } | |
8595 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8596 | { | |
8597 | s += 4; | |
8598 | regno = KT1; | |
8599 | } | |
85b51719 TS |
8600 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8601 | { | |
8602 | s += 5; | |
8603 | regno = ZERO; | |
8604 | } | |
252b5132 RH |
8605 | else if (itbl_have_entries) |
8606 | { | |
8607 | char *p, *n; | |
d7ba4a77 | 8608 | unsigned long r; |
252b5132 | 8609 | |
d7ba4a77 | 8610 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8611 | n = itbl_get_field (&p); /* n is name */ |
8612 | ||
d7ba4a77 ILT |
8613 | /* See if this is a register defined in an |
8614 | itbl entry. */ | |
8615 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8616 | { |
8617 | /* Get_field advances to the start of | |
8618 | the next field, so we need to back | |
d7ba4a77 | 8619 | rack to the end of the last field. */ |
bdaaa2e1 | 8620 | if (p) |
252b5132 | 8621 | s = p - 1; |
bdaaa2e1 | 8622 | else |
d7ba4a77 | 8623 | s = strchr (s, '\0'); |
252b5132 RH |
8624 | regno = r; |
8625 | } | |
8626 | else | |
8627 | goto notreg; | |
beae10d5 | 8628 | } |
252b5132 RH |
8629 | else |
8630 | goto notreg; | |
8631 | } | |
8632 | if (regno == AT | |
8633 | && ! mips_opts.noat | |
8634 | && *args != 'E' | |
af7ee8bf CD |
8635 | && *args != 'G' |
8636 | && *args != 'K') | |
252b5132 RH |
8637 | as_warn (_("Used $at without \".set noat\"")); |
8638 | c = *args; | |
8639 | if (*s == ' ') | |
f9419b05 | 8640 | ++s; |
252b5132 RH |
8641 | if (args[1] != *s) |
8642 | { | |
8643 | if (c == 'r' || c == 'v' || c == 'w') | |
8644 | { | |
8645 | regno = lastregno; | |
8646 | s = s_reset; | |
f9419b05 | 8647 | ++args; |
252b5132 RH |
8648 | } |
8649 | } | |
8650 | /* 'z' only matches $0. */ | |
8651 | if (c == 'z' && regno != 0) | |
8652 | break; | |
8653 | ||
bdaaa2e1 KH |
8654 | /* Now that we have assembled one operand, we use the args string |
8655 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8656 | switch (c) |
8657 | { | |
8658 | case 'r': | |
8659 | case 's': | |
8660 | case 'v': | |
8661 | case 'b': | |
38487616 | 8662 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8663 | break; |
8664 | case 'd': | |
8665 | case 'G': | |
af7ee8bf | 8666 | case 'K': |
38487616 | 8667 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8668 | break; |
4372b673 | 8669 | case 'U': |
38487616 TS |
8670 | ip->insn_opcode |= regno << OP_SH_RD; |
8671 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8672 | break; |
252b5132 RH |
8673 | case 'w': |
8674 | case 't': | |
8675 | case 'E': | |
38487616 | 8676 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8677 | break; |
8678 | case 'x': | |
8679 | /* This case exists because on the r3000 trunc | |
8680 | expands into a macro which requires a gp | |
8681 | register. On the r6000 or r4000 it is | |
8682 | assembled into a single instruction which | |
8683 | ignores the register. Thus the insn version | |
8684 | is MIPS_ISA2 and uses 'x', and the macro | |
8685 | version is MIPS_ISA1 and uses 't'. */ | |
8686 | break; | |
8687 | case 'z': | |
8688 | /* This case is for the div instruction, which | |
8689 | acts differently if the destination argument | |
8690 | is $0. This only matches $0, and is checked | |
8691 | outside the switch. */ | |
8692 | break; | |
8693 | case 'D': | |
8694 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8695 | break; | |
8696 | /* What about all other operands like 'i', which | |
8697 | can be specified in the opcode table? */ | |
8698 | } | |
8699 | lastregno = regno; | |
8700 | continue; | |
8701 | } | |
8702 | notreg: | |
8703 | switch (*args++) | |
8704 | { | |
8705 | case 'r': | |
8706 | case 'v': | |
38487616 | 8707 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8708 | continue; |
8709 | case 'w': | |
38487616 | 8710 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8711 | continue; |
8712 | } | |
8713 | break; | |
8714 | ||
deec1734 CD |
8715 | case 'O': /* MDMX alignment immediate constant. */ |
8716 | my_getExpression (&imm_expr, s); | |
8717 | check_absolute_expr (ip, &imm_expr); | |
8718 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8719 | { | |
8720 | as_warn ("Improper align amount (%ld), using low bits", | |
8721 | (long) imm_expr.X_add_number); | |
8722 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8723 | } | |
8724 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8725 | imm_expr.X_op = O_absent; | |
8726 | s = expr_end; | |
8727 | continue; | |
8728 | ||
8729 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8730 | if (s[0] != '$') | |
8731 | { | |
8732 | /* MDMX Immediate. */ | |
8733 | my_getExpression (&imm_expr, s); | |
8734 | check_absolute_expr (ip, &imm_expr); | |
8735 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8736 | { | |
8737 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8738 | (long) imm_expr.X_add_number); | |
8739 | imm_expr.X_add_number &= OP_MASK_FT; | |
8740 | } | |
8741 | imm_expr.X_add_number &= OP_MASK_FT; | |
8742 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8743 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8744 | else | |
8745 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8746 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8747 | imm_expr.X_op = O_absent; | |
8748 | s = expr_end; | |
8749 | continue; | |
8750 | } | |
8751 | /* Not MDMX Immediate. Fall through. */ | |
8752 | case 'X': /* MDMX destination register. */ | |
8753 | case 'Y': /* MDMX source register. */ | |
8754 | case 'Z': /* MDMX target register. */ | |
8755 | is_mdmx = 1; | |
252b5132 RH |
8756 | case 'D': /* floating point destination register */ |
8757 | case 'S': /* floating point source register */ | |
8758 | case 'T': /* floating point target register */ | |
8759 | case 'R': /* floating point source register */ | |
8760 | case 'V': | |
8761 | case 'W': | |
8762 | s_reset = s; | |
deec1734 CD |
8763 | /* Accept $fN for FP and MDMX register numbers, and in |
8764 | addition accept $vN for MDMX register numbers. */ | |
8765 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8766 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8767 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8768 | { |
8769 | s += 2; | |
8770 | regno = 0; | |
8771 | do | |
8772 | { | |
8773 | regno *= 10; | |
8774 | regno += *s - '0'; | |
8775 | ++s; | |
8776 | } | |
3882b010 | 8777 | while (ISDIGIT (*s)); |
252b5132 RH |
8778 | |
8779 | if (regno > 31) | |
8780 | as_bad (_("Invalid float register number (%d)"), regno); | |
8781 | ||
8782 | if ((regno & 1) != 0 | |
ca4e0257 | 8783 | && HAVE_32BIT_FPRS |
252b5132 RH |
8784 | && ! (strcmp (str, "mtc1") == 0 |
8785 | || strcmp (str, "mfc1") == 0 | |
8786 | || strcmp (str, "lwc1") == 0 | |
8787 | || strcmp (str, "swc1") == 0 | |
8788 | || strcmp (str, "l.s") == 0 | |
8789 | || strcmp (str, "s.s") == 0)) | |
8790 | as_warn (_("Float register should be even, was %d"), | |
8791 | regno); | |
8792 | ||
8793 | c = *args; | |
8794 | if (*s == ' ') | |
f9419b05 | 8795 | ++s; |
252b5132 RH |
8796 | if (args[1] != *s) |
8797 | { | |
8798 | if (c == 'V' || c == 'W') | |
8799 | { | |
8800 | regno = lastregno; | |
8801 | s = s_reset; | |
f9419b05 | 8802 | ++args; |
252b5132 RH |
8803 | } |
8804 | } | |
8805 | switch (c) | |
8806 | { | |
8807 | case 'D': | |
deec1734 | 8808 | case 'X': |
38487616 | 8809 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8810 | break; |
8811 | case 'V': | |
8812 | case 'S': | |
deec1734 | 8813 | case 'Y': |
38487616 | 8814 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8815 | break; |
deec1734 CD |
8816 | case 'Q': |
8817 | /* This is like 'Z', but also needs to fix the MDMX | |
8818 | vector/scalar select bits. Note that the | |
8819 | scalar immediate case is handled above. */ | |
8820 | if (*s == '[') | |
8821 | { | |
8822 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8823 | int max_el = (is_qh ? 3 : 7); | |
8824 | s++; | |
8825 | my_getExpression(&imm_expr, s); | |
8826 | check_absolute_expr (ip, &imm_expr); | |
8827 | s = expr_end; | |
8828 | if (imm_expr.X_add_number > max_el) | |
8829 | as_bad(_("Bad element selector %ld"), | |
8830 | (long) imm_expr.X_add_number); | |
8831 | imm_expr.X_add_number &= max_el; | |
8832 | ip->insn_opcode |= (imm_expr.X_add_number | |
8833 | << (OP_SH_VSEL + | |
8834 | (is_qh ? 2 : 1))); | |
8835 | if (*s != ']') | |
8836 | as_warn(_("Expecting ']' found '%s'"), s); | |
8837 | else | |
8838 | s++; | |
8839 | } | |
8840 | else | |
8841 | { | |
8842 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8843 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8844 | << OP_SH_VSEL); | |
8845 | else | |
8846 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8847 | OP_SH_VSEL); | |
8848 | } | |
8849 | /* Fall through */ | |
252b5132 RH |
8850 | case 'W': |
8851 | case 'T': | |
deec1734 | 8852 | case 'Z': |
38487616 | 8853 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8854 | break; |
8855 | case 'R': | |
38487616 | 8856 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8857 | break; |
8858 | } | |
8859 | lastregno = regno; | |
8860 | continue; | |
8861 | } | |
8862 | ||
252b5132 RH |
8863 | switch (*args++) |
8864 | { | |
8865 | case 'V': | |
38487616 | 8866 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8867 | continue; |
8868 | case 'W': | |
38487616 | 8869 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8870 | continue; |
8871 | } | |
8872 | break; | |
8873 | ||
8874 | case 'I': | |
8875 | my_getExpression (&imm_expr, s); | |
8876 | if (imm_expr.X_op != O_big | |
8877 | && imm_expr.X_op != O_constant) | |
8878 | insn_error = _("absolute expression required"); | |
8879 | s = expr_end; | |
8880 | continue; | |
8881 | ||
8882 | case 'A': | |
8883 | my_getExpression (&offset_expr, s); | |
f6688943 | 8884 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8885 | s = expr_end; |
8886 | continue; | |
8887 | ||
8888 | case 'F': | |
8889 | case 'L': | |
8890 | case 'f': | |
8891 | case 'l': | |
8892 | { | |
8893 | int f64; | |
ca4e0257 | 8894 | int using_gprs; |
252b5132 RH |
8895 | char *save_in; |
8896 | char *err; | |
8897 | unsigned char temp[8]; | |
8898 | int len; | |
8899 | unsigned int length; | |
8900 | segT seg; | |
8901 | subsegT subseg; | |
8902 | char *p; | |
8903 | ||
8904 | /* These only appear as the last operand in an | |
8905 | instruction, and every instruction that accepts | |
8906 | them in any variant accepts them in all variants. | |
8907 | This means we don't have to worry about backing out | |
8908 | any changes if the instruction does not match. | |
8909 | ||
8910 | The difference between them is the size of the | |
8911 | floating point constant and where it goes. For 'F' | |
8912 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8913 | is 32 bits. Where the constant is placed is based | |
8914 | on how the MIPS assembler does things: | |
8915 | F -- .rdata | |
8916 | L -- .lit8 | |
8917 | f -- immediate value | |
8918 | l -- .lit4 | |
8919 | ||
8920 | The .lit4 and .lit8 sections are only used if | |
8921 | permitted by the -G argument. | |
8922 | ||
8923 | When generating embedded PIC code, we use the | |
8924 | .lit8 section but not the .lit4 section (we can do | |
8925 | .lit4 inline easily; we need to put .lit8 | |
8926 | somewhere in the data segment, and using .lit8 | |
8927 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8928 | .lit8 entries). |
8929 | ||
8930 | The code below needs to know whether the target register | |
8931 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8932 | 'F' are used with GPR-based instructions and 'l' and | |
8933 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8934 | |
8935 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8936 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8937 | |
8938 | save_in = input_line_pointer; | |
8939 | input_line_pointer = s; | |
8940 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8941 | length = len; | |
8942 | s = input_line_pointer; | |
8943 | input_line_pointer = save_in; | |
8944 | if (err != NULL && *err != '\0') | |
8945 | { | |
8946 | as_bad (_("Bad floating point constant: %s"), err); | |
8947 | memset (temp, '\0', sizeof temp); | |
8948 | length = f64 ? 8 : 4; | |
8949 | } | |
8950 | ||
156c2f8b | 8951 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8952 | |
8953 | if (*args == 'f' | |
8954 | || (*args == 'l' | |
8955 | && (! USE_GLOBAL_POINTER_OPT | |
8956 | || mips_pic == EMBEDDED_PIC | |
8957 | || g_switch_value < 4 | |
8958 | || (temp[0] == 0 && temp[1] == 0) | |
8959 | || (temp[2] == 0 && temp[3] == 0)))) | |
8960 | { | |
8961 | imm_expr.X_op = O_constant; | |
8962 | if (! target_big_endian) | |
8963 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8964 | else | |
8965 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8966 | } | |
8967 | else if (length > 4 | |
119d663a | 8968 | && ! mips_disable_float_construction |
ca4e0257 RS |
8969 | /* Constants can only be constructed in GPRs and |
8970 | copied to FPRs if the GPRs are at least as wide | |
8971 | as the FPRs. Force the constant into memory if | |
8972 | we are using 64-bit FPRs but the GPRs are only | |
8973 | 32 bits wide. */ | |
8974 | && (using_gprs | |
8975 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8976 | && ((temp[0] == 0 && temp[1] == 0) |
8977 | || (temp[2] == 0 && temp[3] == 0)) | |
8978 | && ((temp[4] == 0 && temp[5] == 0) | |
8979 | || (temp[6] == 0 && temp[7] == 0))) | |
8980 | { | |
ca4e0257 RS |
8981 | /* The value is simple enough to load with a couple of |
8982 | instructions. If using 32-bit registers, set | |
8983 | imm_expr to the high order 32 bits and offset_expr to | |
8984 | the low order 32 bits. Otherwise, set imm_expr to | |
8985 | the entire 64 bit constant. */ | |
8986 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8987 | { |
8988 | imm_expr.X_op = O_constant; | |
8989 | offset_expr.X_op = O_constant; | |
8990 | if (! target_big_endian) | |
8991 | { | |
8992 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8993 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8994 | } | |
8995 | else | |
8996 | { | |
8997 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8998 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8999 | } | |
9000 | if (offset_expr.X_add_number == 0) | |
9001 | offset_expr.X_op = O_absent; | |
9002 | } | |
9003 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9004 | { | |
9005 | imm_expr.X_op = O_constant; | |
9006 | if (! target_big_endian) | |
9007 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9008 | else | |
9009 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9010 | } | |
9011 | else | |
9012 | { | |
9013 | imm_expr.X_op = O_big; | |
9014 | imm_expr.X_add_number = 4; | |
9015 | if (! target_big_endian) | |
9016 | { | |
9017 | generic_bignum[0] = bfd_getl16 (temp); | |
9018 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9019 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9020 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9021 | } | |
9022 | else | |
9023 | { | |
9024 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9025 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9026 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9027 | generic_bignum[3] = bfd_getb16 (temp); | |
9028 | } | |
9029 | } | |
9030 | } | |
9031 | else | |
9032 | { | |
9033 | const char *newname; | |
9034 | segT new_seg; | |
9035 | ||
9036 | /* Switch to the right section. */ | |
9037 | seg = now_seg; | |
9038 | subseg = now_subseg; | |
9039 | switch (*args) | |
9040 | { | |
9041 | default: /* unused default case avoids warnings. */ | |
9042 | case 'L': | |
9043 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
9044 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
9045 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
9046 | newname = ".lit8"; |
9047 | break; | |
9048 | case 'F': | |
bb2d6cd7 GK |
9049 | if (mips_pic == EMBEDDED_PIC) |
9050 | newname = ".lit8"; | |
9051 | else | |
9052 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
9053 | break; |
9054 | case 'l': | |
9055 | assert (!USE_GLOBAL_POINTER_OPT | |
9056 | || g_switch_value >= 4); | |
9057 | newname = ".lit4"; | |
9058 | break; | |
9059 | } | |
9060 | new_seg = subseg_new (newname, (subsegT) 0); | |
9061 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9062 | bfd_set_section_flags (stdoutput, new_seg, | |
9063 | (SEC_ALLOC | |
9064 | | SEC_LOAD | |
9065 | | SEC_READONLY | |
9066 | | SEC_DATA)); | |
9067 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9068 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9069 | && strcmp (TARGET_OS, "elf") != 0) | |
9070 | record_alignment (new_seg, 4); | |
9071 | else | |
9072 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9073 | if (seg == now_seg) | |
9074 | as_bad (_("Can't use floating point insn in this section")); | |
9075 | ||
9076 | /* Set the argument to the current address in the | |
9077 | section. */ | |
9078 | offset_expr.X_op = O_symbol; | |
9079 | offset_expr.X_add_symbol = | |
9080 | symbol_new ("L0\001", now_seg, | |
9081 | (valueT) frag_now_fix (), frag_now); | |
9082 | offset_expr.X_add_number = 0; | |
9083 | ||
9084 | /* Put the floating point number into the section. */ | |
9085 | p = frag_more ((int) length); | |
9086 | memcpy (p, temp, length); | |
9087 | ||
9088 | /* Switch back to the original section. */ | |
9089 | subseg_set (seg, subseg); | |
9090 | } | |
9091 | } | |
9092 | continue; | |
9093 | ||
9094 | case 'i': /* 16 bit unsigned immediate */ | |
9095 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9096 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9097 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9098 | { |
9099 | int more; | |
5e0116d5 RS |
9100 | offsetT minval, maxval; |
9101 | ||
9102 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9103 | && strcmp (insn->name, insn[1].name) == 0); | |
9104 | ||
9105 | /* If the expression was written as an unsigned number, | |
9106 | only treat it as signed if there are no more | |
9107 | alternatives. */ | |
9108 | if (more | |
9109 | && *args == 'j' | |
9110 | && sizeof (imm_expr.X_add_number) <= 4 | |
9111 | && imm_expr.X_op == O_constant | |
9112 | && imm_expr.X_add_number < 0 | |
9113 | && imm_expr.X_unsigned | |
9114 | && HAVE_64BIT_GPRS) | |
9115 | break; | |
9116 | ||
9117 | /* For compatibility with older assemblers, we accept | |
9118 | 0x8000-0xffff as signed 16-bit numbers when only | |
9119 | signed numbers are allowed. */ | |
9120 | if (*args == 'i') | |
9121 | minval = 0, maxval = 0xffff; | |
9122 | else if (more) | |
9123 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9124 | else |
5e0116d5 RS |
9125 | minval = -0x8000, maxval = 0xffff; |
9126 | ||
9127 | if (imm_expr.X_op != O_constant | |
9128 | || imm_expr.X_add_number < minval | |
9129 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9130 | { |
9131 | if (more) | |
9132 | break; | |
2ae7e77b AH |
9133 | if (imm_expr.X_op == O_constant |
9134 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9135 | as_bad (_("expression out of range")); |
252b5132 RH |
9136 | } |
9137 | } | |
9138 | s = expr_end; | |
9139 | continue; | |
9140 | ||
9141 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9142 | /* Check whether there is only a single bracketed expression |
9143 | left. If so, it must be the base register and the | |
9144 | constant must be zero. */ | |
9145 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9146 | { | |
9147 | offset_expr.X_op = O_constant; | |
9148 | offset_expr.X_add_number = 0; | |
9149 | continue; | |
9150 | } | |
252b5132 RH |
9151 | |
9152 | /* If this value won't fit into a 16 bit offset, then go | |
9153 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9154 | code pattern. */ |
5e0116d5 | 9155 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9156 | && (offset_expr.X_op != O_constant |
9157 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9158 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9159 | break; |
9160 | ||
252b5132 RH |
9161 | s = expr_end; |
9162 | continue; | |
9163 | ||
9164 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9165 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9166 | my_getExpression (&offset_expr, s); |
9167 | s = expr_end; | |
9168 | continue; | |
9169 | ||
9170 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9171 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9172 | && imm_expr.X_op == O_constant | |
9173 | && (imm_expr.X_add_number < 0 | |
9174 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9175 | as_bad (_("lui expression not in range 0..65535")); |
9176 | s = expr_end; | |
9177 | continue; | |
9178 | ||
9179 | case 'a': /* 26 bit address */ | |
9180 | my_getExpression (&offset_expr, s); | |
9181 | s = expr_end; | |
f6688943 | 9182 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9183 | continue; |
9184 | ||
9185 | case 'N': /* 3 bit branch condition code */ | |
9186 | case 'M': /* 3 bit compare condition code */ | |
9187 | if (strncmp (s, "$fcc", 4) != 0) | |
9188 | break; | |
9189 | s += 4; | |
9190 | regno = 0; | |
9191 | do | |
9192 | { | |
9193 | regno *= 10; | |
9194 | regno += *s - '0'; | |
9195 | ++s; | |
9196 | } | |
3882b010 | 9197 | while (ISDIGIT (*s)); |
252b5132 RH |
9198 | if (regno > 7) |
9199 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
9200 | if (*args == 'N') | |
9201 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9202 | else | |
9203 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9204 | continue; |
252b5132 | 9205 | |
156c2f8b NC |
9206 | case 'H': |
9207 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9208 | s += 2; | |
3882b010 | 9209 | if (ISDIGIT (*s)) |
156c2f8b NC |
9210 | { |
9211 | c = 0; | |
9212 | do | |
9213 | { | |
9214 | c *= 10; | |
9215 | c += *s - '0'; | |
9216 | ++s; | |
9217 | } | |
3882b010 | 9218 | while (ISDIGIT (*s)); |
156c2f8b NC |
9219 | } |
9220 | else | |
9221 | c = 8; /* Invalid sel value. */ | |
9222 | ||
9223 | if (c > 7) | |
9224 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9225 | ip->insn_opcode |= c; | |
9226 | continue; | |
9227 | ||
60b63b72 RS |
9228 | case 'e': |
9229 | /* Must be at least one digit. */ | |
9230 | my_getExpression (&imm_expr, s); | |
9231 | check_absolute_expr (ip, &imm_expr); | |
9232 | ||
9233 | if ((unsigned long) imm_expr.X_add_number | |
9234 | > (unsigned long) OP_MASK_VECBYTE) | |
9235 | { | |
9236 | as_bad (_("bad byte vector index (%ld)"), | |
9237 | (long) imm_expr.X_add_number); | |
9238 | imm_expr.X_add_number = 0; | |
9239 | } | |
9240 | ||
9241 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9242 | imm_expr.X_op = O_absent; | |
9243 | s = expr_end; | |
9244 | continue; | |
9245 | ||
9246 | case '%': | |
9247 | my_getExpression (&imm_expr, s); | |
9248 | check_absolute_expr (ip, &imm_expr); | |
9249 | ||
9250 | if ((unsigned long) imm_expr.X_add_number | |
9251 | > (unsigned long) OP_MASK_VECALIGN) | |
9252 | { | |
9253 | as_bad (_("bad byte vector index (%ld)"), | |
9254 | (long) imm_expr.X_add_number); | |
9255 | imm_expr.X_add_number = 0; | |
9256 | } | |
9257 | ||
9258 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9259 | imm_expr.X_op = O_absent; | |
9260 | s = expr_end; | |
9261 | continue; | |
9262 | ||
252b5132 RH |
9263 | default: |
9264 | as_bad (_("bad char = '%c'\n"), *args); | |
9265 | internalError (); | |
9266 | } | |
9267 | break; | |
9268 | } | |
9269 | /* Args don't match. */ | |
9270 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9271 | !strcmp (insn->name, insn[1].name)) | |
9272 | { | |
9273 | ++insn; | |
9274 | s = argsStart; | |
268f6bed | 9275 | insn_error = _("illegal operands"); |
252b5132 RH |
9276 | continue; |
9277 | } | |
268f6bed L |
9278 | if (save_c) |
9279 | *(--s) = save_c; | |
252b5132 RH |
9280 | insn_error = _("illegal operands"); |
9281 | return; | |
9282 | } | |
9283 | } | |
9284 | ||
9285 | /* This routine assembles an instruction into its binary format when | |
9286 | assembling for the mips16. As a side effect, it sets one of the | |
9287 | global variables imm_reloc or offset_reloc to the type of | |
9288 | relocation to do if one of the operands is an address expression. | |
9289 | It also sets mips16_small and mips16_ext if the user explicitly | |
9290 | requested a small or extended instruction. */ | |
9291 | ||
9292 | static void | |
17a2f251 | 9293 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9294 | { |
9295 | char *s; | |
9296 | const char *args; | |
9297 | struct mips_opcode *insn; | |
9298 | char *argsstart; | |
9299 | unsigned int regno; | |
9300 | unsigned int lastregno = 0; | |
9301 | char *s_reset; | |
9302 | ||
9303 | insn_error = NULL; | |
9304 | ||
b34976b6 AM |
9305 | mips16_small = FALSE; |
9306 | mips16_ext = FALSE; | |
252b5132 | 9307 | |
3882b010 | 9308 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9309 | ; |
9310 | switch (*s) | |
9311 | { | |
9312 | case '\0': | |
9313 | break; | |
9314 | ||
9315 | case ' ': | |
9316 | *s++ = '\0'; | |
9317 | break; | |
9318 | ||
9319 | case '.': | |
9320 | if (s[1] == 't' && s[2] == ' ') | |
9321 | { | |
9322 | *s = '\0'; | |
b34976b6 | 9323 | mips16_small = TRUE; |
252b5132 RH |
9324 | s += 3; |
9325 | break; | |
9326 | } | |
9327 | else if (s[1] == 'e' && s[2] == ' ') | |
9328 | { | |
9329 | *s = '\0'; | |
b34976b6 | 9330 | mips16_ext = TRUE; |
252b5132 RH |
9331 | s += 3; |
9332 | break; | |
9333 | } | |
9334 | /* Fall through. */ | |
9335 | default: | |
9336 | insn_error = _("unknown opcode"); | |
9337 | return; | |
9338 | } | |
9339 | ||
9340 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9341 | mips16_small = TRUE; |
252b5132 RH |
9342 | |
9343 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9344 | { | |
9345 | insn_error = _("unrecognized opcode"); | |
9346 | return; | |
9347 | } | |
9348 | ||
9349 | argsstart = s; | |
9350 | for (;;) | |
9351 | { | |
9352 | assert (strcmp (insn->name, str) == 0); | |
9353 | ||
9354 | ip->insn_mo = insn; | |
9355 | ip->insn_opcode = insn->match; | |
b34976b6 | 9356 | ip->use_extend = FALSE; |
252b5132 | 9357 | imm_expr.X_op = O_absent; |
f6688943 TS |
9358 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9359 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9360 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 9361 | offset_expr.X_op = O_absent; |
f6688943 TS |
9362 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9363 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9364 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9365 | for (args = insn->args; 1; ++args) |
9366 | { | |
9367 | int c; | |
9368 | ||
9369 | if (*s == ' ') | |
9370 | ++s; | |
9371 | ||
9372 | /* In this switch statement we call break if we did not find | |
9373 | a match, continue if we did find a match, or return if we | |
9374 | are done. */ | |
9375 | ||
9376 | c = *args; | |
9377 | switch (c) | |
9378 | { | |
9379 | case '\0': | |
9380 | if (*s == '\0') | |
9381 | { | |
9382 | /* Stuff the immediate value in now, if we can. */ | |
9383 | if (imm_expr.X_op == O_constant | |
f6688943 | 9384 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9385 | && insn->pinfo != INSN_MACRO) |
9386 | { | |
c4e7957c | 9387 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9388 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9389 | mips16_ext, &ip->insn_opcode, |
9390 | &ip->use_extend, &ip->extend); | |
9391 | imm_expr.X_op = O_absent; | |
f6688943 | 9392 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9393 | } |
9394 | ||
9395 | return; | |
9396 | } | |
9397 | break; | |
9398 | ||
9399 | case ',': | |
9400 | if (*s++ == c) | |
9401 | continue; | |
9402 | s--; | |
9403 | switch (*++args) | |
9404 | { | |
9405 | case 'v': | |
9406 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9407 | continue; | |
9408 | case 'w': | |
9409 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9410 | continue; | |
9411 | } | |
9412 | break; | |
9413 | ||
9414 | case '(': | |
9415 | case ')': | |
9416 | if (*s++ == c) | |
9417 | continue; | |
9418 | break; | |
9419 | ||
9420 | case 'v': | |
9421 | case 'w': | |
9422 | if (s[0] != '$') | |
9423 | { | |
9424 | if (c == 'v') | |
9425 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9426 | else | |
9427 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9428 | ++args; | |
9429 | continue; | |
9430 | } | |
9431 | /* Fall through. */ | |
9432 | case 'x': | |
9433 | case 'y': | |
9434 | case 'z': | |
9435 | case 'Z': | |
9436 | case '0': | |
9437 | case 'S': | |
9438 | case 'R': | |
9439 | case 'X': | |
9440 | case 'Y': | |
9441 | if (s[0] != '$') | |
9442 | break; | |
9443 | s_reset = s; | |
3882b010 | 9444 | if (ISDIGIT (s[1])) |
252b5132 RH |
9445 | { |
9446 | ++s; | |
9447 | regno = 0; | |
9448 | do | |
9449 | { | |
9450 | regno *= 10; | |
9451 | regno += *s - '0'; | |
9452 | ++s; | |
9453 | } | |
3882b010 | 9454 | while (ISDIGIT (*s)); |
252b5132 RH |
9455 | if (regno > 31) |
9456 | { | |
9457 | as_bad (_("invalid register number (%d)"), regno); | |
9458 | regno = 2; | |
9459 | } | |
9460 | } | |
9461 | else | |
9462 | { | |
76db943d TS |
9463 | if (s[1] == 'r' && s[2] == 'a') |
9464 | { | |
9465 | s += 3; | |
9466 | regno = RA; | |
9467 | } | |
9468 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9469 | { |
9470 | s += 3; | |
9471 | regno = FP; | |
9472 | } | |
9473 | else if (s[1] == 's' && s[2] == 'p') | |
9474 | { | |
9475 | s += 3; | |
9476 | regno = SP; | |
9477 | } | |
9478 | else if (s[1] == 'g' && s[2] == 'p') | |
9479 | { | |
9480 | s += 3; | |
9481 | regno = GP; | |
9482 | } | |
9483 | else if (s[1] == 'a' && s[2] == 't') | |
9484 | { | |
9485 | s += 3; | |
9486 | regno = AT; | |
9487 | } | |
9488 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9489 | { | |
9490 | s += 4; | |
9491 | regno = KT0; | |
9492 | } | |
9493 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9494 | { | |
9495 | s += 4; | |
9496 | regno = KT1; | |
9497 | } | |
85b51719 TS |
9498 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9499 | { | |
9500 | s += 5; | |
9501 | regno = ZERO; | |
9502 | } | |
252b5132 RH |
9503 | else |
9504 | break; | |
9505 | } | |
9506 | ||
9507 | if (*s == ' ') | |
9508 | ++s; | |
9509 | if (args[1] != *s) | |
9510 | { | |
9511 | if (c == 'v' || c == 'w') | |
9512 | { | |
9513 | regno = mips16_to_32_reg_map[lastregno]; | |
9514 | s = s_reset; | |
f9419b05 | 9515 | ++args; |
252b5132 RH |
9516 | } |
9517 | } | |
9518 | ||
9519 | switch (c) | |
9520 | { | |
9521 | case 'x': | |
9522 | case 'y': | |
9523 | case 'z': | |
9524 | case 'v': | |
9525 | case 'w': | |
9526 | case 'Z': | |
9527 | regno = mips32_to_16_reg_map[regno]; | |
9528 | break; | |
9529 | ||
9530 | case '0': | |
9531 | if (regno != 0) | |
9532 | regno = ILLEGAL_REG; | |
9533 | break; | |
9534 | ||
9535 | case 'S': | |
9536 | if (regno != SP) | |
9537 | regno = ILLEGAL_REG; | |
9538 | break; | |
9539 | ||
9540 | case 'R': | |
9541 | if (regno != RA) | |
9542 | regno = ILLEGAL_REG; | |
9543 | break; | |
9544 | ||
9545 | case 'X': | |
9546 | case 'Y': | |
9547 | if (regno == AT && ! mips_opts.noat) | |
9548 | as_warn (_("used $at without \".set noat\"")); | |
9549 | break; | |
9550 | ||
9551 | default: | |
9552 | internalError (); | |
9553 | } | |
9554 | ||
9555 | if (regno == ILLEGAL_REG) | |
9556 | break; | |
9557 | ||
9558 | switch (c) | |
9559 | { | |
9560 | case 'x': | |
9561 | case 'v': | |
9562 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9563 | break; | |
9564 | case 'y': | |
9565 | case 'w': | |
9566 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9567 | break; | |
9568 | case 'z': | |
9569 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9570 | break; | |
9571 | case 'Z': | |
9572 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9573 | case '0': | |
9574 | case 'S': | |
9575 | case 'R': | |
9576 | break; | |
9577 | case 'X': | |
9578 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9579 | break; | |
9580 | case 'Y': | |
9581 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9582 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9583 | break; | |
9584 | default: | |
9585 | internalError (); | |
9586 | } | |
9587 | ||
9588 | lastregno = regno; | |
9589 | continue; | |
9590 | ||
9591 | case 'P': | |
9592 | if (strncmp (s, "$pc", 3) == 0) | |
9593 | { | |
9594 | s += 3; | |
9595 | continue; | |
9596 | } | |
9597 | break; | |
9598 | ||
9599 | case '<': | |
9600 | case '>': | |
9601 | case '[': | |
9602 | case ']': | |
9603 | case '4': | |
9604 | case '5': | |
9605 | case 'H': | |
9606 | case 'W': | |
9607 | case 'D': | |
9608 | case 'j': | |
9609 | case '8': | |
9610 | case 'V': | |
9611 | case 'C': | |
9612 | case 'U': | |
9613 | case 'k': | |
9614 | case 'K': | |
9615 | if (s[0] == '%' | |
9616 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9617 | { | |
9618 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9619 | and generate the appropriate reloc. If the text | |
9620 | inside %gprel is not a symbol name with an | |
9621 | optional offset, then we generate a normal reloc | |
9622 | and will probably fail later. */ | |
9623 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9624 | if (imm_expr.X_op == O_symbol) | |
9625 | { | |
b34976b6 | 9626 | mips16_ext = TRUE; |
f6688943 | 9627 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9628 | s = expr_end; |
b34976b6 | 9629 | ip->use_extend = TRUE; |
252b5132 RH |
9630 | ip->extend = 0; |
9631 | continue; | |
9632 | } | |
9633 | } | |
9634 | else | |
9635 | { | |
9636 | /* Just pick up a normal expression. */ | |
9637 | my_getExpression (&imm_expr, s); | |
9638 | } | |
9639 | ||
9640 | if (imm_expr.X_op == O_register) | |
9641 | { | |
9642 | /* What we thought was an expression turned out to | |
9643 | be a register. */ | |
9644 | ||
9645 | if (s[0] == '(' && args[1] == '(') | |
9646 | { | |
9647 | /* It looks like the expression was omitted | |
9648 | before a register indirection, which means | |
9649 | that the expression is implicitly zero. We | |
9650 | still set up imm_expr, so that we handle | |
9651 | explicit extensions correctly. */ | |
9652 | imm_expr.X_op = O_constant; | |
9653 | imm_expr.X_add_number = 0; | |
f6688943 | 9654 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9655 | continue; |
9656 | } | |
9657 | ||
9658 | break; | |
9659 | } | |
9660 | ||
9661 | /* We need to relax this instruction. */ | |
f6688943 | 9662 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9663 | s = expr_end; |
9664 | continue; | |
9665 | ||
9666 | case 'p': | |
9667 | case 'q': | |
9668 | case 'A': | |
9669 | case 'B': | |
9670 | case 'E': | |
9671 | /* We use offset_reloc rather than imm_reloc for the PC | |
9672 | relative operands. This lets macros with both | |
9673 | immediate and address operands work correctly. */ | |
9674 | my_getExpression (&offset_expr, s); | |
9675 | ||
9676 | if (offset_expr.X_op == O_register) | |
9677 | break; | |
9678 | ||
9679 | /* We need to relax this instruction. */ | |
f6688943 | 9680 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9681 | s = expr_end; |
9682 | continue; | |
9683 | ||
9684 | case '6': /* break code */ | |
9685 | my_getExpression (&imm_expr, s); | |
9686 | check_absolute_expr (ip, &imm_expr); | |
9687 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9688 | { | |
9689 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9690 | ip->insn_mo->name, | |
9691 | (unsigned long) imm_expr.X_add_number); | |
9692 | imm_expr.X_add_number &= 0x3f; | |
9693 | } | |
9694 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9695 | imm_expr.X_op = O_absent; | |
9696 | s = expr_end; | |
9697 | continue; | |
9698 | ||
9699 | case 'a': /* 26 bit address */ | |
9700 | my_getExpression (&offset_expr, s); | |
9701 | s = expr_end; | |
f6688943 | 9702 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9703 | ip->insn_opcode <<= 16; |
9704 | continue; | |
9705 | ||
9706 | case 'l': /* register list for entry macro */ | |
9707 | case 'L': /* register list for exit macro */ | |
9708 | { | |
9709 | int mask; | |
9710 | ||
9711 | if (c == 'l') | |
9712 | mask = 0; | |
9713 | else | |
9714 | mask = 7 << 3; | |
9715 | while (*s != '\0') | |
9716 | { | |
9717 | int freg, reg1, reg2; | |
9718 | ||
9719 | while (*s == ' ' || *s == ',') | |
9720 | ++s; | |
9721 | if (*s != '$') | |
9722 | { | |
9723 | as_bad (_("can't parse register list")); | |
9724 | break; | |
9725 | } | |
9726 | ++s; | |
9727 | if (*s != 'f') | |
9728 | freg = 0; | |
9729 | else | |
9730 | { | |
9731 | freg = 1; | |
9732 | ++s; | |
9733 | } | |
9734 | reg1 = 0; | |
3882b010 | 9735 | while (ISDIGIT (*s)) |
252b5132 RH |
9736 | { |
9737 | reg1 *= 10; | |
9738 | reg1 += *s - '0'; | |
9739 | ++s; | |
9740 | } | |
9741 | if (*s == ' ') | |
9742 | ++s; | |
9743 | if (*s != '-') | |
9744 | reg2 = reg1; | |
9745 | else | |
9746 | { | |
9747 | ++s; | |
9748 | if (*s != '$') | |
9749 | break; | |
9750 | ++s; | |
9751 | if (freg) | |
9752 | { | |
9753 | if (*s == 'f') | |
9754 | ++s; | |
9755 | else | |
9756 | { | |
9757 | as_bad (_("invalid register list")); | |
9758 | break; | |
9759 | } | |
9760 | } | |
9761 | reg2 = 0; | |
3882b010 | 9762 | while (ISDIGIT (*s)) |
252b5132 RH |
9763 | { |
9764 | reg2 *= 10; | |
9765 | reg2 += *s - '0'; | |
9766 | ++s; | |
9767 | } | |
9768 | } | |
9769 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9770 | { | |
9771 | mask &= ~ (7 << 3); | |
9772 | mask |= 5 << 3; | |
9773 | } | |
9774 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9775 | { | |
9776 | mask &= ~ (7 << 3); | |
9777 | mask |= 6 << 3; | |
9778 | } | |
9779 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9780 | mask |= (reg2 - 3) << 3; | |
9781 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9782 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9783 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9784 | mask |= 1; |
9785 | else | |
9786 | { | |
9787 | as_bad (_("invalid register list")); | |
9788 | break; | |
9789 | } | |
9790 | } | |
9791 | /* The mask is filled in in the opcode table for the | |
9792 | benefit of the disassembler. We remove it before | |
9793 | applying the actual mask. */ | |
9794 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9795 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9796 | } | |
9797 | continue; | |
9798 | ||
9799 | case 'e': /* extend code */ | |
9800 | my_getExpression (&imm_expr, s); | |
9801 | check_absolute_expr (ip, &imm_expr); | |
9802 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9803 | { | |
9804 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9805 | ip->insn_mo->name, | |
9806 | (unsigned long) imm_expr.X_add_number); | |
9807 | imm_expr.X_add_number &= 0x7ff; | |
9808 | } | |
9809 | ip->insn_opcode |= imm_expr.X_add_number; | |
9810 | imm_expr.X_op = O_absent; | |
9811 | s = expr_end; | |
9812 | continue; | |
9813 | ||
9814 | default: | |
9815 | internalError (); | |
9816 | } | |
9817 | break; | |
9818 | } | |
9819 | ||
9820 | /* Args don't match. */ | |
9821 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9822 | strcmp (insn->name, insn[1].name) == 0) | |
9823 | { | |
9824 | ++insn; | |
9825 | s = argsstart; | |
9826 | continue; | |
9827 | } | |
9828 | ||
9829 | insn_error = _("illegal operands"); | |
9830 | ||
9831 | return; | |
9832 | } | |
9833 | } | |
9834 | ||
9835 | /* This structure holds information we know about a mips16 immediate | |
9836 | argument type. */ | |
9837 | ||
e972090a NC |
9838 | struct mips16_immed_operand |
9839 | { | |
252b5132 RH |
9840 | /* The type code used in the argument string in the opcode table. */ |
9841 | int type; | |
9842 | /* The number of bits in the short form of the opcode. */ | |
9843 | int nbits; | |
9844 | /* The number of bits in the extended form of the opcode. */ | |
9845 | int extbits; | |
9846 | /* The amount by which the short form is shifted when it is used; | |
9847 | for example, the sw instruction has a shift count of 2. */ | |
9848 | int shift; | |
9849 | /* The amount by which the short form is shifted when it is stored | |
9850 | into the instruction code. */ | |
9851 | int op_shift; | |
9852 | /* Non-zero if the short form is unsigned. */ | |
9853 | int unsp; | |
9854 | /* Non-zero if the extended form is unsigned. */ | |
9855 | int extu; | |
9856 | /* Non-zero if the value is PC relative. */ | |
9857 | int pcrel; | |
9858 | }; | |
9859 | ||
9860 | /* The mips16 immediate operand types. */ | |
9861 | ||
9862 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9863 | { | |
9864 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9865 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9866 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9867 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9868 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9869 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9870 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9871 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9872 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9873 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9874 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9875 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9876 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9877 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9878 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9879 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9880 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9881 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9882 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9883 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9884 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9885 | }; | |
9886 | ||
9887 | #define MIPS16_NUM_IMMED \ | |
9888 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9889 | ||
9890 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9891 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9892 | whether an extended value is needed; if one is needed, it sets | |
9893 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9894 | If SMALL is true, an unextended opcode was explicitly requested. | |
9895 | If EXT is true, an extended opcode was explicitly requested. If | |
9896 | WARN is true, warn if EXT does not match reality. */ | |
9897 | ||
9898 | static void | |
17a2f251 TS |
9899 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9900 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9901 | unsigned long *insn, bfd_boolean *use_extend, | |
9902 | unsigned short *extend) | |
252b5132 RH |
9903 | { |
9904 | register const struct mips16_immed_operand *op; | |
9905 | int mintiny, maxtiny; | |
b34976b6 | 9906 | bfd_boolean needext; |
252b5132 RH |
9907 | |
9908 | op = mips16_immed_operands; | |
9909 | while (op->type != type) | |
9910 | { | |
9911 | ++op; | |
9912 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9913 | } | |
9914 | ||
9915 | if (op->unsp) | |
9916 | { | |
9917 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9918 | { | |
9919 | mintiny = 1; | |
9920 | maxtiny = 1 << op->nbits; | |
9921 | } | |
9922 | else | |
9923 | { | |
9924 | mintiny = 0; | |
9925 | maxtiny = (1 << op->nbits) - 1; | |
9926 | } | |
9927 | } | |
9928 | else | |
9929 | { | |
9930 | mintiny = - (1 << (op->nbits - 1)); | |
9931 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9932 | } | |
9933 | ||
9934 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9935 | if (type == 'p' || type == 'q') | |
9936 | val /= 2; | |
9937 | ||
9938 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9939 | || val < (mintiny << op->shift) | |
9940 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9941 | needext = TRUE; |
252b5132 | 9942 | else |
b34976b6 | 9943 | needext = FALSE; |
252b5132 RH |
9944 | |
9945 | if (warn && ext && ! needext) | |
beae10d5 KH |
9946 | as_warn_where (file, line, |
9947 | _("extended operand requested but not required")); | |
252b5132 RH |
9948 | if (small && needext) |
9949 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9950 | ||
9951 | if (small || (! ext && ! needext)) | |
9952 | { | |
9953 | int insnval; | |
9954 | ||
b34976b6 | 9955 | *use_extend = FALSE; |
252b5132 RH |
9956 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9957 | insnval <<= op->op_shift; | |
9958 | *insn |= insnval; | |
9959 | } | |
9960 | else | |
9961 | { | |
9962 | long minext, maxext; | |
9963 | int extval; | |
9964 | ||
9965 | if (op->extu) | |
9966 | { | |
9967 | minext = 0; | |
9968 | maxext = (1 << op->extbits) - 1; | |
9969 | } | |
9970 | else | |
9971 | { | |
9972 | minext = - (1 << (op->extbits - 1)); | |
9973 | maxext = (1 << (op->extbits - 1)) - 1; | |
9974 | } | |
9975 | if (val < minext || val > maxext) | |
9976 | as_bad_where (file, line, | |
9977 | _("operand value out of range for instruction")); | |
9978 | ||
b34976b6 | 9979 | *use_extend = TRUE; |
252b5132 RH |
9980 | if (op->extbits == 16) |
9981 | { | |
9982 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9983 | val &= 0x1f; | |
9984 | } | |
9985 | else if (op->extbits == 15) | |
9986 | { | |
9987 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9988 | val &= 0xf; | |
9989 | } | |
9990 | else | |
9991 | { | |
9992 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9993 | val = 0; | |
9994 | } | |
9995 | ||
9996 | *extend = (unsigned short) extval; | |
9997 | *insn |= val; | |
9998 | } | |
9999 | } | |
10000 | \f | |
5e0116d5 | 10001 | static const struct percent_op_match |
ad8d3bb3 | 10002 | { |
5e0116d5 RS |
10003 | const char *str; |
10004 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
10005 | } percent_op[] = |
10006 | { | |
5e0116d5 | 10007 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10008 | #ifdef OBJ_ELF |
5e0116d5 RS |
10009 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10010 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10011 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10012 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10013 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10014 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10015 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10016 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10017 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10018 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10019 | {"%half", BFD_RELOC_16}, | |
10020 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10021 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10022 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 10023 | #endif |
5e0116d5 | 10024 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10025 | }; |
10026 | ||
252b5132 | 10027 | |
5e0116d5 RS |
10028 | /* Return true if *STR points to a relocation operator. When returning true, |
10029 | move *STR over the operator and store its relocation code in *RELOC. | |
10030 | Leave both *STR and *RELOC alone when returning false. */ | |
10031 | ||
10032 | static bfd_boolean | |
17a2f251 | 10033 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10034 | { |
5e0116d5 | 10035 | size_t i; |
76b3015f | 10036 | |
5e0116d5 RS |
10037 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
10038 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 10039 | { |
5e0116d5 RS |
10040 | *str += strlen (percent_op[i].str); |
10041 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10042 | |
5e0116d5 RS |
10043 | /* Check whether the output BFD supports this relocation. |
10044 | If not, issue an error and fall back on something safe. */ | |
10045 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10046 | { |
5e0116d5 RS |
10047 | as_bad ("relocation %s isn't supported by the current ABI", |
10048 | percent_op[i].str); | |
10049 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 10050 | } |
5e0116d5 | 10051 | return TRUE; |
394f9b3a | 10052 | } |
5e0116d5 | 10053 | return FALSE; |
394f9b3a | 10054 | } |
ad8d3bb3 | 10055 | |
ad8d3bb3 | 10056 | |
5e0116d5 RS |
10057 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10058 | expression in *EP and the relocations in the array starting | |
10059 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10060 | |
5e0116d5 RS |
10061 | On exit, EXPR_END points to the first character after the expression. |
10062 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 10063 | |
5e0116d5 | 10064 | static size_t |
17a2f251 TS |
10065 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10066 | char *str) | |
ad8d3bb3 | 10067 | { |
5e0116d5 RS |
10068 | bfd_reloc_code_real_type reversed_reloc[3]; |
10069 | size_t reloc_index, i; | |
09b8f35a RS |
10070 | int crux_depth, str_depth; |
10071 | char *crux; | |
5e0116d5 RS |
10072 | |
10073 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10074 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10075 | of the main expression and with CRUX_DEPTH containing the number | |
10076 | of open brackets at that point. */ | |
10077 | reloc_index = -1; | |
10078 | str_depth = 0; | |
10079 | do | |
fb1b3232 | 10080 | { |
09b8f35a RS |
10081 | reloc_index++; |
10082 | crux = str; | |
10083 | crux_depth = str_depth; | |
10084 | ||
10085 | /* Skip over whitespace and brackets, keeping count of the number | |
10086 | of brackets. */ | |
10087 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10088 | if (*str++ == '(') | |
10089 | str_depth++; | |
5e0116d5 | 10090 | } |
09b8f35a RS |
10091 | while (*str == '%' |
10092 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10093 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10094 | |
09b8f35a | 10095 | my_getExpression (ep, crux); |
5e0116d5 | 10096 | str = expr_end; |
394f9b3a | 10097 | |
5e0116d5 | 10098 | /* Match every open bracket. */ |
09b8f35a | 10099 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10100 | if (*str++ == ')') |
09b8f35a | 10101 | crux_depth--; |
394f9b3a | 10102 | |
09b8f35a | 10103 | if (crux_depth > 0) |
5e0116d5 | 10104 | as_bad ("unclosed '('"); |
394f9b3a | 10105 | |
5e0116d5 | 10106 | expr_end = str; |
252b5132 | 10107 | |
64bdfcaf RS |
10108 | if (reloc_index == 0) |
10109 | reloc[0] = BFD_RELOC_LO16; | |
10110 | else | |
10111 | { | |
10112 | prev_reloc_op_frag = frag_now; | |
10113 | for (i = 0; i < reloc_index; i++) | |
10114 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10115 | } | |
fb1b3232 | 10116 | |
5e0116d5 | 10117 | return reloc_index; |
252b5132 RH |
10118 | } |
10119 | ||
10120 | static void | |
17a2f251 | 10121 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10122 | { |
10123 | char *save_in; | |
98aa84af | 10124 | valueT val; |
252b5132 RH |
10125 | |
10126 | save_in = input_line_pointer; | |
10127 | input_line_pointer = str; | |
10128 | expression (ep); | |
10129 | expr_end = input_line_pointer; | |
10130 | input_line_pointer = save_in; | |
10131 | ||
10132 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10133 | then we bump the value of the symbol by 1 since that is how other | |
10134 | text symbols are handled. We don't bother to handle complex | |
10135 | expressions, just `.' plus or minus a constant. */ | |
10136 | if (mips_opts.mips16 | |
10137 | && ep->X_op == O_symbol | |
10138 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10139 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10140 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10141 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10142 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10143 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10144 | } |
10145 | ||
10146 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10147 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10148 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10149 | returned, or NULL on OK. */ |
10150 | ||
10151 | char * | |
17a2f251 | 10152 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10153 | { |
10154 | int prec; | |
10155 | LITTLENUM_TYPE words[4]; | |
10156 | char *t; | |
10157 | int i; | |
10158 | ||
10159 | switch (type) | |
10160 | { | |
10161 | case 'f': | |
10162 | prec = 2; | |
10163 | break; | |
10164 | ||
10165 | case 'd': | |
10166 | prec = 4; | |
10167 | break; | |
10168 | ||
10169 | default: | |
10170 | *sizeP = 0; | |
10171 | return _("bad call to md_atof"); | |
10172 | } | |
10173 | ||
10174 | t = atof_ieee (input_line_pointer, type, words); | |
10175 | if (t) | |
10176 | input_line_pointer = t; | |
10177 | ||
10178 | *sizeP = prec * 2; | |
10179 | ||
10180 | if (! target_big_endian) | |
10181 | { | |
10182 | for (i = prec - 1; i >= 0; i--) | |
10183 | { | |
17a2f251 | 10184 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10185 | litP += 2; |
10186 | } | |
10187 | } | |
10188 | else | |
10189 | { | |
10190 | for (i = 0; i < prec; i++) | |
10191 | { | |
17a2f251 | 10192 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10193 | litP += 2; |
10194 | } | |
10195 | } | |
bdaaa2e1 | 10196 | |
252b5132 RH |
10197 | return NULL; |
10198 | } | |
10199 | ||
10200 | void | |
17a2f251 | 10201 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10202 | { |
10203 | if (target_big_endian) | |
10204 | number_to_chars_bigendian (buf, val, n); | |
10205 | else | |
10206 | number_to_chars_littleendian (buf, val, n); | |
10207 | } | |
10208 | \f | |
ae948b86 | 10209 | #ifdef OBJ_ELF |
e013f690 TS |
10210 | static int support_64bit_objects(void) |
10211 | { | |
10212 | const char **list, **l; | |
aa3d8fdf | 10213 | int yes; |
e013f690 TS |
10214 | |
10215 | list = bfd_target_list (); | |
10216 | for (l = list; *l != NULL; l++) | |
10217 | #ifdef TE_TMIPS | |
10218 | /* This is traditional mips */ | |
10219 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10220 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10221 | #else | |
10222 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10223 | || strcmp (*l, "elf64-littlemips") == 0) | |
10224 | #endif | |
10225 | break; | |
aa3d8fdf | 10226 | yes = (*l != NULL); |
e013f690 | 10227 | free (list); |
aa3d8fdf | 10228 | return yes; |
e013f690 | 10229 | } |
ae948b86 | 10230 | #endif /* OBJ_ELF */ |
e013f690 | 10231 | |
5a38dc70 | 10232 | const char *md_shortopts = "nO::g::G:"; |
252b5132 | 10233 | |
e972090a NC |
10234 | struct option md_longopts[] = |
10235 | { | |
f9b4148d CD |
10236 | /* Options which specify architecture. */ |
10237 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10238 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10239 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10240 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10241 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10242 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10243 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10244 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10245 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10246 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10247 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10248 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10249 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10250 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10251 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10252 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10253 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10254 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10255 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10256 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10257 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10258 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
10259 | ||
10260 | /* Options which specify Application Specific Extensions (ASEs). */ | |
10261 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10) | |
10262 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) | |
10263 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10264 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10265 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10266 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10267 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10268 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10269 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10270 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10271 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10272 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10273 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10274 | ||
10275 | /* Old-style architecture options. Don't add more of these. */ | |
10276 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10277 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10278 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10279 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10280 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10281 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10282 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10283 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10284 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10285 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10286 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10287 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10288 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10289 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10290 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10291 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10292 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10293 | ||
10294 | /* Options which enable bug fixes. */ | |
10295 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10296 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10297 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10298 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10299 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10300 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10301 | #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2) | |
10302 | #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3) | |
10303 | {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, | |
10304 | {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, | |
10305 | ||
10306 | /* Miscellaneous options. */ | |
10307 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
10308 | #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) | |
252b5132 | 10309 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
f9b4148d | 10310 | #define OPTION_TRAP (OPTION_MISC_BASE + 1) |
252b5132 RH |
10311 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10312 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
f9b4148d | 10313 | #define OPTION_BREAK (OPTION_MISC_BASE + 2) |
252b5132 RH |
10314 | {"break", no_argument, NULL, OPTION_BREAK}, |
10315 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
f9b4148d | 10316 | #define OPTION_EB (OPTION_MISC_BASE + 3) |
252b5132 | 10317 | {"EB", no_argument, NULL, OPTION_EB}, |
f9b4148d | 10318 | #define OPTION_EL (OPTION_MISC_BASE + 4) |
252b5132 | 10319 | {"EL", no_argument, NULL, OPTION_EL}, |
f9b4148d | 10320 | #define OPTION_FP32 (OPTION_MISC_BASE + 5) |
ae948b86 | 10321 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
f9b4148d | 10322 | #define OPTION_GP32 (OPTION_MISC_BASE + 6) |
c97ef257 | 10323 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
f9b4148d | 10324 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10325 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
f9b4148d | 10326 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) |
119d663a | 10327 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
f9b4148d | 10328 | #define OPTION_FP64 (OPTION_MISC_BASE + 9) |
316f5878 | 10329 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
f9b4148d | 10330 | #define OPTION_GP64 (OPTION_MISC_BASE + 10) |
ae948b86 | 10331 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
f9b4148d CD |
10332 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) |
10333 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) | |
4a6a3df4 AO |
10334 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10335 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10336 | |
10337 | /* ELF-specific options. */ | |
156c2f8b | 10338 | #ifdef OBJ_ELF |
f9b4148d | 10339 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) |
156c2f8b | 10340 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10341 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10342 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10343 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10344 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10345 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10346 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10347 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10348 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10349 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10350 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10351 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10352 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10353 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10354 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10355 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10356 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10357 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10358 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10359 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10360 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10361 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10362 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10363 | #endif /* OBJ_ELF */ |
f9b4148d | 10364 | |
252b5132 RH |
10365 | {NULL, no_argument, NULL, 0} |
10366 | }; | |
156c2f8b | 10367 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10368 | |
316f5878 RS |
10369 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10370 | NEW_VALUE. Warn if another value was already specified. Note: | |
10371 | we have to defer parsing the -march and -mtune arguments in order | |
10372 | to handle 'from-abi' correctly, since the ABI might be specified | |
10373 | in a later argument. */ | |
10374 | ||
10375 | static void | |
17a2f251 | 10376 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10377 | { |
10378 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10379 | as_warn (_("A different %s was already specified, is now %s"), | |
10380 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10381 | new_value); | |
10382 | ||
10383 | *string_ptr = new_value; | |
10384 | } | |
10385 | ||
252b5132 | 10386 | int |
17a2f251 | 10387 | md_parse_option (int c, char *arg) |
252b5132 RH |
10388 | { |
10389 | switch (c) | |
10390 | { | |
119d663a NC |
10391 | case OPTION_CONSTRUCT_FLOATS: |
10392 | mips_disable_float_construction = 0; | |
10393 | break; | |
bdaaa2e1 | 10394 | |
119d663a NC |
10395 | case OPTION_NO_CONSTRUCT_FLOATS: |
10396 | mips_disable_float_construction = 1; | |
10397 | break; | |
bdaaa2e1 | 10398 | |
252b5132 RH |
10399 | case OPTION_TRAP: |
10400 | mips_trap = 1; | |
10401 | break; | |
10402 | ||
10403 | case OPTION_BREAK: | |
10404 | mips_trap = 0; | |
10405 | break; | |
10406 | ||
10407 | case OPTION_EB: | |
10408 | target_big_endian = 1; | |
10409 | break; | |
10410 | ||
10411 | case OPTION_EL: | |
10412 | target_big_endian = 0; | |
10413 | break; | |
10414 | ||
39c0a331 L |
10415 | case 'n': |
10416 | warn_nops = 1; | |
10417 | break; | |
10418 | ||
252b5132 RH |
10419 | case 'O': |
10420 | if (arg && arg[1] == '0') | |
10421 | mips_optimize = 1; | |
10422 | else | |
10423 | mips_optimize = 2; | |
10424 | break; | |
10425 | ||
10426 | case 'g': | |
10427 | if (arg == NULL) | |
10428 | mips_debug = 2; | |
10429 | else | |
10430 | mips_debug = atoi (arg); | |
10431 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10432 | optimizations which limit full symbolic debugging. We take | |
10433 | that to be equivalent to -O0. */ | |
10434 | if (mips_debug == 2) | |
10435 | mips_optimize = 1; | |
10436 | break; | |
10437 | ||
10438 | case OPTION_MIPS1: | |
316f5878 | 10439 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10440 | break; |
10441 | ||
10442 | case OPTION_MIPS2: | |
316f5878 | 10443 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10444 | break; |
10445 | ||
10446 | case OPTION_MIPS3: | |
316f5878 | 10447 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10448 | break; |
10449 | ||
10450 | case OPTION_MIPS4: | |
316f5878 | 10451 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10452 | break; |
10453 | ||
84ea6cf2 | 10454 | case OPTION_MIPS5: |
316f5878 | 10455 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10456 | break; |
10457 | ||
e7af610e | 10458 | case OPTION_MIPS32: |
316f5878 | 10459 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10460 | break; |
10461 | ||
af7ee8bf CD |
10462 | case OPTION_MIPS32R2: |
10463 | file_mips_isa = ISA_MIPS32R2; | |
10464 | break; | |
10465 | ||
84ea6cf2 | 10466 | case OPTION_MIPS64: |
316f5878 | 10467 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10468 | break; |
10469 | ||
ec68c924 | 10470 | case OPTION_MTUNE: |
316f5878 RS |
10471 | mips_set_option_string (&mips_tune_string, arg); |
10472 | break; | |
ec68c924 | 10473 | |
316f5878 RS |
10474 | case OPTION_MARCH: |
10475 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10476 | break; |
10477 | ||
10478 | case OPTION_M4650: | |
316f5878 RS |
10479 | mips_set_option_string (&mips_arch_string, "4650"); |
10480 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10481 | break; |
10482 | ||
10483 | case OPTION_NO_M4650: | |
10484 | break; | |
10485 | ||
10486 | case OPTION_M4010: | |
316f5878 RS |
10487 | mips_set_option_string (&mips_arch_string, "4010"); |
10488 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10489 | break; |
10490 | ||
10491 | case OPTION_NO_M4010: | |
10492 | break; | |
10493 | ||
10494 | case OPTION_M4100: | |
316f5878 RS |
10495 | mips_set_option_string (&mips_arch_string, "4100"); |
10496 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10497 | break; |
10498 | ||
10499 | case OPTION_NO_M4100: | |
10500 | break; | |
10501 | ||
252b5132 | 10502 | case OPTION_M3900: |
316f5878 RS |
10503 | mips_set_option_string (&mips_arch_string, "3900"); |
10504 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10505 | break; |
bdaaa2e1 | 10506 | |
252b5132 RH |
10507 | case OPTION_NO_M3900: |
10508 | break; | |
10509 | ||
deec1734 CD |
10510 | case OPTION_MDMX: |
10511 | mips_opts.ase_mdmx = 1; | |
10512 | break; | |
10513 | ||
10514 | case OPTION_NO_MDMX: | |
10515 | mips_opts.ase_mdmx = 0; | |
10516 | break; | |
10517 | ||
252b5132 RH |
10518 | case OPTION_MIPS16: |
10519 | mips_opts.mips16 = 1; | |
b34976b6 | 10520 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10521 | break; |
10522 | ||
10523 | case OPTION_NO_MIPS16: | |
10524 | mips_opts.mips16 = 0; | |
b34976b6 | 10525 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10526 | break; |
10527 | ||
1f25f5d3 CD |
10528 | case OPTION_MIPS3D: |
10529 | mips_opts.ase_mips3d = 1; | |
10530 | break; | |
10531 | ||
10532 | case OPTION_NO_MIPS3D: | |
10533 | mips_opts.ase_mips3d = 0; | |
10534 | break; | |
10535 | ||
252b5132 RH |
10536 | case OPTION_MEMBEDDED_PIC: |
10537 | mips_pic = EMBEDDED_PIC; | |
10538 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10539 | { | |
10540 | as_bad (_("-G may not be used with embedded PIC code")); | |
10541 | return 0; | |
10542 | } | |
10543 | g_switch_value = 0x7fffffff; | |
10544 | break; | |
10545 | ||
60b63b72 RS |
10546 | case OPTION_FIX_VR4122: |
10547 | mips_fix_4122_bugs = 1; | |
10548 | break; | |
10549 | ||
10550 | case OPTION_NO_FIX_VR4122: | |
10551 | mips_fix_4122_bugs = 0; | |
10552 | break; | |
10553 | ||
4a6a3df4 AO |
10554 | case OPTION_RELAX_BRANCH: |
10555 | mips_relax_branch = 1; | |
10556 | break; | |
10557 | ||
10558 | case OPTION_NO_RELAX_BRANCH: | |
10559 | mips_relax_branch = 0; | |
10560 | break; | |
10561 | ||
0f074f60 | 10562 | #ifdef OBJ_ELF |
252b5132 RH |
10563 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10564 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10565 | intended to be compatible with Irix 5. */ | |
10566 | case OPTION_CALL_SHARED: | |
10567 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10568 | { | |
10569 | as_bad (_("-call_shared is supported only for ELF format")); | |
10570 | return 0; | |
10571 | } | |
10572 | mips_pic = SVR4_PIC; | |
143d77c5 | 10573 | mips_abicalls = TRUE; |
252b5132 RH |
10574 | if (g_switch_seen && g_switch_value != 0) |
10575 | { | |
10576 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10577 | return 0; | |
10578 | } | |
10579 | g_switch_value = 0; | |
10580 | break; | |
10581 | ||
10582 | case OPTION_NON_SHARED: | |
10583 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10584 | { | |
10585 | as_bad (_("-non_shared is supported only for ELF format")); | |
10586 | return 0; | |
10587 | } | |
10588 | mips_pic = NO_PIC; | |
143d77c5 | 10589 | mips_abicalls = FALSE; |
252b5132 RH |
10590 | break; |
10591 | ||
10592 | /* The -xgot option tells the assembler to use 32 offsets when | |
10593 | accessing the got in SVR4_PIC mode. It is for Irix | |
10594 | compatibility. */ | |
10595 | case OPTION_XGOT: | |
10596 | mips_big_got = 1; | |
10597 | break; | |
0f074f60 | 10598 | #endif /* OBJ_ELF */ |
252b5132 RH |
10599 | |
10600 | case 'G': | |
10601 | if (! USE_GLOBAL_POINTER_OPT) | |
10602 | { | |
10603 | as_bad (_("-G is not supported for this configuration")); | |
10604 | return 0; | |
10605 | } | |
10606 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10607 | { | |
10608 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10609 | return 0; | |
10610 | } | |
10611 | else | |
10612 | g_switch_value = atoi (arg); | |
10613 | g_switch_seen = 1; | |
10614 | break; | |
10615 | ||
0f074f60 | 10616 | #ifdef OBJ_ELF |
34ba82a8 TS |
10617 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10618 | and -mabi=64. */ | |
252b5132 | 10619 | case OPTION_32: |
34ba82a8 TS |
10620 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10621 | { | |
10622 | as_bad (_("-32 is supported for ELF format only")); | |
10623 | return 0; | |
10624 | } | |
316f5878 | 10625 | mips_abi = O32_ABI; |
252b5132 RH |
10626 | break; |
10627 | ||
e013f690 | 10628 | case OPTION_N32: |
34ba82a8 TS |
10629 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10630 | { | |
10631 | as_bad (_("-n32 is supported for ELF format only")); | |
10632 | return 0; | |
10633 | } | |
316f5878 | 10634 | mips_abi = N32_ABI; |
e013f690 | 10635 | break; |
252b5132 | 10636 | |
e013f690 | 10637 | case OPTION_64: |
34ba82a8 TS |
10638 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10639 | { | |
10640 | as_bad (_("-64 is supported for ELF format only")); | |
10641 | return 0; | |
10642 | } | |
316f5878 | 10643 | mips_abi = N64_ABI; |
e013f690 TS |
10644 | if (! support_64bit_objects()) |
10645 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10646 | break; |
ae948b86 | 10647 | #endif /* OBJ_ELF */ |
252b5132 | 10648 | |
c97ef257 | 10649 | case OPTION_GP32: |
a325df1d | 10650 | file_mips_gp32 = 1; |
c97ef257 AH |
10651 | break; |
10652 | ||
10653 | case OPTION_GP64: | |
a325df1d | 10654 | file_mips_gp32 = 0; |
c97ef257 | 10655 | break; |
252b5132 | 10656 | |
ca4e0257 | 10657 | case OPTION_FP32: |
a325df1d | 10658 | file_mips_fp32 = 1; |
316f5878 RS |
10659 | break; |
10660 | ||
10661 | case OPTION_FP64: | |
10662 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10663 | break; |
10664 | ||
ae948b86 | 10665 | #ifdef OBJ_ELF |
252b5132 | 10666 | case OPTION_MABI: |
34ba82a8 TS |
10667 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10668 | { | |
10669 | as_bad (_("-mabi is supported for ELF format only")); | |
10670 | return 0; | |
10671 | } | |
e013f690 | 10672 | if (strcmp (arg, "32") == 0) |
316f5878 | 10673 | mips_abi = O32_ABI; |
e013f690 | 10674 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10675 | mips_abi = O64_ABI; |
e013f690 | 10676 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10677 | mips_abi = N32_ABI; |
e013f690 TS |
10678 | else if (strcmp (arg, "64") == 0) |
10679 | { | |
316f5878 | 10680 | mips_abi = N64_ABI; |
e013f690 TS |
10681 | if (! support_64bit_objects()) |
10682 | as_fatal (_("No compiled in support for 64 bit object file " | |
10683 | "format")); | |
10684 | } | |
10685 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10686 | mips_abi = EABI_ABI; |
e013f690 | 10687 | else |
da0e507f TS |
10688 | { |
10689 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10690 | return 0; | |
10691 | } | |
252b5132 | 10692 | break; |
e013f690 | 10693 | #endif /* OBJ_ELF */ |
252b5132 | 10694 | |
6b76fefe | 10695 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10696 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10697 | break; |
10698 | ||
9ee72ff1 | 10699 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10700 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10701 | break; |
10702 | ||
ecb4347a DJ |
10703 | #ifdef OBJ_ELF |
10704 | case OPTION_MDEBUG: | |
b34976b6 | 10705 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10706 | break; |
10707 | ||
10708 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10709 | mips_flag_mdebug = FALSE; |
ecb4347a | 10710 | break; |
dcd410fe RO |
10711 | |
10712 | case OPTION_PDR: | |
10713 | mips_flag_pdr = TRUE; | |
10714 | break; | |
10715 | ||
10716 | case OPTION_NO_PDR: | |
10717 | mips_flag_pdr = FALSE; | |
10718 | break; | |
ecb4347a DJ |
10719 | #endif /* OBJ_ELF */ |
10720 | ||
252b5132 RH |
10721 | default: |
10722 | return 0; | |
10723 | } | |
10724 | ||
10725 | return 1; | |
10726 | } | |
316f5878 RS |
10727 | \f |
10728 | /* Set up globals to generate code for the ISA or processor | |
10729 | described by INFO. */ | |
252b5132 | 10730 | |
252b5132 | 10731 | static void |
17a2f251 | 10732 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10733 | { |
316f5878 | 10734 | if (info != 0) |
252b5132 | 10735 | { |
fef14a42 TS |
10736 | file_mips_arch = info->cpu; |
10737 | mips_opts.arch = info->cpu; | |
316f5878 | 10738 | mips_opts.isa = info->isa; |
252b5132 | 10739 | } |
252b5132 RH |
10740 | } |
10741 | ||
252b5132 | 10742 | |
316f5878 | 10743 | /* Likewise for tuning. */ |
252b5132 | 10744 | |
316f5878 | 10745 | static void |
17a2f251 | 10746 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10747 | { |
10748 | if (info != 0) | |
fef14a42 | 10749 | mips_tune = info->cpu; |
316f5878 | 10750 | } |
80cc45a5 | 10751 | |
34ba82a8 | 10752 | |
252b5132 | 10753 | void |
17a2f251 | 10754 | mips_after_parse_args (void) |
e9670677 | 10755 | { |
fef14a42 TS |
10756 | const struct mips_cpu_info *arch_info = 0; |
10757 | const struct mips_cpu_info *tune_info = 0; | |
10758 | ||
e9670677 MR |
10759 | /* GP relative stuff not working for PE */ |
10760 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10761 | && g_switch_value != 0) | |
10762 | { | |
10763 | if (g_switch_seen) | |
10764 | as_bad (_("-G not supported in this configuration.")); | |
10765 | g_switch_value = 0; | |
10766 | } | |
10767 | ||
cac012d6 AO |
10768 | if (mips_abi == NO_ABI) |
10769 | mips_abi = MIPS_DEFAULT_ABI; | |
10770 | ||
22923709 RS |
10771 | /* The following code determines the architecture and register size. |
10772 | Similar code was added to GCC 3.3 (see override_options() in | |
10773 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10774 | as much as possible. */ | |
e9670677 | 10775 | |
316f5878 | 10776 | if (mips_arch_string != 0) |
fef14a42 | 10777 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10778 | |
316f5878 | 10779 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10780 | { |
316f5878 | 10781 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10782 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10783 | the -march selection (if any). */ |
fef14a42 | 10784 | if (arch_info != 0) |
e9670677 | 10785 | { |
316f5878 RS |
10786 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10787 | There's no harm in specifying both as long as the ISA levels | |
10788 | are the same. */ | |
fef14a42 | 10789 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10790 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10791 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10792 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10793 | } |
316f5878 | 10794 | else |
fef14a42 | 10795 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10796 | } |
10797 | ||
fef14a42 TS |
10798 | if (arch_info == 0) |
10799 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10800 | |
fef14a42 | 10801 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10802 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10803 | arch_info->name); |
10804 | ||
10805 | mips_set_architecture (arch_info); | |
10806 | ||
10807 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10808 | if (mips_tune_string != 0) | |
10809 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10810 | |
fef14a42 TS |
10811 | if (tune_info == 0) |
10812 | mips_set_tune (arch_info); | |
10813 | else | |
10814 | mips_set_tune (tune_info); | |
e9670677 | 10815 | |
316f5878 | 10816 | if (file_mips_gp32 >= 0) |
e9670677 | 10817 | { |
316f5878 RS |
10818 | /* The user specified the size of the integer registers. Make sure |
10819 | it agrees with the ABI and ISA. */ | |
10820 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10821 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10822 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10823 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10824 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10825 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10826 | } |
10827 | else | |
10828 | { | |
316f5878 RS |
10829 | /* Infer the integer register size from the ABI and processor. |
10830 | Restrict ourselves to 32-bit registers if that's all the | |
10831 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10832 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10833 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10834 | } |
10835 | ||
316f5878 RS |
10836 | /* ??? GAS treats single-float processors as though they had 64-bit |
10837 | float registers (although it complains when double-precision | |
10838 | instructions are used). As things stand, saying they have 32-bit | |
10839 | registers would lead to spurious "register must be even" messages. | |
10840 | So here we assume float registers are always the same size as | |
10841 | integer ones, unless the user says otherwise. */ | |
10842 | if (file_mips_fp32 < 0) | |
10843 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10844 | |
316f5878 | 10845 | /* End of GCC-shared inference code. */ |
e9670677 | 10846 | |
17a2f251 TS |
10847 | /* This flag is set when we have a 64-bit capable CPU but use only |
10848 | 32-bit wide registers. Note that EABI does not use it. */ | |
10849 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10850 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10851 | || mips_abi == O32_ABI)) | |
316f5878 | 10852 | mips_32bitmode = 1; |
e9670677 MR |
10853 | |
10854 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10855 | as_bad (_("trap exception not supported at ISA 1")); | |
10856 | ||
e9670677 MR |
10857 | /* If the selected architecture includes support for ASEs, enable |
10858 | generation of code for them. */ | |
a4672219 | 10859 | if (mips_opts.mips16 == -1) |
fef14a42 | 10860 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10861 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10862 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10863 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10864 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10865 | |
e9670677 | 10866 | file_mips_isa = mips_opts.isa; |
a4672219 | 10867 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10868 | file_ase_mips3d = mips_opts.ase_mips3d; |
10869 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10870 | mips_opts.gp32 = file_mips_gp32; | |
10871 | mips_opts.fp32 = file_mips_fp32; | |
10872 | ||
ecb4347a DJ |
10873 | if (mips_flag_mdebug < 0) |
10874 | { | |
10875 | #ifdef OBJ_MAYBE_ECOFF | |
10876 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10877 | mips_flag_mdebug = 1; | |
10878 | else | |
10879 | #endif /* OBJ_MAYBE_ECOFF */ | |
10880 | mips_flag_mdebug = 0; | |
10881 | } | |
e9670677 MR |
10882 | } |
10883 | \f | |
10884 | void | |
17a2f251 | 10885 | mips_init_after_args (void) |
252b5132 RH |
10886 | { |
10887 | /* initialize opcodes */ | |
10888 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10889 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10890 | } |
10891 | ||
10892 | long | |
17a2f251 | 10893 | md_pcrel_from (fixS *fixP) |
252b5132 | 10894 | { |
a7ebbfdf TS |
10895 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10896 | switch (fixP->fx_r_type) | |
10897 | { | |
10898 | case BFD_RELOC_16_PCREL_S2: | |
10899 | case BFD_RELOC_MIPS_JMP: | |
10900 | /* Return the address of the delay slot. */ | |
10901 | return addr + 4; | |
10902 | default: | |
10903 | return addr; | |
10904 | } | |
252b5132 RH |
10905 | } |
10906 | ||
252b5132 RH |
10907 | /* This is called before the symbol table is processed. In order to |
10908 | work with gcc when using mips-tfile, we must keep all local labels. | |
10909 | However, in other cases, we want to discard them. If we were | |
10910 | called with -g, but we didn't see any debugging information, it may | |
10911 | mean that gcc is smuggling debugging information through to | |
10912 | mips-tfile, in which case we must generate all local labels. */ | |
10913 | ||
10914 | void | |
17a2f251 | 10915 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10916 | { |
10917 | #ifndef NO_ECOFF_DEBUGGING | |
10918 | if (ECOFF_DEBUGGING | |
10919 | && mips_debug != 0 | |
10920 | && ! ecoff_debugging_seen) | |
10921 | flag_keep_locals = 1; | |
10922 | #endif | |
10923 | } | |
10924 | ||
10925 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10926 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10927 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10928 | explicit use of the %hi modifier. */ | |
10929 | ||
10930 | void | |
17a2f251 | 10931 | mips_frob_file (void) |
252b5132 RH |
10932 | { |
10933 | struct mips_hi_fixup *l; | |
10934 | ||
10935 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10936 | { | |
10937 | segment_info_type *seginfo; | |
10938 | int pass; | |
10939 | ||
5919d012 | 10940 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10941 | |
5919d012 RS |
10942 | /* If a GOT16 relocation turns out to be against a global symbol, |
10943 | there isn't supposed to be a matching LO. */ | |
10944 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10945 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10946 | continue; | |
10947 | ||
10948 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10949 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10950 | continue; |
10951 | ||
10952 | /* Look through the fixups for this segment for a matching %lo. | |
10953 | When we find one, move the %hi just in front of it. We do | |
10954 | this in two passes. In the first pass, we try to find a | |
10955 | unique %lo. In the second pass, we permit multiple %hi | |
10956 | relocs for a single %lo (this is a GNU extension). */ | |
10957 | seginfo = seg_info (l->seg); | |
10958 | for (pass = 0; pass < 2; pass++) | |
10959 | { | |
10960 | fixS *f, *prev; | |
10961 | ||
10962 | prev = NULL; | |
10963 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10964 | { | |
10965 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10966 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10967 | && f->fx_addsy == l->fixp->fx_addsy | |
10968 | && f->fx_offset == l->fixp->fx_offset | |
10969 | && (pass == 1 | |
10970 | || prev == NULL | |
5919d012 RS |
10971 | || !reloc_needs_lo_p (prev->fx_r_type) |
10972 | || !fixup_has_matching_lo_p (prev))) | |
252b5132 RH |
10973 | { |
10974 | fixS **pf; | |
10975 | ||
10976 | /* Move l->fixp before f. */ | |
10977 | for (pf = &seginfo->fix_root; | |
10978 | *pf != l->fixp; | |
10979 | pf = &(*pf)->fx_next) | |
10980 | assert (*pf != NULL); | |
10981 | ||
10982 | *pf = l->fixp->fx_next; | |
10983 | ||
10984 | l->fixp->fx_next = f; | |
10985 | if (prev == NULL) | |
10986 | seginfo->fix_root = l->fixp; | |
10987 | else | |
10988 | prev->fx_next = l->fixp; | |
10989 | ||
10990 | break; | |
10991 | } | |
10992 | ||
10993 | prev = f; | |
10994 | } | |
10995 | ||
10996 | if (f != NULL) | |
10997 | break; | |
10998 | ||
10999 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
11000 | can leave a %hi without a %lo. */ | |
11001 | if (pass == 1) | |
11002 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
11003 | _("Unmatched %%hi reloc")); | |
11004 | #endif | |
11005 | } | |
11006 | } | |
11007 | } | |
11008 | ||
11009 | /* When generating embedded PIC code we need to use a special | |
11010 | relocation to represent the difference of two symbols in the .text | |
11011 | section (switch tables use a difference of this sort). See | |
11012 | include/coff/mips.h for details. This macro checks whether this | |
11013 | fixup requires the special reloc. */ | |
11014 | #define SWITCH_TABLE(fixp) \ | |
11015 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 11016 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
11017 | && (fixp)->fx_addsy != NULL \ |
11018 | && (fixp)->fx_subsy != NULL \ | |
11019 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
11020 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
11021 | ||
11022 | /* When generating embedded PIC code we must keep all PC relative | |
11023 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
11024 | to keep relocations for switch table entries. |
11025 | ||
11026 | We may have combined relocations without symbols in the N32/N64 ABI. | |
11027 | We have to prevent gas from dropping them. */ | |
252b5132 | 11028 | |
252b5132 | 11029 | int |
17a2f251 | 11030 | mips_force_relocation (fixS *fixp) |
252b5132 | 11031 | { |
ae6063d4 | 11032 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11033 | return 1; |
11034 | ||
f6688943 TS |
11035 | if (HAVE_NEWABI |
11036 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11037 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11038 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11039 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11040 | return 1; | |
11041 | ||
252b5132 RH |
11042 | return (mips_pic == EMBEDDED_PIC |
11043 | && (fixp->fx_pcrel | |
11044 | || SWITCH_TABLE (fixp) | |
11045 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
11046 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
11047 | } | |
11048 | ||
45f8dfe8 AO |
11049 | /* This hook is called before a fix is simplified. We don't really |
11050 | decide whether to skip a fix here. Rather, we turn global symbols | |
11051 | used as branch targets into local symbols, such that they undergo | |
11052 | simplification. We can only do this if the symbol is defined and | |
11053 | it is in the same section as the branch. If this doesn't hold, we | |
11054 | emit a better error message than just saying the relocation is not | |
11055 | valid for the selected object format. | |
11056 | ||
11057 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
11058 | segment in which the fix up occurs. The return value should be | |
11059 | non-zero to indicate the fix-up is valid for further | |
11060 | simplifications. */ | |
11061 | ||
11062 | int | |
17a2f251 | 11063 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
11064 | { |
11065 | /* There's a lot of discussion on whether it should be possible to | |
11066 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11067 | seems to be that it can, but gas/bfd are very broken in creating | |
11068 | RELA relocations for this, so for now we only accept branches to | |
11069 | symbols in the same section. Anything else is of dubious value, | |
11070 | since there's no guarantee that at link time the symbol would be | |
11071 | in range. Even for branches to local symbols this is arguably | |
11072 | wrong, since it we assume the symbol is not going to be | |
11073 | overridden, which should be possible per ELF library semantics, | |
11074 | but then, there isn't a dynamic relocation that could be used to | |
11075 | this effect, and the target would likely be out of range as well. | |
11076 | ||
11077 | Unfortunately, it seems that there is too much code out there | |
11078 | that relies on branches to symbols that are global to be resolved | |
11079 | as if they were local, like the IRIX tools do, so we do it as | |
11080 | well, but with a warning so that people are reminded to fix their | |
11081 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11082 | targets, this entire block should go away (and probably the | |
11083 | whole function). */ | |
11084 | ||
11085 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
11086 | && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
11087 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11088 | && mips_pic != EMBEDDED_PIC) | |
11089 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) | |
11090 | && fixP->fx_addsy) | |
11091 | { | |
11092 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11093 | { | |
11094 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11095 | _("Cannot branch to undefined symbol.")); | |
11096 | /* Avoid any further errors about this fixup. */ | |
11097 | fixP->fx_done = 1; | |
11098 | } | |
11099 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11100 | { | |
11101 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11102 | _("Cannot branch to symbol in another section.")); | |
11103 | fixP->fx_done = 1; | |
11104 | } | |
11105 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11106 | { | |
11107 | symbolS *sym = fixP->fx_addsy; | |
11108 | ||
115695a8 CD |
11109 | if (mips_pic == SVR4_PIC) |
11110 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11111 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
11112 | |
11113 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11114 | S_GET_SEGMENT (sym), | |
11115 | S_GET_VALUE (sym), | |
11116 | symbol_get_frag (sym)); | |
11117 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11118 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11119 | assert (symbol_resolved_p (sym)); | |
11120 | symbol_mark_resolved (fixP->fx_addsy); | |
11121 | } | |
11122 | } | |
11123 | ||
11124 | return 1; | |
11125 | } | |
11126 | ||
add55e1f RS |
11127 | #ifdef OBJ_ELF |
11128 | static int | |
17a2f251 | 11129 | mips_need_elf_addend_fixup (fixS *fixP) |
add55e1f | 11130 | { |
2d2bf3e0 CD |
11131 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
11132 | return 1; | |
b25a253c CD |
11133 | if (mips_pic == EMBEDDED_PIC |
11134 | && S_IS_WEAK (fixP->fx_addsy)) | |
11135 | return 1; | |
11136 | if (mips_pic != EMBEDDED_PIC | |
11137 | && (S_IS_WEAK (fixP->fx_addsy) | |
bad9ca53 | 11138 | || S_IS_EXTERNAL (fixP->fx_addsy)) |
2d2bf3e0 CD |
11139 | && !S_IS_COMMON (fixP->fx_addsy)) |
11140 | return 1; | |
9204e615 DJ |
11141 | if (((bfd_get_section_flags (stdoutput, |
11142 | S_GET_SEGMENT (fixP->fx_addsy)) | |
11143 | & (SEC_LINK_ONCE | SEC_MERGE)) != 0) | |
11144 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
11145 | ".gnu.linkonce", | |
11146 | sizeof (".gnu.linkonce") - 1)) | |
2d2bf3e0 CD |
11147 | return 1; |
11148 | return 0; | |
add55e1f RS |
11149 | } |
11150 | #endif | |
11151 | ||
252b5132 RH |
11152 | /* Apply a fixup to the object file. */ |
11153 | ||
94f592af | 11154 | void |
17a2f251 | 11155 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11156 | { |
874e8986 | 11157 | bfd_byte *buf; |
98aa84af | 11158 | long insn; |
ed6fb7bd | 11159 | static int previous_fx_r_type = 0; |
a7ebbfdf | 11160 | reloc_howto_type *howto; |
252b5132 | 11161 | |
a7ebbfdf TS |
11162 | /* We ignore generic BFD relocations we don't know about. */ |
11163 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11164 | if (! howto) | |
11165 | return; | |
65551fa4 | 11166 | |
252b5132 RH |
11167 | assert (fixP->fx_size == 4 |
11168 | || fixP->fx_r_type == BFD_RELOC_16 | |
11169 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11170 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11171 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11172 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11173 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11174 | |
a7ebbfdf | 11175 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 RH |
11176 | |
11177 | /* If we aren't adjusting this fixup to be against the section | |
11178 | symbol, we need to adjust the value. */ | |
11179 | #ifdef OBJ_ELF | |
11180 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 11181 | { |
a7ebbfdf TS |
11182 | if (mips_need_elf_addend_fixup (fixP) |
11183 | && howto->partial_inplace | |
11184 | && fixP->fx_r_type != BFD_RELOC_GPREL16 | |
11185 | && fixP->fx_r_type != BFD_RELOC_GPREL32 | |
11186 | && fixP->fx_r_type != BFD_RELOC_MIPS16_GPREL) | |
11187 | { | |
11188 | /* In this case, the bfd_install_relocation routine will | |
11189 | incorrectly add the symbol value back in. We just want | |
11190 | the addend to appear in the object file. | |
11191 | ||
11192 | The condition above used to include | |
11193 | "&& (! fixP->fx_pcrel || howto->pcrel_offset)". | |
11194 | ||
11195 | However, howto can't be trusted here, because we | |
11196 | might change the reloc type in tc_gen_reloc. We can | |
11197 | check howto->partial_inplace because that conversion | |
11198 | happens to preserve howto->partial_inplace; but it | |
11199 | does not preserve howto->pcrel_offset. I've just | |
11200 | eliminated the check, because all MIPS PC-relative | |
11201 | relocations are marked howto->pcrel_offset. | |
11202 | ||
11203 | howto->pcrel_offset was originally added for | |
11204 | R_MIPS_PC16, which is generated for code like | |
11205 | ||
11206 | globl g1 .text | |
11207 | .text | |
11208 | .space 20 | |
11209 | g1: | |
11210 | x: | |
11211 | bal g1 | |
11212 | */ | |
11213 | *valP -= S_GET_VALUE (fixP->fx_addsy); | |
98aa84af | 11214 | } |
252b5132 | 11215 | |
bb2d6cd7 GK |
11216 | /* This code was generated using trial and error and so is |
11217 | fragile and not trustworthy. If you change it, you should | |
11218 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
11219 | they still pass. */ | |
a7ebbfdf | 11220 | if (fixP->fx_pcrel) |
bb2d6cd7 | 11221 | { |
a7ebbfdf | 11222 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
bb2d6cd7 GK |
11223 | |
11224 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
11225 | This gives the right results, but it can't possibly | |
11226 | be the way things are supposed to work. */ | |
a7ebbfdf | 11227 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
bb2d6cd7 GK |
11228 | } |
11229 | } | |
11230 | #endif | |
252b5132 | 11231 | |
ed6fb7bd SC |
11232 | /* We are not done if this is a composite relocation to set up gp. */ |
11233 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
11234 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10181a0d AO |
11235 | || (fixP->fx_r_type == BFD_RELOC_64 |
11236 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
11237 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
11238 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
11239 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
11240 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 11241 | fixP->fx_done = 1; |
ed6fb7bd | 11242 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
11243 | |
11244 | switch (fixP->fx_r_type) | |
11245 | { | |
11246 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11247 | case BFD_RELOC_MIPS_SHIFT5: |
11248 | case BFD_RELOC_MIPS_SHIFT6: | |
11249 | case BFD_RELOC_MIPS_GOT_DISP: | |
11250 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11251 | case BFD_RELOC_MIPS_GOT_OFST: | |
11252 | case BFD_RELOC_MIPS_SUB: | |
11253 | case BFD_RELOC_MIPS_INSERT_A: | |
11254 | case BFD_RELOC_MIPS_INSERT_B: | |
11255 | case BFD_RELOC_MIPS_DELETE: | |
11256 | case BFD_RELOC_MIPS_HIGHEST: | |
11257 | case BFD_RELOC_MIPS_HIGHER: | |
11258 | case BFD_RELOC_MIPS_SCN_DISP: | |
11259 | case BFD_RELOC_MIPS_REL16: | |
11260 | case BFD_RELOC_MIPS_RELGOT: | |
11261 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11262 | case BFD_RELOC_HI16: |
11263 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11264 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11265 | case BFD_RELOC_MIPS_LITERAL: |
11266 | case BFD_RELOC_MIPS_CALL16: | |
11267 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11268 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11269 | case BFD_RELOC_MIPS_GOT_HI16: |
11270 | case BFD_RELOC_MIPS_GOT_LO16: | |
11271 | case BFD_RELOC_MIPS_CALL_HI16: | |
11272 | case BFD_RELOC_MIPS_CALL_LO16: | |
11273 | case BFD_RELOC_MIPS16_GPREL: | |
11274 | if (fixP->fx_pcrel) | |
11275 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11276 | _("Invalid PC relative reloc")); | |
11277 | /* Nothing needed to do. The value comes from the reloc entry */ | |
11278 | break; | |
11279 | ||
11280 | case BFD_RELOC_MIPS16_JMP: | |
11281 | /* We currently always generate a reloc against a symbol, which | |
11282 | means that we don't want an addend even if the symbol is | |
11283 | defined. */ | |
a7ebbfdf | 11284 | *valP = 0; |
252b5132 RH |
11285 | break; |
11286 | ||
11287 | case BFD_RELOC_PCREL_HI16_S: | |
11288 | /* The addend for this is tricky if it is internal, so we just | |
11289 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11290 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11291 | break; |
11292 | if (fixP->fx_addsy | |
11293 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
11294 | { |
11295 | /* For an external symbol adjust by the address to make it | |
11296 | pcrel_offset. We use the address of the RELLO reloc | |
11297 | which follows this one. */ | |
a7ebbfdf | 11298 | *valP += (fixP->fx_next->fx_frag->fr_address |
252b5132 RH |
11299 | + fixP->fx_next->fx_where); |
11300 | } | |
a7ebbfdf | 11301 | *valP = ((*valP + 0x8000) >> 16) & 0xffff; |
252b5132 RH |
11302 | if (target_big_endian) |
11303 | buf += 2; | |
17a2f251 | 11304 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11305 | break; |
11306 | ||
11307 | case BFD_RELOC_PCREL_LO16: | |
11308 | /* The addend for this is tricky if it is internal, so we just | |
11309 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11310 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11311 | break; |
11312 | if (fixP->fx_addsy | |
11313 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
a7ebbfdf | 11314 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
252b5132 RH |
11315 | if (target_big_endian) |
11316 | buf += 2; | |
17a2f251 | 11317 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11318 | break; |
11319 | ||
11320 | case BFD_RELOC_64: | |
11321 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11322 | extended value if we are only 32 bits. */ | |
11323 | if (fixP->fx_done | |
11324 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11325 | { | |
11326 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 11327 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11328 | else |
11329 | { | |
a7ebbfdf | 11330 | valueT hiv; |
252b5132 | 11331 | |
a7ebbfdf | 11332 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11333 | hiv = 0xffffffff; |
11334 | else | |
11335 | hiv = 0; | |
a7ebbfdf TS |
11336 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11337 | *valP, 4); | |
11338 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11339 | hiv, 4); | |
252b5132 RH |
11340 | } |
11341 | } | |
11342 | break; | |
11343 | ||
056350c6 | 11344 | case BFD_RELOC_RVA: |
252b5132 RH |
11345 | case BFD_RELOC_32: |
11346 | /* If we are deleting this reloc entry, we must fill in the | |
11347 | value now. This can happen if we have a .word which is not | |
11348 | resolved when it appears but is later defined. We also need | |
11349 | to fill in the value if this is an embedded PIC switch table | |
11350 | entry. */ | |
11351 | if (fixP->fx_done | |
11352 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
a7ebbfdf | 11353 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11354 | break; |
11355 | ||
11356 | case BFD_RELOC_16: | |
11357 | /* If we are deleting this reloc entry, we must fill in the | |
11358 | value now. */ | |
11359 | assert (fixP->fx_size == 2); | |
11360 | if (fixP->fx_done) | |
a7ebbfdf | 11361 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11362 | break; |
11363 | ||
11364 | case BFD_RELOC_LO16: | |
11365 | /* When handling an embedded PIC switch statement, we can wind | |
11366 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11367 | if (fixP->fx_done) | |
11368 | { | |
a7ebbfdf | 11369 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11370 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11371 | _("relocation overflow")); | |
252b5132 RH |
11372 | if (target_big_endian) |
11373 | buf += 2; | |
17a2f251 | 11374 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11375 | } |
11376 | break; | |
11377 | ||
11378 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11379 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11380 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11381 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11382 | |
252b5132 RH |
11383 | /* |
11384 | * We need to save the bits in the instruction since fixup_segment() | |
11385 | * might be deleting the relocation entry (i.e., a branch within | |
11386 | * the current segment). | |
11387 | */ | |
a7ebbfdf | 11388 | if (! fixP->fx_done) |
bb2d6cd7 | 11389 | break; |
252b5132 RH |
11390 | |
11391 | /* update old instruction data */ | |
252b5132 RH |
11392 | if (target_big_endian) |
11393 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11394 | else | |
11395 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11396 | ||
a7ebbfdf TS |
11397 | if (*valP + 0x20000 <= 0x3ffff) |
11398 | { | |
11399 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11400 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11401 | } |
11402 | else if (mips_pic == NO_PIC | |
11403 | && fixP->fx_done | |
11404 | && fixP->fx_frag->fr_address >= text_section->vma | |
11405 | && (fixP->fx_frag->fr_address | |
11406 | < text_section->vma + text_section->_raw_size) | |
11407 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11408 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11409 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11410 | { |
11411 | /* The branch offset is too large. If this is an | |
11412 | unconditional branch, and we are not generating PIC code, | |
11413 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11414 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11415 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11416 | else |
a7ebbfdf TS |
11417 | insn = 0x08000000; /* j */ |
11418 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11419 | fixP->fx_done = 0; | |
11420 | fixP->fx_addsy = section_symbol (text_section); | |
11421 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11422 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11423 | } |
11424 | else | |
11425 | { | |
11426 | /* If we got here, we have branch-relaxation disabled, | |
11427 | and there's nothing we can do to fix this instruction | |
11428 | without turning it into a longer sequence. */ | |
11429 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11430 | _("Branch out of range")); | |
252b5132 | 11431 | } |
252b5132 RH |
11432 | break; |
11433 | ||
11434 | case BFD_RELOC_VTABLE_INHERIT: | |
11435 | fixP->fx_done = 0; | |
11436 | if (fixP->fx_addsy | |
11437 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11438 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11439 | S_SET_WEAK (fixP->fx_addsy); | |
11440 | break; | |
11441 | ||
11442 | case BFD_RELOC_VTABLE_ENTRY: | |
11443 | fixP->fx_done = 0; | |
11444 | break; | |
11445 | ||
11446 | default: | |
11447 | internalError (); | |
11448 | } | |
a7ebbfdf TS |
11449 | |
11450 | /* Remember value for tc_gen_reloc. */ | |
11451 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11452 | } |
11453 | ||
11454 | #if 0 | |
11455 | void | |
17a2f251 | 11456 | printInsn (unsigned long oc) |
252b5132 RH |
11457 | { |
11458 | const struct mips_opcode *p; | |
11459 | int treg, sreg, dreg, shamt; | |
11460 | short imm; | |
11461 | const char *args; | |
11462 | int i; | |
11463 | ||
11464 | for (i = 0; i < NUMOPCODES; ++i) | |
11465 | { | |
11466 | p = &mips_opcodes[i]; | |
11467 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11468 | { | |
11469 | printf ("%08lx %s\t", oc, p->name); | |
11470 | treg = (oc >> 16) & 0x1f; | |
11471 | sreg = (oc >> 21) & 0x1f; | |
11472 | dreg = (oc >> 11) & 0x1f; | |
11473 | shamt = (oc >> 6) & 0x1f; | |
11474 | imm = oc; | |
11475 | for (args = p->args;; ++args) | |
11476 | { | |
11477 | switch (*args) | |
11478 | { | |
11479 | case '\0': | |
11480 | printf ("\n"); | |
11481 | break; | |
11482 | ||
11483 | case ',': | |
11484 | case '(': | |
11485 | case ')': | |
11486 | printf ("%c", *args); | |
11487 | continue; | |
11488 | ||
11489 | case 'r': | |
11490 | assert (treg == sreg); | |
11491 | printf ("$%d,$%d", treg, sreg); | |
11492 | continue; | |
11493 | ||
11494 | case 'd': | |
11495 | case 'G': | |
11496 | printf ("$%d", dreg); | |
11497 | continue; | |
11498 | ||
11499 | case 't': | |
11500 | case 'E': | |
11501 | printf ("$%d", treg); | |
11502 | continue; | |
11503 | ||
11504 | case 'k': | |
11505 | printf ("0x%x", treg); | |
11506 | continue; | |
11507 | ||
11508 | case 'b': | |
11509 | case 's': | |
11510 | printf ("$%d", sreg); | |
11511 | continue; | |
11512 | ||
11513 | case 'a': | |
11514 | printf ("0x%08lx", oc & 0x1ffffff); | |
11515 | continue; | |
11516 | ||
11517 | case 'i': | |
11518 | case 'j': | |
11519 | case 'o': | |
11520 | case 'u': | |
11521 | printf ("%d", imm); | |
11522 | continue; | |
11523 | ||
11524 | case '<': | |
11525 | case '>': | |
11526 | printf ("$%d", shamt); | |
11527 | continue; | |
11528 | ||
11529 | default: | |
11530 | internalError (); | |
11531 | } | |
11532 | break; | |
11533 | } | |
11534 | return; | |
11535 | } | |
11536 | } | |
11537 | printf (_("%08lx UNDEFINED\n"), oc); | |
11538 | } | |
11539 | #endif | |
11540 | ||
11541 | static symbolS * | |
17a2f251 | 11542 | get_symbol (void) |
252b5132 RH |
11543 | { |
11544 | int c; | |
11545 | char *name; | |
11546 | symbolS *p; | |
11547 | ||
11548 | name = input_line_pointer; | |
11549 | c = get_symbol_end (); | |
11550 | p = (symbolS *) symbol_find_or_make (name); | |
11551 | *input_line_pointer = c; | |
11552 | return p; | |
11553 | } | |
11554 | ||
11555 | /* Align the current frag to a given power of two. The MIPS assembler | |
11556 | also automatically adjusts any preceding label. */ | |
11557 | ||
11558 | static void | |
17a2f251 | 11559 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11560 | { |
b34976b6 | 11561 | mips_emit_delays (FALSE); |
252b5132 RH |
11562 | frag_align (to, fill, 0); |
11563 | record_alignment (now_seg, to); | |
11564 | if (label != NULL) | |
11565 | { | |
11566 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11567 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11568 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11569 | } | |
11570 | } | |
11571 | ||
11572 | /* Align to a given power of two. .align 0 turns off the automatic | |
11573 | alignment used by the data creating pseudo-ops. */ | |
11574 | ||
11575 | static void | |
17a2f251 | 11576 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11577 | { |
11578 | register int temp; | |
11579 | register long temp_fill; | |
11580 | long max_alignment = 15; | |
11581 | ||
11582 | /* | |
11583 | ||
11584 | o Note that the assembler pulls down any immediately preceeding label | |
11585 | to the aligned address. | |
11586 | o It's not documented but auto alignment is reinstated by | |
11587 | a .align pseudo instruction. | |
11588 | o Note also that after auto alignment is turned off the mips assembler | |
11589 | issues an error on attempt to assemble an improperly aligned data item. | |
11590 | We don't. | |
11591 | ||
11592 | */ | |
11593 | ||
11594 | temp = get_absolute_expression (); | |
11595 | if (temp > max_alignment) | |
11596 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11597 | else if (temp < 0) | |
11598 | { | |
11599 | as_warn (_("Alignment negative: 0 assumed.")); | |
11600 | temp = 0; | |
11601 | } | |
11602 | if (*input_line_pointer == ',') | |
11603 | { | |
f9419b05 | 11604 | ++input_line_pointer; |
252b5132 RH |
11605 | temp_fill = get_absolute_expression (); |
11606 | } | |
11607 | else | |
11608 | temp_fill = 0; | |
11609 | if (temp) | |
11610 | { | |
11611 | auto_align = 1; | |
11612 | mips_align (temp, (int) temp_fill, | |
11613 | insn_labels != NULL ? insn_labels->label : NULL); | |
11614 | } | |
11615 | else | |
11616 | { | |
11617 | auto_align = 0; | |
11618 | } | |
11619 | ||
11620 | demand_empty_rest_of_line (); | |
11621 | } | |
11622 | ||
11623 | void | |
17a2f251 | 11624 | mips_flush_pending_output (void) |
252b5132 | 11625 | { |
b34976b6 | 11626 | mips_emit_delays (FALSE); |
252b5132 RH |
11627 | mips_clear_insn_labels (); |
11628 | } | |
11629 | ||
11630 | static void | |
17a2f251 | 11631 | s_change_sec (int sec) |
252b5132 RH |
11632 | { |
11633 | segT seg; | |
11634 | ||
11635 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11636 | .sdata and .sbss sections. We change the .data and .rdata | |
11637 | pseudo-ops to use .sdata. */ | |
11638 | if (mips_pic == EMBEDDED_PIC | |
11639 | && (sec == 'd' || sec == 'r')) | |
11640 | sec = 's'; | |
11641 | ||
11642 | #ifdef OBJ_ELF | |
11643 | /* The ELF backend needs to know that we are changing sections, so | |
11644 | that .previous works correctly. We could do something like check | |
b6ff326e | 11645 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11646 | as it would not be appropriate to use it in the section changing |
11647 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11648 | This should be cleaner, somehow. */ | |
11649 | obj_elf_section_change_hook (); | |
11650 | #endif | |
11651 | ||
b34976b6 | 11652 | mips_emit_delays (FALSE); |
252b5132 RH |
11653 | switch (sec) |
11654 | { | |
11655 | case 't': | |
11656 | s_text (0); | |
11657 | break; | |
11658 | case 'd': | |
11659 | s_data (0); | |
11660 | break; | |
11661 | case 'b': | |
11662 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11663 | demand_empty_rest_of_line (); | |
11664 | break; | |
11665 | ||
11666 | case 'r': | |
11667 | if (USE_GLOBAL_POINTER_OPT) | |
11668 | { | |
11669 | seg = subseg_new (RDATA_SECTION_NAME, | |
11670 | (subsegT) get_absolute_expression ()); | |
11671 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11672 | { | |
11673 | bfd_set_section_flags (stdoutput, seg, | |
11674 | (SEC_ALLOC | |
11675 | | SEC_LOAD | |
11676 | | SEC_READONLY | |
11677 | | SEC_RELOC | |
11678 | | SEC_DATA)); | |
11679 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11680 | record_alignment (seg, 4); |
252b5132 RH |
11681 | } |
11682 | demand_empty_rest_of_line (); | |
11683 | } | |
11684 | else | |
11685 | { | |
11686 | as_bad (_("No read only data section in this object file format")); | |
11687 | demand_empty_rest_of_line (); | |
11688 | return; | |
11689 | } | |
11690 | break; | |
11691 | ||
11692 | case 's': | |
11693 | if (USE_GLOBAL_POINTER_OPT) | |
11694 | { | |
11695 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11696 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11697 | { | |
11698 | bfd_set_section_flags (stdoutput, seg, | |
11699 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11700 | | SEC_DATA); | |
11701 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11702 | record_alignment (seg, 4); |
252b5132 RH |
11703 | } |
11704 | demand_empty_rest_of_line (); | |
11705 | break; | |
11706 | } | |
11707 | else | |
11708 | { | |
11709 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11710 | demand_empty_rest_of_line (); | |
11711 | return; | |
11712 | } | |
11713 | } | |
11714 | ||
11715 | auto_align = 1; | |
11716 | } | |
b34976b6 | 11717 | |
cca86cc8 | 11718 | void |
17a2f251 | 11719 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11720 | { |
7ed4a06a | 11721 | #ifdef OBJ_ELF |
cca86cc8 SC |
11722 | char *section_name; |
11723 | char c; | |
684022ea | 11724 | char next_c = 0; |
cca86cc8 SC |
11725 | int section_type; |
11726 | int section_flag; | |
11727 | int section_entry_size; | |
11728 | int section_alignment; | |
b34976b6 | 11729 | |
7ed4a06a TS |
11730 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11731 | return; | |
11732 | ||
cca86cc8 SC |
11733 | section_name = input_line_pointer; |
11734 | c = get_symbol_end (); | |
a816d1ed AO |
11735 | if (c) |
11736 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11737 | |
4cf0dd0d TS |
11738 | /* Do we have .section Name<,"flags">? */ |
11739 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11740 | { |
4cf0dd0d TS |
11741 | /* just after name is now '\0'. */ |
11742 | *input_line_pointer = c; | |
cca86cc8 SC |
11743 | input_line_pointer = section_name; |
11744 | obj_elf_section (ignore); | |
11745 | return; | |
11746 | } | |
11747 | input_line_pointer++; | |
11748 | ||
11749 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11750 | if (c == ',') | |
11751 | section_type = get_absolute_expression (); | |
11752 | else | |
11753 | section_type = 0; | |
11754 | if (*input_line_pointer++ == ',') | |
11755 | section_flag = get_absolute_expression (); | |
11756 | else | |
11757 | section_flag = 0; | |
11758 | if (*input_line_pointer++ == ',') | |
11759 | section_entry_size = get_absolute_expression (); | |
11760 | else | |
11761 | section_entry_size = 0; | |
11762 | if (*input_line_pointer++ == ',') | |
11763 | section_alignment = get_absolute_expression (); | |
11764 | else | |
11765 | section_alignment = 0; | |
11766 | ||
a816d1ed AO |
11767 | section_name = xstrdup (section_name); |
11768 | ||
cca86cc8 SC |
11769 | obj_elf_change_section (section_name, section_type, section_flag, |
11770 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11771 | |
11772 | if (now_seg->name != section_name) | |
11773 | free (section_name); | |
7ed4a06a | 11774 | #endif /* OBJ_ELF */ |
cca86cc8 | 11775 | } |
252b5132 RH |
11776 | |
11777 | void | |
17a2f251 | 11778 | mips_enable_auto_align (void) |
252b5132 RH |
11779 | { |
11780 | auto_align = 1; | |
11781 | } | |
11782 | ||
11783 | static void | |
17a2f251 | 11784 | s_cons (int log_size) |
252b5132 RH |
11785 | { |
11786 | symbolS *label; | |
11787 | ||
11788 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11789 | mips_emit_delays (FALSE); |
252b5132 RH |
11790 | if (log_size > 0 && auto_align) |
11791 | mips_align (log_size, 0, label); | |
11792 | mips_clear_insn_labels (); | |
11793 | cons (1 << log_size); | |
11794 | } | |
11795 | ||
11796 | static void | |
17a2f251 | 11797 | s_float_cons (int type) |
252b5132 RH |
11798 | { |
11799 | symbolS *label; | |
11800 | ||
11801 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11802 | ||
b34976b6 | 11803 | mips_emit_delays (FALSE); |
252b5132 RH |
11804 | |
11805 | if (auto_align) | |
49309057 ILT |
11806 | { |
11807 | if (type == 'd') | |
11808 | mips_align (3, 0, label); | |
11809 | else | |
11810 | mips_align (2, 0, label); | |
11811 | } | |
252b5132 RH |
11812 | |
11813 | mips_clear_insn_labels (); | |
11814 | ||
11815 | float_cons (type); | |
11816 | } | |
11817 | ||
11818 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11819 | permitted to say | |
11820 | .globl foo .text | |
11821 | where foo is an undefined symbol, to mean that foo should be | |
11822 | considered to be the address of a function. */ | |
11823 | ||
11824 | static void | |
17a2f251 | 11825 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11826 | { |
11827 | char *name; | |
11828 | int c; | |
11829 | symbolS *symbolP; | |
11830 | flagword flag; | |
11831 | ||
11832 | name = input_line_pointer; | |
11833 | c = get_symbol_end (); | |
11834 | symbolP = symbol_find_or_make (name); | |
11835 | *input_line_pointer = c; | |
11836 | SKIP_WHITESPACE (); | |
11837 | ||
11838 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11839 | being a function is apparently labelled as being an object. */ | |
11840 | flag = BSF_OBJECT; | |
11841 | ||
11842 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11843 | { | |
11844 | char *secname; | |
11845 | asection *sec; | |
11846 | ||
11847 | secname = input_line_pointer; | |
11848 | c = get_symbol_end (); | |
11849 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11850 | if (sec == NULL) | |
11851 | as_bad (_("%s: no such section"), secname); | |
11852 | *input_line_pointer = c; | |
11853 | ||
11854 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11855 | flag = BSF_FUNCTION; | |
11856 | } | |
11857 | ||
49309057 | 11858 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11859 | |
11860 | S_SET_EXTERNAL (symbolP); | |
11861 | demand_empty_rest_of_line (); | |
11862 | } | |
11863 | ||
11864 | static void | |
17a2f251 | 11865 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11866 | { |
11867 | char *opt; | |
11868 | char c; | |
11869 | ||
11870 | opt = input_line_pointer; | |
11871 | c = get_symbol_end (); | |
11872 | ||
11873 | if (*opt == 'O') | |
11874 | { | |
11875 | /* FIXME: What does this mean? */ | |
11876 | } | |
11877 | else if (strncmp (opt, "pic", 3) == 0) | |
11878 | { | |
11879 | int i; | |
11880 | ||
11881 | i = atoi (opt + 3); | |
11882 | if (i == 0) | |
11883 | mips_pic = NO_PIC; | |
11884 | else if (i == 2) | |
143d77c5 | 11885 | { |
252b5132 | 11886 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11887 | mips_abicalls = TRUE; |
11888 | } | |
252b5132 RH |
11889 | else |
11890 | as_bad (_(".option pic%d not supported"), i); | |
11891 | ||
11892 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11893 | { | |
11894 | if (g_switch_seen && g_switch_value != 0) | |
11895 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11896 | g_switch_value = 0; | |
11897 | bfd_set_gp_size (stdoutput, 0); | |
11898 | } | |
11899 | } | |
11900 | else | |
11901 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11902 | ||
11903 | *input_line_pointer = c; | |
11904 | demand_empty_rest_of_line (); | |
11905 | } | |
11906 | ||
11907 | /* This structure is used to hold a stack of .set values. */ | |
11908 | ||
e972090a NC |
11909 | struct mips_option_stack |
11910 | { | |
252b5132 RH |
11911 | struct mips_option_stack *next; |
11912 | struct mips_set_options options; | |
11913 | }; | |
11914 | ||
11915 | static struct mips_option_stack *mips_opts_stack; | |
11916 | ||
11917 | /* Handle the .set pseudo-op. */ | |
11918 | ||
11919 | static void | |
17a2f251 | 11920 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11921 | { |
11922 | char *name = input_line_pointer, ch; | |
11923 | ||
11924 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11925 | ++input_line_pointer; |
252b5132 RH |
11926 | ch = *input_line_pointer; |
11927 | *input_line_pointer = '\0'; | |
11928 | ||
11929 | if (strcmp (name, "reorder") == 0) | |
11930 | { | |
11931 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11932 | { | |
11933 | /* If we still have pending nops, we can discard them. The | |
11934 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11935 | needed. */ |
252b5132 RH |
11936 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11937 | * (mips_opts.mips16 ? 2 : 4)); | |
11938 | prev_nop_frag = NULL; | |
11939 | } | |
11940 | mips_opts.noreorder = 0; | |
11941 | } | |
11942 | else if (strcmp (name, "noreorder") == 0) | |
11943 | { | |
b34976b6 | 11944 | mips_emit_delays (TRUE); |
252b5132 RH |
11945 | mips_opts.noreorder = 1; |
11946 | mips_any_noreorder = 1; | |
11947 | } | |
11948 | else if (strcmp (name, "at") == 0) | |
11949 | { | |
11950 | mips_opts.noat = 0; | |
11951 | } | |
11952 | else if (strcmp (name, "noat") == 0) | |
11953 | { | |
11954 | mips_opts.noat = 1; | |
11955 | } | |
11956 | else if (strcmp (name, "macro") == 0) | |
11957 | { | |
11958 | mips_opts.warn_about_macros = 0; | |
11959 | } | |
11960 | else if (strcmp (name, "nomacro") == 0) | |
11961 | { | |
11962 | if (mips_opts.noreorder == 0) | |
11963 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11964 | mips_opts.warn_about_macros = 1; | |
11965 | } | |
11966 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11967 | { | |
11968 | mips_opts.nomove = 0; | |
11969 | } | |
11970 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11971 | { | |
11972 | mips_opts.nomove = 1; | |
11973 | } | |
11974 | else if (strcmp (name, "bopt") == 0) | |
11975 | { | |
11976 | mips_opts.nobopt = 0; | |
11977 | } | |
11978 | else if (strcmp (name, "nobopt") == 0) | |
11979 | { | |
11980 | mips_opts.nobopt = 1; | |
11981 | } | |
11982 | else if (strcmp (name, "mips16") == 0 | |
11983 | || strcmp (name, "MIPS-16") == 0) | |
11984 | mips_opts.mips16 = 1; | |
11985 | else if (strcmp (name, "nomips16") == 0 | |
11986 | || strcmp (name, "noMIPS-16") == 0) | |
11987 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11988 | else if (strcmp (name, "mips3d") == 0) |
11989 | mips_opts.ase_mips3d = 1; | |
11990 | else if (strcmp (name, "nomips3d") == 0) | |
11991 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11992 | else if (strcmp (name, "mdmx") == 0) |
11993 | mips_opts.ase_mdmx = 1; | |
11994 | else if (strcmp (name, "nomdmx") == 0) | |
11995 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11996 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11997 | { |
af7ee8bf | 11998 | int reset = 0; |
252b5132 | 11999 | |
1a2c1fad CD |
12000 | /* Permit the user to change the ISA and architecture on the fly. |
12001 | Needless to say, misuse can cause serious problems. */ | |
af7ee8bf CD |
12002 | if (strcmp (name, "mips0") == 0) |
12003 | { | |
12004 | reset = 1; | |
12005 | mips_opts.isa = file_mips_isa; | |
12006 | } | |
12007 | else if (strcmp (name, "mips1") == 0) | |
12008 | mips_opts.isa = ISA_MIPS1; | |
12009 | else if (strcmp (name, "mips2") == 0) | |
12010 | mips_opts.isa = ISA_MIPS2; | |
12011 | else if (strcmp (name, "mips3") == 0) | |
12012 | mips_opts.isa = ISA_MIPS3; | |
12013 | else if (strcmp (name, "mips4") == 0) | |
12014 | mips_opts.isa = ISA_MIPS4; | |
12015 | else if (strcmp (name, "mips5") == 0) | |
12016 | mips_opts.isa = ISA_MIPS5; | |
12017 | else if (strcmp (name, "mips32") == 0) | |
12018 | mips_opts.isa = ISA_MIPS32; | |
12019 | else if (strcmp (name, "mips32r2") == 0) | |
12020 | mips_opts.isa = ISA_MIPS32R2; | |
12021 | else if (strcmp (name, "mips64") == 0) | |
12022 | mips_opts.isa = ISA_MIPS64; | |
1a2c1fad CD |
12023 | else if (strcmp (name, "arch=default") == 0) |
12024 | { | |
12025 | reset = 1; | |
12026 | mips_opts.arch = file_mips_arch; | |
12027 | mips_opts.isa = file_mips_isa; | |
12028 | } | |
12029 | else if (strncmp (name, "arch=", 5) == 0) | |
12030 | { | |
12031 | const struct mips_cpu_info *p; | |
12032 | ||
12033 | p = mips_parse_cpu("internal use", name + 5); | |
12034 | if (!p) | |
12035 | as_bad (_("unknown architecture %s"), name + 5); | |
12036 | else | |
12037 | { | |
12038 | mips_opts.arch = p->cpu; | |
12039 | mips_opts.isa = p->isa; | |
12040 | } | |
12041 | } | |
af7ee8bf CD |
12042 | else |
12043 | as_bad (_("unknown ISA level %s"), name + 4); | |
12044 | ||
12045 | switch (mips_opts.isa) | |
98d3f06f KH |
12046 | { |
12047 | case 0: | |
98d3f06f | 12048 | break; |
af7ee8bf CD |
12049 | case ISA_MIPS1: |
12050 | case ISA_MIPS2: | |
12051 | case ISA_MIPS32: | |
12052 | case ISA_MIPS32R2: | |
98d3f06f KH |
12053 | mips_opts.gp32 = 1; |
12054 | mips_opts.fp32 = 1; | |
12055 | break; | |
af7ee8bf CD |
12056 | case ISA_MIPS3: |
12057 | case ISA_MIPS4: | |
12058 | case ISA_MIPS5: | |
12059 | case ISA_MIPS64: | |
98d3f06f KH |
12060 | mips_opts.gp32 = 0; |
12061 | mips_opts.fp32 = 0; | |
12062 | break; | |
12063 | default: | |
12064 | as_bad (_("unknown ISA level %s"), name + 4); | |
12065 | break; | |
12066 | } | |
af7ee8bf | 12067 | if (reset) |
98d3f06f | 12068 | { |
af7ee8bf CD |
12069 | mips_opts.gp32 = file_mips_gp32; |
12070 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12071 | } |
252b5132 RH |
12072 | } |
12073 | else if (strcmp (name, "autoextend") == 0) | |
12074 | mips_opts.noautoextend = 0; | |
12075 | else if (strcmp (name, "noautoextend") == 0) | |
12076 | mips_opts.noautoextend = 1; | |
12077 | else if (strcmp (name, "push") == 0) | |
12078 | { | |
12079 | struct mips_option_stack *s; | |
12080 | ||
12081 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12082 | s->next = mips_opts_stack; | |
12083 | s->options = mips_opts; | |
12084 | mips_opts_stack = s; | |
12085 | } | |
12086 | else if (strcmp (name, "pop") == 0) | |
12087 | { | |
12088 | struct mips_option_stack *s; | |
12089 | ||
12090 | s = mips_opts_stack; | |
12091 | if (s == NULL) | |
12092 | as_bad (_(".set pop with no .set push")); | |
12093 | else | |
12094 | { | |
12095 | /* If we're changing the reorder mode we need to handle | |
12096 | delay slots correctly. */ | |
12097 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 12098 | mips_emit_delays (TRUE); |
252b5132 RH |
12099 | else if (! s->options.noreorder && mips_opts.noreorder) |
12100 | { | |
12101 | if (prev_nop_frag != NULL) | |
12102 | { | |
12103 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
12104 | * (mips_opts.mips16 ? 2 : 4)); | |
12105 | prev_nop_frag = NULL; | |
12106 | } | |
12107 | } | |
12108 | ||
12109 | mips_opts = s->options; | |
12110 | mips_opts_stack = s->next; | |
12111 | free (s); | |
12112 | } | |
12113 | } | |
12114 | else | |
12115 | { | |
12116 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12117 | } | |
12118 | *input_line_pointer = ch; | |
12119 | demand_empty_rest_of_line (); | |
12120 | } | |
12121 | ||
12122 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12123 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12124 | ||
12125 | static void | |
17a2f251 | 12126 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12127 | { |
12128 | mips_pic = SVR4_PIC; | |
143d77c5 | 12129 | mips_abicalls = TRUE; |
252b5132 RH |
12130 | if (USE_GLOBAL_POINTER_OPT) |
12131 | { | |
12132 | if (g_switch_seen && g_switch_value != 0) | |
12133 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12134 | g_switch_value = 0; | |
12135 | } | |
12136 | bfd_set_gp_size (stdoutput, 0); | |
12137 | demand_empty_rest_of_line (); | |
12138 | } | |
12139 | ||
12140 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12141 | PIC code. It sets the $gp register for the function based on the | |
12142 | function address, which is in the register named in the argument. | |
12143 | This uses a relocation against _gp_disp, which is handled specially | |
12144 | by the linker. The result is: | |
12145 | lui $gp,%hi(_gp_disp) | |
12146 | addiu $gp,$gp,%lo(_gp_disp) | |
12147 | addu $gp,$gp,.cpload argument | |
12148 | The .cpload argument is normally $25 == $t9. */ | |
12149 | ||
12150 | static void | |
17a2f251 | 12151 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12152 | { |
12153 | expressionS ex; | |
12154 | int icnt = 0; | |
12155 | ||
6478892d TS |
12156 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12157 | .cpload is ignored. */ | |
12158 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12159 | { |
12160 | s_ignore (0); | |
12161 | return; | |
12162 | } | |
12163 | ||
d3ecfc59 | 12164 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12165 | if (mips_opts.noreorder == 0) |
12166 | as_warn (_(".cpload not in noreorder section")); | |
12167 | ||
12168 | ex.X_op = O_symbol; | |
12169 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
12170 | ex.X_op_symbol = NULL; | |
12171 | ex.X_add_number = 0; | |
12172 | ||
12173 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12174 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12175 | |
c9914766 | 12176 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
17a2f251 TS |
12177 | macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register, |
12178 | mips_gp_register, BFD_RELOC_LO16); | |
252b5132 | 12179 | |
17a2f251 TS |
12180 | macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register, |
12181 | mips_gp_register, tc_get_register (0)); | |
252b5132 RH |
12182 | |
12183 | demand_empty_rest_of_line (); | |
12184 | } | |
12185 | ||
6478892d TS |
12186 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12187 | .cpsetup $reg1, offset|$reg2, label | |
12188 | ||
12189 | If offset is given, this results in: | |
12190 | sd $gp, offset($sp) | |
956cd1d6 | 12191 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12192 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12193 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12194 | |
12195 | If $reg2 is given, this results in: | |
12196 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12197 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12198 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12199 | daddu $gp, $gp, $reg1 | |
12200 | $reg1 is normally $25 == $t9. */ | |
6478892d | 12201 | static void |
17a2f251 | 12202 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12203 | { |
12204 | expressionS ex_off; | |
12205 | expressionS ex_sym; | |
12206 | int reg1; | |
12207 | int icnt = 0; | |
f21f8242 | 12208 | char *f; |
6478892d | 12209 | |
8586fc66 | 12210 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12211 | We also need NewABI support. */ |
12212 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12213 | { | |
12214 | s_ignore (0); | |
12215 | return; | |
12216 | } | |
12217 | ||
12218 | reg1 = tc_get_register (0); | |
12219 | SKIP_WHITESPACE (); | |
12220 | if (*input_line_pointer != ',') | |
12221 | { | |
12222 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12223 | return; | |
12224 | } | |
12225 | else | |
80245285 | 12226 | ++input_line_pointer; |
6478892d TS |
12227 | SKIP_WHITESPACE (); |
12228 | if (*input_line_pointer == '$') | |
80245285 TS |
12229 | { |
12230 | mips_cpreturn_register = tc_get_register (0); | |
12231 | mips_cpreturn_offset = -1; | |
12232 | } | |
6478892d | 12233 | else |
80245285 TS |
12234 | { |
12235 | mips_cpreturn_offset = get_absolute_expression (); | |
12236 | mips_cpreturn_register = -1; | |
12237 | } | |
6478892d TS |
12238 | SKIP_WHITESPACE (); |
12239 | if (*input_line_pointer != ',') | |
12240 | { | |
12241 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12242 | return; | |
12243 | } | |
12244 | else | |
f9419b05 | 12245 | ++input_line_pointer; |
6478892d | 12246 | SKIP_WHITESPACE (); |
f21f8242 | 12247 | expression (&ex_sym); |
6478892d TS |
12248 | |
12249 | if (mips_cpreturn_register == -1) | |
12250 | { | |
12251 | ex_off.X_op = O_constant; | |
12252 | ex_off.X_add_symbol = NULL; | |
12253 | ex_off.X_op_symbol = NULL; | |
12254 | ex_off.X_add_number = mips_cpreturn_offset; | |
12255 | ||
17a2f251 TS |
12256 | macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register, |
12257 | BFD_RELOC_LO16, SP); | |
6478892d TS |
12258 | } |
12259 | else | |
17a2f251 TS |
12260 | macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register, |
12261 | mips_gp_register, 0); | |
6478892d | 12262 | |
f21f8242 AO |
12263 | /* Ensure there's room for the next two instructions, so that `f' |
12264 | doesn't end up with an address in the wrong frag. */ | |
12265 | frag_grow (8); | |
12266 | f = frag_more (0); | |
17a2f251 TS |
12267 | macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, |
12268 | BFD_RELOC_GPREL16); | |
f21f8242 | 12269 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12270 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12271 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12272 | 4, NULL, 0, 0, BFD_RELOC_HI16_S); |
f21f8242 AO |
12273 | |
12274 | f = frag_more (0); | |
17a2f251 TS |
12275 | macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register, |
12276 | mips_gp_register, BFD_RELOC_GPREL16); | |
f21f8242 | 12277 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12278 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12279 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12280 | 4, NULL, 0, 0, BFD_RELOC_LO16); |
f21f8242 | 12281 | |
17a2f251 TS |
12282 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, |
12283 | mips_gp_register, reg1); | |
6478892d TS |
12284 | |
12285 | demand_empty_rest_of_line (); | |
12286 | } | |
12287 | ||
12288 | static void | |
17a2f251 | 12289 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12290 | { |
12291 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12292 | .cplocal is ignored. */ | |
12293 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12294 | { | |
12295 | s_ignore (0); | |
12296 | return; | |
12297 | } | |
12298 | ||
12299 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12300 | demand_empty_rest_of_line (); |
6478892d TS |
12301 | } |
12302 | ||
252b5132 RH |
12303 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12304 | offset from $sp. The offset is remembered, and after making a PIC | |
12305 | call $gp is restored from that location. */ | |
12306 | ||
12307 | static void | |
17a2f251 | 12308 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12309 | { |
12310 | expressionS ex; | |
12311 | int icnt = 0; | |
12312 | ||
6478892d | 12313 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12314 | .cprestore is ignored. */ |
6478892d | 12315 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12316 | { |
12317 | s_ignore (0); | |
12318 | return; | |
12319 | } | |
12320 | ||
12321 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12322 | mips_cprestore_valid = 1; |
252b5132 RH |
12323 | |
12324 | ex.X_op = O_constant; | |
12325 | ex.X_add_symbol = NULL; | |
12326 | ex.X_op_symbol = NULL; | |
12327 | ex.X_add_number = mips_cprestore_offset; | |
12328 | ||
17a2f251 | 12329 | macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN, |
256ab948 | 12330 | mips_gp_register, SP, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
12331 | |
12332 | demand_empty_rest_of_line (); | |
12333 | } | |
12334 | ||
6478892d TS |
12335 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
12336 | was given in the preceeding .gpsetup, it results in: | |
12337 | ld $gp, offset($sp) | |
76b3015f | 12338 | |
6478892d TS |
12339 | If a register $reg2 was given there, it results in: |
12340 | daddiu $gp, $gp, $reg2 | |
12341 | */ | |
12342 | static void | |
17a2f251 | 12343 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12344 | { |
12345 | expressionS ex; | |
12346 | int icnt = 0; | |
12347 | ||
12348 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12349 | We also need NewABI support. */ | |
12350 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12351 | { | |
12352 | s_ignore (0); | |
12353 | return; | |
12354 | } | |
12355 | ||
12356 | if (mips_cpreturn_register == -1) | |
12357 | { | |
12358 | ex.X_op = O_constant; | |
12359 | ex.X_add_symbol = NULL; | |
12360 | ex.X_op_symbol = NULL; | |
12361 | ex.X_add_number = mips_cpreturn_offset; | |
12362 | ||
17a2f251 TS |
12363 | macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register, |
12364 | BFD_RELOC_LO16, SP); | |
6478892d TS |
12365 | } |
12366 | else | |
17a2f251 TS |
12367 | macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register, |
12368 | mips_cpreturn_register, 0); | |
6478892d TS |
12369 | |
12370 | demand_empty_rest_of_line (); | |
12371 | } | |
12372 | ||
12373 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12374 | code. It sets the offset to use in gp_rel relocations. */ | |
12375 | ||
12376 | static void | |
17a2f251 | 12377 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12378 | { |
12379 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12380 | We also need NewABI support. */ | |
12381 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12382 | { | |
12383 | s_ignore (0); | |
12384 | return; | |
12385 | } | |
12386 | ||
def2e0dd | 12387 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12388 | |
12389 | demand_empty_rest_of_line (); | |
12390 | } | |
12391 | ||
252b5132 RH |
12392 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12393 | code. It generates a 32 bit GP relative reloc. */ | |
12394 | ||
12395 | static void | |
17a2f251 | 12396 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12397 | { |
12398 | symbolS *label; | |
12399 | expressionS ex; | |
12400 | char *p; | |
12401 | ||
12402 | /* When not generating PIC code, this is treated as .word. */ | |
12403 | if (mips_pic != SVR4_PIC) | |
12404 | { | |
12405 | s_cons (2); | |
12406 | return; | |
12407 | } | |
12408 | ||
12409 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12410 | mips_emit_delays (TRUE); |
252b5132 RH |
12411 | if (auto_align) |
12412 | mips_align (2, 0, label); | |
12413 | mips_clear_insn_labels (); | |
12414 | ||
12415 | expression (&ex); | |
12416 | ||
12417 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12418 | { | |
12419 | as_bad (_("Unsupported use of .gpword")); | |
12420 | ignore_rest_of_line (); | |
12421 | } | |
12422 | ||
12423 | p = frag_more (4); | |
17a2f251 | 12424 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12425 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12426 | BFD_RELOC_GPREL32); |
252b5132 RH |
12427 | |
12428 | demand_empty_rest_of_line (); | |
12429 | } | |
12430 | ||
10181a0d | 12431 | static void |
17a2f251 | 12432 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12433 | { |
12434 | symbolS *label; | |
12435 | expressionS ex; | |
12436 | char *p; | |
12437 | ||
12438 | /* When not generating PIC code, this is treated as .dword. */ | |
12439 | if (mips_pic != SVR4_PIC) | |
12440 | { | |
12441 | s_cons (3); | |
12442 | return; | |
12443 | } | |
12444 | ||
12445 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12446 | mips_emit_delays (TRUE); |
10181a0d AO |
12447 | if (auto_align) |
12448 | mips_align (3, 0, label); | |
12449 | mips_clear_insn_labels (); | |
12450 | ||
12451 | expression (&ex); | |
12452 | ||
12453 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12454 | { | |
12455 | as_bad (_("Unsupported use of .gpdword")); | |
12456 | ignore_rest_of_line (); | |
12457 | } | |
12458 | ||
12459 | p = frag_more (8); | |
17a2f251 | 12460 | md_number_to_chars (p, 0, 8); |
a105a300 | 12461 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
10181a0d AO |
12462 | BFD_RELOC_GPREL32); |
12463 | ||
12464 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12465 | ex.X_op = O_absent; | |
12466 | ex.X_add_symbol = 0; | |
12467 | ex.X_add_number = 0; | |
b34976b6 | 12468 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12469 | BFD_RELOC_64); |
12470 | ||
12471 | demand_empty_rest_of_line (); | |
12472 | } | |
12473 | ||
252b5132 RH |
12474 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12475 | tables in SVR4 PIC code. */ | |
12476 | ||
12477 | static void | |
17a2f251 | 12478 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12479 | { |
12480 | int icnt = 0; | |
12481 | int reg; | |
12482 | ||
10181a0d AO |
12483 | /* This is ignored when not generating SVR4 PIC code. */ |
12484 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12485 | { |
12486 | s_ignore (0); | |
12487 | return; | |
12488 | } | |
12489 | ||
12490 | /* Add $gp to the register named as an argument. */ | |
12491 | reg = tc_get_register (0); | |
17a2f251 TS |
12492 | macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", |
12493 | reg, reg, mips_gp_register); | |
252b5132 | 12494 | |
bdaaa2e1 | 12495 | demand_empty_rest_of_line (); |
252b5132 RH |
12496 | } |
12497 | ||
12498 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12499 | mips16 mode. This permits the linker to handle them specially, | |
12500 | such as generating jalx instructions when needed. We also make | |
12501 | them odd for the duration of the assembly, in order to generate the | |
12502 | right sort of code. We will make them even in the adjust_symtab | |
12503 | routine, while leaving them marked. This is convenient for the | |
12504 | debugger and the disassembler. The linker knows to make them odd | |
12505 | again. */ | |
12506 | ||
12507 | static void | |
17a2f251 | 12508 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12509 | { |
f9419b05 | 12510 | mips16_mark_labels (); |
252b5132 RH |
12511 | |
12512 | demand_empty_rest_of_line (); | |
12513 | } | |
12514 | ||
12515 | /* Handle a .stabn directive. We need these in order to mark a label | |
12516 | as being a mips16 text label correctly. Sometimes the compiler | |
12517 | will emit a label, followed by a .stabn, and then switch sections. | |
12518 | If the label and .stabn are in mips16 mode, then the label is | |
12519 | really a mips16 text label. */ | |
12520 | ||
12521 | static void | |
17a2f251 | 12522 | s_mips_stab (int type) |
252b5132 | 12523 | { |
f9419b05 | 12524 | if (type == 'n') |
252b5132 RH |
12525 | mips16_mark_labels (); |
12526 | ||
12527 | s_stab (type); | |
12528 | } | |
12529 | ||
12530 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12531 | */ | |
12532 | ||
12533 | static void | |
17a2f251 | 12534 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12535 | { |
12536 | char *name; | |
12537 | int c; | |
12538 | symbolS *symbolP; | |
12539 | expressionS exp; | |
12540 | ||
12541 | name = input_line_pointer; | |
12542 | c = get_symbol_end (); | |
12543 | symbolP = symbol_find_or_make (name); | |
12544 | S_SET_WEAK (symbolP); | |
12545 | *input_line_pointer = c; | |
12546 | ||
12547 | SKIP_WHITESPACE (); | |
12548 | ||
12549 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12550 | { | |
12551 | if (S_IS_DEFINED (symbolP)) | |
12552 | { | |
956cd1d6 | 12553 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12554 | S_GET_NAME (symbolP)); |
12555 | ignore_rest_of_line (); | |
12556 | return; | |
12557 | } | |
bdaaa2e1 | 12558 | |
252b5132 RH |
12559 | if (*input_line_pointer == ',') |
12560 | { | |
12561 | ++input_line_pointer; | |
12562 | SKIP_WHITESPACE (); | |
12563 | } | |
bdaaa2e1 | 12564 | |
252b5132 RH |
12565 | expression (&exp); |
12566 | if (exp.X_op != O_symbol) | |
12567 | { | |
12568 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12569 | ignore_rest_of_line (); |
252b5132 RH |
12570 | return; |
12571 | } | |
49309057 | 12572 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12573 | } |
12574 | ||
12575 | demand_empty_rest_of_line (); | |
12576 | } | |
12577 | ||
12578 | /* Parse a register string into a number. Called from the ECOFF code | |
12579 | to parse .frame. The argument is non-zero if this is the frame | |
12580 | register, so that we can record it in mips_frame_reg. */ | |
12581 | ||
12582 | int | |
17a2f251 | 12583 | tc_get_register (int frame) |
252b5132 RH |
12584 | { |
12585 | int reg; | |
12586 | ||
12587 | SKIP_WHITESPACE (); | |
12588 | if (*input_line_pointer++ != '$') | |
12589 | { | |
12590 | as_warn (_("expected `$'")); | |
85b51719 | 12591 | reg = ZERO; |
252b5132 | 12592 | } |
3882b010 | 12593 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12594 | { |
12595 | reg = get_absolute_expression (); | |
12596 | if (reg < 0 || reg >= 32) | |
12597 | { | |
12598 | as_warn (_("Bad register number")); | |
85b51719 | 12599 | reg = ZERO; |
252b5132 RH |
12600 | } |
12601 | } | |
12602 | else | |
12603 | { | |
76db943d | 12604 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12605 | { |
12606 | reg = RA; | |
12607 | input_line_pointer += 2; | |
12608 | } | |
76db943d | 12609 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12610 | { |
12611 | reg = FP; | |
12612 | input_line_pointer += 2; | |
12613 | } | |
252b5132 | 12614 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12615 | { |
12616 | reg = SP; | |
12617 | input_line_pointer += 2; | |
12618 | } | |
252b5132 | 12619 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12620 | { |
12621 | reg = GP; | |
12622 | input_line_pointer += 2; | |
12623 | } | |
252b5132 | 12624 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12625 | { |
12626 | reg = AT; | |
12627 | input_line_pointer += 2; | |
12628 | } | |
12629 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12630 | { | |
12631 | reg = KT0; | |
12632 | input_line_pointer += 3; | |
12633 | } | |
12634 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12635 | { | |
12636 | reg = KT1; | |
12637 | input_line_pointer += 3; | |
12638 | } | |
12639 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12640 | { | |
12641 | reg = ZERO; | |
12642 | input_line_pointer += 4; | |
12643 | } | |
252b5132 RH |
12644 | else |
12645 | { | |
12646 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12647 | reg = ZERO; |
12648 | while (ISALNUM(*input_line_pointer)) | |
12649 | input_line_pointer++; | |
252b5132 | 12650 | } |
252b5132 RH |
12651 | } |
12652 | if (frame) | |
7a621144 DJ |
12653 | { |
12654 | mips_frame_reg = reg != 0 ? reg : SP; | |
12655 | mips_frame_reg_valid = 1; | |
12656 | mips_cprestore_valid = 0; | |
12657 | } | |
252b5132 RH |
12658 | return reg; |
12659 | } | |
12660 | ||
12661 | valueT | |
17a2f251 | 12662 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12663 | { |
12664 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12665 | ||
12666 | #ifdef OBJ_ELF | |
12667 | /* We don't need to align ELF sections to the full alignment. | |
12668 | However, Irix 5 may prefer that we align them at least to a 16 | |
12669 | byte boundary. We don't bother to align the sections if we are | |
12670 | targeted for an embedded system. */ | |
12671 | if (strcmp (TARGET_OS, "elf") == 0) | |
12672 | return addr; | |
12673 | if (align > 4) | |
12674 | align = 4; | |
12675 | #endif | |
12676 | ||
12677 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12678 | } | |
12679 | ||
12680 | /* Utility routine, called from above as well. If called while the | |
12681 | input file is still being read, it's only an approximation. (For | |
12682 | example, a symbol may later become defined which appeared to be | |
12683 | undefined earlier.) */ | |
12684 | ||
12685 | static int | |
17a2f251 | 12686 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12687 | { |
12688 | if (sym == 0) | |
12689 | return 0; | |
12690 | ||
6478892d | 12691 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12692 | { |
12693 | const char *symname; | |
12694 | int change; | |
12695 | ||
c9914766 | 12696 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12697 | register. It can be if it is smaller than the -G size or if |
12698 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12699 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12700 | they can. */ |
12701 | symname = S_GET_NAME (sym); | |
12702 | if (symname != (const char *) NULL | |
12703 | && (strcmp (symname, "eprol") == 0 | |
12704 | || strcmp (symname, "etext") == 0 | |
12705 | || strcmp (symname, "_gp") == 0 | |
12706 | || strcmp (symname, "edata") == 0 | |
12707 | || strcmp (symname, "_fbss") == 0 | |
12708 | || strcmp (symname, "_fdata") == 0 | |
12709 | || strcmp (symname, "_ftext") == 0 | |
12710 | || strcmp (symname, "end") == 0 | |
12711 | || strcmp (symname, "_gp_disp") == 0)) | |
12712 | change = 1; | |
12713 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12714 | && (0 | |
12715 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12716 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12717 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12718 | <= g_switch_value)) | |
252b5132 RH |
12719 | #endif |
12720 | /* We must defer this decision until after the whole | |
12721 | file has been read, since there might be a .extern | |
12722 | after the first use of this symbol. */ | |
12723 | || (before_relaxing | |
12724 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12725 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12726 | #endif |
12727 | && S_GET_VALUE (sym) == 0) | |
12728 | || (S_GET_VALUE (sym) != 0 | |
12729 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12730 | change = 0; | |
12731 | else | |
12732 | { | |
12733 | const char *segname; | |
12734 | ||
12735 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12736 | assert (strcmp (segname, ".lit8") != 0 | |
12737 | && strcmp (segname, ".lit4") != 0); | |
12738 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12739 | && strcmp (segname, ".sbss") != 0 |
12740 | && strncmp (segname, ".sdata.", 7) != 0 | |
12741 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12742 | } |
12743 | return change; | |
12744 | } | |
12745 | else | |
c9914766 | 12746 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12747 | return 1; |
12748 | } | |
12749 | ||
5919d012 RS |
12750 | |
12751 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12752 | ||
12753 | static bfd_boolean | |
17a2f251 | 12754 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12755 | { |
12756 | asection *symsec; | |
12757 | bfd_boolean linkonce; | |
12758 | ||
12759 | /* Handle the case of a symbol equated to another symbol. */ | |
12760 | while (symbol_equated_reloc_p (sym)) | |
12761 | { | |
12762 | symbolS *n; | |
12763 | ||
12764 | /* It's possible to get a loop here in a badly written | |
12765 | program. */ | |
12766 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12767 | if (n == sym) | |
12768 | break; | |
12769 | sym = n; | |
12770 | } | |
12771 | ||
12772 | symsec = S_GET_SEGMENT (sym); | |
12773 | ||
12774 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12775 | linkonce = FALSE; | |
12776 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12777 | { | |
12778 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12779 | != 0) | |
12780 | linkonce = TRUE; | |
12781 | ||
12782 | /* The GNU toolchain uses an extension for ELF: a section | |
12783 | beginning with the magic string .gnu.linkonce is a linkonce | |
12784 | section. */ | |
12785 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12786 | sizeof ".gnu.linkonce" - 1) == 0) | |
12787 | linkonce = TRUE; | |
12788 | } | |
12789 | ||
12790 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12791 | return (symsec != &bfd_und_section | |
12792 | && symsec != &bfd_abs_section | |
12793 | && ! bfd_is_com_section (symsec) | |
12794 | && !linkonce | |
12795 | #ifdef OBJ_ELF | |
12796 | /* A global or weak symbol is treated as external. */ | |
12797 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
12798 | || (! S_IS_WEAK (sym) | |
12799 | && (! S_IS_EXTERNAL (sym) | |
12800 | || mips_pic == EMBEDDED_PIC))) | |
12801 | #endif | |
12802 | ); | |
12803 | } | |
12804 | ||
12805 | ||
252b5132 RH |
12806 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12807 | extended opcode. SEC is the section the frag is in. */ | |
12808 | ||
12809 | static int | |
17a2f251 | 12810 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12811 | { |
12812 | int type; | |
12813 | register const struct mips16_immed_operand *op; | |
12814 | offsetT val; | |
12815 | int mintiny, maxtiny; | |
12816 | segT symsec; | |
98aa84af | 12817 | fragS *sym_frag; |
252b5132 RH |
12818 | |
12819 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12820 | return 0; | |
12821 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12822 | return 1; | |
12823 | ||
12824 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12825 | op = mips16_immed_operands; | |
12826 | while (op->type != type) | |
12827 | { | |
12828 | ++op; | |
12829 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12830 | } | |
12831 | ||
12832 | if (op->unsp) | |
12833 | { | |
12834 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12835 | { | |
12836 | mintiny = 1; | |
12837 | maxtiny = 1 << op->nbits; | |
12838 | } | |
12839 | else | |
12840 | { | |
12841 | mintiny = 0; | |
12842 | maxtiny = (1 << op->nbits) - 1; | |
12843 | } | |
12844 | } | |
12845 | else | |
12846 | { | |
12847 | mintiny = - (1 << (op->nbits - 1)); | |
12848 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12849 | } | |
12850 | ||
98aa84af | 12851 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12852 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12853 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12854 | |
12855 | if (op->pcrel) | |
12856 | { | |
12857 | addressT addr; | |
12858 | ||
12859 | /* We won't have the section when we are called from | |
12860 | mips_relax_frag. However, we will always have been called | |
12861 | from md_estimate_size_before_relax first. If this is a | |
12862 | branch to a different section, we mark it as such. If SEC is | |
12863 | NULL, and the frag is not marked, then it must be a branch to | |
12864 | the same section. */ | |
12865 | if (sec == NULL) | |
12866 | { | |
12867 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12868 | return 1; | |
12869 | } | |
12870 | else | |
12871 | { | |
98aa84af | 12872 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12873 | if (symsec != sec) |
12874 | { | |
12875 | fragp->fr_subtype = | |
12876 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12877 | ||
12878 | /* FIXME: We should support this, and let the linker | |
12879 | catch branches and loads that are out of range. */ | |
12880 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12881 | _("unsupported PC relative reference to different section")); | |
12882 | ||
12883 | return 1; | |
12884 | } | |
98aa84af AM |
12885 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12886 | /* Assume non-extended on the first relaxation pass. | |
12887 | The address we have calculated will be bogus if this is | |
12888 | a forward branch to another frag, as the forward frag | |
12889 | will have fr_address == 0. */ | |
12890 | return 0; | |
252b5132 RH |
12891 | } |
12892 | ||
12893 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12894 | the same section. If the relax_marker of the symbol fragment |
12895 | differs from the relax_marker of this fragment, we have not | |
12896 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12897 | in STRETCH in order to get a better estimate of the address. |
12898 | This particularly matters because of the shift bits. */ | |
12899 | if (stretch != 0 | |
98aa84af | 12900 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12901 | { |
12902 | fragS *f; | |
12903 | ||
12904 | /* Adjust stretch for any alignment frag. Note that if have | |
12905 | been expanding the earlier code, the symbol may be | |
12906 | defined in what appears to be an earlier frag. FIXME: | |
12907 | This doesn't handle the fr_subtype field, which specifies | |
12908 | a maximum number of bytes to skip when doing an | |
12909 | alignment. */ | |
98aa84af | 12910 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12911 | { |
12912 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12913 | { | |
12914 | if (stretch < 0) | |
12915 | stretch = - ((- stretch) | |
12916 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12917 | else | |
12918 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12919 | if (stretch == 0) | |
12920 | break; | |
12921 | } | |
12922 | } | |
12923 | if (f != NULL) | |
12924 | val += stretch; | |
12925 | } | |
12926 | ||
12927 | addr = fragp->fr_address + fragp->fr_fix; | |
12928 | ||
12929 | /* The base address rules are complicated. The base address of | |
12930 | a branch is the following instruction. The base address of a | |
12931 | PC relative load or add is the instruction itself, but if it | |
12932 | is in a delay slot (in which case it can not be extended) use | |
12933 | the address of the instruction whose delay slot it is in. */ | |
12934 | if (type == 'p' || type == 'q') | |
12935 | { | |
12936 | addr += 2; | |
12937 | ||
12938 | /* If we are currently assuming that this frag should be | |
12939 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12940 | higher. */ |
252b5132 RH |
12941 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12942 | addr += 2; | |
12943 | ||
12944 | /* Ignore the low bit in the target, since it will be set | |
12945 | for a text label. */ | |
12946 | if ((val & 1) != 0) | |
12947 | --val; | |
12948 | } | |
12949 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12950 | addr -= 4; | |
12951 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12952 | addr -= 2; | |
12953 | ||
12954 | val -= addr & ~ ((1 << op->shift) - 1); | |
12955 | ||
12956 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12957 | if (type == 'p' || type == 'q') | |
12958 | val /= 2; | |
12959 | ||
12960 | /* If any of the shifted bits are set, we must use an extended | |
12961 | opcode. If the address depends on the size of this | |
12962 | instruction, this can lead to a loop, so we arrange to always | |
12963 | use an extended opcode. We only check this when we are in | |
12964 | the main relaxation loop, when SEC is NULL. */ | |
12965 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12966 | { | |
12967 | fragp->fr_subtype = | |
12968 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12969 | return 1; | |
12970 | } | |
12971 | ||
12972 | /* If we are about to mark a frag as extended because the value | |
12973 | is precisely maxtiny + 1, then there is a chance of an | |
12974 | infinite loop as in the following code: | |
12975 | la $4,foo | |
12976 | .skip 1020 | |
12977 | .align 2 | |
12978 | foo: | |
12979 | In this case when the la is extended, foo is 0x3fc bytes | |
12980 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12981 | the la must be extended. To avoid this loop, we mark the | |
12982 | frag as extended if it was small, and is about to become | |
12983 | extended with a value of maxtiny + 1. */ | |
12984 | if (val == ((maxtiny + 1) << op->shift) | |
12985 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12986 | && sec == NULL) | |
12987 | { | |
12988 | fragp->fr_subtype = | |
12989 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12990 | return 1; | |
12991 | } | |
12992 | } | |
12993 | else if (symsec != absolute_section && sec != NULL) | |
12994 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12995 | ||
12996 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12997 | || val < (mintiny << op->shift) | |
12998 | || val > (maxtiny << op->shift)) | |
12999 | return 1; | |
13000 | else | |
13001 | return 0; | |
13002 | } | |
13003 | ||
4a6a3df4 AO |
13004 | /* Compute the length of a branch sequence, and adjust the |
13005 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13006 | worst-case length is computed, with UPDATE being used to indicate | |
13007 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13008 | branch is to be computed. */ | |
13009 | static int | |
17a2f251 | 13010 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13011 | { |
b34976b6 | 13012 | bfd_boolean toofar; |
4a6a3df4 AO |
13013 | int length; |
13014 | ||
13015 | if (fragp | |
13016 | && S_IS_DEFINED (fragp->fr_symbol) | |
13017 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13018 | { | |
13019 | addressT addr; | |
13020 | offsetT val; | |
13021 | ||
13022 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13023 | ||
13024 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13025 | ||
13026 | val -= addr; | |
13027 | ||
13028 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13029 | } | |
13030 | else if (fragp) | |
13031 | /* If the symbol is not defined or it's in a different segment, | |
13032 | assume the user knows what's going on and emit a short | |
13033 | branch. */ | |
b34976b6 | 13034 | toofar = FALSE; |
4a6a3df4 | 13035 | else |
b34976b6 | 13036 | toofar = TRUE; |
4a6a3df4 AO |
13037 | |
13038 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13039 | fragp->fr_subtype | |
af6ae2ad | 13040 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13041 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13042 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13043 | toofar); | |
13044 | ||
13045 | length = 4; | |
13046 | if (toofar) | |
13047 | { | |
13048 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13049 | length += 8; | |
13050 | ||
13051 | if (mips_pic != NO_PIC) | |
13052 | { | |
13053 | /* Additional space for PIC loading of target address. */ | |
13054 | length += 8; | |
13055 | if (mips_opts.isa == ISA_MIPS1) | |
13056 | /* Additional space for $at-stabilizing nop. */ | |
13057 | length += 4; | |
13058 | } | |
13059 | ||
13060 | /* If branch is conditional. */ | |
13061 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13062 | length += 8; | |
13063 | } | |
b34976b6 | 13064 | |
4a6a3df4 AO |
13065 | return length; |
13066 | } | |
13067 | ||
252b5132 RH |
13068 | /* Estimate the size of a frag before relaxing. Unless this is the |
13069 | mips16, we are not really relaxing here, and the final size is | |
13070 | encoded in the subtype information. For the mips16, we have to | |
13071 | decide whether we are using an extended opcode or not. */ | |
13072 | ||
252b5132 | 13073 | int |
17a2f251 | 13074 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13075 | { |
5919d012 | 13076 | int change; |
252b5132 | 13077 | |
4a6a3df4 AO |
13078 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13079 | { | |
13080 | ||
b34976b6 AM |
13081 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13082 | ||
4a6a3df4 AO |
13083 | return fragp->fr_var; |
13084 | } | |
13085 | ||
252b5132 | 13086 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13087 | /* We don't want to modify the EXTENDED bit here; it might get us |
13088 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13089 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13090 | |
13091 | if (mips_pic == NO_PIC) | |
5919d012 | 13092 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13093 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13094 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
13095 | else |
13096 | abort (); | |
13097 | ||
13098 | if (change) | |
13099 | { | |
13100 | /* Record the offset to the first reloc in the fr_opcode field. | |
13101 | This lets md_convert_frag and tc_gen_reloc know that the code | |
13102 | must be expanded. */ | |
13103 | fragp->fr_opcode = (fragp->fr_literal | |
13104 | + fragp->fr_fix | |
13105 | - RELAX_OLD (fragp->fr_subtype) | |
13106 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
13107 | /* FIXME: This really needs as_warn_where. */ | |
13108 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
13109 | as_warn (_("AT used after \".set noat\" or macro used after " |
13110 | "\".set nomacro\"")); | |
13111 | ||
13112 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
13113 | } |
13114 | ||
9a41af64 | 13115 | return 0; |
252b5132 RH |
13116 | } |
13117 | ||
13118 | /* This is called to see whether a reloc against a defined symbol | |
13119 | should be converted into a reloc against a section. Don't adjust | |
13120 | MIPS16 jump relocations, so we don't have to worry about the format | |
13121 | of the offset in the .o file. Don't adjust relocations against | |
13122 | mips16 symbols, so that the linker can find them if it needs to set | |
13123 | up a stub. */ | |
13124 | ||
13125 | int | |
17a2f251 | 13126 | mips_fix_adjustable (fixS *fixp) |
252b5132 RH |
13127 | { |
13128 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
13129 | return 0; | |
a161fe53 | 13130 | |
252b5132 RH |
13131 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13132 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13133 | return 0; | |
a161fe53 | 13134 | |
252b5132 RH |
13135 | if (fixp->fx_addsy == NULL) |
13136 | return 1; | |
a161fe53 | 13137 | |
252b5132 RH |
13138 | #ifdef OBJ_ELF |
13139 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
13140 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13141 | && fixp->fx_subsy == NULL) | |
13142 | return 0; | |
13143 | #endif | |
a161fe53 | 13144 | |
252b5132 RH |
13145 | return 1; |
13146 | } | |
13147 | ||
13148 | /* Translate internal representation of relocation info to BFD target | |
13149 | format. */ | |
13150 | ||
13151 | arelent ** | |
17a2f251 | 13152 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13153 | { |
13154 | static arelent *retval[4]; | |
13155 | arelent *reloc; | |
13156 | bfd_reloc_code_real_type code; | |
13157 | ||
4b0cff4e TS |
13158 | memset (retval, 0, sizeof(retval)); |
13159 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13160 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13161 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13162 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13163 | ||
13164 | if (mips_pic == EMBEDDED_PIC | |
13165 | && SWITCH_TABLE (fixp)) | |
13166 | { | |
13167 | /* For a switch table entry we use a special reloc. The addend | |
13168 | is actually the difference between the reloc address and the | |
13169 | subtrahend. */ | |
13170 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13171 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
13172 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
13173 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
13174 | } | |
13175 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
13176 | { | |
4514d474 CD |
13177 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13178 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13179 | else |
4514d474 CD |
13180 | { |
13181 | /* We use a special addend for an internal RELLO reloc. */ | |
13182 | if (symbol_section_p (fixp->fx_addsy)) | |
13183 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13184 | else | |
13185 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13186 | } | |
252b5132 RH |
13187 | } |
13188 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
13189 | { | |
13190 | assert (fixp->fx_next != NULL | |
13191 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
13192 | |
13193 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 13194 | accordingly. */ |
4514d474 CD |
13195 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13196 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 13197 | else |
4514d474 CD |
13198 | { |
13199 | /* We use a special addend for an internal RELHI reloc. */ | |
13200 | if (symbol_section_p (fixp->fx_addsy)) | |
13201 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
13202 | + fixp->fx_next->fx_where | |
13203 | - S_GET_VALUE (fixp->fx_subsy)); | |
13204 | else | |
13205 | reloc->addend = (fixp->fx_addnumber | |
13206 | + fixp->fx_next->fx_frag->fr_address | |
13207 | + fixp->fx_next->fx_where); | |
13208 | } | |
252b5132 | 13209 | } |
4514d474 CD |
13210 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
13211 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
13212 | else |
13213 | { | |
13214 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
13215 | /* A gruesome hack which is a result of the gruesome gas reloc | |
13216 | handling. */ | |
13217 | reloc->addend = reloc->address; | |
13218 | else | |
13219 | reloc->addend = -reloc->address; | |
13220 | } | |
13221 | ||
13222 | /* If this is a variant frag, we may need to adjust the existing | |
13223 | reloc and generate a new one. */ | |
13224 | if (fixp->fx_frag->fr_opcode != NULL | |
ed6fb7bd SC |
13225 | && ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13226 | && ! HAVE_NEWABI) | |
f5040a92 AO |
13227 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP |
13228 | && HAVE_NEWABI) | |
252b5132 RH |
13229 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
13230 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
13231 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
13232 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
13233 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d | 13234 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
ed6fb7bd | 13235 | ) |
252b5132 RH |
13236 | { |
13237 | arelent *reloc2; | |
13238 | ||
13239 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
13240 | ||
13241 | /* If this is not the last reloc in this frag, then we have two | |
13242 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
13243 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
13244 | the second one handle all of them. */ | |
13245 | if (fixp->fx_next != NULL | |
13246 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
13247 | { | |
cdf6fd85 TS |
13248 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
13249 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
13250 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
13251 | && (fixp->fx_next->fx_r_type | |
13252 | == BFD_RELOC_MIPS_GOT_LO16)) | |
13253 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
13254 | && (fixp->fx_next->fx_r_type | |
13255 | == BFD_RELOC_MIPS_CALL_LO16))); | |
13256 | retval[0] = NULL; | |
13257 | return retval; | |
13258 | } | |
13259 | ||
13260 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
13261 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
f5040a92 | 13262 | reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset; |
252b5132 | 13263 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); |
49309057 ILT |
13264 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13265 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13266 | reloc2->address = (reloc->address |
13267 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
13268 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
a7ebbfdf | 13269 | reloc2->addend = fixp->fx_addnumber - S_GET_VALUE (fixp->fx_addsy) |
f5040a92 | 13270 | + fixp->fx_frag->tc_frag_data.tc_fr_offset; |
252b5132 RH |
13271 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); |
13272 | assert (reloc2->howto != NULL); | |
13273 | ||
13274 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
13275 | { | |
13276 | arelent *reloc3; | |
13277 | ||
13278 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
252b5132 RH |
13279 | *reloc3 = *reloc2; |
13280 | reloc3->address += 4; | |
13281 | } | |
13282 | ||
13283 | if (mips_pic == NO_PIC) | |
13284 | { | |
cdf6fd85 | 13285 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
13286 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
13287 | } | |
13288 | else if (mips_pic == SVR4_PIC) | |
13289 | { | |
13290 | switch (fixp->fx_r_type) | |
13291 | { | |
13292 | default: | |
13293 | abort (); | |
13294 | case BFD_RELOC_MIPS_GOT16: | |
13295 | break; | |
252b5132 RH |
13296 | case BFD_RELOC_MIPS_GOT_LO16: |
13297 | case BFD_RELOC_MIPS_CALL_LO16: | |
ed6fb7bd SC |
13298 | if (HAVE_NEWABI) |
13299 | { | |
ed6fb7bd SC |
13300 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE; |
13301 | reloc2->howto = bfd_reloc_type_lookup | |
13302 | (stdoutput, BFD_RELOC_MIPS_GOT_OFST); | |
13303 | } | |
13304 | else | |
13305 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13306 | break; | |
f5040a92 AO |
13307 | case BFD_RELOC_MIPS_CALL16: |
13308 | case BFD_RELOC_MIPS_GOT_OFST: | |
13309 | case BFD_RELOC_MIPS_GOT_DISP: | |
13310 | if (HAVE_NEWABI) | |
13311 | { | |
13312 | /* It may seem nonsensical to relax GOT_DISP to | |
13313 | GOT_DISP, but we're actually turning a GOT_DISP | |
13314 | without offset into a GOT_DISP with an offset, | |
13315 | getting rid of the separate addition, which we can | |
13316 | do when the symbol is found to be local. */ | |
13317 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP; | |
13318 | retval[1] = NULL; | |
13319 | } | |
13320 | else | |
13321 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
13322 | break; | |
252b5132 RH |
13323 | } |
13324 | } | |
13325 | else | |
13326 | abort (); | |
13327 | } | |
13328 | ||
438c16b8 TS |
13329 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13330 | entry to be used in the relocation's section offset. */ | |
13331 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13332 | { |
13333 | reloc->address = reloc->addend; | |
13334 | reloc->addend = 0; | |
13335 | } | |
13336 | ||
13337 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
13338 | fixup_segment converted a non-PC relative reloc into a PC | |
13339 | relative reloc. In such a case, we need to convert the reloc | |
13340 | code. */ | |
13341 | code = fixp->fx_r_type; | |
13342 | if (fixp->fx_pcrel) | |
13343 | { | |
13344 | switch (code) | |
13345 | { | |
13346 | case BFD_RELOC_8: | |
13347 | code = BFD_RELOC_8_PCREL; | |
13348 | break; | |
13349 | case BFD_RELOC_16: | |
13350 | code = BFD_RELOC_16_PCREL; | |
13351 | break; | |
13352 | case BFD_RELOC_32: | |
13353 | code = BFD_RELOC_32_PCREL; | |
13354 | break; | |
13355 | case BFD_RELOC_64: | |
13356 | code = BFD_RELOC_64_PCREL; | |
13357 | break; | |
13358 | case BFD_RELOC_8_PCREL: | |
13359 | case BFD_RELOC_16_PCREL: | |
13360 | case BFD_RELOC_32_PCREL: | |
13361 | case BFD_RELOC_64_PCREL: | |
13362 | case BFD_RELOC_16_PCREL_S2: | |
13363 | case BFD_RELOC_PCREL_HI16_S: | |
13364 | case BFD_RELOC_PCREL_LO16: | |
13365 | break; | |
13366 | default: | |
13367 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13368 | _("Cannot make %s relocation PC relative"), | |
13369 | bfd_get_reloc_code_name (code)); | |
13370 | } | |
13371 | } | |
13372 | ||
0b25d3e6 AO |
13373 | /* To support a PC relative reloc when generating embedded PIC code |
13374 | for ECOFF, we use a Cygnus extension. We check for that here to | |
13375 | make sure that we don't let such a reloc escape normally. */ | |
13376 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
13377 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13378 | && code == BFD_RELOC_16_PCREL_S2 | |
13379 | && mips_pic != EMBEDDED_PIC) | |
13380 | reloc->howto = NULL; | |
13381 | else | |
13382 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13383 | ||
252b5132 RH |
13384 | if (reloc->howto == NULL) |
13385 | { | |
13386 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13387 | _("Can not represent %s relocation in this object file format"), | |
13388 | bfd_get_reloc_code_name (code)); | |
13389 | retval[0] = NULL; | |
13390 | } | |
13391 | ||
13392 | return retval; | |
13393 | } | |
13394 | ||
13395 | /* Relax a machine dependent frag. This returns the amount by which | |
13396 | the current size of the frag should change. */ | |
13397 | ||
13398 | int | |
17a2f251 | 13399 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13400 | { |
4a6a3df4 AO |
13401 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13402 | { | |
13403 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13404 | |
13405 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13406 | |
13407 | return fragp->fr_var - old_var; | |
13408 | } | |
13409 | ||
252b5132 RH |
13410 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13411 | return 0; | |
13412 | ||
c4e7957c | 13413 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13414 | { |
13415 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13416 | return 0; | |
13417 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13418 | return 2; | |
13419 | } | |
13420 | else | |
13421 | { | |
13422 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13423 | return 0; | |
13424 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13425 | return -2; | |
13426 | } | |
13427 | ||
13428 | return 0; | |
13429 | } | |
13430 | ||
13431 | /* Convert a machine dependent frag. */ | |
13432 | ||
13433 | void | |
17a2f251 | 13434 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 RH |
13435 | { |
13436 | int old, new; | |
13437 | char *fixptr; | |
13438 | ||
4a6a3df4 AO |
13439 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13440 | { | |
13441 | bfd_byte *buf; | |
13442 | unsigned long insn; | |
13443 | expressionS exp; | |
13444 | fixS *fixp; | |
b34976b6 | 13445 | |
4a6a3df4 AO |
13446 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13447 | ||
13448 | if (target_big_endian) | |
13449 | insn = bfd_getb32 (buf); | |
13450 | else | |
13451 | insn = bfd_getl32 (buf); | |
b34976b6 | 13452 | |
4a6a3df4 AO |
13453 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13454 | { | |
13455 | /* We generate a fixup instead of applying it right now | |
13456 | because, if there are linker relaxations, we're going to | |
13457 | need the relocations. */ | |
13458 | exp.X_op = O_symbol; | |
13459 | exp.X_add_symbol = fragp->fr_symbol; | |
13460 | exp.X_add_number = fragp->fr_offset; | |
13461 | ||
13462 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13463 | 4, &exp, 1, |
13464 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13465 | fixp->fx_file = fragp->fr_file; |
13466 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13467 | |
17a2f251 | 13468 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13469 | buf += 4; |
13470 | } | |
13471 | else | |
13472 | { | |
13473 | int i; | |
13474 | ||
13475 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13476 | _("relaxed out-of-range branch into a jump")); | |
13477 | ||
13478 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13479 | goto uncond; | |
13480 | ||
13481 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13482 | { | |
13483 | /* Reverse the branch. */ | |
13484 | switch ((insn >> 28) & 0xf) | |
13485 | { | |
13486 | case 4: | |
13487 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13488 | have the condition reversed by tweaking a single | |
13489 | bit, and their opcodes all have 0x4???????. */ | |
13490 | assert ((insn & 0xf1000000) == 0x41000000); | |
13491 | insn ^= 0x00010000; | |
13492 | break; | |
13493 | ||
13494 | case 0: | |
13495 | /* bltz 0x04000000 bgez 0x04010000 | |
13496 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13497 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13498 | insn ^= 0x00010000; | |
13499 | break; | |
b34976b6 | 13500 | |
4a6a3df4 AO |
13501 | case 1: |
13502 | /* beq 0x10000000 bne 0x14000000 | |
13503 | blez 0x18000000 bgtz 0x1c000000 */ | |
13504 | insn ^= 0x04000000; | |
13505 | break; | |
13506 | ||
13507 | default: | |
13508 | abort (); | |
13509 | } | |
13510 | } | |
13511 | ||
13512 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13513 | { | |
13514 | /* Clear the and-link bit. */ | |
13515 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13516 | ||
13517 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13518 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13519 | insn &= ~0x00100000; | |
13520 | } | |
13521 | ||
13522 | /* Branch over the branch (if the branch was likely) or the | |
13523 | full jump (not likely case). Compute the offset from the | |
13524 | current instruction to branch to. */ | |
13525 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13526 | i = 16; | |
13527 | else | |
13528 | { | |
13529 | /* How many bytes in instructions we've already emitted? */ | |
13530 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13531 | /* How many bytes in instructions from here to the end? */ | |
13532 | i = fragp->fr_var - i; | |
13533 | } | |
13534 | /* Convert to instruction count. */ | |
13535 | i >>= 2; | |
13536 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13537 | i--; |
4a6a3df4 AO |
13538 | insn |= i; |
13539 | /* Branch over the jump. */ | |
17a2f251 | 13540 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13541 | buf += 4; |
13542 | ||
13543 | /* Nop */ | |
17a2f251 | 13544 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13545 | buf += 4; |
13546 | ||
13547 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13548 | { | |
13549 | /* beql $0, $0, 2f */ | |
13550 | insn = 0x50000000; | |
13551 | /* Compute the PC offset from the current instruction to | |
13552 | the end of the variable frag. */ | |
13553 | /* How many bytes in instructions we've already emitted? */ | |
13554 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13555 | /* How many bytes in instructions from here to the end? */ | |
13556 | i = fragp->fr_var - i; | |
13557 | /* Convert to instruction count. */ | |
13558 | i >>= 2; | |
13559 | /* Don't decrement i, because we want to branch over the | |
13560 | delay slot. */ | |
13561 | ||
13562 | insn |= i; | |
17a2f251 | 13563 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13564 | buf += 4; |
13565 | ||
17a2f251 | 13566 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13567 | buf += 4; |
13568 | } | |
13569 | ||
13570 | uncond: | |
13571 | if (mips_pic == NO_PIC) | |
13572 | { | |
13573 | /* j or jal. */ | |
13574 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13575 | ? 0x0c000000 : 0x08000000); | |
13576 | exp.X_op = O_symbol; | |
13577 | exp.X_add_symbol = fragp->fr_symbol; | |
13578 | exp.X_add_number = fragp->fr_offset; | |
13579 | ||
13580 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13581 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13582 | fixp->fx_file = fragp->fr_file; | |
13583 | fixp->fx_line = fragp->fr_line; | |
13584 | ||
17a2f251 | 13585 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13586 | buf += 4; |
13587 | } | |
13588 | else | |
13589 | { | |
13590 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13591 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13592 | exp.X_op = O_symbol; | |
13593 | exp.X_add_symbol = fragp->fr_symbol; | |
13594 | exp.X_add_number = fragp->fr_offset; | |
13595 | ||
13596 | if (fragp->fr_offset) | |
13597 | { | |
13598 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13599 | exp.X_add_number = 0; | |
13600 | } | |
13601 | ||
13602 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13603 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13604 | fixp->fx_file = fragp->fr_file; | |
13605 | fixp->fx_line = fragp->fr_line; | |
13606 | ||
17a2f251 | 13607 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 13608 | buf += 4; |
b34976b6 | 13609 | |
4a6a3df4 AO |
13610 | if (mips_opts.isa == ISA_MIPS1) |
13611 | { | |
13612 | /* nop */ | |
17a2f251 | 13613 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13614 | buf += 4; |
13615 | } | |
13616 | ||
13617 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13618 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13619 | ||
13620 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13621 | 4, &exp, 0, BFD_RELOC_LO16); | |
13622 | fixp->fx_file = fragp->fr_file; | |
13623 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13624 | |
17a2f251 | 13625 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13626 | buf += 4; |
13627 | ||
13628 | /* j(al)r $at. */ | |
13629 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13630 | insn = 0x0020f809; | |
13631 | else | |
13632 | insn = 0x00200008; | |
13633 | ||
17a2f251 | 13634 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13635 | buf += 4; |
13636 | } | |
13637 | } | |
13638 | ||
13639 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13640 | + fragp->fr_fix + fragp->fr_var); | |
13641 | ||
13642 | fragp->fr_fix += fragp->fr_var; | |
13643 | ||
13644 | return; | |
13645 | } | |
13646 | ||
252b5132 RH |
13647 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13648 | { | |
13649 | int type; | |
13650 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13651 | bfd_boolean small, ext; |
252b5132 RH |
13652 | offsetT val; |
13653 | bfd_byte *buf; | |
13654 | unsigned long insn; | |
b34976b6 | 13655 | bfd_boolean use_extend; |
252b5132 RH |
13656 | unsigned short extend; |
13657 | ||
13658 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13659 | op = mips16_immed_operands; | |
13660 | while (op->type != type) | |
13661 | ++op; | |
13662 | ||
13663 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13664 | { | |
b34976b6 AM |
13665 | small = FALSE; |
13666 | ext = TRUE; | |
252b5132 RH |
13667 | } |
13668 | else | |
13669 | { | |
b34976b6 AM |
13670 | small = TRUE; |
13671 | ext = FALSE; | |
252b5132 RH |
13672 | } |
13673 | ||
6386f3a7 | 13674 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13675 | val = S_GET_VALUE (fragp->fr_symbol); |
13676 | if (op->pcrel) | |
13677 | { | |
13678 | addressT addr; | |
13679 | ||
13680 | addr = fragp->fr_address + fragp->fr_fix; | |
13681 | ||
13682 | /* The rules for the base address of a PC relative reloc are | |
13683 | complicated; see mips16_extended_frag. */ | |
13684 | if (type == 'p' || type == 'q') | |
13685 | { | |
13686 | addr += 2; | |
13687 | if (ext) | |
13688 | addr += 2; | |
13689 | /* Ignore the low bit in the target, since it will be | |
13690 | set for a text label. */ | |
13691 | if ((val & 1) != 0) | |
13692 | --val; | |
13693 | } | |
13694 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13695 | addr -= 4; | |
13696 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13697 | addr -= 2; | |
13698 | ||
13699 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13700 | val -= addr; | |
13701 | ||
13702 | /* Make sure the section winds up with the alignment we have | |
13703 | assumed. */ | |
13704 | if (op->shift > 0) | |
13705 | record_alignment (asec, op->shift); | |
13706 | } | |
13707 | ||
13708 | if (ext | |
13709 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13710 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13711 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13712 | _("extended instruction in delay slot")); | |
13713 | ||
13714 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13715 | ||
13716 | if (target_big_endian) | |
13717 | insn = bfd_getb16 (buf); | |
13718 | else | |
13719 | insn = bfd_getl16 (buf); | |
13720 | ||
13721 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13722 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13723 | small, ext, &insn, &use_extend, &extend); | |
13724 | ||
13725 | if (use_extend) | |
13726 | { | |
17a2f251 | 13727 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13728 | fragp->fr_fix += 2; |
13729 | buf += 2; | |
13730 | } | |
13731 | ||
17a2f251 | 13732 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13733 | fragp->fr_fix += 2; |
13734 | buf += 2; | |
13735 | } | |
13736 | else | |
13737 | { | |
13738 | if (fragp->fr_opcode == NULL) | |
13739 | return; | |
13740 | ||
13741 | old = RELAX_OLD (fragp->fr_subtype); | |
13742 | new = RELAX_NEW (fragp->fr_subtype); | |
13743 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
13744 | ||
13745 | if (new > 0) | |
f5040a92 | 13746 | memmove (fixptr - old, fixptr, new); |
252b5132 RH |
13747 | |
13748 | fragp->fr_fix += new - old; | |
13749 | } | |
13750 | } | |
13751 | ||
13752 | #ifdef OBJ_ELF | |
13753 | ||
13754 | /* This function is called after the relocs have been generated. | |
13755 | We've been storing mips16 text labels as odd. Here we convert them | |
13756 | back to even for the convenience of the debugger. */ | |
13757 | ||
13758 | void | |
17a2f251 | 13759 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13760 | { |
13761 | asymbol **syms; | |
13762 | unsigned int count, i; | |
13763 | ||
13764 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13765 | return; | |
13766 | ||
13767 | syms = bfd_get_outsymbols (stdoutput); | |
13768 | count = bfd_get_symcount (stdoutput); | |
13769 | for (i = 0; i < count; i++, syms++) | |
13770 | { | |
13771 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13772 | && ((*syms)->value & 1) != 0) | |
13773 | { | |
13774 | (*syms)->value &= ~1; | |
13775 | /* If the symbol has an odd size, it was probably computed | |
13776 | incorrectly, so adjust that as well. */ | |
13777 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13778 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13779 | } | |
13780 | } | |
13781 | } | |
13782 | ||
13783 | #endif | |
13784 | ||
13785 | /* This function is called whenever a label is defined. It is used | |
13786 | when handling branch delays; if a branch has a label, we assume we | |
13787 | can not move it. */ | |
13788 | ||
13789 | void | |
17a2f251 | 13790 | mips_define_label (symbolS *sym) |
252b5132 RH |
13791 | { |
13792 | struct insn_label_list *l; | |
13793 | ||
13794 | if (free_insn_labels == NULL) | |
13795 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13796 | else | |
13797 | { | |
13798 | l = free_insn_labels; | |
13799 | free_insn_labels = l->next; | |
13800 | } | |
13801 | ||
13802 | l->label = sym; | |
13803 | l->next = insn_labels; | |
13804 | insn_labels = l; | |
13805 | } | |
13806 | \f | |
13807 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13808 | ||
13809 | /* Some special processing for a MIPS ELF file. */ | |
13810 | ||
13811 | void | |
17a2f251 | 13812 | mips_elf_final_processing (void) |
252b5132 RH |
13813 | { |
13814 | /* Write out the register information. */ | |
316f5878 | 13815 | if (mips_abi != N64_ABI) |
252b5132 RH |
13816 | { |
13817 | Elf32_RegInfo s; | |
13818 | ||
13819 | s.ri_gprmask = mips_gprmask; | |
13820 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13821 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13822 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13823 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13824 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13825 | ||
13826 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13827 | ((Elf32_External_RegInfo *) | |
13828 | mips_regmask_frag)); | |
13829 | } | |
13830 | else | |
13831 | { | |
13832 | Elf64_Internal_RegInfo s; | |
13833 | ||
13834 | s.ri_gprmask = mips_gprmask; | |
13835 | s.ri_pad = 0; | |
13836 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13837 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13838 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13839 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13840 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13841 | ||
13842 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13843 | ((Elf64_External_RegInfo *) | |
13844 | mips_regmask_frag)); | |
13845 | } | |
13846 | ||
13847 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13848 | sort of BFD interface for this. */ | |
13849 | if (mips_any_noreorder) | |
13850 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13851 | if (mips_pic != NO_PIC) | |
143d77c5 | 13852 | { |
252b5132 | 13853 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13854 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13855 | } | |
13856 | if (mips_abicalls) | |
13857 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13858 | |
98d3f06f | 13859 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13860 | if (file_ase_mips16) |
13861 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13862 | #if 0 /* XXX FIXME */ |
13863 | if (file_ase_mips3d) | |
13864 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13865 | #endif | |
deec1734 CD |
13866 | if (file_ase_mdmx) |
13867 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13868 | |
bdaaa2e1 | 13869 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13870 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13871 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13872 | else if (mips_abi == O64_ABI) |
252b5132 | 13873 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13874 | else if (mips_abi == EABI_ABI) |
252b5132 | 13875 | { |
316f5878 | 13876 | if (!file_mips_gp32) |
252b5132 RH |
13877 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13878 | else | |
13879 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13880 | } | |
316f5878 | 13881 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13882 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13883 | ||
c9914766 | 13884 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13885 | |
13886 | if (mips_32bitmode) | |
13887 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13888 | } | |
13889 | ||
13890 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13891 | \f | |
beae10d5 KH |
13892 | typedef struct proc { |
13893 | symbolS *isym; | |
13894 | unsigned long reg_mask; | |
13895 | unsigned long reg_offset; | |
13896 | unsigned long fpreg_mask; | |
13897 | unsigned long fpreg_offset; | |
13898 | unsigned long frame_offset; | |
13899 | unsigned long frame_reg; | |
13900 | unsigned long pc_reg; | |
13901 | } procS; | |
252b5132 RH |
13902 | |
13903 | static procS cur_proc; | |
13904 | static procS *cur_proc_ptr; | |
13905 | static int numprocs; | |
13906 | ||
0a9ef439 | 13907 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13908 | |
0a9ef439 | 13909 | void |
17a2f251 | 13910 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13911 | { |
0a9ef439 RH |
13912 | if (fragp->fr_type != rs_align_code) |
13913 | return; | |
13914 | ||
13915 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13916 | { |
13917 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13918 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13919 | ||
0a9ef439 RH |
13920 | int bytes; |
13921 | char *p; | |
a19d8eb0 | 13922 | |
0a9ef439 RH |
13923 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13924 | p = fragp->fr_literal + fragp->fr_fix; | |
13925 | ||
13926 | if (bytes & 1) | |
13927 | { | |
13928 | *p++ = 0; | |
f9419b05 | 13929 | fragp->fr_fix++; |
0a9ef439 RH |
13930 | } |
13931 | ||
13932 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13933 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13934 | } |
13935 | ||
0a9ef439 | 13936 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13937 | } |
13938 | ||
252b5132 | 13939 | static void |
17a2f251 | 13940 | md_obj_begin (void) |
252b5132 RH |
13941 | { |
13942 | } | |
13943 | ||
13944 | static void | |
17a2f251 | 13945 | md_obj_end (void) |
252b5132 RH |
13946 | { |
13947 | /* check for premature end, nesting errors, etc */ | |
13948 | if (cur_proc_ptr) | |
9a41af64 | 13949 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13950 | } |
13951 | ||
13952 | static long | |
17a2f251 | 13953 | get_number (void) |
252b5132 RH |
13954 | { |
13955 | int negative = 0; | |
13956 | long val = 0; | |
13957 | ||
13958 | if (*input_line_pointer == '-') | |
13959 | { | |
13960 | ++input_line_pointer; | |
13961 | negative = 1; | |
13962 | } | |
3882b010 | 13963 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13964 | as_bad (_("expected simple number")); |
252b5132 RH |
13965 | if (input_line_pointer[0] == '0') |
13966 | { | |
13967 | if (input_line_pointer[1] == 'x') | |
13968 | { | |
13969 | input_line_pointer += 2; | |
3882b010 | 13970 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13971 | { |
13972 | val <<= 4; | |
13973 | val |= hex_value (*input_line_pointer++); | |
13974 | } | |
13975 | return negative ? -val : val; | |
13976 | } | |
13977 | else | |
13978 | { | |
13979 | ++input_line_pointer; | |
3882b010 | 13980 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13981 | { |
13982 | val <<= 3; | |
13983 | val |= *input_line_pointer++ - '0'; | |
13984 | } | |
13985 | return negative ? -val : val; | |
13986 | } | |
13987 | } | |
3882b010 | 13988 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13989 | { |
13990 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13991 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13992 | as_warn (_("invalid number")); |
252b5132 RH |
13993 | return -1; |
13994 | } | |
3882b010 | 13995 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13996 | { |
13997 | val *= 10; | |
13998 | val += *input_line_pointer++ - '0'; | |
13999 | } | |
14000 | return negative ? -val : val; | |
14001 | } | |
14002 | ||
14003 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14004 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14005 | case .file implies DWARF-2. */ | |
14006 | ||
14007 | static void | |
17a2f251 | 14008 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14009 | { |
ecb4347a DJ |
14010 | static int first_file_directive = 0; |
14011 | ||
c5dd6aab DJ |
14012 | if (ECOFF_DEBUGGING) |
14013 | { | |
14014 | get_number (); | |
14015 | s_app_file (0); | |
14016 | } | |
14017 | else | |
ecb4347a DJ |
14018 | { |
14019 | char *filename; | |
14020 | ||
14021 | filename = dwarf2_directive_file (0); | |
14022 | ||
14023 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14024 | directive even for stabs output. Make sure that this | |
14025 | ".file" is handled. Note that you need a version of GCC | |
14026 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14027 | if (filename != NULL && ! first_file_directive) | |
14028 | { | |
14029 | (void) new_logical_line (filename, -1); | |
14030 | s_app_file_string (filename); | |
14031 | } | |
14032 | first_file_directive = 1; | |
14033 | } | |
c5dd6aab DJ |
14034 | } |
14035 | ||
14036 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14037 | |
14038 | static void | |
17a2f251 | 14039 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14040 | { |
c5dd6aab DJ |
14041 | if (!ECOFF_DEBUGGING) |
14042 | dwarf2_directive_loc (0); | |
252b5132 RH |
14043 | } |
14044 | ||
252b5132 RH |
14045 | /* The .end directive. */ |
14046 | ||
14047 | static void | |
17a2f251 | 14048 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14049 | { |
14050 | symbolS *p; | |
252b5132 | 14051 | |
7a621144 DJ |
14052 | /* Following functions need their own .frame and .cprestore directives. */ |
14053 | mips_frame_reg_valid = 0; | |
14054 | mips_cprestore_valid = 0; | |
14055 | ||
252b5132 RH |
14056 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14057 | { | |
14058 | p = get_symbol (); | |
14059 | demand_empty_rest_of_line (); | |
14060 | } | |
14061 | else | |
14062 | p = NULL; | |
14063 | ||
14949570 | 14064 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14065 | as_warn (_(".end not in text section")); |
14066 | ||
14067 | if (!cur_proc_ptr) | |
14068 | { | |
14069 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14070 | demand_empty_rest_of_line (); | |
14071 | return; | |
14072 | } | |
14073 | ||
14074 | if (p != NULL) | |
14075 | { | |
14076 | assert (S_GET_NAME (p)); | |
14077 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
14078 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
14079 | |
14080 | if (debug_type == DEBUG_STABS) | |
14081 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14082 | S_GET_NAME (p)); | |
252b5132 RH |
14083 | } |
14084 | else | |
14085 | as_warn (_(".end directive missing or unknown symbol")); | |
14086 | ||
ecb4347a DJ |
14087 | #ifdef OBJ_ELF |
14088 | /* Generate a .pdr section. */ | |
dcd410fe RO |
14089 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
14090 | && mips_flag_pdr) | |
ecb4347a DJ |
14091 | { |
14092 | segT saved_seg = now_seg; | |
14093 | subsegT saved_subseg = now_subseg; | |
14094 | valueT dot; | |
14095 | expressionS exp; | |
14096 | char *fragp; | |
252b5132 | 14097 | |
ecb4347a | 14098 | dot = frag_now_fix (); |
252b5132 RH |
14099 | |
14100 | #ifdef md_flush_pending_output | |
ecb4347a | 14101 | md_flush_pending_output (); |
252b5132 RH |
14102 | #endif |
14103 | ||
ecb4347a DJ |
14104 | assert (pdr_seg); |
14105 | subseg_set (pdr_seg, 0); | |
252b5132 | 14106 | |
ecb4347a DJ |
14107 | /* Write the symbol. */ |
14108 | exp.X_op = O_symbol; | |
14109 | exp.X_add_symbol = p; | |
14110 | exp.X_add_number = 0; | |
14111 | emit_expr (&exp, 4); | |
252b5132 | 14112 | |
ecb4347a | 14113 | fragp = frag_more (7 * 4); |
252b5132 | 14114 | |
17a2f251 TS |
14115 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14116 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14117 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14118 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14119 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14120 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14121 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14122 | |
ecb4347a DJ |
14123 | subseg_set (saved_seg, saved_subseg); |
14124 | } | |
14125 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14126 | |
14127 | cur_proc_ptr = NULL; | |
14128 | } | |
14129 | ||
14130 | /* The .aent and .ent directives. */ | |
14131 | ||
14132 | static void | |
17a2f251 | 14133 | s_mips_ent (int aent) |
252b5132 | 14134 | { |
252b5132 | 14135 | symbolS *symbolP; |
252b5132 RH |
14136 | |
14137 | symbolP = get_symbol (); | |
14138 | if (*input_line_pointer == ',') | |
f9419b05 | 14139 | ++input_line_pointer; |
252b5132 | 14140 | SKIP_WHITESPACE (); |
3882b010 | 14141 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14142 | || *input_line_pointer == '-') |
874e8986 | 14143 | get_number (); |
252b5132 | 14144 | |
14949570 | 14145 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14146 | as_warn (_(".ent or .aent not in text section.")); |
14147 | ||
14148 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14149 | as_warn (_("missing .end")); |
252b5132 RH |
14150 | |
14151 | if (!aent) | |
14152 | { | |
7a621144 DJ |
14153 | /* This function needs its own .frame and .cprestore directives. */ |
14154 | mips_frame_reg_valid = 0; | |
14155 | mips_cprestore_valid = 0; | |
14156 | ||
252b5132 RH |
14157 | cur_proc_ptr = &cur_proc; |
14158 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14159 | ||
14160 | cur_proc_ptr->isym = symbolP; | |
14161 | ||
49309057 | 14162 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14163 | |
f9419b05 | 14164 | ++numprocs; |
ecb4347a DJ |
14165 | |
14166 | if (debug_type == DEBUG_STABS) | |
14167 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14168 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14169 | } |
14170 | ||
14171 | demand_empty_rest_of_line (); | |
14172 | } | |
14173 | ||
14174 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14175 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14176 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14177 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14178 | symbol table (in the mdebug section). */ |
14179 | ||
14180 | static void | |
17a2f251 | 14181 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14182 | { |
ecb4347a DJ |
14183 | #ifdef OBJ_ELF |
14184 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14185 | { | |
14186 | long val; | |
252b5132 | 14187 | |
ecb4347a DJ |
14188 | if (cur_proc_ptr == (procS *) NULL) |
14189 | { | |
14190 | as_warn (_(".frame outside of .ent")); | |
14191 | demand_empty_rest_of_line (); | |
14192 | return; | |
14193 | } | |
252b5132 | 14194 | |
ecb4347a DJ |
14195 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14196 | ||
14197 | SKIP_WHITESPACE (); | |
14198 | if (*input_line_pointer++ != ',' | |
14199 | || get_absolute_expression_and_terminator (&val) != ',') | |
14200 | { | |
14201 | as_warn (_("Bad .frame directive")); | |
14202 | --input_line_pointer; | |
14203 | demand_empty_rest_of_line (); | |
14204 | return; | |
14205 | } | |
252b5132 | 14206 | |
ecb4347a DJ |
14207 | cur_proc_ptr->frame_offset = val; |
14208 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14209 | |
252b5132 | 14210 | demand_empty_rest_of_line (); |
252b5132 | 14211 | } |
ecb4347a DJ |
14212 | else |
14213 | #endif /* OBJ_ELF */ | |
14214 | s_ignore (ignore); | |
252b5132 RH |
14215 | } |
14216 | ||
bdaaa2e1 KH |
14217 | /* The .fmask and .mask directives. If the mdebug section is present |
14218 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14219 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14220 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14221 | make reference to the ecoff symbol table (in the mdebug section). */ |
14222 | ||
14223 | static void | |
17a2f251 | 14224 | s_mips_mask (int reg_type) |
252b5132 | 14225 | { |
ecb4347a DJ |
14226 | #ifdef OBJ_ELF |
14227 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14228 | { |
ecb4347a | 14229 | long mask, off; |
252b5132 | 14230 | |
ecb4347a DJ |
14231 | if (cur_proc_ptr == (procS *) NULL) |
14232 | { | |
14233 | as_warn (_(".mask/.fmask outside of .ent")); | |
14234 | demand_empty_rest_of_line (); | |
14235 | return; | |
14236 | } | |
252b5132 | 14237 | |
ecb4347a DJ |
14238 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14239 | { | |
14240 | as_warn (_("Bad .mask/.fmask directive")); | |
14241 | --input_line_pointer; | |
14242 | demand_empty_rest_of_line (); | |
14243 | return; | |
14244 | } | |
252b5132 | 14245 | |
ecb4347a DJ |
14246 | off = get_absolute_expression (); |
14247 | ||
14248 | if (reg_type == 'F') | |
14249 | { | |
14250 | cur_proc_ptr->fpreg_mask = mask; | |
14251 | cur_proc_ptr->fpreg_offset = off; | |
14252 | } | |
14253 | else | |
14254 | { | |
14255 | cur_proc_ptr->reg_mask = mask; | |
14256 | cur_proc_ptr->reg_offset = off; | |
14257 | } | |
14258 | ||
14259 | demand_empty_rest_of_line (); | |
252b5132 RH |
14260 | } |
14261 | else | |
ecb4347a DJ |
14262 | #endif /* OBJ_ELF */ |
14263 | s_ignore (reg_type); | |
252b5132 RH |
14264 | } |
14265 | ||
14266 | /* The .loc directive. */ | |
14267 | ||
14268 | #if 0 | |
14269 | static void | |
17a2f251 | 14270 | s_loc (int x) |
252b5132 RH |
14271 | { |
14272 | symbolS *symbolP; | |
14273 | int lineno; | |
14274 | int addroff; | |
14275 | ||
14276 | assert (now_seg == text_section); | |
14277 | ||
14278 | lineno = get_number (); | |
14279 | addroff = frag_now_fix (); | |
14280 | ||
14281 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
14282 | S_SET_TYPE (symbolP, N_SLINE); | |
14283 | S_SET_OTHER (symbolP, 0); | |
14284 | S_SET_DESC (symbolP, lineno); | |
14285 | symbolP->sy_segment = now_seg; | |
14286 | } | |
14287 | #endif | |
e7af610e | 14288 | |
316f5878 RS |
14289 | /* A table describing all the processors gas knows about. Names are |
14290 | matched in the order listed. | |
e7af610e | 14291 | |
316f5878 RS |
14292 | To ease comparison, please keep this table in the same order as |
14293 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14294 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14295 | { | |
316f5878 RS |
14296 | /* Entries for generic ISAs */ |
14297 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14298 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14299 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14300 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14301 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14302 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14303 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 RS |
14304 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
14305 | ||
14306 | /* MIPS I */ | |
14307 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14308 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14309 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14310 | ||
14311 | /* MIPS II */ | |
14312 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14313 | ||
14314 | /* MIPS III */ | |
14315 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14316 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14317 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14318 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14319 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14320 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14321 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14322 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14323 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14324 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14325 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14326 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14327 | ||
14328 | /* MIPS IV */ | |
14329 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14330 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14331 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14332 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14333 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14334 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14335 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14336 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14337 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14338 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14339 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 RS |
14340 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
14341 | { "rm9000", 0, ISA_MIPS4, CPU_RM7000 }, | |
316f5878 RS |
14342 | |
14343 | /* MIPS 32 */ | |
fef14a42 | 14344 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
14345 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
14346 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14347 | |
316f5878 RS |
14348 | /* MIPS 64 */ |
14349 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14350 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 14351 | |
c7a23324 | 14352 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14353 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14354 | |
316f5878 RS |
14355 | /* End marker */ |
14356 | { NULL, 0, 0, 0 } | |
14357 | }; | |
e7af610e | 14358 | |
84ea6cf2 | 14359 | |
316f5878 RS |
14360 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14361 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14362 | |
316f5878 | 14363 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14364 | |
b34976b6 | 14365 | static bfd_boolean |
17a2f251 | 14366 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14367 | { |
14368 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14369 | given++, canonical++; | |
14370 | ||
14371 | return ((*given == 0 && *canonical == 0) | |
14372 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14373 | } | |
14374 | ||
14375 | ||
14376 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14377 | CPU name. We've traditionally allowed a lot of variation here. | |
14378 | ||
14379 | Note: this function is shared between GCC and GAS. */ | |
14380 | ||
b34976b6 | 14381 | static bfd_boolean |
17a2f251 | 14382 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14383 | { |
14384 | /* First see if the name matches exactly, or with a final "000" | |
14385 | turned into "k". */ | |
14386 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14387 | return TRUE; |
316f5878 RS |
14388 | |
14389 | /* If not, try comparing based on numerical designation alone. | |
14390 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14391 | if (TOLOWER (*given) == 'r') | |
14392 | given++; | |
14393 | if (!ISDIGIT (*given)) | |
b34976b6 | 14394 | return FALSE; |
316f5878 RS |
14395 | |
14396 | /* Skip over some well-known prefixes in the canonical name, | |
14397 | hoping to find a number there too. */ | |
14398 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14399 | canonical += 2; | |
14400 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14401 | canonical += 2; | |
14402 | else if (TOLOWER (canonical[0]) == 'r') | |
14403 | canonical += 1; | |
14404 | ||
14405 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14406 | } | |
14407 | ||
14408 | ||
14409 | /* Parse an option that takes the name of a processor as its argument. | |
14410 | OPTION is the name of the option and CPU_STRING is the argument. | |
14411 | Return the corresponding processor enumeration if the CPU_STRING is | |
14412 | recognized, otherwise report an error and return null. | |
14413 | ||
14414 | A similar function exists in GCC. */ | |
e7af610e NC |
14415 | |
14416 | static const struct mips_cpu_info * | |
17a2f251 | 14417 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14418 | { |
316f5878 | 14419 | const struct mips_cpu_info *p; |
e7af610e | 14420 | |
316f5878 RS |
14421 | /* 'from-abi' selects the most compatible architecture for the given |
14422 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14423 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14424 | version. Look first at the -mgp options, if given, otherwise base | |
14425 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14426 | |
316f5878 RS |
14427 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14428 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14429 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14430 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14431 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14432 | { | |
14433 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14434 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14435 | ||
14436 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14437 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14438 | ||
14439 | if (file_mips_gp32 >= 0) | |
14440 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14441 | ||
14442 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14443 | ? ISA_MIPS3 | |
14444 | : ISA_MIPS1); | |
14445 | } | |
14446 | ||
14447 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14448 | if (strcasecmp (cpu_string, "default") == 0) | |
14449 | return 0; | |
14450 | ||
14451 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14452 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14453 | return p; | |
14454 | ||
14455 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14456 | return 0; | |
e7af610e NC |
14457 | } |
14458 | ||
316f5878 RS |
14459 | /* Return the canonical processor information for ISA (a member of the |
14460 | ISA_MIPS* enumeration). */ | |
14461 | ||
e7af610e | 14462 | static const struct mips_cpu_info * |
17a2f251 | 14463 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14464 | { |
14465 | int i; | |
14466 | ||
14467 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14468 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14469 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14470 | return (&mips_cpu_info_table[i]); |
14471 | ||
e972090a | 14472 | return NULL; |
e7af610e | 14473 | } |
fef14a42 TS |
14474 | |
14475 | static const struct mips_cpu_info * | |
17a2f251 | 14476 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14477 | { |
14478 | int i; | |
14479 | ||
14480 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14481 | if (arch == mips_cpu_info_table[i].cpu) | |
14482 | return (&mips_cpu_info_table[i]); | |
14483 | ||
14484 | return NULL; | |
14485 | } | |
316f5878 RS |
14486 | \f |
14487 | static void | |
17a2f251 | 14488 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14489 | { |
14490 | if (*first_p) | |
14491 | { | |
14492 | fprintf (stream, "%24s", ""); | |
14493 | *col_p = 24; | |
14494 | } | |
14495 | else | |
14496 | { | |
14497 | fprintf (stream, ", "); | |
14498 | *col_p += 2; | |
14499 | } | |
e7af610e | 14500 | |
316f5878 RS |
14501 | if (*col_p + strlen (string) > 72) |
14502 | { | |
14503 | fprintf (stream, "\n%24s", ""); | |
14504 | *col_p = 24; | |
14505 | } | |
14506 | ||
14507 | fprintf (stream, "%s", string); | |
14508 | *col_p += strlen (string); | |
14509 | ||
14510 | *first_p = 0; | |
14511 | } | |
14512 | ||
14513 | void | |
17a2f251 | 14514 | md_show_usage (FILE *stream) |
e7af610e | 14515 | { |
316f5878 RS |
14516 | int column, first; |
14517 | size_t i; | |
14518 | ||
14519 | fprintf (stream, _("\ | |
14520 | MIPS options:\n\ | |
14521 | -membedded-pic generate embedded position independent code\n\ | |
14522 | -EB generate big endian output\n\ | |
14523 | -EL generate little endian output\n\ | |
14524 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14525 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14526 | implicitly with the gp register [default 8]\n")); | |
14527 | fprintf (stream, _("\ | |
14528 | -mips1 generate MIPS ISA I instructions\n\ | |
14529 | -mips2 generate MIPS ISA II instructions\n\ | |
14530 | -mips3 generate MIPS ISA III instructions\n\ | |
14531 | -mips4 generate MIPS ISA IV instructions\n\ | |
14532 | -mips5 generate MIPS ISA V instructions\n\ | |
14533 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14534 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 RS |
14535 | -mips64 generate MIPS64 ISA instructions\n\ |
14536 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); | |
14537 | ||
14538 | first = 1; | |
e7af610e NC |
14539 | |
14540 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14541 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14542 | show (stream, "from-abi", &column, &first); | |
14543 | fputc ('\n', stream); | |
e7af610e | 14544 | |
316f5878 RS |
14545 | fprintf (stream, _("\ |
14546 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14547 | -no-mCPU don't generate code specific to CPU.\n\ | |
14548 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14549 | ||
14550 | first = 1; | |
14551 | ||
14552 | show (stream, "3900", &column, &first); | |
14553 | show (stream, "4010", &column, &first); | |
14554 | show (stream, "4100", &column, &first); | |
14555 | show (stream, "4650", &column, &first); | |
14556 | fputc ('\n', stream); | |
14557 | ||
14558 | fprintf (stream, _("\ | |
14559 | -mips16 generate mips16 instructions\n\ | |
14560 | -no-mips16 do not generate mips16 instructions\n")); | |
14561 | fprintf (stream, _("\ | |
14562 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ | |
14563 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14564 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14565 | -O remove unneeded NOPs and swap branches\n\ | |
14566 | -n warn about NOPs generated from macros\n\ | |
14567 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ | |
14568 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14569 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14570 | #ifdef OBJ_ELF | |
14571 | fprintf (stream, _("\ | |
14572 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14573 | -non_shared do not generate position independent code\n\ | |
14574 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14575 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14576 | -mabi=ABI create ABI conformant object file for:\n")); |
14577 | ||
14578 | first = 1; | |
14579 | ||
14580 | show (stream, "32", &column, &first); | |
14581 | show (stream, "o64", &column, &first); | |
14582 | show (stream, "n32", &column, &first); | |
14583 | show (stream, "64", &column, &first); | |
14584 | show (stream, "eabi", &column, &first); | |
14585 | ||
14586 | fputc ('\n', stream); | |
14587 | ||
14588 | fprintf (stream, _("\ | |
14589 | -32 create o32 ABI object file (default)\n\ | |
14590 | -n32 create n32 ABI object file\n\ | |
14591 | -64 create 64 ABI object file\n")); | |
14592 | #endif | |
e7af610e | 14593 | } |
14e777e0 KB |
14594 | |
14595 | enum dwarf2_format | |
17a2f251 | 14596 | mips_dwarf2_format (void) |
14e777e0 KB |
14597 | { |
14598 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14599 | { |
14600 | #ifdef TE_IRIX | |
14601 | return dwarf2_format_64bit_irix; | |
14602 | #else | |
14603 | return dwarf2_format_64bit; | |
14604 | #endif | |
14605 | } | |
14e777e0 KB |
14606 | else |
14607 | return dwarf2_format_32bit; | |
14608 | } |