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* config/tc-hppa.c (call_info struct): Delete unused "frame" field.
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
CommitLineData
3d3c5039
ILT		 1/* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
8358c818
ILT		 5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
6 Support.
3d3c5039
ILT		 7
8 This file is part of GAS.
9
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23
24#include "as.h"
8358c818 25#include "config.h"
3d3c5039
ILT		 26
27#include <ctype.h>
28
29#ifndef __STDC__
30#ifndef NO_STDARG
31#define NO_STDARG
32#endif
33#endif
34
35#ifndef NO_STDARG
36#include <stdarg.h>
37#else
38#ifndef NO_VARARGS
39#include <varargs.h>
40#endif /* NO_VARARGS */
41#endif /* NO_STDARG */
42
918692a5 43#include "opcode/mips.h"
3d3c5039 44
f2a663d3
ILT		 45#ifdef OBJ_ELF
46#include "elf/mips.h"
47
48static char *mips_regmask_frag;
49#endif
50
3d3c5039 51#define AT 1
670a50eb 52#define GP 28
3d3c5039
ILT		 53#define RA 31
54
88225433
ILT		 55/* Decide whether to do GP reference optimizations based on the object
56 file format. */
57#undef GPOPT
58#ifdef OBJ_ECOFF
59#define GPOPT
60#endif
61#ifdef OBJ_ELF
62#define GPOPT
63#endif
64
1aa6938e
ILT		 65/* These variables are filled in with the masks of registers used.
66 The object format code reads them and puts them in the appropriate
67 place. */
68unsigned long mips_gprmask;
69unsigned long mips_cprmask[4];
70
8358c818
ILT		 71/* MIPS ISA (Instruction Set Architecture) level. */
72static int mips_isa = -1;
73
3d3c5039
ILT		 74static int mips_warn_about_macros;
75static int mips_noreorder;
76static int mips_nomove;
77static int mips_noat;
78static int mips_nobopt;
79
88225433 80#ifdef GPOPT
670a50eb
ILT		 81/* The size of the small data section. */
82static int g_switch_value = 8;
83#endif
84
3d3c5039
ILT		 85#define N_RMASK 0xc4
86#define N_VFP 0xd4
87
88/* handle of the OPCODE hash table */
89static struct hash_control *op_hash = NULL;
90
91/* This array holds the chars that always start a comment. If the
92 pre-processor is disabled, these aren't very useful */
93const char comment_chars[] = "#";
94
95/* This array holds the chars that only start a comment at the beginning of
96 a line. If the line seems to have the form '# 123 filename'
97 .line and .file directives will appear in the pre-processed output */
98/* Note that input_file.c hand checks for '#' at the beginning of the
99 first line of the input file. This is because the compiler outputs
100 #NO_APP at the beginning of its output. */
101/* Also note that C style comments are always supported. */
102const char line_comment_chars[] = "#";
103
104/* This array holds machine specific line separator characters. */
105const char line_separator_chars[] = "";
106
107/* Chars that can be used to separate mant from exp in floating point nums */
108const char EXP_CHARS[] = "eE";
109
110/* Chars that mean this number is a floating point constant */
111/* As in 0f12.456 */
112/* or 0d1.2345e12 */
113const char FLT_CHARS[] = "rRsSfFdDxXpP";
114
115/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
116 changed in read.c . Ideally it shouldn't have to know about it at all,
117 but nothing is ideal around here.
118 */
119
670a50eb 120static char *insn_error;
3d3c5039
ILT		 121
122static int byte_order = BYTE_ORDER;
123
124static int auto_align = 1;
becfe05e
ILT		 125
126/* Symbol labelling the current insn. */
127static symbolS *insn_label;
128
129/* To output NOP instructions correctly, we need to keep information
130 about the previous two instructions. */
131
0aa07269
ILT		 132/* Whether we are optimizing. The default value of 2 means to remove
133 unneeded NOPs and swap branch instructions when possible. A value
134 of 1 means to not swap branches. A value of 0 means to always
135 insert NOPs. */
136static int mips_optimize = 2;
4e95866e 137
becfe05e
ILT		 138/* The previous instruction. */
139static struct mips_cl_insn prev_insn;
140
141/* The instruction before prev_insn. */
142static struct mips_cl_insn prev_prev_insn;
143
144/* If we don't want information for prev_insn or prev_prev_insn, we
145 point the insn_mo field at this dummy integer. */
146static const struct mips_opcode dummy_opcode = { 0 };
147
148/* Non-zero if prev_insn is valid. */
149static int prev_insn_valid;
150
151/* The frag for the previous instruction. */
152static struct frag *prev_insn_frag;
153
154/* The offset into prev_insn_frag for the previous instruction. */
155static long prev_insn_where;
156
157/* The reloc for the previous instruction, if any. */
158static fixS *prev_insn_fixp;
159
160/* Non-zero if the previous instruction was in a delay slot. */
161static int prev_insn_is_delay_slot;
4e95866e
ILT		 162
163/* Non-zero if the previous instruction was in a .set noreorder. */
164static int prev_insn_unreordered;
165
166/* Non-zero if the previous previous instruction was in a .set
167 noreorder. */
168static int prev_prev_insn_unreordered;
3d3c5039
ILT		 169\f
170/* Prototypes for static functions. */
171
172#ifdef __STDC__
173#define internalError() \
174 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
175#else
176#define internalError() as_fatal ("MIPS internal Error");
177#endif
178
becfe05e 179static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
604633ae 180 unsigned int reg, int fpr));
670a50eb
ILT		 181static void append_insn PARAMS ((struct mips_cl_insn * ip,
182 expressionS * p,
3d3c5039 183 bfd_reloc_code_real_type r));
becfe05e
ILT		 184static void mips_no_prev_insn PARAMS ((void));
185static void mips_emit_delays PARAMS ((void));
670a50eb
ILT		 186static int gp_reference PARAMS ((expressionS * ep));
187static void macro_build PARAMS ((int *counter, expressionS * ep,
3d3c5039
ILT		 188 const char *name, const char *fmt,
189 ...));
670a50eb 190static void macro_build_lui PARAMS ((int *counter, expressionS * ep,
3d3c5039 191 int regnum));
6e8dda9c 192static void set_at PARAMS ((int *counter, int reg, int unsignedp));
670a50eb 193static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
19ed8960 194 expressionS *));
3d3c5039 195static void load_register PARAMS ((int *counter,
670a50eb
ILT		 196 int reg, expressionS * ep));
197static void macro PARAMS ((struct mips_cl_insn * ip));
198static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
199static int my_getSmallExpression PARAMS ((expressionS * ep, char *str));
200static void my_getExpression PARAMS ((expressionS * ep, char *str));
3d3c5039 201static symbolS *get_symbol PARAMS ((void));
becfe05e 202static void mips_align PARAMS ((int to, int fill));
3d3c5039 203static void s_align PARAMS ((int));
becfe05e 204static void s_stringer PARAMS ((int));
3d3c5039
ILT		 205static void s_change_sec PARAMS ((int));
206static void s_cons PARAMS ((int));
207static void s_err PARAMS ((int));
208static void s_extern PARAMS ((int));
209static void s_float_cons PARAMS ((int));
210static void s_option PARAMS ((int));
211static void s_mipsset PARAMS ((int));
becfe05e 212static void s_mips_space PARAMS ((int));
3d3c5039
ILT		 213#ifndef OBJ_ECOFF
214static void md_obj_begin PARAMS ((void));
215static void md_obj_end PARAMS ((void));
216static long get_number PARAMS ((void));
217static void s_ent PARAMS ((int));
218static void s_mipsend PARAMS ((int));
219static void s_file PARAMS ((int));
88225433 220#if 0
3d3c5039
ILT		 221static void s_frame PARAMS ((int));
222static void s_loc PARAMS ((int));
223static void s_mask PARAMS ((char));
224#endif
88225433 225#endif
3d3c5039
ILT		 226\f
227/* Pseudo-op table.
228
229 The following pseudo-ops from the Kane and Heinrich MIPS book
230 should be defined here, but are currently unsupported: .alias,
231 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
232
233 The following pseudo-ops from the Kane and Heinrich MIPS book are
234 specific to the type of debugging information being generated, and
235 should be defined by the object format: .aent, .begin, .bend,
236 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
237 .vreg.
238
239 The following pseudo-ops from the Kane and Heinrich MIPS book are
240 not MIPS CPU specific, but are also not specific to the object file
241 format. This file is probably the best place to define them, but
242 they are not currently supported: .asm0, .endr, .lab, .repeat,
243 .struct, .weakext. */
244
245const pseudo_typeS md_pseudo_table[] =
246{
670a50eb
ILT		 247 /* MIPS specific pseudo-ops. */
248 {"option", s_option, 0},
249 {"set", s_mipsset, 0},
dd3f1f76
ILT		 250 {"rdata", s_change_sec, 'r'},
251 {"sdata", s_change_sec, 's'},
252 {"livereg", s_ignore, 0},
3d3c5039 253
670a50eb 254 /* Relatively generic pseudo-ops that happen to be used on MIPS
3d3c5039 255 chips. */
becfe05e 256 {"asciiz", s_stringer, 1},
670a50eb
ILT		 257 {"bss", s_change_sec, 'b'},
258 {"err", s_err, 0},
259 {"half", s_cons, 1},
52aa70b5 260 {"dword", s_cons, 3},
3d3c5039 261
670a50eb 262 /* These pseudo-ops are defined in read.c, but must be overridden
3d3c5039 263 here for one reason or another. */
670a50eb 264 {"align", s_align, 0},
becfe05e
ILT		 265 {"ascii", s_stringer, 0},
266 {"asciz", s_stringer, 1},
670a50eb
ILT		 267 {"byte", s_cons, 0},
268 {"data", s_change_sec, 'd'},
becfe05e 269 {"double", s_float_cons, 'd'},
670a50eb 270 {"extern", s_extern, 0},
becfe05e
ILT		 271 {"float", s_float_cons, 'f'},
272 {"space", s_mips_space, 0},
670a50eb
ILT		 273 {"text", s_change_sec, 't'},
274 {"word", s_cons, 2},
3d3c5039
ILT		 275
276#ifndef OBJ_ECOFF
670a50eb 277 /* These pseudo-ops should be defined by the object file format.
3d3c5039
ILT		 278 However, ECOFF is the only format which currently defines them,
279 so we have versions here for a.out. */
670a50eb
ILT		 280 {"aent", s_ent, 1},
281 {"end", s_mipsend, 0},
282 {"ent", s_ent, 0},
283 {"file", s_file, 0},
284 {"fmask", s_ignore, 'F'},
285 {"frame", s_ignore, 0},
286 {"loc", s_ignore, 0},
287 {"mask", s_ignore, 'R'},
288 {"verstamp", s_ignore, 0},
3d3c5039
ILT		 289#endif
290
670a50eb
ILT		 291 /* Sentinel. */
292 {NULL}
3d3c5039
ILT		 293};
294\f
670a50eb
ILT		 295const relax_typeS md_relax_table[] =
296{
918692a5 297 { 0 }
3d3c5039
ILT		 298};
299
300
301static char *expr_end;
302
303static expressionS imm_expr;
304static expressionS offset_expr;
305static bfd_reloc_code_real_type imm_reloc;
306static bfd_reloc_code_real_type offset_reloc;
307
abdad6bc
ILT		 308/* FIXME: This should be handled in a different way. */
309extern int target_big_endian;
310
3d3c5039
ILT		 311/*
312 * This function is called once, at assembler startup time. It should
313 * set up all the tables, etc. that the MD part of the assembler will need.
314 */
315void
670a50eb 316md_begin ()
3d3c5039 317{
97f99d11 318 boolean ok;
604633ae 319 register const char *retval = NULL;
670a50eb 320 register unsigned int i = 0;
3d3c5039 321
8358c818
ILT		 322 if (mips_isa == -1)
323 {
324 if (strcmp (TARGET_CPU, "mips") == 0)
325 mips_isa = 1;
326 else if (strcmp (TARGET_CPU, "r6000") == 0
327 || strcmp (TARGET_CPU, "mips2") == 0)
328 mips_isa = 2;
329 else if (strcmp (TARGET_CPU, "mips64") == 0
330 || strcmp (TARGET_CPU, "r4000") == 0
331 || strcmp (TARGET_CPU, "mips3") == 0)
332 mips_isa = 3;
333 else
334 mips_isa = 1;
335 }
336
97f99d11
ILT		 337 switch (mips_isa)
338 {
339 case 1:
340 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000);
341 break;
342 case 2:
343 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000);
344 break;
345 case 3:
346 ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000);
347 break;
348 }
349 if (! ok)
350 as_warn ("Could not set architecture and machine");
351
670a50eb
ILT		 352 if ((op_hash = hash_new ()) == NULL)
353 {
354 as_fatal ("Virtual memory exhausted");
3d3c5039 355 }
670a50eb
ILT		 356 for (i = 0; i < NUMOPCODES;)
357 {
358 const char *name = mips_opcodes[i].name;
359
604633ae 360 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
abdad6bc 361 if (retval != NULL)
670a50eb
ILT		 362 {
363 fprintf (stderr, "internal error: can't hash `%s': %s\n",
364 mips_opcodes[i].name, retval);
365 as_fatal ("Broken assembler. No assembly attempted.");
366 }
367 do
368 {
8358c818
ILT		 369 if (mips_opcodes[i].pinfo != INSN_MACRO
370 && ((mips_opcodes[i].match & mips_opcodes[i].mask)
371 != mips_opcodes[i].match))
670a50eb
ILT		 372 {
373 fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n",
374 mips_opcodes[i].name, mips_opcodes[i].args);
375 as_fatal ("Broken assembler. No assembly attempted.");
3d3c5039 376 }
670a50eb
ILT		 377 ++i;
378 }
379 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3d3c5039
ILT		 380 }
381
becfe05e
ILT		 382 mips_no_prev_insn ();
383
1aa6938e
ILT		 384 mips_gprmask = 0;
385 mips_cprmask[0] = 0;
386 mips_cprmask[1] = 0;
387 mips_cprmask[2] = 0;
388 mips_cprmask[3] = 0;
389
8358c818
ILT		 390 /* set the default alignment for the text section (2**2) */
391 record_alignment (text_section, 2);
392
abdad6bc
ILT		 393 /* FIXME: This should be handled in a different way. */
394 target_big_endian = byte_order == BIG_ENDIAN;
395
88225433 396#ifdef GPOPT
8358c818
ILT		 397 bfd_set_gp_size (stdoutput, g_switch_value);
398#endif
399
f2a663d3
ILT		 400#ifdef OBJ_ELF
401 /* Create a .reginfo section for register masks. */
402 {
403 segT seg;
404 subsegT subseg;
405 segT regsec;
406
407 seg = now_seg;
408 subseg = now_subseg;
409 regsec = subseg_new (".reginfo", (subsegT) 0);
410
411 /* I don't know why this section should be loaded, but the ABI
412 says that SHF_ALLOC should be set. */
413 bfd_set_section_flags (stdoutput, regsec,
414 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
415
416 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
417
418 subseg_set (seg, subseg);
419 }
420#endif /* OBJ_ELF */
421
3d3c5039 422#ifndef OBJ_ECOFF
670a50eb 423 md_obj_begin ();
3d3c5039
ILT		 424#endif
425}
426
427void
428md_end ()
429{
430#ifndef OBJ_ECOFF
431 md_obj_end ();
432#endif
433}
434
435void
670a50eb
ILT		 436md_assemble (str)
437 char *str;
3d3c5039 438{
670a50eb 439 struct mips_cl_insn insn;
3d3c5039 440
5ac34ac3
ILT		 441 imm_expr.X_op = O_absent;
442 offset_expr.X_op = O_absent;
3d3c5039 443
670a50eb
ILT		 444 mips_ip (str, &insn);
445 if (insn_error)
446 {
447 as_bad ("%s `%s'", insn_error, str);
448 return;
449 }
450 if (insn.insn_mo->pinfo == INSN_MACRO)
451 {
452 macro (&insn);
3d3c5039 453 }
670a50eb
ILT		 454 else
455 {
5ac34ac3 456 if (imm_expr.X_op != O_absent)
670a50eb 457 append_insn (&insn, &imm_expr, imm_reloc);
5ac34ac3 458 else if (offset_expr.X_op != O_absent)
670a50eb
ILT		 459 append_insn (&insn, &offset_expr, offset_reloc);
460 else
461 append_insn (&insn, NULL, BFD_RELOC_UNUSED);
3d3c5039
ILT		 462 }
463}
464
becfe05e
ILT		 465/* See whether instruction IP reads register REG. If FPR is non-zero,
466 REG is a floating point register. */
467
468static int
469insn_uses_reg (ip, reg, fpr)
470 struct mips_cl_insn *ip;
604633ae 471 unsigned int reg;
becfe05e
ILT		 472 int fpr;
473{
474 /* Don't report on general register 0, since it never changes. */
475 if (! fpr && reg == 0)
476 return 0;
477
478 if (fpr)
479 {
480 /* If we are called with either $f0 or $f1, we must check $f0.
481 This is not optimal, because it will introduce an unnecessary
482 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
483 need to distinguish reading both $f0 and $f1 or just one of
484 them. Note that we don't have to check the other way,
485 because there is no instruction that sets both $f0 and $f1
486 and requires a delay. */
487 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
604633ae
ILT		 488 && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS)
489 == (reg &~ (unsigned) 1)))
becfe05e
ILT		 490 return 1;
491 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
604633ae
ILT		 492 && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT)
493 == (reg &~ (unsigned) 1)))
becfe05e
ILT		 494 return 1;
495 }
496 else
497 {
498 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
499 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
500 return 1;
501 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
502 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
503 return 1;
504 }
505
506 return 0;
507}
508
3d3c5039
ILT		 509#define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
510#define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
511
512/*
513 * append insn
514 * Output an instruction.
515 */
516static void
670a50eb
ILT		 517append_insn (ip, address_expr, reloc_type)
518 struct mips_cl_insn *ip;
519 expressionS *address_expr;
520 bfd_reloc_code_real_type reloc_type;
3d3c5039 521{
1aa6938e 522 register unsigned long prev_pinfo, pinfo;
670a50eb 523 char *f;
becfe05e
ILT		 524 fixS *fixp;
525 int nops = 0;
3d3c5039 526
1aa6938e
ILT		 527 prev_pinfo = prev_insn.insn_mo->pinfo;
528 pinfo = ip->insn_mo->pinfo;
529
becfe05e
ILT		 530 if (! mips_noreorder)
531 {
532 /* If the previous insn required any delay slots, see if we need
8358c818 533 to insert a NOP or two. There are eight kinds of possible
becfe05e 534 hazards, of which an instruction can have at most one type.
8358c818
ILT		 535 (1) a load from memory delay
536 (2) a load from a coprocessor delay
537 (3) an unconditional branch delay
538 (4) a conditional branch delay
539 (5) a move to coprocessor register delay
540 (6) a load coprocessor register from memory delay
541 (7) a coprocessor condition code delay
542 (8) a HI/LO special register delay
becfe05e
ILT		 543
544 There are a lot of optimizations we could do that we don't.
545 In particular, we do not, in general, reorder instructions.
546 If you use gcc with optimization, it will reorder
547 instructions and generally do much more optimization then we
548 do here; repeating all that work in the assembler would only
549 benefit hand written assembly code, and does not seem worth
550 it. */
551
552 /* This is how a NOP is emitted. */
553#define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
554
555 /* The previous insn might require a delay slot, depending upon
556 the contents of the current insn. */
1aa6938e 557 if ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
8358c818 558 || (mips_isa < 2
1aa6938e 559 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))
8358c818
ILT		 560 {
561 /* A load from a coprocessor or from memory. All load
562 delays delay the use of general register rt for one
563 instruction on the r3000. The r6000 and r4000 use
564 interlocks. */
1aa6938e 565 know (prev_pinfo & INSN_WRITE_GPR_T);
0aa07269
ILT		 566 if (mips_optimize == 0
567 || insn_uses_reg (ip,
568 ((prev_insn.insn_opcode >> OP_SH_RT)
569 & OP_MASK_RT),
570 0))
becfe05e
ILT		 571 ++nops;
572 }
1aa6938e 573 else if ((prev_pinfo & INSN_COPROC_MOVE_DELAY)
8358c818 574 || (mips_isa < 2
1aa6938e 575 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))
becfe05e
ILT		 576 {
577 /* A generic coprocessor delay. The previous instruction
578 modified a coprocessor general or control register. If
579 it modified a control register, we need to avoid any
580 coprocessor instruction (this is probably not always
581 required, but it sometimes is). If it modified a general
582 register, we avoid using that register.
583
8358c818
ILT		 584 On the r6000 and r4000 loading a coprocessor register
585 from memory is interlocked, and does not require a delay.
586
becfe05e
ILT		 587 This case is not handled very well. There is no special
588 knowledge of CP0 handling, and the coprocessors other
589 than the floating point unit are not distinguished at
590 all. */
1aa6938e 591 if (prev_pinfo & INSN_WRITE_FPR_T)
becfe05e 592 {
0aa07269
ILT		 593 if (mips_optimize == 0
594 || insn_uses_reg (ip,
8358c818
ILT		 595 ((prev_insn.insn_opcode >> OP_SH_FT)
596 & OP_MASK_FT),
0aa07269 597 1))
becfe05e
ILT		 598 ++nops;
599 }
1aa6938e 600 else if (prev_pinfo & INSN_WRITE_FPR_S)
becfe05e 601 {
0aa07269
ILT		 602 if (mips_optimize == 0
603 || insn_uses_reg (ip,
8358c818
ILT		 604 ((prev_insn.insn_opcode >> OP_SH_FS)
605 & OP_MASK_FS),
0aa07269 606 1))
becfe05e
ILT		 607 ++nops;
608 }
609 else
610 {
611 /* We don't know exactly what the previous instruction
612 does. If the current instruction uses a coprocessor
613 register, we must insert a NOP. If previous
614 instruction may set the condition codes, and the
615 current instruction uses them, we must insert two
616 NOPS. */
0aa07269 617 if (mips_optimize == 0
1aa6938e
ILT		 618 || ((prev_pinfo & INSN_WRITE_COND_CODE)
619 && (pinfo & INSN_READ_COND_CODE)))
becfe05e 620 nops += 2;
1aa6938e 621 else if (pinfo & INSN_COP)
becfe05e
ILT		 622 ++nops;
623 }
624 }
1aa6938e 625 else if (prev_pinfo & INSN_WRITE_COND_CODE)
becfe05e
ILT		 626 {
627 /* The previous instruction sets the coprocessor condition
628 codes, but does not require a general coprocessor delay
629 (this means it is a floating point comparison
630 instruction). If this instruction uses the condition
631 codes, we need to insert a single NOP. */
0aa07269 632 if (mips_optimize == 0
1aa6938e 633 || (pinfo & INSN_READ_COND_CODE))
becfe05e
ILT		 634 ++nops;
635 }
1aa6938e 636 else if (prev_pinfo & INSN_READ_LO)
becfe05e
ILT		 637 {
638 /* The previous instruction reads the LO register; if the
639 current instruction writes to the LO register, we must
640 insert two NOPS. */
0aa07269 641 if (mips_optimize == 0
1aa6938e 642 || (pinfo & INSN_WRITE_LO))
becfe05e
ILT		 643 nops += 2;
644 }
645 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
646 {
647 /* The previous instruction reads the HI register; if the
648 current instruction writes to the HI register, we must
649 insert a NOP. */
0aa07269 650 if (mips_optimize == 0
1aa6938e 651 || (pinfo & INSN_WRITE_HI))
becfe05e
ILT		 652 nops += 2;
653 }
654
655 /* There are two cases which require two intervening
656 instructions: 1) setting the condition codes using a move to
657 coprocessor instruction which requires a general coprocessor
658 delay and then reading the condition codes 2) reading the HI
659 or LO register and then writing to it. If we are not already
660 emitting a NOP instruction, we must check for these cases
661 compared to the instruction previous to the previous
662 instruction. */
663 if (nops == 0
8358c818 664 && (((prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
becfe05e 665 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1aa6938e 666 && (pinfo & INSN_READ_COND_CODE))
becfe05e 667 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1aa6938e 668 && (pinfo & INSN_WRITE_LO))
becfe05e 669 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1aa6938e 670 && (pinfo & INSN_WRITE_HI))))
becfe05e
ILT		 671 ++nops;
672
673 /* Now emit the right number of NOP instructions. */
674 if (nops > 0)
675 {
676 emit_nop ();
677 if (nops > 1)
678 emit_nop ();
679 if (insn_label != NULL)
680 {
681 assert (S_GET_SEGMENT (insn_label) == now_seg);
682 insn_label->sy_frag = frag_now;
604633ae 683 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
becfe05e
ILT		 684 }
685 }
686 }
687
670a50eb 688 f = frag_more (4);
becfe05e
ILT		 689#if 0
690 /* This is testing the address of the frag, not the alignment of
691 the instruction in the current section. */
670a50eb
ILT		 692 if ((int) f & 3)
693 {
694 as_bad (ALIGN_ERR);
695 as_bad (ALIGN_ERR2);
3d3c5039
ILT		 696 }
697#endif
becfe05e 698 fixp = NULL;
670a50eb
ILT		 699 if (address_expr != NULL)
700 {
5ac34ac3 701 if (address_expr->X_op == O_constant)
670a50eb
ILT		 702 {
703 switch (reloc_type)
704 {
3d3c5039 705 case BFD_RELOC_32:
670a50eb
ILT		 706 ip->insn_opcode |= address_expr->X_add_number;
707 break;
3d3c5039
ILT		 708
709 case BFD_RELOC_LO16:
670a50eb
ILT		 710 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
711 break;
3d3c5039
ILT		 712
713 case BFD_RELOC_MIPS_JMP:
714 case BFD_RELOC_16_PCREL_S2:
670a50eb 715 goto need_reloc;
3d3c5039
ILT		 716
717 default:
670a50eb 718 internalError ();
3d3c5039 719 }
670a50eb
ILT		 720 }
721 else
722 {
723 assert (reloc_type != BFD_RELOC_UNUSED);
3d3c5039 724 need_reloc:
5ac34ac3
ILT		 725 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
726 address_expr,
727 reloc_type == BFD_RELOC_16_PCREL_S2,
728 reloc_type);
3d3c5039
ILT		 729 }
730 }
becfe05e 731
670a50eb
ILT		 732 md_number_to_chars (f, ip->insn_opcode, 4);
733
1aa6938e
ILT		 734 /* Update the register mask information. */
735 if (pinfo & INSN_WRITE_GPR_D)
736 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
737 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
738 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
739 if (pinfo & INSN_READ_GPR_S)
740 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
741 if (pinfo & INSN_WRITE_GPR_31)
742 mips_gprmask |= 1 << 31;
743 if (pinfo & INSN_WRITE_FPR_D)
744 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
745 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
746 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
747 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
748 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
749 if (pinfo & INSN_COP)
750 {
751 /* We don't keep enough information to sort these cases out. */
752 }
753 /* Never set the bit for $0, which is always zero. */
754 mips_gprmask &=~ 1 << 0;
755
becfe05e 756 if (! mips_noreorder)
670a50eb 757 {
becfe05e
ILT		 758 /* Filling the branch delay slot is more complex. We try to
759 switch the branch with the previous instruction, which we can
760 do if the previous instruction does not set up a condition
761 that the branch tests and if the branch is not itself the
762 target of any branch. */
1aa6938e
ILT		 763 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
764 || (pinfo & INSN_COND_BRANCH_DELAY))
becfe05e 765 {
0aa07269 766 if (mips_optimize < 2
19ed8960
ILT		 767 /* If we have seen .set nobopt, don't optimize. */
768 || mips_nobopt != 0
769 /* If we have seen .set volatile or .set nomove, don't
770 optimize. */
771 || mips_nomove != 0
4e95866e
ILT		 772 /* If we had to emit any NOP instructions, then we
773 already know we can not swap. */
774 || nops != 0
becfe05e
ILT		 775 /* If we don't even know the previous insn, we can not
776 swap. */
777 || ! prev_insn_valid
778 /* If the previous insn is already in a branch delay
779 slot, then we can not swap. */
780 || prev_insn_is_delay_slot
4e95866e
ILT		 781 /* If the previous previous insn was in a .set
782 noreorder, we can't swap. Actually, the MIPS
783 assembler will swap in this situation. However, gcc
784 configured -with-gnu-as will generate code like
785 .set noreorder
786 lw $4,XXX
787 .set reorder
788 INSN
789 bne $4,$0,foo
790 in which we can not swap the bne and INSN. If gcc is
791 not configured -with-gnu-as, it does not output the
792 .set pseudo-ops. We don't have to check
793 prev_insn_unreordered, because prev_insn_valid will
794 be 0 in that case. We don't want to use
795 prev_prev_insn_valid, because we do want to be able
796 to swap at the start of a function. */
797 || prev_prev_insn_unreordered
becfe05e
ILT		 798 /* If the branch is itself the target of a branch, we
799 can not swap. We cheat on this; all we check for is
800 whether there is a label on this instruction. If
801 there are any branches to anything other than a
802 label, users must use .set noreorder. */
803 || insn_label != NULL
804 /* If the branch reads the condition codes, we don't
805 even try to swap, because in the sequence
806 ctc1 $X,$31
807 INSN
808 INSN
809 bc1t LABEL
810 we can not swap, and I don't feel like handling that
811 case. */
1aa6938e 812 || (pinfo & INSN_READ_COND_CODE)
becfe05e
ILT		 813 /* We can not swap with an instruction that requires a
814 delay slot, becase the target of the branch might
815 interfere with that instruction. */
1aa6938e 816 || (prev_pinfo
8358c818
ILT		 817 & (INSN_LOAD_COPROC_DELAY
818 | INSN_COPROC_MOVE_DELAY
becfe05e
ILT		 819 | INSN_WRITE_COND_CODE
820 | INSN_READ_LO
821 | INSN_READ_HI))
8358c818 822 || (mips_isa < 2
1aa6938e 823 && (prev_pinfo
8358c818
ILT		 824 & (INSN_LOAD_MEMORY_DELAY
825 | INSN_COPROC_MEMORY_DELAY)))
becfe05e 826 /* We can not swap with a branch instruction. */
1aa6938e 827 || (prev_pinfo
6e8dda9c
ILT		 828 & (INSN_UNCOND_BRANCH_DELAY
829 | INSN_COND_BRANCH_DELAY
830 | INSN_COND_BRANCH_LIKELY))
abdad6bc
ILT		 831 /* We do not swap with a trap instruction, since it
832 complicates trap handlers to have the trap
833 instruction be in a delay slot. */
1aa6938e 834 || (prev_pinfo & INSN_TRAP)
becfe05e
ILT		 835 /* If the branch reads a register that the previous
836 instruction sets, we can not swap. */
1aa6938e 837 || ((prev_pinfo & INSN_WRITE_GPR_T)
becfe05e
ILT		 838 && insn_uses_reg (ip,
839 ((prev_insn.insn_opcode >> OP_SH_RT)
840 & OP_MASK_RT),
841 0))
1aa6938e 842 || ((prev_pinfo & INSN_WRITE_GPR_D)
becfe05e
ILT		 843 && insn_uses_reg (ip,
844 ((prev_insn.insn_opcode >> OP_SH_RD)
845 & OP_MASK_RD),
846 0))
1849d646
ILT		 847 /* If the branch writes a register that the previous
848 instruction sets, we can not swap (we know that
849 branches write only to RD or to $31). */
1aa6938e
ILT		 850 || ((prev_pinfo & INSN_WRITE_GPR_T)
851 && (((pinfo & INSN_WRITE_GPR_D)
1849d646
ILT		 852 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
853 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
1aa6938e 854 || ((pinfo & INSN_WRITE_GPR_31)
1849d646
ILT		 855 && (((prev_insn.insn_opcode >> OP_SH_RT)
856 & OP_MASK_RT)
857 == 31))))
1aa6938e
ILT		 858 || ((prev_pinfo & INSN_WRITE_GPR_D)
859 && (((pinfo & INSN_WRITE_GPR_D)
1849d646
ILT		 860 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
861 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
1aa6938e 862 || ((pinfo & INSN_WRITE_GPR_31)
1849d646
ILT		 863 && (((prev_insn.insn_opcode >> OP_SH_RD)
864 & OP_MASK_RD)
865 == 31))))
becfe05e
ILT		 866 /* If the branch writes a register that the previous
867 instruction reads, we can not swap (we know that
868 branches only write to RD or to $31). */
1aa6938e 869 || ((pinfo & INSN_WRITE_GPR_D)
becfe05e
ILT		 870 && insn_uses_reg (&prev_insn,
871 ((ip->insn_opcode >> OP_SH_RD)
872 & OP_MASK_RD),
873 0))
1aa6938e 874 || ((pinfo & INSN_WRITE_GPR_31)
becfe05e
ILT		 875 && insn_uses_reg (&prev_insn, 31, 0))
876 /* If the previous previous instruction has a load
877 delay, and sets a register that the branch reads, we
878 can not swap. */
8358c818
ILT		 879 || (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
880 || (mips_isa < 2
881 && (prev_prev_insn.insn_mo->pinfo
882 & INSN_LOAD_MEMORY_DELAY)))
becfe05e
ILT		 883 && insn_uses_reg (ip,
884 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
885 & OP_MASK_RT),
886 0)))
887 {
888 /* We could do even better for unconditional branches to
889 portions of this object file; we could pick up the
890 instruction at the destination, put it in the delay
891 slot, and bump the destination address. */
892 emit_nop ();
893 /* Update the previous insn information. */
894 prev_prev_insn = *ip;
895 prev_insn.insn_mo = &dummy_opcode;
896 }
897 else
898 {
899 char *prev_f;
900 char temp[4];
901
902 /* It looks like we can actually do the swap. */
903 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
904 memcpy (temp, prev_f, 4);
905 memcpy (prev_f, f, 4);
906 memcpy (f, temp, 4);
907 if (prev_insn_fixp)
908 {
909 prev_insn_fixp->fx_frag = frag_now;
910 prev_insn_fixp->fx_where = f - frag_now->fr_literal;
911 }
912 if (fixp)
913 {
914 fixp->fx_frag = prev_insn_frag;
915 fixp->fx_where = prev_insn_where;
916 }
917 /* Update the previous insn information; leave prev_insn
918 unchanged. */
919 prev_prev_insn = *ip;
920 }
921 prev_insn_is_delay_slot = 1;
922
923 /* If that was an unconditional branch, forget the previous
924 insn information. */
1aa6938e 925 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
becfe05e
ILT		 926 {
927 prev_prev_insn.insn_mo = &dummy_opcode;
928 prev_insn.insn_mo = &dummy_opcode;
929 }
930 }
1aa6938e 931 else if (pinfo & INSN_COND_BRANCH_LIKELY)
8358c818
ILT		 932 {
933 /* We don't yet optimize a branch likely. What we should do
934 is look at the target, copy the instruction found there
935 into the delay slot, and increment the branch to jump to
936 the next instruction. */
937 emit_nop ();
938 /* Update the previous insn information. */
939 prev_prev_insn = *ip;
940 prev_insn.insn_mo = &dummy_opcode;
941 }
becfe05e 942 else
670a50eb 943 {
becfe05e
ILT		 944 /* Update the previous insn information. */
945 if (nops > 0)
946 prev_prev_insn.insn_mo = &dummy_opcode;
947 else
948 prev_prev_insn = prev_insn;
949 prev_insn = *ip;
950
951 /* Any time we see a branch, we always fill the delay slot
952 immediately; since this insn is not a branch, we know it
953 is not in a delay slot. */
954 prev_insn_is_delay_slot = 0;
955 }
956
4e95866e
ILT		 957 prev_prev_insn_unreordered = prev_insn_unreordered;
958 prev_insn_unreordered = 0;
becfe05e
ILT		 959 prev_insn_frag = frag_now;
960 prev_insn_where = f - frag_now->fr_literal;
961 prev_insn_fixp = fixp;
962 prev_insn_valid = 1;
963 }
3d3c5039 964
becfe05e
ILT		 965 /* We just output an insn, so the next one doesn't have a label. */
966 insn_label = NULL;
967}
968
969/* This function forgets that there was any previous instruction or
970 label. */
971
972static void
973mips_no_prev_insn ()
974{
975 prev_insn.insn_mo = &dummy_opcode;
976 prev_prev_insn.insn_mo = &dummy_opcode;
977 prev_insn_valid = 0;
978 prev_insn_is_delay_slot = 0;
4e95866e
ILT		 979 prev_insn_unreordered = 0;
980 prev_prev_insn_unreordered = 0;
becfe05e
ILT		 981 insn_label = NULL;
982}
983
984/* This function must be called whenever we turn on noreorder or emit
985 something other than instructions. It inserts any NOPS which might
986 be needed by the previous instruction, and clears the information
987 kept for the previous instructions. */
988
989static void
990mips_emit_delays ()
991{
992 if (! mips_noreorder)
993 {
994 int nop;
995
996 nop = 0;
8358c818
ILT		 997 if ((prev_insn.insn_mo->pinfo
998 & (INSN_LOAD_COPROC_DELAY
999 | INSN_COPROC_MOVE_DELAY
1000 | INSN_WRITE_COND_CODE
1001 | INSN_READ_LO
1002 | INSN_READ_HI))
1003 || (mips_isa < 2
1004 && (prev_insn.insn_mo->pinfo
1005 & (INSN_LOAD_MEMORY_DELAY
1006 | INSN_COPROC_MEMORY_DELAY))))
becfe05e
ILT		 1007 {
1008 nop = 1;
1009 if ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1010 || (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1011 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))
1012 emit_nop ();
1013 }
1014 else if ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1015 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1016 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))
1017 nop = 1;
1018 if (nop)
670a50eb 1019 {
becfe05e
ILT		 1020 emit_nop ();
1021 if (insn_label != NULL)
1022 {
1023 assert (S_GET_SEGMENT (insn_label) == now_seg);
1024 insn_label->sy_frag = frag_now;
604633ae 1025 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
becfe05e 1026 }
3d3c5039 1027 }
becfe05e 1028 mips_no_prev_insn ();
3d3c5039
ILT		 1029 }
1030}
1031
670a50eb
ILT		 1032/* Return 1 if an expression can be accessed via the GP register. */
1033
1034static int
1035gp_reference (ep)
1036 expressionS *ep;
1037{
88225433 1038#ifdef GPOPT
670a50eb 1039 symbolS *sym;
9a7d824a 1040 const char *symname;
670a50eb
ILT		 1041 const char *segname;
1042
1043 sym = ep->X_add_symbol;
1044 if (sym == (symbolS *) NULL
5ac34ac3 1045 || ep->X_op_symbol != (symbolS *) NULL)
670a50eb 1046 return 0;
9a7d824a
ILT		 1047
1048 /* Certain symbols can not be referenced off the GP, although it
1049 appears as though they can. */
1050 symname = S_GET_NAME (sym);
1051 if (symname != (const char *) NULL
1052 && (strcmp (symname, "eprol") == 0
1053 || strcmp (symname, "etext") == 0
1054 || strcmp (symname, "_gp") == 0
1055 || strcmp (symname, "edata") == 0
1056 || strcmp (symname, "_fbss") == 0
1057 || strcmp (symname, "_fdata") == 0
1058 || strcmp (symname, "_ftext") == 0
1059 || strcmp (symname, "end") == 0))
1060 return 0;
670a50eb
ILT		 1061 if (! S_IS_DEFINED (sym)
1062 && S_GET_VALUE (sym) != 0
1063 && S_GET_VALUE (sym) <= g_switch_value)
1064 return 1;
1065 segname = segment_name (S_GET_SEGMENT (ep->X_add_symbol));
1066 return (strcmp (segname, ".sdata") == 0
19ed8960
ILT		 1067 || strcmp (segname, ".sbss") == 0
1068 || strcmp (segname, ".lit8") == 0
1069 || strcmp (segname, ".lit4") == 0);
88225433
ILT		 1070#else /* ! defined (GPOPT) */
1071 /* We are not optimizing for the GP register. */
670a50eb 1072 return 0;
88225433 1073#endif /* ! defined (GPOPT) */
670a50eb
ILT		 1074}
1075
1076/* Build an instruction created by a macro expansion. This is passed
1077 a pointer to the count of instructions created so far, an
1078 expression, the name of the instruction to build, an operand format
1079 string, and corresponding arguments. */
1080
3d3c5039
ILT		 1081#ifndef NO_STDARG
1082static void
1083macro_build (int *counter,
670a50eb 1084 expressionS * ep,
3d3c5039
ILT		 1085 const char *name,
1086 const char *fmt,
1087 ...)
1088#else /* ! defined (NO_STDARG) */
1089static void
1090macro_build (counter, ep, name, fmt, va_alist)
1091 int *counter;
1092 expressionS *ep;
1093 const char *name;
1094 const char *fmt;
1095 va_dcl
1096#endif /* ! defined (NO_STDARG) */
1097{
670a50eb
ILT		 1098 struct mips_cl_insn insn;
1099 bfd_reloc_code_real_type r;
1100 va_list args;
3d3c5039
ILT		 1101
1102#ifndef NO_STDARG
670a50eb 1103 va_start (args, fmt);
3d3c5039 1104#else
670a50eb 1105 va_start (args);
3d3c5039
ILT		 1106#endif
1107
670a50eb
ILT		 1108 /*
1109 * If the macro is about to expand into a second instruction,
1110 * print a warning if needed. We need to pass ip as a parameter
1111 * to generate a better warning message here...
1112 */
1113 if (mips_warn_about_macros && *counter == 1)
1114 as_warn ("Macro instruction expanded into multiple instructions");
1115
1116 *counter += 1; /* bump instruction counter */
1117
1118 r = BFD_RELOC_UNUSED;
1119 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1120 assert (insn.insn_mo);
1121 assert (strcmp (name, insn.insn_mo->name) == 0);
1122
1123 while (strcmp (fmt, insn.insn_mo->args) != 0)
1124 {
1125 ++insn.insn_mo;
1126 assert (insn.insn_mo->name);
1127 assert (strcmp (name, insn.insn_mo->name) == 0);
3d3c5039 1128 }
670a50eb
ILT		 1129 assert (insn.insn_mo->pinfo != INSN_MACRO);
1130 insn.insn_opcode = insn.insn_mo->match;
1131 for (;;)
1132 {
1133 switch (*fmt++)
1134 {
3d3c5039 1135 case '\0':
670a50eb 1136 break;
3d3c5039
ILT		 1137
1138 case ',':
1139 case '(':
1140 case ')':
670a50eb 1141 continue;
3d3c5039
ILT		 1142
1143 case 't':
1144 case 'w':
918692a5 1145 case 'E':
670a50eb
ILT		 1146 insn.insn_opcode |= va_arg (args, int) << 16;
1147 continue;
3d3c5039
ILT		 1148
1149 case 'c':
1150 case 'T':
1151 case 'W':
670a50eb
ILT		 1152 insn.insn_opcode |= va_arg (args, int) << 16;
1153 continue;
3d3c5039
ILT		 1154
1155 case 'd':
918692a5 1156 case 'G':
670a50eb
ILT		 1157 insn.insn_opcode |= va_arg (args, int) << 11;
1158 continue;
3d3c5039
ILT		 1159
1160 case 'V':
1161 case 'S':
670a50eb
ILT		 1162 insn.insn_opcode |= va_arg (args, int) << 11;
1163 continue;
3d3c5039 1164
ff3a5c18
ILT		 1165 case 'z':
1166 continue;
1167
3d3c5039 1168 case '<':
56c96faa 1169 case '>':
670a50eb
ILT		 1170 insn.insn_opcode |= va_arg (args, int) << 6;
1171 continue;
3d3c5039
ILT		 1172
1173 case 'D':
670a50eb
ILT		 1174 insn.insn_opcode |= va_arg (args, int) << 6;
1175 continue;
3d3c5039 1176
918692a5
ILT		 1177 case 'B':
1178 insn.insn_opcode |= va_arg (args, int) << 6;
1179 continue;
1180
3d3c5039
ILT		 1181 case 'b':
1182 case 's':
1183 case 'r':
1184 case 'v':
670a50eb
ILT		 1185 insn.insn_opcode |= va_arg (args, int) << 21;
1186 continue;
3d3c5039
ILT		 1187
1188 case 'i':
1189 case 'j':
1190 case 'o':
670a50eb
ILT		 1191 r = BFD_RELOC_LO16;
1192 continue;
3d3c5039 1193
6e8dda9c
ILT		 1194 case 'u':
1195 assert (ep != NULL && ep->X_op == O_constant);
1196 insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff;
1197 ep = NULL;
1198 continue;
1199
3d3c5039 1200 case 'p':
670a50eb
ILT		 1201 assert (ep != NULL);
1202 /*
1203 * This allows macro() to pass an immediate expression for
1204 * creating short branches without creating a symbol.
1205 * Note that the expression still might come from the assembly
1206 * input, in which case the value is not checked for range nor
1207 * is a relocation entry generated (yuck).
1208 */
5ac34ac3 1209 if (ep->X_op == O_constant)
670a50eb
ILT		 1210 {
1211 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
1212 ep = NULL;
1213 }
1214 else
1215 r = BFD_RELOC_16_PCREL_S2;
1216 continue;
3d3c5039
ILT		 1217
1218 default:
670a50eb 1219 internalError ();
3d3c5039 1220 }
670a50eb 1221 break;
3d3c5039 1222 }
670a50eb
ILT		 1223 va_end (args);
1224 assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1225
1226 /* Use GP relative addressing if possible. */
1227 if (r == BFD_RELOC_LO16
1228 && gp_reference (ep))
1229 r = BFD_RELOC_MIPS_GPREL;
1230
1231 append_insn (&insn, ep, r);
3d3c5039
ILT		 1232}
1233
1234/*
1235 * Generate a "lui" instruction.
1236 */
1237static void
1238macro_build_lui (counter, ep, regnum)
1239 int *counter;
1240 expressionS *ep;
1241 int regnum;
1242{
670a50eb
ILT		 1243 expressionS high_expr;
1244 struct mips_cl_insn insn;
1245 bfd_reloc_code_real_type r;
1246 CONST char *name = "lui";
1247 CONST char *fmt = "t,u";
1248
1249 high_expr = *ep;
1250
5ac34ac3 1251 if (high_expr.X_op == O_constant)
670a50eb
ILT		 1252 {
1253 /* we can compute the instruction now without a relocation entry */
1254 if (high_expr.X_add_number & 0x8000)
1255 high_expr.X_add_number += 0x10000;
1256 high_expr.X_add_number =
1257 ((unsigned long) high_expr.X_add_number >> 16) & 0xffff;
1258 r = BFD_RELOC_UNUSED;
1259 }
1260 else
1261 r = BFD_RELOC_HI16_S;
1262
1263 /*
1264 * If the macro is about to expand into a second instruction,
1265 * print a warning if needed. We need to pass ip as a parameter
1266 * to generate a better warning message here...
1267 */
1268 if (mips_warn_about_macros && *counter == 1)
1269 as_warn ("Macro instruction expanded into multiple instructions");
1270
1271 *counter += 1; /* bump instruction counter */
1272
1273 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
1274 assert (insn.insn_mo);
1275 assert (strcmp (name, insn.insn_mo->name) == 0);
1276 assert (strcmp (fmt, insn.insn_mo->args) == 0);
1277
1278 insn.insn_opcode = insn.insn_mo->match | (regnum << 16);
1279 if (r == BFD_RELOC_UNUSED)
1280 {
1281 insn.insn_opcode |= high_expr.X_add_number;
1282 append_insn (&insn, NULL, r);
1283 }
1284 else
1285 append_insn (&insn, &high_expr, r);
3d3c5039
ILT		 1286}
1287
1288/* set_at()
1289 * Generates code to set the $at register to true (one)
1290 * if reg is less than the immediate expression.
1291 */
1292static void
6e8dda9c 1293set_at (counter, reg, unsignedp)
3d3c5039
ILT		 1294 int *counter;
1295 int reg;
6e8dda9c 1296 int unsignedp;
3d3c5039 1297{
6e8dda9c
ILT		 1298 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
1299 macro_build (counter, &imm_expr,
1300 unsignedp ? "sltiu" : "slti",
1301 "t,r,j", AT, reg);
1302 else
670a50eb 1303 {
6e8dda9c
ILT		 1304 load_register (counter, AT, &imm_expr);
1305 macro_build (counter, NULL,
1306 unsignedp ? "sltu" : "slt",
1307 "d,v,t", AT, reg, AT);
670a50eb 1308 }
3d3c5039
ILT		 1309}
1310
6e8dda9c 1311/* Warn if an expression is not a constant. */
3d3c5039
ILT		 1312
1313static void
19ed8960 1314check_absolute_expr (ip, ex)
3d3c5039 1315 struct mips_cl_insn *ip;
19ed8960 1316 expressionS *ex;
3d3c5039 1317{
19ed8960 1318 if (ex->X_op != O_constant)
670a50eb 1319 as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name);
3d3c5039
ILT		 1320}
1321
1322/* load_register()
1323 * This routine generates the least number of instructions neccessary to load
1324 * an absolute expression value into a register.
1325 */
1326static void
6e8dda9c 1327load_register (counter, reg, ep)
670a50eb 1328 int *counter;
670a50eb
ILT		 1329 int reg;
1330 expressionS *ep;
3d3c5039 1331{
6e8dda9c
ILT		 1332 assert (ep->X_op == O_constant);
1333 if (ep->X_add_number >= -0x8000 && ep->X_add_number < 0x8000)
1334 macro_build (counter, ep,
1335 mips_isa < 3 ? "addiu" : "daddiu",
1336 "t,r,j", reg, 0);
1337 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
1338 macro_build (counter, ep, "ori", "t,r,i", reg, 0);
1339 else if ((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0
1340 || ((ep->X_add_number &~ (offsetT) 0x7fffffff)
1341 == ~ (offsetT) 0x7fffffff))
1342 {
1343 macro_build (counter, ep, "lui", "t,u", reg);
1344 if ((ep->X_add_number & 0xffff) != 0)
1345 macro_build (counter, ep, "ori", "t,r,i", reg, reg);
1346 }
1347 else if (mips_isa < 3)
670a50eb 1348 {
6e8dda9c 1349 as_bad ("Number larger than 32 bits");
670a50eb 1350 macro_build (counter, ep, "addiu", "t,r,j", reg, 0);
6e8dda9c
ILT		 1351 }
1352 else
1353 {
1354 int shift;
1355 expressionS hi32, lo32;
1356
1357 hi32 = *ep;
1358 shift = 32;
1359 hi32.X_add_number >>= shift;
1360 hi32.X_add_number &= 0xffffffff;
1361 if ((hi32.X_add_number & 0x80000000) != 0)
1362 hi32.X_add_number |= ~ (offsetT) 0xffffffff;
1363 load_register (counter, reg, &hi32);
1364 lo32 = *ep;
1365 lo32.X_add_number &= 0xffffffff;
1366 if ((lo32.X_add_number & 0xffff0000) == 0)
1367 macro_build (counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
1368 else
1369 {
1370 expressionS mid16;
670a50eb 1371
6e8dda9c
ILT		 1372 macro_build (counter, NULL, "dsll", "d,w,<", reg, reg, 16);
1373 mid16 = lo32;
1374 mid16.X_add_number >>= 16;
1375 macro_build (counter, &mid16, "ori", "t,r,i", reg, reg);
1376 macro_build (counter, NULL, "dsll", "d,w,<", reg, reg, 16);
1377 }
1378 if ((lo32.X_add_number & 0xffff) != 0)
1379 macro_build (counter, &lo32, "ori", "t,r,i", reg, reg);
670a50eb 1380 }
3d3c5039
ILT		 1381}
1382
3d3c5039
ILT		 1383/*
1384 * Build macros
1385 * This routine implements the seemingly endless macro or synthesized
1386 * instructions and addressing modes in the mips assembly language. Many
1387 * of these macros are simple and are similar to each other. These could
1388 * probably be handled by some kind of table or grammer aproach instead of
1389 * this verbose method. Others are not simple macros but are more like
1390 * optimizing code generation.
1391 * One interesting optimization is when several store macros appear
1392 * consecutivly that would load AT with the upper half of the same address.
1393 * The ensuing load upper instructions are ommited. This implies some kind
1394 * of global optimization. We currently only optimize within a single macro.
1395 * For many of the load and store macros if the address is specified as a
1396 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1397 * first load register 'at' with zero and use it as the base register. The
1398 * mips assembler simply uses register $zero. Just one tiny optimization
1399 * we're missing.
1400 */
1401static void
1402macro (ip)
1403 struct mips_cl_insn *ip;
1404{
670a50eb
ILT		 1405 register int treg, sreg, dreg, breg;
1406 int tempreg;
1407 int mask;
1408 int icnt = 0;
1409 int used_at;
670a50eb
ILT		 1410 expressionS expr1;
1411 const char *s;
8358c818 1412 const char *s2;
670a50eb 1413 const char *fmt;
8358c818
ILT		 1414 int likely = 0;
1415 int dbl = 0;
1416 int coproc = 0;
6e8dda9c 1417 offsetT maxnum;
670a50eb
ILT		 1418
1419 treg = (ip->insn_opcode >> 16) & 0x1f;
1420 dreg = (ip->insn_opcode >> 11) & 0x1f;
1421 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
1422 mask = ip->insn_mo->mask;
1423
5ac34ac3
ILT		 1424 expr1.X_op = O_constant;
1425 expr1.X_op_symbol = NULL;
670a50eb
ILT		 1426 expr1.X_add_symbol = NULL;
1427 expr1.X_add_number = 1;
1428
1429 switch (mask)
1430 {
6e8dda9c
ILT		 1431 case M_DABS:
1432 dbl = 1;
3d3c5039 1433 case M_ABS:
6e8dda9c
ILT		 1434 /* bgez $a0,.+12
1435 move v0,$a0
1436 sub v0,$zero,$a0
1437 */
3d3c5039 1438
becfe05e
ILT		 1439 mips_emit_delays ();
1440 ++mips_noreorder;
3d3c5039 1441
670a50eb
ILT		 1442 expr1.X_add_number = 8;
1443 macro_build (&icnt, &expr1, "bgez", "s,p", sreg);
6e8dda9c
ILT		 1444 if (dreg == sreg)
1445 macro_build (&icnt, NULL, "nop", "", 0);
1446 else
1447 macro_build (&icnt, NULL, "move", "d,s", dreg, sreg, 0);
1448 macro_build (&icnt, NULL,
1449 dbl ? "dsub" : "sub",
1450 "d,v,t", dreg, 0, sreg);
3d3c5039 1451
becfe05e 1452 --mips_noreorder;
670a50eb 1453 return;
3d3c5039
ILT		 1454
1455 case M_ADD_I:
8358c818
ILT		 1456 s = "addi";
1457 s2 = "add";
1458 goto do_addi;
3d3c5039 1459 case M_ADDU_I:
8358c818
ILT		 1460 s = "addiu";
1461 s2 = "addu";
1462 goto do_addi;
1463 case M_DADD_I:
6e8dda9c 1464 dbl = 1;
8358c818
ILT		 1465 s = "daddi";
1466 s2 = "dadd";
1467 goto do_addi;
1468 case M_DADDU_I:
6e8dda9c 1469 dbl = 1;
8358c818
ILT		 1470 s = "daddiu";
1471 s2 = "daddu";
1472 do_addi:
6e8dda9c 1473 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb 1474 {
8358c818 1475 macro_build (&icnt, &imm_expr, s, "t,r,j", treg, sreg);
670a50eb 1476 return;
3d3c5039 1477 }
6e8dda9c 1478 load_register (&icnt, AT, &imm_expr);
8358c818 1479 macro_build (&icnt, NULL, s2, "d,v,t", treg, sreg, AT);
670a50eb 1480 break;
3d3c5039
ILT		 1481
1482 case M_AND_I:
6e8dda9c
ILT		 1483 s = "andi";
1484 s2 = "and";
1485 goto do_bit;
3d3c5039 1486 case M_OR_I:
6e8dda9c
ILT		 1487 s = "ori";
1488 s2 = "or";
1489 goto do_bit;
3d3c5039 1490 case M_NOR_I:
6e8dda9c
ILT		 1491 s = "";
1492 s2 = "nor";
1493 goto do_bit;
3d3c5039 1494 case M_XOR_I:
6e8dda9c
ILT		 1495 s = "xori";
1496 s2 = "xor";
1497 do_bit:
1498 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
670a50eb 1499 {
6e8dda9c
ILT		 1500 if (mask != M_NOR_I)
1501 macro_build (&icnt, &imm_expr, s, "t,r,i", treg, sreg);
1502 else
670a50eb 1503 {
670a50eb
ILT		 1504 macro_build (&icnt, &imm_expr, "ori", "t,r,i", treg, sreg);
1505 macro_build (&icnt, &imm_expr, "nor", "d,v,t", treg, treg, 0);
3d3c5039 1506 }
6e8dda9c 1507 return;
3d3c5039 1508 }
6e8dda9c
ILT		 1509
1510 load_register (&icnt, AT, &imm_expr);
1511 macro_build (&icnt, NULL, s2, "d,v,t", treg, sreg, AT);
670a50eb 1512 break;
3d3c5039
ILT		 1513
1514 case M_BEQ_I:
8358c818
ILT		 1515 s = "beq";
1516 goto beq_i;
1517 case M_BEQL_I:
1518 s = "beql";
1519 likely = 1;
1520 goto beq_i;
3d3c5039 1521 case M_BNE_I:
8358c818
ILT		 1522 s = "bne";
1523 goto beq_i;
1524 case M_BNEL_I:
1525 s = "bnel";
1526 likely = 1;
1527 beq_i:
670a50eb
ILT		 1528 if (imm_expr.X_add_number == 0)
1529 {
8358c818 1530 macro_build (&icnt, &offset_expr, s, "s,t,p", sreg, 0);
670a50eb
ILT		 1531 return;
1532 }
6e8dda9c 1533 load_register (&icnt, AT, &imm_expr);
8358c818 1534 macro_build (&icnt, &offset_expr, s, "s,t,p", sreg, AT);
670a50eb 1535 break;
3d3c5039 1536
8358c818
ILT		 1537 case M_BGEL:
1538 likely = 1;
3d3c5039 1539 case M_BGE:
670a50eb
ILT		 1540 if (treg == 0)
1541 {
8358c818
ILT		 1542 macro_build (&icnt, &offset_expr,
1543 likely ? "bgezl" : "bgez",
1544 "s,p", sreg);
670a50eb 1545 return;
3d3c5039 1546 }
9a7d824a
ILT		 1547 if (sreg == 0)
1548 {
8358c818
ILT		 1549 macro_build (&icnt, &offset_expr,
1550 likely ? "blezl" : "blez",
1551 "s,p", treg);
9a7d824a
ILT		 1552 return;
1553 }
670a50eb 1554 macro_build (&icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
8358c818
ILT		 1555 macro_build (&icnt, &offset_expr,
1556 likely ? "beql" : "beq",
1557 "s,t,p", AT, 0);
670a50eb 1558 break;
3d3c5039 1559
8358c818
ILT		 1560 case M_BGTL_I:
1561 likely = 1;
3d3c5039 1562 case M_BGT_I:
9a7d824a 1563 /* check for > max integer */
6e8dda9c
ILT		 1564 maxnum = 0x7fffffff;
1565 if (mips_isa >= 3)
1566 {
1567 maxnum <<= 16;
1568 maxnum |= 0xffff;
1569 maxnum <<= 16;
1570 maxnum |= 0xffff;
1571 }
1572 if (imm_expr.X_add_number >= maxnum)
9a7d824a
ILT		 1573 {
1574 do_false:
1575 /* result is always false */
8358c818
ILT		 1576 if (! likely)
1577 {
1578 as_warn ("Branch %s is always false (nop)", ip->insn_mo->name);
1579 macro_build (&icnt, NULL, "nop", "", 0);
1580 }
1581 else
1582 {
1583 as_warn ("Branch likely %s is always false", ip->insn_mo->name);
1584 macro_build (&icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
1585 }
9a7d824a
ILT		 1586 return;
1587 }
670a50eb
ILT		 1588 imm_expr.X_add_number++;
1589 /* FALLTHROUGH */
3d3c5039 1590 case M_BGE_I:
8358c818
ILT		 1591 case M_BGEL_I:
1592 if (mask == M_BGEL_I)
1593 likely = 1;
670a50eb
ILT		 1594 if (imm_expr.X_add_number == 0)
1595 {
8358c818
ILT		 1596 macro_build (&icnt, &offset_expr,
1597 likely ? "bgezl" : "bgez",
1598 "s,p", sreg);
670a50eb 1599 return;
3d3c5039 1600 }
670a50eb
ILT		 1601 if (imm_expr.X_add_number == 1)
1602 {
8358c818
ILT		 1603 macro_build (&icnt, &offset_expr,
1604 likely ? "bgtzl" : "bgtz",
1605 "s,p", sreg);
670a50eb 1606 return;
3d3c5039 1607 }
6e8dda9c
ILT		 1608 maxnum = 0x7fffffff;
1609 if (mips_isa >= 3)
1610 {
1611 maxnum <<= 16;
1612 maxnum |= 0xffff;
1613 maxnum <<= 16;
1614 maxnum |= 0xffff;
1615 }
1616 maxnum = - maxnum - 1;
1617 if (imm_expr.X_add_number <= maxnum)
9a7d824a
ILT		 1618 {
1619 do_true:
1620 /* result is always true */
1621 as_warn ("Branch %s is always true", ip->insn_mo->name);
1622 macro_build (&icnt, &offset_expr, "b", "p");
1623 return;
1624 }
6e8dda9c 1625 set_at (&icnt, sreg, 0);
8358c818
ILT		 1626 macro_build (&icnt, &offset_expr,
1627 likely ? "beql" : "beq",
1628 "s,t,p", AT, 0);
670a50eb 1629 break;
3d3c5039 1630
8358c818
ILT		 1631 case M_BGEUL:
1632 likely = 1;
3d3c5039 1633 case M_BGEU:
670a50eb 1634 if (treg == 0)
9a7d824a
ILT		 1635 goto do_true;
1636 if (sreg == 0)
670a50eb 1637 {
8358c818
ILT		 1638 macro_build (&icnt, &offset_expr,
1639 likely ? "beql" : "beq",
1640 "s,t,p", 0, treg);
670a50eb 1641 return;
3d3c5039 1642 }
670a50eb 1643 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
8358c818
ILT		 1644 macro_build (&icnt, &offset_expr,
1645 likely ? "beql" : "beq",
1646 "s,t,p", AT, 0);
670a50eb 1647 break;
3d3c5039 1648
8358c818
ILT		 1649 case M_BGTUL_I:
1650 likely = 1;
9a7d824a 1651 case M_BGTU_I:
6e8dda9c 1652 if (sreg == 0 || imm_expr.X_add_number == -1)
9a7d824a
ILT		 1653 goto do_false;
1654 imm_expr.X_add_number++;
1655 /* FALLTHROUGH */
3d3c5039 1656 case M_BGEU_I:
8358c818
ILT		 1657 case M_BGEUL_I:
1658 if (mask == M_BGEUL_I)
1659 likely = 1;
670a50eb 1660 if (imm_expr.X_add_number == 0)
9a7d824a 1661 goto do_true;
670a50eb
ILT		 1662 if (imm_expr.X_add_number == 1)
1663 {
8358c818
ILT		 1664 macro_build (&icnt, &offset_expr,
1665 likely ? "bnel" : "bne",
1666 "s,t,p", sreg, 0);
670a50eb 1667 return;
3d3c5039 1668 }
6e8dda9c 1669 set_at (&icnt, sreg, 1);
8358c818
ILT		 1670 macro_build (&icnt, &offset_expr,
1671 likely ? "beql" : "beq",
1672 "s,t,p", AT, 0);
670a50eb 1673 break;
3d3c5039 1674
8358c818
ILT		 1675 case M_BGTL:
1676 likely = 1;
3d3c5039 1677 case M_BGT:
670a50eb
ILT		 1678 if (treg == 0)
1679 {
8358c818
ILT		 1680 macro_build (&icnt, &offset_expr,
1681 likely ? "bgtzl" : "bgtz",
1682 "s,p", sreg);
670a50eb 1683 return;
3d3c5039 1684 }
9a7d824a
ILT		 1685 if (sreg == 0)
1686 {
8358c818
ILT		 1687 macro_build (&icnt, &offset_expr,
1688 likely ? "bltzl" : "bltz",
1689 "s,p", treg);
9a7d824a
ILT		 1690 return;
1691 }
670a50eb 1692 macro_build (&icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
8358c818
ILT		 1693 macro_build (&icnt, &offset_expr,
1694 likely ? "bnel" : "bne",
1695 "s,t,p", AT, 0);
670a50eb 1696 break;
3d3c5039 1697
8358c818
ILT		 1698 case M_BGTUL:
1699 likely = 1;
3d3c5039 1700 case M_BGTU:
670a50eb
ILT		 1701 if (treg == 0)
1702 {
8358c818
ILT		 1703 macro_build (&icnt, &offset_expr,
1704 likely ? "bnel" : "bne",
1705 "s,t,p", sreg, 0);
670a50eb 1706 return;
3d3c5039 1707 }
9a7d824a
ILT		 1708 if (sreg == 0)
1709 goto do_false;
670a50eb 1710 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
8358c818
ILT		 1711 macro_build (&icnt, &offset_expr,
1712 likely ? "bnel" : "bne",
1713 "s,t,p", AT, 0);
670a50eb 1714 break;
3d3c5039 1715
8358c818
ILT		 1716 case M_BLEL:
1717 likely = 1;
3d3c5039 1718 case M_BLE:
670a50eb
ILT		 1719 if (treg == 0)
1720 {
8358c818
ILT		 1721 macro_build (&icnt, &offset_expr,
1722 likely ? "blezl" : "blez",
1723 "s,p", sreg);
670a50eb
ILT		 1724 return;
1725 }
9a7d824a
ILT		 1726 if (sreg == 0)
1727 {
8358c818
ILT		 1728 macro_build (&icnt, &offset_expr,
1729 likely ? "bgezl" : "bgez",
1730 "s,p", treg);
9a7d824a
ILT		 1731 return;
1732 }
670a50eb 1733 macro_build (&icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
8358c818
ILT		 1734 macro_build (&icnt, &offset_expr,
1735 likely ? "beql" : "beq",
1736 "s,t,p", AT, 0);
670a50eb 1737 break;
3d3c5039 1738
8358c818
ILT		 1739 case M_BLEL_I:
1740 likely = 1;
3d3c5039 1741 case M_BLE_I:
6e8dda9c
ILT		 1742 maxnum = 0x7fffffff;
1743 if (mips_isa >= 3)
1744 {
1745 maxnum <<= 16;
1746 maxnum |= 0xffff;
1747 maxnum <<= 16;
1748 maxnum |= 0xffff;
1749 }
1750 if (imm_expr.X_add_number >= maxnum)
9a7d824a
ILT		 1751 goto do_true;
1752 imm_expr.X_add_number++;
1753 /* FALLTHROUGH */
9a7d824a 1754 case M_BLT_I:
8358c818
ILT		 1755 case M_BLTL_I:
1756 if (mask == M_BLTL_I)
1757 likely = 1;
670a50eb
ILT		 1758 if (imm_expr.X_add_number == 0)
1759 {
8358c818
ILT		 1760 macro_build (&icnt, &offset_expr,
1761 likely ? "bltzl" : "bltz",
1762 "s,p", sreg);
670a50eb
ILT		 1763 return;
1764 }
9a7d824a 1765 if (imm_expr.X_add_number == 1)
670a50eb 1766 {
8358c818
ILT		 1767 macro_build (&icnt, &offset_expr,
1768 likely ? "blezl" : "blez",
1769 "s,p", sreg);
670a50eb
ILT		 1770 return;
1771 }
6e8dda9c 1772 set_at (&icnt, sreg, 0);
8358c818
ILT		 1773 macro_build (&icnt, &offset_expr,
1774 likely ? "bnel" : "bne",
1775 "s,t,p", AT, 0);
670a50eb 1776 break;
3d3c5039 1777
8358c818
ILT		 1778 case M_BLEUL:
1779 likely = 1;
3d3c5039 1780 case M_BLEU:
670a50eb
ILT		 1781 if (treg == 0)
1782 {
8358c818
ILT		 1783 macro_build (&icnt, &offset_expr,
1784 likely ? "beql" : "beq",
1785 "s,t,p", sreg, 0);
670a50eb 1786 return;
3d3c5039 1787 }
9a7d824a
ILT		 1788 if (sreg == 0)
1789 goto do_true;
670a50eb 1790 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
8358c818
ILT		 1791 macro_build (&icnt, &offset_expr,
1792 likely ? "beql" : "beq",
1793 "s,t,p", AT, 0);
670a50eb 1794 break;
3d3c5039 1795
8358c818
ILT		 1796 case M_BLEUL_I:
1797 likely = 1;
3d3c5039 1798 case M_BLEU_I:
6e8dda9c 1799 if (sreg == 0 || imm_expr.X_add_number == -1)
9a7d824a
ILT		 1800 goto do_true;
1801 imm_expr.X_add_number++;
1802 /* FALLTHROUGH */
9a7d824a 1803 case M_BLTU_I:
8358c818
ILT		 1804 case M_BLTUL_I:
1805 if (mask == M_BLTUL_I)
1806 likely = 1;
670a50eb 1807 if (imm_expr.X_add_number == 0)
9a7d824a
ILT		 1808 goto do_false;
1809 if (imm_expr.X_add_number == 1)
670a50eb 1810 {
8358c818
ILT		 1811 macro_build (&icnt, &offset_expr,
1812 likely ? "beql" : "beq",
1813 "s,t,p", sreg, 0);
670a50eb 1814 return;
3d3c5039 1815 }
6e8dda9c 1816 set_at (&icnt, sreg, 1);
8358c818
ILT		 1817 macro_build (&icnt, &offset_expr,
1818 likely ? "bnel" : "bne",
1819 "s,t,p", AT, 0);
670a50eb 1820 break;
3d3c5039 1821
8358c818
ILT		 1822 case M_BLTL:
1823 likely = 1;
3d3c5039 1824 case M_BLT:
670a50eb
ILT		 1825 if (treg == 0)
1826 {
8358c818
ILT		 1827 macro_build (&icnt, &offset_expr,
1828 likely ? "bltzl" : "bltz",
1829 "s,p", sreg);
670a50eb 1830 return;
3d3c5039 1831 }
9a7d824a 1832 if (sreg == 0)
670a50eb 1833 {
8358c818
ILT		 1834 macro_build (&icnt, &offset_expr,
1835 likely ? "bgtzl" : "bgtz",
1836 "s,p", treg);
670a50eb 1837 return;
3d3c5039 1838 }
9a7d824a 1839 macro_build (&icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
8358c818
ILT		 1840 macro_build (&icnt, &offset_expr,
1841 likely ? "bnel" : "bne",
1842 "s,t,p", AT, 0);
670a50eb 1843 break;
3d3c5039 1844
8358c818
ILT		 1845 case M_BLTUL:
1846 likely = 1;
3d3c5039 1847 case M_BLTU:
670a50eb 1848 if (treg == 0)
9a7d824a
ILT		 1849 goto do_false;
1850 if (sreg == 0)
670a50eb 1851 {
8358c818
ILT		 1852 macro_build (&icnt, &offset_expr,
1853 likely ? "bnel" : "bne",
1854 "s,t,p", 0, treg);
670a50eb
ILT		 1855 return;
1856 }
1857 macro_build (&icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
8358c818
ILT		 1858 macro_build (&icnt, &offset_expr,
1859 likely ? "bnel" : "bne",
1860 "s,t,p", AT, 0);
670a50eb 1861 break;
3d3c5039 1862
8358c818
ILT		 1863 case M_DDIV_3:
1864 dbl = 1;
3d3c5039 1865 case M_DIV_3:
8358c818
ILT		 1866 s = "mflo";
1867 goto do_div3;
1868 case M_DREM_3:
1869 dbl = 1;
3d3c5039 1870 case M_REM_3:
8358c818
ILT		 1871 s = "mfhi";
1872 do_div3:
670a50eb
ILT		 1873 if (treg == 0)
1874 {
1875 as_warn ("Divide by zero.");
1876 macro_build (&icnt, NULL, "break", "c", 7);
1877 return;
1878 }
1879
becfe05e
ILT		 1880 mips_emit_delays ();
1881 ++mips_noreorder;
8358c818
ILT		 1882 macro_build (&icnt, NULL,
1883 dbl ? "ddiv" : "div",
ff3a5c18 1884 "z,s,t", sreg, treg);
670a50eb
ILT		 1885 expr1.X_add_number = 8;
1886 macro_build (&icnt, &expr1, "bne", "s,t,p", treg, 0);
1887 macro_build (&icnt, NULL, "nop", "", 0);
1888 macro_build (&icnt, NULL, "break", "c", 7);
1889 expr1.X_add_number = -1;
8358c818
ILT		 1890 macro_build (&icnt, &expr1,
1891 dbl ? "daddiu" : "addiu",
1892 "t,r,j", AT, 0);
1893 expr1.X_add_number = dbl ? 20 : 16;
670a50eb 1894 macro_build (&icnt, &expr1, "bne", "s,t,p", treg, AT);
8358c818
ILT		 1895 if (dbl)
1896 {
1897 expr1.X_add_number = 1;
1898 macro_build (&icnt, &expr1, "daddiu", "t,r,j", AT, 0);
1899 macro_build (&icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
1900 }
1901 else
1902 {
1903 expr1.X_add_number = 0x80000000;
6e8dda9c 1904 macro_build (&icnt, &expr1, "lui", "t,u", AT);
8358c818 1905 }
670a50eb
ILT		 1906 expr1.X_add_number = 8;
1907 macro_build (&icnt, &expr1, "bne", "s,t,p", sreg, AT);
1908 macro_build (&icnt, NULL, "nop", "", 0);
1909 macro_build (&icnt, NULL, "break", "c", 6);
becfe05e 1910 --mips_noreorder;
8358c818 1911 macro_build (&icnt, NULL, s, "d", dreg);
670a50eb 1912 break;
3d3c5039
ILT		 1913
1914 case M_DIV_3I:
8358c818
ILT		 1915 s = "div";
1916 s2 = "mflo";
1917 goto do_divi;
3d3c5039 1918 case M_DIVU_3I:
8358c818
ILT		 1919 s = "divu";
1920 s2 = "mflo";
1921 goto do_divi;
3d3c5039 1922 case M_REM_3I:
8358c818
ILT		 1923 s = "div";
1924 s2 = "mfhi";
1925 goto do_divi;
3d3c5039 1926 case M_REMU_3I:
8358c818
ILT		 1927 s = "divu";
1928 s2 = "mfhi";
1929 goto do_divi;
1930 case M_DDIV_3I:
1931 dbl = 1;
1932 s = "ddiv";
1933 s2 = "mflo";
1934 goto do_divi;
1935 case M_DDIVU_3I:
1936 dbl = 1;
1937 s = "ddivu";
1938 s2 = "mflo";
1939 goto do_divi;
1940 case M_DREM_3I:
1941 dbl = 1;
1942 s = "ddiv";
1943 s2 = "mfhi";
1944 goto do_divi;
1945 case M_DREMU_3I:
1946 dbl = 1;
1947 s = "ddivu";
1948 s2 = "mfhi";
1949 do_divi:
670a50eb
ILT		 1950 if (imm_expr.X_add_number == 0)
1951 {
1952 as_warn ("Divide by zero.");
1953 macro_build (&icnt, NULL, "break", "c", 7);
1954 return;
1955 }
1956 if (imm_expr.X_add_number == 1)
1957 {
8358c818 1958 if (strcmp (s2, "mflo") == 0)
670a50eb 1959 macro_build (&icnt, NULL, "move", "d,s", dreg, sreg);
3d3c5039 1960 else
670a50eb 1961 macro_build (&icnt, NULL, "move", "d,s", dreg, 0);
3d3c5039
ILT		 1962 return;
1963 }
8358c818
ILT		 1964 if (imm_expr.X_add_number == -1
1965 && s[strlen (s) - 1] != 'u')
1966 {
1967 if (strcmp (s2, "mflo") == 0)
1968 {
1969 if (dbl)
1970 macro_build (&icnt, NULL, "dneg", "d,w", dreg, sreg);
1971 else
1972 macro_build (&icnt, NULL, "neg", "d,w", dreg, sreg);
1973 }
1974 else
1975 macro_build (&icnt, NULL, "move", "d,s", dreg, 0);
1976 return;
1977 }
3d3c5039 1978
6e8dda9c 1979 load_register (&icnt, AT, &imm_expr);
ff3a5c18 1980 macro_build (&icnt, NULL, s, "z,s,t", sreg, AT);
8358c818 1981 macro_build (&icnt, NULL, s2, "d", dreg);
670a50eb
ILT		 1982 break;
1983
1984 case M_DIVU_3:
8358c818
ILT		 1985 s = "divu";
1986 s2 = "mflo";
1987 goto do_divu3;
670a50eb 1988 case M_REMU_3:
8358c818
ILT		 1989 s = "divu";
1990 s2 = "mfhi";
1991 goto do_divu3;
1992 case M_DDIVU_3:
1993 s = "ddivu";
1994 s2 = "mflo";
1995 goto do_divu3;
1996 case M_DREMU_3:
1997 s = "ddivu";
1998 s2 = "mfhi";
1999 do_divu3:
becfe05e
ILT		 2000 mips_emit_delays ();
2001 ++mips_noreorder;
ff3a5c18 2002 macro_build (&icnt, NULL, s, "z,s,t", sreg, treg);
670a50eb
ILT		 2003 expr1.X_add_number = 8;
2004 macro_build (&icnt, &expr1, "bne", "s,t,p", treg, 0);
2005 macro_build (&icnt, NULL, "nop", "", 0);
2006 macro_build (&icnt, NULL, "break", "c", 7);
becfe05e 2007 --mips_noreorder;
8358c818 2008 macro_build (&icnt, NULL, s2, "d", dreg);
670a50eb 2009 return;
3d3c5039
ILT		 2010
2011 case M_LA:
5ac34ac3 2012 if (offset_expr.X_op == O_constant)
670a50eb 2013 {
6e8dda9c 2014 load_register (&icnt, treg, &offset_expr);
670a50eb 2015 return;
3d3c5039 2016 }
670a50eb 2017 if (gp_reference (&offset_expr))
6e8dda9c
ILT		 2018 macro_build (&icnt, &offset_expr,
2019 mips_isa < 3 ? "addiu" : "daddiu",
2020 "t,r,j", treg, GP);
670a50eb
ILT		 2021 else
2022 {
6e8dda9c 2023 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2024 macro_build_lui (&icnt, &offset_expr, treg);
6e8dda9c
ILT		 2025 macro_build (&icnt, &offset_expr,
2026 mips_isa < 3 ? "addiu" : "daddiu",
2027 "t,r,j", treg, treg);
670a50eb
ILT		 2028 }
2029 return;
3d3c5039
ILT		 2030
2031 case M_LA_AB:
670a50eb 2032 tempreg = (breg == treg) ? AT : treg;
5ac34ac3 2033 if (offset_expr.X_op == O_constant)
6e8dda9c 2034 load_register (&icnt, tempreg, &offset_expr);
670a50eb 2035 else if (gp_reference (&offset_expr))
6e8dda9c
ILT		 2036 macro_build (&icnt, &offset_expr,
2037 mips_isa < 3 ? "addiu" : "daddiu",
2038 "t,r,j", tempreg, GP);
670a50eb
ILT		 2039 else
2040 {
6e8dda9c 2041 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2042 macro_build_lui (&icnt, &offset_expr, tempreg);
6e8dda9c
ILT		 2043 macro_build (&icnt, &offset_expr,
2044 mips_isa < 3 ? "addiu" : "daddiu",
2045 "t,r,j", tempreg, tempreg);
670a50eb
ILT		 2046 }
2047 if (breg != 0)
2048 macro_build (&icnt, NULL, "addu", "d,v,t", treg, tempreg, breg);
2049 if (breg == treg)
2050 break;
2051 return;
3d3c5039
ILT		 2052
2053 case M_LB_AB:
670a50eb
ILT		 2054 s = "lb";
2055 goto ld;
3d3c5039 2056 case M_LBU_AB:
670a50eb
ILT		 2057 s = "lbu";
2058 goto ld;
3d3c5039 2059 case M_LH_AB:
670a50eb
ILT		 2060 s = "lh";
2061 goto ld;
3d3c5039 2062 case M_LHU_AB:
670a50eb
ILT		 2063 s = "lhu";
2064 goto ld;
3d3c5039 2065 case M_LW_AB:
670a50eb
ILT		 2066 s = "lw";
2067 goto ld;
3d3c5039 2068 case M_LWC0_AB:
670a50eb 2069 s = "lwc0";
8358c818 2070 coproc = 1;
670a50eb 2071 goto ld;
3d3c5039 2072 case M_LWC1_AB:
19ed8960 2073 case M_LI_SS:
670a50eb 2074 s = "lwc1";
8358c818 2075 coproc = 1;
670a50eb 2076 goto ld;
3d3c5039 2077 case M_LWC2_AB:
670a50eb 2078 s = "lwc2";
8358c818 2079 coproc = 1;
670a50eb 2080 goto ld;
3d3c5039 2081 case M_LWC3_AB:
670a50eb 2082 s = "lwc3";
8358c818 2083 coproc = 1;
670a50eb 2084 goto ld;
3d3c5039 2085 case M_LWL_AB:
670a50eb
ILT		 2086 s = "lwl";
2087 goto ld;
3d3c5039 2088 case M_LWR_AB:
670a50eb 2089 s = "lwr";
8358c818
ILT		 2090 goto ld;
2091 case M_LDC1_AB:
2092 s = "ldc1";
2093 coproc = 1;
2094 goto ld;
2095 case M_LDC2_AB:
2096 s = "ldc2";
2097 coproc = 1;
2098 goto ld;
2099 case M_LDC3_AB:
2100 s = "ldc3";
2101 coproc = 1;
2102 goto ld;
2103 case M_LDL_AB:
2104 s = "ldl";
2105 goto ld;
2106 case M_LDR_AB:
2107 s = "ldr";
2108 goto ld;
2109 case M_LL_AB:
2110 s = "ll";
2111 goto ld;
2112 case M_LLD_AB:
2113 s = "lld";
2114 goto ld;
2115 case M_LWU_AB:
2116 s = "lwu";
3d3c5039 2117 ld:
8358c818 2118 if (breg == treg || coproc)
670a50eb
ILT		 2119 {
2120 tempreg = AT;
2121 used_at = 1;
2122 }
2123 else
2124 {
2125 tempreg = treg;
2126 used_at = 0;
2127 }
2128 goto ld_st;
3d3c5039 2129 case M_SB_AB:
670a50eb
ILT		 2130 s = "sb";
2131 goto st;
3d3c5039 2132 case M_SH_AB:
670a50eb
ILT		 2133 s = "sh";
2134 goto st;
3d3c5039 2135 case M_SW_AB:
670a50eb
ILT		 2136 s = "sw";
2137 goto st;
3d3c5039 2138 case M_SWC0_AB:
670a50eb 2139 s = "swc0";
8358c818 2140 coproc = 1;
670a50eb 2141 goto st;
3d3c5039 2142 case M_SWC1_AB:
670a50eb 2143 s = "swc1";
8358c818 2144 coproc = 1;
670a50eb 2145 goto st;
3d3c5039 2146 case M_SWC2_AB:
670a50eb 2147 s = "swc2";
8358c818 2148 coproc = 1;
670a50eb 2149 goto st;
3d3c5039 2150 case M_SWC3_AB:
670a50eb 2151 s = "swc3";
8358c818 2152 coproc = 1;
670a50eb 2153 goto st;
3d3c5039 2154 case M_SWL_AB:
670a50eb
ILT		 2155 s = "swl";
2156 goto st;
3d3c5039 2157 case M_SWR_AB:
670a50eb 2158 s = "swr";
8358c818
ILT		 2159 goto st;
2160 case M_SC_AB:
2161 s = "sc";
2162 goto st;
2163 case M_SCD_AB:
2164 s = "scd";
2165 goto st;
2166 case M_SDC1_AB:
2167 s = "sdc1";
2168 coproc = 1;
2169 goto st;
2170 case M_SDC2_AB:
2171 s = "sdc2";
2172 coproc = 1;
2173 goto st;
2174 case M_SDC3_AB:
2175 s = "sdc3";
2176 coproc = 1;
2177 goto st;
2178 case M_SDL_AB:
2179 s = "sdl";
2180 goto st;
2181 case M_SDR_AB:
2182 s = "sdr";
3d3c5039 2183 st:
670a50eb
ILT		 2184 tempreg = AT;
2185 used_at = 1;
3d3c5039 2186 ld_st:
8358c818
ILT		 2187 if (mask == M_LWC1_AB
2188 || mask == M_SWC1_AB
2189 || mask == M_LI_SS
2190 || mask == M_LDC1_AB
2191 || mask == M_SDC1_AB)
670a50eb 2192 fmt = "T,o(b)";
8358c818 2193 else if (coproc)
19ed8960 2194 fmt = "E,o(b)";
670a50eb
ILT		 2195 else
2196 fmt = "t,o(b)";
2197 if (gp_reference (&offset_expr))
2198 {
2199 if (breg == 0)
2200 {
2201 macro_build (&icnt, &offset_expr, s, fmt, treg, GP);
2202 return;
2203 }
6e8dda9c
ILT		 2204 macro_build (&icnt, (expressionS *) NULL,
2205 mips_isa < 3 ? "addu" : "daddu",
2206 "d,v,t", tempreg, breg, GP);
670a50eb
ILT		 2207 }
2208 else
2209 {
6e8dda9c 2210 /* FIXME: This won't work for a 64 bit address. */
670a50eb
ILT		 2211 macro_build_lui (&icnt, &offset_expr, tempreg);
2212 if (breg != 0)
6e8dda9c
ILT		 2213 macro_build (&icnt, NULL,
2214 mips_isa < 3 ? "addu" : "daddu",
2215 "d,v,t", tempreg, tempreg, breg);
670a50eb
ILT		 2216 }
2217 macro_build (&icnt, &offset_expr, s, fmt, treg, tempreg);
2218 if (used_at)
2219 break;
2220 return;
3d3c5039
ILT		 2221
2222 case M_LI:
19ed8960 2223 case M_LI_S:
6e8dda9c 2224 load_register (&icnt, treg, &imm_expr);
670a50eb 2225 return;
3d3c5039
ILT		 2226
2227 case M_LI_D:
19ed8960
ILT		 2228 /* lui $at,%hi(foo)
2229 lw $v0,%lo(foo)($at)
2230 lw $v1,%lo(foo+4)($at)
2231 .rdata
2232 foo:
2233 .double 3.133435
2234 */
6e8dda9c 2235 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2236 macro_build_lui (&icnt, &offset_expr, AT);
8358c818
ILT		 2237 if (mips_isa >= 3)
2238 macro_build (&icnt, &offset_expr, "ld", "t,o(b)", treg, AT);
2239 else
2240 {
2241 macro_build (&icnt, &offset_expr, "lw", "t,o(b)", treg, AT);
2242 offset_expr.X_add_number += 4;
2243 macro_build (&icnt, &offset_expr, "lw", "t,o(b)", treg + 1, AT);
2244 }
670a50eb 2245 break;
3d3c5039
ILT		 2246
2247 case M_LI_DD:
19ed8960 2248 /* Load a floating point number from the .lit8 section. */
8358c818
ILT		 2249 if (mips_isa >= 2)
2250 {
2251 macro_build (&icnt, &offset_expr, "ldc1", "T,o(b)", treg, GP);
2252 return;
2253 }
19ed8960
ILT		 2254 breg = GP;
2255 /* Fall through. */
3d3c5039 2256 case M_L_DOB:
9a7d824a
ILT		 2257 /* Even on a big endian machine $fn comes before $fn+1. We have
2258 to adjust when loading from memory. */
8358c818 2259 assert (mips_isa < 2);
9a7d824a
ILT		 2260 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2261 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2262 breg);
670a50eb 2263 offset_expr.X_add_number += 4;
9a7d824a
ILT		 2264 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2265 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2266 breg);
670a50eb 2267 return;
3d3c5039
ILT		 2268
2269 case M_L_DAB:
670a50eb
ILT		 2270 /*
2271 * The MIPS assembler seems to check for X_add_number not
2272 * being double aligned and generating:
2273 * lui at,%hi(foo+1)
2274 * addu at,at,v1
2275 * addiu at,at,%lo(foo+1)
2276 * lwc1 f2,0(at)
2277 * lwc1 f3,4(at)
2278 * But, the resulting address is the same after relocation so why
2279 * generate the extra instruction?
2280 */
2281 if (gp_reference (&offset_expr))
2282 {
2283 if (breg == 0)
2284 tempreg = GP;
2285 else
2286 {
6e8dda9c
ILT		 2287 macro_build (&icnt, &offset_expr,
2288 mips_isa < 3 ? "addu" : "daddu",
2289 "d,v,t", AT, breg, GP);
670a50eb
ILT		 2290 tempreg = AT;
2291 }
2292 }
2293 else
2294 {
6e8dda9c 2295 /* FIXME: This won't work for a 64 bit address. */
670a50eb
ILT		 2296 macro_build_lui (&icnt, &offset_expr, AT);
2297 if (breg != 0)
6e8dda9c
ILT		 2298 macro_build (&icnt, NULL,
2299 mips_isa < 3 ? "addu" : "daddu",
2300 "d,v,t", AT, AT, breg);
670a50eb
ILT		 2301 tempreg = AT;
2302 }
8358c818
ILT		 2303 if (mips_isa >= 2)
2304 macro_build (&icnt, &offset_expr, "ldc1", "T,o(b)", treg, tempreg);
2305 else
2306 {
2307 /* Even on a big endian machine $fn comes before $fn+1. We
2308 have to adjust when loading from memory. */
2309 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2310 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2311 tempreg);
2312 offset_expr.X_add_number += 4;
2313 macro_build (&icnt, &offset_expr, "lwc1", "T,o(b)",
2314 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2315 tempreg);
2316 }
670a50eb 2317 if (tempreg == AT)
3d3c5039 2318 break;
670a50eb 2319 return;
3d3c5039
ILT		 2320
2321 case M_LD_OB:
670a50eb
ILT		 2322 s = "lw";
2323 goto sd_ob;
3d3c5039 2324 case M_SD_OB:
670a50eb 2325 s = "sw";
3d3c5039 2326 sd_ob:
8358c818 2327 assert (mips_isa < 3);
670a50eb 2328 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg, breg);
8358c818 2329 offset_expr.X_add_number += 4;
670a50eb
ILT		 2330 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg + 1, breg);
2331 return;
3d3c5039
ILT		 2332
2333 case M_LD_AB:
670a50eb 2334 s = "lw";
8358c818 2335 s2 = "ld";
670a50eb
ILT		 2336 if (breg == treg)
2337 {
2338 tempreg = AT;
2339 used_at = 1;
2340 }
2341 else
2342 {
2343 tempreg = treg;
2344 used_at = 0;
2345 }
2346 goto sd_ab;
3d3c5039 2347 case M_SD_AB:
670a50eb 2348 s = "sw";
8358c818 2349 s2 = "sd";
670a50eb
ILT		 2350 tempreg = AT;
2351 used_at = 1;
3d3c5039 2352 sd_ab:
670a50eb
ILT		 2353 if (gp_reference (&offset_expr))
2354 {
2355 if (breg == 0)
2356 {
2357 tempreg = GP;
2358 used_at = 0;
2359 }
2360 else
6e8dda9c
ILT		 2361 macro_build (&icnt, (expressionS *) NULL,
2362 mips_isa < 3 ? "addu" : "daddu",
2363 "d,v,t", tempreg, breg, GP);
670a50eb
ILT		 2364 }
2365 else
2366 {
6e8dda9c 2367 /* FIXME: This won't work for a 64 bit address. */
670a50eb
ILT		 2368 macro_build_lui (&icnt, &offset_expr, tempreg);
2369 if (breg != 0)
6e8dda9c
ILT		 2370 macro_build (&icnt, NULL,
2371 mips_isa < 3 ? "addu" : "daddu",
2372 "d,v,t", tempreg, tempreg, breg);
670a50eb 2373 }
8358c818
ILT		 2374 if (mips_isa >= 3)
2375 macro_build (&icnt, &offset_expr, s2, "t,o(b)", treg, tempreg);
2376 else
2377 {
2378 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg, tempreg);
2379 offset_expr.X_add_number += 4;
2380 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg + 1, tempreg);
2381 }
670a50eb
ILT		 2382 if (used_at)
2383 break;
2384 return;
3d3c5039 2385
8358c818
ILT		 2386 case M_DMUL:
2387 dbl = 1;
3d3c5039 2388 case M_MUL:
8358c818
ILT		 2389 macro_build (&icnt, NULL,
2390 dbl ? "dmultu" : "multu",
2391 "s,t", sreg, treg);
670a50eb 2392 macro_build (&icnt, NULL, "mflo", "d", dreg);
670a50eb 2393 return;
3d3c5039 2394
8358c818
ILT		 2395 case M_DMUL_I:
2396 dbl = 1;
3d3c5039 2397 case M_MUL_I:
8358c818
ILT		 2398 /* The MIPS assembler some times generates shifts and adds. I'm
2399 not trying to be that fancy. GCC should do this for us
2400 anyway. */
6e8dda9c 2401 load_register (&icnt, AT, &imm_expr);
8358c818
ILT		 2402 macro_build (&icnt, NULL,
2403 dbl ? "dmult" : "mult",
2404 "s,t", sreg, AT);
670a50eb 2405 macro_build (&icnt, NULL, "mflo", "d", dreg);
670a50eb 2406 break;
3d3c5039 2407
8358c818
ILT		 2408 case M_DMULO:
2409 dbl = 1;
2410 case M_MULO:
2411 mips_emit_delays ();
2412 ++mips_noreorder;
2413 macro_build (&icnt, NULL,
2414 dbl ? "dmult" : "mult",
2415 "s,t", sreg, treg);
2416 macro_build (&icnt, NULL, "mflo", "d", dreg);
2417 macro_build (&icnt, NULL,
2418 dbl ? "dsra32" : "sra",
2419 "d,w,<", dreg, dreg, 31);
2420 macro_build (&icnt, NULL, "mfhi", "d", AT);
2421 expr1.X_add_number = 8;
2422 macro_build (&icnt, &expr1, "beq", "s,t,p", dreg, AT);
2423 macro_build (&icnt, NULL, "nop", "", 0);
2424 macro_build (&icnt, NULL, "break", "c", 6);
2425 --mips_noreorder;
2426 macro_build (&icnt, NULL, "mflo", "d", dreg);
2427 break;
2428
2429 case M_DMULOU:
2430 dbl = 1;
2431 case M_MULOU:
2432 mips_emit_delays ();
2433 ++mips_noreorder;
2434 macro_build (&icnt, NULL,
2435 dbl ? "dmultu" : "multu",
2436 "s,t", sreg, treg);
2437 macro_build (&icnt, NULL, "mfhi", "d", AT);
2438 macro_build (&icnt, NULL, "mflo", "d", dreg);
2439 expr1.X_add_number = 8;
2440 macro_build (&icnt, &expr1, "beq", "s,t,p", AT, 0);
2441 macro_build (&icnt, NULL, "nop", "", 0);
2442 macro_build (&icnt, NULL, "break", "c", 6);
2443 --mips_noreorder;
2444 break;
2445
3d3c5039 2446 case M_ROL:
670a50eb
ILT		 2447 macro_build (&icnt, NULL, "subu", "d,v,t", AT, 0, treg);
2448 macro_build (&icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
2449 macro_build (&icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
2450 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2451 break;
3d3c5039
ILT		 2452
2453 case M_ROL_I:
670a50eb
ILT		 2454 macro_build (&icnt, NULL, "sll", "d,w,<", AT, sreg,
2455 imm_expr.X_add_number & 0x1f);
2456 macro_build (&icnt, NULL, "srl", "d,w,<", dreg, sreg,
2457 (0 - imm_expr.X_add_number) & 0x1f);
2458 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2459 break;
3d3c5039
ILT		 2460
2461 case M_ROR:
670a50eb
ILT		 2462 macro_build (&icnt, NULL, "subu", "d,v,t", AT, 0, treg);
2463 macro_build (&icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
2464 macro_build (&icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
2465 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2466 break;
3d3c5039
ILT		 2467
2468 case M_ROR_I:
670a50eb
ILT		 2469 macro_build (&icnt, NULL, "srl", "d,w,<", AT, sreg,
2470 imm_expr.X_add_number & 0x1f);
2471 macro_build (&icnt, NULL, "sll", "d,w,<", dreg, sreg,
2472 (0 - imm_expr.X_add_number) & 0x1f);
2473 macro_build (&icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
2474 break;
3d3c5039
ILT		 2475
2476 case M_S_DOB:
8358c818 2477 assert (mips_isa < 2);
9a7d824a
ILT		 2478 /* Even on a big endian machine $fn comes before $fn+1. We have
2479 to adjust when storing to memory. */
2480 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2481 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2482 breg);
670a50eb 2483 offset_expr.X_add_number += 4;
9a7d824a
ILT		 2484 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2485 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2486 breg);
670a50eb 2487 return;
3d3c5039
ILT		 2488
2489 case M_S_DAB:
670a50eb
ILT		 2490 if (gp_reference (&offset_expr))
2491 {
2492 if (breg == 0)
2493 tempreg = GP;
2494 else
2495 {
6e8dda9c
ILT		 2496 macro_build (&icnt, (expressionS *) NULL,
2497 mips_isa < 3 ? "addu" : "daddu",
2498 "d,v,t", AT, breg, GP);
670a50eb
ILT		 2499 tempreg = AT;
2500 }
2501 }
2502 else
2503 {
6e8dda9c 2504 /* FIXME: This won't work for a 64 bit address. */
670a50eb
ILT		 2505 macro_build_lui (&icnt, &offset_expr, AT);
2506 if (breg != 0)
6e8dda9c
ILT		 2507 macro_build (&icnt, NULL,
2508 mips_isa < 3 ? "addu" : "daddu",
2509 "d,v,t", AT, AT, breg);
670a50eb
ILT		 2510 tempreg = AT;
2511 }
8358c818
ILT		 2512 if (mips_isa >= 2)
2513 macro_build (&icnt, &offset_expr, "sdc1", "T,o(b)", treg, tempreg);
2514 else
2515 {
2516 /* Even on a big endian machine $fn comes before $fn+1. We
2517 have to adjust when storing to memory. */
2518 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2519 byte_order == LITTLE_ENDIAN ? treg : treg + 1,
2520 tempreg);
2521 offset_expr.X_add_number += 4;
2522 macro_build (&icnt, &offset_expr, "swc1", "T,o(b)",
2523 byte_order == LITTLE_ENDIAN ? treg + 1 : treg,
2524 tempreg);
2525 }
670a50eb 2526 if (tempreg == AT)
3d3c5039 2527 break;
670a50eb 2528 return;
3d3c5039
ILT		 2529
2530 case M_SEQ:
670a50eb
ILT		 2531 if (sreg == 0)
2532 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, treg);
2533 else if (treg == 0)
2534 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, sreg);
2535 else
2536 {
2537 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
2538 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, dreg);
3d3c5039 2539 }
670a50eb 2540 return;
3d3c5039
ILT		 2541
2542 case M_SEQ_I:
670a50eb
ILT		 2543 if (imm_expr.X_add_number == 0)
2544 {
2545 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, sreg);
2546 return;
3d3c5039 2547 }
670a50eb
ILT		 2548 if (sreg == 0)
2549 {
9a7d824a 2550 as_warn ("Instruction %s: result is always false",
6e8dda9c 2551 ip->insn_mo->name);
670a50eb
ILT		 2552 macro_build (&icnt, NULL, "move", "d,s", dreg, 0);
2553 return;
3d3c5039 2554 }
6e8dda9c 2555 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
670a50eb 2556 {
670a50eb
ILT		 2557 macro_build (&icnt, &imm_expr, "xori", "t,r,i", dreg, sreg);
2558 used_at = 0;
6e8dda9c
ILT		 2559 }
2560 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
2561 {
2562 imm_expr.X_add_number = -imm_expr.X_add_number;
2563 macro_build (&icnt, &imm_expr,
2564 mips_isa < 3 ? "addiu" : "daddiu",
2565 "t,r,j", dreg, sreg);
2566 used_at = 0;
2567 }
2568 else
2569 {
2570 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2571 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
2572 used_at = 1;
2573 }
2574 macro_build (&icnt, &expr1, "sltiu", "t,r,j", dreg, dreg);
2575 if (used_at)
2576 break;
2577 return;
3d3c5039
ILT		 2578
2579 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
670a50eb
ILT		 2580 s = "slt";
2581 goto sge;
3d3c5039 2582 case M_SGEU:
670a50eb 2583 s = "sltu";
3d3c5039 2584 sge:
670a50eb
ILT		 2585 macro_build (&icnt, NULL, s, "d,v,t", dreg, sreg, treg);
2586 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
2587 return;
3d3c5039 2588
670a50eb 2589 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
3d3c5039 2590 case M_SGEU_I:
6e8dda9c 2591 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb
ILT		 2592 {
2593 macro_build (&icnt, &expr1,
6e8dda9c
ILT		 2594 mask == M_SGE_I ? "slti" : "sltiu",
2595 "t,r,j", dreg, sreg);
670a50eb
ILT		 2596 used_at = 0;
2597 }
2598 else
2599 {
6e8dda9c 2600 load_register (&icnt, AT, &imm_expr);
670a50eb 2601 macro_build (&icnt, NULL,
6e8dda9c
ILT		 2602 mask == M_SGE_I ? "slt" : "sltu",
2603 "d,v,t", dreg, sreg, AT);
670a50eb
ILT		 2604 used_at = 1;
2605 }
2606 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
2607 if (used_at)
2608 break;
2609 return;
3d3c5039
ILT		 2610
2611 case M_SGT: /* sreg > treg <==> treg < sreg */
670a50eb
ILT		 2612 s = "slt";
2613 goto sgt;
3d3c5039 2614 case M_SGTU:
670a50eb 2615 s = "sltu";
3d3c5039 2616 sgt:
670a50eb
ILT		 2617 macro_build (&icnt, NULL, s, "d,v,t", dreg, treg, sreg);
2618 return;
3d3c5039 2619
670a50eb
ILT		 2620 case M_SGT_I: /* sreg > I <==> I < sreg */
2621 s = "slt";
2622 goto sgti;
3d3c5039 2623 case M_SGTU_I:
670a50eb 2624 s = "sltu";
3d3c5039 2625 sgti:
6e8dda9c 2626 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2627 macro_build (&icnt, NULL, s, "d,v,t", dreg, AT, sreg);
2628 break;
3d3c5039 2629
670a50eb
ILT		 2630 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2631 s = "slt";
2632 goto sle;
3d3c5039 2633 case M_SLEU:
670a50eb 2634 s = "sltu";
3d3c5039 2635 sle:
670a50eb 2636 macro_build (&icnt, NULL, s, "d,v,t", dreg, treg, sreg);
9a7d824a 2637 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
670a50eb 2638 return;
3d3c5039 2639
670a50eb
ILT		 2640 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2641 s = "slt";
2642 goto slei;
3d3c5039 2643 case M_SLEU_I:
670a50eb 2644 s = "sltu";
3d3c5039 2645 slei:
6e8dda9c 2646 load_register (&icnt, AT, &imm_expr);
670a50eb 2647 macro_build (&icnt, NULL, s, "d,v,t", dreg, AT, sreg);
9a7d824a 2648 macro_build (&icnt, &expr1, "xori", "t,r,i", dreg, dreg);
670a50eb 2649 break;
3d3c5039
ILT		 2650
2651 case M_SLT_I:
6e8dda9c 2652 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb
ILT		 2653 {
2654 macro_build (&icnt, &imm_expr, "slti", "t,r,j", dreg, sreg);
2655 return;
3d3c5039 2656 }
6e8dda9c 2657 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2658 macro_build (&icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
2659 break;
3d3c5039
ILT		 2660
2661 case M_SLTU_I:
6e8dda9c 2662 if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000)
670a50eb
ILT		 2663 {
2664 macro_build (&icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg);
2665 return;
3d3c5039 2666 }
6e8dda9c 2667 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2668 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
2669 break;
3d3c5039
ILT		 2670
2671 case M_SNE:
670a50eb
ILT		 2672 if (sreg == 0)
2673 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, treg);
2674 else if (treg == 0)
2675 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
2676 else
2677 {
2678 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
2679 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
3d3c5039 2680 }
670a50eb 2681 return;
3d3c5039
ILT		 2682
2683 case M_SNE_I:
670a50eb
ILT		 2684 if (imm_expr.X_add_number == 0)
2685 {
2686 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
2687 return;
3d3c5039 2688 }
670a50eb
ILT		 2689 if (sreg == 0)
2690 {
9a7d824a 2691 as_warn ("Instruction %s: result is always true",
6e8dda9c
ILT		 2692 ip->insn_mo->name);
2693 macro_build (&icnt, &expr1,
2694 mips_isa < 3 ? "addiu" : "daddiu",
2695 "t,r,j", dreg, 0);
670a50eb 2696 return;
3d3c5039 2697 }
6e8dda9c 2698 if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000)
670a50eb 2699 {
670a50eb
ILT		 2700 macro_build (&icnt, &imm_expr, "xori", "t,r,i", dreg, sreg);
2701 used_at = 0;
6e8dda9c
ILT		 2702 }
2703 else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0)
2704 {
2705 imm_expr.X_add_number = -imm_expr.X_add_number;
2706 macro_build (&icnt, &imm_expr,
2707 mips_isa < 3 ? "addiu" : "daddiu",
2708 "t,r,j", dreg, sreg);
2709 used_at = 0;
2710 }
2711 else
2712 {
2713 load_register (&icnt, AT, &imm_expr);
670a50eb
ILT		 2714 macro_build (&icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
2715 used_at = 1;
2716 }
2717 macro_build (&icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
2718 if (used_at)
2719 break;
2720 return;
3d3c5039 2721
8358c818
ILT		 2722 case M_DSUB_I:
2723 dbl = 1;
3d3c5039 2724 case M_SUB_I:
6e8dda9c 2725 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
670a50eb
ILT		 2726 {
2727 imm_expr.X_add_number = -imm_expr.X_add_number;
8358c818
ILT		 2728 macro_build (&icnt, &imm_expr,
2729 dbl ? "daddi" : "addi",
2730 "t,r,j", dreg, sreg);
670a50eb 2731 return;
3d3c5039 2732 }
6e8dda9c 2733 load_register (&icnt, AT, &imm_expr);
8358c818
ILT		 2734 macro_build (&icnt, NULL,
2735 dbl ? "dsub" : "sub",
2736 "d,v,t", dreg, sreg, AT);
670a50eb 2737 break;
3d3c5039 2738
8358c818
ILT		 2739 case M_DSUBU_I:
2740 dbl = 1;
3d3c5039 2741 case M_SUBU_I:
6e8dda9c 2742 if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000)
670a50eb
ILT		 2743 {
2744 imm_expr.X_add_number = -imm_expr.X_add_number;
8358c818
ILT		 2745 macro_build (&icnt, &imm_expr,
2746 dbl ? "daddiu" : "addiu",
2747 "t,r,j", dreg, sreg);
670a50eb 2748 return;
3d3c5039 2749 }
6e8dda9c 2750 load_register (&icnt, AT, &imm_expr);
8358c818
ILT		 2751 macro_build (&icnt, NULL,
2752 dbl ? "dsubu" : "subu",
2753 "d,v,t", dreg, sreg, AT);
2754 break;
2755
2756 case M_TEQ_I:
2757 s = "teq";
2758 goto trap;
2759 case M_TGE_I:
2760 s = "tge";
2761 goto trap;
2762 case M_TGEU_I:
2763 s = "tgeu";
2764 goto trap;
2765 case M_TLT_I:
2766 s = "tlt";
2767 goto trap;
2768 case M_TLTU_I:
2769 s = "tltu";
2770 goto trap;
2771 case M_TNE_I:
2772 s = "tne";
2773 trap:
6e8dda9c 2774 load_register (&icnt, AT, &imm_expr);
8358c818 2775 macro_build (&icnt, NULL, s, "s,t", sreg, AT);
670a50eb 2776 break;
3d3c5039
ILT		 2777
2778 case M_TRUNCWD:
2779 case M_TRUNCWS:
8358c818 2780 assert (mips_isa < 2);
670a50eb
ILT		 2781 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
2782 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
2783
2784 /*
2785 * Is the double cfc1 instruction a bug in the mips assembler;
2786 * or is there a reason for it?
2787 */
becfe05e
ILT		 2788 mips_emit_delays ();
2789 ++mips_noreorder;
918692a5
ILT		 2790 macro_build (&icnt, NULL, "cfc1", "t,G", treg, 31);
2791 macro_build (&icnt, NULL, "cfc1", "t,G", treg, 31);
670a50eb
ILT		 2792 macro_build (&icnt, NULL, "nop", "");
2793 expr1.X_add_number = 3;
2794 macro_build (&icnt, &expr1, "ori", "t,r,i", AT, treg);
2795 expr1.X_add_number = 2;
2796 macro_build (&icnt, &expr1, "xori", "t,r,i", AT, AT);
918692a5 2797 macro_build (&icnt, NULL, "ctc1", "t,G", AT, 31);
670a50eb
ILT		 2798 macro_build (&icnt, NULL, "nop", "");
2799 macro_build (&icnt, NULL,
2800 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
918692a5 2801 macro_build (&icnt, NULL, "ctc1", "t,G", treg, 31);
670a50eb 2802 macro_build (&icnt, NULL, "nop", "");
becfe05e 2803 --mips_noreorder;
670a50eb 2804 break;
3d3c5039
ILT		 2805
2806 case M_ULH:
670a50eb
ILT		 2807 s = "lb";
2808 goto ulh;
3d3c5039 2809 case M_ULHU:
670a50eb 2810 s = "lbu";
3d3c5039 2811 ulh:
670a50eb
ILT		 2812 /* avoid load delay */
2813 offset_expr.X_add_number += 1;
2814 macro_build (&icnt, &offset_expr, s, "t,o(b)", treg, breg);
2815 offset_expr.X_add_number -= 1;
2816 macro_build (&icnt, &offset_expr, "lbu", "t,o(b)", AT, breg);
2817 macro_build (&icnt, NULL, "sll", "d,w,<", treg, treg, 8);
2818 macro_build (&icnt, NULL, "or", "d,v,t", treg, treg, AT);
2819 break;
3d3c5039
ILT		 2820
2821 case M_ULW:
670a50eb
ILT		 2822 /* does this work on a big endian machine? */
2823 offset_expr.X_add_number += 3;
2824 macro_build (&icnt, &offset_expr, "lwl", "t,o(b)", treg, breg);
2825 offset_expr.X_add_number -= 3;
2826 macro_build (&icnt, &offset_expr, "lwr", "t,o(b)", treg, breg);
2827 return;
3d3c5039
ILT		 2828
2829 case M_ULH_A:
2830 case M_ULHU_A:
2831 case M_ULW_A:
5ac34ac3 2832 if (offset_expr.X_op == O_constant)
6e8dda9c 2833 load_register (&icnt, AT, &offset_expr);
670a50eb 2834 else if (gp_reference (&offset_expr))
6e8dda9c
ILT		 2835 macro_build (&icnt, &offset_expr,
2836 mips_isa < 3 ? "addiu" : "daddiu",
2837 "t,r,j", AT, GP);
670a50eb
ILT		 2838 else
2839 {
6e8dda9c 2840 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2841 macro_build_lui (&icnt, &offset_expr, AT);
6e8dda9c
ILT		 2842 macro_build (&icnt, &offset_expr,
2843 mips_isa < 3 ? "addiu" : "daddiu",
2844 "t,r,j", AT, AT);
3d3c5039 2845 }
670a50eb
ILT		 2846 if (mask == M_ULW_A)
2847 {
2848 expr1.X_add_number = 3;
2849 macro_build (&icnt, &expr1, "lwl", "t,o(b)", treg, AT);
2850 imm_expr.X_add_number = 0;
2851 macro_build (&icnt, &expr1, "lwr", "t,o(b)", treg, AT);
2852 }
2853 else
2854 {
2855 macro_build (&icnt, &expr1,
2856 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, AT);
2857 imm_expr.X_add_number = 0;
2858 macro_build (&icnt, &expr1, "lbu", "t,o(b)", AT, AT);
2859 macro_build (&icnt, NULL, "sll", "d,w,<", treg, treg, 8);
2860 macro_build (&icnt, NULL, "or", "d,v,t", treg, treg, AT);
2861 }
2862 break;
3d3c5039
ILT		 2863
2864 case M_USH:
670a50eb
ILT		 2865 macro_build (&icnt, &offset_expr, "sb", "t,o(b)", treg, breg);
2866 macro_build (&icnt, NULL, "srl", "d,w,<", AT, treg, 8);
2867 offset_expr.X_add_number += 1;
2868 macro_build (&icnt, &offset_expr, "sb", "t,o(b)", AT, breg);
2869 break;
3d3c5039
ILT		 2870
2871 case M_USW:
670a50eb
ILT		 2872 offset_expr.X_add_number += 3;
2873 macro_build (&icnt, &offset_expr, "swl", "t,o(b)", treg, breg);
2874 offset_expr.X_add_number -= 3;
2875 macro_build (&icnt, &offset_expr, "swr", "t,o(b)", treg, breg);
2876 return;
3d3c5039
ILT		 2877
2878 case M_USH_A:
2879 case M_USW_A:
5ac34ac3 2880 if (offset_expr.X_op == O_constant)
6e8dda9c 2881 load_register (&icnt, AT, &offset_expr);
670a50eb 2882 else if (gp_reference (&offset_expr))
6e8dda9c
ILT		 2883 macro_build (&icnt, &offset_expr,
2884 mips_isa < 3 ? "addiu" : "daddiu",
2885 "t,r,j", AT, GP);
670a50eb
ILT		 2886 else
2887 {
6e8dda9c 2888 /* FIXME: This won't work for a 64 bit address. */
670a50eb 2889 macro_build_lui (&icnt, &offset_expr, AT);
6e8dda9c
ILT		 2890 macro_build (&icnt, &offset_expr,
2891 mips_isa < 3 ? "addiu" : "daddiu",
2892 "t,r,j", AT, AT);
3d3c5039 2893 }
670a50eb
ILT		 2894 if (mask == M_USW_A)
2895 {
2896 expr1.X_add_number = 3;
2897 macro_build (&icnt, &expr1, "swl", "t,o(b)", treg, AT);
2898 expr1.X_add_number = 0;
2899 macro_build (&icnt, &expr1, "swr", "t,o(b)", treg, AT);
2900 }
2901 else
2902 {
2903 expr1.X_add_number = 0;
2904 macro_build (&icnt, &expr1, "sb", "t,o(b)", treg, AT);
2905 macro_build (&icnt, NULL, "srl", "d,w,<", treg, treg, 8);
2906 expr1.X_add_number = 1;
2907 macro_build (&icnt, &expr1, "sb", "t,o(b)", treg, AT);
2908 expr1.X_add_number = 0;
2909 macro_build (&icnt, &expr1, "lbu", "t,o(b)", AT, AT);
2910 macro_build (&icnt, NULL, "sll", "d,w,<", treg, treg, 8);
2911 macro_build (&icnt, NULL, "or", "d,v,t", treg, treg, AT);
2912 }
2913 break;
3d3c5039
ILT		 2914
2915 default:
670a50eb 2916 as_bad ("Macro %s not implemented yet", ip->insn_mo->name);
8358c818 2917 break;
3d3c5039 2918 }
670a50eb
ILT		 2919 if (mips_noat)
2920 as_warn ("Macro used $at after \".set noat\"");
3d3c5039
ILT		 2921}
2922
2923
2924/*
2925This routine assembles an instruction into its binary format. As a side
2926effect it sets one of the global variables imm_reloc or offset_reloc to the
2927type of relocation to do if one of the operands is an address expression.
2928*/
2929static void
2930mips_ip (str, ip)
2931 char *str;
2932 struct mips_cl_insn *ip;
2933{
670a50eb
ILT		 2934 char *s;
2935 const char *args;
2936 char c;
2937 struct mips_opcode *insn;
2938 char *argsStart;
2939 unsigned int regno;
2940 unsigned int lastregno = 0;
2941 char *s_reset;
2942
2943 insn_error = NULL;
2944
2945 for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '.'; ++s)
2946 continue;
2947 switch (*s)
2948 {
3d3c5039 2949 case '\0':
670a50eb 2950 break;
3d3c5039
ILT		 2951
2952 case ' ':
670a50eb
ILT		 2953 *s++ = '\0';
2954 break;
3d3c5039
ILT		 2955
2956 default:
670a50eb
ILT		 2957 as_warn ("Unknown opcode: `%s'", str);
2958 exit (1);
3d3c5039 2959 }
670a50eb
ILT		 2960 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
2961 {
2962 as_warn ("`%s' not in hash table.", str);
2963 insn_error = "ERROR: Unrecognized opcode";
2964 return;
3d3c5039 2965 }
670a50eb
ILT		 2966 argsStart = s;
2967 for (;;)
2968 {
8358c818
ILT		 2969 int insn_isa;
2970
670a50eb 2971 assert (strcmp (insn->name, str) == 0);
8358c818
ILT		 2972
2973 if (insn->pinfo == INSN_MACRO)
2974 insn_isa = insn->match;
2975 else if (insn->pinfo & INSN_ISA2)
2976 insn_isa = 2;
2977 else if (insn->pinfo & INSN_ISA3)
2978 insn_isa = 3;
2979 else
2980 insn_isa = 1;
2981
2982 if (insn_isa > mips_isa)
2983 {
2984 if (insn + 1 < &mips_opcodes[NUMOPCODES]
2985 && strcmp (insn->name, insn[1].name) == 0)
2986 {
2987 ++insn;
2988 continue;
2989 }
2990 insn_error = "ERROR: instruction not supported on this processor";
2991 return;
2992 }
2993
670a50eb
ILT		 2994 ip->insn_mo = insn;
2995 ip->insn_opcode = insn->match;
2996 for (args = insn->args;; ++args)
2997 {
2998 if (*s == ' ')
2999 ++s;
3000 switch (*args)
3001 {
3002 case '\0': /* end of args */
3003 if (*s == '\0')
3004 return;
3005 break;
3d3c5039
ILT		 3006
3007 case ',':
670a50eb
ILT		 3008 if (*s++ == *args)
3009 continue;
3010 s--;
3011 switch (*++args)
3012 {
3d3c5039
ILT		 3013 case 'r':
3014 case 'v':
670a50eb
ILT		 3015 ip->insn_opcode |= lastregno << 21;
3016 continue;
3d3c5039
ILT		 3017
3018 case 'w':
3019 case 'W':
670a50eb
ILT		 3020 ip->insn_opcode |= lastregno << 16;
3021 continue;
3d3c5039
ILT		 3022
3023 case 'V':
670a50eb
ILT		 3024 ip->insn_opcode |= lastregno << 11;
3025 continue;
3d3c5039 3026 }
670a50eb 3027 break;
3d3c5039
ILT		 3028
3029 case '(':
670a50eb
ILT		 3030 /* handle optional base register.
3031 Either the base register is omitted or
3032 we must have a left paren. */
3033 /* this is dependent on the next operand specifier
3034 is a 'b' for base register */
3035 assert (args[1] == 'b');
3036 if (*s == '\0')
3037 return;
3d3c5039 3038
670a50eb
ILT		 3039 case ')': /* these must match exactly */
3040 if (*s++ == *args)
3d3c5039 3041 continue;
670a50eb
ILT		 3042 break;
3043
3044 case '<': /* must be at least one digit */
3045 /*
3046 * According to the manual, if the shift amount is greater
3047 * than 31 or less than 0 the the shift amount should be
3048 * mod 32. In reality the mips assembler issues an error.
3049 * We issue a warning and do the mod.
3050 */
3051 my_getExpression (&imm_expr, s);
3052 check_absolute_expr (ip, &imm_expr);
3053 if ((unsigned long) imm_expr.X_add_number > 31)
3054 {
58d4951d
ILT		 3055 as_warn ("Improper shift amount (%ld)",
3056 (long) imm_expr.X_add_number);
670a50eb
ILT		 3057 imm_expr.X_add_number = imm_expr.X_add_number % 32;
3058 }
3059 ip->insn_opcode |= imm_expr.X_add_number << 6;
5ac34ac3 3060 imm_expr.X_op = O_absent;
670a50eb
ILT		 3061 s = expr_end;
3062 continue;
3063
56c96faa
ILT		 3064 case '>': /* shift amount minus 32 */
3065 my_getExpression (&imm_expr, s);
3066 check_absolute_expr (ip, &imm_expr);
3067 if ((unsigned long) imm_expr.X_add_number < 32
3068 || (unsigned long) imm_expr.X_add_number > 63)
3069 break;
3070 ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6;
3071 imm_expr.X_op = O_absent;
3072 s = expr_end;
3073 continue;
3074
670a50eb
ILT		 3075 case 'c': /* break code */
3076 my_getExpression (&imm_expr, s);
3077 check_absolute_expr (ip, &imm_expr);
3078 if ((unsigned) imm_expr.X_add_number > 1023)
58d4951d
ILT		 3079 as_warn ("Illegal break code (%ld)",
3080 (long) imm_expr.X_add_number);
670a50eb 3081 ip->insn_opcode |= imm_expr.X_add_number << 16;
5ac34ac3 3082 imm_expr.X_op = O_absent;
670a50eb
ILT		 3083 s = expr_end;
3084 continue;
3085
918692a5
ILT		 3086 case 'B': /* syscall code */
3087 my_getExpression (&imm_expr, s);
3088 check_absolute_expr (ip, &imm_expr);
3089 if ((unsigned) imm_expr.X_add_number > 0xfffff)
58d4951d
ILT		 3090 as_warn ("Illegal syscall code (%ld)",
3091 (long) imm_expr.X_add_number);
918692a5 3092 ip->insn_opcode |= imm_expr.X_add_number << 6;
5ac34ac3 3093 imm_expr.X_op = O_absent;
918692a5
ILT		 3094 s = expr_end;
3095 continue;
3096
0aa07269
ILT		 3097 case 'C': /* Coprocessor code */
3098 my_getExpression (&imm_expr, s);
3099 check_absolute_expr (ip, &imm_expr);
3100 if ((unsigned long) imm_expr.X_add_number >= (1<<25))
3101 {
58d4951d
ILT		 3102 as_warn ("Coproccesor code > 25 bits (%ld)",
3103 (long) imm_expr.X_add_number);
0aa07269
ILT		 3104 imm_expr.X_add_number &= ((1<<25) - 1);
3105 }
3106 ip->insn_opcode |= imm_expr.X_add_number;
3107 imm_expr.X_op = O_absent;
3108 s = expr_end;
3109 continue;
3110
670a50eb
ILT		 3111 case 'b': /* base register */
3112 case 'd': /* destination register */
3113 case 's': /* source register */
3114 case 't': /* target register */
3115 case 'r': /* both target and source */
3116 case 'v': /* both dest and source */
3117 case 'w': /* both dest and target */
918692a5
ILT		 3118 case 'E': /* coprocessor target register */
3119 case 'G': /* coprocessor destination register */
8358c818 3120 case 'x': /* ignore register name */
ff3a5c18 3121 case 'z': /* must be zero register */
670a50eb
ILT		 3122 s_reset = s;
3123 if (s[0] == '$')
3124 {
3125 if (isdigit (s[1]))
3126 {
3127 ++s;
3128 regno = 0;
3129 do
3130 {
3131 regno *= 10;
3132 regno += *s - '0';
3133 ++s;
3134 }
3135 while (isdigit (*s));
0aa07269
ILT		 3136 if (regno > 31)
3137 as_bad ("Invalid register number (%d)", regno);
670a50eb 3138 }
0aa07269 3139 else if (*args != 'E' && *args != 'G')
670a50eb 3140 {
0aa07269
ILT		 3141 if (s[1] == 'f' && s[2] == 'p')
3142 {
3143 s += 3;
3144 regno = 30;
3145 }
3146 else if (s[1] == 's' && s[2] == 'p')
3147 {
3148 s += 3;
3149 regno = 29;
3150 }
3151 else if (s[1] == 'g' && s[2] == 'p')
3152 {
3153 s += 3;
3154 regno = 28;
3155 }
3156 else if (s[1] == 'a' && s[2] == 't')
3157 {
3158 s += 3;
3159 regno = 1;
3160 }
3161 else
3162 goto notreg;
3163 if (regno == AT && ! mips_noat)
3164 as_warn ("Used $at without \".set noat\"");
670a50eb 3165 }
670a50eb
ILT		 3166 c = *args;
3167 if (*s == ' ')
3168 s++;
3169 if (args[1] != *s)
3170 {
3171 if (c == 'r' || c == 'v' || c == 'w')
3172 {
3173 regno = lastregno;
3174 s = s_reset;
3175 args++;
3176 }
3177 }
ff3a5c18
ILT		 3178 /* 'z' only matches $0. */
3179 if (c == 'z' && regno != 0)
3180 break;
670a50eb
ILT		 3181 switch (c)
3182 {
3d3c5039
ILT		 3183 case 'r':
3184 case 's':
3185 case 'v':
3186 case 'b':
670a50eb
ILT		 3187 ip->insn_opcode |= regno << 21;
3188 break;
3d3c5039 3189 case 'd':
918692a5 3190 case 'G':
670a50eb
ILT		 3191 ip->insn_opcode |= regno << 11;
3192 break;
3d3c5039
ILT		 3193 case 'w':
3194 case 't':
918692a5 3195 case 'E':
670a50eb 3196 ip->insn_opcode |= regno << 16;
8358c818
ILT		 3197 break;
3198 case 'x':
3199 /* This case exists because on the r3000 trunc
3200 expands into a macro which requires a gp
3201 register. On the r6000 or r4000 it is
3202 assembled into a single instruction which
3203 ignores the register. Thus the insn version
3204 is MIPS_ISA2 and uses 'x', and the macro
3205 version is MIPS_ISA1 and uses 't'. */
3206 break;
ff3a5c18
ILT		 3207 case 'z':
3208 /* This case is for the div instruction, which
3209 acts differently if the destination argument
3210 is $0. This only matches $0, and is checked
3211 outside the switch. */
3212 break;
3d3c5039 3213 }
670a50eb
ILT		 3214 lastregno = regno;
3215 continue;
3d3c5039
ILT		 3216 }
3217 notreg:
670a50eb
ILT		 3218 switch (*args++)
3219 {
3d3c5039
ILT		 3220 case 'r':
3221 case 'v':
670a50eb
ILT		 3222 ip->insn_opcode |= lastregno << 21;
3223 continue;
3d3c5039 3224 case 'w':
670a50eb
ILT		 3225 ip->insn_opcode |= lastregno << 16;
3226 continue;
3d3c5039 3227 }
670a50eb 3228 break;
3d3c5039 3229
670a50eb
ILT		 3230 case 'D': /* floating point destination register */
3231 case 'S': /* floating point source register */
3232 case 'T': /* floating point target register */
3d3c5039
ILT		 3233 case 'V':
3234 case 'W':
670a50eb
ILT		 3235 s_reset = s;
3236 if (s[0] == '$' && s[1] == 'f' && isdigit (s[2]))
3237 {
3238 s += 2;
3239 regno = 0;
3240 do
3241 {
3242 regno *= 10;
3243 regno += *s - '0';
3244 ++s;
3245 }
3246 while (isdigit (*s));
3247
3248 if (regno > 31)
3249 as_bad ("Invalid float register number (%d)", regno);
3250
3251 if ((regno & 1) &&
3252 !(strcmp (str, "mtc1") == 0 ||
3253 strcmp (str, "mfc1") == 0 ||
3254 strcmp (str, "lwc1") == 0 ||
3255 strcmp (str, "swc1") == 0))
3256 as_warn ("Float register should be even, was %d",
3257 regno);
3258
3259 c = *args;
3260 if (*s == ' ')
3261 s++;
3262 if (args[1] != *s)
3263 {
3264 if (c == 'V' || c == 'W')
3265 {
3266 regno = lastregno;
3267 s = s_reset;
3268 args++;
3d3c5039
ILT		 3269 }
3270 }
670a50eb
ILT		 3271 switch (c)
3272 {
3d3c5039 3273 case 'D':
670a50eb
ILT		 3274 ip->insn_opcode |= regno << 6;
3275 break;
3d3c5039
ILT		 3276 case 'V':
3277 case 'S':
670a50eb
ILT		 3278 ip->insn_opcode |= regno << 11;
3279 break;
3d3c5039
ILT		 3280 case 'W':
3281 case 'T':
670a50eb 3282 ip->insn_opcode |= regno << 16;
3d3c5039 3283 }
670a50eb
ILT		 3284 lastregno = regno;
3285 continue;
3d3c5039 3286 }
670a50eb
ILT		 3287 switch (*args++)
3288 {
3d3c5039 3289 case 'V':
670a50eb
ILT		 3290 ip->insn_opcode |= lastregno << 11;
3291 continue;
3d3c5039 3292 case 'W':
670a50eb
ILT		 3293 ip->insn_opcode |= lastregno << 16;
3294 continue;
3d3c5039 3295 }
670a50eb 3296 break;
3d3c5039
ILT		 3297
3298 case 'I':
670a50eb
ILT		 3299 my_getExpression (&imm_expr, s);
3300 check_absolute_expr (ip, &imm_expr);
3301 s = expr_end;
3302 continue;
3d3c5039
ILT		 3303
3304 case 'A':
670a50eb
ILT		 3305 my_getExpression (&offset_expr, s);
3306 imm_reloc = BFD_RELOC_32;
3307 s = expr_end;
3308 continue;
3d3c5039
ILT		 3309
3310 case 'F':
19ed8960
ILT		 3311 case 'L':
3312 case 'f':
3313 case 'l':
3314 {
3315 int f64;
3316 char *save_in;
3317 char *err;
3318 unsigned char temp[8];
604633ae
ILT		 3319 int len;
3320 unsigned int length;
19ed8960
ILT		 3321 segT seg;
3322 subsegT subseg;
3323 char *p;
3324
3325 /* These only appear as the last operand in an
3326 instruction, and every instruction that accepts
3327 them in any variant accepts them in all variants.
3328 This means we don't have to worry about backing out
3329 any changes if the instruction does not match.
3330
3331 The difference between them is the size of the
3332 floating point constant and where it goes. For 'F'
3333 and 'L' the constant is 64 bits; for 'f' and 'l' it
3334 is 32 bits. Where the constant is placed is based
3335 on how the MIPS assembler does things:
3336 F -- .rdata
3337 L -- .lit8
3338 f -- immediate value
3339 l -- .lit4
3340 */
3341
3342 f64 = *args == 'F' || *args == 'L';
3343
3344 save_in = input_line_pointer;
3345 input_line_pointer = s;
604633ae
ILT		 3346 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
3347 length = len;
19ed8960
ILT		 3348 s = input_line_pointer;
3349 input_line_pointer = save_in;
3350 if (err != NULL && *err != '\0')
3351 {
3352 as_bad ("Bad floating point constant: %s", err);
3353 memset (temp, '\0', sizeof temp);
3354 length = f64 ? 8 : 4;
3355 }
3356
3357 assert (length == (f64 ? 8 : 4));
3358
3359 if (*args == 'f')
3360 {
3361 imm_expr.X_op = O_constant;
3362 if (byte_order == LITTLE_ENDIAN)
3363 imm_expr.X_add_number =
3364 (((((((int) temp[3] << 8)
3365 | temp[2]) << 8)
3366 | temp[1]) << 8)
3367 | temp[0]);
3368 else
3369 imm_expr.X_add_number =
3370 (((((((int) temp[0] << 8)
3371 | temp[1]) << 8)
3372 | temp[2]) << 8)
3373 | temp[3]);
3374 }
3375 else
3376 {
3377 /* Switch to the right section. */
3378 seg = now_seg;
3379 subseg = now_subseg;
3380 switch (*args)
3381 {
3382 case 'F':
3383 subseg_new (".rdata", (subsegT) 0);
3384 break;
3385 case 'L':
3386 subseg_new (".lit8", (subsegT) 0);
3387 break;
3388 case 'l':
3389 subseg_new (".lit4", (subsegT) 0);
3390 break;
3391 }
3392 if (seg == now_seg)
3393 as_bad ("Can't use floating point insn in this section");
3394
3395 /* Set the argument to the current address in the
6e8dda9c 3396 section. */
19ed8960
ILT		 3397 offset_expr.X_op = O_symbol;
3398 offset_expr.X_add_symbol =
3399 symbol_new ("L0\001", now_seg,
3400 (valueT) frag_now_fix (), frag_now);
3401 offset_expr.X_add_number = 0;
3402
3403 /* Put the floating point number into the section. */
604633ae 3404 p = frag_more ((int) length);
19ed8960
ILT		 3405 memcpy (p, temp, length);
3406
3407 /* Switch back to the original section. */
3408 subseg_set (seg, subseg);
3409 }
3410 }
670a50eb
ILT		 3411 continue;
3412
3413 case 'i': /* 16 bit unsigned immediate */
3414 case 'j': /* 16 bit signed immediate */
3415 imm_reloc = BFD_RELOC_LO16;
3416 c = my_getSmallExpression (&imm_expr, s);
3417 if (c)
3418 {
3419 if (c != 'l')
3420 {
5ac34ac3 3421 if (imm_expr.X_op == O_constant)
670a50eb
ILT		 3422 imm_expr.X_add_number =
3423 (imm_expr.X_add_number >> 16) & 0xffff;
3424 else if (c == 'h')
3425 imm_reloc = BFD_RELOC_HI16_S;
3426 else
3427 imm_reloc = BFD_RELOC_HI16;
3d3c5039 3428 }
670a50eb
ILT		 3429 }
3430 else
3431 check_absolute_expr (ip, &imm_expr);
3432 if (*args == 'i')
3433 {
6e8dda9c
ILT		 3434 if (imm_expr.X_add_number < 0
3435 || imm_expr.X_add_number >= 0x10000)
99c24539
ILT		 3436 {
3437 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
3438 !strcmp (insn->name, insn[1].name))
3439 break;
3440 as_bad ("16 bit expression not in range 0..65535");
3441 }
670a50eb
ILT		 3442 }
3443 else
3444 {
6e8dda9c
ILT		 3445 if (imm_expr.X_add_number < -0x8000 ||
3446 imm_expr.X_add_number >= 0x8000)
99c24539
ILT		 3447 {
3448 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
3449 !strcmp (insn->name, insn[1].name))
3450 break;
3451 as_bad ("16 bit expression not in range -32768..32767");
3452 }
3d3c5039 3453 }
670a50eb
ILT		 3454 s = expr_end;
3455 continue;
3456
3457 case 'o': /* 16 bit offset */
3458 c = my_getSmallExpression (&offset_expr, s);
3459 /*
3460 * If this value won't fit into a 16 bit offset, then
3461 * go find a macro that will generate the 32 bit offset
3462 * code pattern.
3463 */
6e8dda9c
ILT		 3464 if (offset_expr.X_op != O_constant
3465 || offset_expr.X_add_number >= 0x8000
3466 || offset_expr.X_add_number < -0x8000)
670a50eb 3467 break;
3d3c5039 3468
670a50eb
ILT		 3469 offset_reloc = BFD_RELOC_LO16;
3470 if (c == 'h' || c == 'H')
6e8dda9c
ILT		 3471 {
3472 assert (offset_expr.X_op == O_constant);
3473 offset_expr.X_add_number =
3474 (offset_expr.X_add_number >> 16) & 0xffff;
3475 }
670a50eb
ILT		 3476 s = expr_end;
3477 continue;
3478
3479 case 'p': /* pc relative offset */
3480 offset_reloc = BFD_RELOC_16_PCREL_S2;
3481 my_getExpression (&offset_expr, s);
3482 s = expr_end;
3483 continue;
3484
3485 case 'u': /* upper 16 bits */
3486 c = my_getSmallExpression (&imm_expr, s);
6e8dda9c
ILT		 3487 if (imm_expr.X_op != O_constant
3488 || imm_expr.X_add_number < 0
3489 || imm_expr.X_add_number >= 0x10000)
670a50eb
ILT		 3490 as_bad ("lui expression not in range 0..65535");
3491 imm_reloc = BFD_RELOC_LO16;
3492 if (c)
3493 {
3494 if (c != 'l')
3495 {
5ac34ac3 3496 if (imm_expr.X_op == O_constant)
670a50eb
ILT		 3497 imm_expr.X_add_number =
3498 (imm_expr.X_add_number >> 16) & 0xffff;
3499 else if (c == 'h')
3500 imm_reloc = BFD_RELOC_HI16_S;
3501 else
3502 imm_reloc = BFD_RELOC_HI16;
3d3c5039
ILT		 3503 }
3504 }
670a50eb
ILT		 3505 s = expr_end;
3506 continue;
3d3c5039 3507
670a50eb
ILT		 3508 case 'a': /* 26 bit address */
3509 my_getExpression (&offset_expr, s);
3510 s = expr_end;
3511 offset_reloc = BFD_RELOC_MIPS_JMP;
3512 continue;
3d3c5039
ILT		 3513
3514 default:
670a50eb
ILT		 3515 fprintf (stderr, "bad char = '%c'\n", *args);
3516 internalError ();
3d3c5039 3517 }
670a50eb 3518 break;
3d3c5039 3519 }
670a50eb
ILT		 3520 /* Args don't match. */
3521 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
3522 !strcmp (insn->name, insn[1].name))
3523 {
3524 ++insn;
3525 s = argsStart;
3526 continue;
3d3c5039 3527 }
670a50eb
ILT		 3528 insn_error = "ERROR: Illegal operands";
3529 return;
3d3c5039
ILT		 3530 }
3531}
3532
3533#define LP '('
3534#define RP ')'
3535
3536static int
3537my_getSmallExpression (ep, str)
670a50eb
ILT		 3538 expressionS *ep;
3539 char *str;
3d3c5039 3540{
670a50eb
ILT		 3541 char *sp;
3542 int c = 0;
3543
3544 if (*str == ' ')
3545 str++;
3546 if (*str == LP
3547 || (*str == '%' &&
3548 ((str[1] == 'h' && str[2] == 'i')
3549 || (str[1] == 'H' && str[2] == 'I')
3550 || (str[1] == 'l' && str[2] == 'o'))
3551 && str[3] == LP))
3552 {
3553 if (*str == LP)
3554 c = 0;
3555 else
3556 {
3557 c = str[1];
3558 str += 3;
3559 }
3560
3561 /*
3562 * A small expression may be followed by a base register.
3563 * Scan to the end of this operand, and then back over a possible
3564 * base register. Then scan the small expression up to that
3565 * point. (Based on code in sparc.c...)
3566 */
3567 for (sp = str; *sp && *sp != ','; sp++)
3568 ;
3569 if (sp - 4 >= str && sp[-1] == RP)
3570 {
3571 if (isdigit (sp[-2]))
3572 {
3573 for (sp -= 3; sp >= str && isdigit (*sp); sp--)
3574 ;
3575 if (*sp == '$' && sp > str && sp[-1] == LP)
3576 {
3577 sp--;
3578 goto do_it;
3d3c5039 3579 }
670a50eb
ILT		 3580 }
3581 else if (sp - 5 >= str
3582 && sp[-5] == LP
3583 && sp[-4] == '$'
3584 && ((sp[-3] == 'f' && sp[-2] == 'p')
3585 || (sp[-3] == 's' && sp[-2] == 'p')
3586 || (sp[-3] == 'g' && sp[-2] == 'p')
3587 || (sp[-3] == 'a' && sp[-2] == 't')))
3588 {
3589 sp -= 5;
3d3c5039 3590 do_it:
670a50eb
ILT		 3591 if (sp == str)
3592 {
3593 /* no expression means zero offset */
3594 if (c)
3595 {
3596 /* %xx(reg) is an error */
5ac34ac3 3597 ep->X_op = O_absent;
670a50eb 3598 expr_end = str - 3;
3d3c5039 3599 }
670a50eb
ILT		 3600 else
3601 {
52aa70b5 3602 ep->X_op = O_constant;
670a50eb
ILT		 3603 expr_end = sp;
3604 }
3605 ep->X_add_symbol = NULL;
5ac34ac3 3606 ep->X_op_symbol = NULL;
670a50eb
ILT		 3607 ep->X_add_number = 0;
3608 }
3609 else
3610 {
3611 *sp = '\0';
3612 my_getExpression (ep, str);
3613 *sp = LP;
3d3c5039 3614 }
670a50eb 3615 return c;
3d3c5039
ILT		 3616 }
3617 }
3618 }
670a50eb
ILT		 3619 my_getExpression (ep, str);
3620 return c; /* => %hi or %lo encountered */
3d3c5039
ILT		 3621}
3622
3623static void
3624my_getExpression (ep, str)
670a50eb
ILT		 3625 expressionS *ep;
3626 char *str;
3d3c5039 3627{
670a50eb 3628 char *save_in;
670a50eb
ILT		 3629
3630 save_in = input_line_pointer;
3631 input_line_pointer = str;
5ac34ac3 3632 expression (ep);
670a50eb
ILT		 3633 expr_end = input_line_pointer;
3634 input_line_pointer = save_in;
3d3c5039
ILT		 3635}
3636
becfe05e
ILT		 3637/* Turn a string in input_line_pointer into a floating point constant
3638 of type type, and store the appropriate bytes in *litP. The number
3639 of LITTLENUMS emitted is stored in *sizeP . An error message is
3640 returned, or NULL on OK. */
3641
3d3c5039 3642char *
670a50eb 3643md_atof (type, litP, sizeP)
becfe05e 3644 int type;
3d3c5039
ILT		 3645 char *litP;
3646 int *sizeP;
3647{
becfe05e
ILT		 3648 int prec;
3649 LITTLENUM_TYPE words[4];
3650 char *t;
3651 int i;
3652
3653 switch (type)
3654 {
3655 case 'f':
3656 prec = 2;
3657 break;
3658
3659 case 'd':
3660 prec = 4;
3661 break;
3662
3663 default:
3664 *sizeP = 0;
3665 return "bad call to md_atof";
3666 }
3667
3668 t = atof_ieee (input_line_pointer, type, words);
3669 if (t)
3670 input_line_pointer = t;
3671
3672 *sizeP = prec * 2;
3673
3674 if (byte_order == LITTLE_ENDIAN)
3675 {
3676 for (i = prec - 1; i >= 0; i--)
3677 {
3678 md_number_to_chars (litP, (valueT) words[i], 2);
3679 litP += 2;
3680 }
3681 }
3682 else
3683 {
3684 for (i = 0; i < prec; i++)
3685 {
3686 md_number_to_chars (litP, (valueT) words[i], 2);
3687 litP += 2;
3688 }
3689 }
3690
670a50eb 3691 return NULL;
3d3c5039
ILT		 3692}
3693
3694void
3695md_number_to_chars (buf, val, n)
3696 char *buf;
918692a5 3697 valueT val;
3d3c5039
ILT		 3698 int n;
3699{
670a50eb
ILT		 3700 switch (byte_order)
3701 {
3d3c5039 3702 case LITTLE_ENDIAN:
670a50eb
ILT		 3703 switch (n)
3704 {
6e8dda9c
ILT		 3705 case 8:
3706 *buf++ = val;
3707 val >>= 8;
3708 *buf++ = val;
3709 val >>= 8;
3710 *buf++ = val;
3711 val >>= 8;
3712 *buf++ = val;
3713 val >>= 8;
3714 /* FALLTHROUGH */
3d3c5039 3715 case 4:
670a50eb 3716 *buf++ = val;
6e8dda9c
ILT		 3717 val >>= 8;
3718 *buf++ = val;
3719 val >>= 8;
3720 /* FALLTHROUGH */
670a50eb
ILT		 3721 case 2:
3722 *buf++ = val;
6e8dda9c
ILT		 3723 val >>= 8;
3724 /* FALLTHROUGH */
3d3c5039 3725 case 1:
670a50eb
ILT		 3726 *buf = val;
3727 return;
3d3c5039
ILT		 3728
3729 default:
670a50eb 3730 internalError ();
3d3c5039
ILT		 3731 }
3732
3733 case BIG_ENDIAN:
670a50eb
ILT		 3734 switch (n)
3735 {
6e8dda9c
ILT		 3736 case 8:
3737 {
3738 valueT hi;
3739
3740 hi = val;
3741 hi >>= 16;
3742 hi >>= 16;
3743 md_number_to_chars (buf, hi, 4);
3744 buf += 4;
3745 }
3746 /* FALLTHROUGH */
3d3c5039 3747 case 4:
670a50eb
ILT		 3748 *buf++ = val >> 24;
3749 *buf++ = val >> 16;
6e8dda9c 3750 /* FALLTHROUGH */
670a50eb
ILT		 3751 case 2:
3752 *buf++ = val >> 8;
6e8dda9c 3753 /* FALLTHROUGH */
3d3c5039 3754 case 1:
670a50eb
ILT		 3755 *buf = val;
3756 return;
3d3c5039
ILT		 3757
3758 default:
670a50eb 3759 internalError ();
3d3c5039
ILT		 3760 }
3761
3762 default:
670a50eb 3763 internalError ();
3d3c5039
ILT		 3764 }
3765}
3766
3767int
3768md_parse_option (argP, cntP, vecP)
3769 char **argP;
3770 int *cntP;
3771 char ***vecP;
3772{
670a50eb 3773 /* Accept -nocpp but ignore it. */
8358c818 3774 if (strcmp (*argP, "nocpp") == 0)
670a50eb
ILT		 3775 {
3776 *argP += 5;
3777 return 1;
3778 }
3779
3780 if (strcmp (*argP, "EL") == 0
3781 || strcmp (*argP, "EB") == 0)
3782 {
3783 /* FIXME: This breaks -L -EL. */
3784 flagseen['L'] = 0;
3785 *argP = "";
3786 return 1;
3787 }
3788
4e95866e
ILT		 3789 if (**argP == 'O')
3790 {
0aa07269
ILT		 3791 if ((*argP)[1] == '0')
3792 mips_optimize = 1;
3793 else
3794 mips_optimize = 2;
3795 return 1;
3796 }
3797
3798 if (**argP == 'g')
3799 {
3800 if ((*argP)[1] == '\0' || (*argP)[1] == '2')
3801 mips_optimize = 0;
4e95866e
ILT		 3802 return 1;
3803 }
3804
8358c818
ILT		 3805 if (strncmp (*argP, "mips", 4) == 0)
3806 {
3807 mips_isa = atol (*argP + 4);
3808 if (mips_isa == 0)
3809 mips_isa = 1;
3810 else if (mips_isa < 1 || mips_isa > 3)
3811 {
3812 as_bad ("-mips%d not supported", mips_isa);
3813 mips_isa = 1;
3814 }
3815 *argP = "";
3816 return 1;
3817 }
3818
3819 if (strncmp (*argP, "mcpu=", 5) == 0)
3820 {
3821 char *p;
3822
3823 /* Identify the processor type */
3824 p = *argP + 5;
3825 if (strcmp (p, "default") == 0
3826 || strcmp (p, "DEFAULT") == 0)
3827 mips_isa = -1;
3828 else
3829 {
3830 if (*p == 'r' || *p == 'R')
3831 p++;
3832
3833 mips_isa = -1;
3834 switch (*p)
3835 {
3836 case '2':
3837 if (strcmp (p, "2000") == 0
3838 || strcmp (p, "2k") == 0
3839 || strcmp (p, "2K") == 0)
3840 mips_isa = 1;
3841 break;
3842
3843 case '3':
3844 if (strcmp (p, "3000") == 0
3845 || strcmp (p, "3k") == 0
3846 || strcmp (p, "3K") == 0)
3847 mips_isa = 1;
3848 break;
3849
3850 case '4':
3851 if (strcmp (p, "4000") == 0
3852 || strcmp (p, "4k") == 0
3853 || strcmp (p, "4K") == 0)
3854 mips_isa = 3;
3855 break;
3856
3857 case '6':
3858 if (strcmp (p, "6000") == 0
3859 || strcmp (p, "6k") == 0
3860 || strcmp (p, "6K") == 0)
3861 mips_isa = 2;
3862 break;
3863 }
3864
3865 if (mips_isa == -1)
3866 {
3867 as_bad ("bad value (%s) for -mcpu= switch", *argP + 5);
3868 mips_isa = 1;
3869 }
3870 }
3871
3872 *argP = "";
3873 return 1;
3874 }
3875
3876
88225433 3877#ifdef GPOPT
670a50eb
ILT		 3878 if (**argP == 'G')
3879 {
3880 if ((*argP)[1] != '\0')
3881 g_switch_value = atoi (*argP + 1);
3882 else if (*cntP)
3883 {
3884 **vecP = (char *) NULL;
3885 (*cntP)--;
3886 (*vecP)++;
3887 g_switch_value = atoi (**vecP);
3888 }
3889 else
3890 as_warn ("Number expected after -G");
3891 *argP = "";
3892 return 1;
3d3c5039 3893 }
670a50eb 3894#endif
4e95866e 3895
670a50eb 3896 return 1; /* pretend you parsed the character */
3d3c5039
ILT		 3897}
3898
3899long
3900md_pcrel_from (fixP)
3901 fixS *fixP;
3902{
670a50eb
ILT		 3903 /* return the address of the delay slot */
3904 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
3d3c5039
ILT		 3905}
3906
abdad6bc
ILT		 3907/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3908 reloc for a cons. We could use the definition there, except that
3909 we want to handle 64 bit relocs specially. */
3910
3911void
3912cons_fix_new_mips (frag, where, nbytes, exp)
3913 fragS *frag;
3914 int where;
3915 unsigned int nbytes;
3916 expressionS *exp;
3917{
3918 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
3919 4 byte reloc.
3920 FIXME: There is no way to select anything but 32 bit mode right
3921 now. */
3922 if (nbytes == 8)
3923 {
3924 if (byte_order == BIG_ENDIAN)
3925 where += 4;
3926 nbytes = 4;
3927 }
3928
3929 if (nbytes != 2 && nbytes != 4)
3930 as_bad ("Unsupported reloc size %d", nbytes);
3931
3932 fix_new_exp (frag_now, where, (int) nbytes, exp, 0,
3933 nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32);
3934}
3935
3d3c5039
ILT		 3936int
3937md_apply_fix (fixP, valueP)
3938 fixS *fixP;
918692a5 3939 valueT *valueP;
3d3c5039 3940{
670a50eb
ILT		 3941 unsigned char *buf;
3942 long insn, value;
3d3c5039 3943
670a50eb 3944 assert (fixP->fx_size == 4);
3d3c5039 3945
670a50eb
ILT		 3946 value = *valueP;
3947 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */
3d3c5039 3948
670a50eb
ILT		 3949 switch (fixP->fx_r_type)
3950 {
3d3c5039
ILT		 3951 case BFD_RELOC_32:
3952 case BFD_RELOC_MIPS_JMP:
3953 case BFD_RELOC_HI16:
3954 case BFD_RELOC_HI16_S:
3955 case BFD_RELOC_LO16:
670a50eb
ILT		 3956 case BFD_RELOC_MIPS_GPREL:
3957 /* Nothing needed to do. The value comes from the reloc entry */
3958 return 1;
3d3c5039
ILT		 3959
3960 case BFD_RELOC_16_PCREL_S2:
670a50eb
ILT		 3961 /*
3962 * We need to save the bits in the instruction since fixup_segment()
3963 * might be deleting the relocation entry (i.e., a branch within
3964 * the current segment).
3965 */
3966 if (value & 0x3)
58d4951d 3967 as_warn ("Branch to odd address (%lx)", value);
670a50eb
ILT		 3968 value >>= 2;
3969 if ((value & ~0xFFFF) && (value & ~0xFFFF) != (-1 & ~0xFFFF))
3970 as_bad ("Relocation overflow");
3971
3972 /* update old instruction data */
3973 buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal);
3974 switch (byte_order)
3975 {
3d3c5039 3976 case LITTLE_ENDIAN:
670a50eb
ILT		 3977 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
3978 break;
3d3c5039
ILT		 3979
3980 case BIG_ENDIAN:
670a50eb
ILT		 3981 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
3982 break;
3d3c5039
ILT		 3983
3984 default:
670a50eb
ILT		 3985 internalError ();
3986 return 0;
3d3c5039 3987 }
670a50eb 3988 insn |= value & 0xFFFF;
604633ae 3989 md_number_to_chars ((char *) buf, (valueT) insn, 4);
670a50eb 3990 break;
3d3c5039
ILT		 3991
3992 default:
670a50eb 3993 internalError ();
3d3c5039 3994 }
670a50eb 3995 return 1;
3d3c5039
ILT		 3996}
3997
3998#if 0
3999void
670a50eb
ILT		 4000printInsn (oc)
4001 unsigned long oc;
3d3c5039 4002{
670a50eb
ILT		 4003 const struct mips_opcode *p;
4004 int treg, sreg, dreg, shamt;
4005 short imm;
4006 const char *args;
4007 int i;
3d3c5039 4008
670a50eb
ILT		 4009 for (i = 0; i < NUMOPCODES; ++i)
4010 {
4011 p = &mips_opcodes[i];
4012 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
4013 {
4014 printf ("%08lx %s\t", oc, p->name);
4015 treg = (oc >> 16) & 0x1f;
4016 sreg = (oc >> 21) & 0x1f;
4017 dreg = (oc >> 11) & 0x1f;
4018 shamt = (oc >> 6) & 0x1f;
4019 imm = oc;
4020 for (args = p->args;; ++args)
4021 {
4022 switch (*args)
4023 {
3d3c5039 4024 case '\0':
670a50eb
ILT		 4025 printf ("\n");
4026 break;
3d3c5039
ILT		 4027
4028 case ',':
4029 case '(':
4030 case ')':
670a50eb
ILT		 4031 printf ("%c", *args);
4032 continue;
3d3c5039
ILT		 4033
4034 case 'r':
670a50eb
ILT		 4035 assert (treg == sreg);
4036 printf ("$%d,$%d", treg, sreg);
4037 continue;
3d3c5039
ILT		 4038
4039 case 'd':
918692a5 4040 case 'G':
670a50eb
ILT		 4041 printf ("$%d", dreg);
4042 continue;
3d3c5039
ILT		 4043
4044 case 't':
918692a5 4045 case 'E':
670a50eb
ILT		 4046 printf ("$%d", treg);
4047 continue;
3d3c5039
ILT		 4048
4049 case 'b':
4050 case 's':
670a50eb
ILT		 4051 printf ("$%d", sreg);
4052 continue;
3d3c5039
ILT		 4053
4054 case 'a':
670a50eb
ILT		 4055 printf ("0x%08lx", oc & 0x1ffffff);
4056 continue;
3d3c5039
ILT		 4057
4058 case 'i':
4059 case 'j':
4060 case 'o':
4061 case 'u':
670a50eb
ILT		 4062 printf ("%d", imm);
4063 continue;
3d3c5039
ILT		 4064
4065 case '<':
56c96faa 4066 case '>':
670a50eb
ILT		 4067 printf ("$%d", shamt);
4068 continue;
3d3c5039
ILT		 4069
4070 default:
670a50eb 4071 internalError ();
3d3c5039 4072 }
670a50eb 4073 break;
3d3c5039 4074 }
670a50eb 4075 return;
3d3c5039
ILT		 4076 }
4077 }
670a50eb 4078 printf ("%08lx UNDEFINED\n", oc);
3d3c5039
ILT		 4079}
4080#endif
4081
4082static symbolS *
4083get_symbol ()
4084{
670a50eb
ILT		 4085 int c;
4086 char *name;
4087 symbolS *p;
4088
4089 name = input_line_pointer;
4090 c = get_symbol_end ();
4091 p = (symbolS *) symbol_find_or_make (name);
4092 *input_line_pointer = c;
4093 return p;
3d3c5039
ILT		 4094}
4095
becfe05e
ILT		 4096/* Align the current frag to a given power of two. The MIPS assembler
4097 also automatically adjusts any preceding label. */
4098
4099static void
4100mips_align (to, fill)
4101 int to;
4102 int fill;
4103{
4104 mips_emit_delays ();
4105 frag_align (to, fill);
4106 record_alignment (now_seg, to);
4107 if (insn_label != NULL)
4108 {
4109 assert (S_GET_SEGMENT (insn_label) == now_seg);
4110 insn_label->sy_frag = frag_now;
604633ae 4111 S_SET_VALUE (insn_label, (valueT) frag_now_fix ());
1849d646 4112 insn_label = NULL;
becfe05e
ILT		 4113 }
4114}
4115
4116/* Align to a given power of two. .align 0 turns off the automatic
4117 alignment used by the data creating pseudo-ops. */
4118
3d3c5039
ILT		 4119static void
4120s_align (x)
4121 int x;
4122{
670a50eb
ILT		 4123 register int temp;
4124 register long temp_fill;
4125 long max_alignment = 15;
3d3c5039 4126
670a50eb 4127 /*
3d3c5039
ILT		 4128
4129 o Note that the assembler pulls down any immediately preceeding label
4130 to the aligned address.
4131 o It's not documented but auto alignment is reinstated by
4132 a .align pseudo instruction.
4133 o Note also that after auto alignment is turned off the mips assembler
4134 issues an error on attempt to assemble an improperly aligned data item.
4135 We don't.
4136
4137 */
4138
670a50eb
ILT		 4139 temp = get_absolute_expression ();
4140 if (temp > max_alignment)
4141 as_bad ("Alignment too large: %d. assumed.", temp = max_alignment);
4142 else if (temp < 0)
4143 {
4144 as_warn ("Alignment negative: 0 assumed.");
4145 temp = 0;
4146 }
4147 if (*input_line_pointer == ',')
4148 {
4149 input_line_pointer++;
4150 temp_fill = get_absolute_expression ();
4151 }
4152 else
4153 temp_fill = 0;
4154 if (temp)
4155 {
4156 auto_align = 1;
becfe05e 4157 mips_align (temp, (int) temp_fill);
3d3c5039 4158 }
670a50eb
ILT		 4159 else
4160 {
4161 auto_align = 0;
3d3c5039
ILT		 4162 }
4163
670a50eb 4164 demand_empty_rest_of_line ();
3d3c5039
ILT		 4165}
4166
becfe05e
ILT		 4167/* Handle .ascii and .asciiz. This just calls stringer and forgets
4168 that there was a previous instruction. */
4169
4170static void
4171s_stringer (append_zero)
4172 int append_zero;
4173{
4174 mips_emit_delays ();
1849d646 4175 insn_label = NULL;
becfe05e
ILT		 4176 stringer (append_zero);
4177}
4178
3d3c5039
ILT		 4179static void
4180s_change_sec (sec)
4181 int sec;
4182{
88225433
ILT		 4183#ifdef GPOPT
4184 segT seg;
4185#endif
becfe05e
ILT		 4186
4187 mips_emit_delays ();
670a50eb
ILT		 4188 switch (sec)
4189 {
3d3c5039 4190 case 't':
604633ae 4191 s_text (0);
670a50eb 4192 break;
3d3c5039 4193 case 'd':
604633ae 4194 s_data (0);
670a50eb 4195 break;
3d3c5039 4196 case 'b':
670a50eb 4197 subseg_set (bss_section, (subsegT) get_absolute_expression ());
670a50eb
ILT		 4198 demand_empty_rest_of_line ();
4199 break;
88225433
ILT		 4200
4201 case 'r':
670a50eb 4202#ifdef OBJ_ECOFF
88225433 4203 subseg_new (".rdata", (subsegT) get_absolute_expression ());
becfe05e 4204 demand_empty_rest_of_line ();
670a50eb 4205 break;
88225433
ILT		 4206#else /* ! defined (OBJ_ECOFF) */
4207#ifdef OBJ_ELF
4208 seg = subseg_new (".rodata", (subsegT) get_absolute_expression ());
4209 bfd_set_section_flags (stdoutput, seg,
4210 (SEC_ALLOC
4211 | SEC_LOAD
4212 | SEC_READONLY
4213 | SEC_RELOC
4214 | SEC_DATA));
4215 demand_empty_rest_of_line ();
4216 break;
4217#else /* ! defined (OBJ_ELF) */
4218 s_data (0);
4219 break;
4220#endif /* ! defined (OBJ_ELF) */
4221#endif /* ! defined (OBJ_ECOFF) */
4222
4223 case 's':
4224#ifdef GPOPT
4225 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
4226#ifdef OBJ_ELF
4227 bfd_set_section_flags (stdoutput, seg,
4228 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
4229#endif
4230 demand_empty_rest_of_line ();
4231 break;
4232#else /* ! defined (GPOPT) */
670a50eb 4233 as_bad ("Global pointers not supported; recompile -G 0");
becfe05e 4234 demand_empty_rest_of_line ();
670a50eb 4235 return;
88225433 4236#endif /* ! defined (GPOPT) */
3d3c5039 4237 }
88225433 4238
670a50eb 4239 auto_align = 1;
3d3c5039
ILT		 4240}
4241
4242static void
4243s_cons (log_size)
4244 int log_size;
4245{
becfe05e 4246 mips_emit_delays ();
670a50eb 4247 if (log_size > 0 && auto_align)
becfe05e 4248 mips_align (log_size, 0);
1849d646 4249 insn_label = NULL;
670a50eb 4250 cons (1 << log_size);
3d3c5039
ILT		 4251}
4252
4253static void
4254s_err (x)
4255 int x;
4256{
670a50eb 4257 as_fatal ("Encountered `.err', aborting assembly");
3d3c5039
ILT		 4258}
4259
4260static void
4261s_extern (x)
4262 int x;
4263{
604633ae 4264 valueT size;
670a50eb
ILT		 4265 symbolS *symbolP;
4266
4267 symbolP = get_symbol ();
4268 if (*input_line_pointer == ',')
4269 input_line_pointer++;
5ac34ac3 4270 size = get_absolute_expression ();
670a50eb
ILT		 4271 S_SET_VALUE (symbolP, size);
4272 S_SET_EXTERNAL (symbolP);
4273
4274#ifdef OBJ_ECOFF
4275 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4276 so we use an additional ECOFF specific field. */
4277 symbolP->ecoff_undefined = 1;
4278#endif
3d3c5039
ILT		 4279}
4280
4281static void
becfe05e
ILT		 4282s_float_cons (type)
4283 int type;
3d3c5039 4284{
becfe05e 4285 mips_emit_delays ();
670a50eb
ILT		 4286
4287 if (auto_align)
becfe05e
ILT		 4288 if (type == 'd')
4289 mips_align (3, 0);
670a50eb 4290 else
becfe05e 4291 mips_align (2, 0);
670a50eb 4292
1849d646
ILT		 4293 insn_label = NULL;
4294
becfe05e 4295 float_cons (type);
3d3c5039
ILT		 4296}
4297
4298static void
4299s_option (x)
4300 int x;
4301{
dd3f1f76
ILT		 4302 char *opt;
4303 char c;
4304
4305 opt = input_line_pointer;
4306 c = get_symbol_end ();
4307
4308 /* FIXME: What do these options mean? */
4309 if (*opt == 'O')
4310 ;
4311 else if (strncmp (opt, "pic", 3) == 0)
4312 ;
4313 else
4314 as_warn ("Unrecognized option \"%s\"", opt);
4315
4316 *input_line_pointer = c;
670a50eb 4317 demand_empty_rest_of_line ();
3d3c5039
ILT		 4318}
4319
4320static void
4321s_mipsset (x)
4322 int x;
4323{
670a50eb
ILT		 4324 char *name = input_line_pointer, ch;
4325
4326 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4327 input_line_pointer++;
4328 ch = *input_line_pointer;
4329 *input_line_pointer = '\0';
4330
4331 if (strcmp (name, "reorder") == 0)
4332 {
4e95866e
ILT		 4333 if (mips_noreorder)
4334 {
4335 prev_insn_unreordered = 1;
4336 prev_prev_insn_unreordered = 1;
4337 }
670a50eb
ILT		 4338 mips_noreorder = 0;
4339 }
4340 else if (strcmp (name, "noreorder") == 0)
4341 {
becfe05e 4342 mips_emit_delays ();
670a50eb
ILT		 4343 mips_noreorder = 1;
4344 }
4345 else if (strcmp (name, "at") == 0)
4346 {
4347 mips_noat = 0;
4348 }
4349 else if (strcmp (name, "noat") == 0)
4350 {
4351 mips_noat = 1;
3d3c5039 4352 }
670a50eb
ILT		 4353 else if (strcmp (name, "macro") == 0)
4354 {
4355 mips_warn_about_macros = 0;
4356 }
4357 else if (strcmp (name, "nomacro") == 0)
4358 {
4359 if (mips_noreorder == 0)
4360 as_bad ("`noreorder' must be set before `nomacro'");
4361 mips_warn_about_macros = 1;
4362 }
4363 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
4364 {
4365 mips_nomove = 0;
4366 }
4367 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
4368 {
4369 mips_nomove = 1;
4370 }
4371 else if (strcmp (name, "bopt") == 0)
4372 {
4373 mips_nobopt = 0;
4374 }
4375 else if (strcmp (name, "nobopt") == 0)
4376 {
4377 mips_nobopt = 1;
4378 }
4379 else
4380 {
4381 as_warn ("Tried to set unrecognized symbol: %s\n", name);
4382 }
4383 *input_line_pointer = ch;
4384 demand_empty_rest_of_line ();
3d3c5039
ILT		 4385}
4386
becfe05e
ILT		 4387/* The same as the usual .space directive, except that we have to
4388 forget about any previous instruction. */
4389
4390static void
4391s_mips_space (param)
4392 int param;
4393{
4394 mips_emit_delays ();
1849d646 4395 insn_label = NULL;
becfe05e
ILT		 4396 s_space (param);
4397}
4398
3d3c5039
ILT		 4399int
4400tc_get_register ()
4401{
4402 int reg;
4403
4404 SKIP_WHITESPACE ();
4405 if (*input_line_pointer++ != '$')
4406 {
4407 as_warn ("expected `$'");
4408 return 0;
4409 }
4410 if (isdigit ((unsigned char) *input_line_pointer))
4411 {
4412 reg = get_absolute_expression ();
4413 if (reg < 0 || reg >= 32)
4414 {
4415 as_warn ("Bad register number");
4416 reg = 0;
4417 }
4418 }
4419 else
4420 {
4421 if (strncmp (input_line_pointer, "fp", 2) == 0)
4422 reg = 30;
4423 else if (strncmp (input_line_pointer, "sp", 2) == 0)
4424 reg = 29;
4425 else if (strncmp (input_line_pointer, "gp", 2) == 0)
4426 reg = 28;
4427 else if (strncmp (input_line_pointer, "at", 2) == 0)
4428 reg = 1;
4429 else
4430 {
4431 as_warn ("Unrecognized register name");
4432 return 0;
4433 }
4434 input_line_pointer += 2;
4435 }
4436 return reg;
4437}
4438
4439/*
4440 * Translate internal representation of relocation info to BFD target format.
4441 */
4442arelent *
4443tc_gen_reloc (section, fixp)
4444 asection *section;
4445 fixS *fixp;
4446{
4447 arelent *reloc;
4448
4449 reloc = (arelent *) xmalloc (sizeof (arelent));
4450 assert (reloc != 0);
4451
4452 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
4453 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
4454 if (fixp->fx_pcrel == 0)
4455 reloc->addend = fixp->fx_addnumber;
4456 else
4457#ifdef OBJ_ELF
4458 reloc->addend = 0;
4459#else
670a50eb 4460 reloc->addend = -reloc->address;
3d3c5039
ILT		 4461#endif
4462 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
52aa70b5
JW		 4463 if (reloc->howto == NULL)
4464 {
4465 as_bad_where (fixp->fx_file, fixp->fx_line,
4466 "Can not represent relocation in this object file format");
4467 return NULL;
4468 }
3d3c5039 4469
3d3c5039
ILT		 4470 return reloc;
4471}
4472
4473/* should never be called */
918692a5 4474valueT
670a50eb
ILT		 4475md_section_align (seg, addr)
4476 asection *seg;
918692a5 4477 valueT addr;
3d3c5039 4478{
670a50eb 4479 int align = bfd_get_section_alignment (stdoutput, seg);
3d3c5039 4480
670a50eb 4481 return ((addr + (1 << align) - 1) & (-1 << align));
3d3c5039
ILT		 4482}
4483
4484int
670a50eb
ILT		 4485md_estimate_size_before_relax (fragP, segtype)
4486 fragS *fragP;
4487 asection *segtype;
3d3c5039 4488{
670a50eb
ILT		 4489 as_fatal ("md_estimate_size_before_relax");
4490 return (1);
4491} /* md_estimate_size_before_relax() */
becfe05e
ILT		 4492
4493/* This function is called whenever a label is defined. It is used
4494 when handling branch delays; if a branch has a label, we assume we
4495 can not move it. */
4496
4497void
4498mips_define_label (sym)
4499 symbolS *sym;
4500{
4501 insn_label = sym;
4502}
3d3c5039 4503\f
f2a663d3
ILT		 4504#ifdef OBJ_ELF
4505
4506/* Write out the .reginfo section for a MIPS ELF file. */
4507
4508void
4509mips_elf_final_processing ()
4510{
4511 Elf32_RegInfo s;
4512
4513 s.ri_gprmask = mips_gprmask;
4514 s.ri_cprmask[0] = mips_cprmask[0];
4515 s.ri_cprmask[1] = mips_cprmask[1];
4516 s.ri_cprmask[2] = mips_cprmask[2];
4517 s.ri_cprmask[3] = mips_cprmask[3];
4518 /* The gp_value field is set by the MIPS ELF backend. */
4519
4520 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
4521 ((Elf32_External_RegInfo *)
4522 mips_regmask_frag));
4523}
4524
4525#endif /* OBJ_ELF */
4526\f
3d3c5039
ILT		 4527#ifndef OBJ_ECOFF
4528
4529/* These functions should really be defined by the object file format,
4530 since they are related to debugging information. However, this
4531 code has to work for the a.out format, which does not define them,
4532 so we provide simple versions here. These don't actually generate
4533 any debugging information, but they do simple checking and someday
4534 somebody may make them useful. */
4535
670a50eb
ILT		 4536typedef struct loc
4537{
4538 struct loc *loc_next;
4539 unsigned long loc_fileno;
4540 unsigned long loc_lineno;
4541 unsigned long loc_offset;
4542 unsigned short loc_delta;
4543 unsigned short loc_count;
3d3c5039 4544#if 0
670a50eb 4545 fragS *loc_frag;
3d3c5039 4546#endif
670a50eb
ILT		 4547}
4548locS;
3d3c5039 4549
670a50eb
ILT		 4550typedef struct proc
4551 {
3d3c5039
ILT		 4552 struct proc *proc_next;
4553 struct symbol *proc_isym;
4554 struct symbol *proc_end;
4555 unsigned long proc_reg_mask;
4556 unsigned long proc_reg_offset;
4557 unsigned long proc_fpreg_mask;
4558 unsigned long proc_fpreg_offset;
4559 unsigned long proc_frameoffset;
4560 unsigned long proc_framereg;
4561 unsigned long proc_pcreg;
4562 locS *proc_iline;
4563 struct file *proc_file;
4564 int proc_index;
670a50eb
ILT		 4565 }
4566procS;
3d3c5039 4567
670a50eb
ILT		 4568typedef struct file
4569 {
3d3c5039
ILT		 4570 struct file *file_next;
4571 unsigned long file_fileno;
4572 struct symbol *file_symbol;
4573 struct symbol *file_end;
4574 struct proc *file_proc;
4575 int file_numprocs;
670a50eb
ILT		 4576 }
4577fileS;
3d3c5039
ILT		 4578
4579static struct obstack proc_frags;
4580static procS *proc_lastP;
4581static procS *proc_rootP;
4582static int numprocs;
4583
4584static void
4585md_obj_begin ()
4586{
670a50eb 4587 obstack_begin (&proc_frags, 0x2000);
3d3c5039
ILT		 4588}
4589
4590static void
4591md_obj_end ()
4592{
4593 /* check for premature end, nesting errors, etc */
4594 if (proc_lastP && proc_lastP->proc_end == NULL)
670a50eb 4595 as_warn ("missing `.end' at end of assembly");
3d3c5039
ILT		 4596}
4597
4598extern char hex_value[];
4599
4600static long
4601get_number ()
4602{
670a50eb
ILT		 4603 int negative = 0;
4604 long val = 0;
3d3c5039 4605
670a50eb
ILT		 4606 if (*input_line_pointer == '-')
4607 {
4608 ++input_line_pointer;
4609 negative = 1;
3d3c5039 4610 }
670a50eb
ILT		 4611 if (!isdigit (*input_line_pointer))
4612 as_bad ("Expected simple number.");
4613 if (input_line_pointer[0] == '0')
4614 {
4615 if (input_line_pointer[1] == 'x')
4616 {
4617 input_line_pointer += 2;
4618 while (isxdigit (*input_line_pointer))
4619 {
4620 val <<= 4;
4621 val |= hex_value[(int) *input_line_pointer++];
3d3c5039 4622 }
670a50eb
ILT		 4623 return negative ? -val : val;
4624 }
4625 else
4626 {
4627 ++input_line_pointer;
4628 while (isdigit (*input_line_pointer))
4629 {
4630 val <<= 3;
4631 val |= *input_line_pointer++ - '0';
3d3c5039 4632 }
670a50eb 4633 return negative ? -val : val;
3d3c5039
ILT		 4634 }
4635 }
670a50eb
ILT		 4636 if (!isdigit (*input_line_pointer))
4637 {
4638 printf (" *input_line_pointer == '%c' 0x%02x\n",
4639 *input_line_pointer, *input_line_pointer);
4640 as_warn ("Invalid number");
4641 return -1;
3d3c5039 4642 }
670a50eb
ILT		 4643 while (isdigit (*input_line_pointer))
4644 {
4645 val *= 10;
4646 val += *input_line_pointer++ - '0';
3d3c5039 4647 }
670a50eb 4648 return negative ? -val : val;
3d3c5039
ILT		 4649}
4650
4651/* The .file directive; just like the usual .file directive, but there
4652 is an initial number which is the ECOFF file index. */
4653
4654static void
4655s_file (x)
4656 int x;
4657{
670a50eb 4658 int line;
3d3c5039 4659
670a50eb 4660 line = get_number ();
9a7d824a 4661 s_app_file (0);
3d3c5039
ILT		 4662}
4663
4664
4665/* The .end directive. */
4666
4667static void
4668s_mipsend (x)
4669 int x;
4670{
670a50eb
ILT		 4671 symbolS *p;
4672
4673 if (!is_end_of_line[(unsigned char) *input_line_pointer])
4674 {
4675 p = get_symbol ();
4676 demand_empty_rest_of_line ();
4677 }
4678 else
4679 p = NULL;
4680 if (now_seg != text_section)
4681 as_warn (".end not in text section");
4682 if (!proc_lastP)
4683 {
4684 as_warn (".end and no .ent seen yet.");
4685 return;
3d3c5039
ILT		 4686 }
4687
670a50eb
ILT		 4688 if (p != NULL)
4689 {
4690 assert (S_GET_NAME (p));
4691 if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym)))
4692 as_warn (".end symbol does not match .ent symbol.");
3d3c5039
ILT		 4693 }
4694
670a50eb 4695 proc_lastP->proc_end = (symbolS *) 1;
3d3c5039
ILT		 4696}
4697
4698/* The .aent and .ent directives. */
4699
4700static void
4701s_ent (aent)
4702 int aent;
4703{
670a50eb
ILT		 4704 int number = 0;
4705 procS *procP;
4706 symbolS *symbolP;
4707
4708 symbolP = get_symbol ();
4709 if (*input_line_pointer == ',')
4710 input_line_pointer++;
dd3f1f76 4711 SKIP_WHITESPACE ();
670a50eb
ILT		 4712 if (isdigit (*input_line_pointer) || *input_line_pointer == '-')
4713 number = get_number ();
4714 if (now_seg != text_section)
4715 as_warn (".ent or .aent not in text section.");
4716
4717 if (!aent && proc_lastP && proc_lastP->proc_end == NULL)
4718 as_warn ("missing `.end'");
4719
4720 if (!aent)
4721 {
4722 procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP));
4723 procP->proc_isym = symbolP;
4724 procP->proc_reg_mask = 0;
4725 procP->proc_reg_offset = 0;
4726 procP->proc_fpreg_mask = 0;
4727 procP->proc_fpreg_offset = 0;
4728 procP->proc_frameoffset = 0;
4729 procP->proc_framereg = 0;
4730 procP->proc_pcreg = 0;
4731 procP->proc_end = NULL;
4732 procP->proc_next = NULL;
4733 if (proc_lastP)
4734 proc_lastP->proc_next = procP;
4735 else
4736 proc_rootP = procP;
4737 proc_lastP = procP;
4738 numprocs++;
3d3c5039 4739 }
670a50eb 4740 demand_empty_rest_of_line ();
3d3c5039
ILT		 4741}
4742
4743/* The .frame directive. */
4744
88225433 4745#if 0
3d3c5039
ILT		 4746static void
4747s_frame (x)
670a50eb 4748 int x;
3d3c5039 4749{
670a50eb
ILT		 4750 char str[100];
4751 symbolS *symP;
4752 int frame_reg;
4753 int frame_off;
4754 int pcreg;
4755
4756 frame_reg = tc_get_register ();
4757 if (*input_line_pointer == ',')
4758 input_line_pointer++;
5ac34ac3 4759 frame_off = get_absolute_expression ();
670a50eb
ILT		 4760 if (*input_line_pointer == ',')
4761 input_line_pointer++;
4762 pcreg = tc_get_register ();
4763
4764 /* bob third eye */
4765 assert (proc_rootP);
4766 proc_rootP->proc_framereg = frame_reg;
4767 proc_rootP->proc_frameoffset = frame_off;
4768 proc_rootP->proc_pcreg = pcreg;
4769 /* bob macho .frame */
4770
4771 /* We don't have to write out a frame stab for unoptimized code. */
4772 if (!(frame_reg == 30 && frame_off == 0))
4773 {
4774 if (!proc_lastP)
4775 as_warn ("No .ent for .frame to use.");
4776 (void) sprintf (str, "R%d;%d", frame_reg, frame_off);
4777 symP = symbol_new (str, N_VFP, 0, frag_now);
4778 S_SET_TYPE (symP, N_RMASK);
4779 S_SET_OTHER (symP, 0);
4780 S_SET_DESC (symP, 0);
4781 symP->sy_forward = proc_lastP->proc_isym;
4782 /* bob perhaps I should have used pseudo set */
3d3c5039 4783 }
670a50eb 4784 demand_empty_rest_of_line ();
3d3c5039 4785}
88225433 4786#endif
3d3c5039
ILT		 4787
4788/* The .fmask and .mask directives. */
4789
88225433 4790#if 0
3d3c5039
ILT		 4791static void
4792s_mask (reg_type)
4793 char reg_type;
4794{
670a50eb
ILT		 4795 char str[100], *strP;
4796 symbolS *symP;
4797 int i;
4798 unsigned int mask;
4799 int off;
4800
4801 mask = get_number ();
4802 if (*input_line_pointer == ',')
4803 input_line_pointer++;
4804 off = get_absolute_expression ();
4805
4806 /* bob only for coff */
4807 assert (proc_rootP);
4808 if (reg_type == 'F')
4809 {
4810 proc_rootP->proc_fpreg_mask = mask;
4811 proc_rootP->proc_fpreg_offset = off;
3d3c5039 4812 }
670a50eb
ILT		 4813 else
4814 {
4815 proc_rootP->proc_reg_mask = mask;
4816 proc_rootP->proc_reg_offset = off;
4817 }
4818
4819 /* bob macho .mask + .fmask */
3d3c5039 4820
670a50eb
ILT		 4821 /* We don't have to write out a mask stab if no saved regs. */
4822 if (!(mask == 0))
4823 {
4824 if (!proc_lastP)
4825 as_warn ("No .ent for .mask to use.");
4826 strP = str;
4827 for (i = 0; i < 32; i++)
4828 {
4829 if (mask % 2)
4830 {
4831 sprintf (strP, "%c%d,", reg_type, i);
4832 strP += strlen (strP);
4833 }
3d3c5039 4834 mask /= 2;
670a50eb
ILT		 4835 }
4836 sprintf (strP, ";%d,", off);
4837 symP = symbol_new (str, N_RMASK, 0, frag_now);
4838 S_SET_TYPE (symP, N_RMASK);
4839 S_SET_OTHER (symP, 0);
4840 S_SET_DESC (symP, 0);
4841 symP->sy_forward = proc_lastP->proc_isym;
4842 /* bob perhaps I should have used pseudo set */
3d3c5039 4843 }
3d3c5039 4844}
88225433 4845#endif
3d3c5039
ILT		 4846
4847/* The .loc directive. */
4848
88225433 4849#if 0
3d3c5039
ILT		 4850static void
4851s_loc (x)
4852 int x;
4853{
670a50eb
ILT		 4854 symbolS *symbolP;
4855 int lineno;
4856 int addroff;
3d3c5039 4857
670a50eb 4858 assert (now_seg == text_section);
3d3c5039 4859
670a50eb
ILT		 4860 lineno = get_number ();
4861 addroff = obstack_next_free (&frags) - frag_now->fr_literal;
3d3c5039 4862
670a50eb
ILT		 4863 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
4864 S_SET_TYPE (symbolP, N_SLINE);
4865 S_SET_OTHER (symbolP, 0);
4866 S_SET_DESC (symbolP, lineno);
4867 symbolP->sy_segment = now_seg;
3d3c5039 4868}
88225433 4869#endif
3d3c5039
ILT		 4870
4871#endif /* ! defined (OBJ_ECOFF) */
GDB Binutils - Deliverables
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