Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b3adc24a | 2 | Copyright (C) 1993-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
6f2117ba PH |
144 | /* The name if this is an label. */ |
145 | char label[16]; | |
146 | ||
147 | /* The target label name if this is an branch. */ | |
148 | char target[16]; | |
149 | ||
47e39b9d RS |
150 | /* The frag that contains the instruction. */ |
151 | struct frag *frag; | |
152 | ||
153 | /* The offset into FRAG of the first instruction byte. */ | |
154 | long where; | |
155 | ||
156 | /* The relocs associated with the instruction, if any. */ | |
157 | fixS *fixp[3]; | |
158 | ||
a38419a5 RS |
159 | /* True if this entry cannot be moved from its current position. */ |
160 | unsigned int fixed_p : 1; | |
47e39b9d | 161 | |
708587a4 | 162 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
163 | unsigned int noreorder_p : 1; |
164 | ||
2fa15973 RS |
165 | /* True for mips16 instructions that jump to an absolute address. */ |
166 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
167 | |
168 | /* True if this instruction is complete. */ | |
169 | unsigned int complete_p : 1; | |
e407c74b NC |
170 | |
171 | /* True if this instruction is cleared from history by unconditional | |
172 | branch. */ | |
173 | unsigned int cleared_p : 1; | |
47e39b9d RS |
174 | }; |
175 | ||
a325df1d TS |
176 | /* The ABI to use. */ |
177 | enum mips_abi_level | |
178 | { | |
179 | NO_ABI = 0, | |
180 | O32_ABI, | |
181 | O64_ABI, | |
182 | N32_ABI, | |
183 | N64_ABI, | |
184 | EABI_ABI | |
185 | }; | |
186 | ||
187 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 188 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 189 | |
143d77c5 EC |
190 | /* Whether or not we have code that can call pic code. */ |
191 | int mips_abicalls = FALSE; | |
192 | ||
aa6975fb ILT |
193 | /* Whether or not we have code which can be put into a shared |
194 | library. */ | |
195 | static bfd_boolean mips_in_shared = TRUE; | |
196 | ||
252b5132 RH |
197 | /* This is the set of options which may be modified by the .set |
198 | pseudo-op. We use a struct so that .set push and .set pop are more | |
199 | reliable. */ | |
200 | ||
e972090a NC |
201 | struct mips_set_options |
202 | { | |
252b5132 RH |
203 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
204 | if it has not been initialized. Changed by `.set mipsN', and the | |
205 | -mipsN command line option, and the default CPU. */ | |
206 | int isa; | |
846ef2d0 RS |
207 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
208 | <asename>', by command line options, and based on the default | |
209 | architecture. */ | |
210 | int ase; | |
252b5132 RH |
211 | /* Whether we are assembling for the mips16 processor. 0 if we are |
212 | not, 1 if we are, and -1 if the value has not been initialized. | |
213 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
214 | -nomips16 command line options, and the default CPU. */ | |
215 | int mips16; | |
df58fc94 RS |
216 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
217 | 1 if we are, and -1 if the value has not been initialized. Changed | |
218 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
219 | and -mno-micromips command line options, and the default CPU. */ | |
220 | int micromips; | |
252b5132 RH |
221 | /* Non-zero if we should not reorder instructions. Changed by `.set |
222 | reorder' and `.set noreorder'. */ | |
223 | int noreorder; | |
741fe287 MR |
224 | /* Non-zero if we should not permit the register designated "assembler |
225 | temporary" to be used in instructions. The value is the register | |
226 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
227 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
228 | unsigned int at; | |
252b5132 RH |
229 | /* Non-zero if we should warn when a macro instruction expands into |
230 | more than one machine instruction. Changed by `.set nomacro' and | |
231 | `.set macro'. */ | |
232 | int warn_about_macros; | |
233 | /* Non-zero if we should not move instructions. Changed by `.set | |
234 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
235 | int nomove; | |
236 | /* Non-zero if we should not optimize branches by moving the target | |
237 | of the branch into the delay slot. Actually, we don't perform | |
238 | this optimization anyhow. Changed by `.set bopt' and `.set | |
239 | nobopt'. */ | |
240 | int nobopt; | |
241 | /* Non-zero if we should not autoextend mips16 instructions. | |
242 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
243 | int noautoextend; | |
833794fc MR |
244 | /* True if we should only emit 32-bit microMIPS instructions. |
245 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
246 | and -mno-insn32 command line options. */ | |
247 | bfd_boolean insn32; | |
a325df1d TS |
248 | /* Restrict general purpose registers and floating point registers |
249 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
250 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 251 | int gp; |
0b35dfee | 252 | int fp; |
fef14a42 TS |
253 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
254 | command line option, and the default CPU. */ | |
255 | int arch; | |
aed1a261 RS |
256 | /* True if ".set sym32" is in effect. */ |
257 | bfd_boolean sym32; | |
037b32b9 AN |
258 | /* True if floating-point operations are not allowed. Changed by .set |
259 | softfloat or .set hardfloat, by command line options -msoft-float or | |
260 | -mhard-float. The default is false. */ | |
261 | bfd_boolean soft_float; | |
262 | ||
263 | /* True if only single-precision floating-point operations are allowed. | |
264 | Changed by .set singlefloat or .set doublefloat, command-line options | |
265 | -msingle-float or -mdouble-float. The default is false. */ | |
266 | bfd_boolean single_float; | |
351cdf24 MF |
267 | |
268 | /* 1 if single-precision operations on odd-numbered registers are | |
269 | allowed. */ | |
270 | int oddspreg; | |
3315614d MF |
271 | |
272 | /* The set of ASEs that should be enabled for the user specified | |
273 | architecture. This cannot be inferred from 'arch' for all cores | |
274 | as processors only have a unique 'arch' if they add architecture | |
275 | specific instructions (UDI). */ | |
276 | int init_ase; | |
252b5132 RH |
277 | }; |
278 | ||
919731af | 279 | /* Specifies whether module level options have been checked yet. */ |
280 | static bfd_boolean file_mips_opts_checked = FALSE; | |
281 | ||
7361da2c AB |
282 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
283 | value has not been initialized. Changed by `.nan legacy' and | |
284 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
285 | options, and the default CPU. */ | |
286 | static int mips_nan2008 = -1; | |
a325df1d | 287 | |
0b35dfee | 288 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 289 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 290 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 291 | |
0b35dfee | 292 | static struct mips_set_options file_mips_opts = |
293 | { | |
294 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
295 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
296 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 297 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
3315614d MF |
298 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, |
299 | /* init_ase */ 0 | |
0b35dfee | 300 | }; |
252b5132 | 301 | |
0b35dfee | 302 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 303 | |
e972090a NC |
304 | static struct mips_set_options mips_opts = |
305 | { | |
846ef2d0 | 306 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 307 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 308 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 309 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
3315614d MF |
310 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, |
311 | /* init_ase */ 0 | |
e7af610e | 312 | }; |
252b5132 | 313 | |
846ef2d0 RS |
314 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
315 | static unsigned int file_ase_explicit; | |
316 | ||
252b5132 RH |
317 | /* These variables are filled in with the masks of registers used. |
318 | The object format code reads them and puts them in the appropriate | |
319 | place. */ | |
320 | unsigned long mips_gprmask; | |
321 | unsigned long mips_cprmask[4]; | |
322 | ||
738f4d98 | 323 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
324 | static int file_ase_mips16; |
325 | ||
3994f87e TS |
326 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
327 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
328 | || mips_opts.isa == ISA_MIPS32R3 \ |
329 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 330 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
331 | || mips_opts.isa == ISA_MIPS64R2 \ |
332 | || mips_opts.isa == ISA_MIPS64R3 \ | |
333 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 334 | |
df58fc94 RS |
335 | /* True if any microMIPS code was produced. */ |
336 | static int file_ase_micromips; | |
337 | ||
b12dd2e4 CF |
338 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
339 | #ifdef TE_IRIX | |
1180b5a4 | 340 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 341 | #else |
1180b5a4 RS |
342 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
343 | because there's no place for any addend, the only acceptable | |
344 | expression is a bare symbol. */ | |
345 | #define MIPS_JALR_HINT_P(EXPR) \ | |
346 | (!HAVE_IN_PLACE_ADDENDS \ | |
347 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
348 | #endif |
349 | ||
ec68c924 | 350 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 351 | static const char *mips_arch_string; |
ec68c924 EC |
352 | |
353 | /* The argument of the -mtune= flag. The architecture for which we | |
354 | are optimizing. */ | |
355 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 356 | static const char *mips_tune_string; |
ec68c924 | 357 | |
316f5878 | 358 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
359 | static int mips_32bitmode = 0; |
360 | ||
316f5878 RS |
361 | /* True if the given ABI requires 32-bit registers. */ |
362 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
363 | ||
364 | /* Likewise 64-bit registers. */ | |
707bfff6 | 365 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 366 | ((ABI) == N32_ABI \ |
707bfff6 | 367 | || (ABI) == N64_ABI \ |
316f5878 RS |
368 | || (ABI) == O64_ABI) |
369 | ||
7361da2c AB |
370 | #define ISA_IS_R6(ISA) \ |
371 | ((ISA) == ISA_MIPS32R6 \ | |
372 | || (ISA) == ISA_MIPS64R6) | |
373 | ||
ad3fea08 | 374 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
375 | #define ISA_HAS_64BIT_REGS(ISA) \ |
376 | ((ISA) == ISA_MIPS3 \ | |
377 | || (ISA) == ISA_MIPS4 \ | |
378 | || (ISA) == ISA_MIPS5 \ | |
379 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
380 | || (ISA) == ISA_MIPS64R2 \ |
381 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
382 | || (ISA) == ISA_MIPS64R5 \ |
383 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 384 | |
ad3fea08 TS |
385 | /* Return true if ISA supports 64 bit wide float registers. */ |
386 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
387 | ((ISA) == ISA_MIPS3 \ | |
388 | || (ISA) == ISA_MIPS4 \ | |
389 | || (ISA) == ISA_MIPS5 \ | |
390 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
391 | || (ISA) == ISA_MIPS32R3 \ |
392 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 393 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 394 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
395 | || (ISA) == ISA_MIPS64R2 \ |
396 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
397 | || (ISA) == ISA_MIPS64R5 \ |
398 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 399 | |
af7ee8bf CD |
400 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
401 | instructions. */ | |
707bfff6 | 402 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 403 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
404 | || (ISA) == ISA_MIPS64R3 \ |
405 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 406 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
407 | || (mips_opts.micromips \ |
408 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
409 | ) | |
af7ee8bf CD |
410 | |
411 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
412 | instructions. */ | |
707bfff6 TS |
413 | #define ISA_HAS_ROR(ISA) \ |
414 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
415 | || (ISA) == ISA_MIPS32R3 \ |
416 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 417 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 418 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
419 | || (ISA) == ISA_MIPS64R3 \ |
420 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 421 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 422 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
423 | || mips_opts.micromips \ |
424 | ) | |
707bfff6 | 425 | |
7455baf8 | 426 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
427 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
428 | (((ISA) == ISA_MIPS32 \ | |
429 | || (ISA) == ISA_MIPS32R2 \ | |
430 | || (ISA) == ISA_MIPS32R3 \ | |
431 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 432 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
433 | || (ISA) == ISA_MIPS64 \ |
434 | || (ISA) == ISA_MIPS64R2 \ | |
435 | || (ISA) == ISA_MIPS64R3 \ | |
436 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 437 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 | 438 | || (CPU) == CPU_R5900) \ |
bd782c07 | 439 | && ((CPU) != CPU_GS464 \ |
9108bc33 CX |
440 | || (CPU) != CPU_GS464E \ |
441 | || (CPU) != CPU_GS264E)) | |
af7ee8bf | 442 | |
ad3fea08 TS |
443 | /* Return true if ISA supports move to/from high part of a 64-bit |
444 | floating-point register. */ | |
445 | #define ISA_HAS_MXHC1(ISA) \ | |
446 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
447 | || (ISA) == ISA_MIPS32R3 \ |
448 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
449 | || (ISA) == ISA_MIPS32R6 \ |
450 | || (ISA) == ISA_MIPS64R2 \ | |
451 | || (ISA) == ISA_MIPS64R3 \ | |
452 | || (ISA) == ISA_MIPS64R5 \ | |
453 | || (ISA) == ISA_MIPS64R6) | |
454 | ||
455 | /* Return true if ISA supports legacy NAN. */ | |
456 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
457 | ((ISA) == ISA_MIPS1 \ | |
458 | || (ISA) == ISA_MIPS2 \ | |
459 | || (ISA) == ISA_MIPS3 \ | |
460 | || (ISA) == ISA_MIPS4 \ | |
461 | || (ISA) == ISA_MIPS5 \ | |
462 | || (ISA) == ISA_MIPS32 \ | |
463 | || (ISA) == ISA_MIPS32R2 \ | |
464 | || (ISA) == ISA_MIPS32R3 \ | |
465 | || (ISA) == ISA_MIPS32R5 \ | |
466 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
467 | || (ISA) == ISA_MIPS64R2 \ |
468 | || (ISA) == ISA_MIPS64R3 \ | |
469 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 470 | |
bad1aba3 | 471 | #define GPR_SIZE \ |
472 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
473 | ? 32 \ | |
474 | : mips_opts.gp) | |
ca4e0257 | 475 | |
bad1aba3 | 476 | #define FPR_SIZE \ |
477 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
478 | ? 32 \ | |
479 | : mips_opts.fp) | |
ca4e0257 | 480 | |
316f5878 | 481 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 482 | |
316f5878 | 483 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 484 | |
3b91255e RS |
485 | /* True if relocations are stored in-place. */ |
486 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
487 | ||
aed1a261 RS |
488 | /* The ABI-derived address size. */ |
489 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 490 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 491 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 492 | |
aed1a261 RS |
493 | /* The size of symbolic constants (i.e., expressions of the form |
494 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
495 | #define HAVE_32BIT_SYMBOLS \ | |
496 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
497 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 498 | |
b7c7d6c1 TS |
499 | /* Addresses are loaded in different ways, depending on the address size |
500 | in use. The n32 ABI Documentation also mandates the use of additions | |
501 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 502 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 503 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
504 | |
505 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 506 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
507 | |
508 | #define ADDRESS_LOAD_INSN \ | |
509 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
510 | ||
511 | #define ADDRESS_STORE_INSN \ | |
512 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
513 | ||
a4672219 | 514 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
515 | #define CPU_HAS_MIPS16(cpu) \ |
516 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
517 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 518 | |
2309ddf2 | 519 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
520 | #define CPU_HAS_MICROMIPS(cpu) 0 |
521 | ||
60b63b72 RS |
522 | /* True if CPU has a dror instruction. */ |
523 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
524 | ||
525 | /* True if CPU has a ror instruction. */ | |
526 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
527 | ||
6f2117ba | 528 | /* True if CPU is in the Octeon family. */ |
2c629856 N |
529 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
530 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 531 | |
dd3cbb7e | 532 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 533 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 534 | |
0aa27725 RS |
535 | /* True, if CPU has support for ldc1 and sdc1. */ |
536 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
537 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
538 | ||
c8978940 CD |
539 | /* True if mflo and mfhi can be immediately followed by instructions |
540 | which write to the HI and LO registers. | |
541 | ||
542 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
543 | (at least) two instructions between the reads of HI/LO and | |
544 | instructions which write them, and later ISAs do not. Contradicting | |
545 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
546 | the UM for the NEC Vr5000) document needing the instructions between | |
547 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
548 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
549 | earlier-ISA CPUs for which CPU documentation declares that the | |
550 | instructions are really interlocked. */ | |
551 | #define hilo_interlocks \ | |
552 | (mips_opts.isa == ISA_MIPS32 \ | |
553 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
554 | || mips_opts.isa == ISA_MIPS32R3 \ |
555 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 556 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
557 | || mips_opts.isa == ISA_MIPS64 \ |
558 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
559 | || mips_opts.isa == ISA_MIPS64R3 \ |
560 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 561 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 562 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 563 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
564 | || mips_opts.arch == CPU_R10000 \ |
565 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
566 | || mips_opts.arch == CPU_R14000 \ |
567 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 568 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 569 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 570 | || mips_opts.micromips \ |
c8978940 | 571 | ) |
252b5132 RH |
572 | |
573 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
574 | from the GPRs after they are loaded from memory, and thus does not |
575 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 576 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
577 | level I and microMIPS mode instructions are always interlocked. */ |
578 | #define gpr_interlocks \ | |
579 | (mips_opts.isa != ISA_MIPS1 \ | |
580 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 581 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
582 | || mips_opts.micromips \ |
583 | ) | |
252b5132 | 584 | |
81912461 ILT |
585 | /* Whether the processor uses hardware interlocks to avoid delays |
586 | required by coprocessor instructions, and thus does not require | |
587 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
588 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
589 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 590 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
591 | levels I, II, and III and microMIPS mode instructions are always |
592 | interlocked. */ | |
bdaaa2e1 | 593 | /* Itbl support may require additional care here. */ |
81912461 ILT |
594 | #define cop_interlocks \ |
595 | ((mips_opts.isa != ISA_MIPS1 \ | |
596 | && mips_opts.isa != ISA_MIPS2 \ | |
597 | && mips_opts.isa != ISA_MIPS3) \ | |
598 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 599 | || mips_opts.micromips \ |
81912461 ILT |
600 | ) |
601 | ||
602 | /* Whether the processor uses hardware interlocks to protect reads | |
603 | from coprocessor registers after they are loaded from memory, and | |
604 | thus does not require nops to be inserted. This applies to | |
605 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
606 | requires at MIPS ISA level I and microMIPS mode instructions are |
607 | always interlocked. */ | |
608 | #define cop_mem_interlocks \ | |
609 | (mips_opts.isa != ISA_MIPS1 \ | |
610 | || mips_opts.micromips \ | |
611 | ) | |
252b5132 | 612 | |
6b76fefe CM |
613 | /* Is this a mfhi or mflo instruction? */ |
614 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
615 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
616 | ||
df58fc94 RS |
617 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
618 | has been selected. This implies, in particular, that addresses of text | |
619 | labels have their LSB set. */ | |
620 | #define HAVE_CODE_COMPRESSION \ | |
621 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
622 | ||
42429eac | 623 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 624 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
625 | #define GPR_SMIN (-GPR_SMAX - 1) |
626 | ||
252b5132 RH |
627 | /* MIPS PIC level. */ |
628 | ||
a161fe53 | 629 | enum mips_pic_level mips_pic; |
252b5132 | 630 | |
c9914766 | 631 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 632 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 633 | static int mips_big_got = 0; |
252b5132 RH |
634 | |
635 | /* 1 if trap instructions should used for overflow rather than break | |
636 | instructions. */ | |
c9914766 | 637 | static int mips_trap = 0; |
252b5132 | 638 | |
119d663a | 639 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 640 | by assembling two single width halves into two single width floating |
119d663a NC |
641 | point registers which just happen to alias the double width destination |
642 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 643 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
644 | automatically at assemble time. */ |
645 | static int mips_disable_float_construction; | |
646 | ||
252b5132 RH |
647 | /* Non-zero if any .set noreorder directives were used. */ |
648 | ||
649 | static int mips_any_noreorder; | |
650 | ||
6b76fefe CM |
651 | /* Non-zero if nops should be inserted when the register referenced in |
652 | an mfhi/mflo instruction is read in the next two instructions. */ | |
653 | static int mips_7000_hilo_fix; | |
654 | ||
02ffd3e4 | 655 | /* The size of objects in the small data section. */ |
156c2f8b | 656 | static unsigned int g_switch_value = 8; |
252b5132 RH |
657 | /* Whether the -G option was used. */ |
658 | static int g_switch_seen = 0; | |
659 | ||
660 | #define N_RMASK 0xc4 | |
661 | #define N_VFP 0xd4 | |
662 | ||
663 | /* If we can determine in advance that GP optimization won't be | |
664 | possible, we can skip the relaxation stuff that tries to produce | |
665 | GP-relative references. This makes delay slot optimization work | |
666 | better. | |
667 | ||
668 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
669 | gcc output. It needs to guess right for gcc, otherwise gcc |
670 | will put what it thinks is a GP-relative instruction in a branch | |
671 | delay slot. | |
252b5132 RH |
672 | |
673 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
674 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 675 | static int nopic_need_relax (symbolS *, int); |
252b5132 | 676 | |
6f2117ba | 677 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
678 | static struct hash_control *op_hash = NULL; |
679 | ||
680 | /* The opcode hash table we use for the mips16. */ | |
681 | static struct hash_control *mips16_op_hash = NULL; | |
682 | ||
df58fc94 RS |
683 | /* The opcode hash table we use for the microMIPS ASE. */ |
684 | static struct hash_control *micromips_op_hash = NULL; | |
685 | ||
252b5132 | 686 | /* This array holds the chars that always start a comment. If the |
6f2117ba | 687 | pre-processor is disabled, these aren't very useful. */ |
252b5132 RH |
688 | const char comment_chars[] = "#"; |
689 | ||
690 | /* This array holds the chars that only start a comment at the beginning of | |
691 | a line. If the line seems to have the form '# 123 filename' | |
6f2117ba | 692 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
693 | /* Note that input_file.c hand checks for '#' at the beginning of the |
694 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 695 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
696 | /* Also note that C style comments are always supported. */ |
697 | const char line_comment_chars[] = "#"; | |
698 | ||
bdaaa2e1 | 699 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 700 | const char line_separator_chars[] = ";"; |
252b5132 | 701 | |
6f2117ba | 702 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
252b5132 RH |
703 | const char EXP_CHARS[] = "eE"; |
704 | ||
6f2117ba PH |
705 | /* Chars that mean this number is a floating point constant. |
706 | As in 0f12.456 | |
707 | or 0d1.2345e12. */ | |
252b5132 RH |
708 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
709 | ||
710 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
711 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
6f2117ba | 712 | but nothing is ideal around here. */ |
252b5132 | 713 | |
e3de51ce | 714 | /* Types of printf format used for instruction-related error messages. |
6f2117ba PH |
715 | "I" means int ("%d") and "S" means string ("%s"). */ |
716 | enum mips_insn_error_format | |
717 | { | |
e3de51ce RS |
718 | ERR_FMT_PLAIN, |
719 | ERR_FMT_I, | |
720 | ERR_FMT_SS, | |
721 | }; | |
722 | ||
723 | /* Information about an error that was found while assembling the current | |
724 | instruction. */ | |
6f2117ba PH |
725 | struct mips_insn_error |
726 | { | |
e3de51ce RS |
727 | /* We sometimes need to match an instruction against more than one |
728 | opcode table entry. Errors found during this matching are reported | |
729 | against a particular syntactic argument rather than against the | |
730 | instruction as a whole. We grade these messages so that errors | |
731 | against argument N have a greater priority than an error against | |
732 | any argument < N, since the former implies that arguments up to N | |
733 | were acceptable and that the opcode entry was therefore a closer match. | |
734 | If several matches report an error against the same argument, | |
735 | we only use that error if it is the same in all cases. | |
736 | ||
737 | min_argnum is the minimum argument number for which an error message | |
738 | should be accepted. It is 0 if MSG is against the instruction as | |
739 | a whole. */ | |
740 | int min_argnum; | |
741 | ||
742 | /* The printf()-style message, including its format and arguments. */ | |
743 | enum mips_insn_error_format format; | |
744 | const char *msg; | |
6f2117ba PH |
745 | union |
746 | { | |
e3de51ce RS |
747 | int i; |
748 | const char *ss[2]; | |
749 | } u; | |
750 | }; | |
751 | ||
752 | /* The error that should be reported for the current instruction. */ | |
753 | static struct mips_insn_error insn_error; | |
252b5132 RH |
754 | |
755 | static int auto_align = 1; | |
756 | ||
757 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
758 | offset in the stack frame from which to restore the $gp register. | |
759 | This is set by the .cprestore pseudo-op, and saved in this | |
760 | variable. */ | |
761 | static offsetT mips_cprestore_offset = -1; | |
762 | ||
67c1ffbe | 763 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 764 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 765 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
766 | static offsetT mips_cpreturn_offset = -1; |
767 | static int mips_cpreturn_register = -1; | |
768 | static int mips_gp_register = GP; | |
def2e0dd | 769 | static int mips_gprel_offset = 0; |
6478892d | 770 | |
7a621144 DJ |
771 | /* Whether mips_cprestore_offset has been set in the current function |
772 | (or whether it has already been warned about, if not). */ | |
773 | static int mips_cprestore_valid = 0; | |
774 | ||
252b5132 RH |
775 | /* This is the register which holds the stack frame, as set by the |
776 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
777 | static int mips_frame_reg = SP; | |
778 | ||
7a621144 DJ |
779 | /* Whether mips_frame_reg has been set in the current function |
780 | (or whether it has already been warned about, if not). */ | |
781 | static int mips_frame_reg_valid = 0; | |
782 | ||
252b5132 RH |
783 | /* To output NOP instructions correctly, we need to keep information |
784 | about the previous two instructions. */ | |
785 | ||
786 | /* Whether we are optimizing. The default value of 2 means to remove | |
787 | unneeded NOPs and swap branch instructions when possible. A value | |
788 | of 1 means to not swap branches. A value of 0 means to always | |
789 | insert NOPs. */ | |
790 | static int mips_optimize = 2; | |
791 | ||
792 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
793 | equivalent to seeing no -g option at all. */ | |
794 | static int mips_debug = 0; | |
795 | ||
7d8e00cf RS |
796 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
797 | #define MAX_VR4130_NOPS 4 | |
798 | ||
799 | /* The maximum number of NOPs needed to fill delay slots. */ | |
800 | #define MAX_DELAY_NOPS 2 | |
801 | ||
802 | /* The maximum number of NOPs needed for any purpose. */ | |
803 | #define MAX_NOPS 4 | |
71400594 | 804 | |
6f2117ba PH |
805 | /* The maximum range of context length of ll/sc. */ |
806 | #define MAX_LLSC_RANGE 20 | |
807 | ||
71400594 RS |
808 | /* A list of previous instructions, with index 0 being the most recent. |
809 | We need to look back MAX_NOPS instructions when filling delay slots | |
810 | or working around processor errata. We need to look back one | |
811 | instruction further if we're thinking about using history[0] to | |
812 | fill a branch delay slot. */ | |
6f2117ba | 813 | static struct mips_cl_insn history[1 + MAX_NOPS + MAX_LLSC_RANGE]; |
252b5132 | 814 | |
fc76e730 | 815 | /* Arrays of operands for each instruction. */ |
14daeee3 | 816 | #define MAX_OPERANDS 6 |
6f2117ba PH |
817 | struct mips_operand_array |
818 | { | |
fc76e730 RS |
819 | const struct mips_operand *operand[MAX_OPERANDS]; |
820 | }; | |
821 | static struct mips_operand_array *mips_operands; | |
822 | static struct mips_operand_array *mips16_operands; | |
823 | static struct mips_operand_array *micromips_operands; | |
824 | ||
1e915849 | 825 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
826 | static struct mips_cl_insn nop_insn; |
827 | static struct mips_cl_insn mips16_nop_insn; | |
828 | static struct mips_cl_insn micromips_nop16_insn; | |
829 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 | 830 | |
6f2117ba PH |
831 | /* Sync instructions used by insert sync. */ |
832 | static struct mips_cl_insn sync_insn; | |
833 | ||
1e915849 | 834 | /* The appropriate nop for the current mode. */ |
833794fc MR |
835 | #define NOP_INSN (mips_opts.mips16 \ |
836 | ? &mips16_nop_insn \ | |
837 | : (mips_opts.micromips \ | |
838 | ? (mips_opts.insn32 \ | |
839 | ? µmips_nop32_insn \ | |
840 | : µmips_nop16_insn) \ | |
841 | : &nop_insn)) | |
df58fc94 RS |
842 | |
843 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
844 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
845 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
846 | ? 2 : 4) | |
252b5132 | 847 | |
252b5132 RH |
848 | /* If this is set, it points to a frag holding nop instructions which |
849 | were inserted before the start of a noreorder section. If those | |
850 | nops turn out to be unnecessary, the size of the frag can be | |
851 | decreased. */ | |
852 | static fragS *prev_nop_frag; | |
853 | ||
854 | /* The number of nop instructions we created in prev_nop_frag. */ | |
855 | static int prev_nop_frag_holds; | |
856 | ||
857 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 858 | prev_nop_frag. */ |
252b5132 RH |
859 | static int prev_nop_frag_required; |
860 | ||
861 | /* The number of instructions we've seen since prev_nop_frag. */ | |
862 | static int prev_nop_frag_since; | |
863 | ||
e8044f35 RS |
864 | /* Relocations against symbols are sometimes done in two parts, with a HI |
865 | relocation and a LO relocation. Each relocation has only 16 bits of | |
866 | space to store an addend. This means that in order for the linker to | |
867 | handle carries correctly, it must be able to locate both the HI and | |
868 | the LO relocation. This means that the relocations must appear in | |
869 | order in the relocation table. | |
252b5132 RH |
870 | |
871 | In order to implement this, we keep track of each unmatched HI | |
872 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 873 | corresponding LO relocation. */ |
252b5132 | 874 | |
e972090a NC |
875 | struct mips_hi_fixup |
876 | { | |
252b5132 RH |
877 | /* Next HI fixup. */ |
878 | struct mips_hi_fixup *next; | |
879 | /* This fixup. */ | |
880 | fixS *fixp; | |
881 | /* The section this fixup is in. */ | |
882 | segT seg; | |
883 | }; | |
884 | ||
885 | /* The list of unmatched HI relocs. */ | |
886 | ||
887 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
888 | ||
64bdfcaf RS |
889 | /* The frag containing the last explicit relocation operator. |
890 | Null if explicit relocations have not been used. */ | |
891 | ||
892 | static fragS *prev_reloc_op_frag; | |
893 | ||
252b5132 RH |
894 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
895 | ||
e972090a NC |
896 | static const unsigned int mips16_to_32_reg_map[] = |
897 | { | |
252b5132 RH |
898 | 16, 17, 2, 3, 4, 5, 6, 7 |
899 | }; | |
60b63b72 | 900 | |
df58fc94 RS |
901 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
902 | ||
df58fc94 | 903 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
904 | |
905 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 906 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
907 | { |
908 | 5, 5, 6, 4, 4, 4, 4, 4 | |
909 | }; | |
e76ff5ab | 910 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
911 | { |
912 | 6, 7, 7, 21, 22, 5, 6, 7 | |
913 | }; | |
914 | ||
df58fc94 RS |
915 | /* The microMIPS registers with type m. */ |
916 | static const unsigned int micromips_to_32_reg_m_map[] = | |
917 | { | |
918 | 0, 17, 2, 3, 16, 18, 19, 20 | |
919 | }; | |
920 | ||
921 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
922 | ||
71400594 RS |
923 | /* Classifies the kind of instructions we're interested in when |
924 | implementing -mfix-vr4120. */ | |
c67a084a NC |
925 | enum fix_vr4120_class |
926 | { | |
71400594 RS |
927 | FIX_VR4120_MACC, |
928 | FIX_VR4120_DMACC, | |
929 | FIX_VR4120_MULT, | |
930 | FIX_VR4120_DMULT, | |
931 | FIX_VR4120_DIV, | |
932 | FIX_VR4120_MTHILO, | |
933 | NUM_FIX_VR4120_CLASSES | |
934 | }; | |
935 | ||
c67a084a NC |
936 | /* ...likewise -mfix-loongson2f-jump. */ |
937 | static bfd_boolean mips_fix_loongson2f_jump; | |
938 | ||
939 | /* ...likewise -mfix-loongson2f-nop. */ | |
940 | static bfd_boolean mips_fix_loongson2f_nop; | |
941 | ||
942 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
943 | static bfd_boolean mips_fix_loongson2f; | |
944 | ||
71400594 RS |
945 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
946 | there must be at least one other instruction between an instruction | |
947 | of type X and an instruction of type Y. */ | |
948 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
949 | ||
950 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 951 | static int mips_fix_vr4120; |
4a6a3df4 | 952 | |
7d8e00cf RS |
953 | /* ...likewise -mfix-vr4130. */ |
954 | static int mips_fix_vr4130; | |
955 | ||
6a32d874 CM |
956 | /* ...likewise -mfix-24k. */ |
957 | static int mips_fix_24k; | |
958 | ||
a8d14a88 CM |
959 | /* ...likewise -mfix-rm7000 */ |
960 | static int mips_fix_rm7000; | |
961 | ||
d954098f DD |
962 | /* ...likewise -mfix-cn63xxp1 */ |
963 | static bfd_boolean mips_fix_cn63xxp1; | |
964 | ||
27c634e0 FN |
965 | /* ...likewise -mfix-r5900 */ |
966 | static bfd_boolean mips_fix_r5900; | |
967 | static bfd_boolean mips_fix_r5900_explicit; | |
968 | ||
6f2117ba PH |
969 | /* ...likewise -mfix-loongson3-llsc. */ |
970 | static bfd_boolean mips_fix_loongson3_llsc = DEFAULT_MIPS_FIX_LOONGSON3_LLSC; | |
971 | ||
4a6a3df4 AO |
972 | /* We don't relax branches by default, since this causes us to expand |
973 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
974 | fail to compute the offset before expanding the macro to the most | |
975 | efficient expansion. */ | |
976 | ||
977 | static int mips_relax_branch; | |
8b10b0b3 MR |
978 | |
979 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
980 | Needed for broken assembly produced by some GCC versions and some | |
981 | sloppy code out there, where branches to data labels are present. */ | |
982 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 983 | \f |
4d7206a2 RS |
984 | /* The expansion of many macros depends on the type of symbol that |
985 | they refer to. For example, when generating position-dependent code, | |
986 | a macro that refers to a symbol may have two different expansions, | |
987 | one which uses GP-relative addresses and one which uses absolute | |
988 | addresses. When generating SVR4-style PIC, a macro may have | |
989 | different expansions for local and global symbols. | |
990 | ||
991 | We handle these situations by generating both sequences and putting | |
992 | them in variant frags. In position-dependent code, the first sequence | |
993 | will be the GP-relative one and the second sequence will be the | |
994 | absolute one. In SVR4 PIC, the first sequence will be for global | |
995 | symbols and the second will be for local symbols. | |
996 | ||
584892a6 RS |
997 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
998 | SECOND are the lengths of the two sequences in bytes. These fields | |
999 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
1000 | the subtype has the following flags: | |
4d7206a2 | 1001 | |
ce8ad872 MR |
1002 | RELAX_PIC |
1003 | Set if generating PIC code. | |
1004 | ||
584892a6 RS |
1005 | RELAX_USE_SECOND |
1006 | Set if it has been decided that we should use the second | |
1007 | sequence instead of the first. | |
1008 | ||
1009 | RELAX_SECOND_LONGER | |
1010 | Set in the first variant frag if the macro's second implementation | |
1011 | is longer than its first. This refers to the macro as a whole, | |
1012 | not an individual relaxation. | |
1013 | ||
1014 | RELAX_NOMACRO | |
1015 | Set in the first variant frag if the macro appeared in a .set nomacro | |
1016 | block and if one alternative requires a warning but the other does not. | |
1017 | ||
1018 | RELAX_DELAY_SLOT | |
1019 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
1020 | delay slot. | |
4d7206a2 | 1021 | |
df58fc94 RS |
1022 | RELAX_DELAY_SLOT_16BIT |
1023 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
1024 | 16-bit instruction. | |
1025 | ||
1026 | RELAX_DELAY_SLOT_SIZE_FIRST | |
1027 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
1028 | the macro is of the wrong size for the branch delay slot. | |
1029 | ||
1030 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1031 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1032 | the macro is of the wrong size for the branch delay slot. | |
1033 | ||
4d7206a2 RS |
1034 | The frag's "opcode" points to the first fixup for relaxable code. |
1035 | ||
1036 | Relaxable macros are generated using a sequence such as: | |
1037 | ||
1038 | relax_start (SYMBOL); | |
1039 | ... generate first expansion ... | |
1040 | relax_switch (); | |
1041 | ... generate second expansion ... | |
1042 | relax_end (); | |
1043 | ||
1044 | The code and fixups for the unwanted alternative are discarded | |
1045 | by md_convert_frag. */ | |
ce8ad872 MR |
1046 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1047 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1048 | |
584892a6 RS |
1049 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1050 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1051 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1052 | #define RELAX_USE_SECOND 0x20000 | |
1053 | #define RELAX_SECOND_LONGER 0x40000 | |
1054 | #define RELAX_NOMACRO 0x80000 | |
1055 | #define RELAX_DELAY_SLOT 0x100000 | |
1056 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1057 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1058 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1059 | |
4a6a3df4 AO |
1060 | /* Branch without likely bit. If label is out of range, we turn: |
1061 | ||
134c0c8b | 1062 | beq reg1, reg2, label |
4a6a3df4 AO |
1063 | delay slot |
1064 | ||
1065 | into | |
1066 | ||
1067 | bne reg1, reg2, 0f | |
1068 | nop | |
1069 | j label | |
1070 | 0: delay slot | |
1071 | ||
1072 | with the following opcode replacements: | |
1073 | ||
1074 | beq <-> bne | |
1075 | blez <-> bgtz | |
1076 | bltz <-> bgez | |
1077 | bc1f <-> bc1t | |
1078 | ||
1079 | bltzal <-> bgezal (with jal label instead of j label) | |
1080 | ||
1081 | Even though keeping the delay slot instruction in the delay slot of | |
1082 | the branch would be more efficient, it would be very tricky to do | |
1083 | correctly, because we'd have to introduce a variable frag *after* | |
1084 | the delay slot instruction, and expand that instead. Let's do it | |
1085 | the easy way for now, even if the branch-not-taken case now costs | |
1086 | one additional instruction. Out-of-range branches are not supposed | |
1087 | to be common, anyway. | |
1088 | ||
1089 | Branch likely. If label is out of range, we turn: | |
1090 | ||
1091 | beql reg1, reg2, label | |
1092 | delay slot (annulled if branch not taken) | |
1093 | ||
1094 | into | |
1095 | ||
1096 | beql reg1, reg2, 1f | |
1097 | nop | |
1098 | beql $0, $0, 2f | |
1099 | nop | |
1100 | 1: j[al] label | |
1101 | delay slot (executed only if branch taken) | |
1102 | 2: | |
1103 | ||
1104 | It would be possible to generate a shorter sequence by losing the | |
1105 | likely bit, generating something like: | |
b34976b6 | 1106 | |
4a6a3df4 AO |
1107 | bne reg1, reg2, 0f |
1108 | nop | |
1109 | j[al] label | |
1110 | delay slot (executed only if branch taken) | |
1111 | 0: | |
1112 | ||
1113 | beql -> bne | |
1114 | bnel -> beq | |
1115 | blezl -> bgtz | |
1116 | bgtzl -> blez | |
1117 | bltzl -> bgez | |
1118 | bgezl -> bltz | |
1119 | bc1fl -> bc1t | |
1120 | bc1tl -> bc1f | |
1121 | ||
1122 | bltzall -> bgezal (with jal label instead of j label) | |
1123 | bgezall -> bltzal (ditto) | |
1124 | ||
1125 | ||
1126 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1127 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1128 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1129 | ((relax_substateT) \ |
1130 | (0xc0000000 \ | |
1131 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1132 | | ((pic) ? 0x20 : 0) \ |
1133 | | ((toofar) ? 0x40 : 0) \ | |
1134 | | ((link) ? 0x80 : 0) \ | |
1135 | | ((likely) ? 0x100 : 0) \ | |
1136 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1137 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1138 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1139 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1140 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1141 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1142 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1143 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1144 | |
252b5132 RH |
1145 | /* For mips16 code, we use an entirely different form of relaxation. |
1146 | mips16 supports two versions of most instructions which take | |
1147 | immediate values: a small one which takes some small value, and a | |
1148 | larger one which takes a 16 bit value. Since branches also follow | |
1149 | this pattern, relaxing these values is required. | |
1150 | ||
1151 | We can assemble both mips16 and normal MIPS code in a single | |
1152 | object. Therefore, we need to support this type of relaxation at | |
1153 | the same time that we support the relaxation described above. We | |
1154 | use the high bit of the subtype field to distinguish these cases. | |
1155 | ||
1156 | The information we store for this type of relaxation is the | |
1157 | argument code found in the opcode file for this relocation, whether | |
1158 | the user explicitly requested a small or extended form, and whether | |
1159 | the relocation is in a jump or jal delay slot. That tells us the | |
1160 | size of the value, and how it should be stored. We also store | |
1161 | whether the fragment is considered to be extended or not. We also | |
1162 | store whether this is known to be a branch to a different section, | |
1163 | whether we have tried to relax this frag yet, and whether we have | |
1164 | ever extended a PC relative fragment because of a shift count. */ | |
25499ac7 | 1165 | #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ |
8507b6e7 MR |
1166 | small, ext, \ |
1167 | dslot, jal_dslot) \ | |
252b5132 RH |
1168 | (0x80000000 \ |
1169 | | ((type) & 0xff) \ | |
25499ac7 MR |
1170 | | ((e2) ? 0x100 : 0) \ |
1171 | | ((pic) ? 0x200 : 0) \ | |
1172 | | ((sym32) ? 0x400 : 0) \ | |
1173 | | ((nomacro) ? 0x800 : 0) \ | |
1174 | | ((small) ? 0x1000 : 0) \ | |
1175 | | ((ext) ? 0x2000 : 0) \ | |
1176 | | ((dslot) ? 0x4000 : 0) \ | |
1177 | | ((jal_dslot) ? 0x8000 : 0)) | |
8507b6e7 | 1178 | |
4a6a3df4 | 1179 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1180 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
25499ac7 MR |
1181 | #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) |
1182 | #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) | |
1183 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) | |
1184 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) | |
1185 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) | |
1186 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) | |
1187 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) | |
1188 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) | |
1189 | ||
1190 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) | |
1191 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) | |
1192 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) | |
1193 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) | |
1194 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) | |
1195 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) | |
1196 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) | |
1197 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) | |
1198 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) | |
885add95 | 1199 | |
df58fc94 RS |
1200 | /* For microMIPS code, we use relaxation similar to one we use for |
1201 | MIPS16 code. Some instructions that take immediate values support | |
1202 | two encodings: a small one which takes some small value, and a | |
1203 | larger one which takes a 16 bit value. As some branches also follow | |
1204 | this pattern, relaxing these values is required. | |
1205 | ||
1206 | We can assemble both microMIPS and normal MIPS code in a single | |
1207 | object. Therefore, we need to support this type of relaxation at | |
1208 | the same time that we support the relaxation described above. We | |
1209 | use one of the high bits of the subtype field to distinguish these | |
1210 | cases. | |
1211 | ||
1212 | The information we store for this type of relaxation is the argument | |
1213 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1214 | selected as the assembler temporary, whether in the 32-bit |
1215 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1216 | compact, whether there is no delay-slot instruction available to fill |
1217 | in, whether it stores the link address implicitly in $ra, whether | |
1218 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1219 | instructions is enabled, and whether the displacement of a branch is |
1220 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1221 | branch, respectively. */ | |
ce8ad872 | 1222 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1223 | uncond, compact, link, nods, \ |
40209cad MR |
1224 | relax32, toofar16, toofar32) \ |
1225 | (0x40000000 \ | |
1226 | | ((type) & 0xff) \ | |
1227 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1228 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1229 | | ((pic) ? 0x4000 : 0) \ |
1230 | | ((uncond) ? 0x8000 : 0) \ | |
1231 | | ((compact) ? 0x10000 : 0) \ | |
1232 | | ((link) ? 0x20000 : 0) \ | |
1233 | | ((nods) ? 0x40000 : 0) \ | |
1234 | | ((relax32) ? 0x80000 : 0) \ | |
1235 | | ((toofar16) ? 0x100000 : 0) \ | |
1236 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1237 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1238 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1239 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1240 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1241 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1242 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1243 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1244 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1245 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1246 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1247 | ||
1248 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1249 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1250 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1251 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1252 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1253 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1254 | |
43c0598f RS |
1255 | /* Sign-extend 16-bit value X. */ |
1256 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1257 | ||
885add95 CD |
1258 | /* Is the given value a sign-extended 32-bit value? */ |
1259 | #define IS_SEXT_32BIT_NUM(x) \ | |
1260 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1261 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1262 | ||
1263 | /* Is the given value a sign-extended 16-bit value? */ | |
1264 | #define IS_SEXT_16BIT_NUM(x) \ | |
1265 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1266 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1267 | ||
df58fc94 RS |
1268 | /* Is the given value a sign-extended 12-bit value? */ |
1269 | #define IS_SEXT_12BIT_NUM(x) \ | |
1270 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1271 | ||
7f3c4072 CM |
1272 | /* Is the given value a sign-extended 9-bit value? */ |
1273 | #define IS_SEXT_9BIT_NUM(x) \ | |
1274 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1275 | ||
2051e8c4 MR |
1276 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1277 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1278 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1279 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1280 | ||
bf12938e RS |
1281 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1282 | SHIFT places. */ | |
1283 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1284 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1285 | ||
bf12938e | 1286 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1287 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1288 | (!(MICROMIPS) \ | |
1289 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1290 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1291 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1292 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1293 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1294 | MIPS16OP_MASK_##FIELD, \ | |
1295 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1296 | |
1297 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1298 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1299 | \f |
df58fc94 RS |
1300 | /* Whether or not we are emitting a branch-likely macro. */ |
1301 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1302 | ||
4d7206a2 RS |
1303 | /* Global variables used when generating relaxable macros. See the |
1304 | comment above RELAX_ENCODE for more details about how relaxation | |
1305 | is used. */ | |
1306 | static struct { | |
1307 | /* 0 if we're not emitting a relaxable macro. | |
1308 | 1 if we're emitting the first of the two relaxation alternatives. | |
1309 | 2 if we're emitting the second alternative. */ | |
1310 | int sequence; | |
1311 | ||
1312 | /* The first relaxable fixup in the current frag. (In other words, | |
1313 | the first fixup that refers to relaxable code.) */ | |
1314 | fixS *first_fixup; | |
1315 | ||
1316 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1317 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1318 | unsigned int sizes[2]; | |
1319 | ||
1320 | /* The symbol on which the choice of sequence depends. */ | |
1321 | symbolS *symbol; | |
1322 | } mips_relax; | |
252b5132 | 1323 | \f |
584892a6 RS |
1324 | /* Global variables used to decide whether a macro needs a warning. */ |
1325 | static struct { | |
1326 | /* True if the macro is in a branch delay slot. */ | |
1327 | bfd_boolean delay_slot_p; | |
1328 | ||
df58fc94 RS |
1329 | /* Set to the length in bytes required if the macro is in a delay slot |
1330 | that requires a specific length of instruction, otherwise zero. */ | |
1331 | unsigned int delay_slot_length; | |
1332 | ||
584892a6 RS |
1333 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1334 | in bytes and sizes[1] is the length of the second alternative. | |
1335 | For non-relaxable macros, both elements give the length of the | |
1336 | macro in bytes. */ | |
1337 | unsigned int sizes[2]; | |
1338 | ||
df58fc94 RS |
1339 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1340 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1341 | is the length of the first instruction of the second alternative. | |
1342 | For non-relaxable macros, both elements give the length of the first | |
1343 | instruction in bytes. | |
1344 | ||
1345 | Set to zero if we haven't yet seen the first instruction. */ | |
1346 | unsigned int first_insn_sizes[2]; | |
1347 | ||
1348 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1349 | first alternative and insns[1] is the number of instructions for the | |
1350 | second alternative. | |
1351 | ||
1352 | For non-relaxable macros, both elements give the number of | |
1353 | instructions for the macro. */ | |
1354 | unsigned int insns[2]; | |
1355 | ||
584892a6 RS |
1356 | /* The first variant frag for this macro. */ |
1357 | fragS *first_frag; | |
1358 | } mips_macro_warning; | |
1359 | \f | |
252b5132 RH |
1360 | /* Prototypes for static functions. */ |
1361 | ||
252b5132 RH |
1362 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1363 | ||
b34976b6 | 1364 | static void append_insn |
df58fc94 RS |
1365 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1366 | bfd_boolean expansionp); | |
7d10b47d | 1367 | static void mips_no_prev_insn (void); |
c67a084a | 1368 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1369 | static void mips16_macro_build |
03ea81db | 1370 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1371 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1372 | static void macro_start (void); |
1373 | static void macro_end (void); | |
833794fc | 1374 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1375 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1376 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1377 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
25499ac7 | 1378 | static unsigned long mips16_immed_extend (offsetT, unsigned int); |
b34976b6 | 1379 | static void mips16_immed |
3b4dbbbf | 1380 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1381 | unsigned int, unsigned long *); |
5e0116d5 | 1382 | static size_t my_getSmallExpression |
17a2f251 TS |
1383 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1384 | static void my_getExpression (expressionS *, char *); | |
1385 | static void s_align (int); | |
1386 | static void s_change_sec (int); | |
1387 | static void s_change_section (int); | |
1388 | static void s_cons (int); | |
1389 | static void s_float_cons (int); | |
1390 | static void s_mips_globl (int); | |
1391 | static void s_option (int); | |
1392 | static void s_mipsset (int); | |
1393 | static void s_abicalls (int); | |
1394 | static void s_cpload (int); | |
1395 | static void s_cpsetup (int); | |
1396 | static void s_cplocal (int); | |
1397 | static void s_cprestore (int); | |
1398 | static void s_cpreturn (int); | |
741d6ea8 JM |
1399 | static void s_dtprelword (int); |
1400 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1401 | static void s_tprelword (int); |
1402 | static void s_tpreldword (int); | |
17a2f251 TS |
1403 | static void s_gpvalue (int); |
1404 | static void s_gpword (int); | |
1405 | static void s_gpdword (int); | |
a3f278e2 | 1406 | static void s_ehword (int); |
17a2f251 TS |
1407 | static void s_cpadd (int); |
1408 | static void s_insn (int); | |
ba92f887 | 1409 | static void s_nan (int); |
919731af | 1410 | static void s_module (int); |
17a2f251 TS |
1411 | static void s_mips_ent (int); |
1412 | static void s_mips_end (int); | |
1413 | static void s_mips_frame (int); | |
1414 | static void s_mips_mask (int reg_type); | |
1415 | static void s_mips_stab (int); | |
1416 | static void s_mips_weakext (int); | |
1417 | static void s_mips_file (int); | |
1418 | static void s_mips_loc (int); | |
9e009953 | 1419 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1420 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1421 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1422 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1423 | static void file_mips_check_options (void); |
e7af610e NC |
1424 | |
1425 | /* Table and functions used to map between CPU/ISA names, and | |
1426 | ISA levels, and CPU numbers. */ | |
1427 | ||
e972090a NC |
1428 | struct mips_cpu_info |
1429 | { | |
e7af610e | 1430 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1431 | int flags; /* MIPS_CPU_* flags. */ |
1432 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1433 | int isa; /* ISA level. */ |
1434 | int cpu; /* CPU number (default CPU if ISA). */ | |
1435 | }; | |
1436 | ||
ad3fea08 | 1437 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1438 | |
17a2f251 TS |
1439 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1440 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1441 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1442 | \f |
c31f3936 RS |
1443 | /* Command-line options. */ |
1444 | const char *md_shortopts = "O::g::G:"; | |
1445 | ||
1446 | enum options | |
1447 | { | |
1448 | OPTION_MARCH = OPTION_MD_BASE, | |
1449 | OPTION_MTUNE, | |
1450 | OPTION_MIPS1, | |
1451 | OPTION_MIPS2, | |
1452 | OPTION_MIPS3, | |
1453 | OPTION_MIPS4, | |
1454 | OPTION_MIPS5, | |
1455 | OPTION_MIPS32, | |
1456 | OPTION_MIPS64, | |
1457 | OPTION_MIPS32R2, | |
ae52f483 AB |
1458 | OPTION_MIPS32R3, |
1459 | OPTION_MIPS32R5, | |
7361da2c | 1460 | OPTION_MIPS32R6, |
c31f3936 | 1461 | OPTION_MIPS64R2, |
ae52f483 AB |
1462 | OPTION_MIPS64R3, |
1463 | OPTION_MIPS64R5, | |
7361da2c | 1464 | OPTION_MIPS64R6, |
c31f3936 RS |
1465 | OPTION_MIPS16, |
1466 | OPTION_NO_MIPS16, | |
1467 | OPTION_MIPS3D, | |
1468 | OPTION_NO_MIPS3D, | |
1469 | OPTION_MDMX, | |
1470 | OPTION_NO_MDMX, | |
1471 | OPTION_DSP, | |
1472 | OPTION_NO_DSP, | |
1473 | OPTION_MT, | |
1474 | OPTION_NO_MT, | |
1475 | OPTION_VIRT, | |
1476 | OPTION_NO_VIRT, | |
56d438b1 CF |
1477 | OPTION_MSA, |
1478 | OPTION_NO_MSA, | |
c31f3936 RS |
1479 | OPTION_SMARTMIPS, |
1480 | OPTION_NO_SMARTMIPS, | |
1481 | OPTION_DSPR2, | |
1482 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1483 | OPTION_DSPR3, |
1484 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1485 | OPTION_EVA, |
1486 | OPTION_NO_EVA, | |
7d64c587 AB |
1487 | OPTION_XPA, |
1488 | OPTION_NO_XPA, | |
c31f3936 RS |
1489 | OPTION_MICROMIPS, |
1490 | OPTION_NO_MICROMIPS, | |
1491 | OPTION_MCU, | |
1492 | OPTION_NO_MCU, | |
25499ac7 MR |
1493 | OPTION_MIPS16E2, |
1494 | OPTION_NO_MIPS16E2, | |
730c3174 SE |
1495 | OPTION_CRC, |
1496 | OPTION_NO_CRC, | |
c31f3936 RS |
1497 | OPTION_M4650, |
1498 | OPTION_NO_M4650, | |
1499 | OPTION_M4010, | |
1500 | OPTION_NO_M4010, | |
1501 | OPTION_M4100, | |
1502 | OPTION_NO_M4100, | |
1503 | OPTION_M3900, | |
1504 | OPTION_NO_M3900, | |
1505 | OPTION_M7000_HILO_FIX, | |
1506 | OPTION_MNO_7000_HILO_FIX, | |
1507 | OPTION_FIX_24K, | |
1508 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1509 | OPTION_FIX_RM7000, |
1510 | OPTION_NO_FIX_RM7000, | |
6f2117ba PH |
1511 | OPTION_FIX_LOONGSON3_LLSC, |
1512 | OPTION_NO_FIX_LOONGSON3_LLSC, | |
c31f3936 RS |
1513 | OPTION_FIX_LOONGSON2F_JUMP, |
1514 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1515 | OPTION_FIX_LOONGSON2F_NOP, | |
1516 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1517 | OPTION_FIX_VR4120, | |
1518 | OPTION_NO_FIX_VR4120, | |
1519 | OPTION_FIX_VR4130, | |
1520 | OPTION_NO_FIX_VR4130, | |
1521 | OPTION_FIX_CN63XXP1, | |
1522 | OPTION_NO_FIX_CN63XXP1, | |
27c634e0 FN |
1523 | OPTION_FIX_R5900, |
1524 | OPTION_NO_FIX_R5900, | |
c31f3936 RS |
1525 | OPTION_TRAP, |
1526 | OPTION_BREAK, | |
1527 | OPTION_EB, | |
1528 | OPTION_EL, | |
1529 | OPTION_FP32, | |
1530 | OPTION_GP32, | |
1531 | OPTION_CONSTRUCT_FLOATS, | |
1532 | OPTION_NO_CONSTRUCT_FLOATS, | |
1533 | OPTION_FP64, | |
351cdf24 | 1534 | OPTION_FPXX, |
c31f3936 RS |
1535 | OPTION_GP64, |
1536 | OPTION_RELAX_BRANCH, | |
1537 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1538 | OPTION_IGNORE_BRANCH_ISA, |
1539 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1540 | OPTION_INSN32, |
1541 | OPTION_NO_INSN32, | |
c31f3936 RS |
1542 | OPTION_MSHARED, |
1543 | OPTION_MNO_SHARED, | |
1544 | OPTION_MSYM32, | |
1545 | OPTION_MNO_SYM32, | |
1546 | OPTION_SOFT_FLOAT, | |
1547 | OPTION_HARD_FLOAT, | |
1548 | OPTION_SINGLE_FLOAT, | |
1549 | OPTION_DOUBLE_FLOAT, | |
1550 | OPTION_32, | |
c31f3936 RS |
1551 | OPTION_CALL_SHARED, |
1552 | OPTION_CALL_NONPIC, | |
1553 | OPTION_NON_SHARED, | |
1554 | OPTION_XGOT, | |
1555 | OPTION_MABI, | |
1556 | OPTION_N32, | |
1557 | OPTION_64, | |
1558 | OPTION_MDEBUG, | |
1559 | OPTION_NO_MDEBUG, | |
1560 | OPTION_PDR, | |
1561 | OPTION_NO_PDR, | |
1562 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1563 | OPTION_NAN, |
351cdf24 MF |
1564 | OPTION_ODD_SPREG, |
1565 | OPTION_NO_ODD_SPREG, | |
6f20c942 FS |
1566 | OPTION_GINV, |
1567 | OPTION_NO_GINV, | |
8095d2f7 CX |
1568 | OPTION_LOONGSON_MMI, |
1569 | OPTION_NO_LOONGSON_MMI, | |
716c08de CX |
1570 | OPTION_LOONGSON_CAM, |
1571 | OPTION_NO_LOONGSON_CAM, | |
bdc6c06e CX |
1572 | OPTION_LOONGSON_EXT, |
1573 | OPTION_NO_LOONGSON_EXT, | |
a693765e CX |
1574 | OPTION_LOONGSON_EXT2, |
1575 | OPTION_NO_LOONGSON_EXT2, | |
c31f3936 RS |
1576 | OPTION_END_OF_ENUM |
1577 | }; | |
1578 | ||
1579 | struct option md_longopts[] = | |
1580 | { | |
1581 | /* Options which specify architecture. */ | |
1582 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1583 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1584 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1585 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1586 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1587 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1588 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1589 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1590 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1591 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1592 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1593 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1594 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1595 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1596 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1597 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1598 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1599 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1600 | |
1601 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1602 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1603 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1604 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1605 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1606 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1607 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1608 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1609 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1610 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1611 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1612 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1613 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1614 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1615 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1616 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1617 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1618 | {"meva", no_argument, NULL, OPTION_EVA}, |
1619 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1620 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1621 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1622 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1623 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1624 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1625 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1626 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1627 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1628 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1629 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
25499ac7 MR |
1630 | {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, |
1631 | {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, | |
730c3174 SE |
1632 | {"mcrc", no_argument, NULL, OPTION_CRC}, |
1633 | {"mno-crc", no_argument, NULL, OPTION_NO_CRC}, | |
6f20c942 FS |
1634 | {"mginv", no_argument, NULL, OPTION_GINV}, |
1635 | {"mno-ginv", no_argument, NULL, OPTION_NO_GINV}, | |
8095d2f7 CX |
1636 | {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI}, |
1637 | {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI}, | |
716c08de CX |
1638 | {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM}, |
1639 | {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM}, | |
bdc6c06e CX |
1640 | {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT}, |
1641 | {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT}, | |
a693765e CX |
1642 | {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2}, |
1643 | {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2}, | |
c31f3936 RS |
1644 | |
1645 | /* Old-style architecture options. Don't add more of these. */ | |
1646 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1647 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1648 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1649 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1650 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1651 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1652 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1653 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1654 | ||
1655 | /* Options which enable bug fixes. */ | |
1656 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1657 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1658 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
6f2117ba PH |
1659 | {"mfix-loongson3-llsc", no_argument, NULL, OPTION_FIX_LOONGSON3_LLSC}, |
1660 | {"mno-fix-loongson3-llsc", no_argument, NULL, OPTION_NO_FIX_LOONGSON3_LLSC}, | |
c31f3936 RS |
1661 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
1662 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1663 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1664 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1665 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1666 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1667 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1668 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1669 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1670 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1671 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1672 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1673 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1674 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
27c634e0 FN |
1675 | {"mfix-r5900", no_argument, NULL, OPTION_FIX_R5900}, |
1676 | {"mno-fix-r5900", no_argument, NULL, OPTION_NO_FIX_R5900}, | |
c31f3936 RS |
1677 | |
1678 | /* Miscellaneous options. */ | |
1679 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1680 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1681 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1682 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1683 | {"EB", no_argument, NULL, OPTION_EB}, | |
1684 | {"EL", no_argument, NULL, OPTION_EL}, | |
1685 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1686 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1687 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1688 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1689 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1690 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1691 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1692 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1693 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1694 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1695 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1696 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1697 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1698 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1699 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1700 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1701 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1702 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1703 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1704 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1705 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1706 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1707 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1708 | |
1709 | /* Strictly speaking this next option is ELF specific, | |
1710 | but we allow it for other ports as well in order to | |
1711 | make testing easier. */ | |
1712 | {"32", no_argument, NULL, OPTION_32}, | |
1713 | ||
1714 | /* ELF-specific options. */ | |
c31f3936 RS |
1715 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1716 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1717 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1718 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1719 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1720 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1721 | {"n32", no_argument, NULL, OPTION_N32}, | |
1722 | {"64", no_argument, NULL, OPTION_64}, | |
1723 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1724 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1725 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1726 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1727 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1728 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1729 | |
1730 | {NULL, no_argument, NULL, 0} | |
1731 | }; | |
1732 | size_t md_longopts_size = sizeof (md_longopts); | |
1733 | \f | |
c6278170 RS |
1734 | /* Information about either an Application Specific Extension or an |
1735 | optional architecture feature that, for simplicity, we treat in the | |
1736 | same way as an ASE. */ | |
1737 | struct mips_ase | |
1738 | { | |
1739 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1740 | const char *name; | |
1741 | ||
1742 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1743 | and 64-bit architectures, the flags here refer to the subset that | |
1744 | is available on both. */ | |
1745 | unsigned int flags; | |
1746 | ||
1747 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1748 | architectures but that are not included in FLAGS. */ | |
1749 | unsigned int flags64; | |
1750 | ||
1751 | /* The command-line options that turn the ASE on and off. */ | |
1752 | int option_on; | |
1753 | int option_off; | |
1754 | ||
1755 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1756 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1757 | int mips32_rev; | |
1758 | int mips64_rev; | |
1759 | int micromips32_rev; | |
1760 | int micromips64_rev; | |
7361da2c AB |
1761 | |
1762 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1763 | been removed. */ | |
1764 | int rem_rev; | |
c6278170 RS |
1765 | }; |
1766 | ||
1767 | /* A table of all supported ASEs. */ | |
1768 | static const struct mips_ase mips_ases[] = { | |
1769 | { "dsp", ASE_DSP, ASE_DSP64, | |
1770 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1771 | 2, 2, 2, 2, |
1772 | -1 }, | |
c6278170 RS |
1773 | |
1774 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1775 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1776 | 2, 2, 2, 2, |
1777 | -1 }, | |
c6278170 | 1778 | |
8f4f9071 MF |
1779 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1780 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1781 | 6, 6, -1, -1, | |
1782 | -1 }, | |
1783 | ||
c6278170 RS |
1784 | { "eva", ASE_EVA, 0, |
1785 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1786 | 2, 2, 2, 2, |
1787 | -1 }, | |
c6278170 RS |
1788 | |
1789 | { "mcu", ASE_MCU, 0, | |
1790 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1791 | 2, 2, 2, 2, |
1792 | -1 }, | |
c6278170 RS |
1793 | |
1794 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1795 | { "mdmx", ASE_MDMX, 0, | |
1796 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1797 | -1, 1, -1, -1, |
1798 | 6 }, | |
c6278170 RS |
1799 | |
1800 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1801 | { "mips3d", ASE_MIPS3D, 0, | |
1802 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1803 | 2, 1, -1, -1, |
1804 | 6 }, | |
c6278170 RS |
1805 | |
1806 | { "mt", ASE_MT, 0, | |
1807 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1808 | 2, 2, -1, -1, |
1809 | -1 }, | |
c6278170 RS |
1810 | |
1811 | { "smartmips", ASE_SMARTMIPS, 0, | |
1812 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1813 | 1, -1, -1, -1, |
1814 | 6 }, | |
c6278170 RS |
1815 | |
1816 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1817 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1818 | 2, 2, 2, 2, |
1819 | -1 }, | |
56d438b1 CF |
1820 | |
1821 | { "msa", ASE_MSA, ASE_MSA64, | |
1822 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1823 | 2, 2, 2, 2, |
1824 | -1 }, | |
7d64c587 AB |
1825 | |
1826 | { "xpa", ASE_XPA, 0, | |
1827 | OPTION_XPA, OPTION_NO_XPA, | |
909b4e3d | 1828 | 2, 2, 2, 2, |
7361da2c | 1829 | -1 }, |
25499ac7 MR |
1830 | |
1831 | { "mips16e2", ASE_MIPS16E2, 0, | |
1832 | OPTION_MIPS16E2, OPTION_NO_MIPS16E2, | |
1833 | 2, 2, -1, -1, | |
1834 | 6 }, | |
730c3174 SE |
1835 | |
1836 | { "crc", ASE_CRC, ASE_CRC64, | |
1837 | OPTION_CRC, OPTION_NO_CRC, | |
1838 | 6, 6, -1, -1, | |
1839 | -1 }, | |
6f20c942 FS |
1840 | |
1841 | { "ginv", ASE_GINV, 0, | |
1842 | OPTION_GINV, OPTION_NO_GINV, | |
1843 | 6, 6, 6, 6, | |
1844 | -1 }, | |
8095d2f7 CX |
1845 | |
1846 | { "loongson-mmi", ASE_LOONGSON_MMI, 0, | |
1847 | OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI, | |
1848 | 0, 0, -1, -1, | |
1849 | -1 }, | |
716c08de CX |
1850 | |
1851 | { "loongson-cam", ASE_LOONGSON_CAM, 0, | |
1852 | OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM, | |
1853 | 0, 0, -1, -1, | |
1854 | -1 }, | |
bdc6c06e CX |
1855 | |
1856 | { "loongson-ext", ASE_LOONGSON_EXT, 0, | |
1857 | OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT, | |
1858 | 0, 0, -1, -1, | |
1859 | -1 }, | |
a693765e CX |
1860 | |
1861 | { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0, | |
1862 | OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2, | |
1863 | 0, 0, -1, -1, | |
1864 | -1 }, | |
c6278170 RS |
1865 | }; |
1866 | ||
1867 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1868 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1869 | |
1870 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1871 | static const unsigned int mips_ase_groups[] = { | |
a693765e CX |
1872 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3, |
1873 | ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2 | |
c6278170 RS |
1874 | }; |
1875 | \f | |
252b5132 RH |
1876 | /* Pseudo-op table. |
1877 | ||
1878 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1879 | should be defined here, but are currently unsupported: .alias, | |
1880 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1881 | ||
1882 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1883 | specific to the type of debugging information being generated, and | |
1884 | should be defined by the object format: .aent, .begin, .bend, | |
1885 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1886 | .vreg. | |
1887 | ||
1888 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1889 | not MIPS CPU specific, but are also not specific to the object file | |
1890 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1891 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1892 | |
e972090a NC |
1893 | static const pseudo_typeS mips_pseudo_table[] = |
1894 | { | |
beae10d5 | 1895 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1896 | {"option", s_option, 0}, |
1897 | {"set", s_mipsset, 0}, | |
1898 | {"rdata", s_change_sec, 'r'}, | |
1899 | {"sdata", s_change_sec, 's'}, | |
1900 | {"livereg", s_ignore, 0}, | |
1901 | {"abicalls", s_abicalls, 0}, | |
1902 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1903 | {"cpsetup", s_cpsetup, 0}, |
1904 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1905 | {"cprestore", s_cprestore, 0}, |
6478892d | 1906 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1907 | {"dtprelword", s_dtprelword, 0}, |
1908 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1909 | {"tprelword", s_tprelword, 0}, |
1910 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1911 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1912 | {"gpword", s_gpword, 0}, |
10181a0d | 1913 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1914 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1915 | {"cpadd", s_cpadd, 0}, |
1916 | {"insn", s_insn, 0}, | |
ba92f887 | 1917 | {"nan", s_nan, 0}, |
919731af | 1918 | {"module", s_module, 0}, |
252b5132 | 1919 | |
beae10d5 | 1920 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1921 | chips. */ |
38a57ae7 | 1922 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1923 | {"bss", s_change_sec, 'b'}, |
1924 | {"err", s_err, 0}, | |
1925 | {"half", s_cons, 1}, | |
1926 | {"dword", s_cons, 3}, | |
1927 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1928 | {"origin", s_org, 0}, |
1929 | {"repeat", s_rept, 0}, | |
252b5132 | 1930 | |
998b3c36 MR |
1931 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1932 | {"sbss", s_change_sec, 'B'}, | |
1933 | ||
beae10d5 | 1934 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1935 | here for one reason or another. */ |
1936 | {"align", s_align, 0}, | |
1937 | {"byte", s_cons, 0}, | |
1938 | {"data", s_change_sec, 'd'}, | |
1939 | {"double", s_float_cons, 'd'}, | |
1940 | {"float", s_float_cons, 'f'}, | |
1941 | {"globl", s_mips_globl, 0}, | |
1942 | {"global", s_mips_globl, 0}, | |
1943 | {"hword", s_cons, 1}, | |
1944 | {"int", s_cons, 2}, | |
1945 | {"long", s_cons, 2}, | |
1946 | {"octa", s_cons, 4}, | |
1947 | {"quad", s_cons, 3}, | |
cca86cc8 | 1948 | {"section", s_change_section, 0}, |
252b5132 RH |
1949 | {"short", s_cons, 1}, |
1950 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1951 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1952 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1953 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1954 | {"text", s_change_sec, 't'}, |
1955 | {"word", s_cons, 2}, | |
add56521 | 1956 | |
add56521 | 1957 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1958 | |
43841e91 | 1959 | { NULL, NULL, 0 }, |
252b5132 RH |
1960 | }; |
1961 | ||
e972090a NC |
1962 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1963 | { | |
beae10d5 KH |
1964 | /* These pseudo-ops should be defined by the object file format. |
1965 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1966 | {"aent", s_mips_ent, 1}, |
1967 | {"bgnb", s_ignore, 0}, | |
1968 | {"end", s_mips_end, 0}, | |
1969 | {"endb", s_ignore, 0}, | |
1970 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1971 | {"file", s_mips_file, 0}, |
252b5132 RH |
1972 | {"fmask", s_mips_mask, 'F'}, |
1973 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1974 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1975 | {"mask", s_mips_mask, 'R'}, |
1976 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1977 | { NULL, NULL, 0 }, |
252b5132 RH |
1978 | }; |
1979 | ||
3ae8dd8d MR |
1980 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1981 | purpose of the `.dc.a' internal pseudo-op. */ | |
1982 | ||
1983 | int | |
1984 | mips_address_bytes (void) | |
1985 | { | |
919731af | 1986 | file_mips_check_options (); |
3ae8dd8d MR |
1987 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1988 | } | |
1989 | ||
17a2f251 | 1990 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1991 | |
1992 | void | |
17a2f251 | 1993 | mips_pop_insert (void) |
252b5132 RH |
1994 | { |
1995 | pop_insert (mips_pseudo_table); | |
1996 | if (! ECOFF_DEBUGGING) | |
1997 | pop_insert (mips_nonecoff_pseudo_table); | |
1998 | } | |
1999 | \f | |
2000 | /* Symbols labelling the current insn. */ | |
2001 | ||
e972090a NC |
2002 | struct insn_label_list |
2003 | { | |
252b5132 RH |
2004 | struct insn_label_list *next; |
2005 | symbolS *label; | |
2006 | }; | |
2007 | ||
252b5132 | 2008 | static struct insn_label_list *free_insn_labels; |
742a56fe | 2009 | #define label_list tc_segment_info_data.labels |
252b5132 | 2010 | |
17a2f251 | 2011 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
2012 | static void mips_mark_labels (void); |
2013 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
2014 | |
2015 | static inline void | |
17a2f251 | 2016 | mips_clear_insn_labels (void) |
252b5132 | 2017 | { |
ed9e98c2 | 2018 | struct insn_label_list **pl; |
a8dbcb85 | 2019 | segment_info_type *si; |
252b5132 | 2020 | |
a8dbcb85 TS |
2021 | if (now_seg) |
2022 | { | |
2023 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
2024 | ; | |
3739860c | 2025 | |
a8dbcb85 TS |
2026 | si = seg_info (now_seg); |
2027 | *pl = si->label_list; | |
2028 | si->label_list = NULL; | |
2029 | } | |
252b5132 | 2030 | } |
a8dbcb85 | 2031 | |
df58fc94 RS |
2032 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
2033 | ||
2034 | static inline void | |
2035 | mips_mark_labels (void) | |
2036 | { | |
2037 | if (HAVE_CODE_COMPRESSION) | |
2038 | mips_compressed_mark_labels (); | |
2039 | } | |
252b5132 RH |
2040 | \f |
2041 | static char *expr_end; | |
2042 | ||
e423441d | 2043 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 2044 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
2045 | |
2046 | static expressionS imm_expr; | |
252b5132 | 2047 | |
77bd4346 RS |
2048 | /* The relocatable field in an instruction and the relocs associated |
2049 | with it. These variables are used for instructions like LUI and | |
2050 | JAL as well as true offsets. They are also used for address | |
2051 | operands in macros. */ | |
252b5132 | 2052 | |
77bd4346 | 2053 | static expressionS offset_expr; |
f6688943 TS |
2054 | static bfd_reloc_code_real_type offset_reloc[3] |
2055 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 2056 | |
df58fc94 RS |
2057 | /* This is set to the resulting size of the instruction to be produced |
2058 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
2059 | explicit size is supplied. */ | |
252b5132 | 2060 | |
df58fc94 | 2061 | static unsigned int forced_insn_length; |
252b5132 | 2062 | |
e1b47bd5 RS |
2063 | /* True if we are assembling an instruction. All dot symbols defined during |
2064 | this time should be treated as code labels. */ | |
2065 | ||
2066 | static bfd_boolean mips_assembling_insn; | |
2067 | ||
ecb4347a DJ |
2068 | /* The pdr segment for per procedure frame/regmask info. Not used for |
2069 | ECOFF debugging. */ | |
252b5132 RH |
2070 | |
2071 | static segT pdr_seg; | |
252b5132 | 2072 | |
e013f690 TS |
2073 | /* The default target format to use. */ |
2074 | ||
aeffff67 RS |
2075 | #if defined (TE_FreeBSD) |
2076 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
2077 | #elif defined (TE_TMIPS) | |
2078 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
2079 | #else | |
2080 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
2081 | #endif | |
2082 | ||
e013f690 | 2083 | const char * |
17a2f251 | 2084 | mips_target_format (void) |
e013f690 TS |
2085 | { |
2086 | switch (OUTPUT_FLAVOR) | |
2087 | { | |
e013f690 | 2088 | case bfd_target_elf_flavour: |
0a44bf69 RS |
2089 | #ifdef TE_VXWORKS |
2090 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
2091 | return (target_big_endian | |
2092 | ? "elf32-bigmips-vxworks" | |
2093 | : "elf32-littlemips-vxworks"); | |
2094 | #endif | |
e013f690 | 2095 | return (target_big_endian |
cfe86eaa | 2096 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 2097 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 2098 | : (HAVE_NEWABI |
aeffff67 RS |
2099 | ? ELF_TARGET ("elf32-n", "big") |
2100 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 2101 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 2102 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 2103 | : (HAVE_NEWABI |
aeffff67 RS |
2104 | ? ELF_TARGET ("elf32-n", "little") |
2105 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2106 | default: |
2107 | abort (); | |
2108 | return NULL; | |
2109 | } | |
2110 | } | |
2111 | ||
c6278170 RS |
2112 | /* Return the ISA revision that is currently in use, or 0 if we are |
2113 | generating code for MIPS V or below. */ | |
2114 | ||
2115 | static int | |
2116 | mips_isa_rev (void) | |
2117 | { | |
2118 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2119 | return 2; | |
2120 | ||
ae52f483 AB |
2121 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2122 | return 3; | |
2123 | ||
2124 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2125 | return 5; | |
2126 | ||
7361da2c AB |
2127 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2128 | return 6; | |
2129 | ||
c6278170 RS |
2130 | /* microMIPS implies revision 2 or above. */ |
2131 | if (mips_opts.micromips) | |
2132 | return 2; | |
2133 | ||
2134 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2135 | return 1; | |
2136 | ||
2137 | return 0; | |
2138 | } | |
2139 | ||
2140 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2141 | ||
2142 | static unsigned int | |
2143 | mips_ase_mask (unsigned int flags) | |
2144 | { | |
2145 | unsigned int i; | |
2146 | ||
2147 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2148 | if (flags & mips_ase_groups[i]) | |
2149 | flags |= mips_ase_groups[i]; | |
2150 | return flags; | |
2151 | } | |
2152 | ||
2153 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2154 | appropriate. */ | |
2155 | ||
2156 | static void | |
2157 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2158 | { | |
2159 | const char *base; | |
2160 | int min_rev, size; | |
2161 | static unsigned int warned_isa; | |
2162 | static unsigned int warned_fp32; | |
2163 | ||
2164 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2165 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2166 | else | |
2167 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2168 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2169 | && (warned_isa & ase->flags) != ase->flags) | |
2170 | { | |
2171 | warned_isa |= ase->flags; | |
2172 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2173 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2174 | if (min_rev < 0) | |
1661c76c | 2175 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2176 | " `%s' extension"), size, base, ase->name); |
2177 | else | |
1661c76c | 2178 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2179 | ase->name, base, size, min_rev); |
2180 | } | |
7361da2c AB |
2181 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2182 | && (warned_isa & ase->flags) != ase->flags) | |
2183 | { | |
2184 | warned_isa |= ase->flags; | |
2185 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2186 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2187 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2188 | ase->name, base, size, ase->rem_rev); | |
2189 | } | |
2190 | ||
c6278170 | 2191 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2192 | && mips_opts.fp != 64 |
c6278170 RS |
2193 | && (warned_fp32 & ase->flags) != ase->flags) |
2194 | { | |
2195 | warned_fp32 |= ase->flags; | |
1661c76c | 2196 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2197 | } |
2198 | } | |
2199 | ||
2200 | /* Check all enabled ASEs to see whether they are supported by the | |
2201 | chosen architecture. */ | |
2202 | ||
2203 | static void | |
2204 | mips_check_isa_supports_ases (void) | |
2205 | { | |
2206 | unsigned int i, mask; | |
2207 | ||
2208 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2209 | { | |
2210 | mask = mips_ase_mask (mips_ases[i].flags); | |
2211 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2212 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2217 | that were affected. */ | |
2218 | ||
2219 | static unsigned int | |
919731af | 2220 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2221 | bfd_boolean enabled_p) | |
c6278170 RS |
2222 | { |
2223 | unsigned int mask; | |
2224 | ||
2225 | mask = mips_ase_mask (ase->flags); | |
919731af | 2226 | opts->ase &= ~mask; |
92cebb3d MR |
2227 | |
2228 | /* Clear combination ASE flags, which need to be recalculated based on | |
2229 | updated regular ASE settings. */ | |
41cee089 | 2230 | opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6); |
92cebb3d | 2231 | |
c6278170 | 2232 | if (enabled_p) |
919731af | 2233 | opts->ase |= ase->flags; |
25499ac7 | 2234 | |
9785fc2a MR |
2235 | /* The Virtualization ASE has eXtended Physical Addressing (XPA) |
2236 | instructions which are only valid when both ASEs are enabled. | |
2237 | This sets the ASE_XPA_VIRT flag when both ASEs are present. */ | |
2238 | if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) | |
2239 | { | |
2240 | opts->ase |= ASE_XPA_VIRT; | |
2241 | mask |= ASE_XPA_VIRT; | |
2242 | } | |
25499ac7 MR |
2243 | if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) |
2244 | { | |
2245 | opts->ase |= ASE_MIPS16E2_MT; | |
2246 | mask |= ASE_MIPS16E2_MT; | |
2247 | } | |
2248 | ||
41cee089 FS |
2249 | /* The EVA Extension has instructions which are only valid when the R6 ISA |
2250 | is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are | |
2251 | present. */ | |
2252 | if (((opts->ase & ASE_EVA) != 0) && ISA_IS_R6 (opts->isa)) | |
2253 | { | |
2254 | opts->ase |= ASE_EVA_R6; | |
2255 | mask |= ASE_EVA_R6; | |
2256 | } | |
2257 | ||
c6278170 RS |
2258 | return mask; |
2259 | } | |
2260 | ||
2261 | /* Return the ASE called NAME, or null if none. */ | |
2262 | ||
2263 | static const struct mips_ase * | |
2264 | mips_lookup_ase (const char *name) | |
2265 | { | |
2266 | unsigned int i; | |
2267 | ||
2268 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2269 | if (strcmp (name, mips_ases[i].name) == 0) | |
2270 | return &mips_ases[i]; | |
2271 | return NULL; | |
2272 | } | |
2273 | ||
df58fc94 | 2274 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2275 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2276 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2277 | |
2278 | static inline unsigned int | |
2279 | micromips_insn_length (const struct mips_opcode *mo) | |
2280 | { | |
7fd53920 | 2281 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2282 | } |
2283 | ||
5c04167a RS |
2284 | /* Return the length of MIPS16 instruction OPCODE. */ |
2285 | ||
2286 | static inline unsigned int | |
2287 | mips16_opcode_length (unsigned long opcode) | |
2288 | { | |
2289 | return (opcode >> 16) == 0 ? 2 : 4; | |
2290 | } | |
2291 | ||
1e915849 RS |
2292 | /* Return the length of instruction INSN. */ |
2293 | ||
2294 | static inline unsigned int | |
2295 | insn_length (const struct mips_cl_insn *insn) | |
2296 | { | |
df58fc94 RS |
2297 | if (mips_opts.micromips) |
2298 | return micromips_insn_length (insn->insn_mo); | |
2299 | else if (mips_opts.mips16) | |
5c04167a | 2300 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2301 | else |
1e915849 | 2302 | return 4; |
1e915849 RS |
2303 | } |
2304 | ||
2305 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2306 | ||
2307 | static void | |
2308 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2309 | { | |
2310 | size_t i; | |
2311 | ||
2312 | insn->insn_mo = mo; | |
1e915849 RS |
2313 | insn->insn_opcode = mo->match; |
2314 | insn->frag = NULL; | |
2315 | insn->where = 0; | |
2316 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2317 | insn->fixp[i] = NULL; | |
2318 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2319 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2320 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2321 | insn->complete_p = 0; |
e407c74b | 2322 | insn->cleared_p = 0; |
1e915849 RS |
2323 | } |
2324 | ||
fc76e730 RS |
2325 | /* Get a list of all the operands in INSN. */ |
2326 | ||
2327 | static const struct mips_operand_array * | |
2328 | insn_operands (const struct mips_cl_insn *insn) | |
2329 | { | |
2330 | if (insn->insn_mo >= &mips_opcodes[0] | |
2331 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2332 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2333 | ||
2334 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2335 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2336 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2337 | ||
2338 | if (insn->insn_mo >= µmips_opcodes[0] | |
2339 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2340 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2341 | ||
2342 | abort (); | |
2343 | } | |
2344 | ||
2345 | /* Get a description of operand OPNO of INSN. */ | |
2346 | ||
2347 | static const struct mips_operand * | |
2348 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2349 | { | |
2350 | const struct mips_operand_array *operands; | |
2351 | ||
2352 | operands = insn_operands (insn); | |
2353 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2354 | abort (); | |
2355 | return operands->operand[opno]; | |
2356 | } | |
2357 | ||
e077a1c8 RS |
2358 | /* Install UVAL as the value of OPERAND in INSN. */ |
2359 | ||
2360 | static inline void | |
2361 | insn_insert_operand (struct mips_cl_insn *insn, | |
2362 | const struct mips_operand *operand, unsigned int uval) | |
2363 | { | |
25499ac7 MR |
2364 | if (mips_opts.mips16 |
2365 | && operand->type == OP_INT && operand->lsb == 0 | |
2366 | && mips_opcode_32bit_p (insn->insn_mo)) | |
2367 | insn->insn_opcode |= mips16_immed_extend (uval, operand->size); | |
2368 | else | |
2369 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
e077a1c8 RS |
2370 | } |
2371 | ||
fc76e730 RS |
2372 | /* Extract the value of OPERAND from INSN. */ |
2373 | ||
2374 | static inline unsigned | |
2375 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2376 | const struct mips_operand *operand) | |
2377 | { | |
2378 | return mips_extract_operand (operand, insn->insn_opcode); | |
2379 | } | |
2380 | ||
df58fc94 | 2381 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2382 | |
2383 | static void | |
df58fc94 | 2384 | mips_record_compressed_mode (void) |
742a56fe RS |
2385 | { |
2386 | segment_info_type *si; | |
2387 | ||
2388 | si = seg_info (now_seg); | |
2389 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2390 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2391 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2392 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2393 | } |
2394 | ||
4d68580a RS |
2395 | /* Read a standard MIPS instruction from BUF. */ |
2396 | ||
2397 | static unsigned long | |
2398 | read_insn (char *buf) | |
2399 | { | |
2400 | if (target_big_endian) | |
2401 | return bfd_getb32 ((bfd_byte *) buf); | |
2402 | else | |
2403 | return bfd_getl32 ((bfd_byte *) buf); | |
2404 | } | |
2405 | ||
2406 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2407 | the next byte. */ | |
2408 | ||
2409 | static char * | |
2410 | write_insn (char *buf, unsigned int insn) | |
2411 | { | |
2412 | md_number_to_chars (buf, insn, 4); | |
2413 | return buf + 4; | |
2414 | } | |
2415 | ||
2416 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2417 | has length LENGTH. */ | |
2418 | ||
2419 | static unsigned long | |
2420 | read_compressed_insn (char *buf, unsigned int length) | |
2421 | { | |
2422 | unsigned long insn; | |
2423 | unsigned int i; | |
2424 | ||
2425 | insn = 0; | |
2426 | for (i = 0; i < length; i += 2) | |
2427 | { | |
2428 | insn <<= 16; | |
2429 | if (target_big_endian) | |
2430 | insn |= bfd_getb16 ((char *) buf); | |
2431 | else | |
2432 | insn |= bfd_getl16 ((char *) buf); | |
2433 | buf += 2; | |
2434 | } | |
2435 | return insn; | |
2436 | } | |
2437 | ||
5c04167a RS |
2438 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2439 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2440 | ||
2441 | static char * | |
2442 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2443 | { | |
2444 | unsigned int i; | |
2445 | ||
2446 | for (i = 0; i < length; i += 2) | |
2447 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2448 | return buf + length; | |
2449 | } | |
2450 | ||
1e915849 RS |
2451 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2452 | ||
2453 | static void | |
2454 | install_insn (const struct mips_cl_insn *insn) | |
2455 | { | |
2456 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2457 | if (HAVE_CODE_COMPRESSION) |
2458 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2459 | else |
4d68580a | 2460 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2461 | mips_record_compressed_mode (); |
1e915849 RS |
2462 | } |
2463 | ||
2464 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2465 | and install the opcode in the new location. */ | |
2466 | ||
2467 | static void | |
2468 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2469 | { | |
2470 | size_t i; | |
2471 | ||
2472 | insn->frag = frag; | |
2473 | insn->where = where; | |
2474 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2475 | if (insn->fixp[i] != NULL) | |
2476 | { | |
2477 | insn->fixp[i]->fx_frag = frag; | |
2478 | insn->fixp[i]->fx_where = where; | |
2479 | } | |
2480 | install_insn (insn); | |
2481 | } | |
2482 | ||
2483 | /* Add INSN to the end of the output. */ | |
2484 | ||
2485 | static void | |
2486 | add_fixed_insn (struct mips_cl_insn *insn) | |
2487 | { | |
2488 | char *f = frag_more (insn_length (insn)); | |
2489 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2490 | } | |
2491 | ||
2492 | /* Start a variant frag and move INSN to the start of the variant part, | |
2493 | marking it as fixed. The other arguments are as for frag_var. */ | |
2494 | ||
2495 | static void | |
2496 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2497 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2498 | { | |
2499 | frag_grow (max_chars); | |
2500 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2501 | insn->fixed_p = 1; | |
2502 | frag_var (rs_machine_dependent, max_chars, var, | |
2503 | subtype, symbol, offset, NULL); | |
2504 | } | |
2505 | ||
2506 | /* Insert N copies of INSN into the history buffer, starting at | |
2507 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2508 | ||
2509 | static void | |
2510 | insert_into_history (unsigned int first, unsigned int n, | |
2511 | const struct mips_cl_insn *insn) | |
2512 | { | |
2513 | if (mips_relax.sequence != 2) | |
2514 | { | |
2515 | unsigned int i; | |
2516 | ||
2517 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2518 | if (i >= first + n) | |
2519 | history[i] = history[i - n]; | |
2520 | else | |
2521 | history[i] = *insn; | |
2522 | } | |
2523 | } | |
2524 | ||
e3de51ce RS |
2525 | /* Clear the error in insn_error. */ |
2526 | ||
2527 | static void | |
2528 | clear_insn_error (void) | |
2529 | { | |
2530 | memset (&insn_error, 0, sizeof (insn_error)); | |
2531 | } | |
2532 | ||
2533 | /* Possibly record error message MSG for the current instruction. | |
2534 | If the error is about a particular argument, ARGNUM is the 1-based | |
2535 | number of that argument, otherwise it is 0. FORMAT is the format | |
2536 | of MSG. Return true if MSG was used, false if the current message | |
2537 | was kept. */ | |
2538 | ||
2539 | static bfd_boolean | |
2540 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2541 | const char *msg) | |
2542 | { | |
2543 | if (argnum == 0) | |
2544 | { | |
2545 | /* Give priority to errors against specific arguments, and to | |
2546 | the first whole-instruction message. */ | |
2547 | if (insn_error.msg) | |
2548 | return FALSE; | |
2549 | } | |
2550 | else | |
2551 | { | |
2552 | /* Keep insn_error if it is against a later argument. */ | |
2553 | if (argnum < insn_error.min_argnum) | |
2554 | return FALSE; | |
2555 | ||
2556 | /* If both errors are against the same argument but are different, | |
2557 | give up on reporting a specific error for this argument. | |
2558 | See the comment about mips_insn_error for details. */ | |
2559 | if (argnum == insn_error.min_argnum | |
2560 | && insn_error.msg | |
2561 | && strcmp (insn_error.msg, msg) != 0) | |
2562 | { | |
2563 | insn_error.msg = 0; | |
2564 | insn_error.min_argnum += 1; | |
2565 | return FALSE; | |
2566 | } | |
2567 | } | |
2568 | insn_error.min_argnum = argnum; | |
2569 | insn_error.format = format; | |
2570 | insn_error.msg = msg; | |
2571 | return TRUE; | |
2572 | } | |
2573 | ||
2574 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2575 | as for set_insn_error_format. */ | |
2576 | ||
2577 | static void | |
2578 | set_insn_error (int argnum, const char *msg) | |
2579 | { | |
2580 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2581 | } | |
2582 | ||
2583 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2584 | as for set_insn_error_format. */ | |
2585 | ||
2586 | static void | |
2587 | set_insn_error_i (int argnum, const char *msg, int i) | |
2588 | { | |
2589 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2590 | insn_error.u.i = i; | |
2591 | } | |
2592 | ||
2593 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2594 | are as for set_insn_error_format. */ | |
2595 | ||
2596 | static void | |
2597 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2598 | { | |
2599 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2600 | { | |
2601 | insn_error.u.ss[0] = s1; | |
2602 | insn_error.u.ss[1] = s2; | |
2603 | } | |
2604 | } | |
2605 | ||
2606 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2607 | ||
2608 | static void | |
2609 | report_insn_error (const char *str) | |
2610 | { | |
e1fa0163 | 2611 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2612 | |
e3de51ce RS |
2613 | switch (insn_error.format) |
2614 | { | |
2615 | case ERR_FMT_PLAIN: | |
2616 | as_bad (msg, str); | |
2617 | break; | |
2618 | ||
2619 | case ERR_FMT_I: | |
2620 | as_bad (msg, insn_error.u.i, str); | |
2621 | break; | |
2622 | ||
2623 | case ERR_FMT_SS: | |
2624 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2625 | break; | |
2626 | } | |
e1fa0163 NC |
2627 | |
2628 | free ((char *) msg); | |
e3de51ce RS |
2629 | } |
2630 | ||
71400594 RS |
2631 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2632 | the idea is to make it obvious at a glance that each errata is | |
2633 | included. */ | |
2634 | ||
2635 | static void | |
2636 | init_vr4120_conflicts (void) | |
2637 | { | |
2638 | #define CONFLICT(FIRST, SECOND) \ | |
2639 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2640 | ||
2641 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2642 | CONFLICT (MACC, DIV); | |
2643 | CONFLICT (DMACC, DIV); | |
2644 | ||
2645 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2646 | CONFLICT (DMULT, DMULT); | |
2647 | CONFLICT (DMULT, DMACC); | |
2648 | CONFLICT (DMACC, DMULT); | |
2649 | CONFLICT (DMACC, DMACC); | |
2650 | ||
2651 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2652 | CONFLICT (MACC, MTHILO); | |
2653 | CONFLICT (DMACC, MTHILO); | |
2654 | ||
2655 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2656 | instruction is executed immediately after a MACC or DMACC | |
2657 | instruction, the result of [either instruction] is incorrect." */ | |
2658 | CONFLICT (MACC, MULT); | |
2659 | CONFLICT (MACC, DMULT); | |
2660 | CONFLICT (DMACC, MULT); | |
2661 | CONFLICT (DMACC, DMULT); | |
2662 | ||
2663 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2664 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2665 | DDIV or DDIVU instruction, the result of the MACC or | |
2666 | DMACC instruction is incorrect.". */ | |
2667 | CONFLICT (DMULT, MACC); | |
2668 | CONFLICT (DMULT, DMACC); | |
2669 | CONFLICT (DIV, MACC); | |
2670 | CONFLICT (DIV, DMACC); | |
2671 | ||
2672 | #undef CONFLICT | |
2673 | } | |
2674 | ||
707bfff6 TS |
2675 | struct regname { |
2676 | const char *name; | |
2677 | unsigned int num; | |
2678 | }; | |
2679 | ||
14daeee3 | 2680 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2681 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2682 | #define RTYPE_NUM 0x0000100 |
2683 | #define RTYPE_FPU 0x0000200 | |
2684 | #define RTYPE_FCC 0x0000400 | |
2685 | #define RTYPE_VEC 0x0000800 | |
2686 | #define RTYPE_GP 0x0001000 | |
2687 | #define RTYPE_CP0 0x0002000 | |
2688 | #define RTYPE_PC 0x0004000 | |
2689 | #define RTYPE_ACC 0x0008000 | |
2690 | #define RTYPE_CCC 0x0010000 | |
2691 | #define RTYPE_VI 0x0020000 | |
2692 | #define RTYPE_VF 0x0040000 | |
2693 | #define RTYPE_R5900_I 0x0080000 | |
2694 | #define RTYPE_R5900_Q 0x0100000 | |
2695 | #define RTYPE_R5900_R 0x0200000 | |
2696 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2697 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2698 | #define RWARN 0x8000000 |
707bfff6 TS |
2699 | |
2700 | #define GENERIC_REGISTER_NUMBERS \ | |
2701 | {"$0", RTYPE_NUM | 0}, \ | |
2702 | {"$1", RTYPE_NUM | 1}, \ | |
2703 | {"$2", RTYPE_NUM | 2}, \ | |
2704 | {"$3", RTYPE_NUM | 3}, \ | |
2705 | {"$4", RTYPE_NUM | 4}, \ | |
2706 | {"$5", RTYPE_NUM | 5}, \ | |
2707 | {"$6", RTYPE_NUM | 6}, \ | |
2708 | {"$7", RTYPE_NUM | 7}, \ | |
2709 | {"$8", RTYPE_NUM | 8}, \ | |
2710 | {"$9", RTYPE_NUM | 9}, \ | |
2711 | {"$10", RTYPE_NUM | 10}, \ | |
2712 | {"$11", RTYPE_NUM | 11}, \ | |
2713 | {"$12", RTYPE_NUM | 12}, \ | |
2714 | {"$13", RTYPE_NUM | 13}, \ | |
2715 | {"$14", RTYPE_NUM | 14}, \ | |
2716 | {"$15", RTYPE_NUM | 15}, \ | |
2717 | {"$16", RTYPE_NUM | 16}, \ | |
2718 | {"$17", RTYPE_NUM | 17}, \ | |
2719 | {"$18", RTYPE_NUM | 18}, \ | |
2720 | {"$19", RTYPE_NUM | 19}, \ | |
2721 | {"$20", RTYPE_NUM | 20}, \ | |
2722 | {"$21", RTYPE_NUM | 21}, \ | |
2723 | {"$22", RTYPE_NUM | 22}, \ | |
2724 | {"$23", RTYPE_NUM | 23}, \ | |
2725 | {"$24", RTYPE_NUM | 24}, \ | |
2726 | {"$25", RTYPE_NUM | 25}, \ | |
2727 | {"$26", RTYPE_NUM | 26}, \ | |
2728 | {"$27", RTYPE_NUM | 27}, \ | |
2729 | {"$28", RTYPE_NUM | 28}, \ | |
2730 | {"$29", RTYPE_NUM | 29}, \ | |
2731 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2732 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2733 | |
2734 | #define FPU_REGISTER_NAMES \ | |
2735 | {"$f0", RTYPE_FPU | 0}, \ | |
2736 | {"$f1", RTYPE_FPU | 1}, \ | |
2737 | {"$f2", RTYPE_FPU | 2}, \ | |
2738 | {"$f3", RTYPE_FPU | 3}, \ | |
2739 | {"$f4", RTYPE_FPU | 4}, \ | |
2740 | {"$f5", RTYPE_FPU | 5}, \ | |
2741 | {"$f6", RTYPE_FPU | 6}, \ | |
2742 | {"$f7", RTYPE_FPU | 7}, \ | |
2743 | {"$f8", RTYPE_FPU | 8}, \ | |
2744 | {"$f9", RTYPE_FPU | 9}, \ | |
2745 | {"$f10", RTYPE_FPU | 10}, \ | |
2746 | {"$f11", RTYPE_FPU | 11}, \ | |
2747 | {"$f12", RTYPE_FPU | 12}, \ | |
2748 | {"$f13", RTYPE_FPU | 13}, \ | |
2749 | {"$f14", RTYPE_FPU | 14}, \ | |
2750 | {"$f15", RTYPE_FPU | 15}, \ | |
2751 | {"$f16", RTYPE_FPU | 16}, \ | |
2752 | {"$f17", RTYPE_FPU | 17}, \ | |
2753 | {"$f18", RTYPE_FPU | 18}, \ | |
2754 | {"$f19", RTYPE_FPU | 19}, \ | |
2755 | {"$f20", RTYPE_FPU | 20}, \ | |
2756 | {"$f21", RTYPE_FPU | 21}, \ | |
2757 | {"$f22", RTYPE_FPU | 22}, \ | |
2758 | {"$f23", RTYPE_FPU | 23}, \ | |
2759 | {"$f24", RTYPE_FPU | 24}, \ | |
2760 | {"$f25", RTYPE_FPU | 25}, \ | |
2761 | {"$f26", RTYPE_FPU | 26}, \ | |
2762 | {"$f27", RTYPE_FPU | 27}, \ | |
2763 | {"$f28", RTYPE_FPU | 28}, \ | |
2764 | {"$f29", RTYPE_FPU | 29}, \ | |
2765 | {"$f30", RTYPE_FPU | 30}, \ | |
2766 | {"$f31", RTYPE_FPU | 31} | |
2767 | ||
2768 | #define FPU_CONDITION_CODE_NAMES \ | |
2769 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2770 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2771 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2772 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2773 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2774 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2775 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2776 | {"$fcc7", RTYPE_FCC | 7} | |
2777 | ||
2778 | #define COPROC_CONDITION_CODE_NAMES \ | |
2779 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2780 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2781 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2782 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2783 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2784 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2785 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2786 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2787 | ||
2788 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2789 | {"$a4", RTYPE_GP | 8}, \ | |
2790 | {"$a5", RTYPE_GP | 9}, \ | |
2791 | {"$a6", RTYPE_GP | 10}, \ | |
2792 | {"$a7", RTYPE_GP | 11}, \ | |
2793 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2794 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2795 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2796 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2797 | {"$t0", RTYPE_GP | 12}, \ | |
2798 | {"$t1", RTYPE_GP | 13}, \ | |
2799 | {"$t2", RTYPE_GP | 14}, \ | |
2800 | {"$t3", RTYPE_GP | 15} | |
2801 | ||
2802 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2803 | {"$t0", RTYPE_GP | 8}, \ | |
2804 | {"$t1", RTYPE_GP | 9}, \ | |
2805 | {"$t2", RTYPE_GP | 10}, \ | |
2806 | {"$t3", RTYPE_GP | 11}, \ | |
2807 | {"$t4", RTYPE_GP | 12}, \ | |
2808 | {"$t5", RTYPE_GP | 13}, \ | |
2809 | {"$t6", RTYPE_GP | 14}, \ | |
2810 | {"$t7", RTYPE_GP | 15}, \ | |
2811 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2812 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2813 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2814 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 | 2815 | |
6f2117ba | 2816 | /* Remaining symbolic register names. */ |
707bfff6 TS |
2817 | #define SYMBOLIC_REGISTER_NAMES \ |
2818 | {"$zero", RTYPE_GP | 0}, \ | |
2819 | {"$at", RTYPE_GP | 1}, \ | |
2820 | {"$AT", RTYPE_GP | 1}, \ | |
2821 | {"$v0", RTYPE_GP | 2}, \ | |
2822 | {"$v1", RTYPE_GP | 3}, \ | |
2823 | {"$a0", RTYPE_GP | 4}, \ | |
2824 | {"$a1", RTYPE_GP | 5}, \ | |
2825 | {"$a2", RTYPE_GP | 6}, \ | |
2826 | {"$a3", RTYPE_GP | 7}, \ | |
2827 | {"$s0", RTYPE_GP | 16}, \ | |
2828 | {"$s1", RTYPE_GP | 17}, \ | |
2829 | {"$s2", RTYPE_GP | 18}, \ | |
2830 | {"$s3", RTYPE_GP | 19}, \ | |
2831 | {"$s4", RTYPE_GP | 20}, \ | |
2832 | {"$s5", RTYPE_GP | 21}, \ | |
2833 | {"$s6", RTYPE_GP | 22}, \ | |
2834 | {"$s7", RTYPE_GP | 23}, \ | |
2835 | {"$t8", RTYPE_GP | 24}, \ | |
2836 | {"$t9", RTYPE_GP | 25}, \ | |
2837 | {"$k0", RTYPE_GP | 26}, \ | |
2838 | {"$kt0", RTYPE_GP | 26}, \ | |
2839 | {"$k1", RTYPE_GP | 27}, \ | |
2840 | {"$kt1", RTYPE_GP | 27}, \ | |
2841 | {"$gp", RTYPE_GP | 28}, \ | |
2842 | {"$sp", RTYPE_GP | 29}, \ | |
2843 | {"$s8", RTYPE_GP | 30}, \ | |
2844 | {"$fp", RTYPE_GP | 30}, \ | |
2845 | {"$ra", RTYPE_GP | 31} | |
2846 | ||
2847 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2848 | {"$pc", RTYPE_PC | 0} | |
2849 | ||
2850 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
6f2117ba PH |
2851 | /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \ |
2852 | /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \ | |
707bfff6 TS |
2853 | {"$v2", RTYPE_VEC | 2}, \ |
2854 | {"$v3", RTYPE_VEC | 3}, \ | |
2855 | {"$v4", RTYPE_VEC | 4}, \ | |
2856 | {"$v5", RTYPE_VEC | 5}, \ | |
2857 | {"$v6", RTYPE_VEC | 6}, \ | |
2858 | {"$v7", RTYPE_VEC | 7}, \ | |
2859 | {"$v8", RTYPE_VEC | 8}, \ | |
2860 | {"$v9", RTYPE_VEC | 9}, \ | |
2861 | {"$v10", RTYPE_VEC | 10}, \ | |
2862 | {"$v11", RTYPE_VEC | 11}, \ | |
2863 | {"$v12", RTYPE_VEC | 12}, \ | |
2864 | {"$v13", RTYPE_VEC | 13}, \ | |
2865 | {"$v14", RTYPE_VEC | 14}, \ | |
2866 | {"$v15", RTYPE_VEC | 15}, \ | |
2867 | {"$v16", RTYPE_VEC | 16}, \ | |
2868 | {"$v17", RTYPE_VEC | 17}, \ | |
2869 | {"$v18", RTYPE_VEC | 18}, \ | |
2870 | {"$v19", RTYPE_VEC | 19}, \ | |
2871 | {"$v20", RTYPE_VEC | 20}, \ | |
2872 | {"$v21", RTYPE_VEC | 21}, \ | |
2873 | {"$v22", RTYPE_VEC | 22}, \ | |
2874 | {"$v23", RTYPE_VEC | 23}, \ | |
2875 | {"$v24", RTYPE_VEC | 24}, \ | |
2876 | {"$v25", RTYPE_VEC | 25}, \ | |
2877 | {"$v26", RTYPE_VEC | 26}, \ | |
2878 | {"$v27", RTYPE_VEC | 27}, \ | |
2879 | {"$v28", RTYPE_VEC | 28}, \ | |
2880 | {"$v29", RTYPE_VEC | 29}, \ | |
2881 | {"$v30", RTYPE_VEC | 30}, \ | |
2882 | {"$v31", RTYPE_VEC | 31} | |
2883 | ||
14daeee3 RS |
2884 | #define R5900_I_NAMES \ |
2885 | {"$I", RTYPE_R5900_I | 0} | |
2886 | ||
2887 | #define R5900_Q_NAMES \ | |
2888 | {"$Q", RTYPE_R5900_Q | 0} | |
2889 | ||
2890 | #define R5900_R_NAMES \ | |
2891 | {"$R", RTYPE_R5900_R | 0} | |
2892 | ||
2893 | #define R5900_ACC_NAMES \ | |
2894 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2895 | ||
707bfff6 TS |
2896 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2897 | {"$ac0", RTYPE_ACC | 0}, \ | |
2898 | {"$ac1", RTYPE_ACC | 1}, \ | |
2899 | {"$ac2", RTYPE_ACC | 2}, \ | |
2900 | {"$ac3", RTYPE_ACC | 3} | |
2901 | ||
2902 | static const struct regname reg_names[] = { | |
2903 | GENERIC_REGISTER_NUMBERS, | |
2904 | FPU_REGISTER_NAMES, | |
2905 | FPU_CONDITION_CODE_NAMES, | |
2906 | COPROC_CONDITION_CODE_NAMES, | |
2907 | ||
2908 | /* The $txx registers depends on the abi, | |
2909 | these will be added later into the symbol table from | |
3739860c | 2910 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2911 | parsing of arguments from the command line. */ |
2912 | SYMBOLIC_REGISTER_NAMES, | |
2913 | ||
2914 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2915 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2916 | R5900_I_NAMES, |
2917 | R5900_Q_NAMES, | |
2918 | R5900_R_NAMES, | |
2919 | R5900_ACC_NAMES, | |
707bfff6 TS |
2920 | MIPS_DSP_ACCUMULATOR_NAMES, |
2921 | {0, 0} | |
2922 | }; | |
2923 | ||
2924 | static const struct regname reg_names_o32[] = { | |
2925 | O32_SYMBOLIC_REGISTER_NAMES, | |
2926 | {0, 0} | |
2927 | }; | |
2928 | ||
2929 | static const struct regname reg_names_n32n64[] = { | |
2930 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2931 | {0, 0} | |
2932 | }; | |
2933 | ||
a92713e6 RS |
2934 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2935 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2936 | of these register symbols, return the associated vector register, | |
2937 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2938 | |
a92713e6 RS |
2939 | static unsigned int |
2940 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2941 | { |
a92713e6 RS |
2942 | if ((symval & -2) == (RTYPE_GP | 2)) |
2943 | return RTYPE_VEC | (symval & 1); | |
2944 | return symval; | |
2945 | } | |
2946 | ||
14daeee3 RS |
2947 | /* Return true if string [S, E) is a valid register name, storing its |
2948 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2949 | |
2950 | static bfd_boolean | |
14daeee3 | 2951 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2952 | { |
707bfff6 | 2953 | char save_c; |
14daeee3 | 2954 | symbolS *symbol; |
707bfff6 TS |
2955 | |
2956 | /* Terminate name. */ | |
2957 | save_c = *e; | |
2958 | *e = '\0'; | |
2959 | ||
a92713e6 RS |
2960 | /* Look up the name. */ |
2961 | symbol = symbol_find (s); | |
2962 | *e = save_c; | |
2963 | ||
2964 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2965 | return FALSE; | |
2966 | ||
14daeee3 RS |
2967 | *symval_ptr = S_GET_VALUE (symbol); |
2968 | return TRUE; | |
2969 | } | |
2970 | ||
2971 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2972 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2973 | is nonnull. | |
2974 | ||
2975 | When returning true, move *SPTR past the register, store the | |
2976 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2977 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2978 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2979 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2980 | ||
2981 | static bfd_boolean | |
2982 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2983 | unsigned int *channels_ptr) | |
2984 | { | |
2985 | char *s, *e, *m; | |
2986 | const char *q; | |
2987 | unsigned int channels, symval, bit; | |
2988 | ||
2989 | /* Find end of name. */ | |
2990 | s = e = *sptr; | |
2991 | if (is_name_beginner (*e)) | |
2992 | ++e; | |
2993 | while (is_part_of_name (*e)) | |
2994 | ++e; | |
2995 | ||
2996 | channels = 0; | |
2997 | if (!mips_parse_register_1 (s, e, &symval)) | |
2998 | { | |
2999 | if (!channels_ptr) | |
3000 | return FALSE; | |
3001 | ||
3002 | /* Eat characters from the end of the string that are valid | |
3003 | channel suffixes. The preceding register must be $ACC or | |
3004 | end with a digit, so there is no ambiguity. */ | |
3005 | bit = 1; | |
3006 | m = e; | |
3007 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
3008 | if (m > s && m[-1] == *q) | |
3009 | { | |
3010 | --m; | |
3011 | channels |= bit; | |
3012 | } | |
3013 | ||
3014 | if (channels == 0 | |
3015 | || !mips_parse_register_1 (s, m, &symval) | |
3016 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
3017 | return FALSE; | |
3018 | } | |
3019 | ||
a92713e6 | 3020 | *sptr = e; |
14daeee3 RS |
3021 | *symval_ptr = symval; |
3022 | if (channels_ptr) | |
3023 | *channels_ptr = channels; | |
a92713e6 RS |
3024 | return TRUE; |
3025 | } | |
3026 | ||
3027 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
3028 | If so, then return 1, advance S to consume the specifier and store | |
3029 | the register's number in REGNOP, otherwise return 0. */ | |
3030 | ||
3031 | static int | |
3032 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
3033 | { | |
3034 | unsigned int regno; | |
3035 | ||
14daeee3 | 3036 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 3037 | { |
a92713e6 RS |
3038 | if (types & RTYPE_VEC) |
3039 | regno = mips_prefer_vec_regno (regno); | |
3040 | if (regno & types) | |
3041 | regno &= RNUM_MASK; | |
3042 | else | |
3043 | regno = ~0; | |
707bfff6 | 3044 | } |
a92713e6 | 3045 | else |
707bfff6 | 3046 | { |
a92713e6 | 3047 | if (types & RWARN) |
1661c76c | 3048 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 3049 | regno = ~0; |
707bfff6 | 3050 | } |
707bfff6 | 3051 | if (regnop) |
a92713e6 RS |
3052 | *regnop = regno; |
3053 | return regno <= RNUM_MASK; | |
707bfff6 TS |
3054 | } |
3055 | ||
14daeee3 RS |
3056 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
3057 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
3058 | ||
3059 | static char * | |
3060 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
3061 | { | |
3062 | unsigned int i; | |
3063 | ||
3064 | *channels = 0; | |
3065 | for (i = 0; i < 4; i++) | |
3066 | if (*s == "xyzw"[i]) | |
3067 | { | |
3068 | *channels |= 1 << (3 - i); | |
3069 | ++s; | |
3070 | } | |
3071 | return s; | |
3072 | } | |
3073 | ||
a92713e6 RS |
3074 | /* Token types for parsed operand lists. */ |
3075 | enum mips_operand_token_type { | |
3076 | /* A plain register, e.g. $f2. */ | |
3077 | OT_REG, | |
df58fc94 | 3078 | |
14daeee3 RS |
3079 | /* A 4-bit XYZW channel mask. */ |
3080 | OT_CHANNELS, | |
3081 | ||
56d438b1 CF |
3082 | /* A constant vector index, e.g. [1]. */ |
3083 | OT_INTEGER_INDEX, | |
3084 | ||
3085 | /* A register vector index, e.g. [$2]. */ | |
3086 | OT_REG_INDEX, | |
df58fc94 | 3087 | |
a92713e6 RS |
3088 | /* A continuous range of registers, e.g. $s0-$s4. */ |
3089 | OT_REG_RANGE, | |
3090 | ||
3091 | /* A (possibly relocated) expression. */ | |
3092 | OT_INTEGER, | |
3093 | ||
3094 | /* A floating-point value. */ | |
3095 | OT_FLOAT, | |
3096 | ||
3097 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
3098 | before OT_REGs. */ | |
3099 | OT_CHAR, | |
3100 | ||
14daeee3 RS |
3101 | /* A doubled character, either "--" or "++". */ |
3102 | OT_DOUBLE_CHAR, | |
3103 | ||
a92713e6 RS |
3104 | /* The end of the operand list. */ |
3105 | OT_END | |
3106 | }; | |
3107 | ||
3108 | /* A parsed operand token. */ | |
3109 | struct mips_operand_token | |
3110 | { | |
3111 | /* The type of token. */ | |
3112 | enum mips_operand_token_type type; | |
3113 | union | |
3114 | { | |
56d438b1 | 3115 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
3116 | unsigned int regno; |
3117 | ||
14daeee3 RS |
3118 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
3119 | unsigned int channels; | |
3120 | ||
56d438b1 CF |
3121 | /* The integer value of an OT_INTEGER_INDEX. */ |
3122 | addressT index; | |
a92713e6 RS |
3123 | |
3124 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
3125 | struct { | |
3126 | unsigned int regno1; | |
3127 | unsigned int regno2; | |
3128 | } reg_range; | |
3129 | ||
3130 | /* The value of an OT_INTEGER. The value is represented as an | |
3131 | expression and the relocation operators that were applied to | |
3132 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
3133 | relocation operators were used. */ | |
3134 | struct { | |
3135 | expressionS value; | |
3136 | bfd_reloc_code_real_type relocs[3]; | |
3137 | } integer; | |
3138 | ||
3139 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3140 | in the constant. */ | |
3141 | struct { | |
3142 | unsigned char data[8]; | |
3143 | int length; | |
3144 | } flt; | |
3145 | ||
14daeee3 | 3146 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3147 | char ch; |
3148 | } u; | |
3149 | }; | |
3150 | ||
3151 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3152 | static struct obstack mips_operand_tokens; | |
3153 | ||
3154 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3155 | ||
3156 | static void | |
3157 | mips_add_token (struct mips_operand_token *token, | |
3158 | enum mips_operand_token_type type) | |
3159 | { | |
3160 | token->type = type; | |
3161 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3162 | } | |
3163 | ||
3164 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3165 | and OT_REG tokens for them if so, and return a pointer to the first | |
3166 | unconsumed character. Return null otherwise. */ | |
3167 | ||
3168 | static char * | |
3169 | mips_parse_base_start (char *s) | |
3170 | { | |
3171 | struct mips_operand_token token; | |
14daeee3 RS |
3172 | unsigned int regno, channels; |
3173 | bfd_boolean decrement_p; | |
df58fc94 | 3174 | |
a92713e6 RS |
3175 | if (*s != '(') |
3176 | return 0; | |
3177 | ||
3178 | ++s; | |
3179 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3180 | |
3181 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3182 | is a double negative. */ | |
3183 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3184 | if (decrement_p) | |
3185 | { | |
3186 | s += 2; | |
3187 | SKIP_SPACE_TABS (s); | |
3188 | } | |
3189 | ||
3190 | /* Allow a channel specifier because that leads to better error messages | |
3191 | than treating something like "$vf0x++" as an expression. */ | |
3192 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3193 | return 0; |
3194 | ||
3195 | token.u.ch = '('; | |
3196 | mips_add_token (&token, OT_CHAR); | |
3197 | ||
14daeee3 RS |
3198 | if (decrement_p) |
3199 | { | |
3200 | token.u.ch = '-'; | |
3201 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3202 | } | |
3203 | ||
a92713e6 RS |
3204 | token.u.regno = regno; |
3205 | mips_add_token (&token, OT_REG); | |
3206 | ||
14daeee3 RS |
3207 | if (channels) |
3208 | { | |
3209 | token.u.channels = channels; | |
3210 | mips_add_token (&token, OT_CHANNELS); | |
3211 | } | |
3212 | ||
3213 | /* For consistency, only match "++" as part of base expressions too. */ | |
3214 | SKIP_SPACE_TABS (s); | |
3215 | if (s[0] == '+' && s[1] == '+') | |
3216 | { | |
3217 | s += 2; | |
3218 | token.u.ch = '+'; | |
3219 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3220 | } | |
3221 | ||
a92713e6 RS |
3222 | return s; |
3223 | } | |
3224 | ||
3225 | /* Parse one or more tokens from S. Return a pointer to the first | |
3226 | unconsumed character on success. Return null if an error was found | |
3227 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3228 | mips_parse_arguments. */ | |
3229 | ||
3230 | static char * | |
3231 | mips_parse_argument_token (char *s, char float_format) | |
3232 | { | |
6d4af3c2 AM |
3233 | char *end, *save_in; |
3234 | const char *err; | |
14daeee3 | 3235 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3236 | struct mips_operand_token token; |
3237 | ||
3238 | /* First look for "($reg", since we want to treat that as an | |
3239 | OT_CHAR and OT_REG rather than an expression. */ | |
3240 | end = mips_parse_base_start (s); | |
3241 | if (end) | |
3242 | return end; | |
3243 | ||
3244 | /* Handle other characters that end up as OT_CHARs. */ | |
3245 | if (*s == ')' || *s == ',') | |
3246 | { | |
3247 | token.u.ch = *s; | |
3248 | mips_add_token (&token, OT_CHAR); | |
3249 | ++s; | |
3250 | return s; | |
3251 | } | |
3252 | ||
3253 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3254 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3255 | { |
14daeee3 RS |
3256 | if (channels) |
3257 | { | |
3258 | /* A register and a VU0 channel suffix. */ | |
3259 | token.u.regno = regno1; | |
3260 | mips_add_token (&token, OT_REG); | |
3261 | ||
3262 | token.u.channels = channels; | |
3263 | mips_add_token (&token, OT_CHANNELS); | |
3264 | return s; | |
3265 | } | |
3266 | ||
a92713e6 RS |
3267 | SKIP_SPACE_TABS (s); |
3268 | if (*s == '-') | |
df58fc94 | 3269 | { |
a92713e6 RS |
3270 | /* A register range. */ |
3271 | ++s; | |
3272 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3273 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3274 | { |
1661c76c | 3275 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3276 | return 0; |
3277 | } | |
df58fc94 | 3278 | |
a92713e6 RS |
3279 | token.u.reg_range.regno1 = regno1; |
3280 | token.u.reg_range.regno2 = regno2; | |
3281 | mips_add_token (&token, OT_REG_RANGE); | |
3282 | return s; | |
3283 | } | |
a92713e6 | 3284 | |
56d438b1 CF |
3285 | /* Add the register itself. */ |
3286 | token.u.regno = regno1; | |
3287 | mips_add_token (&token, OT_REG); | |
3288 | ||
3289 | /* Check for a vector index. */ | |
3290 | if (*s == '[') | |
3291 | { | |
a92713e6 RS |
3292 | ++s; |
3293 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3294 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3295 | mips_add_token (&token, OT_REG_INDEX); | |
3296 | else | |
a92713e6 | 3297 | { |
56d438b1 CF |
3298 | expressionS element; |
3299 | ||
3300 | my_getExpression (&element, s); | |
3301 | if (element.X_op != O_constant) | |
3302 | { | |
3303 | set_insn_error (0, _("vector element must be constant")); | |
3304 | return 0; | |
3305 | } | |
3306 | s = expr_end; | |
3307 | token.u.index = element.X_add_number; | |
3308 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3309 | } |
a92713e6 RS |
3310 | SKIP_SPACE_TABS (s); |
3311 | if (*s != ']') | |
3312 | { | |
1661c76c | 3313 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3314 | return 0; |
3315 | } | |
3316 | ++s; | |
df58fc94 | 3317 | } |
a92713e6 | 3318 | return s; |
df58fc94 RS |
3319 | } |
3320 | ||
a92713e6 RS |
3321 | if (float_format) |
3322 | { | |
3323 | /* First try to treat expressions as floats. */ | |
3324 | save_in = input_line_pointer; | |
3325 | input_line_pointer = s; | |
3326 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3327 | &token.u.flt.length); | |
3328 | end = input_line_pointer; | |
3329 | input_line_pointer = save_in; | |
3330 | if (err && *err) | |
3331 | { | |
e3de51ce | 3332 | set_insn_error (0, err); |
a92713e6 RS |
3333 | return 0; |
3334 | } | |
3335 | if (s != end) | |
3336 | { | |
3337 | mips_add_token (&token, OT_FLOAT); | |
3338 | return end; | |
3339 | } | |
3340 | } | |
3341 | ||
3342 | /* Treat everything else as an integer expression. */ | |
3343 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3344 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3345 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3346 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3347 | s = expr_end; | |
3348 | mips_add_token (&token, OT_INTEGER); | |
3349 | return s; | |
3350 | } | |
3351 | ||
3352 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3353 | if expressions should be treated as 32-bit floating-point constants, | |
3354 | 'd' if they should be treated as 64-bit floating-point constants, | |
3355 | or 0 if they should be treated as integer expressions (the usual case). | |
3356 | ||
3357 | Return a list of tokens on success, otherwise return 0. The caller | |
3358 | must obstack_free the list after use. */ | |
3359 | ||
3360 | static struct mips_operand_token * | |
3361 | mips_parse_arguments (char *s, char float_format) | |
3362 | { | |
3363 | struct mips_operand_token token; | |
3364 | ||
3365 | SKIP_SPACE_TABS (s); | |
3366 | while (*s) | |
3367 | { | |
3368 | s = mips_parse_argument_token (s, float_format); | |
3369 | if (!s) | |
3370 | { | |
3371 | obstack_free (&mips_operand_tokens, | |
3372 | obstack_finish (&mips_operand_tokens)); | |
3373 | return 0; | |
3374 | } | |
3375 | SKIP_SPACE_TABS (s); | |
3376 | } | |
3377 | mips_add_token (&token, OT_END); | |
3378 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3379 | } |
3380 | ||
d301a56b RS |
3381 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3382 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3383 | |
3384 | static bfd_boolean | |
f79e2745 | 3385 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3386 | { |
3387 | int isa = mips_opts.isa; | |
846ef2d0 | 3388 | int ase = mips_opts.ase; |
037b32b9 | 3389 | int fp_s, fp_d; |
c6278170 | 3390 | unsigned int i; |
037b32b9 | 3391 | |
be0fcbee | 3392 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3393 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3394 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3395 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3396 | |
d301a56b | 3397 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3398 | return FALSE; |
3399 | ||
3400 | /* Check whether the instruction or macro requires single-precision or | |
3401 | double-precision floating-point support. Note that this information is | |
3402 | stored differently in the opcode table for insns and macros. */ | |
3403 | if (mo->pinfo == INSN_MACRO) | |
3404 | { | |
3405 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3406 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3407 | } | |
3408 | else | |
3409 | { | |
3410 | fp_s = mo->pinfo & FP_S; | |
3411 | fp_d = mo->pinfo & FP_D; | |
3412 | } | |
3413 | ||
3414 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3415 | return FALSE; | |
3416 | ||
3417 | if (fp_s && mips_opts.soft_float) | |
3418 | return FALSE; | |
3419 | ||
3420 | return TRUE; | |
3421 | } | |
3422 | ||
3423 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3424 | selected ISA and architecture. */ | |
3425 | ||
3426 | static bfd_boolean | |
3427 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3428 | { | |
25499ac7 MR |
3429 | int isa = mips_opts.isa; |
3430 | int ase = mips_opts.ase; | |
3431 | unsigned int i; | |
3432 | ||
3433 | if (ISA_HAS_64BIT_REGS (isa)) | |
3434 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3435 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3436 | ase |= mips_ases[i].flags64; | |
3437 | ||
3438 | return opcode_is_member (mo, isa, ase, mips_opts.arch); | |
037b32b9 AN |
3439 | } |
3440 | ||
df58fc94 | 3441 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3442 | explicitly requested. Always TRUE in the standard MIPS mode. |
3443 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3444 | |
3445 | static bfd_boolean | |
3446 | is_size_valid (const struct mips_opcode *mo) | |
3447 | { | |
3448 | if (!mips_opts.micromips) | |
3449 | return TRUE; | |
3450 | ||
833794fc MR |
3451 | if (mips_opts.insn32) |
3452 | { | |
3453 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3454 | return FALSE; | |
3455 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3456 | return FALSE; | |
3457 | } | |
df58fc94 RS |
3458 | if (!forced_insn_length) |
3459 | return TRUE; | |
3460 | if (mo->pinfo == INSN_MACRO) | |
3461 | return FALSE; | |
3462 | return forced_insn_length == micromips_insn_length (mo); | |
3463 | } | |
3464 | ||
7fd53920 MR |
3465 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3466 | explicitly requested. */ | |
3467 | ||
3468 | static bfd_boolean | |
3469 | is_size_valid_16 (const struct mips_opcode *mo) | |
3470 | { | |
3471 | if (!forced_insn_length) | |
3472 | return TRUE; | |
3473 | if (mo->pinfo == INSN_MACRO) | |
3474 | return FALSE; | |
3475 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3476 | return FALSE; | |
0674ee5d MR |
3477 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3478 | return FALSE; | |
7fd53920 MR |
3479 | return TRUE; |
3480 | } | |
3481 | ||
df58fc94 | 3482 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3483 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3484 | ||
3485 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3486 | a macro expansion fails because it relies on a preceding 32-bit real | |
3487 | instruction to have matched and does not handle the operands correctly. | |
3488 | The only macros that may expand to 16-bit instructions are JAL that | |
3489 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3490 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3491 | a NOP. In all these cases the macros precede any corresponding real | |
3492 | instruction definitions in the opcode table, so they will match in the | |
3493 | second pass where the size of the delay slot is ignored and therefore | |
3494 | produce correct code. */ | |
df58fc94 RS |
3495 | |
3496 | static bfd_boolean | |
3497 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3498 | { | |
3499 | if (!mips_opts.micromips) | |
3500 | return TRUE; | |
3501 | ||
3502 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3503 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3504 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3505 | && micromips_insn_length (mo) != 4) | |
3506 | return FALSE; | |
3507 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3508 | && micromips_insn_length (mo) != 2) | |
3509 | return FALSE; | |
3510 | ||
3511 | return TRUE; | |
3512 | } | |
3513 | ||
fc76e730 RS |
3514 | /* For consistency checking, verify that all bits of OPCODE are specified |
3515 | either by the match/mask part of the instruction definition, or by the | |
3516 | operand list. Also build up a list of operands in OPERANDS. | |
3517 | ||
3518 | INSN_BITS says which bits of the instruction are significant. | |
3519 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3520 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3521 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3522 | |
3523 | static int | |
3524 | validate_mips_insn (const struct mips_opcode *opcode, | |
3525 | unsigned long insn_bits, | |
fc76e730 RS |
3526 | const struct mips_operand *(*decode_operand) (const char *), |
3527 | struct mips_operand_array *operands) | |
ab902481 RS |
3528 | { |
3529 | const char *s; | |
fc76e730 | 3530 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3531 | const struct mips_operand *operand; |
3532 | ||
fc76e730 RS |
3533 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3534 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3535 | { |
3536 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3537 | opcode->name, opcode->args); | |
3538 | return 0; | |
3539 | } | |
3540 | used_bits = 0; | |
fc76e730 | 3541 | opno = 0; |
14daeee3 RS |
3542 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3543 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3544 | for (s = opcode->args; *s; ++s) |
3545 | switch (*s) | |
3546 | { | |
3547 | case ',': | |
3548 | case '(': | |
3549 | case ')': | |
3550 | break; | |
3551 | ||
14daeee3 RS |
3552 | case '#': |
3553 | s++; | |
3554 | break; | |
3555 | ||
ab902481 | 3556 | default: |
fc76e730 | 3557 | if (!decode_operand) |
7fd53920 | 3558 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3559 | else |
3560 | operand = decode_operand (s); | |
3561 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3562 | { |
3563 | as_bad (_("internal: unknown operand type: %s %s"), | |
3564 | opcode->name, opcode->args); | |
3565 | return 0; | |
3566 | } | |
fc76e730 RS |
3567 | gas_assert (opno < MAX_OPERANDS); |
3568 | operands->operand[opno] = operand; | |
25499ac7 MR |
3569 | if (!decode_operand && operand |
3570 | && operand->type == OP_INT && operand->lsb == 0 | |
3571 | && mips_opcode_32bit_p (opcode)) | |
3572 | used_bits |= mips16_immed_extend (-1, operand->size); | |
3573 | else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) | |
fc76e730 | 3574 | { |
14daeee3 | 3575 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3576 | if (operand->type == OP_MDMX_IMM_REG) |
3577 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3578 | has separate entries for each format. */ | |
3579 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3580 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3581 | used_bits &= ~(mask & 0x700); | |
38bf472a MR |
3582 | /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous |
3583 | operand field that cannot be fully described with LSB/SIZE. */ | |
3584 | if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6) | |
3585 | used_bits &= ~0x6000; | |
fc76e730 | 3586 | } |
ab902481 | 3587 | /* Skip prefix characters. */ |
7361da2c | 3588 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3589 | ++s; |
fc76e730 | 3590 | opno += 1; |
ab902481 RS |
3591 | break; |
3592 | } | |
fc76e730 | 3593 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3594 | if (doubled) |
3595 | { | |
3596 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3597 | " %s %s"), doubled, opcode->name, opcode->args); | |
3598 | return 0; | |
3599 | } | |
fc76e730 | 3600 | used_bits |= mask; |
ab902481 | 3601 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3602 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3603 | { |
3604 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3605 | undefined, opcode->name, opcode->args); | |
3606 | return 0; | |
3607 | } | |
3608 | used_bits &= ~insn_bits; | |
3609 | if (used_bits) | |
3610 | { | |
3611 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3612 | used_bits, opcode->name, opcode->args); | |
3613 | return 0; | |
3614 | } | |
3615 | return 1; | |
3616 | } | |
3617 | ||
fc76e730 RS |
3618 | /* The MIPS16 version of validate_mips_insn. */ |
3619 | ||
3620 | static int | |
3621 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3622 | struct mips_operand_array *operands) | |
3623 | { | |
7fd53920 | 3624 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3625 | |
7fd53920 | 3626 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3627 | } |
3628 | ||
ab902481 RS |
3629 | /* The microMIPS version of validate_mips_insn. */ |
3630 | ||
3631 | static int | |
fc76e730 RS |
3632 | validate_micromips_insn (const struct mips_opcode *opc, |
3633 | struct mips_operand_array *operands) | |
ab902481 RS |
3634 | { |
3635 | unsigned long insn_bits; | |
3636 | unsigned long major; | |
3637 | unsigned int length; | |
3638 | ||
fc76e730 RS |
3639 | if (opc->pinfo == INSN_MACRO) |
3640 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3641 | operands); | |
3642 | ||
ab902481 RS |
3643 | length = micromips_insn_length (opc); |
3644 | if (length != 2 && length != 4) | |
3645 | { | |
1661c76c | 3646 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3647 | "%s %s"), length, opc->name, opc->args); |
3648 | return 0; | |
3649 | } | |
3650 | major = opc->match >> (10 + 8 * (length - 2)); | |
3651 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3652 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3653 | { | |
1661c76c | 3654 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3655 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3656 | return 0; | |
3657 | } | |
3658 | ||
3659 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3660 | insn_bits = 1 << 4 * length; | |
3661 | insn_bits <<= 4 * length; | |
3662 | insn_bits -= 1; | |
fc76e730 RS |
3663 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3664 | operands); | |
ab902481 RS |
3665 | } |
3666 | ||
707bfff6 TS |
3667 | /* This function is called once, at assembler startup time. It should set up |
3668 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3669 | |
252b5132 | 3670 | void |
17a2f251 | 3671 | md_begin (void) |
252b5132 | 3672 | { |
3994f87e | 3673 | const char *retval = NULL; |
156c2f8b | 3674 | int i = 0; |
252b5132 | 3675 | int broken = 0; |
1f25f5d3 | 3676 | |
0a44bf69 RS |
3677 | if (mips_pic != NO_PIC) |
3678 | { | |
3679 | if (g_switch_seen && g_switch_value != 0) | |
3680 | as_bad (_("-G may not be used in position-independent code")); | |
3681 | g_switch_value = 0; | |
3682 | } | |
00acd688 CM |
3683 | else if (mips_abicalls) |
3684 | { | |
3685 | if (g_switch_seen && g_switch_value != 0) | |
3686 | as_bad (_("-G may not be used with abicalls")); | |
3687 | g_switch_value = 0; | |
3688 | } | |
0a44bf69 | 3689 | |
0b35dfee | 3690 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3691 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3692 | |
252b5132 RH |
3693 | op_hash = hash_new (); |
3694 | ||
fc76e730 | 3695 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3696 | for (i = 0; i < NUMOPCODES;) |
3697 | { | |
3698 | const char *name = mips_opcodes[i].name; | |
3699 | ||
17a2f251 | 3700 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3701 | if (retval != NULL) |
3702 | { | |
3703 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3704 | mips_opcodes[i].name, retval); | |
3705 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3706 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3707 | } |
3708 | do | |
3709 | { | |
fc76e730 RS |
3710 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3711 | decode_mips_operand, &mips_operands[i])) | |
3712 | broken = 1; | |
6f2117ba | 3713 | |
fc76e730 | 3714 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
252b5132 | 3715 | { |
fc76e730 RS |
3716 | create_insn (&nop_insn, mips_opcodes + i); |
3717 | if (mips_fix_loongson2f_nop) | |
3718 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3719 | nop_insn.fixed_p = 1; | |
252b5132 | 3720 | } |
6f2117ba PH |
3721 | |
3722 | if (sync_insn.insn_mo == NULL && strcmp (name, "sync") == 0) | |
3723 | create_insn (&sync_insn, mips_opcodes + i); | |
3724 | ||
252b5132 RH |
3725 | ++i; |
3726 | } | |
3727 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3728 | } | |
3729 | ||
3730 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3731 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3732 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3733 | |
3734 | i = 0; | |
3735 | while (i < bfd_mips16_num_opcodes) | |
3736 | { | |
3737 | const char *name = mips16_opcodes[i].name; | |
3738 | ||
17a2f251 | 3739 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3740 | if (retval != NULL) |
3741 | as_fatal (_("internal: can't hash `%s': %s"), | |
3742 | mips16_opcodes[i].name, retval); | |
3743 | do | |
3744 | { | |
fc76e730 RS |
3745 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3746 | broken = 1; | |
1e915849 RS |
3747 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3748 | { | |
3749 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3750 | mips16_nop_insn.fixed_p = 1; | |
3751 | } | |
252b5132 RH |
3752 | ++i; |
3753 | } | |
3754 | while (i < bfd_mips16_num_opcodes | |
3755 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3756 | } | |
3757 | ||
df58fc94 | 3758 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3759 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3760 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3761 | |
3762 | i = 0; | |
3763 | while (i < bfd_micromips_num_opcodes) | |
3764 | { | |
3765 | const char *name = micromips_opcodes[i].name; | |
3766 | ||
3767 | retval = hash_insert (micromips_op_hash, name, | |
3768 | (void *) µmips_opcodes[i]); | |
3769 | if (retval != NULL) | |
3770 | as_fatal (_("internal: can't hash `%s': %s"), | |
3771 | micromips_opcodes[i].name, retval); | |
3772 | do | |
fc76e730 RS |
3773 | { |
3774 | struct mips_cl_insn *micromips_nop_insn; | |
3775 | ||
3776 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3777 | µmips_operands[i])) | |
3778 | broken = 1; | |
3779 | ||
3780 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3781 | { | |
3782 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3783 | micromips_nop_insn = µmips_nop16_insn; | |
3784 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3785 | micromips_nop_insn = µmips_nop32_insn; | |
3786 | else | |
3787 | continue; | |
3788 | ||
3789 | if (micromips_nop_insn->insn_mo == NULL | |
3790 | && strcmp (name, "nop") == 0) | |
3791 | { | |
3792 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3793 | micromips_nop_insn->fixed_p = 1; | |
3794 | } | |
3795 | } | |
3796 | } | |
df58fc94 RS |
3797 | while (++i < bfd_micromips_num_opcodes |
3798 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3799 | } | |
3800 | ||
252b5132 | 3801 | if (broken) |
1661c76c | 3802 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3803 | |
3804 | /* We add all the general register names to the symbol table. This | |
3805 | helps us detect invalid uses of them. */ | |
3739860c | 3806 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3807 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3808 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3809 | &zero_address_frag)); |
3810 | if (HAVE_NEWABI) | |
3739860c | 3811 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3812 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3813 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3814 | &zero_address_frag)); |
707bfff6 | 3815 | else |
3739860c | 3816 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3817 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3818 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3819 | &zero_address_frag)); |
6047c971 | 3820 | |
14daeee3 RS |
3821 | for (i = 0; i < 32; i++) |
3822 | { | |
92fce9bd | 3823 | char regname[6]; |
14daeee3 RS |
3824 | |
3825 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3826 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3827 | symbol_table_insert (symbol_new (regname, reg_section, |
3828 | RTYPE_VF | i, &zero_address_frag)); | |
3829 | ||
3830 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3831 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3832 | symbol_table_insert (symbol_new (regname, reg_section, |
3833 | RTYPE_VI | i, &zero_address_frag)); | |
3834 | ||
56d438b1 | 3835 | /* MSA register. */ |
92fce9bd | 3836 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3837 | symbol_table_insert (symbol_new (regname, reg_section, |
3838 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3839 | } |
3840 | ||
a92713e6 RS |
3841 | obstack_init (&mips_operand_tokens); |
3842 | ||
7d10b47d | 3843 | mips_no_prev_insn (); |
252b5132 RH |
3844 | |
3845 | mips_gprmask = 0; | |
3846 | mips_cprmask[0] = 0; | |
3847 | mips_cprmask[1] = 0; | |
3848 | mips_cprmask[2] = 0; | |
3849 | mips_cprmask[3] = 0; | |
3850 | ||
3851 | /* set the default alignment for the text section (2**2) */ | |
3852 | record_alignment (text_section, 2); | |
3853 | ||
4d0d148d | 3854 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3855 | |
f3ded42a RS |
3856 | /* On a native system other than VxWorks, sections must be aligned |
3857 | to 16 byte boundaries. When configured for an embedded ELF | |
3858 | target, we don't bother. */ | |
3859 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3860 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3861 | { |
fd361982 AM |
3862 | bfd_set_section_alignment (text_section, 4); |
3863 | bfd_set_section_alignment (data_section, 4); | |
3864 | bfd_set_section_alignment (bss_section, 4); | |
f3ded42a | 3865 | } |
252b5132 | 3866 | |
f3ded42a RS |
3867 | /* Create a .reginfo section for register masks and a .mdebug |
3868 | section for debugging information. */ | |
3869 | { | |
3870 | segT seg; | |
3871 | subsegT subseg; | |
3872 | flagword flags; | |
3873 | segT sec; | |
3874 | ||
3875 | seg = now_seg; | |
3876 | subseg = now_subseg; | |
3877 | ||
3878 | /* The ABI says this section should be loaded so that the | |
3879 | running program can access it. However, we don't load it | |
6f2117ba | 3880 | if we are configured for an embedded target. */ |
f3ded42a RS |
3881 | flags = SEC_READONLY | SEC_DATA; |
3882 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3883 | flags |= SEC_ALLOC | SEC_LOAD; | |
3884 | ||
3885 | if (mips_abi != N64_ABI) | |
252b5132 | 3886 | { |
f3ded42a | 3887 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3888 | |
fd361982 AM |
3889 | bfd_set_section_flags (sec, flags); |
3890 | bfd_set_section_alignment (sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3891 | |
f3ded42a RS |
3892 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3893 | } | |
3894 | else | |
3895 | { | |
3896 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3897 | .reginfo section. */ | |
3898 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
fd361982 AM |
3899 | bfd_set_section_flags (sec, flags); |
3900 | bfd_set_section_alignment (sec, 3); | |
252b5132 | 3901 | |
f3ded42a RS |
3902 | /* Set up the option header. */ |
3903 | { | |
3904 | Elf_Internal_Options opthdr; | |
3905 | char *f; | |
3906 | ||
3907 | opthdr.kind = ODK_REGINFO; | |
3908 | opthdr.size = (sizeof (Elf_External_Options) | |
3909 | + sizeof (Elf64_External_RegInfo)); | |
3910 | opthdr.section = 0; | |
3911 | opthdr.info = 0; | |
3912 | f = frag_more (sizeof (Elf_External_Options)); | |
3913 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3914 | (Elf_External_Options *) f); | |
3915 | ||
3916 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3917 | } | |
3918 | } | |
252b5132 | 3919 | |
351cdf24 | 3920 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
fd361982 | 3921 | bfd_set_section_flags (sec, |
351cdf24 | 3922 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); |
fd361982 | 3923 | bfd_set_section_alignment (sec, 3); |
351cdf24 MF |
3924 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); |
3925 | ||
f3ded42a RS |
3926 | if (ECOFF_DEBUGGING) |
3927 | { | |
3928 | sec = subseg_new (".mdebug", (subsegT) 0); | |
fd361982 AM |
3929 | bfd_set_section_flags (sec, SEC_HAS_CONTENTS | SEC_READONLY); |
3930 | bfd_set_section_alignment (sec, 2); | |
252b5132 | 3931 | } |
f3ded42a RS |
3932 | else if (mips_flag_pdr) |
3933 | { | |
3934 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
fd361982 AM |
3935 | bfd_set_section_flags (pdr_seg, |
3936 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
3937 | bfd_set_section_alignment (pdr_seg, 2); | |
f3ded42a RS |
3938 | } |
3939 | ||
3940 | subseg_set (seg, subseg); | |
3941 | } | |
252b5132 | 3942 | |
71400594 RS |
3943 | if (mips_fix_vr4120) |
3944 | init_vr4120_conflicts (); | |
252b5132 RH |
3945 | } |
3946 | ||
351cdf24 MF |
3947 | static inline void |
3948 | fpabi_incompatible_with (int fpabi, const char *what) | |
3949 | { | |
3950 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3951 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3952 | } | |
3953 | ||
3954 | static inline void | |
3955 | fpabi_requires (int fpabi, const char *what) | |
3956 | { | |
3957 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3958 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3959 | } | |
3960 | ||
3961 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3962 | static void | |
3963 | check_fpabi (int fpabi) | |
3964 | { | |
351cdf24 MF |
3965 | switch (fpabi) |
3966 | { | |
3967 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3968 | if (file_mips_opts.soft_float) |
3969 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3970 | else if (file_mips_opts.single_float) | |
3971 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3972 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3973 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3974 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3975 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3976 | break; |
3977 | ||
3978 | case Val_GNU_MIPS_ABI_FP_XX: | |
3979 | if (mips_abi != O32_ABI) | |
3980 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3981 | else if (file_mips_opts.soft_float) |
3982 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3983 | else if (file_mips_opts.single_float) | |
3984 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3985 | else if (file_mips_opts.fp != 0) |
3986 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3987 | break; |
3988 | ||
3989 | case Val_GNU_MIPS_ABI_FP_64A: | |
3990 | case Val_GNU_MIPS_ABI_FP_64: | |
3991 | if (mips_abi != O32_ABI) | |
3992 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3993 | else if (file_mips_opts.soft_float) |
3994 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3995 | else if (file_mips_opts.single_float) | |
3996 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3997 | else if (file_mips_opts.fp != 64) |
3998 | fpabi_requires (fpabi, "fp=64"); | |
3999 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
4000 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
4001 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
4002 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
4003 | break; |
4004 | ||
4005 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
4006 | if (file_mips_opts.soft_float) | |
4007 | fpabi_incompatible_with (fpabi, "softfloat"); | |
4008 | else if (!file_mips_opts.single_float) | |
4009 | fpabi_requires (fpabi, "singlefloat"); | |
4010 | break; | |
4011 | ||
4012 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
4013 | if (!file_mips_opts.soft_float) | |
4014 | fpabi_requires (fpabi, "softfloat"); | |
4015 | break; | |
4016 | ||
4017 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
4018 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
4019 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
4020 | break; | |
4021 | ||
3350cc01 CM |
4022 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
4023 | /* Silently ignore compatibility value. */ | |
4024 | break; | |
4025 | ||
351cdf24 MF |
4026 | default: |
4027 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
4028 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
4029 | break; | |
4030 | } | |
351cdf24 MF |
4031 | } |
4032 | ||
919731af | 4033 | /* Perform consistency checks on the current options. */ |
4034 | ||
4035 | static void | |
4036 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
4037 | { | |
4038 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
4039 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
4040 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
4041 | else if (abi_checks | |
4042 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4043 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
4044 | else if (abi_checks | |
4045 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
4046 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
4047 | ||
4048 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
4049 | switch (opts->fp) | |
4050 | { | |
351cdf24 MF |
4051 | case 0: |
4052 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
4053 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
4054 | else if (opts->single_float == 1) | |
4055 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
4056 | break; | |
919731af | 4057 | case 64: |
4058 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
4059 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
4060 | else if (abi_checks | |
4061 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
4062 | && !ISA_HAS_MXHC1 (opts->isa)) | |
4063 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
4064 | break; | |
4065 | case 32: | |
4066 | if (abi_checks | |
4067 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4068 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 4069 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 4070 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 4071 | break; |
4072 | default: | |
4073 | as_bad (_("Unknown size of floating point registers")); | |
4074 | break; | |
4075 | } | |
4076 | ||
351cdf24 MF |
4077 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
4078 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
4079 | ||
919731af | 4080 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 4081 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 4082 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
4083 | && (opts->micromips == 1 |
4084 | || opts->mips16 == 1)) | |
1357373c | 4085 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 4086 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 4087 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
4088 | |
4089 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
4090 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
4091 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 4092 | } |
4093 | ||
4094 | /* Perform consistency checks on the module level options exactly once. | |
4095 | This is a deferred check that happens: | |
4096 | at the first .set directive | |
4097 | or, at the first pseudo op that generates code (inc .dc.a) | |
4098 | or, at the first instruction | |
4099 | or, at the end. */ | |
4100 | ||
4101 | static void | |
4102 | file_mips_check_options (void) | |
4103 | { | |
919731af | 4104 | if (file_mips_opts_checked) |
4105 | return; | |
4106 | ||
4107 | /* The following code determines the register size. | |
4108 | Similar code was added to GCC 3.3 (see override_options() in | |
4109 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
4110 | as much as possible. */ | |
4111 | ||
4112 | if (file_mips_opts.gp < 0) | |
4113 | { | |
4114 | /* Infer the integer register size from the ABI and processor. | |
4115 | Restrict ourselves to 32-bit registers if that's all the | |
4116 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
4117 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
4118 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
4119 | ? 32 : 64; | |
4120 | } | |
4121 | ||
4122 | if (file_mips_opts.fp < 0) | |
4123 | { | |
4124 | /* No user specified float register size. | |
4125 | ??? GAS treats single-float processors as though they had 64-bit | |
4126 | float registers (although it complains when double-precision | |
4127 | instructions are used). As things stand, saying they have 32-bit | |
4128 | registers would lead to spurious "register must be even" messages. | |
4129 | So here we assume float registers are never smaller than the | |
4130 | integer ones. */ | |
4131 | if (file_mips_opts.gp == 64) | |
4132 | /* 64-bit integer registers implies 64-bit float registers. */ | |
4133 | file_mips_opts.fp = 64; | |
4134 | else if ((file_mips_opts.ase & FP64_ASES) | |
4135 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
4136 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
4137 | file_mips_opts.fp = 64; | |
7361da2c AB |
4138 | else if (ISA_IS_R6 (mips_opts.isa)) |
4139 | /* R6 implies 64-bit float registers. */ | |
4140 | file_mips_opts.fp = 64; | |
919731af | 4141 | else |
4142 | /* 32-bit float registers. */ | |
4143 | file_mips_opts.fp = 32; | |
4144 | } | |
4145 | ||
351cdf24 MF |
4146 | /* Disable operations on odd-numbered floating-point registers by default |
4147 | when using the FPXX ABI. */ | |
4148 | if (file_mips_opts.oddspreg < 0) | |
4149 | { | |
4150 | if (file_mips_opts.fp == 0) | |
4151 | file_mips_opts.oddspreg = 0; | |
4152 | else | |
4153 | file_mips_opts.oddspreg = 1; | |
4154 | } | |
4155 | ||
919731af | 4156 | /* End of GCC-shared inference code. */ |
4157 | ||
4158 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4159 | 32-bit wide registers. Note that EABI does not use it. */ | |
4160 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4161 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4162 | || mips_abi == O32_ABI)) | |
4163 | mips_32bitmode = 1; | |
4164 | ||
4165 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4166 | as_bad (_("trap exception not supported at ISA 1")); | |
4167 | ||
4168 | /* If the selected architecture includes support for ASEs, enable | |
4169 | generation of code for them. */ | |
4170 | if (file_mips_opts.mips16 == -1) | |
4171 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4172 | if (file_mips_opts.micromips == -1) | |
4173 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4174 | ? 1 : 0; | |
4175 | ||
7361da2c AB |
4176 | if (mips_nan2008 == -1) |
4177 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4178 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4179 | as_fatal (_("`%s' does not support legacy NaN"), | |
4180 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4181 | ||
919731af | 4182 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4183 | being selected implicitly. */ | |
4184 | if (file_mips_opts.fp != 64) | |
4185 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4186 | ||
4187 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4188 | use the default setting for the CPU. */ | |
3315614d | 4189 | file_mips_opts.ase |= (file_mips_opts.init_ase & ~file_ase_explicit); |
919731af | 4190 | |
4191 | /* Set up the current options. These may change throughout assembly. */ | |
4192 | mips_opts = file_mips_opts; | |
4193 | ||
4194 | mips_check_isa_supports_ases (); | |
4195 | mips_check_options (&file_mips_opts, TRUE); | |
4196 | file_mips_opts_checked = TRUE; | |
4197 | ||
4198 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4199 | as_warn (_("could not set architecture and machine")); | |
4200 | } | |
4201 | ||
252b5132 | 4202 | void |
17a2f251 | 4203 | md_assemble (char *str) |
252b5132 RH |
4204 | { |
4205 | struct mips_cl_insn insn; | |
f6688943 TS |
4206 | bfd_reloc_code_real_type unused_reloc[3] |
4207 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4208 | |
919731af | 4209 | file_mips_check_options (); |
4210 | ||
252b5132 | 4211 | imm_expr.X_op = O_absent; |
252b5132 | 4212 | offset_expr.X_op = O_absent; |
f6688943 TS |
4213 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4214 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4215 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4216 | |
e1b47bd5 RS |
4217 | mips_mark_labels (); |
4218 | mips_assembling_insn = TRUE; | |
e3de51ce | 4219 | clear_insn_error (); |
e1b47bd5 | 4220 | |
252b5132 RH |
4221 | if (mips_opts.mips16) |
4222 | mips16_ip (str, &insn); | |
4223 | else | |
4224 | { | |
4225 | mips_ip (str, &insn); | |
beae10d5 KH |
4226 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4227 | str, insn.insn_opcode)); | |
252b5132 RH |
4228 | } |
4229 | ||
e3de51ce RS |
4230 | if (insn_error.msg) |
4231 | report_insn_error (str); | |
e1b47bd5 | 4232 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4233 | { |
584892a6 | 4234 | macro_start (); |
252b5132 RH |
4235 | if (mips_opts.mips16) |
4236 | mips16_macro (&insn); | |
4237 | else | |
833794fc | 4238 | macro (&insn, str); |
584892a6 | 4239 | macro_end (); |
252b5132 RH |
4240 | } |
4241 | else | |
4242 | { | |
77bd4346 | 4243 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4244 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4245 | else |
df58fc94 | 4246 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4247 | } |
e1b47bd5 RS |
4248 | |
4249 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4250 | } |
4251 | ||
738e5348 RS |
4252 | /* Convenience functions for abstracting away the differences between |
4253 | MIPS16 and non-MIPS16 relocations. */ | |
4254 | ||
4255 | static inline bfd_boolean | |
4256 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4257 | { | |
4258 | switch (reloc) | |
4259 | { | |
4260 | case BFD_RELOC_MIPS16_JMP: | |
4261 | case BFD_RELOC_MIPS16_GPREL: | |
4262 | case BFD_RELOC_MIPS16_GOT16: | |
4263 | case BFD_RELOC_MIPS16_CALL16: | |
4264 | case BFD_RELOC_MIPS16_HI16_S: | |
4265 | case BFD_RELOC_MIPS16_HI16: | |
4266 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4267 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4268 | return TRUE; |
4269 | ||
4270 | default: | |
4271 | return FALSE; | |
4272 | } | |
4273 | } | |
4274 | ||
df58fc94 RS |
4275 | static inline bfd_boolean |
4276 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4277 | { | |
4278 | switch (reloc) | |
4279 | { | |
4280 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4281 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4282 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4283 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4284 | case BFD_RELOC_MICROMIPS_JMP: | |
4285 | case BFD_RELOC_MICROMIPS_HI16: | |
4286 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4287 | case BFD_RELOC_MICROMIPS_LO16: | |
4288 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4289 | case BFD_RELOC_MICROMIPS_GOT16: | |
4290 | case BFD_RELOC_MICROMIPS_CALL16: | |
4291 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4292 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4293 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4294 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4295 | case BFD_RELOC_MICROMIPS_SUB: | |
4296 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4297 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4298 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4299 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4300 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4301 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4302 | case BFD_RELOC_MICROMIPS_JALR: | |
4303 | return TRUE; | |
4304 | ||
4305 | default: | |
4306 | return FALSE; | |
4307 | } | |
4308 | } | |
4309 | ||
2309ddf2 MR |
4310 | static inline bfd_boolean |
4311 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4312 | { | |
4313 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4314 | } | |
4315 | ||
0e9c5a5c MR |
4316 | static inline bfd_boolean |
4317 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4318 | { | |
4319 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4320 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4321 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4322 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4323 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4324 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4325 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4326 | } | |
4327 | ||
738e5348 RS |
4328 | static inline bfd_boolean |
4329 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4330 | { | |
2309ddf2 | 4331 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4332 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4333 | } |
4334 | ||
4335 | static inline bfd_boolean | |
4336 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4337 | { | |
2309ddf2 | 4338 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4339 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4340 | } |
4341 | ||
4342 | static inline bfd_boolean | |
4343 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4344 | { | |
2309ddf2 | 4345 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4346 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4347 | } | |
4348 | ||
df58fc94 RS |
4349 | static inline bfd_boolean |
4350 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4351 | { | |
2309ddf2 | 4352 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4353 | } |
4354 | ||
f2ae14a1 RS |
4355 | static inline bfd_boolean |
4356 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4357 | { | |
4358 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4359 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4360 | } | |
4361 | ||
2de39019 CM |
4362 | /* Return true if RELOC is a PC-relative relocation that does not have |
4363 | full address range. */ | |
4364 | ||
4365 | static inline bfd_boolean | |
4366 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4367 | { | |
4368 | switch (reloc) | |
4369 | { | |
4370 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4371 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4372 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4373 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4374 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4375 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4376 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4377 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4378 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4379 | return TRUE; |
4380 | ||
b47468a6 | 4381 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4382 | case BFD_RELOC_HI16_S_PCREL: |
4383 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4384 | return HAVE_64BIT_ADDRESSES; |
4385 | ||
2de39019 CM |
4386 | default: |
4387 | return FALSE; | |
4388 | } | |
4389 | } | |
b47468a6 | 4390 | |
5919d012 | 4391 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4392 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4393 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4394 | |
4395 | static inline bfd_boolean | |
17a2f251 | 4396 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4397 | { |
3b91255e | 4398 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4399 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4400 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4401 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4402 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4403 | } | |
4404 | ||
4405 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4406 | reloc_needs_lo_p. */ | |
4407 | ||
4408 | static inline bfd_reloc_code_real_type | |
4409 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4410 | { | |
df58fc94 RS |
4411 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4412 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4413 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4414 | } |
4415 | ||
4416 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4417 | relocation. */ | |
4418 | ||
4419 | static inline bfd_boolean | |
17a2f251 | 4420 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4421 | { |
4422 | return (fixp->fx_next != NULL | |
738e5348 | 4423 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4424 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4425 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4426 | } | |
4427 | ||
462427c4 RS |
4428 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4429 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4430 | |
4431 | static void | |
462427c4 | 4432 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4433 | { |
4434 | struct insn_label_list *l; | |
4435 | valueT val; | |
4436 | ||
462427c4 | 4437 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4438 | { |
9c2799c2 | 4439 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4440 | symbol_set_frag (l->label, frag_now); |
4441 | val = (valueT) frag_now_fix (); | |
770c0151 FS |
4442 | /* MIPS16/microMIPS text labels are stored as odd. |
4443 | We just carry the ISA mode bit forward. */ | |
462427c4 | 4444 | if (text_p && HAVE_CODE_COMPRESSION) |
770c0151 | 4445 | val |= (S_GET_VALUE (l->label) & 0x1); |
404a8071 RS |
4446 | S_SET_VALUE (l->label, val); |
4447 | } | |
4448 | } | |
4449 | ||
462427c4 RS |
4450 | /* Move all labels in insn_labels to the current insertion point |
4451 | and treat them as text labels. */ | |
4452 | ||
4453 | static void | |
4454 | mips_move_text_labels (void) | |
4455 | { | |
4456 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4457 | } | |
4458 | ||
9e009953 MR |
4459 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4460 | ||
5f0fe04b TS |
4461 | static bfd_boolean |
4462 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4463 | { | |
4464 | bfd_boolean linkonce = FALSE; | |
4465 | segT symseg = S_GET_SEGMENT (sym); | |
4466 | ||
4467 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4468 | { | |
fd361982 | 4469 | if ((bfd_section_flags (symseg) & SEC_LINK_ONCE)) |
5f0fe04b | 4470 | linkonce = TRUE; |
5f0fe04b TS |
4471 | /* The GNU toolchain uses an extension for ELF: a section |
4472 | beginning with the magic string .gnu.linkonce is a | |
4473 | linkonce section. */ | |
4474 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4475 | sizeof ".gnu.linkonce" - 1) == 0) | |
4476 | linkonce = TRUE; | |
5f0fe04b TS |
4477 | } |
4478 | return linkonce; | |
4479 | } | |
4480 | ||
e1b47bd5 | 4481 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4482 | linker to handle them specially, such as generating jalx instructions |
4483 | when needed. We also make them odd for the duration of the assembly, | |
4484 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4485 | in the adjust_symtab routine, while leaving them marked. This is |
4486 | convenient for the debugger and the disassembler. The linker knows | |
4487 | to make them odd again. */ | |
4488 | ||
4489 | static void | |
e1b47bd5 | 4490 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4491 | { |
df58fc94 | 4492 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4493 | |
f3ded42a RS |
4494 | if (mips_opts.mips16) |
4495 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4496 | else | |
4497 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4498 | if ((S_GET_VALUE (label) & 1) == 0 |
4499 | /* Don't adjust the address if the label is global or weak, or | |
4500 | in a link-once section, since we'll be emitting symbol reloc | |
4501 | references to it which will be patched up by the linker, and | |
4502 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4503 | && !S_IS_WEAK (label) | |
4504 | && !S_IS_EXTERNAL (label) | |
4505 | && !s_is_linkonce (label, now_seg)) | |
4506 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4507 | } | |
4508 | ||
4509 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4510 | ||
4511 | static void | |
4512 | mips_compressed_mark_labels (void) | |
4513 | { | |
4514 | struct insn_label_list *l; | |
4515 | ||
4516 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4517 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4518 | } |
4519 | ||
4d7206a2 RS |
4520 | /* End the current frag. Make it a variant frag and record the |
4521 | relaxation info. */ | |
4522 | ||
4523 | static void | |
4524 | relax_close_frag (void) | |
4525 | { | |
584892a6 | 4526 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4527 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4528 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4529 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4530 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4531 | ||
4532 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4533 | mips_relax.first_fixup = 0; | |
4534 | } | |
4535 | ||
4536 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4537 | See the comment above RELAX_ENCODE for more details. */ | |
4538 | ||
4539 | static void | |
4540 | relax_start (symbolS *symbol) | |
4541 | { | |
9c2799c2 | 4542 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4543 | mips_relax.sequence = 1; |
4544 | mips_relax.symbol = symbol; | |
4545 | } | |
4546 | ||
4547 | /* Start generating the second version of a relaxable sequence. | |
4548 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4549 | |
4550 | static void | |
4d7206a2 RS |
4551 | relax_switch (void) |
4552 | { | |
9c2799c2 | 4553 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4554 | mips_relax.sequence = 2; |
4555 | } | |
4556 | ||
4557 | /* End the current relaxable sequence. */ | |
4558 | ||
4559 | static void | |
4560 | relax_end (void) | |
4561 | { | |
9c2799c2 | 4562 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4563 | relax_close_frag (); |
4564 | mips_relax.sequence = 0; | |
4565 | } | |
4566 | ||
11625dd8 RS |
4567 | /* Return true if IP is a delayed branch or jump. */ |
4568 | ||
4569 | static inline bfd_boolean | |
4570 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4571 | { | |
4572 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4573 | | INSN_COND_BRANCH_DELAY | |
4574 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4575 | } | |
4576 | ||
4577 | /* Return true if IP is a compact branch or jump. */ | |
4578 | ||
4579 | static inline bfd_boolean | |
4580 | compact_branch_p (const struct mips_cl_insn *ip) | |
4581 | { | |
26545944 RS |
4582 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4583 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4584 | } |
4585 | ||
4586 | /* Return true if IP is an unconditional branch or jump. */ | |
4587 | ||
4588 | static inline bfd_boolean | |
4589 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4590 | { | |
4591 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4592 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4593 | } |
4594 | ||
4595 | /* Return true if IP is a branch-likely instruction. */ | |
4596 | ||
4597 | static inline bfd_boolean | |
4598 | branch_likely_p (const struct mips_cl_insn *ip) | |
4599 | { | |
4600 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4601 | } | |
4602 | ||
14fe068b RS |
4603 | /* Return the type of nop that should be used to fill the delay slot |
4604 | of delayed branch IP. */ | |
4605 | ||
4606 | static struct mips_cl_insn * | |
4607 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4608 | { | |
4609 | if (mips_opts.micromips | |
4610 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4611 | return µmips_nop32_insn; | |
4612 | return NOP_INSN; | |
4613 | } | |
4614 | ||
fc76e730 RS |
4615 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4616 | in operand N. */ | |
df58fc94 RS |
4617 | |
4618 | static unsigned int | |
fc76e730 | 4619 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4620 | { |
fc76e730 RS |
4621 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4622 | } | |
df58fc94 | 4623 | |
fc76e730 RS |
4624 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4625 | in operand N. */ | |
4626 | ||
4627 | static unsigned int | |
4628 | insn_write_mask (const struct mips_opcode *opcode) | |
4629 | { | |
4630 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4631 | } | |
4632 | ||
4633 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4634 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4635 | is set. */ | |
4636 | ||
4637 | static unsigned int | |
4638 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4639 | const struct mips_operand *operand, | |
4640 | unsigned int type_mask) | |
4641 | { | |
4642 | unsigned int uval, vsel; | |
4643 | ||
4644 | switch (operand->type) | |
df58fc94 | 4645 | { |
fc76e730 RS |
4646 | case OP_INT: |
4647 | case OP_MAPPED_INT: | |
4648 | case OP_MSB: | |
4649 | case OP_PCREL: | |
4650 | case OP_PERF_REG: | |
4651 | case OP_ADDIUSP_INT: | |
4652 | case OP_ENTRY_EXIT_LIST: | |
4653 | case OP_REPEAT_DEST_REG: | |
4654 | case OP_REPEAT_PREV_REG: | |
4655 | case OP_PC: | |
14daeee3 RS |
4656 | case OP_VU0_SUFFIX: |
4657 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4658 | case OP_IMM_INDEX: |
fc76e730 RS |
4659 | abort (); |
4660 | ||
25499ac7 MR |
4661 | case OP_REG28: |
4662 | return 1 << 28; | |
4663 | ||
fc76e730 | 4664 | case OP_REG: |
0f35dbc4 | 4665 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4666 | { |
4667 | const struct mips_reg_operand *reg_op; | |
4668 | ||
4669 | reg_op = (const struct mips_reg_operand *) operand; | |
4670 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4671 | return 0; | |
4672 | uval = insn_extract_operand (insn, operand); | |
4673 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4674 | } | |
4675 | ||
4676 | case OP_REG_PAIR: | |
4677 | { | |
4678 | const struct mips_reg_pair_operand *pair_op; | |
4679 | ||
4680 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4681 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4682 | return 0; | |
4683 | uval = insn_extract_operand (insn, operand); | |
4684 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4685 | } | |
4686 | ||
4687 | case OP_CLO_CLZ_DEST: | |
4688 | if (!(type_mask & (1 << OP_REG_GP))) | |
4689 | return 0; | |
4690 | uval = insn_extract_operand (insn, operand); | |
4691 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4692 | ||
7361da2c AB |
4693 | case OP_SAME_RS_RT: |
4694 | if (!(type_mask & (1 << OP_REG_GP))) | |
4695 | return 0; | |
4696 | uval = insn_extract_operand (insn, operand); | |
4697 | gas_assert ((uval & 31) == (uval >> 5)); | |
4698 | return 1 << (uval & 31); | |
4699 | ||
4700 | case OP_CHECK_PREV: | |
4701 | case OP_NON_ZERO_REG: | |
4702 | if (!(type_mask & (1 << OP_REG_GP))) | |
4703 | return 0; | |
4704 | uval = insn_extract_operand (insn, operand); | |
4705 | return 1 << (uval & 31); | |
4706 | ||
fc76e730 RS |
4707 | case OP_LWM_SWM_LIST: |
4708 | abort (); | |
4709 | ||
4710 | case OP_SAVE_RESTORE_LIST: | |
4711 | abort (); | |
4712 | ||
4713 | case OP_MDMX_IMM_REG: | |
4714 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4715 | return 0; | |
4716 | uval = insn_extract_operand (insn, operand); | |
4717 | vsel = uval >> 5; | |
4718 | if ((vsel & 0x18) == 0x18) | |
4719 | return 0; | |
4720 | return 1 << (uval & 31); | |
56d438b1 CF |
4721 | |
4722 | case OP_REG_INDEX: | |
4723 | if (!(type_mask & (1 << OP_REG_GP))) | |
4724 | return 0; | |
4725 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4726 | } |
fc76e730 RS |
4727 | abort (); |
4728 | } | |
4729 | ||
4730 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4731 | where bit N of OPNO_MASK is set if operand N should be included. | |
4732 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4733 | is set. */ | |
4734 | ||
4735 | static unsigned int | |
4736 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4737 | unsigned int type_mask, unsigned int opno_mask) | |
4738 | { | |
4739 | unsigned int opno, reg_mask; | |
4740 | ||
4741 | opno = 0; | |
4742 | reg_mask = 0; | |
4743 | while (opno_mask != 0) | |
4744 | { | |
4745 | if (opno_mask & 1) | |
4746 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4747 | opno_mask >>= 1; | |
4748 | opno += 1; | |
4749 | } | |
4750 | return reg_mask; | |
df58fc94 RS |
4751 | } |
4752 | ||
4c260379 RS |
4753 | /* Return the mask of core registers that IP reads. */ |
4754 | ||
4755 | static unsigned int | |
4756 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4757 | { | |
4758 | unsigned long pinfo, pinfo2; | |
4759 | unsigned int mask; | |
4760 | ||
fc76e730 | 4761 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4762 | pinfo = ip->insn_mo->pinfo; |
4763 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4764 | if (pinfo & INSN_UDI) |
4c260379 | 4765 | { |
fc76e730 RS |
4766 | /* UDI instructions have traditionally been assumed to read RS |
4767 | and RT. */ | |
4768 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4769 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4770 | } |
fc76e730 RS |
4771 | if (pinfo & INSN_READ_GPR_24) |
4772 | mask |= 1 << 24; | |
4773 | if (pinfo2 & INSN2_READ_GPR_16) | |
4774 | mask |= 1 << 16; | |
4775 | if (pinfo2 & INSN2_READ_SP) | |
4776 | mask |= 1 << SP; | |
26545944 | 4777 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4778 | mask |= 1 << 31; |
fe35f09f RS |
4779 | /* Don't include register 0. */ |
4780 | return mask & ~1; | |
4c260379 RS |
4781 | } |
4782 | ||
4783 | /* Return the mask of core registers that IP writes. */ | |
4784 | ||
4785 | static unsigned int | |
4786 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4787 | { | |
4788 | unsigned long pinfo, pinfo2; | |
4789 | unsigned int mask; | |
4790 | ||
fc76e730 | 4791 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4792 | pinfo = ip->insn_mo->pinfo; |
4793 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4794 | if (pinfo & INSN_WRITE_GPR_24) |
4795 | mask |= 1 << 24; | |
4796 | if (pinfo & INSN_WRITE_GPR_31) | |
4797 | mask |= 1 << 31; | |
4798 | if (pinfo & INSN_UDI) | |
4799 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4800 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4801 | if (pinfo2 & INSN2_WRITE_SP) | |
4802 | mask |= 1 << SP; | |
fe35f09f RS |
4803 | /* Don't include register 0. */ |
4804 | return mask & ~1; | |
4c260379 RS |
4805 | } |
4806 | ||
4807 | /* Return the mask of floating-point registers that IP reads. */ | |
4808 | ||
4809 | static unsigned int | |
4810 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4811 | { | |
fc76e730 | 4812 | unsigned long pinfo; |
4c260379 RS |
4813 | unsigned int mask; |
4814 | ||
9d5de888 CF |
4815 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4816 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4817 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4818 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4819 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4820 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4821 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4822 | mask |= mask << 1; |
4823 | return mask; | |
4824 | } | |
4825 | ||
4826 | /* Return the mask of floating-point registers that IP writes. */ | |
4827 | ||
4828 | static unsigned int | |
4829 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4830 | { | |
fc76e730 | 4831 | unsigned long pinfo; |
4c260379 RS |
4832 | unsigned int mask; |
4833 | ||
9d5de888 CF |
4834 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4835 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4836 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4837 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4838 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4839 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4840 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4841 | mask |= mask << 1; |
4842 | return mask; | |
4843 | } | |
4844 | ||
a1d78564 RS |
4845 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4846 | Check whether that is allowed. */ | |
4847 | ||
4848 | static bfd_boolean | |
4849 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4850 | { | |
4851 | const char *s = insn->name; | |
351cdf24 MF |
4852 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4853 | || FPR_SIZE == 64) | |
4854 | && mips_opts.oddspreg; | |
a1d78564 RS |
4855 | |
4856 | if (insn->pinfo == INSN_MACRO) | |
4857 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4858 | return TRUE; | |
4859 | ||
351cdf24 MF |
4860 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4861 | otherwise it depends on oddspreg. */ | |
4862 | if ((insn->pinfo & FP_S) | |
4863 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4864 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4865 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4866 | |
351cdf24 MF |
4867 | /* Allow odd registers for single-precision ops and double-precision if the |
4868 | floating-point registers are 64-bit wide. */ | |
4869 | switch (insn->pinfo & (FP_S | FP_D)) | |
4870 | { | |
4871 | case FP_S: | |
4872 | case 0: | |
4873 | return oddspreg; | |
4874 | case FP_D: | |
4875 | return FPR_SIZE == 64; | |
4876 | default: | |
4877 | break; | |
a1d78564 RS |
4878 | } |
4879 | ||
351cdf24 MF |
4880 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4881 | s = strchr (insn->name, '.'); | |
4882 | if (s != NULL && opnum == 2) | |
4883 | s = strchr (s + 1, '.'); | |
4884 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4885 | return oddspreg; | |
a1d78564 | 4886 | |
351cdf24 | 4887 | return FPR_SIZE == 64; |
a1d78564 RS |
4888 | } |
4889 | ||
a1d78564 RS |
4890 | /* Information about an instruction argument that we're trying to match. */ |
4891 | struct mips_arg_info | |
4892 | { | |
4893 | /* The instruction so far. */ | |
4894 | struct mips_cl_insn *insn; | |
4895 | ||
a92713e6 RS |
4896 | /* The first unconsumed operand token. */ |
4897 | struct mips_operand_token *token; | |
4898 | ||
a1d78564 RS |
4899 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4900 | int opnum; | |
4901 | ||
4902 | /* The 1-based argument number, for error reporting. This does not | |
4903 | count elided optional registers, etc.. */ | |
4904 | int argnum; | |
4905 | ||
4906 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4907 | unsigned int last_regno; | |
4908 | ||
4909 | /* If the first operand was an OP_REG, this is the register that it | |
4910 | specified, otherwise it is ILLEGAL_REG. */ | |
4911 | unsigned int dest_regno; | |
4912 | ||
4913 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4914 | where it gives the lsb position. */ | |
4915 | unsigned int last_op_int; | |
4916 | ||
60f20e8b | 4917 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4918 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4919 | possible. Match routines should not report errors if something |
4920 | is only invalid for !LAX_MATCH. */ | |
4921 | bfd_boolean lax_match; | |
a1d78564 | 4922 | |
a1d78564 RS |
4923 | /* True if a reference to the current AT register was seen. */ |
4924 | bfd_boolean seen_at; | |
4925 | }; | |
4926 | ||
1a00e612 RS |
4927 | /* Record that the argument is out of range. */ |
4928 | ||
4929 | static void | |
4930 | match_out_of_range (struct mips_arg_info *arg) | |
4931 | { | |
4932 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4933 | } | |
4934 | ||
4935 | /* Record that the argument isn't constant but needs to be. */ | |
4936 | ||
4937 | static void | |
4938 | match_not_constant (struct mips_arg_info *arg) | |
4939 | { | |
4940 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4941 | arg->argnum); | |
4942 | } | |
4943 | ||
a92713e6 RS |
4944 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4945 | and return true on success, otherwise return false. */ | |
a1d78564 | 4946 | |
a92713e6 RS |
4947 | static bfd_boolean |
4948 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4949 | { |
a92713e6 RS |
4950 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4951 | { | |
4952 | ++arg->token; | |
4953 | if (ch == ',') | |
4954 | arg->argnum += 1; | |
4955 | return TRUE; | |
4956 | } | |
4957 | return FALSE; | |
4958 | } | |
a1d78564 | 4959 | |
a92713e6 RS |
4960 | /* Try to get an expression from the next tokens in ARG. Consume the |
4961 | tokens and return true on success, storing the expression value in | |
4962 | VALUE and relocation types in R. */ | |
4963 | ||
4964 | static bfd_boolean | |
4965 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4966 | bfd_reloc_code_real_type *r) | |
4967 | { | |
d436c1c2 RS |
4968 | /* If the next token is a '(' that was parsed as being part of a base |
4969 | expression, assume we have an elided offset. The later match will fail | |
4970 | if this turns out to be wrong. */ | |
4971 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4972 | { |
d436c1c2 RS |
4973 | value->X_op = O_constant; |
4974 | value->X_add_number = 0; | |
4975 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4976 | return TRUE; |
4977 | } | |
4978 | ||
d436c1c2 RS |
4979 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4980 | For plain registers the default error seems more appropriate. */ | |
4981 | if (arg->token->type == OT_INTEGER | |
4982 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4983 | { |
d436c1c2 RS |
4984 | set_insn_error (arg->argnum, _("register value used as expression")); |
4985 | return FALSE; | |
a1d78564 | 4986 | } |
d436c1c2 RS |
4987 | |
4988 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4989 | { |
d436c1c2 RS |
4990 | *value = arg->token->u.integer.value; |
4991 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4992 | ++arg->token; | |
4993 | return TRUE; | |
a92713e6 | 4994 | } |
a92713e6 | 4995 | |
d436c1c2 RS |
4996 | set_insn_error_i |
4997 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4998 | arg->argnum); | |
4999 | return FALSE; | |
a92713e6 RS |
5000 | } |
5001 | ||
5002 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
de194d85 | 5003 | the tokens and return true on success, storing the constant value |
a54d5f8b | 5004 | in *VALUE. */ |
a92713e6 RS |
5005 | |
5006 | static bfd_boolean | |
1a00e612 | 5007 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
5008 | { |
5009 | expressionS ex; | |
5010 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 5011 | |
a92713e6 RS |
5012 | if (!match_expression (arg, &ex, r)) |
5013 | return FALSE; | |
5014 | ||
5015 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
5016 | *value = ex.X_add_number; |
5017 | else | |
5018 | { | |
c96425c5 MR |
5019 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
5020 | match_out_of_range (arg); | |
5021 | else | |
5022 | match_not_constant (arg); | |
1a00e612 | 5023 | return FALSE; |
a1d78564 | 5024 | } |
a92713e6 | 5025 | return TRUE; |
a1d78564 RS |
5026 | } |
5027 | ||
5028 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
5029 | appears in instruction OPCODE. */ | |
5030 | ||
5031 | static unsigned int | |
5032 | convert_reg_type (const struct mips_opcode *opcode, | |
5033 | enum mips_reg_operand_type type) | |
5034 | { | |
5035 | switch (type) | |
5036 | { | |
5037 | case OP_REG_GP: | |
5038 | return RTYPE_NUM | RTYPE_GP; | |
5039 | ||
5040 | case OP_REG_FP: | |
5041 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
5042 | FPR load, store or move (including moves to and from GPRs). */ | |
5043 | if ((mips_opts.ase & ASE_MDMX) | |
5044 | && (opcode->pinfo & FP_D) | |
43885403 | 5045 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 5046 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 5047 | | INSN_LOAD_COPROC |
67dc82bc | 5048 | | INSN_LOAD_MEMORY |
a1d78564 RS |
5049 | | INSN_STORE_MEMORY))) |
5050 | return RTYPE_FPU | RTYPE_VEC; | |
5051 | return RTYPE_FPU; | |
5052 | ||
5053 | case OP_REG_CCC: | |
5054 | if (opcode->pinfo & (FP_D | FP_S)) | |
5055 | return RTYPE_CCC | RTYPE_FCC; | |
5056 | return RTYPE_CCC; | |
5057 | ||
5058 | case OP_REG_VEC: | |
5059 | if (opcode->membership & INSN_5400) | |
5060 | return RTYPE_FPU; | |
5061 | return RTYPE_FPU | RTYPE_VEC; | |
5062 | ||
5063 | case OP_REG_ACC: | |
5064 | return RTYPE_ACC; | |
5065 | ||
5066 | case OP_REG_COPRO: | |
5067 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
5068 | return RTYPE_NUM | RTYPE_CP0; | |
5069 | return RTYPE_NUM; | |
5070 | ||
5071 | case OP_REG_HW: | |
5072 | return RTYPE_NUM; | |
14daeee3 RS |
5073 | |
5074 | case OP_REG_VI: | |
5075 | return RTYPE_NUM | RTYPE_VI; | |
5076 | ||
5077 | case OP_REG_VF: | |
5078 | return RTYPE_NUM | RTYPE_VF; | |
5079 | ||
5080 | case OP_REG_R5900_I: | |
5081 | return RTYPE_R5900_I; | |
5082 | ||
5083 | case OP_REG_R5900_Q: | |
5084 | return RTYPE_R5900_Q; | |
5085 | ||
5086 | case OP_REG_R5900_R: | |
5087 | return RTYPE_R5900_R; | |
5088 | ||
5089 | case OP_REG_R5900_ACC: | |
5090 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
5091 | |
5092 | case OP_REG_MSA: | |
5093 | return RTYPE_MSA; | |
5094 | ||
5095 | case OP_REG_MSA_CTRL: | |
5096 | return RTYPE_NUM; | |
a1d78564 RS |
5097 | } |
5098 | abort (); | |
5099 | } | |
5100 | ||
5101 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
5102 | ||
5103 | static void | |
5104 | check_regno (struct mips_arg_info *arg, | |
5105 | enum mips_reg_operand_type type, unsigned int regno) | |
5106 | { | |
5107 | if (AT && type == OP_REG_GP && regno == AT) | |
5108 | arg->seen_at = TRUE; | |
5109 | ||
5110 | if (type == OP_REG_FP | |
5111 | && (regno & 1) != 0 | |
a1d78564 | 5112 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
5113 | { |
5114 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
5115 | so maintain a warning for FP32 but raise an error for the new | |
5116 | cases. */ | |
5117 | if (FPR_SIZE == 32) | |
5118 | as_warn (_("float register should be even, was %d"), regno); | |
5119 | else | |
5120 | as_bad (_("float register should be even, was %d"), regno); | |
5121 | } | |
a1d78564 RS |
5122 | |
5123 | if (type == OP_REG_CCC) | |
5124 | { | |
5125 | const char *name; | |
5126 | size_t length; | |
5127 | ||
5128 | name = arg->insn->insn_mo->name; | |
5129 | length = strlen (name); | |
5130 | if ((regno & 1) != 0 | |
5131 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
5132 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 5133 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
5134 | name, regno); |
5135 | ||
5136 | if ((regno & 3) != 0 | |
5137 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 5138 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
5139 | name, regno); |
5140 | } | |
5141 | } | |
5142 | ||
a92713e6 RS |
5143 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
5144 | a register of type TYPE. Return true on success, storing the register | |
5145 | number in *REGNO and warning about any dubious uses. */ | |
5146 | ||
5147 | static bfd_boolean | |
5148 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5149 | unsigned int symval, unsigned int *regno) | |
5150 | { | |
5151 | if (type == OP_REG_VEC) | |
5152 | symval = mips_prefer_vec_regno (symval); | |
5153 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
5154 | return FALSE; | |
5155 | ||
5156 | *regno = symval & RNUM_MASK; | |
5157 | check_regno (arg, type, *regno); | |
5158 | return TRUE; | |
5159 | } | |
5160 | ||
5161 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
5162 | Consume the token and return true on success, storing the register | |
5163 | number in *REGNO. Return false on failure. */ | |
5164 | ||
5165 | static bfd_boolean | |
5166 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5167 | unsigned int *regno) | |
5168 | { | |
5169 | if (arg->token->type == OT_REG | |
5170 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5171 | { | |
5172 | ++arg->token; | |
5173 | return TRUE; | |
5174 | } | |
5175 | return FALSE; | |
5176 | } | |
5177 | ||
5178 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5179 | Consume the token and return true on success, storing the register numbers | |
5180 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5181 | ||
5182 | static bfd_boolean | |
5183 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5184 | unsigned int *regno1, unsigned int *regno2) | |
5185 | { | |
5186 | if (match_reg (arg, type, regno1)) | |
5187 | { | |
5188 | *regno2 = *regno1; | |
5189 | return TRUE; | |
5190 | } | |
5191 | if (arg->token->type == OT_REG_RANGE | |
5192 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5193 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5194 | && *regno1 <= *regno2) | |
5195 | { | |
5196 | ++arg->token; | |
5197 | return TRUE; | |
5198 | } | |
5199 | return FALSE; | |
5200 | } | |
5201 | ||
a1d78564 RS |
5202 | /* OP_INT matcher. */ |
5203 | ||
a92713e6 | 5204 | static bfd_boolean |
a1d78564 | 5205 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5206 | const struct mips_operand *operand_base) |
a1d78564 RS |
5207 | { |
5208 | const struct mips_int_operand *operand; | |
3ccad066 | 5209 | unsigned int uval; |
a1d78564 RS |
5210 | int min_val, max_val, factor; |
5211 | offsetT sval; | |
a1d78564 RS |
5212 | |
5213 | operand = (const struct mips_int_operand *) operand_base; | |
5214 | factor = 1 << operand->shift; | |
3ccad066 RS |
5215 | min_val = mips_int_operand_min (operand); |
5216 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5217 | |
d436c1c2 RS |
5218 | if (operand_base->lsb == 0 |
5219 | && operand_base->size == 16 | |
5220 | && operand->shift == 0 | |
5221 | && operand->bias == 0 | |
5222 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5223 | { |
5224 | /* The operand can be relocated. */ | |
a92713e6 RS |
5225 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5226 | return FALSE; | |
5227 | ||
c96425c5 MR |
5228 | if (offset_expr.X_op == O_big) |
5229 | { | |
5230 | match_out_of_range (arg); | |
5231 | return FALSE; | |
5232 | } | |
5233 | ||
a92713e6 | 5234 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
33eaf5de | 5235 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5236 | leave the relocation value in offset_expr and offset_relocs |
5237 | for the caller to process. */ | |
a92713e6 RS |
5238 | return TRUE; |
5239 | ||
5240 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5241 | { |
60f20e8b RS |
5242 | /* Accept non-constant operands if no later alternative matches, |
5243 | leaving it for the caller to process. */ | |
5244 | if (!arg->lax_match) | |
602b88e3 MR |
5245 | { |
5246 | match_not_constant (arg); | |
5247 | return FALSE; | |
5248 | } | |
a92713e6 RS |
5249 | offset_reloc[0] = BFD_RELOC_LO16; |
5250 | return TRUE; | |
a1d78564 | 5251 | } |
a92713e6 | 5252 | |
a1d78564 RS |
5253 | /* Clear the global state; we're going to install the operand |
5254 | ourselves. */ | |
a92713e6 | 5255 | sval = offset_expr.X_add_number; |
a1d78564 | 5256 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5257 | |
5258 | /* For compatibility with older assemblers, we accept | |
5259 | 0x8000-0xffff as signed 16-bit numbers when only | |
5260 | signed numbers are allowed. */ | |
5261 | if (sval > max_val) | |
5262 | { | |
5263 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5264 | if (!arg->lax_match && sval <= max_val) | |
20c59b84 MR |
5265 | { |
5266 | match_out_of_range (arg); | |
5267 | return FALSE; | |
5268 | } | |
60f20e8b | 5269 | } |
a1d78564 RS |
5270 | } |
5271 | else | |
5272 | { | |
1a00e612 | 5273 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5274 | return FALSE; |
a1d78564 RS |
5275 | } |
5276 | ||
5277 | arg->last_op_int = sval; | |
5278 | ||
1a00e612 | 5279 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5280 | { |
1a00e612 RS |
5281 | match_out_of_range (arg); |
5282 | return FALSE; | |
a1d78564 RS |
5283 | } |
5284 | ||
5285 | uval = (unsigned int) sval >> operand->shift; | |
5286 | uval -= operand->bias; | |
5287 | ||
5288 | /* Handle -mfix-cn63xxp1. */ | |
5289 | if (arg->opnum == 1 | |
5290 | && mips_fix_cn63xxp1 | |
5291 | && !mips_opts.micromips | |
5292 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5293 | switch (uval) | |
5294 | { | |
5295 | case 5: | |
5296 | case 25: | |
5297 | case 26: | |
5298 | case 27: | |
5299 | case 28: | |
5300 | case 29: | |
5301 | case 30: | |
5302 | case 31: | |
5303 | /* These are ok. */ | |
5304 | break; | |
5305 | ||
5306 | default: | |
5307 | /* The rest must be changed to 28. */ | |
5308 | uval = 28; | |
5309 | break; | |
5310 | } | |
5311 | ||
5312 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5313 | return TRUE; |
a1d78564 RS |
5314 | } |
5315 | ||
5316 | /* OP_MAPPED_INT matcher. */ | |
5317 | ||
a92713e6 | 5318 | static bfd_boolean |
a1d78564 | 5319 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5320 | const struct mips_operand *operand_base) |
a1d78564 RS |
5321 | { |
5322 | const struct mips_mapped_int_operand *operand; | |
5323 | unsigned int uval, num_vals; | |
5324 | offsetT sval; | |
5325 | ||
5326 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5327 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5328 | return FALSE; |
a1d78564 RS |
5329 | |
5330 | num_vals = 1 << operand_base->size; | |
5331 | for (uval = 0; uval < num_vals; uval++) | |
5332 | if (operand->int_map[uval] == sval) | |
5333 | break; | |
5334 | if (uval == num_vals) | |
1a00e612 RS |
5335 | { |
5336 | match_out_of_range (arg); | |
5337 | return FALSE; | |
5338 | } | |
a1d78564 RS |
5339 | |
5340 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5341 | return TRUE; |
a1d78564 RS |
5342 | } |
5343 | ||
5344 | /* OP_MSB matcher. */ | |
5345 | ||
a92713e6 | 5346 | static bfd_boolean |
a1d78564 | 5347 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5348 | const struct mips_operand *operand_base) |
a1d78564 RS |
5349 | { |
5350 | const struct mips_msb_operand *operand; | |
5351 | int min_val, max_val, max_high; | |
5352 | offsetT size, sval, high; | |
5353 | ||
5354 | operand = (const struct mips_msb_operand *) operand_base; | |
5355 | min_val = operand->bias; | |
5356 | max_val = min_val + (1 << operand_base->size) - 1; | |
5357 | max_high = operand->opsize; | |
5358 | ||
1a00e612 | 5359 | if (!match_const_int (arg, &size)) |
a92713e6 | 5360 | return FALSE; |
a1d78564 RS |
5361 | |
5362 | high = size + arg->last_op_int; | |
5363 | sval = operand->add_lsb ? high : size; | |
5364 | ||
5365 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5366 | { | |
1a00e612 RS |
5367 | match_out_of_range (arg); |
5368 | return FALSE; | |
a1d78564 RS |
5369 | } |
5370 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5371 | return TRUE; |
a1d78564 RS |
5372 | } |
5373 | ||
5374 | /* OP_REG matcher. */ | |
5375 | ||
a92713e6 | 5376 | static bfd_boolean |
a1d78564 | 5377 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5378 | const struct mips_operand *operand_base) |
a1d78564 RS |
5379 | { |
5380 | const struct mips_reg_operand *operand; | |
a92713e6 | 5381 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5382 | |
5383 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5384 | if (!match_reg (arg, operand->reg_type, ®no)) |
5385 | return FALSE; | |
a1d78564 RS |
5386 | |
5387 | if (operand->reg_map) | |
5388 | { | |
5389 | num_vals = 1 << operand->root.size; | |
5390 | for (uval = 0; uval < num_vals; uval++) | |
5391 | if (operand->reg_map[uval] == regno) | |
5392 | break; | |
5393 | if (num_vals == uval) | |
a92713e6 | 5394 | return FALSE; |
a1d78564 RS |
5395 | } |
5396 | else | |
5397 | uval = regno; | |
5398 | ||
a1d78564 RS |
5399 | arg->last_regno = regno; |
5400 | if (arg->opnum == 1) | |
5401 | arg->dest_regno = regno; | |
5402 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5403 | return TRUE; |
a1d78564 RS |
5404 | } |
5405 | ||
5406 | /* OP_REG_PAIR matcher. */ | |
5407 | ||
a92713e6 | 5408 | static bfd_boolean |
a1d78564 | 5409 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5410 | const struct mips_operand *operand_base) |
a1d78564 RS |
5411 | { |
5412 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5413 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5414 | |
5415 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5416 | if (!match_reg (arg, operand->reg_type, ®no1) |
5417 | || !match_char (arg, ',') | |
5418 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5419 | return FALSE; | |
a1d78564 RS |
5420 | |
5421 | num_vals = 1 << operand_base->size; | |
5422 | for (uval = 0; uval < num_vals; uval++) | |
5423 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5424 | break; | |
5425 | if (uval == num_vals) | |
a92713e6 | 5426 | return FALSE; |
a1d78564 | 5427 | |
a1d78564 | 5428 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5429 | return TRUE; |
a1d78564 RS |
5430 | } |
5431 | ||
5432 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5433 | ||
a92713e6 RS |
5434 | static bfd_boolean |
5435 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5436 | { |
a92713e6 RS |
5437 | bfd_reloc_code_real_type r[3]; |
5438 | ||
5439 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5440 | } |
5441 | ||
5442 | /* OP_PERF_REG matcher. */ | |
5443 | ||
a92713e6 | 5444 | static bfd_boolean |
a1d78564 | 5445 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5446 | const struct mips_operand *operand) |
a1d78564 RS |
5447 | { |
5448 | offsetT sval; | |
5449 | ||
1a00e612 | 5450 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5451 | return FALSE; |
a1d78564 RS |
5452 | |
5453 | if (sval != 0 | |
5454 | && (sval != 1 | |
5455 | || (mips_opts.arch == CPU_R5900 | |
5456 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5457 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5458 | { | |
1a00e612 RS |
5459 | set_insn_error (arg->argnum, _("invalid performance register")); |
5460 | return FALSE; | |
a1d78564 RS |
5461 | } |
5462 | ||
5463 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5464 | return TRUE; |
a1d78564 RS |
5465 | } |
5466 | ||
5467 | /* OP_ADDIUSP matcher. */ | |
5468 | ||
a92713e6 | 5469 | static bfd_boolean |
a1d78564 | 5470 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5471 | const struct mips_operand *operand) |
a1d78564 RS |
5472 | { |
5473 | offsetT sval; | |
5474 | unsigned int uval; | |
5475 | ||
1a00e612 | 5476 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5477 | return FALSE; |
a1d78564 RS |
5478 | |
5479 | if (sval % 4) | |
1a00e612 RS |
5480 | { |
5481 | match_out_of_range (arg); | |
5482 | return FALSE; | |
5483 | } | |
a1d78564 RS |
5484 | |
5485 | sval /= 4; | |
5486 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5487 | { |
5488 | match_out_of_range (arg); | |
5489 | return FALSE; | |
5490 | } | |
a1d78564 RS |
5491 | |
5492 | uval = (unsigned int) sval; | |
5493 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5494 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5495 | return TRUE; |
a1d78564 RS |
5496 | } |
5497 | ||
5498 | /* OP_CLO_CLZ_DEST matcher. */ | |
5499 | ||
a92713e6 | 5500 | static bfd_boolean |
a1d78564 | 5501 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5502 | const struct mips_operand *operand) |
a1d78564 RS |
5503 | { |
5504 | unsigned int regno; | |
5505 | ||
a92713e6 RS |
5506 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5507 | return FALSE; | |
a1d78564 | 5508 | |
a1d78564 | 5509 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5510 | return TRUE; |
a1d78564 RS |
5511 | } |
5512 | ||
7361da2c AB |
5513 | /* OP_CHECK_PREV matcher. */ |
5514 | ||
5515 | static bfd_boolean | |
5516 | match_check_prev_operand (struct mips_arg_info *arg, | |
5517 | const struct mips_operand *operand_base) | |
5518 | { | |
5519 | const struct mips_check_prev_operand *operand; | |
5520 | unsigned int regno; | |
5521 | ||
5522 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5523 | ||
5524 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5525 | return FALSE; | |
5526 | ||
5527 | if (!operand->zero_ok && regno == 0) | |
5528 | return FALSE; | |
5529 | ||
5530 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5531 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5532 | || (operand->equal_ok && regno == arg->last_regno)) | |
5533 | { | |
5534 | arg->last_regno = regno; | |
5535 | insn_insert_operand (arg->insn, operand_base, regno); | |
5536 | return TRUE; | |
5537 | } | |
5538 | ||
5539 | return FALSE; | |
5540 | } | |
5541 | ||
5542 | /* OP_SAME_RS_RT matcher. */ | |
5543 | ||
5544 | static bfd_boolean | |
5545 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5546 | const struct mips_operand *operand) | |
5547 | { | |
5548 | unsigned int regno; | |
5549 | ||
5550 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5551 | return FALSE; | |
5552 | ||
5553 | if (regno == 0) | |
5554 | { | |
5555 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5556 | return FALSE; | |
5557 | } | |
5558 | ||
5559 | arg->last_regno = regno; | |
5560 | ||
5561 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5562 | return TRUE; | |
5563 | } | |
5564 | ||
a1d78564 RS |
5565 | /* OP_LWM_SWM_LIST matcher. */ |
5566 | ||
a92713e6 | 5567 | static bfd_boolean |
a1d78564 | 5568 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5569 | const struct mips_operand *operand) |
a1d78564 | 5570 | { |
a92713e6 RS |
5571 | unsigned int reglist, sregs, ra, regno1, regno2; |
5572 | struct mips_arg_info reset; | |
a1d78564 | 5573 | |
a92713e6 RS |
5574 | reglist = 0; |
5575 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5576 | return FALSE; | |
5577 | do | |
5578 | { | |
5579 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5580 | { | |
5581 | reglist |= 1 << FP; | |
5582 | regno2 = S7; | |
5583 | } | |
5584 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5585 | reset = *arg; | |
5586 | } | |
5587 | while (match_char (arg, ',') | |
5588 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5589 | *arg = reset; | |
a1d78564 RS |
5590 | |
5591 | if (operand->size == 2) | |
5592 | { | |
5593 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5594 | ||
5595 | s0, ra | |
5596 | s0, s1, ra, s2, s3 | |
5597 | s0-s2, ra | |
5598 | ||
5599 | and any permutations of these. */ | |
5600 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5601 | return FALSE; |
a1d78564 RS |
5602 | |
5603 | sregs = (reglist >> 17) & 7; | |
5604 | ra = 0; | |
5605 | } | |
5606 | else | |
5607 | { | |
5608 | /* The list must include at least one of ra and s0-sN, | |
5609 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5610 | which are $23 and $30 respectively.) E.g.: | |
5611 | ||
5612 | ra | |
5613 | s0 | |
5614 | ra, s0, s1, s2 | |
5615 | s0-s8 | |
5616 | s0-s5, ra | |
5617 | ||
5618 | and any permutations of these. */ | |
5619 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5620 | return FALSE; |
a1d78564 RS |
5621 | |
5622 | ra = (reglist >> 27) & 0x10; | |
5623 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5624 | } | |
5625 | sregs += 1; | |
5626 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5627 | return FALSE; |
a1d78564 RS |
5628 | |
5629 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5630 | return TRUE; |
a1d78564 RS |
5631 | } |
5632 | ||
364215c8 RS |
5633 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5634 | ||
a92713e6 | 5635 | static unsigned int |
364215c8 | 5636 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5637 | const struct mips_operand *operand) |
364215c8 RS |
5638 | { |
5639 | unsigned int mask; | |
5640 | bfd_boolean is_exit; | |
5641 | ||
5642 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5643 | are different. */ | |
5644 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5645 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5646 | do |
364215c8 RS |
5647 | { |
5648 | unsigned int regno1, regno2; | |
5649 | bfd_boolean is_freg; | |
5650 | ||
a92713e6 | 5651 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5652 | is_freg = FALSE; |
a92713e6 | 5653 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5654 | is_freg = TRUE; |
5655 | else | |
a92713e6 | 5656 | return FALSE; |
364215c8 RS |
5657 | |
5658 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5659 | { | |
5660 | mask &= ~(7 << 3); | |
5661 | mask |= (5 + regno2) << 3; | |
5662 | } | |
5663 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5664 | mask |= (regno2 - 3) << 3; | |
5665 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5666 | mask |= (regno2 - 15) << 1; | |
5667 | else if (regno1 == RA && regno2 == RA) | |
5668 | mask |= 1; | |
5669 | else | |
a92713e6 | 5670 | return FALSE; |
364215c8 | 5671 | } |
a92713e6 RS |
5672 | while (match_char (arg, ',')); |
5673 | ||
364215c8 | 5674 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5675 | return TRUE; |
364215c8 RS |
5676 | } |
5677 | ||
38bf472a MR |
5678 | /* Encode regular MIPS SAVE/RESTORE instruction operands according to |
5679 | the argument register mask AMASK, the number of static registers | |
5680 | saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5681 | respectively, and the frame size FRAME_SIZE. */ | |
5682 | ||
5683 | static unsigned int | |
5684 | mips_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5685 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5686 | unsigned int frame_size) | |
5687 | { | |
5688 | return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15) | |
5689 | | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6)); | |
5690 | } | |
5691 | ||
5692 | /* Encode MIPS16 SAVE/RESTORE instruction operands according to the | |
5693 | argument register mask AMASK, the number of static registers saved | |
5694 | NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5695 | respectively, and the frame size FRAME_SIZE. */ | |
5696 | ||
5697 | static unsigned int | |
5698 | mips16_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5699 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5700 | unsigned int frame_size) | |
5701 | { | |
5702 | unsigned int args; | |
5703 | ||
5704 | args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf); | |
5705 | if (nsreg || amask || frame_size == 0 || frame_size > 16) | |
5706 | args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16) | |
5707 | | ((frame_size & 0xf0) << 16)); | |
5708 | return args; | |
5709 | } | |
5710 | ||
364215c8 RS |
5711 | /* OP_SAVE_RESTORE_LIST matcher. */ |
5712 | ||
a92713e6 RS |
5713 | static bfd_boolean |
5714 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5715 | { |
5716 | unsigned int opcode, args, statics, sregs; | |
5717 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
38bf472a | 5718 | unsigned int arg_mask, ra, s0, s1; |
364215c8 | 5719 | offsetT frame_size; |
364215c8 | 5720 | |
364215c8 RS |
5721 | opcode = arg->insn->insn_opcode; |
5722 | frame_size = 0; | |
5723 | num_frame_sizes = 0; | |
5724 | args = 0; | |
5725 | statics = 0; | |
5726 | sregs = 0; | |
38bf472a MR |
5727 | ra = 0; |
5728 | s0 = 0; | |
5729 | s1 = 0; | |
a92713e6 | 5730 | do |
364215c8 RS |
5731 | { |
5732 | unsigned int regno1, regno2; | |
5733 | ||
a92713e6 | 5734 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5735 | { |
5736 | /* Handle the frame size. */ | |
1a00e612 | 5737 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5738 | return FALSE; |
364215c8 | 5739 | num_frame_sizes += 1; |
364215c8 RS |
5740 | } |
5741 | else | |
5742 | { | |
a92713e6 RS |
5743 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5744 | return FALSE; | |
364215c8 RS |
5745 | |
5746 | while (regno1 <= regno2) | |
5747 | { | |
5748 | if (regno1 >= 4 && regno1 <= 7) | |
5749 | { | |
5750 | if (num_frame_sizes == 0) | |
5751 | /* args $a0-$a3 */ | |
5752 | args |= 1 << (regno1 - 4); | |
5753 | else | |
5754 | /* statics $a0-$a3 */ | |
5755 | statics |= 1 << (regno1 - 4); | |
5756 | } | |
5757 | else if (regno1 >= 16 && regno1 <= 23) | |
5758 | /* $s0-$s7 */ | |
5759 | sregs |= 1 << (regno1 - 16); | |
5760 | else if (regno1 == 30) | |
5761 | /* $s8 */ | |
5762 | sregs |= 1 << 8; | |
5763 | else if (regno1 == 31) | |
5764 | /* Add $ra to insn. */ | |
38bf472a | 5765 | ra = 1; |
364215c8 | 5766 | else |
a92713e6 | 5767 | return FALSE; |
364215c8 RS |
5768 | regno1 += 1; |
5769 | if (regno1 == 24) | |
5770 | regno1 = 30; | |
5771 | } | |
5772 | } | |
364215c8 | 5773 | } |
a92713e6 | 5774 | while (match_char (arg, ',')); |
364215c8 RS |
5775 | |
5776 | /* Encode args/statics combination. */ | |
5777 | if (args & statics) | |
a92713e6 | 5778 | return FALSE; |
364215c8 RS |
5779 | else if (args == 0xf) |
5780 | /* All $a0-$a3 are args. */ | |
38bf472a | 5781 | arg_mask = MIPS_SVRS_ALL_ARGS; |
364215c8 RS |
5782 | else if (statics == 0xf) |
5783 | /* All $a0-$a3 are statics. */ | |
38bf472a | 5784 | arg_mask = MIPS_SVRS_ALL_STATICS; |
364215c8 RS |
5785 | else |
5786 | { | |
5787 | /* Count arg registers. */ | |
5788 | num_args = 0; | |
5789 | while (args & 0x1) | |
5790 | { | |
5791 | args >>= 1; | |
5792 | num_args += 1; | |
5793 | } | |
5794 | if (args != 0) | |
a92713e6 | 5795 | return FALSE; |
364215c8 RS |
5796 | |
5797 | /* Count static registers. */ | |
5798 | num_statics = 0; | |
5799 | while (statics & 0x8) | |
5800 | { | |
5801 | statics = (statics << 1) & 0xf; | |
5802 | num_statics += 1; | |
5803 | } | |
5804 | if (statics != 0) | |
a92713e6 | 5805 | return FALSE; |
364215c8 RS |
5806 | |
5807 | /* Encode args/statics. */ | |
38bf472a | 5808 | arg_mask = (num_args << 2) | num_statics; |
364215c8 RS |
5809 | } |
5810 | ||
5811 | /* Encode $s0/$s1. */ | |
5812 | if (sregs & (1 << 0)) /* $s0 */ | |
38bf472a | 5813 | s0 = 1; |
364215c8 | 5814 | if (sregs & (1 << 1)) /* $s1 */ |
38bf472a | 5815 | s1 = 1; |
364215c8 RS |
5816 | sregs >>= 2; |
5817 | ||
5818 | /* Encode $s2-$s8. */ | |
5819 | num_sregs = 0; | |
5820 | while (sregs & 1) | |
5821 | { | |
5822 | sregs >>= 1; | |
5823 | num_sregs += 1; | |
5824 | } | |
5825 | if (sregs != 0) | |
a92713e6 | 5826 | return FALSE; |
364215c8 RS |
5827 | |
5828 | /* Encode frame size. */ | |
5829 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5830 | { |
5831 | set_insn_error (arg->argnum, _("missing frame size")); | |
5832 | return FALSE; | |
5833 | } | |
5834 | if (num_frame_sizes > 1) | |
5835 | { | |
5836 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5837 | return FALSE; | |
5838 | } | |
5839 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5840 | { | |
5841 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5842 | return FALSE; | |
5843 | } | |
38bf472a | 5844 | frame_size /= 8; |
364215c8 | 5845 | |
364215c8 | 5846 | /* Finally build the instruction. */ |
38bf472a MR |
5847 | if (mips_opts.mips16) |
5848 | opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5849 | frame_size); | |
5850 | else if (!mips_opts.micromips) | |
5851 | opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5852 | frame_size); | |
5853 | else | |
5854 | abort (); | |
5855 | ||
364215c8 | 5856 | arg->insn->insn_opcode = opcode; |
a92713e6 | 5857 | return TRUE; |
364215c8 RS |
5858 | } |
5859 | ||
a1d78564 RS |
5860 | /* OP_MDMX_IMM_REG matcher. */ |
5861 | ||
a92713e6 | 5862 | static bfd_boolean |
a1d78564 | 5863 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5864 | const struct mips_operand *operand) |
a1d78564 | 5865 | { |
a92713e6 | 5866 | unsigned int regno, uval; |
a1d78564 RS |
5867 | bfd_boolean is_qh; |
5868 | const struct mips_opcode *opcode; | |
5869 | ||
5870 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5871 | instruction. Start out with that bit in place. */ | |
5872 | opcode = arg->insn->insn_mo; | |
5873 | uval = mips_extract_operand (operand, opcode->match); | |
5874 | is_qh = (uval != 0); | |
5875 | ||
56d438b1 | 5876 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5877 | { |
5878 | if ((opcode->membership & INSN_5400) | |
5879 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5880 | { | |
1a00e612 RS |
5881 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5882 | arg->argnum); | |
5883 | return FALSE; | |
a1d78564 RS |
5884 | } |
5885 | ||
56d438b1 CF |
5886 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5887 | return FALSE; | |
5888 | ++arg->token; | |
5889 | ||
a1d78564 RS |
5890 | /* Check whether this is a vector register or a broadcast of |
5891 | a single element. */ | |
56d438b1 | 5892 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5893 | { |
56d438b1 | 5894 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5895 | { |
1a00e612 RS |
5896 | set_insn_error (arg->argnum, _("invalid element selector")); |
5897 | return FALSE; | |
a1d78564 | 5898 | } |
56d438b1 CF |
5899 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5900 | ++arg->token; | |
a1d78564 RS |
5901 | } |
5902 | else | |
5903 | { | |
5904 | /* A full vector. */ | |
5905 | if ((opcode->membership & INSN_5400) | |
5906 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5907 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5908 | { | |
1a00e612 RS |
5909 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5910 | arg->argnum); | |
5911 | return FALSE; | |
a1d78564 RS |
5912 | } |
5913 | ||
5914 | if (is_qh) | |
5915 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5916 | else | |
5917 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5918 | } | |
a1d78564 RS |
5919 | uval |= regno; |
5920 | } | |
5921 | else | |
5922 | { | |
5923 | offsetT sval; | |
5924 | ||
1a00e612 | 5925 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5926 | return FALSE; |
a1d78564 RS |
5927 | if (sval < 0 || sval > 31) |
5928 | { | |
1a00e612 RS |
5929 | match_out_of_range (arg); |
5930 | return FALSE; | |
a1d78564 RS |
5931 | } |
5932 | uval |= (sval & 31); | |
5933 | if (is_qh) | |
5934 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5935 | else | |
5936 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5937 | } | |
5938 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5939 | return TRUE; |
a1d78564 RS |
5940 | } |
5941 | ||
56d438b1 CF |
5942 | /* OP_IMM_INDEX matcher. */ |
5943 | ||
5944 | static bfd_boolean | |
5945 | match_imm_index_operand (struct mips_arg_info *arg, | |
5946 | const struct mips_operand *operand) | |
5947 | { | |
5948 | unsigned int max_val; | |
5949 | ||
5950 | if (arg->token->type != OT_INTEGER_INDEX) | |
5951 | return FALSE; | |
5952 | ||
5953 | max_val = (1 << operand->size) - 1; | |
5954 | if (arg->token->u.index > max_val) | |
5955 | { | |
5956 | match_out_of_range (arg); | |
5957 | return FALSE; | |
5958 | } | |
5959 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5960 | ++arg->token; | |
5961 | return TRUE; | |
5962 | } | |
5963 | ||
5964 | /* OP_REG_INDEX matcher. */ | |
5965 | ||
5966 | static bfd_boolean | |
5967 | match_reg_index_operand (struct mips_arg_info *arg, | |
5968 | const struct mips_operand *operand) | |
5969 | { | |
5970 | unsigned int regno; | |
5971 | ||
5972 | if (arg->token->type != OT_REG_INDEX) | |
5973 | return FALSE; | |
5974 | ||
5975 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5976 | return FALSE; | |
5977 | ||
5978 | insn_insert_operand (arg->insn, operand, regno); | |
5979 | ++arg->token; | |
5980 | return TRUE; | |
5981 | } | |
5982 | ||
a1d78564 RS |
5983 | /* OP_PC matcher. */ |
5984 | ||
a92713e6 RS |
5985 | static bfd_boolean |
5986 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5987 | { |
a92713e6 RS |
5988 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5989 | { | |
5990 | ++arg->token; | |
5991 | return TRUE; | |
5992 | } | |
5993 | return FALSE; | |
a1d78564 RS |
5994 | } |
5995 | ||
25499ac7 MR |
5996 | /* OP_REG28 matcher. */ |
5997 | ||
5998 | static bfd_boolean | |
5999 | match_reg28_operand (struct mips_arg_info *arg) | |
6000 | { | |
6001 | unsigned int regno; | |
6002 | ||
6003 | if (arg->token->type == OT_REG | |
6004 | && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) | |
6005 | && regno == GP) | |
6006 | { | |
6007 | ++arg->token; | |
6008 | return TRUE; | |
6009 | } | |
6010 | return FALSE; | |
6011 | } | |
6012 | ||
7361da2c AB |
6013 | /* OP_NON_ZERO_REG matcher. */ |
6014 | ||
6015 | static bfd_boolean | |
6016 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
6017 | const struct mips_operand *operand) | |
6018 | { | |
6019 | unsigned int regno; | |
6020 | ||
6021 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
6022 | return FALSE; | |
6023 | ||
6024 | if (regno == 0) | |
85bec12d MF |
6025 | { |
6026 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
6027 | return FALSE; | |
6028 | } | |
7361da2c AB |
6029 | |
6030 | arg->last_regno = regno; | |
6031 | insn_insert_operand (arg->insn, operand, regno); | |
6032 | return TRUE; | |
6033 | } | |
6034 | ||
a1d78564 RS |
6035 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
6036 | register that we need to match. */ | |
6037 | ||
a92713e6 RS |
6038 | static bfd_boolean |
6039 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
6040 | { |
6041 | unsigned int regno; | |
6042 | ||
a92713e6 | 6043 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
6044 | } |
6045 | ||
33f46696 MR |
6046 | /* Try to match a floating-point constant from ARG for LI.S or LI.D. |
6047 | LENGTH is the length of the value in bytes (4 for float, 8 for double) | |
6048 | and USING_GPRS says whether the destination is a GPR rather than an FPR. | |
89565f1b RS |
6049 | |
6050 | Return the constant in IMM and OFFSET as follows: | |
6051 | ||
6052 | - If the constant should be loaded via memory, set IMM to O_absent and | |
6053 | OFFSET to the memory address. | |
6054 | ||
6055 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
6056 | set IMM to the O_constant to load into the high register and OFFSET | |
6057 | to the corresponding value for the low register. | |
6058 | ||
6059 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
6060 | ||
6061 | These constants only appear as the last operand in an instruction, | |
6062 | and every instruction that accepts them in any variant accepts them | |
6063 | in all variants. This means we don't have to worry about backing out | |
6064 | any changes if the instruction does not match. We just match | |
6065 | unconditionally and report an error if the constant is invalid. */ | |
6066 | ||
a92713e6 RS |
6067 | static bfd_boolean |
6068 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
6069 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 6070 | { |
a92713e6 | 6071 | char *p; |
89565f1b RS |
6072 | segT seg, new_seg; |
6073 | subsegT subseg; | |
6074 | const char *newname; | |
a92713e6 | 6075 | unsigned char *data; |
89565f1b RS |
6076 | |
6077 | /* Where the constant is placed is based on how the MIPS assembler | |
6078 | does things: | |
6079 | ||
6080 | length == 4 && using_gprs -- immediate value only | |
6081 | length == 8 && using_gprs -- .rdata or immediate value | |
6082 | length == 4 && !using_gprs -- .lit4 or immediate value | |
6083 | length == 8 && !using_gprs -- .lit8 or immediate value | |
6084 | ||
6085 | The .lit4 and .lit8 sections are only used if permitted by the | |
6086 | -G argument. */ | |
a92713e6 | 6087 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
6088 | { |
6089 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
6090 | return FALSE; | |
6091 | } | |
a92713e6 RS |
6092 | |
6093 | gas_assert (arg->token->u.flt.length == length); | |
6094 | data = arg->token->u.flt.data; | |
6095 | ++arg->token; | |
89565f1b RS |
6096 | |
6097 | /* Handle 32-bit constants for which an immediate value is best. */ | |
6098 | if (length == 4 | |
6099 | && (using_gprs | |
6100 | || g_switch_value < 4 | |
6101 | || (data[0] == 0 && data[1] == 0) | |
6102 | || (data[2] == 0 && data[3] == 0))) | |
6103 | { | |
6104 | imm->X_op = O_constant; | |
6105 | if (!target_big_endian) | |
6106 | imm->X_add_number = bfd_getl32 (data); | |
6107 | else | |
6108 | imm->X_add_number = bfd_getb32 (data); | |
6109 | offset->X_op = O_absent; | |
a92713e6 | 6110 | return TRUE; |
89565f1b RS |
6111 | } |
6112 | ||
6113 | /* Handle 64-bit constants for which an immediate value is best. */ | |
6114 | if (length == 8 | |
6115 | && !mips_disable_float_construction | |
351cdf24 MF |
6116 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
6117 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
6118 | Unlike most tests for 32-bit floating-point registers this check | |
6119 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
6120 | permit 64-bit moves without MXHC1. | |
6121 | Force the constant into memory otherwise. */ | |
6122 | && (using_gprs | |
6123 | || GPR_SIZE == 64 | |
6124 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
6125 | || FPR_SIZE == 32) | |
89565f1b RS |
6126 | && ((data[0] == 0 && data[1] == 0) |
6127 | || (data[2] == 0 && data[3] == 0)) | |
6128 | && ((data[4] == 0 && data[5] == 0) | |
6129 | || (data[6] == 0 && data[7] == 0))) | |
6130 | { | |
6131 | /* The value is simple enough to load with a couple of instructions. | |
6132 | If using 32-bit registers, set IMM to the high order 32 bits and | |
6133 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
6134 | 64 bit constant. */ | |
351cdf24 | 6135 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
6136 | { |
6137 | imm->X_op = O_constant; | |
6138 | offset->X_op = O_constant; | |
6139 | if (!target_big_endian) | |
6140 | { | |
6141 | imm->X_add_number = bfd_getl32 (data + 4); | |
6142 | offset->X_add_number = bfd_getl32 (data); | |
6143 | } | |
6144 | else | |
6145 | { | |
6146 | imm->X_add_number = bfd_getb32 (data); | |
6147 | offset->X_add_number = bfd_getb32 (data + 4); | |
6148 | } | |
6149 | if (offset->X_add_number == 0) | |
6150 | offset->X_op = O_absent; | |
6151 | } | |
6152 | else | |
6153 | { | |
6154 | imm->X_op = O_constant; | |
6155 | if (!target_big_endian) | |
6156 | imm->X_add_number = bfd_getl64 (data); | |
6157 | else | |
6158 | imm->X_add_number = bfd_getb64 (data); | |
6159 | offset->X_op = O_absent; | |
6160 | } | |
a92713e6 | 6161 | return TRUE; |
89565f1b RS |
6162 | } |
6163 | ||
6164 | /* Switch to the right section. */ | |
6165 | seg = now_seg; | |
6166 | subseg = now_subseg; | |
6167 | if (length == 4) | |
6168 | { | |
6169 | gas_assert (!using_gprs && g_switch_value >= 4); | |
6170 | newname = ".lit4"; | |
6171 | } | |
6172 | else | |
6173 | { | |
6174 | if (using_gprs || g_switch_value < 8) | |
6175 | newname = RDATA_SECTION_NAME; | |
6176 | else | |
6177 | newname = ".lit8"; | |
6178 | } | |
6179 | ||
6180 | new_seg = subseg_new (newname, (subsegT) 0); | |
fd361982 | 6181 | bfd_set_section_flags (new_seg, |
89565f1b RS |
6182 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); |
6183 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
6184 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
6185 | record_alignment (new_seg, 4); | |
6186 | else | |
6187 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
6188 | if (seg == now_seg) | |
1661c76c | 6189 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
6190 | |
6191 | /* Set the argument to the current address in the section. */ | |
6192 | imm->X_op = O_absent; | |
6193 | offset->X_op = O_symbol; | |
6194 | offset->X_add_symbol = symbol_temp_new_now (); | |
6195 | offset->X_add_number = 0; | |
6196 | ||
6197 | /* Put the floating point number into the section. */ | |
6198 | p = frag_more (length); | |
6199 | memcpy (p, data, length); | |
6200 | ||
6201 | /* Switch back to the original section. */ | |
6202 | subseg_set (seg, subseg); | |
a92713e6 | 6203 | return TRUE; |
89565f1b RS |
6204 | } |
6205 | ||
14daeee3 RS |
6206 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
6207 | them. */ | |
6208 | ||
6209 | static bfd_boolean | |
6210 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
6211 | const struct mips_operand *operand, | |
6212 | bfd_boolean match_p) | |
6213 | { | |
6214 | unsigned int uval; | |
6215 | ||
6216 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
6217 | (with X being 0). */ | |
6218 | gas_assert (operand->size == 2 || operand->size == 4); | |
6219 | ||
ee5734f0 | 6220 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 6221 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 6222 | return match_p; |
14daeee3 RS |
6223 | |
6224 | uval = arg->token->u.channels; | |
6225 | if (operand->size == 2) | |
6226 | { | |
6227 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
6228 | if ((uval & -uval) != uval) | |
6229 | return FALSE; | |
6230 | uval = 4 - ffs (uval); | |
6231 | } | |
6232 | ||
6233 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6234 | return FALSE; | |
6235 | ||
6236 | ++arg->token; | |
6237 | if (!match_p) | |
6238 | insn_insert_operand (arg->insn, operand, uval); | |
6239 | return TRUE; | |
6240 | } | |
6241 | ||
33f46696 MR |
6242 | /* Try to match a token from ARG against OPERAND. Consume the token |
6243 | and return true on success, otherwise return false. */ | |
a1d78564 | 6244 | |
a92713e6 | 6245 | static bfd_boolean |
a1d78564 | 6246 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6247 | const struct mips_operand *operand) |
a1d78564 RS |
6248 | { |
6249 | switch (operand->type) | |
6250 | { | |
6251 | case OP_INT: | |
a92713e6 | 6252 | return match_int_operand (arg, operand); |
a1d78564 RS |
6253 | |
6254 | case OP_MAPPED_INT: | |
a92713e6 | 6255 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6256 | |
6257 | case OP_MSB: | |
a92713e6 | 6258 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6259 | |
6260 | case OP_REG: | |
0f35dbc4 | 6261 | case OP_OPTIONAL_REG: |
a92713e6 | 6262 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6263 | |
6264 | case OP_REG_PAIR: | |
a92713e6 | 6265 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6266 | |
6267 | case OP_PCREL: | |
a92713e6 | 6268 | return match_pcrel_operand (arg); |
a1d78564 RS |
6269 | |
6270 | case OP_PERF_REG: | |
a92713e6 | 6271 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6272 | |
6273 | case OP_ADDIUSP_INT: | |
a92713e6 | 6274 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6275 | |
6276 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6277 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6278 | |
6279 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6280 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6281 | |
6282 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6283 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6284 | |
a1d78564 | 6285 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6286 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6287 | |
6288 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6289 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6290 | |
6291 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6292 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6293 | |
6294 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6295 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6296 | |
6297 | case OP_PC: | |
a92713e6 | 6298 | return match_pc_operand (arg); |
14daeee3 | 6299 | |
25499ac7 MR |
6300 | case OP_REG28: |
6301 | return match_reg28_operand (arg); | |
6302 | ||
14daeee3 RS |
6303 | case OP_VU0_SUFFIX: |
6304 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6305 | ||
6306 | case OP_VU0_MATCH_SUFFIX: | |
6307 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6308 | |
6309 | case OP_IMM_INDEX: | |
6310 | return match_imm_index_operand (arg, operand); | |
6311 | ||
6312 | case OP_REG_INDEX: | |
6313 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6314 | |
6315 | case OP_SAME_RS_RT: | |
6316 | return match_same_rs_rt_operand (arg, operand); | |
6317 | ||
6318 | case OP_CHECK_PREV: | |
6319 | return match_check_prev_operand (arg, operand); | |
6320 | ||
6321 | case OP_NON_ZERO_REG: | |
6322 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6323 | } |
6324 | abort (); | |
6325 | } | |
6326 | ||
6327 | /* ARG is the state after successfully matching an instruction. | |
6328 | Issue any queued-up warnings. */ | |
6329 | ||
6330 | static void | |
6331 | check_completed_insn (struct mips_arg_info *arg) | |
6332 | { | |
6333 | if (arg->seen_at) | |
6334 | { | |
6335 | if (AT == ATREG) | |
1661c76c | 6336 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6337 | else |
1661c76c | 6338 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6339 | } |
6340 | } | |
a1d78564 | 6341 | |
85fcb30f RS |
6342 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6343 | ||
6344 | static bfd_boolean | |
6345 | reg_needs_delay (unsigned int reg) | |
6346 | { | |
6347 | unsigned long prev_pinfo; | |
6348 | ||
6349 | prev_pinfo = history[0].insn_mo->pinfo; | |
6350 | if (!mips_opts.noreorder | |
67dc82bc | 6351 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6352 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6353 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6354 | return TRUE; | |
6355 | ||
6356 | return FALSE; | |
6357 | } | |
6358 | ||
71400594 RS |
6359 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6360 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6361 | by VR4120 errata. */ | |
4d7206a2 | 6362 | |
71400594 RS |
6363 | static unsigned int |
6364 | classify_vr4120_insn (const char *name) | |
252b5132 | 6365 | { |
71400594 RS |
6366 | if (strncmp (name, "macc", 4) == 0) |
6367 | return FIX_VR4120_MACC; | |
6368 | if (strncmp (name, "dmacc", 5) == 0) | |
6369 | return FIX_VR4120_DMACC; | |
6370 | if (strncmp (name, "mult", 4) == 0) | |
6371 | return FIX_VR4120_MULT; | |
6372 | if (strncmp (name, "dmult", 5) == 0) | |
6373 | return FIX_VR4120_DMULT; | |
6374 | if (strstr (name, "div")) | |
6375 | return FIX_VR4120_DIV; | |
6376 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6377 | return FIX_VR4120_MTHILO; | |
6378 | return NUM_FIX_VR4120_CLASSES; | |
6379 | } | |
252b5132 | 6380 | |
a8d14a88 CM |
6381 | #define INSN_ERET 0x42000018 |
6382 | #define INSN_DERET 0x4200001f | |
6383 | #define INSN_DMULT 0x1c | |
6384 | #define INSN_DMULTU 0x1d | |
ff239038 | 6385 | |
71400594 RS |
6386 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6387 | where INSN1 is the earlier instruction. Return the worst-case value | |
6388 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6389 | |
71400594 RS |
6390 | static unsigned int |
6391 | insns_between (const struct mips_cl_insn *insn1, | |
6392 | const struct mips_cl_insn *insn2) | |
6393 | { | |
6394 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6395 | unsigned int mask; |
71400594 | 6396 | |
85fcb30f RS |
6397 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6398 | the second instruction. */ | |
71400594 RS |
6399 | pinfo1 = insn1->insn_mo->pinfo; |
6400 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6401 | |
71400594 RS |
6402 | /* For most targets, write-after-read dependencies on the HI and LO |
6403 | registers must be separated by at least two instructions. */ | |
6404 | if (!hilo_interlocks) | |
252b5132 | 6405 | { |
71400594 RS |
6406 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6407 | return 2; | |
6408 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6409 | return 2; | |
6410 | } | |
6411 | ||
6412 | /* If we're working around r7000 errata, there must be two instructions | |
6413 | between an mfhi or mflo and any instruction that uses the result. */ | |
6414 | if (mips_7000_hilo_fix | |
df58fc94 | 6415 | && !mips_opts.micromips |
71400594 | 6416 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6417 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6418 | return 2; |
6419 | ||
ff239038 CM |
6420 | /* If we're working around 24K errata, one instruction is required |
6421 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6422 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6423 | { |
6424 | if (insn1->insn_opcode == INSN_ERET | |
6425 | || insn1->insn_opcode == INSN_DERET) | |
6426 | { | |
6427 | if (insn2 == NULL | |
6428 | || insn2->insn_opcode == INSN_ERET | |
6429 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6430 | || delayed_branch_p (insn2)) |
ff239038 CM |
6431 | return 1; |
6432 | } | |
6433 | } | |
6434 | ||
a8d14a88 CM |
6435 | /* If we're working around PMC RM7000 errata, there must be three |
6436 | nops between a dmult and a load instruction. */ | |
6437 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6438 | { | |
6439 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6440 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6441 | { | |
6442 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6443 | return 3; | |
6444 | } | |
6445 | } | |
6446 | ||
71400594 RS |
6447 | /* If working around VR4120 errata, check for combinations that need |
6448 | a single intervening instruction. */ | |
df58fc94 | 6449 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6450 | { |
6451 | unsigned int class1, class2; | |
252b5132 | 6452 | |
71400594 RS |
6453 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6454 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6455 | { |
71400594 RS |
6456 | if (insn2 == NULL) |
6457 | return 1; | |
6458 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6459 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6460 | return 1; | |
252b5132 | 6461 | } |
71400594 RS |
6462 | } |
6463 | ||
df58fc94 | 6464 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6465 | { |
6466 | /* Check for GPR or coprocessor load delays. All such delays | |
6467 | are on the RT register. */ | |
6468 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6469 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6470 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6471 | { |
85fcb30f | 6472 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6473 | return 1; |
6474 | } | |
6475 | ||
6476 | /* Check for generic coprocessor hazards. | |
6477 | ||
6478 | This case is not handled very well. There is no special | |
6479 | knowledge of CP0 handling, and the coprocessors other than | |
6480 | the floating point unit are not distinguished at all. */ | |
6481 | /* Itbl support may require additional care here. FIXME! | |
6482 | Need to modify this to include knowledge about | |
6483 | user specified delays! */ | |
43885403 | 6484 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6485 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6486 | { | |
6487 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6488 | register. There must be a one instruction delay before INSN2 | |
6489 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6490 | mask = fpr_write_mask (insn1); |
6491 | if (mask != 0) | |
252b5132 | 6492 | { |
4c260379 | 6493 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6494 | return 1; |
252b5132 RH |
6495 | } |
6496 | else | |
6497 | { | |
71400594 RS |
6498 | /* Read-after-write dependencies on the control registers |
6499 | require a two-instruction gap. */ | |
6500 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6501 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6502 | return 2; | |
6503 | ||
6504 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6505 | also a coprocessor instruction, assume there must be | |
6506 | a one instruction gap. */ | |
6507 | if (pinfo2 & INSN_COP) | |
6508 | return 1; | |
252b5132 RH |
6509 | } |
6510 | } | |
6b76fefe | 6511 | |
71400594 RS |
6512 | /* Check for read-after-write dependencies on the coprocessor |
6513 | control registers in cases where INSN1 does not need a general | |
6514 | coprocessor delay. This means that INSN1 is a floating point | |
6515 | comparison instruction. */ | |
6516 | /* Itbl support may require additional care here. */ | |
6517 | else if (!cop_interlocks | |
6518 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6519 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6520 | return 1; | |
6521 | } | |
6b76fefe | 6522 | |
7361da2c AB |
6523 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6524 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6525 | and pause. */ | |
6526 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6527 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6528 | || (insn2 && delayed_branch_p (insn2)))) | |
6529 | return 1; | |
6530 | ||
71400594 RS |
6531 | return 0; |
6532 | } | |
6b76fefe | 6533 | |
7d8e00cf RS |
6534 | /* Return the number of nops that would be needed to work around the |
6535 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6536 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6537 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6538 | |
6539 | static int | |
932d1a1b | 6540 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6541 | const struct mips_cl_insn *insn) |
6542 | { | |
4c260379 RS |
6543 | int i, j; |
6544 | unsigned int mask; | |
7d8e00cf RS |
6545 | |
6546 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6547 | are not affected by the errata. */ | |
6548 | if (insn != 0 | |
6549 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6550 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6551 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6552 | return 0; | |
6553 | ||
6554 | /* Search for the first MFLO or MFHI. */ | |
6555 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6556 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6557 | { |
6558 | /* Extract the destination register. */ | |
4c260379 | 6559 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6560 | |
6561 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6562 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6563 | return 0; |
6564 | ||
6565 | /* ...or if any of the intervening instructions do. */ | |
6566 | for (j = 0; j < i; j++) | |
4c260379 | 6567 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6568 | return 0; |
6569 | ||
932d1a1b RS |
6570 | if (i >= ignore) |
6571 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6572 | } |
6573 | return 0; | |
6574 | } | |
6575 | ||
134c0c8b MR |
6576 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6577 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6578 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6579 | ||
6580 | /* Return the minimum alignment for this store instruction. */ | |
6581 | ||
6582 | static int | |
6583 | fix_24k_align_to (const struct mips_opcode *mo) | |
6584 | { | |
6585 | if (strcmp (mo->name, "sh") == 0) | |
6586 | return 2; | |
6587 | ||
6588 | if (strcmp (mo->name, "swc1") == 0 | |
6589 | || strcmp (mo->name, "swc2") == 0 | |
6590 | || strcmp (mo->name, "sw") == 0 | |
6591 | || strcmp (mo->name, "sc") == 0 | |
6592 | || strcmp (mo->name, "s.s") == 0) | |
6593 | return 4; | |
6594 | ||
6595 | if (strcmp (mo->name, "sdc1") == 0 | |
6596 | || strcmp (mo->name, "sdc2") == 0 | |
6597 | || strcmp (mo->name, "s.d") == 0) | |
6598 | return 8; | |
6599 | ||
6600 | /* sb, swl, swr */ | |
6601 | return 1; | |
6602 | } | |
6603 | ||
6604 | struct fix_24k_store_info | |
6605 | { | |
6606 | /* Immediate offset, if any, for this store instruction. */ | |
6607 | short off; | |
6608 | /* Alignment required by this store instruction. */ | |
6609 | int align_to; | |
6610 | /* True for register offsets. */ | |
6611 | int register_offset; | |
6612 | }; | |
6613 | ||
6614 | /* Comparison function used by qsort. */ | |
6615 | ||
6616 | static int | |
6617 | fix_24k_sort (const void *a, const void *b) | |
6618 | { | |
6619 | const struct fix_24k_store_info *pos1 = a; | |
6620 | const struct fix_24k_store_info *pos2 = b; | |
6621 | ||
6622 | return (pos1->off - pos2->off); | |
6623 | } | |
6624 | ||
6625 | /* INSN is a store instruction. Try to record the store information | |
6626 | in STINFO. Return false if the information isn't known. */ | |
6627 | ||
6628 | static bfd_boolean | |
6629 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6630 | const struct mips_cl_insn *insn) |
15be625d CM |
6631 | { |
6632 | /* The instruction must have a known offset. */ | |
6633 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6634 | return FALSE; | |
6635 | ||
6636 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6637 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6638 | return TRUE; | |
6639 | } | |
6640 | ||
932d1a1b RS |
6641 | /* Return the number of nops that would be needed to work around the 24k |
6642 | "lost data on stores during refill" errata if instruction INSN | |
6643 | immediately followed the 2 instructions described by HIST. | |
6644 | Ignore hazards that are contained within the first IGNORE | |
6645 | instructions of HIST. | |
6646 | ||
6647 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6648 | for the data cache refills and store data. The following describes | |
6649 | the scenario where the store data could be lost. | |
6650 | ||
6651 | * A data cache miss, due to either a load or a store, causing fill | |
6652 | data to be supplied by the memory subsystem | |
6653 | * The first three doublewords of fill data are returned and written | |
6654 | into the cache | |
6655 | * A sequence of four stores occurs in consecutive cycles around the | |
6656 | final doubleword of the fill: | |
6657 | * Store A | |
6658 | * Store B | |
6659 | * Store C | |
6660 | * Zero, One or more instructions | |
6661 | * Store D | |
6662 | ||
6663 | The four stores A-D must be to different doublewords of the line that | |
6664 | is being filled. The fourth instruction in the sequence above permits | |
6665 | the fill of the final doubleword to be transferred from the FSB into | |
6666 | the cache. In the sequence above, the stores may be either integer | |
6667 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6668 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6669 | different doublewords on the line. If the floating point unit is | |
6670 | running in 1:2 mode, it is not possible to create the sequence above | |
6671 | using only floating point store instructions. | |
15be625d CM |
6672 | |
6673 | In this case, the cache line being filled is incorrectly marked | |
6674 | invalid, thereby losing the data from any store to the line that | |
6675 | occurs between the original miss and the completion of the five | |
6676 | cycle sequence shown above. | |
6677 | ||
932d1a1b | 6678 | The workarounds are: |
15be625d | 6679 | |
932d1a1b RS |
6680 | * Run the data cache in write-through mode. |
6681 | * Insert a non-store instruction between | |
6682 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6683 | |
15be625d | 6684 | static int |
932d1a1b | 6685 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6686 | const struct mips_cl_insn *insn) |
6687 | { | |
6688 | struct fix_24k_store_info pos[3]; | |
6689 | int align, i, base_offset; | |
6690 | ||
932d1a1b RS |
6691 | if (ignore >= 2) |
6692 | return 0; | |
6693 | ||
ab9794cf RS |
6694 | /* If the previous instruction wasn't a store, there's nothing to |
6695 | worry about. */ | |
15be625d CM |
6696 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6697 | return 0; | |
6698 | ||
ab9794cf RS |
6699 | /* If the instructions after the previous one are unknown, we have |
6700 | to assume the worst. */ | |
6701 | if (!insn) | |
15be625d CM |
6702 | return 1; |
6703 | ||
ab9794cf RS |
6704 | /* Check whether we are dealing with three consecutive stores. */ |
6705 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6706 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6707 | return 0; |
6708 | ||
6709 | /* If we don't know the relationship between the store addresses, | |
6710 | assume the worst. */ | |
ab9794cf | 6711 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6712 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6713 | return 1; | |
6714 | ||
6715 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6716 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6717 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6718 | return 1; | |
6719 | ||
6720 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6721 | ||
6722 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6723 | X bytes and such that the base register + X is known to be aligned | |
6724 | to align bytes. */ | |
6725 | ||
6726 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6727 | align = 8; | |
6728 | else | |
6729 | { | |
6730 | align = pos[0].align_to; | |
6731 | base_offset = pos[0].off; | |
6732 | for (i = 1; i < 3; i++) | |
6733 | if (align < pos[i].align_to) | |
6734 | { | |
6735 | align = pos[i].align_to; | |
6736 | base_offset = pos[i].off; | |
6737 | } | |
6738 | for (i = 0; i < 3; i++) | |
6739 | pos[i].off -= base_offset; | |
6740 | } | |
6741 | ||
6742 | pos[0].off &= ~align + 1; | |
6743 | pos[1].off &= ~align + 1; | |
6744 | pos[2].off &= ~align + 1; | |
6745 | ||
6746 | /* If any two stores write to the same chunk, they also write to the | |
6747 | same doubleword. The offsets are still sorted at this point. */ | |
6748 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6749 | return 0; | |
6750 | ||
6751 | /* A range of at least 9 bytes is needed for the stores to be in | |
6752 | non-overlapping doublewords. */ | |
6753 | if (pos[2].off - pos[0].off <= 8) | |
6754 | return 0; | |
6755 | ||
6756 | if (pos[2].off - pos[1].off >= 24 | |
6757 | || pos[1].off - pos[0].off >= 24 | |
6758 | || pos[2].off - pos[0].off >= 32) | |
6759 | return 0; | |
6760 | ||
6761 | return 1; | |
6762 | } | |
6763 | ||
71400594 | 6764 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6765 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6766 | where HIST[0] is the most recent instruction. Ignore hazards |
6767 | between INSN and the first IGNORE instructions in HIST. | |
6768 | ||
6769 | If INSN is null, return the worse-case number of nops for any | |
6770 | instruction. */ | |
bdaaa2e1 | 6771 | |
71400594 | 6772 | static int |
932d1a1b | 6773 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6774 | const struct mips_cl_insn *insn) |
6775 | { | |
6776 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6777 | |
71400594 | 6778 | nops = 0; |
932d1a1b | 6779 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6780 | { |
91d6fa6a | 6781 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6782 | if (tmp_nops > nops) |
6783 | nops = tmp_nops; | |
6784 | } | |
7d8e00cf | 6785 | |
df58fc94 | 6786 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6787 | { |
932d1a1b | 6788 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6789 | if (tmp_nops > nops) |
6790 | nops = tmp_nops; | |
6791 | } | |
6792 | ||
df58fc94 | 6793 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6794 | { |
932d1a1b | 6795 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6796 | if (tmp_nops > nops) |
6797 | nops = tmp_nops; | |
6798 | } | |
6799 | ||
71400594 RS |
6800 | return nops; |
6801 | } | |
252b5132 | 6802 | |
71400594 | 6803 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6804 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6805 | would be needed after the extended sequence, ignoring hazards |
6806 | in the first IGNORE instructions. */ | |
252b5132 | 6807 | |
71400594 | 6808 | static int |
932d1a1b RS |
6809 | nops_for_sequence (int num_insns, int ignore, |
6810 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6811 | { |
6812 | va_list args; | |
6813 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6814 | struct mips_cl_insn *cursor; | |
6815 | int nops; | |
6816 | ||
91d6fa6a | 6817 | va_start (args, hist); |
71400594 | 6818 | cursor = buffer + num_insns; |
91d6fa6a | 6819 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6820 | while (cursor > buffer) |
6821 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6822 | ||
932d1a1b | 6823 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6824 | va_end (args); |
6825 | return nops; | |
6826 | } | |
252b5132 | 6827 | |
71400594 RS |
6828 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6829 | worst-case delay for the branch target. */ | |
252b5132 | 6830 | |
71400594 | 6831 | static int |
932d1a1b | 6832 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6833 | const struct mips_cl_insn *insn) |
6834 | { | |
6835 | int nops, tmp_nops; | |
60b63b72 | 6836 | |
932d1a1b | 6837 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6838 | if (delayed_branch_p (insn)) |
71400594 | 6839 | { |
932d1a1b | 6840 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6841 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6842 | if (tmp_nops > nops) |
6843 | nops = tmp_nops; | |
6844 | } | |
11625dd8 | 6845 | else if (compact_branch_p (insn)) |
71400594 | 6846 | { |
932d1a1b | 6847 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6848 | if (tmp_nops > nops) |
6849 | nops = tmp_nops; | |
6850 | } | |
6851 | return nops; | |
6852 | } | |
6853 | ||
c67a084a NC |
6854 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6855 | ||
6856 | static void | |
6857 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6858 | { | |
df58fc94 | 6859 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6860 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6861 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6862 | } | |
6863 | ||
6864 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6865 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6866 | ||
6867 | static void | |
6868 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6869 | { | |
df58fc94 | 6870 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6871 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6872 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6873 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6874 | { | |
6875 | int sreg; | |
6876 | expressionS ep; | |
6877 | ||
6878 | if (! mips_opts.at) | |
6879 | return; | |
6880 | ||
df58fc94 | 6881 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6882 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6883 | return; | |
6884 | ||
6885 | ep.X_op = O_constant; | |
6886 | ep.X_add_number = 0xcfff0000; | |
6887 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6888 | ep.X_add_number = 0xffff; | |
6889 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6890 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6891 | } | |
6892 | } | |
6893 | ||
6894 | static void | |
6895 | fix_loongson2f (struct mips_cl_insn * ip) | |
6896 | { | |
6897 | if (mips_fix_loongson2f_nop) | |
6898 | fix_loongson2f_nop (ip); | |
6899 | ||
6900 | if (mips_fix_loongson2f_jump) | |
6901 | fix_loongson2f_jump (ip); | |
6902 | } | |
6903 | ||
6f2117ba PH |
6904 | /* Fix loongson3 llsc errata: Insert sync before ll/lld. */ |
6905 | ||
6906 | static void | |
6907 | fix_loongson3_llsc (struct mips_cl_insn * ip) | |
6908 | { | |
6909 | gas_assert (!HAVE_CODE_COMPRESSION); | |
6910 | ||
6911 | /* If is an local label and the insn is not sync, | |
6912 | look forward that whether an branch between ll/sc jump to here | |
6913 | if so, insert a sync. */ | |
6914 | if (seg_info (now_seg)->label_list | |
6915 | && S_IS_LOCAL (seg_info (now_seg)->label_list->label) | |
6916 | && (strcmp (ip->insn_mo->name, "sync") != 0)) | |
6917 | { | |
6918 | const char *label_name = S_GET_NAME (seg_info (now_seg)->label_list->label); | |
6919 | unsigned long lookback = ARRAY_SIZE (history); | |
6920 | unsigned long i; | |
6921 | ||
6922 | for (i = 0; i < lookback; i++) | |
6923 | { | |
6924 | if (streq (history[i].insn_mo->name, "ll") | |
6925 | || streq (history[i].insn_mo->name, "lld")) | |
6926 | break; | |
6927 | ||
6928 | if (streq (history[i].insn_mo->name, "sc") | |
6929 | || streq (history[i].insn_mo->name, "scd")) | |
6930 | { | |
6931 | unsigned long j; | |
6932 | ||
6933 | for (j = i + 1; j < lookback; j++) | |
6934 | { | |
6935 | if (streq (history[i].insn_mo->name, "ll") | |
6936 | || streq (history[i].insn_mo->name, "lld")) | |
6937 | break; | |
6938 | ||
6939 | if (delayed_branch_p (&history[j])) | |
6940 | { | |
6941 | if (streq (history[j].target, label_name)) | |
6942 | { | |
6943 | add_fixed_insn (&sync_insn); | |
6944 | insert_into_history (0, 1, &sync_insn); | |
6945 | i = lookback; | |
6946 | break; | |
6947 | } | |
6948 | } | |
6949 | } | |
6950 | } | |
6951 | } | |
6952 | } | |
6953 | /* If we find a sc, we look forward to look for an branch insn, | |
6954 | and see whether it jump back and out of ll/sc. */ | |
6955 | else if (streq(ip->insn_mo->name, "sc") || streq(ip->insn_mo->name, "scd")) | |
6956 | { | |
6957 | unsigned long lookback = ARRAY_SIZE (history) - 1; | |
6958 | unsigned long i; | |
6959 | ||
6960 | for (i = 0; i < lookback; i++) | |
6961 | { | |
6962 | if (streq (history[i].insn_mo->name, "ll") | |
6963 | || streq (history[i].insn_mo->name, "lld")) | |
6964 | break; | |
6965 | ||
6966 | if (delayed_branch_p (&history[i])) | |
6967 | { | |
6968 | unsigned long j; | |
6969 | ||
6970 | for (j = i + 1; j < lookback; j++) | |
6971 | { | |
6972 | if (streq (history[j].insn_mo->name, "ll") | |
6973 | || streq (history[i].insn_mo->name, "lld")) | |
6974 | break; | |
6975 | } | |
6976 | ||
6977 | for (; j < lookback; j++) | |
6978 | { | |
6979 | if (history[j].label[0] != '\0' | |
6980 | && streq (history[j].label, history[i].target) | |
6981 | && strcmp (history[j+1].insn_mo->name, "sync") != 0) | |
6982 | { | |
6983 | add_fixed_insn (&sync_insn); | |
6984 | insert_into_history (++j, 1, &sync_insn); | |
6985 | } | |
6986 | } | |
6987 | } | |
6988 | } | |
6989 | } | |
6990 | ||
6991 | /* Skip if there is a sync before ll/lld. */ | |
6992 | if ((strcmp (ip->insn_mo->name, "ll") == 0 | |
6993 | || strcmp (ip->insn_mo->name, "lld") == 0) | |
6994 | && (strcmp (history[0].insn_mo->name, "sync") != 0)) | |
6995 | { | |
6996 | add_fixed_insn (&sync_insn); | |
6997 | insert_into_history (0, 1, &sync_insn); | |
6998 | } | |
6999 | } | |
7000 | ||
a4e06468 RS |
7001 | /* IP is a branch that has a delay slot, and we need to fill it |
7002 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
7003 | with the previous instruction. |
7004 | ADDRESS_EXPR is an operand of the instruction to be used with | |
7005 | RELOC_TYPE. */ | |
a4e06468 RS |
7006 | |
7007 | static bfd_boolean | |
e407c74b | 7008 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 7009 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 7010 | { |
2b0c8b40 | 7011 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 7012 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 7013 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
7014 | |
7015 | /* -O2 and above is required for this optimization. */ | |
7016 | if (mips_optimize < 2) | |
7017 | return FALSE; | |
7018 | ||
7019 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
7020 | if (mips_opts.nomove) | |
7021 | return FALSE; | |
7022 | ||
7023 | /* We can't swap if the previous instruction's position is fixed. */ | |
7024 | if (history[0].fixed_p) | |
7025 | return FALSE; | |
7026 | ||
7027 | /* If the previous previous insn was in a .set noreorder, we can't | |
7028 | swap. Actually, the MIPS assembler will swap in this situation. | |
7029 | However, gcc configured -with-gnu-as will generate code like | |
7030 | ||
7031 | .set noreorder | |
7032 | lw $4,XXX | |
7033 | .set reorder | |
7034 | INSN | |
7035 | bne $4,$0,foo | |
7036 | ||
7037 | in which we can not swap the bne and INSN. If gcc is not configured | |
7038 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
7039 | if (history[1].noreorder_p) | |
7040 | return FALSE; | |
7041 | ||
87333bb7 MR |
7042 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
7043 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
7044 | if (mips_opts.mips16 && history[0].fixp[0]) |
7045 | return FALSE; | |
7046 | ||
7047 | /* If the branch is itself the target of a branch, we can not swap. | |
7048 | We cheat on this; all we check for is whether there is a label on | |
7049 | this instruction. If there are any branches to anything other than | |
7050 | a label, users must use .set noreorder. */ | |
7051 | if (seg_info (now_seg)->label_list) | |
7052 | return FALSE; | |
7053 | ||
7054 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 7055 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
7056 | MIPS16 code, which uses variant frags for different purposes. */ |
7057 | if (!mips_opts.mips16 | |
a4e06468 RS |
7058 | && history[0].frag |
7059 | && history[0].frag->fr_type == rs_machine_dependent) | |
7060 | return FALSE; | |
7061 | ||
bcd530a7 RS |
7062 | /* We do not swap with instructions that cannot architecturally |
7063 | be placed in a branch delay slot, such as SYNC or ERET. We | |
7064 | also refrain from swapping with a trap instruction, since it | |
7065 | complicates trap handlers to have the trap instruction be in | |
7066 | a delay slot. */ | |
a4e06468 | 7067 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 7068 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
7069 | return FALSE; |
7070 | ||
7071 | /* Check for conflicts between the branch and the instructions | |
7072 | before the candidate delay slot. */ | |
7073 | if (nops_for_insn (0, history + 1, ip) > 0) | |
7074 | return FALSE; | |
7075 | ||
7076 | /* Check for conflicts between the swapped sequence and the | |
7077 | target of the branch. */ | |
7078 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
7079 | return FALSE; | |
7080 | ||
7081 | /* If the branch reads a register that the previous | |
7082 | instruction sets, we can not swap. */ | |
7083 | gpr_read = gpr_read_mask (ip); | |
7084 | prev_gpr_write = gpr_write_mask (&history[0]); | |
7085 | if (gpr_read & prev_gpr_write) | |
7086 | return FALSE; | |
7087 | ||
9d5de888 CF |
7088 | fpr_read = fpr_read_mask (ip); |
7089 | prev_fpr_write = fpr_write_mask (&history[0]); | |
7090 | if (fpr_read & prev_fpr_write) | |
7091 | return FALSE; | |
7092 | ||
a4e06468 RS |
7093 | /* If the branch writes a register that the previous |
7094 | instruction sets, we can not swap. */ | |
7095 | gpr_write = gpr_write_mask (ip); | |
7096 | if (gpr_write & prev_gpr_write) | |
7097 | return FALSE; | |
7098 | ||
7099 | /* If the branch writes a register that the previous | |
7100 | instruction reads, we can not swap. */ | |
7101 | prev_gpr_read = gpr_read_mask (&history[0]); | |
7102 | if (gpr_write & prev_gpr_read) | |
7103 | return FALSE; | |
7104 | ||
7105 | /* If one instruction sets a condition code and the | |
7106 | other one uses a condition code, we can not swap. */ | |
7107 | pinfo = ip->insn_mo->pinfo; | |
7108 | if ((pinfo & INSN_READ_COND_CODE) | |
7109 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
7110 | return FALSE; | |
7111 | if ((pinfo & INSN_WRITE_COND_CODE) | |
7112 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
7113 | return FALSE; | |
7114 | ||
7115 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 7116 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 7117 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 7118 | return FALSE; |
a4e06468 | 7119 | |
df58fc94 RS |
7120 | /* If the previous instruction has an incorrect size for a fixed |
7121 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
7122 | pinfo2 = ip->insn_mo->pinfo2; |
7123 | if (mips_opts.micromips | |
7124 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
7125 | && insn_length (history) != 2) | |
7126 | return FALSE; | |
7127 | if (mips_opts.micromips | |
7128 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
7129 | && insn_length (history) != 4) | |
7130 | return FALSE; | |
7131 | ||
33d64ca5 FN |
7132 | /* On the R5900 short loops need to be fixed by inserting a NOP in the |
7133 | branch delay slot. | |
7134 | ||
7135 | The short loop bug under certain conditions causes loops to execute | |
7136 | only once or twice. We must ensure that the assembler never | |
7137 | generates loops that satisfy all of the following conditions: | |
7138 | ||
7139 | - a loop consists of less than or equal to six instructions | |
7140 | (including the branch delay slot); | |
7141 | - a loop contains only one conditional branch instruction at the end | |
7142 | of the loop; | |
7143 | - a loop does not contain any other branch or jump instructions; | |
7144 | - a branch delay slot of the loop is not NOP (EE 2.9 or later). | |
7145 | ||
7146 | We need to do this because of a hardware bug in the R5900 chip. */ | |
27c634e0 | 7147 | if (mips_fix_r5900 |
e407c74b NC |
7148 | /* Check if instruction has a parameter, ignore "j $31". */ |
7149 | && (address_expr != NULL) | |
7150 | /* Parameter must be 16 bit. */ | |
7151 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
7152 | /* Branch to same segment. */ | |
41065f5e | 7153 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 7154 | /* Branch to same code fragment. */ |
41065f5e | 7155 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 7156 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 7157 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
7158 | /* Check if branch is really conditional. */ |
7159 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
7160 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
7161 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
7162 | { | |
7163 | int distance; | |
33d64ca5 FN |
7164 | /* Check if loop is shorter than or equal to 6 instructions |
7165 | including branch and delay slot. */ | |
41065f5e | 7166 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
7167 | if (distance <= 20) |
7168 | { | |
7169 | int i; | |
7170 | int rv; | |
7171 | ||
7172 | rv = FALSE; | |
7173 | /* When the loop includes branches or jumps, | |
7174 | it is not a short loop. */ | |
7175 | for (i = 0; i < (distance / 4); i++) | |
7176 | { | |
7177 | if ((history[i].cleared_p) | |
41065f5e | 7178 | || delayed_branch_p (&history[i])) |
e407c74b NC |
7179 | { |
7180 | rv = TRUE; | |
7181 | break; | |
7182 | } | |
7183 | } | |
535b785f | 7184 | if (!rv) |
e407c74b NC |
7185 | { |
7186 | /* Insert nop after branch to fix short loop. */ | |
7187 | return FALSE; | |
7188 | } | |
7189 | } | |
7190 | } | |
7191 | ||
a4e06468 RS |
7192 | return TRUE; |
7193 | } | |
7194 | ||
e407c74b NC |
7195 | /* Decide how we should add IP to the instruction stream. |
7196 | ADDRESS_EXPR is an operand of the instruction to be used with | |
7197 | RELOC_TYPE. */ | |
a4e06468 RS |
7198 | |
7199 | static enum append_method | |
e407c74b | 7200 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 7201 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 7202 | { |
a4e06468 RS |
7203 | /* The relaxed version of a macro sequence must be inherently |
7204 | hazard-free. */ | |
7205 | if (mips_relax.sequence == 2) | |
7206 | return APPEND_ADD; | |
7207 | ||
3b821a28 | 7208 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
7209 | if (mips_opts.noreorder) |
7210 | return APPEND_ADD; | |
7211 | ||
7212 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 7213 | if (delayed_branch_p (ip)) |
a4e06468 | 7214 | { |
e407c74b NC |
7215 | if (!branch_likely_p (ip) |
7216 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
7217 | return APPEND_SWAP; |
7218 | ||
7219 | if (mips_opts.mips16 | |
7220 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 7221 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
7222 | return APPEND_ADD_COMPACT; |
7223 | ||
7bd374a4 MR |
7224 | if (mips_opts.micromips |
7225 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
7226 | || (!forced_insn_length | |
7227 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
7228 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
7229 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
7230 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
7231 | return APPEND_ADD_COMPACT; | |
7232 | ||
a4e06468 RS |
7233 | return APPEND_ADD_WITH_NOP; |
7234 | } | |
7235 | ||
a4e06468 RS |
7236 | return APPEND_ADD; |
7237 | } | |
7238 | ||
7bd374a4 MR |
7239 | /* IP is an instruction whose opcode we have just changed, END points |
7240 | to the end of the opcode table processed. Point IP->insn_mo to the | |
7241 | new opcode's definition. */ | |
ceb94aa5 RS |
7242 | |
7243 | static void | |
7bd374a4 | 7244 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 7245 | { |
7bd374a4 | 7246 | const struct mips_opcode *mo; |
ceb94aa5 | 7247 | |
ceb94aa5 | 7248 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
7249 | if (mo->pinfo != INSN_MACRO |
7250 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
7251 | { |
7252 | ip->insn_mo = mo; | |
7253 | return; | |
7254 | } | |
7255 | abort (); | |
7256 | } | |
7257 | ||
7bd374a4 MR |
7258 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
7259 | Point IP->insn_mo to the new opcode's definition. */ | |
7260 | ||
7261 | static void | |
7262 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
7263 | { | |
7264 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
7265 | } | |
7266 | ||
7267 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
7268 | Point IP->insn_mo to the new opcode's definition. */ | |
7269 | ||
7270 | static void | |
7271 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
7272 | { | |
7273 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
7274 | } | |
7275 | ||
df58fc94 RS |
7276 | /* For microMIPS macros, we need to generate a local number label |
7277 | as the target of branches. */ | |
7278 | #define MICROMIPS_LABEL_CHAR '\037' | |
7279 | static unsigned long micromips_target_label; | |
7280 | static char micromips_target_name[32]; | |
7281 | ||
7282 | static char * | |
7283 | micromips_label_name (void) | |
7284 | { | |
7285 | char *p = micromips_target_name; | |
7286 | char symbol_name_temporary[24]; | |
7287 | unsigned long l; | |
7288 | int i; | |
7289 | ||
7290 | if (*p) | |
7291 | return p; | |
7292 | ||
7293 | i = 0; | |
7294 | l = micromips_target_label; | |
7295 | #ifdef LOCAL_LABEL_PREFIX | |
7296 | *p++ = LOCAL_LABEL_PREFIX; | |
7297 | #endif | |
7298 | *p++ = 'L'; | |
7299 | *p++ = MICROMIPS_LABEL_CHAR; | |
7300 | do | |
7301 | { | |
7302 | symbol_name_temporary[i++] = l % 10 + '0'; | |
7303 | l /= 10; | |
7304 | } | |
7305 | while (l != 0); | |
7306 | while (i > 0) | |
7307 | *p++ = symbol_name_temporary[--i]; | |
7308 | *p = '\0'; | |
7309 | ||
7310 | return micromips_target_name; | |
7311 | } | |
7312 | ||
7313 | static void | |
7314 | micromips_label_expr (expressionS *label_expr) | |
7315 | { | |
7316 | label_expr->X_op = O_symbol; | |
7317 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
7318 | label_expr->X_add_number = 0; | |
7319 | } | |
7320 | ||
7321 | static void | |
7322 | micromips_label_inc (void) | |
7323 | { | |
7324 | micromips_target_label++; | |
7325 | *micromips_target_name = '\0'; | |
7326 | } | |
7327 | ||
7328 | static void | |
7329 | micromips_add_label (void) | |
7330 | { | |
7331 | symbolS *s; | |
7332 | ||
7333 | s = colon (micromips_label_name ()); | |
7334 | micromips_label_inc (); | |
f3ded42a | 7335 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
7336 | } |
7337 | ||
7338 | /* If assembling microMIPS code, then return the microMIPS reloc | |
7339 | corresponding to the requested one if any. Otherwise return | |
7340 | the reloc unchanged. */ | |
7341 | ||
7342 | static bfd_reloc_code_real_type | |
7343 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
7344 | { | |
7345 | static const bfd_reloc_code_real_type relocs[][2] = | |
7346 | { | |
7347 | /* Keep sorted incrementally by the left-hand key. */ | |
7348 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7349 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7350 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7351 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7352 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7353 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7354 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7355 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7356 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7357 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7358 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7359 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7360 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7361 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7362 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7363 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7364 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7365 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7366 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7367 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7368 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7369 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7370 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7371 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7372 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7373 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7374 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7375 | }; | |
7376 | bfd_reloc_code_real_type r; | |
7377 | size_t i; | |
7378 | ||
7379 | if (!mips_opts.micromips) | |
7380 | return reloc; | |
7381 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7382 | { | |
7383 | r = relocs[i][0]; | |
7384 | if (r > reloc) | |
7385 | return reloc; | |
7386 | if (r == reloc) | |
7387 | return relocs[i][1]; | |
7388 | } | |
7389 | return reloc; | |
7390 | } | |
7391 | ||
b886a2ab RS |
7392 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7393 | Return true on success, storing the resolved value in RESULT. */ | |
7394 | ||
7395 | static bfd_boolean | |
7396 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7397 | offsetT *result) | |
7398 | { | |
7399 | switch (reloc) | |
7400 | { | |
7401 | case BFD_RELOC_MIPS_HIGHEST: | |
7402 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7403 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7404 | return TRUE; | |
7405 | ||
7406 | case BFD_RELOC_MIPS_HIGHER: | |
7407 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7408 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7409 | return TRUE; | |
7410 | ||
7411 | case BFD_RELOC_HI16_S: | |
41947d9e | 7412 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7413 | case BFD_RELOC_MICROMIPS_HI16_S: |
7414 | case BFD_RELOC_MIPS16_HI16_S: | |
7415 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7416 | return TRUE; | |
7417 | ||
7418 | case BFD_RELOC_HI16: | |
7419 | case BFD_RELOC_MICROMIPS_HI16: | |
7420 | case BFD_RELOC_MIPS16_HI16: | |
7421 | *result = (operand >> 16) & 0xffff; | |
7422 | return TRUE; | |
7423 | ||
7424 | case BFD_RELOC_LO16: | |
41947d9e | 7425 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7426 | case BFD_RELOC_MICROMIPS_LO16: |
7427 | case BFD_RELOC_MIPS16_LO16: | |
7428 | *result = operand & 0xffff; | |
7429 | return TRUE; | |
7430 | ||
7431 | case BFD_RELOC_UNUSED: | |
7432 | *result = operand; | |
7433 | return TRUE; | |
7434 | ||
7435 | default: | |
7436 | return FALSE; | |
7437 | } | |
7438 | } | |
7439 | ||
71400594 RS |
7440 | /* Output an instruction. IP is the instruction information. |
7441 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7442 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7443 | a macro expansion. */ | |
71400594 RS |
7444 | |
7445 | static void | |
7446 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7447 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7448 | { |
14fe068b | 7449 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7450 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7451 | enum append_method method; |
2309ddf2 | 7452 | bfd_boolean relax32; |
2b0c8b40 | 7453 | int branch_disp; |
71400594 | 7454 | |
2309ddf2 | 7455 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7456 | fix_loongson2f (ip); |
7457 | ||
6f2117ba PH |
7458 | ip->target[0] = '\0'; |
7459 | if (offset_expr.X_op == O_symbol) | |
7460 | strncpy (ip->target, S_GET_NAME (offset_expr.X_add_symbol), 15); | |
7461 | ip->label[0] = '\0'; | |
7462 | if (seg_info (now_seg)->label_list) | |
7463 | strncpy (ip->label, S_GET_NAME (seg_info (now_seg)->label_list->label), 15); | |
7464 | if (mips_fix_loongson3_llsc && !HAVE_CODE_COMPRESSION) | |
7465 | fix_loongson3_llsc (ip); | |
7466 | ||
738f4d98 | 7467 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7468 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7469 | |
df58fc94 | 7470 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7471 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7472 | |
7bd374a4 MR |
7473 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7474 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7475 | if (mips_opts.micromips |
7476 | && !expansionp | |
7bd374a4 MR |
7477 | && !(history[0].frag |
7478 | && history[0].frag->fr_type == rs_machine_dependent | |
7479 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7480 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7481 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7482 | && micromips_insn_length (ip->insn_mo) != 2) | |
7483 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7484 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7485 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7486 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7487 | |
15be625d CM |
7488 | if (address_expr == NULL) |
7489 | ip->complete_p = 1; | |
b886a2ab RS |
7490 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7491 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7492 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7493 | && address_expr->X_op == O_constant) |
7494 | { | |
15be625d CM |
7495 | switch (*reloc_type) |
7496 | { | |
15be625d | 7497 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7498 | { |
7499 | int shift; | |
7500 | ||
17c6c9d9 MR |
7501 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7502 | shift = (mips_opts.micromips | |
7503 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7504 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7505 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7506 | (unsigned long) address_expr->X_add_number); | |
7507 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7508 | & 0x3ffffff); | |
335574df | 7509 | ip->complete_p = 1; |
df58fc94 | 7510 | } |
15be625d CM |
7511 | break; |
7512 | ||
7513 | case BFD_RELOC_MIPS16_JMP: | |
7514 | if ((address_expr->X_add_number & 3) != 0) | |
7515 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7516 | (unsigned long) address_expr->X_add_number); | |
7517 | ip->insn_opcode |= | |
7518 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7519 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7520 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7521 | ip->complete_p = 1; |
15be625d CM |
7522 | break; |
7523 | ||
7524 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7525 | { |
7526 | int shift; | |
7527 | ||
7528 | shift = mips_opts.micromips ? 1 : 2; | |
7529 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7530 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7531 | (unsigned long) address_expr->X_add_number); | |
7532 | if (!mips_relax_branch) | |
7533 | { | |
7534 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7535 | & ~((1 << (shift + 16)) - 1)) | |
7536 | as_bad (_("branch address range overflow (0x%lx)"), | |
7537 | (unsigned long) address_expr->X_add_number); | |
7538 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7539 | & 0xffff); | |
7540 | } | |
df58fc94 | 7541 | } |
15be625d CM |
7542 | break; |
7543 | ||
7361da2c AB |
7544 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7545 | { | |
7546 | int shift; | |
7547 | ||
7548 | shift = 2; | |
7549 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7550 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7551 | (unsigned long) address_expr->X_add_number); | |
7552 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7553 | & ~((1 << (shift + 21)) - 1)) | |
7554 | as_bad (_("branch address range overflow (0x%lx)"), | |
7555 | (unsigned long) address_expr->X_add_number); | |
7556 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7557 | & 0x1fffff); | |
7558 | } | |
7559 | break; | |
7560 | ||
7561 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7562 | { | |
7563 | int shift; | |
7564 | ||
7565 | shift = 2; | |
7566 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7567 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7568 | (unsigned long) address_expr->X_add_number); | |
7569 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7570 | & ~((1 << (shift + 26)) - 1)) | |
7571 | as_bad (_("branch address range overflow (0x%lx)"), | |
7572 | (unsigned long) address_expr->X_add_number); | |
7573 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7574 | & 0x3ffffff); | |
7575 | } | |
7576 | break; | |
7577 | ||
15be625d | 7578 | default: |
b886a2ab RS |
7579 | { |
7580 | offsetT value; | |
7581 | ||
7582 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7583 | &value)) | |
7584 | { | |
7585 | ip->insn_opcode |= value & 0xffff; | |
7586 | ip->complete_p = 1; | |
7587 | } | |
7588 | } | |
7589 | break; | |
7590 | } | |
15be625d CM |
7591 | } |
7592 | ||
71400594 RS |
7593 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7594 | { | |
7595 | /* There are a lot of optimizations we could do that we don't. | |
7596 | In particular, we do not, in general, reorder instructions. | |
7597 | If you use gcc with optimization, it will reorder | |
7598 | instructions and generally do much more optimization then we | |
7599 | do here; repeating all that work in the assembler would only | |
7600 | benefit hand written assembly code, and does not seem worth | |
7601 | it. */ | |
7602 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7603 | ? nops_for_insn (0, history, NULL) |
7604 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7605 | if (nops > 0) |
252b5132 RH |
7606 | { |
7607 | fragS *old_frag; | |
7608 | unsigned long old_frag_offset; | |
7609 | int i; | |
252b5132 RH |
7610 | |
7611 | old_frag = frag_now; | |
7612 | old_frag_offset = frag_now_fix (); | |
7613 | ||
7614 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7615 | add_fixed_insn (NOP_INSN); |
7616 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7617 | |
7618 | if (listing) | |
7619 | { | |
7620 | listing_prev_line (); | |
7621 | /* We may be at the start of a variant frag. In case we | |
7622 | are, make sure there is enough space for the frag | |
7623 | after the frags created by listing_prev_line. The | |
7624 | argument to frag_grow here must be at least as large | |
7625 | as the argument to all other calls to frag_grow in | |
7626 | this file. We don't have to worry about being in the | |
7627 | middle of a variant frag, because the variants insert | |
7628 | all needed nop instructions themselves. */ | |
7629 | frag_grow (40); | |
7630 | } | |
7631 | ||
462427c4 | 7632 | mips_move_text_labels (); |
252b5132 RH |
7633 | |
7634 | #ifndef NO_ECOFF_DEBUGGING | |
7635 | if (ECOFF_DEBUGGING) | |
7636 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7637 | #endif | |
7638 | } | |
71400594 RS |
7639 | } |
7640 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7641 | { | |
932d1a1b RS |
7642 | int nops; |
7643 | ||
7644 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7645 | ignoring hazards generated by the first prev_nop_frag_since | |
7646 | instructions. */ | |
7647 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7648 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7649 | |
71400594 RS |
7650 | /* Enforce NOPS as a minimum. */ |
7651 | if (nops > prev_nop_frag_required) | |
7652 | prev_nop_frag_required = nops; | |
252b5132 | 7653 | |
71400594 RS |
7654 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7655 | { | |
7656 | /* Settle for the current number of nops. Update the history | |
7657 | accordingly (for the benefit of any future .set reorder code). */ | |
7658 | prev_nop_frag = NULL; | |
7659 | insert_into_history (prev_nop_frag_since, | |
7660 | prev_nop_frag_holds, NOP_INSN); | |
7661 | } | |
7662 | else | |
7663 | { | |
7664 | /* Allow this instruction to replace one of the nops that was | |
7665 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7666 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7667 | prev_nop_frag_holds--; |
7668 | prev_nop_frag_since++; | |
252b5132 RH |
7669 | } |
7670 | } | |
7671 | ||
e407c74b | 7672 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7673 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7674 | |
e410add4 RS |
7675 | dwarf2_emit_insn (0); |
7676 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7677 | so "move" the instruction address accordingly. | |
7678 | ||
7679 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7680 | entries. If this instruction is a branch that we are going to swap | |
7681 | with the previous instruction, the two instructions should be | |
7682 | treated as a unit, and the debug information for both instructions | |
7683 | should refer to the start of the branch sequence. Using the | |
7684 | current position is certainly wrong when swapping a 32-bit branch | |
7685 | and a 16-bit delay slot, since the current position would then be | |
7686 | in the middle of a branch. */ | |
7687 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7688 | |
df58fc94 RS |
7689 | relax32 = (mips_relax_branch |
7690 | /* Don't try branch relaxation within .set nomacro, or within | |
7691 | .set noat if we use $at for PIC computations. If it turns | |
7692 | out that the branch was out-of-range, we'll get an error. */ | |
7693 | && !mips_opts.warn_about_macros | |
7694 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7695 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7696 | as they have no complementing branches. */ | |
7697 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7698 | |
7699 | if (!HAVE_CODE_COMPRESSION | |
7700 | && address_expr | |
7701 | && relax32 | |
0b25d3e6 | 7702 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7703 | && delayed_branch_p (ip)) |
4a6a3df4 | 7704 | { |
895921c9 | 7705 | relaxed_branch = TRUE; |
1e915849 RS |
7706 | add_relaxed_insn (ip, (relaxed_branch_length |
7707 | (NULL, NULL, | |
11625dd8 RS |
7708 | uncond_branch_p (ip) ? -1 |
7709 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7710 | : 0)), 4, |
7711 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7712 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7713 | uncond_branch_p (ip), |
7714 | branch_likely_p (ip), | |
1e915849 RS |
7715 | pinfo & INSN_WRITE_GPR_31, |
7716 | 0), | |
7717 | address_expr->X_add_symbol, | |
7718 | address_expr->X_add_number); | |
4a6a3df4 AO |
7719 | *reloc_type = BFD_RELOC_UNUSED; |
7720 | } | |
df58fc94 RS |
7721 | else if (mips_opts.micromips |
7722 | && address_expr | |
7723 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7724 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7725 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7726 | /* Don't try branch relaxation when users specify | |
7727 | 16-bit/32-bit instructions. */ | |
7728 | && !forced_insn_length) | |
df58fc94 | 7729 | { |
7bd374a4 MR |
7730 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7731 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7732 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7733 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7734 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7735 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7736 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7737 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7738 | |
7739 | gas_assert (address_expr != NULL); | |
7740 | gas_assert (!mips_relax.sequence); | |
7741 | ||
2b0c8b40 | 7742 | relaxed_branch = TRUE; |
7bd374a4 MR |
7743 | if (nods) |
7744 | method = APPEND_ADD; | |
7745 | if (relax32) | |
7746 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7747 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7748 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7749 | mips_pic != NO_PIC, |
7bd374a4 | 7750 | uncond, compact, al, nods, |
40209cad | 7751 | relax32, 0, 0), |
df58fc94 RS |
7752 | address_expr->X_add_symbol, |
7753 | address_expr->X_add_number); | |
7754 | *reloc_type = BFD_RELOC_UNUSED; | |
7755 | } | |
7756 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7757 | { |
7fd53920 MR |
7758 | bfd_boolean require_unextended; |
7759 | bfd_boolean require_extended; | |
88a7ef16 MR |
7760 | symbolS *symbol; |
7761 | offsetT offset; | |
7762 | ||
7fd53920 MR |
7763 | if (forced_insn_length != 0) |
7764 | { | |
7765 | require_unextended = forced_insn_length == 2; | |
7766 | require_extended = forced_insn_length == 4; | |
7767 | } | |
7768 | else | |
7769 | { | |
7770 | require_unextended = (mips_opts.noautoextend | |
7771 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7772 | require_extended = 0; | |
7773 | } | |
7774 | ||
252b5132 | 7775 | /* We need to set up a variant frag. */ |
df58fc94 | 7776 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7777 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7778 | symbol created by `make_expr_symbol' may not get a necessary | |
7779 | external relocation produced. */ | |
7780 | if (address_expr->X_op == O_symbol) | |
7781 | { | |
7782 | symbol = address_expr->X_add_symbol; | |
7783 | offset = address_expr->X_add_number; | |
7784 | } | |
7785 | else | |
7786 | { | |
7787 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7788 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7789 | offset = 0; |
7790 | } | |
8507b6e7 | 7791 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7792 | RELAX_MIPS16_ENCODE |
7793 | (*reloc_type - BFD_RELOC_UNUSED, | |
25499ac7 | 7794 | mips_opts.ase & ASE_MIPS16E2, |
8507b6e7 MR |
7795 | mips_pic != NO_PIC, |
7796 | HAVE_32BIT_SYMBOLS, | |
7797 | mips_opts.warn_about_macros, | |
7fd53920 | 7798 | require_unextended, require_extended, |
11625dd8 | 7799 | delayed_branch_p (&history[0]), |
1e915849 | 7800 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7801 | symbol, offset); |
252b5132 | 7802 | } |
5c04167a | 7803 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7804 | { |
11625dd8 | 7805 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7806 | /* Make sure there is enough room to swap this instruction with |
7807 | a following jump instruction. */ | |
7808 | frag_grow (6); | |
1e915849 | 7809 | add_fixed_insn (ip); |
252b5132 RH |
7810 | } |
7811 | else | |
7812 | { | |
7813 | if (mips_opts.mips16 | |
7814 | && mips_opts.noreorder | |
11625dd8 | 7815 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7816 | as_warn (_("extended instruction in delay slot")); |
7817 | ||
4d7206a2 RS |
7818 | if (mips_relax.sequence) |
7819 | { | |
7820 | /* If we've reached the end of this frag, turn it into a variant | |
7821 | frag and record the information for the instructions we've | |
7822 | written so far. */ | |
7823 | if (frag_room () < 4) | |
7824 | relax_close_frag (); | |
df58fc94 | 7825 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7826 | } |
7827 | ||
584892a6 | 7828 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7829 | { |
7830 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7831 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7832 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7833 | mips_macro_warning.insns[0]++; | |
7834 | } | |
584892a6 | 7835 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7836 | { |
7837 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7838 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7839 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7840 | mips_macro_warning.insns[1]++; | |
7841 | } | |
584892a6 | 7842 | |
1e915849 RS |
7843 | if (mips_opts.mips16) |
7844 | { | |
7845 | ip->fixed_p = 1; | |
7846 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7847 | } | |
7848 | add_fixed_insn (ip); | |
252b5132 RH |
7849 | } |
7850 | ||
9fe77896 | 7851 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7852 | { |
df58fc94 | 7853 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7854 | reloc_howto_type *howto0; |
9fe77896 RS |
7855 | reloc_howto_type *howto; |
7856 | int i; | |
34ce925e | 7857 | |
df58fc94 RS |
7858 | /* Perform any necessary conversion to microMIPS relocations |
7859 | and find out how many relocations there actually are. */ | |
7860 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7861 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7862 | ||
9fe77896 RS |
7863 | /* In a compound relocation, it is the final (outermost) |
7864 | operator that determines the relocated field. */ | |
2309ddf2 | 7865 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7866 | if (!howto) |
7867 | abort (); | |
2309ddf2 MR |
7868 | |
7869 | if (i > 1) | |
7870 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7871 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7872 | bfd_get_reloc_size (howto), | |
7873 | address_expr, | |
2309ddf2 MR |
7874 | howto0 && howto0->pc_relative, |
7875 | final_type[0]); | |
ce8ad872 MR |
7876 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7877 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7878 | |
7879 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7880 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7881 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7882 | ||
7883 | /* These relocations can have an addend that won't fit in | |
7884 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7885 | if (GPR_SIZE == 64 |
9fe77896 RS |
7886 | && ! howto->partial_inplace |
7887 | && (reloc_type[0] == BFD_RELOC_16 | |
7888 | || reloc_type[0] == BFD_RELOC_32 | |
7889 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7890 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7891 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7892 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7893 | || reloc_type[0] == BFD_RELOC_64 | |
7894 | || reloc_type[0] == BFD_RELOC_CTOR | |
7895 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7896 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7897 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7898 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7899 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7900 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7901 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7902 | || hi16_reloc_p (reloc_type[0]) | |
7903 | || lo16_reloc_p (reloc_type[0]))) | |
7904 | ip->fixp[0]->fx_no_overflow = 1; | |
7905 | ||
ddaf2c41 MR |
7906 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7907 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7908 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7909 | ip->fixp[0]->fx_no_overflow = 1; | |
7910 | ||
9fe77896 RS |
7911 | if (mips_relax.sequence) |
7912 | { | |
7913 | if (mips_relax.first_fixup == 0) | |
7914 | mips_relax.first_fixup = ip->fixp[0]; | |
7915 | } | |
7916 | else if (reloc_needs_lo_p (*reloc_type)) | |
7917 | { | |
7918 | struct mips_hi_fixup *hi_fixup; | |
7919 | ||
7920 | /* Reuse the last entry if it already has a matching %lo. */ | |
7921 | hi_fixup = mips_hi_fixup_list; | |
7922 | if (hi_fixup == 0 | |
7923 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7924 | { |
325801bd | 7925 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7926 | hi_fixup->next = mips_hi_fixup_list; |
7927 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7928 | } |
9fe77896 RS |
7929 | hi_fixup->fixp = ip->fixp[0]; |
7930 | hi_fixup->seg = now_seg; | |
7931 | } | |
252b5132 | 7932 | |
9fe77896 RS |
7933 | /* Add fixups for the second and third relocations, if given. |
7934 | Note that the ABI allows the second relocation to be | |
7935 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7936 | moment we only use RSS_UNDEF, but we could add support | |
7937 | for the others if it ever becomes necessary. */ | |
7938 | for (i = 1; i < 3; i++) | |
7939 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7940 | { | |
7941 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7942 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7943 | FALSE, final_type[i]); |
f6688943 | 7944 | |
9fe77896 RS |
7945 | /* Use fx_tcbit to mark compound relocs. */ |
7946 | ip->fixp[0]->fx_tcbit = 1; | |
7947 | ip->fixp[i]->fx_tcbit = 1; | |
7948 | } | |
252b5132 | 7949 | } |
252b5132 RH |
7950 | |
7951 | /* Update the register mask information. */ | |
4c260379 RS |
7952 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7953 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7954 | |
a4e06468 | 7955 | switch (method) |
252b5132 | 7956 | { |
a4e06468 RS |
7957 | case APPEND_ADD: |
7958 | insert_into_history (0, 1, ip); | |
7959 | break; | |
7960 | ||
7961 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7962 | { |
7963 | struct mips_cl_insn *nop; | |
7964 | ||
7965 | insert_into_history (0, 1, ip); | |
7966 | nop = get_delay_slot_nop (ip); | |
7967 | add_fixed_insn (nop); | |
7968 | insert_into_history (0, 1, nop); | |
7969 | if (mips_relax.sequence) | |
7970 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7971 | } | |
a4e06468 RS |
7972 | break; |
7973 | ||
7974 | case APPEND_ADD_COMPACT: | |
7975 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
7976 | if (mips_opts.mips16) |
7977 | { | |
7978 | ip->insn_opcode |= 0x0080; | |
7979 | find_altered_mips16_opcode (ip); | |
7980 | } | |
7981 | /* Convert microMIPS instructions. */ | |
7982 | else if (mips_opts.micromips) | |
7983 | { | |
7984 | /* jr16->jrc */ | |
7985 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
7986 | ip->insn_opcode |= 0x0020; | |
7987 | /* b16->bc */ | |
7988 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
7989 | ip->insn_opcode = 0x40e00000; | |
7990 | /* beqz16->beqzc, bnez16->bnezc */ | |
7991 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
7992 | { | |
7993 | unsigned long regno; | |
7994 | ||
7995 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
7996 | regno &= MICROMIPSOP_MASK_MD; | |
7997 | regno = micromips_to_32_reg_d_map[regno]; | |
7998 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
7999 | | (regno << MICROMIPSOP_SH_RS) | |
8000 | | 0x40a00000) ^ 0x00400000; | |
8001 | } | |
8002 | /* beqz->beqzc, bnez->bnezc */ | |
8003 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
8004 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
8005 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
8006 | | 0x40a00000) ^ 0x00400000; | |
8007 | /* beq $0->beqzc, bne $0->bnezc */ | |
8008 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
8009 | ip->insn_opcode = (((ip->insn_opcode >> | |
8010 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
8011 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
8012 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
8013 | | 0x40a00000) ^ 0x00400000; | |
8014 | else | |
8015 | abort (); | |
8016 | find_altered_micromips_opcode (ip); | |
8017 | } | |
8018 | else | |
8019 | abort (); | |
a4e06468 RS |
8020 | install_insn (ip); |
8021 | insert_into_history (0, 1, ip); | |
8022 | break; | |
8023 | ||
8024 | case APPEND_SWAP: | |
8025 | { | |
8026 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
8027 | |
8028 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
8029 | { |
8030 | /* Add the delay slot instruction to the end of the | |
8031 | current frag and shrink the fixed part of the | |
8032 | original frag. If the branch occupies the tail of | |
8033 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 8034 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 8035 | if (delay.frag == ip->frag) |
2b0c8b40 | 8036 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
8037 | add_fixed_insn (&delay); |
8038 | } | |
8039 | else | |
8040 | { | |
5e35670b MR |
8041 | /* If this is not a relaxed branch and we are in the |
8042 | same frag, then just swap the instructions. */ | |
8043 | move_insn (ip, delay.frag, delay.where); | |
8044 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
8045 | } |
8046 | history[0] = *ip; | |
8047 | delay.fixed_p = 1; | |
8048 | insert_into_history (0, 1, &delay); | |
8049 | } | |
8050 | break; | |
252b5132 RH |
8051 | } |
8052 | ||
13408f1e | 8053 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
8054 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
8055 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
8056 | { |
8057 | unsigned int i; | |
8058 | ||
79850f26 | 8059 | mips_no_prev_insn (); |
13408f1e | 8060 | |
e407c74b | 8061 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 8062 | history[i].cleared_p = 1; |
e407c74b NC |
8063 | } |
8064 | ||
df58fc94 RS |
8065 | /* We need to emit a label at the end of branch-likely macros. */ |
8066 | if (emit_branch_likely_macro) | |
8067 | { | |
8068 | emit_branch_likely_macro = FALSE; | |
8069 | micromips_add_label (); | |
8070 | } | |
8071 | ||
252b5132 RH |
8072 | /* We just output an insn, so the next one doesn't have a label. */ |
8073 | mips_clear_insn_labels (); | |
252b5132 RH |
8074 | } |
8075 | ||
e407c74b NC |
8076 | /* Forget that there was any previous instruction or label. |
8077 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
8078 | |
8079 | static void | |
7d10b47d | 8080 | mips_no_prev_insn (void) |
252b5132 | 8081 | { |
7d10b47d RS |
8082 | prev_nop_frag = NULL; |
8083 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
8084 | mips_clear_insn_labels (); |
8085 | } | |
8086 | ||
7d10b47d RS |
8087 | /* This function must be called before we emit something other than |
8088 | instructions. It is like mips_no_prev_insn except that it inserts | |
8089 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 8090 | |
7d10b47d RS |
8091 | void |
8092 | mips_emit_delays (void) | |
252b5132 RH |
8093 | { |
8094 | if (! mips_opts.noreorder) | |
8095 | { | |
932d1a1b | 8096 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
8097 | if (nops > 0) |
8098 | { | |
7d10b47d RS |
8099 | while (nops-- > 0) |
8100 | add_fixed_insn (NOP_INSN); | |
462427c4 | 8101 | mips_move_text_labels (); |
7d10b47d RS |
8102 | } |
8103 | } | |
8104 | mips_no_prev_insn (); | |
8105 | } | |
8106 | ||
8107 | /* Start a (possibly nested) noreorder block. */ | |
8108 | ||
8109 | static void | |
8110 | start_noreorder (void) | |
8111 | { | |
8112 | if (mips_opts.noreorder == 0) | |
8113 | { | |
8114 | unsigned int i; | |
8115 | int nops; | |
8116 | ||
8117 | /* None of the instructions before the .set noreorder can be moved. */ | |
8118 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
8119 | history[i].fixed_p = 1; | |
8120 | ||
8121 | /* Insert any nops that might be needed between the .set noreorder | |
8122 | block and the previous instructions. We will later remove any | |
8123 | nops that turn out not to be needed. */ | |
932d1a1b | 8124 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
8125 | if (nops > 0) |
8126 | { | |
8127 | if (mips_optimize != 0) | |
252b5132 RH |
8128 | { |
8129 | /* Record the frag which holds the nop instructions, so | |
8130 | that we can remove them if we don't need them. */ | |
df58fc94 | 8131 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
8132 | prev_nop_frag = frag_now; |
8133 | prev_nop_frag_holds = nops; | |
8134 | prev_nop_frag_required = 0; | |
8135 | prev_nop_frag_since = 0; | |
8136 | } | |
8137 | ||
8138 | for (; nops > 0; --nops) | |
1e915849 | 8139 | add_fixed_insn (NOP_INSN); |
252b5132 | 8140 | |
7d10b47d RS |
8141 | /* Move on to a new frag, so that it is safe to simply |
8142 | decrease the size of prev_nop_frag. */ | |
8143 | frag_wane (frag_now); | |
8144 | frag_new (0); | |
462427c4 | 8145 | mips_move_text_labels (); |
252b5132 | 8146 | } |
df58fc94 | 8147 | mips_mark_labels (); |
7d10b47d | 8148 | mips_clear_insn_labels (); |
252b5132 | 8149 | } |
7d10b47d RS |
8150 | mips_opts.noreorder++; |
8151 | mips_any_noreorder = 1; | |
8152 | } | |
252b5132 | 8153 | |
7d10b47d | 8154 | /* End a nested noreorder block. */ |
252b5132 | 8155 | |
7d10b47d RS |
8156 | static void |
8157 | end_noreorder (void) | |
8158 | { | |
8159 | mips_opts.noreorder--; | |
8160 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
8161 | { | |
8162 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
8163 | handling nop insertion the .set reorder way. */ | |
8164 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 8165 | * NOP_INSN_SIZE); |
7d10b47d RS |
8166 | insert_into_history (prev_nop_frag_since, |
8167 | prev_nop_frag_required, NOP_INSN); | |
8168 | prev_nop_frag = NULL; | |
8169 | } | |
252b5132 RH |
8170 | } |
8171 | ||
97d87491 RS |
8172 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
8173 | higher bits unset. */ | |
8174 | ||
8175 | static void | |
8176 | normalize_constant_expr (expressionS *ex) | |
8177 | { | |
8178 | if (ex->X_op == O_constant | |
8179 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8180 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8181 | - 0x80000000); | |
8182 | } | |
8183 | ||
8184 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
8185 | all higher bits unset. */ | |
8186 | ||
8187 | static void | |
8188 | normalize_address_expr (expressionS *ex) | |
8189 | { | |
8190 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
8191 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
8192 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8193 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8194 | - 0x80000000); | |
8195 | } | |
8196 | ||
8197 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
8198 | Return true if the match was successful. | |
8199 | ||
8200 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
8201 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
8202 | there are more alternatives after OPCODE and SOFT_MATCH is | |
8203 | as for mips_arg_info. */ | |
8204 | ||
8205 | static bfd_boolean | |
8206 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
8207 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 8208 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
8209 | { |
8210 | const char *args; | |
8211 | struct mips_arg_info arg; | |
8212 | const struct mips_operand *operand; | |
8213 | char c; | |
8214 | ||
8215 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8216 | offset_expr.X_op = O_absent; |
8217 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8218 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8219 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8220 | ||
8221 | create_insn (insn, opcode); | |
60f20e8b RS |
8222 | /* When no opcode suffix is specified, assume ".xyzw". */ |
8223 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
8224 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
8225 | else | |
8226 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
8227 | memset (&arg, 0, sizeof (arg)); |
8228 | arg.insn = insn; | |
8229 | arg.token = tokens; | |
8230 | arg.argnum = 1; | |
8231 | arg.last_regno = ILLEGAL_REG; | |
8232 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 8233 | arg.lax_match = lax_match; |
97d87491 RS |
8234 | for (args = opcode->args;; ++args) |
8235 | { | |
8236 | if (arg.token->type == OT_END) | |
8237 | { | |
8238 | /* Handle unary instructions in which only one operand is given. | |
8239 | The source is then the same as the destination. */ | |
8240 | if (arg.opnum == 1 && *args == ',') | |
8241 | { | |
8242 | operand = (mips_opts.micromips | |
8243 | ? decode_micromips_operand (args + 1) | |
8244 | : decode_mips_operand (args + 1)); | |
8245 | if (operand && mips_optional_operand_p (operand)) | |
8246 | { | |
8247 | arg.token = tokens; | |
8248 | arg.argnum = 1; | |
8249 | continue; | |
8250 | } | |
8251 | } | |
8252 | ||
8253 | /* Treat elided base registers as $0. */ | |
8254 | if (strcmp (args, "(b)") == 0) | |
8255 | args += 3; | |
8256 | ||
8257 | if (args[0] == '+') | |
8258 | switch (args[1]) | |
8259 | { | |
8260 | case 'K': | |
8261 | case 'N': | |
8262 | /* The register suffix is optional. */ | |
8263 | args += 2; | |
8264 | break; | |
8265 | } | |
8266 | ||
8267 | /* Fail the match if there were too few operands. */ | |
8268 | if (*args) | |
8269 | return FALSE; | |
8270 | ||
8271 | /* Successful match. */ | |
60f20e8b RS |
8272 | if (!complete_p) |
8273 | return TRUE; | |
e3de51ce | 8274 | clear_insn_error (); |
97d87491 RS |
8275 | if (arg.dest_regno == arg.last_regno |
8276 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
8277 | { | |
8278 | if (arg.opnum == 2) | |
e3de51ce | 8279 | set_insn_error |
1661c76c | 8280 | (0, _("source and destination must be different")); |
97d87491 | 8281 | else if (arg.last_regno == 31) |
e3de51ce | 8282 | set_insn_error |
1661c76c | 8283 | (0, _("a destination register must be supplied")); |
97d87491 | 8284 | } |
173d3447 CF |
8285 | else if (arg.last_regno == 31 |
8286 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
8287 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
8288 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
8289 | check_completed_insn (&arg); |
8290 | return TRUE; | |
8291 | } | |
8292 | ||
8293 | /* Fail the match if the line has too many operands. */ | |
8294 | if (*args == 0) | |
8295 | return FALSE; | |
8296 | ||
8297 | /* Handle characters that need to match exactly. */ | |
8298 | if (*args == '(' || *args == ')' || *args == ',') | |
8299 | { | |
8300 | if (match_char (&arg, *args)) | |
8301 | continue; | |
8302 | return FALSE; | |
8303 | } | |
8304 | if (*args == '#') | |
8305 | { | |
8306 | ++args; | |
8307 | if (arg.token->type == OT_DOUBLE_CHAR | |
8308 | && arg.token->u.ch == *args) | |
8309 | { | |
8310 | ++arg.token; | |
8311 | continue; | |
8312 | } | |
8313 | return FALSE; | |
8314 | } | |
8315 | ||
8316 | /* Handle special macro operands. Work out the properties of | |
8317 | other operands. */ | |
8318 | arg.opnum += 1; | |
97d87491 RS |
8319 | switch (*args) |
8320 | { | |
7361da2c AB |
8321 | case '-': |
8322 | switch (args[1]) | |
8323 | { | |
8324 | case 'A': | |
8325 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
8326 | break; | |
8327 | ||
8328 | case 'B': | |
8329 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
8330 | break; | |
8331 | } | |
8332 | break; | |
8333 | ||
97d87491 RS |
8334 | case '+': |
8335 | switch (args[1]) | |
8336 | { | |
97d87491 RS |
8337 | case 'i': |
8338 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8339 | break; | |
7361da2c AB |
8340 | |
8341 | case '\'': | |
8342 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
8343 | break; | |
8344 | ||
8345 | case '\"': | |
8346 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
8347 | break; | |
97d87491 RS |
8348 | } |
8349 | break; | |
8350 | ||
97d87491 | 8351 | case 'I': |
1a00e612 RS |
8352 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8353 | return FALSE; | |
8354 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8355 | if (GPR_SIZE == 32) |
97d87491 RS |
8356 | normalize_constant_expr (&imm_expr); |
8357 | continue; | |
8358 | ||
8359 | case 'A': | |
8360 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8361 | { | |
8362 | /* Assume that the offset has been elided and that what | |
8363 | we saw was a base register. The match will fail later | |
8364 | if that assumption turns out to be wrong. */ | |
8365 | offset_expr.X_op = O_constant; | |
8366 | offset_expr.X_add_number = 0; | |
8367 | } | |
97d87491 | 8368 | else |
1a00e612 RS |
8369 | { |
8370 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8371 | return FALSE; | |
8372 | normalize_address_expr (&offset_expr); | |
8373 | } | |
97d87491 RS |
8374 | continue; |
8375 | ||
8376 | case 'F': | |
8377 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8378 | 8, TRUE)) | |
1a00e612 | 8379 | return FALSE; |
97d87491 RS |
8380 | continue; |
8381 | ||
8382 | case 'L': | |
8383 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8384 | 8, FALSE)) | |
1a00e612 | 8385 | return FALSE; |
97d87491 RS |
8386 | continue; |
8387 | ||
8388 | case 'f': | |
8389 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8390 | 4, TRUE)) | |
1a00e612 | 8391 | return FALSE; |
97d87491 RS |
8392 | continue; |
8393 | ||
8394 | case 'l': | |
8395 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8396 | 4, FALSE)) | |
1a00e612 | 8397 | return FALSE; |
97d87491 RS |
8398 | continue; |
8399 | ||
97d87491 RS |
8400 | case 'p': |
8401 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8402 | break; | |
8403 | ||
8404 | case 'a': | |
8405 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8406 | break; | |
8407 | ||
8408 | case 'm': | |
8409 | gas_assert (mips_opts.micromips); | |
8410 | c = args[1]; | |
8411 | switch (c) | |
8412 | { | |
8413 | case 'D': | |
8414 | case 'E': | |
8415 | if (!forced_insn_length) | |
8416 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8417 | else if (c == 'D') | |
8418 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8419 | else | |
8420 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8421 | break; | |
8422 | } | |
8423 | break; | |
8424 | } | |
8425 | ||
8426 | operand = (mips_opts.micromips | |
8427 | ? decode_micromips_operand (args) | |
8428 | : decode_mips_operand (args)); | |
8429 | if (!operand) | |
8430 | abort (); | |
8431 | ||
8432 | /* Skip prefixes. */ | |
7361da2c | 8433 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8434 | args++; |
8435 | ||
8436 | if (mips_optional_operand_p (operand) | |
8437 | && args[1] == ',' | |
8438 | && (arg.token[0].type != OT_REG | |
8439 | || arg.token[1].type == OT_END)) | |
8440 | { | |
8441 | /* Assume that the register has been elided and is the | |
8442 | same as the first operand. */ | |
8443 | arg.token = tokens; | |
8444 | arg.argnum = 1; | |
8445 | } | |
8446 | ||
8447 | if (!match_operand (&arg, operand)) | |
8448 | return FALSE; | |
8449 | } | |
8450 | } | |
8451 | ||
8452 | /* Like match_insn, but for MIPS16. */ | |
8453 | ||
8454 | static bfd_boolean | |
8455 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8456 | struct mips_operand_token *tokens) |
97d87491 RS |
8457 | { |
8458 | const char *args; | |
8459 | const struct mips_operand *operand; | |
8460 | const struct mips_operand *ext_operand; | |
82d808ed | 8461 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8462 | int required_insn_length; |
97d87491 RS |
8463 | struct mips_arg_info arg; |
8464 | int relax_char; | |
8465 | ||
7fd53920 MR |
8466 | if (forced_insn_length) |
8467 | required_insn_length = forced_insn_length; | |
8468 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8469 | required_insn_length = 2; | |
8470 | else | |
8471 | required_insn_length = 0; | |
8472 | ||
97d87491 RS |
8473 | create_insn (insn, opcode); |
8474 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8475 | offset_expr.X_op = O_absent; |
8476 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8477 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8478 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8479 | relax_char = 0; | |
8480 | ||
8481 | memset (&arg, 0, sizeof (arg)); | |
8482 | arg.insn = insn; | |
8483 | arg.token = tokens; | |
8484 | arg.argnum = 1; | |
8485 | arg.last_regno = ILLEGAL_REG; | |
8486 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8487 | relax_char = 0; |
8488 | for (args = opcode->args;; ++args) | |
8489 | { | |
8490 | int c; | |
8491 | ||
8492 | if (arg.token->type == OT_END) | |
8493 | { | |
8494 | offsetT value; | |
8495 | ||
8496 | /* Handle unary instructions in which only one operand is given. | |
8497 | The source is then the same as the destination. */ | |
8498 | if (arg.opnum == 1 && *args == ',') | |
8499 | { | |
8500 | operand = decode_mips16_operand (args[1], FALSE); | |
8501 | if (operand && mips_optional_operand_p (operand)) | |
8502 | { | |
8503 | arg.token = tokens; | |
8504 | arg.argnum = 1; | |
8505 | continue; | |
8506 | } | |
8507 | } | |
8508 | ||
8509 | /* Fail the match if there were too few operands. */ | |
8510 | if (*args) | |
8511 | return FALSE; | |
8512 | ||
8513 | /* Successful match. Stuff the immediate value in now, if | |
8514 | we can. */ | |
e3de51ce | 8515 | clear_insn_error (); |
97d87491 RS |
8516 | if (opcode->pinfo == INSN_MACRO) |
8517 | { | |
8518 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8519 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8520 | } | |
8521 | else if (relax_char | |
8522 | && offset_expr.X_op == O_constant | |
82d808ed | 8523 | && !pcrel |
97d87491 RS |
8524 | && calculate_reloc (*offset_reloc, |
8525 | offset_expr.X_add_number, | |
8526 | &value)) | |
8527 | { | |
8528 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8529 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8530 | offset_expr.X_op = O_absent; |
8531 | *offset_reloc = BFD_RELOC_UNUSED; | |
8532 | } | |
8533 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8534 | { | |
7fd53920 | 8535 | if (required_insn_length == 2) |
e3de51ce | 8536 | set_insn_error (0, _("invalid unextended operand value")); |
25499ac7 | 8537 | else if (!mips_opcode_32bit_p (opcode)) |
1da43acc MR |
8538 | { |
8539 | forced_insn_length = 4; | |
8540 | insn->insn_opcode |= MIPS16_EXTEND; | |
8541 | } | |
97d87491 RS |
8542 | } |
8543 | else if (relax_char) | |
8544 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8545 | ||
8546 | check_completed_insn (&arg); | |
8547 | return TRUE; | |
8548 | } | |
8549 | ||
8550 | /* Fail the match if the line has too many operands. */ | |
8551 | if (*args == 0) | |
8552 | return FALSE; | |
8553 | ||
8554 | /* Handle characters that need to match exactly. */ | |
8555 | if (*args == '(' || *args == ')' || *args == ',') | |
8556 | { | |
8557 | if (match_char (&arg, *args)) | |
8558 | continue; | |
8559 | return FALSE; | |
8560 | } | |
8561 | ||
8562 | arg.opnum += 1; | |
8563 | c = *args; | |
8564 | switch (c) | |
8565 | { | |
8566 | case 'p': | |
8567 | case 'q': | |
8568 | case 'A': | |
8569 | case 'B': | |
8570 | case 'E': | |
25499ac7 MR |
8571 | case 'V': |
8572 | case 'u': | |
97d87491 RS |
8573 | relax_char = c; |
8574 | break; | |
8575 | ||
8576 | case 'I': | |
1a00e612 RS |
8577 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8578 | return FALSE; | |
8579 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8580 | if (GPR_SIZE == 32) |
97d87491 RS |
8581 | normalize_constant_expr (&imm_expr); |
8582 | continue; | |
8583 | ||
8584 | case 'a': | |
8585 | case 'i': | |
8586 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8587 | break; |
8588 | } | |
8589 | ||
7fd53920 | 8590 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8591 | if (!operand) |
8592 | abort (); | |
8593 | ||
82d808ed MR |
8594 | if (operand->type == OP_PCREL) |
8595 | pcrel = TRUE; | |
8596 | else | |
97d87491 RS |
8597 | { |
8598 | ext_operand = decode_mips16_operand (c, TRUE); | |
8599 | if (operand != ext_operand) | |
8600 | { | |
8601 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8602 | { | |
8603 | offset_expr.X_op = O_constant; | |
8604 | offset_expr.X_add_number = 0; | |
8605 | relax_char = c; | |
8606 | continue; | |
8607 | } | |
8608 | ||
1a7bf198 | 8609 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
97d87491 RS |
8610 | return FALSE; |
8611 | ||
8612 | /* '8' is used for SLTI(U) and has traditionally not | |
8613 | been allowed to take relocation operators. */ | |
8614 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8615 | && (ext_operand->size != 16 || c == '8')) | |
e295202f MR |
8616 | { |
8617 | match_not_constant (&arg); | |
8618 | return FALSE; | |
8619 | } | |
97d87491 | 8620 | |
c96425c5 MR |
8621 | if (offset_expr.X_op == O_big) |
8622 | { | |
8623 | match_out_of_range (&arg); | |
8624 | return FALSE; | |
8625 | } | |
8626 | ||
97d87491 RS |
8627 | relax_char = c; |
8628 | continue; | |
8629 | } | |
8630 | } | |
8631 | ||
8632 | if (mips_optional_operand_p (operand) | |
8633 | && args[1] == ',' | |
8634 | && (arg.token[0].type != OT_REG | |
8635 | || arg.token[1].type == OT_END)) | |
8636 | { | |
8637 | /* Assume that the register has been elided and is the | |
8638 | same as the first operand. */ | |
8639 | arg.token = tokens; | |
8640 | arg.argnum = 1; | |
8641 | } | |
8642 | ||
8643 | if (!match_operand (&arg, operand)) | |
8644 | return FALSE; | |
8645 | } | |
8646 | } | |
8647 | ||
60f20e8b RS |
8648 | /* Record that the current instruction is invalid for the current ISA. */ |
8649 | ||
8650 | static void | |
8651 | match_invalid_for_isa (void) | |
8652 | { | |
8653 | set_insn_error_ss | |
1661c76c | 8654 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8655 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8656 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8657 | } | |
8658 | ||
8659 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8660 | Return true if a definite match or failure was found, storing any match | |
8661 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8662 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8663 | tried and failed to match under normal conditions and now want to try a | |
8664 | more relaxed match. */ | |
8665 | ||
8666 | static bfd_boolean | |
8667 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8668 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8669 | int opcode_extra, bfd_boolean lax_match) | |
8670 | { | |
8671 | const struct mips_opcode *opcode; | |
8672 | const struct mips_opcode *invalid_delay_slot; | |
8673 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8674 | ||
8675 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8676 | current ISA or forced_length. */ | |
8677 | invalid_delay_slot = 0; | |
8678 | seen_valid_for_isa = FALSE; | |
8679 | seen_valid_for_size = FALSE; | |
8680 | opcode = first; | |
8681 | do | |
8682 | { | |
8683 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8684 | if (is_opcode_valid (opcode)) | |
8685 | { | |
8686 | seen_valid_for_isa = TRUE; | |
8687 | if (is_size_valid (opcode)) | |
8688 | { | |
8689 | bfd_boolean delay_slot_ok; | |
8690 | ||
8691 | seen_valid_for_size = TRUE; | |
8692 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8693 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8694 | lax_match, delay_slot_ok)) | |
8695 | { | |
8696 | if (!delay_slot_ok) | |
8697 | { | |
8698 | if (!invalid_delay_slot) | |
8699 | invalid_delay_slot = opcode; | |
8700 | } | |
8701 | else | |
8702 | return TRUE; | |
8703 | } | |
8704 | } | |
8705 | } | |
8706 | ++opcode; | |
8707 | } | |
8708 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8709 | ||
8710 | /* If the only matches we found had the wrong length for the delay slot, | |
8711 | pick the first such match. We'll issue an appropriate warning later. */ | |
8712 | if (invalid_delay_slot) | |
8713 | { | |
8714 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8715 | lax_match, TRUE)) | |
8716 | return TRUE; | |
8717 | abort (); | |
8718 | } | |
8719 | ||
8720 | /* Handle the case where we didn't try to match an instruction because | |
8721 | all the alternatives were incompatible with the current ISA. */ | |
8722 | if (!seen_valid_for_isa) | |
8723 | { | |
8724 | match_invalid_for_isa (); | |
8725 | return TRUE; | |
8726 | } | |
8727 | ||
8728 | /* Handle the case where we didn't try to match an instruction because | |
8729 | all the alternatives were of the wrong size. */ | |
8730 | if (!seen_valid_for_size) | |
8731 | { | |
8732 | if (mips_opts.insn32) | |
1661c76c | 8733 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8734 | else |
8735 | set_insn_error_i | |
1661c76c | 8736 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8737 | 8 * forced_insn_length); |
8738 | return TRUE; | |
8739 | } | |
8740 | ||
8741 | return FALSE; | |
8742 | } | |
8743 | ||
8744 | /* Like match_insns, but for MIPS16. */ | |
8745 | ||
8746 | static bfd_boolean | |
8747 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8748 | struct mips_operand_token *tokens) | |
8749 | { | |
8750 | const struct mips_opcode *opcode; | |
8751 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8752 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8753 | |
8754 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8755 | current ISA. There are no separate entries for extended forms so | |
8756 | we deal with forced_length later. */ | |
8757 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8758 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8759 | opcode = first; |
8760 | do | |
8761 | { | |
8762 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8763 | if (is_opcode_valid_16 (opcode)) | |
8764 | { | |
8765 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8766 | if (is_size_valid_16 (opcode)) |
8767 | { | |
8768 | seen_valid_for_size = TRUE; | |
8769 | if (match_mips16_insn (insn, opcode, tokens)) | |
8770 | return TRUE; | |
8771 | } | |
60f20e8b RS |
8772 | } |
8773 | ++opcode; | |
8774 | } | |
8775 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8776 | && strcmp (opcode->name, first->name) == 0); | |
8777 | ||
8778 | /* Handle the case where we didn't try to match an instruction because | |
8779 | all the alternatives were incompatible with the current ISA. */ | |
8780 | if (!seen_valid_for_isa) | |
8781 | { | |
8782 | match_invalid_for_isa (); | |
8783 | return TRUE; | |
8784 | } | |
8785 | ||
7fd53920 MR |
8786 | /* Handle the case where we didn't try to match an instruction because |
8787 | all the alternatives were of the wrong size. */ | |
8788 | if (!seen_valid_for_size) | |
8789 | { | |
8790 | if (forced_insn_length == 2) | |
8791 | set_insn_error | |
8792 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8793 | else | |
8794 | set_insn_error | |
8795 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8796 | return TRUE; | |
8797 | } | |
8798 | ||
60f20e8b RS |
8799 | return FALSE; |
8800 | } | |
8801 | ||
584892a6 RS |
8802 | /* Set up global variables for the start of a new macro. */ |
8803 | ||
8804 | static void | |
8805 | macro_start (void) | |
8806 | { | |
8807 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8808 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8809 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8810 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8811 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8812 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8813 | if (history[0].frag |
8814 | && history[0].frag->fr_type == rs_machine_dependent | |
8815 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8816 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8817 | mips_macro_warning.delay_slot_length = 0; | |
8818 | else | |
8819 | switch (history[0].insn_mo->pinfo2 | |
8820 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8821 | { | |
8822 | case INSN2_BRANCH_DELAY_32BIT: | |
8823 | mips_macro_warning.delay_slot_length = 4; | |
8824 | break; | |
8825 | case INSN2_BRANCH_DELAY_16BIT: | |
8826 | mips_macro_warning.delay_slot_length = 2; | |
8827 | break; | |
8828 | default: | |
8829 | mips_macro_warning.delay_slot_length = 0; | |
8830 | break; | |
8831 | } | |
df58fc94 | 8832 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8833 | } |
8834 | ||
df58fc94 RS |
8835 | /* Given that a macro is longer than one instruction or of the wrong size, |
8836 | return the appropriate warning for it. Return null if no warning is | |
8837 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8838 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8839 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8840 | |
8841 | static const char * | |
8842 | macro_warning (relax_substateT subtype) | |
8843 | { | |
8844 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8845 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8846 | " in a branch delay slot"); |
8847 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8848 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8849 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8850 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8851 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8852 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8853 | " in a 16-bit branch delay slot") |
1661c76c | 8854 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8855 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8856 | else |
8857 | return 0; | |
8858 | } | |
8859 | ||
8860 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8861 | ||
8862 | static void | |
8863 | macro_end (void) | |
8864 | { | |
df58fc94 RS |
8865 | /* Relaxation warning flags. */ |
8866 | relax_substateT subtype = 0; | |
8867 | ||
8868 | /* Check delay slot size requirements. */ | |
8869 | if (mips_macro_warning.delay_slot_length == 2) | |
8870 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8871 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8872 | { |
df58fc94 RS |
8873 | if (mips_macro_warning.delay_slot_length |
8874 | != mips_macro_warning.first_insn_sizes[0]) | |
8875 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8876 | if (mips_macro_warning.delay_slot_length | |
8877 | != mips_macro_warning.first_insn_sizes[1]) | |
8878 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8879 | } | |
584892a6 | 8880 | |
df58fc94 RS |
8881 | /* Check instruction count requirements. */ |
8882 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8883 | { | |
8884 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8885 | subtype |= RELAX_SECOND_LONGER; |
8886 | if (mips_opts.warn_about_macros) | |
8887 | subtype |= RELAX_NOMACRO; | |
8888 | if (mips_macro_warning.delay_slot_p) | |
8889 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8890 | } |
584892a6 | 8891 | |
df58fc94 RS |
8892 | /* If both alternatives fail to fill a delay slot correctly, |
8893 | emit the warning now. */ | |
8894 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8895 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8896 | { | |
8897 | relax_substateT s; | |
8898 | const char *msg; | |
8899 | ||
8900 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8901 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8902 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8903 | msg = macro_warning (s); | |
8904 | if (msg != NULL) | |
8905 | as_warn ("%s", msg); | |
8906 | subtype &= ~s; | |
8907 | } | |
8908 | ||
8909 | /* If both implementations are longer than 1 instruction, then emit the | |
8910 | warning now. */ | |
8911 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8912 | { | |
8913 | relax_substateT s; | |
8914 | const char *msg; | |
8915 | ||
8916 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8917 | msg = macro_warning (s); | |
8918 | if (msg != NULL) | |
8919 | as_warn ("%s", msg); | |
8920 | subtype &= ~s; | |
584892a6 | 8921 | } |
df58fc94 RS |
8922 | |
8923 | /* If any flags still set, then one implementation might need a warning | |
8924 | and the other either will need one of a different kind or none at all. | |
8925 | Pass any remaining flags over to relaxation. */ | |
8926 | if (mips_macro_warning.first_frag != NULL) | |
8927 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8928 | } |
8929 | ||
df58fc94 RS |
8930 | /* Instruction operand formats used in macros that vary between |
8931 | standard MIPS and microMIPS code. */ | |
8932 | ||
833794fc | 8933 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8934 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8935 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8936 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8937 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8938 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8939 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8940 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8941 | ||
833794fc | 8942 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8943 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8944 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8945 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8946 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8947 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8948 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8949 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8950 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8951 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8952 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8953 | ||
6e1304d8 RS |
8954 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8955 | The first argument in *ARGS will be either the code for a single | |
8956 | relocation or -1 followed by the three codes that make up a | |
8957 | composite relocation. */ | |
8958 | ||
8959 | static void | |
8960 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8961 | { | |
8962 | int i, next; | |
8963 | ||
8964 | next = va_arg (*args, int); | |
8965 | if (next >= 0) | |
8966 | r[0] = (bfd_reloc_code_real_type) next; | |
8967 | else | |
f2ae14a1 RS |
8968 | { |
8969 | for (i = 0; i < 3; i++) | |
8970 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8971 | /* This function is only used for 16-bit relocation fields. | |
8972 | To make the macro code simpler, treat an unrelocated value | |
8973 | in the same way as BFD_RELOC_LO16. */ | |
8974 | if (r[0] == BFD_RELOC_UNUSED) | |
8975 | r[0] = BFD_RELOC_LO16; | |
8976 | } | |
6e1304d8 RS |
8977 | } |
8978 | ||
252b5132 RH |
8979 | /* Build an instruction created by a macro expansion. This is passed |
8980 | a pointer to the count of instructions created so far, an | |
8981 | expression, the name of the instruction to build, an operand format | |
8982 | string, and corresponding arguments. */ | |
8983 | ||
252b5132 | 8984 | static void |
67c0d1eb | 8985 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8986 | { |
df58fc94 | 8987 | const struct mips_opcode *mo = NULL; |
f6688943 | 8988 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8989 | const struct mips_opcode *amo; |
e077a1c8 | 8990 | const struct mips_operand *operand; |
df58fc94 RS |
8991 | struct hash_control *hash; |
8992 | struct mips_cl_insn insn; | |
252b5132 | 8993 | va_list args; |
e077a1c8 | 8994 | unsigned int uval; |
252b5132 | 8995 | |
252b5132 | 8996 | va_start (args, fmt); |
252b5132 | 8997 | |
252b5132 RH |
8998 | if (mips_opts.mips16) |
8999 | { | |
03ea81db | 9000 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
9001 | va_end (args); |
9002 | return; | |
9003 | } | |
9004 | ||
f6688943 TS |
9005 | r[0] = BFD_RELOC_UNUSED; |
9006 | r[1] = BFD_RELOC_UNUSED; | |
9007 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
9008 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
9009 | amo = (struct mips_opcode *) hash_find (hash, name); | |
9010 | gas_assert (amo); | |
9011 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 9012 | |
df58fc94 | 9013 | do |
8b082fb1 TS |
9014 | { |
9015 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 9016 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 9017 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
9018 | slot instruction length requirement (if any) of the previous |
9019 | instruction. While doing this we record the first instruction | |
9020 | seen that matches all the other conditions and use it anyway | |
9021 | if the requirement cannot be met; we will issue an appropriate | |
9022 | warning later on. */ | |
9023 | if (strcmp (fmt, amo->args) == 0 | |
9024 | && amo->pinfo != INSN_MACRO | |
9025 | && is_opcode_valid (amo) | |
9026 | && is_size_valid (amo)) | |
9027 | { | |
9028 | if (is_delay_slot_valid (amo)) | |
9029 | { | |
9030 | mo = amo; | |
9031 | break; | |
9032 | } | |
9033 | else if (!mo) | |
9034 | mo = amo; | |
9035 | } | |
8b082fb1 | 9036 | |
df58fc94 RS |
9037 | ++amo; |
9038 | gas_assert (amo->name); | |
252b5132 | 9039 | } |
df58fc94 | 9040 | while (strcmp (name, amo->name) == 0); |
252b5132 | 9041 | |
df58fc94 | 9042 | gas_assert (mo); |
1e915849 | 9043 | create_insn (&insn, mo); |
e077a1c8 | 9044 | for (; *fmt; ++fmt) |
252b5132 | 9045 | { |
e077a1c8 | 9046 | switch (*fmt) |
252b5132 | 9047 | { |
252b5132 RH |
9048 | case ',': |
9049 | case '(': | |
9050 | case ')': | |
252b5132 | 9051 | case 'z': |
e077a1c8 | 9052 | break; |
252b5132 RH |
9053 | |
9054 | case 'i': | |
9055 | case 'j': | |
6e1304d8 | 9056 | macro_read_relocs (&args, r); |
9c2799c2 | 9057 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
9058 | || *r == BFD_RELOC_MIPS_HIGHER |
9059 | || *r == BFD_RELOC_HI16_S | |
9060 | || *r == BFD_RELOC_LO16 | |
14c80123 MR |
9061 | || *r == BFD_RELOC_MIPS_GOT_OFST |
9062 | || (mips_opts.micromips | |
9063 | && (*r == BFD_RELOC_16 | |
9064 | || *r == BFD_RELOC_MIPS_GOT16 | |
9065 | || *r == BFD_RELOC_MIPS_CALL16 | |
9066 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
9067 | || *r == BFD_RELOC_MIPS_GOT_LO16 | |
9068 | || *r == BFD_RELOC_MIPS_CALL_HI16 | |
9069 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
9070 | || *r == BFD_RELOC_MIPS_SUB | |
9071 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
9072 | || *r == BFD_RELOC_MIPS_HIGHEST | |
9073 | || *r == BFD_RELOC_MIPS_GOT_DISP | |
9074 | || *r == BFD_RELOC_MIPS_TLS_GD | |
9075 | || *r == BFD_RELOC_MIPS_TLS_LDM | |
9076 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16 | |
9077 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16 | |
9078 | || *r == BFD_RELOC_MIPS_TLS_GOTTPREL | |
9079 | || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16 | |
9080 | || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16))); | |
e077a1c8 | 9081 | break; |
e391c024 RS |
9082 | |
9083 | case 'o': | |
9084 | macro_read_relocs (&args, r); | |
e077a1c8 | 9085 | break; |
252b5132 RH |
9086 | |
9087 | case 'u': | |
6e1304d8 | 9088 | macro_read_relocs (&args, r); |
9c2799c2 | 9089 | gas_assert (ep != NULL |
90ecf173 MR |
9090 | && (ep->X_op == O_constant |
9091 | || (ep->X_op == O_symbol | |
9092 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
9093 | || *r == BFD_RELOC_HI16_S | |
9094 | || *r == BFD_RELOC_HI16 | |
9095 | || *r == BFD_RELOC_GPREL16 | |
9096 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
9097 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 9098 | break; |
252b5132 RH |
9099 | |
9100 | case 'p': | |
9c2799c2 | 9101 | gas_assert (ep != NULL); |
bad36eac | 9102 | |
252b5132 RH |
9103 | /* |
9104 | * This allows macro() to pass an immediate expression for | |
9105 | * creating short branches without creating a symbol. | |
bad36eac DJ |
9106 | * |
9107 | * We don't allow branch relaxation for these branches, as | |
9108 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
9109 | */ |
9110 | if (ep->X_op == O_constant) | |
9111 | { | |
df58fc94 RS |
9112 | /* For microMIPS we always use relocations for branches. |
9113 | So we should not resolve immediate values. */ | |
9114 | gas_assert (!mips_opts.micromips); | |
9115 | ||
bad36eac DJ |
9116 | if ((ep->X_add_number & 3) != 0) |
9117 | as_bad (_("branch to misaligned address (0x%lx)"), | |
9118 | (unsigned long) ep->X_add_number); | |
9119 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
9120 | as_bad (_("branch address range overflow (0x%lx)"), | |
9121 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
9122 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
9123 | ep = NULL; | |
9124 | } | |
9125 | else | |
0b25d3e6 | 9126 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 9127 | break; |
252b5132 RH |
9128 | |
9129 | case 'a': | |
9c2799c2 | 9130 | gas_assert (ep != NULL); |
f6688943 | 9131 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 9132 | break; |
d43b4baf | 9133 | |
252b5132 | 9134 | default: |
e077a1c8 RS |
9135 | operand = (mips_opts.micromips |
9136 | ? decode_micromips_operand (fmt) | |
9137 | : decode_mips_operand (fmt)); | |
9138 | if (!operand) | |
9139 | abort (); | |
9140 | ||
9141 | uval = va_arg (args, int); | |
9142 | if (operand->type == OP_CLO_CLZ_DEST) | |
9143 | uval |= (uval << 5); | |
9144 | insn_insert_operand (&insn, operand, uval); | |
9145 | ||
7361da2c | 9146 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
9147 | ++fmt; |
9148 | break; | |
252b5132 | 9149 | } |
252b5132 RH |
9150 | } |
9151 | va_end (args); | |
9c2799c2 | 9152 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9153 | |
df58fc94 | 9154 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9155 | } |
9156 | ||
9157 | static void | |
67c0d1eb | 9158 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 9159 | va_list *args) |
252b5132 | 9160 | { |
1e915849 | 9161 | struct mips_opcode *mo; |
252b5132 | 9162 | struct mips_cl_insn insn; |
e077a1c8 | 9163 | const struct mips_operand *operand; |
f6688943 TS |
9164 | bfd_reloc_code_real_type r[3] |
9165 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 9166 | |
1e915849 | 9167 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
9168 | gas_assert (mo); |
9169 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 9170 | |
1e915849 | 9171 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 9172 | { |
1e915849 | 9173 | ++mo; |
9c2799c2 NC |
9174 | gas_assert (mo->name); |
9175 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
9176 | } |
9177 | ||
1e915849 | 9178 | create_insn (&insn, mo); |
e077a1c8 | 9179 | for (; *fmt; ++fmt) |
252b5132 RH |
9180 | { |
9181 | int c; | |
9182 | ||
e077a1c8 | 9183 | c = *fmt; |
252b5132 RH |
9184 | switch (c) |
9185 | { | |
252b5132 RH |
9186 | case ',': |
9187 | case '(': | |
9188 | case ')': | |
e077a1c8 | 9189 | break; |
252b5132 | 9190 | |
d8722d76 | 9191 | case '.': |
252b5132 RH |
9192 | case 'S': |
9193 | case 'P': | |
9194 | case 'R': | |
e077a1c8 | 9195 | break; |
252b5132 RH |
9196 | |
9197 | case '<': | |
252b5132 | 9198 | case '5': |
d8722d76 | 9199 | case 'F': |
252b5132 RH |
9200 | case 'H': |
9201 | case 'W': | |
9202 | case 'D': | |
9203 | case 'j': | |
9204 | case '8': | |
9205 | case 'V': | |
9206 | case 'C': | |
9207 | case 'U': | |
9208 | case 'k': | |
9209 | case 'K': | |
9210 | case 'p': | |
9211 | case 'q': | |
9212 | { | |
b886a2ab RS |
9213 | offsetT value; |
9214 | ||
9c2799c2 | 9215 | gas_assert (ep != NULL); |
252b5132 RH |
9216 | |
9217 | if (ep->X_op != O_constant) | |
874e8986 | 9218 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 9219 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 9220 | { |
b886a2ab | 9221 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 9222 | ep = NULL; |
f6688943 | 9223 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
9224 | } |
9225 | } | |
e077a1c8 | 9226 | break; |
252b5132 | 9227 | |
e077a1c8 RS |
9228 | default: |
9229 | operand = decode_mips16_operand (c, FALSE); | |
9230 | if (!operand) | |
9231 | abort (); | |
252b5132 | 9232 | |
4a06e5a2 | 9233 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
9234 | break; |
9235 | } | |
252b5132 RH |
9236 | } |
9237 | ||
9c2799c2 | 9238 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9239 | |
df58fc94 | 9240 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9241 | } |
9242 | ||
438c16b8 TS |
9243 | /* |
9244 | * Generate a "jalr" instruction with a relocation hint to the called | |
9245 | * function. This occurs in NewABI PIC code. | |
9246 | */ | |
9247 | static void | |
df58fc94 | 9248 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 9249 | { |
df58fc94 RS |
9250 | static const bfd_reloc_code_real_type jalr_relocs[2] |
9251 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
9252 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
9253 | const char *jalr; | |
685736be | 9254 | char *f = NULL; |
b34976b6 | 9255 | |
1180b5a4 | 9256 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 9257 | { |
cc3d92a5 | 9258 | frag_grow (8); |
f21f8242 AO |
9259 | f = frag_more (0); |
9260 | } | |
2906b037 | 9261 | if (mips_opts.micromips) |
df58fc94 | 9262 | { |
833794fc MR |
9263 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
9264 | ? "jalr" : "jalrs"); | |
e64af278 | 9265 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 9266 | || mips_opts.insn32 |
e64af278 | 9267 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
9268 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
9269 | else | |
9270 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
9271 | } | |
2906b037 MR |
9272 | else |
9273 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 9274 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 9275 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
9276 | } |
9277 | ||
252b5132 RH |
9278 | /* |
9279 | * Generate a "lui" instruction. | |
9280 | */ | |
9281 | static void | |
67c0d1eb | 9282 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 9283 | { |
9c2799c2 | 9284 | gas_assert (! mips_opts.mips16); |
252b5132 | 9285 | |
df58fc94 | 9286 | if (ep->X_op != O_constant) |
252b5132 | 9287 | { |
9c2799c2 | 9288 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
9289 | /* _gp_disp is a special case, used from s_cpload. |
9290 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 9291 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 9292 | || (! HAVE_NEWABI |
aa6975fb ILT |
9293 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
9294 | || (! mips_in_shared | |
bbe506e8 TS |
9295 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
9296 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
9297 | } |
9298 | ||
df58fc94 | 9299 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
9300 | } |
9301 | ||
885add95 CD |
9302 | /* Generate a sequence of instructions to do a load or store from a constant |
9303 | offset off of a base register (breg) into/from a target register (treg), | |
9304 | using AT if necessary. */ | |
9305 | static void | |
67c0d1eb RS |
9306 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
9307 | int treg, int breg, int dbl) | |
885add95 | 9308 | { |
9c2799c2 | 9309 | gas_assert (ep->X_op == O_constant); |
885add95 | 9310 | |
256ab948 | 9311 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
9312 | if (!dbl) |
9313 | normalize_constant_expr (ep); | |
256ab948 | 9314 | |
67c1ffbe | 9315 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 9316 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
9317 | as_warn (_("operand overflow")); |
9318 | ||
9319 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
9320 | { | |
9321 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 9322 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
9323 | } |
9324 | else | |
9325 | { | |
9326 | /* 32-bit offset, need multiple instructions and AT, like: | |
9327 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
9328 | addu $tempreg,$tempreg,$breg | |
9329 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
9330 | to handle the complete offset. */ | |
67c0d1eb RS |
9331 | macro_build_lui (ep, AT); |
9332 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
9333 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 9334 | |
741fe287 | 9335 | if (!mips_opts.at) |
1661c76c | 9336 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
9337 | } |
9338 | } | |
9339 | ||
252b5132 RH |
9340 | /* set_at() |
9341 | * Generates code to set the $at register to true (one) | |
9342 | * if reg is less than the immediate expression. | |
9343 | */ | |
9344 | static void | |
67c0d1eb | 9345 | set_at (int reg, int unsignedp) |
252b5132 | 9346 | { |
b0e6f033 | 9347 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 9348 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
9349 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
9350 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
9351 | else |
9352 | { | |
bad1aba3 | 9353 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 9354 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
9355 | } |
9356 | } | |
9357 | ||
252b5132 RH |
9358 | /* Count the leading zeroes by performing a binary chop. This is a |
9359 | bulky bit of source, but performance is a LOT better for the | |
9360 | majority of values than a simple loop to count the bits: | |
9361 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
9362 | if ((v) & (1 << (31 - lcnt))) | |
9363 | break; | |
9364 | However it is not code size friendly, and the gain will drop a bit | |
9365 | on certain cached systems. | |
9366 | */ | |
9367 | #define COUNT_TOP_ZEROES(v) \ | |
9368 | (((v) & ~0xffff) == 0 \ | |
9369 | ? ((v) & ~0xff) == 0 \ | |
9370 | ? ((v) & ~0xf) == 0 \ | |
9371 | ? ((v) & ~0x3) == 0 \ | |
9372 | ? ((v) & ~0x1) == 0 \ | |
9373 | ? !(v) \ | |
9374 | ? 32 \ | |
9375 | : 31 \ | |
9376 | : 30 \ | |
9377 | : ((v) & ~0x7) == 0 \ | |
9378 | ? 29 \ | |
9379 | : 28 \ | |
9380 | : ((v) & ~0x3f) == 0 \ | |
9381 | ? ((v) & ~0x1f) == 0 \ | |
9382 | ? 27 \ | |
9383 | : 26 \ | |
9384 | : ((v) & ~0x7f) == 0 \ | |
9385 | ? 25 \ | |
9386 | : 24 \ | |
9387 | : ((v) & ~0xfff) == 0 \ | |
9388 | ? ((v) & ~0x3ff) == 0 \ | |
9389 | ? ((v) & ~0x1ff) == 0 \ | |
9390 | ? 23 \ | |
9391 | : 22 \ | |
9392 | : ((v) & ~0x7ff) == 0 \ | |
9393 | ? 21 \ | |
9394 | : 20 \ | |
9395 | : ((v) & ~0x3fff) == 0 \ | |
9396 | ? ((v) & ~0x1fff) == 0 \ | |
9397 | ? 19 \ | |
9398 | : 18 \ | |
9399 | : ((v) & ~0x7fff) == 0 \ | |
9400 | ? 17 \ | |
9401 | : 16 \ | |
9402 | : ((v) & ~0xffffff) == 0 \ | |
9403 | ? ((v) & ~0xfffff) == 0 \ | |
9404 | ? ((v) & ~0x3ffff) == 0 \ | |
9405 | ? ((v) & ~0x1ffff) == 0 \ | |
9406 | ? 15 \ | |
9407 | : 14 \ | |
9408 | : ((v) & ~0x7ffff) == 0 \ | |
9409 | ? 13 \ | |
9410 | : 12 \ | |
9411 | : ((v) & ~0x3fffff) == 0 \ | |
9412 | ? ((v) & ~0x1fffff) == 0 \ | |
9413 | ? 11 \ | |
9414 | : 10 \ | |
9415 | : ((v) & ~0x7fffff) == 0 \ | |
9416 | ? 9 \ | |
9417 | : 8 \ | |
9418 | : ((v) & ~0xfffffff) == 0 \ | |
9419 | ? ((v) & ~0x3ffffff) == 0 \ | |
9420 | ? ((v) & ~0x1ffffff) == 0 \ | |
9421 | ? 7 \ | |
9422 | : 6 \ | |
9423 | : ((v) & ~0x7ffffff) == 0 \ | |
9424 | ? 5 \ | |
9425 | : 4 \ | |
9426 | : ((v) & ~0x3fffffff) == 0 \ | |
9427 | ? ((v) & ~0x1fffffff) == 0 \ | |
9428 | ? 3 \ | |
9429 | : 2 \ | |
9430 | : ((v) & ~0x7fffffff) == 0 \ | |
9431 | ? 1 \ | |
9432 | : 0) | |
9433 | ||
9434 | /* load_register() | |
67c1ffbe | 9435 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9436 | * an absolute expression value into a register. |
9437 | */ | |
9438 | static void | |
67c0d1eb | 9439 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9440 | { |
9441 | int freg; | |
9442 | expressionS hi32, lo32; | |
9443 | ||
9444 | if (ep->X_op != O_big) | |
9445 | { | |
9c2799c2 | 9446 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9447 | |
9448 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9449 | if (!dbl) |
9450 | normalize_constant_expr (ep); | |
256ab948 TS |
9451 | |
9452 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9453 | { |
9454 | /* We can handle 16 bit signed values with an addiu to | |
9455 | $zero. No need to ever use daddiu here, since $zero and | |
9456 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9457 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9458 | return; |
9459 | } | |
9460 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9461 | { | |
9462 | /* We can handle 16 bit unsigned values with an ori to | |
9463 | $zero. */ | |
67c0d1eb | 9464 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9465 | return; |
9466 | } | |
256ab948 | 9467 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9468 | { |
9469 | /* 32 bit values require an lui. */ | |
df58fc94 | 9470 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9471 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9472 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9473 | return; |
9474 | } | |
9475 | } | |
9476 | ||
9477 | /* The value is larger than 32 bits. */ | |
9478 | ||
bad1aba3 | 9479 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9480 | { |
55e08f71 NC |
9481 | char value[32]; |
9482 | ||
9483 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9484 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9485 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9486 | return; |
9487 | } | |
9488 | ||
9489 | if (ep->X_op != O_big) | |
9490 | { | |
9491 | hi32 = *ep; | |
9492 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9493 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9494 | hi32.X_add_number &= 0xffffffff; | |
9495 | lo32 = *ep; | |
9496 | lo32.X_add_number &= 0xffffffff; | |
9497 | } | |
9498 | else | |
9499 | { | |
9c2799c2 | 9500 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9501 | if (ep->X_add_number == 3) |
9502 | generic_bignum[3] = 0; | |
9503 | else if (ep->X_add_number > 4) | |
1661c76c | 9504 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9505 | lo32.X_op = O_constant; |
9506 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9507 | hi32.X_op = O_constant; | |
9508 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9509 | } | |
9510 | ||
9511 | if (hi32.X_add_number == 0) | |
9512 | freg = 0; | |
9513 | else | |
9514 | { | |
9515 | int shift, bit; | |
9516 | unsigned long hi, lo; | |
9517 | ||
956cd1d6 | 9518 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9519 | { |
9520 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9521 | { | |
67c0d1eb | 9522 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9523 | return; |
9524 | } | |
9525 | if (lo32.X_add_number & 0x80000000) | |
9526 | { | |
df58fc94 | 9527 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9528 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9529 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9530 | return; |
9531 | } | |
9532 | } | |
252b5132 RH |
9533 | |
9534 | /* Check for 16bit shifted constant. We know that hi32 is | |
9535 | non-zero, so start the mask on the first bit of the hi32 | |
9536 | value. */ | |
9537 | shift = 17; | |
9538 | do | |
beae10d5 KH |
9539 | { |
9540 | unsigned long himask, lomask; | |
9541 | ||
9542 | if (shift < 32) | |
9543 | { | |
9544 | himask = 0xffff >> (32 - shift); | |
9545 | lomask = (0xffff << shift) & 0xffffffff; | |
9546 | } | |
9547 | else | |
9548 | { | |
9549 | himask = 0xffff << (shift - 32); | |
9550 | lomask = 0; | |
9551 | } | |
9552 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9553 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9554 | { | |
9555 | expressionS tmp; | |
9556 | ||
9557 | tmp.X_op = O_constant; | |
9558 | if (shift < 32) | |
9559 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9560 | | (lo32.X_add_number >> shift)); | |
9561 | else | |
9562 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9563 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9564 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9565 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9566 | return; |
9567 | } | |
f9419b05 | 9568 | ++shift; |
beae10d5 KH |
9569 | } |
9570 | while (shift <= (64 - 16)); | |
252b5132 RH |
9571 | |
9572 | /* Find the bit number of the lowest one bit, and store the | |
9573 | shifted value in hi/lo. */ | |
9574 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9575 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9576 | if (lo != 0) | |
9577 | { | |
9578 | bit = 0; | |
9579 | while ((lo & 1) == 0) | |
9580 | { | |
9581 | lo >>= 1; | |
9582 | ++bit; | |
9583 | } | |
9584 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9585 | hi >>= bit; | |
9586 | } | |
9587 | else | |
9588 | { | |
9589 | bit = 32; | |
9590 | while ((hi & 1) == 0) | |
9591 | { | |
9592 | hi >>= 1; | |
9593 | ++bit; | |
9594 | } | |
9595 | lo = hi; | |
9596 | hi = 0; | |
9597 | } | |
9598 | ||
9599 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9600 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9601 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9602 | { |
9603 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9604 | if (shift != 0) |
beae10d5 | 9605 | { |
252b5132 RH |
9606 | expressionS tmp; |
9607 | ||
9608 | /* This instruction will set the register to be all | |
9609 | ones. */ | |
beae10d5 KH |
9610 | tmp.X_op = O_constant; |
9611 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9612 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9613 | if (bit != 0) |
9614 | { | |
9615 | bit += shift; | |
df58fc94 | 9616 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9617 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9618 | } |
df58fc94 | 9619 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9620 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9621 | return; |
9622 | } | |
9623 | } | |
252b5132 RH |
9624 | |
9625 | /* Sign extend hi32 before calling load_register, because we can | |
9626 | generally get better code when we load a sign extended value. */ | |
9627 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9628 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9629 | load_register (reg, &hi32, 0); |
252b5132 RH |
9630 | freg = reg; |
9631 | } | |
9632 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9633 | { | |
9634 | if (freg != 0) | |
9635 | { | |
df58fc94 | 9636 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9637 | freg = reg; |
9638 | } | |
9639 | } | |
9640 | else | |
9641 | { | |
9642 | expressionS mid16; | |
9643 | ||
956cd1d6 | 9644 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9645 | { |
df58fc94 RS |
9646 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9647 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9648 | return; |
9649 | } | |
252b5132 RH |
9650 | |
9651 | if (freg != 0) | |
9652 | { | |
df58fc94 | 9653 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9654 | freg = reg; |
9655 | } | |
9656 | mid16 = lo32; | |
9657 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9658 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9659 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9660 | freg = reg; |
9661 | } | |
9662 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9663 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9664 | } |
9665 | ||
269137b2 TS |
9666 | static inline void |
9667 | load_delay_nop (void) | |
9668 | { | |
9669 | if (!gpr_interlocks) | |
9670 | macro_build (NULL, "nop", ""); | |
9671 | } | |
9672 | ||
252b5132 RH |
9673 | /* Load an address into a register. */ |
9674 | ||
9675 | static void | |
67c0d1eb | 9676 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9677 | { |
252b5132 RH |
9678 | if (ep->X_op != O_constant |
9679 | && ep->X_op != O_symbol) | |
9680 | { | |
9681 | as_bad (_("expression too complex")); | |
9682 | ep->X_op = O_constant; | |
9683 | } | |
9684 | ||
9685 | if (ep->X_op == O_constant) | |
9686 | { | |
67c0d1eb | 9687 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9688 | return; |
9689 | } | |
9690 | ||
9691 | if (mips_pic == NO_PIC) | |
9692 | { | |
9693 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9694 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9695 | Otherwise we want |
9696 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9697 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9698 | If we have an addend, we always use the latter form. |
76b3015f | 9699 | |
d6bc6245 TS |
9700 | With 64bit address space and a usable $at we want |
9701 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9702 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9703 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9704 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9705 | dsll32 $reg,0 | |
3a482fd5 | 9706 | daddu $reg,$reg,$at |
76b3015f | 9707 | |
c03099e6 | 9708 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9709 | on superscalar processors. |
9710 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9711 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9712 | dsll $reg,16 | |
9713 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9714 | dsll $reg,16 | |
9715 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9716 | |
9717 | For GP relative symbols in 64bit address space we can use | |
9718 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9719 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9720 | { |
6caf9ef4 TS |
9721 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9722 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9723 | { | |
9724 | relax_start (ep->X_add_symbol); | |
9725 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9726 | mips_gp_register, BFD_RELOC_GPREL16); | |
9727 | relax_switch (); | |
9728 | } | |
d6bc6245 | 9729 | |
741fe287 | 9730 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9731 | { |
df58fc94 RS |
9732 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9733 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9734 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9735 | BFD_RELOC_MIPS_HIGHER); | |
9736 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9737 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9738 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9739 | *used_at = 1; |
9740 | } | |
9741 | else | |
9742 | { | |
df58fc94 | 9743 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9744 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9745 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9746 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9747 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9748 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9749 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9750 | } |
6caf9ef4 TS |
9751 | |
9752 | if (mips_relax.sequence) | |
9753 | relax_end (); | |
d6bc6245 | 9754 | } |
252b5132 RH |
9755 | else |
9756 | { | |
d6bc6245 | 9757 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9758 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9759 | { |
4d7206a2 | 9760 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9761 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9762 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9763 | relax_switch (); |
d6bc6245 | 9764 | } |
67c0d1eb RS |
9765 | macro_build_lui (ep, reg); |
9766 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9767 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9768 | if (mips_relax.sequence) |
9769 | relax_end (); | |
d6bc6245 | 9770 | } |
252b5132 | 9771 | } |
0a44bf69 | 9772 | else if (!mips_big_got) |
252b5132 RH |
9773 | { |
9774 | expressionS ex; | |
9775 | ||
9776 | /* If this is a reference to an external symbol, we want | |
9777 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9778 | Otherwise we want | |
9779 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9780 | nop | |
9781 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9782 | If there is a constant, it must be added in after. |
9783 | ||
ed6fb7bd | 9784 | If we have NewABI, we want |
f5040a92 AO |
9785 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9786 | unless we're referencing a global symbol with a non-zero | |
9787 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9788 | if (HAVE_NEWABI) |
9789 | { | |
f5040a92 AO |
9790 | if (ep->X_add_number) |
9791 | { | |
4d7206a2 | 9792 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9793 | ep->X_add_number = 0; |
4d7206a2 | 9794 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9795 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9796 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9797 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9798 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9799 | ex.X_op = O_constant; | |
67c0d1eb | 9800 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9801 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9802 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9803 | relax_switch (); |
f5040a92 | 9804 | } |
67c0d1eb | 9805 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9806 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9807 | if (mips_relax.sequence) |
9808 | relax_end (); | |
ed6fb7bd SC |
9809 | } |
9810 | else | |
9811 | { | |
f5040a92 AO |
9812 | ex.X_add_number = ep->X_add_number; |
9813 | ep->X_add_number = 0; | |
67c0d1eb RS |
9814 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9815 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9816 | load_delay_nop (); |
4d7206a2 RS |
9817 | relax_start (ep->X_add_symbol); |
9818 | relax_switch (); | |
67c0d1eb | 9819 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9820 | BFD_RELOC_LO16); |
4d7206a2 | 9821 | relax_end (); |
ed6fb7bd | 9822 | |
f5040a92 AO |
9823 | if (ex.X_add_number != 0) |
9824 | { | |
9825 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9826 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9827 | ex.X_op = O_constant; | |
67c0d1eb | 9828 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9829 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9830 | } |
252b5132 RH |
9831 | } |
9832 | } | |
0a44bf69 | 9833 | else if (mips_big_got) |
252b5132 RH |
9834 | { |
9835 | expressionS ex; | |
252b5132 RH |
9836 | |
9837 | /* This is the large GOT case. If this is a reference to an | |
9838 | external symbol, we want | |
9839 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9840 | addu $reg,$reg,$gp | |
9841 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9842 | |
9843 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9844 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9845 | nop | |
9846 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9847 | If there is a constant, it must be added in after. |
f5040a92 AO |
9848 | |
9849 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9850 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9851 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9852 | */ |
438c16b8 TS |
9853 | if (HAVE_NEWABI) |
9854 | { | |
4d7206a2 | 9855 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9856 | ep->X_add_number = 0; |
4d7206a2 | 9857 | relax_start (ep->X_add_symbol); |
df58fc94 | 9858 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9859 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9860 | reg, reg, mips_gp_register); | |
9861 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9862 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9863 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9864 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9865 | else if (ex.X_add_number) | |
9866 | { | |
9867 | ex.X_op = O_constant; | |
67c0d1eb RS |
9868 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9869 | BFD_RELOC_LO16); | |
f5040a92 AO |
9870 | } |
9871 | ||
9872 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9873 | relax_switch (); |
67c0d1eb | 9874 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9875 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9876 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9877 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9878 | relax_end (); |
438c16b8 | 9879 | } |
252b5132 | 9880 | else |
438c16b8 | 9881 | { |
f5040a92 AO |
9882 | ex.X_add_number = ep->X_add_number; |
9883 | ep->X_add_number = 0; | |
4d7206a2 | 9884 | relax_start (ep->X_add_symbol); |
df58fc94 | 9885 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9886 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9887 | reg, reg, mips_gp_register); | |
9888 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9889 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9890 | relax_switch (); |
9891 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9892 | { |
9893 | /* We need a nop before loading from $gp. This special | |
9894 | check is required because the lui which starts the main | |
9895 | instruction stream does not refer to $gp, and so will not | |
9896 | insert the nop which may be required. */ | |
67c0d1eb | 9897 | macro_build (NULL, "nop", ""); |
438c16b8 | 9898 | } |
67c0d1eb | 9899 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9900 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9901 | load_delay_nop (); |
67c0d1eb | 9902 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9903 | BFD_RELOC_LO16); |
4d7206a2 | 9904 | relax_end (); |
438c16b8 | 9905 | |
f5040a92 AO |
9906 | if (ex.X_add_number != 0) |
9907 | { | |
9908 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9909 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9910 | ex.X_op = O_constant; | |
67c0d1eb RS |
9911 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9912 | BFD_RELOC_LO16); | |
f5040a92 | 9913 | } |
252b5132 RH |
9914 | } |
9915 | } | |
252b5132 RH |
9916 | else |
9917 | abort (); | |
8fc2e39e | 9918 | |
741fe287 | 9919 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9920 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9921 | } |
9922 | ||
ea1fb5dc RS |
9923 | /* Move the contents of register SOURCE into register DEST. */ |
9924 | ||
9925 | static void | |
67c0d1eb | 9926 | move_register (int dest, int source) |
ea1fb5dc | 9927 | { |
df58fc94 RS |
9928 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9929 | instruction specifically requires a 32-bit one. */ | |
9930 | if (mips_opts.micromips | |
833794fc | 9931 | && !mips_opts.insn32 |
df58fc94 | 9932 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9933 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9934 | else |
40fc1451 | 9935 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9936 | } |
9937 | ||
4d7206a2 | 9938 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9939 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9940 | The two alternatives are: | |
4d7206a2 | 9941 | |
33eaf5de | 9942 | Global symbol Local symbol |
4d7206a2 RS |
9943 | ------------- ------------ |
9944 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9945 | ... ... | |
9946 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9947 | ||
9948 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9949 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9950 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9951 | |
9952 | static void | |
67c0d1eb | 9953 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9954 | { |
9955 | expressionS global; | |
9956 | ||
9957 | global = *local; | |
9958 | global.X_add_number = 0; | |
9959 | ||
9960 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9961 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9962 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9963 | relax_switch (); |
67c0d1eb RS |
9964 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9965 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9966 | relax_end (); |
9967 | } | |
9968 | ||
9969 | static void | |
67c0d1eb | 9970 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9971 | { |
9972 | expressionS global; | |
9973 | ||
9974 | global.X_op = O_constant; | |
9975 | global.X_op_symbol = NULL; | |
9976 | global.X_add_symbol = NULL; | |
9977 | global.X_add_number = local->X_add_number; | |
9978 | ||
9979 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9980 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9981 | dest, dest, BFD_RELOC_LO16); |
9982 | relax_switch (); | |
67c0d1eb | 9983 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9984 | relax_end (); |
9985 | } | |
9986 | ||
f6a22291 MR |
9987 | static void |
9988 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9989 | { | |
9990 | expressionS global; | |
9991 | int hold_mips_optimize; | |
9992 | ||
9993 | global.X_op = O_constant; | |
9994 | global.X_op_symbol = NULL; | |
9995 | global.X_add_symbol = NULL; | |
9996 | global.X_add_number = local->X_add_number; | |
9997 | ||
9998 | relax_start (local->X_add_symbol); | |
9999 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
10000 | relax_switch (); | |
10001 | /* Set mips_optimize around the lui instruction to avoid | |
10002 | inserting an unnecessary nop after the lw. */ | |
10003 | hold_mips_optimize = mips_optimize; | |
10004 | mips_optimize = 2; | |
10005 | macro_build_lui (&global, tmp); | |
10006 | mips_optimize = hold_mips_optimize; | |
10007 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
10008 | relax_end (); | |
10009 | ||
10010 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
10011 | } | |
10012 | ||
df58fc94 RS |
10013 | /* Emit a sequence of instructions to emulate a branch likely operation. |
10014 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
10015 | is its complementing branch with the original condition negated. | |
10016 | CALL is set if the original branch specified the link operation. | |
10017 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
10018 | ||
10019 | Code like this is produced in the noreorder mode: | |
10020 | ||
10021 | BRNEG <args>, 1f | |
10022 | nop | |
10023 | b <sym> | |
10024 | delay slot (executed only if branch taken) | |
10025 | 1: | |
10026 | ||
10027 | or, if CALL is set: | |
10028 | ||
10029 | BRNEG <args>, 1f | |
10030 | nop | |
10031 | bal <sym> | |
10032 | delay slot (executed only if branch taken) | |
10033 | 1: | |
10034 | ||
10035 | In the reorder mode the delay slot would be filled with a nop anyway, | |
10036 | so code produced is simply: | |
10037 | ||
10038 | BR <args>, <sym> | |
10039 | nop | |
10040 | ||
10041 | This function is used when producing code for the microMIPS ASE that | |
10042 | does not implement branch likely instructions in hardware. */ | |
10043 | ||
10044 | static void | |
10045 | macro_build_branch_likely (const char *br, const char *brneg, | |
10046 | int call, expressionS *ep, const char *fmt, | |
10047 | unsigned int sreg, unsigned int treg) | |
10048 | { | |
10049 | int noreorder = mips_opts.noreorder; | |
10050 | expressionS expr1; | |
10051 | ||
10052 | gas_assert (mips_opts.micromips); | |
10053 | start_noreorder (); | |
10054 | if (noreorder) | |
10055 | { | |
10056 | micromips_label_expr (&expr1); | |
10057 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
10058 | macro_build (NULL, "nop", ""); | |
10059 | macro_build (ep, call ? "bal" : "b", "p"); | |
10060 | ||
10061 | /* Set to true so that append_insn adds a label. */ | |
10062 | emit_branch_likely_macro = TRUE; | |
10063 | } | |
10064 | else | |
10065 | { | |
10066 | macro_build (ep, br, fmt, sreg, treg); | |
10067 | macro_build (NULL, "nop", ""); | |
10068 | } | |
10069 | end_noreorder (); | |
10070 | } | |
10071 | ||
10072 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
10073 | the condition code tested. EP specifies the branch target. */ | |
10074 | ||
10075 | static void | |
10076 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
10077 | { | |
10078 | const int call = 0; | |
10079 | const char *brneg; | |
10080 | const char *br; | |
10081 | ||
10082 | switch (type) | |
10083 | { | |
10084 | case M_BC1FL: | |
10085 | br = "bc1f"; | |
10086 | brneg = "bc1t"; | |
10087 | break; | |
10088 | case M_BC1TL: | |
10089 | br = "bc1t"; | |
10090 | brneg = "bc1f"; | |
10091 | break; | |
10092 | case M_BC2FL: | |
10093 | br = "bc2f"; | |
10094 | brneg = "bc2t"; | |
10095 | break; | |
10096 | case M_BC2TL: | |
10097 | br = "bc2t"; | |
10098 | brneg = "bc2f"; | |
10099 | break; | |
10100 | default: | |
10101 | abort (); | |
10102 | } | |
10103 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
10104 | } | |
10105 | ||
10106 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
10107 | the register tested. EP specifies the branch target. */ | |
10108 | ||
10109 | static void | |
10110 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
10111 | { | |
10112 | const char *brneg = NULL; | |
10113 | const char *br; | |
10114 | int call = 0; | |
10115 | ||
10116 | switch (type) | |
10117 | { | |
10118 | case M_BGEZ: | |
10119 | br = "bgez"; | |
10120 | break; | |
10121 | case M_BGEZL: | |
10122 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
10123 | brneg = "bltz"; | |
10124 | break; | |
10125 | case M_BGEZALL: | |
10126 | gas_assert (mips_opts.micromips); | |
833794fc | 10127 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
10128 | brneg = "bltz"; |
10129 | call = 1; | |
10130 | break; | |
10131 | case M_BGTZ: | |
10132 | br = "bgtz"; | |
10133 | break; | |
10134 | case M_BGTZL: | |
10135 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
10136 | brneg = "blez"; | |
10137 | break; | |
10138 | case M_BLEZ: | |
10139 | br = "blez"; | |
10140 | break; | |
10141 | case M_BLEZL: | |
10142 | br = mips_opts.micromips ? "blez" : "blezl"; | |
10143 | brneg = "bgtz"; | |
10144 | break; | |
10145 | case M_BLTZ: | |
10146 | br = "bltz"; | |
10147 | break; | |
10148 | case M_BLTZL: | |
10149 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
10150 | brneg = "bgez"; | |
10151 | break; | |
10152 | case M_BLTZALL: | |
10153 | gas_assert (mips_opts.micromips); | |
833794fc | 10154 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
10155 | brneg = "bgez"; |
10156 | call = 1; | |
10157 | break; | |
10158 | default: | |
10159 | abort (); | |
10160 | } | |
10161 | if (mips_opts.micromips && brneg) | |
10162 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
10163 | else | |
10164 | macro_build (ep, br, "s,p", sreg); | |
10165 | } | |
10166 | ||
10167 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
10168 | TREG as the registers tested. EP specifies the branch target. */ | |
10169 | ||
10170 | static void | |
10171 | macro_build_branch_rsrt (int type, expressionS *ep, | |
10172 | unsigned int sreg, unsigned int treg) | |
10173 | { | |
10174 | const char *brneg = NULL; | |
10175 | const int call = 0; | |
10176 | const char *br; | |
10177 | ||
10178 | switch (type) | |
10179 | { | |
10180 | case M_BEQ: | |
10181 | case M_BEQ_I: | |
10182 | br = "beq"; | |
10183 | break; | |
10184 | case M_BEQL: | |
10185 | case M_BEQL_I: | |
10186 | br = mips_opts.micromips ? "beq" : "beql"; | |
10187 | brneg = "bne"; | |
10188 | break; | |
10189 | case M_BNE: | |
10190 | case M_BNE_I: | |
10191 | br = "bne"; | |
10192 | break; | |
10193 | case M_BNEL: | |
10194 | case M_BNEL_I: | |
10195 | br = mips_opts.micromips ? "bne" : "bnel"; | |
10196 | brneg = "beq"; | |
10197 | break; | |
10198 | default: | |
10199 | abort (); | |
10200 | } | |
10201 | if (mips_opts.micromips && brneg) | |
10202 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
10203 | else | |
10204 | macro_build (ep, br, "s,t,p", sreg, treg); | |
10205 | } | |
10206 | ||
f2ae14a1 RS |
10207 | /* Return the high part that should be loaded in order to make the low |
10208 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
10209 | ||
10210 | static offsetT | |
10211 | offset_high_part (offsetT value, unsigned int offbits) | |
10212 | { | |
10213 | offsetT bias; | |
10214 | addressT low_mask; | |
10215 | ||
10216 | if (offbits == 0) | |
10217 | return value; | |
10218 | bias = 1 << (offbits - 1); | |
10219 | low_mask = bias * 2 - 1; | |
10220 | return (value + bias) & ~low_mask; | |
10221 | } | |
10222 | ||
10223 | /* Return true if the value stored in offset_expr and offset_reloc | |
10224 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
10225 | amount that the caller wants to add without inducing overflow | |
10226 | and ALIGN is the known alignment of the value in bytes. */ | |
10227 | ||
10228 | static bfd_boolean | |
10229 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
10230 | { | |
10231 | if (offbits == 16) | |
10232 | { | |
10233 | /* Accept any relocation operator if overflow isn't a concern. */ | |
10234 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
10235 | return TRUE; | |
10236 | ||
10237 | /* These relocations are guaranteed not to overflow in correct links. */ | |
10238 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
10239 | || gprel16_reloc_p (*offset_reloc)) | |
10240 | return TRUE; | |
10241 | } | |
10242 | if (offset_expr.X_op == O_constant | |
10243 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
10244 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
10245 | return TRUE; | |
10246 | return FALSE; | |
10247 | } | |
10248 | ||
252b5132 RH |
10249 | /* |
10250 | * Build macros | |
10251 | * This routine implements the seemingly endless macro or synthesized | |
10252 | * instructions and addressing modes in the mips assembly language. Many | |
10253 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 10254 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
10255 | * this verbose method. Others are not simple macros but are more like |
10256 | * optimizing code generation. | |
10257 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 10258 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 10259 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
10260 | * of global optimization. We currently only optimize within a single macro. |
10261 | * For many of the load and store macros if the address is specified as a | |
10262 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
10263 | * first load register 'at' with zero and use it as the base register. The | |
10264 | * mips assembler simply uses register $zero. Just one tiny optimization | |
10265 | * we're missing. | |
10266 | */ | |
10267 | static void | |
833794fc | 10268 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 10269 | { |
c0ebe874 RS |
10270 | const struct mips_operand_array *operands; |
10271 | unsigned int breg, i; | |
741fe287 | 10272 | unsigned int tempreg; |
252b5132 | 10273 | int mask; |
43841e91 | 10274 | int used_at = 0; |
df58fc94 | 10275 | expressionS label_expr; |
252b5132 | 10276 | expressionS expr1; |
df58fc94 | 10277 | expressionS *ep; |
252b5132 RH |
10278 | const char *s; |
10279 | const char *s2; | |
10280 | const char *fmt; | |
10281 | int likely = 0; | |
252b5132 | 10282 | int coproc = 0; |
7f3c4072 | 10283 | int offbits = 16; |
1abe91b1 | 10284 | int call = 0; |
df58fc94 RS |
10285 | int jals = 0; |
10286 | int dbl = 0; | |
10287 | int imm = 0; | |
10288 | int ust = 0; | |
10289 | int lp = 0; | |
a45328b9 | 10290 | int ll_sc_paired = 0; |
f2ae14a1 | 10291 | bfd_boolean large_offset; |
252b5132 | 10292 | int off; |
252b5132 | 10293 | int hold_mips_optimize; |
f2ae14a1 | 10294 | unsigned int align; |
c0ebe874 | 10295 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 10296 | |
9c2799c2 | 10297 | gas_assert (! mips_opts.mips16); |
252b5132 | 10298 | |
c0ebe874 RS |
10299 | operands = insn_operands (ip); |
10300 | for (i = 0; i < MAX_OPERANDS; i++) | |
10301 | if (operands->operand[i]) | |
10302 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
10303 | else | |
10304 | op[i] = -1; | |
10305 | ||
252b5132 RH |
10306 | mask = ip->insn_mo->mask; |
10307 | ||
df58fc94 RS |
10308 | label_expr.X_op = O_constant; |
10309 | label_expr.X_op_symbol = NULL; | |
10310 | label_expr.X_add_symbol = NULL; | |
10311 | label_expr.X_add_number = 0; | |
10312 | ||
252b5132 RH |
10313 | expr1.X_op = O_constant; |
10314 | expr1.X_op_symbol = NULL; | |
10315 | expr1.X_add_symbol = NULL; | |
10316 | expr1.X_add_number = 1; | |
f2ae14a1 | 10317 | align = 1; |
252b5132 RH |
10318 | |
10319 | switch (mask) | |
10320 | { | |
10321 | case M_DABS: | |
10322 | dbl = 1; | |
1a0670f3 | 10323 | /* Fall through. */ |
252b5132 | 10324 | case M_ABS: |
df58fc94 RS |
10325 | /* bgez $a0,1f |
10326 | move v0,$a0 | |
10327 | sub v0,$zero,$a0 | |
10328 | 1: | |
10329 | */ | |
252b5132 | 10330 | |
7d10b47d | 10331 | start_noreorder (); |
252b5132 | 10332 | |
df58fc94 RS |
10333 | if (mips_opts.micromips) |
10334 | micromips_label_expr (&label_expr); | |
10335 | else | |
10336 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10337 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
10338 | if (op[0] == op[1]) | |
a605d2b3 | 10339 | macro_build (NULL, "nop", ""); |
252b5132 | 10340 | else |
c0ebe874 RS |
10341 | move_register (op[0], op[1]); |
10342 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
10343 | if (mips_opts.micromips) |
10344 | micromips_add_label (); | |
252b5132 | 10345 | |
7d10b47d | 10346 | end_noreorder (); |
8fc2e39e | 10347 | break; |
252b5132 RH |
10348 | |
10349 | case M_ADD_I: | |
10350 | s = "addi"; | |
10351 | s2 = "add"; | |
387e7624 FS |
10352 | if (ISA_IS_R6 (mips_opts.isa)) |
10353 | goto do_addi_i; | |
10354 | else | |
10355 | goto do_addi; | |
252b5132 RH |
10356 | case M_ADDU_I: |
10357 | s = "addiu"; | |
10358 | s2 = "addu"; | |
10359 | goto do_addi; | |
10360 | case M_DADD_I: | |
10361 | dbl = 1; | |
10362 | s = "daddi"; | |
10363 | s2 = "dadd"; | |
387e7624 | 10364 | if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa)) |
df58fc94 | 10365 | goto do_addi; |
b0e6f033 | 10366 | if (imm_expr.X_add_number >= -0x200 |
387e7624 FS |
10367 | && imm_expr.X_add_number < 0x200 |
10368 | && !ISA_IS_R6 (mips_opts.isa)) | |
df58fc94 | 10369 | { |
b0e6f033 RS |
10370 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
10371 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
10372 | break; |
10373 | } | |
10374 | goto do_addi_i; | |
252b5132 RH |
10375 | case M_DADDU_I: |
10376 | dbl = 1; | |
10377 | s = "daddiu"; | |
10378 | s2 = "daddu"; | |
10379 | do_addi: | |
b0e6f033 | 10380 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
10381 | && imm_expr.X_add_number < 0x8000) |
10382 | { | |
c0ebe874 | 10383 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 10384 | break; |
252b5132 | 10385 | } |
df58fc94 | 10386 | do_addi_i: |
8fc2e39e | 10387 | used_at = 1; |
67c0d1eb | 10388 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10389 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10390 | break; |
10391 | ||
10392 | case M_AND_I: | |
10393 | s = "andi"; | |
10394 | s2 = "and"; | |
10395 | goto do_bit; | |
10396 | case M_OR_I: | |
10397 | s = "ori"; | |
10398 | s2 = "or"; | |
10399 | goto do_bit; | |
10400 | case M_NOR_I: | |
10401 | s = ""; | |
10402 | s2 = "nor"; | |
10403 | goto do_bit; | |
10404 | case M_XOR_I: | |
10405 | s = "xori"; | |
10406 | s2 = "xor"; | |
10407 | do_bit: | |
b0e6f033 | 10408 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10409 | && imm_expr.X_add_number < 0x10000) |
10410 | { | |
10411 | if (mask != M_NOR_I) | |
c0ebe874 | 10412 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10413 | else |
10414 | { | |
67c0d1eb | 10415 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10416 | op[0], op[1], BFD_RELOC_LO16); |
10417 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10418 | } |
8fc2e39e | 10419 | break; |
252b5132 RH |
10420 | } |
10421 | ||
8fc2e39e | 10422 | used_at = 1; |
bad1aba3 | 10423 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10424 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10425 | break; |
10426 | ||
8b082fb1 TS |
10427 | case M_BALIGN: |
10428 | switch (imm_expr.X_add_number) | |
10429 | { | |
10430 | case 0: | |
10431 | macro_build (NULL, "nop", ""); | |
10432 | break; | |
10433 | case 2: | |
c0ebe874 | 10434 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10435 | break; |
03f66e8a MR |
10436 | case 1: |
10437 | case 3: | |
c0ebe874 | 10438 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10439 | (int) imm_expr.X_add_number); |
8b082fb1 | 10440 | break; |
03f66e8a MR |
10441 | default: |
10442 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10443 | (unsigned long) imm_expr.X_add_number); | |
10444 | break; | |
8b082fb1 TS |
10445 | } |
10446 | break; | |
10447 | ||
df58fc94 RS |
10448 | case M_BC1FL: |
10449 | case M_BC1TL: | |
10450 | case M_BC2FL: | |
10451 | case M_BC2TL: | |
10452 | gas_assert (mips_opts.micromips); | |
10453 | macro_build_branch_ccl (mask, &offset_expr, | |
10454 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10455 | break; | |
10456 | ||
252b5132 | 10457 | case M_BEQ_I: |
252b5132 | 10458 | case M_BEQL_I: |
252b5132 | 10459 | case M_BNE_I: |
252b5132 | 10460 | case M_BNEL_I: |
b0e6f033 | 10461 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10462 | op[1] = 0; |
df58fc94 | 10463 | else |
252b5132 | 10464 | { |
c0ebe874 | 10465 | op[1] = AT; |
df58fc94 | 10466 | used_at = 1; |
bad1aba3 | 10467 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10468 | } |
df58fc94 RS |
10469 | /* Fall through. */ |
10470 | case M_BEQL: | |
10471 | case M_BNEL: | |
c0ebe874 | 10472 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10473 | break; |
10474 | ||
10475 | case M_BGEL: | |
10476 | likely = 1; | |
1a0670f3 | 10477 | /* Fall through. */ |
252b5132 | 10478 | case M_BGE: |
c0ebe874 RS |
10479 | if (op[1] == 0) |
10480 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10481 | else if (op[0] == 0) | |
10482 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10483 | else |
252b5132 | 10484 | { |
df58fc94 | 10485 | used_at = 1; |
c0ebe874 | 10486 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10487 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10488 | &offset_expr, AT, ZERO); | |
252b5132 | 10489 | } |
df58fc94 RS |
10490 | break; |
10491 | ||
10492 | case M_BGEZL: | |
10493 | case M_BGEZALL: | |
10494 | case M_BGTZL: | |
10495 | case M_BLEZL: | |
10496 | case M_BLTZL: | |
10497 | case M_BLTZALL: | |
c0ebe874 | 10498 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10499 | break; |
10500 | ||
10501 | case M_BGTL_I: | |
10502 | likely = 1; | |
1a0670f3 | 10503 | /* Fall through. */ |
252b5132 | 10504 | case M_BGT_I: |
90ecf173 | 10505 | /* Check for > max integer. */ |
b0e6f033 | 10506 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10507 | { |
10508 | do_false: | |
90ecf173 | 10509 | /* Result is always false. */ |
252b5132 | 10510 | if (! likely) |
a605d2b3 | 10511 | macro_build (NULL, "nop", ""); |
252b5132 | 10512 | else |
df58fc94 | 10513 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10514 | break; |
252b5132 | 10515 | } |
f9419b05 | 10516 | ++imm_expr.X_add_number; |
6f2117ba | 10517 | /* Fall through. */ |
252b5132 RH |
10518 | case M_BGE_I: |
10519 | case M_BGEL_I: | |
10520 | if (mask == M_BGEL_I) | |
10521 | likely = 1; | |
b0e6f033 | 10522 | if (imm_expr.X_add_number == 0) |
252b5132 | 10523 | { |
df58fc94 | 10524 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10525 | &offset_expr, op[0]); |
8fc2e39e | 10526 | break; |
252b5132 | 10527 | } |
b0e6f033 | 10528 | if (imm_expr.X_add_number == 1) |
252b5132 | 10529 | { |
df58fc94 | 10530 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10531 | &offset_expr, op[0]); |
8fc2e39e | 10532 | break; |
252b5132 | 10533 | } |
b0e6f033 | 10534 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10535 | { |
10536 | do_true: | |
6f2117ba | 10537 | /* Result is always true. */ |
1661c76c | 10538 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10539 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10540 | break; |
252b5132 | 10541 | } |
8fc2e39e | 10542 | used_at = 1; |
c0ebe874 | 10543 | set_at (op[0], 0); |
df58fc94 RS |
10544 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10545 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10546 | break; |
10547 | ||
10548 | case M_BGEUL: | |
10549 | likely = 1; | |
1a0670f3 | 10550 | /* Fall through. */ |
252b5132 | 10551 | case M_BGEU: |
c0ebe874 | 10552 | if (op[1] == 0) |
252b5132 | 10553 | goto do_true; |
c0ebe874 | 10554 | else if (op[0] == 0) |
df58fc94 | 10555 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10556 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10557 | else |
252b5132 | 10558 | { |
df58fc94 | 10559 | used_at = 1; |
c0ebe874 | 10560 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10561 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10562 | &offset_expr, AT, ZERO); | |
252b5132 | 10563 | } |
252b5132 RH |
10564 | break; |
10565 | ||
10566 | case M_BGTUL_I: | |
10567 | likely = 1; | |
1a0670f3 | 10568 | /* Fall through. */ |
252b5132 | 10569 | case M_BGTU_I: |
c0ebe874 | 10570 | if (op[0] == 0 |
bad1aba3 | 10571 | || (GPR_SIZE == 32 |
f01dc953 | 10572 | && imm_expr.X_add_number == -1)) |
252b5132 | 10573 | goto do_false; |
f9419b05 | 10574 | ++imm_expr.X_add_number; |
6f2117ba | 10575 | /* Fall through. */ |
252b5132 RH |
10576 | case M_BGEU_I: |
10577 | case M_BGEUL_I: | |
10578 | if (mask == M_BGEUL_I) | |
10579 | likely = 1; | |
b0e6f033 | 10580 | if (imm_expr.X_add_number == 0) |
252b5132 | 10581 | goto do_true; |
b0e6f033 | 10582 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10583 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10584 | &offset_expr, op[0], ZERO); |
df58fc94 | 10585 | else |
252b5132 | 10586 | { |
df58fc94 | 10587 | used_at = 1; |
c0ebe874 | 10588 | set_at (op[0], 1); |
df58fc94 RS |
10589 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10590 | &offset_expr, AT, ZERO); | |
252b5132 | 10591 | } |
252b5132 RH |
10592 | break; |
10593 | ||
10594 | case M_BGTL: | |
10595 | likely = 1; | |
1a0670f3 | 10596 | /* Fall through. */ |
252b5132 | 10597 | case M_BGT: |
c0ebe874 RS |
10598 | if (op[1] == 0) |
10599 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10600 | else if (op[0] == 0) | |
10601 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10602 | else |
252b5132 | 10603 | { |
df58fc94 | 10604 | used_at = 1; |
c0ebe874 | 10605 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10606 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10607 | &offset_expr, AT, ZERO); | |
252b5132 | 10608 | } |
252b5132 RH |
10609 | break; |
10610 | ||
10611 | case M_BGTUL: | |
10612 | likely = 1; | |
1a0670f3 | 10613 | /* Fall through. */ |
252b5132 | 10614 | case M_BGTU: |
c0ebe874 | 10615 | if (op[1] == 0) |
df58fc94 | 10616 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10617 | &offset_expr, op[0], ZERO); |
10618 | else if (op[0] == 0) | |
df58fc94 RS |
10619 | goto do_false; |
10620 | else | |
252b5132 | 10621 | { |
df58fc94 | 10622 | used_at = 1; |
c0ebe874 | 10623 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10624 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10625 | &offset_expr, AT, ZERO); | |
252b5132 | 10626 | } |
252b5132 RH |
10627 | break; |
10628 | ||
10629 | case M_BLEL: | |
10630 | likely = 1; | |
1a0670f3 | 10631 | /* Fall through. */ |
252b5132 | 10632 | case M_BLE: |
c0ebe874 RS |
10633 | if (op[1] == 0) |
10634 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10635 | else if (op[0] == 0) | |
10636 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10637 | else |
252b5132 | 10638 | { |
df58fc94 | 10639 | used_at = 1; |
c0ebe874 | 10640 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10641 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10642 | &offset_expr, AT, ZERO); | |
252b5132 | 10643 | } |
252b5132 RH |
10644 | break; |
10645 | ||
10646 | case M_BLEL_I: | |
10647 | likely = 1; | |
1a0670f3 | 10648 | /* Fall through. */ |
252b5132 | 10649 | case M_BLE_I: |
b0e6f033 | 10650 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10651 | goto do_true; |
f9419b05 | 10652 | ++imm_expr.X_add_number; |
6f2117ba | 10653 | /* Fall through. */ |
252b5132 RH |
10654 | case M_BLT_I: |
10655 | case M_BLTL_I: | |
10656 | if (mask == M_BLTL_I) | |
10657 | likely = 1; | |
b0e6f033 | 10658 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10659 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10660 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10661 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10662 | else |
252b5132 | 10663 | { |
df58fc94 | 10664 | used_at = 1; |
c0ebe874 | 10665 | set_at (op[0], 0); |
df58fc94 RS |
10666 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10667 | &offset_expr, AT, ZERO); | |
252b5132 | 10668 | } |
252b5132 RH |
10669 | break; |
10670 | ||
10671 | case M_BLEUL: | |
10672 | likely = 1; | |
1a0670f3 | 10673 | /* Fall through. */ |
252b5132 | 10674 | case M_BLEU: |
c0ebe874 | 10675 | if (op[1] == 0) |
df58fc94 | 10676 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10677 | &offset_expr, op[0], ZERO); |
10678 | else if (op[0] == 0) | |
df58fc94 RS |
10679 | goto do_true; |
10680 | else | |
252b5132 | 10681 | { |
df58fc94 | 10682 | used_at = 1; |
c0ebe874 | 10683 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10684 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10685 | &offset_expr, AT, ZERO); | |
252b5132 | 10686 | } |
252b5132 RH |
10687 | break; |
10688 | ||
10689 | case M_BLEUL_I: | |
10690 | likely = 1; | |
1a0670f3 | 10691 | /* Fall through. */ |
252b5132 | 10692 | case M_BLEU_I: |
c0ebe874 | 10693 | if (op[0] == 0 |
bad1aba3 | 10694 | || (GPR_SIZE == 32 |
f01dc953 | 10695 | && imm_expr.X_add_number == -1)) |
252b5132 | 10696 | goto do_true; |
f9419b05 | 10697 | ++imm_expr.X_add_number; |
6f2117ba | 10698 | /* Fall through. */ |
252b5132 RH |
10699 | case M_BLTU_I: |
10700 | case M_BLTUL_I: | |
10701 | if (mask == M_BLTUL_I) | |
10702 | likely = 1; | |
b0e6f033 | 10703 | if (imm_expr.X_add_number == 0) |
252b5132 | 10704 | goto do_false; |
b0e6f033 | 10705 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10706 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10707 | &offset_expr, op[0], ZERO); |
df58fc94 | 10708 | else |
252b5132 | 10709 | { |
df58fc94 | 10710 | used_at = 1; |
c0ebe874 | 10711 | set_at (op[0], 1); |
df58fc94 RS |
10712 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10713 | &offset_expr, AT, ZERO); | |
252b5132 | 10714 | } |
252b5132 RH |
10715 | break; |
10716 | ||
10717 | case M_BLTL: | |
10718 | likely = 1; | |
1a0670f3 | 10719 | /* Fall through. */ |
252b5132 | 10720 | case M_BLT: |
c0ebe874 RS |
10721 | if (op[1] == 0) |
10722 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10723 | else if (op[0] == 0) | |
10724 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10725 | else |
252b5132 | 10726 | { |
df58fc94 | 10727 | used_at = 1; |
c0ebe874 | 10728 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10729 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10730 | &offset_expr, AT, ZERO); | |
252b5132 | 10731 | } |
252b5132 RH |
10732 | break; |
10733 | ||
10734 | case M_BLTUL: | |
10735 | likely = 1; | |
1a0670f3 | 10736 | /* Fall through. */ |
252b5132 | 10737 | case M_BLTU: |
c0ebe874 | 10738 | if (op[1] == 0) |
252b5132 | 10739 | goto do_false; |
c0ebe874 | 10740 | else if (op[0] == 0) |
df58fc94 | 10741 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10742 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10743 | else |
252b5132 | 10744 | { |
df58fc94 | 10745 | used_at = 1; |
c0ebe874 | 10746 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10747 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10748 | &offset_expr, AT, ZERO); | |
252b5132 | 10749 | } |
252b5132 RH |
10750 | break; |
10751 | ||
10752 | case M_DDIV_3: | |
10753 | dbl = 1; | |
1a0670f3 | 10754 | /* Fall through. */ |
252b5132 RH |
10755 | case M_DIV_3: |
10756 | s = "mflo"; | |
10757 | goto do_div3; | |
10758 | case M_DREM_3: | |
10759 | dbl = 1; | |
1a0670f3 | 10760 | /* Fall through. */ |
252b5132 RH |
10761 | case M_REM_3: |
10762 | s = "mfhi"; | |
10763 | do_div3: | |
c0ebe874 | 10764 | if (op[2] == 0) |
252b5132 | 10765 | { |
1661c76c | 10766 | as_warn (_("divide by zero")); |
252b5132 | 10767 | if (mips_trap) |
df58fc94 | 10768 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10769 | else |
df58fc94 | 10770 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10771 | break; |
252b5132 RH |
10772 | } |
10773 | ||
7d10b47d | 10774 | start_noreorder (); |
252b5132 RH |
10775 | if (mips_trap) |
10776 | { | |
c0ebe874 RS |
10777 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10778 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10779 | } |
10780 | else | |
10781 | { | |
df58fc94 RS |
10782 | if (mips_opts.micromips) |
10783 | micromips_label_expr (&label_expr); | |
10784 | else | |
10785 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10786 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10787 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10788 | macro_build (NULL, "break", BRK_FMT, 7); |
10789 | if (mips_opts.micromips) | |
10790 | micromips_add_label (); | |
252b5132 RH |
10791 | } |
10792 | expr1.X_add_number = -1; | |
8fc2e39e | 10793 | used_at = 1; |
f6a22291 | 10794 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10795 | if (mips_opts.micromips) |
10796 | micromips_label_expr (&label_expr); | |
10797 | else | |
10798 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10799 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10800 | if (dbl) |
10801 | { | |
10802 | expr1.X_add_number = 1; | |
f6a22291 | 10803 | load_register (AT, &expr1, dbl); |
df58fc94 | 10804 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10805 | } |
10806 | else | |
10807 | { | |
10808 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10809 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10810 | } |
10811 | if (mips_trap) | |
10812 | { | |
c0ebe874 | 10813 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10814 | /* We want to close the noreorder block as soon as possible, so |
10815 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10816 | end_noreorder (); |
252b5132 RH |
10817 | } |
10818 | else | |
10819 | { | |
df58fc94 RS |
10820 | if (mips_opts.micromips) |
10821 | micromips_label_expr (&label_expr); | |
10822 | else | |
10823 | label_expr.X_add_number = 8; | |
c0ebe874 | 10824 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10825 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10826 | |
10827 | /* We want to close the noreorder block as soon as possible, so | |
10828 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10829 | end_noreorder (); |
252b5132 | 10830 | |
df58fc94 | 10831 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10832 | } |
df58fc94 RS |
10833 | if (mips_opts.micromips) |
10834 | micromips_add_label (); | |
c0ebe874 | 10835 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10836 | break; |
10837 | ||
10838 | case M_DIV_3I: | |
10839 | s = "div"; | |
10840 | s2 = "mflo"; | |
10841 | goto do_divi; | |
10842 | case M_DIVU_3I: | |
10843 | s = "divu"; | |
10844 | s2 = "mflo"; | |
10845 | goto do_divi; | |
10846 | case M_REM_3I: | |
10847 | s = "div"; | |
10848 | s2 = "mfhi"; | |
10849 | goto do_divi; | |
10850 | case M_REMU_3I: | |
10851 | s = "divu"; | |
10852 | s2 = "mfhi"; | |
10853 | goto do_divi; | |
10854 | case M_DDIV_3I: | |
10855 | dbl = 1; | |
10856 | s = "ddiv"; | |
10857 | s2 = "mflo"; | |
10858 | goto do_divi; | |
10859 | case M_DDIVU_3I: | |
10860 | dbl = 1; | |
10861 | s = "ddivu"; | |
10862 | s2 = "mflo"; | |
10863 | goto do_divi; | |
10864 | case M_DREM_3I: | |
10865 | dbl = 1; | |
10866 | s = "ddiv"; | |
10867 | s2 = "mfhi"; | |
10868 | goto do_divi; | |
10869 | case M_DREMU_3I: | |
10870 | dbl = 1; | |
10871 | s = "ddivu"; | |
10872 | s2 = "mfhi"; | |
10873 | do_divi: | |
b0e6f033 | 10874 | if (imm_expr.X_add_number == 0) |
252b5132 | 10875 | { |
1661c76c | 10876 | as_warn (_("divide by zero")); |
252b5132 | 10877 | if (mips_trap) |
df58fc94 | 10878 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10879 | else |
df58fc94 | 10880 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10881 | break; |
252b5132 | 10882 | } |
b0e6f033 | 10883 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10884 | { |
10885 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10886 | move_register (op[0], op[1]); |
252b5132 | 10887 | else |
c0ebe874 | 10888 | move_register (op[0], ZERO); |
8fc2e39e | 10889 | break; |
252b5132 | 10890 | } |
b0e6f033 | 10891 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10892 | { |
10893 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10894 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10895 | else |
c0ebe874 | 10896 | move_register (op[0], ZERO); |
8fc2e39e | 10897 | break; |
252b5132 RH |
10898 | } |
10899 | ||
8fc2e39e | 10900 | used_at = 1; |
67c0d1eb | 10901 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10902 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10903 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10904 | break; |
10905 | ||
10906 | case M_DIVU_3: | |
10907 | s = "divu"; | |
10908 | s2 = "mflo"; | |
10909 | goto do_divu3; | |
10910 | case M_REMU_3: | |
10911 | s = "divu"; | |
10912 | s2 = "mfhi"; | |
10913 | goto do_divu3; | |
10914 | case M_DDIVU_3: | |
10915 | s = "ddivu"; | |
10916 | s2 = "mflo"; | |
10917 | goto do_divu3; | |
10918 | case M_DREMU_3: | |
10919 | s = "ddivu"; | |
10920 | s2 = "mfhi"; | |
10921 | do_divu3: | |
7d10b47d | 10922 | start_noreorder (); |
252b5132 RH |
10923 | if (mips_trap) |
10924 | { | |
c0ebe874 RS |
10925 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10926 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10927 | /* We want to close the noreorder block as soon as possible, so |
10928 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10929 | end_noreorder (); |
252b5132 RH |
10930 | } |
10931 | else | |
10932 | { | |
df58fc94 RS |
10933 | if (mips_opts.micromips) |
10934 | micromips_label_expr (&label_expr); | |
10935 | else | |
10936 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10937 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10938 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10939 | |
10940 | /* We want to close the noreorder block as soon as possible, so | |
10941 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10942 | end_noreorder (); |
df58fc94 RS |
10943 | macro_build (NULL, "break", BRK_FMT, 7); |
10944 | if (mips_opts.micromips) | |
10945 | micromips_add_label (); | |
252b5132 | 10946 | } |
c0ebe874 | 10947 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10948 | break; |
252b5132 | 10949 | |
1abe91b1 MR |
10950 | case M_DLCA_AB: |
10951 | dbl = 1; | |
1a0670f3 | 10952 | /* Fall through. */ |
1abe91b1 MR |
10953 | case M_LCA_AB: |
10954 | call = 1; | |
10955 | goto do_la; | |
252b5132 RH |
10956 | case M_DLA_AB: |
10957 | dbl = 1; | |
1a0670f3 | 10958 | /* Fall through. */ |
252b5132 | 10959 | case M_LA_AB: |
1abe91b1 | 10960 | do_la: |
252b5132 RH |
10961 | /* Load the address of a symbol into a register. If breg is not |
10962 | zero, we then add a base register to it. */ | |
10963 | ||
c0ebe874 | 10964 | breg = op[2]; |
bad1aba3 | 10965 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10966 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10967 | "instead")); | |
3bec30a8 | 10968 | |
90ecf173 | 10969 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10970 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10971 | "instead")); | |
3bec30a8 | 10972 | |
f2ae14a1 | 10973 | if (small_offset_p (0, align, 16)) |
0c11417f | 10974 | { |
c0ebe874 | 10975 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10976 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10977 | break; |
0c11417f MR |
10978 | } |
10979 | ||
c0ebe874 | 10980 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10981 | { |
10982 | tempreg = AT; | |
10983 | used_at = 1; | |
10984 | } | |
10985 | else | |
c0ebe874 | 10986 | tempreg = op[0]; |
afdbd6d0 | 10987 | |
252b5132 RH |
10988 | if (offset_expr.X_op != O_symbol |
10989 | && offset_expr.X_op != O_constant) | |
10990 | { | |
1661c76c | 10991 | as_bad (_("expression too complex")); |
252b5132 RH |
10992 | offset_expr.X_op = O_constant; |
10993 | } | |
10994 | ||
252b5132 | 10995 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10996 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10997 | else if (mips_pic == NO_PIC) |
10998 | { | |
d6bc6245 | 10999 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 11000 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
11001 | Otherwise we want |
11002 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11003 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11004 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 11005 | so we may as well always use the latter form. |
76b3015f | 11006 | |
6caf9ef4 TS |
11007 | With 64bit address space and a usable $at we want |
11008 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11009 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11010 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11011 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
11012 | dsll32 $tempreg,0 | |
11013 | daddu $tempreg,$tempreg,$at | |
11014 | ||
11015 | If $at is already in use, we use a path which is suboptimal | |
11016 | on superscalar processors. | |
11017 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11018 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11019 | dsll $tempreg,16 | |
11020 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11021 | dsll $tempreg,16 | |
11022 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
11023 | ||
11024 | For GP relative symbols in 64bit address space we can use | |
11025 | the same sequence as in 32bit address space. */ | |
aed1a261 | 11026 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 11027 | { |
6caf9ef4 TS |
11028 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
11029 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
11030 | { | |
11031 | relax_start (offset_expr.X_add_symbol); | |
11032 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11033 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
11034 | relax_switch (); | |
11035 | } | |
d6bc6245 | 11036 | |
741fe287 | 11037 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 11038 | { |
df58fc94 | 11039 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11040 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 11041 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11042 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 11043 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11044 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 11045 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11046 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 11047 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 11048 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
11049 | used_at = 1; |
11050 | } | |
11051 | else | |
11052 | { | |
df58fc94 | 11053 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11054 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 11055 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11056 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 11057 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 11058 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11059 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 11060 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 11061 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11062 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 11063 | } |
6caf9ef4 TS |
11064 | |
11065 | if (mips_relax.sequence) | |
11066 | relax_end (); | |
98d3f06f KH |
11067 | } |
11068 | else | |
11069 | { | |
11070 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 11071 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 11072 | { |
4d7206a2 | 11073 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11074 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11075 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 11076 | relax_switch (); |
98d3f06f | 11077 | } |
6943caf0 | 11078 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 11079 | as_bad (_("offset too large")); |
67c0d1eb RS |
11080 | macro_build_lui (&offset_expr, tempreg); |
11081 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11082 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
11083 | if (mips_relax.sequence) |
11084 | relax_end (); | |
98d3f06f | 11085 | } |
252b5132 | 11086 | } |
0a44bf69 | 11087 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 11088 | { |
9117d219 NC |
11089 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
11090 | ||
252b5132 RH |
11091 | /* If this is a reference to an external symbol, and there |
11092 | is no constant, we want | |
11093 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 11094 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 11095 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
11096 | For a local symbol, we want |
11097 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11098 | nop | |
11099 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11100 | ||
11101 | If we have a small constant, and this is a reference to | |
11102 | an external symbol, we want | |
11103 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11104 | nop | |
11105 | addiu $tempreg,$tempreg,<constant> | |
11106 | For a local symbol, we want the same instruction | |
11107 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
11108 | addiu instruction. | |
11109 | ||
11110 | If we have a large constant, and this is a reference to | |
11111 | an external symbol, we want | |
11112 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11113 | lui $at,<hiconstant> | |
11114 | addiu $at,$at,<loconstant> | |
11115 | addu $tempreg,$tempreg,$at | |
11116 | For a local symbol, we want the same instruction | |
11117 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 11118 | addiu instruction. |
ed6fb7bd SC |
11119 | */ |
11120 | ||
4d7206a2 | 11121 | if (offset_expr.X_add_number == 0) |
252b5132 | 11122 | { |
0a44bf69 RS |
11123 | if (mips_pic == SVR4_PIC |
11124 | && breg == 0 | |
11125 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
11126 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
11127 | ||
11128 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
11129 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11130 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 11131 | if (breg != 0) |
252b5132 RH |
11132 | { |
11133 | /* We're going to put in an addu instruction using | |
11134 | tempreg, so we may as well insert the nop right | |
11135 | now. */ | |
269137b2 | 11136 | load_delay_nop (); |
252b5132 | 11137 | } |
4d7206a2 | 11138 | relax_switch (); |
67c0d1eb RS |
11139 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11140 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 11141 | load_delay_nop (); |
67c0d1eb RS |
11142 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11143 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 11144 | relax_end (); |
252b5132 RH |
11145 | /* FIXME: If breg == 0, and the next instruction uses |
11146 | $tempreg, then if this variant case is used an extra | |
11147 | nop will be generated. */ | |
11148 | } | |
4d7206a2 RS |
11149 | else if (offset_expr.X_add_number >= -0x8000 |
11150 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 11151 | { |
67c0d1eb | 11152 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 11153 | load_delay_nop (); |
67c0d1eb | 11154 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
11155 | } |
11156 | else | |
11157 | { | |
4d7206a2 RS |
11158 | expr1.X_add_number = offset_expr.X_add_number; |
11159 | offset_expr.X_add_number = | |
43c0598f | 11160 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 11161 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 11162 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
11163 | /* If we are going to add in a base register, and the |
11164 | target register and the base register are the same, | |
11165 | then we are using AT as a temporary register. Since | |
11166 | we want to load the constant into AT, we add our | |
11167 | current AT (from the global offset table) and the | |
11168 | register into the register now, and pretend we were | |
11169 | not using a base register. */ | |
c0ebe874 | 11170 | if (breg == op[0]) |
252b5132 | 11171 | { |
269137b2 | 11172 | load_delay_nop (); |
67c0d1eb | 11173 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11174 | op[0], AT, breg); |
252b5132 | 11175 | breg = 0; |
c0ebe874 | 11176 | tempreg = op[0]; |
252b5132 | 11177 | } |
f6a22291 | 11178 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
11179 | used_at = 1; |
11180 | } | |
11181 | } | |
0a44bf69 | 11182 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 11183 | { |
67c0d1eb | 11184 | int add_breg_early = 0; |
f5040a92 AO |
11185 | |
11186 | /* If this is a reference to an external, and there is no | |
11187 | constant, or local symbol (*), with or without a | |
11188 | constant, we want | |
11189 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 11190 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11191 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
11192 | ||
11193 | If we have a small constant, and this is a reference to | |
11194 | an external symbol, we want | |
11195 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11196 | addiu $tempreg,$tempreg,<constant> | |
11197 | ||
11198 | If we have a large constant, and this is a reference to | |
11199 | an external symbol, we want | |
11200 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11201 | lui $at,<hiconstant> | |
11202 | addiu $at,$at,<loconstant> | |
11203 | addu $tempreg,$tempreg,$at | |
11204 | ||
11205 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
11206 | local symbols, even though it introduces an additional | |
11207 | instruction. */ | |
11208 | ||
f5040a92 AO |
11209 | if (offset_expr.X_add_number) |
11210 | { | |
4d7206a2 | 11211 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11212 | offset_expr.X_add_number = 0; |
11213 | ||
4d7206a2 | 11214 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11215 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11216 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11217 | |
11218 | if (expr1.X_add_number >= -0x8000 | |
11219 | && expr1.X_add_number < 0x8000) | |
11220 | { | |
67c0d1eb RS |
11221 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
11222 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 11223 | } |
ecd13cd3 | 11224 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11225 | { |
c0ebe874 RS |
11226 | unsigned int dreg; |
11227 | ||
f5040a92 AO |
11228 | /* If we are going to add in a base register, and the |
11229 | target register and the base register are the same, | |
11230 | then we are using AT as a temporary register. Since | |
11231 | we want to load the constant into AT, we add our | |
11232 | current AT (from the global offset table) and the | |
11233 | register into the register now, and pretend we were | |
11234 | not using a base register. */ | |
c0ebe874 | 11235 | if (breg != op[0]) |
f5040a92 AO |
11236 | dreg = tempreg; |
11237 | else | |
11238 | { | |
9c2799c2 | 11239 | gas_assert (tempreg == AT); |
67c0d1eb | 11240 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11241 | op[0], AT, breg); |
11242 | dreg = op[0]; | |
67c0d1eb | 11243 | add_breg_early = 1; |
f5040a92 AO |
11244 | } |
11245 | ||
f6a22291 | 11246 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11247 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11248 | dreg, dreg, AT); |
f5040a92 | 11249 | |
f5040a92 AO |
11250 | used_at = 1; |
11251 | } | |
11252 | else | |
11253 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11254 | ||
4d7206a2 | 11255 | relax_switch (); |
f5040a92 AO |
11256 | offset_expr.X_add_number = expr1.X_add_number; |
11257 | ||
67c0d1eb RS |
11258 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11259 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
11260 | if (add_breg_early) | |
f5040a92 | 11261 | { |
67c0d1eb | 11262 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11263 | op[0], tempreg, breg); |
f5040a92 | 11264 | breg = 0; |
c0ebe874 | 11265 | tempreg = op[0]; |
f5040a92 | 11266 | } |
4d7206a2 | 11267 | relax_end (); |
f5040a92 | 11268 | } |
4d7206a2 | 11269 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 11270 | { |
4d7206a2 | 11271 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11272 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11273 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 11274 | relax_switch (); |
67c0d1eb RS |
11275 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11276 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 11277 | relax_end (); |
f5040a92 | 11278 | } |
4d7206a2 | 11279 | else |
f5040a92 | 11280 | { |
67c0d1eb RS |
11281 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11282 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11283 | } |
11284 | } | |
0a44bf69 | 11285 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11286 | { |
67c0d1eb | 11287 | int gpdelay; |
9117d219 NC |
11288 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11289 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 11290 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
11291 | |
11292 | /* This is the large GOT case. If this is a reference to an | |
11293 | external symbol, and there is no constant, we want | |
11294 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11295 | addu $tempreg,$tempreg,$gp | |
11296 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11297 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
11298 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11299 | addu $tempreg,$tempreg,$gp | |
11300 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
11301 | For a local symbol, we want |
11302 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11303 | nop | |
11304 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11305 | ||
11306 | If we have a small constant, and this is a reference to | |
11307 | an external symbol, we want | |
11308 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11309 | addu $tempreg,$tempreg,$gp | |
11310 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11311 | nop | |
11312 | addiu $tempreg,$tempreg,<constant> | |
11313 | For a local symbol, we want | |
11314 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11315 | nop | |
11316 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
11317 | ||
11318 | If we have a large constant, and this is a reference to | |
11319 | an external symbol, we want | |
11320 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11321 | addu $tempreg,$tempreg,$gp | |
11322 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11323 | lui $at,<hiconstant> | |
11324 | addiu $at,$at,<loconstant> | |
11325 | addu $tempreg,$tempreg,$at | |
11326 | For a local symbol, we want | |
11327 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11328 | lui $at,<hiconstant> | |
11329 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
11330 | addu $tempreg,$tempreg,$at | |
f5040a92 | 11331 | */ |
438c16b8 | 11332 | |
252b5132 RH |
11333 | expr1.X_add_number = offset_expr.X_add_number; |
11334 | offset_expr.X_add_number = 0; | |
4d7206a2 | 11335 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11336 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
11337 | if (expr1.X_add_number == 0 && breg == 0 |
11338 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
11339 | { |
11340 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11341 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11342 | } | |
df58fc94 | 11343 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11344 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11345 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 11346 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 11347 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
11348 | if (expr1.X_add_number == 0) |
11349 | { | |
67c0d1eb | 11350 | if (breg != 0) |
252b5132 RH |
11351 | { |
11352 | /* We're going to put in an addu instruction using | |
11353 | tempreg, so we may as well insert the nop right | |
11354 | now. */ | |
269137b2 | 11355 | load_delay_nop (); |
252b5132 | 11356 | } |
252b5132 RH |
11357 | } |
11358 | else if (expr1.X_add_number >= -0x8000 | |
11359 | && expr1.X_add_number < 0x8000) | |
11360 | { | |
269137b2 | 11361 | load_delay_nop (); |
67c0d1eb | 11362 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11363 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
11364 | } |
11365 | else | |
11366 | { | |
c0ebe874 RS |
11367 | unsigned int dreg; |
11368 | ||
252b5132 RH |
11369 | /* If we are going to add in a base register, and the |
11370 | target register and the base register are the same, | |
11371 | then we are using AT as a temporary register. Since | |
11372 | we want to load the constant into AT, we add our | |
11373 | current AT (from the global offset table) and the | |
11374 | register into the register now, and pretend we were | |
11375 | not using a base register. */ | |
c0ebe874 | 11376 | if (breg != op[0]) |
67c0d1eb | 11377 | dreg = tempreg; |
252b5132 RH |
11378 | else |
11379 | { | |
9c2799c2 | 11380 | gas_assert (tempreg == AT); |
269137b2 | 11381 | load_delay_nop (); |
67c0d1eb | 11382 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11383 | op[0], AT, breg); |
11384 | dreg = op[0]; | |
252b5132 RH |
11385 | } |
11386 | ||
f6a22291 | 11387 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11388 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11389 | |
252b5132 RH |
11390 | used_at = 1; |
11391 | } | |
43c0598f | 11392 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11393 | relax_switch (); |
252b5132 | 11394 | |
67c0d1eb | 11395 | if (gpdelay) |
252b5132 RH |
11396 | { |
11397 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11398 | the first instruction on the main stream does not. */ |
67c0d1eb | 11399 | macro_build (NULL, "nop", ""); |
252b5132 | 11400 | } |
ed6fb7bd | 11401 | |
67c0d1eb RS |
11402 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11403 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11404 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11405 | && expr1.X_add_number < 0x8000) |
11406 | { | |
269137b2 | 11407 | load_delay_nop (); |
67c0d1eb RS |
11408 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11409 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11410 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11411 | register, the external symbol case ended with a load, |
11412 | so if the symbol turns out to not be external, and | |
11413 | the next instruction uses tempreg, an unnecessary nop | |
11414 | will be inserted. */ | |
252b5132 RH |
11415 | } |
11416 | else | |
11417 | { | |
c0ebe874 | 11418 | if (breg == op[0]) |
252b5132 RH |
11419 | { |
11420 | /* We must add in the base register now, as in the | |
f5040a92 | 11421 | external symbol case. */ |
9c2799c2 | 11422 | gas_assert (tempreg == AT); |
269137b2 | 11423 | load_delay_nop (); |
67c0d1eb | 11424 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11425 | op[0], AT, breg); |
11426 | tempreg = op[0]; | |
252b5132 | 11427 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11428 | it in in both cases. */ |
252b5132 RH |
11429 | breg = 0; |
11430 | } | |
11431 | ||
67c0d1eb RS |
11432 | macro_build_lui (&expr1, AT); |
11433 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11434 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11435 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11436 | tempreg, tempreg, AT); |
8fc2e39e | 11437 | used_at = 1; |
252b5132 | 11438 | } |
4d7206a2 | 11439 | relax_end (); |
252b5132 | 11440 | } |
0a44bf69 | 11441 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11442 | { |
f5040a92 AO |
11443 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11444 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11445 | int add_breg_early = 0; |
f5040a92 AO |
11446 | |
11447 | /* This is the large GOT case. If this is a reference to an | |
11448 | external symbol, and there is no constant, we want | |
11449 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11450 | add $tempreg,$tempreg,$gp | |
11451 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11452 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11453 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11454 | add $tempreg,$tempreg,$gp | |
11455 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11456 | ||
11457 | If we have a small constant, and this is a reference to | |
11458 | an external symbol, we want | |
11459 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11460 | add $tempreg,$tempreg,$gp | |
11461 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11462 | addi $tempreg,$tempreg,<constant> | |
11463 | ||
11464 | If we have a large constant, and this is a reference to | |
11465 | an external symbol, we want | |
11466 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11467 | addu $tempreg,$tempreg,$gp | |
11468 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11469 | lui $at,<hiconstant> | |
11470 | addi $at,$at,<loconstant> | |
11471 | add $tempreg,$tempreg,$at | |
11472 | ||
11473 | If we have NewABI, and we know it's a local symbol, we want | |
11474 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11475 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11476 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11477 | ||
4d7206a2 | 11478 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11479 | |
4d7206a2 | 11480 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11481 | offset_expr.X_add_number = 0; |
11482 | ||
1abe91b1 MR |
11483 | if (expr1.X_add_number == 0 && breg == 0 |
11484 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11485 | { |
11486 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11487 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11488 | } | |
df58fc94 | 11489 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11490 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11491 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11492 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11493 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11494 | |
11495 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11496 | ; |
f5040a92 AO |
11497 | else if (expr1.X_add_number >= -0x8000 |
11498 | && expr1.X_add_number < 0x8000) | |
11499 | { | |
67c0d1eb | 11500 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11501 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11502 | } |
ecd13cd3 | 11503 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11504 | { |
c0ebe874 RS |
11505 | unsigned int dreg; |
11506 | ||
f5040a92 AO |
11507 | /* If we are going to add in a base register, and the |
11508 | target register and the base register are the same, | |
11509 | then we are using AT as a temporary register. Since | |
11510 | we want to load the constant into AT, we add our | |
11511 | current AT (from the global offset table) and the | |
11512 | register into the register now, and pretend we were | |
11513 | not using a base register. */ | |
c0ebe874 | 11514 | if (breg != op[0]) |
f5040a92 AO |
11515 | dreg = tempreg; |
11516 | else | |
11517 | { | |
9c2799c2 | 11518 | gas_assert (tempreg == AT); |
67c0d1eb | 11519 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11520 | op[0], AT, breg); |
11521 | dreg = op[0]; | |
67c0d1eb | 11522 | add_breg_early = 1; |
f5040a92 AO |
11523 | } |
11524 | ||
f6a22291 | 11525 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11526 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11527 | |
f5040a92 AO |
11528 | used_at = 1; |
11529 | } | |
11530 | else | |
11531 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11532 | ||
4d7206a2 | 11533 | relax_switch (); |
f5040a92 | 11534 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11535 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11536 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11537 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11538 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11539 | if (add_breg_early) | |
f5040a92 | 11540 | { |
67c0d1eb | 11541 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11542 | op[0], tempreg, breg); |
f5040a92 | 11543 | breg = 0; |
c0ebe874 | 11544 | tempreg = op[0]; |
f5040a92 | 11545 | } |
4d7206a2 | 11546 | relax_end (); |
f5040a92 | 11547 | } |
252b5132 RH |
11548 | else |
11549 | abort (); | |
11550 | ||
11551 | if (breg != 0) | |
c0ebe874 | 11552 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11553 | break; |
11554 | ||
52b6b6b9 | 11555 | case M_MSGSND: |
df58fc94 | 11556 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11557 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11558 | break; |
52b6b6b9 JM |
11559 | |
11560 | case M_MSGLD: | |
df58fc94 | 11561 | gas_assert (!mips_opts.micromips); |
c8276761 | 11562 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11563 | break; |
52b6b6b9 JM |
11564 | |
11565 | case M_MSGLD_T: | |
df58fc94 | 11566 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11567 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11568 | break; |
52b6b6b9 JM |
11569 | |
11570 | case M_MSGWAIT: | |
df58fc94 | 11571 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11572 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11573 | break; |
52b6b6b9 JM |
11574 | |
11575 | case M_MSGWAIT_T: | |
df58fc94 | 11576 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11577 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11578 | break; |
52b6b6b9 | 11579 | |
252b5132 RH |
11580 | case M_J_A: |
11581 | /* The j instruction may not be used in PIC code, since it | |
11582 | requires an absolute address. We convert it to a b | |
11583 | instruction. */ | |
11584 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11585 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11586 | else |
67c0d1eb | 11587 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11588 | break; |
252b5132 RH |
11589 | |
11590 | /* The jal instructions must be handled as macros because when | |
11591 | generating PIC code they expand to multi-instruction | |
11592 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11593 | case M_JALS_1: |
c0ebe874 RS |
11594 | op[1] = op[0]; |
11595 | op[0] = RA; | |
df58fc94 RS |
11596 | /* Fall through. */ |
11597 | case M_JALS_2: | |
11598 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11599 | if (mips_opts.insn32) |
11600 | { | |
1661c76c | 11601 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11602 | break; |
11603 | } | |
df58fc94 RS |
11604 | jals = 1; |
11605 | goto jal; | |
252b5132 | 11606 | case M_JAL_1: |
c0ebe874 RS |
11607 | op[1] = op[0]; |
11608 | op[0] = RA; | |
252b5132 RH |
11609 | /* Fall through. */ |
11610 | case M_JAL_2: | |
df58fc94 | 11611 | jal: |
3e722fb5 | 11612 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11613 | { |
11614 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11615 | if (mips_opts.micromips |
833794fc | 11616 | && !mips_opts.insn32 |
c0ebe874 | 11617 | && op[0] == RA |
e64af278 | 11618 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11619 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11620 | else |
c0ebe874 | 11621 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11622 | } |
0a44bf69 | 11623 | else |
252b5132 | 11624 | { |
df58fc94 RS |
11625 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11626 | && mips_cprestore_offset >= 0); | |
11627 | ||
c0ebe874 | 11628 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11629 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11630 | |
833794fc MR |
11631 | s = ((mips_opts.micromips |
11632 | && !mips_opts.insn32 | |
11633 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11634 | ? "jalrs" : "jalr"); |
e64af278 | 11635 | if (mips_opts.micromips |
833794fc | 11636 | && !mips_opts.insn32 |
c0ebe874 | 11637 | && op[0] == RA |
e64af278 | 11638 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11639 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11640 | else |
c0ebe874 | 11641 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11642 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11643 | { |
6478892d | 11644 | if (mips_cprestore_offset < 0) |
1661c76c | 11645 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11646 | else |
11647 | { | |
90ecf173 | 11648 | if (!mips_frame_reg_valid) |
7a621144 | 11649 | { |
1661c76c | 11650 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11651 | /* Quiet this warning. */ |
11652 | mips_frame_reg_valid = 1; | |
11653 | } | |
90ecf173 | 11654 | if (!mips_cprestore_valid) |
7a621144 | 11655 | { |
1661c76c | 11656 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11657 | /* Quiet this warning. */ |
11658 | mips_cprestore_valid = 1; | |
11659 | } | |
d3fca0b5 MR |
11660 | if (mips_opts.noreorder) |
11661 | macro_build (NULL, "nop", ""); | |
6478892d | 11662 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11663 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11664 | mips_gp_register, |
256ab948 TS |
11665 | mips_frame_reg, |
11666 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11667 | } |
252b5132 RH |
11668 | } |
11669 | } | |
252b5132 | 11670 | |
8fc2e39e | 11671 | break; |
252b5132 | 11672 | |
df58fc94 RS |
11673 | case M_JALS_A: |
11674 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11675 | if (mips_opts.insn32) |
11676 | { | |
1661c76c | 11677 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11678 | break; |
11679 | } | |
df58fc94 RS |
11680 | jals = 1; |
11681 | /* Fall through. */ | |
252b5132 RH |
11682 | case M_JAL_A: |
11683 | if (mips_pic == NO_PIC) | |
df58fc94 | 11684 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11685 | else if (mips_pic == SVR4_PIC) |
11686 | { | |
11687 | /* If this is a reference to an external symbol, and we are | |
11688 | using a small GOT, we want | |
11689 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11690 | nop | |
f9419b05 | 11691 | jalr $ra,$25 |
252b5132 RH |
11692 | nop |
11693 | lw $gp,cprestore($sp) | |
11694 | The cprestore value is set using the .cprestore | |
11695 | pseudo-op. If we are using a big GOT, we want | |
11696 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11697 | addu $25,$25,$gp | |
11698 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11699 | nop | |
f9419b05 | 11700 | jalr $ra,$25 |
252b5132 RH |
11701 | nop |
11702 | lw $gp,cprestore($sp) | |
11703 | If the symbol is not external, we want | |
11704 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11705 | nop | |
11706 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11707 | jalr $ra,$25 |
252b5132 | 11708 | nop |
438c16b8 | 11709 | lw $gp,cprestore($sp) |
f5040a92 AO |
11710 | |
11711 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11712 | sequences above, minus nops, unless the symbol is local, | |
11713 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11714 | GOT_DISP. */ | |
438c16b8 | 11715 | if (HAVE_NEWABI) |
252b5132 | 11716 | { |
90ecf173 | 11717 | if (!mips_big_got) |
f5040a92 | 11718 | { |
4d7206a2 | 11719 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11720 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11721 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11722 | mips_gp_register); |
4d7206a2 | 11723 | relax_switch (); |
67c0d1eb RS |
11724 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11725 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11726 | mips_gp_register); |
11727 | relax_end (); | |
f5040a92 AO |
11728 | } |
11729 | else | |
11730 | { | |
4d7206a2 | 11731 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11732 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11733 | BFD_RELOC_MIPS_CALL_HI16); |
11734 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11735 | PIC_CALL_REG, mips_gp_register); | |
11736 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11737 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11738 | PIC_CALL_REG); | |
4d7206a2 | 11739 | relax_switch (); |
67c0d1eb RS |
11740 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11741 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11742 | mips_gp_register); | |
11743 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11744 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11745 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11746 | relax_end (); |
f5040a92 | 11747 | } |
684022ea | 11748 | |
df58fc94 | 11749 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11750 | } |
11751 | else | |
11752 | { | |
4d7206a2 | 11753 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11754 | if (!mips_big_got) |
438c16b8 | 11755 | { |
67c0d1eb RS |
11756 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11757 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11758 | mips_gp_register); |
269137b2 | 11759 | load_delay_nop (); |
4d7206a2 | 11760 | relax_switch (); |
438c16b8 | 11761 | } |
252b5132 | 11762 | else |
252b5132 | 11763 | { |
67c0d1eb RS |
11764 | int gpdelay; |
11765 | ||
11766 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11767 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11768 | BFD_RELOC_MIPS_CALL_HI16); |
11769 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11770 | PIC_CALL_REG, mips_gp_register); | |
11771 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11772 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11773 | PIC_CALL_REG); | |
269137b2 | 11774 | load_delay_nop (); |
4d7206a2 | 11775 | relax_switch (); |
67c0d1eb RS |
11776 | if (gpdelay) |
11777 | macro_build (NULL, "nop", ""); | |
252b5132 | 11778 | } |
67c0d1eb RS |
11779 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11780 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11781 | mips_gp_register); |
269137b2 | 11782 | load_delay_nop (); |
67c0d1eb RS |
11783 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11784 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11785 | relax_end (); |
df58fc94 | 11786 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11787 | |
6478892d | 11788 | if (mips_cprestore_offset < 0) |
1661c76c | 11789 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11790 | else |
11791 | { | |
90ecf173 | 11792 | if (!mips_frame_reg_valid) |
7a621144 | 11793 | { |
1661c76c | 11794 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11795 | /* Quiet this warning. */ |
11796 | mips_frame_reg_valid = 1; | |
11797 | } | |
90ecf173 | 11798 | if (!mips_cprestore_valid) |
7a621144 | 11799 | { |
1661c76c | 11800 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11801 | /* Quiet this warning. */ |
11802 | mips_cprestore_valid = 1; | |
11803 | } | |
6478892d | 11804 | if (mips_opts.noreorder) |
67c0d1eb | 11805 | macro_build (NULL, "nop", ""); |
6478892d | 11806 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11807 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11808 | mips_gp_register, |
256ab948 TS |
11809 | mips_frame_reg, |
11810 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11811 | } |
252b5132 RH |
11812 | } |
11813 | } | |
0a44bf69 | 11814 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11815 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11816 | else |
11817 | abort (); | |
11818 | ||
8fc2e39e | 11819 | break; |
252b5132 | 11820 | |
7f3c4072 | 11821 | case M_LBUE_AB: |
7f3c4072 CM |
11822 | s = "lbue"; |
11823 | fmt = "t,+j(b)"; | |
11824 | offbits = 9; | |
11825 | goto ld_st; | |
11826 | case M_LHUE_AB: | |
7f3c4072 CM |
11827 | s = "lhue"; |
11828 | fmt = "t,+j(b)"; | |
11829 | offbits = 9; | |
11830 | goto ld_st; | |
11831 | case M_LBE_AB: | |
7f3c4072 CM |
11832 | s = "lbe"; |
11833 | fmt = "t,+j(b)"; | |
11834 | offbits = 9; | |
11835 | goto ld_st; | |
11836 | case M_LHE_AB: | |
7f3c4072 CM |
11837 | s = "lhe"; |
11838 | fmt = "t,+j(b)"; | |
11839 | offbits = 9; | |
11840 | goto ld_st; | |
11841 | case M_LLE_AB: | |
7f3c4072 CM |
11842 | s = "lle"; |
11843 | fmt = "t,+j(b)"; | |
11844 | offbits = 9; | |
11845 | goto ld_st; | |
11846 | case M_LWE_AB: | |
7f3c4072 CM |
11847 | s = "lwe"; |
11848 | fmt = "t,+j(b)"; | |
11849 | offbits = 9; | |
11850 | goto ld_st; | |
11851 | case M_LWLE_AB: | |
7f3c4072 CM |
11852 | s = "lwle"; |
11853 | fmt = "t,+j(b)"; | |
11854 | offbits = 9; | |
11855 | goto ld_st; | |
11856 | case M_LWRE_AB: | |
7f3c4072 CM |
11857 | s = "lwre"; |
11858 | fmt = "t,+j(b)"; | |
11859 | offbits = 9; | |
11860 | goto ld_st; | |
11861 | case M_SBE_AB: | |
7f3c4072 CM |
11862 | s = "sbe"; |
11863 | fmt = "t,+j(b)"; | |
11864 | offbits = 9; | |
11865 | goto ld_st; | |
11866 | case M_SCE_AB: | |
7f3c4072 CM |
11867 | s = "sce"; |
11868 | fmt = "t,+j(b)"; | |
11869 | offbits = 9; | |
11870 | goto ld_st; | |
11871 | case M_SHE_AB: | |
7f3c4072 CM |
11872 | s = "she"; |
11873 | fmt = "t,+j(b)"; | |
11874 | offbits = 9; | |
11875 | goto ld_st; | |
11876 | case M_SWE_AB: | |
7f3c4072 CM |
11877 | s = "swe"; |
11878 | fmt = "t,+j(b)"; | |
11879 | offbits = 9; | |
11880 | goto ld_st; | |
11881 | case M_SWLE_AB: | |
7f3c4072 CM |
11882 | s = "swle"; |
11883 | fmt = "t,+j(b)"; | |
11884 | offbits = 9; | |
11885 | goto ld_st; | |
11886 | case M_SWRE_AB: | |
7f3c4072 CM |
11887 | s = "swre"; |
11888 | fmt = "t,+j(b)"; | |
11889 | offbits = 9; | |
11890 | goto ld_st; | |
dec0624d | 11891 | case M_ACLR_AB: |
dec0624d | 11892 | s = "aclr"; |
dec0624d | 11893 | fmt = "\\,~(b)"; |
7f3c4072 | 11894 | offbits = 12; |
dec0624d MR |
11895 | goto ld_st; |
11896 | case M_ASET_AB: | |
dec0624d | 11897 | s = "aset"; |
dec0624d | 11898 | fmt = "\\,~(b)"; |
7f3c4072 | 11899 | offbits = 12; |
dec0624d | 11900 | goto ld_st; |
252b5132 RH |
11901 | case M_LB_AB: |
11902 | s = "lb"; | |
df58fc94 | 11903 | fmt = "t,o(b)"; |
252b5132 RH |
11904 | goto ld; |
11905 | case M_LBU_AB: | |
11906 | s = "lbu"; | |
df58fc94 | 11907 | fmt = "t,o(b)"; |
252b5132 RH |
11908 | goto ld; |
11909 | case M_LH_AB: | |
11910 | s = "lh"; | |
df58fc94 | 11911 | fmt = "t,o(b)"; |
252b5132 RH |
11912 | goto ld; |
11913 | case M_LHU_AB: | |
11914 | s = "lhu"; | |
df58fc94 | 11915 | fmt = "t,o(b)"; |
252b5132 RH |
11916 | goto ld; |
11917 | case M_LW_AB: | |
11918 | s = "lw"; | |
df58fc94 | 11919 | fmt = "t,o(b)"; |
252b5132 RH |
11920 | goto ld; |
11921 | case M_LWC0_AB: | |
df58fc94 | 11922 | gas_assert (!mips_opts.micromips); |
252b5132 | 11923 | s = "lwc0"; |
df58fc94 | 11924 | fmt = "E,o(b)"; |
bdaaa2e1 | 11925 | /* Itbl support may require additional care here. */ |
252b5132 | 11926 | coproc = 1; |
df58fc94 | 11927 | goto ld_st; |
252b5132 RH |
11928 | case M_LWC1_AB: |
11929 | s = "lwc1"; | |
df58fc94 | 11930 | fmt = "T,o(b)"; |
bdaaa2e1 | 11931 | /* Itbl support may require additional care here. */ |
252b5132 | 11932 | coproc = 1; |
df58fc94 | 11933 | goto ld_st; |
252b5132 RH |
11934 | case M_LWC2_AB: |
11935 | s = "lwc2"; | |
df58fc94 | 11936 | fmt = COP12_FMT; |
7361da2c AB |
11937 | offbits = (mips_opts.micromips ? 12 |
11938 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11939 | : 16); | |
bdaaa2e1 | 11940 | /* Itbl support may require additional care here. */ |
252b5132 | 11941 | coproc = 1; |
df58fc94 | 11942 | goto ld_st; |
252b5132 | 11943 | case M_LWC3_AB: |
df58fc94 | 11944 | gas_assert (!mips_opts.micromips); |
252b5132 | 11945 | s = "lwc3"; |
df58fc94 | 11946 | fmt = "E,o(b)"; |
bdaaa2e1 | 11947 | /* Itbl support may require additional care here. */ |
252b5132 | 11948 | coproc = 1; |
df58fc94 | 11949 | goto ld_st; |
252b5132 RH |
11950 | case M_LWL_AB: |
11951 | s = "lwl"; | |
df58fc94 | 11952 | fmt = MEM12_FMT; |
7f3c4072 | 11953 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11954 | goto ld_st; |
252b5132 RH |
11955 | case M_LWR_AB: |
11956 | s = "lwr"; | |
df58fc94 | 11957 | fmt = MEM12_FMT; |
7f3c4072 | 11958 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11959 | goto ld_st; |
252b5132 | 11960 | case M_LDC1_AB: |
252b5132 | 11961 | s = "ldc1"; |
df58fc94 | 11962 | fmt = "T,o(b)"; |
bdaaa2e1 | 11963 | /* Itbl support may require additional care here. */ |
252b5132 | 11964 | coproc = 1; |
df58fc94 | 11965 | goto ld_st; |
252b5132 RH |
11966 | case M_LDC2_AB: |
11967 | s = "ldc2"; | |
df58fc94 | 11968 | fmt = COP12_FMT; |
7361da2c AB |
11969 | offbits = (mips_opts.micromips ? 12 |
11970 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11971 | : 16); | |
bdaaa2e1 | 11972 | /* Itbl support may require additional care here. */ |
252b5132 | 11973 | coproc = 1; |
df58fc94 | 11974 | goto ld_st; |
c77c0862 | 11975 | case M_LQC2_AB: |
c77c0862 | 11976 | s = "lqc2"; |
14daeee3 | 11977 | fmt = "+7,o(b)"; |
c77c0862 RS |
11978 | /* Itbl support may require additional care here. */ |
11979 | coproc = 1; | |
11980 | goto ld_st; | |
252b5132 RH |
11981 | case M_LDC3_AB: |
11982 | s = "ldc3"; | |
df58fc94 | 11983 | fmt = "E,o(b)"; |
bdaaa2e1 | 11984 | /* Itbl support may require additional care here. */ |
252b5132 | 11985 | coproc = 1; |
df58fc94 | 11986 | goto ld_st; |
252b5132 RH |
11987 | case M_LDL_AB: |
11988 | s = "ldl"; | |
df58fc94 | 11989 | fmt = MEM12_FMT; |
7f3c4072 | 11990 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11991 | goto ld_st; |
252b5132 RH |
11992 | case M_LDR_AB: |
11993 | s = "ldr"; | |
df58fc94 | 11994 | fmt = MEM12_FMT; |
7f3c4072 | 11995 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11996 | goto ld_st; |
252b5132 RH |
11997 | case M_LL_AB: |
11998 | s = "ll"; | |
7361da2c AB |
11999 | fmt = LL_SC_FMT; |
12000 | offbits = (mips_opts.micromips ? 12 | |
12001 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12002 | : 16); | |
252b5132 RH |
12003 | goto ld; |
12004 | case M_LLD_AB: | |
12005 | s = "lld"; | |
7361da2c AB |
12006 | fmt = LL_SC_FMT; |
12007 | offbits = (mips_opts.micromips ? 12 | |
12008 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12009 | : 16); | |
252b5132 RH |
12010 | goto ld; |
12011 | case M_LWU_AB: | |
12012 | s = "lwu"; | |
df58fc94 | 12013 | fmt = MEM12_FMT; |
7f3c4072 | 12014 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12015 | goto ld; |
12016 | case M_LWP_AB: | |
df58fc94 RS |
12017 | gas_assert (mips_opts.micromips); |
12018 | s = "lwp"; | |
12019 | fmt = "t,~(b)"; | |
7f3c4072 | 12020 | offbits = 12; |
df58fc94 RS |
12021 | lp = 1; |
12022 | goto ld; | |
12023 | case M_LDP_AB: | |
df58fc94 RS |
12024 | gas_assert (mips_opts.micromips); |
12025 | s = "ldp"; | |
12026 | fmt = "t,~(b)"; | |
7f3c4072 | 12027 | offbits = 12; |
df58fc94 RS |
12028 | lp = 1; |
12029 | goto ld; | |
a45328b9 AB |
12030 | case M_LLDP_AB: |
12031 | case M_LLWP_AB: | |
41cee089 | 12032 | case M_LLWPE_AB: |
a45328b9 AB |
12033 | s = ip->insn_mo->name; |
12034 | fmt = "t,d,s"; | |
12035 | ll_sc_paired = 1; | |
12036 | offbits = 0; | |
12037 | goto ld; | |
df58fc94 | 12038 | case M_LWM_AB: |
df58fc94 RS |
12039 | gas_assert (mips_opts.micromips); |
12040 | s = "lwm"; | |
12041 | fmt = "n,~(b)"; | |
7f3c4072 | 12042 | offbits = 12; |
df58fc94 RS |
12043 | goto ld_st; |
12044 | case M_LDM_AB: | |
df58fc94 RS |
12045 | gas_assert (mips_opts.micromips); |
12046 | s = "ldm"; | |
12047 | fmt = "n,~(b)"; | |
7f3c4072 | 12048 | offbits = 12; |
df58fc94 RS |
12049 | goto ld_st; |
12050 | ||
252b5132 | 12051 | ld: |
a45328b9 AB |
12052 | /* Try to use one the the load registers to compute the base address. |
12053 | We don't want to use $0 as tempreg. */ | |
12054 | if (ll_sc_paired) | |
12055 | { | |
12056 | if ((op[0] == ZERO && op[3] == op[1]) | |
12057 | || (op[1] == ZERO && op[3] == op[0]) | |
12058 | || (op[0] == ZERO && op[1] == ZERO)) | |
12059 | goto ld_st; | |
12060 | else if (op[0] != op[3] && op[0] != ZERO) | |
12061 | tempreg = op[0]; | |
12062 | else | |
12063 | tempreg = op[1]; | |
12064 | } | |
252b5132 | 12065 | else |
a45328b9 AB |
12066 | { |
12067 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) | |
12068 | goto ld_st; | |
12069 | else | |
12070 | tempreg = op[0] + lp; | |
12071 | } | |
df58fc94 RS |
12072 | goto ld_noat; |
12073 | ||
252b5132 RH |
12074 | case M_SB_AB: |
12075 | s = "sb"; | |
df58fc94 RS |
12076 | fmt = "t,o(b)"; |
12077 | goto ld_st; | |
252b5132 RH |
12078 | case M_SH_AB: |
12079 | s = "sh"; | |
df58fc94 RS |
12080 | fmt = "t,o(b)"; |
12081 | goto ld_st; | |
252b5132 RH |
12082 | case M_SW_AB: |
12083 | s = "sw"; | |
df58fc94 RS |
12084 | fmt = "t,o(b)"; |
12085 | goto ld_st; | |
252b5132 | 12086 | case M_SWC0_AB: |
df58fc94 | 12087 | gas_assert (!mips_opts.micromips); |
252b5132 | 12088 | s = "swc0"; |
df58fc94 | 12089 | fmt = "E,o(b)"; |
bdaaa2e1 | 12090 | /* Itbl support may require additional care here. */ |
252b5132 | 12091 | coproc = 1; |
df58fc94 | 12092 | goto ld_st; |
252b5132 RH |
12093 | case M_SWC1_AB: |
12094 | s = "swc1"; | |
df58fc94 | 12095 | fmt = "T,o(b)"; |
bdaaa2e1 | 12096 | /* Itbl support may require additional care here. */ |
252b5132 | 12097 | coproc = 1; |
df58fc94 | 12098 | goto ld_st; |
252b5132 RH |
12099 | case M_SWC2_AB: |
12100 | s = "swc2"; | |
df58fc94 | 12101 | fmt = COP12_FMT; |
7361da2c AB |
12102 | offbits = (mips_opts.micromips ? 12 |
12103 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12104 | : 16); | |
bdaaa2e1 | 12105 | /* Itbl support may require additional care here. */ |
252b5132 | 12106 | coproc = 1; |
df58fc94 | 12107 | goto ld_st; |
252b5132 | 12108 | case M_SWC3_AB: |
df58fc94 | 12109 | gas_assert (!mips_opts.micromips); |
252b5132 | 12110 | s = "swc3"; |
df58fc94 | 12111 | fmt = "E,o(b)"; |
bdaaa2e1 | 12112 | /* Itbl support may require additional care here. */ |
252b5132 | 12113 | coproc = 1; |
df58fc94 | 12114 | goto ld_st; |
252b5132 RH |
12115 | case M_SWL_AB: |
12116 | s = "swl"; | |
df58fc94 | 12117 | fmt = MEM12_FMT; |
7f3c4072 | 12118 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12119 | goto ld_st; |
252b5132 RH |
12120 | case M_SWR_AB: |
12121 | s = "swr"; | |
df58fc94 | 12122 | fmt = MEM12_FMT; |
7f3c4072 | 12123 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12124 | goto ld_st; |
252b5132 RH |
12125 | case M_SC_AB: |
12126 | s = "sc"; | |
7361da2c AB |
12127 | fmt = LL_SC_FMT; |
12128 | offbits = (mips_opts.micromips ? 12 | |
12129 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12130 | : 16); | |
df58fc94 | 12131 | goto ld_st; |
252b5132 RH |
12132 | case M_SCD_AB: |
12133 | s = "scd"; | |
7361da2c AB |
12134 | fmt = LL_SC_FMT; |
12135 | offbits = (mips_opts.micromips ? 12 | |
12136 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12137 | : 16); | |
df58fc94 | 12138 | goto ld_st; |
a45328b9 AB |
12139 | case M_SCDP_AB: |
12140 | case M_SCWP_AB: | |
41cee089 | 12141 | case M_SCWPE_AB: |
a45328b9 AB |
12142 | s = ip->insn_mo->name; |
12143 | fmt = "t,d,s"; | |
12144 | ll_sc_paired = 1; | |
12145 | offbits = 0; | |
12146 | goto ld_st; | |
d43b4baf TS |
12147 | case M_CACHE_AB: |
12148 | s = "cache"; | |
7361da2c AB |
12149 | fmt = (mips_opts.micromips ? "k,~(b)" |
12150 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
12151 | : "k,o(b)"); | |
12152 | offbits = (mips_opts.micromips ? 12 | |
12153 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12154 | : 16); | |
7f3c4072 CM |
12155 | goto ld_st; |
12156 | case M_CACHEE_AB: | |
7f3c4072 CM |
12157 | s = "cachee"; |
12158 | fmt = "k,+j(b)"; | |
12159 | offbits = 9; | |
df58fc94 | 12160 | goto ld_st; |
3eebd5eb MR |
12161 | case M_PREF_AB: |
12162 | s = "pref"; | |
7361da2c AB |
12163 | fmt = (mips_opts.micromips ? "k,~(b)" |
12164 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
12165 | : "k,o(b)"); | |
12166 | offbits = (mips_opts.micromips ? 12 | |
12167 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12168 | : 16); | |
7f3c4072 CM |
12169 | goto ld_st; |
12170 | case M_PREFE_AB: | |
7f3c4072 CM |
12171 | s = "prefe"; |
12172 | fmt = "k,+j(b)"; | |
12173 | offbits = 9; | |
df58fc94 | 12174 | goto ld_st; |
252b5132 | 12175 | case M_SDC1_AB: |
252b5132 | 12176 | s = "sdc1"; |
df58fc94 | 12177 | fmt = "T,o(b)"; |
252b5132 | 12178 | coproc = 1; |
bdaaa2e1 | 12179 | /* Itbl support may require additional care here. */ |
df58fc94 | 12180 | goto ld_st; |
252b5132 RH |
12181 | case M_SDC2_AB: |
12182 | s = "sdc2"; | |
df58fc94 | 12183 | fmt = COP12_FMT; |
7361da2c AB |
12184 | offbits = (mips_opts.micromips ? 12 |
12185 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12186 | : 16); | |
c77c0862 RS |
12187 | /* Itbl support may require additional care here. */ |
12188 | coproc = 1; | |
12189 | goto ld_st; | |
12190 | case M_SQC2_AB: | |
c77c0862 | 12191 | s = "sqc2"; |
14daeee3 | 12192 | fmt = "+7,o(b)"; |
bdaaa2e1 | 12193 | /* Itbl support may require additional care here. */ |
252b5132 | 12194 | coproc = 1; |
df58fc94 | 12195 | goto ld_st; |
252b5132 | 12196 | case M_SDC3_AB: |
df58fc94 | 12197 | gas_assert (!mips_opts.micromips); |
252b5132 | 12198 | s = "sdc3"; |
df58fc94 | 12199 | fmt = "E,o(b)"; |
bdaaa2e1 | 12200 | /* Itbl support may require additional care here. */ |
252b5132 | 12201 | coproc = 1; |
df58fc94 | 12202 | goto ld_st; |
252b5132 RH |
12203 | case M_SDL_AB: |
12204 | s = "sdl"; | |
df58fc94 | 12205 | fmt = MEM12_FMT; |
7f3c4072 | 12206 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12207 | goto ld_st; |
252b5132 RH |
12208 | case M_SDR_AB: |
12209 | s = "sdr"; | |
df58fc94 | 12210 | fmt = MEM12_FMT; |
7f3c4072 | 12211 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12212 | goto ld_st; |
12213 | case M_SWP_AB: | |
df58fc94 RS |
12214 | gas_assert (mips_opts.micromips); |
12215 | s = "swp"; | |
12216 | fmt = "t,~(b)"; | |
7f3c4072 | 12217 | offbits = 12; |
df58fc94 RS |
12218 | goto ld_st; |
12219 | case M_SDP_AB: | |
df58fc94 RS |
12220 | gas_assert (mips_opts.micromips); |
12221 | s = "sdp"; | |
12222 | fmt = "t,~(b)"; | |
7f3c4072 | 12223 | offbits = 12; |
df58fc94 RS |
12224 | goto ld_st; |
12225 | case M_SWM_AB: | |
df58fc94 RS |
12226 | gas_assert (mips_opts.micromips); |
12227 | s = "swm"; | |
12228 | fmt = "n,~(b)"; | |
7f3c4072 | 12229 | offbits = 12; |
df58fc94 RS |
12230 | goto ld_st; |
12231 | case M_SDM_AB: | |
df58fc94 RS |
12232 | gas_assert (mips_opts.micromips); |
12233 | s = "sdm"; | |
12234 | fmt = "n,~(b)"; | |
7f3c4072 | 12235 | offbits = 12; |
df58fc94 RS |
12236 | |
12237 | ld_st: | |
8fc2e39e | 12238 | tempreg = AT; |
df58fc94 | 12239 | ld_noat: |
a45328b9 | 12240 | breg = ll_sc_paired ? op[3] : op[2]; |
f2ae14a1 RS |
12241 | if (small_offset_p (0, align, 16)) |
12242 | { | |
12243 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
12244 | macros for o32 but which should act like normal instructions | |
12245 | otherwise. */ | |
12246 | if (offbits == 16) | |
c0ebe874 | 12247 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12248 | offset_reloc[1], offset_reloc[2], breg); |
12249 | else if (small_offset_p (0, align, offbits)) | |
12250 | { | |
12251 | if (offbits == 0) | |
a45328b9 AB |
12252 | { |
12253 | if (ll_sc_paired) | |
12254 | macro_build (NULL, s, fmt, op[0], op[1], breg); | |
12255 | else | |
12256 | macro_build (NULL, s, fmt, op[0], breg); | |
12257 | } | |
f2ae14a1 | 12258 | else |
c0ebe874 | 12259 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12260 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
12261 | } |
12262 | else | |
12263 | { | |
12264 | if (tempreg == AT) | |
12265 | used_at = 1; | |
12266 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
12267 | tempreg, breg, -1, offset_reloc[0], | |
12268 | offset_reloc[1], offset_reloc[2]); | |
12269 | if (offbits == 0) | |
a45328b9 AB |
12270 | { |
12271 | if (ll_sc_paired) | |
12272 | macro_build (NULL, s, fmt, op[0], op[1], tempreg); | |
12273 | else | |
12274 | macro_build (NULL, s, fmt, op[0], tempreg); | |
12275 | } | |
f2ae14a1 | 12276 | else |
c0ebe874 | 12277 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
12278 | } |
12279 | break; | |
12280 | } | |
12281 | ||
12282 | if (tempreg == AT) | |
12283 | used_at = 1; | |
12284 | ||
252b5132 RH |
12285 | if (offset_expr.X_op != O_constant |
12286 | && offset_expr.X_op != O_symbol) | |
12287 | { | |
1661c76c | 12288 | as_bad (_("expression too complex")); |
252b5132 RH |
12289 | offset_expr.X_op = O_constant; |
12290 | } | |
12291 | ||
2051e8c4 MR |
12292 | if (HAVE_32BIT_ADDRESSES |
12293 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12294 | { |
12295 | char value [32]; | |
12296 | ||
12297 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12298 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12299 | } |
2051e8c4 | 12300 | |
252b5132 RH |
12301 | /* A constant expression in PIC code can be handled just as it |
12302 | is in non PIC code. */ | |
aed1a261 RS |
12303 | if (offset_expr.X_op == O_constant) |
12304 | { | |
f2ae14a1 RS |
12305 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
12306 | offbits == 0 ? 16 : offbits); | |
12307 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 12308 | |
f2ae14a1 RS |
12309 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
12310 | if (breg != 0) | |
12311 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12312 | tempreg, tempreg, breg); | |
7f3c4072 | 12313 | if (offbits == 0) |
dd6a37e7 | 12314 | { |
f2ae14a1 | 12315 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 12316 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 12317 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
a45328b9 AB |
12318 | if (ll_sc_paired) |
12319 | macro_build (NULL, s, fmt, op[0], op[1], tempreg); | |
12320 | else | |
12321 | macro_build (NULL, s, fmt, op[0], tempreg); | |
dd6a37e7 | 12322 | } |
7f3c4072 | 12323 | else if (offbits == 16) |
c0ebe874 | 12324 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 12325 | else |
c0ebe874 | 12326 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12327 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 12328 | } |
7f3c4072 | 12329 | else if (offbits != 16) |
df58fc94 | 12330 | { |
7f3c4072 | 12331 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 12332 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
12333 | register. */ |
12334 | load_address (tempreg, &offset_expr, &used_at); | |
12335 | if (breg != 0) | |
12336 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12337 | tempreg, tempreg, breg); | |
7f3c4072 | 12338 | if (offbits == 0) |
a45328b9 AB |
12339 | { |
12340 | if (ll_sc_paired) | |
12341 | macro_build (NULL, s, fmt, op[0], op[1], tempreg); | |
12342 | else | |
12343 | macro_build (NULL, s, fmt, op[0], tempreg); | |
12344 | } | |
dd6a37e7 | 12345 | else |
c0ebe874 | 12346 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
12347 | } |
12348 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
12349 | { |
12350 | /* If this is a reference to a GP relative symbol, and there | |
12351 | is no base register, we want | |
c0ebe874 | 12352 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
12353 | Otherwise, if there is no base register, we want |
12354 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 12355 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
12356 | If we have a constant, we need two instructions anyhow, |
12357 | so we always use the latter form. | |
12358 | ||
12359 | If we have a base register, and this is a reference to a | |
12360 | GP relative symbol, we want | |
12361 | addu $tempreg,$breg,$gp | |
c0ebe874 | 12362 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
12363 | Otherwise we want |
12364 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12365 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 12366 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 12367 | With a constant we always use the latter case. |
76b3015f | 12368 | |
d6bc6245 TS |
12369 | With 64bit address space and no base register and $at usable, |
12370 | we want | |
12371 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12372 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12373 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12374 | dsll32 $tempreg,0 | |
12375 | daddu $tempreg,$at | |
c0ebe874 | 12376 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12377 | If we have a base register, we want |
12378 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12379 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12380 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12381 | daddu $at,$breg | |
12382 | dsll32 $tempreg,0 | |
12383 | daddu $tempreg,$at | |
c0ebe874 | 12384 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12385 | |
12386 | Without $at we can't generate the optimal path for superscalar | |
12387 | processors here since this would require two temporary registers. | |
12388 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12389 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12390 | dsll $tempreg,16 | |
12391 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12392 | dsll $tempreg,16 | |
c0ebe874 | 12393 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12394 | If we have a base register, we want |
12395 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12396 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12397 | dsll $tempreg,16 | |
12398 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12399 | dsll $tempreg,16 | |
12400 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 12401 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 12402 | |
6caf9ef4 | 12403 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
12404 | the same sequence as in 32bit address space. */ |
12405 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 12406 | { |
aed1a261 | 12407 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
12408 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
12409 | { | |
12410 | relax_start (offset_expr.X_add_symbol); | |
12411 | if (breg == 0) | |
12412 | { | |
c0ebe874 | 12413 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12414 | BFD_RELOC_GPREL16, mips_gp_register); |
12415 | } | |
12416 | else | |
12417 | { | |
12418 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12419 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 12420 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12421 | BFD_RELOC_GPREL16, tempreg); |
12422 | } | |
12423 | relax_switch (); | |
12424 | } | |
d6bc6245 | 12425 | |
741fe287 | 12426 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 12427 | { |
df58fc94 | 12428 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 12429 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 12430 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
12431 | BFD_RELOC_HI16_S); |
12432 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12433 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 12434 | if (breg != 0) |
67c0d1eb | 12435 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12436 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12437 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12438 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12439 | tempreg); |
d6bc6245 TS |
12440 | used_at = 1; |
12441 | } | |
12442 | else | |
12443 | { | |
df58fc94 | 12444 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12445 | BFD_RELOC_MIPS_HIGHEST); |
12446 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12447 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12448 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12449 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12450 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12451 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12452 | if (breg != 0) |
67c0d1eb | 12453 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12454 | tempreg, tempreg, breg); |
c0ebe874 | 12455 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12456 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12457 | } |
6caf9ef4 TS |
12458 | |
12459 | if (mips_relax.sequence) | |
12460 | relax_end (); | |
8fc2e39e | 12461 | break; |
d6bc6245 | 12462 | } |
256ab948 | 12463 | |
252b5132 RH |
12464 | if (breg == 0) |
12465 | { | |
67c0d1eb | 12466 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12467 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12468 | { |
4d7206a2 | 12469 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12470 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12471 | mips_gp_register); |
4d7206a2 | 12472 | relax_switch (); |
252b5132 | 12473 | } |
67c0d1eb | 12474 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12475 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12476 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12477 | if (mips_relax.sequence) |
12478 | relax_end (); | |
252b5132 RH |
12479 | } |
12480 | else | |
12481 | { | |
67c0d1eb | 12482 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12483 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12484 | { |
4d7206a2 | 12485 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12486 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12487 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12488 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12489 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12490 | relax_switch (); |
252b5132 | 12491 | } |
67c0d1eb RS |
12492 | macro_build_lui (&offset_expr, tempreg); |
12493 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12494 | tempreg, tempreg, breg); |
c0ebe874 | 12495 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12496 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12497 | if (mips_relax.sequence) |
12498 | relax_end (); | |
252b5132 RH |
12499 | } |
12500 | } | |
0a44bf69 | 12501 | else if (!mips_big_got) |
252b5132 | 12502 | { |
ed6fb7bd | 12503 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12504 | |
252b5132 RH |
12505 | /* If this is a reference to an external symbol, we want |
12506 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12507 | nop | |
c0ebe874 | 12508 | <op> op[0],0($tempreg) |
252b5132 RH |
12509 | Otherwise we want |
12510 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12511 | nop | |
12512 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12513 | <op> op[0],0($tempreg) |
f5040a92 AO |
12514 | |
12515 | For NewABI, we want | |
12516 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12517 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12518 | |
252b5132 RH |
12519 | If there is a base register, we add it to $tempreg before |
12520 | the <op>. If there is a constant, we stick it in the | |
12521 | <op> instruction. We don't handle constants larger than | |
12522 | 16 bits, because we have no way to load the upper 16 bits | |
12523 | (actually, we could handle them for the subset of cases | |
12524 | in which we are not using $at). */ | |
9c2799c2 | 12525 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12526 | if (HAVE_NEWABI) |
12527 | { | |
67c0d1eb RS |
12528 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12529 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12530 | if (breg != 0) |
67c0d1eb | 12531 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12532 | tempreg, tempreg, breg); |
c0ebe874 | 12533 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12534 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12535 | break; |
12536 | } | |
252b5132 RH |
12537 | expr1.X_add_number = offset_expr.X_add_number; |
12538 | offset_expr.X_add_number = 0; | |
12539 | if (expr1.X_add_number < -0x8000 | |
12540 | || expr1.X_add_number >= 0x8000) | |
12541 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12542 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12543 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12544 | load_delay_nop (); |
4d7206a2 RS |
12545 | relax_start (offset_expr.X_add_symbol); |
12546 | relax_switch (); | |
67c0d1eb RS |
12547 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12548 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12549 | relax_end (); |
252b5132 | 12550 | if (breg != 0) |
67c0d1eb | 12551 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12552 | tempreg, tempreg, breg); |
c0ebe874 | 12553 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12554 | } |
0a44bf69 | 12555 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12556 | { |
67c0d1eb | 12557 | int gpdelay; |
252b5132 RH |
12558 | |
12559 | /* If this is a reference to an external symbol, we want | |
12560 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12561 | addu $tempreg,$tempreg,$gp | |
12562 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12563 | <op> op[0],0($tempreg) |
252b5132 RH |
12564 | Otherwise we want |
12565 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12566 | nop | |
12567 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12568 | <op> op[0],0($tempreg) |
252b5132 RH |
12569 | If there is a base register, we add it to $tempreg before |
12570 | the <op>. If there is a constant, we stick it in the | |
12571 | <op> instruction. We don't handle constants larger than | |
12572 | 16 bits, because we have no way to load the upper 16 bits | |
12573 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12574 | in which we are not using $at). */ |
9c2799c2 | 12575 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12576 | expr1.X_add_number = offset_expr.X_add_number; |
12577 | offset_expr.X_add_number = 0; | |
12578 | if (expr1.X_add_number < -0x8000 | |
12579 | || expr1.X_add_number >= 0x8000) | |
12580 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12581 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12582 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12583 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12584 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12585 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12586 | mips_gp_register); | |
12587 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12588 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12589 | relax_switch (); |
67c0d1eb RS |
12590 | if (gpdelay) |
12591 | macro_build (NULL, "nop", ""); | |
12592 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12593 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12594 | load_delay_nop (); |
67c0d1eb RS |
12595 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12596 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12597 | relax_end (); |
12598 | ||
252b5132 | 12599 | if (breg != 0) |
67c0d1eb | 12600 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12601 | tempreg, tempreg, breg); |
c0ebe874 | 12602 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12603 | } |
0a44bf69 | 12604 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12605 | { |
f5040a92 AO |
12606 | /* If this is a reference to an external symbol, we want |
12607 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12608 | add $tempreg,$tempreg,$gp | |
12609 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12610 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12611 | Otherwise, for local symbols, we want: |
12612 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12613 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12614 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12615 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12616 | offset_expr.X_add_number = 0; |
12617 | if (expr1.X_add_number < -0x8000 | |
12618 | || expr1.X_add_number >= 0x8000) | |
12619 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12620 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12621 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12622 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12623 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12624 | mips_gp_register); | |
12625 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12626 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12627 | if (breg != 0) |
67c0d1eb | 12628 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12629 | tempreg, tempreg, breg); |
c0ebe874 | 12630 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12631 | |
4d7206a2 | 12632 | relax_switch (); |
f5040a92 | 12633 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12634 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12635 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12636 | if (breg != 0) |
67c0d1eb | 12637 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12638 | tempreg, tempreg, breg); |
c0ebe874 | 12639 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12640 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12641 | relax_end (); |
f5040a92 | 12642 | } |
252b5132 RH |
12643 | else |
12644 | abort (); | |
12645 | ||
252b5132 RH |
12646 | break; |
12647 | ||
833794fc MR |
12648 | case M_JRADDIUSP: |
12649 | gas_assert (mips_opts.micromips); | |
12650 | gas_assert (mips_opts.insn32); | |
12651 | start_noreorder (); | |
12652 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12653 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12654 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12655 | end_noreorder (); | |
12656 | break; | |
12657 | ||
12658 | case M_JRC: | |
12659 | gas_assert (mips_opts.micromips); | |
12660 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12661 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12662 | if (mips_opts.noreorder) |
12663 | macro_build (NULL, "nop", ""); | |
12664 | break; | |
12665 | ||
252b5132 RH |
12666 | case M_LI: |
12667 | case M_LI_S: | |
c0ebe874 | 12668 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12669 | break; |
252b5132 RH |
12670 | |
12671 | case M_DLI: | |
c0ebe874 | 12672 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12673 | break; |
252b5132 RH |
12674 | |
12675 | case M_LI_SS: | |
12676 | if (imm_expr.X_op == O_constant) | |
12677 | { | |
8fc2e39e | 12678 | used_at = 1; |
67c0d1eb | 12679 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12680 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12681 | break; |
12682 | } | |
12683 | else | |
12684 | { | |
b0e6f033 RS |
12685 | gas_assert (imm_expr.X_op == O_absent |
12686 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12687 | && strcmp (segment_name (S_GET_SEGMENT |
12688 | (offset_expr.X_add_symbol)), | |
12689 | ".lit4") == 0 | |
12690 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12691 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12692 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12693 | break; |
252b5132 RH |
12694 | } |
12695 | ||
12696 | case M_LI_D: | |
ca4e0257 RS |
12697 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12698 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12699 | order 32 bits of the value and the low order 32 bits are either | |
12700 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12701 | if (imm_expr.X_op == O_constant) |
252b5132 | 12702 | { |
bad1aba3 | 12703 | if (GPR_SIZE == 64) |
c0ebe874 | 12704 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12705 | else |
12706 | { | |
12707 | int hreg, lreg; | |
12708 | ||
12709 | if (target_big_endian) | |
12710 | { | |
c0ebe874 RS |
12711 | hreg = op[0]; |
12712 | lreg = op[0] + 1; | |
252b5132 RH |
12713 | } |
12714 | else | |
12715 | { | |
c0ebe874 RS |
12716 | hreg = op[0] + 1; |
12717 | lreg = op[0]; | |
252b5132 RH |
12718 | } |
12719 | ||
12720 | if (hreg <= 31) | |
67c0d1eb | 12721 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12722 | if (lreg <= 31) |
12723 | { | |
12724 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12725 | move_register (lreg, 0); |
252b5132 RH |
12726 | else |
12727 | { | |
9c2799c2 | 12728 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12729 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12730 | } |
12731 | } | |
12732 | } | |
8fc2e39e | 12733 | break; |
252b5132 | 12734 | } |
b0e6f033 | 12735 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12736 | |
12737 | /* We know that sym is in the .rdata section. First we get the | |
12738 | upper 16 bits of the address. */ | |
12739 | if (mips_pic == NO_PIC) | |
12740 | { | |
67c0d1eb | 12741 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12742 | used_at = 1; |
252b5132 | 12743 | } |
0a44bf69 | 12744 | else |
252b5132 | 12745 | { |
67c0d1eb RS |
12746 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12747 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12748 | used_at = 1; |
252b5132 | 12749 | } |
bdaaa2e1 | 12750 | |
252b5132 | 12751 | /* Now we load the register(s). */ |
bad1aba3 | 12752 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12753 | { |
12754 | used_at = 1; | |
c0ebe874 RS |
12755 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12756 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12757 | } |
252b5132 RH |
12758 | else |
12759 | { | |
8fc2e39e | 12760 | used_at = 1; |
c0ebe874 RS |
12761 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12762 | BFD_RELOC_LO16, AT); | |
12763 | if (op[0] != RA) | |
252b5132 RH |
12764 | { |
12765 | /* FIXME: How in the world do we deal with the possible | |
12766 | overflow here? */ | |
12767 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12768 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12769 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12770 | } |
12771 | } | |
252b5132 RH |
12772 | break; |
12773 | ||
12774 | case M_LI_DD: | |
ca4e0257 RS |
12775 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12776 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12777 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12778 | the value and the low order 32 bits are either zero or in | |
12779 | OFFSET_EXPR. */ | |
b0e6f033 | 12780 | if (imm_expr.X_op == O_constant) |
252b5132 | 12781 | { |
9b444f95 FS |
12782 | tempreg = ZERO; |
12783 | if (((FPR_SIZE == 64 && GPR_SIZE == 64) | |
12784 | || !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12785 | && imm_expr.X_add_number != 0) | |
12786 | { | |
12787 | used_at = 1; | |
12788 | tempreg = AT; | |
12789 | load_register (AT, &imm_expr, FPR_SIZE == 64); | |
12790 | } | |
351cdf24 | 12791 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
9b444f95 | 12792 | macro_build (NULL, "dmtc1", "t,S", tempreg, op[0]); |
252b5132 RH |
12793 | else |
12794 | { | |
9b444f95 FS |
12795 | if (!ISA_HAS_MXHC1 (mips_opts.isa)) |
12796 | { | |
12797 | if (FPR_SIZE != 32) | |
12798 | as_bad (_("Unable to generate `%s' compliant code " | |
12799 | "without mthc1"), | |
12800 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12801 | else | |
12802 | macro_build (NULL, "mtc1", "t,G", tempreg, op[0] + 1); | |
12803 | } | |
252b5132 | 12804 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12805 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12806 | else |
12807 | { | |
9c2799c2 | 12808 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12809 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12810 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 | 12811 | } |
9b444f95 FS |
12812 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12813 | { | |
12814 | if (imm_expr.X_add_number != 0) | |
12815 | { | |
12816 | used_at = 1; | |
12817 | tempreg = AT; | |
12818 | load_register (AT, &imm_expr, 0); | |
12819 | } | |
12820 | macro_build (NULL, "mthc1", "t,G", tempreg, op[0]); | |
12821 | } | |
252b5132 RH |
12822 | } |
12823 | break; | |
12824 | } | |
12825 | ||
b0e6f033 RS |
12826 | gas_assert (imm_expr.X_op == O_absent |
12827 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12828 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12829 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12830 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12831 | { |
12832 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12833 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12834 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12835 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12836 | } |
12837 | else | |
12838 | { | |
9c2799c2 | 12839 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12840 | used_at = 1; |
0a44bf69 | 12841 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12842 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12843 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12844 | else |
12845 | { | |
12846 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12847 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12848 | } |
bdaaa2e1 | 12849 | |
c0ebe874 | 12850 | op[2] = AT; |
f2ae14a1 RS |
12851 | offset_reloc[0] = BFD_RELOC_LO16; |
12852 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12853 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12854 | } |
f2ae14a1 | 12855 | align = 8; |
6f2117ba | 12856 | /* Fall through. */ |
c4a68bea | 12857 | |
252b5132 | 12858 | case M_L_DAB: |
6f2117ba PH |
12859 | /* The MIPS assembler seems to check for X_add_number not |
12860 | being double aligned and generating: | |
12861 | lui at,%hi(foo+1) | |
12862 | addu at,at,v1 | |
12863 | addiu at,at,%lo(foo+1) | |
12864 | lwc1 f2,0(at) | |
12865 | lwc1 f3,4(at) | |
12866 | But, the resulting address is the same after relocation so why | |
12867 | generate the extra instruction? */ | |
bdaaa2e1 | 12868 | /* Itbl support may require additional care here. */ |
252b5132 | 12869 | coproc = 1; |
df58fc94 | 12870 | fmt = "T,o(b)"; |
0aa27725 | 12871 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12872 | { |
12873 | s = "ldc1"; | |
df58fc94 | 12874 | goto ld_st; |
252b5132 | 12875 | } |
252b5132 | 12876 | s = "lwc1"; |
252b5132 RH |
12877 | goto ldd_std; |
12878 | ||
12879 | case M_S_DAB: | |
df58fc94 RS |
12880 | gas_assert (!mips_opts.micromips); |
12881 | /* Itbl support may require additional care here. */ | |
12882 | coproc = 1; | |
12883 | fmt = "T,o(b)"; | |
0aa27725 | 12884 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12885 | { |
12886 | s = "sdc1"; | |
df58fc94 | 12887 | goto ld_st; |
252b5132 | 12888 | } |
252b5132 | 12889 | s = "swc1"; |
252b5132 RH |
12890 | goto ldd_std; |
12891 | ||
e407c74b NC |
12892 | case M_LQ_AB: |
12893 | fmt = "t,o(b)"; | |
12894 | s = "lq"; | |
12895 | goto ld; | |
12896 | ||
12897 | case M_SQ_AB: | |
12898 | fmt = "t,o(b)"; | |
12899 | s = "sq"; | |
12900 | goto ld_st; | |
12901 | ||
252b5132 | 12902 | case M_LD_AB: |
df58fc94 | 12903 | fmt = "t,o(b)"; |
bad1aba3 | 12904 | if (GPR_SIZE == 64) |
252b5132 RH |
12905 | { |
12906 | s = "ld"; | |
12907 | goto ld; | |
12908 | } | |
252b5132 | 12909 | s = "lw"; |
252b5132 RH |
12910 | goto ldd_std; |
12911 | ||
12912 | case M_SD_AB: | |
df58fc94 | 12913 | fmt = "t,o(b)"; |
bad1aba3 | 12914 | if (GPR_SIZE == 64) |
252b5132 RH |
12915 | { |
12916 | s = "sd"; | |
df58fc94 | 12917 | goto ld_st; |
252b5132 | 12918 | } |
252b5132 | 12919 | s = "sw"; |
252b5132 RH |
12920 | |
12921 | ldd_std: | |
f2ae14a1 RS |
12922 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12923 | to adjust when loading from memory. We set coproc if we must | |
12924 | load $fn+1 first. */ | |
12925 | /* Itbl support may require additional care here. */ | |
12926 | if (!target_big_endian) | |
12927 | coproc = 0; | |
12928 | ||
c0ebe874 | 12929 | breg = op[2]; |
f2ae14a1 RS |
12930 | if (small_offset_p (0, align, 16)) |
12931 | { | |
12932 | ep = &offset_expr; | |
12933 | if (!small_offset_p (4, align, 16)) | |
12934 | { | |
12935 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12936 | -1, offset_reloc[0], offset_reloc[1], | |
12937 | offset_reloc[2]); | |
12938 | expr1.X_add_number = 0; | |
12939 | ep = &expr1; | |
12940 | breg = AT; | |
12941 | used_at = 1; | |
12942 | offset_reloc[0] = BFD_RELOC_LO16; | |
12943 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12944 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12945 | } | |
c0ebe874 | 12946 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12947 | { |
12948 | ep->X_add_number += 4; | |
c0ebe874 | 12949 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12950 | offset_reloc[1], offset_reloc[2], breg); |
12951 | ep->X_add_number -= 4; | |
c0ebe874 | 12952 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12953 | offset_reloc[1], offset_reloc[2], breg); |
12954 | } | |
12955 | else | |
12956 | { | |
c0ebe874 | 12957 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12958 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12959 | breg); | |
12960 | ep->X_add_number += 4; | |
c0ebe874 | 12961 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12962 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12963 | breg); | |
12964 | } | |
12965 | break; | |
12966 | } | |
12967 | ||
252b5132 RH |
12968 | if (offset_expr.X_op != O_symbol |
12969 | && offset_expr.X_op != O_constant) | |
12970 | { | |
1661c76c | 12971 | as_bad (_("expression too complex")); |
252b5132 RH |
12972 | offset_expr.X_op = O_constant; |
12973 | } | |
12974 | ||
2051e8c4 MR |
12975 | if (HAVE_32BIT_ADDRESSES |
12976 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12977 | { |
12978 | char value [32]; | |
12979 | ||
12980 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12981 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12982 | } |
2051e8c4 | 12983 | |
90ecf173 | 12984 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12985 | { |
12986 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12987 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12988 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12989 | If we have a base register, we use this |
12990 | addu $at,$breg,$gp | |
c0ebe874 RS |
12991 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12992 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12993 | If this is not a GP relative symbol, we want |
12994 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12995 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12996 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12997 | If there is a base register, we add it to $at after the |
12998 | lui instruction. If there is a constant, we always use | |
12999 | the last case. */ | |
39a59cf8 MR |
13000 | if (offset_expr.X_op == O_symbol |
13001 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 13002 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 13003 | { |
4d7206a2 | 13004 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
13005 | if (breg == 0) |
13006 | { | |
c9914766 | 13007 | tempreg = mips_gp_register; |
252b5132 RH |
13008 | } |
13009 | else | |
13010 | { | |
67c0d1eb | 13011 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 13012 | AT, breg, mips_gp_register); |
252b5132 | 13013 | tempreg = AT; |
252b5132 RH |
13014 | used_at = 1; |
13015 | } | |
13016 | ||
beae10d5 | 13017 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13018 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13019 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
13020 | offset_expr.X_add_number += 4; |
13021 | ||
13022 | /* Set mips_optimize to 2 to avoid inserting an | |
13023 | undesired nop. */ | |
13024 | hold_mips_optimize = mips_optimize; | |
13025 | mips_optimize = 2; | |
beae10d5 | 13026 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13027 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13028 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
13029 | mips_optimize = hold_mips_optimize; |
13030 | ||
4d7206a2 | 13031 | relax_switch (); |
252b5132 | 13032 | |
0970e49e | 13033 | offset_expr.X_add_number -= 4; |
252b5132 | 13034 | } |
8fc2e39e | 13035 | used_at = 1; |
f2ae14a1 RS |
13036 | if (offset_high_part (offset_expr.X_add_number, 16) |
13037 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
13038 | { | |
13039 | load_address (AT, &offset_expr, &used_at); | |
13040 | offset_expr.X_op = O_constant; | |
13041 | offset_expr.X_add_number = 0; | |
13042 | } | |
13043 | else | |
13044 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 13045 | if (breg != 0) |
67c0d1eb | 13046 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13047 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13048 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13049 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13050 | /* FIXME: How do we handle overflow here? */ |
13051 | offset_expr.X_add_number += 4; | |
beae10d5 | 13052 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13053 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13054 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
13055 | if (mips_relax.sequence) |
13056 | relax_end (); | |
bdaaa2e1 | 13057 | } |
0a44bf69 | 13058 | else if (!mips_big_got) |
252b5132 | 13059 | { |
252b5132 RH |
13060 | /* If this is a reference to an external symbol, we want |
13061 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13062 | nop | |
c0ebe874 RS |
13063 | <op> op[0],0($at) |
13064 | <op> op[0]+1,4($at) | |
252b5132 RH |
13065 | Otherwise we want |
13066 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13067 | nop | |
c0ebe874 RS |
13068 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
13069 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
13070 | If there is a base register we add it to $at before the |
13071 | lwc1 instructions. If there is a constant we include it | |
13072 | in the lwc1 instructions. */ | |
13073 | used_at = 1; | |
13074 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
13075 | if (expr1.X_add_number < -0x8000 |
13076 | || expr1.X_add_number >= 0x8000 - 4) | |
13077 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 13078 | load_got_offset (AT, &offset_expr); |
269137b2 | 13079 | load_delay_nop (); |
252b5132 | 13080 | if (breg != 0) |
67c0d1eb | 13081 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
13082 | |
13083 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13084 | nop. */ | |
13085 | hold_mips_optimize = mips_optimize; | |
13086 | mips_optimize = 2; | |
4d7206a2 | 13087 | |
beae10d5 | 13088 | /* Itbl support may require additional care here. */ |
4d7206a2 | 13089 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 13090 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13091 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13092 | expr1.X_add_number += 4; |
c0ebe874 | 13093 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13094 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13095 | relax_switch (); |
c0ebe874 | 13096 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13097 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13098 | offset_expr.X_add_number += 4; |
c0ebe874 | 13099 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13100 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13101 | relax_end (); |
252b5132 | 13102 | |
4d7206a2 | 13103 | mips_optimize = hold_mips_optimize; |
252b5132 | 13104 | } |
0a44bf69 | 13105 | else if (mips_big_got) |
252b5132 | 13106 | { |
67c0d1eb | 13107 | int gpdelay; |
252b5132 RH |
13108 | |
13109 | /* If this is a reference to an external symbol, we want | |
13110 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
13111 | addu $at,$at,$gp | |
13112 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
13113 | nop | |
c0ebe874 RS |
13114 | <op> op[0],0($at) |
13115 | <op> op[0]+1,4($at) | |
252b5132 RH |
13116 | Otherwise we want |
13117 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13118 | nop | |
c0ebe874 RS |
13119 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
13120 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
13121 | If there is a base register we add it to $at before the |
13122 | lwc1 instructions. If there is a constant we include it | |
13123 | in the lwc1 instructions. */ | |
13124 | used_at = 1; | |
13125 | expr1.X_add_number = offset_expr.X_add_number; | |
13126 | offset_expr.X_add_number = 0; | |
13127 | if (expr1.X_add_number < -0x8000 | |
13128 | || expr1.X_add_number >= 0x8000 - 4) | |
13129 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 13130 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 13131 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 13132 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
13133 | AT, BFD_RELOC_MIPS_GOT_HI16); |
13134 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 13135 | AT, AT, mips_gp_register); |
67c0d1eb | 13136 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 13137 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 13138 | load_delay_nop (); |
252b5132 | 13139 | if (breg != 0) |
67c0d1eb | 13140 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13141 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13142 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13143 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13144 | expr1.X_add_number += 4; |
13145 | ||
13146 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13147 | nop. */ | |
13148 | hold_mips_optimize = mips_optimize; | |
13149 | mips_optimize = 2; | |
beae10d5 | 13150 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13151 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13152 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13153 | mips_optimize = hold_mips_optimize; |
13154 | expr1.X_add_number -= 4; | |
13155 | ||
4d7206a2 RS |
13156 | relax_switch (); |
13157 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
13158 | if (gpdelay) |
13159 | macro_build (NULL, "nop", ""); | |
13160 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
13161 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 13162 | load_delay_nop (); |
252b5132 | 13163 | if (breg != 0) |
67c0d1eb | 13164 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13165 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13166 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13167 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13168 | offset_expr.X_add_number += 4; |
252b5132 RH |
13169 | |
13170 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13171 | nop. */ | |
13172 | hold_mips_optimize = mips_optimize; | |
13173 | mips_optimize = 2; | |
beae10d5 | 13174 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13175 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13176 | BFD_RELOC_LO16, AT); |
252b5132 | 13177 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 13178 | relax_end (); |
252b5132 | 13179 | } |
252b5132 RH |
13180 | else |
13181 | abort (); | |
13182 | ||
252b5132 | 13183 | break; |
3739860c | 13184 | |
dd6a37e7 | 13185 | case M_SAA_AB: |
dd6a37e7 | 13186 | s = "saa"; |
0db377d0 | 13187 | goto saa_saad; |
dd6a37e7 | 13188 | case M_SAAD_AB: |
dd6a37e7 | 13189 | s = "saad"; |
0db377d0 MR |
13190 | saa_saad: |
13191 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 13192 | offbits = 0; |
dd6a37e7 AP |
13193 | fmt = "t,(b)"; |
13194 | goto ld_st; | |
13195 | ||
252b5132 RH |
13196 | /* New code added to support COPZ instructions. |
13197 | This code builds table entries out of the macros in mip_opcodes. | |
13198 | R4000 uses interlocks to handle coproc delays. | |
13199 | Other chips (like the R3000) require nops to be inserted for delays. | |
13200 | ||
f72c8c98 | 13201 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
13202 | In order to fill delay slots for non-interlocked chips, |
13203 | we must have a way to specify delays based on the coprocessor. | |
13204 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
13205 | What are the side-effects of the cop instruction? | |
13206 | What cache support might we have and what are its effects? | |
13207 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 13208 | What registers are read/set/modified? |
252b5132 RH |
13209 | |
13210 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 13211 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
13212 | |
13213 | case M_COP0: | |
13214 | s = "c0"; | |
13215 | goto copz; | |
13216 | case M_COP1: | |
13217 | s = "c1"; | |
13218 | goto copz; | |
13219 | case M_COP2: | |
13220 | s = "c2"; | |
13221 | goto copz; | |
13222 | case M_COP3: | |
13223 | s = "c3"; | |
13224 | copz: | |
df58fc94 | 13225 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
13226 | /* For now we just do C (same as Cz). The parameter will be |
13227 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 13228 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 13229 | break; |
252b5132 | 13230 | |
ea1fb5dc | 13231 | case M_MOVE: |
c0ebe874 | 13232 | move_register (op[0], op[1]); |
8fc2e39e | 13233 | break; |
ea1fb5dc | 13234 | |
833794fc MR |
13235 | case M_MOVEP: |
13236 | gas_assert (mips_opts.micromips); | |
13237 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
13238 | move_register (micromips_to_32_reg_h_map1[op[0]], |
13239 | micromips_to_32_reg_m_map[op[1]]); | |
13240 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
13241 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
13242 | break; |
13243 | ||
252b5132 RH |
13244 | case M_DMUL: |
13245 | dbl = 1; | |
1a0670f3 | 13246 | /* Fall through. */ |
252b5132 | 13247 | case M_MUL: |
e407c74b | 13248 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
13249 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
13250 | op[2]); | |
e407c74b NC |
13251 | else |
13252 | { | |
c0ebe874 RS |
13253 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
13254 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 13255 | } |
8fc2e39e | 13256 | break; |
252b5132 RH |
13257 | |
13258 | case M_DMUL_I: | |
13259 | dbl = 1; | |
1a0670f3 | 13260 | /* Fall through. */ |
252b5132 RH |
13261 | case M_MUL_I: |
13262 | /* The MIPS assembler some times generates shifts and adds. I'm | |
13263 | not trying to be that fancy. GCC should do this for us | |
13264 | anyway. */ | |
8fc2e39e | 13265 | used_at = 1; |
67c0d1eb | 13266 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13267 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
13268 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
13269 | break; |
13270 | ||
13271 | case M_DMULO_I: | |
13272 | dbl = 1; | |
1a0670f3 | 13273 | /* Fall through. */ |
252b5132 RH |
13274 | case M_MULO_I: |
13275 | imm = 1; | |
13276 | goto do_mulo; | |
13277 | ||
13278 | case M_DMULO: | |
13279 | dbl = 1; | |
1a0670f3 | 13280 | /* Fall through. */ |
252b5132 RH |
13281 | case M_MULO: |
13282 | do_mulo: | |
7d10b47d | 13283 | start_noreorder (); |
8fc2e39e | 13284 | used_at = 1; |
252b5132 | 13285 | if (imm) |
67c0d1eb | 13286 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13287 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
13288 | op[1], imm ? AT : op[2]); | |
13289 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
13290 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 13291 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 13292 | if (mips_trap) |
c0ebe874 | 13293 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
13294 | else |
13295 | { | |
df58fc94 RS |
13296 | if (mips_opts.micromips) |
13297 | micromips_label_expr (&label_expr); | |
13298 | else | |
13299 | label_expr.X_add_number = 8; | |
c0ebe874 | 13300 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 13301 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13302 | macro_build (NULL, "break", BRK_FMT, 6); |
13303 | if (mips_opts.micromips) | |
13304 | micromips_add_label (); | |
252b5132 | 13305 | } |
7d10b47d | 13306 | end_noreorder (); |
c0ebe874 | 13307 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
13308 | break; |
13309 | ||
13310 | case M_DMULOU_I: | |
13311 | dbl = 1; | |
1a0670f3 | 13312 | /* Fall through. */ |
252b5132 RH |
13313 | case M_MULOU_I: |
13314 | imm = 1; | |
13315 | goto do_mulou; | |
13316 | ||
13317 | case M_DMULOU: | |
13318 | dbl = 1; | |
1a0670f3 | 13319 | /* Fall through. */ |
252b5132 RH |
13320 | case M_MULOU: |
13321 | do_mulou: | |
7d10b47d | 13322 | start_noreorder (); |
8fc2e39e | 13323 | used_at = 1; |
252b5132 | 13324 | if (imm) |
67c0d1eb RS |
13325 | load_register (AT, &imm_expr, dbl); |
13326 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 13327 | op[1], imm ? AT : op[2]); |
df58fc94 | 13328 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 13329 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 13330 | if (mips_trap) |
df58fc94 | 13331 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
13332 | else |
13333 | { | |
df58fc94 RS |
13334 | if (mips_opts.micromips) |
13335 | micromips_label_expr (&label_expr); | |
13336 | else | |
13337 | label_expr.X_add_number = 8; | |
13338 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 13339 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13340 | macro_build (NULL, "break", BRK_FMT, 6); |
13341 | if (mips_opts.micromips) | |
13342 | micromips_add_label (); | |
252b5132 | 13343 | } |
7d10b47d | 13344 | end_noreorder (); |
252b5132 RH |
13345 | break; |
13346 | ||
771c7ce4 | 13347 | case M_DROL: |
fef14a42 | 13348 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13349 | { |
c0ebe874 | 13350 | if (op[0] == op[1]) |
82dd0097 CD |
13351 | { |
13352 | tempreg = AT; | |
13353 | used_at = 1; | |
13354 | } | |
13355 | else | |
c0ebe874 RS |
13356 | tempreg = op[0]; |
13357 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
13358 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13359 | break; |
82dd0097 | 13360 | } |
8fc2e39e | 13361 | used_at = 1; |
c0ebe874 RS |
13362 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13363 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
13364 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
13365 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13366 | break; |
13367 | ||
252b5132 | 13368 | case M_ROL: |
fef14a42 | 13369 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13370 | { |
c0ebe874 | 13371 | if (op[0] == op[1]) |
82dd0097 CD |
13372 | { |
13373 | tempreg = AT; | |
13374 | used_at = 1; | |
13375 | } | |
13376 | else | |
c0ebe874 RS |
13377 | tempreg = op[0]; |
13378 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
13379 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13380 | break; |
82dd0097 | 13381 | } |
8fc2e39e | 13382 | used_at = 1; |
c0ebe874 RS |
13383 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13384 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
13385 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
13386 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13387 | break; |
13388 | ||
771c7ce4 TS |
13389 | case M_DROL_I: |
13390 | { | |
13391 | unsigned int rot; | |
e0471c16 TS |
13392 | const char *l; |
13393 | const char *rr; | |
771c7ce4 | 13394 | |
771c7ce4 | 13395 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13396 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
13397 | { |
13398 | rot = (64 - rot) & 0x3f; | |
13399 | if (rot >= 32) | |
c0ebe874 | 13400 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 13401 | else |
c0ebe874 | 13402 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13403 | break; |
60b63b72 | 13404 | } |
483fc7cd | 13405 | if (rot == 0) |
483fc7cd | 13406 | { |
c0ebe874 | 13407 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13408 | break; |
483fc7cd | 13409 | } |
82dd0097 | 13410 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 13411 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 13412 | rot &= 0x1f; |
8fc2e39e | 13413 | used_at = 1; |
c0ebe874 RS |
13414 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
13415 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13416 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13417 | } |
13418 | break; | |
13419 | ||
252b5132 | 13420 | case M_ROL_I: |
771c7ce4 TS |
13421 | { |
13422 | unsigned int rot; | |
13423 | ||
771c7ce4 | 13424 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13425 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 13426 | { |
c0ebe874 RS |
13427 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
13428 | (32 - rot) & 0x1f); | |
8fc2e39e | 13429 | break; |
60b63b72 | 13430 | } |
483fc7cd | 13431 | if (rot == 0) |
483fc7cd | 13432 | { |
c0ebe874 | 13433 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13434 | break; |
483fc7cd | 13435 | } |
8fc2e39e | 13436 | used_at = 1; |
c0ebe874 RS |
13437 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
13438 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13439 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13440 | } |
13441 | break; | |
13442 | ||
13443 | case M_DROR: | |
fef14a42 | 13444 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13445 | { |
c0ebe874 | 13446 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13447 | break; |
82dd0097 | 13448 | } |
8fc2e39e | 13449 | used_at = 1; |
c0ebe874 RS |
13450 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13451 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13452 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13453 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13454 | break; |
13455 | ||
13456 | case M_ROR: | |
fef14a42 | 13457 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13458 | { |
c0ebe874 | 13459 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13460 | break; |
82dd0097 | 13461 | } |
8fc2e39e | 13462 | used_at = 1; |
c0ebe874 RS |
13463 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13464 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13465 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13466 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13467 | break; |
13468 | ||
771c7ce4 TS |
13469 | case M_DROR_I: |
13470 | { | |
13471 | unsigned int rot; | |
e0471c16 TS |
13472 | const char *l; |
13473 | const char *rr; | |
771c7ce4 | 13474 | |
771c7ce4 | 13475 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13476 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13477 | { |
13478 | if (rot >= 32) | |
c0ebe874 | 13479 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13480 | else |
c0ebe874 | 13481 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13482 | break; |
82dd0097 | 13483 | } |
483fc7cd | 13484 | if (rot == 0) |
483fc7cd | 13485 | { |
c0ebe874 | 13486 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13487 | break; |
483fc7cd | 13488 | } |
91d6fa6a | 13489 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13490 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13491 | rot &= 0x1f; | |
8fc2e39e | 13492 | used_at = 1; |
c0ebe874 RS |
13493 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13494 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13495 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13496 | } |
13497 | break; | |
13498 | ||
252b5132 | 13499 | case M_ROR_I: |
771c7ce4 TS |
13500 | { |
13501 | unsigned int rot; | |
13502 | ||
771c7ce4 | 13503 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13504 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13505 | { |
c0ebe874 | 13506 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13507 | break; |
82dd0097 | 13508 | } |
483fc7cd | 13509 | if (rot == 0) |
483fc7cd | 13510 | { |
c0ebe874 | 13511 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13512 | break; |
483fc7cd | 13513 | } |
8fc2e39e | 13514 | used_at = 1; |
c0ebe874 RS |
13515 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13516 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13517 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13518 | } |
252b5132 RH |
13519 | break; |
13520 | ||
252b5132 | 13521 | case M_SEQ: |
c0ebe874 RS |
13522 | if (op[1] == 0) |
13523 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13524 | else if (op[2] == 0) | |
13525 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13526 | else |
13527 | { | |
c0ebe874 RS |
13528 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13529 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13530 | } |
8fc2e39e | 13531 | break; |
252b5132 RH |
13532 | |
13533 | case M_SEQ_I: | |
b0e6f033 | 13534 | if (imm_expr.X_add_number == 0) |
252b5132 | 13535 | { |
c0ebe874 | 13536 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13537 | break; |
252b5132 | 13538 | } |
c0ebe874 | 13539 | if (op[1] == 0) |
252b5132 | 13540 | { |
1661c76c | 13541 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13542 | ip->insn_mo->name); |
c0ebe874 | 13543 | move_register (op[0], 0); |
8fc2e39e | 13544 | break; |
252b5132 | 13545 | } |
dd3cbb7e NC |
13546 | if (CPU_HAS_SEQ (mips_opts.arch) |
13547 | && -512 <= imm_expr.X_add_number | |
13548 | && imm_expr.X_add_number < 512) | |
13549 | { | |
c0ebe874 | 13550 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13551 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13552 | break; |
13553 | } | |
b0e6f033 | 13554 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13555 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13556 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13557 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13558 | && imm_expr.X_add_number < 0) |
13559 | { | |
13560 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13561 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13562 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13563 | } |
dd3cbb7e NC |
13564 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13565 | { | |
13566 | used_at = 1; | |
bad1aba3 | 13567 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13568 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13569 | break; |
13570 | } | |
252b5132 RH |
13571 | else |
13572 | { | |
bad1aba3 | 13573 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13574 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13575 | used_at = 1; |
13576 | } | |
c0ebe874 | 13577 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13578 | break; |
252b5132 | 13579 | |
c0ebe874 | 13580 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13581 | s = "slt"; |
13582 | goto sge; | |
13583 | case M_SGEU: | |
13584 | s = "sltu"; | |
13585 | sge: | |
c0ebe874 RS |
13586 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13587 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13588 | break; |
252b5132 | 13589 | |
6f2117ba | 13590 | case M_SGE_I: /* X >= I <==> not (X < I). */ |
252b5132 | 13591 | case M_SGEU_I: |
b0e6f033 | 13592 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13593 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13594 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13595 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13596 | else |
13597 | { | |
bad1aba3 | 13598 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13599 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13600 | op[0], op[1], AT); |
252b5132 RH |
13601 | used_at = 1; |
13602 | } | |
c0ebe874 | 13603 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13604 | break; |
252b5132 | 13605 | |
6f2117ba | 13606 | case M_SGT: /* X > Y <==> Y < X. */ |
252b5132 RH |
13607 | s = "slt"; |
13608 | goto sgt; | |
13609 | case M_SGTU: | |
13610 | s = "sltu"; | |
13611 | sgt: | |
c0ebe874 | 13612 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13613 | break; |
252b5132 | 13614 | |
6f2117ba | 13615 | case M_SGT_I: /* X > I <==> I < X. */ |
252b5132 RH |
13616 | s = "slt"; |
13617 | goto sgti; | |
13618 | case M_SGTU_I: | |
13619 | s = "sltu"; | |
13620 | sgti: | |
8fc2e39e | 13621 | used_at = 1; |
bad1aba3 | 13622 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13623 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13624 | break; |
13625 | ||
6f2117ba | 13626 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X). */ |
252b5132 RH |
13627 | s = "slt"; |
13628 | goto sle; | |
13629 | case M_SLEU: | |
13630 | s = "sltu"; | |
13631 | sle: | |
c0ebe874 RS |
13632 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13633 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13634 | break; |
252b5132 | 13635 | |
c0ebe874 | 13636 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13637 | s = "slt"; |
13638 | goto slei; | |
13639 | case M_SLEU_I: | |
13640 | s = "sltu"; | |
13641 | slei: | |
8fc2e39e | 13642 | used_at = 1; |
bad1aba3 | 13643 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13644 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13645 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13646 | break; |
13647 | ||
13648 | case M_SLT_I: | |
b0e6f033 | 13649 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13650 | && imm_expr.X_add_number < 0x8000) |
13651 | { | |
c0ebe874 RS |
13652 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13653 | BFD_RELOC_LO16); | |
8fc2e39e | 13654 | break; |
252b5132 | 13655 | } |
8fc2e39e | 13656 | used_at = 1; |
bad1aba3 | 13657 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13658 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13659 | break; |
13660 | ||
13661 | case M_SLTU_I: | |
b0e6f033 | 13662 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13663 | && imm_expr.X_add_number < 0x8000) |
13664 | { | |
c0ebe874 | 13665 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13666 | BFD_RELOC_LO16); |
8fc2e39e | 13667 | break; |
252b5132 | 13668 | } |
8fc2e39e | 13669 | used_at = 1; |
bad1aba3 | 13670 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13671 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13672 | break; |
13673 | ||
13674 | case M_SNE: | |
c0ebe874 RS |
13675 | if (op[1] == 0) |
13676 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13677 | else if (op[2] == 0) | |
13678 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13679 | else |
13680 | { | |
c0ebe874 RS |
13681 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13682 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13683 | } |
8fc2e39e | 13684 | break; |
252b5132 RH |
13685 | |
13686 | case M_SNE_I: | |
b0e6f033 | 13687 | if (imm_expr.X_add_number == 0) |
252b5132 | 13688 | { |
c0ebe874 | 13689 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13690 | break; |
252b5132 | 13691 | } |
c0ebe874 | 13692 | if (op[1] == 0) |
252b5132 | 13693 | { |
1661c76c | 13694 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13695 | ip->insn_mo->name); |
bad1aba3 | 13696 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13697 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13698 | break; |
252b5132 | 13699 | } |
dd3cbb7e NC |
13700 | if (CPU_HAS_SEQ (mips_opts.arch) |
13701 | && -512 <= imm_expr.X_add_number | |
13702 | && imm_expr.X_add_number < 512) | |
13703 | { | |
c0ebe874 | 13704 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13705 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13706 | break; |
13707 | } | |
b0e6f033 | 13708 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13709 | && imm_expr.X_add_number < 0x10000) |
13710 | { | |
c0ebe874 RS |
13711 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13712 | BFD_RELOC_LO16); | |
252b5132 | 13713 | } |
b0e6f033 | 13714 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13715 | && imm_expr.X_add_number < 0) |
13716 | { | |
13717 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13718 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13719 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13720 | } |
dd3cbb7e NC |
13721 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13722 | { | |
13723 | used_at = 1; | |
bad1aba3 | 13724 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13725 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13726 | break; |
13727 | } | |
252b5132 RH |
13728 | else |
13729 | { | |
bad1aba3 | 13730 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13731 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13732 | used_at = 1; |
13733 | } | |
c0ebe874 | 13734 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13735 | break; |
252b5132 | 13736 | |
df58fc94 RS |
13737 | case M_SUB_I: |
13738 | s = "addi"; | |
13739 | s2 = "sub"; | |
387e7624 FS |
13740 | if (ISA_IS_R6 (mips_opts.isa)) |
13741 | goto do_subi_i; | |
13742 | else | |
13743 | goto do_subi; | |
df58fc94 RS |
13744 | case M_SUBU_I: |
13745 | s = "addiu"; | |
13746 | s2 = "subu"; | |
13747 | goto do_subi; | |
252b5132 RH |
13748 | case M_DSUB_I: |
13749 | dbl = 1; | |
df58fc94 RS |
13750 | s = "daddi"; |
13751 | s2 = "dsub"; | |
387e7624 | 13752 | if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa)) |
df58fc94 | 13753 | goto do_subi; |
b0e6f033 | 13754 | if (imm_expr.X_add_number > -0x200 |
387e7624 FS |
13755 | && imm_expr.X_add_number <= 0x200 |
13756 | && !ISA_IS_R6 (mips_opts.isa)) | |
252b5132 | 13757 | { |
b0e6f033 RS |
13758 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13759 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13760 | break; |
252b5132 | 13761 | } |
df58fc94 | 13762 | goto do_subi_i; |
252b5132 RH |
13763 | case M_DSUBU_I: |
13764 | dbl = 1; | |
df58fc94 RS |
13765 | s = "daddiu"; |
13766 | s2 = "dsubu"; | |
13767 | do_subi: | |
b0e6f033 | 13768 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13769 | && imm_expr.X_add_number <= 0x8000) |
13770 | { | |
13771 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13772 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13773 | break; |
252b5132 | 13774 | } |
df58fc94 | 13775 | do_subi_i: |
8fc2e39e | 13776 | used_at = 1; |
67c0d1eb | 13777 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13778 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13779 | break; |
13780 | ||
13781 | case M_TEQ_I: | |
13782 | s = "teq"; | |
13783 | goto trap; | |
13784 | case M_TGE_I: | |
13785 | s = "tge"; | |
13786 | goto trap; | |
13787 | case M_TGEU_I: | |
13788 | s = "tgeu"; | |
13789 | goto trap; | |
13790 | case M_TLT_I: | |
13791 | s = "tlt"; | |
13792 | goto trap; | |
13793 | case M_TLTU_I: | |
13794 | s = "tltu"; | |
13795 | goto trap; | |
13796 | case M_TNE_I: | |
13797 | s = "tne"; | |
13798 | trap: | |
8fc2e39e | 13799 | used_at = 1; |
bad1aba3 | 13800 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13801 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13802 | break; |
13803 | ||
252b5132 | 13804 | case M_TRUNCWS: |
43841e91 | 13805 | case M_TRUNCWD: |
df58fc94 | 13806 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13807 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13808 | used_at = 1; |
252b5132 RH |
13809 | |
13810 | /* | |
13811 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13812 | * or is there a reason for it? | |
13813 | */ | |
7d10b47d | 13814 | start_noreorder (); |
c0ebe874 RS |
13815 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13816 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13817 | macro_build (NULL, "nop", ""); |
252b5132 | 13818 | expr1.X_add_number = 3; |
c0ebe874 | 13819 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13820 | expr1.X_add_number = 2; |
67c0d1eb RS |
13821 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13822 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13823 | macro_build (NULL, "nop", ""); | |
13824 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13825 | op[0], op[1]); |
13826 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13827 | macro_build (NULL, "nop", ""); |
7d10b47d | 13828 | end_noreorder (); |
252b5132 RH |
13829 | break; |
13830 | ||
f2ae14a1 | 13831 | case M_ULH_AB: |
252b5132 | 13832 | s = "lb"; |
df58fc94 RS |
13833 | s2 = "lbu"; |
13834 | off = 1; | |
13835 | goto uld_st; | |
f2ae14a1 | 13836 | case M_ULHU_AB: |
252b5132 | 13837 | s = "lbu"; |
df58fc94 RS |
13838 | s2 = "lbu"; |
13839 | off = 1; | |
13840 | goto uld_st; | |
f2ae14a1 | 13841 | case M_ULW_AB: |
df58fc94 RS |
13842 | s = "lwl"; |
13843 | s2 = "lwr"; | |
7f3c4072 | 13844 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13845 | off = 3; |
13846 | goto uld_st; | |
f2ae14a1 | 13847 | case M_ULD_AB: |
252b5132 RH |
13848 | s = "ldl"; |
13849 | s2 = "ldr"; | |
7f3c4072 | 13850 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13851 | off = 7; |
df58fc94 | 13852 | goto uld_st; |
f2ae14a1 | 13853 | case M_USH_AB: |
df58fc94 RS |
13854 | s = "sb"; |
13855 | s2 = "sb"; | |
13856 | off = 1; | |
13857 | ust = 1; | |
13858 | goto uld_st; | |
f2ae14a1 | 13859 | case M_USW_AB: |
df58fc94 RS |
13860 | s = "swl"; |
13861 | s2 = "swr"; | |
7f3c4072 | 13862 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13863 | off = 3; |
df58fc94 RS |
13864 | ust = 1; |
13865 | goto uld_st; | |
f2ae14a1 | 13866 | case M_USD_AB: |
df58fc94 RS |
13867 | s = "sdl"; |
13868 | s2 = "sdr"; | |
7f3c4072 | 13869 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13870 | off = 7; |
13871 | ust = 1; | |
13872 | ||
13873 | uld_st: | |
c0ebe874 | 13874 | breg = op[2]; |
f2ae14a1 | 13875 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13876 | ep = &offset_expr; |
13877 | expr1.X_add_number = 0; | |
f2ae14a1 | 13878 | if (large_offset) |
df58fc94 RS |
13879 | { |
13880 | used_at = 1; | |
13881 | tempreg = AT; | |
f2ae14a1 RS |
13882 | if (small_offset_p (0, align, 16)) |
13883 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13884 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13885 | else | |
13886 | { | |
13887 | load_address (tempreg, ep, &used_at); | |
13888 | if (breg != 0) | |
13889 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13890 | tempreg, tempreg, breg); | |
13891 | } | |
13892 | offset_reloc[0] = BFD_RELOC_LO16; | |
13893 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13894 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13895 | breg = tempreg; |
c0ebe874 | 13896 | tempreg = op[0]; |
df58fc94 RS |
13897 | ep = &expr1; |
13898 | } | |
c0ebe874 | 13899 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13900 | { |
13901 | used_at = 1; | |
13902 | tempreg = AT; | |
13903 | } | |
252b5132 | 13904 | else |
c0ebe874 | 13905 | tempreg = op[0]; |
af22f5b2 | 13906 | |
df58fc94 RS |
13907 | if (off == 1) |
13908 | goto ulh_sh; | |
252b5132 | 13909 | |
90ecf173 | 13910 | if (!target_big_endian) |
df58fc94 | 13911 | ep->X_add_number += off; |
f2ae14a1 | 13912 | if (offbits == 12) |
c8276761 | 13913 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13914 | else |
13915 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13916 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13917 | |
90ecf173 | 13918 | if (!target_big_endian) |
df58fc94 | 13919 | ep->X_add_number -= off; |
252b5132 | 13920 | else |
df58fc94 | 13921 | ep->X_add_number += off; |
f2ae14a1 | 13922 | if (offbits == 12) |
df58fc94 | 13923 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13924 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13925 | else |
13926 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13927 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13928 | |
df58fc94 | 13929 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13930 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13931 | { |
13932 | /* Protect second load's delay slot. */ | |
13933 | load_delay_nop (); | |
c0ebe874 | 13934 | move_register (op[0], tempreg); |
df58fc94 | 13935 | } |
8fc2e39e | 13936 | break; |
252b5132 | 13937 | |
df58fc94 | 13938 | ulh_sh: |
d6bc6245 | 13939 | used_at = 1; |
df58fc94 RS |
13940 | if (target_big_endian == ust) |
13941 | ep->X_add_number += off; | |
c0ebe874 | 13942 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13943 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13944 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13945 | |
13946 | /* For halfword transfers we need a temporary register to shuffle | |
13947 | bytes. Unfortunately for M_USH_A we have none available before | |
13948 | the next store as AT holds the base address. We deal with this | |
13949 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13950 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13951 | if (ust) |
c0ebe874 | 13952 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13953 | |
13954 | if (target_big_endian == ust) | |
13955 | ep->X_add_number -= off; | |
252b5132 | 13956 | else |
df58fc94 | 13957 | ep->X_add_number += off; |
f2ae14a1 RS |
13958 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13959 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13960 | |
df58fc94 | 13961 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13962 | if (ust && large_offset) |
df58fc94 RS |
13963 | { |
13964 | if (target_big_endian) | |
13965 | ep->X_add_number += off; | |
13966 | else | |
13967 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13968 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13969 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13970 | } |
13971 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13972 | if (!ust || large_offset) |
df58fc94 | 13973 | { |
c0ebe874 | 13974 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13975 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13976 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13977 | } |
252b5132 RH |
13978 | break; |
13979 | ||
13980 | default: | |
13981 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13982 | are added dynamically. */ |
1661c76c | 13983 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13984 | break; |
13985 | } | |
741fe287 | 13986 | if (!mips_opts.at && used_at) |
1661c76c | 13987 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13988 | } |
13989 | ||
13990 | /* Implement macros in mips16 mode. */ | |
13991 | ||
13992 | static void | |
17a2f251 | 13993 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13994 | { |
c0ebe874 | 13995 | const struct mips_operand_array *operands; |
252b5132 | 13996 | int mask; |
c0ebe874 | 13997 | int tmp; |
252b5132 RH |
13998 | expressionS expr1; |
13999 | int dbl; | |
14000 | const char *s, *s2, *s3; | |
c0ebe874 RS |
14001 | unsigned int op[MAX_OPERANDS]; |
14002 | unsigned int i; | |
252b5132 RH |
14003 | |
14004 | mask = ip->insn_mo->mask; | |
14005 | ||
c0ebe874 RS |
14006 | operands = insn_operands (ip); |
14007 | for (i = 0; i < MAX_OPERANDS; i++) | |
14008 | if (operands->operand[i]) | |
14009 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
14010 | else | |
14011 | op[i] = -1; | |
252b5132 | 14012 | |
252b5132 RH |
14013 | expr1.X_op = O_constant; |
14014 | expr1.X_op_symbol = NULL; | |
14015 | expr1.X_add_symbol = NULL; | |
14016 | expr1.X_add_number = 1; | |
14017 | ||
14018 | dbl = 0; | |
14019 | ||
14020 | switch (mask) | |
14021 | { | |
14022 | default: | |
b37df7c4 | 14023 | abort (); |
252b5132 RH |
14024 | |
14025 | case M_DDIV_3: | |
14026 | dbl = 1; | |
1a0670f3 | 14027 | /* Fall through. */ |
252b5132 RH |
14028 | case M_DIV_3: |
14029 | s = "mflo"; | |
14030 | goto do_div3; | |
14031 | case M_DREM_3: | |
14032 | dbl = 1; | |
1a0670f3 | 14033 | /* Fall through. */ |
252b5132 RH |
14034 | case M_REM_3: |
14035 | s = "mfhi"; | |
14036 | do_div3: | |
7d10b47d | 14037 | start_noreorder (); |
d8722d76 | 14038 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 14039 | expr1.X_add_number = 2; |
c0ebe874 | 14040 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 14041 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 14042 | |
252b5132 RH |
14043 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
14044 | since that causes an overflow. We should do that as well, | |
14045 | but I don't see how to do the comparisons without a temporary | |
14046 | register. */ | |
7d10b47d | 14047 | end_noreorder (); |
c0ebe874 | 14048 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
14049 | break; |
14050 | ||
14051 | case M_DIVU_3: | |
14052 | s = "divu"; | |
14053 | s2 = "mflo"; | |
14054 | goto do_divu3; | |
14055 | case M_REMU_3: | |
14056 | s = "divu"; | |
14057 | s2 = "mfhi"; | |
14058 | goto do_divu3; | |
14059 | case M_DDIVU_3: | |
14060 | s = "ddivu"; | |
14061 | s2 = "mflo"; | |
14062 | goto do_divu3; | |
14063 | case M_DREMU_3: | |
14064 | s = "ddivu"; | |
14065 | s2 = "mfhi"; | |
14066 | do_divu3: | |
7d10b47d | 14067 | start_noreorder (); |
d8722d76 | 14068 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 14069 | expr1.X_add_number = 2; |
c0ebe874 | 14070 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 14071 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 14072 | end_noreorder (); |
c0ebe874 | 14073 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
14074 | break; |
14075 | ||
14076 | case M_DMUL: | |
14077 | dbl = 1; | |
1a0670f3 | 14078 | /* Fall through. */ |
252b5132 | 14079 | case M_MUL: |
c0ebe874 RS |
14080 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
14081 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 14082 | break; |
252b5132 RH |
14083 | |
14084 | case M_DSUBU_I: | |
14085 | dbl = 1; | |
14086 | goto do_subu; | |
14087 | case M_SUBU_I: | |
14088 | do_subu: | |
252b5132 | 14089 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 14090 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
14091 | break; |
14092 | ||
14093 | case M_SUBU_I_2: | |
252b5132 | 14094 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 14095 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
14096 | break; |
14097 | ||
14098 | case M_DSUBU_I_2: | |
252b5132 | 14099 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 14100 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
14101 | break; |
14102 | ||
14103 | case M_BEQ: | |
14104 | s = "cmp"; | |
14105 | s2 = "bteqz"; | |
14106 | goto do_branch; | |
14107 | case M_BNE: | |
14108 | s = "cmp"; | |
14109 | s2 = "btnez"; | |
14110 | goto do_branch; | |
14111 | case M_BLT: | |
14112 | s = "slt"; | |
14113 | s2 = "btnez"; | |
14114 | goto do_branch; | |
14115 | case M_BLTU: | |
14116 | s = "sltu"; | |
14117 | s2 = "btnez"; | |
14118 | goto do_branch; | |
14119 | case M_BLE: | |
14120 | s = "slt"; | |
14121 | s2 = "bteqz"; | |
14122 | goto do_reverse_branch; | |
14123 | case M_BLEU: | |
14124 | s = "sltu"; | |
14125 | s2 = "bteqz"; | |
14126 | goto do_reverse_branch; | |
14127 | case M_BGE: | |
14128 | s = "slt"; | |
14129 | s2 = "bteqz"; | |
14130 | goto do_branch; | |
14131 | case M_BGEU: | |
14132 | s = "sltu"; | |
14133 | s2 = "bteqz"; | |
14134 | goto do_branch; | |
14135 | case M_BGT: | |
14136 | s = "slt"; | |
14137 | s2 = "btnez"; | |
14138 | goto do_reverse_branch; | |
14139 | case M_BGTU: | |
14140 | s = "sltu"; | |
14141 | s2 = "btnez"; | |
14142 | ||
14143 | do_reverse_branch: | |
c0ebe874 RS |
14144 | tmp = op[1]; |
14145 | op[1] = op[0]; | |
14146 | op[0] = tmp; | |
252b5132 RH |
14147 | |
14148 | do_branch: | |
c0ebe874 | 14149 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 14150 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
14151 | break; |
14152 | ||
14153 | case M_BEQ_I: | |
14154 | s = "cmpi"; | |
14155 | s2 = "bteqz"; | |
14156 | s3 = "x,U"; | |
14157 | goto do_branch_i; | |
14158 | case M_BNE_I: | |
14159 | s = "cmpi"; | |
14160 | s2 = "btnez"; | |
14161 | s3 = "x,U"; | |
14162 | goto do_branch_i; | |
14163 | case M_BLT_I: | |
14164 | s = "slti"; | |
14165 | s2 = "btnez"; | |
14166 | s3 = "x,8"; | |
14167 | goto do_branch_i; | |
14168 | case M_BLTU_I: | |
14169 | s = "sltiu"; | |
14170 | s2 = "btnez"; | |
14171 | s3 = "x,8"; | |
14172 | goto do_branch_i; | |
14173 | case M_BLE_I: | |
14174 | s = "slti"; | |
14175 | s2 = "btnez"; | |
14176 | s3 = "x,8"; | |
14177 | goto do_addone_branch_i; | |
14178 | case M_BLEU_I: | |
14179 | s = "sltiu"; | |
14180 | s2 = "btnez"; | |
14181 | s3 = "x,8"; | |
14182 | goto do_addone_branch_i; | |
14183 | case M_BGE_I: | |
14184 | s = "slti"; | |
14185 | s2 = "bteqz"; | |
14186 | s3 = "x,8"; | |
14187 | goto do_branch_i; | |
14188 | case M_BGEU_I: | |
14189 | s = "sltiu"; | |
14190 | s2 = "bteqz"; | |
14191 | s3 = "x,8"; | |
14192 | goto do_branch_i; | |
14193 | case M_BGT_I: | |
14194 | s = "slti"; | |
14195 | s2 = "bteqz"; | |
14196 | s3 = "x,8"; | |
14197 | goto do_addone_branch_i; | |
14198 | case M_BGTU_I: | |
14199 | s = "sltiu"; | |
14200 | s2 = "bteqz"; | |
14201 | s3 = "x,8"; | |
14202 | ||
14203 | do_addone_branch_i: | |
252b5132 RH |
14204 | ++imm_expr.X_add_number; |
14205 | ||
14206 | do_branch_i: | |
c0ebe874 | 14207 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 14208 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
14209 | break; |
14210 | ||
14211 | case M_ABS: | |
14212 | expr1.X_add_number = 0; | |
c0ebe874 RS |
14213 | macro_build (&expr1, "slti", "x,8", op[1]); |
14214 | if (op[0] != op[1]) | |
14215 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 14216 | expr1.X_add_number = 2; |
67c0d1eb | 14217 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 14218 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 14219 | break; |
252b5132 RH |
14220 | } |
14221 | } | |
14222 | ||
14daeee3 RS |
14223 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
14224 | opcode bits in *OPCODE_EXTRA. */ | |
14225 | ||
14226 | static struct mips_opcode * | |
14227 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 14228 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
14229 | { |
14230 | char *name, *dot, *p; | |
14231 | unsigned int mask, suffix; | |
da8bca91 | 14232 | ssize_t opend; |
14daeee3 RS |
14233 | struct mips_opcode *insn; |
14234 | ||
14235 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 14236 | name = xstrndup (start, length); |
14daeee3 RS |
14237 | |
14238 | /* Look up the instruction as-is. */ | |
14239 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 14240 | if (insn) |
e1fa0163 | 14241 | goto end; |
14daeee3 RS |
14242 | |
14243 | dot = strchr (name, '.'); | |
14244 | if (dot && dot[1]) | |
14245 | { | |
14246 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
14247 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
14248 | if (*p == 0 && mask != 0) | |
14249 | { | |
14250 | *dot = 0; | |
14251 | insn = (struct mips_opcode *) hash_find (hash, name); | |
14252 | *dot = '.'; | |
14253 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
14254 | { | |
14255 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 14256 | goto end; |
14daeee3 RS |
14257 | } |
14258 | } | |
14259 | } | |
14260 | ||
14261 | if (mips_opts.micromips) | |
14262 | { | |
14263 | /* See if there's an instruction size override suffix, | |
14264 | either `16' or `32', at the end of the mnemonic proper, | |
14265 | that defines the operation, i.e. before the first `.' | |
14266 | character if any. Strip it and retry. */ | |
14267 | opend = dot != NULL ? dot - name : length; | |
14268 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
14269 | suffix = 2; | |
3076e594 | 14270 | else if (opend >= 2 && name[opend - 2] == '3' && name[opend - 1] == '2') |
14daeee3 RS |
14271 | suffix = 4; |
14272 | else | |
14273 | suffix = 0; | |
14274 | if (suffix) | |
14275 | { | |
39334a61 | 14276 | memmove (name + opend - 2, name + opend, length - opend + 1); |
14daeee3 | 14277 | insn = (struct mips_opcode *) hash_find (hash, name); |
ee5734f0 | 14278 | if (insn) |
14daeee3 RS |
14279 | { |
14280 | forced_insn_length = suffix; | |
e1fa0163 | 14281 | goto end; |
14daeee3 RS |
14282 | } |
14283 | } | |
14284 | } | |
14285 | ||
e1fa0163 NC |
14286 | insn = NULL; |
14287 | end: | |
14288 | free (name); | |
14289 | return insn; | |
14daeee3 RS |
14290 | } |
14291 | ||
77bd4346 | 14292 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
14293 | is a macro, set imm_expr and offset_expr to the values associated |
14294 | with "I" and "A" operands respectively. Otherwise store the value | |
14295 | of the relocatable field (if any) in offset_expr. In both cases | |
14296 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
14297 | |
14298 | static void | |
60f20e8b | 14299 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14300 | { |
60f20e8b | 14301 | const struct mips_opcode *first, *past; |
df58fc94 | 14302 | struct hash_control *hash; |
a92713e6 | 14303 | char format; |
14daeee3 | 14304 | size_t end; |
a92713e6 | 14305 | struct mips_operand_token *tokens; |
14daeee3 | 14306 | unsigned int opcode_extra; |
252b5132 | 14307 | |
df58fc94 RS |
14308 | if (mips_opts.micromips) |
14309 | { | |
14310 | hash = micromips_op_hash; | |
14311 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
14312 | } | |
14313 | else | |
14314 | { | |
14315 | hash = op_hash; | |
14316 | past = &mips_opcodes[NUMOPCODES]; | |
14317 | } | |
14318 | forced_insn_length = 0; | |
14daeee3 | 14319 | opcode_extra = 0; |
252b5132 | 14320 | |
df58fc94 | 14321 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
14322 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
14323 | continue; | |
bdaaa2e1 | 14324 | |
60f20e8b RS |
14325 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
14326 | if (first == NULL) | |
252b5132 | 14327 | { |
1661c76c | 14328 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 14329 | return; |
252b5132 RH |
14330 | } |
14331 | ||
60f20e8b | 14332 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 14333 | format = 'f'; |
60f20e8b | 14334 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
14335 | format = 'd'; |
14336 | else | |
14337 | format = 0; | |
14338 | tokens = mips_parse_arguments (str + end, format); | |
14339 | if (!tokens) | |
14340 | return; | |
14341 | ||
60f20e8b RS |
14342 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
14343 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 14344 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 14345 | |
e3de51ce | 14346 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14347 | } |
14348 | ||
77bd4346 RS |
14349 | /* As for mips_ip, but used when assembling MIPS16 code. |
14350 | Also set forced_insn_length to the resulting instruction size in | |
14351 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
14352 | |
14353 | static void | |
60f20e8b | 14354 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14355 | { |
1a00e612 | 14356 | char *end, *s, c; |
60f20e8b | 14357 | struct mips_opcode *first; |
a92713e6 | 14358 | struct mips_operand_token *tokens; |
3fb49709 | 14359 | unsigned int l; |
252b5132 | 14360 | |
25499ac7 | 14361 | for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) |
252b5132 | 14362 | ; |
1a00e612 RS |
14363 | end = s; |
14364 | c = *end; | |
3fb49709 MR |
14365 | |
14366 | l = 0; | |
1a00e612 | 14367 | switch (c) |
252b5132 RH |
14368 | { |
14369 | case '\0': | |
14370 | break; | |
14371 | ||
14372 | case ' ': | |
1a00e612 | 14373 | s++; |
252b5132 RH |
14374 | break; |
14375 | ||
14376 | case '.': | |
3fb49709 MR |
14377 | s++; |
14378 | if (*s == 't') | |
252b5132 | 14379 | { |
3fb49709 MR |
14380 | l = 2; |
14381 | s++; | |
252b5132 | 14382 | } |
3fb49709 | 14383 | else if (*s == 'e') |
252b5132 | 14384 | { |
3fb49709 MR |
14385 | l = 4; |
14386 | s++; | |
252b5132 | 14387 | } |
3fb49709 MR |
14388 | if (*s == '\0') |
14389 | break; | |
14390 | else if (*s++ == ' ') | |
14391 | break; | |
1661c76c | 14392 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14393 | return; |
14394 | } | |
3fb49709 | 14395 | forced_insn_length = l; |
252b5132 | 14396 | |
1a00e612 | 14397 | *end = 0; |
60f20e8b | 14398 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
14399 | *end = c; |
14400 | ||
60f20e8b | 14401 | if (!first) |
252b5132 | 14402 | { |
1661c76c | 14403 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14404 | return; |
14405 | } | |
14406 | ||
a92713e6 RS |
14407 | tokens = mips_parse_arguments (s, 0); |
14408 | if (!tokens) | |
14409 | return; | |
14410 | ||
60f20e8b | 14411 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 14412 | set_insn_error (0, _("invalid operands")); |
252b5132 | 14413 | |
e3de51ce | 14414 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14415 | } |
14416 | ||
b886a2ab RS |
14417 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14418 | NBITS is the number of significant bits in VAL. */ | |
14419 | ||
14420 | static unsigned long | |
14421 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14422 | { | |
14423 | int extval; | |
25499ac7 MR |
14424 | |
14425 | extval = 0; | |
14426 | val &= (1U << nbits) - 1; | |
14427 | if (nbits == 16 || nbits == 9) | |
b886a2ab RS |
14428 | { |
14429 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14430 | val &= 0x1f; | |
14431 | } | |
14432 | else if (nbits == 15) | |
14433 | { | |
14434 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14435 | val &= 0xf; | |
14436 | } | |
25499ac7 | 14437 | else if (nbits == 6) |
b886a2ab RS |
14438 | { |
14439 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14440 | val = 0; | |
14441 | } | |
14442 | return (extval << 16) | val; | |
14443 | } | |
14444 | ||
3ccad066 RS |
14445 | /* Like decode_mips16_operand, but require the operand to be defined and |
14446 | require it to be an integer. */ | |
14447 | ||
14448 | static const struct mips_int_operand * | |
14449 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
14450 | { | |
14451 | const struct mips_operand *operand; | |
14452 | ||
14453 | operand = decode_mips16_operand (type, extended_p); | |
14454 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
14455 | abort (); | |
14456 | return (const struct mips_int_operand *) operand; | |
14457 | } | |
14458 | ||
14459 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14460 | ||
14461 | static bfd_boolean | |
14462 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14463 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14464 | { | |
14465 | int min_val, max_val; | |
14466 | ||
14467 | min_val = mips_int_operand_min (operand); | |
14468 | max_val = mips_int_operand_max (operand); | |
14469 | if (reloc != BFD_RELOC_UNUSED) | |
14470 | { | |
14471 | if (min_val < 0) | |
14472 | sval = SEXT_16BIT (sval); | |
14473 | else | |
14474 | sval &= 0xffff; | |
14475 | } | |
14476 | ||
14477 | return (sval >= min_val | |
14478 | && sval <= max_val | |
14479 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14480 | } | |
14481 | ||
5c04167a RS |
14482 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14483 | extending it if necessary. The instruction in *INSN may | |
14484 | already be extended. | |
14485 | ||
43c0598f RS |
14486 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14487 | if none. In the former case, VAL is a 16-bit number with no | |
14488 | defined signedness. | |
14489 | ||
14490 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14491 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14492 | |
14493 | static void | |
3b4dbbbf | 14494 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14495 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14496 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14497 | { |
3ccad066 RS |
14498 | const struct mips_int_operand *operand; |
14499 | unsigned int uval, length; | |
252b5132 | 14500 | |
3ccad066 RS |
14501 | operand = mips16_immed_operand (type, FALSE); |
14502 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14503 | { |
14504 | /* We need an extended instruction. */ | |
14505 | if (user_insn_length == 2) | |
14506 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14507 | else | |
14508 | *insn |= MIPS16_EXTEND; | |
14509 | } | |
14510 | else if (user_insn_length == 4) | |
14511 | { | |
14512 | /* The operand doesn't force an unextended instruction to be extended. | |
14513 | Warn if the user wanted an extended instruction anyway. */ | |
14514 | *insn |= MIPS16_EXTEND; | |
14515 | as_warn_where (file, line, | |
14516 | _("extended operand requested but not required")); | |
14517 | } | |
252b5132 | 14518 | |
3ccad066 RS |
14519 | length = mips16_opcode_length (*insn); |
14520 | if (length == 4) | |
252b5132 | 14521 | { |
3ccad066 RS |
14522 | operand = mips16_immed_operand (type, TRUE); |
14523 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14524 | as_bad_where (file, line, | |
14525 | _("operand value out of range for instruction")); | |
252b5132 | 14526 | } |
3ccad066 | 14527 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14528 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14529 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14530 | else |
3ccad066 | 14531 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14532 | } |
14533 | \f | |
d6f16593 | 14534 | struct percent_op_match |
ad8d3bb3 | 14535 | { |
5e0116d5 RS |
14536 | const char *str; |
14537 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14538 | }; |
14539 | ||
14540 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14541 | { |
5e0116d5 | 14542 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14543 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14544 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14545 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14546 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14547 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14548 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14549 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14550 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14551 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14552 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14553 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14554 | {"%half", BFD_RELOC_16}, |
14555 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14556 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14557 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14558 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14559 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14560 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14561 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14562 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14563 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14564 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14565 | {"%hi", BFD_RELOC_HI16_S}, |
14566 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14567 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14568 | }; |
14569 | ||
d6f16593 MR |
14570 | static const struct percent_op_match mips16_percent_op[] = |
14571 | { | |
14572 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14573 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14574 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14575 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14576 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14577 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14578 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14579 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14580 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14581 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14582 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14583 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14584 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14585 | }; |
14586 | ||
252b5132 | 14587 | |
5e0116d5 RS |
14588 | /* Return true if *STR points to a relocation operator. When returning true, |
14589 | move *STR over the operator and store its relocation code in *RELOC. | |
14590 | Leave both *STR and *RELOC alone when returning false. */ | |
14591 | ||
14592 | static bfd_boolean | |
17a2f251 | 14593 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14594 | { |
d6f16593 MR |
14595 | const struct percent_op_match *percent_op; |
14596 | size_t limit, i; | |
14597 | ||
14598 | if (mips_opts.mips16) | |
14599 | { | |
14600 | percent_op = mips16_percent_op; | |
14601 | limit = ARRAY_SIZE (mips16_percent_op); | |
14602 | } | |
14603 | else | |
14604 | { | |
14605 | percent_op = mips_percent_op; | |
14606 | limit = ARRAY_SIZE (mips_percent_op); | |
14607 | } | |
76b3015f | 14608 | |
d6f16593 | 14609 | for (i = 0; i < limit; i++) |
5e0116d5 | 14610 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14611 | { |
3f98094e DJ |
14612 | int len = strlen (percent_op[i].str); |
14613 | ||
14614 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14615 | continue; | |
14616 | ||
5e0116d5 RS |
14617 | *str += strlen (percent_op[i].str); |
14618 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14619 | |
5e0116d5 RS |
14620 | /* Check whether the output BFD supports this relocation. |
14621 | If not, issue an error and fall back on something safe. */ | |
14622 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14623 | { |
20203fb9 | 14624 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14625 | percent_op[i].str); |
01a3f561 | 14626 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14627 | } |
5e0116d5 | 14628 | return TRUE; |
394f9b3a | 14629 | } |
5e0116d5 | 14630 | return FALSE; |
394f9b3a | 14631 | } |
ad8d3bb3 | 14632 | |
ad8d3bb3 | 14633 | |
5e0116d5 RS |
14634 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14635 | expression in *EP and the relocations in the array starting | |
14636 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14637 | |
01a3f561 | 14638 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14639 | |
5e0116d5 | 14640 | static size_t |
17a2f251 TS |
14641 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14642 | char *str) | |
ad8d3bb3 | 14643 | { |
5e0116d5 RS |
14644 | bfd_reloc_code_real_type reversed_reloc[3]; |
14645 | size_t reloc_index, i; | |
09b8f35a RS |
14646 | int crux_depth, str_depth; |
14647 | char *crux; | |
5e0116d5 RS |
14648 | |
14649 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14650 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14651 | of the main expression and with CRUX_DEPTH containing the number | |
14652 | of open brackets at that point. */ | |
14653 | reloc_index = -1; | |
14654 | str_depth = 0; | |
14655 | do | |
fb1b3232 | 14656 | { |
09b8f35a RS |
14657 | reloc_index++; |
14658 | crux = str; | |
14659 | crux_depth = str_depth; | |
14660 | ||
14661 | /* Skip over whitespace and brackets, keeping count of the number | |
14662 | of brackets. */ | |
14663 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14664 | if (*str++ == '(') | |
14665 | str_depth++; | |
5e0116d5 | 14666 | } |
09b8f35a RS |
14667 | while (*str == '%' |
14668 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14669 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14670 | |
09b8f35a | 14671 | my_getExpression (ep, crux); |
5e0116d5 | 14672 | str = expr_end; |
394f9b3a | 14673 | |
5e0116d5 | 14674 | /* Match every open bracket. */ |
09b8f35a | 14675 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14676 | if (*str++ == ')') |
09b8f35a | 14677 | crux_depth--; |
394f9b3a | 14678 | |
09b8f35a | 14679 | if (crux_depth > 0) |
20203fb9 | 14680 | as_bad (_("unclosed '('")); |
394f9b3a | 14681 | |
5e0116d5 | 14682 | expr_end = str; |
252b5132 | 14683 | |
01a3f561 | 14684 | if (reloc_index != 0) |
64bdfcaf RS |
14685 | { |
14686 | prev_reloc_op_frag = frag_now; | |
14687 | for (i = 0; i < reloc_index; i++) | |
14688 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14689 | } | |
fb1b3232 | 14690 | |
5e0116d5 | 14691 | return reloc_index; |
252b5132 RH |
14692 | } |
14693 | ||
14694 | static void | |
17a2f251 | 14695 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14696 | { |
14697 | char *save_in; | |
14698 | ||
14699 | save_in = input_line_pointer; | |
14700 | input_line_pointer = str; | |
14701 | expression (ep); | |
14702 | expr_end = input_line_pointer; | |
14703 | input_line_pointer = save_in; | |
252b5132 RH |
14704 | } |
14705 | ||
6d4af3c2 | 14706 | const char * |
17a2f251 | 14707 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14708 | { |
499ac353 | 14709 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14710 | } |
14711 | ||
14712 | void | |
17a2f251 | 14713 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14714 | { |
14715 | if (target_big_endian) | |
14716 | number_to_chars_bigendian (buf, val, n); | |
14717 | else | |
14718 | number_to_chars_littleendian (buf, val, n); | |
14719 | } | |
14720 | \f | |
e013f690 TS |
14721 | static int support_64bit_objects(void) |
14722 | { | |
14723 | const char **list, **l; | |
aa3d8fdf | 14724 | int yes; |
e013f690 TS |
14725 | |
14726 | list = bfd_target_list (); | |
14727 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14728 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14729 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14730 | break; |
aa3d8fdf | 14731 | yes = (*l != NULL); |
e013f690 | 14732 | free (list); |
aa3d8fdf | 14733 | return yes; |
e013f690 TS |
14734 | } |
14735 | ||
316f5878 RS |
14736 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14737 | NEW_VALUE. Warn if another value was already specified. Note: | |
14738 | we have to defer parsing the -march and -mtune arguments in order | |
14739 | to handle 'from-abi' correctly, since the ABI might be specified | |
14740 | in a later argument. */ | |
14741 | ||
14742 | static void | |
17a2f251 | 14743 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14744 | { |
14745 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14746 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14747 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14748 | new_value); | |
14749 | ||
14750 | *string_ptr = new_value; | |
14751 | } | |
14752 | ||
252b5132 | 14753 | int |
17b9d67d | 14754 | md_parse_option (int c, const char *arg) |
252b5132 | 14755 | { |
c6278170 RS |
14756 | unsigned int i; |
14757 | ||
14758 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14759 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14760 | { | |
919731af | 14761 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14762 | c == mips_ases[i].option_on); |
14763 | return 1; | |
14764 | } | |
14765 | ||
252b5132 RH |
14766 | switch (c) |
14767 | { | |
119d663a NC |
14768 | case OPTION_CONSTRUCT_FLOATS: |
14769 | mips_disable_float_construction = 0; | |
14770 | break; | |
bdaaa2e1 | 14771 | |
119d663a NC |
14772 | case OPTION_NO_CONSTRUCT_FLOATS: |
14773 | mips_disable_float_construction = 1; | |
14774 | break; | |
bdaaa2e1 | 14775 | |
252b5132 RH |
14776 | case OPTION_TRAP: |
14777 | mips_trap = 1; | |
14778 | break; | |
14779 | ||
14780 | case OPTION_BREAK: | |
14781 | mips_trap = 0; | |
14782 | break; | |
14783 | ||
14784 | case OPTION_EB: | |
14785 | target_big_endian = 1; | |
14786 | break; | |
14787 | ||
14788 | case OPTION_EL: | |
14789 | target_big_endian = 0; | |
14790 | break; | |
14791 | ||
14792 | case 'O': | |
4ffff32f TS |
14793 | if (arg == NULL) |
14794 | mips_optimize = 1; | |
14795 | else if (arg[0] == '0') | |
14796 | mips_optimize = 0; | |
14797 | else if (arg[0] == '1') | |
252b5132 RH |
14798 | mips_optimize = 1; |
14799 | else | |
14800 | mips_optimize = 2; | |
14801 | break; | |
14802 | ||
14803 | case 'g': | |
14804 | if (arg == NULL) | |
14805 | mips_debug = 2; | |
14806 | else | |
14807 | mips_debug = atoi (arg); | |
252b5132 RH |
14808 | break; |
14809 | ||
14810 | case OPTION_MIPS1: | |
0b35dfee | 14811 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14812 | break; |
14813 | ||
14814 | case OPTION_MIPS2: | |
0b35dfee | 14815 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14816 | break; |
14817 | ||
14818 | case OPTION_MIPS3: | |
0b35dfee | 14819 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14820 | break; |
14821 | ||
14822 | case OPTION_MIPS4: | |
0b35dfee | 14823 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14824 | break; |
14825 | ||
84ea6cf2 | 14826 | case OPTION_MIPS5: |
0b35dfee | 14827 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14828 | break; |
14829 | ||
e7af610e | 14830 | case OPTION_MIPS32: |
0b35dfee | 14831 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14832 | break; |
14833 | ||
af7ee8bf | 14834 | case OPTION_MIPS32R2: |
0b35dfee | 14835 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14836 | break; |
14837 | ||
ae52f483 | 14838 | case OPTION_MIPS32R3: |
0ae19f05 | 14839 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14840 | break; |
14841 | ||
14842 | case OPTION_MIPS32R5: | |
0ae19f05 | 14843 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14844 | break; |
14845 | ||
7361da2c AB |
14846 | case OPTION_MIPS32R6: |
14847 | file_mips_opts.isa = ISA_MIPS32R6; | |
14848 | break; | |
14849 | ||
5f74bc13 | 14850 | case OPTION_MIPS64R2: |
0b35dfee | 14851 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14852 | break; |
14853 | ||
ae52f483 | 14854 | case OPTION_MIPS64R3: |
0ae19f05 | 14855 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14856 | break; |
14857 | ||
14858 | case OPTION_MIPS64R5: | |
0ae19f05 | 14859 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14860 | break; |
14861 | ||
7361da2c AB |
14862 | case OPTION_MIPS64R6: |
14863 | file_mips_opts.isa = ISA_MIPS64R6; | |
14864 | break; | |
14865 | ||
84ea6cf2 | 14866 | case OPTION_MIPS64: |
0b35dfee | 14867 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14868 | break; |
14869 | ||
ec68c924 | 14870 | case OPTION_MTUNE: |
316f5878 RS |
14871 | mips_set_option_string (&mips_tune_string, arg); |
14872 | break; | |
ec68c924 | 14873 | |
316f5878 RS |
14874 | case OPTION_MARCH: |
14875 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14876 | break; |
14877 | ||
14878 | case OPTION_M4650: | |
316f5878 RS |
14879 | mips_set_option_string (&mips_arch_string, "4650"); |
14880 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14881 | break; |
14882 | ||
14883 | case OPTION_NO_M4650: | |
14884 | break; | |
14885 | ||
14886 | case OPTION_M4010: | |
316f5878 RS |
14887 | mips_set_option_string (&mips_arch_string, "4010"); |
14888 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14889 | break; |
14890 | ||
14891 | case OPTION_NO_M4010: | |
14892 | break; | |
14893 | ||
14894 | case OPTION_M4100: | |
316f5878 RS |
14895 | mips_set_option_string (&mips_arch_string, "4100"); |
14896 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14897 | break; |
14898 | ||
14899 | case OPTION_NO_M4100: | |
14900 | break; | |
14901 | ||
252b5132 | 14902 | case OPTION_M3900: |
316f5878 RS |
14903 | mips_set_option_string (&mips_arch_string, "3900"); |
14904 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14905 | break; |
bdaaa2e1 | 14906 | |
252b5132 RH |
14907 | case OPTION_NO_M3900: |
14908 | break; | |
14909 | ||
df58fc94 | 14910 | case OPTION_MICROMIPS: |
919731af | 14911 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14912 | { |
14913 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14914 | return 0; | |
14915 | } | |
919731af | 14916 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14917 | mips_no_prev_insn (); |
14918 | break; | |
14919 | ||
14920 | case OPTION_NO_MICROMIPS: | |
919731af | 14921 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14922 | mips_no_prev_insn (); |
14923 | break; | |
14924 | ||
252b5132 | 14925 | case OPTION_MIPS16: |
919731af | 14926 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14927 | { |
14928 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14929 | return 0; | |
14930 | } | |
919731af | 14931 | file_mips_opts.mips16 = 1; |
7d10b47d | 14932 | mips_no_prev_insn (); |
252b5132 RH |
14933 | break; |
14934 | ||
14935 | case OPTION_NO_MIPS16: | |
919731af | 14936 | file_mips_opts.mips16 = 0; |
7d10b47d | 14937 | mips_no_prev_insn (); |
252b5132 RH |
14938 | break; |
14939 | ||
6a32d874 CM |
14940 | case OPTION_FIX_24K: |
14941 | mips_fix_24k = 1; | |
14942 | break; | |
14943 | ||
14944 | case OPTION_NO_FIX_24K: | |
14945 | mips_fix_24k = 0; | |
14946 | break; | |
14947 | ||
a8d14a88 CM |
14948 | case OPTION_FIX_RM7000: |
14949 | mips_fix_rm7000 = 1; | |
14950 | break; | |
14951 | ||
14952 | case OPTION_NO_FIX_RM7000: | |
14953 | mips_fix_rm7000 = 0; | |
14954 | break; | |
14955 | ||
6f2117ba PH |
14956 | case OPTION_FIX_LOONGSON3_LLSC: |
14957 | mips_fix_loongson3_llsc = TRUE; | |
14958 | break; | |
14959 | ||
14960 | case OPTION_NO_FIX_LOONGSON3_LLSC: | |
14961 | mips_fix_loongson3_llsc = FALSE; | |
14962 | break; | |
14963 | ||
c67a084a NC |
14964 | case OPTION_FIX_LOONGSON2F_JUMP: |
14965 | mips_fix_loongson2f_jump = TRUE; | |
14966 | break; | |
14967 | ||
14968 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14969 | mips_fix_loongson2f_jump = FALSE; | |
14970 | break; | |
14971 | ||
14972 | case OPTION_FIX_LOONGSON2F_NOP: | |
14973 | mips_fix_loongson2f_nop = TRUE; | |
14974 | break; | |
14975 | ||
14976 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14977 | mips_fix_loongson2f_nop = FALSE; | |
14978 | break; | |
14979 | ||
d766e8ec RS |
14980 | case OPTION_FIX_VR4120: |
14981 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14982 | break; |
14983 | ||
d766e8ec RS |
14984 | case OPTION_NO_FIX_VR4120: |
14985 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14986 | break; |
14987 | ||
7d8e00cf RS |
14988 | case OPTION_FIX_VR4130: |
14989 | mips_fix_vr4130 = 1; | |
14990 | break; | |
14991 | ||
14992 | case OPTION_NO_FIX_VR4130: | |
14993 | mips_fix_vr4130 = 0; | |
14994 | break; | |
14995 | ||
d954098f DD |
14996 | case OPTION_FIX_CN63XXP1: |
14997 | mips_fix_cn63xxp1 = TRUE; | |
14998 | break; | |
14999 | ||
15000 | case OPTION_NO_FIX_CN63XXP1: | |
15001 | mips_fix_cn63xxp1 = FALSE; | |
15002 | break; | |
15003 | ||
27c634e0 FN |
15004 | case OPTION_FIX_R5900: |
15005 | mips_fix_r5900 = TRUE; | |
15006 | mips_fix_r5900_explicit = TRUE; | |
15007 | break; | |
15008 | ||
15009 | case OPTION_NO_FIX_R5900: | |
15010 | mips_fix_r5900 = FALSE; | |
15011 | mips_fix_r5900_explicit = TRUE; | |
15012 | break; | |
15013 | ||
4a6a3df4 AO |
15014 | case OPTION_RELAX_BRANCH: |
15015 | mips_relax_branch = 1; | |
15016 | break; | |
15017 | ||
15018 | case OPTION_NO_RELAX_BRANCH: | |
15019 | mips_relax_branch = 0; | |
15020 | break; | |
15021 | ||
8b10b0b3 MR |
15022 | case OPTION_IGNORE_BRANCH_ISA: |
15023 | mips_ignore_branch_isa = TRUE; | |
15024 | break; | |
15025 | ||
15026 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
15027 | mips_ignore_branch_isa = FALSE; | |
15028 | break; | |
15029 | ||
833794fc | 15030 | case OPTION_INSN32: |
919731af | 15031 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
15032 | break; |
15033 | ||
15034 | case OPTION_NO_INSN32: | |
919731af | 15035 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
15036 | break; |
15037 | ||
aa6975fb ILT |
15038 | case OPTION_MSHARED: |
15039 | mips_in_shared = TRUE; | |
15040 | break; | |
15041 | ||
15042 | case OPTION_MNO_SHARED: | |
15043 | mips_in_shared = FALSE; | |
15044 | break; | |
15045 | ||
aed1a261 | 15046 | case OPTION_MSYM32: |
919731af | 15047 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
15048 | break; |
15049 | ||
15050 | case OPTION_MNO_SYM32: | |
919731af | 15051 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
15052 | break; |
15053 | ||
252b5132 RH |
15054 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15055 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15056 | intended to be compatible with Irix 5. */ | |
15057 | case OPTION_CALL_SHARED: | |
252b5132 | 15058 | mips_pic = SVR4_PIC; |
143d77c5 | 15059 | mips_abicalls = TRUE; |
252b5132 RH |
15060 | break; |
15061 | ||
861fb55a | 15062 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
15063 | mips_pic = NO_PIC; |
15064 | mips_abicalls = TRUE; | |
15065 | break; | |
15066 | ||
252b5132 | 15067 | case OPTION_NON_SHARED: |
252b5132 | 15068 | mips_pic = NO_PIC; |
143d77c5 | 15069 | mips_abicalls = FALSE; |
252b5132 RH |
15070 | break; |
15071 | ||
44075ae2 TS |
15072 | /* The -xgot option tells the assembler to use 32 bit offsets |
15073 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15074 | compatibility. */ |
15075 | case OPTION_XGOT: | |
15076 | mips_big_got = 1; | |
15077 | break; | |
15078 | ||
15079 | case 'G': | |
6caf9ef4 TS |
15080 | g_switch_value = atoi (arg); |
15081 | g_switch_seen = 1; | |
252b5132 RH |
15082 | break; |
15083 | ||
34ba82a8 TS |
15084 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15085 | and -mabi=64. */ | |
252b5132 | 15086 | case OPTION_32: |
f3ded42a | 15087 | mips_abi = O32_ABI; |
252b5132 RH |
15088 | break; |
15089 | ||
e013f690 | 15090 | case OPTION_N32: |
316f5878 | 15091 | mips_abi = N32_ABI; |
e013f690 | 15092 | break; |
252b5132 | 15093 | |
e013f690 | 15094 | case OPTION_64: |
316f5878 | 15095 | mips_abi = N64_ABI; |
f43abd2b | 15096 | if (!support_64bit_objects()) |
1661c76c | 15097 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
15098 | break; |
15099 | ||
c97ef257 | 15100 | case OPTION_GP32: |
bad1aba3 | 15101 | file_mips_opts.gp = 32; |
c97ef257 AH |
15102 | break; |
15103 | ||
15104 | case OPTION_GP64: | |
bad1aba3 | 15105 | file_mips_opts.gp = 64; |
c97ef257 | 15106 | break; |
252b5132 | 15107 | |
ca4e0257 | 15108 | case OPTION_FP32: |
0b35dfee | 15109 | file_mips_opts.fp = 32; |
316f5878 RS |
15110 | break; |
15111 | ||
351cdf24 MF |
15112 | case OPTION_FPXX: |
15113 | file_mips_opts.fp = 0; | |
15114 | break; | |
15115 | ||
316f5878 | 15116 | case OPTION_FP64: |
0b35dfee | 15117 | file_mips_opts.fp = 64; |
ca4e0257 RS |
15118 | break; |
15119 | ||
351cdf24 MF |
15120 | case OPTION_ODD_SPREG: |
15121 | file_mips_opts.oddspreg = 1; | |
15122 | break; | |
15123 | ||
15124 | case OPTION_NO_ODD_SPREG: | |
15125 | file_mips_opts.oddspreg = 0; | |
15126 | break; | |
15127 | ||
037b32b9 | 15128 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 15129 | file_mips_opts.single_float = 1; |
037b32b9 AN |
15130 | break; |
15131 | ||
15132 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 15133 | file_mips_opts.single_float = 0; |
037b32b9 AN |
15134 | break; |
15135 | ||
15136 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 15137 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
15138 | break; |
15139 | ||
15140 | case OPTION_HARD_FLOAT: | |
0b35dfee | 15141 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
15142 | break; |
15143 | ||
252b5132 | 15144 | case OPTION_MABI: |
e013f690 | 15145 | if (strcmp (arg, "32") == 0) |
316f5878 | 15146 | mips_abi = O32_ABI; |
e013f690 | 15147 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15148 | mips_abi = O64_ABI; |
e013f690 | 15149 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15150 | mips_abi = N32_ABI; |
e013f690 TS |
15151 | else if (strcmp (arg, "64") == 0) |
15152 | { | |
316f5878 | 15153 | mips_abi = N64_ABI; |
e013f690 | 15154 | if (! support_64bit_objects()) |
1661c76c | 15155 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
15156 | "format")); |
15157 | } | |
15158 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15159 | mips_abi = EABI_ABI; |
e013f690 | 15160 | else |
da0e507f TS |
15161 | { |
15162 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15163 | return 0; | |
15164 | } | |
252b5132 RH |
15165 | break; |
15166 | ||
6b76fefe | 15167 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15168 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15169 | break; |
15170 | ||
9ee72ff1 | 15171 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15172 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15173 | break; |
15174 | ||
ecb4347a | 15175 | case OPTION_MDEBUG: |
b34976b6 | 15176 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15177 | break; |
15178 | ||
15179 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15180 | mips_flag_mdebug = FALSE; |
ecb4347a | 15181 | break; |
dcd410fe RO |
15182 | |
15183 | case OPTION_PDR: | |
15184 | mips_flag_pdr = TRUE; | |
15185 | break; | |
15186 | ||
15187 | case OPTION_NO_PDR: | |
15188 | mips_flag_pdr = FALSE; | |
15189 | break; | |
0a44bf69 RS |
15190 | |
15191 | case OPTION_MVXWORKS_PIC: | |
15192 | mips_pic = VXWORKS_PIC; | |
15193 | break; | |
ecb4347a | 15194 | |
ba92f887 MR |
15195 | case OPTION_NAN: |
15196 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 15197 | mips_nan2008 = 1; |
ba92f887 | 15198 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 15199 | mips_nan2008 = 0; |
ba92f887 MR |
15200 | else |
15201 | { | |
1661c76c | 15202 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
15203 | return 0; |
15204 | } | |
15205 | break; | |
15206 | ||
252b5132 RH |
15207 | default: |
15208 | return 0; | |
15209 | } | |
15210 | ||
c67a084a NC |
15211 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15212 | ||
252b5132 RH |
15213 | return 1; |
15214 | } | |
316f5878 | 15215 | \f |
919731af | 15216 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 15217 | |
316f5878 | 15218 | static void |
17a2f251 | 15219 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15220 | { |
15221 | if (info != 0) | |
fef14a42 | 15222 | mips_tune = info->cpu; |
316f5878 | 15223 | } |
80cc45a5 | 15224 | |
34ba82a8 | 15225 | |
252b5132 | 15226 | void |
17a2f251 | 15227 | mips_after_parse_args (void) |
e9670677 | 15228 | { |
fef14a42 TS |
15229 | const struct mips_cpu_info *arch_info = 0; |
15230 | const struct mips_cpu_info *tune_info = 0; | |
15231 | ||
6f2117ba | 15232 | /* GP relative stuff not working for PE. */ |
6caf9ef4 | 15233 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15234 | { |
6caf9ef4 | 15235 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 15236 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
15237 | g_switch_value = 0; |
15238 | } | |
15239 | ||
cac012d6 AO |
15240 | if (mips_abi == NO_ABI) |
15241 | mips_abi = MIPS_DEFAULT_ABI; | |
15242 | ||
919731af | 15243 | /* The following code determines the architecture. |
22923709 RS |
15244 | Similar code was added to GCC 3.3 (see override_options() in |
15245 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15246 | as much as possible. */ | |
e9670677 | 15247 | |
316f5878 | 15248 | if (mips_arch_string != 0) |
fef14a42 | 15249 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15250 | |
0b35dfee | 15251 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 15252 | { |
0b35dfee | 15253 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 15254 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15255 | the -march selection (if any). */ |
fef14a42 | 15256 | if (arch_info != 0) |
e9670677 | 15257 | { |
316f5878 RS |
15258 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15259 | There's no harm in specifying both as long as the ISA levels | |
15260 | are the same. */ | |
0b35dfee | 15261 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
15262 | as_bad (_("-%s conflicts with the other architecture options," |
15263 | " which imply -%s"), | |
0b35dfee | 15264 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 15265 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15266 | } |
316f5878 | 15267 | else |
0b35dfee | 15268 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
15269 | } |
15270 | ||
fef14a42 | 15271 | if (arch_info == 0) |
95bfe26e MF |
15272 | { |
15273 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15274 | gas_assert (arch_info); | |
15275 | } | |
e9670677 | 15276 | |
fef14a42 | 15277 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15278 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15279 | arch_info->name); |
15280 | ||
919731af | 15281 | file_mips_opts.arch = arch_info->cpu; |
15282 | file_mips_opts.isa = arch_info->isa; | |
3315614d | 15283 | file_mips_opts.init_ase = arch_info->ase; |
919731af | 15284 | |
41cee089 FS |
15285 | /* The EVA Extension has instructions which are only valid when the R6 ISA |
15286 | is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are | |
15287 | present. */ | |
15288 | if (((file_mips_opts.ase & ASE_EVA) != 0) && ISA_IS_R6 (file_mips_opts.isa)) | |
15289 | file_mips_opts.ase |= ASE_EVA_R6; | |
15290 | ||
919731af | 15291 | /* Set up initial mips_opts state. */ |
15292 | mips_opts = file_mips_opts; | |
15293 | ||
27c634e0 FN |
15294 | /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */ |
15295 | if (!mips_fix_r5900_explicit) | |
15296 | mips_fix_r5900 = file_mips_opts.arch == CPU_R5900; | |
15297 | ||
919731af | 15298 | /* The register size inference code is now placed in |
15299 | file_mips_check_options. */ | |
fef14a42 | 15300 | |
0b35dfee | 15301 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
15302 | processor. */ | |
fef14a42 TS |
15303 | if (mips_tune_string != 0) |
15304 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15305 | |
fef14a42 TS |
15306 | if (tune_info == 0) |
15307 | mips_set_tune (arch_info); | |
15308 | else | |
15309 | mips_set_tune (tune_info); | |
e9670677 | 15310 | |
ecb4347a | 15311 | if (mips_flag_mdebug < 0) |
e8044f35 | 15312 | mips_flag_mdebug = 0; |
e9670677 MR |
15313 | } |
15314 | \f | |
15315 | void | |
17a2f251 | 15316 | mips_init_after_args (void) |
252b5132 | 15317 | { |
6f2117ba | 15318 | /* Initialize opcodes. */ |
252b5132 | 15319 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; |
beae10d5 | 15320 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15321 | } |
15322 | ||
15323 | long | |
17a2f251 | 15324 | md_pcrel_from (fixS *fixP) |
252b5132 | 15325 | { |
a7ebbfdf | 15326 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
6f2117ba | 15327 | |
a7ebbfdf TS |
15328 | switch (fixP->fx_r_type) |
15329 | { | |
df58fc94 RS |
15330 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15331 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15332 | /* Return the address of the delay slot. */ | |
15333 | return addr + 2; | |
15334 | ||
15335 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15336 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 15337 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 15338 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
15339 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15340 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
15341 | case BFD_RELOC_MIPS_JMP: |
15342 | /* Return the address of the delay slot. */ | |
15343 | return addr + 4; | |
df58fc94 | 15344 | |
51f6035b MR |
15345 | case BFD_RELOC_MIPS_18_PCREL_S3: |
15346 | /* Return the aligned address of the doubleword containing | |
15347 | the instruction. */ | |
15348 | return addr & ~7; | |
15349 | ||
a7ebbfdf TS |
15350 | default: |
15351 | return addr; | |
15352 | } | |
252b5132 RH |
15353 | } |
15354 | ||
252b5132 RH |
15355 | /* This is called before the symbol table is processed. In order to |
15356 | work with gcc when using mips-tfile, we must keep all local labels. | |
15357 | However, in other cases, we want to discard them. If we were | |
15358 | called with -g, but we didn't see any debugging information, it may | |
15359 | mean that gcc is smuggling debugging information through to | |
15360 | mips-tfile, in which case we must generate all local labels. */ | |
15361 | ||
15362 | void | |
17a2f251 | 15363 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15364 | { |
15365 | #ifndef NO_ECOFF_DEBUGGING | |
15366 | if (ECOFF_DEBUGGING | |
15367 | && mips_debug != 0 | |
15368 | && ! ecoff_debugging_seen) | |
15369 | flag_keep_locals = 1; | |
15370 | #endif | |
15371 | } | |
15372 | ||
3b91255e | 15373 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15374 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15375 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15376 | relocation operators. | |
15377 | ||
15378 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15379 | expression if: | |
15380 | ||
15381 | (a) it refers to the same symbol; and | |
15382 | (b) the offset applied in the %lo() expression is no lower than | |
15383 | the offset applied in the %got() or %hi(). | |
15384 | ||
15385 | (b) allows us to cope with code like: | |
15386 | ||
15387 | lui $4,%hi(foo) | |
15388 | lh $4,%lo(foo+2)($4) | |
15389 | ||
15390 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15391 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15392 | the high 16 bits. | |
15393 | ||
15394 | When several %lo()s match a particular %got() or %hi(), we use the | |
15395 | following rules to distinguish them: | |
15396 | ||
15397 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15398 | higher offsets. | |
15399 | ||
15400 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15401 | that already have a matching %got() or %hi(). | |
15402 | ||
15403 | (3) later %lo()s are better than earlier %lo()s. | |
15404 | ||
15405 | These rules are applied in order. | |
15406 | ||
15407 | (1) means, among other things, that %lo()s with identical offsets are | |
15408 | chosen if they exist. | |
15409 | ||
15410 | (2) means that we won't associate several high-part relocations with | |
15411 | the same low-part relocation unless there's no alternative. Having | |
15412 | several high parts for the same low part is a GNU extension; this rule | |
15413 | allows careful users to avoid it. | |
15414 | ||
15415 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15416 | with the last high-part relocation being at the front of the list. | |
15417 | It therefore makes sense to choose the last matching low-part | |
15418 | relocation, all other things being equal. It's also easier | |
15419 | to code that way. */ | |
252b5132 RH |
15420 | |
15421 | void | |
17a2f251 | 15422 | mips_frob_file (void) |
252b5132 RH |
15423 | { |
15424 | struct mips_hi_fixup *l; | |
35903be0 | 15425 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15426 | |
15427 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15428 | { | |
15429 | segment_info_type *seginfo; | |
3b91255e RS |
15430 | bfd_boolean matched_lo_p; |
15431 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15432 | |
9c2799c2 | 15433 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15434 | |
5919d012 | 15435 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15436 | there isn't supposed to be a matching LO. Ignore %gots against |
15437 | constants; we'll report an error for those later. */ | |
738e5348 | 15438 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 15439 | && !(l->fixp->fx_addsy |
9e009953 | 15440 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
15441 | continue; |
15442 | ||
15443 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15444 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15445 | continue; |
15446 | ||
252b5132 | 15447 | seginfo = seg_info (l->seg); |
252b5132 | 15448 | |
3b91255e RS |
15449 | /* Set HI_POS to the position of this relocation in the chain. |
15450 | Set LO_POS to the position of the chosen low-part relocation. | |
15451 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15452 | relocation that matches an immediately-preceding high-part | |
15453 | relocation. */ | |
15454 | hi_pos = NULL; | |
15455 | lo_pos = NULL; | |
15456 | matched_lo_p = FALSE; | |
738e5348 | 15457 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15458 | |
3b91255e RS |
15459 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15460 | { | |
15461 | if (*pos == l->fixp) | |
15462 | hi_pos = pos; | |
15463 | ||
35903be0 | 15464 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15465 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15466 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15467 | && (lo_pos == NULL | |
15468 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15469 | || (!matched_lo_p | |
15470 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15471 | lo_pos = pos; | |
15472 | ||
15473 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15474 | && fixup_has_matching_lo_p (*pos)); | |
15475 | } | |
15476 | ||
15477 | /* If we found a match, remove the high-part relocation from its | |
15478 | current position and insert it before the low-part relocation. | |
15479 | Make the offsets match so that fixup_has_matching_lo_p() | |
15480 | will return true. | |
15481 | ||
15482 | We don't warn about unmatched high-part relocations since some | |
15483 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15484 | instructions. */ | |
15485 | if (lo_pos != NULL) | |
15486 | { | |
15487 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15488 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15489 | { |
3b91255e RS |
15490 | *hi_pos = l->fixp->fx_next; |
15491 | l->fixp->fx_next = *lo_pos; | |
15492 | *lo_pos = l->fixp; | |
252b5132 | 15493 | } |
252b5132 RH |
15494 | } |
15495 | } | |
15496 | } | |
15497 | ||
252b5132 | 15498 | int |
17a2f251 | 15499 | mips_force_relocation (fixS *fixp) |
252b5132 | 15500 | { |
ae6063d4 | 15501 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15502 | return 1; |
15503 | ||
df58fc94 RS |
15504 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15505 | so that the linker relaxation can update targets. */ | |
15506 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15507 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15508 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15509 | return 1; | |
15510 | ||
5caa2b07 MR |
15511 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15512 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15513 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15514 | and BAL to JALX conversion by the linker. */ | |
15515 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15516 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15517 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15518 | && fixp->fx_addsy | |
15519 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15520 | return 1; | |
15521 | ||
7361da2c | 15522 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15523 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15524 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15525 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15526 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15527 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15528 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15529 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15530 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15531 | return 1; | |
15532 | ||
3e722fb5 | 15533 | return 0; |
252b5132 RH |
15534 | } |
15535 | ||
b416ba9b MR |
15536 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15537 | ||
15538 | bfd_boolean | |
15539 | mips_force_relocation_abs (fixS *fixp) | |
15540 | { | |
15541 | if (generic_force_reloc (fixp)) | |
15542 | return TRUE; | |
15543 | ||
15544 | /* These relocations do not have enough bits in the in-place addend | |
15545 | to hold an arbitrary absolute section's offset. */ | |
15546 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15547 | return TRUE; | |
15548 | ||
15549 | return FALSE; | |
15550 | } | |
15551 | ||
b886a2ab RS |
15552 | /* Read the instruction associated with RELOC from BUF. */ |
15553 | ||
15554 | static unsigned int | |
15555 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15556 | { | |
15557 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15558 | return read_compressed_insn (buf, 4); | |
15559 | else | |
15560 | return read_insn (buf); | |
15561 | } | |
15562 | ||
15563 | /* Write instruction INSN to BUF, given that it has been relocated | |
15564 | by RELOC. */ | |
15565 | ||
15566 | static void | |
15567 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15568 | unsigned long insn) | |
15569 | { | |
15570 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15571 | write_compressed_insn (buf, insn, 4); | |
15572 | else | |
15573 | write_insn (buf, insn); | |
15574 | } | |
15575 | ||
9d862524 MR |
15576 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15577 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15578 | ||
15579 | static bfd_boolean | |
15580 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15581 | { | |
15582 | unsigned long opcode; | |
15583 | int other; | |
15584 | char *buf; | |
15585 | ||
15586 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15587 | return FALSE; | |
15588 | ||
15589 | other = S_GET_OTHER (fixP->fx_addsy); | |
15590 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15591 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15592 | switch (fixP->fx_r_type) | |
15593 | { | |
15594 | case BFD_RELOC_MIPS_JMP: | |
15595 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15596 | case BFD_RELOC_MICROMIPS_JMP: | |
15597 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15598 | default: | |
15599 | return FALSE; | |
15600 | } | |
15601 | } | |
15602 | ||
15603 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15604 | jump to a symbol in the same ISA mode. */ | |
15605 | ||
15606 | static bfd_boolean | |
15607 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15608 | { | |
15609 | unsigned long opcode; | |
15610 | int other; | |
15611 | char *buf; | |
15612 | ||
15613 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15614 | return FALSE; | |
15615 | ||
15616 | other = S_GET_OTHER (fixP->fx_addsy); | |
15617 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15618 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15619 | switch (fixP->fx_r_type) | |
15620 | { | |
15621 | case BFD_RELOC_MIPS_JMP: | |
15622 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15623 | case BFD_RELOC_MIPS16_JMP: | |
15624 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15625 | case BFD_RELOC_MICROMIPS_JMP: | |
15626 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15627 | default: | |
15628 | return FALSE; | |
15629 | } | |
15630 | } | |
15631 | ||
15632 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15633 | to a symbol whose value plus addend is not aligned according to the | |
15634 | ultimate (after linker relaxation) jump instruction's immediate field | |
15635 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15636 | regular MIPS code, to (1 << 2). */ | |
15637 | ||
15638 | static bfd_boolean | |
15639 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15640 | { | |
15641 | bfd_boolean micro_to_mips_p; | |
15642 | valueT val; | |
15643 | int other; | |
15644 | ||
15645 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15646 | return FALSE; | |
15647 | ||
15648 | other = S_GET_OTHER (fixP->fx_addsy); | |
15649 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15650 | val += fixP->fx_offset; | |
15651 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15652 | && !ELF_ST_IS_MICROMIPS (other)); | |
15653 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15654 | != ELF_ST_IS_COMPRESSED (other)); | |
15655 | } | |
15656 | ||
15657 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15658 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15659 | symbols check the ISA bit instead. |
15660 | ||
15661 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15662 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15663 | MIPS symbols and associated with BAL instructions as these instructions | |
de194d85 | 15664 | may be converted to JALX by the linker. */ |
9d862524 MR |
15665 | |
15666 | static bfd_boolean | |
15667 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15668 | { | |
15669 | bfd_boolean absolute_p; | |
15670 | unsigned long opcode; | |
15671 | asection *symsec; | |
15672 | valueT val; | |
15673 | int other; | |
15674 | char *buf; | |
15675 | ||
8b10b0b3 MR |
15676 | if (mips_ignore_branch_isa) |
15677 | return FALSE; | |
15678 | ||
9d862524 MR |
15679 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15680 | return FALSE; | |
15681 | ||
15682 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15683 | absolute_p = bfd_is_abs_section (symsec); | |
15684 | ||
15685 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15686 | other = S_GET_OTHER (fixP->fx_addsy); | |
15687 | ||
15688 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15689 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15690 | switch (fixP->fx_r_type) | |
15691 | { | |
15692 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15693 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15694 | && opcode != 0x0411); | |
15695 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15696 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15697 | && opcode != 0x4060); | |
9d862524 MR |
15698 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15699 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15700 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15701 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15702 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15703 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15704 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15705 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15706 | default: | |
15707 | abort (); | |
15708 | } | |
15709 | } | |
15710 | ||
15711 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15712 | branch instruction pointed to by FIXP is not aligned according to the | |
15713 | branch instruction's immediate field requirement. We need the addend | |
15714 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15715 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15716 | won't be set in the symbol's value then. */ | |
15717 | ||
15718 | static bfd_boolean | |
15719 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15720 | { | |
15721 | bfd_boolean absolute_p; | |
15722 | asection *symsec; | |
15723 | valueT isa_bit; | |
15724 | valueT val; | |
15725 | valueT off; | |
15726 | int other; | |
15727 | ||
15728 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15729 | return FALSE; | |
15730 | ||
15731 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15732 | absolute_p = bfd_is_abs_section (symsec); | |
15733 | ||
15734 | val = S_GET_VALUE (fixP->fx_addsy); | |
15735 | other = S_GET_OTHER (fixP->fx_addsy); | |
15736 | off = fixP->fx_offset; | |
15737 | ||
15738 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15739 | val |= ELF_ST_IS_COMPRESSED (other); | |
15740 | val += off; | |
15741 | return (val & 0x3) != isa_bit; | |
15742 | } | |
15743 | ||
52031738 FS |
15744 | /* Calculate the relocation target by masking off ISA mode bit before |
15745 | combining symbol and addend. */ | |
15746 | ||
15747 | static valueT | |
15748 | fix_bad_misaligned_address (fixS *fixP) | |
15749 | { | |
15750 | valueT val; | |
15751 | valueT off; | |
15752 | unsigned isa_mode; | |
15753 | gas_assert (fixP != NULL && fixP->fx_addsy != NULL); | |
15754 | val = S_GET_VALUE (fixP->fx_addsy); | |
15755 | off = fixP->fx_offset; | |
15756 | isa_mode = (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP->fx_addsy)) | |
15757 | ? 1 : 0); | |
15758 | ||
15759 | return ((val & ~isa_mode) + off); | |
15760 | } | |
15761 | ||
9d862524 MR |
15762 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP |
15763 | and its calculated value VAL. */ | |
15764 | ||
15765 | static void | |
15766 | fix_validate_branch (fixS *fixP, valueT val) | |
15767 | { | |
15768 | if (fixP->fx_done && (val & 0x3) != 0) | |
15769 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15770 | _("branch to misaligned address (0x%lx)"), | |
15771 | (long) (val + md_pcrel_from (fixP))); | |
15772 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15773 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15774 | _("branch to a symbol in another ISA mode")); | |
15775 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15776 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15777 | _("branch to misaligned address (0x%lx)"), | |
52031738 | 15778 | (long) fix_bad_misaligned_address (fixP)); |
9d862524 MR |
15779 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) |
15780 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15781 | _("cannot encode misaligned addend " | |
15782 | "in the relocatable field (0x%lx)"), | |
15783 | (long) fixP->fx_offset); | |
15784 | } | |
15785 | ||
252b5132 RH |
15786 | /* Apply a fixup to the object file. */ |
15787 | ||
94f592af | 15788 | void |
55cf6793 | 15789 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15790 | { |
4d68580a | 15791 | char *buf; |
b886a2ab | 15792 | unsigned long insn; |
a7ebbfdf | 15793 | reloc_howto_type *howto; |
252b5132 | 15794 | |
d56a8dda RS |
15795 | if (fixP->fx_pcrel) |
15796 | switch (fixP->fx_r_type) | |
15797 | { | |
15798 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15799 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15800 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15801 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15802 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15803 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15804 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15805 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15806 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15807 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15808 | case BFD_RELOC_HI16_S_PCREL: | |
15809 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15810 | break; |
15811 | ||
15812 | case BFD_RELOC_32: | |
15813 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15814 | break; | |
15815 | ||
15816 | default: | |
15817 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15818 | _("PC-relative reference to a different section")); | |
15819 | break; | |
15820 | } | |
15821 | ||
15822 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15823 | that have no MIPS ELF equivalent. */ | |
15824 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15825 | { | |
15826 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15827 | if (!howto) | |
15828 | return; | |
15829 | } | |
65551fa4 | 15830 | |
df58fc94 RS |
15831 | gas_assert (fixP->fx_size == 2 |
15832 | || fixP->fx_size == 4 | |
d56a8dda | 15833 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15834 | || fixP->fx_r_type == BFD_RELOC_16 |
15835 | || fixP->fx_r_type == BFD_RELOC_64 | |
15836 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15837 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15838 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15839 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15840 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15841 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15842 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15843 | |
4d68580a | 15844 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15845 | |
b1dca8ee RS |
15846 | /* Don't treat parts of a composite relocation as done. There are two |
15847 | reasons for this: | |
15848 | ||
15849 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15850 | should nevertheless be emitted if the first part is. | |
15851 | ||
15852 | (2) In normal usage, composite relocations are never assembly-time | |
15853 | constants. The easiest way of dealing with the pathological | |
15854 | exceptions is to generate a relocation against STN_UNDEF and | |
15855 | leave everything up to the linker. */ | |
3994f87e | 15856 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15857 | fixP->fx_done = 1; |
15858 | ||
15859 | switch (fixP->fx_r_type) | |
15860 | { | |
3f98094e DJ |
15861 | case BFD_RELOC_MIPS_TLS_GD: |
15862 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15863 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15864 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15865 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15866 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15867 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15868 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15869 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15870 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15871 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15872 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15873 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15874 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15875 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15876 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15877 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15878 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15879 | case BFD_RELOC_MIPS16_TLS_GD: |
15880 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15881 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15882 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15883 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15884 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15885 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15886 | if (fixP->fx_addsy) |
15887 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15888 | else | |
15889 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15890 | _("TLS relocation against a constant")); | |
15891 | break; | |
3f98094e | 15892 | |
252b5132 | 15893 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15894 | case BFD_RELOC_MIPS16_JMP: |
15895 | case BFD_RELOC_MICROMIPS_JMP: | |
15896 | { | |
15897 | int shift; | |
15898 | ||
15899 | gas_assert (!fixP->fx_done); | |
15900 | ||
15901 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15902 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15903 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15904 | shift = 1; | |
15905 | else | |
15906 | shift = 2; | |
15907 | ||
15908 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15909 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15910 | _("jump to a symbol in another ISA mode")); | |
15911 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15912 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15913 | _("JALX to a symbol in the same ISA mode")); | |
15914 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15915 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15916 | _("jump to misaligned address (0x%lx)"), | |
52031738 | 15917 | (long) fix_bad_misaligned_address (fixP)); |
9d862524 MR |
15918 | else if (HAVE_IN_PLACE_ADDENDS |
15919 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15920 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15921 | _("cannot encode misaligned addend " | |
15922 | "in the relocatable field (0x%lx)"), | |
15923 | (long) fixP->fx_offset); | |
15924 | } | |
15925 | /* Fall through. */ | |
15926 | ||
e369bcce TS |
15927 | case BFD_RELOC_MIPS_SHIFT5: |
15928 | case BFD_RELOC_MIPS_SHIFT6: | |
15929 | case BFD_RELOC_MIPS_GOT_DISP: | |
15930 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15931 | case BFD_RELOC_MIPS_GOT_OFST: | |
15932 | case BFD_RELOC_MIPS_SUB: | |
15933 | case BFD_RELOC_MIPS_INSERT_A: | |
15934 | case BFD_RELOC_MIPS_INSERT_B: | |
15935 | case BFD_RELOC_MIPS_DELETE: | |
15936 | case BFD_RELOC_MIPS_HIGHEST: | |
15937 | case BFD_RELOC_MIPS_HIGHER: | |
15938 | case BFD_RELOC_MIPS_SCN_DISP: | |
15939 | case BFD_RELOC_MIPS_REL16: | |
15940 | case BFD_RELOC_MIPS_RELGOT: | |
15941 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15942 | case BFD_RELOC_HI16: |
15943 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15944 | case BFD_RELOC_LO16: |
cdf6fd85 | 15945 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15946 | case BFD_RELOC_MIPS_LITERAL: |
15947 | case BFD_RELOC_MIPS_CALL16: | |
15948 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15949 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15950 | case BFD_RELOC_MIPS_GOT_HI16: |
15951 | case BFD_RELOC_MIPS_GOT_LO16: | |
15952 | case BFD_RELOC_MIPS_CALL_HI16: | |
15953 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15954 | case BFD_RELOC_HI16_S_PCREL: |
15955 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15956 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15957 | case BFD_RELOC_MIPS16_GOT16: |
15958 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15959 | case BFD_RELOC_MIPS16_HI16: |
15960 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15961 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15962 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15963 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15964 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15965 | case BFD_RELOC_MICROMIPS_SUB: | |
15966 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15967 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15968 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15969 | case BFD_RELOC_MICROMIPS_JALR: | |
15970 | case BFD_RELOC_MICROMIPS_HI16: | |
15971 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15972 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15973 | case BFD_RELOC_MICROMIPS_GPREL16: |
15974 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15975 | case BFD_RELOC_MICROMIPS_CALL16: | |
15976 | case BFD_RELOC_MICROMIPS_GOT16: | |
15977 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15978 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15979 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15980 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15981 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15982 | if (fixP->fx_done) |
15983 | { | |
15984 | offsetT value; | |
15985 | ||
15986 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15987 | { | |
15988 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15989 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15990 | insn |= mips16_immed_extend (value, 16); | |
15991 | else | |
15992 | insn |= (value & 0xffff); | |
15993 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15994 | } | |
15995 | else | |
15996 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15997 | _("unsupported constant in relocation")); |
b886a2ab | 15998 | } |
252b5132 RH |
15999 | break; |
16000 | ||
252b5132 RH |
16001 | case BFD_RELOC_64: |
16002 | /* This is handled like BFD_RELOC_32, but we output a sign | |
16003 | extended value if we are only 32 bits. */ | |
3e722fb5 | 16004 | if (fixP->fx_done) |
252b5132 RH |
16005 | { |
16006 | if (8 <= sizeof (valueT)) | |
4d68580a | 16007 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
16008 | else |
16009 | { | |
a7ebbfdf | 16010 | valueT hiv; |
252b5132 | 16011 | |
a7ebbfdf | 16012 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
16013 | hiv = 0xffffffff; |
16014 | else | |
16015 | hiv = 0; | |
4d68580a RS |
16016 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
16017 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
16018 | } |
16019 | } | |
16020 | break; | |
16021 | ||
056350c6 | 16022 | case BFD_RELOC_RVA: |
252b5132 | 16023 | case BFD_RELOC_32: |
b47468a6 | 16024 | case BFD_RELOC_32_PCREL: |
252b5132 | 16025 | case BFD_RELOC_16: |
d56a8dda | 16026 | case BFD_RELOC_8: |
252b5132 | 16027 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
16028 | value now. This can happen if we have a .word which is not |
16029 | resolved when it appears but is later defined. */ | |
252b5132 | 16030 | if (fixP->fx_done) |
4d68580a | 16031 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
16032 | break; |
16033 | ||
7361da2c | 16034 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 16035 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
16036 | if (!fixP->fx_done) |
16037 | break; | |
16038 | ||
16039 | if (*valP + 0x400000 <= 0x7fffff) | |
16040 | { | |
16041 | insn = read_insn (buf); | |
16042 | insn |= (*valP >> 2) & 0x1fffff; | |
16043 | write_insn (buf, insn); | |
16044 | } | |
16045 | else | |
16046 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16047 | _("branch out of range")); | |
16048 | break; | |
16049 | ||
7361da2c | 16050 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 16051 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
16052 | if (!fixP->fx_done) |
16053 | break; | |
7361da2c | 16054 | |
41947d9e MR |
16055 | if (*valP + 0x8000000 <= 0xfffffff) |
16056 | { | |
16057 | insn = read_insn (buf); | |
16058 | insn |= (*valP >> 2) & 0x3ffffff; | |
16059 | write_insn (buf, insn); | |
16060 | } | |
16061 | else | |
16062 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16063 | _("branch out of range")); | |
7361da2c AB |
16064 | break; |
16065 | ||
16066 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 16067 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 16068 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
16069 | _("PC-relative access using misaligned symbol (%lx)"), |
16070 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
16071 | if ((fixP->fx_offset & 0x7) != 0) | |
16072 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16073 | _("PC-relative access using misaligned offset (%lx)"), | |
16074 | (long) fixP->fx_offset); | |
41947d9e MR |
16075 | if (!fixP->fx_done) |
16076 | break; | |
7361da2c | 16077 | |
41947d9e MR |
16078 | if (*valP + 0x100000 <= 0x1fffff) |
16079 | { | |
16080 | insn = read_insn (buf); | |
16081 | insn |= (*valP >> 3) & 0x3ffff; | |
16082 | write_insn (buf, insn); | |
16083 | } | |
16084 | else | |
16085 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16086 | _("PC-relative access out of range")); | |
7361da2c AB |
16087 | break; |
16088 | ||
16089 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
16090 | if ((*valP & 0x3) != 0) | |
16091 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16092 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 16093 | (long) *valP); |
41947d9e MR |
16094 | if (!fixP->fx_done) |
16095 | break; | |
7361da2c | 16096 | |
41947d9e MR |
16097 | if (*valP + 0x100000 <= 0x1fffff) |
16098 | { | |
16099 | insn = read_insn (buf); | |
16100 | insn |= (*valP >> 2) & 0x7ffff; | |
16101 | write_insn (buf, insn); | |
16102 | } | |
16103 | else | |
16104 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16105 | _("PC-relative access out of range")); | |
7361da2c AB |
16106 | break; |
16107 | ||
252b5132 | 16108 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 16109 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 16110 | |
54f4ddb3 TS |
16111 | /* We need to save the bits in the instruction since fixup_segment() |
16112 | might be deleting the relocation entry (i.e., a branch within | |
16113 | the current segment). */ | |
a7ebbfdf | 16114 | if (! fixP->fx_done) |
bb2d6cd7 | 16115 | break; |
252b5132 | 16116 | |
54f4ddb3 | 16117 | /* Update old instruction data. */ |
4d68580a | 16118 | insn = read_insn (buf); |
252b5132 | 16119 | |
a7ebbfdf TS |
16120 | if (*valP + 0x20000 <= 0x3ffff) |
16121 | { | |
16122 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 16123 | write_insn (buf, insn); |
a7ebbfdf | 16124 | } |
ce8ad872 | 16125 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
16126 | && fixP->fx_done |
16127 | && fixP->fx_frag->fr_address >= text_section->vma | |
16128 | && (fixP->fx_frag->fr_address | |
fd361982 | 16129 | < text_section->vma + bfd_section_size (text_section)) |
a7ebbfdf TS |
16130 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
16131 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
16132 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
16133 | { |
16134 | /* The branch offset is too large. If this is an | |
16135 | unconditional branch, and we are not generating PIC code, | |
16136 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
16137 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
16138 | insn = 0x0c000000; /* jal */ | |
252b5132 | 16139 | else |
a7ebbfdf TS |
16140 | insn = 0x08000000; /* j */ |
16141 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
16142 | fixP->fx_done = 0; | |
16143 | fixP->fx_addsy = section_symbol (text_section); | |
16144 | *valP += md_pcrel_from (fixP); | |
4d68580a | 16145 | write_insn (buf, insn); |
a7ebbfdf TS |
16146 | } |
16147 | else | |
16148 | { | |
16149 | /* If we got here, we have branch-relaxation disabled, | |
16150 | and there's nothing we can do to fix this instruction | |
16151 | without turning it into a longer sequence. */ | |
16152 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 16153 | _("branch out of range")); |
252b5132 | 16154 | } |
252b5132 RH |
16155 | break; |
16156 | ||
c9775dde | 16157 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
16158 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
16159 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
16160 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 16161 | gas_assert (!fixP->fx_done); |
9d862524 MR |
16162 | if (fix_bad_cross_mode_branch_p (fixP)) |
16163 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16164 | _("branch to a symbol in another ISA mode")); | |
16165 | else if (fixP->fx_addsy | |
16166 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
16167 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
16168 | && (fixP->fx_offset & 0x1) != 0) | |
16169 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16170 | _("branch to misaligned address (0x%lx)"), | |
52031738 | 16171 | (long) fix_bad_misaligned_address (fixP)); |
9d862524 MR |
16172 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) |
16173 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16174 | _("cannot encode misaligned addend " | |
16175 | "in the relocatable field (0x%lx)"), | |
16176 | (long) fixP->fx_offset); | |
df58fc94 RS |
16177 | break; |
16178 | ||
252b5132 RH |
16179 | case BFD_RELOC_VTABLE_INHERIT: |
16180 | fixP->fx_done = 0; | |
16181 | if (fixP->fx_addsy | |
16182 | && !S_IS_DEFINED (fixP->fx_addsy) | |
16183 | && !S_IS_WEAK (fixP->fx_addsy)) | |
16184 | S_SET_WEAK (fixP->fx_addsy); | |
16185 | break; | |
16186 | ||
2f0c68f2 | 16187 | case BFD_RELOC_NONE: |
252b5132 RH |
16188 | case BFD_RELOC_VTABLE_ENTRY: |
16189 | fixP->fx_done = 0; | |
16190 | break; | |
16191 | ||
16192 | default: | |
b37df7c4 | 16193 | abort (); |
252b5132 | 16194 | } |
a7ebbfdf TS |
16195 | |
16196 | /* Remember value for tc_gen_reloc. */ | |
16197 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
16198 | } |
16199 | ||
252b5132 | 16200 | static symbolS * |
17a2f251 | 16201 | get_symbol (void) |
252b5132 RH |
16202 | { |
16203 | int c; | |
16204 | char *name; | |
16205 | symbolS *p; | |
16206 | ||
d02603dc | 16207 | c = get_symbol_name (&name); |
252b5132 | 16208 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 16209 | (void) restore_line_pointer (c); |
252b5132 RH |
16210 | return p; |
16211 | } | |
16212 | ||
742a56fe RS |
16213 | /* Align the current frag to a given power of two. If a particular |
16214 | fill byte should be used, FILL points to an integer that contains | |
16215 | that byte, otherwise FILL is null. | |
16216 | ||
462427c4 RS |
16217 | This function used to have the comment: |
16218 | ||
16219 | The MIPS assembler also automatically adjusts any preceding label. | |
16220 | ||
16221 | The implementation therefore applied the adjustment to a maximum of | |
16222 | one label. However, other label adjustments are applied to batches | |
16223 | of labels, and adjusting just one caused problems when new labels | |
16224 | were added for the sake of debugging or unwind information. | |
16225 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
16226 | |
16227 | static void | |
462427c4 | 16228 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16229 | { |
7d10b47d | 16230 | mips_emit_delays (); |
df58fc94 | 16231 | mips_record_compressed_mode (); |
742a56fe RS |
16232 | if (fill == NULL && subseg_text_p (now_seg)) |
16233 | frag_align_code (to, 0); | |
16234 | else | |
16235 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16236 | record_alignment (now_seg, to); |
770c0151 | 16237 | mips_move_labels (labels, subseg_text_p (now_seg)); |
252b5132 RH |
16238 | } |
16239 | ||
16240 | /* Align to a given power of two. .align 0 turns off the automatic | |
16241 | alignment used by the data creating pseudo-ops. */ | |
16242 | ||
16243 | static void | |
17a2f251 | 16244 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16245 | { |
742a56fe | 16246 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16247 | long max_alignment = 28; |
252b5132 | 16248 | |
54f4ddb3 | 16249 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16250 | to the aligned address. |
54f4ddb3 | 16251 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16252 | a .align pseudo instruction. |
54f4ddb3 | 16253 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16254 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16255 | We don't. */ |
252b5132 RH |
16256 | |
16257 | temp = get_absolute_expression (); | |
16258 | if (temp > max_alignment) | |
1661c76c | 16259 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
16260 | else if (temp < 0) |
16261 | { | |
1661c76c | 16262 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
16263 | temp = 0; |
16264 | } | |
16265 | if (*input_line_pointer == ',') | |
16266 | { | |
f9419b05 | 16267 | ++input_line_pointer; |
742a56fe RS |
16268 | fill_value = get_absolute_expression (); |
16269 | fill_ptr = &fill_value; | |
252b5132 RH |
16270 | } |
16271 | else | |
742a56fe | 16272 | fill_ptr = 0; |
252b5132 RH |
16273 | if (temp) |
16274 | { | |
a8dbcb85 TS |
16275 | segment_info_type *si = seg_info (now_seg); |
16276 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16277 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16278 | auto_align = 1; |
462427c4 | 16279 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16280 | } |
16281 | else | |
16282 | { | |
16283 | auto_align = 0; | |
16284 | } | |
16285 | ||
16286 | demand_empty_rest_of_line (); | |
16287 | } | |
16288 | ||
252b5132 | 16289 | static void |
17a2f251 | 16290 | s_change_sec (int sec) |
252b5132 RH |
16291 | { |
16292 | segT seg; | |
16293 | ||
252b5132 RH |
16294 | /* The ELF backend needs to know that we are changing sections, so |
16295 | that .previous works correctly. We could do something like check | |
b6ff326e | 16296 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16297 | as it would not be appropriate to use it in the section changing |
16298 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16299 | This should be cleaner, somehow. */ | |
f3ded42a | 16300 | obj_elf_section_change_hook (); |
252b5132 | 16301 | |
7d10b47d | 16302 | mips_emit_delays (); |
6a32d874 | 16303 | |
252b5132 RH |
16304 | switch (sec) |
16305 | { | |
16306 | case 't': | |
16307 | s_text (0); | |
16308 | break; | |
16309 | case 'd': | |
16310 | s_data (0); | |
16311 | break; | |
16312 | case 'b': | |
16313 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16314 | demand_empty_rest_of_line (); | |
16315 | break; | |
16316 | ||
16317 | case 'r': | |
4d0d148d TS |
16318 | seg = subseg_new (RDATA_SECTION_NAME, |
16319 | (subsegT) get_absolute_expression ()); | |
fd361982 AM |
16320 | bfd_set_section_flags (seg, (SEC_ALLOC | SEC_LOAD | SEC_READONLY |
16321 | | SEC_RELOC | SEC_DATA)); | |
f3ded42a RS |
16322 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
16323 | record_alignment (seg, 4); | |
4d0d148d | 16324 | demand_empty_rest_of_line (); |
252b5132 RH |
16325 | break; |
16326 | ||
16327 | case 's': | |
4d0d148d | 16328 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
fd361982 | 16329 | bfd_set_section_flags (seg, |
f3ded42a RS |
16330 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); |
16331 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16332 | record_alignment (seg, 4); | |
4d0d148d TS |
16333 | demand_empty_rest_of_line (); |
16334 | break; | |
998b3c36 MR |
16335 | |
16336 | case 'B': | |
16337 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
fd361982 | 16338 | bfd_set_section_flags (seg, SEC_ALLOC); |
f3ded42a RS |
16339 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
16340 | record_alignment (seg, 4); | |
998b3c36 MR |
16341 | demand_empty_rest_of_line (); |
16342 | break; | |
252b5132 RH |
16343 | } |
16344 | ||
16345 | auto_align = 1; | |
16346 | } | |
b34976b6 | 16347 | |
cca86cc8 | 16348 | void |
17a2f251 | 16349 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16350 | { |
d02603dc | 16351 | char *saved_ilp; |
cca86cc8 | 16352 | char *section_name; |
d02603dc | 16353 | char c, endc; |
684022ea | 16354 | char next_c = 0; |
cca86cc8 SC |
16355 | int section_type; |
16356 | int section_flag; | |
16357 | int section_entry_size; | |
16358 | int section_alignment; | |
b34976b6 | 16359 | |
d02603dc NC |
16360 | saved_ilp = input_line_pointer; |
16361 | endc = get_symbol_name (§ion_name); | |
16362 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 16363 | if (c) |
d02603dc | 16364 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 16365 | |
4cf0dd0d TS |
16366 | /* Do we have .section Name<,"flags">? */ |
16367 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16368 | { |
d02603dc NC |
16369 | /* Just after name is now '\0'. */ |
16370 | (void) restore_line_pointer (endc); | |
16371 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
16372 | obj_elf_section (ignore); |
16373 | return; | |
16374 | } | |
d02603dc NC |
16375 | |
16376 | section_name = xstrdup (section_name); | |
16377 | c = restore_line_pointer (endc); | |
16378 | ||
cca86cc8 SC |
16379 | input_line_pointer++; |
16380 | ||
16381 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16382 | if (c == ',') | |
16383 | section_type = get_absolute_expression (); | |
16384 | else | |
16385 | section_type = 0; | |
d02603dc | 16386 | |
cca86cc8 SC |
16387 | if (*input_line_pointer++ == ',') |
16388 | section_flag = get_absolute_expression (); | |
16389 | else | |
16390 | section_flag = 0; | |
d02603dc | 16391 | |
cca86cc8 SC |
16392 | if (*input_line_pointer++ == ',') |
16393 | section_entry_size = get_absolute_expression (); | |
16394 | else | |
16395 | section_entry_size = 0; | |
d02603dc | 16396 | |
cca86cc8 SC |
16397 | if (*input_line_pointer++ == ',') |
16398 | section_alignment = get_absolute_expression (); | |
16399 | else | |
16400 | section_alignment = 0; | |
d02603dc | 16401 | |
87975d2a AM |
16402 | /* FIXME: really ignore? */ |
16403 | (void) section_alignment; | |
cca86cc8 | 16404 | |
8ab8a5c8 RS |
16405 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16406 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16407 | traditionally had to fall back on the more common @progbits instead. | |
16408 | ||
16409 | There's nothing really harmful in this, since bfd will correct | |
16410 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16411 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16412 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16413 | ||
16414 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16415 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16416 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16417 | generic type-checking code. */ | |
16418 | if (section_type == SHT_MIPS_DWARF) | |
16419 | section_type = SHT_PROGBITS; | |
16420 | ||
a91e1603 | 16421 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
cca86cc8 | 16422 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
16423 | |
16424 | if (now_seg->name != section_name) | |
16425 | free (section_name); | |
cca86cc8 | 16426 | } |
252b5132 RH |
16427 | |
16428 | void | |
17a2f251 | 16429 | mips_enable_auto_align (void) |
252b5132 RH |
16430 | { |
16431 | auto_align = 1; | |
16432 | } | |
16433 | ||
16434 | static void | |
17a2f251 | 16435 | s_cons (int log_size) |
252b5132 | 16436 | { |
a8dbcb85 TS |
16437 | segment_info_type *si = seg_info (now_seg); |
16438 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16439 | |
7d10b47d | 16440 | mips_emit_delays (); |
252b5132 | 16441 | if (log_size > 0 && auto_align) |
462427c4 | 16442 | mips_align (log_size, 0, l); |
252b5132 | 16443 | cons (1 << log_size); |
a1facbec | 16444 | mips_clear_insn_labels (); |
252b5132 RH |
16445 | } |
16446 | ||
16447 | static void | |
17a2f251 | 16448 | s_float_cons (int type) |
252b5132 | 16449 | { |
a8dbcb85 TS |
16450 | segment_info_type *si = seg_info (now_seg); |
16451 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16452 | |
7d10b47d | 16453 | mips_emit_delays (); |
252b5132 RH |
16454 | |
16455 | if (auto_align) | |
49309057 ILT |
16456 | { |
16457 | if (type == 'd') | |
462427c4 | 16458 | mips_align (3, 0, l); |
49309057 | 16459 | else |
462427c4 | 16460 | mips_align (2, 0, l); |
49309057 | 16461 | } |
252b5132 | 16462 | |
252b5132 | 16463 | float_cons (type); |
a1facbec | 16464 | mips_clear_insn_labels (); |
252b5132 RH |
16465 | } |
16466 | ||
16467 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16468 | permitted to say | |
16469 | .globl foo .text | |
16470 | where foo is an undefined symbol, to mean that foo should be | |
16471 | considered to be the address of a function. */ | |
16472 | ||
16473 | static void | |
17a2f251 | 16474 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16475 | { |
16476 | char *name; | |
16477 | int c; | |
16478 | symbolS *symbolP; | |
252b5132 | 16479 | |
8a06b769 | 16480 | do |
252b5132 | 16481 | { |
d02603dc | 16482 | c = get_symbol_name (&name); |
8a06b769 TS |
16483 | symbolP = symbol_find_or_make (name); |
16484 | S_SET_EXTERNAL (symbolP); | |
16485 | ||
252b5132 | 16486 | *input_line_pointer = c; |
d02603dc | 16487 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 16488 | |
8a06b769 TS |
16489 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16490 | && (*input_line_pointer != ',')) | |
16491 | { | |
16492 | char *secname; | |
16493 | asection *sec; | |
16494 | ||
d02603dc | 16495 | c = get_symbol_name (&secname); |
8a06b769 TS |
16496 | sec = bfd_get_section_by_name (stdoutput, secname); |
16497 | if (sec == NULL) | |
16498 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16499 | (void) restore_line_pointer (c); |
8a06b769 TS |
16500 | |
16501 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
d69cd47e | 16502 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
8a06b769 TS |
16503 | } |
16504 | ||
8a06b769 TS |
16505 | c = *input_line_pointer; |
16506 | if (c == ',') | |
16507 | { | |
16508 | input_line_pointer++; | |
16509 | SKIP_WHITESPACE (); | |
16510 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16511 | c = '\n'; | |
16512 | } | |
16513 | } | |
16514 | while (c == ','); | |
252b5132 | 16515 | |
252b5132 RH |
16516 | demand_empty_rest_of_line (); |
16517 | } | |
16518 | ||
d69cd47e AM |
16519 | #ifdef TE_IRIX |
16520 | /* The Irix 5 and 6 assemblers set the type of any common symbol and | |
16521 | any undefined non-function symbol to STT_OBJECT. We try to be | |
16522 | compatible, since newer Irix 5 and 6 linkers care. */ | |
16523 | ||
16524 | void | |
16525 | mips_frob_symbol (symbolS *symp ATTRIBUTE_UNUSED) | |
16526 | { | |
16527 | /* This late in assembly we can set BSF_OBJECT indiscriminately | |
16528 | and let elf.c:swap_out_syms sort out the symbol type. */ | |
16529 | flagword *flags = &symbol_get_bfdsym (symp)->flags; | |
16530 | if ((*flags & (BSF_GLOBAL | BSF_WEAK)) != 0 | |
16531 | || !S_IS_DEFINED (symp)) | |
16532 | *flags |= BSF_OBJECT; | |
16533 | } | |
16534 | #endif | |
16535 | ||
252b5132 | 16536 | static void |
17a2f251 | 16537 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16538 | { |
16539 | char *opt; | |
16540 | char c; | |
16541 | ||
d02603dc | 16542 | c = get_symbol_name (&opt); |
252b5132 RH |
16543 | |
16544 | if (*opt == 'O') | |
16545 | { | |
16546 | /* FIXME: What does this mean? */ | |
16547 | } | |
41a1578e | 16548 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16549 | { |
16550 | int i; | |
16551 | ||
16552 | i = atoi (opt + 3); | |
668c5ebc MR |
16553 | if (i != 0 && i != 2) |
16554 | as_bad (_(".option pic%d not supported"), i); | |
16555 | else if (mips_pic == VXWORKS_PIC) | |
16556 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16557 | else if (i == 0) | |
252b5132 RH |
16558 | mips_pic = NO_PIC; |
16559 | else if (i == 2) | |
143d77c5 | 16560 | { |
8b828383 | 16561 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16562 | mips_abicalls = TRUE; |
16563 | } | |
252b5132 | 16564 | |
4d0d148d | 16565 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16566 | { |
16567 | if (g_switch_seen && g_switch_value != 0) | |
16568 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16569 | g_switch_value = 0; | |
16570 | bfd_set_gp_size (stdoutput, 0); | |
16571 | } | |
16572 | } | |
16573 | else | |
1661c76c | 16574 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16575 | |
d02603dc | 16576 | (void) restore_line_pointer (c); |
252b5132 RH |
16577 | demand_empty_rest_of_line (); |
16578 | } | |
16579 | ||
16580 | /* This structure is used to hold a stack of .set values. */ | |
16581 | ||
e972090a NC |
16582 | struct mips_option_stack |
16583 | { | |
252b5132 RH |
16584 | struct mips_option_stack *next; |
16585 | struct mips_set_options options; | |
16586 | }; | |
16587 | ||
16588 | static struct mips_option_stack *mips_opts_stack; | |
16589 | ||
22522f88 MR |
16590 | /* Return status for .set/.module option handling. */ |
16591 | ||
16592 | enum code_option_type | |
16593 | { | |
16594 | /* Unrecognized option. */ | |
16595 | OPTION_TYPE_BAD = -1, | |
16596 | ||
16597 | /* Ordinary option. */ | |
16598 | OPTION_TYPE_NORMAL, | |
16599 | ||
16600 | /* ISA changing option. */ | |
16601 | OPTION_TYPE_ISA | |
16602 | }; | |
16603 | ||
16604 | /* Handle common .set/.module options. Return status indicating option | |
16605 | type. */ | |
16606 | ||
16607 | static enum code_option_type | |
919731af | 16608 | parse_code_option (char * name) |
252b5132 | 16609 | { |
22522f88 | 16610 | bfd_boolean isa_set = FALSE; |
c6278170 | 16611 | const struct mips_ase *ase; |
22522f88 | 16612 | |
919731af | 16613 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16614 | { |
16615 | char *s = name + 3; | |
16616 | ||
16617 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16618 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16619 | } |
252b5132 | 16620 | else if (strcmp (name, "at") == 0) |
919731af | 16621 | mips_opts.at = ATREG; |
252b5132 | 16622 | else if (strcmp (name, "noat") == 0) |
919731af | 16623 | mips_opts.at = ZERO; |
252b5132 | 16624 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16625 | mips_opts.nomove = 0; |
252b5132 | 16626 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16627 | mips_opts.nomove = 1; |
252b5132 | 16628 | else if (strcmp (name, "bopt") == 0) |
919731af | 16629 | mips_opts.nobopt = 0; |
252b5132 | 16630 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16631 | mips_opts.nobopt = 1; |
ad3fea08 | 16632 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16633 | mips_opts.gp = 32; |
ad3fea08 | 16634 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16635 | mips_opts.gp = 64; |
ad3fea08 | 16636 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16637 | mips_opts.fp = 32; |
351cdf24 MF |
16638 | else if (strcmp (name, "fp=xx") == 0) |
16639 | mips_opts.fp = 0; | |
ad3fea08 | 16640 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16641 | mips_opts.fp = 64; |
037b32b9 AN |
16642 | else if (strcmp (name, "softfloat") == 0) |
16643 | mips_opts.soft_float = 1; | |
16644 | else if (strcmp (name, "hardfloat") == 0) | |
16645 | mips_opts.soft_float = 0; | |
16646 | else if (strcmp (name, "singlefloat") == 0) | |
16647 | mips_opts.single_float = 1; | |
16648 | else if (strcmp (name, "doublefloat") == 0) | |
16649 | mips_opts.single_float = 0; | |
351cdf24 MF |
16650 | else if (strcmp (name, "nooddspreg") == 0) |
16651 | mips_opts.oddspreg = 0; | |
16652 | else if (strcmp (name, "oddspreg") == 0) | |
16653 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16654 | else if (strcmp (name, "mips16") == 0 |
16655 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16656 | mips_opts.mips16 = 1; |
252b5132 RH |
16657 | else if (strcmp (name, "nomips16") == 0 |
16658 | || strcmp (name, "noMIPS-16") == 0) | |
16659 | mips_opts.mips16 = 0; | |
df58fc94 | 16660 | else if (strcmp (name, "micromips") == 0) |
919731af | 16661 | mips_opts.micromips = 1; |
df58fc94 RS |
16662 | else if (strcmp (name, "nomicromips") == 0) |
16663 | mips_opts.micromips = 0; | |
c6278170 RS |
16664 | else if (name[0] == 'n' |
16665 | && name[1] == 'o' | |
16666 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16667 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16668 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16669 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16670 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16671 | { |
1a2c1fad CD |
16672 | /* Permit the user to change the ISA and architecture on the fly. |
16673 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16674 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16675 | { |
16676 | const struct mips_cpu_info *p; | |
16677 | ||
919731af | 16678 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16679 | if (!p) |
16680 | as_bad (_("unknown architecture %s"), name + 5); | |
16681 | else | |
16682 | { | |
16683 | mips_opts.arch = p->cpu; | |
16684 | mips_opts.isa = p->isa; | |
22522f88 | 16685 | isa_set = TRUE; |
3315614d | 16686 | mips_opts.init_ase = p->ase; |
1a2c1fad CD |
16687 | } |
16688 | } | |
81a21e38 TS |
16689 | else if (strncmp (name, "mips", 4) == 0) |
16690 | { | |
16691 | const struct mips_cpu_info *p; | |
16692 | ||
919731af | 16693 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16694 | if (!p) |
16695 | as_bad (_("unknown ISA level %s"), name + 4); | |
16696 | else | |
16697 | { | |
16698 | mips_opts.arch = p->cpu; | |
16699 | mips_opts.isa = p->isa; | |
22522f88 | 16700 | isa_set = TRUE; |
3315614d | 16701 | mips_opts.init_ase = p->ase; |
81a21e38 TS |
16702 | } |
16703 | } | |
af7ee8bf | 16704 | else |
81a21e38 | 16705 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16706 | } |
16707 | else if (strcmp (name, "autoextend") == 0) | |
16708 | mips_opts.noautoextend = 0; | |
16709 | else if (strcmp (name, "noautoextend") == 0) | |
16710 | mips_opts.noautoextend = 1; | |
833794fc MR |
16711 | else if (strcmp (name, "insn32") == 0) |
16712 | mips_opts.insn32 = TRUE; | |
16713 | else if (strcmp (name, "noinsn32") == 0) | |
16714 | mips_opts.insn32 = FALSE; | |
919731af | 16715 | else if (strcmp (name, "sym32") == 0) |
16716 | mips_opts.sym32 = TRUE; | |
16717 | else if (strcmp (name, "nosym32") == 0) | |
16718 | mips_opts.sym32 = FALSE; | |
16719 | else | |
22522f88 MR |
16720 | return OPTION_TYPE_BAD; |
16721 | ||
16722 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16723 | } |
16724 | ||
16725 | /* Handle the .set pseudo-op. */ | |
16726 | ||
16727 | static void | |
16728 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16729 | { | |
22522f88 | 16730 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16731 | char *name = input_line_pointer, ch; |
919731af | 16732 | |
16733 | file_mips_check_options (); | |
16734 | ||
16735 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16736 | ++input_line_pointer; | |
16737 | ch = *input_line_pointer; | |
16738 | *input_line_pointer = '\0'; | |
16739 | ||
16740 | if (strchr (name, ',')) | |
16741 | { | |
16742 | /* Generic ".set" directive; use the generic handler. */ | |
16743 | *input_line_pointer = ch; | |
16744 | input_line_pointer = name; | |
16745 | s_set (0); | |
16746 | return; | |
16747 | } | |
16748 | ||
16749 | if (strcmp (name, "reorder") == 0) | |
16750 | { | |
16751 | if (mips_opts.noreorder) | |
16752 | end_noreorder (); | |
16753 | } | |
16754 | else if (strcmp (name, "noreorder") == 0) | |
16755 | { | |
16756 | if (!mips_opts.noreorder) | |
16757 | start_noreorder (); | |
16758 | } | |
16759 | else if (strcmp (name, "macro") == 0) | |
16760 | mips_opts.warn_about_macros = 0; | |
16761 | else if (strcmp (name, "nomacro") == 0) | |
16762 | { | |
16763 | if (mips_opts.noreorder == 0) | |
16764 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16765 | mips_opts.warn_about_macros = 1; | |
16766 | } | |
16767 | else if (strcmp (name, "gp=default") == 0) | |
16768 | mips_opts.gp = file_mips_opts.gp; | |
16769 | else if (strcmp (name, "fp=default") == 0) | |
16770 | mips_opts.fp = file_mips_opts.fp; | |
16771 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16772 | { | |
16773 | mips_opts.isa = file_mips_opts.isa; | |
16774 | mips_opts.arch = file_mips_opts.arch; | |
3315614d | 16775 | mips_opts.init_ase = file_mips_opts.init_ase; |
919731af | 16776 | mips_opts.gp = file_mips_opts.gp; |
16777 | mips_opts.fp = file_mips_opts.fp; | |
16778 | } | |
252b5132 RH |
16779 | else if (strcmp (name, "push") == 0) |
16780 | { | |
16781 | struct mips_option_stack *s; | |
16782 | ||
325801bd | 16783 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16784 | s->next = mips_opts_stack; |
16785 | s->options = mips_opts; | |
16786 | mips_opts_stack = s; | |
16787 | } | |
16788 | else if (strcmp (name, "pop") == 0) | |
16789 | { | |
16790 | struct mips_option_stack *s; | |
16791 | ||
16792 | s = mips_opts_stack; | |
16793 | if (s == NULL) | |
16794 | as_bad (_(".set pop with no .set push")); | |
16795 | else | |
16796 | { | |
16797 | /* If we're changing the reorder mode we need to handle | |
16798 | delay slots correctly. */ | |
16799 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16800 | start_noreorder (); |
252b5132 | 16801 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16802 | end_noreorder (); |
252b5132 RH |
16803 | |
16804 | mips_opts = s->options; | |
16805 | mips_opts_stack = s->next; | |
16806 | free (s); | |
16807 | } | |
16808 | } | |
22522f88 MR |
16809 | else |
16810 | { | |
16811 | type = parse_code_option (name); | |
16812 | if (type == OPTION_TYPE_BAD) | |
16813 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16814 | } | |
919731af | 16815 | |
16816 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16817 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16818 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16819 | { |
919731af | 16820 | switch (mips_opts.isa) |
16821 | { | |
16822 | case 0: | |
16823 | break; | |
16824 | case ISA_MIPS1: | |
351cdf24 MF |
16825 | /* MIPS I cannot support FPXX. */ |
16826 | mips_opts.fp = 32; | |
16827 | /* fall-through. */ | |
919731af | 16828 | case ISA_MIPS2: |
16829 | case ISA_MIPS32: | |
16830 | case ISA_MIPS32R2: | |
16831 | case ISA_MIPS32R3: | |
16832 | case ISA_MIPS32R5: | |
16833 | mips_opts.gp = 32; | |
351cdf24 MF |
16834 | if (mips_opts.fp != 0) |
16835 | mips_opts.fp = 32; | |
919731af | 16836 | break; |
7361da2c AB |
16837 | case ISA_MIPS32R6: |
16838 | mips_opts.gp = 32; | |
16839 | mips_opts.fp = 64; | |
16840 | break; | |
919731af | 16841 | case ISA_MIPS3: |
16842 | case ISA_MIPS4: | |
16843 | case ISA_MIPS5: | |
16844 | case ISA_MIPS64: | |
16845 | case ISA_MIPS64R2: | |
16846 | case ISA_MIPS64R3: | |
16847 | case ISA_MIPS64R5: | |
7361da2c | 16848 | case ISA_MIPS64R6: |
919731af | 16849 | mips_opts.gp = 64; |
351cdf24 MF |
16850 | if (mips_opts.fp != 0) |
16851 | { | |
16852 | if (mips_opts.arch == CPU_R5900) | |
16853 | mips_opts.fp = 32; | |
16854 | else | |
16855 | mips_opts.fp = 64; | |
16856 | } | |
919731af | 16857 | break; |
16858 | default: | |
16859 | as_bad (_("unknown ISA level %s"), name + 4); | |
16860 | break; | |
16861 | } | |
e6559e01 | 16862 | } |
919731af | 16863 | |
16864 | mips_check_options (&mips_opts, FALSE); | |
16865 | ||
16866 | mips_check_isa_supports_ases (); | |
16867 | *input_line_pointer = ch; | |
16868 | demand_empty_rest_of_line (); | |
16869 | } | |
16870 | ||
16871 | /* Handle the .module pseudo-op. */ | |
16872 | ||
16873 | static void | |
16874 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16875 | { | |
16876 | char *name = input_line_pointer, ch; | |
16877 | ||
16878 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16879 | ++input_line_pointer; | |
16880 | ch = *input_line_pointer; | |
16881 | *input_line_pointer = '\0'; | |
16882 | ||
16883 | if (!file_mips_opts_checked) | |
252b5132 | 16884 | { |
22522f88 | 16885 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16886 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16887 | ||
16888 | /* Update module level settings from mips_opts. */ | |
16889 | file_mips_opts = mips_opts; | |
252b5132 | 16890 | } |
919731af | 16891 | else |
16892 | as_bad (_(".module is not permitted after generating code")); | |
16893 | ||
252b5132 RH |
16894 | *input_line_pointer = ch; |
16895 | demand_empty_rest_of_line (); | |
16896 | } | |
16897 | ||
16898 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16899 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16900 | ||
16901 | static void | |
17a2f251 | 16902 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16903 | { |
16904 | mips_pic = SVR4_PIC; | |
143d77c5 | 16905 | mips_abicalls = TRUE; |
4d0d148d TS |
16906 | |
16907 | if (g_switch_seen && g_switch_value != 0) | |
16908 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16909 | g_switch_value = 0; | |
16910 | ||
252b5132 RH |
16911 | bfd_set_gp_size (stdoutput, 0); |
16912 | demand_empty_rest_of_line (); | |
16913 | } | |
16914 | ||
16915 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16916 | PIC code. It sets the $gp register for the function based on the | |
16917 | function address, which is in the register named in the argument. | |
16918 | This uses a relocation against _gp_disp, which is handled specially | |
16919 | by the linker. The result is: | |
16920 | lui $gp,%hi(_gp_disp) | |
16921 | addiu $gp,$gp,%lo(_gp_disp) | |
16922 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16923 | The .cpload argument is normally $25 == $t9. |
16924 | ||
16925 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16926 | lui $gp,%hi(__gnu_local_gp) |
16927 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16928 | and the argument is ignored. This saves an instruction, but the |
16929 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16930 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16931 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16932 | |
16933 | static void | |
17a2f251 | 16934 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16935 | { |
16936 | expressionS ex; | |
aa6975fb ILT |
16937 | int reg; |
16938 | int in_shared; | |
252b5132 | 16939 | |
919731af | 16940 | file_mips_check_options (); |
16941 | ||
6478892d TS |
16942 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16943 | .cpload is ignored. */ | |
16944 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16945 | { |
16946 | s_ignore (0); | |
16947 | return; | |
16948 | } | |
16949 | ||
a276b80c MR |
16950 | if (mips_opts.mips16) |
16951 | { | |
16952 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16953 | ignore_rest_of_line (); | |
16954 | return; | |
16955 | } | |
16956 | ||
d3ecfc59 | 16957 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16958 | if (mips_opts.noreorder == 0) |
16959 | as_warn (_(".cpload not in noreorder section")); | |
16960 | ||
aa6975fb ILT |
16961 | reg = tc_get_register (0); |
16962 | ||
16963 | /* If we need to produce a 64-bit address, we are better off using | |
16964 | the default instruction sequence. */ | |
aed1a261 | 16965 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16966 | |
252b5132 | 16967 | ex.X_op = O_symbol; |
bbe506e8 TS |
16968 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16969 | "__gnu_local_gp"); | |
252b5132 RH |
16970 | ex.X_op_symbol = NULL; |
16971 | ex.X_add_number = 0; | |
16972 | ||
16973 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16974 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16975 | |
8a75745d MR |
16976 | mips_mark_labels (); |
16977 | mips_assembling_insn = TRUE; | |
16978 | ||
584892a6 | 16979 | macro_start (); |
67c0d1eb RS |
16980 | macro_build_lui (&ex, mips_gp_register); |
16981 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16982 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16983 | if (in_shared) |
16984 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16985 | mips_gp_register, reg); | |
584892a6 | 16986 | macro_end (); |
252b5132 | 16987 | |
8a75745d | 16988 | mips_assembling_insn = FALSE; |
252b5132 RH |
16989 | demand_empty_rest_of_line (); |
16990 | } | |
16991 | ||
6478892d TS |
16992 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16993 | .cpsetup $reg1, offset|$reg2, label | |
16994 | ||
16995 | If offset is given, this results in: | |
16996 | sd $gp, offset($sp) | |
956cd1d6 | 16997 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16998 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16999 | daddu $gp, $gp, $reg1 | |
6478892d TS |
17000 | |
17001 | If $reg2 is given, this results in: | |
40fc1451 | 17002 | or $reg2, $gp, $0 |
956cd1d6 | 17003 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
17004 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
17005 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
17006 | $reg1 is normally $25 == $t9. |
17007 | ||
17008 | The -mno-shared option replaces the last three instructions with | |
17009 | lui $gp,%hi(_gp) | |
54f4ddb3 | 17010 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 17011 | |
6478892d | 17012 | static void |
17a2f251 | 17013 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17014 | { |
17015 | expressionS ex_off; | |
17016 | expressionS ex_sym; | |
17017 | int reg1; | |
6478892d | 17018 | |
919731af | 17019 | file_mips_check_options (); |
17020 | ||
8586fc66 | 17021 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
17022 | We also need NewABI support. */ |
17023 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17024 | { | |
17025 | s_ignore (0); | |
17026 | return; | |
17027 | } | |
17028 | ||
a276b80c MR |
17029 | if (mips_opts.mips16) |
17030 | { | |
17031 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
17032 | ignore_rest_of_line (); | |
17033 | return; | |
17034 | } | |
17035 | ||
6478892d TS |
17036 | reg1 = tc_get_register (0); |
17037 | SKIP_WHITESPACE (); | |
17038 | if (*input_line_pointer != ',') | |
17039 | { | |
17040 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
17041 | return; | |
17042 | } | |
17043 | else | |
80245285 | 17044 | ++input_line_pointer; |
6478892d TS |
17045 | SKIP_WHITESPACE (); |
17046 | if (*input_line_pointer == '$') | |
80245285 TS |
17047 | { |
17048 | mips_cpreturn_register = tc_get_register (0); | |
17049 | mips_cpreturn_offset = -1; | |
17050 | } | |
6478892d | 17051 | else |
80245285 TS |
17052 | { |
17053 | mips_cpreturn_offset = get_absolute_expression (); | |
17054 | mips_cpreturn_register = -1; | |
17055 | } | |
6478892d TS |
17056 | SKIP_WHITESPACE (); |
17057 | if (*input_line_pointer != ',') | |
17058 | { | |
17059 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
17060 | return; | |
17061 | } | |
17062 | else | |
f9419b05 | 17063 | ++input_line_pointer; |
6478892d | 17064 | SKIP_WHITESPACE (); |
f21f8242 | 17065 | expression (&ex_sym); |
6478892d | 17066 | |
8a75745d MR |
17067 | mips_mark_labels (); |
17068 | mips_assembling_insn = TRUE; | |
17069 | ||
584892a6 | 17070 | macro_start (); |
6478892d TS |
17071 | if (mips_cpreturn_register == -1) |
17072 | { | |
17073 | ex_off.X_op = O_constant; | |
17074 | ex_off.X_add_symbol = NULL; | |
17075 | ex_off.X_op_symbol = NULL; | |
17076 | ex_off.X_add_number = mips_cpreturn_offset; | |
17077 | ||
67c0d1eb | 17078 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 17079 | BFD_RELOC_LO16, SP); |
6478892d TS |
17080 | } |
17081 | else | |
40fc1451 | 17082 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 17083 | |
aed1a261 | 17084 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 17085 | { |
df58fc94 | 17086 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
17087 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
17088 | BFD_RELOC_HI16_S); | |
17089 | ||
17090 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
17091 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
17092 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
17093 | ||
17094 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
17095 | mips_gp_register, reg1); | |
17096 | } | |
17097 | else | |
17098 | { | |
17099 | expressionS ex; | |
17100 | ||
17101 | ex.X_op = O_symbol; | |
4184909a | 17102 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
17103 | ex.X_op_symbol = NULL; |
17104 | ex.X_add_number = 0; | |
6e1304d8 | 17105 | |
aa6975fb ILT |
17106 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
17107 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
17108 | ||
17109 | macro_build_lui (&ex, mips_gp_register); | |
17110 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17111 | mips_gp_register, BFD_RELOC_LO16); | |
17112 | } | |
f21f8242 | 17113 | |
584892a6 | 17114 | macro_end (); |
6478892d | 17115 | |
8a75745d | 17116 | mips_assembling_insn = FALSE; |
6478892d TS |
17117 | demand_empty_rest_of_line (); |
17118 | } | |
17119 | ||
17120 | static void | |
17a2f251 | 17121 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 17122 | { |
919731af | 17123 | file_mips_check_options (); |
17124 | ||
6478892d | 17125 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 17126 | .cplocal is ignored. */ |
6478892d TS |
17127 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
17128 | { | |
17129 | s_ignore (0); | |
17130 | return; | |
17131 | } | |
17132 | ||
a276b80c MR |
17133 | if (mips_opts.mips16) |
17134 | { | |
17135 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
17136 | ignore_rest_of_line (); | |
17137 | return; | |
17138 | } | |
17139 | ||
6478892d | 17140 | mips_gp_register = tc_get_register (0); |
85b51719 | 17141 | demand_empty_rest_of_line (); |
6478892d TS |
17142 | } |
17143 | ||
252b5132 RH |
17144 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
17145 | offset from $sp. The offset is remembered, and after making a PIC | |
17146 | call $gp is restored from that location. */ | |
17147 | ||
17148 | static void | |
17a2f251 | 17149 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17150 | { |
17151 | expressionS ex; | |
252b5132 | 17152 | |
919731af | 17153 | file_mips_check_options (); |
17154 | ||
6478892d | 17155 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 17156 | .cprestore is ignored. */ |
6478892d | 17157 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
17158 | { |
17159 | s_ignore (0); | |
17160 | return; | |
17161 | } | |
17162 | ||
a276b80c MR |
17163 | if (mips_opts.mips16) |
17164 | { | |
17165 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
17166 | ignore_rest_of_line (); | |
17167 | return; | |
17168 | } | |
17169 | ||
252b5132 | 17170 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 17171 | mips_cprestore_valid = 1; |
252b5132 RH |
17172 | |
17173 | ex.X_op = O_constant; | |
17174 | ex.X_add_symbol = NULL; | |
17175 | ex.X_op_symbol = NULL; | |
17176 | ex.X_add_number = mips_cprestore_offset; | |
17177 | ||
8a75745d MR |
17178 | mips_mark_labels (); |
17179 | mips_assembling_insn = TRUE; | |
17180 | ||
584892a6 | 17181 | macro_start (); |
67c0d1eb RS |
17182 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
17183 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 17184 | macro_end (); |
252b5132 | 17185 | |
8a75745d | 17186 | mips_assembling_insn = FALSE; |
252b5132 RH |
17187 | demand_empty_rest_of_line (); |
17188 | } | |
17189 | ||
6478892d | 17190 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 17191 | was given in the preceding .cpsetup, it results in: |
6478892d | 17192 | ld $gp, offset($sp) |
76b3015f | 17193 | |
6478892d | 17194 | If a register $reg2 was given there, it results in: |
40fc1451 | 17195 | or $gp, $reg2, $0 */ |
54f4ddb3 | 17196 | |
6478892d | 17197 | static void |
17a2f251 | 17198 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17199 | { |
17200 | expressionS ex; | |
6478892d | 17201 | |
919731af | 17202 | file_mips_check_options (); |
17203 | ||
6478892d TS |
17204 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
17205 | We also need NewABI support. */ | |
17206 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17207 | { | |
17208 | s_ignore (0); | |
17209 | return; | |
17210 | } | |
17211 | ||
a276b80c MR |
17212 | if (mips_opts.mips16) |
17213 | { | |
17214 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
17215 | ignore_rest_of_line (); | |
17216 | return; | |
17217 | } | |
17218 | ||
8a75745d MR |
17219 | mips_mark_labels (); |
17220 | mips_assembling_insn = TRUE; | |
17221 | ||
584892a6 | 17222 | macro_start (); |
6478892d TS |
17223 | if (mips_cpreturn_register == -1) |
17224 | { | |
17225 | ex.X_op = O_constant; | |
17226 | ex.X_add_symbol = NULL; | |
17227 | ex.X_op_symbol = NULL; | |
17228 | ex.X_add_number = mips_cpreturn_offset; | |
17229 | ||
67c0d1eb | 17230 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
17231 | } |
17232 | else | |
40fc1451 SD |
17233 | move_register (mips_gp_register, mips_cpreturn_register); |
17234 | ||
584892a6 | 17235 | macro_end (); |
6478892d | 17236 | |
8a75745d | 17237 | mips_assembling_insn = FALSE; |
6478892d TS |
17238 | demand_empty_rest_of_line (); |
17239 | } | |
17240 | ||
d0f13682 CLT |
17241 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
17242 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
17243 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
17244 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
17245 | |
17246 | static void | |
d0f13682 CLT |
17247 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
17248 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
17249 | { |
17250 | expressionS ex; | |
17251 | char *p; | |
17252 | ||
17253 | expression (&ex); | |
17254 | ||
17255 | if (ex.X_op != O_symbol) | |
17256 | { | |
1661c76c | 17257 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
17258 | ignore_rest_of_line (); |
17259 | } | |
17260 | ||
17261 | p = frag_more (bytes); | |
17262 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17263 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17264 | demand_empty_rest_of_line (); |
de64cffd | 17265 | mips_clear_insn_labels (); |
741d6ea8 JM |
17266 | } |
17267 | ||
17268 | /* Handle .dtprelword. */ | |
17269 | ||
17270 | static void | |
17271 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17272 | { | |
d0f13682 | 17273 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17274 | } |
17275 | ||
17276 | /* Handle .dtpreldword. */ | |
17277 | ||
17278 | static void | |
17279 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17280 | { | |
d0f13682 CLT |
17281 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17282 | } | |
17283 | ||
17284 | /* Handle .tprelword. */ | |
17285 | ||
17286 | static void | |
17287 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17288 | { | |
17289 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17290 | } | |
17291 | ||
17292 | /* Handle .tpreldword. */ | |
17293 | ||
17294 | static void | |
17295 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17296 | { | |
17297 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17298 | } |
17299 | ||
6478892d TS |
17300 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17301 | code. It sets the offset to use in gp_rel relocations. */ | |
17302 | ||
17303 | static void | |
17a2f251 | 17304 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17305 | { |
17306 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17307 | We also need NewABI support. */ | |
17308 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17309 | { | |
17310 | s_ignore (0); | |
17311 | return; | |
17312 | } | |
17313 | ||
def2e0dd | 17314 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17315 | |
17316 | demand_empty_rest_of_line (); | |
17317 | } | |
17318 | ||
252b5132 RH |
17319 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17320 | code. It generates a 32 bit GP relative reloc. */ | |
17321 | ||
17322 | static void | |
17a2f251 | 17323 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17324 | { |
a8dbcb85 TS |
17325 | segment_info_type *si; |
17326 | struct insn_label_list *l; | |
252b5132 RH |
17327 | expressionS ex; |
17328 | char *p; | |
17329 | ||
17330 | /* When not generating PIC code, this is treated as .word. */ | |
17331 | if (mips_pic != SVR4_PIC) | |
17332 | { | |
17333 | s_cons (2); | |
17334 | return; | |
17335 | } | |
17336 | ||
a8dbcb85 TS |
17337 | si = seg_info (now_seg); |
17338 | l = si->label_list; | |
7d10b47d | 17339 | mips_emit_delays (); |
252b5132 | 17340 | if (auto_align) |
462427c4 | 17341 | mips_align (2, 0, l); |
252b5132 RH |
17342 | |
17343 | expression (&ex); | |
a1facbec | 17344 | mips_clear_insn_labels (); |
252b5132 RH |
17345 | |
17346 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17347 | { | |
1661c76c | 17348 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
17349 | ignore_rest_of_line (); |
17350 | } | |
17351 | ||
17352 | p = frag_more (4); | |
17a2f251 | 17353 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17354 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17355 | BFD_RELOC_GPREL32); |
252b5132 RH |
17356 | |
17357 | demand_empty_rest_of_line (); | |
17358 | } | |
17359 | ||
10181a0d | 17360 | static void |
17a2f251 | 17361 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17362 | { |
a8dbcb85 TS |
17363 | segment_info_type *si; |
17364 | struct insn_label_list *l; | |
10181a0d AO |
17365 | expressionS ex; |
17366 | char *p; | |
17367 | ||
17368 | /* When not generating PIC code, this is treated as .dword. */ | |
17369 | if (mips_pic != SVR4_PIC) | |
17370 | { | |
17371 | s_cons (3); | |
17372 | return; | |
17373 | } | |
17374 | ||
a8dbcb85 TS |
17375 | si = seg_info (now_seg); |
17376 | l = si->label_list; | |
7d10b47d | 17377 | mips_emit_delays (); |
10181a0d | 17378 | if (auto_align) |
462427c4 | 17379 | mips_align (3, 0, l); |
10181a0d AO |
17380 | |
17381 | expression (&ex); | |
a1facbec | 17382 | mips_clear_insn_labels (); |
10181a0d AO |
17383 | |
17384 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17385 | { | |
1661c76c | 17386 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
17387 | ignore_rest_of_line (); |
17388 | } | |
17389 | ||
17390 | p = frag_more (8); | |
17a2f251 | 17391 | md_number_to_chars (p, 0, 8); |
a105a300 | 17392 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17393 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17394 | |
17395 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17396 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17397 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17398 | |
17399 | demand_empty_rest_of_line (); | |
17400 | } | |
17401 | ||
a3f278e2 CM |
17402 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17403 | tables. It generates a R_MIPS_EH reloc. */ | |
17404 | ||
17405 | static void | |
17406 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17407 | { | |
17408 | expressionS ex; | |
17409 | char *p; | |
17410 | ||
17411 | mips_emit_delays (); | |
17412 | ||
17413 | expression (&ex); | |
17414 | mips_clear_insn_labels (); | |
17415 | ||
17416 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17417 | { | |
1661c76c | 17418 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
17419 | ignore_rest_of_line (); |
17420 | } | |
17421 | ||
17422 | p = frag_more (4); | |
17423 | md_number_to_chars (p, 0, 4); | |
17424 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 17425 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
17426 | |
17427 | demand_empty_rest_of_line (); | |
17428 | } | |
17429 | ||
252b5132 RH |
17430 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17431 | tables in SVR4 PIC code. */ | |
17432 | ||
17433 | static void | |
17a2f251 | 17434 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17435 | { |
252b5132 RH |
17436 | int reg; |
17437 | ||
919731af | 17438 | file_mips_check_options (); |
17439 | ||
10181a0d AO |
17440 | /* This is ignored when not generating SVR4 PIC code. */ |
17441 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17442 | { |
17443 | s_ignore (0); | |
17444 | return; | |
17445 | } | |
17446 | ||
8a75745d MR |
17447 | mips_mark_labels (); |
17448 | mips_assembling_insn = TRUE; | |
17449 | ||
252b5132 | 17450 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17451 | macro_start (); |
252b5132 | 17452 | reg = tc_get_register (0); |
67c0d1eb | 17453 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17454 | macro_end (); |
252b5132 | 17455 | |
8a75745d | 17456 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17457 | demand_empty_rest_of_line (); |
252b5132 RH |
17458 | } |
17459 | ||
17460 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17461 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17462 | such as generating jalx instructions when needed. We also make |
17463 | them odd for the duration of the assembly, in order to generate the | |
17464 | right sort of code. We will make them even in the adjust_symtab | |
17465 | routine, while leaving them marked. This is convenient for the | |
17466 | debugger and the disassembler. The linker knows to make them odd | |
17467 | again. */ | |
17468 | ||
17469 | static void | |
17a2f251 | 17470 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17471 | { |
7bb01e2d MR |
17472 | file_mips_check_options (); |
17473 | file_ase_mips16 |= mips_opts.mips16; | |
17474 | file_ase_micromips |= mips_opts.micromips; | |
17475 | ||
df58fc94 | 17476 | mips_mark_labels (); |
252b5132 RH |
17477 | |
17478 | demand_empty_rest_of_line (); | |
17479 | } | |
17480 | ||
ba92f887 MR |
17481 | /* Handle the .nan pseudo-op. */ |
17482 | ||
17483 | static void | |
17484 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17485 | { | |
17486 | static const char str_legacy[] = "legacy"; | |
17487 | static const char str_2008[] = "2008"; | |
17488 | size_t i; | |
17489 | ||
17490 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17491 | ||
17492 | if (i == sizeof (str_2008) - 1 | |
17493 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 17494 | mips_nan2008 = 1; |
ba92f887 MR |
17495 | else if (i == sizeof (str_legacy) - 1 |
17496 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
17497 | { |
17498 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
17499 | mips_nan2008 = 0; | |
17500 | else | |
17501 | as_bad (_("`%s' does not support legacy NaN"), | |
17502 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
17503 | } | |
ba92f887 | 17504 | else |
1661c76c | 17505 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
17506 | |
17507 | input_line_pointer += i; | |
17508 | demand_empty_rest_of_line (); | |
17509 | } | |
17510 | ||
754e2bb9 RS |
17511 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17512 | implemented in a transparent way, so that removing them would not | |
17513 | have any effect on the generated instructions. However, s_stab | |
17514 | internally changes the section, so in practice we need to decide | |
17515 | now whether the preceding label marks compressed code. We do not | |
17516 | support changing the compression mode of a label after a .stab* | |
17517 | directive, such as in: | |
17518 | ||
17519 | foo: | |
134c0c8b | 17520 | .stabs ... |
754e2bb9 RS |
17521 | .set mips16 |
17522 | ||
17523 | so the current mode wins. */ | |
252b5132 RH |
17524 | |
17525 | static void | |
17a2f251 | 17526 | s_mips_stab (int type) |
252b5132 | 17527 | { |
42c0794e | 17528 | file_mips_check_options (); |
754e2bb9 | 17529 | mips_mark_labels (); |
252b5132 RH |
17530 | s_stab (type); |
17531 | } | |
17532 | ||
54f4ddb3 | 17533 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17534 | |
17535 | static void | |
17a2f251 | 17536 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17537 | { |
17538 | char *name; | |
17539 | int c; | |
17540 | symbolS *symbolP; | |
17541 | expressionS exp; | |
17542 | ||
d02603dc | 17543 | c = get_symbol_name (&name); |
252b5132 RH |
17544 | symbolP = symbol_find_or_make (name); |
17545 | S_SET_WEAK (symbolP); | |
17546 | *input_line_pointer = c; | |
17547 | ||
d02603dc | 17548 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17549 | |
17550 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17551 | { | |
17552 | if (S_IS_DEFINED (symbolP)) | |
17553 | { | |
20203fb9 | 17554 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17555 | S_GET_NAME (symbolP)); |
17556 | ignore_rest_of_line (); | |
17557 | return; | |
17558 | } | |
bdaaa2e1 | 17559 | |
252b5132 RH |
17560 | if (*input_line_pointer == ',') |
17561 | { | |
17562 | ++input_line_pointer; | |
17563 | SKIP_WHITESPACE (); | |
17564 | } | |
bdaaa2e1 | 17565 | |
252b5132 RH |
17566 | expression (&exp); |
17567 | if (exp.X_op != O_symbol) | |
17568 | { | |
20203fb9 | 17569 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17570 | ignore_rest_of_line (); |
252b5132 RH |
17571 | return; |
17572 | } | |
49309057 | 17573 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17574 | } |
17575 | ||
17576 | demand_empty_rest_of_line (); | |
17577 | } | |
17578 | ||
17579 | /* Parse a register string into a number. Called from the ECOFF code | |
17580 | to parse .frame. The argument is non-zero if this is the frame | |
17581 | register, so that we can record it in mips_frame_reg. */ | |
17582 | ||
17583 | int | |
17a2f251 | 17584 | tc_get_register (int frame) |
252b5132 | 17585 | { |
707bfff6 | 17586 | unsigned int reg; |
252b5132 RH |
17587 | |
17588 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17589 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17590 | reg = 0; | |
252b5132 | 17591 | if (frame) |
7a621144 DJ |
17592 | { |
17593 | mips_frame_reg = reg != 0 ? reg : SP; | |
17594 | mips_frame_reg_valid = 1; | |
17595 | mips_cprestore_valid = 0; | |
17596 | } | |
252b5132 RH |
17597 | return reg; |
17598 | } | |
17599 | ||
17600 | valueT | |
17a2f251 | 17601 | md_section_align (asection *seg, valueT addr) |
252b5132 | 17602 | { |
fd361982 | 17603 | int align = bfd_section_alignment (seg); |
252b5132 | 17604 | |
f3ded42a RS |
17605 | /* We don't need to align ELF sections to the full alignment. |
17606 | However, Irix 5 may prefer that we align them at least to a 16 | |
17607 | byte boundary. We don't bother to align the sections if we | |
17608 | are targeted for an embedded system. */ | |
17609 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17610 | return addr; | |
17611 | if (align > 4) | |
17612 | align = 4; | |
252b5132 | 17613 | |
8d3842cd | 17614 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17615 | } |
17616 | ||
17617 | /* Utility routine, called from above as well. If called while the | |
17618 | input file is still being read, it's only an approximation. (For | |
17619 | example, a symbol may later become defined which appeared to be | |
17620 | undefined earlier.) */ | |
17621 | ||
17622 | static int | |
17a2f251 | 17623 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17624 | { |
17625 | if (sym == 0) | |
17626 | return 0; | |
17627 | ||
4d0d148d | 17628 | if (g_switch_value > 0) |
252b5132 RH |
17629 | { |
17630 | const char *symname; | |
17631 | int change; | |
17632 | ||
c9914766 | 17633 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17634 | register. It can be if it is smaller than the -G size or if |
17635 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17636 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17637 | they can. */ |
17638 | symname = S_GET_NAME (sym); | |
17639 | if (symname != (const char *) NULL | |
17640 | && (strcmp (symname, "eprol") == 0 | |
17641 | || strcmp (symname, "etext") == 0 | |
17642 | || strcmp (symname, "_gp") == 0 | |
17643 | || strcmp (symname, "edata") == 0 | |
17644 | || strcmp (symname, "_fbss") == 0 | |
17645 | || strcmp (symname, "_fdata") == 0 | |
17646 | || strcmp (symname, "_ftext") == 0 | |
17647 | || strcmp (symname, "end") == 0 | |
17648 | || strcmp (symname, "_gp_disp") == 0)) | |
17649 | change = 1; | |
17650 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17651 | && (0 | |
17652 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17653 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17654 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17655 | <= g_switch_value)) | |
252b5132 RH |
17656 | #endif |
17657 | /* We must defer this decision until after the whole | |
17658 | file has been read, since there might be a .extern | |
17659 | after the first use of this symbol. */ | |
17660 | || (before_relaxing | |
17661 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17662 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17663 | #endif |
17664 | && S_GET_VALUE (sym) == 0) | |
17665 | || (S_GET_VALUE (sym) != 0 | |
17666 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17667 | change = 0; | |
17668 | else | |
17669 | { | |
17670 | const char *segname; | |
17671 | ||
17672 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17673 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17674 | && strcmp (segname, ".lit4") != 0); |
17675 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17676 | && strcmp (segname, ".sbss") != 0 |
17677 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17678 | && strncmp (segname, ".sbss.", 6) != 0 |
17679 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17680 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17681 | } |
17682 | return change; | |
17683 | } | |
17684 | else | |
c9914766 | 17685 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17686 | return 1; |
17687 | } | |
17688 | ||
5919d012 RS |
17689 | |
17690 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17691 | ||
17692 | static bfd_boolean | |
9e009953 | 17693 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17694 | { |
17695 | asection *symsec; | |
5919d012 RS |
17696 | |
17697 | /* Handle the case of a symbol equated to another symbol. */ | |
17698 | while (symbol_equated_reloc_p (sym)) | |
17699 | { | |
17700 | symbolS *n; | |
17701 | ||
5f0fe04b | 17702 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17703 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17704 | if (n == sym) | |
17705 | break; | |
17706 | sym = n; | |
17707 | } | |
17708 | ||
df1f3cda DD |
17709 | if (symbol_section_p (sym)) |
17710 | return TRUE; | |
17711 | ||
5919d012 RS |
17712 | symsec = S_GET_SEGMENT (sym); |
17713 | ||
5919d012 | 17714 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17715 | return (!bfd_is_und_section (symsec) |
17716 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17717 | && !bfd_is_com_section (symsec) |
5919d012 | 17718 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17719 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17720 | } |
14f72d45 MR |
17721 | \f |
17722 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17723 | convert a section-relative value VAL to the equivalent PC-relative | |
17724 | value. */ | |
17725 | ||
17726 | static offsetT | |
17727 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17728 | offsetT val, long stretch) | |
17729 | { | |
17730 | fragS *sym_frag; | |
17731 | addressT addr; | |
17732 | ||
17733 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17734 | ||
17735 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17736 | ||
17737 | /* If the relax_marker of the symbol fragment differs from the | |
17738 | relax_marker of this fragment, we have not yet adjusted the | |
17739 | symbol fragment fr_address. We want to add in STRETCH in | |
17740 | order to get a better estimate of the address. This | |
17741 | particularly matters because of the shift bits. */ | |
17742 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17743 | { | |
17744 | fragS *f; | |
17745 | ||
17746 | /* Adjust stretch for any alignment frag. Note that if have | |
17747 | been expanding the earlier code, the symbol may be | |
17748 | defined in what appears to be an earlier frag. FIXME: | |
17749 | This doesn't handle the fr_subtype field, which specifies | |
17750 | a maximum number of bytes to skip when doing an | |
17751 | alignment. */ | |
17752 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17753 | { | |
17754 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17755 | { | |
17756 | if (stretch < 0) | |
17757 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17758 | else | |
17759 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17760 | if (stretch == 0) | |
17761 | break; | |
17762 | } | |
17763 | } | |
17764 | if (f != NULL) | |
17765 | val += stretch; | |
17766 | } | |
17767 | ||
17768 | addr = fragp->fr_address + fragp->fr_fix; | |
17769 | ||
17770 | /* The base address rules are complicated. The base address of | |
17771 | a branch is the following instruction. The base address of a | |
17772 | PC relative load or add is the instruction itself, but if it | |
17773 | is in a delay slot (in which case it can not be extended) use | |
17774 | the address of the instruction whose delay slot it is in. */ | |
17775 | if (pcrel_op->include_isa_bit) | |
17776 | { | |
17777 | addr += 2; | |
17778 | ||
17779 | /* If we are currently assuming that this frag should be | |
17780 | extended, then the current address is two bytes higher. */ | |
17781 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17782 | addr += 2; | |
17783 | ||
17784 | /* Ignore the low bit in the target, since it will be set | |
17785 | for a text label. */ | |
17786 | val &= -2; | |
17787 | } | |
17788 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17789 | addr -= 4; | |
17790 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17791 | addr -= 2; | |
5919d012 | 17792 | |
14f72d45 MR |
17793 | val -= addr & -(1 << pcrel_op->align_log2); |
17794 | ||
17795 | return val; | |
17796 | } | |
5919d012 | 17797 | |
252b5132 RH |
17798 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17799 | extended opcode. SEC is the section the frag is in. */ | |
17800 | ||
17801 | static int | |
17a2f251 | 17802 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17803 | { |
3ccad066 | 17804 | const struct mips_int_operand *operand; |
252b5132 | 17805 | offsetT val; |
252b5132 | 17806 | segT symsec; |
14f72d45 | 17807 | int type; |
252b5132 RH |
17808 | |
17809 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17810 | return 0; | |
17811 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17812 | return 1; | |
17813 | ||
88a7ef16 | 17814 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17815 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17816 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17817 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17818 | || (operand->root.type == OP_PCREL | |
17819 | ? sec != symsec | |
17820 | : !bfd_is_abs_section (symsec))) | |
17821 | return 1; | |
252b5132 | 17822 | |
88a7ef16 | 17823 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17824 | |
3ccad066 | 17825 | if (operand->root.type == OP_PCREL) |
252b5132 | 17826 | { |
3ccad066 | 17827 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17828 | offsetT maxtiny; |
252b5132 | 17829 | |
1425c41d | 17830 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17831 | return 1; |
252b5132 | 17832 | |
88a7ef16 | 17833 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17834 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17835 | |
17836 | /* If any of the shifted bits are set, we must use an extended | |
17837 | opcode. If the address depends on the size of this | |
17838 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17839 | use an extended opcode. */ |
17840 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17841 | { |
17842 | fragp->fr_subtype = | |
1425c41d | 17843 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17844 | return 1; |
17845 | } | |
17846 | ||
17847 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17848 | is precisely the next value above maxtiny, then there is a |
17849 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17850 | la $4,foo |
17851 | .skip 1020 | |
17852 | .align 2 | |
17853 | foo: | |
17854 | In this case when the la is extended, foo is 0x3fc bytes | |
17855 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17856 | the la must be extended. To avoid this loop, we mark the | |
17857 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17858 | extended with the next value above maxtiny. */ |
17859 | maxtiny = mips_int_operand_max (operand); | |
17860 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17861 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17862 | { |
17863 | fragp->fr_subtype = | |
1425c41d | 17864 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17865 | return 1; |
17866 | } | |
17867 | } | |
252b5132 | 17868 | |
3ccad066 | 17869 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17870 | } |
17871 | ||
8507b6e7 MR |
17872 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17873 | macro expansion. SEC is the section the frag is in. We only | |
17874 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17875 | non-PIC code using 32-bit addressing. */ | |
17876 | ||
17877 | static int | |
17878 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17879 | { | |
17880 | const struct mips_pcrel_operand *pcrel_op; | |
17881 | const struct mips_int_operand *operand; | |
17882 | offsetT val; | |
17883 | segT symsec; | |
17884 | int type; | |
17885 | ||
17886 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17887 | ||
17888 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17889 | return 0; | |
17890 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17891 | return 0; | |
17892 | ||
17893 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17894 | switch (type) | |
17895 | { | |
17896 | case 'A': | |
17897 | case 'B': | |
17898 | case 'E': | |
17899 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17900 | if (bfd_is_abs_section (symsec)) | |
17901 | return 1; | |
17902 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17903 | return 0; | |
17904 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17905 | return 1; | |
17906 | ||
17907 | operand = mips16_immed_operand (type, TRUE); | |
17908 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17909 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17910 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17911 | ||
17912 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17913 | ||
17914 | default: | |
17915 | return 0; | |
17916 | } | |
17917 | } | |
17918 | ||
4a6a3df4 AO |
17919 | /* Compute the length of a branch sequence, and adjust the |
17920 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17921 | worst-case length is computed, with UPDATE being used to indicate | |
17922 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17923 | branch is to be computed. */ | |
17924 | static int | |
17a2f251 | 17925 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17926 | { |
b34976b6 | 17927 | bfd_boolean toofar; |
4a6a3df4 AO |
17928 | int length; |
17929 | ||
17930 | if (fragp | |
17931 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17932 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17933 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17934 | { | |
17935 | addressT addr; | |
17936 | offsetT val; | |
17937 | ||
17938 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17939 | ||
17940 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17941 | ||
17942 | val -= addr; | |
17943 | ||
17944 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17945 | } | |
4a6a3df4 | 17946 | else |
c1f61bd2 MR |
17947 | /* If the symbol is not defined or it's in a different segment, |
17948 | we emit the long sequence. */ | |
b34976b6 | 17949 | toofar = TRUE; |
4a6a3df4 AO |
17950 | |
17951 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17952 | fragp->fr_subtype | |
66b3e8da | 17953 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17954 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17955 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17956 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17957 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17958 | toofar); | |
17959 | ||
17960 | length = 4; | |
17961 | if (toofar) | |
17962 | { | |
17963 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17964 | length += 8; | |
17965 | ||
ce8ad872 | 17966 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17967 | { |
17968 | /* Additional space for PIC loading of target address. */ | |
17969 | length += 8; | |
17970 | if (mips_opts.isa == ISA_MIPS1) | |
17971 | /* Additional space for $at-stabilizing nop. */ | |
17972 | length += 4; | |
17973 | } | |
17974 | ||
17975 | /* If branch is conditional. */ | |
17976 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17977 | length += 8; | |
17978 | } | |
b34976b6 | 17979 | |
4a6a3df4 AO |
17980 | return length; |
17981 | } | |
17982 | ||
7bd374a4 MR |
17983 | /* Get a FRAG's branch instruction delay slot size, either from the |
17984 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
17985 | or SHORT_INSN_SIZE otherwise. */ | |
17986 | ||
17987 | static int | |
17988 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
17989 | { | |
17990 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
17991 | ||
17992 | if (al) | |
17993 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
17994 | else | |
17995 | return short_insn_size; | |
17996 | } | |
17997 | ||
df58fc94 RS |
17998 | /* Compute the length of a branch sequence, and adjust the |
17999 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
18000 | worst-case length is computed, with UPDATE being used to indicate | |
18001 | whether an unconditional (-1), or regular (0) branch is to be | |
18002 | computed. */ | |
18003 | ||
18004 | static int | |
18005 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
18006 | { | |
7bd374a4 MR |
18007 | bfd_boolean insn32 = TRUE; |
18008 | bfd_boolean nods = TRUE; | |
ce8ad872 | 18009 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
18010 | bfd_boolean al = TRUE; |
18011 | int short_insn_size; | |
df58fc94 RS |
18012 | bfd_boolean toofar; |
18013 | int length; | |
18014 | ||
7bd374a4 MR |
18015 | if (fragp) |
18016 | { | |
18017 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
18018 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 18019 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
18020 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18021 | } | |
18022 | short_insn_size = insn32 ? 4 : 2; | |
18023 | ||
df58fc94 RS |
18024 | if (fragp |
18025 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 18026 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
18027 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
18028 | { | |
18029 | addressT addr; | |
18030 | offsetT val; | |
18031 | ||
18032 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
18033 | /* Ignore the low bit in the target, since it will be set | |
18034 | for a text label. */ | |
18035 | if ((val & 1) != 0) | |
18036 | --val; | |
18037 | ||
18038 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
18039 | ||
18040 | val -= addr; | |
18041 | ||
18042 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
18043 | } | |
df58fc94 | 18044 | else |
c1f61bd2 MR |
18045 | /* If the symbol is not defined or it's in a different segment, |
18046 | we emit the long sequence. */ | |
df58fc94 RS |
18047 | toofar = TRUE; |
18048 | ||
18049 | if (fragp && update | |
18050 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18051 | fragp->fr_subtype = (toofar | |
18052 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
18053 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
18054 | ||
18055 | length = 4; | |
18056 | if (toofar) | |
18057 | { | |
18058 | bfd_boolean compact_known = fragp != NULL; | |
18059 | bfd_boolean compact = FALSE; | |
18060 | bfd_boolean uncond; | |
18061 | ||
df58fc94 | 18062 | if (fragp) |
8484fb75 MR |
18063 | { |
18064 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
18065 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 18066 | } |
df58fc94 RS |
18067 | else |
18068 | uncond = update < 0; | |
18069 | ||
18070 | /* If label is out of range, we turn branch <br>: | |
18071 | ||
18072 | <br> label # 4 bytes | |
18073 | 0: | |
18074 | ||
18075 | into: | |
18076 | ||
18077 | j label # 4 bytes | |
8484fb75 MR |
18078 | nop # 2/4 bytes if |
18079 | # compact && (!PIC || insn32) | |
df58fc94 RS |
18080 | 0: |
18081 | */ | |
ce8ad872 | 18082 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 18083 | length += short_insn_size; |
df58fc94 RS |
18084 | |
18085 | /* If assembling PIC code, we further turn: | |
18086 | ||
18087 | j label # 4 bytes | |
18088 | ||
18089 | into: | |
18090 | ||
18091 | lw/ld at, %got(label)(gp) # 4 bytes | |
18092 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 18093 | jr/c at # 2/4 bytes |
df58fc94 | 18094 | */ |
ce8ad872 | 18095 | if (pic) |
8484fb75 | 18096 | length += 4 + short_insn_size; |
df58fc94 | 18097 | |
7bd374a4 MR |
18098 | /* Add an extra nop if the jump has no compact form and we need |
18099 | to fill the delay slot. */ | |
ce8ad872 | 18100 | if ((!pic || al) && nods) |
7bd374a4 MR |
18101 | length += (fragp |
18102 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
18103 | : short_insn_size); | |
18104 | ||
df58fc94 RS |
18105 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
18106 | ||
18107 | <brneg> 0f # 4 bytes | |
8484fb75 | 18108 | nop # 2/4 bytes if !compact |
df58fc94 RS |
18109 | */ |
18110 | if (!uncond) | |
8484fb75 | 18111 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 18112 | } |
7bd374a4 MR |
18113 | else if (nods) |
18114 | { | |
18115 | /* Add an extra nop to fill the delay slot. */ | |
18116 | gas_assert (fragp); | |
18117 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
18118 | } | |
df58fc94 RS |
18119 | |
18120 | return length; | |
18121 | } | |
18122 | ||
18123 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
18124 | bit accordingly. */ | |
18125 | ||
18126 | static int | |
18127 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
18128 | { | |
18129 | bfd_boolean toofar; | |
18130 | ||
df58fc94 RS |
18131 | if (fragp |
18132 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 18133 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
18134 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
18135 | { | |
18136 | addressT addr; | |
18137 | offsetT val; | |
18138 | int type; | |
18139 | ||
18140 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
18141 | /* Ignore the low bit in the target, since it will be set | |
18142 | for a text label. */ | |
18143 | if ((val & 1) != 0) | |
18144 | --val; | |
18145 | ||
18146 | /* Assume this is a 2-byte branch. */ | |
18147 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
18148 | ||
18149 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
18150 | long branches. */ | |
18151 | ||
18152 | val -= addr; | |
18153 | ||
18154 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
18155 | if (type == 'D') | |
18156 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
18157 | else if (type == 'E') | |
18158 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
18159 | else | |
18160 | abort (); | |
18161 | } | |
18162 | else | |
18163 | /* If the symbol is not defined or it's in a different segment, | |
18164 | we emit a normal 32-bit branch. */ | |
18165 | toofar = TRUE; | |
18166 | ||
18167 | if (fragp && update | |
18168 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18169 | fragp->fr_subtype | |
18170 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
18171 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
18172 | ||
18173 | if (toofar) | |
18174 | return 4; | |
18175 | ||
18176 | return 2; | |
18177 | } | |
18178 | ||
252b5132 RH |
18179 | /* Estimate the size of a frag before relaxing. Unless this is the |
18180 | mips16, we are not really relaxing here, and the final size is | |
18181 | encoded in the subtype information. For the mips16, we have to | |
18182 | decide whether we are using an extended opcode or not. */ | |
18183 | ||
252b5132 | 18184 | int |
17a2f251 | 18185 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 18186 | { |
5919d012 | 18187 | int change; |
252b5132 | 18188 | |
4a6a3df4 AO |
18189 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18190 | { | |
18191 | ||
b34976b6 AM |
18192 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
18193 | ||
4a6a3df4 AO |
18194 | return fragp->fr_var; |
18195 | } | |
18196 | ||
252b5132 | 18197 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
18198 | { |
18199 | /* We don't want to modify the EXTENDED bit here; it might get us | |
18200 | into infinite loops. We change it only in mips_relax_frag(). */ | |
18201 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
25499ac7 | 18202 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; |
8507b6e7 MR |
18203 | else |
18204 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
18205 | } | |
252b5132 | 18206 | |
df58fc94 RS |
18207 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18208 | { | |
18209 | int length = 4; | |
18210 | ||
18211 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18212 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
18213 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18214 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
18215 | fragp->fr_var = length; | |
18216 | ||
18217 | return length; | |
18218 | } | |
18219 | ||
ce8ad872 | 18220 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
18221 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
18222 | change = 0; | |
ce8ad872 MR |
18223 | else if (RELAX_PIC (fragp->fr_subtype)) |
18224 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 18225 | else |
ce8ad872 | 18226 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
18227 | |
18228 | if (change) | |
18229 | { | |
4d7206a2 | 18230 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 18231 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 18232 | } |
4d7206a2 RS |
18233 | else |
18234 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
18235 | } |
18236 | ||
18237 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 18238 | should be converted into a reloc against a section. */ |
252b5132 RH |
18239 | |
18240 | int | |
17a2f251 | 18241 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 18242 | { |
252b5132 RH |
18243 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
18244 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
18245 | return 0; | |
a161fe53 | 18246 | |
252b5132 RH |
18247 | if (fixp->fx_addsy == NULL) |
18248 | return 1; | |
a161fe53 | 18249 | |
2f0c68f2 CM |
18250 | /* Allow relocs used for EH tables. */ |
18251 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
18252 | return 1; | |
18253 | ||
de7e6852 RS |
18254 | /* If symbol SYM is in a mergeable section, relocations of the form |
18255 | SYM + 0 can usually be made section-relative. The mergeable data | |
18256 | is then identified by the section offset rather than by the symbol. | |
18257 | ||
18258 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 18259 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
18260 | need to recalculate the complete offset in order to correctly identify |
18261 | the merge data. | |
18262 | ||
33eaf5de | 18263 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
18264 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
18265 | placed anywhere. Rather than break backwards compatibility by changing | |
18266 | this, it seems better not to force the issue, and instead keep the | |
18267 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 18268 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 18269 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
18270 | && HAVE_IN_PLACE_ADDENDS |
18271 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
18272 | return 0; | |
18273 | ||
97f50151 MR |
18274 | /* There is no place to store an in-place offset for JALR relocations. */ |
18275 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
18276 | return 0; | |
18277 | ||
18278 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 18279 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
18280 | start address of the symbol's containing section. |
18281 | ||
18282 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
18283 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 18284 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 18285 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
18286 | return 0; |
18287 | ||
b314ec0e RS |
18288 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
18289 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
18290 | relocations against MIPS16 functions; in this case, the stub becomes | |
18291 | the function's canonical address. | |
18292 | ||
18293 | Floating-point stubs are stored in unique .mips16.call.* or | |
18294 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
18295 | the first relocation in section S must be against F; this is how the | |
18296 | linker determines the target function. All relocations that might | |
18297 | resolve to T must also be against F. We therefore have the following | |
18298 | restrictions, which are given in an intentionally-redundant way: | |
18299 | ||
18300 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
18301 | symbols. | |
18302 | ||
18303 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
18304 | if that stub might be used. | |
18305 | ||
18306 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
18307 | symbols. | |
18308 | ||
18309 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
18310 | that stub might be used. | |
18311 | ||
18312 | There is a further restriction: | |
18313 | ||
df58fc94 | 18314 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 18315 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
18316 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
18317 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
18318 | against MIPS16 or microMIPS symbols because we need to keep the | |
18319 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
18320 | detection and JAL or BAL to JALX instruction conversion in the |
18321 | linker. | |
b314ec0e | 18322 | |
df58fc94 | 18323 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 18324 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 18325 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
18326 | |
18327 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18328 | relocation against some symbol R, no relocation against R may be | |
18329 | reduced. (Note that this deals with (2) as well as (1) because | |
18330 | relocations against global symbols will never be reduced on ELF | |
18331 | targets.) This approach is a little simpler than trying to detect | |
18332 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18333 | that we have for MIPS16 symbols. */ | |
f3ded42a | 18334 | if (fixp->fx_subsy == NULL |
30c09090 | 18335 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 18336 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
18337 | && (jmp_reloc_p (fixp->fx_r_type) |
18338 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 18339 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 18340 | return 0; |
a161fe53 | 18341 | |
252b5132 RH |
18342 | return 1; |
18343 | } | |
18344 | ||
18345 | /* Translate internal representation of relocation info to BFD target | |
18346 | format. */ | |
18347 | ||
18348 | arelent ** | |
17a2f251 | 18349 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18350 | { |
18351 | static arelent *retval[4]; | |
18352 | arelent *reloc; | |
18353 | bfd_reloc_code_real_type code; | |
18354 | ||
4b0cff4e | 18355 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
18356 | reloc = retval[0] = XCNEW (arelent); |
18357 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 18358 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
18359 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18360 | ||
bad36eac DJ |
18361 | if (fixp->fx_pcrel) |
18362 | { | |
df58fc94 | 18363 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 18364 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
18365 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
18366 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 18367 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
18368 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
18369 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
18370 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
18371 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
18372 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
18373 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
18374 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
18375 | |
18376 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18377 | Relocations want only the symbol offset. */ | |
51f6035b MR |
18378 | switch (fixp->fx_r_type) |
18379 | { | |
18380 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
18381 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
18382 | break; | |
18383 | default: | |
18384 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
18385 | break; | |
18386 | } | |
bad36eac | 18387 | } |
17c6c9d9 MR |
18388 | else if (HAVE_IN_PLACE_ADDENDS |
18389 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
18390 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
18391 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
18392 | { | |
18393 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
18394 | addend accordingly. */ | |
18395 | reloc->addend = fixp->fx_addnumber >> 1; | |
18396 | } | |
bad36eac DJ |
18397 | else |
18398 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18399 | |
438c16b8 TS |
18400 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18401 | entry to be used in the relocation's section offset. */ | |
18402 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18403 | { |
18404 | reloc->address = reloc->addend; | |
18405 | reloc->addend = 0; | |
18406 | } | |
18407 | ||
252b5132 | 18408 | code = fixp->fx_r_type; |
252b5132 | 18409 | |
bad36eac | 18410 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18411 | if (reloc->howto == NULL) |
18412 | { | |
18413 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
18414 | _("cannot represent %s relocation in this object file" |
18415 | " format"), | |
252b5132 RH |
18416 | bfd_get_reloc_code_name (code)); |
18417 | retval[0] = NULL; | |
18418 | } | |
18419 | ||
18420 | return retval; | |
18421 | } | |
18422 | ||
18423 | /* Relax a machine dependent frag. This returns the amount by which | |
18424 | the current size of the frag should change. */ | |
18425 | ||
18426 | int | |
17a2f251 | 18427 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18428 | { |
4a6a3df4 AO |
18429 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18430 | { | |
18431 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18432 | |
18433 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18434 | |
18435 | return fragp->fr_var - old_var; | |
18436 | } | |
18437 | ||
df58fc94 RS |
18438 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18439 | { | |
18440 | offsetT old_var = fragp->fr_var; | |
18441 | offsetT new_var = 4; | |
18442 | ||
18443 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18444 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18445 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18446 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18447 | fragp->fr_var = new_var; | |
18448 | ||
18449 | return new_var - old_var; | |
18450 | } | |
18451 | ||
252b5132 RH |
18452 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18453 | return 0; | |
18454 | ||
8507b6e7 | 18455 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 18456 | { |
8507b6e7 MR |
18457 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
18458 | { | |
18459 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
25499ac7 | 18460 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; |
8507b6e7 MR |
18461 | } |
18462 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18463 | { | |
18464 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18465 | return -2; | |
18466 | } | |
18467 | else | |
18468 | return 0; | |
18469 | } | |
18470 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
18471 | { | |
18472 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
18473 | { | |
18474 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
18475 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
25499ac7 | 18476 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; |
8507b6e7 MR |
18477 | } |
18478 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18479 | { | |
18480 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18481 | return 2; | |
18482 | } | |
18483 | else | |
252b5132 | 18484 | return 0; |
252b5132 RH |
18485 | } |
18486 | else | |
18487 | { | |
8507b6e7 | 18488 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 18489 | return 0; |
8507b6e7 MR |
18490 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
18491 | { | |
18492 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18493 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18494 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; |
8507b6e7 MR |
18495 | } |
18496 | else | |
18497 | { | |
18498 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18499 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; |
8507b6e7 | 18500 | } |
252b5132 RH |
18501 | } |
18502 | ||
18503 | return 0; | |
18504 | } | |
18505 | ||
18506 | /* Convert a machine dependent frag. */ | |
18507 | ||
18508 | void | |
17a2f251 | 18509 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18510 | { |
4a6a3df4 AO |
18511 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18512 | { | |
4d68580a | 18513 | char *buf; |
4a6a3df4 | 18514 | unsigned long insn; |
4a6a3df4 | 18515 | fixS *fixp; |
b34976b6 | 18516 | |
4d68580a RS |
18517 | buf = fragp->fr_literal + fragp->fr_fix; |
18518 | insn = read_insn (buf); | |
b34976b6 | 18519 | |
4a6a3df4 AO |
18520 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18521 | { | |
18522 | /* We generate a fixup instead of applying it right now | |
18523 | because, if there are linker relaxations, we're going to | |
18524 | need the relocations. */ | |
bbd27b76 MR |
18525 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18526 | fragp->fr_symbol, fragp->fr_offset, | |
18527 | TRUE, BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18528 | fixp->fx_file = fragp->fr_file; |
18529 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18530 | |
4d68580a | 18531 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18532 | } |
18533 | else | |
18534 | { | |
18535 | int i; | |
18536 | ||
18537 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18538 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18539 | |
18540 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18541 | goto uncond; | |
18542 | ||
18543 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18544 | { | |
18545 | /* Reverse the branch. */ | |
18546 | switch ((insn >> 28) & 0xf) | |
18547 | { | |
18548 | case 4: | |
56d438b1 CF |
18549 | if ((insn & 0xff000000) == 0x47000000 |
18550 | || (insn & 0xff600000) == 0x45600000) | |
18551 | { | |
18552 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18553 | reversed by tweaking bit 23. */ | |
18554 | insn ^= 0x00800000; | |
18555 | } | |
18556 | else | |
18557 | { | |
18558 | /* bc[0-3][tf]l? instructions can have the condition | |
18559 | reversed by tweaking a single TF bit, and their | |
18560 | opcodes all have 0x4???????. */ | |
18561 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18562 | insn ^= 0x00010000; | |
18563 | } | |
4a6a3df4 AO |
18564 | break; |
18565 | ||
18566 | case 0: | |
18567 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18568 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18569 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18570 | insn ^= 0x00010000; |
18571 | break; | |
b34976b6 | 18572 | |
4a6a3df4 AO |
18573 | case 1: |
18574 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18575 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18576 | insn ^= 0x04000000; |
18577 | break; | |
18578 | ||
18579 | default: | |
18580 | abort (); | |
18581 | } | |
18582 | } | |
18583 | ||
18584 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18585 | { | |
18586 | /* Clear the and-link bit. */ | |
9c2799c2 | 18587 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18588 | |
54f4ddb3 TS |
18589 | /* bltzal 0x04100000 bgezal 0x04110000 |
18590 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18591 | insn &= ~0x00100000; |
18592 | } | |
18593 | ||
18594 | /* Branch over the branch (if the branch was likely) or the | |
18595 | full jump (not likely case). Compute the offset from the | |
18596 | current instruction to branch to. */ | |
18597 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18598 | i = 16; | |
18599 | else | |
18600 | { | |
18601 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18602 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18603 | /* How many bytes in instructions from here to the end? */ |
18604 | i = fragp->fr_var - i; | |
18605 | } | |
18606 | /* Convert to instruction count. */ | |
18607 | i >>= 2; | |
18608 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18609 | i--; |
4a6a3df4 AO |
18610 | insn |= i; |
18611 | /* Branch over the jump. */ | |
4d68580a | 18612 | buf = write_insn (buf, insn); |
4a6a3df4 | 18613 | |
54f4ddb3 | 18614 | /* nop */ |
4d68580a | 18615 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18616 | |
18617 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18618 | { | |
18619 | /* beql $0, $0, 2f */ | |
18620 | insn = 0x50000000; | |
18621 | /* Compute the PC offset from the current instruction to | |
18622 | the end of the variable frag. */ | |
18623 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18624 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18625 | /* How many bytes in instructions from here to the end? */ |
18626 | i = fragp->fr_var - i; | |
18627 | /* Convert to instruction count. */ | |
18628 | i >>= 2; | |
18629 | /* Don't decrement i, because we want to branch over the | |
18630 | delay slot. */ | |
4a6a3df4 | 18631 | insn |= i; |
4a6a3df4 | 18632 | |
4d68580a RS |
18633 | buf = write_insn (buf, insn); |
18634 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18635 | } |
18636 | ||
18637 | uncond: | |
ce8ad872 | 18638 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18639 | { |
18640 | /* j or jal. */ | |
18641 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18642 | ? 0x0c000000 : 0x08000000); | |
4a6a3df4 | 18643 | |
bbd27b76 MR |
18644 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18645 | fragp->fr_symbol, fragp->fr_offset, | |
18646 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18647 | fixp->fx_file = fragp->fr_file; |
18648 | fixp->fx_line = fragp->fr_line; | |
18649 | ||
4d68580a | 18650 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18651 | } |
18652 | else | |
18653 | { | |
66b3e8da MR |
18654 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18655 | ||
4a6a3df4 | 18656 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18657 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18658 | insn |= at << OP_SH_RT; | |
4a6a3df4 | 18659 | |
bbd27b76 MR |
18660 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18661 | fragp->fr_symbol, fragp->fr_offset, | |
18662 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18663 | fixp->fx_file = fragp->fr_file; |
18664 | fixp->fx_line = fragp->fr_line; | |
18665 | ||
4d68580a | 18666 | buf = write_insn (buf, insn); |
b34976b6 | 18667 | |
4a6a3df4 | 18668 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18669 | /* nop */ |
18670 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18671 | |
18672 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18673 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18674 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18675 | |
bbd27b76 MR |
18676 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18677 | fragp->fr_symbol, fragp->fr_offset, | |
18678 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18679 | fixp->fx_file = fragp->fr_file; |
18680 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18681 | |
4d68580a | 18682 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18683 | |
18684 | /* j(al)r $at. */ | |
18685 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18686 | insn = 0x0000f809; |
4a6a3df4 | 18687 | else |
66b3e8da MR |
18688 | insn = 0x00000008; |
18689 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18690 | |
4d68580a | 18691 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18692 | } |
18693 | } | |
18694 | ||
4a6a3df4 | 18695 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18696 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18697 | return; |
18698 | } | |
18699 | ||
df58fc94 RS |
18700 | /* Relax microMIPS branches. */ |
18701 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18702 | { | |
4d68580a | 18703 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18704 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18705 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18706 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18707 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18708 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18709 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18710 | bfd_boolean short_ds; |
df58fc94 | 18711 | unsigned long insn; |
df58fc94 RS |
18712 | fixS *fixp; |
18713 | ||
df58fc94 RS |
18714 | fragp->fr_fix += fragp->fr_var; |
18715 | ||
18716 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18717 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18718 | { | |
18719 | /* We generate a fixup instead of applying it right now, | |
18720 | because if there is linker relaxation, we're going to | |
18721 | need the relocations. */ | |
834a65aa MR |
18722 | switch (type) |
18723 | { | |
18724 | case 'D': | |
18725 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18726 | fragp->fr_symbol, fragp->fr_offset, | |
18727 | TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
18728 | break; | |
18729 | case 'E': | |
18730 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18731 | fragp->fr_symbol, fragp->fr_offset, | |
18732 | TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
18733 | break; | |
18734 | default: | |
18735 | abort (); | |
18736 | } | |
df58fc94 RS |
18737 | |
18738 | fixp->fx_file = fragp->fr_file; | |
18739 | fixp->fx_line = fragp->fr_line; | |
18740 | ||
18741 | /* These relocations can have an addend that won't fit in | |
18742 | 2 octets. */ | |
18743 | fixp->fx_no_overflow = 1; | |
18744 | ||
18745 | return; | |
18746 | } | |
18747 | ||
2309ddf2 | 18748 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18749 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18750 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18751 | { | |
18752 | /* We generate a fixup instead of applying it right now, | |
18753 | because if there is linker relaxation, we're going to | |
18754 | need the relocations. */ | |
bbd27b76 MR |
18755 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18756 | fragp->fr_symbol, fragp->fr_offset, | |
18757 | TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18758 | fixp->fx_file = fragp->fr_file; |
18759 | fixp->fx_line = fragp->fr_line; | |
18760 | ||
18761 | if (type == 0) | |
7bd374a4 MR |
18762 | { |
18763 | insn = read_compressed_insn (buf, 4); | |
18764 | buf += 4; | |
18765 | ||
18766 | if (nods) | |
18767 | { | |
18768 | /* Check the short-delay-slot bit. */ | |
18769 | if (!al || (insn & 0x02000000) != 0) | |
18770 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18771 | else | |
18772 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18773 | } | |
18774 | ||
18775 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18776 | return; | |
18777 | } | |
df58fc94 RS |
18778 | } |
18779 | ||
18780 | /* Relax 16-bit branches to 32-bit branches. */ | |
18781 | if (type != 0) | |
18782 | { | |
4d68580a | 18783 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18784 | |
18785 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18786 | insn = 0x94000000; /* beq */ | |
18787 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18788 | { | |
18789 | unsigned long regno; | |
18790 | ||
18791 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18792 | regno = micromips_to_32_reg_d_map [regno]; | |
18793 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18794 | insn |= regno << MICROMIPSOP_SH_RS; | |
18795 | } | |
18796 | else | |
18797 | abort (); | |
18798 | ||
18799 | /* Nothing else to do, just write it out. */ | |
18800 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18801 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18802 | { | |
4d68580a | 18803 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18804 | if (nods) |
18805 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18806 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18807 | return; |
18808 | } | |
18809 | } | |
18810 | else | |
4d68580a | 18811 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18812 | |
18813 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18814 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18815 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18816 | |
2309ddf2 | 18817 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18818 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18819 | |
18820 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18821 | { | |
18822 | symbolS *l; | |
18823 | ||
18824 | /* Reverse the branch. */ | |
18825 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18826 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18827 | insn ^= 0x20000000; | |
18828 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18829 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18830 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18831 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18832 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18833 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18834 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18835 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18836 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18837 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18838 | insn ^= 0x00400000; | |
18839 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18840 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18841 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18842 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18843 | insn ^= 0x00200000; | |
56d438b1 CF |
18844 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18845 | BNZ.df */ | |
18846 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18847 | BNZ.V */ | |
18848 | insn ^= 0x00800000; | |
df58fc94 RS |
18849 | else |
18850 | abort (); | |
18851 | ||
18852 | if (al) | |
18853 | { | |
18854 | /* Clear the and-link and short-delay-slot bits. */ | |
18855 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18856 | ||
18857 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18858 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18859 | insn &= ~0x02200000; | |
18860 | } | |
18861 | ||
18862 | /* Make a label at the end for use with the branch. */ | |
18863 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18864 | micromips_label_inc (); | |
f3ded42a | 18865 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18866 | |
18867 | /* Refer to it. */ | |
4d68580a RS |
18868 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18869 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18870 | fixp->fx_file = fragp->fr_file; |
18871 | fixp->fx_line = fragp->fr_line; | |
18872 | ||
18873 | /* Branch over the jump. */ | |
4d68580a | 18874 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18875 | |
df58fc94 | 18876 | if (!compact) |
8484fb75 MR |
18877 | { |
18878 | /* nop */ | |
18879 | if (insn32) | |
18880 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18881 | else | |
18882 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18883 | } | |
df58fc94 RS |
18884 | } |
18885 | ||
ce8ad872 | 18886 | if (!pic) |
df58fc94 | 18887 | { |
7bd374a4 MR |
18888 | unsigned long jal = (short_ds || nods |
18889 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18890 | |
df58fc94 RS |
18891 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18892 | insn = al ? jal : 0xd4000000; | |
18893 | ||
bbd27b76 MR |
18894 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18895 | fragp->fr_symbol, fragp->fr_offset, | |
18896 | FALSE, BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18897 | fixp->fx_file = fragp->fr_file; |
18898 | fixp->fx_line = fragp->fr_line; | |
18899 | ||
4d68580a | 18900 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18901 | |
7bd374a4 | 18902 | if (compact || nods) |
8484fb75 MR |
18903 | { |
18904 | /* nop */ | |
18905 | if (insn32) | |
18906 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18907 | else | |
18908 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18909 | } | |
df58fc94 RS |
18910 | } |
18911 | else | |
18912 | { | |
18913 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18914 | ||
18915 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18916 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18917 | insn |= at << MICROMIPSOP_SH_RT; | |
18918 | ||
bbd27b76 MR |
18919 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18920 | fragp->fr_symbol, fragp->fr_offset, | |
18921 | FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18922 | fixp->fx_file = fragp->fr_file; |
18923 | fixp->fx_line = fragp->fr_line; | |
18924 | ||
4d68580a | 18925 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18926 | |
18927 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18928 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18929 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18930 | ||
bbd27b76 MR |
18931 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18932 | fragp->fr_symbol, fragp->fr_offset, | |
18933 | FALSE, BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18934 | fixp->fx_file = fragp->fr_file; |
18935 | fixp->fx_line = fragp->fr_line; | |
18936 | ||
4d68580a | 18937 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18938 | |
8484fb75 MR |
18939 | if (insn32) |
18940 | { | |
18941 | /* jr/jalr $at */ | |
18942 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18943 | insn |= at << MICROMIPSOP_SH_RS; | |
18944 | ||
18945 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18946 | |
7bd374a4 | 18947 | if (compact || nods) |
8484fb75 MR |
18948 | /* nop */ |
18949 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18950 | } | |
18951 | else | |
18952 | { | |
18953 | /* jr/jrc/jalr/jalrs $at */ | |
18954 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18955 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18956 | |
18957 | insn = al ? jalr : jr; | |
18958 | insn |= at << MICROMIPSOP_SH_MJ; | |
18959 | ||
18960 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18961 | if (al && nods) |
18962 | { | |
18963 | /* nop */ | |
18964 | if (short_ds) | |
18965 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18966 | else | |
18967 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18968 | } | |
8484fb75 | 18969 | } |
df58fc94 RS |
18970 | } |
18971 | ||
4d68580a | 18972 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18973 | return; |
18974 | } | |
18975 | ||
252b5132 RH |
18976 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18977 | { | |
18978 | int type; | |
3ccad066 | 18979 | const struct mips_int_operand *operand; |
252b5132 | 18980 | offsetT val; |
5c04167a | 18981 | char *buf; |
8507b6e7 | 18982 | unsigned int user_length; |
9d862524 | 18983 | bfd_boolean need_reloc; |
252b5132 | 18984 | unsigned long insn; |
8507b6e7 | 18985 | bfd_boolean mac; |
5c04167a | 18986 | bfd_boolean ext; |
88a7ef16 | 18987 | segT symsec; |
252b5132 RH |
18988 | |
18989 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 18990 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 18991 | |
8507b6e7 | 18992 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 18993 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 18994 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
18995 | |
18996 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
18997 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 18998 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
18999 | ? asec != symsec |
19000 | : !bfd_is_abs_section (symsec))); | |
19001 | ||
8507b6e7 | 19002 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 19003 | { |
3ccad066 | 19004 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 19005 | |
3ccad066 | 19006 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 19007 | |
14f72d45 | 19008 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 19009 | { |
37b2d327 MR |
19010 | if (!mips_ignore_branch_isa |
19011 | && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) | |
14f72d45 MR |
19012 | as_bad_where (fragp->fr_file, fragp->fr_line, |
19013 | _("branch to a symbol in another ISA mode")); | |
19014 | else if ((fragp->fr_offset & 0x1) != 0) | |
19015 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19016 | _("branch to misaligned address (0x%lx)"), | |
52031738 FS |
19017 | (long) (resolve_symbol_value (fragp->fr_symbol) |
19018 | + (fragp->fr_offset & ~1))); | |
252b5132 | 19019 | } |
252b5132 | 19020 | |
14f72d45 | 19021 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
19022 | |
19023 | /* Make sure the section winds up with the alignment we have | |
19024 | assumed. */ | |
3ccad066 RS |
19025 | if (operand->shift > 0) |
19026 | record_alignment (asec, operand->shift); | |
252b5132 RH |
19027 | } |
19028 | ||
8507b6e7 MR |
19029 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
19030 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
19031 | { | |
19032 | if (mac) | |
19033 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
19034 | _("macro instruction expanded into multiple " | |
19035 | "instructions in a branch delay slot")); | |
19036 | else if (ext) | |
19037 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
19038 | _("extended instruction in a branch delay slot")); | |
19039 | } | |
19040 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 19041 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
19042 | _("macro instruction expanded into multiple " |
19043 | "instructions")); | |
252b5132 | 19044 | |
5c04167a | 19045 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 19046 | |
4d68580a | 19047 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
19048 | if (ext) |
19049 | insn |= MIPS16_EXTEND; | |
252b5132 | 19050 | |
5c04167a RS |
19051 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
19052 | user_length = 4; | |
19053 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
19054 | user_length = 2; | |
19055 | else | |
19056 | user_length = 0; | |
19057 | ||
8507b6e7 | 19058 | if (mac) |
c9775dde | 19059 | { |
8507b6e7 MR |
19060 | unsigned long reg; |
19061 | unsigned long new; | |
19062 | unsigned long op; | |
25499ac7 | 19063 | bfd_boolean e2; |
8507b6e7 MR |
19064 | |
19065 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
19066 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 19067 | |
25499ac7 MR |
19068 | e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); |
19069 | ||
8507b6e7 | 19070 | if (need_reloc) |
c9775dde | 19071 | { |
8507b6e7 MR |
19072 | fixS *fixp; |
19073 | ||
19074 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
19075 | ||
19076 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
19077 | fragp->fr_symbol, fragp->fr_offset, | |
19078 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
19079 | fixp->fx_file = fragp->fr_file; | |
19080 | fixp->fx_line = fragp->fr_line; | |
19081 | ||
25499ac7 | 19082 | fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, |
8507b6e7 MR |
19083 | fragp->fr_symbol, fragp->fr_offset, |
19084 | FALSE, BFD_RELOC_MIPS16_LO16); | |
19085 | fixp->fx_file = fragp->fr_file; | |
19086 | fixp->fx_line = fragp->fr_line; | |
19087 | ||
19088 | val = 0; | |
19089 | } | |
19090 | ||
19091 | switch (insn & 0xf800) | |
19092 | { | |
19093 | case 0x0800: /* ADDIU */ | |
19094 | reg = (insn >> 8) & 0x7; | |
19095 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 19096 | break; |
8507b6e7 MR |
19097 | case 0xb000: /* LW */ |
19098 | reg = (insn >> 8) & 0x7; | |
19099 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 19100 | break; |
8507b6e7 MR |
19101 | case 0xf800: /* I64 */ |
19102 | reg = (insn >> 5) & 0x7; | |
19103 | switch (insn & 0x0700) | |
19104 | { | |
19105 | case 0x0400: /* LD */ | |
19106 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
19107 | break; | |
19108 | case 0x0600: /* DADDIU */ | |
19109 | op = 0xf000fd00 | (reg << 5); | |
19110 | break; | |
19111 | default: | |
19112 | abort (); | |
19113 | } | |
19114 | break; | |
19115 | default: | |
19116 | abort (); | |
c9775dde | 19117 | } |
8507b6e7 | 19118 | |
25499ac7 | 19119 | new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ |
8507b6e7 MR |
19120 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); |
19121 | buf = write_compressed_insn (buf, new, 4); | |
25499ac7 MR |
19122 | if (!e2) |
19123 | { | |
19124 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
19125 | buf = write_compressed_insn (buf, new, 4); | |
19126 | } | |
8507b6e7 MR |
19127 | op |= mips16_immed_extend (val, 16); |
19128 | buf = write_compressed_insn (buf, op, 4); | |
19129 | ||
25499ac7 | 19130 | fragp->fr_fix += e2 ? 8 : 12; |
8507b6e7 MR |
19131 | } |
19132 | else | |
19133 | { | |
19134 | unsigned int length = ext ? 4 : 2; | |
19135 | ||
19136 | if (need_reloc) | |
c9775dde | 19137 | { |
8507b6e7 | 19138 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
8507b6e7 | 19139 | fixS *fixp; |
c9775dde | 19140 | |
8507b6e7 MR |
19141 | switch (type) |
19142 | { | |
19143 | case 'p': | |
19144 | case 'q': | |
19145 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
19146 | break; | |
19147 | default: | |
19148 | break; | |
19149 | } | |
19150 | if (mac || reloc == BFD_RELOC_NONE) | |
19151 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19152 | _("unsupported relocation")); | |
19153 | else if (ext) | |
19154 | { | |
bbd27b76 MR |
19155 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
19156 | fragp->fr_symbol, fragp->fr_offset, | |
19157 | TRUE, reloc); | |
8507b6e7 MR |
19158 | fixp->fx_file = fragp->fr_file; |
19159 | fixp->fx_line = fragp->fr_line; | |
19160 | } | |
19161 | else | |
19162 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19163 | _("invalid unextended operand value")); | |
c9775dde | 19164 | } |
eefc3365 | 19165 | else |
8507b6e7 MR |
19166 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
19167 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 19168 | |
8507b6e7 MR |
19169 | gas_assert (mips16_opcode_length (insn) == length); |
19170 | write_compressed_insn (buf, insn, length); | |
19171 | fragp->fr_fix += length; | |
19172 | } | |
252b5132 RH |
19173 | } |
19174 | else | |
19175 | { | |
df58fc94 RS |
19176 | relax_substateT subtype = fragp->fr_subtype; |
19177 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
19178 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
871a6bd2 | 19179 | unsigned int first, second; |
4d7206a2 | 19180 | fixS *fixp; |
252b5132 | 19181 | |
df58fc94 RS |
19182 | first = RELAX_FIRST (subtype); |
19183 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 19184 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 19185 | |
df58fc94 RS |
19186 | /* If the delay slot chosen does not match the size of the instruction, |
19187 | then emit a warning. */ | |
19188 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
19189 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
19190 | { | |
19191 | relax_substateT s; | |
19192 | const char *msg; | |
19193 | ||
19194 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
19195 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
19196 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
19197 | msg = macro_warning (s); | |
19198 | if (msg != NULL) | |
db9b2be4 | 19199 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
19200 | subtype &= ~s; |
19201 | } | |
19202 | ||
584892a6 | 19203 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 19204 | if (use_second == second_longer) |
584892a6 | 19205 | { |
df58fc94 RS |
19206 | relax_substateT s; |
19207 | const char *msg; | |
19208 | ||
19209 | s = (subtype | |
19210 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
19211 | msg = macro_warning (s); | |
19212 | if (msg != NULL) | |
db9b2be4 | 19213 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 19214 | subtype &= ~s; |
584892a6 RS |
19215 | } |
19216 | ||
4d7206a2 RS |
19217 | /* Go through all the fixups for the first sequence. Disable them |
19218 | (by marking them as done) if we're going to use the second | |
19219 | sequence instead. */ | |
19220 | while (fixp | |
19221 | && fixp->fx_frag == fragp | |
90bd3c90 | 19222 | && fixp->fx_where + second < fragp->fr_fix) |
4d7206a2 | 19223 | { |
df58fc94 | 19224 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19225 | fixp->fx_done = 1; |
19226 | fixp = fixp->fx_next; | |
19227 | } | |
252b5132 | 19228 | |
4d7206a2 RS |
19229 | /* Go through the fixups for the second sequence. Disable them if |
19230 | we're going to use the first sequence, otherwise adjust their | |
19231 | addresses to account for the relaxation. */ | |
19232 | while (fixp && fixp->fx_frag == fragp) | |
19233 | { | |
df58fc94 | 19234 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19235 | fixp->fx_where -= first; |
19236 | else | |
19237 | fixp->fx_done = 1; | |
19238 | fixp = fixp->fx_next; | |
19239 | } | |
19240 | ||
19241 | /* Now modify the frag contents. */ | |
df58fc94 | 19242 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19243 | { |
19244 | char *start; | |
19245 | ||
19246 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
19247 | memmove (start, start + first, second); | |
19248 | fragp->fr_fix -= first; | |
19249 | } | |
19250 | else | |
19251 | fragp->fr_fix -= second; | |
252b5132 RH |
19252 | } |
19253 | } | |
19254 | ||
252b5132 RH |
19255 | /* This function is called after the relocs have been generated. |
19256 | We've been storing mips16 text labels as odd. Here we convert them | |
19257 | back to even for the convenience of the debugger. */ | |
19258 | ||
19259 | void | |
17a2f251 | 19260 | mips_frob_file_after_relocs (void) |
252b5132 RH |
19261 | { |
19262 | asymbol **syms; | |
19263 | unsigned int count, i; | |
19264 | ||
252b5132 RH |
19265 | syms = bfd_get_outsymbols (stdoutput); |
19266 | count = bfd_get_symcount (stdoutput); | |
19267 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
19268 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
19269 | && ((*syms)->value & 1) != 0) | |
19270 | { | |
19271 | (*syms)->value &= ~1; | |
19272 | /* If the symbol has an odd size, it was probably computed | |
19273 | incorrectly, so adjust that as well. */ | |
19274 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
19275 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
19276 | } | |
252b5132 RH |
19277 | } |
19278 | ||
a1facbec MR |
19279 | /* This function is called whenever a label is defined, including fake |
19280 | labels instantiated off the dot special symbol. It is used when | |
19281 | handling branch delays; if a branch has a label, we assume we cannot | |
19282 | move it. This also bumps the value of the symbol by 1 in compressed | |
19283 | code. */ | |
252b5132 | 19284 | |
e1b47bd5 | 19285 | static void |
a1facbec | 19286 | mips_record_label (symbolS *sym) |
252b5132 | 19287 | { |
a8dbcb85 | 19288 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
19289 | struct insn_label_list *l; |
19290 | ||
19291 | if (free_insn_labels == NULL) | |
325801bd | 19292 | l = XNEW (struct insn_label_list); |
252b5132 RH |
19293 | else |
19294 | { | |
19295 | l = free_insn_labels; | |
19296 | free_insn_labels = l->next; | |
19297 | } | |
19298 | ||
19299 | l->label = sym; | |
a8dbcb85 TS |
19300 | l->next = si->label_list; |
19301 | si->label_list = l; | |
a1facbec | 19302 | } |
07a53e5c | 19303 | |
a1facbec MR |
19304 | /* This function is called as tc_frob_label() whenever a label is defined |
19305 | and adds a DWARF-2 record we only want for true labels. */ | |
19306 | ||
19307 | void | |
19308 | mips_define_label (symbolS *sym) | |
19309 | { | |
19310 | mips_record_label (sym); | |
07a53e5c | 19311 | dwarf2_emit_label (sym); |
252b5132 | 19312 | } |
e1b47bd5 RS |
19313 | |
19314 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
19315 | is defined. */ | |
19316 | ||
19317 | void | |
19318 | mips_add_dot_label (symbolS *sym) | |
19319 | { | |
19320 | mips_record_label (sym); | |
19321 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
19322 | mips_compressed_mark_label (sym); | |
19323 | } | |
252b5132 | 19324 | \f |
351cdf24 MF |
19325 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
19326 | static unsigned int | |
19327 | mips_convert_ase_flags (int ase) | |
19328 | { | |
19329 | unsigned int ext_ases = 0; | |
19330 | ||
19331 | if (ase & ASE_DSP) | |
19332 | ext_ases |= AFL_ASE_DSP; | |
19333 | if (ase & ASE_DSPR2) | |
19334 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
19335 | if (ase & ASE_DSPR3) |
19336 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
19337 | if (ase & ASE_EVA) |
19338 | ext_ases |= AFL_ASE_EVA; | |
19339 | if (ase & ASE_MCU) | |
19340 | ext_ases |= AFL_ASE_MCU; | |
19341 | if (ase & ASE_MDMX) | |
19342 | ext_ases |= AFL_ASE_MDMX; | |
19343 | if (ase & ASE_MIPS3D) | |
19344 | ext_ases |= AFL_ASE_MIPS3D; | |
19345 | if (ase & ASE_MT) | |
19346 | ext_ases |= AFL_ASE_MT; | |
19347 | if (ase & ASE_SMARTMIPS) | |
19348 | ext_ases |= AFL_ASE_SMARTMIPS; | |
19349 | if (ase & ASE_VIRT) | |
19350 | ext_ases |= AFL_ASE_VIRT; | |
19351 | if (ase & ASE_MSA) | |
19352 | ext_ases |= AFL_ASE_MSA; | |
19353 | if (ase & ASE_XPA) | |
19354 | ext_ases |= AFL_ASE_XPA; | |
25499ac7 MR |
19355 | if (ase & ASE_MIPS16E2) |
19356 | ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; | |
730c3174 SE |
19357 | if (ase & ASE_CRC) |
19358 | ext_ases |= AFL_ASE_CRC; | |
6f20c942 FS |
19359 | if (ase & ASE_GINV) |
19360 | ext_ases |= AFL_ASE_GINV; | |
8095d2f7 CX |
19361 | if (ase & ASE_LOONGSON_MMI) |
19362 | ext_ases |= AFL_ASE_LOONGSON_MMI; | |
716c08de CX |
19363 | if (ase & ASE_LOONGSON_CAM) |
19364 | ext_ases |= AFL_ASE_LOONGSON_CAM; | |
bdc6c06e CX |
19365 | if (ase & ASE_LOONGSON_EXT) |
19366 | ext_ases |= AFL_ASE_LOONGSON_EXT; | |
a693765e CX |
19367 | if (ase & ASE_LOONGSON_EXT2) |
19368 | ext_ases |= AFL_ASE_LOONGSON_EXT2; | |
351cdf24 MF |
19369 | |
19370 | return ext_ases; | |
19371 | } | |
252b5132 RH |
19372 | /* Some special processing for a MIPS ELF file. */ |
19373 | ||
19374 | void | |
17a2f251 | 19375 | mips_elf_final_processing (void) |
252b5132 | 19376 | { |
351cdf24 MF |
19377 | int fpabi; |
19378 | Elf_Internal_ABIFlags_v0 flags; | |
19379 | ||
19380 | flags.version = 0; | |
19381 | flags.isa_rev = 0; | |
19382 | switch (file_mips_opts.isa) | |
19383 | { | |
19384 | case INSN_ISA1: | |
19385 | flags.isa_level = 1; | |
19386 | break; | |
19387 | case INSN_ISA2: | |
19388 | flags.isa_level = 2; | |
19389 | break; | |
19390 | case INSN_ISA3: | |
19391 | flags.isa_level = 3; | |
19392 | break; | |
19393 | case INSN_ISA4: | |
19394 | flags.isa_level = 4; | |
19395 | break; | |
19396 | case INSN_ISA5: | |
19397 | flags.isa_level = 5; | |
19398 | break; | |
19399 | case INSN_ISA32: | |
19400 | flags.isa_level = 32; | |
19401 | flags.isa_rev = 1; | |
19402 | break; | |
19403 | case INSN_ISA32R2: | |
19404 | flags.isa_level = 32; | |
19405 | flags.isa_rev = 2; | |
19406 | break; | |
19407 | case INSN_ISA32R3: | |
19408 | flags.isa_level = 32; | |
19409 | flags.isa_rev = 3; | |
19410 | break; | |
19411 | case INSN_ISA32R5: | |
19412 | flags.isa_level = 32; | |
19413 | flags.isa_rev = 5; | |
19414 | break; | |
09c14161 MF |
19415 | case INSN_ISA32R6: |
19416 | flags.isa_level = 32; | |
19417 | flags.isa_rev = 6; | |
19418 | break; | |
351cdf24 MF |
19419 | case INSN_ISA64: |
19420 | flags.isa_level = 64; | |
19421 | flags.isa_rev = 1; | |
19422 | break; | |
19423 | case INSN_ISA64R2: | |
19424 | flags.isa_level = 64; | |
19425 | flags.isa_rev = 2; | |
19426 | break; | |
19427 | case INSN_ISA64R3: | |
19428 | flags.isa_level = 64; | |
19429 | flags.isa_rev = 3; | |
19430 | break; | |
19431 | case INSN_ISA64R5: | |
19432 | flags.isa_level = 64; | |
19433 | flags.isa_rev = 5; | |
19434 | break; | |
09c14161 MF |
19435 | case INSN_ISA64R6: |
19436 | flags.isa_level = 64; | |
19437 | flags.isa_rev = 6; | |
19438 | break; | |
351cdf24 MF |
19439 | } |
19440 | ||
19441 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
19442 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
19443 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
19444 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
19445 | : AFL_REG_32; | |
19446 | flags.cpr2_size = AFL_REG_NONE; | |
19447 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19448 | Tag_GNU_MIPS_ABI_FP); | |
19449 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
19450 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
19451 | if (file_ase_mips16) | |
19452 | flags.ases |= AFL_ASE_MIPS16; | |
19453 | if (file_ase_micromips) | |
19454 | flags.ases |= AFL_ASE_MICROMIPS; | |
19455 | flags.flags1 = 0; | |
19456 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
19457 | || file_mips_opts.fp == 64) | |
19458 | && file_mips_opts.oddspreg) | |
19459 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
19460 | flags.flags2 = 0; | |
19461 | ||
19462 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
19463 | ((Elf_External_ABIFlags_v0 *) | |
19464 | mips_flags_frag)); | |
19465 | ||
252b5132 | 19466 | /* Write out the register information. */ |
316f5878 | 19467 | if (mips_abi != N64_ABI) |
252b5132 RH |
19468 | { |
19469 | Elf32_RegInfo s; | |
19470 | ||
19471 | s.ri_gprmask = mips_gprmask; | |
19472 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19473 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19474 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19475 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19476 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19477 | ||
19478 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
19479 | ((Elf32_External_RegInfo *) | |
19480 | mips_regmask_frag)); | |
19481 | } | |
19482 | else | |
19483 | { | |
19484 | Elf64_Internal_RegInfo s; | |
19485 | ||
19486 | s.ri_gprmask = mips_gprmask; | |
19487 | s.ri_pad = 0; | |
19488 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19489 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19490 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19491 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19492 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19493 | ||
19494 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
19495 | ((Elf64_External_RegInfo *) | |
19496 | mips_regmask_frag)); | |
19497 | } | |
19498 | ||
19499 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
19500 | sort of BFD interface for this. */ | |
19501 | if (mips_any_noreorder) | |
19502 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19503 | if (mips_pic != NO_PIC) | |
143d77c5 | 19504 | { |
8b828383 | 19505 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19506 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19507 | } | |
19508 | if (mips_abicalls) | |
19509 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19510 | |
b015e599 AP |
19511 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19512 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19513 | if (file_ase_mips16) |
19514 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19515 | if (file_ase_micromips) |
19516 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 19517 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 19518 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 19519 | |
bdaaa2e1 | 19520 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19521 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19522 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19523 | else if (mips_abi == O64_ABI) |
252b5132 | 19524 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19525 | else if (mips_abi == EABI_ABI) |
252b5132 | 19526 | { |
bad1aba3 | 19527 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19528 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19529 | else | |
19530 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19531 | } | |
be00bddd | 19532 | |
defc8e2b | 19533 | /* Nothing to do for N32_ABI or N64_ABI. */ |
252b5132 RH |
19534 | |
19535 | if (mips_32bitmode) | |
19536 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19537 | |
7361da2c | 19538 | if (mips_nan2008 == 1) |
ba92f887 MR |
19539 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19540 | ||
ad3fea08 | 19541 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19542 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19543 | Tag_GNU_MIPS_ABI_FP); | |
19544 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19545 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19546 | } |
252b5132 | 19547 | \f |
beae10d5 | 19548 | typedef struct proc { |
9b2f1d35 EC |
19549 | symbolS *func_sym; |
19550 | symbolS *func_end_sym; | |
beae10d5 KH |
19551 | unsigned long reg_mask; |
19552 | unsigned long reg_offset; | |
19553 | unsigned long fpreg_mask; | |
19554 | unsigned long fpreg_offset; | |
19555 | unsigned long frame_offset; | |
19556 | unsigned long frame_reg; | |
19557 | unsigned long pc_reg; | |
19558 | } procS; | |
252b5132 RH |
19559 | |
19560 | static procS cur_proc; | |
19561 | static procS *cur_proc_ptr; | |
19562 | static int numprocs; | |
19563 | ||
df58fc94 RS |
19564 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19565 | as "2", and a normal nop as "0". */ | |
19566 | ||
19567 | #define NOP_OPCODE_MIPS 0 | |
19568 | #define NOP_OPCODE_MIPS16 1 | |
19569 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19570 | |
19571 | char | |
19572 | mips_nop_opcode (void) | |
19573 | { | |
df58fc94 RS |
19574 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19575 | return NOP_OPCODE_MICROMIPS; | |
19576 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19577 | return NOP_OPCODE_MIPS16; | |
19578 | else | |
19579 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19580 | } |
19581 | ||
df58fc94 RS |
19582 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19583 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19584 | |
0a9ef439 | 19585 | void |
17a2f251 | 19586 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19587 | { |
df58fc94 | 19588 | char nop_opcode; |
742a56fe | 19589 | char *p; |
c67a084a NC |
19590 | int bytes, size, excess; |
19591 | valueT opcode; | |
742a56fe | 19592 | |
0a9ef439 RH |
19593 | if (fragp->fr_type != rs_align_code) |
19594 | return; | |
19595 | ||
742a56fe | 19596 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19597 | nop_opcode = *p; |
19598 | switch (nop_opcode) | |
a19d8eb0 | 19599 | { |
df58fc94 RS |
19600 | case NOP_OPCODE_MICROMIPS: |
19601 | opcode = micromips_nop32_insn.insn_opcode; | |
19602 | size = 4; | |
19603 | break; | |
19604 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19605 | opcode = mips16_nop_insn.insn_opcode; |
19606 | size = 2; | |
df58fc94 RS |
19607 | break; |
19608 | case NOP_OPCODE_MIPS: | |
19609 | default: | |
c67a084a NC |
19610 | opcode = nop_insn.insn_opcode; |
19611 | size = 4; | |
df58fc94 | 19612 | break; |
c67a084a | 19613 | } |
a19d8eb0 | 19614 | |
c67a084a NC |
19615 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19616 | excess = bytes % size; | |
df58fc94 RS |
19617 | |
19618 | /* Handle the leading part if we're not inserting a whole number of | |
19619 | instructions, and make it the end of the fixed part of the frag. | |
19620 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19621 | and use zeroes otherwise. */ | |
19622 | gas_assert (excess < 4); | |
19623 | fragp->fr_fix += excess; | |
19624 | switch (excess) | |
c67a084a | 19625 | { |
df58fc94 RS |
19626 | case 3: |
19627 | *p++ = '\0'; | |
19628 | /* Fall through. */ | |
19629 | case 2: | |
833794fc | 19630 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19631 | { |
4d68580a | 19632 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19633 | break; |
19634 | } | |
19635 | *p++ = '\0'; | |
19636 | /* Fall through. */ | |
19637 | case 1: | |
19638 | *p++ = '\0'; | |
19639 | /* Fall through. */ | |
19640 | case 0: | |
19641 | break; | |
a19d8eb0 | 19642 | } |
c67a084a NC |
19643 | |
19644 | md_number_to_chars (p, opcode, size); | |
19645 | fragp->fr_var = size; | |
a19d8eb0 CP |
19646 | } |
19647 | ||
252b5132 | 19648 | static long |
17a2f251 | 19649 | get_number (void) |
252b5132 RH |
19650 | { |
19651 | int negative = 0; | |
19652 | long val = 0; | |
19653 | ||
19654 | if (*input_line_pointer == '-') | |
19655 | { | |
19656 | ++input_line_pointer; | |
19657 | negative = 1; | |
19658 | } | |
3882b010 | 19659 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19660 | as_bad (_("expected simple number")); |
252b5132 RH |
19661 | if (input_line_pointer[0] == '0') |
19662 | { | |
19663 | if (input_line_pointer[1] == 'x') | |
19664 | { | |
19665 | input_line_pointer += 2; | |
3882b010 | 19666 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19667 | { |
19668 | val <<= 4; | |
19669 | val |= hex_value (*input_line_pointer++); | |
19670 | } | |
19671 | return negative ? -val : val; | |
19672 | } | |
19673 | else | |
19674 | { | |
19675 | ++input_line_pointer; | |
3882b010 | 19676 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19677 | { |
19678 | val <<= 3; | |
19679 | val |= *input_line_pointer++ - '0'; | |
19680 | } | |
19681 | return negative ? -val : val; | |
19682 | } | |
19683 | } | |
3882b010 | 19684 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19685 | { |
19686 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19687 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19688 | as_warn (_("invalid number")); |
252b5132 RH |
19689 | return -1; |
19690 | } | |
3882b010 | 19691 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19692 | { |
19693 | val *= 10; | |
19694 | val += *input_line_pointer++ - '0'; | |
19695 | } | |
19696 | return negative ? -val : val; | |
19697 | } | |
19698 | ||
19699 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19700 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19701 | case .file implies DWARF-2. */ | |
19702 | ||
19703 | static void | |
17a2f251 | 19704 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19705 | { |
ecb4347a DJ |
19706 | static int first_file_directive = 0; |
19707 | ||
c5dd6aab DJ |
19708 | if (ECOFF_DEBUGGING) |
19709 | { | |
19710 | get_number (); | |
19711 | s_app_file (0); | |
19712 | } | |
19713 | else | |
ecb4347a DJ |
19714 | { |
19715 | char *filename; | |
19716 | ||
68d20676 | 19717 | filename = dwarf2_directive_filename (); |
ecb4347a DJ |
19718 | |
19719 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19720 | directive even for stabs output. Make sure that this | |
19721 | ".file" is handled. Note that you need a version of GCC | |
19722 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19723 | if (filename != NULL && ! first_file_directive) | |
19724 | { | |
19725 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19726 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19727 | } |
19728 | first_file_directive = 1; | |
19729 | } | |
c5dd6aab DJ |
19730 | } |
19731 | ||
19732 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19733 | |
19734 | static void | |
17a2f251 | 19735 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19736 | { |
c5dd6aab DJ |
19737 | if (!ECOFF_DEBUGGING) |
19738 | dwarf2_directive_loc (0); | |
252b5132 RH |
19739 | } |
19740 | ||
252b5132 RH |
19741 | /* The .end directive. */ |
19742 | ||
19743 | static void | |
17a2f251 | 19744 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19745 | { |
19746 | symbolS *p; | |
252b5132 | 19747 | |
7a621144 DJ |
19748 | /* Following functions need their own .frame and .cprestore directives. */ |
19749 | mips_frame_reg_valid = 0; | |
19750 | mips_cprestore_valid = 0; | |
19751 | ||
252b5132 RH |
19752 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19753 | { | |
19754 | p = get_symbol (); | |
19755 | demand_empty_rest_of_line (); | |
19756 | } | |
19757 | else | |
19758 | p = NULL; | |
19759 | ||
fd361982 | 19760 | if ((bfd_section_flags (now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19761 | as_warn (_(".end not in text section")); |
19762 | ||
19763 | if (!cur_proc_ptr) | |
19764 | { | |
1661c76c | 19765 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19766 | demand_empty_rest_of_line (); |
19767 | return; | |
19768 | } | |
19769 | ||
19770 | if (p != NULL) | |
19771 | { | |
9c2799c2 | 19772 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19773 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19774 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19775 | |
19776 | if (debug_type == DEBUG_STABS) | |
19777 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19778 | S_GET_NAME (p)); | |
252b5132 RH |
19779 | } |
19780 | else | |
19781 | as_warn (_(".end directive missing or unknown symbol")); | |
19782 | ||
9b2f1d35 EC |
19783 | /* Create an expression to calculate the size of the function. */ |
19784 | if (p && cur_proc_ptr) | |
19785 | { | |
19786 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19787 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19788 | |
19789 | obj->size = exp; | |
19790 | exp->X_op = O_subtract; | |
19791 | exp->X_add_symbol = symbol_temp_new_now (); | |
19792 | exp->X_op_symbol = p; | |
19793 | exp->X_add_number = 0; | |
19794 | ||
19795 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19796 | } | |
19797 | ||
5ff6a06c MR |
19798 | #ifdef md_flush_pending_output |
19799 | md_flush_pending_output (); | |
19800 | #endif | |
19801 | ||
ecb4347a | 19802 | /* Generate a .pdr section. */ |
f3ded42a | 19803 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19804 | { |
19805 | segT saved_seg = now_seg; | |
19806 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19807 | expressionS exp; |
19808 | char *fragp; | |
252b5132 | 19809 | |
9c2799c2 | 19810 | gas_assert (pdr_seg); |
ecb4347a | 19811 | subseg_set (pdr_seg, 0); |
252b5132 | 19812 | |
ecb4347a DJ |
19813 | /* Write the symbol. */ |
19814 | exp.X_op = O_symbol; | |
19815 | exp.X_add_symbol = p; | |
19816 | exp.X_add_number = 0; | |
19817 | emit_expr (&exp, 4); | |
252b5132 | 19818 | |
ecb4347a | 19819 | fragp = frag_more (7 * 4); |
252b5132 | 19820 | |
17a2f251 TS |
19821 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19822 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19823 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19824 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19825 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19826 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19827 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19828 | |
ecb4347a DJ |
19829 | subseg_set (saved_seg, saved_subseg); |
19830 | } | |
252b5132 RH |
19831 | |
19832 | cur_proc_ptr = NULL; | |
19833 | } | |
19834 | ||
19835 | /* The .aent and .ent directives. */ | |
19836 | ||
19837 | static void | |
17a2f251 | 19838 | s_mips_ent (int aent) |
252b5132 | 19839 | { |
252b5132 | 19840 | symbolS *symbolP; |
252b5132 RH |
19841 | |
19842 | symbolP = get_symbol (); | |
19843 | if (*input_line_pointer == ',') | |
f9419b05 | 19844 | ++input_line_pointer; |
252b5132 | 19845 | SKIP_WHITESPACE (); |
3882b010 | 19846 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19847 | || *input_line_pointer == '-') |
874e8986 | 19848 | get_number (); |
252b5132 | 19849 | |
fd361982 | 19850 | if ((bfd_section_flags (now_seg) & SEC_CODE) == 0) |
1661c76c | 19851 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19852 | |
19853 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19854 | as_warn (_("missing .end")); |
252b5132 RH |
19855 | |
19856 | if (!aent) | |
19857 | { | |
7a621144 DJ |
19858 | /* This function needs its own .frame and .cprestore directives. */ |
19859 | mips_frame_reg_valid = 0; | |
19860 | mips_cprestore_valid = 0; | |
19861 | ||
252b5132 RH |
19862 | cur_proc_ptr = &cur_proc; |
19863 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19864 | ||
9b2f1d35 | 19865 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19866 | |
f9419b05 | 19867 | ++numprocs; |
ecb4347a DJ |
19868 | |
19869 | if (debug_type == DEBUG_STABS) | |
19870 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19871 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19872 | } |
19873 | ||
7c0fc524 MR |
19874 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19875 | ||
252b5132 RH |
19876 | demand_empty_rest_of_line (); |
19877 | } | |
19878 | ||
19879 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19880 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19881 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19882 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19883 | symbol table (in the mdebug section). */ |
19884 | ||
19885 | static void | |
17a2f251 | 19886 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19887 | { |
f3ded42a RS |
19888 | if (ECOFF_DEBUGGING) |
19889 | s_ignore (ignore); | |
19890 | else | |
ecb4347a DJ |
19891 | { |
19892 | long val; | |
252b5132 | 19893 | |
ecb4347a DJ |
19894 | if (cur_proc_ptr == (procS *) NULL) |
19895 | { | |
19896 | as_warn (_(".frame outside of .ent")); | |
19897 | demand_empty_rest_of_line (); | |
19898 | return; | |
19899 | } | |
252b5132 | 19900 | |
ecb4347a DJ |
19901 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19902 | ||
19903 | SKIP_WHITESPACE (); | |
19904 | if (*input_line_pointer++ != ',' | |
19905 | || get_absolute_expression_and_terminator (&val) != ',') | |
19906 | { | |
1661c76c | 19907 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19908 | --input_line_pointer; |
19909 | demand_empty_rest_of_line (); | |
19910 | return; | |
19911 | } | |
252b5132 | 19912 | |
ecb4347a DJ |
19913 | cur_proc_ptr->frame_offset = val; |
19914 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19915 | |
252b5132 | 19916 | demand_empty_rest_of_line (); |
252b5132 | 19917 | } |
252b5132 RH |
19918 | } |
19919 | ||
bdaaa2e1 KH |
19920 | /* The .fmask and .mask directives. If the mdebug section is present |
19921 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19922 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19923 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19924 | make reference to the ecoff symbol table (in the mdebug section). */ |
19925 | ||
19926 | static void | |
17a2f251 | 19927 | s_mips_mask (int reg_type) |
252b5132 | 19928 | { |
f3ded42a RS |
19929 | if (ECOFF_DEBUGGING) |
19930 | s_ignore (reg_type); | |
19931 | else | |
252b5132 | 19932 | { |
ecb4347a | 19933 | long mask, off; |
252b5132 | 19934 | |
ecb4347a DJ |
19935 | if (cur_proc_ptr == (procS *) NULL) |
19936 | { | |
19937 | as_warn (_(".mask/.fmask outside of .ent")); | |
19938 | demand_empty_rest_of_line (); | |
19939 | return; | |
19940 | } | |
252b5132 | 19941 | |
ecb4347a DJ |
19942 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19943 | { | |
1661c76c | 19944 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19945 | --input_line_pointer; |
19946 | demand_empty_rest_of_line (); | |
19947 | return; | |
19948 | } | |
252b5132 | 19949 | |
ecb4347a DJ |
19950 | off = get_absolute_expression (); |
19951 | ||
19952 | if (reg_type == 'F') | |
19953 | { | |
19954 | cur_proc_ptr->fpreg_mask = mask; | |
19955 | cur_proc_ptr->fpreg_offset = off; | |
19956 | } | |
19957 | else | |
19958 | { | |
19959 | cur_proc_ptr->reg_mask = mask; | |
19960 | cur_proc_ptr->reg_offset = off; | |
19961 | } | |
19962 | ||
19963 | demand_empty_rest_of_line (); | |
252b5132 | 19964 | } |
252b5132 RH |
19965 | } |
19966 | ||
316f5878 RS |
19967 | /* A table describing all the processors gas knows about. Names are |
19968 | matched in the order listed. | |
e7af610e | 19969 | |
316f5878 RS |
19970 | To ease comparison, please keep this table in the same order as |
19971 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19972 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19973 | { | |
6f2117ba | 19974 | /* Entries for generic ISAs. */ |
d16afab6 RS |
19975 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19976 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19977 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19978 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19979 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19980 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19981 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
19982 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
19983 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 19984 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
19985 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
19986 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
19987 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
19988 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 19989 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
19990 | |
19991 | /* MIPS I */ | |
d16afab6 RS |
19992 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19993 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19994 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19995 | |
19996 | /* MIPS II */ | |
d16afab6 | 19997 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19998 | |
19999 | /* MIPS III */ | |
d16afab6 RS |
20000 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
20001 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
20002 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
20003 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
20004 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
20005 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
20006 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
20007 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
20008 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
20009 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
20010 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
20011 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
20012 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
6f2117ba | 20013 | /* ST Microelectronics Loongson 2E and 2F cores. */ |
d16afab6 | 20014 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
8095d2f7 | 20015 | { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F }, |
316f5878 RS |
20016 | |
20017 | /* MIPS IV */ | |
d16afab6 RS |
20018 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
20019 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
20020 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
20021 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
20022 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
20023 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20024 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
20025 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
20026 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20027 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20028 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20029 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20030 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
20031 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
20032 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
20033 | |
20034 | /* MIPS 32 */ | |
d16afab6 RS |
20035 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
20036 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
20037 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
20038 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
20039 | |
20040 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
20041 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20042 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20043 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20044 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20045 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20046 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20047 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20048 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20049 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
20050 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20051 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
20052 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20053 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20054 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20055 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20056 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20057 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20058 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20059 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 20060 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
20061 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20062 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20063 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20064 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20065 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20066 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20067 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 20068 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
20069 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20070 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20071 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20072 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20073 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20074 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20075 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 20076 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 20077 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 20078 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
20079 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20080 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20081 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20082 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20083 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 20084 | /* Deprecated forms of the above. */ |
d16afab6 RS |
20085 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20086 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 20087 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
20088 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
20089 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20090 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
20091 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
6f2117ba | 20092 | /* interaptiv is the new name for 1004kf. */ |
77403ce9 | 20093 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
38bf472a MR |
20094 | { "interaptiv-mr2", 0, |
20095 | ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT, | |
20096 | ISA_MIPS32R3, CPU_INTERAPTIV_MR2 }, | |
6f2117ba | 20097 | /* M5100 family. */ |
c6e5c03a RS |
20098 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, |
20099 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 20100 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 20101 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 20102 | |
316f5878 | 20103 | /* MIPS 64 */ |
d16afab6 RS |
20104 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
20105 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
20106 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
20107 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 20108 | |
6f2117ba | 20109 | /* Broadcom SB-1 CPU core. */ |
d16afab6 | 20110 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
6f2117ba | 20111 | /* Broadcom SB-1A CPU core. */ |
d16afab6 | 20112 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 20113 | |
6f2117ba PH |
20114 | /* MIPS 64 Release 2. */ |
20115 | /* Loongson CPU core. */ | |
20116 | /* -march=loongson3a is an alias of -march=gs464 for compatibility. */ | |
bdc6c06e | 20117 | { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, |
ac8cb70f CX |
20118 | ISA_MIPS64R2, CPU_GS464 }, |
20119 | { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, | |
20120 | ISA_MIPS64R2, CPU_GS464 }, | |
bd782c07 CX |
20121 | { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
20122 | | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E }, | |
9108bc33 CX |
20123 | { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
20124 | | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E }, | |
ed163775 | 20125 | |
6f2117ba | 20126 | /* Cavium Networks Octeon CPU core. */ |
d16afab6 RS |
20127 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
20128 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
20129 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 20130 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 20131 | |
52b6b6b9 | 20132 | /* RMI Xlr */ |
d16afab6 | 20133 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 20134 | |
55a36193 MK |
20135 | /* Broadcom XLP. |
20136 | XLP is mostly like XLR, with the prominent exception that it is | |
20137 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 20138 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 20139 | |
6f2117ba | 20140 | /* MIPS 64 Release 6. */ |
bdc8beb4 MF |
20141 | { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
20142 | { "i6500", 0, ASE_VIRT | ASE_MSA | ASE_CRC | ASE_GINV, | |
20143 | ISA_MIPS64R6, CPU_MIPS64R6}, | |
a4968f42 | 20144 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 20145 | |
6f2117ba | 20146 | /* End marker. */ |
d16afab6 | 20147 | { NULL, 0, 0, 0, 0 } |
316f5878 | 20148 | }; |
e7af610e | 20149 | |
84ea6cf2 | 20150 | |
316f5878 RS |
20151 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
20152 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 20153 | |
316f5878 | 20154 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 20155 | |
b34976b6 | 20156 | static bfd_boolean |
17a2f251 | 20157 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
20158 | { |
20159 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
20160 | given++, canonical++; | |
20161 | ||
20162 | return ((*given == 0 && *canonical == 0) | |
20163 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
20164 | } | |
20165 | ||
20166 | ||
20167 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
20168 | CPU name. We've traditionally allowed a lot of variation here. | |
20169 | ||
20170 | Note: this function is shared between GCC and GAS. */ | |
20171 | ||
b34976b6 | 20172 | static bfd_boolean |
17a2f251 | 20173 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
20174 | { |
20175 | /* First see if the name matches exactly, or with a final "000" | |
20176 | turned into "k". */ | |
20177 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 20178 | return TRUE; |
316f5878 RS |
20179 | |
20180 | /* If not, try comparing based on numerical designation alone. | |
20181 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
20182 | if (TOLOWER (*given) == 'r') | |
20183 | given++; | |
20184 | if (!ISDIGIT (*given)) | |
b34976b6 | 20185 | return FALSE; |
316f5878 RS |
20186 | |
20187 | /* Skip over some well-known prefixes in the canonical name, | |
20188 | hoping to find a number there too. */ | |
20189 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
20190 | canonical += 2; | |
20191 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
20192 | canonical += 2; | |
20193 | else if (TOLOWER (canonical[0]) == 'r') | |
20194 | canonical += 1; | |
20195 | ||
20196 | return mips_strict_matching_cpu_name_p (canonical, given); | |
20197 | } | |
20198 | ||
20199 | ||
20200 | /* Parse an option that takes the name of a processor as its argument. | |
20201 | OPTION is the name of the option and CPU_STRING is the argument. | |
20202 | Return the corresponding processor enumeration if the CPU_STRING is | |
20203 | recognized, otherwise report an error and return null. | |
20204 | ||
20205 | A similar function exists in GCC. */ | |
e7af610e NC |
20206 | |
20207 | static const struct mips_cpu_info * | |
17a2f251 | 20208 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 20209 | { |
316f5878 | 20210 | const struct mips_cpu_info *p; |
e7af610e | 20211 | |
316f5878 RS |
20212 | /* 'from-abi' selects the most compatible architecture for the given |
20213 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
20214 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
20215 | version. Look first at the -mgp options, if given, otherwise base | |
20216 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 20217 | |
316f5878 RS |
20218 | Treat NO_ABI like the EABIs. One reason to do this is that the |
20219 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
20220 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
20221 | 'mips64', just as we did in the days before 'from-abi'. */ | |
20222 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
20223 | { | |
20224 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
20225 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
20226 | ||
20227 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
20228 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
20229 | ||
bad1aba3 | 20230 | if (file_mips_opts.gp >= 0) |
20231 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 20232 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
20233 | |
20234 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
20235 | ? ISA_MIPS3 | |
20236 | : ISA_MIPS1); | |
20237 | } | |
20238 | ||
20239 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
20240 | if (strcasecmp (cpu_string, "default") == 0) | |
20241 | return 0; | |
20242 | ||
20243 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
20244 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
20245 | return p; | |
20246 | ||
1661c76c | 20247 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 20248 | return 0; |
e7af610e NC |
20249 | } |
20250 | ||
316f5878 RS |
20251 | /* Return the canonical processor information for ISA (a member of the |
20252 | ISA_MIPS* enumeration). */ | |
20253 | ||
e7af610e | 20254 | static const struct mips_cpu_info * |
17a2f251 | 20255 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
20256 | { |
20257 | int i; | |
20258 | ||
20259 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 20260 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 20261 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
20262 | return (&mips_cpu_info_table[i]); |
20263 | ||
e972090a | 20264 | return NULL; |
e7af610e | 20265 | } |
fef14a42 TS |
20266 | |
20267 | static const struct mips_cpu_info * | |
17a2f251 | 20268 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
20269 | { |
20270 | int i; | |
20271 | ||
20272 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
20273 | if (arch == mips_cpu_info_table[i].cpu) | |
20274 | return (&mips_cpu_info_table[i]); | |
20275 | ||
20276 | return NULL; | |
20277 | } | |
316f5878 RS |
20278 | \f |
20279 | static void | |
17a2f251 | 20280 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
20281 | { |
20282 | if (*first_p) | |
20283 | { | |
20284 | fprintf (stream, "%24s", ""); | |
20285 | *col_p = 24; | |
20286 | } | |
20287 | else | |
20288 | { | |
20289 | fprintf (stream, ", "); | |
20290 | *col_p += 2; | |
20291 | } | |
e7af610e | 20292 | |
316f5878 RS |
20293 | if (*col_p + strlen (string) > 72) |
20294 | { | |
20295 | fprintf (stream, "\n%24s", ""); | |
20296 | *col_p = 24; | |
20297 | } | |
20298 | ||
20299 | fprintf (stream, "%s", string); | |
20300 | *col_p += strlen (string); | |
20301 | ||
20302 | *first_p = 0; | |
20303 | } | |
20304 | ||
20305 | void | |
17a2f251 | 20306 | md_show_usage (FILE *stream) |
e7af610e | 20307 | { |
316f5878 RS |
20308 | int column, first; |
20309 | size_t i; | |
20310 | ||
20311 | fprintf (stream, _("\ | |
20312 | MIPS options:\n\ | |
316f5878 RS |
20313 | -EB generate big endian output\n\ |
20314 | -EL generate little endian output\n\ | |
20315 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
20316 | -G NUM allow referencing objects up to NUM bytes\n\ | |
20317 | implicitly with the gp register [default 8]\n")); | |
20318 | fprintf (stream, _("\ | |
20319 | -mips1 generate MIPS ISA I instructions\n\ | |
20320 | -mips2 generate MIPS ISA II instructions\n\ | |
20321 | -mips3 generate MIPS ISA III instructions\n\ | |
20322 | -mips4 generate MIPS ISA IV instructions\n\ | |
20323 | -mips5 generate MIPS ISA V instructions\n\ | |
20324 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 20325 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
20326 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
20327 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 20328 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 20329 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 20330 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
20331 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
20332 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 20333 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
20334 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
20335 | ||
20336 | first = 1; | |
e7af610e NC |
20337 | |
20338 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
20339 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
20340 | show (stream, "from-abi", &column, &first); | |
20341 | fputc ('\n', stream); | |
e7af610e | 20342 | |
316f5878 RS |
20343 | fprintf (stream, _("\ |
20344 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
20345 | -no-mCPU don't generate code specific to CPU.\n\ | |
20346 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
20347 | ||
20348 | first = 1; | |
20349 | ||
20350 | show (stream, "3900", &column, &first); | |
20351 | show (stream, "4010", &column, &first); | |
20352 | show (stream, "4100", &column, &first); | |
20353 | show (stream, "4650", &column, &first); | |
20354 | fputc ('\n', stream); | |
20355 | ||
20356 | fprintf (stream, _("\ | |
20357 | -mips16 generate mips16 instructions\n\ | |
20358 | -no-mips16 do not generate mips16 instructions\n")); | |
20359 | fprintf (stream, _("\ | |
f866b262 MR |
20360 | -mmips16e2 generate MIPS16e2 instructions\n\ |
20361 | -mno-mips16e2 do not generate MIPS16e2 instructions\n")); | |
20362 | fprintf (stream, _("\ | |
df58fc94 RS |
20363 | -mmicromips generate microMIPS instructions\n\ |
20364 | -mno-micromips do not generate microMIPS instructions\n")); | |
20365 | fprintf (stream, _("\ | |
e16bfa71 | 20366 | -msmartmips generate smartmips instructions\n\ |
3739860c | 20367 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 20368 | fprintf (stream, _("\ |
74cd071d CF |
20369 | -mdsp generate DSP instructions\n\ |
20370 | -mno-dsp do not generate DSP instructions\n")); | |
20371 | fprintf (stream, _("\ | |
8b082fb1 TS |
20372 | -mdspr2 generate DSP R2 instructions\n\ |
20373 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
20374 | fprintf (stream, _("\ | |
8f4f9071 MF |
20375 | -mdspr3 generate DSP R3 instructions\n\ |
20376 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
20377 | fprintf (stream, _("\ | |
ef2e4d86 CF |
20378 | -mmt generate MT instructions\n\ |
20379 | -mno-mt do not generate MT instructions\n")); | |
20380 | fprintf (stream, _("\ | |
dec0624d MR |
20381 | -mmcu generate MCU instructions\n\ |
20382 | -mno-mcu do not generate MCU instructions\n")); | |
20383 | fprintf (stream, _("\ | |
56d438b1 CF |
20384 | -mmsa generate MSA instructions\n\ |
20385 | -mno-msa do not generate MSA instructions\n")); | |
20386 | fprintf (stream, _("\ | |
7d64c587 AB |
20387 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
20388 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
20389 | fprintf (stream, _("\ | |
b015e599 AP |
20390 | -mvirt generate Virtualization instructions\n\ |
20391 | -mno-virt do not generate Virtualization instructions\n")); | |
20392 | fprintf (stream, _("\ | |
730c3174 SE |
20393 | -mcrc generate CRC instructions\n\ |
20394 | -mno-crc do not generate CRC instructions\n")); | |
20395 | fprintf (stream, _("\ | |
6f20c942 FS |
20396 | -mginv generate Global INValidate (GINV) instructions\n\ |
20397 | -mno-ginv do not generate Global INValidate instructions\n")); | |
20398 | fprintf (stream, _("\ | |
8095d2f7 CX |
20399 | -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\ |
20400 | -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n")); | |
20401 | fprintf (stream, _("\ | |
716c08de CX |
20402 | -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\ |
20403 | -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n")); | |
20404 | fprintf (stream, _("\ | |
bdc6c06e CX |
20405 | -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\ |
20406 | -mno-loongson-ext do not generate Loongson EXTensions Instructions\n")); | |
20407 | fprintf (stream, _("\ | |
a693765e CX |
20408 | -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\ |
20409 | -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n")); | |
20410 | fprintf (stream, _("\ | |
833794fc MR |
20411 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
20412 | -mno-insn32 generate all microMIPS instructions\n")); | |
6f2117ba PH |
20413 | #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC |
20414 | fprintf (stream, _("\ | |
20415 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\ | |
20416 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n")); | |
20417 | #else | |
20418 | fprintf (stream, _("\ | |
20419 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ | |
20420 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n")); | |
20421 | #endif | |
833794fc | 20422 | fprintf (stream, _("\ |
c67a084a NC |
20423 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
20424 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
6f2117ba PH |
20425 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ |
20426 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\ | |
d766e8ec | 20427 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 20428 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 20429 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 20430 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
27c634e0 | 20431 | -mfix-r5900 work around R5900 short loop errata\n\ |
316f5878 RS |
20432 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
20433 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 20434 | -msym32 assume all symbols have 32-bit values\n\ |
092a534f MR |
20435 | -O0 do not remove unneeded NOPs, do not swap branches\n\ |
20436 | -O, -O1 remove unneeded NOPs, do not swap branches\n\ | |
20437 | -O2 remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
20438 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
20439 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
20440 | fprintf (stream, _("\ |
20441 | -mhard-float allow floating-point instructions\n\ | |
20442 | -msoft-float do not allow floating-point instructions\n\ | |
20443 | -msingle-float only allow 32-bit floating-point operations\n\ | |
20444 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 20445 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 20446 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
20447 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
20448 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
20449 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
20450 | ||
20451 | first = 1; | |
20452 | ||
20453 | show (stream, "legacy", &column, &first); | |
20454 | show (stream, "2008", &column, &first); | |
20455 | ||
20456 | fputc ('\n', stream); | |
20457 | ||
316f5878 RS |
20458 | fprintf (stream, _("\ |
20459 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 20460 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 20461 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 20462 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 20463 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 20464 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 20465 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 20466 | position dependent (non shared) code\n\ |
316f5878 RS |
20467 | -mabi=ABI create ABI conformant object file for:\n")); |
20468 | ||
20469 | first = 1; | |
20470 | ||
20471 | show (stream, "32", &column, &first); | |
20472 | show (stream, "o64", &column, &first); | |
20473 | show (stream, "n32", &column, &first); | |
20474 | show (stream, "64", &column, &first); | |
20475 | show (stream, "eabi", &column, &first); | |
20476 | ||
20477 | fputc ('\n', stream); | |
20478 | ||
20479 | fprintf (stream, _("\ | |
b4f6242e MR |
20480 | -32 create o32 ABI object file%s\n"), |
20481 | MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : ""); | |
20482 | fprintf (stream, _("\ | |
20483 | -n32 create n32 ABI object file%s\n"), | |
20484 | MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : ""); | |
20485 | fprintf (stream, _("\ | |
20486 | -64 create 64 ABI object file%s\n"), | |
20487 | MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : ""); | |
e7af610e | 20488 | } |
14e777e0 | 20489 | |
1575952e | 20490 | #ifdef TE_IRIX |
14e777e0 | 20491 | enum dwarf2_format |
413a266c | 20492 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 20493 | { |
369943fe | 20494 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 20495 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
20496 | else |
20497 | return dwarf2_format_32bit; | |
20498 | } | |
1575952e | 20499 | #endif |
73369e65 EC |
20500 | |
20501 | int | |
20502 | mips_dwarf2_addr_size (void) | |
20503 | { | |
6b6b3450 | 20504 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 20505 | return 8; |
73369e65 EC |
20506 | else |
20507 | return 4; | |
20508 | } | |
5862107c EC |
20509 | |
20510 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
20511 | void | |
20512 | mips_cfi_frame_initial_instructions (void) | |
20513 | { | |
20514 | cfi_add_CFA_def_cfa_register (SP); | |
20515 | } | |
20516 | ||
707bfff6 TS |
20517 | int |
20518 | tc_mips_regname_to_dw2regnum (char *regname) | |
20519 | { | |
20520 | unsigned int regnum = -1; | |
20521 | unsigned int reg; | |
20522 | ||
20523 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
20524 | regnum = reg; | |
20525 | ||
20526 | return regnum; | |
20527 | } | |
263b2574 | 20528 | |
20529 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
20530 | Given a symbolic attribute NAME, return the proper integer value. | |
20531 | Returns -1 if the attribute is not known. */ | |
20532 | ||
20533 | int | |
20534 | mips_convert_symbolic_attribute (const char *name) | |
20535 | { | |
20536 | static const struct | |
20537 | { | |
20538 | const char * name; | |
20539 | const int tag; | |
20540 | } | |
20541 | attribute_table[] = | |
20542 | { | |
20543 | #define T(tag) {#tag, tag} | |
20544 | T (Tag_GNU_MIPS_ABI_FP), | |
20545 | T (Tag_GNU_MIPS_ABI_MSA), | |
20546 | #undef T | |
20547 | }; | |
20548 | unsigned int i; | |
20549 | ||
20550 | if (name == NULL) | |
20551 | return -1; | |
20552 | ||
20553 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
20554 | if (streq (name, attribute_table[i].name)) | |
20555 | return attribute_table[i].tag; | |
20556 | ||
20557 | return -1; | |
20558 | } | |
fd5c94ab RS |
20559 | |
20560 | void | |
20561 | md_mips_end (void) | |
20562 | { | |
351cdf24 MF |
20563 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
20564 | ||
fd5c94ab RS |
20565 | mips_emit_delays (); |
20566 | if (cur_proc_ptr) | |
20567 | as_warn (_("missing .end at end of assembly")); | |
919731af | 20568 | |
20569 | /* Just in case no code was emitted, do the consistency check. */ | |
20570 | file_mips_check_options (); | |
351cdf24 MF |
20571 | |
20572 | /* Set a floating-point ABI if the user did not. */ | |
20573 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20574 | { | |
20575 | /* Perform consistency checks on the floating-point ABI. */ | |
20576 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20577 | Tag_GNU_MIPS_ABI_FP); | |
20578 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20579 | check_fpabi (fpabi); | |
20580 | } | |
20581 | else | |
20582 | { | |
20583 | /* Soft-float gets precedence over single-float, the two options should | |
20584 | not be used together so this should not matter. */ | |
20585 | if (file_mips_opts.soft_float == 1) | |
20586 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20587 | /* Single-float gets precedence over all double_float cases. */ | |
20588 | else if (file_mips_opts.single_float == 1) | |
20589 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20590 | else | |
20591 | { | |
20592 | switch (file_mips_opts.fp) | |
20593 | { | |
20594 | case 32: | |
20595 | if (file_mips_opts.gp == 32) | |
20596 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20597 | break; | |
20598 | case 0: | |
20599 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20600 | break; | |
20601 | case 64: | |
20602 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20603 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20604 | else if (file_mips_opts.gp == 32) | |
20605 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20606 | else | |
20607 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20608 | break; | |
20609 | } | |
20610 | } | |
20611 | ||
20612 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20613 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20614 | } | |
fd5c94ab | 20615 | } |
2f0c68f2 CM |
20616 | |
20617 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20618 | ||
20619 | bfd_reloc_code_real_type | |
20620 | mips_cfi_reloc_for_encoding (int encoding) | |
20621 | { | |
20622 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20623 | return BFD_RELOC_32_PCREL; | |
20624 | else return BFD_RELOC_NONE; | |
20625 | } |