Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
3d3c5039 | 39 | |
739708fa KR |
40 | #ifdef OBJ_MAYBE_ELF |
41 | /* Clean up namespace so we can include obj-elf.h too. */ | |
42 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
43 | #undef OBJ_PROCESS_STAB | |
44 | #undef OUTPUT_FLAVOR | |
45 | #undef S_GET_ALIGN | |
46 | #undef S_GET_SIZE | |
47 | #undef S_SET_ALIGN | |
48 | #undef S_SET_SIZE | |
49 | #undef TARGET_SYMBOL_FIELDS | |
50 | #undef obj_frob_file | |
cc5703cd | 51 | #undef obj_frob_file_after_relocs |
739708fa KR |
52 | #undef obj_frob_symbol |
53 | #undef obj_pop_insert | |
54 | #undef obj_sec_sym_ok_for_reloc | |
55 | ||
56 | #include "obj-elf.h" | |
57 | /* Fix any of them that we actually care about. */ | |
58 | #undef OUTPUT_FLAVOR | |
59 | #define OUTPUT_FLAVOR mips_output_flavor() | |
60 | #endif | |
61 | ||
62 | #if defined (OBJ_ELF) | |
f2a663d3 | 63 | #include "elf/mips.h" |
1dc1e798 | 64 | #endif |
f2a663d3 | 65 | |
739708fa | 66 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 67 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
68 | #define ECOFF_DEBUGGING 0 |
69 | #endif | |
70 | ||
22ba90ce ILT |
71 | #include "ecoff.h" |
72 | ||
a8aed9dd | 73 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 74 | static char *mips_regmask_frag; |
a8aed9dd | 75 | #endif |
f2a663d3 | 76 | |
3d3c5039 | 77 | #define AT 1 |
cc5703cd | 78 | #define TREG 24 |
9226253a | 79 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
80 | #define KT0 26 |
81 | #define KT1 27 | |
670a50eb | 82 | #define GP 28 |
9226253a ILT |
83 | #define SP 29 |
84 | #define FP 30 | |
3d3c5039 ILT |
85 | #define RA 31 |
86 | ||
cc5703cd ILT |
87 | #define ILLEGAL_REG (32) |
88 | ||
1dc1e798 | 89 | extern int target_big_endian; |
88225433 | 90 | |
7f9880e5 ILT |
91 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
92 | 32 bit ABI. This has no meaning for ECOFF. */ | |
93 | static int mips_64; | |
94 | ||
04cb3372 | 95 | /* The default target format to use. */ |
1dc1e798 KR |
96 | const char * |
97 | mips_target_format () | |
98 | { | |
99 | switch (OUTPUT_FLAVOR) | |
100 | { | |
101 | case bfd_target_aout_flavour: | |
102 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
103 | case bfd_target_ecoff_flavour: | |
104 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
105 | case bfd_target_elf_flavour: | |
7f9880e5 ILT |
106 | return (target_big_endian |
107 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
108 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
109 | default: |
110 | abort (); | |
111 | } | |
112 | } | |
04cb3372 | 113 | |
d2c71068 | 114 | /* The name of the readonly data section. */ |
1dc1e798 KR |
115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
116 | ? ".data" \ | |
117 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
118 | ? ".rdata" \ | |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
d2c71068 | 122 | |
1aa6938e ILT |
123 | /* These variables are filled in with the masks of registers used. |
124 | The object format code reads them and puts them in the appropriate | |
125 | place. */ | |
126 | unsigned long mips_gprmask; | |
127 | unsigned long mips_cprmask[4]; | |
128 | ||
1051c97f ILT |
129 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
130 | temporarily using .set mipsN). */ | |
8358c818 ILT |
131 | static int mips_isa = -1; |
132 | ||
1051c97f ILT |
133 | /* MIPS ISA we are using for this output file. */ |
134 | static int file_mips_isa; | |
135 | ||
cc5703cd ILT |
136 | /* Whether we are assembling for the mips16 processor. */ |
137 | static int mips16 = -1; | |
138 | ||
8c63448a | 139 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 140 | static int mips_cpu = -1; |
8c63448a | 141 | |
b2b8c24e ILT |
142 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
143 | static int mips_4650 = -1; | |
144 | ||
e532b44c ILT |
145 | /* Whether the 4010 instructions are permitted. */ |
146 | static int mips_4010 = -1; | |
147 | ||
c625fc23 JSC |
148 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
149 | static int mips_4100 = -1; | |
150 | ||
276c2d7d GRK |
151 | /* start-sanitize-r5900 */ |
152 | /* Whether Toshiba r5900 instructions are permitted. */ | |
153 | static int mips_5900 = -1; | |
154 | /* end-sanitize-r5900 */ | |
155 | ||
e532b44c ILT |
156 | /* Whether the processor uses hardware interlocks, and thus does not |
157 | require nops to be inserted. */ | |
158 | static int interlocks = -1; | |
159 | ||
344a8d61 JSC |
160 | /* As with "interlocks" this is used by hardware that has FP |
161 | (co-processor) interlocks. */ | |
162 | static int cop_interlocks = -1; | |
163 | ||
d9aba805 ILT |
164 | /* MIPS PIC level. */ |
165 | ||
166 | enum mips_pic_level | |
167 | { | |
168 | /* Do not generate PIC code. */ | |
169 | NO_PIC, | |
170 | ||
171 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
172 | not sure what it is supposed to do. */ | |
173 | IRIX4_PIC, | |
174 | ||
175 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
176 | SVR4_PIC, | |
177 | ||
178 | /* Generate PIC code without using a global offset table: the data | |
179 | segment has a maximum size of 64K, all data references are off | |
180 | the $gp register, and all text references are PC relative. This | |
181 | is used on some embedded systems. */ | |
182 | EMBEDDED_PIC | |
183 | }; | |
184 | ||
185 | static enum mips_pic_level mips_pic; | |
9226253a | 186 | |
fb251650 ILT |
187 | /* 1 if we should generate 32 bit offsets from the GP register in |
188 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
189 | static int mips_big_got; | |
190 | ||
8ea7f4e8 ILT |
191 | /* 1 if trap instructions should used for overflow rather than break |
192 | instructions. */ | |
193 | static int mips_trap; | |
194 | ||
cc5703cd ILT |
195 | /* 1 if we should autoextend mips16 instructions. */ |
196 | static int mips16_autoextend = 1; | |
197 | ||
3d3c5039 ILT |
198 | static int mips_warn_about_macros; |
199 | static int mips_noreorder; | |
0dd2d296 | 200 | static int mips_any_noreorder; |
3d3c5039 ILT |
201 | static int mips_nomove; |
202 | static int mips_noat; | |
203 | static int mips_nobopt; | |
204 | ||
670a50eb ILT |
205 | /* The size of the small data section. */ |
206 | static int g_switch_value = 8; | |
42562568 ILT |
207 | /* Whether the -G option was used. */ |
208 | static int g_switch_seen = 0; | |
670a50eb | 209 | |
3d3c5039 ILT |
210 | #define N_RMASK 0xc4 |
211 | #define N_VFP 0xd4 | |
212 | ||
d8a1c247 KR |
213 | /* If we can determine in advance that GP optimization won't be |
214 | possible, we can skip the relaxation stuff that tries to produce | |
215 | GP-relative references. This makes delay slot optimization work | |
216 | better. | |
217 | ||
218 | This function can only provide a guess, but it seems to work for | |
219 | gcc output. If it guesses wrong, the only loss should be in | |
220 | efficiency; it shouldn't introduce any bugs. | |
221 | ||
222 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
223 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
224 | static int nopic_need_relax PARAMS ((symbolS *)); | |
225 | ||
3d3c5039 ILT |
226 | /* handle of the OPCODE hash table */ |
227 | static struct hash_control *op_hash = NULL; | |
228 | ||
cc5703cd ILT |
229 | /* The opcode hash table we use for the mips16. */ |
230 | static struct hash_control *mips16_op_hash = NULL; | |
231 | ||
3d3c5039 ILT |
232 | /* This array holds the chars that always start a comment. If the |
233 | pre-processor is disabled, these aren't very useful */ | |
234 | const char comment_chars[] = "#"; | |
235 | ||
236 | /* This array holds the chars that only start a comment at the beginning of | |
237 | a line. If the line seems to have the form '# 123 filename' | |
238 | .line and .file directives will appear in the pre-processed output */ | |
239 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
240 | first line of the input file. This is because the compiler outputs | |
241 | #NO_APP at the beginning of its output. */ | |
242 | /* Also note that C style comments are always supported. */ | |
243 | const char line_comment_chars[] = "#"; | |
244 | ||
245 | /* This array holds machine specific line separator characters. */ | |
246 | const char line_separator_chars[] = ""; | |
247 | ||
248 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
249 | const char EXP_CHARS[] = "eE"; | |
250 | ||
251 | /* Chars that mean this number is a floating point constant */ | |
252 | /* As in 0f12.456 */ | |
253 | /* or 0d1.2345e12 */ | |
254 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
255 | ||
256 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
257 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
258 | but nothing is ideal around here. | |
259 | */ | |
260 | ||
670a50eb | 261 | static char *insn_error; |
3d3c5039 | 262 | |
3d3c5039 | 263 | static int auto_align = 1; |
becfe05e | 264 | |
9226253a ILT |
265 | /* When outputting SVR4 PIC code, the assembler needs to know the |
266 | offset in the stack frame from which to restore the $gp register. | |
267 | This is set by the .cprestore pseudo-op, and saved in this | |
268 | variable. */ | |
0dd2d296 ILT |
269 | static offsetT mips_cprestore_offset = -1; |
270 | ||
271 | /* This is the register which holds the stack frame, as set by the | |
272 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
273 | static int mips_frame_reg = SP; | |
9226253a | 274 | |
becfe05e ILT |
275 | /* To output NOP instructions correctly, we need to keep information |
276 | about the previous two instructions. */ | |
277 | ||
0aa07269 ILT |
278 | /* Whether we are optimizing. The default value of 2 means to remove |
279 | unneeded NOPs and swap branch instructions when possible. A value | |
280 | of 1 means to not swap branches. A value of 0 means to always | |
281 | insert NOPs. */ | |
282 | static int mips_optimize = 2; | |
4e95866e | 283 | |
22ba90ce ILT |
284 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
285 | equivalent to seeing no -g option at all. */ | |
286 | static int mips_debug = 0; | |
287 | ||
becfe05e ILT |
288 | /* The previous instruction. */ |
289 | static struct mips_cl_insn prev_insn; | |
290 | ||
291 | /* The instruction before prev_insn. */ | |
292 | static struct mips_cl_insn prev_prev_insn; | |
293 | ||
294 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
295 | point the insn_mo field at this dummy integer. */ | |
296 | static const struct mips_opcode dummy_opcode = { 0 }; | |
297 | ||
298 | /* Non-zero if prev_insn is valid. */ | |
299 | static int prev_insn_valid; | |
300 | ||
301 | /* The frag for the previous instruction. */ | |
302 | static struct frag *prev_insn_frag; | |
303 | ||
304 | /* The offset into prev_insn_frag for the previous instruction. */ | |
305 | static long prev_insn_where; | |
306 | ||
a677feeb ILT |
307 | /* The reloc type for the previous instruction, if any. */ |
308 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
309 | ||
becfe05e ILT |
310 | /* The reloc for the previous instruction, if any. */ |
311 | static fixS *prev_insn_fixp; | |
312 | ||
313 | /* Non-zero if the previous instruction was in a delay slot. */ | |
314 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
315 | |
316 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
317 | static int prev_insn_unreordered; | |
318 | ||
cc5703cd ILT |
319 | /* Non-zero if the previous instruction uses an extend opcode (if |
320 | mips16). */ | |
321 | static int prev_insn_extended; | |
322 | ||
4e95866e ILT |
323 | /* Non-zero if the previous previous instruction was in a .set |
324 | noreorder. */ | |
325 | static int prev_prev_insn_unreordered; | |
867a58b3 ILT |
326 | |
327 | /* For ECOFF and ELF, relocations against symbols are done in two | |
328 | parts, with a HI relocation and a LO relocation. Each relocation | |
329 | has only 16 bits of space to store an addend. This means that in | |
330 | order for the linker to handle carries correctly, it must be able | |
331 | to locate both the HI and the LO relocation. This means that the | |
332 | relocations must appear in order in the relocation table. | |
333 | ||
334 | In order to implement this, we keep track of each unmatched HI | |
335 | relocation. We then sort them so that they immediately precede the | |
336 | corresponding LO relocation. */ | |
337 | ||
338 | struct mips_hi_fixup | |
339 | { | |
340 | /* Next HI fixup. */ | |
341 | struct mips_hi_fixup *next; | |
342 | /* This fixup. */ | |
343 | fixS *fixp; | |
344 | /* The section this fixup is in. */ | |
345 | segT seg; | |
346 | }; | |
347 | ||
348 | /* The list of unmatched HI relocs. */ | |
349 | ||
350 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
351 | |
352 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
353 | ||
354 | #define X ILLEGAL_REG | |
355 | static const int mips32_to_16_reg_map[] = | |
356 | { | |
357 | X, X, 2, 3, 4, 5, 6, 7, | |
358 | X, X, X, X, X, X, X, X, | |
359 | 0, 1, X, X, X, X, X, X, | |
360 | X, X, X, X, X, X, X, X | |
361 | }; | |
362 | #undef X | |
363 | ||
364 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
365 | ||
366 | static const int mips16_to_32_reg_map[] = | |
367 | { | |
368 | 16, 17, 2, 3, 4, 5, 6, 7 | |
369 | }; | |
3d3c5039 | 370 | \f |
0dd2d296 ILT |
371 | /* Since the MIPS does not have multiple forms of PC relative |
372 | instructions, we do not have to do relaxing as is done on other | |
373 | platforms. However, we do have to handle GP relative addressing | |
374 | correctly, which turns out to be a similar problem. | |
375 | ||
376 | Every macro that refers to a symbol can occur in (at least) two | |
377 | forms, one with GP relative addressing and one without. For | |
378 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 379 | a macro instruction like this: |
0dd2d296 ILT |
380 | lw $4,i |
381 | If i can be addressed off the GP register (this is true if it is in | |
382 | the .sbss or .sdata section, or if it is known to be smaller than | |
383 | the -G argument) this will generate the following instruction: | |
384 | lw $4,i($gp) | |
385 | This instruction will use a GPREL reloc. If i can not be addressed | |
386 | off the GP register, the following instruction sequence will be used: | |
387 | lui $at,i | |
388 | lw $4,i($at) | |
389 | In this case the first instruction will have a HI16 reloc, and the | |
390 | second reloc will have a LO16 reloc. Both relocs will be against | |
391 | the symbol i. | |
392 | ||
393 | The issue here is that we may not know whether i is GP addressable | |
394 | until after we see the instruction that uses it. Therefore, we | |
395 | want to be able to choose the final instruction sequence only at | |
396 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 397 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
398 | end of assembly. |
399 | ||
400 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
401 | addressing in quite the same way, but the issue still arises as |
402 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
403 | |
404 | We handle these issues by actually generating both possible | |
405 | instruction sequences. The longer one is put in a frag_var with | |
406 | type rs_machine_dependent. We encode what to do with the frag in | |
407 | the subtype field. We encode (1) the number of existing bytes to | |
408 | replace, (2) the number of new bytes to use, (3) the offset from | |
409 | the start of the existing bytes to the first reloc we must generate | |
410 | (that is, the offset is applied from the start of the existing | |
411 | bytes after they are replaced by the new bytes, if any), (4) the | |
412 | offset from the start of the existing bytes to the second reloc, | |
413 | (5) whether a third reloc is needed (the third reloc is always four | |
414 | bytes after the second reloc), and (6) whether to warn if this | |
415 | variant is used (this is sometimes needed if .set nomacro or .set | |
416 | noat is in effect). All these numbers are reasonably small. | |
417 | ||
418 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
419 | ensure that delay slots are handled correctly. Fortunately, there |
420 | are a limited number of cases. When the second instruction | |
421 | sequence is generated, append_insn is directed to maintain the | |
422 | existing delay slot information, so it continues to apply to any | |
423 | code after the second instruction sequence. This means that the | |
424 | second instruction sequence must not impose any requirements not | |
425 | required by the first instruction sequence. | |
0dd2d296 ILT |
426 | |
427 | These variant frags are then handled in functions called by the | |
428 | machine independent code. md_estimate_size_before_relax returns | |
429 | the final size of the frag. md_convert_frag sets up the final form | |
430 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
431 | one if needed. */ | |
432 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
433 | ((relax_substateT) \ | |
cc5703cd | 434 | (((old) << 23) \ |
0dd2d296 ILT |
435 | | ((new) << 16) \ |
436 | | (((reloc1) + 64) << 9) \ | |
437 | | (((reloc2) + 64) << 2) \ | |
438 | | ((reloc3) ? (1 << 1) : 0) \ | |
439 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
440 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
441 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
442 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
443 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
444 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
445 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
446 | |
447 | /* For mips16 code, we use an entirely different form of relaxation. | |
448 | mips16 supports two versions of most instructions which take | |
449 | immediate values: a small one which takes some small value, and a | |
450 | larger one which takes a 16 bit value. Since branches also follow | |
451 | this pattern, relaxing these values is required. | |
452 | ||
453 | We can assemble both mips16 and normal MIPS code in a single | |
454 | object. Therefore, we need to support this type of relaxation at | |
455 | the same time that we support the relaxation described above. We | |
456 | use the high bit of the subtype field to distinguish these cases. | |
457 | ||
a677feeb ILT |
458 | The information we store for this type of relaxation is the |
459 | argument code found in the opcode file for this relocation, whether | |
460 | the user explicitly requested a small or extended form, and whether | |
461 | the relocation is in a jump or jal delay slot. That tells us the | |
462 | size of the value, and how it should be stored. We also store | |
463 | whether the fragment is considered to be extended or not. We also | |
464 | store whether this is known to be a branch to a different section, | |
465 | whether we have tried to relax this frag yet, and whether we have | |
466 | ever extended a PC relative fragment because of a shift count. */ | |
467 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
468 | (0x80000000 \ | |
469 | | ((type) & 0xff) \ | |
470 | | ((small) ? 0x100 : 0) \ | |
471 | | ((ext) ? 0x200 : 0) \ | |
472 | | ((dslot) ? 0x400 : 0) \ | |
473 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
474 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
475 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
476 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
477 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
478 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
479 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
480 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
481 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
482 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
483 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
484 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
485 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 486 | \f |
3d3c5039 ILT |
487 | /* Prototypes for static functions. */ |
488 | ||
489 | #ifdef __STDC__ | |
490 | #define internalError() \ | |
491 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
492 | #else | |
493 | #define internalError() as_fatal ("MIPS internal Error"); | |
494 | #endif | |
495 | ||
cc5703cd ILT |
496 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
497 | ||
becfe05e | 498 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 499 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 500 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
501 | static void append_insn PARAMS ((char *place, |
502 | struct mips_cl_insn * ip, | |
670a50eb | 503 | expressionS * p, |
867a58b3 ILT |
504 | bfd_reloc_code_real_type r, |
505 | boolean)); | |
becfe05e | 506 | static void mips_no_prev_insn PARAMS ((void)); |
fbcfacb7 | 507 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 508 | #ifdef USE_STDARG |
0dd2d296 | 509 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
510 | const char *name, const char *fmt, |
511 | ...)); | |
c625fc23 JSC |
512 | #else |
513 | static void macro_build (); | |
514 | #endif | |
cc5703cd ILT |
515 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
516 | const char *, const char *, | |
517 | va_list)); | |
0dd2d296 ILT |
518 | static void macro_build_lui PARAMS ((char *place, int *counter, |
519 | expressionS * ep, int regnum)); | |
6e8dda9c | 520 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 521 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 522 | expressionS *)); |
d8a1c247 | 523 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 524 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 525 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 526 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
527 | #ifdef LOSING_COMPILER |
528 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
529 | #endif | |
670a50eb | 530 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 531 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
532 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
533 | boolean, boolean, unsigned long *, | |
534 | boolean *, unsigned short *)); | |
670a50eb ILT |
535 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
536 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 537 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 538 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
539 | static void s_align PARAMS ((int)); |
540 | static void s_change_sec PARAMS ((int)); | |
541 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 542 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 543 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
544 | static void s_option PARAMS ((int)); |
545 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
546 | static void s_abicalls PARAMS ((int)); |
547 | static void s_cpload PARAMS ((int)); | |
548 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
549 | static void s_gpword PARAMS ((int)); |
550 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 551 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
552 | static void md_obj_begin PARAMS ((void)); |
553 | static void md_obj_end PARAMS ((void)); | |
554 | static long get_number PARAMS ((void)); | |
555 | static void s_ent PARAMS ((int)); | |
556 | static void s_mipsend PARAMS ((int)); | |
557 | static void s_file PARAMS ((int)); | |
cc5703cd | 558 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
559 | \f |
560 | /* Pseudo-op table. | |
561 | ||
562 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
563 | should be defined here, but are currently unsupported: .alias, | |
564 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
565 | ||
566 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
567 | specific to the type of debugging information being generated, and | |
568 | should be defined by the object format: .aent, .begin, .bend, | |
569 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
570 | .vreg. | |
571 | ||
572 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
573 | not MIPS CPU specific, but are also not specific to the object file | |
574 | format. This file is probably the best place to define them, but | |
575 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
576 | .struct, .weakext. */ | |
577 | ||
739708fa | 578 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 579 | { |
670a50eb ILT |
580 | /* MIPS specific pseudo-ops. */ |
581 | {"option", s_option, 0}, | |
582 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
583 | {"rdata", s_change_sec, 'r'}, |
584 | {"sdata", s_change_sec, 's'}, | |
585 | {"livereg", s_ignore, 0}, | |
739708fa KR |
586 | {"abicalls", s_abicalls, 0}, |
587 | {"cpload", s_cpload, 0}, | |
588 | {"cprestore", s_cprestore, 0}, | |
589 | {"gpword", s_gpword, 0}, | |
590 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 591 | {"insn", s_insn, 0}, |
3d3c5039 | 592 | |
670a50eb | 593 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 594 | chips. */ |
739708fa | 595 | {"asciiz", stringer, 1}, |
670a50eb ILT |
596 | {"bss", s_change_sec, 'b'}, |
597 | {"err", s_err, 0}, | |
598 | {"half", s_cons, 1}, | |
52aa70b5 | 599 | {"dword", s_cons, 3}, |
3d3c5039 | 600 | |
670a50eb | 601 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 602 | here for one reason or another. */ |
670a50eb ILT |
603 | {"align", s_align, 0}, |
604 | {"byte", s_cons, 0}, | |
605 | {"data", s_change_sec, 'd'}, | |
becfe05e | 606 | {"double", s_float_cons, 'd'}, |
becfe05e | 607 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
608 | {"globl", s_mips_globl, 0}, |
609 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
610 | {"hword", s_cons, 1}, |
611 | {"int", s_cons, 2}, | |
612 | {"long", s_cons, 2}, | |
613 | {"octa", s_cons, 4}, | |
614 | {"quad", s_cons, 3}, | |
615 | {"short", s_cons, 1}, | |
616 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
617 | {"text", s_change_sec, 't'}, |
618 | {"word", s_cons, 2}, | |
739708fa KR |
619 | { 0 }, |
620 | }; | |
3d3c5039 | 621 | |
739708fa | 622 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 623 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 624 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 625 | {"aent", s_ent, 1}, |
9226253a | 626 | {"bgnb", s_ignore, 0}, |
670a50eb | 627 | {"end", s_mipsend, 0}, |
9226253a | 628 | {"endb", s_ignore, 0}, |
670a50eb ILT |
629 | {"ent", s_ent, 0}, |
630 | {"file", s_file, 0}, | |
631 | {"fmask", s_ignore, 'F'}, | |
632 | {"frame", s_ignore, 0}, | |
633 | {"loc", s_ignore, 0}, | |
634 | {"mask", s_ignore, 'R'}, | |
635 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
636 | { 0 }, |
637 | }; | |
61420a20 | 638 | |
739708fa KR |
639 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
640 | ||
641 | void | |
642 | mips_pop_insert () | |
643 | { | |
644 | pop_insert (mips_pseudo_table); | |
645 | if (! ECOFF_DEBUGGING) | |
646 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 647 | } |
3d3c5039 | 648 | \f |
fbcfacb7 ILT |
649 | /* Symbols labelling the current insn. */ |
650 | ||
651 | struct insn_label_list | |
652 | { | |
653 | struct insn_label_list *next; | |
654 | symbolS *label; | |
655 | }; | |
656 | ||
657 | static struct insn_label_list *insn_labels; | |
658 | static struct insn_label_list *free_insn_labels; | |
659 | ||
660 | static void mips_clear_insn_labels PARAMS ((void)); | |
661 | ||
662 | static inline void | |
663 | mips_clear_insn_labels () | |
664 | { | |
665 | register struct insn_label_list **pl; | |
666 | ||
667 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
668 | ; | |
669 | *pl = insn_labels; | |
670 | insn_labels = NULL; | |
671 | } | |
672 | \f | |
3d3c5039 ILT |
673 | static char *expr_end; |
674 | ||
867a58b3 ILT |
675 | /* Expressions which appear in instructions. These are set by |
676 | mips_ip. */ | |
677 | ||
3d3c5039 ILT |
678 | static expressionS imm_expr; |
679 | static expressionS offset_expr; | |
867a58b3 ILT |
680 | |
681 | /* Relocs associated with imm_expr and offset_expr. */ | |
682 | ||
3d3c5039 ILT |
683 | static bfd_reloc_code_real_type imm_reloc; |
684 | static bfd_reloc_code_real_type offset_reloc; | |
685 | ||
867a58b3 ILT |
686 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
687 | ||
688 | static boolean imm_unmatched_hi; | |
689 | ||
8728fa92 ILT |
690 | /* These are set by mips16_ip if an explicit extension is used. */ |
691 | ||
692 | static boolean mips16_small, mips16_ext; | |
693 | ||
3d3c5039 ILT |
694 | /* |
695 | * This function is called once, at assembler startup time. It should | |
696 | * set up all the tables, etc. that the MD part of the assembler will need. | |
697 | */ | |
698 | void | |
670a50eb | 699 | md_begin () |
3d3c5039 | 700 | { |
0dd2d296 | 701 | boolean ok = false; |
604633ae | 702 | register const char *retval = NULL; |
670a50eb | 703 | register unsigned int i = 0; |
3d3c5039 | 704 | |
8358c818 ILT |
705 | if (mips_isa == -1) |
706 | { | |
8c63448a ILT |
707 | const char *cpu; |
708 | char *a = NULL; | |
709 | ||
710 | cpu = TARGET_CPU; | |
711 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
712 | { | |
713 | a = xmalloc (sizeof TARGET_CPU); | |
714 | strcpy (a, TARGET_CPU); | |
715 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
716 | cpu = a; | |
717 | } | |
718 | ||
719 | if (strcmp (cpu, "mips") == 0) | |
720 | { | |
721 | mips_isa = 1; | |
4bb0cc41 ILT |
722 | if (mips_cpu == -1) |
723 | mips_cpu = 3000; | |
8c63448a ILT |
724 | } |
725 | else if (strcmp (cpu, "r6000") == 0 | |
726 | || strcmp (cpu, "mips2") == 0) | |
727 | { | |
728 | mips_isa = 2; | |
4bb0cc41 ILT |
729 | if (mips_cpu == -1) |
730 | mips_cpu = 6000; | |
8c63448a ILT |
731 | } |
732 | else if (strcmp (cpu, "mips64") == 0 | |
733 | || strcmp (cpu, "r4000") == 0 | |
734 | || strcmp (cpu, "mips3") == 0) | |
735 | { | |
736 | mips_isa = 3; | |
4bb0cc41 ILT |
737 | if (mips_cpu == -1) |
738 | mips_cpu = 4000; | |
8c63448a ILT |
739 | } |
740 | else if (strcmp (cpu, "r4400") == 0) | |
741 | { | |
742 | mips_isa = 3; | |
4bb0cc41 ILT |
743 | if (mips_cpu == -1) |
744 | mips_cpu = 4400; | |
8c63448a ILT |
745 | } |
746 | else if (strcmp (cpu, "mips64orion") == 0 | |
747 | || strcmp (cpu, "r4600") == 0) | |
748 | { | |
749 | mips_isa = 3; | |
4bb0cc41 ILT |
750 | if (mips_cpu == -1) |
751 | mips_cpu = 4600; | |
8c63448a | 752 | } |
b2b8c24e ILT |
753 | else if (strcmp (cpu, "r4650") == 0) |
754 | { | |
755 | mips_isa = 3; | |
756 | if (mips_cpu == -1) | |
757 | mips_cpu = 4650; | |
758 | if (mips_4650 == -1) | |
759 | mips_4650 = 1; | |
760 | } | |
c625fc23 JSC |
761 | else if (strcmp (cpu, "mips64vr4300") == 0) |
762 | { | |
763 | mips_isa = 3; | |
764 | if (mips_cpu == -1) | |
765 | mips_cpu = 4300; | |
766 | } | |
767 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
768 | { | |
769 | mips_isa = 3; | |
770 | if (mips_cpu == -1) | |
771 | mips_cpu = 4100; | |
772 | if (mips_4100 == -1) | |
773 | mips_4100 = 1; | |
774 | } | |
e532b44c ILT |
775 | else if (strcmp (cpu, "r4010") == 0) |
776 | { | |
777 | mips_isa = 2; | |
778 | if (mips_cpu == -1) | |
779 | mips_cpu = 4010; | |
780 | if (mips_4010 == -1) | |
781 | mips_4010 = 1; | |
782 | } | |
517078c1 ILT |
783 | else if (strcmp (cpu, "r5000") == 0 |
784 | || strcmp (cpu, "mips64vr5000") == 0) | |
785 | { | |
786 | mips_isa = 4; | |
787 | if (mips_cpu == -1) | |
788 | mips_cpu = 5000; | |
789 | } | |
276c2d7d GRK |
790 | /* start-sanitize-r5900 */ |
791 | else if (strcmp (cpu, "r5900") == 0 | |
792 | || strcmp (cpu, "mips64vr5900") == 0 | |
793 | || strcmp (cpu, "mips64vr5900el") == 0) | |
794 | { | |
795 | mips_isa = 3; | |
796 | if (mips_cpu == -1) | |
797 | mips_cpu = 5900; | |
16262668 | 798 | if (mips_5900 == -1) |
276c2d7d GRK |
799 | mips_5900 = 1; |
800 | } | |
801 | /* end-sanitize-r5900 */ | |
d8a1c247 KR |
802 | else if (strcmp (cpu, "r8000") == 0 |
803 | || strcmp (cpu, "mips4") == 0) | |
804 | { | |
805 | mips_isa = 4; | |
806 | if (mips_cpu == -1) | |
807 | mips_cpu = 8000; | |
808 | } | |
809 | else if (strcmp (cpu, "r10000") == 0) | |
810 | { | |
811 | mips_isa = 4; | |
812 | if (mips_cpu == -1) | |
813 | mips_cpu = 10000; | |
814 | } | |
cc5703cd ILT |
815 | else if (strcmp (cpu, "mips16") == 0) |
816 | { | |
817 | mips_isa = 3; | |
818 | if (mips_cpu == -1) | |
819 | mips_cpu = 0; /* FIXME */ | |
820 | } | |
8358c818 | 821 | else |
8c63448a ILT |
822 | { |
823 | mips_isa = 1; | |
4bb0cc41 ILT |
824 | if (mips_cpu == -1) |
825 | mips_cpu = 3000; | |
8c63448a ILT |
826 | } |
827 | ||
828 | if (a != NULL) | |
829 | free (a); | |
8358c818 ILT |
830 | } |
831 | ||
cc5703cd ILT |
832 | if (mips16 < 0) |
833 | { | |
834 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
835 | mips16 = 1; | |
836 | else | |
837 | mips16 = 0; | |
838 | } | |
839 | ||
b2b8c24e ILT |
840 | if (mips_4650 < 0) |
841 | mips_4650 = 0; | |
842 | ||
e532b44c ILT |
843 | if (mips_4010 < 0) |
844 | mips_4010 = 0; | |
845 | ||
c625fc23 JSC |
846 | if (mips_4100 < 0) |
847 | mips_4100 = 0; | |
848 | ||
276c2d7d GRK |
849 | /* start-sanitize-r5900 */ |
850 | if (mips_5900 < 0) | |
851 | mips_5900 = 0; | |
852 | /* end-sanitize-r5900 */ | |
853 | ||
c36a90ef | 854 | if (mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
855 | interlocks = 1; |
856 | else | |
857 | interlocks = 0; | |
858 | ||
ca296aab | 859 | if (mips_cpu == 4300) |
344a8d61 JSC |
860 | cop_interlocks = 1; |
861 | else | |
862 | cop_interlocks = 0; | |
863 | ||
8ea7f4e8 ILT |
864 | if (mips_isa < 2 && mips_trap) |
865 | as_bad ("trap exception not supported at ISA 1"); | |
866 | ||
97f99d11 ILT |
867 | switch (mips_isa) |
868 | { | |
869 | case 1: | |
870 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
871 | break; | |
872 | case 2: | |
873 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
874 | break; | |
875 | case 3: | |
876 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
877 | break; | |
d8a1c247 KR |
878 | case 4: |
879 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
880 | break; | |
97f99d11 ILT |
881 | } |
882 | if (! ok) | |
883 | as_warn ("Could not set architecture and machine"); | |
884 | ||
1051c97f ILT |
885 | file_mips_isa = mips_isa; |
886 | ||
13fe1379 ILT |
887 | op_hash = hash_new (); |
888 | ||
670a50eb ILT |
889 | for (i = 0; i < NUMOPCODES;) |
890 | { | |
891 | const char *name = mips_opcodes[i].name; | |
892 | ||
604633ae | 893 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 894 | if (retval != NULL) |
670a50eb ILT |
895 | { |
896 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
897 | mips_opcodes[i].name, retval); | |
898 | as_fatal ("Broken assembler. No assembly attempted."); | |
899 | } | |
900 | do | |
901 | { | |
8358c818 ILT |
902 | if (mips_opcodes[i].pinfo != INSN_MACRO |
903 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
904 | != mips_opcodes[i].match)) | |
670a50eb ILT |
905 | { |
906 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
907 | mips_opcodes[i].name, mips_opcodes[i].args); | |
908 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 909 | } |
670a50eb ILT |
910 | ++i; |
911 | } | |
912 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
913 | } |
914 | ||
cc5703cd ILT |
915 | mips16_op_hash = hash_new (); |
916 | ||
917 | i = 0; | |
918 | while (i < bfd_mips16_num_opcodes) | |
919 | { | |
920 | const char *name = mips16_opcodes[i].name; | |
921 | ||
922 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
923 | if (retval != NULL) | |
924 | as_fatal ("internal error: can't hash `%s': %s\n", | |
925 | mips16_opcodes[i].name, retval); | |
926 | do | |
927 | { | |
928 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
929 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
930 | != mips16_opcodes[i].match)) | |
931 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
932 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
933 | ++i; | |
934 | } | |
935 | while (i < bfd_mips16_num_opcodes | |
936 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
937 | } | |
938 | ||
ebf28372 ILT |
939 | /* We add all the general register names to the symbol table. This |
940 | helps us detect invalid uses of them. */ | |
941 | for (i = 0; i < 32; i++) | |
942 | { | |
943 | char buf[5]; | |
944 | ||
945 | sprintf (buf, "$%d", i); | |
946 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
947 | &zero_address_frag)); | |
948 | } | |
949 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
950 | &zero_address_frag)); | |
951 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
952 | &zero_address_frag)); | |
953 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
954 | &zero_address_frag)); | |
955 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
956 | &zero_address_frag)); | |
957 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
958 | &zero_address_frag)); | |
959 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
960 | &zero_address_frag)); | |
961 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
962 | &zero_address_frag)); | |
963 | ||
becfe05e ILT |
964 | mips_no_prev_insn (); |
965 | ||
1aa6938e ILT |
966 | mips_gprmask = 0; |
967 | mips_cprmask[0] = 0; | |
968 | mips_cprmask[1] = 0; | |
969 | mips_cprmask[2] = 0; | |
970 | mips_cprmask[3] = 0; | |
971 | ||
8358c818 | 972 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 973 | record_alignment (text_section, 2); |
8358c818 | 974 | |
1dc1e798 KR |
975 | if (USE_GLOBAL_POINTER_OPT) |
976 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 977 | |
1dc1e798 KR |
978 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
979 | { | |
08e17202 ILT |
980 | /* On a native system, sections must be aligned to 16 byte |
981 | boundaries. When configured for an embedded ELF target, we | |
982 | don't bother. */ | |
983 | if (strcmp (TARGET_OS, "elf") != 0) | |
984 | { | |
985 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
986 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
987 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
988 | } | |
1dc1e798 KR |
989 | |
990 | /* Create a .reginfo section for register masks and a .mdebug | |
991 | section for debugging information. */ | |
992 | { | |
993 | segT seg; | |
994 | subsegT subseg; | |
b3a64736 | 995 | flagword flags; |
1dc1e798 KR |
996 | segT sec; |
997 | ||
998 | seg = now_seg; | |
999 | subseg = now_subseg; | |
1dc1e798 | 1000 | |
b3a64736 ILT |
1001 | /* The ABI says this section should be loaded so that the |
1002 | running program can access it. However, we don't load it | |
1003 | if we are configured for an embedded target */ | |
1004 | flags = SEC_READONLY | SEC_DATA; | |
1005 | if (strcmp (TARGET_OS, "elf") != 0) | |
1006 | flags |= SEC_ALLOC | SEC_LOAD; | |
1007 | ||
87178180 ILT |
1008 | if (! mips_64) |
1009 | { | |
1010 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1011 | |
b3a64736 ILT |
1012 | |
1013 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1014 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1015 | ||
f2a663d3 | 1016 | #ifdef OBJ_ELF |
87178180 | 1017 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1018 | #endif |
87178180 ILT |
1019 | } |
1020 | else | |
1021 | { | |
1022 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1023 | .reginfo section. */ | |
1024 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1025 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1026 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1027 | ||
1028 | #ifdef OBJ_ELF | |
1029 | /* Set up the option header. */ | |
1030 | { | |
1031 | Elf_Internal_Options opthdr; | |
1032 | char *f; | |
1033 | ||
1034 | opthdr.kind = ODK_REGINFO; | |
1035 | opthdr.size = (sizeof (Elf_External_Options) | |
1036 | + sizeof (Elf64_External_RegInfo)); | |
1037 | opthdr.section = 0; | |
1038 | opthdr.info = 0; | |
1039 | f = frag_more (sizeof (Elf_External_Options)); | |
1040 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1041 | (Elf_External_Options *) f); | |
1042 | ||
1043 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1044 | } | |
1045 | #endif | |
1046 | } | |
f2a663d3 | 1047 | |
739708fa KR |
1048 | if (ECOFF_DEBUGGING) |
1049 | { | |
1050 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1051 | (void) bfd_set_section_flags (stdoutput, sec, | |
1052 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1053 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1054 | } | |
0dd2d296 | 1055 | |
1dc1e798 KR |
1056 | subseg_set (seg, subseg); |
1057 | } | |
1058 | } | |
f2a663d3 | 1059 | |
739708fa KR |
1060 | if (! ECOFF_DEBUGGING) |
1061 | md_obj_begin (); | |
3d3c5039 ILT |
1062 | } |
1063 | ||
1064 | void | |
13fe1379 | 1065 | md_mips_end () |
3d3c5039 | 1066 | { |
739708fa KR |
1067 | if (! ECOFF_DEBUGGING) |
1068 | md_obj_end (); | |
3d3c5039 ILT |
1069 | } |
1070 | ||
1071 | void | |
670a50eb ILT |
1072 | md_assemble (str) |
1073 | char *str; | |
3d3c5039 | 1074 | { |
670a50eb | 1075 | struct mips_cl_insn insn; |
3d3c5039 | 1076 | |
5ac34ac3 | 1077 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1078 | imm_reloc = BFD_RELOC_UNUSED; |
1079 | imm_unmatched_hi = false; | |
5ac34ac3 | 1080 | offset_expr.X_op = O_absent; |
867a58b3 | 1081 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1082 | |
cc5703cd ILT |
1083 | if (mips16) |
1084 | mips16_ip (str, &insn); | |
1085 | else | |
1086 | mips_ip (str, &insn); | |
1087 | ||
670a50eb ILT |
1088 | if (insn_error) |
1089 | { | |
1090 | as_bad ("%s `%s'", insn_error, str); | |
1091 | return; | |
1092 | } | |
cc5703cd | 1093 | |
670a50eb ILT |
1094 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1095 | { | |
cc5703cd ILT |
1096 | if (mips16) |
1097 | mips16_macro (&insn); | |
1098 | else | |
1099 | macro (&insn); | |
3d3c5039 | 1100 | } |
670a50eb ILT |
1101 | else |
1102 | { | |
5ac34ac3 | 1103 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1104 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1105 | imm_unmatched_hi); | |
5ac34ac3 | 1106 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1107 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1108 | else |
867a58b3 | 1109 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1110 | } |
1111 | } | |
1112 | ||
cc5703cd ILT |
1113 | /* See whether instruction IP reads register REG. CLASS is the type |
1114 | of register. */ | |
becfe05e ILT |
1115 | |
1116 | static int | |
cc5703cd | 1117 | insn_uses_reg (ip, reg, class) |
becfe05e | 1118 | struct mips_cl_insn *ip; |
604633ae | 1119 | unsigned int reg; |
cc5703cd | 1120 | enum mips_regclass class; |
becfe05e | 1121 | { |
cc5703cd ILT |
1122 | if (class == MIPS16_REG) |
1123 | { | |
1124 | assert (mips16); | |
1125 | reg = mips16_to_32_reg_map[reg]; | |
1126 | class = MIPS_GR_REG; | |
1127 | } | |
1128 | ||
becfe05e | 1129 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1130 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1131 | return 0; |
1132 | ||
cc5703cd | 1133 | if (class == MIPS_FP_REG) |
becfe05e | 1134 | { |
cc5703cd | 1135 | assert (! mips16); |
becfe05e ILT |
1136 | /* If we are called with either $f0 or $f1, we must check $f0. |
1137 | This is not optimal, because it will introduce an unnecessary | |
1138 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1139 | need to distinguish reading both $f0 and $f1 or just one of | |
1140 | them. Note that we don't have to check the other way, | |
1141 | because there is no instruction that sets both $f0 and $f1 | |
1142 | and requires a delay. */ | |
1143 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1144 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1145 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1146 | return 1; |
1147 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1148 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1149 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1150 | return 1; |
1151 | } | |
cc5703cd | 1152 | else if (! mips16) |
becfe05e ILT |
1153 | { |
1154 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1155 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1156 | return 1; | |
1157 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1158 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1159 | return 1; | |
1160 | } | |
cc5703cd ILT |
1161 | else |
1162 | { | |
1163 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1164 | && ((ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) == reg) | |
1165 | return 1; | |
1166 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1167 | && ((ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY) == reg) | |
1168 | return 1; | |
1169 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1170 | && ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1171 | & MIPS16OP_MASK_MOVE32Z) == reg) | |
1172 | return 1; | |
1173 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1174 | return 1; | |
1175 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1176 | return 1; | |
1177 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1178 | return 1; | |
1179 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1180 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1181 | & MIPS16OP_MASK_REGR32) == reg) | |
1182 | return 1; | |
1183 | } | |
becfe05e ILT |
1184 | |
1185 | return 0; | |
1186 | } | |
1187 | ||
fb251650 ILT |
1188 | /* This function returns true if modifying a register requires a |
1189 | delay. */ | |
1190 | ||
1191 | static int | |
1192 | reg_needs_delay (reg) | |
1193 | int reg; | |
1194 | { | |
1195 | unsigned long prev_pinfo; | |
1196 | ||
1197 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1198 | if (! mips_noreorder | |
1199 | && mips_isa < 4 | |
1200 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1201 | || (mips_isa < 2 | |
1202 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1203 | { | |
1204 | /* A load from a coprocessor or from memory. All load | |
1205 | delays delay the use of general register rt for one | |
1206 | instruction on the r3000. The r6000 and r4000 use | |
1207 | interlocks. */ | |
1208 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1209 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1210 | return 1; | |
1211 | } | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
0dd2d296 ILT |
1216 | /* Output an instruction. PLACE is where to put the instruction; if |
1217 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1218 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1219 | used with RELOC_TYPE. */ | |
3d3c5039 | 1220 | |
3d3c5039 | 1221 | static void |
867a58b3 | 1222 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1223 | char *place; |
670a50eb ILT |
1224 | struct mips_cl_insn *ip; |
1225 | expressionS *address_expr; | |
1226 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1227 | boolean unmatched_hi; |
3d3c5039 | 1228 | { |
1aa6938e | 1229 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1230 | char *f; |
becfe05e ILT |
1231 | fixS *fixp; |
1232 | int nops = 0; | |
3d3c5039 | 1233 | |
fbcfacb7 ILT |
1234 | /* Mark instruction labels in mips16 mode. This permits the linker |
1235 | to handle them specially, such as generating jalx instructions | |
1236 | when needed. We also make them odd for the duration of the | |
1237 | assembly, in order to generate the right sort of code. We will | |
1238 | make them even in the adjust_symtab routine, while leaving them | |
1239 | marked. This is convenient for the debugger and the | |
1240 | disassembler. The linker knows to make them odd again. */ | |
1241 | if (mips16) | |
1242 | { | |
1243 | struct insn_label_list *l; | |
1244 | ||
1245 | for (l = insn_labels; l != NULL; l = l->next) | |
1246 | { | |
1247 | #ifdef S_SET_OTHER | |
1248 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1249 | S_SET_OTHER (l->label, STO_MIPS16); | |
1250 | #endif | |
1251 | ++l->label->sy_value.X_add_number; | |
1252 | } | |
1253 | } | |
1254 | ||
1aa6938e ILT |
1255 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1256 | pinfo = ip->insn_mo->pinfo; | |
1257 | ||
0dd2d296 | 1258 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
1259 | { |
1260 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 1261 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1262 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1263 | (1) a load from memory delay |
1264 | (2) a load from a coprocessor delay | |
1265 | (3) an unconditional branch delay | |
1266 | (4) a conditional branch delay | |
1267 | (5) a move to coprocessor register delay | |
1268 | (6) a load coprocessor register from memory delay | |
1269 | (7) a coprocessor condition code delay | |
1270 | (8) a HI/LO special register delay | |
becfe05e ILT |
1271 | |
1272 | There are a lot of optimizations we could do that we don't. | |
1273 | In particular, we do not, in general, reorder instructions. | |
1274 | If you use gcc with optimization, it will reorder | |
1275 | instructions and generally do much more optimization then we | |
1276 | do here; repeating all that work in the assembler would only | |
1277 | benefit hand written assembly code, and does not seem worth | |
1278 | it. */ | |
1279 | ||
1280 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1281 | #define emit_nop() \ |
1282 | (mips16 \ | |
1283 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1284 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1285 | |
1286 | /* The previous insn might require a delay slot, depending upon | |
1287 | the contents of the current insn. */ | |
cc5703cd ILT |
1288 | if (! mips16 |
1289 | && mips_isa < 4 | |
5af96dce ILT |
1290 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1291 | && ! cop_interlocks) | |
d8a1c247 KR |
1292 | || (mips_isa < 2 |
1293 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1294 | { |
1295 | /* A load from a coprocessor or from memory. All load | |
1296 | delays delay the use of general register rt for one | |
1297 | instruction on the r3000. The r6000 and r4000 use | |
1298 | interlocks. */ | |
1aa6938e | 1299 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1300 | if (mips_optimize == 0 |
1301 | || insn_uses_reg (ip, | |
1302 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1303 | & OP_MASK_RT), | |
cc5703cd | 1304 | MIPS_GR_REG)) |
becfe05e ILT |
1305 | ++nops; |
1306 | } | |
cc5703cd ILT |
1307 | else if (! mips16 |
1308 | && mips_isa < 4 | |
5af96dce ILT |
1309 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1310 | && ! cop_interlocks) | |
d8a1c247 KR |
1311 | || (mips_isa < 2 |
1312 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1313 | { |
1314 | /* A generic coprocessor delay. The previous instruction | |
1315 | modified a coprocessor general or control register. If | |
1316 | it modified a control register, we need to avoid any | |
1317 | coprocessor instruction (this is probably not always | |
1318 | required, but it sometimes is). If it modified a general | |
1319 | register, we avoid using that register. | |
1320 | ||
8358c818 ILT |
1321 | On the r6000 and r4000 loading a coprocessor register |
1322 | from memory is interlocked, and does not require a delay. | |
1323 | ||
becfe05e ILT |
1324 | This case is not handled very well. There is no special |
1325 | knowledge of CP0 handling, and the coprocessors other | |
1326 | than the floating point unit are not distinguished at | |
1327 | all. */ | |
1aa6938e | 1328 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1329 | { |
0aa07269 ILT |
1330 | if (mips_optimize == 0 |
1331 | || insn_uses_reg (ip, | |
8358c818 ILT |
1332 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1333 | & OP_MASK_FT), | |
cc5703cd | 1334 | MIPS_FP_REG)) |
becfe05e ILT |
1335 | ++nops; |
1336 | } | |
1aa6938e | 1337 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1338 | { |
0aa07269 ILT |
1339 | if (mips_optimize == 0 |
1340 | || insn_uses_reg (ip, | |
8358c818 ILT |
1341 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1342 | & OP_MASK_FS), | |
cc5703cd | 1343 | MIPS_FP_REG)) |
becfe05e ILT |
1344 | ++nops; |
1345 | } | |
1346 | else | |
1347 | { | |
1348 | /* We don't know exactly what the previous instruction | |
1349 | does. If the current instruction uses a coprocessor | |
1350 | register, we must insert a NOP. If previous | |
1351 | instruction may set the condition codes, and the | |
1352 | current instruction uses them, we must insert two | |
1353 | NOPS. */ | |
0aa07269 | 1354 | if (mips_optimize == 0 |
1aa6938e ILT |
1355 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1356 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1357 | nops += 2; |
1aa6938e | 1358 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1359 | ++nops; |
1360 | } | |
1361 | } | |
cc5703cd ILT |
1362 | else if (! mips16 |
1363 | && mips_isa < 4 | |
344a8d61 JSC |
1364 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1365 | && ! cop_interlocks) | |
becfe05e ILT |
1366 | { |
1367 | /* The previous instruction sets the coprocessor condition | |
1368 | codes, but does not require a general coprocessor delay | |
1369 | (this means it is a floating point comparison | |
1370 | instruction). If this instruction uses the condition | |
1371 | codes, we need to insert a single NOP. */ | |
0aa07269 | 1372 | if (mips_optimize == 0 |
1aa6938e | 1373 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1374 | ++nops; |
1375 | } | |
1aa6938e | 1376 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1377 | { |
1378 | /* The previous instruction reads the LO register; if the | |
1379 | current instruction writes to the LO register, we must | |
517078c1 | 1380 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1381 | if (! interlocks |
b2b8c24e ILT |
1382 | && (mips_optimize == 0 |
1383 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1384 | nops += 2; |
1385 | } | |
1386 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1387 | { | |
1388 | /* The previous instruction reads the HI register; if the | |
1389 | current instruction writes to the HI register, we must | |
517078c1 | 1390 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1391 | if (! interlocks |
b2b8c24e ILT |
1392 | && (mips_optimize == 0 |
1393 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1394 | nops += 2; |
1395 | } | |
1396 | ||
1397 | /* There are two cases which require two intervening | |
1398 | instructions: 1) setting the condition codes using a move to | |
1399 | coprocessor instruction which requires a general coprocessor | |
1400 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1401 | or LO register and then writing to it (except on processors |
1402 | which have interlocks). If we are not already emitting a NOP | |
1403 | instruction, we must check for these cases compared to the | |
1404 | instruction previous to the previous instruction. */ | |
becfe05e | 1405 | if (nops == 0 |
cc5703cd ILT |
1406 | && ((! mips16 |
1407 | && mips_isa < 4 | |
d8a1c247 | 1408 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 1409 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
344a8d61 JSC |
1410 | && (pinfo & INSN_READ_COND_CODE) |
1411 | && ! cop_interlocks) | |
becfe05e | 1412 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
b2b8c24e | 1413 | && (pinfo & INSN_WRITE_LO) |
e532b44c | 1414 | && ! interlocks) |
becfe05e | 1415 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
b2b8c24e | 1416 | && (pinfo & INSN_WRITE_HI) |
e532b44c | 1417 | && ! interlocks))) |
becfe05e ILT |
1418 | ++nops; |
1419 | ||
0dd2d296 ILT |
1420 | /* If we are being given a nop instruction, don't bother with |
1421 | one of the nops we would otherwise output. This will only | |
1422 | happen when a nop instruction is used with mips_optimize set | |
1423 | to 0. */ | |
cc5703cd | 1424 | if (nops > 0 && ip->insn_opcode == (mips16 ? 0x6500 : 0)) |
0dd2d296 ILT |
1425 | --nops; |
1426 | ||
becfe05e ILT |
1427 | /* Now emit the right number of NOP instructions. */ |
1428 | if (nops > 0) | |
1429 | { | |
5af96dce ILT |
1430 | fragS *old_frag; |
1431 | unsigned long old_frag_offset; | |
8c63448a | 1432 | int i; |
fbcfacb7 | 1433 | struct insn_label_list *l; |
8c63448a | 1434 | |
5af96dce ILT |
1435 | old_frag = frag_now; |
1436 | old_frag_offset = frag_now_fix (); | |
1437 | ||
8c63448a | 1438 | for (i = 0; i < nops; i++) |
becfe05e | 1439 | emit_nop (); |
5af96dce | 1440 | |
af255ca0 | 1441 | if (listing) |
546f5536 ILT |
1442 | { |
1443 | listing_prev_line (); | |
1444 | /* We may be at the start of a variant frag. In case we | |
1445 | are, make sure there is enough space for the frag | |
1446 | after the frags created by listing_prev_line. The | |
1447 | argument to frag_grow here must be at least as large | |
1448 | as the argument to all other calls to frag_grow in | |
1449 | this file. We don't have to worry about being in the | |
1450 | middle of a variant frag, because the variants insert | |
1451 | all needed nop instructions themselves. */ | |
1452 | frag_grow (40); | |
1453 | } | |
5af96dce | 1454 | |
fbcfacb7 | 1455 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1456 | { |
fbcfacb7 ILT |
1457 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1458 | l->label->sy_frag = frag_now; | |
1459 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1460 | /* mips16 text labels are stored as odd. */ | |
1461 | if (mips16) | |
1462 | ++l->label->sy_value.X_add_number; | |
becfe05e | 1463 | } |
5af96dce ILT |
1464 | |
1465 | #ifndef NO_ECOFF_DEBUGGING | |
1466 | if (ECOFF_DEBUGGING) | |
1467 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1468 | #endif | |
becfe05e ILT |
1469 | } |
1470 | } | |
1471 | ||
cc5703cd ILT |
1472 | if (reloc_type > BFD_RELOC_UNUSED) |
1473 | { | |
1474 | /* We need to set up a variant frag. */ | |
1475 | assert (mips16 && address_expr != NULL); | |
1476 | f = frag_var (rs_machine_dependent, 4, 0, | |
8728fa92 | 1477 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1478 | mips16_small, mips16_ext, |
1479 | (prev_pinfo | |
1480 | & INSN_UNCOND_BRANCH_DELAY), | |
1481 | (prev_insn_reloc_type | |
1482 | == BFD_RELOC_MIPS16_JMP)), | |
cc5703cd ILT |
1483 | make_expr_symbol (address_expr), (long) 0, |
1484 | (char *) NULL); | |
1485 | } | |
1486 | else if (place != NULL) | |
0dd2d296 | 1487 | f = place; |
cc5703cd | 1488 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
08e17202 ILT |
1489 | { |
1490 | /* Make sure there is enough room to swap this instruction with | |
1491 | a following jump instruction. */ | |
1492 | frag_grow (6); | |
1493 | f = frag_more (2); | |
1494 | } | |
cc5703cd | 1495 | else |
035936da ILT |
1496 | { |
1497 | if (mips16 | |
1498 | && mips_noreorder | |
1499 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1500 | as_warn ("extended instruction in delay slot"); | |
1501 | ||
1502 | f = frag_more (4); | |
1503 | } | |
1504 | ||
becfe05e | 1505 | fixp = NULL; |
cc5703cd | 1506 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1507 | { |
5ac34ac3 | 1508 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1509 | { |
1510 | switch (reloc_type) | |
1511 | { | |
3d3c5039 | 1512 | case BFD_RELOC_32: |
670a50eb ILT |
1513 | ip->insn_opcode |= address_expr->X_add_number; |
1514 | break; | |
3d3c5039 ILT |
1515 | |
1516 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1517 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1518 | break; | |
3d3c5039 ILT |
1519 | |
1520 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1521 | if ((address_expr->X_add_number & 3) != 0) |
1522 | as_bad ("jump to misaligned address (0x%lx)", | |
1523 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1524 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1525 | break; | |
1526 | ||
cc5703cd | 1527 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1528 | if ((address_expr->X_add_number & 3) != 0) |
1529 | as_bad ("jump to misaligned address (0x%lx)", | |
1530 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1531 | ip->insn_opcode |= |
1532 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1533 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1534 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1535 | break; | |
1536 | ||
3d3c5039 | 1537 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1538 | goto need_reloc; |
3d3c5039 ILT |
1539 | |
1540 | default: | |
670a50eb | 1541 | internalError (); |
3d3c5039 | 1542 | } |
670a50eb ILT |
1543 | } |
1544 | else | |
1545 | { | |
3d3c5039 | 1546 | need_reloc: |
0dd2d296 ILT |
1547 | /* Don't generate a reloc if we are writing into a variant |
1548 | frag. */ | |
1549 | if (place == NULL) | |
867a58b3 ILT |
1550 | { |
1551 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1552 | address_expr, | |
1553 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1554 | reloc_type); | |
1555 | if (unmatched_hi) | |
1556 | { | |
1557 | struct mips_hi_fixup *hi_fixup; | |
1558 | ||
1559 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1560 | hi_fixup = ((struct mips_hi_fixup *) | |
1561 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1562 | hi_fixup->fixp = fixp; | |
1563 | hi_fixup->seg = now_seg; | |
1564 | hi_fixup->next = mips_hi_fixup_list; | |
1565 | mips_hi_fixup_list = hi_fixup; | |
1566 | } | |
1567 | } | |
3d3c5039 ILT |
1568 | } |
1569 | } | |
becfe05e | 1570 | |
16262668 | 1571 | if (! mips16) |
cc5703cd | 1572 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1573 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1574 | { | |
1575 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1576 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1577 | } | |
cc5703cd ILT |
1578 | else |
1579 | { | |
1580 | if (ip->use_extend) | |
1581 | { | |
1582 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1583 | f += 2; | |
1584 | } | |
1585 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1586 | } | |
670a50eb | 1587 | |
1aa6938e | 1588 | /* Update the register mask information. */ |
cc5703cd ILT |
1589 | if (! mips16) |
1590 | { | |
1591 | if (pinfo & INSN_WRITE_GPR_D) | |
1592 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1593 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1594 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1595 | if (pinfo & INSN_READ_GPR_S) | |
1596 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1597 | if (pinfo & INSN_WRITE_GPR_31) | |
1598 | mips_gprmask |= 1 << 31; | |
1599 | if (pinfo & INSN_WRITE_FPR_D) | |
1600 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1601 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1602 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1603 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1604 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1605 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1606 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1607 | if (pinfo & INSN_COP) | |
1608 | { | |
1609 | /* We don't keep enough information to sort these cases out. */ | |
1610 | } | |
1611 | /* Never set the bit for $0, which is always zero. */ | |
1612 | mips_gprmask &=~ 1 << 0; | |
1613 | } | |
1614 | else | |
1aa6938e | 1615 | { |
cc5703cd ILT |
1616 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1617 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1618 | & MIPS16OP_MASK_RX); | |
1619 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1620 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1621 | & MIPS16OP_MASK_RY); | |
1622 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1623 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1624 | & MIPS16OP_MASK_RZ); | |
1625 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1626 | mips_gprmask |= 1 << TREG; | |
1627 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1628 | mips_gprmask |= 1 << SP; | |
1629 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1630 | mips_gprmask |= 1 << RA; | |
1631 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1632 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1633 | if (pinfo & MIPS16_INSN_READ_Z) | |
1634 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1635 | & MIPS16OP_MASK_MOVE32Z); | |
1636 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1637 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1638 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1639 | } |
1aa6938e | 1640 | |
0dd2d296 | 1641 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1642 | { |
becfe05e ILT |
1643 | /* Filling the branch delay slot is more complex. We try to |
1644 | switch the branch with the previous instruction, which we can | |
1645 | do if the previous instruction does not set up a condition | |
1646 | that the branch tests and if the branch is not itself the | |
1647 | target of any branch. */ | |
1aa6938e ILT |
1648 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1649 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1650 | { |
0aa07269 | 1651 | if (mips_optimize < 2 |
19ed8960 ILT |
1652 | /* If we have seen .set volatile or .set nomove, don't |
1653 | optimize. */ | |
1654 | || mips_nomove != 0 | |
4e95866e ILT |
1655 | /* If we had to emit any NOP instructions, then we |
1656 | already know we can not swap. */ | |
1657 | || nops != 0 | |
becfe05e ILT |
1658 | /* If we don't even know the previous insn, we can not |
1659 | swap. */ | |
1660 | || ! prev_insn_valid | |
1661 | /* If the previous insn is already in a branch delay | |
1662 | slot, then we can not swap. */ | |
1663 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1664 | /* If the previous previous insn was in a .set |
1665 | noreorder, we can't swap. Actually, the MIPS | |
1666 | assembler will swap in this situation. However, gcc | |
1667 | configured -with-gnu-as will generate code like | |
1668 | .set noreorder | |
1669 | lw $4,XXX | |
1670 | .set reorder | |
1671 | INSN | |
1672 | bne $4,$0,foo | |
1673 | in which we can not swap the bne and INSN. If gcc is | |
1674 | not configured -with-gnu-as, it does not output the | |
1675 | .set pseudo-ops. We don't have to check | |
1676 | prev_insn_unreordered, because prev_insn_valid will | |
1677 | be 0 in that case. We don't want to use | |
1678 | prev_prev_insn_valid, because we do want to be able | |
1679 | to swap at the start of a function. */ | |
1680 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1681 | /* If the branch is itself the target of a branch, we |
1682 | can not swap. We cheat on this; all we check for is | |
1683 | whether there is a label on this instruction. If | |
1684 | there are any branches to anything other than a | |
1685 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1686 | || insn_labels != NULL |
777ad64d | 1687 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1688 | can not do the swap. This does not apply to the |
1689 | mips16, which uses variant frags for different | |
1690 | purposes. */ | |
1691 | || (! mips16 | |
1692 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1693 | /* If the branch reads the condition codes, we don't |
1694 | even try to swap, because in the sequence | |
1695 | ctc1 $X,$31 | |
1696 | INSN | |
1697 | INSN | |
1698 | bc1t LABEL | |
1699 | we can not swap, and I don't feel like handling that | |
1700 | case. */ | |
cc5703cd ILT |
1701 | || (! mips16 |
1702 | && mips_isa < 4 | |
d8a1c247 | 1703 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1704 | /* We can not swap with an instruction that requires a |
1705 | delay slot, becase the target of the branch might | |
1706 | interfere with that instruction. */ | |
cc5703cd ILT |
1707 | || (! mips16 |
1708 | && mips_isa < 4 | |
d8a1c247 KR |
1709 | && (prev_pinfo |
1710 | & (INSN_LOAD_COPROC_DELAY | |
1711 | | INSN_COPROC_MOVE_DELAY | |
1712 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1713 | || (! interlocks |
b2b8c24e ILT |
1714 | && (prev_pinfo |
1715 | & (INSN_READ_LO | |
1716 | | INSN_READ_HI))) | |
cc5703cd ILT |
1717 | || (! mips16 |
1718 | && mips_isa < 2 | |
1aa6938e | 1719 | && (prev_pinfo |
8358c818 ILT |
1720 | & (INSN_LOAD_MEMORY_DELAY |
1721 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1722 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1723 | || (prev_pinfo |
6e8dda9c ILT |
1724 | & (INSN_UNCOND_BRANCH_DELAY |
1725 | | INSN_COND_BRANCH_DELAY | |
1726 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1727 | /* We do not swap with a trap instruction, since it |
1728 | complicates trap handlers to have the trap | |
1729 | instruction be in a delay slot. */ | |
1aa6938e | 1730 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1731 | /* If the branch reads a register that the previous |
1732 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1733 | || (! mips16 |
1734 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1735 | && insn_uses_reg (ip, |
1736 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1737 | & OP_MASK_RT), | |
cc5703cd ILT |
1738 | MIPS_GR_REG)) |
1739 | || (! mips16 | |
1740 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1741 | && insn_uses_reg (ip, |
1742 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1743 | & OP_MASK_RD), | |
cc5703cd ILT |
1744 | MIPS_GR_REG)) |
1745 | || (mips16 | |
1746 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1747 | && insn_uses_reg (ip, | |
1748 | ((prev_insn.insn_opcode | |
1749 | >> MIPS16OP_SH_RX) | |
1750 | & MIPS16OP_MASK_RX), | |
1751 | MIPS16_REG)) | |
1752 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1753 | && insn_uses_reg (ip, | |
1754 | ((prev_insn.insn_opcode | |
1755 | >> MIPS16OP_SH_RY) | |
1756 | & MIPS16OP_MASK_RY), | |
1757 | MIPS16_REG)) | |
1758 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1759 | && insn_uses_reg (ip, | |
1760 | ((prev_insn.insn_opcode | |
1761 | >> MIPS16OP_SH_RZ) | |
1762 | & MIPS16OP_MASK_RZ), | |
1763 | MIPS16_REG)) | |
1764 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1765 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1766 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1767 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1768 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1769 | && insn_uses_reg (ip, | |
1770 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1771 | insn_opcode), | |
1772 | MIPS_GR_REG)))) | |
1849d646 ILT |
1773 | /* If the branch writes a register that the previous |
1774 | instruction sets, we can not swap (we know that | |
1775 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1776 | || (! mips16 |
1777 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1778 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1779 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1780 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1781 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1782 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1783 | & OP_MASK_RT) | |
1784 | == 31)))) | |
cc5703cd ILT |
1785 | || (! mips16 |
1786 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1787 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1788 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1789 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1790 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1791 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1792 | & OP_MASK_RD) | |
1793 | == 31)))) | |
cc5703cd ILT |
1794 | || (mips16 |
1795 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1796 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1797 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1798 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1799 | == RA)))) | |
becfe05e ILT |
1800 | /* If the branch writes a register that the previous |
1801 | instruction reads, we can not swap (we know that | |
1802 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1803 | || (! mips16 |
1804 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1805 | && insn_uses_reg (&prev_insn, |
1806 | ((ip->insn_opcode >> OP_SH_RD) | |
1807 | & OP_MASK_RD), | |
cc5703cd ILT |
1808 | MIPS_GR_REG)) |
1809 | || (! mips16 | |
1810 | && (pinfo & INSN_WRITE_GPR_31) | |
1811 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1812 | || (mips16 | |
1813 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1814 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1815 | /* If we are generating embedded PIC code, the branch |
1816 | might be expanded into a sequence which uses $at, so | |
1817 | we can't swap with an instruction which reads it. */ | |
1818 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1819 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1820 | /* If the previous previous instruction has a load |
1821 | delay, and sets a register that the branch reads, we | |
1822 | can not swap. */ | |
cc5703cd ILT |
1823 | || (! mips16 |
1824 | && mips_isa < 4 | |
d8a1c247 KR |
1825 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1826 | || (mips_isa < 2 | |
1827 | && (prev_prev_insn.insn_mo->pinfo | |
1828 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1829 | && insn_uses_reg (ip, |
1830 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1831 | & OP_MASK_RT), | |
cc5703cd | 1832 | MIPS_GR_REG)) |
d31a3f5e ILT |
1833 | /* If one instruction sets a condition code and the |
1834 | other one uses a condition code, we can not swap. */ | |
1835 | || ((pinfo & INSN_READ_COND_CODE) | |
1836 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1837 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1838 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1839 | /* If the previous instruction uses the PC, we can not | |
1840 | swap. */ | |
1841 | || (mips16 | |
1842 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1843 | /* If the previous instruction was extended, we can not | |
1844 | swap. */ | |
1845 | || (mips16 && prev_insn_extended) | |
1846 | /* If the previous instruction had a fixup in mips16 | |
1847 | mode, we can not swap. This normally means that the | |
1848 | previous instruction was a 4 byte branch anyhow. */ | |
1849 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1850 | { |
1851 | /* We could do even better for unconditional branches to | |
1852 | portions of this object file; we could pick up the | |
1853 | instruction at the destination, put it in the delay | |
1854 | slot, and bump the destination address. */ | |
1855 | emit_nop (); | |
1856 | /* Update the previous insn information. */ | |
1857 | prev_prev_insn = *ip; | |
1858 | prev_insn.insn_mo = &dummy_opcode; | |
1859 | } | |
1860 | else | |
1861 | { | |
becfe05e | 1862 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1863 | if (! mips16) |
1864 | { | |
1865 | char *prev_f; | |
1866 | char temp[4]; | |
1867 | ||
1868 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1869 | memcpy (temp, prev_f, 4); | |
1870 | memcpy (prev_f, f, 4); | |
1871 | memcpy (f, temp, 4); | |
1872 | if (prev_insn_fixp) | |
1873 | { | |
1874 | prev_insn_fixp->fx_frag = frag_now; | |
1875 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1876 | } | |
1877 | if (fixp) | |
1878 | { | |
1879 | fixp->fx_frag = prev_insn_frag; | |
1880 | fixp->fx_where = prev_insn_where; | |
1881 | } | |
1882 | } | |
1883 | else if (reloc_type > BFD_RELOC_UNUSED) | |
becfe05e | 1884 | { |
cc5703cd ILT |
1885 | char *prev_f; |
1886 | char temp[2]; | |
1887 | ||
1888 | /* We are in mips16 mode, and we have just created a | |
1889 | variant frag. We need to extract the old | |
1890 | instruction from the end of the previous frag, | |
1891 | and add it to a new frag. */ | |
1892 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1893 | memcpy (temp, prev_f, 2); | |
1894 | prev_insn_frag->fr_fix -= 2; | |
1895 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
1896 | { | |
1897 | assert (prev_insn_where == prev_insn_frag->fr_fix); | |
1898 | memcpy (prev_f, prev_f + 2, 2); | |
1899 | } | |
1900 | memcpy (frag_more (2), temp, 2); | |
becfe05e | 1901 | } |
cc5703cd | 1902 | else |
becfe05e | 1903 | { |
cc5703cd ILT |
1904 | char *prev_f; |
1905 | char temp[2]; | |
1906 | ||
1907 | assert (prev_insn_fixp == NULL); | |
1908 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1909 | memcpy (temp, prev_f, 2); | |
1910 | memcpy (prev_f, f, 2); | |
1911 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
1912 | memcpy (f, temp, 2); | |
1913 | else | |
1914 | { | |
1915 | memcpy (f, f + 2, 2); | |
1916 | memcpy (f + 2, temp, 2); | |
1917 | } | |
1918 | if (fixp) | |
1919 | { | |
1920 | fixp->fx_frag = prev_insn_frag; | |
1921 | fixp->fx_where = prev_insn_where; | |
1922 | } | |
becfe05e | 1923 | } |
cc5703cd | 1924 | |
becfe05e ILT |
1925 | /* Update the previous insn information; leave prev_insn |
1926 | unchanged. */ | |
1927 | prev_prev_insn = *ip; | |
1928 | } | |
1929 | prev_insn_is_delay_slot = 1; | |
1930 | ||
1931 | /* If that was an unconditional branch, forget the previous | |
1932 | insn information. */ | |
1aa6938e | 1933 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1934 | { |
1935 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1936 | prev_insn.insn_mo = &dummy_opcode; | |
1937 | } | |
a677feeb ILT |
1938 | |
1939 | prev_insn_fixp = NULL; | |
1940 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1941 | prev_insn_extended = 0; | |
becfe05e | 1942 | } |
1aa6938e | 1943 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1944 | { |
1945 | /* We don't yet optimize a branch likely. What we should do | |
1946 | is look at the target, copy the instruction found there | |
1947 | into the delay slot, and increment the branch to jump to | |
1948 | the next instruction. */ | |
1949 | emit_nop (); | |
1950 | /* Update the previous insn information. */ | |
1951 | prev_prev_insn = *ip; | |
1952 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
1953 | prev_insn_fixp = NULL; |
1954 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1955 | prev_insn_extended = 0; | |
8358c818 | 1956 | } |
becfe05e | 1957 | else |
670a50eb | 1958 | { |
becfe05e ILT |
1959 | /* Update the previous insn information. */ |
1960 | if (nops > 0) | |
1961 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1962 | else | |
1963 | prev_prev_insn = prev_insn; | |
1964 | prev_insn = *ip; | |
1965 | ||
1966 | /* Any time we see a branch, we always fill the delay slot | |
1967 | immediately; since this insn is not a branch, we know it | |
1968 | is not in a delay slot. */ | |
1969 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
1970 | |
1971 | prev_insn_fixp = fixp; | |
1972 | prev_insn_reloc_type = reloc_type; | |
1973 | if (mips16) | |
1974 | prev_insn_extended = (ip->use_extend | |
1975 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
1976 | } |
1977 | ||
4e95866e ILT |
1978 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1979 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1980 | prev_insn_frag = frag_now; |
1981 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
1982 | prev_insn_valid = 1; |
1983 | } | |
fbcfacb7 | 1984 | else if (place == NULL) |
a677feeb | 1985 | { |
fbcfacb7 | 1986 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
1987 | reordering, in order to determine the base address for mips16 |
1988 | PC relative relocs. */ | |
1989 | prev_insn = *ip; | |
1990 | prev_insn_reloc_type = reloc_type; | |
035936da | 1991 | prev_insn_valid = 1; |
a677feeb | 1992 | } |
3d3c5039 | 1993 | |
becfe05e | 1994 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 1995 | mips_clear_insn_labels (); |
becfe05e ILT |
1996 | } |
1997 | ||
1998 | /* This function forgets that there was any previous instruction or | |
1999 | label. */ | |
2000 | ||
2001 | static void | |
2002 | mips_no_prev_insn () | |
2003 | { | |
2004 | prev_insn.insn_mo = &dummy_opcode; | |
2005 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2006 | prev_insn_valid = 0; | |
2007 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2008 | prev_insn_unreordered = 0; |
cc5703cd | 2009 | prev_insn_extended = 0; |
a677feeb | 2010 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2011 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2012 | mips_clear_insn_labels (); |
becfe05e ILT |
2013 | } |
2014 | ||
2015 | /* This function must be called whenever we turn on noreorder or emit | |
2016 | something other than instructions. It inserts any NOPS which might | |
2017 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2018 | kept for the previous instructions. The INSNS parameter is true if |
2019 | instructions are to follow. */ | |
becfe05e ILT |
2020 | |
2021 | static void | |
fbcfacb7 ILT |
2022 | mips_emit_delays (insns) |
2023 | boolean insns; | |
becfe05e ILT |
2024 | { |
2025 | if (! mips_noreorder) | |
2026 | { | |
2027 | int nop; | |
2028 | ||
2029 | nop = 0; | |
cc5703cd ILT |
2030 | if ((! mips16 |
2031 | && mips_isa < 4 | |
344a8d61 JSC |
2032 | && (! cop_interlocks |
2033 | && (prev_insn.insn_mo->pinfo | |
2034 | & (INSN_LOAD_COPROC_DELAY | |
2035 | | INSN_COPROC_MOVE_DELAY | |
2036 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 2037 | || (! interlocks |
b2b8c24e ILT |
2038 | && (prev_insn.insn_mo->pinfo |
2039 | & (INSN_READ_LO | |
2040 | | INSN_READ_HI))) | |
cc5703cd ILT |
2041 | || (! mips16 |
2042 | && mips_isa < 2 | |
8358c818 ILT |
2043 | && (prev_insn.insn_mo->pinfo |
2044 | & (INSN_LOAD_MEMORY_DELAY | |
2045 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
2046 | { |
2047 | nop = 1; | |
cc5703cd ILT |
2048 | if ((! mips16 |
2049 | && mips_isa < 4 | |
344a8d61 JSC |
2050 | && (! cop_interlocks |
2051 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2052 | || (! interlocks |
b2b8c24e ILT |
2053 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2054 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
2055 | emit_nop (); |
2056 | } | |
cc5703cd ILT |
2057 | else if ((! mips16 |
2058 | && mips_isa < 4 | |
344a8d61 JSC |
2059 | && (! cop_interlocks |
2060 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2061 | || (! interlocks |
b2b8c24e ILT |
2062 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2063 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
2064 | nop = 1; |
2065 | if (nop) | |
670a50eb | 2066 | { |
fbcfacb7 ILT |
2067 | struct insn_label_list *l; |
2068 | ||
becfe05e | 2069 | emit_nop (); |
fbcfacb7 | 2070 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2071 | { |
fbcfacb7 ILT |
2072 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2073 | l->label->sy_frag = frag_now; | |
2074 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2075 | /* mips16 text labels are stored as odd. */ | |
2076 | if (mips16) | |
2077 | ++l->label->sy_value.X_add_number; | |
becfe05e | 2078 | } |
3d3c5039 ILT |
2079 | } |
2080 | } | |
0221ddf7 | 2081 | |
fbcfacb7 ILT |
2082 | /* Mark instruction labels in mips16 mode. This permits the linker |
2083 | to handle them specially, such as generating jalx instructions | |
2084 | when needed. We also make them odd for the duration of the | |
2085 | assembly, in order to generate the right sort of code. We will | |
2086 | make them even in the adjust_symtab routine, while leaving them | |
2087 | marked. This is convenient for the debugger and the | |
2088 | disassembler. The linker knows to make them odd again. */ | |
2089 | if (mips16 && insns) | |
2090 | { | |
2091 | struct insn_label_list *l; | |
2092 | ||
2093 | for (l = insn_labels; l != NULL; l = l->next) | |
2094 | { | |
2095 | #ifdef S_SET_OTHER | |
2096 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2097 | S_SET_OTHER (l->label, STO_MIPS16); | |
2098 | #endif | |
2099 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
2100 | ++l->label->sy_value.X_add_number; | |
2101 | } | |
2102 | } | |
2103 | ||
0221ddf7 | 2104 | mips_no_prev_insn (); |
3d3c5039 ILT |
2105 | } |
2106 | ||
670a50eb ILT |
2107 | /* Build an instruction created by a macro expansion. This is passed |
2108 | a pointer to the count of instructions created so far, an | |
2109 | expression, the name of the instruction to build, an operand format | |
2110 | string, and corresponding arguments. */ | |
2111 | ||
1dc1e798 | 2112 | #ifdef USE_STDARG |
3d3c5039 | 2113 | static void |
0dd2d296 ILT |
2114 | macro_build (char *place, |
2115 | int *counter, | |
670a50eb | 2116 | expressionS * ep, |
3d3c5039 ILT |
2117 | const char *name, |
2118 | const char *fmt, | |
2119 | ...) | |
1dc1e798 | 2120 | #else |
3d3c5039 | 2121 | static void |
0dd2d296 ILT |
2122 | macro_build (place, counter, ep, name, fmt, va_alist) |
2123 | char *place; | |
3d3c5039 ILT |
2124 | int *counter; |
2125 | expressionS *ep; | |
2126 | const char *name; | |
2127 | const char *fmt; | |
2128 | va_dcl | |
1dc1e798 | 2129 | #endif |
3d3c5039 | 2130 | { |
670a50eb ILT |
2131 | struct mips_cl_insn insn; |
2132 | bfd_reloc_code_real_type r; | |
2133 | va_list args; | |
3d3c5039 | 2134 | |
1dc1e798 | 2135 | #ifdef USE_STDARG |
670a50eb | 2136 | va_start (args, fmt); |
3d3c5039 | 2137 | #else |
670a50eb | 2138 | va_start (args); |
3d3c5039 ILT |
2139 | #endif |
2140 | ||
670a50eb ILT |
2141 | /* |
2142 | * If the macro is about to expand into a second instruction, | |
2143 | * print a warning if needed. We need to pass ip as a parameter | |
2144 | * to generate a better warning message here... | |
2145 | */ | |
0dd2d296 | 2146 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2147 | as_warn ("Macro instruction expanded into multiple instructions"); |
2148 | ||
0dd2d296 ILT |
2149 | if (place == NULL) |
2150 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2151 | |
cc5703cd ILT |
2152 | if (mips16) |
2153 | { | |
2154 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2155 | va_end (args); | |
2156 | return; | |
2157 | } | |
2158 | ||
670a50eb ILT |
2159 | r = BFD_RELOC_UNUSED; |
2160 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2161 | assert (insn.insn_mo); | |
2162 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2163 | ||
9226253a | 2164 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
2165 | || insn.insn_mo->pinfo == INSN_MACRO |
2166 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
2167 | && mips_isa < 2) | |
2168 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
2169 | && mips_isa < 3) | |
2170 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
2171 | && mips_isa < 4) | |
2172 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
2173 | && ! mips_4650) | |
2174 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
2175 | && ! mips_4010) | |
2176 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
276c2d7d GRK |
2177 | && ! mips_4100) |
2178 | /* start-sanitize-r5900 */ | |
2179 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_5900 | |
2180 | && ! mips_5900) | |
2181 | /* end-sanitize-r5900 */ | |
2182 | ) | |
670a50eb ILT |
2183 | { |
2184 | ++insn.insn_mo; | |
2185 | assert (insn.insn_mo->name); | |
2186 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2187 | } |
670a50eb ILT |
2188 | insn.insn_opcode = insn.insn_mo->match; |
2189 | for (;;) | |
2190 | { | |
2191 | switch (*fmt++) | |
2192 | { | |
3d3c5039 | 2193 | case '\0': |
670a50eb | 2194 | break; |
3d3c5039 ILT |
2195 | |
2196 | case ',': | |
2197 | case '(': | |
2198 | case ')': | |
670a50eb | 2199 | continue; |
3d3c5039 ILT |
2200 | |
2201 | case 't': | |
2202 | case 'w': | |
918692a5 | 2203 | case 'E': |
670a50eb ILT |
2204 | insn.insn_opcode |= va_arg (args, int) << 16; |
2205 | continue; | |
3d3c5039 ILT |
2206 | |
2207 | case 'c': | |
2208 | case 'T': | |
2209 | case 'W': | |
670a50eb ILT |
2210 | insn.insn_opcode |= va_arg (args, int) << 16; |
2211 | continue; | |
3d3c5039 ILT |
2212 | |
2213 | case 'd': | |
918692a5 | 2214 | case 'G': |
670a50eb ILT |
2215 | insn.insn_opcode |= va_arg (args, int) << 11; |
2216 | continue; | |
3d3c5039 ILT |
2217 | |
2218 | case 'V': | |
2219 | case 'S': | |
670a50eb ILT |
2220 | insn.insn_opcode |= va_arg (args, int) << 11; |
2221 | continue; | |
3d3c5039 | 2222 | |
ff3a5c18 ILT |
2223 | case 'z': |
2224 | continue; | |
2225 | ||
3d3c5039 | 2226 | case '<': |
670a50eb ILT |
2227 | insn.insn_opcode |= va_arg (args, int) << 6; |
2228 | continue; | |
3d3c5039 ILT |
2229 | |
2230 | case 'D': | |
670a50eb ILT |
2231 | insn.insn_opcode |= va_arg (args, int) << 6; |
2232 | continue; | |
3d3c5039 | 2233 | |
918692a5 ILT |
2234 | case 'B': |
2235 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2236 | continue; | |
2237 | ||
3d3c5039 ILT |
2238 | case 'b': |
2239 | case 's': | |
2240 | case 'r': | |
2241 | case 'v': | |
670a50eb ILT |
2242 | insn.insn_opcode |= va_arg (args, int) << 21; |
2243 | continue; | |
3d3c5039 ILT |
2244 | |
2245 | case 'i': | |
2246 | case 'j': | |
2247 | case 'o': | |
9226253a | 2248 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2249 | assert (r == BFD_RELOC_MIPS_GPREL |
2250 | || r == BFD_RELOC_MIPS_LITERAL | |
2251 | || r == BFD_RELOC_LO16 | |
2252 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2253 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2254 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2255 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2256 | || (ep->X_op == O_subtract |
2257 | && now_seg == text_section | |
ecd4ca1c | 2258 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2259 | continue; |
3d3c5039 | 2260 | |
6e8dda9c | 2261 | case 'u': |
ecd4ca1c ILT |
2262 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2263 | assert (ep != NULL | |
2264 | && (ep->X_op == O_constant | |
2265 | || (ep->X_op == O_symbol | |
2266 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2267 | || r == BFD_RELOC_HI16 |
2268 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2269 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2270 | || (ep->X_op == O_subtract |
2271 | && now_seg == text_section | |
ecd4ca1c ILT |
2272 | && r == BFD_RELOC_PCREL_HI16_S))); |
2273 | if (ep->X_op == O_constant) | |
2274 | { | |
2275 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2276 | ep = NULL; | |
2277 | r = BFD_RELOC_UNUSED; | |
2278 | } | |
6e8dda9c ILT |
2279 | continue; |
2280 | ||
3d3c5039 | 2281 | case 'p': |
670a50eb ILT |
2282 | assert (ep != NULL); |
2283 | /* | |
2284 | * This allows macro() to pass an immediate expression for | |
2285 | * creating short branches without creating a symbol. | |
2286 | * Note that the expression still might come from the assembly | |
2287 | * input, in which case the value is not checked for range nor | |
2288 | * is a relocation entry generated (yuck). | |
2289 | */ | |
5ac34ac3 | 2290 | if (ep->X_op == O_constant) |
670a50eb ILT |
2291 | { |
2292 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2293 | ep = NULL; | |
2294 | } | |
2295 | else | |
2296 | r = BFD_RELOC_16_PCREL_S2; | |
2297 | continue; | |
3d3c5039 | 2298 | |
9226253a ILT |
2299 | case 'a': |
2300 | assert (ep != NULL); | |
2301 | r = BFD_RELOC_MIPS_JMP; | |
2302 | continue; | |
2303 | ||
3d3c5039 | 2304 | default: |
670a50eb | 2305 | internalError (); |
3d3c5039 | 2306 | } |
670a50eb | 2307 | break; |
3d3c5039 | 2308 | } |
670a50eb ILT |
2309 | va_end (args); |
2310 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2311 | ||
867a58b3 | 2312 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2313 | } |
2314 | ||
cc5703cd ILT |
2315 | static void |
2316 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2317 | char *place; | |
2318 | int *counter; | |
2319 | expressionS *ep; | |
2320 | const char *name; | |
2321 | const char *fmt; | |
2322 | va_list args; | |
2323 | { | |
2324 | struct mips_cl_insn insn; | |
2325 | bfd_reloc_code_real_type r; | |
2326 | ||
2327 | r = BFD_RELOC_UNUSED; | |
2328 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2329 | assert (insn.insn_mo); | |
2330 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2331 | ||
2332 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2333 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2334 | { | |
2335 | ++insn.insn_mo; | |
2336 | assert (insn.insn_mo->name); | |
2337 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2338 | } | |
2339 | ||
2340 | insn.insn_opcode = insn.insn_mo->match; | |
2341 | insn.use_extend = false; | |
2342 | ||
2343 | for (;;) | |
2344 | { | |
2345 | int c; | |
2346 | ||
2347 | c = *fmt++; | |
2348 | switch (c) | |
2349 | { | |
2350 | case '\0': | |
2351 | break; | |
2352 | ||
2353 | case ',': | |
2354 | case '(': | |
2355 | case ')': | |
2356 | continue; | |
2357 | ||
2358 | case 'y': | |
2359 | case 'w': | |
2360 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2361 | continue; | |
2362 | ||
2363 | case 'x': | |
2364 | case 'v': | |
2365 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2366 | continue; | |
2367 | ||
2368 | case 'z': | |
2369 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2370 | continue; | |
2371 | ||
2372 | case 'Z': | |
2373 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2374 | continue; | |
2375 | ||
2376 | case '0': | |
2377 | case 'S': | |
2378 | case 'P': | |
2379 | case 'R': | |
2380 | continue; | |
2381 | ||
2382 | case 'X': | |
2383 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2384 | continue; | |
2385 | ||
2386 | case 'Y': | |
2387 | { | |
2388 | int regno; | |
2389 | ||
2390 | regno = va_arg (args, int); | |
2391 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2392 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2393 | } | |
2394 | continue; | |
2395 | ||
2396 | case '<': | |
2397 | case '>': | |
2398 | case '4': | |
2399 | case '5': | |
2400 | case 'H': | |
2401 | case 'W': | |
2402 | case 'D': | |
2403 | case 'j': | |
2404 | case '8': | |
2405 | case 'V': | |
2406 | case 'C': | |
2407 | case 'U': | |
2408 | case 'k': | |
2409 | case 'K': | |
2410 | case 'p': | |
2411 | case 'q': | |
2412 | { | |
2413 | assert (ep != NULL); | |
2414 | ||
2415 | if (ep->X_op != O_constant) | |
2416 | r = BFD_RELOC_UNUSED + c; | |
2417 | else | |
2418 | { | |
15e69f98 ILT |
2419 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2420 | false, false, &insn.insn_opcode, | |
2421 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2422 | ep = NULL; |
2423 | r = BFD_RELOC_UNUSED; | |
2424 | } | |
2425 | } | |
2426 | continue; | |
2427 | ||
2428 | case '6': | |
2429 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2430 | continue; | |
2431 | } | |
2432 | ||
2433 | break; | |
2434 | } | |
2435 | ||
2436 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2437 | ||
2438 | append_insn (place, &insn, ep, r, false); | |
2439 | } | |
2440 | ||
3d3c5039 ILT |
2441 | /* |
2442 | * Generate a "lui" instruction. | |
2443 | */ | |
2444 | static void | |
0dd2d296 ILT |
2445 | macro_build_lui (place, counter, ep, regnum) |
2446 | char *place; | |
3d3c5039 ILT |
2447 | int *counter; |
2448 | expressionS *ep; | |
2449 | int regnum; | |
2450 | { | |
670a50eb ILT |
2451 | expressionS high_expr; |
2452 | struct mips_cl_insn insn; | |
2453 | bfd_reloc_code_real_type r; | |
2454 | CONST char *name = "lui"; | |
2455 | CONST char *fmt = "t,u"; | |
2456 | ||
cc5703cd ILT |
2457 | assert (! mips16); |
2458 | ||
0dd2d296 ILT |
2459 | if (place == NULL) |
2460 | high_expr = *ep; | |
2461 | else | |
2462 | { | |
2463 | high_expr.X_op = O_constant; | |
fb251650 | 2464 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2465 | } |
670a50eb | 2466 | |
5ac34ac3 | 2467 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2468 | { |
2469 | /* we can compute the instruction now without a relocation entry */ | |
2470 | if (high_expr.X_add_number & 0x8000) | |
2471 | high_expr.X_add_number += 0x10000; | |
2472 | high_expr.X_add_number = | |
2473 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2474 | r = BFD_RELOC_UNUSED; | |
2475 | } | |
2476 | else | |
0dd2d296 ILT |
2477 | { |
2478 | assert (ep->X_op == O_symbol); | |
2479 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2480 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2481 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2482 | r = BFD_RELOC_HI16_S; | |
2483 | } | |
670a50eb ILT |
2484 | |
2485 | /* | |
2486 | * If the macro is about to expand into a second instruction, | |
2487 | * print a warning if needed. We need to pass ip as a parameter | |
2488 | * to generate a better warning message here... | |
2489 | */ | |
0dd2d296 | 2490 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2491 | as_warn ("Macro instruction expanded into multiple instructions"); |
2492 | ||
0dd2d296 ILT |
2493 | if (place == NULL) |
2494 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2495 | |
2496 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2497 | assert (insn.insn_mo); | |
2498 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2499 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2500 | ||
0dd2d296 | 2501 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2502 | if (r == BFD_RELOC_UNUSED) |
2503 | { | |
2504 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2505 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2506 | } |
2507 | else | |
867a58b3 | 2508 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2509 | } |
2510 | ||
2511 | /* set_at() | |
2512 | * Generates code to set the $at register to true (one) | |
2513 | * if reg is less than the immediate expression. | |
2514 | */ | |
2515 | static void | |
6e8dda9c | 2516 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2517 | int *counter; |
2518 | int reg; | |
6e8dda9c | 2519 | int unsignedp; |
3d3c5039 | 2520 | { |
6e8dda9c | 2521 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2522 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2523 | unsignedp ? "sltiu" : "slti", |
9226253a | 2524 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2525 | else |
670a50eb | 2526 | { |
d8a1c247 | 2527 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2528 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2529 | unsignedp ? "sltu" : "slt", |
2530 | "d,v,t", AT, reg, AT); | |
670a50eb | 2531 | } |
3d3c5039 ILT |
2532 | } |
2533 | ||
6e8dda9c | 2534 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2535 | |
2536 | static void | |
19ed8960 | 2537 | check_absolute_expr (ip, ex) |
3d3c5039 | 2538 | struct mips_cl_insn *ip; |
19ed8960 | 2539 | expressionS *ex; |
3d3c5039 | 2540 | { |
19ed8960 | 2541 | if (ex->X_op != O_constant) |
670a50eb | 2542 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2543 | } |
2544 | ||
ff8716f5 JSC |
2545 | /* Count the leading zeroes by performing a binary chop. This is a |
2546 | bulky bit of source, but performance is a LOT better for the | |
2547 | majority of values than a simple loop to count the bits: | |
2548 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2549 | if ((v) & (1 << (31 - lcnt))) | |
2550 | break; | |
2551 | However it is not code size friendly, and the gain will drop a bit | |
2552 | on certain cached systems. | |
2553 | */ | |
2554 | #define COUNT_TOP_ZEROES(v) \ | |
2555 | (((v) & ~0xffff) == 0 \ | |
2556 | ? ((v) & ~0xff) == 0 \ | |
2557 | ? ((v) & ~0xf) == 0 \ | |
2558 | ? ((v) & ~0x3) == 0 \ | |
2559 | ? ((v) & ~0x1) == 0 \ | |
2560 | ? !(v) \ | |
2561 | ? 32 \ | |
2562 | : 31 \ | |
2563 | : 30 \ | |
2564 | : ((v) & ~0x7) == 0 \ | |
2565 | ? 29 \ | |
2566 | : 28 \ | |
2567 | : ((v) & ~0x3f) == 0 \ | |
2568 | ? ((v) & ~0x1f) == 0 \ | |
2569 | ? 27 \ | |
2570 | : 26 \ | |
2571 | : ((v) & ~0x7f) == 0 \ | |
2572 | ? 25 \ | |
2573 | : 24 \ | |
2574 | : ((v) & ~0xfff) == 0 \ | |
2575 | ? ((v) & ~0x3ff) == 0 \ | |
2576 | ? ((v) & ~0x1ff) == 0 \ | |
2577 | ? 23 \ | |
2578 | : 22 \ | |
2579 | : ((v) & ~0x7ff) == 0 \ | |
2580 | ? 21 \ | |
2581 | : 20 \ | |
2582 | : ((v) & ~0x3fff) == 0 \ | |
2583 | ? ((v) & ~0x1fff) == 0 \ | |
2584 | ? 19 \ | |
2585 | : 18 \ | |
2586 | : ((v) & ~0x7fff) == 0 \ | |
2587 | ? 17 \ | |
2588 | : 16 \ | |
2589 | : ((v) & ~0xffffff) == 0 \ | |
2590 | ? ((v) & ~0xfffff) == 0 \ | |
2591 | ? ((v) & ~0x3ffff) == 0 \ | |
2592 | ? ((v) & ~0x1ffff) == 0 \ | |
2593 | ? 15 \ | |
2594 | : 14 \ | |
2595 | : ((v) & ~0x7ffff) == 0 \ | |
2596 | ? 13 \ | |
2597 | : 12 \ | |
2598 | : ((v) & ~0x3fffff) == 0 \ | |
2599 | ? ((v) & ~0x1fffff) == 0 \ | |
2600 | ? 11 \ | |
2601 | : 10 \ | |
2602 | : ((v) & ~0x7fffff) == 0 \ | |
2603 | ? 9 \ | |
2604 | : 8 \ | |
2605 | : ((v) & ~0xfffffff) == 0 \ | |
2606 | ? ((v) & ~0x3ffffff) == 0 \ | |
2607 | ? ((v) & ~0x1ffffff) == 0 \ | |
2608 | ? 7 \ | |
2609 | : 6 \ | |
2610 | : ((v) & ~0x7ffffff) == 0 \ | |
2611 | ? 5 \ | |
2612 | : 4 \ | |
2613 | : ((v) & ~0x3fffffff) == 0 \ | |
2614 | ? ((v) & ~0x1fffffff) == 0 \ | |
2615 | ? 3 \ | |
2616 | : 2 \ | |
2617 | : ((v) & ~0x7fffffff) == 0 \ | |
2618 | ? 1 \ | |
2619 | : 0) | |
2620 | ||
3d3c5039 ILT |
2621 | /* load_register() |
2622 | * This routine generates the least number of instructions neccessary to load | |
2623 | * an absolute expression value into a register. | |
2624 | */ | |
2625 | static void | |
d8a1c247 | 2626 | load_register (counter, reg, ep, dbl) |
670a50eb | 2627 | int *counter; |
670a50eb ILT |
2628 | int reg; |
2629 | expressionS *ep; | |
d8a1c247 | 2630 | int dbl; |
3d3c5039 | 2631 | { |
c36a90ef ILT |
2632 | int freg; |
2633 | expressionS hi32, lo32; | |
847a01cd ILT |
2634 | |
2635 | if (ep->X_op != O_big) | |
6e8dda9c | 2636 | { |
847a01cd | 2637 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2638 | if (ep->X_add_number < 0x8000 |
2639 | && (ep->X_add_number >= 0 | |
2640 | || (ep->X_add_number >= -0x8000 | |
2641 | && (! dbl | |
2642 | || ! ep->X_unsigned | |
2643 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2644 | { |
2645 | /* We can handle 16 bit signed values with an addiu to | |
2646 | $zero. No need to ever use daddiu here, since $zero and | |
2647 | the result are always correct in 32 bit mode. */ | |
2648 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2649 | (int) BFD_RELOC_LO16); | |
2650 | return; | |
2651 | } | |
2652 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2653 | { | |
2654 | /* We can handle 16 bit unsigned values with an ori to | |
2655 | $zero. */ | |
2656 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2657 | (int) BFD_RELOC_LO16); | |
2658 | return; | |
2659 | } | |
98bfd087 ILT |
2660 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2661 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2662 | == ~ (offsetT) 0x7fffffff)) | |
2663 | && (! dbl | |
2664 | || ! ep->X_unsigned | |
2665 | || sizeof (ep->X_add_number) > 4 | |
2666 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2667 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2668 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2669 | { |
2670 | /* 32 bit values require an lui. */ | |
2671 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2672 | (int) BFD_RELOC_HI16); | |
2673 | if ((ep->X_add_number & 0xffff) != 0) | |
2674 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2675 | (int) BFD_RELOC_LO16); | |
2676 | return; | |
2677 | } | |
6e8dda9c | 2678 | } |
847a01cd ILT |
2679 | |
2680 | /* The value is larger than 32 bits. */ | |
2681 | ||
2682 | if (mips_isa < 3) | |
670a50eb | 2683 | { |
6e8dda9c | 2684 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2685 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2686 | (int) BFD_RELOC_LO16); |
847a01cd | 2687 | return; |
6e8dda9c | 2688 | } |
6e8dda9c | 2689 | |
847a01cd ILT |
2690 | if (ep->X_op != O_big) |
2691 | { | |
6e8dda9c | 2692 | hi32 = *ep; |
c36a90ef ILT |
2693 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2694 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2695 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2696 | lo32 = *ep; |
2697 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2698 | } |
847a01cd ILT |
2699 | else |
2700 | { | |
2701 | assert (ep->X_add_number > 2); | |
2702 | if (ep->X_add_number == 3) | |
2703 | generic_bignum[3] = 0; | |
2704 | else if (ep->X_add_number > 4) | |
2705 | as_bad ("Number larger than 64 bits"); | |
2706 | lo32.X_op = O_constant; | |
2707 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2708 | hi32.X_op = O_constant; | |
2709 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2710 | } | |
2711 | ||
d8a1c247 KR |
2712 | if (hi32.X_add_number == 0) |
2713 | freg = 0; | |
2714 | else | |
2715 | { | |
c36a90ef ILT |
2716 | int shift, bit; |
2717 | unsigned long hi, lo; | |
2718 | ||
fb251650 ILT |
2719 | if (hi32.X_add_number == 0xffffffff) |
2720 | { | |
2721 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2722 | { | |
c36a90ef ILT |
2723 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2724 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2725 | return; |
2726 | } | |
2727 | if (lo32.X_add_number & 0x80000000) | |
2728 | { | |
2729 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2730 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2731 | if (lo32.X_add_number & 0xffff) |
2732 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2733 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2734 | return; |
2735 | } | |
2736 | } | |
ff8716f5 | 2737 | |
c36a90ef ILT |
2738 | /* Check for 16bit shifted constant. We know that hi32 is |
2739 | non-zero, so start the mask on the first bit of the hi32 | |
2740 | value. */ | |
ff8716f5 JSC |
2741 | shift = 17; |
2742 | do | |
2743 | { | |
c36a90ef ILT |
2744 | unsigned long himask, lomask; |
2745 | ||
2746 | if (shift < 32) | |
2747 | { | |
2748 | himask = 0xffff >> (32 - shift); | |
2749 | lomask = (0xffff << shift) & 0xffffffff; | |
2750 | } | |
2751 | else | |
2752 | { | |
2753 | himask = 0xffff << (shift - 32); | |
2754 | lomask = 0; | |
2755 | } | |
2756 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2757 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2758 | { | |
2759 | expressionS tmp; | |
2760 | ||
2761 | tmp.X_op = O_constant; | |
2762 | if (shift < 32) | |
2763 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2764 | | (lo32.X_add_number >> shift)); | |
2765 | else | |
2766 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2767 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2768 | (int) BFD_RELOC_LO16); | |
2769 | macro_build ((char *) NULL, counter, NULL, | |
2770 | (shift >= 32) ? "dsll32" : "dsll", | |
2771 | "d,w,<", reg, reg, | |
2772 | (shift >= 32) ? shift - 32 : shift); | |
2773 | return; | |
2774 | } | |
ff8716f5 JSC |
2775 | shift++; |
2776 | } while (shift <= (64 - 16)); | |
2777 | ||
c36a90ef ILT |
2778 | /* Find the bit number of the lowest one bit, and store the |
2779 | shifted value in hi/lo. */ | |
2780 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
2781 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
2782 | if (lo != 0) | |
2783 | { | |
2784 | bit = 0; | |
2785 | while ((lo & 1) == 0) | |
2786 | { | |
2787 | lo >>= 1; | |
2788 | ++bit; | |
2789 | } | |
2790 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
2791 | hi >>= bit; | |
2792 | } | |
2793 | else | |
2794 | { | |
2795 | bit = 32; | |
2796 | while ((hi & 1) == 0) | |
2797 | { | |
2798 | hi >>= 1; | |
2799 | ++bit; | |
2800 | } | |
2801 | lo = hi; | |
2802 | hi = 0; | |
2803 | } | |
2804 | ||
2805 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
2806 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
2807 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 2808 | { |
c36a90ef | 2809 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
2810 | if (shift != 0) |
2811 | { | |
c36a90ef ILT |
2812 | expressionS tmp; |
2813 | ||
2814 | /* This instruction will set the register to be all | |
2815 | ones. */ | |
ff8716f5 | 2816 | tmp.X_op = O_constant; |
c36a90ef ILT |
2817 | tmp.X_add_number = (offsetT) -1; |
2818 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
2819 | reg, 0, (int) BFD_RELOC_LO16); | |
2820 | if (bit != 0) | |
ff8716f5 | 2821 | { |
c36a90ef | 2822 | bit += shift; |
ff8716f5 | 2823 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 2824 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 2825 | "d,w,<", reg, reg, |
c36a90ef | 2826 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 2827 | } |
c36a90ef ILT |
2828 | macro_build ((char *) NULL, counter, NULL, |
2829 | (shift >= 32) ? "dsrl32" : "dsrl", | |
2830 | "d,w,<", reg, reg, | |
2831 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
2832 | return; |
2833 | } | |
2834 | } | |
c36a90ef ILT |
2835 | |
2836 | /* Sign extend hi32 before calling load_register, because we can | |
2837 | generally get better code when we load a sign extended value. */ | |
2838 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2839 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
2840 | load_register (counter, reg, &hi32, 0); |
2841 | freg = reg; | |
2842 | } | |
847a01cd | 2843 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2844 | { |
2845 | if (freg != 0) | |
2846 | { | |
2847 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2848 | freg, 0); | |
2849 | freg = reg; | |
2850 | } | |
2851 | } | |
847a01cd ILT |
2852 | else |
2853 | { | |
2854 | expressionS mid16; | |
2855 | ||
fb251650 ILT |
2856 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2857 | { | |
2858 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2859 | (int) BFD_RELOC_HI16); | |
2860 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2861 | reg, 0); |
fb251650 ILT |
2862 | return; |
2863 | } | |
2864 | ||
d8a1c247 KR |
2865 | if (freg != 0) |
2866 | { | |
2867 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2868 | freg, 16); | |
2869 | freg = reg; | |
2870 | } | |
847a01cd ILT |
2871 | mid16 = lo32; |
2872 | mid16.X_add_number >>= 16; | |
2873 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 2874 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
2875 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
2876 | reg, 16); | |
d8a1c247 | 2877 | freg = reg; |
847a01cd ILT |
2878 | } |
2879 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 2880 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 2881 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
2882 | } |
2883 | ||
0dd2d296 ILT |
2884 | /* Load an address into a register. */ |
2885 | ||
2886 | static void | |
2887 | load_address (counter, reg, ep) | |
2888 | int *counter; | |
2889 | int reg; | |
2890 | expressionS *ep; | |
2891 | { | |
2892 | char *p; | |
2893 | ||
2894 | if (ep->X_op != O_constant | |
2895 | && ep->X_op != O_symbol) | |
2896 | { | |
2897 | as_bad ("expression too complex"); | |
2898 | ep->X_op = O_constant; | |
2899 | } | |
2900 | ||
2901 | if (ep->X_op == O_constant) | |
d9aba805 | 2902 | { |
d8a1c247 | 2903 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
2904 | return; |
2905 | } | |
2906 | ||
2907 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
2908 | { |
2909 | /* If this is a reference to a GP relative symbol, we want | |
2910 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2911 | Otherwise we want | |
04cb3372 | 2912 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
2913 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
2914 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
2915 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
2916 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
2917 | p = NULL; |
2918 | else | |
2919 | { | |
8ea7f4e8 | 2920 | frag_grow (20); |
0dd2d296 ILT |
2921 | macro_build ((char *) NULL, counter, ep, |
2922 | mips_isa < 3 ? "addiu" : "daddiu", | |
2923 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2924 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 2925 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
2926 | ep->X_add_symbol, (long) 0, (char *) NULL); |
2927 | } | |
2928 | macro_build_lui (p, counter, ep, reg); | |
2929 | if (p != NULL) | |
2930 | p += 4; | |
2931 | macro_build (p, counter, ep, | |
2932 | mips_isa < 3 ? "addiu" : "daddiu", | |
2933 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2934 | } | |
fb251650 | 2935 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
2936 | { |
2937 | expressionS ex; | |
2938 | ||
2939 | /* If this is a reference to an external symbol, we want | |
2940 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2941 | Otherwise we want | |
2942 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2943 | nop | |
2944 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 2945 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
2946 | ex.X_add_number = ep->X_add_number; |
2947 | ep->X_add_number = 0; | |
8ea7f4e8 | 2948 | frag_grow (20); |
0dd2d296 ILT |
2949 | macro_build ((char *) NULL, counter, ep, |
2950 | mips_isa < 3 ? "lw" : "ld", | |
2951 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2952 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
2953 | p = frag_var (rs_machine_dependent, 4, 0, | |
2954 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
2955 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2956 | macro_build (p, counter, ep, | |
2957 | mips_isa < 3 ? "addiu" : "daddiu", | |
2958 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2959 | if (ex.X_add_number != 0) | |
2960 | { | |
2961 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2962 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2963 | ex.X_op = O_constant; | |
fb251650 ILT |
2964 | macro_build ((char *) NULL, counter, &ex, |
2965 | mips_isa < 3 ? "addiu" : "daddiu", | |
2966 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2967 | } | |
2968 | } | |
2969 | else if (mips_pic == SVR4_PIC) | |
2970 | { | |
2971 | expressionS ex; | |
2972 | int off; | |
2973 | ||
2974 | /* This is the large GOT case. If this is a reference to an | |
2975 | external symbol, we want | |
2976 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2977 | addu $reg,$reg,$gp | |
2978 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
2979 | Otherwise, for a reference to a local symbol, we want | |
2980 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2981 | nop | |
2982 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
2983 | If there is a constant, it must be added in after. */ | |
2984 | ex.X_add_number = ep->X_add_number; | |
2985 | ep->X_add_number = 0; | |
2986 | if (reg_needs_delay (GP)) | |
2987 | off = 4; | |
2988 | else | |
2989 | off = 0; | |
2990 | frag_grow (32); | |
2991 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2992 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
2993 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
2994 | mips_isa < 3 ? "addu" : "daddu", | |
2995 | "d,v,t", reg, reg, GP); | |
2996 | macro_build ((char *) NULL, counter, ep, | |
2997 | mips_isa < 3 ? "lw" : "ld", | |
2998 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
2999 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3000 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3001 | mips_warn_about_macros), | |
3002 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
3003 | if (off > 0) | |
3004 | { | |
3005 | /* We need a nop before loading from $gp. This special | |
3006 | check is required because the lui which starts the main | |
3007 | instruction stream does not refer to $gp, and so will not | |
3008 | insert the nop which may be required. */ | |
3009 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3010 | p += 4; | |
3011 | } | |
3012 | macro_build (p, counter, ep, | |
3013 | mips_isa < 3 ? "lw" : "ld", | |
3014 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3015 | p += 4; | |
3016 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3017 | p += 4; | |
3018 | macro_build (p, counter, ep, | |
3019 | mips_isa < 3 ? "addiu" : "daddiu", | |
3020 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3021 | if (ex.X_add_number != 0) | |
3022 | { | |
3023 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3024 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3025 | ex.X_op = O_constant; | |
3026 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
3027 | mips_isa < 3 ? "addiu" : "daddiu", |
3028 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3029 | } | |
d9aba805 ILT |
3030 | } |
3031 | else if (mips_pic == EMBEDDED_PIC) | |
3032 | { | |
3033 | /* We always do | |
3034 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3035 | */ | |
3036 | macro_build ((char *) NULL, counter, ep, | |
3037 | mips_isa < 3 ? "addiu" : "daddiu", | |
3038 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3039 | } | |
3040 | else | |
3041 | abort (); | |
0dd2d296 ILT |
3042 | } |
3043 | ||
3d3c5039 ILT |
3044 | /* |
3045 | * Build macros | |
3046 | * This routine implements the seemingly endless macro or synthesized | |
3047 | * instructions and addressing modes in the mips assembly language. Many | |
3048 | * of these macros are simple and are similar to each other. These could | |
3049 | * probably be handled by some kind of table or grammer aproach instead of | |
3050 | * this verbose method. Others are not simple macros but are more like | |
3051 | * optimizing code generation. | |
3052 | * One interesting optimization is when several store macros appear | |
3053 | * consecutivly that would load AT with the upper half of the same address. | |
3054 | * The ensuing load upper instructions are ommited. This implies some kind | |
3055 | * of global optimization. We currently only optimize within a single macro. | |
3056 | * For many of the load and store macros if the address is specified as a | |
3057 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3058 | * first load register 'at' with zero and use it as the base register. The | |
3059 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3060 | * we're missing. | |
3061 | */ | |
3062 | static void | |
3063 | macro (ip) | |
3064 | struct mips_cl_insn *ip; | |
3065 | { | |
670a50eb ILT |
3066 | register int treg, sreg, dreg, breg; |
3067 | int tempreg; | |
3068 | int mask; | |
3069 | int icnt = 0; | |
3070 | int used_at; | |
670a50eb ILT |
3071 | expressionS expr1; |
3072 | const char *s; | |
8358c818 | 3073 | const char *s2; |
670a50eb | 3074 | const char *fmt; |
8358c818 ILT |
3075 | int likely = 0; |
3076 | int dbl = 0; | |
3077 | int coproc = 0; | |
b2b8c24e | 3078 | int lr = 0; |
6e8dda9c | 3079 | offsetT maxnum; |
adcf2b9d | 3080 | int off; |
9226253a | 3081 | bfd_reloc_code_real_type r; |
0dd2d296 | 3082 | char *p; |
55933a58 | 3083 | int hold_mips_optimize; |
670a50eb | 3084 | |
cc5703cd ILT |
3085 | assert (! mips16); |
3086 | ||
670a50eb ILT |
3087 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3088 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3089 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3090 | mask = ip->insn_mo->mask; | |
3091 | ||
5ac34ac3 ILT |
3092 | expr1.X_op = O_constant; |
3093 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3094 | expr1.X_add_symbol = NULL; |
3095 | expr1.X_add_number = 1; | |
3096 | ||
3097 | switch (mask) | |
3098 | { | |
6e8dda9c ILT |
3099 | case M_DABS: |
3100 | dbl = 1; | |
3d3c5039 | 3101 | case M_ABS: |
6e8dda9c ILT |
3102 | /* bgez $a0,.+12 |
3103 | move v0,$a0 | |
3104 | sub v0,$zero,$a0 | |
3105 | */ | |
3d3c5039 | 3106 | |
fbcfacb7 | 3107 | mips_emit_delays (true); |
becfe05e | 3108 | ++mips_noreorder; |
0dd2d296 | 3109 | mips_any_noreorder = 1; |
3d3c5039 | 3110 | |
670a50eb | 3111 | expr1.X_add_number = 8; |
0dd2d296 | 3112 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3113 | if (dreg == sreg) |
0dd2d296 | 3114 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3115 | else |
0dd2d296 ILT |
3116 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3117 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3118 | dbl ? "dsub" : "sub", |
3119 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3120 | |
becfe05e | 3121 | --mips_noreorder; |
670a50eb | 3122 | return; |
3d3c5039 ILT |
3123 | |
3124 | case M_ADD_I: | |
8358c818 ILT |
3125 | s = "addi"; |
3126 | s2 = "add"; | |
3127 | goto do_addi; | |
3d3c5039 | 3128 | case M_ADDU_I: |
8358c818 ILT |
3129 | s = "addiu"; |
3130 | s2 = "addu"; | |
3131 | goto do_addi; | |
3132 | case M_DADD_I: | |
6e8dda9c | 3133 | dbl = 1; |
8358c818 ILT |
3134 | s = "daddi"; |
3135 | s2 = "dadd"; | |
3136 | goto do_addi; | |
3137 | case M_DADDU_I: | |
6e8dda9c | 3138 | dbl = 1; |
8358c818 ILT |
3139 | s = "daddiu"; |
3140 | s2 = "daddu"; | |
3141 | do_addi: | |
6e8dda9c | 3142 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3143 | { |
0dd2d296 | 3144 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3145 | (int) BFD_RELOC_LO16); |
670a50eb | 3146 | return; |
3d3c5039 | 3147 | } |
d8a1c247 | 3148 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3149 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3150 | break; |
3d3c5039 ILT |
3151 | |
3152 | case M_AND_I: | |
6e8dda9c ILT |
3153 | s = "andi"; |
3154 | s2 = "and"; | |
3155 | goto do_bit; | |
3d3c5039 | 3156 | case M_OR_I: |
6e8dda9c ILT |
3157 | s = "ori"; |
3158 | s2 = "or"; | |
3159 | goto do_bit; | |
3d3c5039 | 3160 | case M_NOR_I: |
6e8dda9c ILT |
3161 | s = ""; |
3162 | s2 = "nor"; | |
3163 | goto do_bit; | |
3d3c5039 | 3164 | case M_XOR_I: |
6e8dda9c ILT |
3165 | s = "xori"; |
3166 | s2 = "xor"; | |
3167 | do_bit: | |
3168 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3169 | { |
6e8dda9c | 3170 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3171 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3172 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3173 | else |
670a50eb | 3174 | { |
0dd2d296 ILT |
3175 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3176 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3177 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3178 | treg, treg, 0); |
3d3c5039 | 3179 | } |
6e8dda9c | 3180 | return; |
3d3c5039 | 3181 | } |
6e8dda9c | 3182 | |
d8a1c247 | 3183 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3184 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3185 | break; |
3d3c5039 ILT |
3186 | |
3187 | case M_BEQ_I: | |
8358c818 ILT |
3188 | s = "beq"; |
3189 | goto beq_i; | |
3190 | case M_BEQL_I: | |
3191 | s = "beql"; | |
3192 | likely = 1; | |
3193 | goto beq_i; | |
3d3c5039 | 3194 | case M_BNE_I: |
8358c818 ILT |
3195 | s = "bne"; |
3196 | goto beq_i; | |
3197 | case M_BNEL_I: | |
3198 | s = "bnel"; | |
3199 | likely = 1; | |
3200 | beq_i: | |
670a50eb ILT |
3201 | if (imm_expr.X_add_number == 0) |
3202 | { | |
0dd2d296 ILT |
3203 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3204 | 0); | |
670a50eb ILT |
3205 | return; |
3206 | } | |
d8a1c247 | 3207 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3208 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3209 | break; |
3d3c5039 | 3210 | |
8358c818 ILT |
3211 | case M_BGEL: |
3212 | likely = 1; | |
3d3c5039 | 3213 | case M_BGE: |
670a50eb ILT |
3214 | if (treg == 0) |
3215 | { | |
0dd2d296 | 3216 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3217 | likely ? "bgezl" : "bgez", |
3218 | "s,p", sreg); | |
670a50eb | 3219 | return; |
3d3c5039 | 3220 | } |
9a7d824a ILT |
3221 | if (sreg == 0) |
3222 | { | |
0dd2d296 | 3223 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3224 | likely ? "blezl" : "blez", |
3225 | "s,p", treg); | |
9a7d824a ILT |
3226 | return; |
3227 | } | |
0dd2d296 ILT |
3228 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3229 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3230 | likely ? "beql" : "beq", |
3231 | "s,t,p", AT, 0); | |
670a50eb | 3232 | break; |
3d3c5039 | 3233 | |
8358c818 ILT |
3234 | case M_BGTL_I: |
3235 | likely = 1; | |
3d3c5039 | 3236 | case M_BGT_I: |
9a7d824a | 3237 | /* check for > max integer */ |
6e8dda9c ILT |
3238 | maxnum = 0x7fffffff; |
3239 | if (mips_isa >= 3) | |
3240 | { | |
3241 | maxnum <<= 16; | |
3242 | maxnum |= 0xffff; | |
3243 | maxnum <<= 16; | |
3244 | maxnum |= 0xffff; | |
3245 | } | |
7b777690 ILT |
3246 | if (imm_expr.X_add_number >= maxnum |
3247 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3248 | { |
3249 | do_false: | |
3250 | /* result is always false */ | |
8358c818 ILT |
3251 | if (! likely) |
3252 | { | |
3253 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3254 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3255 | } |
3256 | else | |
3257 | { | |
3258 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3259 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3260 | "s,t,p", 0, 0); | |
8358c818 | 3261 | } |
9a7d824a ILT |
3262 | return; |
3263 | } | |
670a50eb ILT |
3264 | imm_expr.X_add_number++; |
3265 | /* FALLTHROUGH */ | |
3d3c5039 | 3266 | case M_BGE_I: |
8358c818 ILT |
3267 | case M_BGEL_I: |
3268 | if (mask == M_BGEL_I) | |
3269 | likely = 1; | |
670a50eb ILT |
3270 | if (imm_expr.X_add_number == 0) |
3271 | { | |
0dd2d296 | 3272 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3273 | likely ? "bgezl" : "bgez", |
3274 | "s,p", sreg); | |
670a50eb | 3275 | return; |
3d3c5039 | 3276 | } |
670a50eb ILT |
3277 | if (imm_expr.X_add_number == 1) |
3278 | { | |
0dd2d296 | 3279 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3280 | likely ? "bgtzl" : "bgtz", |
3281 | "s,p", sreg); | |
670a50eb | 3282 | return; |
3d3c5039 | 3283 | } |
6e8dda9c ILT |
3284 | maxnum = 0x7fffffff; |
3285 | if (mips_isa >= 3) | |
3286 | { | |
3287 | maxnum <<= 16; | |
3288 | maxnum |= 0xffff; | |
3289 | maxnum <<= 16; | |
3290 | maxnum |= 0xffff; | |
3291 | } | |
3292 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3293 | if (imm_expr.X_add_number <= maxnum |
3294 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3295 | { |
3296 | do_true: | |
3297 | /* result is always true */ | |
3298 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3299 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3300 | return; |
3301 | } | |
6e8dda9c | 3302 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3303 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3304 | likely ? "beql" : "beq", |
3305 | "s,t,p", AT, 0); | |
670a50eb | 3306 | break; |
3d3c5039 | 3307 | |
8358c818 ILT |
3308 | case M_BGEUL: |
3309 | likely = 1; | |
3d3c5039 | 3310 | case M_BGEU: |
670a50eb | 3311 | if (treg == 0) |
9a7d824a ILT |
3312 | goto do_true; |
3313 | if (sreg == 0) | |
670a50eb | 3314 | { |
0dd2d296 | 3315 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3316 | likely ? "beql" : "beq", |
3317 | "s,t,p", 0, treg); | |
670a50eb | 3318 | return; |
3d3c5039 | 3319 | } |
0dd2d296 ILT |
3320 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3321 | treg); | |
3322 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3323 | likely ? "beql" : "beq", |
3324 | "s,t,p", AT, 0); | |
670a50eb | 3325 | break; |
3d3c5039 | 3326 | |
8358c818 ILT |
3327 | case M_BGTUL_I: |
3328 | likely = 1; | |
9a7d824a | 3329 | case M_BGTU_I: |
6e8dda9c | 3330 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3331 | goto do_false; |
3332 | imm_expr.X_add_number++; | |
3333 | /* FALLTHROUGH */ | |
3d3c5039 | 3334 | case M_BGEU_I: |
8358c818 ILT |
3335 | case M_BGEUL_I: |
3336 | if (mask == M_BGEUL_I) | |
3337 | likely = 1; | |
670a50eb | 3338 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3339 | goto do_true; |
670a50eb ILT |
3340 | if (imm_expr.X_add_number == 1) |
3341 | { | |
0dd2d296 | 3342 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3343 | likely ? "bnel" : "bne", |
3344 | "s,t,p", sreg, 0); | |
670a50eb | 3345 | return; |
3d3c5039 | 3346 | } |
6e8dda9c | 3347 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3348 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3349 | likely ? "beql" : "beq", |
3350 | "s,t,p", AT, 0); | |
670a50eb | 3351 | break; |
3d3c5039 | 3352 | |
8358c818 ILT |
3353 | case M_BGTL: |
3354 | likely = 1; | |
3d3c5039 | 3355 | case M_BGT: |
670a50eb ILT |
3356 | if (treg == 0) |
3357 | { | |
0dd2d296 | 3358 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3359 | likely ? "bgtzl" : "bgtz", |
3360 | "s,p", sreg); | |
670a50eb | 3361 | return; |
3d3c5039 | 3362 | } |
9a7d824a ILT |
3363 | if (sreg == 0) |
3364 | { | |
0dd2d296 | 3365 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3366 | likely ? "bltzl" : "bltz", |
3367 | "s,p", treg); | |
9a7d824a ILT |
3368 | return; |
3369 | } | |
0dd2d296 ILT |
3370 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3371 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3372 | likely ? "bnel" : "bne", |
3373 | "s,t,p", AT, 0); | |
670a50eb | 3374 | break; |
3d3c5039 | 3375 | |
8358c818 ILT |
3376 | case M_BGTUL: |
3377 | likely = 1; | |
3d3c5039 | 3378 | case M_BGTU: |
670a50eb ILT |
3379 | if (treg == 0) |
3380 | { | |
0dd2d296 | 3381 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3382 | likely ? "bnel" : "bne", |
3383 | "s,t,p", sreg, 0); | |
670a50eb | 3384 | return; |
3d3c5039 | 3385 | } |
9a7d824a ILT |
3386 | if (sreg == 0) |
3387 | goto do_false; | |
0dd2d296 ILT |
3388 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3389 | sreg); | |
3390 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3391 | likely ? "bnel" : "bne", |
3392 | "s,t,p", AT, 0); | |
670a50eb | 3393 | break; |
3d3c5039 | 3394 | |
8358c818 ILT |
3395 | case M_BLEL: |
3396 | likely = 1; | |
3d3c5039 | 3397 | case M_BLE: |
670a50eb ILT |
3398 | if (treg == 0) |
3399 | { | |
0dd2d296 | 3400 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3401 | likely ? "blezl" : "blez", |
3402 | "s,p", sreg); | |
670a50eb ILT |
3403 | return; |
3404 | } | |
9a7d824a ILT |
3405 | if (sreg == 0) |
3406 | { | |
0dd2d296 | 3407 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3408 | likely ? "bgezl" : "bgez", |
3409 | "s,p", treg); | |
9a7d824a ILT |
3410 | return; |
3411 | } | |
0dd2d296 ILT |
3412 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3413 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3414 | likely ? "beql" : "beq", |
3415 | "s,t,p", AT, 0); | |
670a50eb | 3416 | break; |
3d3c5039 | 3417 | |
8358c818 ILT |
3418 | case M_BLEL_I: |
3419 | likely = 1; | |
3d3c5039 | 3420 | case M_BLE_I: |
6e8dda9c ILT |
3421 | maxnum = 0x7fffffff; |
3422 | if (mips_isa >= 3) | |
3423 | { | |
3424 | maxnum <<= 16; | |
3425 | maxnum |= 0xffff; | |
3426 | maxnum <<= 16; | |
3427 | maxnum |= 0xffff; | |
3428 | } | |
7b777690 ILT |
3429 | if (imm_expr.X_add_number >= maxnum |
3430 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3431 | goto do_true; |
3432 | imm_expr.X_add_number++; | |
3433 | /* FALLTHROUGH */ | |
9a7d824a | 3434 | case M_BLT_I: |
8358c818 ILT |
3435 | case M_BLTL_I: |
3436 | if (mask == M_BLTL_I) | |
3437 | likely = 1; | |
670a50eb ILT |
3438 | if (imm_expr.X_add_number == 0) |
3439 | { | |
0dd2d296 | 3440 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3441 | likely ? "bltzl" : "bltz", |
3442 | "s,p", sreg); | |
670a50eb ILT |
3443 | return; |
3444 | } | |
9a7d824a | 3445 | if (imm_expr.X_add_number == 1) |
670a50eb | 3446 | { |
0dd2d296 | 3447 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3448 | likely ? "blezl" : "blez", |
3449 | "s,p", sreg); | |
670a50eb ILT |
3450 | return; |
3451 | } | |
6e8dda9c | 3452 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3453 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3454 | likely ? "bnel" : "bne", |
3455 | "s,t,p", AT, 0); | |
670a50eb | 3456 | break; |
3d3c5039 | 3457 | |
8358c818 ILT |
3458 | case M_BLEUL: |
3459 | likely = 1; | |
3d3c5039 | 3460 | case M_BLEU: |
670a50eb ILT |
3461 | if (treg == 0) |
3462 | { | |
0dd2d296 | 3463 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3464 | likely ? "beql" : "beq", |
3465 | "s,t,p", sreg, 0); | |
670a50eb | 3466 | return; |
3d3c5039 | 3467 | } |
9a7d824a ILT |
3468 | if (sreg == 0) |
3469 | goto do_true; | |
0dd2d296 ILT |
3470 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3471 | sreg); | |
3472 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3473 | likely ? "beql" : "beq", |
3474 | "s,t,p", AT, 0); | |
670a50eb | 3475 | break; |
3d3c5039 | 3476 | |
8358c818 ILT |
3477 | case M_BLEUL_I: |
3478 | likely = 1; | |
3d3c5039 | 3479 | case M_BLEU_I: |
6e8dda9c | 3480 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3481 | goto do_true; |
3482 | imm_expr.X_add_number++; | |
3483 | /* FALLTHROUGH */ | |
9a7d824a | 3484 | case M_BLTU_I: |
8358c818 ILT |
3485 | case M_BLTUL_I: |
3486 | if (mask == M_BLTUL_I) | |
3487 | likely = 1; | |
670a50eb | 3488 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3489 | goto do_false; |
3490 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3491 | { |
0dd2d296 | 3492 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3493 | likely ? "beql" : "beq", |
3494 | "s,t,p", sreg, 0); | |
670a50eb | 3495 | return; |
3d3c5039 | 3496 | } |
6e8dda9c | 3497 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3498 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3499 | likely ? "bnel" : "bne", |
3500 | "s,t,p", AT, 0); | |
670a50eb | 3501 | break; |
3d3c5039 | 3502 | |
8358c818 ILT |
3503 | case M_BLTL: |
3504 | likely = 1; | |
3d3c5039 | 3505 | case M_BLT: |
670a50eb ILT |
3506 | if (treg == 0) |
3507 | { | |
0dd2d296 | 3508 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3509 | likely ? "bltzl" : "bltz", |
3510 | "s,p", sreg); | |
670a50eb | 3511 | return; |
3d3c5039 | 3512 | } |
9a7d824a | 3513 | if (sreg == 0) |
670a50eb | 3514 | { |
0dd2d296 | 3515 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3516 | likely ? "bgtzl" : "bgtz", |
3517 | "s,p", treg); | |
670a50eb | 3518 | return; |
3d3c5039 | 3519 | } |
0dd2d296 ILT |
3520 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3521 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3522 | likely ? "bnel" : "bne", |
3523 | "s,t,p", AT, 0); | |
670a50eb | 3524 | break; |
3d3c5039 | 3525 | |
8358c818 ILT |
3526 | case M_BLTUL: |
3527 | likely = 1; | |
3d3c5039 | 3528 | case M_BLTU: |
670a50eb | 3529 | if (treg == 0) |
9a7d824a ILT |
3530 | goto do_false; |
3531 | if (sreg == 0) | |
670a50eb | 3532 | { |
0dd2d296 | 3533 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3534 | likely ? "bnel" : "bne", |
3535 | "s,t,p", 0, treg); | |
670a50eb ILT |
3536 | return; |
3537 | } | |
0dd2d296 ILT |
3538 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3539 | treg); | |
3540 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3541 | likely ? "bnel" : "bne", |
3542 | "s,t,p", AT, 0); | |
670a50eb | 3543 | break; |
3d3c5039 | 3544 | |
8358c818 ILT |
3545 | case M_DDIV_3: |
3546 | dbl = 1; | |
3d3c5039 | 3547 | case M_DIV_3: |
8358c818 ILT |
3548 | s = "mflo"; |
3549 | goto do_div3; | |
3550 | case M_DREM_3: | |
3551 | dbl = 1; | |
3d3c5039 | 3552 | case M_REM_3: |
8358c818 ILT |
3553 | s = "mfhi"; |
3554 | do_div3: | |
670a50eb ILT |
3555 | if (treg == 0) |
3556 | { | |
3557 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3558 | if (mips_trap) |
3559 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3560 | else | |
3561 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3562 | return; |
3563 | } | |
3564 | ||
fbcfacb7 | 3565 | mips_emit_delays (true); |
becfe05e | 3566 | ++mips_noreorder; |
0dd2d296 ILT |
3567 | mips_any_noreorder = 1; |
3568 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3569 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3570 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3571 | if (mips_trap) |
3572 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3573 | else | |
3574 | { | |
3575 | expr1.X_add_number = 8; | |
3576 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3577 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3578 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3579 | } | |
670a50eb | 3580 | expr1.X_add_number = -1; |
0dd2d296 | 3581 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3582 | dbl ? "daddiu" : "addiu", |
9226253a | 3583 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3584 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3585 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3586 | if (dbl) |
3587 | { | |
3588 | expr1.X_add_number = 1; | |
0dd2d296 | 3589 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3590 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3591 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3592 | 31); | |
8358c818 ILT |
3593 | } |
3594 | else | |
3595 | { | |
3596 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3597 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3598 | (int) BFD_RELOC_HI16); | |
8358c818 | 3599 | } |
8ea7f4e8 ILT |
3600 | if (mips_trap) |
3601 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3602 | else | |
3603 | { | |
3604 | expr1.X_add_number = 8; | |
3605 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3606 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3607 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3608 | } | |
becfe05e | 3609 | --mips_noreorder; |
0dd2d296 | 3610 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3611 | break; |
3d3c5039 ILT |
3612 | |
3613 | case M_DIV_3I: | |
8358c818 ILT |
3614 | s = "div"; |
3615 | s2 = "mflo"; | |
3616 | goto do_divi; | |
3d3c5039 | 3617 | case M_DIVU_3I: |
8358c818 ILT |
3618 | s = "divu"; |
3619 | s2 = "mflo"; | |
3620 | goto do_divi; | |
3d3c5039 | 3621 | case M_REM_3I: |
8358c818 ILT |
3622 | s = "div"; |
3623 | s2 = "mfhi"; | |
3624 | goto do_divi; | |
3d3c5039 | 3625 | case M_REMU_3I: |
8358c818 ILT |
3626 | s = "divu"; |
3627 | s2 = "mfhi"; | |
3628 | goto do_divi; | |
3629 | case M_DDIV_3I: | |
3630 | dbl = 1; | |
3631 | s = "ddiv"; | |
3632 | s2 = "mflo"; | |
3633 | goto do_divi; | |
3634 | case M_DDIVU_3I: | |
3635 | dbl = 1; | |
3636 | s = "ddivu"; | |
3637 | s2 = "mflo"; | |
3638 | goto do_divi; | |
3639 | case M_DREM_3I: | |
3640 | dbl = 1; | |
3641 | s = "ddiv"; | |
3642 | s2 = "mfhi"; | |
3643 | goto do_divi; | |
3644 | case M_DREMU_3I: | |
3645 | dbl = 1; | |
3646 | s = "ddivu"; | |
3647 | s2 = "mfhi"; | |
3648 | do_divi: | |
670a50eb ILT |
3649 | if (imm_expr.X_add_number == 0) |
3650 | { | |
3651 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3652 | if (mips_trap) |
3653 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3654 | else | |
3655 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3656 | return; |
3657 | } | |
3658 | if (imm_expr.X_add_number == 1) | |
3659 | { | |
8358c818 | 3660 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3661 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3662 | sreg); | |
3d3c5039 | 3663 | else |
0dd2d296 | 3664 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3665 | return; |
3666 | } | |
8358c818 ILT |
3667 | if (imm_expr.X_add_number == -1 |
3668 | && s[strlen (s) - 1] != 'u') | |
3669 | { | |
3670 | if (strcmp (s2, "mflo") == 0) | |
3671 | { | |
3672 | if (dbl) | |
0dd2d296 ILT |
3673 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3674 | sreg); | |
8358c818 | 3675 | else |
0dd2d296 ILT |
3676 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3677 | sreg); | |
8358c818 ILT |
3678 | } |
3679 | else | |
0dd2d296 | 3680 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3681 | return; |
3682 | } | |
3d3c5039 | 3683 | |
d8a1c247 | 3684 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3685 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3686 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3687 | break; |
3688 | ||
3689 | case M_DIVU_3: | |
8358c818 ILT |
3690 | s = "divu"; |
3691 | s2 = "mflo"; | |
3692 | goto do_divu3; | |
670a50eb | 3693 | case M_REMU_3: |
8358c818 ILT |
3694 | s = "divu"; |
3695 | s2 = "mfhi"; | |
3696 | goto do_divu3; | |
3697 | case M_DDIVU_3: | |
3698 | s = "ddivu"; | |
3699 | s2 = "mflo"; | |
3700 | goto do_divu3; | |
3701 | case M_DREMU_3: | |
3702 | s = "ddivu"; | |
3703 | s2 = "mfhi"; | |
3704 | do_divu3: | |
fbcfacb7 | 3705 | mips_emit_delays (true); |
becfe05e | 3706 | ++mips_noreorder; |
0dd2d296 ILT |
3707 | mips_any_noreorder = 1; |
3708 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3709 | if (mips_trap) |
3710 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3711 | else | |
3712 | { | |
3713 | expr1.X_add_number = 8; | |
3714 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3715 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3716 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3717 | } | |
becfe05e | 3718 | --mips_noreorder; |
0dd2d296 | 3719 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3720 | return; |
3d3c5039 | 3721 | |
d8a1c247 KR |
3722 | case M_DLA_AB: |
3723 | dbl = 1; | |
0dd2d296 | 3724 | case M_LA_AB: |
d9aba805 ILT |
3725 | /* Load the address of a symbol into a register. If breg is not |
3726 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3727 | |
3728 | /* When generating embedded PIC code, we permit expressions of | |
3729 | the form | |
3730 | la $4,foo-bar | |
3731 | where bar is an address in the .text section. These are used | |
3732 | when getting the addresses of functions. We don't permit | |
3733 | X_add_number to be non-zero, because if the symbol is | |
3734 | external the relaxing code needs to know that any addend is | |
3735 | purely the offset to X_op_symbol. */ | |
3736 | if (mips_pic == EMBEDDED_PIC | |
3737 | && offset_expr.X_op == O_subtract | |
3738 | && now_seg == text_section | |
847a01cd ILT |
3739 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3740 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3741 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3742 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3743 | ->sy_value.X_add_symbol) | |
3744 | == text_section))) | |
ecd4ca1c ILT |
3745 | && breg == 0 |
3746 | && offset_expr.X_add_number == 0) | |
3747 | { | |
3748 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3749 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3750 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3751 | mips_isa < 3 ? "addiu" : "daddiu", | |
3752 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3753 | return; | |
3754 | } | |
3755 | ||
0dd2d296 ILT |
3756 | if (offset_expr.X_op != O_symbol |
3757 | && offset_expr.X_op != O_constant) | |
670a50eb | 3758 | { |
0dd2d296 ILT |
3759 | as_bad ("expression too complex"); |
3760 | offset_expr.X_op = O_constant; | |
3761 | } | |
3762 | ||
3763 | if (treg == breg) | |
3764 | { | |
3765 | tempreg = AT; | |
3766 | used_at = 1; | |
3d3c5039 | 3767 | } |
670a50eb ILT |
3768 | else |
3769 | { | |
0dd2d296 ILT |
3770 | tempreg = treg; |
3771 | used_at = 0; | |
670a50eb | 3772 | } |
3d3c5039 | 3773 | |
5ac34ac3 | 3774 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3775 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3776 | else if (mips_pic == NO_PIC) |
670a50eb | 3777 | { |
0dd2d296 ILT |
3778 | /* If this is a reference to an GP relative symbol, we want |
3779 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3780 | Otherwise we want | |
3781 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3782 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3783 | If we have a constant, we need two instructions anyhow, | |
3784 | so we may as well always use the latter form. */ | |
7a15a226 | 3785 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3786 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3787 | p = NULL; |
3788 | else | |
3789 | { | |
8ea7f4e8 | 3790 | frag_grow (20); |
0dd2d296 ILT |
3791 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3792 | mips_isa < 3 ? "addiu" : "daddiu", | |
3793 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3794 | p = frag_var (rs_machine_dependent, 8, 0, | |
3795 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3796 | mips_warn_about_macros), | |
3797 | offset_expr.X_add_symbol, (long) 0, | |
3798 | (char *) NULL); | |
3799 | } | |
3800 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3801 | if (p != NULL) | |
3802 | p += 4; | |
3803 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3804 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3805 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3806 | } | |
fb251650 | 3807 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3808 | { |
3809 | /* If this is a reference to an external symbol, and there | |
3810 | is no constant, we want | |
3811 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3812 | For a local symbol, we want | |
3813 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3814 | nop | |
3815 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3816 | ||
3817 | If we have a small constant, and this is a reference to | |
3818 | an external symbol, we want | |
3819 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3820 | nop | |
3821 | addiu $tempreg,$tempreg,<constant> | |
3822 | For a local symbol, we want the same instruction | |
3823 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3824 | addiu instruction. | |
3825 | ||
3826 | If we have a large constant, and this is a reference to | |
3827 | an external symbol, we want | |
3828 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3829 | lui $at,<hiconstant> | |
3830 | addiu $at,$at,<loconstant> | |
3831 | addu $tempreg,$tempreg,$at | |
3832 | For a local symbol, we want the same instruction | |
3833 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3834 | addiu instruction. */ | |
3835 | expr1.X_add_number = offset_expr.X_add_number; | |
3836 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3837 | frag_grow (32); |
0dd2d296 | 3838 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3839 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3840 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3841 | if (expr1.X_add_number == 0) | |
3842 | { | |
3843 | int off; | |
3844 | ||
3845 | if (breg == 0) | |
3846 | off = 0; | |
3847 | else | |
3848 | { | |
3849 | /* We're going to put in an addu instruction using | |
3850 | tempreg, so we may as well insert the nop right | |
3851 | now. */ | |
3852 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3853 | "nop", ""); | |
3854 | off = 4; | |
3855 | } | |
3856 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3857 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3858 | (breg == 0 | |
3859 | ? mips_warn_about_macros | |
3860 | : 0)), | |
3861 | offset_expr.X_add_symbol, (long) 0, | |
3862 | (char *) NULL); | |
3863 | if (breg == 0) | |
3864 | { | |
3865 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3866 | p += 4; | |
3867 | } | |
3868 | macro_build (p, &icnt, &expr1, | |
3869 | mips_isa < 3 ? "addiu" : "daddiu", | |
3870 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3871 | /* FIXME: If breg == 0, and the next instruction uses | |
3872 | $tempreg, then if this variant case is used an extra | |
3873 | nop will be generated. */ | |
3874 | } | |
3875 | else if (expr1.X_add_number >= -0x8000 | |
3876 | && expr1.X_add_number < 0x8000) | |
3877 | { | |
3878 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3879 | "nop", ""); | |
3880 | macro_build ((char *) NULL, &icnt, &expr1, | |
3881 | mips_isa < 3 ? "addiu" : "daddiu", | |
3882 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3883 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3884 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
3885 | offset_expr.X_add_symbol, (long) 0, | |
3886 | (char *) NULL); | |
3887 | } | |
3888 | else | |
3889 | { | |
3890 | int off1; | |
3891 | ||
3892 | /* If we are going to add in a base register, and the | |
3893 | target register and the base register are the same, | |
3894 | then we are using AT as a temporary register. Since | |
3895 | we want to load the constant into AT, we add our | |
3896 | current AT (from the global offset table) and the | |
3897 | register into the register now, and pretend we were | |
3898 | not using a base register. */ | |
3899 | if (breg != treg) | |
3900 | off1 = 0; | |
3901 | else | |
3902 | { | |
3903 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3904 | "nop", ""); | |
3905 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3906 | mips_isa < 3 ? "addu" : "daddu", | |
3907 | "d,v,t", treg, AT, breg); | |
3908 | breg = 0; | |
3909 | tempreg = treg; | |
3910 | off1 = -8; | |
3911 | } | |
3912 | ||
55933a58 ILT |
3913 | /* Set mips_optimize around the lui instruction to avoid |
3914 | inserting an unnecessary nop after the lw. */ | |
3915 | hold_mips_optimize = mips_optimize; | |
3916 | mips_optimize = 2; | |
0dd2d296 | 3917 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
3918 | mips_optimize = hold_mips_optimize; |
3919 | ||
0dd2d296 ILT |
3920 | macro_build ((char *) NULL, &icnt, &expr1, |
3921 | mips_isa < 3 ? "addiu" : "daddiu", | |
3922 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3923 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3924 | mips_isa < 3 ? "addu" : "daddu", | |
3925 | "d,v,t", tempreg, tempreg, AT); | |
3926 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3927 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
3928 | offset_expr.X_add_symbol, (long) 0, | |
3929 | (char *) NULL); | |
3930 | used_at = 1; | |
3931 | } | |
670a50eb | 3932 | } |
fb251650 ILT |
3933 | else if (mips_pic == SVR4_PIC) |
3934 | { | |
3935 | int gpdel; | |
3936 | ||
3937 | /* This is the large GOT case. If this is a reference to an | |
3938 | external symbol, and there is no constant, we want | |
3939 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3940 | addu $tempreg,$tempreg,$gp | |
3941 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3942 | For a local symbol, we want | |
3943 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3944 | nop | |
3945 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3946 | ||
3947 | If we have a small constant, and this is a reference to | |
3948 | an external symbol, we want | |
3949 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3950 | addu $tempreg,$tempreg,$gp | |
3951 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3952 | nop | |
3953 | addiu $tempreg,$tempreg,<constant> | |
3954 | For a local symbol, we want | |
3955 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3956 | nop | |
3957 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
3958 | ||
3959 | If we have a large constant, and this is a reference to | |
3960 | an external symbol, we want | |
3961 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3962 | addu $tempreg,$tempreg,$gp | |
3963 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3964 | lui $at,<hiconstant> | |
3965 | addiu $at,$at,<loconstant> | |
3966 | addu $tempreg,$tempreg,$at | |
3967 | For a local symbol, we want | |
3968 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3969 | lui $at,<hiconstant> | |
3970 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
3971 | addu $tempreg,$tempreg,$at | |
3972 | */ | |
3973 | expr1.X_add_number = offset_expr.X_add_number; | |
3974 | offset_expr.X_add_number = 0; | |
3975 | frag_grow (52); | |
3976 | if (reg_needs_delay (GP)) | |
3977 | gpdel = 4; | |
3978 | else | |
3979 | gpdel = 0; | |
3980 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3981 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3982 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3983 | mips_isa < 3 ? "addu" : "daddu", | |
3984 | "d,v,t", tempreg, tempreg, GP); | |
3985 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3986 | dbl ? "ld" : "lw", | |
3987 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
3988 | tempreg); | |
3989 | if (expr1.X_add_number == 0) | |
3990 | { | |
3991 | int off; | |
3992 | ||
3993 | if (breg == 0) | |
3994 | off = 0; | |
3995 | else | |
3996 | { | |
3997 | /* We're going to put in an addu instruction using | |
3998 | tempreg, so we may as well insert the nop right | |
3999 | now. */ | |
4000 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4001 | "nop", ""); | |
4002 | off = 4; | |
4003 | } | |
4004 | ||
4005 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4006 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4007 | 8 + gpdel, 0, | |
4008 | (breg == 0 | |
4009 | ? mips_warn_about_macros | |
4010 | : 0)), | |
4011 | offset_expr.X_add_symbol, (long) 0, | |
4012 | (char *) NULL); | |
4013 | } | |
4014 | else if (expr1.X_add_number >= -0x8000 | |
4015 | && expr1.X_add_number < 0x8000) | |
4016 | { | |
4017 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4018 | "nop", ""); | |
4019 | macro_build ((char *) NULL, &icnt, &expr1, | |
4020 | mips_isa < 3 ? "addiu" : "daddiu", | |
4021 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4022 | ||
4023 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4024 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4025 | (breg == 0 | |
4026 | ? mips_warn_about_macros | |
4027 | : 0)), | |
4028 | offset_expr.X_add_symbol, (long) 0, | |
4029 | (char *) NULL); | |
4030 | } | |
4031 | else | |
4032 | { | |
4033 | int adj, dreg; | |
4034 | ||
4035 | /* If we are going to add in a base register, and the | |
4036 | target register and the base register are the same, | |
4037 | then we are using AT as a temporary register. Since | |
4038 | we want to load the constant into AT, we add our | |
4039 | current AT (from the global offset table) and the | |
4040 | register into the register now, and pretend we were | |
4041 | not using a base register. */ | |
4042 | if (breg != treg) | |
4043 | { | |
4044 | adj = 0; | |
4045 | dreg = tempreg; | |
4046 | } | |
4047 | else | |
4048 | { | |
4049 | assert (tempreg == AT); | |
4050 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4051 | "nop", ""); | |
4052 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4053 | mips_isa < 3 ? "addu" : "daddu", | |
4054 | "d,v,t", treg, AT, breg); | |
4055 | dreg = treg; | |
4056 | adj = 8; | |
4057 | } | |
4058 | ||
4059 | /* Set mips_optimize around the lui instruction to avoid | |
4060 | inserting an unnecessary nop after the lw. */ | |
4061 | hold_mips_optimize = mips_optimize; | |
4062 | mips_optimize = 2; | |
4063 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4064 | mips_optimize = hold_mips_optimize; | |
4065 | ||
4066 | macro_build ((char *) NULL, &icnt, &expr1, | |
4067 | mips_isa < 3 ? "addiu" : "daddiu", | |
4068 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4069 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4070 | mips_isa < 3 ? "addu" : "daddu", | |
4071 | "d,v,t", dreg, dreg, AT); | |
4072 | ||
4073 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4074 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4075 | 8 + gpdel, 0, | |
4076 | (breg == 0 | |
4077 | ? mips_warn_about_macros | |
4078 | : 0)), | |
4079 | offset_expr.X_add_symbol, (long) 0, | |
4080 | (char *) NULL); | |
4081 | ||
4082 | used_at = 1; | |
4083 | } | |
4084 | ||
4085 | if (gpdel > 0) | |
4086 | { | |
4087 | /* This is needed because this instruction uses $gp, but | |
4088 | the first instruction on the main stream does not. */ | |
4089 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4090 | p += 4; | |
4091 | } | |
4092 | macro_build (p, &icnt, &offset_expr, | |
4093 | dbl ? "ld" : "lw", | |
4094 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4095 | p += 4; | |
4096 | if (expr1.X_add_number >= -0x8000 | |
4097 | && expr1.X_add_number < 0x8000) | |
4098 | { | |
4099 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4100 | p += 4; | |
4101 | macro_build (p, &icnt, &expr1, | |
4102 | mips_isa < 3 ? "addiu" : "daddiu", | |
4103 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4104 | /* FIXME: If add_number is 0, and there was no base | |
4105 | register, the external symbol case ended with a load, | |
4106 | so if the symbol turns out to not be external, and | |
4107 | the next instruction uses tempreg, an unnecessary nop | |
4108 | will be inserted. */ | |
4109 | } | |
4110 | else | |
4111 | { | |
4112 | if (breg == treg) | |
4113 | { | |
4114 | /* We must add in the base register now, as in the | |
4115 | external symbol case. */ | |
4116 | assert (tempreg == AT); | |
4117 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4118 | p += 4; | |
4119 | macro_build (p, &icnt, (expressionS *) NULL, | |
4120 | mips_isa < 3 ? "addu" : "daddu", | |
4121 | "d,v,t", treg, AT, breg); | |
4122 | p += 4; | |
4123 | tempreg = treg; | |
4124 | /* We set breg to 0 because we have arranged to add | |
4125 | it in in both cases. */ | |
4126 | breg = 0; | |
4127 | } | |
4128 | ||
4129 | macro_build_lui (p, &icnt, &expr1, AT); | |
4130 | p += 4; | |
4131 | macro_build (p, &icnt, &expr1, | |
4132 | mips_isa < 3 ? "addiu" : "daddiu", | |
4133 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4134 | p += 4; | |
4135 | macro_build (p, &icnt, (expressionS *) NULL, | |
4136 | mips_isa < 3 ? "addu" : "daddu", | |
4137 | "d,v,t", tempreg, tempreg, AT); | |
4138 | p += 4; | |
4139 | } | |
4140 | } | |
d9aba805 ILT |
4141 | else if (mips_pic == EMBEDDED_PIC) |
4142 | { | |
4143 | /* We use | |
4144 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4145 | */ | |
4146 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4147 | mips_isa < 3 ? "addiu" : "daddiu", | |
4148 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4149 | } | |
4150 | else | |
4151 | abort (); | |
0dd2d296 | 4152 | |
670a50eb | 4153 | if (breg != 0) |
0dd2d296 ILT |
4154 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4155 | mips_isa < 3 ? "addu" : "daddu", | |
4156 | "d,v,t", treg, tempreg, breg); | |
4157 | ||
4158 | if (! used_at) | |
4159 | return; | |
4160 | ||
4161 | break; | |
4162 | ||
4163 | case M_J_A: | |
4164 | /* The j instruction may not be used in PIC code, since it | |
4165 | requires an absolute address. We convert it to a b | |
4166 | instruction. */ | |
d9aba805 | 4167 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4168 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4169 | else | |
4170 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4171 | return; |
3d3c5039 | 4172 | |
9226253a ILT |
4173 | /* The jal instructions must be handled as macros because when |
4174 | generating PIC code they expand to multi-instruction | |
4175 | sequences. Normally they are simple instructions. */ | |
4176 | case M_JAL_1: | |
4177 | dreg = RA; | |
4178 | /* Fall through. */ | |
4179 | case M_JAL_2: | |
d9aba805 ILT |
4180 | if (mips_pic == NO_PIC |
4181 | || mips_pic == EMBEDDED_PIC) | |
4182 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4183 | "d,s", dreg, sreg); | |
4184 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4185 | { |
d9aba805 ILT |
4186 | if (sreg != PIC_CALL_REG) |
4187 | as_warn ("MIPS PIC call to register other than $25"); | |
4188 | ||
0dd2d296 ILT |
4189 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4190 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4191 | if (mips_cprestore_offset < 0) |
4192 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4193 | else | |
4194 | { | |
4195 | expr1.X_add_number = mips_cprestore_offset; | |
4196 | macro_build ((char *) NULL, &icnt, &expr1, | |
4197 | mips_isa < 3 ? "lw" : "ld", | |
4198 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4199 | } | |
9226253a | 4200 | } |
0dd2d296 | 4201 | else |
d9aba805 ILT |
4202 | abort (); |
4203 | ||
9226253a ILT |
4204 | return; |
4205 | ||
4206 | case M_JAL_A: | |
d9aba805 ILT |
4207 | if (mips_pic == NO_PIC) |
4208 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4209 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4210 | { |
fb251650 ILT |
4211 | /* If this is a reference to an external symbol, and we are |
4212 | using a small GOT, we want | |
d9aba805 ILT |
4213 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4214 | nop | |
4215 | jalr $25 | |
4216 | nop | |
4217 | lw $gp,cprestore($sp) | |
4218 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4219 | pseudo-op. If we are using a big GOT, we want |
4220 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4221 | addu $25,$25,$gp | |
4222 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4223 | nop | |
4224 | jalr $25 | |
4225 | nop | |
4226 | lw $gp,cprestore($sp) | |
4227 | If the symbol is not external, we want | |
d9aba805 ILT |
4228 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4229 | nop | |
4230 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4231 | jalr $25 | |
4232 | nop | |
fb251650 ILT |
4233 | lw $gp,cprestore($sp) */ |
4234 | frag_grow (40); | |
4235 | if (! mips_big_got) | |
4236 | { | |
4237 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4238 | mips_isa < 3 ? "lw" : "ld", | |
4239 | "t,o(b)", PIC_CALL_REG, | |
4240 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4241 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4242 | "nop", ""); | |
4243 | p = frag_var (rs_machine_dependent, 4, 0, | |
4244 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4245 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4246 | } | |
4247 | else | |
4248 | { | |
4249 | int gpdel; | |
4250 | ||
4251 | if (reg_needs_delay (GP)) | |
4252 | gpdel = 4; | |
4253 | else | |
4254 | gpdel = 0; | |
4255 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4256 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4257 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4258 | mips_isa < 3 ? "addu" : "daddu", | |
4259 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4260 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4261 | mips_isa < 3 ? "lw" : "ld", | |
4262 | "t,o(b)", PIC_CALL_REG, | |
4263 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4264 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4265 | "nop", ""); | |
4266 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4267 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4268 | 0, 0), | |
4269 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4270 | if (gpdel > 0) | |
4271 | { | |
4272 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4273 | p += 4; | |
4274 | } | |
4275 | macro_build (p, &icnt, &offset_expr, | |
4276 | mips_isa < 3 ? "lw" : "ld", | |
4277 | "t,o(b)", PIC_CALL_REG, | |
4278 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4279 | p += 4; | |
4280 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4281 | p += 4; | |
4282 | } | |
d9aba805 ILT |
4283 | macro_build (p, &icnt, &offset_expr, |
4284 | mips_isa < 3 ? "addiu" : "daddiu", | |
4285 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4286 | (int) BFD_RELOC_LO16); | |
4287 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4288 | "jalr", "s", PIC_CALL_REG); | |
4289 | if (mips_cprestore_offset < 0) | |
4290 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4291 | else | |
4292 | { | |
4293 | if (mips_noreorder) | |
4294 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4295 | "nop", ""); | |
4296 | expr1.X_add_number = mips_cprestore_offset; | |
4297 | macro_build ((char *) NULL, &icnt, &expr1, | |
4298 | mips_isa < 3 ? "lw" : "ld", | |
4299 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4300 | mips_frame_reg); | |
4301 | } | |
0dd2d296 | 4302 | } |
d9aba805 | 4303 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4304 | { |
4305 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4306 | /* The linker may expand the call to a longer sequence which | |
4307 | uses $at, so we must break rather than return. */ | |
4308 | break; | |
4309 | } | |
d9aba805 ILT |
4310 | else |
4311 | abort (); | |
4312 | ||
9226253a ILT |
4313 | return; |
4314 | ||
3d3c5039 | 4315 | case M_LB_AB: |
670a50eb ILT |
4316 | s = "lb"; |
4317 | goto ld; | |
3d3c5039 | 4318 | case M_LBU_AB: |
670a50eb ILT |
4319 | s = "lbu"; |
4320 | goto ld; | |
3d3c5039 | 4321 | case M_LH_AB: |
670a50eb ILT |
4322 | s = "lh"; |
4323 | goto ld; | |
3d3c5039 | 4324 | case M_LHU_AB: |
670a50eb ILT |
4325 | s = "lhu"; |
4326 | goto ld; | |
3d3c5039 | 4327 | case M_LW_AB: |
670a50eb ILT |
4328 | s = "lw"; |
4329 | goto ld; | |
3d3c5039 | 4330 | case M_LWC0_AB: |
670a50eb | 4331 | s = "lwc0"; |
8358c818 | 4332 | coproc = 1; |
670a50eb | 4333 | goto ld; |
3d3c5039 | 4334 | case M_LWC1_AB: |
670a50eb | 4335 | s = "lwc1"; |
8358c818 | 4336 | coproc = 1; |
670a50eb | 4337 | goto ld; |
3d3c5039 | 4338 | case M_LWC2_AB: |
670a50eb | 4339 | s = "lwc2"; |
8358c818 | 4340 | coproc = 1; |
670a50eb | 4341 | goto ld; |
3d3c5039 | 4342 | case M_LWC3_AB: |
670a50eb | 4343 | s = "lwc3"; |
8358c818 | 4344 | coproc = 1; |
670a50eb | 4345 | goto ld; |
3d3c5039 | 4346 | case M_LWL_AB: |
670a50eb | 4347 | s = "lwl"; |
b2b8c24e | 4348 | lr = 1; |
670a50eb | 4349 | goto ld; |
3d3c5039 | 4350 | case M_LWR_AB: |
670a50eb | 4351 | s = "lwr"; |
b2b8c24e | 4352 | lr = 1; |
8358c818 ILT |
4353 | goto ld; |
4354 | case M_LDC1_AB: | |
4355 | s = "ldc1"; | |
4356 | coproc = 1; | |
4357 | goto ld; | |
4358 | case M_LDC2_AB: | |
4359 | s = "ldc2"; | |
4360 | coproc = 1; | |
4361 | goto ld; | |
4362 | case M_LDC3_AB: | |
4363 | s = "ldc3"; | |
4364 | coproc = 1; | |
4365 | goto ld; | |
4366 | case M_LDL_AB: | |
4367 | s = "ldl"; | |
b2b8c24e | 4368 | lr = 1; |
8358c818 ILT |
4369 | goto ld; |
4370 | case M_LDR_AB: | |
4371 | s = "ldr"; | |
b2b8c24e | 4372 | lr = 1; |
8358c818 ILT |
4373 | goto ld; |
4374 | case M_LL_AB: | |
4375 | s = "ll"; | |
4376 | goto ld; | |
4377 | case M_LLD_AB: | |
4378 | s = "lld"; | |
4379 | goto ld; | |
4380 | case M_LWU_AB: | |
4381 | s = "lwu"; | |
3d3c5039 | 4382 | ld: |
b2b8c24e | 4383 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4384 | { |
4385 | tempreg = AT; | |
4386 | used_at = 1; | |
4387 | } | |
4388 | else | |
4389 | { | |
4390 | tempreg = treg; | |
4391 | used_at = 0; | |
4392 | } | |
4393 | goto ld_st; | |
3d3c5039 | 4394 | case M_SB_AB: |
670a50eb ILT |
4395 | s = "sb"; |
4396 | goto st; | |
3d3c5039 | 4397 | case M_SH_AB: |
670a50eb ILT |
4398 | s = "sh"; |
4399 | goto st; | |
3d3c5039 | 4400 | case M_SW_AB: |
670a50eb ILT |
4401 | s = "sw"; |
4402 | goto st; | |
3d3c5039 | 4403 | case M_SWC0_AB: |
670a50eb | 4404 | s = "swc0"; |
8358c818 | 4405 | coproc = 1; |
670a50eb | 4406 | goto st; |
3d3c5039 | 4407 | case M_SWC1_AB: |
670a50eb | 4408 | s = "swc1"; |
8358c818 | 4409 | coproc = 1; |
670a50eb | 4410 | goto st; |
3d3c5039 | 4411 | case M_SWC2_AB: |
670a50eb | 4412 | s = "swc2"; |
8358c818 | 4413 | coproc = 1; |
670a50eb | 4414 | goto st; |
3d3c5039 | 4415 | case M_SWC3_AB: |
670a50eb | 4416 | s = "swc3"; |
8358c818 | 4417 | coproc = 1; |
670a50eb | 4418 | goto st; |
3d3c5039 | 4419 | case M_SWL_AB: |
670a50eb ILT |
4420 | s = "swl"; |
4421 | goto st; | |
3d3c5039 | 4422 | case M_SWR_AB: |
670a50eb | 4423 | s = "swr"; |
8358c818 ILT |
4424 | goto st; |
4425 | case M_SC_AB: | |
4426 | s = "sc"; | |
4427 | goto st; | |
4428 | case M_SCD_AB: | |
4429 | s = "scd"; | |
4430 | goto st; | |
4431 | case M_SDC1_AB: | |
4432 | s = "sdc1"; | |
4433 | coproc = 1; | |
4434 | goto st; | |
4435 | case M_SDC2_AB: | |
4436 | s = "sdc2"; | |
4437 | coproc = 1; | |
4438 | goto st; | |
4439 | case M_SDC3_AB: | |
4440 | s = "sdc3"; | |
4441 | coproc = 1; | |
4442 | goto st; | |
4443 | case M_SDL_AB: | |
4444 | s = "sdl"; | |
4445 | goto st; | |
4446 | case M_SDR_AB: | |
4447 | s = "sdr"; | |
3d3c5039 | 4448 | st: |
670a50eb ILT |
4449 | tempreg = AT; |
4450 | used_at = 1; | |
3d3c5039 | 4451 | ld_st: |
8358c818 ILT |
4452 | if (mask == M_LWC1_AB |
4453 | || mask == M_SWC1_AB | |
8358c818 | 4454 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4455 | || mask == M_SDC1_AB |
4456 | || mask == M_L_DAB | |
4457 | || mask == M_S_DAB) | |
670a50eb | 4458 | fmt = "T,o(b)"; |
8358c818 | 4459 | else if (coproc) |
19ed8960 | 4460 | fmt = "E,o(b)"; |
670a50eb ILT |
4461 | else |
4462 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4463 | |
4464 | if (offset_expr.X_op != O_constant | |
4465 | && offset_expr.X_op != O_symbol) | |
4466 | { | |
4467 | as_bad ("expression too complex"); | |
4468 | offset_expr.X_op = O_constant; | |
4469 | } | |
4470 | ||
4471 | /* A constant expression in PIC code can be handled just as it | |
4472 | is in non PIC code. */ | |
d9aba805 | 4473 | if (mips_pic == NO_PIC |
0dd2d296 | 4474 | || offset_expr.X_op == O_constant) |
670a50eb | 4475 | { |
0dd2d296 ILT |
4476 | /* If this is a reference to a GP relative symbol, and there |
4477 | is no base register, we want | |
4478 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4479 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4480 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4481 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4482 | If we have a constant, we need two instructions anyhow, | |
4483 | so we always use the latter form. | |
4484 | ||
4485 | If we have a base register, and this is a reference to a | |
4486 | GP relative symbol, we want | |
4487 | addu $tempreg,$breg,$gp | |
4488 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4489 | Otherwise we want | |
4490 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4491 | addu $tempreg,$tempreg,$breg | |
4492 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4493 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4494 | if (breg == 0) |
4495 | { | |
7a15a226 | 4496 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4497 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4498 | p = NULL; |
4499 | else | |
4500 | { | |
8ea7f4e8 | 4501 | frag_grow (20); |
0dd2d296 ILT |
4502 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4503 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4504 | p = frag_var (rs_machine_dependent, 8, 0, | |
4505 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4506 | (mips_warn_about_macros |
4507 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
4508 | offset_expr.X_add_symbol, (long) 0, |
4509 | (char *) NULL); | |
8197b589 | 4510 | used_at = 0; |
0dd2d296 ILT |
4511 | } |
4512 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4513 | if (p != NULL) | |
4514 | p += 4; | |
4515 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4516 | (int) BFD_RELOC_LO16, tempreg); | |
4517 | } | |
4518 | else | |
4519 | { | |
7a15a226 | 4520 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4521 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4522 | p = NULL; |
4523 | else | |
4524 | { | |
8ea7f4e8 | 4525 | frag_grow (28); |
0dd2d296 ILT |
4526 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4527 | mips_isa < 3 ? "addu" : "daddu", | |
4528 | "d,v,t", tempreg, breg, GP); | |
4529 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4530 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4531 | p = frag_var (rs_machine_dependent, 12, 0, | |
4532 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4533 | offset_expr.X_add_symbol, (long) 0, | |
4534 | (char *) NULL); | |
4535 | } | |
4536 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4537 | if (p != NULL) | |
4538 | p += 4; | |
4539 | macro_build (p, &icnt, (expressionS *) NULL, | |
4540 | mips_isa < 3 ? "addu" : "daddu", | |
4541 | "d,v,t", tempreg, tempreg, breg); | |
4542 | if (p != NULL) | |
4543 | p += 4; | |
4544 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4545 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4546 | } |
670a50eb | 4547 | } |
fb251650 | 4548 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4549 | { |
0dd2d296 ILT |
4550 | /* If this is a reference to an external symbol, we want |
4551 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4552 | nop | |
4553 | <op> $treg,0($tempreg) | |
4554 | Otherwise we want | |
4555 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4556 | nop | |
4557 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4558 | <op> $treg,0($tempreg) | |
4559 | If there is a base register, we add it to $tempreg before | |
4560 | the <op>. If there is a constant, we stick it in the | |
4561 | <op> instruction. We don't handle constants larger than | |
4562 | 16 bits, because we have no way to load the upper 16 bits | |
4563 | (actually, we could handle them for the subset of cases | |
4564 | in which we are not using $at). */ | |
4565 | assert (offset_expr.X_op == O_symbol); | |
4566 | expr1.X_add_number = offset_expr.X_add_number; | |
4567 | offset_expr.X_add_number = 0; | |
4568 | if (expr1.X_add_number < -0x8000 | |
4569 | || expr1.X_add_number >= 0x8000) | |
4570 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4571 | frag_grow (20); |
0dd2d296 ILT |
4572 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4573 | mips_isa < 3 ? "lw" : "ld", | |
4574 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4575 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4576 | p = frag_var (rs_machine_dependent, 4, 0, | |
4577 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4578 | offset_expr.X_add_symbol, (long) 0, | |
4579 | (char *) NULL); | |
4580 | macro_build (p, &icnt, &offset_expr, | |
4581 | mips_isa < 3 ? "addiu" : "daddiu", | |
4582 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4583 | if (breg != 0) |
0dd2d296 | 4584 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4585 | mips_isa < 3 ? "addu" : "daddu", |
4586 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4587 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4588 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4589 | } |
fb251650 ILT |
4590 | else if (mips_pic == SVR4_PIC) |
4591 | { | |
4592 | int gpdel; | |
4593 | ||
4594 | /* If this is a reference to an external symbol, we want | |
4595 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4596 | addu $tempreg,$tempreg,$gp | |
4597 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4598 | <op> $treg,0($tempreg) | |
4599 | Otherwise we want | |
4600 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4601 | nop | |
4602 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4603 | <op> $treg,0($tempreg) | |
4604 | If there is a base register, we add it to $tempreg before | |
4605 | the <op>. If there is a constant, we stick it in the | |
4606 | <op> instruction. We don't handle constants larger than | |
4607 | 16 bits, because we have no way to load the upper 16 bits | |
4608 | (actually, we could handle them for the subset of cases | |
4609 | in which we are not using $at). */ | |
4610 | assert (offset_expr.X_op == O_symbol); | |
4611 | expr1.X_add_number = offset_expr.X_add_number; | |
4612 | offset_expr.X_add_number = 0; | |
4613 | if (expr1.X_add_number < -0x8000 | |
4614 | || expr1.X_add_number >= 0x8000) | |
4615 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4616 | if (reg_needs_delay (GP)) | |
4617 | gpdel = 4; | |
4618 | else | |
4619 | gpdel = 0; | |
4620 | frag_grow (36); | |
4621 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4622 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4623 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4624 | mips_isa < 3 ? "addu" : "daddu", | |
4625 | "d,v,t", tempreg, tempreg, GP); | |
4626 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4627 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4628 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4629 | tempreg); | |
fb251650 ILT |
4630 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4631 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
4632 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4633 | if (gpdel > 0) | |
4634 | { | |
4635 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4636 | p += 4; | |
4637 | } | |
4638 | macro_build (p, &icnt, &offset_expr, | |
4639 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4640 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4641 | p += 4; |
4642 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4643 | p += 4; | |
4644 | macro_build (p, &icnt, &offset_expr, | |
4645 | mips_isa < 3 ? "addiu" : "daddiu", | |
4646 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4647 | if (breg != 0) | |
4648 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4649 | mips_isa < 3 ? "addu" : "daddu", | |
4650 | "d,v,t", tempreg, tempreg, breg); | |
4651 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4652 | (int) BFD_RELOC_LO16, tempreg); | |
4653 | } | |
d9aba805 ILT |
4654 | else if (mips_pic == EMBEDDED_PIC) |
4655 | { | |
4656 | /* If there is no base register, we want | |
4657 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4658 | If there is a base register, we want | |
4659 | addu $tempreg,$breg,$gp | |
4660 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4661 | */ | |
4662 | assert (offset_expr.X_op == O_symbol); | |
4663 | if (breg == 0) | |
4664 | { | |
4665 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4666 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4667 | used_at = 0; | |
4668 | } | |
4669 | else | |
4670 | { | |
4671 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4672 | mips_isa < 3 ? "addu" : "daddu", | |
4673 | "d,v,t", tempreg, breg, GP); | |
4674 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4675 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4676 | } | |
4677 | } | |
4678 | else | |
4679 | abort (); | |
0dd2d296 ILT |
4680 | |
4681 | if (! used_at) | |
4682 | return; | |
4683 | ||
4684 | break; | |
3d3c5039 ILT |
4685 | |
4686 | case M_LI: | |
19ed8960 | 4687 | case M_LI_S: |
d8a1c247 KR |
4688 | load_register (&icnt, treg, &imm_expr, 0); |
4689 | return; | |
4690 | ||
4691 | case M_DLI: | |
4692 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4693 | return; |
3d3c5039 | 4694 | |
0dd2d296 | 4695 | case M_LI_SS: |
55933a58 | 4696 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4697 | { |
d8a1c247 | 4698 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4699 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4700 | "mtc1", "t,G", AT, treg); | |
4701 | break; | |
0dd2d296 | 4702 | } |
d9aba805 | 4703 | else |
d2c71068 | 4704 | { |
55933a58 ILT |
4705 | assert (offset_expr.X_op == O_symbol |
4706 | && strcmp (segment_name (S_GET_SEGMENT | |
4707 | (offset_expr.X_add_symbol)), | |
4708 | ".lit4") == 0 | |
4709 | && offset_expr.X_add_number == 0); | |
4710 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4711 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4712 | return; |
4713 | } | |
0dd2d296 | 4714 | |
3d3c5039 | 4715 | case M_LI_D: |
d9aba805 ILT |
4716 | /* We know that sym is in the .rdata section. First we get the |
4717 | upper 16 bits of the address. */ | |
4718 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4719 | { |
4720 | /* FIXME: This won't work for a 64 bit address. */ | |
4721 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4722 | } | |
d9aba805 | 4723 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4724 | { |
4725 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4726 | mips_isa < 3 ? "lw" : "ld", | |
4727 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4728 | } | |
d9aba805 ILT |
4729 | else if (mips_pic == EMBEDDED_PIC) |
4730 | { | |
4731 | /* For embedded PIC we pick up the entire address off $gp in | |
4732 | a single instruction. */ | |
4733 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4734 | mips_isa < 3 ? "addiu" : "daddiu", | |
4735 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4736 | offset_expr.X_op = O_constant; | |
4737 | offset_expr.X_add_number = 0; | |
4738 | } | |
4739 | else | |
4740 | abort (); | |
4741 | ||
0dd2d296 | 4742 | /* Now we load the register(s). */ |
8358c818 | 4743 | if (mips_isa >= 3) |
0dd2d296 ILT |
4744 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4745 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4746 | else |
4747 | { | |
0dd2d296 ILT |
4748 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4749 | treg, (int) BFD_RELOC_LO16, AT); | |
4750 | if (treg != 31) | |
4751 | { | |
4752 | /* FIXME: How in the world do we deal with the possible | |
4753 | overflow here? */ | |
4754 | offset_expr.X_add_number += 4; | |
4755 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4756 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4757 | } | |
8358c818 | 4758 | } |
d2c71068 ILT |
4759 | |
4760 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4761 | does not become a variant frag. */ | |
4762 | frag_wane (frag_now); | |
4763 | frag_new (0); | |
4764 | ||
670a50eb | 4765 | break; |
3d3c5039 ILT |
4766 | |
4767 | case M_LI_DD: | |
55933a58 ILT |
4768 | assert (offset_expr.X_op == O_symbol |
4769 | && offset_expr.X_add_number == 0); | |
4770 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4771 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4772 | { |
0dd2d296 ILT |
4773 | if (mips_isa >= 2) |
4774 | { | |
4775 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4776 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4777 | return; | |
4778 | } | |
4779 | breg = GP; | |
4780 | r = BFD_RELOC_MIPS_LITERAL; | |
4781 | goto dob; | |
4782 | } | |
55933a58 | 4783 | else |
0dd2d296 | 4784 | { |
55933a58 ILT |
4785 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4786 | if (mips_pic == SVR4_PIC) | |
4787 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4788 | mips_isa < 3 ? "lw" : "ld", | |
4789 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4790 | else | |
4791 | { | |
4792 | /* FIXME: This won't work for a 64 bit address. */ | |
4793 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4794 | } | |
4795 | ||
0dd2d296 ILT |
4796 | if (mips_isa >= 2) |
4797 | { | |
4798 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4799 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4800 | |
4801 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4802 | that this does not become a variant frag. */ | |
4803 | frag_wane (frag_now); | |
4804 | frag_new (0); | |
4805 | ||
0dd2d296 ILT |
4806 | break; |
4807 | } | |
4808 | breg = AT; | |
4809 | r = BFD_RELOC_LO16; | |
4810 | goto dob; | |
8358c818 | 4811 | } |
9226253a | 4812 | |
3d3c5039 | 4813 | case M_L_DOB: |
9a7d824a ILT |
4814 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4815 | to adjust when loading from memory. */ | |
9226253a ILT |
4816 | r = BFD_RELOC_LO16; |
4817 | dob: | |
8358c818 | 4818 | assert (mips_isa < 2); |
0dd2d296 | 4819 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4820 | target_big_endian ? treg + 1 : treg, |
9226253a | 4821 | (int) r, breg); |
0dd2d296 ILT |
4822 | /* FIXME: A possible overflow which I don't know how to deal |
4823 | with. */ | |
670a50eb | 4824 | offset_expr.X_add_number += 4; |
0dd2d296 | 4825 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4826 | target_big_endian ? treg : treg + 1, |
9226253a | 4827 | (int) r, breg); |
d2c71068 ILT |
4828 | |
4829 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4830 | does not become a variant frag. */ | |
4831 | frag_wane (frag_now); | |
4832 | frag_new (0); | |
4833 | ||
0dd2d296 ILT |
4834 | if (breg != AT) |
4835 | return; | |
4836 | break; | |
3d3c5039 ILT |
4837 | |
4838 | case M_L_DAB: | |
670a50eb ILT |
4839 | /* |
4840 | * The MIPS assembler seems to check for X_add_number not | |
4841 | * being double aligned and generating: | |
4842 | * lui at,%hi(foo+1) | |
4843 | * addu at,at,v1 | |
4844 | * addiu at,at,%lo(foo+1) | |
4845 | * lwc1 f2,0(at) | |
4846 | * lwc1 f3,4(at) | |
4847 | * But, the resulting address is the same after relocation so why | |
4848 | * generate the extra instruction? | |
4849 | */ | |
4032d3f0 | 4850 | coproc = 1; |
0dd2d296 | 4851 | if (mips_isa >= 2) |
670a50eb | 4852 | { |
0dd2d296 ILT |
4853 | s = "ldc1"; |
4854 | goto ld; | |
670a50eb | 4855 | } |
0dd2d296 ILT |
4856 | |
4857 | s = "lwc1"; | |
4858 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
4859 | goto ldd_std; |
4860 | ||
4861 | case M_S_DAB: | |
8358c818 | 4862 | if (mips_isa >= 2) |
8358c818 | 4863 | { |
0dd2d296 ILT |
4864 | s = "sdc1"; |
4865 | goto st; | |
8358c818 | 4866 | } |
3d3c5039 | 4867 | |
0dd2d296 ILT |
4868 | s = "swc1"; |
4869 | fmt = "T,o(b)"; | |
4870 | coproc = 1; | |
4871 | goto ldd_std; | |
3d3c5039 ILT |
4872 | |
4873 | case M_LD_AB: | |
0dd2d296 | 4874 | if (mips_isa >= 3) |
670a50eb | 4875 | { |
0dd2d296 ILT |
4876 | s = "ld"; |
4877 | goto ld; | |
670a50eb | 4878 | } |
0dd2d296 ILT |
4879 | |
4880 | s = "lw"; | |
4881 | fmt = "t,o(b)"; | |
4882 | goto ldd_std; | |
4883 | ||
4884 | case M_SD_AB: | |
4885 | if (mips_isa >= 3) | |
670a50eb | 4886 | { |
0dd2d296 ILT |
4887 | s = "sd"; |
4888 | goto st; | |
670a50eb | 4889 | } |
0dd2d296 | 4890 | |
670a50eb | 4891 | s = "sw"; |
0dd2d296 ILT |
4892 | fmt = "t,o(b)"; |
4893 | ||
4894 | ldd_std: | |
4895 | if (offset_expr.X_op != O_symbol | |
4896 | && offset_expr.X_op != O_constant) | |
670a50eb | 4897 | { |
0dd2d296 ILT |
4898 | as_bad ("expression too complex"); |
4899 | offset_expr.X_op = O_constant; | |
4900 | } | |
4901 | ||
4902 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
4903 | to adjust when loading from memory. We set coproc if we must | |
4904 | load $fn+1 first. */ | |
b9129c6f | 4905 | if (! target_big_endian) |
0dd2d296 ILT |
4906 | coproc = 0; |
4907 | ||
d9aba805 | 4908 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
4909 | || offset_expr.X_op == O_constant) |
4910 | { | |
4911 | /* If this is a reference to a GP relative symbol, we want | |
4912 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4913 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4914 | If we have a base register, we use this | |
4915 | addu $at,$breg,$gp | |
4916 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4917 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4918 | If this is not a GP relative symbol, we want | |
4919 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4920 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4921 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4922 | If there is a base register, we add it to $at after the | |
4923 | lui instruction. If there is a constant, we always use | |
4924 | the last case. */ | |
7a15a226 | 4925 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4926 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 4927 | { |
0dd2d296 ILT |
4928 | p = NULL; |
4929 | used_at = 1; | |
670a50eb ILT |
4930 | } |
4931 | else | |
0dd2d296 ILT |
4932 | { |
4933 | int off; | |
4934 | ||
4935 | if (breg == 0) | |
4936 | { | |
8ea7f4e8 | 4937 | frag_grow (28); |
0dd2d296 ILT |
4938 | tempreg = GP; |
4939 | off = 0; | |
4940 | used_at = 0; | |
4941 | } | |
4942 | else | |
4943 | { | |
8ea7f4e8 | 4944 | frag_grow (36); |
0dd2d296 ILT |
4945 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4946 | mips_isa < 3 ? "addu" : "daddu", | |
4947 | "d,v,t", AT, breg, GP); | |
4948 | tempreg = AT; | |
4949 | off = 4; | |
4950 | used_at = 1; | |
4951 | } | |
4952 | ||
4953 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4954 | coproc ? treg + 1 : treg, | |
4955 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4956 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
4957 | |
4958 | /* Set mips_optimize to 2 to avoid inserting an | |
4959 | undesired nop. */ | |
4960 | hold_mips_optimize = mips_optimize; | |
4961 | mips_optimize = 2; | |
0dd2d296 ILT |
4962 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4963 | coproc ? treg : treg + 1, | |
4964 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
4965 | mips_optimize = hold_mips_optimize; |
4966 | ||
0dd2d296 ILT |
4967 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
4968 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 4969 | used_at && mips_noat), |
0dd2d296 ILT |
4970 | offset_expr.X_add_symbol, (long) 0, |
4971 | (char *) NULL); | |
777ad64d ILT |
4972 | |
4973 | /* We just generated two relocs. When tc_gen_reloc | |
4974 | handles this case, it will skip the first reloc and | |
4975 | handle the second. The second reloc already has an | |
4976 | extra addend of 4, which we added above. We must | |
4977 | subtract it out, and then subtract another 4 to make | |
4978 | the first reloc come out right. The second reloc | |
4979 | will come out right because we are going to add 4 to | |
4980 | offset_expr when we build its instruction below. */ | |
4981 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
4982 | offset_expr.X_op = O_constant; |
4983 | } | |
4984 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
4985 | if (p != NULL) | |
4986 | p += 4; | |
4987 | if (breg != 0) | |
4988 | { | |
4989 | macro_build (p, &icnt, (expressionS *) NULL, | |
4990 | mips_isa < 3 ? "addu" : "daddu", | |
4991 | "d,v,t", AT, breg, AT); | |
4992 | if (p != NULL) | |
4993 | p += 4; | |
4994 | } | |
4995 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4996 | coproc ? treg + 1 : treg, | |
4997 | (int) BFD_RELOC_LO16, AT); | |
4998 | if (p != NULL) | |
4999 | p += 4; | |
5000 | /* FIXME: How do we handle overflow here? */ | |
5001 | offset_expr.X_add_number += 4; | |
5002 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
5003 | coproc ? treg : treg + 1, | |
5004 | (int) BFD_RELOC_LO16, AT); | |
5005 | } | |
fb251650 | 5006 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5007 | { |
0dd2d296 ILT |
5008 | int off; |
5009 | ||
5010 | /* If this is a reference to an external symbol, we want | |
5011 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5012 | nop | |
5013 | <op> $treg,0($at) | |
5014 | <op> $treg+1,4($at) | |
5015 | Otherwise we want | |
5016 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5017 | nop | |
5018 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5019 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5020 | If there is a base register we add it to $at before the | |
5021 | lwc1 instructions. If there is a constant we include it | |
5022 | in the lwc1 instructions. */ | |
5023 | used_at = 1; | |
5024 | expr1.X_add_number = offset_expr.X_add_number; | |
5025 | offset_expr.X_add_number = 0; | |
5026 | if (expr1.X_add_number < -0x8000 | |
5027 | || expr1.X_add_number >= 0x8000 - 4) | |
5028 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5029 | if (breg == 0) | |
5030 | off = 0; | |
5031 | else | |
5032 | off = 4; | |
8ea7f4e8 | 5033 | frag_grow (24 + off); |
0dd2d296 ILT |
5034 | macro_build ((char *) NULL, &icnt, &offset_expr, |
5035 | mips_isa < 3 ? "lw" : "ld", | |
5036 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5037 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5038 | if (breg != 0) |
0dd2d296 | 5039 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 5040 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
5041 | "d,v,t", AT, breg, AT); |
5042 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5043 | coproc ? treg + 1 : treg, | |
5044 | (int) BFD_RELOC_LO16, AT); | |
5045 | expr1.X_add_number += 4; | |
55933a58 ILT |
5046 | |
5047 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5048 | nop. */ | |
5049 | hold_mips_optimize = mips_optimize; | |
5050 | mips_optimize = 2; | |
0dd2d296 ILT |
5051 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5052 | coproc ? treg : treg + 1, | |
5053 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5054 | mips_optimize = hold_mips_optimize; |
5055 | ||
0dd2d296 ILT |
5056 | (void) frag_var (rs_machine_dependent, 0, 0, |
5057 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5058 | offset_expr.X_add_symbol, (long) 0, | |
5059 | (char *) NULL); | |
8358c818 | 5060 | } |
fb251650 ILT |
5061 | else if (mips_pic == SVR4_PIC) |
5062 | { | |
5063 | int gpdel, off; | |
5064 | ||
5065 | /* If this is a reference to an external symbol, we want | |
5066 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5067 | addu $at,$at,$gp | |
5068 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5069 | nop | |
5070 | <op> $treg,0($at) | |
5071 | <op> $treg+1,4($at) | |
5072 | Otherwise we want | |
5073 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5074 | nop | |
5075 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5076 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5077 | If there is a base register we add it to $at before the | |
5078 | lwc1 instructions. If there is a constant we include it | |
5079 | in the lwc1 instructions. */ | |
5080 | used_at = 1; | |
5081 | expr1.X_add_number = offset_expr.X_add_number; | |
5082 | offset_expr.X_add_number = 0; | |
5083 | if (expr1.X_add_number < -0x8000 | |
5084 | || expr1.X_add_number >= 0x8000 - 4) | |
5085 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5086 | if (reg_needs_delay (GP)) | |
5087 | gpdel = 4; | |
5088 | else | |
5089 | gpdel = 0; | |
5090 | if (breg == 0) | |
5091 | off = 0; | |
5092 | else | |
5093 | off = 4; | |
5094 | frag_grow (56); | |
5095 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5096 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5097 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5098 | mips_isa < 3 ? "addu" : "daddu", | |
5099 | "d,v,t", AT, AT, GP); | |
5100 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5101 | mips_isa < 3 ? "lw" : "ld", | |
5102 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5103 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5104 | if (breg != 0) | |
5105 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5106 | mips_isa < 3 ? "addu" : "daddu", | |
5107 | "d,v,t", AT, breg, AT); | |
5108 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5109 | coproc ? treg + 1 : treg, | |
5110 | (int) BFD_RELOC_LO16, AT); | |
5111 | expr1.X_add_number += 4; | |
5112 | ||
5113 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5114 | nop. */ | |
5115 | hold_mips_optimize = mips_optimize; | |
5116 | mips_optimize = 2; | |
5117 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5118 | coproc ? treg : treg + 1, | |
5119 | (int) BFD_RELOC_LO16, AT); | |
5120 | mips_optimize = hold_mips_optimize; | |
5121 | expr1.X_add_number -= 4; | |
5122 | ||
5123 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5124 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5125 | 8 + gpdel + off, 1, 0), | |
5126 | offset_expr.X_add_symbol, (long) 0, | |
5127 | (char *) NULL); | |
5128 | if (gpdel > 0) | |
5129 | { | |
5130 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5131 | p += 4; | |
5132 | } | |
5133 | macro_build (p, &icnt, &offset_expr, | |
5134 | mips_isa < 3 ? "lw" : "ld", | |
5135 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5136 | p += 4; | |
5137 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5138 | p += 4; | |
5139 | if (breg != 0) | |
5140 | { | |
5141 | macro_build (p, &icnt, (expressionS *) NULL, | |
5142 | mips_isa < 3 ? "addu" : "daddu", | |
5143 | "d,v,t", AT, breg, AT); | |
5144 | p += 4; | |
5145 | } | |
5146 | macro_build (p, &icnt, &expr1, s, fmt, | |
5147 | coproc ? treg + 1 : treg, | |
5148 | (int) BFD_RELOC_LO16, AT); | |
5149 | p += 4; | |
5150 | expr1.X_add_number += 4; | |
5151 | ||
5152 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5153 | nop. */ | |
5154 | hold_mips_optimize = mips_optimize; | |
5155 | mips_optimize = 2; | |
5156 | macro_build (p, &icnt, &expr1, s, fmt, | |
5157 | coproc ? treg : treg + 1, | |
5158 | (int) BFD_RELOC_LO16, AT); | |
5159 | mips_optimize = hold_mips_optimize; | |
5160 | } | |
d9aba805 ILT |
5161 | else if (mips_pic == EMBEDDED_PIC) |
5162 | { | |
5163 | /* If there is no base register, we use | |
5164 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5165 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5166 | If we have a base register, we use | |
5167 | addu $at,$breg,$gp | |
5168 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5169 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5170 | */ | |
5171 | if (breg == 0) | |
5172 | { | |
5173 | tempreg = GP; | |
5174 | used_at = 0; | |
5175 | } | |
5176 | else | |
5177 | { | |
5178 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5179 | mips_isa < 3 ? "addu" : "daddu", | |
5180 | "d,v,t", AT, breg, GP); | |
5181 | tempreg = AT; | |
5182 | used_at = 1; | |
5183 | } | |
5184 | ||
5185 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5186 | coproc ? treg + 1 : treg, | |
5187 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5188 | offset_expr.X_add_number += 4; | |
5189 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5190 | coproc ? treg : treg + 1, | |
5191 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5192 | } | |
5193 | else | |
5194 | abort (); | |
0dd2d296 ILT |
5195 | |
5196 | if (! used_at) | |
5197 | return; | |
5198 | ||
5199 | break; | |
5200 | ||
5201 | case M_LD_OB: | |
5202 | s = "lw"; | |
5203 | goto sd_ob; | |
5204 | case M_SD_OB: | |
5205 | s = "sw"; | |
5206 | sd_ob: | |
5207 | assert (mips_isa < 3); | |
5208 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
5209 | (int) BFD_RELOC_LO16, breg); | |
5210 | offset_expr.X_add_number += 4; | |
5211 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5212 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5213 | return; |
917fae09 SS |
5214 | #ifdef LOSING_COMPILER |
5215 | default: | |
5216 | macro2 (ip); | |
5217 | return; | |
5218 | } | |
5219 | if (mips_noat) | |
5220 | as_warn ("Macro used $at after \".set noat\""); | |
5221 | } | |
5222 | ||
5223 | static void | |
5224 | macro2 (ip) | |
5225 | struct mips_cl_insn *ip; | |
5226 | { | |
5227 | register int treg, sreg, dreg, breg; | |
5228 | int tempreg; | |
5229 | int mask; | |
5230 | int icnt = 0; | |
5231 | int used_at; | |
5232 | expressionS expr1; | |
5233 | const char *s; | |
5234 | const char *s2; | |
5235 | const char *fmt; | |
5236 | int likely = 0; | |
5237 | int dbl = 0; | |
5238 | int coproc = 0; | |
adcf2b9d ILT |
5239 | int lr = 0; |
5240 | int off; | |
917fae09 SS |
5241 | offsetT maxnum; |
5242 | bfd_reloc_code_real_type r; | |
5243 | char *p; | |
5244 | ||
5245 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5246 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5247 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5248 | mask = ip->insn_mo->mask; | |
5249 | ||
5250 | expr1.X_op = O_constant; | |
5251 | expr1.X_op_symbol = NULL; | |
5252 | expr1.X_add_symbol = NULL; | |
5253 | expr1.X_add_number = 1; | |
5254 | ||
5255 | switch (mask) | |
5256 | { | |
5257 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5258 | |
8358c818 ILT |
5259 | case M_DMUL: |
5260 | dbl = 1; | |
3d3c5039 | 5261 | case M_MUL: |
0dd2d296 | 5262 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5263 | dbl ? "dmultu" : "multu", |
5264 | "s,t", sreg, treg); | |
0dd2d296 | 5265 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5266 | return; |
3d3c5039 | 5267 | |
8358c818 ILT |
5268 | case M_DMUL_I: |
5269 | dbl = 1; | |
3d3c5039 | 5270 | case M_MUL_I: |
8358c818 ILT |
5271 | /* The MIPS assembler some times generates shifts and adds. I'm |
5272 | not trying to be that fancy. GCC should do this for us | |
5273 | anyway. */ | |
d8a1c247 | 5274 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5275 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5276 | dbl ? "dmult" : "mult", |
5277 | "s,t", sreg, AT); | |
0dd2d296 | 5278 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5279 | break; |
3d3c5039 | 5280 | |
8358c818 ILT |
5281 | case M_DMULO: |
5282 | dbl = 1; | |
5283 | case M_MULO: | |
fbcfacb7 | 5284 | mips_emit_delays (true); |
8358c818 | 5285 | ++mips_noreorder; |
0dd2d296 ILT |
5286 | mips_any_noreorder = 1; |
5287 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5288 | dbl ? "dmult" : "mult", |
5289 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5290 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5291 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5292 | dbl ? "dsra32" : "sra", |
5293 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5294 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5295 | if (mips_trap) |
5296 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5297 | else | |
5298 | { | |
5299 | expr1.X_add_number = 8; | |
5300 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5301 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5302 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5303 | } | |
8358c818 | 5304 | --mips_noreorder; |
0dd2d296 | 5305 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5306 | break; |
5307 | ||
5308 | case M_DMULOU: | |
5309 | dbl = 1; | |
5310 | case M_MULOU: | |
fbcfacb7 | 5311 | mips_emit_delays (true); |
8358c818 | 5312 | ++mips_noreorder; |
0dd2d296 ILT |
5313 | mips_any_noreorder = 1; |
5314 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5315 | dbl ? "dmultu" : "multu", |
5316 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5317 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5318 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5319 | if (mips_trap) |
5320 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5321 | else | |
5322 | { | |
5323 | expr1.X_add_number = 8; | |
5324 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5325 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5326 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5327 | } | |
8358c818 ILT |
5328 | --mips_noreorder; |
5329 | break; | |
5330 | ||
3d3c5039 | 5331 | case M_ROL: |
0dd2d296 ILT |
5332 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5333 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5334 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5335 | treg); | |
5336 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5337 | break; |
3d3c5039 ILT |
5338 | |
5339 | case M_ROL_I: | |
0dd2d296 | 5340 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5341 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5342 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5343 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5344 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5345 | break; |
3d3c5039 ILT |
5346 | |
5347 | case M_ROR: | |
0dd2d296 ILT |
5348 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5349 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5350 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5351 | treg); | |
5352 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5353 | break; |
3d3c5039 ILT |
5354 | |
5355 | case M_ROR_I: | |
0dd2d296 | 5356 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5357 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5358 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5359 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5360 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5361 | break; |
3d3c5039 ILT |
5362 | |
5363 | case M_S_DOB: | |
8358c818 | 5364 | assert (mips_isa < 2); |
9a7d824a ILT |
5365 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5366 | to adjust when storing to memory. */ | |
0dd2d296 | 5367 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5368 | target_big_endian ? treg + 1 : treg, |
9226253a | 5369 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5370 | offset_expr.X_add_number += 4; |
0dd2d296 | 5371 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5372 | target_big_endian ? treg : treg + 1, |
9226253a | 5373 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5374 | return; |
3d3c5039 | 5375 | |
3d3c5039 | 5376 | case M_SEQ: |
670a50eb | 5377 | if (sreg == 0) |
0dd2d296 ILT |
5378 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5379 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5380 | else if (treg == 0) |
0dd2d296 ILT |
5381 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5382 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5383 | else |
5384 | { | |
0dd2d296 ILT |
5385 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5386 | sreg, treg); | |
5387 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5388 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5389 | } |
670a50eb | 5390 | return; |
3d3c5039 ILT |
5391 | |
5392 | case M_SEQ_I: | |
670a50eb ILT |
5393 | if (imm_expr.X_add_number == 0) |
5394 | { | |
0dd2d296 ILT |
5395 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5396 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5397 | return; |
3d3c5039 | 5398 | } |
670a50eb ILT |
5399 | if (sreg == 0) |
5400 | { | |
9a7d824a | 5401 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5402 | ip->insn_mo->name); |
0dd2d296 | 5403 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5404 | return; |
3d3c5039 | 5405 | } |
6e8dda9c | 5406 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5407 | { |
0dd2d296 ILT |
5408 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5409 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5410 | used_at = 0; |
6e8dda9c ILT |
5411 | } |
5412 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5413 | { | |
5414 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5415 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5416 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5417 | "t,r,j", dreg, sreg, |
5418 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5419 | used_at = 0; |
5420 | } | |
5421 | else | |
5422 | { | |
d8a1c247 | 5423 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5424 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5425 | sreg, AT); | |
670a50eb ILT |
5426 | used_at = 1; |
5427 | } | |
0dd2d296 | 5428 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5429 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5430 | if (used_at) |
5431 | break; | |
5432 | return; | |
3d3c5039 ILT |
5433 | |
5434 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5435 | s = "slt"; |
5436 | goto sge; | |
3d3c5039 | 5437 | case M_SGEU: |
670a50eb | 5438 | s = "sltu"; |
3d3c5039 | 5439 | sge: |
0dd2d296 ILT |
5440 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5441 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5442 | (int) BFD_RELOC_LO16); |
670a50eb | 5443 | return; |
3d3c5039 | 5444 | |
670a50eb | 5445 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5446 | case M_SGEU_I: |
6e8dda9c | 5447 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5448 | { |
0dd2d296 | 5449 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5450 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5451 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5452 | used_at = 0; |
5453 | } | |
5454 | else | |
5455 | { | |
d8a1c247 | 5456 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5457 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5458 | mask == M_SGE_I ? "slt" : "sltu", |
5459 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5460 | used_at = 1; |
5461 | } | |
0dd2d296 | 5462 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5463 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5464 | if (used_at) |
5465 | break; | |
5466 | return; | |
3d3c5039 ILT |
5467 | |
5468 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5469 | s = "slt"; |
5470 | goto sgt; | |
3d3c5039 | 5471 | case M_SGTU: |
670a50eb | 5472 | s = "sltu"; |
3d3c5039 | 5473 | sgt: |
0dd2d296 | 5474 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5475 | return; |
3d3c5039 | 5476 | |
670a50eb ILT |
5477 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5478 | s = "slt"; | |
5479 | goto sgti; | |
3d3c5039 | 5480 | case M_SGTU_I: |
670a50eb | 5481 | s = "sltu"; |
3d3c5039 | 5482 | sgti: |
d8a1c247 | 5483 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5484 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5485 | break; |
3d3c5039 | 5486 | |
670a50eb ILT |
5487 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5488 | s = "slt"; | |
5489 | goto sle; | |
3d3c5039 | 5490 | case M_SLEU: |
670a50eb | 5491 | s = "sltu"; |
3d3c5039 | 5492 | sle: |
0dd2d296 ILT |
5493 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5494 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5495 | (int) BFD_RELOC_LO16); |
670a50eb | 5496 | return; |
3d3c5039 | 5497 | |
670a50eb ILT |
5498 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5499 | s = "slt"; | |
5500 | goto slei; | |
3d3c5039 | 5501 | case M_SLEU_I: |
670a50eb | 5502 | s = "sltu"; |
3d3c5039 | 5503 | slei: |
d8a1c247 | 5504 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5505 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5506 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5507 | (int) BFD_RELOC_LO16); |
670a50eb | 5508 | break; |
3d3c5039 ILT |
5509 | |
5510 | case M_SLT_I: | |
6e8dda9c | 5511 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5512 | { |
0dd2d296 ILT |
5513 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5514 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5515 | return; |
3d3c5039 | 5516 | } |
d8a1c247 | 5517 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5518 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5519 | break; |
3d3c5039 ILT |
5520 | |
5521 | case M_SLTU_I: | |
6e8dda9c | 5522 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5523 | { |
0dd2d296 ILT |
5524 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5525 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5526 | return; |
3d3c5039 | 5527 | } |
d8a1c247 | 5528 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5529 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5530 | AT); | |
670a50eb | 5531 | break; |
3d3c5039 ILT |
5532 | |
5533 | case M_SNE: | |
670a50eb | 5534 | if (sreg == 0) |
0dd2d296 ILT |
5535 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5536 | treg); | |
670a50eb | 5537 | else if (treg == 0) |
0dd2d296 ILT |
5538 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5539 | sreg); | |
670a50eb ILT |
5540 | else |
5541 | { | |
0dd2d296 ILT |
5542 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5543 | sreg, treg); | |
5544 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5545 | dreg); | |
3d3c5039 | 5546 | } |
670a50eb | 5547 | return; |
3d3c5039 ILT |
5548 | |
5549 | case M_SNE_I: | |
670a50eb ILT |
5550 | if (imm_expr.X_add_number == 0) |
5551 | { | |
0dd2d296 ILT |
5552 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5553 | sreg); | |
670a50eb | 5554 | return; |
3d3c5039 | 5555 | } |
670a50eb ILT |
5556 | if (sreg == 0) |
5557 | { | |
9a7d824a | 5558 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5559 | ip->insn_mo->name); |
0dd2d296 | 5560 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5561 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5562 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5563 | return; |
3d3c5039 | 5564 | } |
6e8dda9c | 5565 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5566 | { |
0dd2d296 ILT |
5567 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5568 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5569 | used_at = 0; |
6e8dda9c ILT |
5570 | } |
5571 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5572 | { | |
5573 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5574 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5575 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5576 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5577 | used_at = 0; |
5578 | } | |
5579 | else | |
5580 | { | |
d8a1c247 | 5581 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5582 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5583 | sreg, AT); | |
670a50eb ILT |
5584 | used_at = 1; |
5585 | } | |
0dd2d296 | 5586 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5587 | if (used_at) |
5588 | break; | |
5589 | return; | |
3d3c5039 | 5590 | |
8358c818 ILT |
5591 | case M_DSUB_I: |
5592 | dbl = 1; | |
3d3c5039 | 5593 | case M_SUB_I: |
6e8dda9c | 5594 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5595 | { |
5596 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5597 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5598 | dbl ? "daddi" : "addi", |
9226253a | 5599 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5600 | return; |
3d3c5039 | 5601 | } |
d8a1c247 | 5602 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5603 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5604 | dbl ? "dsub" : "sub", |
5605 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5606 | break; |
3d3c5039 | 5607 | |
8358c818 ILT |
5608 | case M_DSUBU_I: |
5609 | dbl = 1; | |
3d3c5039 | 5610 | case M_SUBU_I: |
6e8dda9c | 5611 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5612 | { |
5613 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5614 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5615 | dbl ? "daddiu" : "addiu", |
9226253a | 5616 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5617 | return; |
3d3c5039 | 5618 | } |
d8a1c247 | 5619 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5620 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5621 | dbl ? "dsubu" : "subu", |
5622 | "d,v,t", dreg, sreg, AT); | |
5623 | break; | |
5624 | ||
5625 | case M_TEQ_I: | |
5626 | s = "teq"; | |
5627 | goto trap; | |
5628 | case M_TGE_I: | |
5629 | s = "tge"; | |
5630 | goto trap; | |
5631 | case M_TGEU_I: | |
5632 | s = "tgeu"; | |
5633 | goto trap; | |
5634 | case M_TLT_I: | |
5635 | s = "tlt"; | |
5636 | goto trap; | |
5637 | case M_TLTU_I: | |
5638 | s = "tltu"; | |
5639 | goto trap; | |
5640 | case M_TNE_I: | |
5641 | s = "tne"; | |
5642 | trap: | |
d8a1c247 | 5643 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5644 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5645 | break; |
3d3c5039 ILT |
5646 | |
5647 | case M_TRUNCWD: | |
5648 | case M_TRUNCWS: | |
8358c818 | 5649 | assert (mips_isa < 2); |
670a50eb ILT |
5650 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5651 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5652 | ||
5653 | /* | |
5654 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5655 | * or is there a reason for it? | |
5656 | */ | |
fbcfacb7 | 5657 | mips_emit_delays (true); |
becfe05e | 5658 | ++mips_noreorder; |
0dd2d296 ILT |
5659 | mips_any_noreorder = 1; |
5660 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5661 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5662 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5663 | expr1.X_add_number = 3; |
0dd2d296 | 5664 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5665 | (int) BFD_RELOC_LO16); |
670a50eb | 5666 | expr1.X_add_number = 2; |
0dd2d296 | 5667 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5668 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5669 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5670 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5671 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5672 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5673 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5674 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5675 | --mips_noreorder; |
670a50eb | 5676 | break; |
3d3c5039 ILT |
5677 | |
5678 | case M_ULH: | |
670a50eb ILT |
5679 | s = "lb"; |
5680 | goto ulh; | |
3d3c5039 | 5681 | case M_ULHU: |
670a50eb | 5682 | s = "lbu"; |
3d3c5039 | 5683 | ulh: |
8ea7f4e8 ILT |
5684 | if (offset_expr.X_add_number >= 0x7fff) |
5685 | as_bad ("operand overflow"); | |
670a50eb | 5686 | /* avoid load delay */ |
b9129c6f | 5687 | if (! target_big_endian) |
8ea7f4e8 | 5688 | offset_expr.X_add_number += 1; |
0dd2d296 | 5689 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5690 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5691 | if (! target_big_endian) |
8ea7f4e8 ILT |
5692 | offset_expr.X_add_number -= 1; |
5693 | else | |
5694 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5695 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5696 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5697 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5698 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5699 | break; |
3d3c5039 | 5700 | |
adcf2b9d ILT |
5701 | case M_ULD: |
5702 | s = "ldl"; | |
5703 | s2 = "ldr"; | |
5704 | off = 7; | |
5705 | goto ulw; | |
3d3c5039 | 5706 | case M_ULW: |
adcf2b9d ILT |
5707 | s = "lwl"; |
5708 | s2 = "lwr"; | |
5709 | off = 3; | |
5710 | ulw: | |
5711 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5712 | as_bad ("operand overflow"); |
b9129c6f | 5713 | if (! target_big_endian) |
adcf2b9d ILT |
5714 | offset_expr.X_add_number += off; |
5715 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5716 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5717 | if (! target_big_endian) |
adcf2b9d | 5718 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5719 | else |
adcf2b9d ILT |
5720 | offset_expr.X_add_number += off; |
5721 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5722 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5723 | return; |
3d3c5039 | 5724 | |
adcf2b9d ILT |
5725 | case M_ULD_A: |
5726 | s = "ldl"; | |
5727 | s2 = "ldr"; | |
5728 | off = 7; | |
5729 | goto ulwa; | |
5730 | case M_ULW_A: | |
5731 | s = "lwl"; | |
5732 | s2 = "lwr"; | |
5733 | off = 3; | |
5734 | ulwa: | |
5735 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5736 | if (breg != 0) |
5737 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5738 | mips_isa < 3 ? "addu" : "daddu", | |
5739 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5740 | if (! target_big_endian) |
adcf2b9d ILT |
5741 | expr1.X_add_number = off; |
5742 | else | |
5743 | expr1.X_add_number = 0; | |
5744 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5745 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5746 | if (! target_big_endian) |
adcf2b9d ILT |
5747 | expr1.X_add_number = 0; |
5748 | else | |
5749 | expr1.X_add_number = off; | |
5750 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5751 | (int) BFD_RELOC_LO16, AT); | |
5752 | break; | |
5753 | ||
3d3c5039 ILT |
5754 | case M_ULH_A: |
5755 | case M_ULHU_A: | |
0dd2d296 | 5756 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5757 | if (breg != 0) |
5758 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5759 | mips_isa < 3 ? "addu" : "daddu", | |
5760 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5761 | if (target_big_endian) |
adcf2b9d ILT |
5762 | expr1.X_add_number = 0; |
5763 | macro_build ((char *) NULL, &icnt, &expr1, | |
5764 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5765 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5766 | if (target_big_endian) |
adcf2b9d | 5767 | expr1.X_add_number = 1; |
670a50eb | 5768 | else |
adcf2b9d ILT |
5769 | expr1.X_add_number = 0; |
5770 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5771 | (int) BFD_RELOC_LO16, AT); | |
5772 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5773 | treg, 8); | |
5774 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5775 | treg, AT); | |
670a50eb | 5776 | break; |
3d3c5039 ILT |
5777 | |
5778 | case M_USH: | |
8ea7f4e8 ILT |
5779 | if (offset_expr.X_add_number >= 0x7fff) |
5780 | as_bad ("operand overflow"); | |
b9129c6f | 5781 | if (target_big_endian) |
8ea7f4e8 | 5782 | offset_expr.X_add_number += 1; |
0dd2d296 | 5783 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5784 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5785 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 5786 | if (target_big_endian) |
8ea7f4e8 ILT |
5787 | offset_expr.X_add_number -= 1; |
5788 | else | |
5789 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5790 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5791 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5792 | break; |
3d3c5039 | 5793 | |
adcf2b9d ILT |
5794 | case M_USD: |
5795 | s = "sdl"; | |
5796 | s2 = "sdr"; | |
5797 | off = 7; | |
5798 | goto usw; | |
3d3c5039 | 5799 | case M_USW: |
adcf2b9d ILT |
5800 | s = "swl"; |
5801 | s2 = "swr"; | |
5802 | off = 3; | |
5803 | usw: | |
5804 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5805 | as_bad ("operand overflow"); |
b9129c6f | 5806 | if (! target_big_endian) |
adcf2b9d ILT |
5807 | offset_expr.X_add_number += off; |
5808 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5809 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5810 | if (! target_big_endian) |
adcf2b9d | 5811 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5812 | else |
adcf2b9d ILT |
5813 | offset_expr.X_add_number += off; |
5814 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5815 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5816 | return; |
3d3c5039 | 5817 | |
adcf2b9d ILT |
5818 | case M_USD_A: |
5819 | s = "sdl"; | |
5820 | s2 = "sdr"; | |
5821 | off = 7; | |
5822 | goto uswa; | |
3d3c5039 | 5823 | case M_USW_A: |
adcf2b9d ILT |
5824 | s = "swl"; |
5825 | s2 = "swr"; | |
5826 | off = 3; | |
5827 | uswa: | |
0dd2d296 | 5828 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5829 | if (breg != 0) |
5830 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5831 | mips_isa < 3 ? "addu" : "daddu", | |
5832 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5833 | if (! target_big_endian) |
adcf2b9d | 5834 | expr1.X_add_number = off; |
670a50eb | 5835 | else |
adcf2b9d ILT |
5836 | expr1.X_add_number = 0; |
5837 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5838 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5839 | if (! target_big_endian) |
adcf2b9d ILT |
5840 | expr1.X_add_number = 0; |
5841 | else | |
5842 | expr1.X_add_number = off; | |
5843 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5844 | (int) BFD_RELOC_LO16, AT); | |
5845 | break; | |
5846 | ||
5847 | case M_USH_A: | |
5848 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5849 | if (breg != 0) |
5850 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5851 | mips_isa < 3 ? "addu" : "daddu", | |
5852 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5853 | if (! target_big_endian) |
adcf2b9d ILT |
5854 | expr1.X_add_number = 0; |
5855 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5856 | (int) BFD_RELOC_LO16, AT); | |
5857 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
5858 | treg, 8); | |
b9129c6f | 5859 | if (! target_big_endian) |
adcf2b9d ILT |
5860 | expr1.X_add_number = 1; |
5861 | else | |
5862 | expr1.X_add_number = 0; | |
5863 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5864 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5865 | if (! target_big_endian) |
adcf2b9d ILT |
5866 | expr1.X_add_number = 0; |
5867 | else | |
5868 | expr1.X_add_number = 1; | |
5869 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5870 | (int) BFD_RELOC_LO16, AT); | |
5871 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5872 | treg, 8); | |
5873 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5874 | treg, AT); | |
670a50eb | 5875 | break; |
3d3c5039 ILT |
5876 | |
5877 | default: | |
670a50eb | 5878 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 5879 | break; |
3d3c5039 | 5880 | } |
670a50eb ILT |
5881 | if (mips_noat) |
5882 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
5883 | } |
5884 | ||
cc5703cd | 5885 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 5886 | |
3d3c5039 | 5887 | static void |
cc5703cd | 5888 | mips16_macro (ip) |
3d3c5039 ILT |
5889 | struct mips_cl_insn *ip; |
5890 | { | |
cc5703cd ILT |
5891 | int mask; |
5892 | int xreg, yreg, zreg, tmp; | |
5893 | int icnt; | |
5894 | expressionS expr1; | |
5895 | int dbl; | |
5896 | const char *s, *s2, *s3; | |
3d3c5039 | 5897 | |
cc5703cd | 5898 | mask = ip->insn_mo->mask; |
3d3c5039 | 5899 | |
cc5703cd ILT |
5900 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
5901 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
5902 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 5903 | |
cc5703cd | 5904 | icnt = 0; |
8358c818 | 5905 | |
cc5703cd ILT |
5906 | expr1.X_op = O_constant; |
5907 | expr1.X_op_symbol = NULL; | |
5908 | expr1.X_add_symbol = NULL; | |
5909 | expr1.X_add_number = 1; | |
8358c818 | 5910 | |
cc5703cd | 5911 | dbl = 0; |
517078c1 | 5912 | |
cc5703cd ILT |
5913 | switch (mask) |
5914 | { | |
5915 | default: | |
5916 | internalError (); | |
5917 | ||
5918 | case M_DDIV_3: | |
5919 | dbl = 1; | |
5920 | case M_DIV_3: | |
5921 | s = "mflo"; | |
5922 | goto do_div3; | |
5923 | case M_DREM_3: | |
5924 | dbl = 1; | |
5925 | case M_REM_3: | |
5926 | s = "mfhi"; | |
5927 | do_div3: | |
fbcfacb7 | 5928 | mips_emit_delays (true); |
cc5703cd ILT |
5929 | ++mips_noreorder; |
5930 | mips_any_noreorder = 1; | |
5931 | macro_build ((char *) NULL, &icnt, NULL, | |
5932 | dbl ? "ddiv" : "div", | |
5933 | "0,x,y", xreg, yreg); | |
8a8121d5 | 5934 | expr1.X_add_number = 2; |
cc5703cd | 5935 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5936 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5937 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
5938 | since that causes an overflow. We should do that as well, | |
5939 | but I don't see how to do the comparisons without a temporary | |
5940 | register. */ | |
5941 | --mips_noreorder; | |
5942 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
5943 | break; | |
5944 | ||
5945 | case M_DIVU_3: | |
5946 | s = "divu"; | |
5947 | s2 = "mflo"; | |
5948 | goto do_divu3; | |
5949 | case M_REMU_3: | |
5950 | s = "divu"; | |
5951 | s2 = "mfhi"; | |
5952 | goto do_divu3; | |
5953 | case M_DDIVU_3: | |
5954 | s = "ddivu"; | |
5955 | s2 = "mflo"; | |
5956 | goto do_divu3; | |
5957 | case M_DREMU_3: | |
5958 | s = "ddivu"; | |
5959 | s2 = "mfhi"; | |
5960 | do_divu3: | |
fbcfacb7 | 5961 | mips_emit_delays (true); |
cc5703cd ILT |
5962 | ++mips_noreorder; |
5963 | mips_any_noreorder = 1; | |
5964 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 5965 | expr1.X_add_number = 2; |
cc5703cd | 5966 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5967 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5968 | --mips_noreorder; | |
5969 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
5970 | break; | |
5971 | ||
5972 | case M_DSUBU_I: | |
5973 | dbl = 1; | |
5974 | goto do_subu; | |
5975 | case M_SUBU_I: | |
5976 | do_subu: | |
5977 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5978 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
5979 | dbl ? "daddiu" : "addiu", | |
5980 | "y,x,4", yreg, xreg); | |
5981 | break; | |
5982 | ||
5983 | case M_SUBU_I_2: | |
5984 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5985 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
5986 | "x,k", xreg); | |
5987 | break; | |
5988 | ||
5989 | case M_DSUBU_I_2: | |
5990 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5991 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
5992 | "y,j", yreg); | |
5993 | break; | |
5994 | ||
5995 | case M_BEQ: | |
5996 | s = "cmp"; | |
5997 | s2 = "bteqz"; | |
5998 | goto do_branch; | |
5999 | case M_BNE: | |
6000 | s = "cmp"; | |
6001 | s2 = "btnez"; | |
6002 | goto do_branch; | |
6003 | case M_BLT: | |
6004 | s = "slt"; | |
6005 | s2 = "btnez"; | |
6006 | goto do_branch; | |
6007 | case M_BLTU: | |
6008 | s = "sltu"; | |
6009 | s2 = "btnez"; | |
6010 | goto do_branch; | |
6011 | case M_BLE: | |
6012 | s = "slt"; | |
6013 | s2 = "bteqz"; | |
6014 | goto do_reverse_branch; | |
6015 | case M_BLEU: | |
6016 | s = "sltu"; | |
6017 | s2 = "bteqz"; | |
6018 | goto do_reverse_branch; | |
6019 | case M_BGE: | |
6020 | s = "slt"; | |
6021 | s2 = "bteqz"; | |
6022 | goto do_branch; | |
6023 | case M_BGEU: | |
6024 | s = "sltu"; | |
6025 | s2 = "bteqz"; | |
6026 | goto do_branch; | |
6027 | case M_BGT: | |
6028 | s = "slt"; | |
6029 | s2 = "btnez"; | |
6030 | goto do_reverse_branch; | |
6031 | case M_BGTU: | |
6032 | s = "sltu"; | |
6033 | s2 = "btnez"; | |
6034 | ||
6035 | do_reverse_branch: | |
6036 | tmp = xreg; | |
6037 | xreg = yreg; | |
6038 | yreg = tmp; | |
6039 | ||
6040 | do_branch: | |
6041 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6042 | xreg, yreg); | |
6043 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6044 | break; | |
6045 | ||
6046 | case M_BEQ_I: | |
6047 | s = "cmpi"; | |
6048 | s2 = "bteqz"; | |
6049 | s3 = "x,U"; | |
6050 | goto do_branch_i; | |
6051 | case M_BNE_I: | |
6052 | s = "cmpi"; | |
6053 | s2 = "btnez"; | |
6054 | s3 = "x,U"; | |
6055 | goto do_branch_i; | |
6056 | case M_BLT_I: | |
6057 | s = "slti"; | |
6058 | s2 = "btnez"; | |
6059 | s3 = "x,8"; | |
6060 | goto do_branch_i; | |
6061 | case M_BLTU_I: | |
6062 | s = "sltiu"; | |
6063 | s2 = "btnez"; | |
6064 | s3 = "x,8"; | |
6065 | goto do_branch_i; | |
6066 | case M_BLE_I: | |
6067 | s = "slti"; | |
6068 | s2 = "btnez"; | |
6069 | s3 = "x,8"; | |
6070 | goto do_addone_branch_i; | |
6071 | case M_BLEU_I: | |
6072 | s = "sltiu"; | |
6073 | s2 = "btnez"; | |
6074 | s3 = "x,8"; | |
6075 | goto do_addone_branch_i; | |
6076 | case M_BGE_I: | |
6077 | s = "slti"; | |
6078 | s2 = "bteqz"; | |
6079 | s3 = "x,8"; | |
6080 | goto do_branch_i; | |
6081 | case M_BGEU_I: | |
6082 | s = "sltiu"; | |
6083 | s2 = "bteqz"; | |
6084 | s3 = "x,8"; | |
6085 | goto do_branch_i; | |
6086 | case M_BGT_I: | |
6087 | s = "slti"; | |
6088 | s2 = "bteqz"; | |
6089 | s3 = "x,8"; | |
6090 | goto do_addone_branch_i; | |
6091 | case M_BGTU_I: | |
6092 | s = "sltiu"; | |
6093 | s2 = "bteqz"; | |
6094 | s3 = "x,8"; | |
6095 | ||
6096 | do_addone_branch_i: | |
6097 | ++imm_expr.X_add_number; | |
6098 | ||
6099 | do_branch_i: | |
6100 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6101 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6102 | break; | |
18e0764d ILT |
6103 | |
6104 | case M_ABS: | |
6105 | expr1.X_add_number = 0; | |
6106 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6107 | if (xreg != yreg) | |
6108 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6109 | "move", "y,X", xreg, yreg); | |
6110 | expr1.X_add_number = 2; | |
6111 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6112 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6113 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6114 | } |
6115 | } | |
6116 | ||
6117 | /* This routine assembles an instruction into its binary format. As a | |
6118 | side effect, it sets one of the global variables imm_reloc or | |
6119 | offset_reloc to the type of relocation to do if one of the operands | |
6120 | is an address expression. */ | |
6121 | ||
6122 | static void | |
6123 | mips_ip (str, ip) | |
6124 | char *str; | |
6125 | struct mips_cl_insn *ip; | |
6126 | { | |
6127 | char *s; | |
6128 | const char *args; | |
6129 | char c; | |
6130 | struct mips_opcode *insn; | |
6131 | char *argsStart; | |
6132 | unsigned int regno; | |
6133 | unsigned int lastregno = 0; | |
6134 | char *s_reset; | |
6135 | ||
6136 | insn_error = NULL; | |
6137 | ||
6138 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s) | |
6139 | continue; | |
6140 | switch (*s) | |
6141 | { | |
6142 | case '\0': | |
6143 | break; | |
6144 | ||
6145 | case ' ': | |
6146 | *s++ = '\0'; | |
6147 | break; | |
6148 | ||
6149 | default: | |
6150 | as_fatal ("Unknown opcode: `%s'", str); | |
6151 | } | |
6152 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
6153 | { | |
6154 | insn_error = "unrecognized opcode"; | |
6155 | return; | |
6156 | } | |
6157 | argsStart = s; | |
6158 | for (;;) | |
6159 | { | |
6160 | int insn_isa; | |
6161 | ||
6162 | assert (strcmp (insn->name, str) == 0); | |
6163 | ||
6164 | if (insn->pinfo == INSN_MACRO) | |
6165 | insn_isa = insn->match; | |
6166 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
6167 | insn_isa = 2; | |
6168 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
6169 | insn_isa = 3; | |
6170 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
6171 | insn_isa = 4; | |
6172 | else | |
6173 | insn_isa = 1; | |
6174 | ||
6175 | if (insn_isa > mips_isa | |
16262668 ILT |
6176 | || (insn->pinfo != INSN_MACRO |
6177 | && (((insn->pinfo & INSN_ISA) == INSN_4650 | |
6178 | && ! mips_4650) | |
6179 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
6180 | && ! mips_4010) | |
6181 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
6182 | && ! mips_4100) | |
6183 | /* start-sanitize-r5900 */ | |
6184 | || ((insn->pinfo & INSN_ISA) == INSN_5900 | |
6185 | && ! mips_5900) | |
6186 | /* end-sanitize-r5900 */ | |
6187 | ))) | |
cc5703cd ILT |
6188 | { |
6189 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6190 | && strcmp (insn->name, insn[1].name) == 0) | |
6191 | { | |
6192 | ++insn; | |
6193 | continue; | |
6194 | } | |
6195 | if (insn_isa <= mips_isa) | |
6196 | insn_error = "opcode not supported on this processor"; | |
6197 | else | |
6198 | { | |
6199 | static char buf[100]; | |
6200 | ||
6201 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6202 | insn_error = buf; | |
6203 | } | |
6204 | return; | |
6205 | } | |
8358c818 | 6206 | |
670a50eb ILT |
6207 | ip->insn_mo = insn; |
6208 | ip->insn_opcode = insn->match; | |
6209 | for (args = insn->args;; ++args) | |
6210 | { | |
6211 | if (*s == ' ') | |
6212 | ++s; | |
6213 | switch (*args) | |
6214 | { | |
6215 | case '\0': /* end of args */ | |
6216 | if (*s == '\0') | |
6217 | return; | |
6218 | break; | |
3d3c5039 ILT |
6219 | |
6220 | case ',': | |
670a50eb ILT |
6221 | if (*s++ == *args) |
6222 | continue; | |
6223 | s--; | |
6224 | switch (*++args) | |
6225 | { | |
3d3c5039 ILT |
6226 | case 'r': |
6227 | case 'v': | |
670a50eb ILT |
6228 | ip->insn_opcode |= lastregno << 21; |
6229 | continue; | |
3d3c5039 ILT |
6230 | |
6231 | case 'w': | |
6232 | case 'W': | |
670a50eb ILT |
6233 | ip->insn_opcode |= lastregno << 16; |
6234 | continue; | |
3d3c5039 ILT |
6235 | |
6236 | case 'V': | |
670a50eb ILT |
6237 | ip->insn_opcode |= lastregno << 11; |
6238 | continue; | |
3d3c5039 | 6239 | } |
670a50eb | 6240 | break; |
3d3c5039 ILT |
6241 | |
6242 | case '(': | |
670a50eb ILT |
6243 | /* handle optional base register. |
6244 | Either the base register is omitted or | |
6245 | we must have a left paren. */ | |
6246 | /* this is dependent on the next operand specifier | |
6247 | is a 'b' for base register */ | |
6248 | assert (args[1] == 'b'); | |
6249 | if (*s == '\0') | |
6250 | return; | |
3d3c5039 | 6251 | |
670a50eb ILT |
6252 | case ')': /* these must match exactly */ |
6253 | if (*s++ == *args) | |
3d3c5039 | 6254 | continue; |
670a50eb ILT |
6255 | break; |
6256 | ||
6257 | case '<': /* must be at least one digit */ | |
6258 | /* | |
6259 | * According to the manual, if the shift amount is greater | |
6260 | * than 31 or less than 0 the the shift amount should be | |
6261 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6262 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6263 | */ |
6264 | my_getExpression (&imm_expr, s); | |
6265 | check_absolute_expr (ip, &imm_expr); | |
6266 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6267 | { | |
58d4951d ILT |
6268 | as_warn ("Improper shift amount (%ld)", |
6269 | (long) imm_expr.X_add_number); | |
9226253a | 6270 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6271 | } |
6272 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6273 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6274 | s = expr_end; |
6275 | continue; | |
6276 | ||
56c96faa ILT |
6277 | case '>': /* shift amount minus 32 */ |
6278 | my_getExpression (&imm_expr, s); | |
6279 | check_absolute_expr (ip, &imm_expr); | |
6280 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6281 | || (unsigned long) imm_expr.X_add_number > 63) | |
6282 | break; | |
6283 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6284 | imm_expr.X_op = O_absent; | |
6285 | s = expr_end; | |
6286 | continue; | |
6287 | ||
9226253a | 6288 | case 'k': /* cache code */ |
d8a1c247 | 6289 | case 'h': /* prefx code */ |
9226253a ILT |
6290 | my_getExpression (&imm_expr, s); |
6291 | check_absolute_expr (ip, &imm_expr); | |
6292 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6293 | { | |
d8a1c247 KR |
6294 | as_warn ("Invalid value for `%s' (%lu)", |
6295 | ip->insn_mo->name, | |
9226253a ILT |
6296 | (unsigned long) imm_expr.X_add_number); |
6297 | imm_expr.X_add_number &= 0x1f; | |
6298 | } | |
d8a1c247 KR |
6299 | if (*args == 'k') |
6300 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6301 | else | |
6302 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6303 | imm_expr.X_op = O_absent; |
6304 | s = expr_end; | |
6305 | continue; | |
6306 | ||
670a50eb ILT |
6307 | case 'c': /* break code */ |
6308 | my_getExpression (&imm_expr, s); | |
6309 | check_absolute_expr (ip, &imm_expr); | |
6310 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6311 | as_warn ("Illegal break code (%ld)", |
6312 | (long) imm_expr.X_add_number); | |
670a50eb | 6313 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6314 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6315 | s = expr_end; |
6316 | continue; | |
6317 | ||
918692a5 ILT |
6318 | case 'B': /* syscall code */ |
6319 | my_getExpression (&imm_expr, s); | |
6320 | check_absolute_expr (ip, &imm_expr); | |
6321 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6322 | as_warn ("Illegal syscall code (%ld)", |
6323 | (long) imm_expr.X_add_number); | |
918692a5 | 6324 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6325 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6326 | s = expr_end; |
6327 | continue; | |
6328 | ||
0aa07269 ILT |
6329 | case 'C': /* Coprocessor code */ |
6330 | my_getExpression (&imm_expr, s); | |
6331 | check_absolute_expr (ip, &imm_expr); | |
6332 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6333 | { | |
58d4951d ILT |
6334 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6335 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6336 | imm_expr.X_add_number &= ((1<<25) - 1); |
6337 | } | |
6338 | ip->insn_opcode |= imm_expr.X_add_number; | |
6339 | imm_expr.X_op = O_absent; | |
6340 | s = expr_end; | |
6341 | continue; | |
6342 | ||
670a50eb ILT |
6343 | case 'b': /* base register */ |
6344 | case 'd': /* destination register */ | |
6345 | case 's': /* source register */ | |
6346 | case 't': /* target register */ | |
6347 | case 'r': /* both target and source */ | |
6348 | case 'v': /* both dest and source */ | |
6349 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6350 | case 'E': /* coprocessor target register */ |
6351 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6352 | case 'x': /* ignore register name */ |
ff3a5c18 | 6353 | case 'z': /* must be zero register */ |
670a50eb ILT |
6354 | s_reset = s; |
6355 | if (s[0] == '$') | |
6356 | { | |
6357 | if (isdigit (s[1])) | |
6358 | { | |
6359 | ++s; | |
6360 | regno = 0; | |
6361 | do | |
6362 | { | |
6363 | regno *= 10; | |
6364 | regno += *s - '0'; | |
6365 | ++s; | |
6366 | } | |
6367 | while (isdigit (*s)); | |
0aa07269 ILT |
6368 | if (regno > 31) |
6369 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6370 | } |
0dd2d296 ILT |
6371 | else if (*args == 'E' || *args == 'G') |
6372 | goto notreg; | |
6373 | else | |
670a50eb | 6374 | { |
0aa07269 ILT |
6375 | if (s[1] == 'f' && s[2] == 'p') |
6376 | { | |
6377 | s += 3; | |
9226253a | 6378 | regno = FP; |
0aa07269 ILT |
6379 | } |
6380 | else if (s[1] == 's' && s[2] == 'p') | |
6381 | { | |
6382 | s += 3; | |
9226253a | 6383 | regno = SP; |
0aa07269 ILT |
6384 | } |
6385 | else if (s[1] == 'g' && s[2] == 'p') | |
6386 | { | |
6387 | s += 3; | |
9226253a | 6388 | regno = GP; |
0aa07269 ILT |
6389 | } |
6390 | else if (s[1] == 'a' && s[2] == 't') | |
6391 | { | |
6392 | s += 3; | |
9226253a | 6393 | regno = AT; |
0aa07269 | 6394 | } |
b2b8c24e ILT |
6395 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6396 | { | |
6397 | s += 4; | |
6398 | regno = KT0; | |
6399 | } | |
6400 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6401 | { | |
6402 | s += 4; | |
6403 | regno = KT1; | |
6404 | } | |
0aa07269 ILT |
6405 | else |
6406 | goto notreg; | |
670a50eb | 6407 | } |
9753202d ILT |
6408 | if (regno == AT |
6409 | && ! mips_noat | |
6410 | && *args != 'E' | |
6411 | && *args != 'G') | |
13fe1379 | 6412 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6413 | c = *args; |
6414 | if (*s == ' ') | |
6415 | s++; | |
6416 | if (args[1] != *s) | |
6417 | { | |
6418 | if (c == 'r' || c == 'v' || c == 'w') | |
6419 | { | |
6420 | regno = lastregno; | |
6421 | s = s_reset; | |
6422 | args++; | |
6423 | } | |
6424 | } | |
ff3a5c18 ILT |
6425 | /* 'z' only matches $0. */ |
6426 | if (c == 'z' && regno != 0) | |
6427 | break; | |
670a50eb ILT |
6428 | switch (c) |
6429 | { | |
3d3c5039 ILT |
6430 | case 'r': |
6431 | case 's': | |
6432 | case 'v': | |
6433 | case 'b': | |
670a50eb ILT |
6434 | ip->insn_opcode |= regno << 21; |
6435 | break; | |
3d3c5039 | 6436 | case 'd': |
918692a5 | 6437 | case 'G': |
670a50eb ILT |
6438 | ip->insn_opcode |= regno << 11; |
6439 | break; | |
3d3c5039 ILT |
6440 | case 'w': |
6441 | case 't': | |
918692a5 | 6442 | case 'E': |
670a50eb | 6443 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6444 | break; |
6445 | case 'x': | |
6446 | /* This case exists because on the r3000 trunc | |
6447 | expands into a macro which requires a gp | |
6448 | register. On the r6000 or r4000 it is | |
6449 | assembled into a single instruction which | |
6450 | ignores the register. Thus the insn version | |
6451 | is MIPS_ISA2 and uses 'x', and the macro | |
6452 | version is MIPS_ISA1 and uses 't'. */ | |
6453 | break; | |
ff3a5c18 ILT |
6454 | case 'z': |
6455 | /* This case is for the div instruction, which | |
6456 | acts differently if the destination argument | |
6457 | is $0. This only matches $0, and is checked | |
6458 | outside the switch. */ | |
6459 | break; | |
3d3c5039 | 6460 | } |
670a50eb ILT |
6461 | lastregno = regno; |
6462 | continue; | |
3d3c5039 ILT |
6463 | } |
6464 | notreg: | |
670a50eb ILT |
6465 | switch (*args++) |
6466 | { | |
3d3c5039 ILT |
6467 | case 'r': |
6468 | case 'v': | |
670a50eb ILT |
6469 | ip->insn_opcode |= lastregno << 21; |
6470 | continue; | |
3d3c5039 | 6471 | case 'w': |
670a50eb ILT |
6472 | ip->insn_opcode |= lastregno << 16; |
6473 | continue; | |
3d3c5039 | 6474 | } |
670a50eb | 6475 | break; |
3d3c5039 | 6476 | |
670a50eb ILT |
6477 | case 'D': /* floating point destination register */ |
6478 | case 'S': /* floating point source register */ | |
6479 | case 'T': /* floating point target register */ | |
d8a1c247 | 6480 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6481 | case 'V': |
6482 | case 'W': | |
670a50eb ILT |
6483 | s_reset = s; |
6484 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6485 | { | |
6486 | s += 2; | |
6487 | regno = 0; | |
6488 | do | |
6489 | { | |
6490 | regno *= 10; | |
6491 | regno += *s - '0'; | |
6492 | ++s; | |
6493 | } | |
6494 | while (isdigit (*s)); | |
6495 | ||
6496 | if (regno > 31) | |
6497 | as_bad ("Invalid float register number (%d)", regno); | |
6498 | ||
9226253a ILT |
6499 | if ((regno & 1) != 0 |
6500 | && mips_isa < 3 | |
538034cf ILT |
6501 | && ! (strcmp (str, "mtc1") == 0 |
6502 | || strcmp (str, "mfc1") == 0 | |
6503 | || strcmp (str, "lwc1") == 0 | |
6504 | || strcmp (str, "swc1") == 0 | |
6505 | || strcmp (str, "l.s") == 0 | |
6506 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6507 | as_warn ("Float register should be even, was %d", |
6508 | regno); | |
6509 | ||
6510 | c = *args; | |
6511 | if (*s == ' ') | |
6512 | s++; | |
6513 | if (args[1] != *s) | |
6514 | { | |
6515 | if (c == 'V' || c == 'W') | |
6516 | { | |
6517 | regno = lastregno; | |
6518 | s = s_reset; | |
6519 | args++; | |
3d3c5039 ILT |
6520 | } |
6521 | } | |
670a50eb ILT |
6522 | switch (c) |
6523 | { | |
3d3c5039 | 6524 | case 'D': |
670a50eb ILT |
6525 | ip->insn_opcode |= regno << 6; |
6526 | break; | |
3d3c5039 ILT |
6527 | case 'V': |
6528 | case 'S': | |
670a50eb ILT |
6529 | ip->insn_opcode |= regno << 11; |
6530 | break; | |
3d3c5039 ILT |
6531 | case 'W': |
6532 | case 'T': | |
670a50eb | 6533 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6534 | break; |
6535 | case 'R': | |
6536 | ip->insn_opcode |= regno << 21; | |
6537 | break; | |
3d3c5039 | 6538 | } |
670a50eb ILT |
6539 | lastregno = regno; |
6540 | continue; | |
3d3c5039 | 6541 | } |
670a50eb ILT |
6542 | switch (*args++) |
6543 | { | |
3d3c5039 | 6544 | case 'V': |
670a50eb ILT |
6545 | ip->insn_opcode |= lastregno << 11; |
6546 | continue; | |
3d3c5039 | 6547 | case 'W': |
670a50eb ILT |
6548 | ip->insn_opcode |= lastregno << 16; |
6549 | continue; | |
3d3c5039 | 6550 | } |
670a50eb | 6551 | break; |
3d3c5039 ILT |
6552 | |
6553 | case 'I': | |
670a50eb | 6554 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6555 | if (imm_expr.X_op != O_big |
6556 | && imm_expr.X_op != O_constant) | |
6557 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6558 | s = expr_end; |
6559 | continue; | |
3d3c5039 ILT |
6560 | |
6561 | case 'A': | |
670a50eb ILT |
6562 | my_getExpression (&offset_expr, s); |
6563 | imm_reloc = BFD_RELOC_32; | |
6564 | s = expr_end; | |
6565 | continue; | |
3d3c5039 ILT |
6566 | |
6567 | case 'F': | |
19ed8960 ILT |
6568 | case 'L': |
6569 | case 'f': | |
6570 | case 'l': | |
6571 | { | |
6572 | int f64; | |
6573 | char *save_in; | |
6574 | char *err; | |
6575 | unsigned char temp[8]; | |
604633ae ILT |
6576 | int len; |
6577 | unsigned int length; | |
19ed8960 ILT |
6578 | segT seg; |
6579 | subsegT subseg; | |
6580 | char *p; | |
6581 | ||
6582 | /* These only appear as the last operand in an | |
6583 | instruction, and every instruction that accepts | |
6584 | them in any variant accepts them in all variants. | |
6585 | This means we don't have to worry about backing out | |
6586 | any changes if the instruction does not match. | |
6587 | ||
6588 | The difference between them is the size of the | |
6589 | floating point constant and where it goes. For 'F' | |
6590 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6591 | is 32 bits. Where the constant is placed is based | |
6592 | on how the MIPS assembler does things: | |
6593 | F -- .rdata | |
6594 | L -- .lit8 | |
6595 | f -- immediate value | |
6596 | l -- .lit4 | |
0dd2d296 | 6597 | |
55933a58 ILT |
6598 | The .lit4 and .lit8 sections are only used if |
6599 | permitted by the -G argument. | |
6600 | ||
6601 | When generating embedded PIC code, we use the | |
6602 | .lit8 section but not the .lit4 section (we can do | |
6603 | .lit4 inline easily; we need to put .lit8 | |
6604 | somewhere in the data segment, and using .lit8 | |
6605 | permits the linker to eventually combine identical | |
6606 | .lit8 entries). */ | |
19ed8960 ILT |
6607 | |
6608 | f64 = *args == 'F' || *args == 'L'; | |
6609 | ||
6610 | save_in = input_line_pointer; | |
6611 | input_line_pointer = s; | |
604633ae ILT |
6612 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6613 | length = len; | |
19ed8960 ILT |
6614 | s = input_line_pointer; |
6615 | input_line_pointer = save_in; | |
6616 | if (err != NULL && *err != '\0') | |
6617 | { | |
6618 | as_bad ("Bad floating point constant: %s", err); | |
6619 | memset (temp, '\0', sizeof temp); | |
6620 | length = f64 ? 8 : 4; | |
6621 | } | |
6622 | ||
6623 | assert (length == (f64 ? 8 : 4)); | |
6624 | ||
0dd2d296 | 6625 | if (*args == 'f' |
55933a58 | 6626 | || (*args == 'l' |
1dc1e798 KR |
6627 | && (! USE_GLOBAL_POINTER_OPT |
6628 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6629 | || g_switch_value < 4) |
1113140a | 6630 | )) |
19ed8960 ILT |
6631 | { |
6632 | imm_expr.X_op = O_constant; | |
b9129c6f | 6633 | if (! target_big_endian) |
19ed8960 ILT |
6634 | imm_expr.X_add_number = |
6635 | (((((((int) temp[3] << 8) | |
6636 | | temp[2]) << 8) | |
6637 | | temp[1]) << 8) | |
6638 | | temp[0]); | |
6639 | else | |
6640 | imm_expr.X_add_number = | |
6641 | (((((((int) temp[0] << 8) | |
6642 | | temp[1]) << 8) | |
6643 | | temp[2]) << 8) | |
6644 | | temp[3]); | |
6645 | } | |
6646 | else | |
6647 | { | |
0dd2d296 ILT |
6648 | const char *newname; |
6649 | segT new_seg; | |
6650 | ||
19ed8960 ILT |
6651 | /* Switch to the right section. */ |
6652 | seg = now_seg; | |
6653 | subseg = now_subseg; | |
6654 | switch (*args) | |
6655 | { | |
0dd2d296 | 6656 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6657 | case 'L': |
1113140a | 6658 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6659 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6660 | newname = ".lit8"; |
0dd2d296 ILT |
6661 | break; |
6662 | case 'F': | |
d2c71068 | 6663 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6664 | break; |
6665 | case 'l': | |
1dc1e798 KR |
6666 | assert (!USE_GLOBAL_POINTER_OPT |
6667 | || g_switch_value >= 4); | |
0dd2d296 | 6668 | newname = ".lit4"; |
19ed8960 ILT |
6669 | break; |
6670 | } | |
0dd2d296 | 6671 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6672 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6673 | bfd_set_section_flags (stdoutput, new_seg, | |
6674 | (SEC_ALLOC | |
6675 | | SEC_LOAD | |
6676 | | SEC_READONLY | |
6677 | | SEC_DATA)); | |
0221ddf7 | 6678 | frag_align (*args == 'l' ? 2 : 3, 0); |
1dc1e798 KR |
6679 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6680 | record_alignment (new_seg, 4); | |
6681 | else | |
6682 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6683 | if (seg == now_seg) |
6684 | as_bad ("Can't use floating point insn in this section"); | |
6685 | ||
6686 | /* Set the argument to the current address in the | |
6e8dda9c | 6687 | section. */ |
19ed8960 ILT |
6688 | offset_expr.X_op = O_symbol; |
6689 | offset_expr.X_add_symbol = | |
6690 | symbol_new ("L0\001", now_seg, | |
6691 | (valueT) frag_now_fix (), frag_now); | |
6692 | offset_expr.X_add_number = 0; | |
6693 | ||
6694 | /* Put the floating point number into the section. */ | |
604633ae | 6695 | p = frag_more ((int) length); |
19ed8960 ILT |
6696 | memcpy (p, temp, length); |
6697 | ||
6698 | /* Switch back to the original section. */ | |
6699 | subseg_set (seg, subseg); | |
6700 | } | |
6701 | } | |
670a50eb ILT |
6702 | continue; |
6703 | ||
6704 | case 'i': /* 16 bit unsigned immediate */ | |
6705 | case 'j': /* 16 bit signed immediate */ | |
6706 | imm_reloc = BFD_RELOC_LO16; | |
6707 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6708 | if (c != '\0') |
670a50eb ILT |
6709 | { |
6710 | if (c != 'l') | |
6711 | { | |
5ac34ac3 | 6712 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6713 | imm_expr.X_add_number = |
6714 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6715 | else if (c == 'h') | |
867a58b3 ILT |
6716 | { |
6717 | imm_reloc = BFD_RELOC_HI16_S; | |
6718 | imm_unmatched_hi = true; | |
6719 | } | |
670a50eb ILT |
6720 | else |
6721 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6722 | } |
670a50eb | 6723 | } |
670a50eb ILT |
6724 | if (*args == 'i') |
6725 | { | |
344a8d61 | 6726 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6727 | || ((imm_expr.X_add_number < 0 |
6728 | || imm_expr.X_add_number >= 0x10000) | |
6729 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6730 | { |
6731 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6732 | !strcmp (insn->name, insn[1].name)) | |
6733 | break; | |
9753202d ILT |
6734 | if (imm_expr.X_op != O_constant |
6735 | && imm_expr.X_op != O_big) | |
6736 | insn_error = "absolute expression required"; | |
6737 | else | |
6738 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6739 | } |
670a50eb ILT |
6740 | } |
6741 | else | |
6742 | { | |
d9aba805 ILT |
6743 | int more; |
6744 | offsetT max; | |
6745 | ||
be22008b ILT |
6746 | /* The upper bound should be 0x8000, but |
6747 | unfortunately the MIPS assembler accepts numbers | |
6748 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6749 | we want to be compatible. We only permit this |
6750 | extended range for an instruction which does not | |
6751 | provide any further alternates, since those | |
6752 | alternates may handle other cases. People should | |
6753 | use the numbers they mean, rather than relying on | |
6754 | a mysterious sign extension. */ | |
6755 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6756 | strcmp (insn->name, insn[1].name) == 0); | |
6757 | if (more) | |
6758 | max = 0x8000; | |
6759 | else | |
6760 | max = 0x10000; | |
344a8d61 | 6761 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6762 | || ((imm_expr.X_add_number < -0x8000 |
6763 | || imm_expr.X_add_number >= max) | |
6764 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
6765 | || (more |
6766 | && imm_expr.X_add_number < 0 | |
6767 | && mips_isa >= 3 | |
6768 | && imm_expr.X_unsigned | |
6769 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 6770 | { |
d9aba805 | 6771 | if (more) |
99c24539 | 6772 | break; |
9753202d ILT |
6773 | if (imm_expr.X_op != O_constant |
6774 | && imm_expr.X_op != O_big) | |
6775 | insn_error = "absolute expression required"; | |
6776 | else | |
6777 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 6778 | } |
3d3c5039 | 6779 | } |
670a50eb ILT |
6780 | s = expr_end; |
6781 | continue; | |
6782 | ||
6783 | case 'o': /* 16 bit offset */ | |
6784 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
6785 | |
6786 | /* If this value won't fit into a 16 bit offset, then go | |
6787 | find a macro that will generate the 32 bit offset | |
6788 | code pattern. As a special hack, we accept the | |
6789 | difference of two local symbols as a constant. This | |
6790 | is required to suppose embedded PIC switches, which | |
6791 | use an instruction which looks like | |
6792 | lw $4,$L12-$LS12($4) | |
6793 | The problem with handling this in a more general | |
6794 | fashion is that the macro function doesn't expect to | |
6795 | see anything which can be handled in a single | |
6796 | constant instruction. */ | |
6f0b87c3 SS |
6797 | if (c == 0 |
6798 | && (offset_expr.X_op != O_constant | |
6799 | || offset_expr.X_add_number >= 0x8000 | |
6800 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
6801 | && (mips_pic != EMBEDDED_PIC |
6802 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
6803 | || now_seg != text_section |
6804 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
6805 | != text_section))) | |
670a50eb | 6806 | break; |
3d3c5039 | 6807 | |
670a50eb ILT |
6808 | offset_reloc = BFD_RELOC_LO16; |
6809 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
6810 | { |
6811 | assert (offset_expr.X_op == O_constant); | |
6812 | offset_expr.X_add_number = | |
6813 | (offset_expr.X_add_number >> 16) & 0xffff; | |
6814 | } | |
cc5703cd ILT |
6815 | s = expr_end; |
6816 | continue; | |
6817 | ||
6818 | case 'p': /* pc relative offset */ | |
6819 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
6820 | my_getExpression (&offset_expr, s); | |
6821 | s = expr_end; | |
6822 | continue; | |
6823 | ||
6824 | case 'u': /* upper 16 bits */ | |
6825 | c = my_getSmallExpression (&imm_expr, s); | |
6826 | if (imm_expr.X_op == O_constant | |
6827 | && (imm_expr.X_add_number < 0 | |
6828 | || imm_expr.X_add_number >= 0x10000)) | |
6829 | as_bad ("lui expression not in range 0..65535"); | |
6830 | imm_reloc = BFD_RELOC_LO16; | |
6831 | if (c) | |
6832 | { | |
6833 | if (c != 'l') | |
6834 | { | |
6835 | if (imm_expr.X_op == O_constant) | |
6836 | imm_expr.X_add_number = | |
6837 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6838 | else if (c == 'h') | |
6839 | { | |
6840 | imm_reloc = BFD_RELOC_HI16_S; | |
6841 | imm_unmatched_hi = true; | |
6842 | } | |
6843 | else | |
6844 | imm_reloc = BFD_RELOC_HI16; | |
6845 | } | |
6846 | } | |
6847 | s = expr_end; | |
6848 | continue; | |
6849 | ||
6850 | case 'a': /* 26 bit address */ | |
6851 | my_getExpression (&offset_expr, s); | |
6852 | s = expr_end; | |
6853 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
6854 | continue; | |
6855 | ||
6856 | case 'N': /* 3 bit branch condition code */ | |
6857 | case 'M': /* 3 bit compare condition code */ | |
6858 | if (strncmp (s, "$fcc", 4) != 0) | |
6859 | break; | |
6860 | s += 4; | |
6861 | regno = 0; | |
6862 | do | |
6863 | { | |
6864 | regno *= 10; | |
6865 | regno += *s - '0'; | |
6866 | ++s; | |
6867 | } | |
6868 | while (isdigit (*s)); | |
6869 | if (regno > 7) | |
6870 | as_bad ("invalid condition code register $fcc%d", regno); | |
6871 | if (*args == 'N') | |
6872 | ip->insn_opcode |= regno << OP_SH_BCC; | |
6873 | else | |
6874 | ip->insn_opcode |= regno << OP_SH_CCC; | |
6875 | continue; | |
6876 | ||
6877 | default: | |
6878 | fprintf (stderr, "bad char = '%c'\n", *args); | |
6879 | internalError (); | |
6880 | } | |
6881 | break; | |
6882 | } | |
6883 | /* Args don't match. */ | |
6884 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6885 | !strcmp (insn->name, insn[1].name)) | |
6886 | { | |
6887 | ++insn; | |
6888 | s = argsStart; | |
6889 | continue; | |
6890 | } | |
6891 | insn_error = "illegal operands"; | |
6892 | return; | |
6893 | } | |
6894 | } | |
6895 | ||
6896 | /* This routine assembles an instruction into its binary format when | |
6897 | assembling for the mips16. As a side effect, it sets one of the | |
6898 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
6899 | relocation to do if one of the operands is an address expression. |
6900 | It also sets mips16_small and mips16_ext if the user explicitly | |
6901 | requested a small or extended instruction. */ | |
cc5703cd ILT |
6902 | |
6903 | static void | |
6904 | mips16_ip (str, ip) | |
6905 | char *str; | |
6906 | struct mips_cl_insn *ip; | |
6907 | { | |
6908 | char *s; | |
cc5703cd ILT |
6909 | const char *args; |
6910 | struct mips_opcode *insn; | |
6911 | char *argsstart; | |
6912 | unsigned int regno; | |
6913 | unsigned int lastregno = 0; | |
6914 | char *s_reset; | |
6915 | ||
6916 | insn_error = NULL; | |
6917 | ||
8728fa92 ILT |
6918 | mips16_small = false; |
6919 | mips16_ext = false; | |
cc5703cd ILT |
6920 | |
6921 | for (s = str; islower (*s); ++s) | |
6922 | ; | |
6923 | switch (*s) | |
6924 | { | |
6925 | case '\0': | |
6926 | break; | |
6927 | ||
6928 | case ' ': | |
6929 | *s++ = '\0'; | |
6930 | break; | |
6931 | ||
6932 | case '.': | |
6933 | if (s[1] == 't' && s[2] == ' ') | |
6934 | { | |
6935 | *s = '\0'; | |
8728fa92 | 6936 | mips16_small = true; |
cc5703cd ILT |
6937 | s += 3; |
6938 | break; | |
6939 | } | |
6940 | else if (s[1] == 'e' && s[2] == ' ') | |
6941 | { | |
6942 | *s = '\0'; | |
8728fa92 | 6943 | mips16_ext = true; |
cc5703cd ILT |
6944 | s += 3; |
6945 | break; | |
6946 | } | |
6947 | /* Fall through. */ | |
6948 | default: | |
6949 | insn_error = "unknown opcode"; | |
6950 | return; | |
6951 | } | |
6952 | ||
8728fa92 ILT |
6953 | if (! mips16_autoextend && ! mips16_ext) |
6954 | mips16_small = true; | |
6955 | ||
cc5703cd ILT |
6956 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
6957 | { | |
6958 | insn_error = "unrecognized opcode"; | |
6959 | return; | |
6960 | } | |
6961 | ||
6962 | argsstart = s; | |
6963 | for (;;) | |
6964 | { | |
6965 | assert (strcmp (insn->name, str) == 0); | |
6966 | ||
6967 | ip->insn_mo = insn; | |
6968 | ip->insn_opcode = insn->match; | |
6969 | ip->use_extend = false; | |
6970 | imm_expr.X_op = O_absent; | |
6971 | imm_reloc = BFD_RELOC_UNUSED; | |
6972 | offset_expr.X_op = O_absent; | |
6973 | offset_reloc = BFD_RELOC_UNUSED; | |
6974 | for (args = insn->args; 1; ++args) | |
6975 | { | |
6976 | int c; | |
6977 | ||
6978 | if (*s == ' ') | |
6979 | ++s; | |
6980 | ||
6981 | /* In this switch statement we call break if we did not find | |
6982 | a match, continue if we did find a match, or return if we | |
6983 | are done. */ | |
6984 | ||
6985 | c = *args; | |
6986 | switch (c) | |
6987 | { | |
6988 | case '\0': | |
6989 | if (*s == '\0') | |
6990 | { | |
6991 | /* Stuff the immediate value in now, if we can. */ | |
6992 | if (imm_expr.X_op == O_constant | |
6993 | && imm_reloc > BFD_RELOC_UNUSED | |
6994 | && insn->pinfo != INSN_MACRO) | |
6995 | { | |
15e69f98 ILT |
6996 | mips16_immed ((char *) NULL, 0, |
6997 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
6998 | imm_expr.X_add_number, true, mips16_small, |
6999 | mips16_ext, &ip->insn_opcode, | |
7000 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
7001 | imm_expr.X_op = O_absent; |
7002 | imm_reloc = BFD_RELOC_UNUSED; | |
7003 | } | |
7004 | ||
7005 | return; | |
7006 | } | |
7007 | break; | |
7008 | ||
7009 | case ',': | |
7010 | if (*s++ == c) | |
7011 | continue; | |
7012 | s--; | |
7013 | switch (*++args) | |
7014 | { | |
7015 | case 'v': | |
7016 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7017 | continue; | |
7018 | case 'w': | |
7019 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7020 | continue; | |
7021 | } | |
7022 | break; | |
7023 | ||
7024 | case '(': | |
7025 | case ')': | |
7026 | if (*s++ == c) | |
7027 | continue; | |
7028 | break; | |
7029 | ||
7030 | case 'v': | |
7031 | case 'w': | |
7032 | if (s[0] != '$') | |
7033 | { | |
7034 | if (c == 'v') | |
7035 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7036 | else | |
7037 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7038 | ++args; | |
7039 | continue; | |
7040 | } | |
7041 | /* Fall through. */ | |
7042 | case 'x': | |
7043 | case 'y': | |
7044 | case 'z': | |
7045 | case 'Z': | |
7046 | case '0': | |
7047 | case 'S': | |
7048 | case 'R': | |
7049 | case 'X': | |
7050 | case 'Y': | |
7051 | if (s[0] != '$') | |
7052 | break; | |
7053 | s_reset = s; | |
7054 | if (isdigit (s[1])) | |
7055 | { | |
7056 | ++s; | |
7057 | regno = 0; | |
7058 | do | |
7059 | { | |
7060 | regno *= 10; | |
7061 | regno += *s - '0'; | |
7062 | ++s; | |
7063 | } | |
7064 | while (isdigit (*s)); | |
7065 | if (regno > 31) | |
7066 | { | |
7067 | as_bad ("invalid register number (%d)", regno); | |
7068 | regno = 2; | |
7069 | } | |
7070 | } | |
7071 | else | |
7072 | { | |
7073 | if (s[1] == 'f' && s[2] == 'p') | |
7074 | { | |
7075 | s += 3; | |
7076 | regno = FP; | |
7077 | } | |
7078 | else if (s[1] == 's' && s[2] == 'p') | |
7079 | { | |
7080 | s += 3; | |
7081 | regno = SP; | |
7082 | } | |
7083 | else if (s[1] == 'g' && s[2] == 'p') | |
7084 | { | |
7085 | s += 3; | |
7086 | regno = GP; | |
7087 | } | |
7088 | else if (s[1] == 'a' && s[2] == 't') | |
7089 | { | |
7090 | s += 3; | |
7091 | regno = AT; | |
7092 | } | |
7093 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7094 | { | |
7095 | s += 4; | |
7096 | regno = KT0; | |
7097 | } | |
7098 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7099 | { | |
7100 | s += 4; | |
7101 | regno = KT1; | |
7102 | } | |
7103 | else | |
7104 | break; | |
7105 | } | |
7106 | ||
7107 | if (*s == ' ') | |
7108 | ++s; | |
7109 | if (args[1] != *s) | |
7110 | { | |
7111 | if (c == 'v' || c == 'w') | |
7112 | { | |
7113 | regno = mips16_to_32_reg_map[lastregno]; | |
7114 | s = s_reset; | |
7115 | args++; | |
7116 | } | |
7117 | } | |
7118 | ||
7119 | switch (c) | |
7120 | { | |
7121 | case 'x': | |
7122 | case 'y': | |
7123 | case 'z': | |
7124 | case 'v': | |
7125 | case 'w': | |
7126 | case 'Z': | |
7127 | regno = mips32_to_16_reg_map[regno]; | |
7128 | break; | |
7129 | ||
7130 | case '0': | |
7131 | if (regno != 0) | |
7132 | regno = ILLEGAL_REG; | |
7133 | break; | |
7134 | ||
7135 | case 'S': | |
7136 | if (regno != SP) | |
7137 | regno = ILLEGAL_REG; | |
7138 | break; | |
7139 | ||
7140 | case 'R': | |
7141 | if (regno != RA) | |
7142 | regno = ILLEGAL_REG; | |
7143 | break; | |
7144 | ||
7145 | case 'X': | |
7146 | case 'Y': | |
7147 | if (regno == AT && ! mips_noat) | |
7148 | as_warn ("used $at without \".set noat\""); | |
7149 | break; | |
7150 | ||
7151 | default: | |
7152 | internalError (); | |
7153 | } | |
7154 | ||
7155 | if (regno == ILLEGAL_REG) | |
7156 | break; | |
7157 | ||
7158 | switch (c) | |
7159 | { | |
7160 | case 'x': | |
7161 | case 'v': | |
7162 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7163 | break; | |
7164 | case 'y': | |
7165 | case 'w': | |
7166 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7167 | break; | |
7168 | case 'z': | |
7169 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7170 | break; | |
7171 | case 'Z': | |
7172 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7173 | case '0': | |
7174 | case 'S': | |
7175 | case 'R': | |
7176 | break; | |
7177 | case 'X': | |
7178 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7179 | break; | |
7180 | case 'Y': | |
7181 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7182 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7183 | break; | |
7184 | default: | |
7185 | internalError (); | |
7186 | } | |
7187 | ||
7188 | lastregno = regno; | |
7189 | continue; | |
7190 | ||
7191 | case 'P': | |
7192 | if (strncmp (s, "$pc", 3) == 0) | |
7193 | { | |
7194 | s += 3; | |
7195 | continue; | |
7196 | } | |
7197 | break; | |
7198 | ||
7199 | case '<': | |
7200 | case '>': | |
7201 | case '[': | |
7202 | case ']': | |
7203 | case '4': | |
7204 | case '5': | |
7205 | case 'H': | |
7206 | case 'W': | |
7207 | case 'D': | |
7208 | case 'j': | |
7209 | case '8': | |
7210 | case 'V': | |
7211 | case 'C': | |
7212 | case 'U': | |
7213 | case 'k': | |
7214 | case 'K': | |
16262668 ILT |
7215 | if (s[0] == '%' |
7216 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
7217 | { | |
7218 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
7219 | and generate the appropriate reloc. If the text | |
7220 | inside %gprel is not a symbol name with an | |
7221 | optional offset, then we generate a normal reloc | |
7222 | and will probably fail later. */ | |
7223 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
7224 | if (imm_expr.X_op == O_symbol) | |
7225 | { | |
7226 | mips16_ext = true; | |
7227 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
7228 | s = expr_end; | |
7229 | ip->use_extend = true; | |
7230 | ip->extend = 0; | |
7231 | continue; | |
7232 | } | |
7233 | } | |
7234 | else | |
7235 | { | |
7236 | /* Just pick up a normal expression. */ | |
7237 | my_getExpression (&imm_expr, s); | |
7238 | } | |
7239 | ||
ebf28372 ILT |
7240 | if (imm_expr.X_op == O_register) |
7241 | { | |
7242 | /* What we thought was an expression turned out to | |
7243 | be a register. */ | |
7244 | ||
7245 | if (s[0] == '(' && args[1] == '(') | |
7246 | { | |
7247 | /* It looks like the expression was omitted | |
7248 | before a register indirection, which means | |
7249 | that the expression is implicitly zero. We | |
7250 | still set up imm_expr, so that we handle | |
7251 | explicit extensions correctly. */ | |
7252 | imm_expr.X_op = O_constant; | |
7253 | imm_expr.X_add_number = 0; | |
7254 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7255 | continue; | |
7256 | } | |
7257 | ||
7258 | break; | |
7259 | } | |
7260 | ||
cc5703cd ILT |
7261 | /* We need to relax this instruction. */ |
7262 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7263 | s = expr_end; | |
7264 | continue; | |
7265 | ||
7266 | case 'p': | |
7267 | case 'q': | |
7268 | case 'A': | |
7269 | case 'B': | |
7270 | case 'E': | |
7271 | /* We use offset_reloc rather than imm_reloc for the PC | |
7272 | relative operands. This lets macros with both | |
7273 | immediate and address operands work correctly. */ | |
670a50eb | 7274 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
7275 | |
7276 | if (offset_expr.X_op == O_register) | |
7277 | break; | |
7278 | ||
cc5703cd ILT |
7279 | /* We need to relax this instruction. */ |
7280 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7281 | s = expr_end; |
7282 | continue; | |
7283 | ||
cc5703cd ILT |
7284 | case '6': /* break code */ |
7285 | my_getExpression (&imm_expr, s); | |
7286 | check_absolute_expr (ip, &imm_expr); | |
7287 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7288 | { |
cc5703cd ILT |
7289 | as_warn ("Invalid value for `%s' (%lu)", |
7290 | ip->insn_mo->name, | |
7291 | (unsigned long) imm_expr.X_add_number); | |
7292 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7293 | } |
cc5703cd ILT |
7294 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7295 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7296 | s = expr_end; |
7297 | continue; | |
3d3c5039 | 7298 | |
670a50eb ILT |
7299 | case 'a': /* 26 bit address */ |
7300 | my_getExpression (&offset_expr, s); | |
7301 | s = expr_end; | |
cc5703cd ILT |
7302 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7303 | ip->insn_opcode <<= 16; | |
670a50eb | 7304 | continue; |
3d3c5039 | 7305 | |
cc5703cd ILT |
7306 | case 'l': /* register list for entry macro */ |
7307 | case 'L': /* register list for exit macro */ | |
7308 | { | |
7309 | int mask; | |
7310 | ||
7311 | if (c == 'l') | |
7312 | mask = 0; | |
7313 | else | |
7314 | mask = 7 << 3; | |
7315 | while (*s != '\0') | |
7316 | { | |
c9167640 | 7317 | int freg, reg1, reg2; |
cc5703cd ILT |
7318 | |
7319 | while (*s == ' ' || *s == ',') | |
7320 | ++s; | |
7321 | if (*s != '$') | |
7322 | { | |
7323 | as_bad ("can't parse register list"); | |
7324 | break; | |
7325 | } | |
7326 | ++s; | |
c9167640 ILT |
7327 | if (*s != 'f') |
7328 | freg = 0; | |
7329 | else | |
7330 | { | |
7331 | freg = 1; | |
7332 | ++s; | |
7333 | } | |
cc5703cd ILT |
7334 | reg1 = 0; |
7335 | while (isdigit (*s)) | |
7336 | { | |
7337 | reg1 *= 10; | |
7338 | reg1 += *s - '0'; | |
7339 | ++s; | |
7340 | } | |
7341 | if (*s == ' ') | |
7342 | ++s; | |
7343 | if (*s != '-') | |
7344 | reg2 = reg1; | |
7345 | else | |
7346 | { | |
7347 | ++s; | |
7348 | if (*s != '$') | |
7349 | break; | |
7350 | ++s; | |
c9167640 ILT |
7351 | if (freg) |
7352 | { | |
7353 | if (*s == 'f') | |
7354 | ++s; | |
7355 | else | |
7356 | { | |
7357 | as_bad ("invalid register list"); | |
7358 | break; | |
7359 | } | |
7360 | } | |
cc5703cd ILT |
7361 | reg2 = 0; |
7362 | while (isdigit (*s)) | |
7363 | { | |
7364 | reg2 *= 10; | |
7365 | reg2 += *s - '0'; | |
7366 | ++s; | |
7367 | } | |
7368 | } | |
c9167640 ILT |
7369 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
7370 | { | |
7371 | mask &= ~ (7 << 3); | |
7372 | mask |= 5 << 3; | |
7373 | } | |
7374 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
7375 | { | |
7376 | mask &= ~ (7 << 3); | |
7377 | mask |= 6 << 3; | |
7378 | } | |
7379 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
7380 | mask |= (reg2 - 3) << 3; |
7381 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7382 | mask |= (reg2 - 15) << 1; | |
7383 | else if (reg1 == 31 && reg2 == 31) | |
7384 | mask |= 1; | |
7385 | else | |
c9167640 ILT |
7386 | { |
7387 | as_bad ("invalid register list"); | |
7388 | break; | |
7389 | } | |
cc5703cd | 7390 | } |
c9167640 ILT |
7391 | /* The mask is filled in in the opcode table for the |
7392 | benefit of the disassembler. We remove it before | |
7393 | applying the actual mask. */ | |
7394 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
7395 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
7396 | } | |
7397 | continue; | |
d8a1c247 | 7398 | |
3d3c5039 | 7399 | default: |
670a50eb | 7400 | internalError (); |
3d3c5039 | 7401 | } |
670a50eb | 7402 | break; |
3d3c5039 | 7403 | } |
cc5703cd | 7404 | |
670a50eb | 7405 | /* Args don't match. */ |
cc5703cd ILT |
7406 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7407 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7408 | { |
7409 | ++insn; | |
cc5703cd | 7410 | s = argsstart; |
670a50eb | 7411 | continue; |
3d3c5039 | 7412 | } |
cc5703cd | 7413 | |
9753202d | 7414 | insn_error = "illegal operands"; |
cc5703cd | 7415 | |
670a50eb | 7416 | return; |
3d3c5039 ILT |
7417 | } |
7418 | } | |
7419 | ||
cc5703cd ILT |
7420 | /* This structure holds information we know about a mips16 immediate |
7421 | argument type. */ | |
7422 | ||
7423 | struct mips16_immed_operand | |
7424 | { | |
7425 | /* The type code used in the argument string in the opcode table. */ | |
7426 | int type; | |
7427 | /* The number of bits in the short form of the opcode. */ | |
7428 | int nbits; | |
7429 | /* The number of bits in the extended form of the opcode. */ | |
7430 | int extbits; | |
7431 | /* The amount by which the short form is shifted when it is used; | |
7432 | for example, the sw instruction has a shift count of 2. */ | |
7433 | int shift; | |
7434 | /* The amount by which the short form is shifted when it is stored | |
7435 | into the instruction code. */ | |
7436 | int op_shift; | |
7437 | /* Non-zero if the short form is unsigned. */ | |
7438 | int unsp; | |
7439 | /* Non-zero if the extended form is unsigned. */ | |
7440 | int extu; | |
7441 | /* Non-zero if the value is PC relative. */ | |
7442 | int pcrel; | |
7443 | }; | |
7444 | ||
7445 | /* The mips16 immediate operand types. */ | |
7446 | ||
7447 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7448 | { | |
7449 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7450 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7451 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7452 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7453 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7454 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7455 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7456 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7457 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7458 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7459 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7460 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7461 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7462 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7463 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7464 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7465 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7466 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7467 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7468 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7469 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7470 | }; | |
7471 | ||
7472 | #define MIPS16_NUM_IMMED \ | |
7473 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7474 | ||
7475 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7476 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7477 | whether an extended value is needed; if one is needed, it sets | |
7478 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7479 | If SMALL is true, an unextended opcode was explicitly requested. | |
7480 | If EXT is true, an extended opcode was explicitly requested. If | |
7481 | WARN is true, warn if EXT does not match reality. */ | |
7482 | ||
7483 | static void | |
15e69f98 ILT |
7484 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7485 | extend) | |
7486 | char *file; | |
7487 | unsigned int line; | |
cc5703cd ILT |
7488 | int type; |
7489 | offsetT val; | |
7490 | boolean warn; | |
7491 | boolean small; | |
7492 | boolean ext; | |
7493 | unsigned long *insn; | |
7494 | boolean *use_extend; | |
7495 | unsigned short *extend; | |
7496 | { | |
7497 | register const struct mips16_immed_operand *op; | |
7498 | int mintiny, maxtiny; | |
7499 | boolean needext; | |
7500 | ||
7501 | op = mips16_immed_operands; | |
7502 | while (op->type != type) | |
7503 | { | |
7504 | ++op; | |
7505 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7506 | } | |
7507 | ||
7508 | if (op->unsp) | |
7509 | { | |
7510 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7511 | { | |
7512 | mintiny = 1; | |
7513 | maxtiny = 1 << op->nbits; | |
7514 | } | |
7515 | else | |
7516 | { | |
7517 | mintiny = 0; | |
7518 | maxtiny = (1 << op->nbits) - 1; | |
7519 | } | |
7520 | } | |
7521 | else | |
7522 | { | |
7523 | mintiny = - (1 << (op->nbits - 1)); | |
7524 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7525 | } | |
7526 | ||
7527 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7528 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 7529 | val /= 2; |
cc5703cd ILT |
7530 | |
7531 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7532 | || val < (mintiny << op->shift) | |
7533 | || val > (maxtiny << op->shift)) | |
7534 | needext = true; | |
7535 | else | |
7536 | needext = false; | |
7537 | ||
7538 | if (warn && ext && ! needext) | |
15e69f98 | 7539 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 7540 | if (small && needext) |
15e69f98 | 7541 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
7542 | |
7543 | if (small || (! ext && ! needext)) | |
7544 | { | |
7545 | int insnval; | |
7546 | ||
7547 | *use_extend = false; | |
7548 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7549 | insnval <<= op->op_shift; | |
7550 | *insn |= insnval; | |
7551 | } | |
7552 | else | |
7553 | { | |
7554 | long minext, maxext; | |
7555 | int extval; | |
7556 | ||
7557 | if (op->extu) | |
7558 | { | |
7559 | minext = 0; | |
7560 | maxext = (1 << op->extbits) - 1; | |
7561 | } | |
7562 | else | |
7563 | { | |
7564 | minext = - (1 << (op->extbits - 1)); | |
7565 | maxext = (1 << (op->extbits - 1)) - 1; | |
7566 | } | |
7567 | if (val < minext || val > maxext) | |
15e69f98 ILT |
7568 | as_bad_where (file, line, |
7569 | "operand value out of range for instruction"); | |
cc5703cd ILT |
7570 | |
7571 | *use_extend = true; | |
7572 | if (op->extbits == 16) | |
7573 | { | |
7574 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7575 | val &= 0x1f; | |
7576 | } | |
7577 | else if (op->extbits == 15) | |
7578 | { | |
7579 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7580 | val &= 0xf; | |
7581 | } | |
7582 | else | |
7583 | { | |
7584 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7585 | val = 0; | |
7586 | } | |
7587 | ||
7588 | *extend = (unsigned short) extval; | |
7589 | *insn |= val; | |
7590 | } | |
7591 | } | |
7592 | \f | |
3d3c5039 ILT |
7593 | #define LP '(' |
7594 | #define RP ')' | |
7595 | ||
7596 | static int | |
7597 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7598 | expressionS *ep; |
7599 | char *str; | |
3d3c5039 | 7600 | { |
670a50eb ILT |
7601 | char *sp; |
7602 | int c = 0; | |
7603 | ||
7604 | if (*str == ' ') | |
7605 | str++; | |
7606 | if (*str == LP | |
7607 | || (*str == '%' && | |
7608 | ((str[1] == 'h' && str[2] == 'i') | |
7609 | || (str[1] == 'H' && str[2] == 'I') | |
7610 | || (str[1] == 'l' && str[2] == 'o')) | |
7611 | && str[3] == LP)) | |
7612 | { | |
7613 | if (*str == LP) | |
7614 | c = 0; | |
7615 | else | |
7616 | { | |
7617 | c = str[1]; | |
7618 | str += 3; | |
7619 | } | |
7620 | ||
7621 | /* | |
7622 | * A small expression may be followed by a base register. | |
7623 | * Scan to the end of this operand, and then back over a possible | |
7624 | * base register. Then scan the small expression up to that | |
7625 | * point. (Based on code in sparc.c...) | |
7626 | */ | |
7627 | for (sp = str; *sp && *sp != ','; sp++) | |
7628 | ; | |
7629 | if (sp - 4 >= str && sp[-1] == RP) | |
7630 | { | |
7631 | if (isdigit (sp[-2])) | |
7632 | { | |
7633 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7634 | ; | |
7635 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7636 | { | |
7637 | sp--; | |
7638 | goto do_it; | |
3d3c5039 | 7639 | } |
670a50eb ILT |
7640 | } |
7641 | else if (sp - 5 >= str | |
7642 | && sp[-5] == LP | |
7643 | && sp[-4] == '$' | |
7644 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7645 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7646 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7647 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7648 | { | |
7649 | sp -= 5; | |
3d3c5039 | 7650 | do_it: |
670a50eb ILT |
7651 | if (sp == str) |
7652 | { | |
7653 | /* no expression means zero offset */ | |
7654 | if (c) | |
7655 | { | |
7656 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7657 | ep->X_op = O_absent; |
670a50eb | 7658 | expr_end = str - 3; |
3d3c5039 | 7659 | } |
670a50eb ILT |
7660 | else |
7661 | { | |
52aa70b5 | 7662 | ep->X_op = O_constant; |
670a50eb ILT |
7663 | expr_end = sp; |
7664 | } | |
7665 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7666 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7667 | ep->X_add_number = 0; |
7668 | } | |
7669 | else | |
7670 | { | |
7671 | *sp = '\0'; | |
7672 | my_getExpression (ep, str); | |
7673 | *sp = LP; | |
3d3c5039 | 7674 | } |
670a50eb | 7675 | return c; |
3d3c5039 ILT |
7676 | } |
7677 | } | |
7678 | } | |
670a50eb ILT |
7679 | my_getExpression (ep, str); |
7680 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7681 | } |
7682 | ||
7683 | static void | |
7684 | my_getExpression (ep, str) | |
670a50eb ILT |
7685 | expressionS *ep; |
7686 | char *str; | |
3d3c5039 | 7687 | { |
670a50eb | 7688 | char *save_in; |
670a50eb ILT |
7689 | |
7690 | save_in = input_line_pointer; | |
7691 | input_line_pointer = str; | |
5ac34ac3 | 7692 | expression (ep); |
670a50eb ILT |
7693 | expr_end = input_line_pointer; |
7694 | input_line_pointer = save_in; | |
3d3c5039 ILT |
7695 | } |
7696 | ||
becfe05e ILT |
7697 | /* Turn a string in input_line_pointer into a floating point constant |
7698 | of type type, and store the appropriate bytes in *litP. The number | |
7699 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7700 | returned, or NULL on OK. */ | |
7701 | ||
3d3c5039 | 7702 | char * |
670a50eb | 7703 | md_atof (type, litP, sizeP) |
becfe05e | 7704 | int type; |
3d3c5039 ILT |
7705 | char *litP; |
7706 | int *sizeP; | |
7707 | { | |
becfe05e ILT |
7708 | int prec; |
7709 | LITTLENUM_TYPE words[4]; | |
7710 | char *t; | |
7711 | int i; | |
7712 | ||
7713 | switch (type) | |
7714 | { | |
7715 | case 'f': | |
7716 | prec = 2; | |
7717 | break; | |
7718 | ||
7719 | case 'd': | |
7720 | prec = 4; | |
7721 | break; | |
7722 | ||
7723 | default: | |
7724 | *sizeP = 0; | |
7725 | return "bad call to md_atof"; | |
7726 | } | |
7727 | ||
7728 | t = atof_ieee (input_line_pointer, type, words); | |
7729 | if (t) | |
7730 | input_line_pointer = t; | |
7731 | ||
7732 | *sizeP = prec * 2; | |
7733 | ||
b9129c6f | 7734 | if (! target_big_endian) |
becfe05e ILT |
7735 | { |
7736 | for (i = prec - 1; i >= 0; i--) | |
7737 | { | |
7738 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7739 | litP += 2; | |
7740 | } | |
7741 | } | |
7742 | else | |
7743 | { | |
7744 | for (i = 0; i < prec; i++) | |
7745 | { | |
7746 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7747 | litP += 2; | |
7748 | } | |
7749 | } | |
7750 | ||
670a50eb | 7751 | return NULL; |
3d3c5039 ILT |
7752 | } |
7753 | ||
7754 | void | |
7755 | md_number_to_chars (buf, val, n) | |
7756 | char *buf; | |
918692a5 | 7757 | valueT val; |
3d3c5039 ILT |
7758 | int n; |
7759 | { | |
b9129c6f ILT |
7760 | if (target_big_endian) |
7761 | number_to_chars_bigendian (buf, val, n); | |
7762 | else | |
7763 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 7764 | } |
f3d817d8 | 7765 | \f |
e8d4d475 | 7766 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 7767 | |
f3d817d8 DM |
7768 | struct option md_longopts[] = { |
7769 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
7770 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
7771 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
7772 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
7773 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
7774 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
7775 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
7776 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
7777 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
7778 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 7779 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 7780 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 7781 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 7782 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
7783 | {"trap", no_argument, NULL, OPTION_TRAP}, |
7784 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 7785 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
7786 | {"break", no_argument, NULL, OPTION_BREAK}, |
7787 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 7788 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 7789 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 7790 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 7791 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 7792 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 7793 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 7794 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 7795 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
7796 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
7797 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
7798 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
7799 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
7800 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
7801 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
7802 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
7803 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 7804 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 7805 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 7806 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 7807 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
276c2d7d GRK |
7808 | /* start-sanitize-5900 */ |
7809 | #define OPTION_M5900 (OPTION_MD_BASE + 24) | |
7810 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
7811 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
7812 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
7813 | /* end-sanitize-5900 */ | |
f3d817d8 | 7814 | |
d8a1c247 | 7815 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 7816 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 7817 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
7818 | #define OPTION_32 (OPTION_MD_BASE + 20) |
7819 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 7820 | #ifdef OBJ_ELF |
f3d817d8 | 7821 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 7822 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 7823 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 7824 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
7825 | {"32", no_argument, NULL, OPTION_32}, |
7826 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
7827 | #endif |
7828 | ||
7829 | {NULL, no_argument, NULL, 0} | |
7830 | }; | |
7831 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
7832 | |
7833 | int | |
f3d817d8 DM |
7834 | md_parse_option (c, arg) |
7835 | int c; | |
7836 | char *arg; | |
3d3c5039 | 7837 | { |
f3d817d8 | 7838 | switch (c) |
670a50eb | 7839 | { |
f3d817d8 DM |
7840 | case OPTION_TRAP: |
7841 | mips_trap = 1; | |
7842 | break; | |
670a50eb | 7843 | |
f3d817d8 DM |
7844 | case OPTION_BREAK: |
7845 | mips_trap = 0; | |
7846 | break; | |
7847 | ||
e8d4d475 | 7848 | case OPTION_EB: |
1dc1e798 | 7849 | target_big_endian = 1; |
e8d4d475 | 7850 | break; |
04cb3372 | 7851 | |
e8d4d475 | 7852 | case OPTION_EL: |
1dc1e798 | 7853 | target_big_endian = 0; |
f3d817d8 | 7854 | break; |
670a50eb | 7855 | |
f3d817d8 DM |
7856 | case 'O': |
7857 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
7858 | mips_optimize = 1; |
7859 | else | |
7860 | mips_optimize = 2; | |
f3d817d8 | 7861 | break; |
0aa07269 | 7862 | |
f3d817d8 | 7863 | case 'g': |
22ba90ce ILT |
7864 | if (arg == NULL) |
7865 | mips_debug = 2; | |
7866 | else | |
7867 | mips_debug = atoi (arg); | |
7868 | /* When the MIPS assembler sees -g or -g2, it does not do | |
7869 | optimizations which limit full symbolic debugging. We take | |
7870 | that to be equivalent to -O0. */ | |
7871 | if (mips_debug == 2) | |
0aa07269 | 7872 | mips_optimize = 0; |
f3d817d8 | 7873 | break; |
4e95866e | 7874 | |
f3d817d8 DM |
7875 | case OPTION_MIPS1: |
7876 | mips_isa = 1; | |
4bb0cc41 ILT |
7877 | if (mips_cpu == -1) |
7878 | mips_cpu = 3000; | |
f3d817d8 | 7879 | break; |
8358c818 | 7880 | |
f3d817d8 DM |
7881 | case OPTION_MIPS2: |
7882 | mips_isa = 2; | |
4bb0cc41 ILT |
7883 | if (mips_cpu == -1) |
7884 | mips_cpu = 6000; | |
f3d817d8 | 7885 | break; |
8358c818 | 7886 | |
f3d817d8 DM |
7887 | case OPTION_MIPS3: |
7888 | mips_isa = 3; | |
4bb0cc41 ILT |
7889 | if (mips_cpu == -1) |
7890 | mips_cpu = 4000; | |
f3d817d8 | 7891 | break; |
8358c818 | 7892 | |
d8a1c247 KR |
7893 | case OPTION_MIPS4: |
7894 | mips_isa = 4; | |
7895 | if (mips_cpu == -1) | |
7896 | mips_cpu = 8000; | |
7897 | break; | |
7898 | ||
f3d817d8 DM |
7899 | case OPTION_MCPU: |
7900 | { | |
7901 | char *p; | |
7902 | ||
7903 | /* Identify the processor type */ | |
7904 | p = arg; | |
7905 | if (strcmp (p, "default") == 0 | |
7906 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 7907 | mips_cpu = -1; |
f3d817d8 DM |
7908 | else |
7909 | { | |
c625fc23 JSC |
7910 | int sv = 0; |
7911 | ||
7912 | /* We need to cope with the various "vr" prefixes for the 4300 | |
7913 | processor. */ | |
7914 | if (*p == 'v' || *p == 'V') | |
7915 | { | |
7916 | sv = 1; | |
7917 | p++; | |
7918 | } | |
7919 | ||
f3d817d8 DM |
7920 | if (*p == 'r' || *p == 'R') |
7921 | p++; | |
8358c818 | 7922 | |
4bb0cc41 | 7923 | mips_cpu = -1; |
f3d817d8 DM |
7924 | switch (*p) |
7925 | { | |
d8a1c247 KR |
7926 | case '1': |
7927 | if (strcmp (p, "10000") == 0 | |
7928 | || strcmp (p, "10k") == 0 | |
7929 | || strcmp (p, "10K") == 0) | |
7930 | mips_cpu = 10000; | |
7931 | break; | |
7932 | ||
f3d817d8 DM |
7933 | case '2': |
7934 | if (strcmp (p, "2000") == 0 | |
7935 | || strcmp (p, "2k") == 0 | |
7936 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 7937 | mips_cpu = 2000; |
f3d817d8 | 7938 | break; |
8358c818 | 7939 | |
f3d817d8 DM |
7940 | case '3': |
7941 | if (strcmp (p, "3000") == 0 | |
7942 | || strcmp (p, "3k") == 0 | |
7943 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 7944 | mips_cpu = 3000; |
f3d817d8 | 7945 | break; |
8358c818 | 7946 | |
f3d817d8 DM |
7947 | case '4': |
7948 | if (strcmp (p, "4000") == 0 | |
7949 | || strcmp (p, "4k") == 0 | |
8c63448a | 7950 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 7951 | mips_cpu = 4000; |
c625fc23 JSC |
7952 | else if (strcmp (p, "4100") == 0) |
7953 | { | |
7954 | mips_cpu = 4100; | |
7955 | if (mips_4100 < 0) | |
7956 | mips_4100 = 1; | |
7957 | } | |
7958 | else if (strcmp (p, "4300") == 0) | |
7959 | mips_cpu = 4300; | |
8c63448a | 7960 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 7961 | mips_cpu = 4400; |
8c63448a | 7962 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 7963 | mips_cpu = 4600; |
b2b8c24e ILT |
7964 | else if (strcmp (p, "4650") == 0) |
7965 | { | |
7966 | mips_cpu = 4650; | |
7967 | if (mips_4650 < 0) | |
7968 | mips_4650 = 1; | |
7969 | } | |
e532b44c ILT |
7970 | else if (strcmp (p, "4010") == 0) |
7971 | { | |
7972 | mips_cpu = 4010; | |
7973 | if (mips_4010 < 0) | |
7974 | mips_4010 = 1; | |
7975 | } | |
f3d817d8 | 7976 | break; |
8358c818 | 7977 | |
517078c1 ILT |
7978 | case '5': |
7979 | if (strcmp (p, "5000") == 0 | |
7980 | || strcmp (p, "5k") == 0 | |
7981 | || strcmp (p, "5K") == 0) | |
7982 | mips_cpu = 5000; | |
276c2d7d GRK |
7983 | /* start-sanitize-r5900 */ |
7984 | else if (strcmp (p, "5900") == 0) | |
7985 | mips_cpu = 5900; | |
7986 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
7987 | break; |
7988 | ||
f3d817d8 DM |
7989 | case '6': |
7990 | if (strcmp (p, "6000") == 0 | |
7991 | || strcmp (p, "6k") == 0 | |
7992 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 7993 | mips_cpu = 6000; |
f3d817d8 | 7994 | break; |
55933a58 | 7995 | |
d8a1c247 KR |
7996 | case '8': |
7997 | if (strcmp (p, "8000") == 0 | |
7998 | || strcmp (p, "8k") == 0 | |
7999 | || strcmp (p, "8K") == 0) | |
8000 | mips_cpu = 8000; | |
8001 | break; | |
8002 | ||
55933a58 ILT |
8003 | case 'o': |
8004 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 8005 | mips_cpu = 4600; |
55933a58 | 8006 | break; |
f3d817d8 | 8007 | } |
8358c818 | 8008 | |
517078c1 | 8009 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
8010 | { |
8011 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
8012 | return 0; | |
8013 | } | |
8014 | ||
4bb0cc41 | 8015 | if (mips_cpu == -1) |
f3d817d8 DM |
8016 | { |
8017 | as_bad ("invalid architecture -mcpu=%s", arg); | |
8018 | return 0; | |
8019 | } | |
8020 | } | |
8021 | } | |
8022 | break; | |
8358c818 | 8023 | |
b2b8c24e ILT |
8024 | case OPTION_M4650: |
8025 | mips_4650 = 1; | |
8026 | break; | |
8027 | ||
8028 | case OPTION_NO_M4650: | |
8029 | mips_4650 = 0; | |
8030 | break; | |
8031 | ||
e532b44c ILT |
8032 | case OPTION_M4010: |
8033 | mips_4010 = 1; | |
8034 | break; | |
8035 | ||
8036 | case OPTION_NO_M4010: | |
8037 | mips_4010 = 0; | |
8038 | break; | |
8039 | ||
c625fc23 JSC |
8040 | case OPTION_M4100: |
8041 | mips_4100 = 1; | |
8042 | break; | |
8043 | ||
8044 | case OPTION_NO_M4100: | |
8045 | mips_4100 = 0; | |
8046 | break; | |
8047 | ||
276c2d7d GRK |
8048 | /* start-sanitize-r5900 */ |
8049 | case OPTION_M5900: | |
8050 | mips_5900 = 1; | |
8051 | break; | |
8052 | ||
8053 | case OPTION_NO_M5900: | |
8054 | mips_5900 = 0; | |
8055 | break; | |
8056 | /* end-sanitize-r5900 */ | |
8057 | ||
cc5703cd ILT |
8058 | case OPTION_MIPS16: |
8059 | mips16 = 1; | |
8060 | mips_no_prev_insn (); | |
8061 | break; | |
8062 | ||
8063 | case OPTION_NO_MIPS16: | |
8064 | mips16 = 0; | |
8065 | mips_no_prev_insn (); | |
8066 | break; | |
8067 | ||
f3d817d8 | 8068 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 8069 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 8070 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
8071 | { |
8072 | as_bad ("-G may not be used with embedded PIC code"); | |
8073 | return 0; | |
8074 | } | |
5b63f465 | 8075 | g_switch_value = 0x7fffffff; |
f3d817d8 | 8076 | break; |
d9aba805 | 8077 | |
fb251650 ILT |
8078 | /* When generating ELF code, we permit -KPIC and -call_shared to |
8079 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
8080 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 8081 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
8082 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8083 | { | |
8084 | as_bad ("-call_shared is supported only for ELF format"); | |
8085 | return 0; | |
8086 | } | |
d9aba805 ILT |
8087 | mips_pic = SVR4_PIC; |
8088 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
8089 | { |
8090 | as_bad ("-G may not be used with SVR4 PIC code"); | |
8091 | return 0; | |
8092 | } | |
d9aba805 | 8093 | g_switch_value = 0; |
f3d817d8 DM |
8094 | break; |
8095 | ||
8096 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
8097 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8098 | { | |
8099 | as_bad ("-non_shared is supported only for ELF format"); | |
8100 | return 0; | |
8101 | } | |
d9aba805 | 8102 | mips_pic = NO_PIC; |
f3d817d8 | 8103 | break; |
8358c818 | 8104 | |
fb251650 ILT |
8105 | /* The -xgot option tells the assembler to use 32 offsets when |
8106 | accessing the got in SVR4_PIC mode. It is for Irix | |
8107 | compatibility. */ | |
8108 | case OPTION_XGOT: | |
8109 | mips_big_got = 1; | |
8110 | break; | |
8111 | ||
f3d817d8 | 8112 | case 'G': |
1dc1e798 KR |
8113 | if (! USE_GLOBAL_POINTER_OPT) |
8114 | { | |
8115 | as_bad ("-G is not supported for this configuration"); | |
8116 | return 0; | |
8117 | } | |
8118 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 8119 | { |
f3d817d8 DM |
8120 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
8121 | return 0; | |
670a50eb ILT |
8122 | } |
8123 | else | |
f3d817d8 | 8124 | g_switch_value = atoi (arg); |
42562568 | 8125 | g_switch_seen = 1; |
f3d817d8 | 8126 | break; |
4e95866e | 8127 | |
7f9880e5 ILT |
8128 | /* The -32 and -64 options tell the assembler to output the 32 |
8129 | bit or the 64 bit MIPS ELF format. */ | |
8130 | case OPTION_32: | |
8131 | mips_64 = 0; | |
8132 | break; | |
8133 | ||
8134 | case OPTION_64: | |
9c44af60 ILT |
8135 | { |
8136 | const char **list, **l; | |
8137 | ||
8138 | list = bfd_target_list (); | |
8139 | for (l = list; *l != NULL; l++) | |
8140 | if (strcmp (*l, "elf64-bigmips") == 0 | |
8141 | || strcmp (*l, "elf64-littlemips") == 0) | |
8142 | break; | |
8143 | if (*l == NULL) | |
8144 | as_fatal ("No compiled in support for 64 bit object file format"); | |
8145 | free (list); | |
8146 | mips_64 = 1; | |
8147 | } | |
7f9880e5 ILT |
8148 | break; |
8149 | ||
f3d817d8 DM |
8150 | default: |
8151 | return 0; | |
8ea7f4e8 ILT |
8152 | } |
8153 | ||
f3d817d8 | 8154 | return 1; |
8ea7f4e8 ILT |
8155 | } |
8156 | ||
f3d817d8 DM |
8157 | void |
8158 | md_show_usage (stream) | |
8159 | FILE *stream; | |
8160 | { | |
8161 | fprintf(stream, "\ | |
8162 | MIPS options:\n\ | |
8163 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
8164 | -EB generate big endian output\n\ |
8165 | -EL generate little endian output\n\ | |
8166 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8167 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8168 | implicitly with the gp register [default 8]\n"); |
8169 | fprintf(stream, "\ | |
f3d817d8 DM |
8170 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8171 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8172 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8173 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8174 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8175 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8176 | -m4650 permit R4650 instructions\n\ |
8177 | -no-m4650 do not permit R4650 instructions\n\ | |
8178 | -m4010 permit R4010 instructions\n\ | |
8179 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8180 | -m4100 permit VR4100 instructions\n\ |
8181 | -no-m4100 do not permit VR4100 instructions\n"); | |
8182 | fprintf(stream, "\ | |
cc5703cd ILT |
8183 | -mips16 generate mips16 instructions\n\ |
8184 | -no-mips16 do not generate mips16 instructions\n"); | |
8185 | fprintf(stream, "\ | |
f3d817d8 DM |
8186 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8187 | -O remove unneeded NOPs and swap branches\n\ | |
8188 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8189 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8190 | #ifdef OBJ_ELF | |
8191 | fprintf(stream, "\ | |
8192 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8193 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8194 | -xgot assume a 32 bit GOT\n\ |
8195 | -32 create 32 bit object file (default)\n\ | |
8196 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8197 | #endif |
8198 | } | |
8199 | \f | |
3d3c5039 ILT |
8200 | long |
8201 | md_pcrel_from (fixP) | |
8202 | fixS *fixP; | |
8203 | { | |
1dc1e798 KR |
8204 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8205 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8206 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8207 | { | |
8208 | /* This makes a branch to an undefined symbol be a branch to the | |
8209 | current location. */ | |
8210 | return 4; | |
8211 | } | |
5b63f465 | 8212 | |
670a50eb ILT |
8213 | /* return the address of the delay slot */ |
8214 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8215 | } |
8216 | ||
abdad6bc ILT |
8217 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8218 | reloc for a cons. We could use the definition there, except that | |
8219 | we want to handle 64 bit relocs specially. */ | |
8220 | ||
8221 | void | |
8222 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8223 | fragS *frag; | |
8224 | int where; | |
8225 | unsigned int nbytes; | |
8226 | expressionS *exp; | |
8227 | { | |
bf39474f | 8228 | #ifndef OBJ_ELF |
abdad6bc | 8229 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8230 | 4 byte reloc. */ |
8231 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8232 | { |
b9129c6f | 8233 | if (target_big_endian) |
abdad6bc ILT |
8234 | where += 4; |
8235 | nbytes = 4; | |
8236 | } | |
bf39474f | 8237 | #endif |
abdad6bc | 8238 | |
7f9880e5 | 8239 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8240 | as_bad ("Unsupported reloc size %d", nbytes); |
8241 | ||
8242 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8243 | (nbytes == 2 |
8244 | ? BFD_RELOC_16 | |
8245 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8246 | } |
8247 | ||
867a58b3 ILT |
8248 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8249 | the corresponding LO reloc. This is called before md_apply_fix and | |
8250 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8251 | explicit use of the %hi modifier. */ | |
8252 | ||
8253 | void | |
8254 | mips_frob_file () | |
8255 | { | |
8256 | struct mips_hi_fixup *l; | |
8257 | ||
8258 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8259 | { | |
8260 | segment_info_type *seginfo; | |
9b61d62b | 8261 | int pass; |
867a58b3 ILT |
8262 | |
8263 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8264 | ||
8265 | /* Check quickly whether the next fixup happens to be a matching | |
8266 | %lo. */ | |
8267 | if (l->fixp->fx_next != NULL | |
8268 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8269 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8270 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8271 | continue; | |
8272 | ||
8273 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8274 | When we find one, move the %hi just in front of it. We do |
8275 | this in two passes. In the first pass, we try to find a | |
8276 | unique %lo. In the second pass, we permit multiple %hi | |
8277 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8278 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8279 | for (pass = 0; pass < 2; pass++) |
8280 | { | |
8281 | fixS *f, *prev; | |
8282 | ||
8283 | prev = NULL; | |
8284 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8285 | { |
9b61d62b ILT |
8286 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8287 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8288 | && f->fx_addsy == l->fixp->fx_addsy | |
8289 | && f->fx_offset == l->fixp->fx_offset | |
8290 | && (pass == 1 | |
8291 | || prev == NULL | |
8292 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8293 | || prev->fx_addsy != f->fx_addsy | |
8294 | || prev->fx_offset != f->fx_offset)) | |
8295 | { | |
8296 | fixS **pf; | |
867a58b3 | 8297 | |
9b61d62b ILT |
8298 | /* Move l->fixp before f. */ |
8299 | for (pf = &seginfo->fix_root; | |
8300 | *pf != l->fixp; | |
8301 | pf = &(*pf)->fx_next) | |
8302 | assert (*pf != NULL); | |
867a58b3 | 8303 | |
9b61d62b | 8304 | *pf = l->fixp->fx_next; |
867a58b3 | 8305 | |
9b61d62b ILT |
8306 | l->fixp->fx_next = f; |
8307 | if (prev == NULL) | |
8308 | seginfo->fix_root = l->fixp; | |
8309 | else | |
8310 | prev->fx_next = l->fixp; | |
867a58b3 | 8311 | |
9b61d62b ILT |
8312 | break; |
8313 | } | |
8314 | ||
8315 | prev = f; | |
867a58b3 ILT |
8316 | } |
8317 | ||
9b61d62b ILT |
8318 | if (f != NULL) |
8319 | break; | |
867a58b3 | 8320 | |
9b61d62b ILT |
8321 | if (pass == 1) |
8322 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8323 | "Unmatched %%hi reloc"); | |
8324 | } | |
867a58b3 ILT |
8325 | } |
8326 | } | |
8327 | ||
1c803e52 ILT |
8328 | /* When generating embedded PIC code we need to use a special |
8329 | relocation to represent the difference of two symbols in the .text | |
8330 | section (switch tables use a difference of this sort). See | |
8331 | include/coff/mips.h for details. This macro checks whether this | |
8332 | fixup requires the special reloc. */ | |
8333 | #define SWITCH_TABLE(fixp) \ | |
8334 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8335 | && (fixp)->fx_addsy != NULL \ | |
8336 | && (fixp)->fx_subsy != NULL \ | |
8337 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8338 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8339 | ||
5b63f465 | 8340 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8341 | relocations, in case the linker has to relax a call. We also need |
8342 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8343 | |
8344 | /*ARGSUSED*/ | |
8345 | int | |
8346 | mips_force_relocation (fixp) | |
8347 | fixS *fixp; | |
8348 | { | |
1c803e52 | 8349 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8350 | && (fixp->fx_pcrel |
8351 | || SWITCH_TABLE (fixp) | |
8352 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8353 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8354 | } |
8355 | ||
8356 | /* Apply a fixup to the object file. */ | |
8357 | ||
3d3c5039 ILT |
8358 | int |
8359 | md_apply_fix (fixP, valueP) | |
8360 | fixS *fixP; | |
918692a5 | 8361 | valueT *valueP; |
3d3c5039 | 8362 | { |
670a50eb ILT |
8363 | unsigned char *buf; |
8364 | long insn, value; | |
3d3c5039 | 8365 | |
bf39474f ILT |
8366 | assert (fixP->fx_size == 4 |
8367 | || fixP->fx_r_type == BFD_RELOC_16 | |
8368 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8369 | |
670a50eb | 8370 | value = *valueP; |
1748b9d8 ILT |
8371 | |
8372 | /* If we aren't adjusting this fixup to be against the section | |
8373 | symbol, we need to adjust the value. */ | |
8374 | #ifdef S_GET_OTHER | |
8375 | if (fixP->fx_addsy != NULL | |
1748b9d8 ILT |
8376 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
8377 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
8378 | { | |
8379 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8380 | if (value != 0 && ! fixP->fx_pcrel) | |
8381 | { | |
8382 | /* In this case, the bfd_install_relocation routine will | |
8383 | incorrectly add the symbol value back in. We just want | |
8384 | the addend to appear in the object file. */ | |
8385 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8386 | } | |
8387 | } | |
8388 | #endif | |
8389 | ||
670a50eb | 8390 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 8391 | |
5b63f465 ILT |
8392 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8393 | fixP->fx_done = 1; | |
8394 | ||
670a50eb ILT |
8395 | switch (fixP->fx_r_type) |
8396 | { | |
3d3c5039 ILT |
8397 | case BFD_RELOC_MIPS_JMP: |
8398 | case BFD_RELOC_HI16: | |
8399 | case BFD_RELOC_HI16_S: | |
670a50eb | 8400 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8401 | case BFD_RELOC_MIPS_LITERAL: |
8402 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8403 | case BFD_RELOC_MIPS_GOT16: |
8404 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8405 | case BFD_RELOC_MIPS_GOT_HI16: |
8406 | case BFD_RELOC_MIPS_GOT_LO16: | |
8407 | case BFD_RELOC_MIPS_CALL_HI16: | |
8408 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 8409 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 8410 | if (fixP->fx_pcrel) |
7b777690 ILT |
8411 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8412 | "Invalid PC relative reloc"); | |
670a50eb | 8413 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8414 | break; |
3d3c5039 | 8415 | |
cc5703cd ILT |
8416 | case BFD_RELOC_MIPS16_JMP: |
8417 | /* We currently always generate a reloc against a symbol, which | |
8418 | means that we don't want an addend even if the symbol is | |
8419 | defined. */ | |
8420 | fixP->fx_addnumber = 0; | |
8421 | break; | |
8422 | ||
ecd4ca1c ILT |
8423 | case BFD_RELOC_PCREL_HI16_S: |
8424 | /* The addend for this is tricky if it is internal, so we just | |
8425 | do everything here rather than in bfd_perform_relocation. */ | |
8426 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8427 | { | |
8428 | /* For an external symbol adjust by the address to make it | |
8429 | pcrel_offset. We use the address of the RELLO reloc | |
8430 | which follows this one. */ | |
8431 | value += (fixP->fx_next->fx_frag->fr_address | |
8432 | + fixP->fx_next->fx_where); | |
8433 | } | |
8434 | if (value & 0x8000) | |
8435 | value += 0x10000; | |
8436 | value >>= 16; | |
0221ddf7 | 8437 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8438 | if (target_big_endian) |
ecd4ca1c ILT |
8439 | buf += 2; |
8440 | md_number_to_chars (buf, value, 2); | |
8441 | break; | |
8442 | ||
8443 | case BFD_RELOC_PCREL_LO16: | |
8444 | /* The addend for this is tricky if it is internal, so we just | |
8445 | do everything here rather than in bfd_perform_relocation. */ | |
8446 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8447 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8448 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8449 | if (target_big_endian) |
ecd4ca1c ILT |
8450 | buf += 2; |
8451 | md_number_to_chars (buf, value, 2); | |
8452 | break; | |
8453 | ||
bf39474f ILT |
8454 | case BFD_RELOC_64: |
8455 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8456 | extended value if we are only 32 bits. */ | |
8457 | if (fixP->fx_done | |
8458 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8459 | { | |
8460 | if (8 <= sizeof (valueT)) | |
8461 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8462 | value, 8); | |
8463 | else | |
8464 | { | |
8465 | long w1, w2; | |
8466 | long hiv; | |
8467 | ||
8468 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 8469 | if (target_big_endian) |
bf39474f ILT |
8470 | w1 += 4; |
8471 | else | |
8472 | w2 += 4; | |
8473 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8474 | if ((value & 0x80000000) != 0) | |
8475 | hiv = 0xffffffff; | |
8476 | else | |
8477 | hiv = 0; | |
8478 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8479 | } | |
8480 | } | |
8481 | break; | |
8482 | ||
f3645945 ILT |
8483 | case BFD_RELOC_32: |
8484 | /* If we are deleting this reloc entry, we must fill in the | |
8485 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8486 | resolved when it appears but is later defined. We also need |
8487 | to fill in the value if this is an embedded PIC switch table | |
8488 | entry. */ | |
8489 | if (fixP->fx_done | |
8490 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8491 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8492 | value, 4); | |
8493 | break; | |
8494 | ||
49ad0c4c ILT |
8495 | case BFD_RELOC_16: |
8496 | /* If we are deleting this reloc entry, we must fill in the | |
8497 | value now. */ | |
8498 | assert (fixP->fx_size == 2); | |
8499 | if (fixP->fx_done) | |
8500 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8501 | value, 2); | |
8502 | break; | |
8503 | ||
f3645945 ILT |
8504 | case BFD_RELOC_LO16: |
8505 | /* When handling an embedded PIC switch statement, we can wind | |
8506 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8507 | if (fixP->fx_done) | |
8508 | { | |
8509 | if (value < -0x8000 || value > 0x7fff) | |
8510 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8511 | "relocation overflow"); | |
0221ddf7 | 8512 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8513 | if (target_big_endian) |
f3645945 ILT |
8514 | buf += 2; |
8515 | md_number_to_chars (buf, value, 2); | |
8516 | } | |
8517 | break; | |
8518 | ||
3d3c5039 | 8519 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8520 | /* |
8521 | * We need to save the bits in the instruction since fixup_segment() | |
8522 | * might be deleting the relocation entry (i.e., a branch within | |
8523 | * the current segment). | |
8524 | */ | |
fbcfacb7 | 8525 | if ((value & 0x3) != 0) |
3b320c48 ILT |
8526 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8527 | "Branch to odd address (%lx)", value); | |
670a50eb | 8528 | value >>= 2; |
670a50eb ILT |
8529 | |
8530 | /* update old instruction data */ | |
8531 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
8532 | if (target_big_endian) |
8533 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
8534 | else | |
8535 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
8536 | |
8537 | if (value >= -0x8000 && value < 0x8000) | |
8538 | insn |= value & 0xffff; | |
8539 | else | |
8540 | { | |
8541 | /* The branch offset is too large. If this is an | |
8542 | unconditional branch, and we are not generating PIC code, | |
8543 | we can convert it to an absolute jump instruction. */ | |
8544 | if (mips_pic == NO_PIC | |
8545 | && fixP->fx_done | |
8546 | && fixP->fx_frag->fr_address >= text_section->vma | |
8547 | && (fixP->fx_frag->fr_address | |
8548 | < text_section->vma + text_section->_raw_size) | |
8549 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8550 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8551 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8552 | { | |
8553 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8554 | insn = 0x0c000000; /* jal */ | |
8555 | else | |
8556 | insn = 0x08000000; /* j */ | |
8557 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8558 | fixP->fx_done = 0; | |
8559 | fixP->fx_addsy = section_symbol (text_section); | |
8560 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8561 | } | |
8562 | else | |
8563 | { | |
8564 | /* FIXME. It would be possible in principle to handle | |
8565 | conditional branches which overflow. They could be | |
8566 | transformed into a branch around a jump. This would | |
8567 | require setting up variant frags for each different | |
8568 | branch type. The native MIPS assembler attempts to | |
8569 | handle these cases, but it appears to do it | |
8570 | incorrectly. */ | |
8571 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8572 | "Relocation overflow"); | |
8573 | } | |
8574 | } | |
8575 | ||
604633ae | 8576 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8577 | break; |
3d3c5039 ILT |
8578 | |
8579 | default: | |
670a50eb | 8580 | internalError (); |
3d3c5039 | 8581 | } |
5b63f465 | 8582 | |
670a50eb | 8583 | return 1; |
3d3c5039 ILT |
8584 | } |
8585 | ||
8586 | #if 0 | |
8587 | void | |
670a50eb ILT |
8588 | printInsn (oc) |
8589 | unsigned long oc; | |
3d3c5039 | 8590 | { |
670a50eb ILT |
8591 | const struct mips_opcode *p; |
8592 | int treg, sreg, dreg, shamt; | |
8593 | short imm; | |
8594 | const char *args; | |
8595 | int i; | |
3d3c5039 | 8596 | |
670a50eb ILT |
8597 | for (i = 0; i < NUMOPCODES; ++i) |
8598 | { | |
8599 | p = &mips_opcodes[i]; | |
8600 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8601 | { | |
8602 | printf ("%08lx %s\t", oc, p->name); | |
8603 | treg = (oc >> 16) & 0x1f; | |
8604 | sreg = (oc >> 21) & 0x1f; | |
8605 | dreg = (oc >> 11) & 0x1f; | |
8606 | shamt = (oc >> 6) & 0x1f; | |
8607 | imm = oc; | |
8608 | for (args = p->args;; ++args) | |
8609 | { | |
8610 | switch (*args) | |
8611 | { | |
3d3c5039 | 8612 | case '\0': |
670a50eb ILT |
8613 | printf ("\n"); |
8614 | break; | |
3d3c5039 ILT |
8615 | |
8616 | case ',': | |
8617 | case '(': | |
8618 | case ')': | |
670a50eb ILT |
8619 | printf ("%c", *args); |
8620 | continue; | |
3d3c5039 ILT |
8621 | |
8622 | case 'r': | |
670a50eb ILT |
8623 | assert (treg == sreg); |
8624 | printf ("$%d,$%d", treg, sreg); | |
8625 | continue; | |
3d3c5039 ILT |
8626 | |
8627 | case 'd': | |
918692a5 | 8628 | case 'G': |
670a50eb ILT |
8629 | printf ("$%d", dreg); |
8630 | continue; | |
3d3c5039 ILT |
8631 | |
8632 | case 't': | |
918692a5 | 8633 | case 'E': |
670a50eb ILT |
8634 | printf ("$%d", treg); |
8635 | continue; | |
3d3c5039 | 8636 | |
9226253a ILT |
8637 | case 'k': |
8638 | printf ("0x%x", treg); | |
8639 | continue; | |
8640 | ||
3d3c5039 ILT |
8641 | case 'b': |
8642 | case 's': | |
670a50eb ILT |
8643 | printf ("$%d", sreg); |
8644 | continue; | |
3d3c5039 ILT |
8645 | |
8646 | case 'a': | |
670a50eb ILT |
8647 | printf ("0x%08lx", oc & 0x1ffffff); |
8648 | continue; | |
3d3c5039 ILT |
8649 | |
8650 | case 'i': | |
8651 | case 'j': | |
8652 | case 'o': | |
8653 | case 'u': | |
670a50eb ILT |
8654 | printf ("%d", imm); |
8655 | continue; | |
3d3c5039 ILT |
8656 | |
8657 | case '<': | |
56c96faa | 8658 | case '>': |
670a50eb ILT |
8659 | printf ("$%d", shamt); |
8660 | continue; | |
3d3c5039 ILT |
8661 | |
8662 | default: | |
670a50eb | 8663 | internalError (); |
3d3c5039 | 8664 | } |
670a50eb | 8665 | break; |
3d3c5039 | 8666 | } |
670a50eb | 8667 | return; |
3d3c5039 ILT |
8668 | } |
8669 | } | |
670a50eb | 8670 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8671 | } |
8672 | #endif | |
8673 | ||
8674 | static symbolS * | |
8675 | get_symbol () | |
8676 | { | |
670a50eb ILT |
8677 | int c; |
8678 | char *name; | |
8679 | symbolS *p; | |
8680 | ||
8681 | name = input_line_pointer; | |
8682 | c = get_symbol_end (); | |
8683 | p = (symbolS *) symbol_find_or_make (name); | |
8684 | *input_line_pointer = c; | |
8685 | return p; | |
3d3c5039 ILT |
8686 | } |
8687 | ||
becfe05e ILT |
8688 | /* Align the current frag to a given power of two. The MIPS assembler |
8689 | also automatically adjusts any preceding label. */ | |
8690 | ||
8691 | static void | |
23dc1ae3 | 8692 | mips_align (to, fill, label) |
becfe05e ILT |
8693 | int to; |
8694 | int fill; | |
23dc1ae3 | 8695 | symbolS *label; |
becfe05e | 8696 | { |
fbcfacb7 | 8697 | mips_emit_delays (false); |
becfe05e ILT |
8698 | frag_align (to, fill); |
8699 | record_alignment (now_seg, to); | |
23dc1ae3 | 8700 | if (label != NULL) |
becfe05e | 8701 | { |
23dc1ae3 ILT |
8702 | assert (S_GET_SEGMENT (label) == now_seg); |
8703 | label->sy_frag = frag_now; | |
8704 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
8705 | } |
8706 | } | |
8707 | ||
8708 | /* Align to a given power of two. .align 0 turns off the automatic | |
8709 | alignment used by the data creating pseudo-ops. */ | |
8710 | ||
3d3c5039 ILT |
8711 | static void |
8712 | s_align (x) | |
8713 | int x; | |
8714 | { | |
670a50eb ILT |
8715 | register int temp; |
8716 | register long temp_fill; | |
8717 | long max_alignment = 15; | |
3d3c5039 | 8718 | |
670a50eb | 8719 | /* |
3d3c5039 ILT |
8720 | |
8721 | o Note that the assembler pulls down any immediately preceeding label | |
8722 | to the aligned address. | |
8723 | o It's not documented but auto alignment is reinstated by | |
8724 | a .align pseudo instruction. | |
8725 | o Note also that after auto alignment is turned off the mips assembler | |
8726 | issues an error on attempt to assemble an improperly aligned data item. | |
8727 | We don't. | |
8728 | ||
8729 | */ | |
8730 | ||
670a50eb ILT |
8731 | temp = get_absolute_expression (); |
8732 | if (temp > max_alignment) | |
8733 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
8734 | else if (temp < 0) | |
8735 | { | |
8736 | as_warn ("Alignment negative: 0 assumed."); | |
8737 | temp = 0; | |
8738 | } | |
8739 | if (*input_line_pointer == ',') | |
8740 | { | |
8741 | input_line_pointer++; | |
8742 | temp_fill = get_absolute_expression (); | |
8743 | } | |
8744 | else | |
8745 | temp_fill = 0; | |
8746 | if (temp) | |
8747 | { | |
8748 | auto_align = 1; | |
fbcfacb7 ILT |
8749 | mips_align (temp, (int) temp_fill, |
8750 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 8751 | } |
670a50eb ILT |
8752 | else |
8753 | { | |
8754 | auto_align = 0; | |
3d3c5039 ILT |
8755 | } |
8756 | ||
670a50eb | 8757 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8758 | } |
8759 | ||
739708fa KR |
8760 | void |
8761 | mips_flush_pending_output () | |
becfe05e | 8762 | { |
fbcfacb7 ILT |
8763 | mips_emit_delays (false); |
8764 | mips_clear_insn_labels (); | |
becfe05e ILT |
8765 | } |
8766 | ||
3d3c5039 ILT |
8767 | static void |
8768 | s_change_sec (sec) | |
8769 | int sec; | |
8770 | { | |
88225433 | 8771 | segT seg; |
becfe05e | 8772 | |
5b63f465 ILT |
8773 | /* When generating embedded PIC code, we only use the .text, .lit8, |
8774 | .sdata and .sbss sections. We change the .data and .rdata | |
8775 | pseudo-ops to use .sdata. */ | |
8776 | if (mips_pic == EMBEDDED_PIC | |
8777 | && (sec == 'd' || sec == 'r')) | |
8778 | sec = 's'; | |
8779 | ||
fbcfacb7 | 8780 | mips_emit_delays (false); |
670a50eb ILT |
8781 | switch (sec) |
8782 | { | |
3d3c5039 | 8783 | case 't': |
604633ae | 8784 | s_text (0); |
670a50eb | 8785 | break; |
3d3c5039 | 8786 | case 'd': |
604633ae | 8787 | s_data (0); |
670a50eb | 8788 | break; |
3d3c5039 | 8789 | case 'b': |
670a50eb | 8790 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
8791 | demand_empty_rest_of_line (); |
8792 | break; | |
88225433 ILT |
8793 | |
8794 | case 'r': | |
1dc1e798 KR |
8795 | if (USE_GLOBAL_POINTER_OPT) |
8796 | { | |
8797 | seg = subseg_new (RDATA_SECTION_NAME, | |
8798 | (subsegT) get_absolute_expression ()); | |
8799 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8800 | { | |
8801 | bfd_set_section_flags (stdoutput, seg, | |
8802 | (SEC_ALLOC | |
8803 | | SEC_LOAD | |
8804 | | SEC_READONLY | |
8805 | | SEC_RELOC | |
8806 | | SEC_DATA)); | |
08e17202 ILT |
8807 | if (strcmp (TARGET_OS, "elf") != 0) |
8808 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8809 | } |
8810 | demand_empty_rest_of_line (); | |
8811 | } | |
8812 | else | |
8813 | { | |
8814 | as_bad ("No read only data section in this object file format"); | |
8815 | demand_empty_rest_of_line (); | |
8816 | return; | |
8817 | } | |
88225433 | 8818 | break; |
88225433 ILT |
8819 | |
8820 | case 's': | |
1dc1e798 KR |
8821 | if (USE_GLOBAL_POINTER_OPT) |
8822 | { | |
8823 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
8824 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8825 | { | |
8826 | bfd_set_section_flags (stdoutput, seg, | |
8827 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
8828 | | SEC_DATA); | |
08e17202 ILT |
8829 | if (strcmp (TARGET_OS, "elf") != 0) |
8830 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8831 | } |
8832 | demand_empty_rest_of_line (); | |
8833 | break; | |
8834 | } | |
8835 | else | |
8836 | { | |
8837 | as_bad ("Global pointers not supported; recompile -G 0"); | |
8838 | demand_empty_rest_of_line (); | |
8839 | return; | |
8840 | } | |
3d3c5039 | 8841 | } |
88225433 | 8842 | |
670a50eb | 8843 | auto_align = 1; |
3d3c5039 ILT |
8844 | } |
8845 | ||
739708fa KR |
8846 | void |
8847 | mips_enable_auto_align () | |
9da4c5d1 | 8848 | { |
9da4c5d1 ILT |
8849 | auto_align = 1; |
8850 | } | |
8851 | ||
3d3c5039 ILT |
8852 | static void |
8853 | s_cons (log_size) | |
8854 | int log_size; | |
8855 | { | |
23dc1ae3 ILT |
8856 | symbolS *label; |
8857 | ||
fbcfacb7 ILT |
8858 | label = insn_labels != NULL ? insn_labels->label : NULL; |
8859 | mips_emit_delays (false); | |
670a50eb | 8860 | if (log_size > 0 && auto_align) |
23dc1ae3 | 8861 | mips_align (log_size, 0, label); |
fbcfacb7 | 8862 | mips_clear_insn_labels (); |
670a50eb | 8863 | cons (1 << log_size); |
3d3c5039 ILT |
8864 | } |
8865 | ||
3d3c5039 | 8866 | static void |
becfe05e ILT |
8867 | s_float_cons (type) |
8868 | int type; | |
3d3c5039 | 8869 | { |
23dc1ae3 ILT |
8870 | symbolS *label; |
8871 | ||
fbcfacb7 | 8872 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 8873 | |
fbcfacb7 | 8874 | mips_emit_delays (false); |
670a50eb ILT |
8875 | |
8876 | if (auto_align) | |
becfe05e | 8877 | if (type == 'd') |
23dc1ae3 | 8878 | mips_align (3, 0, label); |
670a50eb | 8879 | else |
23dc1ae3 | 8880 | mips_align (2, 0, label); |
670a50eb | 8881 | |
fbcfacb7 | 8882 | mips_clear_insn_labels (); |
1849d646 | 8883 | |
becfe05e | 8884 | float_cons (type); |
3d3c5039 ILT |
8885 | } |
8886 | ||
c1444ec4 ILT |
8887 | /* Handle .globl. We need to override it because on Irix 5 you are |
8888 | permitted to say | |
8889 | .globl foo .text | |
8890 | where foo is an undefined symbol, to mean that foo should be | |
8891 | considered to be the address of a function. */ | |
8892 | ||
8893 | static void | |
8894 | s_mips_globl (x) | |
8895 | int x; | |
8896 | { | |
8897 | char *name; | |
8898 | int c; | |
8899 | symbolS *symbolP; | |
fb251650 | 8900 | flagword flag; |
c1444ec4 ILT |
8901 | |
8902 | name = input_line_pointer; | |
8903 | c = get_symbol_end (); | |
8904 | symbolP = symbol_find_or_make (name); | |
8905 | *input_line_pointer = c; | |
8906 | SKIP_WHITESPACE (); | |
fb251650 ILT |
8907 | |
8908 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
8909 | being a function is apparently labelled as being an object. */ | |
8910 | flag = BSF_OBJECT; | |
8911 | ||
c1444ec4 ILT |
8912 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
8913 | { | |
8914 | char *secname; | |
8915 | asection *sec; | |
8916 | ||
8917 | secname = input_line_pointer; | |
8918 | c = get_symbol_end (); | |
8919 | sec = bfd_get_section_by_name (stdoutput, secname); | |
8920 | if (sec == NULL) | |
8921 | as_bad ("%s: no such section", secname); | |
8922 | *input_line_pointer = c; | |
8923 | ||
8924 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 8925 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
8926 | } |
8927 | ||
fb251650 ILT |
8928 | symbolP->bsym->flags |= flag; |
8929 | ||
c1444ec4 ILT |
8930 | S_SET_EXTERNAL (symbolP); |
8931 | demand_empty_rest_of_line (); | |
8932 | } | |
8933 | ||
3d3c5039 ILT |
8934 | static void |
8935 | s_option (x) | |
8936 | int x; | |
8937 | { | |
dd3f1f76 ILT |
8938 | char *opt; |
8939 | char c; | |
8940 | ||
8941 | opt = input_line_pointer; | |
8942 | c = get_symbol_end (); | |
8943 | ||
dd3f1f76 | 8944 | if (*opt == 'O') |
9226253a ILT |
8945 | { |
8946 | /* FIXME: What does this mean? */ | |
8947 | } | |
dd3f1f76 | 8948 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 8949 | { |
d9aba805 | 8950 | int i; |
42562568 | 8951 | |
d9aba805 ILT |
8952 | i = atoi (opt + 3); |
8953 | if (i == 0) | |
8954 | mips_pic = NO_PIC; | |
8955 | else if (i == 2) | |
8956 | mips_pic = SVR4_PIC; | |
8957 | else | |
8958 | as_bad (".option pic%d not supported", i); | |
8959 | ||
1dc1e798 | 8960 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
8961 | { |
8962 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 8963 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
8964 | g_switch_value = 0; |
8965 | bfd_set_gp_size (stdoutput, 0); | |
8966 | } | |
9226253a | 8967 | } |
dd3f1f76 ILT |
8968 | else |
8969 | as_warn ("Unrecognized option \"%s\"", opt); | |
8970 | ||
8971 | *input_line_pointer = c; | |
670a50eb | 8972 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8973 | } |
8974 | ||
8975 | static void | |
8976 | s_mipsset (x) | |
8977 | int x; | |
8978 | { | |
670a50eb ILT |
8979 | char *name = input_line_pointer, ch; |
8980 | ||
8981 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
8982 | input_line_pointer++; | |
8983 | ch = *input_line_pointer; | |
8984 | *input_line_pointer = '\0'; | |
8985 | ||
8986 | if (strcmp (name, "reorder") == 0) | |
8987 | { | |
4e95866e ILT |
8988 | if (mips_noreorder) |
8989 | { | |
8990 | prev_insn_unreordered = 1; | |
8991 | prev_prev_insn_unreordered = 1; | |
8992 | } | |
670a50eb ILT |
8993 | mips_noreorder = 0; |
8994 | } | |
8995 | else if (strcmp (name, "noreorder") == 0) | |
8996 | { | |
fbcfacb7 | 8997 | mips_emit_delays (true); |
670a50eb | 8998 | mips_noreorder = 1; |
0dd2d296 | 8999 | mips_any_noreorder = 1; |
670a50eb ILT |
9000 | } |
9001 | else if (strcmp (name, "at") == 0) | |
9002 | { | |
9003 | mips_noat = 0; | |
9004 | } | |
9005 | else if (strcmp (name, "noat") == 0) | |
9006 | { | |
9007 | mips_noat = 1; | |
3d3c5039 | 9008 | } |
670a50eb ILT |
9009 | else if (strcmp (name, "macro") == 0) |
9010 | { | |
9011 | mips_warn_about_macros = 0; | |
9012 | } | |
9013 | else if (strcmp (name, "nomacro") == 0) | |
9014 | { | |
9015 | if (mips_noreorder == 0) | |
9016 | as_bad ("`noreorder' must be set before `nomacro'"); | |
9017 | mips_warn_about_macros = 1; | |
9018 | } | |
9019 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
9020 | { | |
9021 | mips_nomove = 0; | |
9022 | } | |
9023 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
9024 | { | |
9025 | mips_nomove = 1; | |
9026 | } | |
9027 | else if (strcmp (name, "bopt") == 0) | |
9028 | { | |
9029 | mips_nobopt = 0; | |
9030 | } | |
9031 | else if (strcmp (name, "nobopt") == 0) | |
9032 | { | |
9033 | mips_nobopt = 1; | |
9034 | } | |
943321c0 ILT |
9035 | else if (strcmp (name, "mips16") == 0 |
9036 | || strcmp (name, "MIPS-16") == 0) | |
9037 | mips16 = 1; | |
9038 | else if (strcmp (name, "nomips16") == 0 | |
9039 | || strcmp (name, "noMIPS-16") == 0) | |
9040 | mips16 = 0; | |
1051c97f ILT |
9041 | else if (strncmp (name, "mips", 4) == 0) |
9042 | { | |
9043 | int isa; | |
9044 | ||
9045 | /* Permit the user to change the ISA on the fly. Needless to | |
9046 | say, misuse can cause serious problems. */ | |
9047 | isa = atoi (name + 4); | |
9048 | if (isa == 0) | |
9049 | mips_isa = file_mips_isa; | |
d8a1c247 | 9050 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
9051 | as_bad ("unknown ISA level"); |
9052 | else | |
9053 | mips_isa = isa; | |
9054 | } | |
cc5703cd ILT |
9055 | else if (strcmp (name, "autoextend") == 0) |
9056 | mips16_autoextend = 1; | |
9057 | else if (strcmp (name, "noautoextend") == 0) | |
9058 | mips16_autoextend = 0; | |
670a50eb ILT |
9059 | else |
9060 | { | |
9061 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
9062 | } | |
9063 | *input_line_pointer = ch; | |
9064 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
9065 | } |
9066 | ||
9226253a ILT |
9067 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
9068 | .option pic2. It means to generate SVR4 PIC calls. */ | |
9069 | ||
9070 | static void | |
9071 | s_abicalls (ignore) | |
9072 | int ignore; | |
9073 | { | |
d9aba805 | 9074 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
9075 | if (USE_GLOBAL_POINTER_OPT) |
9076 | { | |
9077 | if (g_switch_seen && g_switch_value != 0) | |
9078 | as_warn ("-G may not be used with SVR4 PIC code"); | |
9079 | g_switch_value = 0; | |
9080 | } | |
d9aba805 | 9081 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
9082 | demand_empty_rest_of_line (); |
9083 | } | |
9084 | ||
9085 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
9086 | PIC code. It sets the $gp register for the function based on the | |
9087 | function address, which is in the register named in the argument. | |
9088 | This uses a relocation against _gp_disp, which is handled specially | |
9089 | by the linker. The result is: | |
9090 | lui $gp,%hi(_gp_disp) | |
9091 | addiu $gp,$gp,%lo(_gp_disp) | |
9092 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 9093 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
9094 | |
9095 | static void | |
9096 | s_cpload (ignore) | |
9097 | int ignore; | |
9098 | { | |
9099 | expressionS ex; | |
9100 | int icnt = 0; | |
9101 | ||
d9aba805 ILT |
9102 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
9103 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9104 | { |
9105 | s_ignore (0); | |
9106 | return; | |
9107 | } | |
9108 | ||
9109 | /* .cpload should be a in .set noreorder section. */ | |
9110 | if (mips_noreorder == 0) | |
9111 | as_warn (".cpload not in noreorder section"); | |
9112 | ||
9226253a ILT |
9113 | ex.X_op = O_symbol; |
9114 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
9115 | ex.X_op_symbol = NULL; | |
9116 | ex.X_add_number = 0; | |
9117 | ||
fb251650 ILT |
9118 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
9119 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
9120 | ||
0dd2d296 ILT |
9121 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
9122 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
9123 | (int) BFD_RELOC_LO16); |
9124 | ||
0dd2d296 ILT |
9125 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
9126 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
9127 | |
9128 | demand_empty_rest_of_line (); | |
9129 | } | |
9130 | ||
9131 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
9132 | offset from $sp. The offset is remembered, and after making a PIC | |
9133 | call $gp is restored from that location. */ | |
9134 | ||
9135 | static void | |
9136 | s_cprestore (ignore) | |
9137 | int ignore; | |
9138 | { | |
9139 | expressionS ex; | |
9140 | int icnt = 0; | |
9141 | ||
d9aba805 ILT |
9142 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
9143 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9144 | { |
9145 | s_ignore (0); | |
9146 | return; | |
9147 | } | |
9148 | ||
9226253a ILT |
9149 | mips_cprestore_offset = get_absolute_expression (); |
9150 | ||
9151 | ex.X_op = O_constant; | |
9152 | ex.X_add_symbol = NULL; | |
9153 | ex.X_op_symbol = NULL; | |
9154 | ex.X_add_number = mips_cprestore_offset; | |
9155 | ||
0dd2d296 | 9156 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
9157 | mips_isa < 3 ? "sw" : "sd", |
9158 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
9159 | ||
9160 | demand_empty_rest_of_line (); | |
9161 | } | |
9162 | ||
0dd2d296 ILT |
9163 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
9164 | code. It generates a 32 bit GP relative reloc. */ | |
9165 | ||
9166 | static void | |
9167 | s_gpword (ignore) | |
9168 | int ignore; | |
9169 | { | |
23dc1ae3 | 9170 | symbolS *label; |
0dd2d296 ILT |
9171 | expressionS ex; |
9172 | char *p; | |
9173 | ||
9174 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 9175 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9176 | { |
9177 | s_cons (2); | |
9178 | return; | |
9179 | } | |
9180 | ||
fbcfacb7 ILT |
9181 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9182 | mips_emit_delays (true); | |
0dd2d296 | 9183 | if (auto_align) |
23dc1ae3 | 9184 | mips_align (2, 0, label); |
fbcfacb7 | 9185 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9186 | |
9187 | expression (&ex); | |
9188 | ||
9189 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9190 | { | |
9191 | as_bad ("Unsupported use of .gpword"); | |
9192 | ignore_rest_of_line (); | |
9193 | } | |
9194 | ||
9195 | p = frag_more (4); | |
9196 | md_number_to_chars (p, (valueT) 0, 4); | |
9197 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9198 | BFD_RELOC_MIPS_GPREL32); | |
9199 | ||
9200 | demand_empty_rest_of_line (); | |
9201 | } | |
9202 | ||
9203 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9204 | tables in SVR4 PIC code. */ | |
9205 | ||
9206 | static void | |
9207 | s_cpadd (ignore) | |
9208 | int ignore; | |
9209 | { | |
9210 | int icnt = 0; | |
9211 | int reg; | |
9212 | ||
9213 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9214 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9215 | { |
9216 | s_ignore (0); | |
9217 | return; | |
9218 | } | |
9219 | ||
9220 | /* Add $gp to the register named as an argument. */ | |
9221 | reg = tc_get_register (0); | |
9222 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9223 | mips_isa < 3 ? "addu" : "daddu", | |
9224 | "d,v,t", reg, reg, GP); | |
9225 | ||
9226 | demand_empty_rest_of_line (); | |
9227 | } | |
9228 | ||
ed3eb786 ILT |
9229 | /* Handle the .insn pseudo-op. This marks instruction labels in |
9230 | mips16 mode. This permits the linker to handle them specially, | |
9231 | such as generating jalx instructions when needed. We also make | |
9232 | them odd for the duration of the assembly, in order to generate the | |
9233 | right sort of code. We will make them even in the adjust_symtab | |
9234 | routine, while leaving them marked. This is convenient for the | |
9235 | debugger and the disassembler. The linker knows to make them odd | |
9236 | again. */ | |
9237 | ||
9238 | static void | |
9239 | s_insn (ignore) | |
9240 | int ignore; | |
9241 | { | |
9242 | if (mips16) | |
9243 | { | |
9244 | struct insn_label_list *l; | |
9245 | ||
9246 | for (l = insn_labels; l != NULL; l = l->next) | |
9247 | { | |
9248 | #ifdef S_SET_OTHER | |
9249 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9250 | S_SET_OTHER (l->label, STO_MIPS16); | |
9251 | #endif | |
9252 | ++l->label->sy_value.X_add_number; | |
9253 | } | |
9254 | ||
9255 | mips_clear_insn_labels (); | |
9256 | } | |
9257 | ||
9258 | demand_empty_rest_of_line (); | |
9259 | } | |
9260 | ||
9226253a | 9261 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9262 | to parse .frame. The argument is non-zero if this is the frame |
9263 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9264 | |
3d3c5039 | 9265 | int |
0dd2d296 ILT |
9266 | tc_get_register (frame) |
9267 | int frame; | |
3d3c5039 ILT |
9268 | { |
9269 | int reg; | |
9270 | ||
9271 | SKIP_WHITESPACE (); | |
9272 | if (*input_line_pointer++ != '$') | |
9273 | { | |
9274 | as_warn ("expected `$'"); | |
0dd2d296 | 9275 | reg = 0; |
3d3c5039 | 9276 | } |
0dd2d296 | 9277 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9278 | { |
9279 | reg = get_absolute_expression (); | |
9280 | if (reg < 0 || reg >= 32) | |
9281 | { | |
9282 | as_warn ("Bad register number"); | |
9283 | reg = 0; | |
9284 | } | |
9285 | } | |
9286 | else | |
9287 | { | |
9288 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9289 | reg = FP; |
3d3c5039 | 9290 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9291 | reg = SP; |
3d3c5039 | 9292 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9293 | reg = GP; |
3d3c5039 | 9294 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9295 | reg = AT; |
3d3c5039 ILT |
9296 | else |
9297 | { | |
9298 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9299 | reg = 0; |
3d3c5039 ILT |
9300 | } |
9301 | input_line_pointer += 2; | |
9302 | } | |
0dd2d296 ILT |
9303 | if (frame) |
9304 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9305 | return reg; |
9306 | } | |
9307 | ||
0dd2d296 ILT |
9308 | valueT |
9309 | md_section_align (seg, addr) | |
9310 | asection *seg; | |
9311 | valueT addr; | |
9312 | { | |
9313 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9314 | ||
cf32394d ILT |
9315 | #ifdef OBJ_ELF |
9316 | /* We don't need to align ELF sections to the full alignment. | |
9317 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9318 | byte boundary. We don't bother to align the sections if we are |
9319 | targeted for an embedded system. */ | |
9320 | if (strcmp (TARGET_OS, "elf") == 0) | |
9321 | return addr; | |
943321c0 ILT |
9322 | if (align > 4) |
9323 | align = 4; | |
10a14e36 | 9324 | #endif |
cf32394d ILT |
9325 | |
9326 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9327 | } |
9328 | ||
d8a1c247 KR |
9329 | /* Utility routine, called from above as well. If called while the |
9330 | input file is still being read, it's only an approximation. (For | |
9331 | example, a symbol may later become defined which appeared to be | |
9332 | undefined earlier.) */ | |
22ba90ce ILT |
9333 | |
9334 | static int | |
9335 | nopic_need_relax (sym) | |
d8a1c247 KR |
9336 | symbolS *sym; |
9337 | { | |
9338 | if (sym == 0) | |
9339 | return 0; | |
9340 | ||
1dc1e798 KR |
9341 | if (USE_GLOBAL_POINTER_OPT) |
9342 | { | |
9343 | const char *symname; | |
9344 | int change; | |
9345 | ||
9346 | /* Find out whether this symbol can be referenced off the GP | |
9347 | register. It can be if it is smaller than the -G size or if | |
9348 | it is in the .sdata or .sbss section. Certain symbols can | |
9349 | not be referenced off the GP, although it appears as though | |
9350 | they can. */ | |
9351 | symname = S_GET_NAME (sym); | |
9352 | if (symname != (const char *) NULL | |
9353 | && (strcmp (symname, "eprol") == 0 | |
9354 | || strcmp (symname, "etext") == 0 | |
9355 | || strcmp (symname, "_gp") == 0 | |
9356 | || strcmp (symname, "edata") == 0 | |
9357 | || strcmp (symname, "_fbss") == 0 | |
9358 | || strcmp (symname, "_fdata") == 0 | |
9359 | || strcmp (symname, "_ftext") == 0 | |
9360 | || strcmp (symname, "end") == 0 | |
9361 | || strcmp (symname, "_gp_disp") == 0)) | |
9362 | change = 1; | |
9363 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
9364 | && (0 |
9365 | #ifndef NO_ECOFF_DEBUGGING | |
9366 | || (sym->ecoff_extern_size != 0 | |
9367 | && sym->ecoff_extern_size <= g_switch_value) | |
9368 | #endif | |
1dc1e798 KR |
9369 | || (S_GET_VALUE (sym) != 0 |
9370 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9371 | change = 0; | |
9372 | else | |
9373 | { | |
9374 | const char *segname; | |
d8a1c247 | 9375 | |
1dc1e798 KR |
9376 | segname = segment_name (S_GET_SEGMENT (sym)); |
9377 | assert (strcmp (segname, ".lit8") != 0 | |
9378 | && strcmp (segname, ".lit4") != 0); | |
9379 | change = (strcmp (segname, ".sdata") != 0 | |
9380 | && strcmp (segname, ".sbss") != 0); | |
9381 | } | |
9382 | return change; | |
9383 | } | |
9384 | else | |
9385 | /* We are not optimizing for the GP register. */ | |
9386 | return 1; | |
d8a1c247 KR |
9387 | } |
9388 | ||
cc5703cd ILT |
9389 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
9390 | extended opcode. SEC is the section the frag is in. */ | |
9391 | ||
9392 | static int | |
9393 | mips16_extended_frag (fragp, sec, stretch) | |
9394 | fragS *fragp; | |
9395 | asection *sec; | |
9396 | long stretch; | |
9397 | { | |
9398 | int type; | |
9399 | register const struct mips16_immed_operand *op; | |
9400 | offsetT val; | |
9401 | int mintiny, maxtiny; | |
f74ba7a3 | 9402 | segT symsec; |
cc5703cd | 9403 | |
8728fa92 ILT |
9404 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
9405 | return 0; | |
9406 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
9407 | return 1; | |
9408 | ||
cc5703cd ILT |
9409 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
9410 | op = mips16_immed_operands; | |
9411 | while (op->type != type) | |
9412 | { | |
9413 | ++op; | |
9414 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9415 | } | |
9416 | ||
9417 | if (op->unsp) | |
9418 | { | |
9419 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9420 | { | |
9421 | mintiny = 1; | |
9422 | maxtiny = 1 << op->nbits; | |
9423 | } | |
9424 | else | |
9425 | { | |
9426 | mintiny = 0; | |
9427 | maxtiny = (1 << op->nbits) - 1; | |
9428 | } | |
9429 | } | |
9430 | else | |
9431 | { | |
9432 | mintiny = - (1 << (op->nbits - 1)); | |
9433 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9434 | } | |
9435 | ||
f74ba7a3 ILT |
9436 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
9437 | a particular frag address. */ | |
9438 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
9439 | { | |
9440 | val = (fragp->fr_symbol->sy_value.X_add_number | |
9441 | + fragp->fr_symbol->sy_frag->fr_address); | |
9442 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
9443 | } | |
9444 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
9445 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
9446 | == O_constant)) | |
9447 | { | |
9448 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
9449 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
9450 | + fragp->fr_symbol->sy_value.X_add_number | |
9451 | + fragp->fr_symbol->sy_frag->fr_address); | |
9452 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
9453 | } | |
9454 | else | |
9455 | return 1; | |
cc5703cd ILT |
9456 | |
9457 | if (op->pcrel) | |
9458 | { | |
9459 | addressT addr; | |
9460 | ||
9461 | /* We won't have the section when we are called from | |
9462 | mips_relax_frag. However, we will always have been called | |
9463 | from md_estimate_size_before_relax first. If this is a | |
9464 | branch to a different section, we mark it as such. If SEC is | |
9465 | NULL, and the frag is not marked, then it must be a branch to | |
9466 | the same section. */ | |
9467 | if (sec == NULL) | |
9468 | { | |
9469 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9470 | return 1; | |
9471 | } | |
9472 | else | |
9473 | { | |
f74ba7a3 | 9474 | if (symsec != sec) |
cc5703cd ILT |
9475 | { |
9476 | fragp->fr_subtype = | |
9477 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9478 | ||
9479 | /* FIXME: We should support this, and let the linker | |
9480 | catch branches and loads that are out of range. */ | |
9481 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9482 | "unsupported PC relative reference to different section"); | |
9483 | ||
9484 | return 1; | |
9485 | } | |
9486 | } | |
9487 | ||
9488 | /* In this case, we know for sure that the symbol fragment is in | |
9489 | the same section. If the fr_address of the symbol fragment | |
9490 | is greater then the address of this fragment we want to add | |
9491 | in STRETCH in order to get a better estimate of the address. | |
9492 | This particularly matters because of the shift bits. */ | |
9493 | if (stretch != 0 | |
9494 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9495 | { | |
9496 | fragS *f; | |
9497 | ||
9498 | /* Adjust stretch for any alignment frag. */ | |
9499 | for (f = fragp; f != fragp->fr_symbol->sy_frag; f = f->fr_next) | |
9500 | { | |
9501 | assert (f != NULL); | |
9502 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
9503 | { | |
9504 | if (stretch < 0) | |
9505 | stretch = - ((- stretch) | |
9506 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9507 | else | |
9508 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9509 | if (stretch == 0) | |
9510 | break; | |
9511 | } | |
9512 | } | |
9513 | val += stretch; | |
9514 | } | |
9515 | ||
a677feeb ILT |
9516 | addr = fragp->fr_address + fragp->fr_fix; |
9517 | ||
9518 | /* The base address rules are complicated. The base address of | |
9519 | a branch is the following instruction. The base address of a | |
9520 | PC relative load or add is the instruction itself, but if it | |
9521 | is extended add 2, and if it is in a delay slot (in which | |
9522 | case it can not be extended) use the address of the | |
9523 | instruction whose delay slot it is in. */ | |
9524 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9525 | { |
9526 | addr += 2; | |
9527 | /* Ignore the low bit in the target, since it will be set | |
9528 | for a text label. */ | |
9529 | if ((val & 1) != 0) | |
9530 | --val; | |
9531 | } | |
a677feeb ILT |
9532 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9533 | addr -= 4; | |
9534 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9535 | addr -= 2; | |
cc5703cd ILT |
9536 | |
9537 | /* If we are currently assuming that this frag should be | |
9538 | extended, then the current address is two bytes higher. */ | |
9539 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9540 | addr += 2; | |
9541 | ||
9542 | val -= addr & ~ ((1 << op->shift) - 1); | |
9543 | ||
9544 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9545 | if (type == 'p' || type == 'q') | |
9546 | val /= 2; | |
9547 | ||
9548 | /* If any of the shifted bits are set, we must use an extended | |
9549 | opcode. If the address depends on the size of this | |
9550 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
9551 | use an extended opcode. We only check this when we are in |
9552 | the main relaxation loop, when SEC is NULL. */ | |
9553 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
9554 | { | |
9555 | fragp->fr_subtype = | |
9556 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9557 | return 1; | |
9558 | } | |
9559 | ||
9560 | /* If we are about to mark a frag as extended because the value | |
9561 | is precisely maxtiny + 1, then there is a chance of an | |
9562 | infinite loop as in the following code: | |
9563 | la $4,foo | |
9564 | .skip 1020 | |
9565 | .align 2 | |
9566 | foo: | |
9567 | In this case when the la is extended, foo is 0x3fc bytes | |
9568 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
9569 | the la must be extended. To avoid this loop, we mark the | |
9570 | frag as extended if it was small, and is about to become | |
9571 | extended with a value of maxtiny + 1. */ | |
9572 | if (val == ((maxtiny + 1) << op->shift) | |
9573 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
9574 | && sec == NULL) | |
cc5703cd ILT |
9575 | { |
9576 | fragp->fr_subtype = | |
9577 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9578 | return 1; | |
9579 | } | |
9580 | } | |
41a0ed22 ILT |
9581 | else if (symsec != absolute_section && sec != NULL) |
9582 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
9583 | |
9584 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9585 | || val < (mintiny << op->shift) | |
9586 | || val > (maxtiny << op->shift)) | |
9587 | return 1; | |
9588 | else | |
9589 | return 0; | |
9590 | } | |
9591 | ||
9592 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9593 | mips16, we are not really relaxing here, and the final size is | |
9594 | encoded in the subtype information. For the mips16, we have to | |
9595 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9596 | |
0dd2d296 ILT |
9597 | /*ARGSUSED*/ |
9598 | int | |
9599 | md_estimate_size_before_relax (fragp, segtype) | |
9600 | fragS *fragp; | |
9601 | asection *segtype; | |
9602 | { | |
9603 | int change; | |
9604 | ||
cc5703cd ILT |
9605 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9606 | { | |
9607 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9608 | { | |
9609 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9610 | return 4; | |
9611 | } | |
9612 | else | |
9613 | { | |
9614 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9615 | return 2; | |
9616 | } | |
9617 | } | |
9618 | ||
d9aba805 | 9619 | if (mips_pic == NO_PIC) |
0dd2d296 | 9620 | { |
d8a1c247 | 9621 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9622 | } |
d9aba805 | 9623 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
9624 | { |
9625 | asection *symsec = fragp->fr_symbol->bsym->section; | |
9626 | ||
9627 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9628 | change = (symsec != &bfd_und_section | |
9629 | && symsec != &bfd_abs_section | |
9630 | && ! bfd_is_com_section (symsec)); | |
9631 | } | |
d9aba805 ILT |
9632 | else |
9633 | abort (); | |
0dd2d296 ILT |
9634 | |
9635 | if (change) | |
9636 | { | |
9637 | /* Record the offset to the first reloc in the fr_opcode field. | |
9638 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9639 | must be expanded. */ | |
9640 | fragp->fr_opcode = (fragp->fr_literal | |
9641 | + fragp->fr_fix | |
9642 | - RELAX_OLD (fragp->fr_subtype) | |
9643 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9644 | /* FIXME: This really needs as_warn_where. */ | |
9645 | if (RELAX_WARN (fragp->fr_subtype)) | |
9646 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9647 | } | |
9648 | ||
9649 | if (! change) | |
9650 | return 0; | |
9651 | else | |
9652 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9653 | } | |
9654 | ||
0d7f9025 ILT |
9655 | /* This is called to see whether a reloc against a defined symbol |
9656 | should be converted into a reloc against a section. Don't adjust | |
9657 | MIPS16 jump relocations, so we don't have to worry about the format | |
9658 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
9659 | mips16 symbols, so that the linker can find them if it needs to set |
9660 | up a stub. */ | |
0d7f9025 ILT |
9661 | |
9662 | int | |
9663 | mips_fix_adjustable (fixp) | |
9664 | fixS *fixp; | |
9665 | { | |
9666 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
9667 | return 0; | |
9668 | if (fixp->fx_addsy == NULL) | |
9669 | return 1; | |
0d7f9025 ILT |
9670 | #ifdef S_GET_OTHER |
9671 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9672 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16) | |
9673 | return 0; | |
9674 | #endif | |
9675 | return 1; | |
9676 | } | |
9677 | ||
0dd2d296 ILT |
9678 | /* Translate internal representation of relocation info to BFD target |
9679 | format. */ | |
9680 | ||
9681 | arelent ** | |
3d3c5039 ILT |
9682 | tc_gen_reloc (section, fixp) |
9683 | asection *section; | |
9684 | fixS *fixp; | |
9685 | { | |
0dd2d296 | 9686 | static arelent *retval[4]; |
3d3c5039 | 9687 | arelent *reloc; |
a8aed9dd | 9688 | bfd_reloc_code_real_type code; |
3d3c5039 | 9689 | |
0dd2d296 ILT |
9690 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
9691 | retval[1] = NULL; | |
3d3c5039 ILT |
9692 | |
9693 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9694 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
9695 | |
9696 | if (mips_pic == EMBEDDED_PIC | |
9697 | && SWITCH_TABLE (fixp)) | |
9698 | { | |
9699 | /* For a switch table entry we use a special reloc. The addend | |
9700 | is actually the difference between the reloc address and the | |
9701 | subtrahend. */ | |
9702 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
9703 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
9704 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
9705 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
9706 | } | |
ecd4ca1c ILT |
9707 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
9708 | { | |
9709 | /* We use a special addend for an internal RELLO reloc. */ | |
9710 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9711 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
9712 | else | |
9713 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
9714 | } | |
9715 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
9716 | { | |
9717 | assert (fixp->fx_next != NULL | |
9718 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
9719 | /* We use a special addend for an internal RELHI reloc. The | |
9720 | reloc is relative to the RELLO; adjust the addend | |
9721 | accordingly. */ | |
9722 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9723 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
9724 | + fixp->fx_next->fx_where | |
9725 | - S_GET_VALUE (fixp->fx_subsy)); | |
9726 | else | |
9727 | reloc->addend = (fixp->fx_addnumber | |
9728 | + fixp->fx_next->fx_frag->fr_address | |
9729 | + fixp->fx_next->fx_where); | |
9730 | } | |
1c803e52 | 9731 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
9732 | reloc->addend = fixp->fx_addnumber; |
9733 | else | |
5b63f465 | 9734 | { |
1dc1e798 KR |
9735 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
9736 | /* A gruesome hack which is a result of the gruesome gas reloc | |
9737 | handling. */ | |
9738 | reloc->addend = reloc->address; | |
9739 | else | |
9740 | reloc->addend = -reloc->address; | |
5b63f465 | 9741 | } |
0dd2d296 ILT |
9742 | |
9743 | /* If this is a variant frag, we may need to adjust the existing | |
9744 | reloc and generate a new one. */ | |
9745 | if (fixp->fx_frag->fr_opcode != NULL | |
9746 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
9747 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
9748 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
9749 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9750 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
9751 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9752 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
9753 | { |
9754 | arelent *reloc2; | |
9755 | ||
cc5703cd ILT |
9756 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
9757 | ||
0dd2d296 | 9758 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
9759 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
9760 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
9761 | the second one handle all of them. */ | |
0dd2d296 ILT |
9762 | if (fixp->fx_next != NULL |
9763 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
9764 | { | |
fb251650 ILT |
9765 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
9766 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
9767 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9768 | && (fixp->fx_next->fx_r_type | |
9769 | == BFD_RELOC_MIPS_GOT_LO16)) | |
9770 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9771 | && (fixp->fx_next->fx_r_type | |
9772 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
9773 | retval[0] = NULL; |
9774 | return retval; | |
9775 | } | |
9776 | ||
9777 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
9778 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
9779 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
9780 | retval[2] = NULL; | |
9781 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9782 | reloc2->address = (reloc->address | |
9783 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
9784 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
9785 | reloc2->addend = fixp->fx_addnumber; | |
9786 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
9787 | assert (reloc2->howto != NULL); | |
9788 | ||
9789 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
9790 | { | |
9791 | arelent *reloc3; | |
9792 | ||
9793 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
9794 | retval[3] = NULL; | |
9795 | *reloc3 = *reloc2; | |
9796 | reloc3->address += 4; | |
9797 | } | |
9798 | ||
d9aba805 | 9799 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
9800 | { |
9801 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
9802 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
9803 | } | |
d9aba805 | 9804 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 9805 | { |
fb251650 | 9806 | switch (fixp->fx_r_type) |
0dd2d296 | 9807 | { |
fb251650 ILT |
9808 | default: |
9809 | abort (); | |
9810 | case BFD_RELOC_MIPS_GOT16: | |
9811 | break; | |
9812 | case BFD_RELOC_MIPS_CALL16: | |
9813 | case BFD_RELOC_MIPS_GOT_LO16: | |
9814 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 9815 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 9816 | break; |
0dd2d296 ILT |
9817 | } |
9818 | } | |
d9aba805 ILT |
9819 | else |
9820 | abort (); | |
0dd2d296 ILT |
9821 | } |
9822 | ||
a8aed9dd ILT |
9823 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
9824 | fixup_segment converted a non-PC relative reloc into a PC | |
9825 | relative reloc. In such a case, we need to convert the reloc | |
9826 | code. */ | |
9827 | code = fixp->fx_r_type; | |
9828 | if (fixp->fx_pcrel) | |
9829 | { | |
9830 | switch (code) | |
9831 | { | |
9832 | case BFD_RELOC_8: | |
9833 | code = BFD_RELOC_8_PCREL; | |
9834 | break; | |
9835 | case BFD_RELOC_16: | |
9836 | code = BFD_RELOC_16_PCREL; | |
9837 | break; | |
9838 | case BFD_RELOC_32: | |
9839 | code = BFD_RELOC_32_PCREL; | |
9840 | break; | |
bf39474f ILT |
9841 | case BFD_RELOC_64: |
9842 | code = BFD_RELOC_64_PCREL; | |
9843 | break; | |
a8aed9dd ILT |
9844 | case BFD_RELOC_8_PCREL: |
9845 | case BFD_RELOC_16_PCREL: | |
9846 | case BFD_RELOC_32_PCREL: | |
bf39474f | 9847 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 9848 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
9849 | case BFD_RELOC_PCREL_HI16_S: |
9850 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
9851 | break; |
9852 | default: | |
9853 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9854 | "Cannot make %s relocation PC relative", | |
9855 | bfd_get_reloc_code_name (code)); | |
9856 | } | |
9857 | } | |
9858 | ||
d9aba805 ILT |
9859 | /* To support a PC relative reloc when generating embedded PIC code |
9860 | for ECOFF, we use a Cygnus extension. We check for that here to | |
9861 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 9862 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 9863 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
9864 | && mips_pic != EMBEDDED_PIC) |
9865 | reloc->howto = NULL; | |
9866 | else | |
a8aed9dd | 9867 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 9868 | |
52aa70b5 JW |
9869 | if (reloc->howto == NULL) |
9870 | { | |
9871 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
9872 | "Can not represent %s relocation in this object file format", |
9873 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 9874 | retval[0] = NULL; |
52aa70b5 | 9875 | } |
3d3c5039 | 9876 | |
0dd2d296 | 9877 | return retval; |
3d3c5039 ILT |
9878 | } |
9879 | ||
cc5703cd ILT |
9880 | /* Relax a machine dependent frag. This returns the amount by which |
9881 | the current size of the frag should change. */ | |
9882 | ||
9883 | int | |
9884 | mips_relax_frag (fragp, stretch) | |
9885 | fragS *fragp; | |
9886 | long stretch; | |
9887 | { | |
9888 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
9889 | return 0; | |
9890 | ||
9891 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
9892 | { | |
9893 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9894 | return 0; | |
9895 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9896 | return 2; | |
9897 | } | |
9898 | else | |
9899 | { | |
9900 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9901 | return 0; | |
9902 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9903 | return -2; | |
9904 | } | |
9905 | ||
9906 | return 0; | |
9907 | } | |
9908 | ||
0dd2d296 ILT |
9909 | /* Convert a machine dependent frag. */ |
9910 | ||
9911 | void | |
9912 | md_convert_frag (abfd, asec, fragp) | |
9913 | bfd *abfd; | |
9914 | segT asec; | |
9915 | fragS *fragp; | |
3d3c5039 | 9916 | { |
0dd2d296 ILT |
9917 | int old, new; |
9918 | char *fixptr; | |
3d3c5039 | 9919 | |
cc5703cd ILT |
9920 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9921 | { | |
9922 | int type; | |
9923 | register const struct mips16_immed_operand *op; | |
9924 | boolean small, ext; | |
9925 | offsetT val; | |
9926 | bfd_byte *buf; | |
9927 | unsigned long insn; | |
9928 | boolean use_extend; | |
9929 | unsigned short extend; | |
9930 | ||
9931 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
9932 | op = mips16_immed_operands; | |
9933 | while (op->type != type) | |
9934 | ++op; | |
9935 | ||
9936 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9937 | { | |
9938 | small = false; | |
9939 | ext = true; | |
9940 | } | |
9941 | else | |
9942 | { | |
9943 | small = true; | |
9944 | ext = false; | |
9945 | } | |
9946 | ||
f74ba7a3 | 9947 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 9948 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
9949 | if (op->pcrel) |
9950 | { | |
9951 | addressT addr; | |
9952 | ||
a677feeb ILT |
9953 | addr = fragp->fr_address + fragp->fr_fix; |
9954 | ||
9955 | /* The rules for the base address of a PC relative reloc are | |
9956 | complicated; see mips16_extended_frag. */ | |
9957 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9958 | { |
9959 | addr += 2; | |
9960 | /* Ignore the low bit in the target, since it will be | |
9961 | set for a text label. */ | |
9962 | if ((val & 1) != 0) | |
9963 | --val; | |
9964 | } | |
a677feeb ILT |
9965 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9966 | addr -= 4; | |
9967 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9968 | addr -= 2; | |
9969 | ||
cc5703cd ILT |
9970 | if (ext) |
9971 | addr += 2; | |
9972 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
9973 | val -= addr; | |
a677feeb ILT |
9974 | |
9975 | /* Make sure the section winds up with the alignment we have | |
9976 | assumed. */ | |
9977 | if (op->shift > 0) | |
9978 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
9979 | } |
9980 | ||
035936da ILT |
9981 | if (ext |
9982 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
9983 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
9984 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
9985 | "extended instruction in delay slot"); | |
9986 | ||
cc5703cd ILT |
9987 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
9988 | ||
b9129c6f ILT |
9989 | if (target_big_endian) |
9990 | insn = bfd_getb16 (buf); | |
9991 | else | |
9992 | insn = bfd_getl16 (buf); | |
cc5703cd | 9993 | |
31a2c6ff ILT |
9994 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
9995 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
9996 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
9997 | |
9998 | if (use_extend) | |
9999 | { | |
10000 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
10001 | fragp->fr_fix += 2; | |
10002 | buf += 2; | |
10003 | } | |
3d3c5039 | 10004 | |
cc5703cd ILT |
10005 | md_number_to_chars (buf, insn, 2); |
10006 | fragp->fr_fix += 2; | |
10007 | buf += 2; | |
10008 | } | |
10009 | else | |
10010 | { | |
10011 | if (fragp->fr_opcode == NULL) | |
10012 | return; | |
0dd2d296 | 10013 | |
cc5703cd ILT |
10014 | old = RELAX_OLD (fragp->fr_subtype); |
10015 | new = RELAX_NEW (fragp->fr_subtype); | |
10016 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 10017 | |
cc5703cd ILT |
10018 | if (new > 0) |
10019 | memcpy (fixptr - old, fixptr, new); | |
10020 | ||
10021 | fragp->fr_fix += new - old; | |
10022 | } | |
0dd2d296 | 10023 | } |
becfe05e | 10024 | |
fbcfacb7 ILT |
10025 | #ifdef OBJ_ELF |
10026 | ||
10027 | /* This function is called after the relocs have been generated. | |
10028 | We've been storing mips16 text labels as odd. Here we convert them | |
10029 | back to even for the convenience of the debugger. */ | |
10030 | ||
10031 | void | |
10032 | mips_frob_file_after_relocs () | |
10033 | { | |
10034 | asymbol **syms; | |
10035 | unsigned int count, i; | |
10036 | ||
10037 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10038 | return; | |
10039 | ||
10040 | syms = bfd_get_outsymbols (stdoutput); | |
10041 | count = bfd_get_symcount (stdoutput); | |
10042 | for (i = 0; i < count; i++, syms++) | |
10043 | { | |
10044 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
10045 | && ((*syms)->value & 1) != 0) | |
10046 | { | |
10047 | (*syms)->value &= ~1; | |
10048 | /* If the symbol has an odd size, it was probably computed | |
10049 | incorrectly, so adjust that as well. */ | |
10050 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
10051 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
10052 | } | |
10053 | } | |
10054 | } | |
10055 | ||
10056 | #endif | |
10057 | ||
becfe05e ILT |
10058 | /* This function is called whenever a label is defined. It is used |
10059 | when handling branch delays; if a branch has a label, we assume we | |
10060 | can not move it. */ | |
10061 | ||
10062 | void | |
10063 | mips_define_label (sym) | |
10064 | symbolS *sym; | |
10065 | { | |
fbcfacb7 ILT |
10066 | struct insn_label_list *l; |
10067 | ||
10068 | if (free_insn_labels == NULL) | |
10069 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
10070 | else | |
10071 | { | |
10072 | l = free_insn_labels; | |
10073 | free_insn_labels = l->next; | |
10074 | } | |
10075 | ||
10076 | l->label = sym; | |
10077 | l->next = insn_labels; | |
10078 | insn_labels = l; | |
becfe05e | 10079 | } |
22ba90ce ILT |
10080 | |
10081 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
10082 | In order to work with gcc when using mips-tfile, we must keep all | |
10083 | local labels. However, in other cases, we want to discard them, | |
10084 | since they are useless. */ | |
10085 | ||
10086 | int | |
10087 | mips_local_label (name) | |
10088 | const char *name; | |
10089 | { | |
c625fc23 | 10090 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
10091 | if (ECOFF_DEBUGGING |
10092 | && mips_debug != 0 | |
10093 | && ! ecoff_debugging_seen) | |
10094 | { | |
10095 | /* We were called with -g, but we didn't see any debugging | |
10096 | information. That may mean that gcc is smuggling debugging | |
10097 | information through to mips-tfile, in which case we must | |
10098 | generate all local labels. */ | |
10099 | return 0; | |
10100 | } | |
c625fc23 | 10101 | #endif |
22ba90ce ILT |
10102 | |
10103 | /* Here it's OK to discard local labels. */ | |
10104 | ||
3af584b4 | 10105 | return name[0] == '$'; |
22ba90ce | 10106 | } |
3d3c5039 | 10107 | \f |
739708fa | 10108 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 10109 | |
0dd2d296 | 10110 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
10111 | |
10112 | void | |
10113 | mips_elf_final_processing () | |
10114 | { | |
87178180 ILT |
10115 | /* Write out the register information. */ |
10116 | if (! mips_64) | |
10117 | { | |
10118 | Elf32_RegInfo s; | |
10119 | ||
10120 | s.ri_gprmask = mips_gprmask; | |
10121 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10122 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10123 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10124 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10125 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10126 | ||
10127 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
10128 | ((Elf32_External_RegInfo *) | |
10129 | mips_regmask_frag)); | |
10130 | } | |
10131 | else | |
10132 | { | |
10133 | Elf64_Internal_RegInfo s; | |
10134 | ||
10135 | s.ri_gprmask = mips_gprmask; | |
10136 | s.ri_pad = 0; | |
10137 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10138 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10139 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10140 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10141 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10142 | ||
10143 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
10144 | ((Elf64_External_RegInfo *) | |
10145 | mips_regmask_frag)); | |
10146 | } | |
0dd2d296 ILT |
10147 | |
10148 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
10149 | sort of BFD interface for this. */ | |
10150 | if (mips_any_noreorder) | |
10151 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 10152 | if (mips_pic != NO_PIC) |
0dd2d296 | 10153 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
10154 | } |
10155 | ||
739708fa | 10156 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 10157 | \f |
3d3c5039 ILT |
10158 | /* These functions should really be defined by the object file format, |
10159 | since they are related to debugging information. However, this | |
10160 | code has to work for the a.out format, which does not define them, | |
10161 | so we provide simple versions here. These don't actually generate | |
10162 | any debugging information, but they do simple checking and someday | |
10163 | somebody may make them useful. */ | |
10164 | ||
670a50eb ILT |
10165 | typedef struct loc |
10166 | { | |
10167 | struct loc *loc_next; | |
10168 | unsigned long loc_fileno; | |
10169 | unsigned long loc_lineno; | |
10170 | unsigned long loc_offset; | |
10171 | unsigned short loc_delta; | |
10172 | unsigned short loc_count; | |
3d3c5039 | 10173 | #if 0 |
670a50eb | 10174 | fragS *loc_frag; |
3d3c5039 | 10175 | #endif |
670a50eb ILT |
10176 | } |
10177 | locS; | |
3d3c5039 | 10178 | |
670a50eb ILT |
10179 | typedef struct proc |
10180 | { | |
3d3c5039 ILT |
10181 | struct proc *proc_next; |
10182 | struct symbol *proc_isym; | |
10183 | struct symbol *proc_end; | |
10184 | unsigned long proc_reg_mask; | |
10185 | unsigned long proc_reg_offset; | |
10186 | unsigned long proc_fpreg_mask; | |
10187 | unsigned long proc_fpreg_offset; | |
10188 | unsigned long proc_frameoffset; | |
10189 | unsigned long proc_framereg; | |
10190 | unsigned long proc_pcreg; | |
10191 | locS *proc_iline; | |
10192 | struct file *proc_file; | |
10193 | int proc_index; | |
670a50eb ILT |
10194 | } |
10195 | procS; | |
3d3c5039 | 10196 | |
670a50eb ILT |
10197 | typedef struct file |
10198 | { | |
3d3c5039 ILT |
10199 | struct file *file_next; |
10200 | unsigned long file_fileno; | |
10201 | struct symbol *file_symbol; | |
10202 | struct symbol *file_end; | |
10203 | struct proc *file_proc; | |
10204 | int file_numprocs; | |
670a50eb ILT |
10205 | } |
10206 | fileS; | |
3d3c5039 ILT |
10207 | |
10208 | static struct obstack proc_frags; | |
10209 | static procS *proc_lastP; | |
10210 | static procS *proc_rootP; | |
10211 | static int numprocs; | |
10212 | ||
10213 | static void | |
10214 | md_obj_begin () | |
10215 | { | |
670a50eb | 10216 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
10217 | } |
10218 | ||
10219 | static void | |
10220 | md_obj_end () | |
10221 | { | |
10222 | /* check for premature end, nesting errors, etc */ | |
10223 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 10224 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
10225 | } |
10226 | ||
3d3c5039 ILT |
10227 | static long |
10228 | get_number () | |
10229 | { | |
670a50eb ILT |
10230 | int negative = 0; |
10231 | long val = 0; | |
3d3c5039 | 10232 | |
670a50eb ILT |
10233 | if (*input_line_pointer == '-') |
10234 | { | |
10235 | ++input_line_pointer; | |
10236 | negative = 1; | |
3d3c5039 | 10237 | } |
670a50eb ILT |
10238 | if (!isdigit (*input_line_pointer)) |
10239 | as_bad ("Expected simple number."); | |
10240 | if (input_line_pointer[0] == '0') | |
10241 | { | |
10242 | if (input_line_pointer[1] == 'x') | |
10243 | { | |
10244 | input_line_pointer += 2; | |
10245 | while (isxdigit (*input_line_pointer)) | |
10246 | { | |
10247 | val <<= 4; | |
3a762a0b | 10248 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10249 | } |
670a50eb ILT |
10250 | return negative ? -val : val; |
10251 | } | |
10252 | else | |
10253 | { | |
10254 | ++input_line_pointer; | |
10255 | while (isdigit (*input_line_pointer)) | |
10256 | { | |
10257 | val <<= 3; | |
10258 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10259 | } |
670a50eb | 10260 | return negative ? -val : val; |
3d3c5039 ILT |
10261 | } |
10262 | } | |
670a50eb ILT |
10263 | if (!isdigit (*input_line_pointer)) |
10264 | { | |
10265 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10266 | *input_line_pointer, *input_line_pointer); | |
10267 | as_warn ("Invalid number"); | |
10268 | return -1; | |
3d3c5039 | 10269 | } |
670a50eb ILT |
10270 | while (isdigit (*input_line_pointer)) |
10271 | { | |
10272 | val *= 10; | |
10273 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10274 | } |
670a50eb | 10275 | return negative ? -val : val; |
3d3c5039 ILT |
10276 | } |
10277 | ||
10278 | /* The .file directive; just like the usual .file directive, but there | |
10279 | is an initial number which is the ECOFF file index. */ | |
10280 | ||
10281 | static void | |
10282 | s_file (x) | |
10283 | int x; | |
10284 | { | |
670a50eb | 10285 | int line; |
3d3c5039 | 10286 | |
670a50eb | 10287 | line = get_number (); |
9a7d824a | 10288 | s_app_file (0); |
3d3c5039 ILT |
10289 | } |
10290 | ||
10291 | ||
10292 | /* The .end directive. */ | |
10293 | ||
10294 | static void | |
10295 | s_mipsend (x) | |
10296 | int x; | |
10297 | { | |
670a50eb ILT |
10298 | symbolS *p; |
10299 | ||
10300 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10301 | { | |
10302 | p = get_symbol (); | |
10303 | demand_empty_rest_of_line (); | |
10304 | } | |
10305 | else | |
10306 | p = NULL; | |
10307 | if (now_seg != text_section) | |
10308 | as_warn (".end not in text section"); | |
10309 | if (!proc_lastP) | |
10310 | { | |
10311 | as_warn (".end and no .ent seen yet."); | |
10312 | return; | |
3d3c5039 ILT |
10313 | } |
10314 | ||
670a50eb ILT |
10315 | if (p != NULL) |
10316 | { | |
10317 | assert (S_GET_NAME (p)); | |
10318 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10319 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10320 | } |
10321 | ||
670a50eb | 10322 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10323 | } |
10324 | ||
10325 | /* The .aent and .ent directives. */ | |
10326 | ||
10327 | static void | |
10328 | s_ent (aent) | |
10329 | int aent; | |
10330 | { | |
670a50eb ILT |
10331 | int number = 0; |
10332 | procS *procP; | |
10333 | symbolS *symbolP; | |
10334 | ||
10335 | symbolP = get_symbol (); | |
10336 | if (*input_line_pointer == ',') | |
10337 | input_line_pointer++; | |
dd3f1f76 | 10338 | SKIP_WHITESPACE (); |
670a50eb ILT |
10339 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10340 | number = get_number (); | |
10341 | if (now_seg != text_section) | |
10342 | as_warn (".ent or .aent not in text section."); | |
10343 | ||
10344 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10345 | as_warn ("missing `.end'"); | |
10346 | ||
10347 | if (!aent) | |
10348 | { | |
10349 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10350 | procP->proc_isym = symbolP; | |
10351 | procP->proc_reg_mask = 0; | |
10352 | procP->proc_reg_offset = 0; | |
10353 | procP->proc_fpreg_mask = 0; | |
10354 | procP->proc_fpreg_offset = 0; | |
10355 | procP->proc_frameoffset = 0; | |
10356 | procP->proc_framereg = 0; | |
10357 | procP->proc_pcreg = 0; | |
10358 | procP->proc_end = NULL; | |
10359 | procP->proc_next = NULL; | |
10360 | if (proc_lastP) | |
10361 | proc_lastP->proc_next = procP; | |
10362 | else | |
10363 | proc_rootP = procP; | |
10364 | proc_lastP = procP; | |
10365 | numprocs++; | |
3d3c5039 | 10366 | } |
670a50eb | 10367 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10368 | } |
10369 | ||
10370 | /* The .frame directive. */ | |
10371 | ||
88225433 | 10372 | #if 0 |
3d3c5039 ILT |
10373 | static void |
10374 | s_frame (x) | |
670a50eb | 10375 | int x; |
3d3c5039 | 10376 | { |
670a50eb ILT |
10377 | char str[100]; |
10378 | symbolS *symP; | |
10379 | int frame_reg; | |
10380 | int frame_off; | |
10381 | int pcreg; | |
10382 | ||
0dd2d296 | 10383 | frame_reg = tc_get_register (1); |
670a50eb ILT |
10384 | if (*input_line_pointer == ',') |
10385 | input_line_pointer++; | |
5ac34ac3 | 10386 | frame_off = get_absolute_expression (); |
670a50eb ILT |
10387 | if (*input_line_pointer == ',') |
10388 | input_line_pointer++; | |
0dd2d296 | 10389 | pcreg = tc_get_register (0); |
670a50eb ILT |
10390 | |
10391 | /* bob third eye */ | |
10392 | assert (proc_rootP); | |
10393 | proc_rootP->proc_framereg = frame_reg; | |
10394 | proc_rootP->proc_frameoffset = frame_off; | |
10395 | proc_rootP->proc_pcreg = pcreg; | |
10396 | /* bob macho .frame */ | |
10397 | ||
10398 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 10399 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
10400 | { |
10401 | if (!proc_lastP) | |
10402 | as_warn ("No .ent for .frame to use."); | |
10403 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
10404 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
10405 | S_SET_TYPE (symP, N_RMASK); | |
10406 | S_SET_OTHER (symP, 0); | |
10407 | S_SET_DESC (symP, 0); | |
10408 | symP->sy_forward = proc_lastP->proc_isym; | |
10409 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10410 | } |
670a50eb | 10411 | demand_empty_rest_of_line (); |
3d3c5039 | 10412 | } |
88225433 | 10413 | #endif |
3d3c5039 ILT |
10414 | |
10415 | /* The .fmask and .mask directives. */ | |
10416 | ||
88225433 | 10417 | #if 0 |
3d3c5039 ILT |
10418 | static void |
10419 | s_mask (reg_type) | |
10420 | char reg_type; | |
10421 | { | |
670a50eb ILT |
10422 | char str[100], *strP; |
10423 | symbolS *symP; | |
10424 | int i; | |
10425 | unsigned int mask; | |
10426 | int off; | |
10427 | ||
10428 | mask = get_number (); | |
10429 | if (*input_line_pointer == ',') | |
10430 | input_line_pointer++; | |
10431 | off = get_absolute_expression (); | |
10432 | ||
10433 | /* bob only for coff */ | |
10434 | assert (proc_rootP); | |
10435 | if (reg_type == 'F') | |
10436 | { | |
10437 | proc_rootP->proc_fpreg_mask = mask; | |
10438 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 10439 | } |
670a50eb ILT |
10440 | else |
10441 | { | |
10442 | proc_rootP->proc_reg_mask = mask; | |
10443 | proc_rootP->proc_reg_offset = off; | |
10444 | } | |
10445 | ||
10446 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 10447 | |
670a50eb ILT |
10448 | /* We don't have to write out a mask stab if no saved regs. */ |
10449 | if (!(mask == 0)) | |
10450 | { | |
10451 | if (!proc_lastP) | |
10452 | as_warn ("No .ent for .mask to use."); | |
10453 | strP = str; | |
10454 | for (i = 0; i < 32; i++) | |
10455 | { | |
10456 | if (mask % 2) | |
10457 | { | |
10458 | sprintf (strP, "%c%d,", reg_type, i); | |
10459 | strP += strlen (strP); | |
10460 | } | |
3d3c5039 | 10461 | mask /= 2; |
670a50eb ILT |
10462 | } |
10463 | sprintf (strP, ";%d,", off); | |
10464 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
10465 | S_SET_TYPE (symP, N_RMASK); | |
10466 | S_SET_OTHER (symP, 0); | |
10467 | S_SET_DESC (symP, 0); | |
10468 | symP->sy_forward = proc_lastP->proc_isym; | |
10469 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10470 | } |
3d3c5039 | 10471 | } |
88225433 | 10472 | #endif |
3d3c5039 ILT |
10473 | |
10474 | /* The .loc directive. */ | |
10475 | ||
88225433 | 10476 | #if 0 |
3d3c5039 ILT |
10477 | static void |
10478 | s_loc (x) | |
10479 | int x; | |
10480 | { | |
670a50eb ILT |
10481 | symbolS *symbolP; |
10482 | int lineno; | |
10483 | int addroff; | |
3d3c5039 | 10484 | |
670a50eb | 10485 | assert (now_seg == text_section); |
3d3c5039 | 10486 | |
670a50eb | 10487 | lineno = get_number (); |
87e48495 | 10488 | addroff = frag_now_fix (); |
3d3c5039 | 10489 | |
670a50eb ILT |
10490 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
10491 | S_SET_TYPE (symbolP, N_SLINE); | |
10492 | S_SET_OTHER (symbolP, 0); | |
10493 | S_SET_DESC (symbolP, lineno); | |
10494 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 10495 | } |
88225433 | 10496 | #endif |