Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
ebd1c875 | 3 | 2003, 2004, 2005, 2006 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 RH |
31 | #include "opcode/mips.h" |
32 | #include "itbl-ops.h" | |
c5dd6aab | 33 | #include "dwarf2dbg.h" |
5862107c | 34 | #include "dw2gencfi.h" |
252b5132 RH |
35 | |
36 | #ifdef DEBUG | |
37 | #define DBG(x) printf x | |
38 | #else | |
39 | #define DBG(x) | |
40 | #endif | |
41 | ||
42 | #ifdef OBJ_MAYBE_ELF | |
43 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
44 | static int mips_output_flavor (void); |
45 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
46 | #undef OBJ_PROCESS_STAB |
47 | #undef OUTPUT_FLAVOR | |
48 | #undef S_GET_ALIGN | |
49 | #undef S_GET_SIZE | |
50 | #undef S_SET_ALIGN | |
51 | #undef S_SET_SIZE | |
252b5132 RH |
52 | #undef obj_frob_file |
53 | #undef obj_frob_file_after_relocs | |
54 | #undef obj_frob_symbol | |
55 | #undef obj_pop_insert | |
56 | #undef obj_sec_sym_ok_for_reloc | |
57 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
58 | ||
59 | #include "obj-elf.h" | |
60 | /* Fix any of them that we actually care about. */ | |
61 | #undef OUTPUT_FLAVOR | |
62 | #define OUTPUT_FLAVOR mips_output_flavor() | |
63 | #endif | |
64 | ||
65 | #if defined (OBJ_ELF) | |
66 | #include "elf/mips.h" | |
67 | #endif | |
68 | ||
69 | #ifndef ECOFF_DEBUGGING | |
70 | #define NO_ECOFF_DEBUGGING | |
71 | #define ECOFF_DEBUGGING 0 | |
72 | #endif | |
73 | ||
ecb4347a DJ |
74 | int mips_flag_mdebug = -1; |
75 | ||
dcd410fe RO |
76 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
77 | linker doesn't know about and discards them, but relocations against them | |
78 | remain, leading to rld crashes. */ | |
79 | #ifdef TE_IRIX | |
80 | int mips_flag_pdr = FALSE; | |
81 | #else | |
82 | int mips_flag_pdr = TRUE; | |
83 | #endif | |
84 | ||
252b5132 RH |
85 | #include "ecoff.h" |
86 | ||
87 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
88 | static char *mips_regmask_frag; | |
89 | #endif | |
90 | ||
85b51719 | 91 | #define ZERO 0 |
252b5132 RH |
92 | #define AT 1 |
93 | #define TREG 24 | |
94 | #define PIC_CALL_REG 25 | |
95 | #define KT0 26 | |
96 | #define KT1 27 | |
97 | #define GP 28 | |
98 | #define SP 29 | |
99 | #define FP 30 | |
100 | #define RA 31 | |
101 | ||
102 | #define ILLEGAL_REG (32) | |
103 | ||
104 | /* Allow override of standard little-endian ECOFF format. */ | |
105 | ||
106 | #ifndef ECOFF_LITTLE_FORMAT | |
107 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
108 | #endif | |
109 | ||
110 | extern int target_big_endian; | |
111 | ||
252b5132 | 112 | /* The name of the readonly data section. */ |
4d0d148d | 113 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 114 | ? ".rdata" \ |
056350c6 NC |
115 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
116 | ? ".rdata" \ | |
252b5132 RH |
117 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
118 | ? ".rodata" \ | |
119 | : (abort (), "")) | |
120 | ||
47e39b9d RS |
121 | /* Information about an instruction, including its format, operands |
122 | and fixups. */ | |
123 | struct mips_cl_insn | |
124 | { | |
125 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
126 | const struct mips_opcode *insn_mo; | |
127 | ||
128 | /* True if this is a mips16 instruction and if we want the extended | |
129 | form of INSN_MO. */ | |
130 | bfd_boolean use_extend; | |
131 | ||
132 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
133 | unsigned short extend; | |
134 | ||
135 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
136 | a copy of INSN_MO->match with the operands filled in. */ | |
137 | unsigned long insn_opcode; | |
138 | ||
139 | /* The frag that contains the instruction. */ | |
140 | struct frag *frag; | |
141 | ||
142 | /* The offset into FRAG of the first instruction byte. */ | |
143 | long where; | |
144 | ||
145 | /* The relocs associated with the instruction, if any. */ | |
146 | fixS *fixp[3]; | |
147 | ||
a38419a5 RS |
148 | /* True if this entry cannot be moved from its current position. */ |
149 | unsigned int fixed_p : 1; | |
47e39b9d | 150 | |
708587a4 | 151 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
152 | unsigned int noreorder_p : 1; |
153 | ||
2fa15973 RS |
154 | /* True for mips16 instructions that jump to an absolute address. */ |
155 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
156 | }; |
157 | ||
a325df1d TS |
158 | /* The ABI to use. */ |
159 | enum mips_abi_level | |
160 | { | |
161 | NO_ABI = 0, | |
162 | O32_ABI, | |
163 | O64_ABI, | |
164 | N32_ABI, | |
165 | N64_ABI, | |
166 | EABI_ABI | |
167 | }; | |
168 | ||
169 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 170 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 171 | |
143d77c5 EC |
172 | /* Whether or not we have code that can call pic code. */ |
173 | int mips_abicalls = FALSE; | |
174 | ||
aa6975fb ILT |
175 | /* Whether or not we have code which can be put into a shared |
176 | library. */ | |
177 | static bfd_boolean mips_in_shared = TRUE; | |
178 | ||
252b5132 RH |
179 | /* This is the set of options which may be modified by the .set |
180 | pseudo-op. We use a struct so that .set push and .set pop are more | |
181 | reliable. */ | |
182 | ||
e972090a NC |
183 | struct mips_set_options |
184 | { | |
252b5132 RH |
185 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
186 | if it has not been initialized. Changed by `.set mipsN', and the | |
187 | -mipsN command line option, and the default CPU. */ | |
188 | int isa; | |
1f25f5d3 CD |
189 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
190 | if they have not been initialized. Changed by `.set <asename>', by | |
191 | command line options, and based on the default architecture. */ | |
192 | int ase_mips3d; | |
deec1734 | 193 | int ase_mdmx; |
e16bfa71 | 194 | int ase_smartmips; |
74cd071d | 195 | int ase_dsp; |
ef2e4d86 | 196 | int ase_mt; |
252b5132 RH |
197 | /* Whether we are assembling for the mips16 processor. 0 if we are |
198 | not, 1 if we are, and -1 if the value has not been initialized. | |
199 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
200 | -nomips16 command line options, and the default CPU. */ | |
201 | int mips16; | |
202 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
203 | reorder' and `.set noreorder'. */ | |
204 | int noreorder; | |
205 | /* Non-zero if we should not permit the $at ($1) register to be used | |
206 | in instructions. Changed by `.set at' and `.set noat'. */ | |
207 | int noat; | |
208 | /* Non-zero if we should warn when a macro instruction expands into | |
209 | more than one machine instruction. Changed by `.set nomacro' and | |
210 | `.set macro'. */ | |
211 | int warn_about_macros; | |
212 | /* Non-zero if we should not move instructions. Changed by `.set | |
213 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
214 | int nomove; | |
215 | /* Non-zero if we should not optimize branches by moving the target | |
216 | of the branch into the delay slot. Actually, we don't perform | |
217 | this optimization anyhow. Changed by `.set bopt' and `.set | |
218 | nobopt'. */ | |
219 | int nobopt; | |
220 | /* Non-zero if we should not autoextend mips16 instructions. | |
221 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
222 | int noautoextend; | |
a325df1d TS |
223 | /* Restrict general purpose registers and floating point registers |
224 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
225 | is passed but can changed if the assembler code uses .set mipsN. */ | |
226 | int gp32; | |
227 | int fp32; | |
fef14a42 TS |
228 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
229 | command line option, and the default CPU. */ | |
230 | int arch; | |
aed1a261 RS |
231 | /* True if ".set sym32" is in effect. */ |
232 | bfd_boolean sym32; | |
252b5132 RH |
233 | }; |
234 | ||
a325df1d | 235 | /* True if -mgp32 was passed. */ |
a8e8e863 | 236 | static int file_mips_gp32 = -1; |
a325df1d TS |
237 | |
238 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 239 | static int file_mips_fp32 = -1; |
a325df1d | 240 | |
252b5132 | 241 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 242 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 243 | -1 to indicate that they have not been initialized. */ |
252b5132 | 244 | |
e972090a NC |
245 | static struct mips_set_options mips_opts = |
246 | { | |
e16bfa71 | 247 | ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 248 | }; |
252b5132 RH |
249 | |
250 | /* These variables are filled in with the masks of registers used. | |
251 | The object format code reads them and puts them in the appropriate | |
252 | place. */ | |
253 | unsigned long mips_gprmask; | |
254 | unsigned long mips_cprmask[4]; | |
255 | ||
256 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 257 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 258 | |
a4672219 TS |
259 | /* True if -mips16 was passed or implied by arguments passed on the |
260 | command line (e.g., by -march). */ | |
261 | static int file_ase_mips16; | |
262 | ||
3994f87e TS |
263 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
264 | || mips_opts.isa == ISA_MIPS32R2 \ | |
265 | || mips_opts.isa == ISA_MIPS64 \ | |
266 | || mips_opts.isa == ISA_MIPS64R2) | |
267 | ||
1f25f5d3 CD |
268 | /* True if -mips3d was passed or implied by arguments passed on the |
269 | command line (e.g., by -march). */ | |
270 | static int file_ase_mips3d; | |
271 | ||
deec1734 CD |
272 | /* True if -mdmx was passed or implied by arguments passed on the |
273 | command line (e.g., by -march). */ | |
274 | static int file_ase_mdmx; | |
275 | ||
e16bfa71 TS |
276 | /* True if -msmartmips was passed or implied by arguments passed on the |
277 | command line (e.g., by -march). */ | |
278 | static int file_ase_smartmips; | |
279 | ||
ad3fea08 TS |
280 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
281 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 282 | |
74cd071d CF |
283 | /* True if -mdsp was passed or implied by arguments passed on the |
284 | command line (e.g., by -march). */ | |
285 | static int file_ase_dsp; | |
286 | ||
ad3fea08 TS |
287 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
288 | || mips_opts.isa == ISA_MIPS64R2) | |
289 | ||
65263ce3 TS |
290 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
291 | ||
ef2e4d86 CF |
292 | /* True if -mmt was passed or implied by arguments passed on the |
293 | command line (e.g., by -march). */ | |
294 | static int file_ase_mt; | |
295 | ||
ad3fea08 TS |
296 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
297 | || mips_opts.isa == ISA_MIPS64R2) | |
298 | ||
ec68c924 | 299 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 300 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 301 | static const char *mips_arch_string; |
ec68c924 EC |
302 | |
303 | /* The argument of the -mtune= flag. The architecture for which we | |
304 | are optimizing. */ | |
305 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 306 | static const char *mips_tune_string; |
ec68c924 | 307 | |
316f5878 | 308 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
309 | static int mips_32bitmode = 0; |
310 | ||
316f5878 RS |
311 | /* True if the given ABI requires 32-bit registers. */ |
312 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
313 | ||
314 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
315 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
316 | ((ABI) == N32_ABI \ | |
317 | || (ABI) == N64_ABI \ | |
316f5878 RS |
318 | || (ABI) == O64_ABI) |
319 | ||
ad3fea08 | 320 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
321 | #define ISA_HAS_64BIT_REGS(ISA) \ |
322 | ((ISA) == ISA_MIPS3 \ | |
323 | || (ISA) == ISA_MIPS4 \ | |
324 | || (ISA) == ISA_MIPS5 \ | |
325 | || (ISA) == ISA_MIPS64 \ | |
326 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 327 | |
ad3fea08 TS |
328 | /* Return true if ISA supports 64 bit wide float registers. */ |
329 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
330 | ((ISA) == ISA_MIPS3 \ | |
331 | || (ISA) == ISA_MIPS4 \ | |
332 | || (ISA) == ISA_MIPS5 \ | |
333 | || (ISA) == ISA_MIPS32R2 \ | |
334 | || (ISA) == ISA_MIPS64 \ | |
335 | || (ISA) == ISA_MIPS64R2) | |
336 | ||
af7ee8bf CD |
337 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
338 | instructions. */ | |
707bfff6 TS |
339 | #define ISA_HAS_DROR(ISA) \ |
340 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
341 | |
342 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
343 | instructions. */ | |
707bfff6 TS |
344 | #define ISA_HAS_ROR(ISA) \ |
345 | ((ISA) == ISA_MIPS32R2 \ | |
346 | || (ISA) == ISA_MIPS64R2 \ | |
347 | || mips_opts.ase_smartmips) | |
348 | ||
7455baf8 TS |
349 | /* Return true if ISA supports single-precision floats in odd registers. */ |
350 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
351 | ((ISA) == ISA_MIPS32 \ | |
352 | || (ISA) == ISA_MIPS32R2 \ | |
353 | || (ISA) == ISA_MIPS64 \ | |
354 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 355 | |
ad3fea08 TS |
356 | /* Return true if ISA supports move to/from high part of a 64-bit |
357 | floating-point register. */ | |
358 | #define ISA_HAS_MXHC1(ISA) \ | |
359 | ((ISA) == ISA_MIPS32R2 \ | |
360 | || (ISA) == ISA_MIPS64R2) | |
361 | ||
e013f690 | 362 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 363 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 364 | |
e013f690 | 365 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 366 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 367 | |
ad3fea08 TS |
368 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
369 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 370 | |
316f5878 | 371 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 372 | |
316f5878 | 373 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 374 | |
3b91255e RS |
375 | /* True if relocations are stored in-place. */ |
376 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
377 | ||
aed1a261 RS |
378 | /* The ABI-derived address size. */ |
379 | #define HAVE_64BIT_ADDRESSES \ | |
380 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
381 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 382 | |
aed1a261 RS |
383 | /* The size of symbolic constants (i.e., expressions of the form |
384 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
385 | #define HAVE_32BIT_SYMBOLS \ | |
386 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
387 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 388 | |
b7c7d6c1 TS |
389 | /* Addresses are loaded in different ways, depending on the address size |
390 | in use. The n32 ABI Documentation also mandates the use of additions | |
391 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 392 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 393 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
394 | |
395 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 396 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
397 | |
398 | #define ADDRESS_LOAD_INSN \ | |
399 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
400 | ||
401 | #define ADDRESS_STORE_INSN \ | |
402 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
403 | ||
a4672219 | 404 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
405 | #define CPU_HAS_MIPS16(cpu) \ |
406 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
407 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 408 | |
60b63b72 RS |
409 | /* True if CPU has a dror instruction. */ |
410 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
411 | ||
412 | /* True if CPU has a ror instruction. */ | |
413 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
414 | ||
c8978940 CD |
415 | /* True if mflo and mfhi can be immediately followed by instructions |
416 | which write to the HI and LO registers. | |
417 | ||
418 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
419 | (at least) two instructions between the reads of HI/LO and | |
420 | instructions which write them, and later ISAs do not. Contradicting | |
421 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
422 | the UM for the NEC Vr5000) document needing the instructions between | |
423 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
424 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
425 | earlier-ISA CPUs for which CPU documentation declares that the | |
426 | instructions are really interlocked. */ | |
427 | #define hilo_interlocks \ | |
428 | (mips_opts.isa == ISA_MIPS32 \ | |
429 | || mips_opts.isa == ISA_MIPS32R2 \ | |
430 | || mips_opts.isa == ISA_MIPS64 \ | |
431 | || mips_opts.isa == ISA_MIPS64R2 \ | |
432 | || mips_opts.arch == CPU_R4010 \ | |
433 | || mips_opts.arch == CPU_R10000 \ | |
434 | || mips_opts.arch == CPU_R12000 \ | |
435 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
436 | || mips_opts.arch == CPU_VR5500 \ |
437 | ) | |
252b5132 RH |
438 | |
439 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
440 | from the GPRs after they are loaded from memory, and thus does not |
441 | require nops to be inserted. This applies to instructions marked | |
442 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
443 | level I. */ | |
252b5132 | 444 | #define gpr_interlocks \ |
e7af610e | 445 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 446 | || mips_opts.arch == CPU_R3900) |
252b5132 | 447 | |
81912461 ILT |
448 | /* Whether the processor uses hardware interlocks to avoid delays |
449 | required by coprocessor instructions, and thus does not require | |
450 | nops to be inserted. This applies to instructions marked | |
451 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
452 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
453 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
454 | levels I, II, and III. */ | |
bdaaa2e1 | 455 | /* Itbl support may require additional care here. */ |
81912461 ILT |
456 | #define cop_interlocks \ |
457 | ((mips_opts.isa != ISA_MIPS1 \ | |
458 | && mips_opts.isa != ISA_MIPS2 \ | |
459 | && mips_opts.isa != ISA_MIPS3) \ | |
460 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
461 | ) |
462 | ||
463 | /* Whether the processor uses hardware interlocks to protect reads | |
464 | from coprocessor registers after they are loaded from memory, and | |
465 | thus does not require nops to be inserted. This applies to | |
466 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
467 | requires at MIPS ISA level I. */ | |
468 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 469 | |
6b76fefe CM |
470 | /* Is this a mfhi or mflo instruction? */ |
471 | #define MF_HILO_INSN(PINFO) \ | |
472 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
473 | ||
252b5132 RH |
474 | /* MIPS PIC level. */ |
475 | ||
a161fe53 | 476 | enum mips_pic_level mips_pic; |
252b5132 | 477 | |
c9914766 | 478 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 479 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 480 | static int mips_big_got = 0; |
252b5132 RH |
481 | |
482 | /* 1 if trap instructions should used for overflow rather than break | |
483 | instructions. */ | |
c9914766 | 484 | static int mips_trap = 0; |
252b5132 | 485 | |
119d663a | 486 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 487 | by assembling two single width halves into two single width floating |
119d663a NC |
488 | point registers which just happen to alias the double width destination |
489 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 490 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
491 | automatically at assemble time. */ |
492 | static int mips_disable_float_construction; | |
493 | ||
252b5132 RH |
494 | /* Non-zero if any .set noreorder directives were used. */ |
495 | ||
496 | static int mips_any_noreorder; | |
497 | ||
6b76fefe CM |
498 | /* Non-zero if nops should be inserted when the register referenced in |
499 | an mfhi/mflo instruction is read in the next two instructions. */ | |
500 | static int mips_7000_hilo_fix; | |
501 | ||
252b5132 | 502 | /* The size of the small data section. */ |
156c2f8b | 503 | static unsigned int g_switch_value = 8; |
252b5132 RH |
504 | /* Whether the -G option was used. */ |
505 | static int g_switch_seen = 0; | |
506 | ||
507 | #define N_RMASK 0xc4 | |
508 | #define N_VFP 0xd4 | |
509 | ||
510 | /* If we can determine in advance that GP optimization won't be | |
511 | possible, we can skip the relaxation stuff that tries to produce | |
512 | GP-relative references. This makes delay slot optimization work | |
513 | better. | |
514 | ||
515 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
516 | gcc output. It needs to guess right for gcc, otherwise gcc |
517 | will put what it thinks is a GP-relative instruction in a branch | |
518 | delay slot. | |
252b5132 RH |
519 | |
520 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
521 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 522 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
523 | |
524 | /* handle of the OPCODE hash table */ | |
525 | static struct hash_control *op_hash = NULL; | |
526 | ||
527 | /* The opcode hash table we use for the mips16. */ | |
528 | static struct hash_control *mips16_op_hash = NULL; | |
529 | ||
530 | /* This array holds the chars that always start a comment. If the | |
531 | pre-processor is disabled, these aren't very useful */ | |
532 | const char comment_chars[] = "#"; | |
533 | ||
534 | /* This array holds the chars that only start a comment at the beginning of | |
535 | a line. If the line seems to have the form '# 123 filename' | |
536 | .line and .file directives will appear in the pre-processed output */ | |
537 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
538 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 539 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
540 | /* Also note that C style comments are always supported. */ |
541 | const char line_comment_chars[] = "#"; | |
542 | ||
bdaaa2e1 | 543 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 544 | const char line_separator_chars[] = ";"; |
252b5132 RH |
545 | |
546 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
547 | const char EXP_CHARS[] = "eE"; | |
548 | ||
549 | /* Chars that mean this number is a floating point constant */ | |
550 | /* As in 0f12.456 */ | |
551 | /* or 0d1.2345e12 */ | |
552 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
553 | ||
554 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
555 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
556 | but nothing is ideal around here. | |
557 | */ | |
558 | ||
559 | static char *insn_error; | |
560 | ||
561 | static int auto_align = 1; | |
562 | ||
563 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
564 | offset in the stack frame from which to restore the $gp register. | |
565 | This is set by the .cprestore pseudo-op, and saved in this | |
566 | variable. */ | |
567 | static offsetT mips_cprestore_offset = -1; | |
568 | ||
67c1ffbe | 569 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 570 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 571 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
572 | static offsetT mips_cpreturn_offset = -1; |
573 | static int mips_cpreturn_register = -1; | |
574 | static int mips_gp_register = GP; | |
def2e0dd | 575 | static int mips_gprel_offset = 0; |
6478892d | 576 | |
7a621144 DJ |
577 | /* Whether mips_cprestore_offset has been set in the current function |
578 | (or whether it has already been warned about, if not). */ | |
579 | static int mips_cprestore_valid = 0; | |
580 | ||
252b5132 RH |
581 | /* This is the register which holds the stack frame, as set by the |
582 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
583 | static int mips_frame_reg = SP; | |
584 | ||
7a621144 DJ |
585 | /* Whether mips_frame_reg has been set in the current function |
586 | (or whether it has already been warned about, if not). */ | |
587 | static int mips_frame_reg_valid = 0; | |
588 | ||
252b5132 RH |
589 | /* To output NOP instructions correctly, we need to keep information |
590 | about the previous two instructions. */ | |
591 | ||
592 | /* Whether we are optimizing. The default value of 2 means to remove | |
593 | unneeded NOPs and swap branch instructions when possible. A value | |
594 | of 1 means to not swap branches. A value of 0 means to always | |
595 | insert NOPs. */ | |
596 | static int mips_optimize = 2; | |
597 | ||
598 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
599 | equivalent to seeing no -g option at all. */ | |
600 | static int mips_debug = 0; | |
601 | ||
7d8e00cf RS |
602 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
603 | #define MAX_VR4130_NOPS 4 | |
604 | ||
605 | /* The maximum number of NOPs needed to fill delay slots. */ | |
606 | #define MAX_DELAY_NOPS 2 | |
607 | ||
608 | /* The maximum number of NOPs needed for any purpose. */ | |
609 | #define MAX_NOPS 4 | |
71400594 RS |
610 | |
611 | /* A list of previous instructions, with index 0 being the most recent. | |
612 | We need to look back MAX_NOPS instructions when filling delay slots | |
613 | or working around processor errata. We need to look back one | |
614 | instruction further if we're thinking about using history[0] to | |
615 | fill a branch delay slot. */ | |
616 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 617 | |
1e915849 RS |
618 | /* Nop instructions used by emit_nop. */ |
619 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
620 | ||
621 | /* The appropriate nop for the current mode. */ | |
622 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 623 | |
252b5132 RH |
624 | /* If this is set, it points to a frag holding nop instructions which |
625 | were inserted before the start of a noreorder section. If those | |
626 | nops turn out to be unnecessary, the size of the frag can be | |
627 | decreased. */ | |
628 | static fragS *prev_nop_frag; | |
629 | ||
630 | /* The number of nop instructions we created in prev_nop_frag. */ | |
631 | static int prev_nop_frag_holds; | |
632 | ||
633 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 634 | prev_nop_frag. */ |
252b5132 RH |
635 | static int prev_nop_frag_required; |
636 | ||
637 | /* The number of instructions we've seen since prev_nop_frag. */ | |
638 | static int prev_nop_frag_since; | |
639 | ||
640 | /* For ECOFF and ELF, relocations against symbols are done in two | |
641 | parts, with a HI relocation and a LO relocation. Each relocation | |
642 | has only 16 bits of space to store an addend. This means that in | |
643 | order for the linker to handle carries correctly, it must be able | |
644 | to locate both the HI and the LO relocation. This means that the | |
645 | relocations must appear in order in the relocation table. | |
646 | ||
647 | In order to implement this, we keep track of each unmatched HI | |
648 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 649 | corresponding LO relocation. */ |
252b5132 | 650 | |
e972090a NC |
651 | struct mips_hi_fixup |
652 | { | |
252b5132 RH |
653 | /* Next HI fixup. */ |
654 | struct mips_hi_fixup *next; | |
655 | /* This fixup. */ | |
656 | fixS *fixp; | |
657 | /* The section this fixup is in. */ | |
658 | segT seg; | |
659 | }; | |
660 | ||
661 | /* The list of unmatched HI relocs. */ | |
662 | ||
663 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
664 | ||
64bdfcaf RS |
665 | /* The frag containing the last explicit relocation operator. |
666 | Null if explicit relocations have not been used. */ | |
667 | ||
668 | static fragS *prev_reloc_op_frag; | |
669 | ||
252b5132 RH |
670 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
671 | ||
672 | #define X ILLEGAL_REG | |
e972090a NC |
673 | static const int mips32_to_16_reg_map[] = |
674 | { | |
252b5132 RH |
675 | X, X, 2, 3, 4, 5, 6, 7, |
676 | X, X, X, X, X, X, X, X, | |
677 | 0, 1, X, X, X, X, X, X, | |
678 | X, X, X, X, X, X, X, X | |
679 | }; | |
680 | #undef X | |
681 | ||
682 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
683 | ||
e972090a NC |
684 | static const unsigned int mips16_to_32_reg_map[] = |
685 | { | |
252b5132 RH |
686 | 16, 17, 2, 3, 4, 5, 6, 7 |
687 | }; | |
60b63b72 | 688 | |
71400594 RS |
689 | /* Classifies the kind of instructions we're interested in when |
690 | implementing -mfix-vr4120. */ | |
691 | enum fix_vr4120_class { | |
692 | FIX_VR4120_MACC, | |
693 | FIX_VR4120_DMACC, | |
694 | FIX_VR4120_MULT, | |
695 | FIX_VR4120_DMULT, | |
696 | FIX_VR4120_DIV, | |
697 | FIX_VR4120_MTHILO, | |
698 | NUM_FIX_VR4120_CLASSES | |
699 | }; | |
700 | ||
701 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
702 | there must be at least one other instruction between an instruction | |
703 | of type X and an instruction of type Y. */ | |
704 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
705 | ||
706 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 707 | static int mips_fix_vr4120; |
4a6a3df4 | 708 | |
7d8e00cf RS |
709 | /* ...likewise -mfix-vr4130. */ |
710 | static int mips_fix_vr4130; | |
711 | ||
4a6a3df4 AO |
712 | /* We don't relax branches by default, since this causes us to expand |
713 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
714 | fail to compute the offset before expanding the macro to the most | |
715 | efficient expansion. */ | |
716 | ||
717 | static int mips_relax_branch; | |
252b5132 | 718 | \f |
4d7206a2 RS |
719 | /* The expansion of many macros depends on the type of symbol that |
720 | they refer to. For example, when generating position-dependent code, | |
721 | a macro that refers to a symbol may have two different expansions, | |
722 | one which uses GP-relative addresses and one which uses absolute | |
723 | addresses. When generating SVR4-style PIC, a macro may have | |
724 | different expansions for local and global symbols. | |
725 | ||
726 | We handle these situations by generating both sequences and putting | |
727 | them in variant frags. In position-dependent code, the first sequence | |
728 | will be the GP-relative one and the second sequence will be the | |
729 | absolute one. In SVR4 PIC, the first sequence will be for global | |
730 | symbols and the second will be for local symbols. | |
731 | ||
584892a6 RS |
732 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
733 | SECOND are the lengths of the two sequences in bytes. These fields | |
734 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
735 | the subtype has the following flags: | |
4d7206a2 | 736 | |
584892a6 RS |
737 | RELAX_USE_SECOND |
738 | Set if it has been decided that we should use the second | |
739 | sequence instead of the first. | |
740 | ||
741 | RELAX_SECOND_LONGER | |
742 | Set in the first variant frag if the macro's second implementation | |
743 | is longer than its first. This refers to the macro as a whole, | |
744 | not an individual relaxation. | |
745 | ||
746 | RELAX_NOMACRO | |
747 | Set in the first variant frag if the macro appeared in a .set nomacro | |
748 | block and if one alternative requires a warning but the other does not. | |
749 | ||
750 | RELAX_DELAY_SLOT | |
751 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
752 | delay slot. | |
4d7206a2 RS |
753 | |
754 | The frag's "opcode" points to the first fixup for relaxable code. | |
755 | ||
756 | Relaxable macros are generated using a sequence such as: | |
757 | ||
758 | relax_start (SYMBOL); | |
759 | ... generate first expansion ... | |
760 | relax_switch (); | |
761 | ... generate second expansion ... | |
762 | relax_end (); | |
763 | ||
764 | The code and fixups for the unwanted alternative are discarded | |
765 | by md_convert_frag. */ | |
584892a6 | 766 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 767 | |
584892a6 RS |
768 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
769 | #define RELAX_SECOND(X) ((X) & 0xff) | |
770 | #define RELAX_USE_SECOND 0x10000 | |
771 | #define RELAX_SECOND_LONGER 0x20000 | |
772 | #define RELAX_NOMACRO 0x40000 | |
773 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 774 | |
4a6a3df4 AO |
775 | /* Branch without likely bit. If label is out of range, we turn: |
776 | ||
777 | beq reg1, reg2, label | |
778 | delay slot | |
779 | ||
780 | into | |
781 | ||
782 | bne reg1, reg2, 0f | |
783 | nop | |
784 | j label | |
785 | 0: delay slot | |
786 | ||
787 | with the following opcode replacements: | |
788 | ||
789 | beq <-> bne | |
790 | blez <-> bgtz | |
791 | bltz <-> bgez | |
792 | bc1f <-> bc1t | |
793 | ||
794 | bltzal <-> bgezal (with jal label instead of j label) | |
795 | ||
796 | Even though keeping the delay slot instruction in the delay slot of | |
797 | the branch would be more efficient, it would be very tricky to do | |
798 | correctly, because we'd have to introduce a variable frag *after* | |
799 | the delay slot instruction, and expand that instead. Let's do it | |
800 | the easy way for now, even if the branch-not-taken case now costs | |
801 | one additional instruction. Out-of-range branches are not supposed | |
802 | to be common, anyway. | |
803 | ||
804 | Branch likely. If label is out of range, we turn: | |
805 | ||
806 | beql reg1, reg2, label | |
807 | delay slot (annulled if branch not taken) | |
808 | ||
809 | into | |
810 | ||
811 | beql reg1, reg2, 1f | |
812 | nop | |
813 | beql $0, $0, 2f | |
814 | nop | |
815 | 1: j[al] label | |
816 | delay slot (executed only if branch taken) | |
817 | 2: | |
818 | ||
819 | It would be possible to generate a shorter sequence by losing the | |
820 | likely bit, generating something like: | |
b34976b6 | 821 | |
4a6a3df4 AO |
822 | bne reg1, reg2, 0f |
823 | nop | |
824 | j[al] label | |
825 | delay slot (executed only if branch taken) | |
826 | 0: | |
827 | ||
828 | beql -> bne | |
829 | bnel -> beq | |
830 | blezl -> bgtz | |
831 | bgtzl -> blez | |
832 | bltzl -> bgez | |
833 | bgezl -> bltz | |
834 | bc1fl -> bc1t | |
835 | bc1tl -> bc1f | |
836 | ||
837 | bltzall -> bgezal (with jal label instead of j label) | |
838 | bgezall -> bltzal (ditto) | |
839 | ||
840 | ||
841 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 842 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
843 | ((relax_substateT) \ |
844 | (0xc0000000 \ | |
845 | | ((toofar) ? 1 : 0) \ | |
846 | | ((link) ? 2 : 0) \ | |
847 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 848 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 849 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
850 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
851 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
852 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 853 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 854 | |
252b5132 RH |
855 | /* For mips16 code, we use an entirely different form of relaxation. |
856 | mips16 supports two versions of most instructions which take | |
857 | immediate values: a small one which takes some small value, and a | |
858 | larger one which takes a 16 bit value. Since branches also follow | |
859 | this pattern, relaxing these values is required. | |
860 | ||
861 | We can assemble both mips16 and normal MIPS code in a single | |
862 | object. Therefore, we need to support this type of relaxation at | |
863 | the same time that we support the relaxation described above. We | |
864 | use the high bit of the subtype field to distinguish these cases. | |
865 | ||
866 | The information we store for this type of relaxation is the | |
867 | argument code found in the opcode file for this relocation, whether | |
868 | the user explicitly requested a small or extended form, and whether | |
869 | the relocation is in a jump or jal delay slot. That tells us the | |
870 | size of the value, and how it should be stored. We also store | |
871 | whether the fragment is considered to be extended or not. We also | |
872 | store whether this is known to be a branch to a different section, | |
873 | whether we have tried to relax this frag yet, and whether we have | |
874 | ever extended a PC relative fragment because of a shift count. */ | |
875 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
876 | (0x80000000 \ | |
877 | | ((type) & 0xff) \ | |
878 | | ((small) ? 0x100 : 0) \ | |
879 | | ((ext) ? 0x200 : 0) \ | |
880 | | ((dslot) ? 0x400 : 0) \ | |
881 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 882 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
883 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
884 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
885 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
886 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
887 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
888 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
889 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
890 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
891 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
892 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
893 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
894 | |
895 | /* Is the given value a sign-extended 32-bit value? */ | |
896 | #define IS_SEXT_32BIT_NUM(x) \ | |
897 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
898 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
899 | ||
900 | /* Is the given value a sign-extended 16-bit value? */ | |
901 | #define IS_SEXT_16BIT_NUM(x) \ | |
902 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
903 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
904 | ||
2051e8c4 MR |
905 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
906 | #define IS_ZEXT_32BIT_NUM(x) \ | |
907 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
908 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
909 | ||
bf12938e RS |
910 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
911 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
912 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
913 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
914 | | (((VALUE) & (MASK)) << (SHIFT))) | |
915 | ||
916 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
917 | SHIFT places. */ | |
918 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
919 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
920 | ||
921 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
922 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
923 | ||
924 | include/opcode/mips.h specifies operand fields using the macros | |
925 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
926 | with "MIPS16OP" instead of "OP". */ | |
927 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
928 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
929 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
930 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
931 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
932 | ||
933 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
934 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
935 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
936 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
937 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
938 | MIPS16OP_MASK_##FIELD, \ | |
939 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
940 | \f |
941 | /* Global variables used when generating relaxable macros. See the | |
942 | comment above RELAX_ENCODE for more details about how relaxation | |
943 | is used. */ | |
944 | static struct { | |
945 | /* 0 if we're not emitting a relaxable macro. | |
946 | 1 if we're emitting the first of the two relaxation alternatives. | |
947 | 2 if we're emitting the second alternative. */ | |
948 | int sequence; | |
949 | ||
950 | /* The first relaxable fixup in the current frag. (In other words, | |
951 | the first fixup that refers to relaxable code.) */ | |
952 | fixS *first_fixup; | |
953 | ||
954 | /* sizes[0] says how many bytes of the first alternative are stored in | |
955 | the current frag. Likewise sizes[1] for the second alternative. */ | |
956 | unsigned int sizes[2]; | |
957 | ||
958 | /* The symbol on which the choice of sequence depends. */ | |
959 | symbolS *symbol; | |
960 | } mips_relax; | |
252b5132 | 961 | \f |
584892a6 RS |
962 | /* Global variables used to decide whether a macro needs a warning. */ |
963 | static struct { | |
964 | /* True if the macro is in a branch delay slot. */ | |
965 | bfd_boolean delay_slot_p; | |
966 | ||
967 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
968 | in bytes and sizes[1] is the length of the second alternative. | |
969 | For non-relaxable macros, both elements give the length of the | |
970 | macro in bytes. */ | |
971 | unsigned int sizes[2]; | |
972 | ||
973 | /* The first variant frag for this macro. */ | |
974 | fragS *first_frag; | |
975 | } mips_macro_warning; | |
976 | \f | |
252b5132 RH |
977 | /* Prototypes for static functions. */ |
978 | ||
17a2f251 | 979 | #define internalError() \ |
252b5132 | 980 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
981 | |
982 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
983 | ||
b34976b6 | 984 | static void append_insn |
4d7206a2 | 985 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 986 | static void mips_no_prev_insn (void); |
b34976b6 | 987 | static void mips16_macro_build |
67c0d1eb RS |
988 | (expressionS *, const char *, const char *, va_list); |
989 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
990 | static void macro_start (void); |
991 | static void macro_end (void); | |
17a2f251 TS |
992 | static void macro (struct mips_cl_insn * ip); |
993 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 994 | #ifdef LOSING_COMPILER |
17a2f251 | 995 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 996 | #endif |
17a2f251 TS |
997 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
998 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 999 | static void mips16_immed |
17a2f251 TS |
1000 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1001 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1002 | static size_t my_getSmallExpression |
17a2f251 TS |
1003 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1004 | static void my_getExpression (expressionS *, char *); | |
1005 | static void s_align (int); | |
1006 | static void s_change_sec (int); | |
1007 | static void s_change_section (int); | |
1008 | static void s_cons (int); | |
1009 | static void s_float_cons (int); | |
1010 | static void s_mips_globl (int); | |
1011 | static void s_option (int); | |
1012 | static void s_mipsset (int); | |
1013 | static void s_abicalls (int); | |
1014 | static void s_cpload (int); | |
1015 | static void s_cpsetup (int); | |
1016 | static void s_cplocal (int); | |
1017 | static void s_cprestore (int); | |
1018 | static void s_cpreturn (int); | |
1019 | static void s_gpvalue (int); | |
1020 | static void s_gpword (int); | |
1021 | static void s_gpdword (int); | |
1022 | static void s_cpadd (int); | |
1023 | static void s_insn (int); | |
1024 | static void md_obj_begin (void); | |
1025 | static void md_obj_end (void); | |
1026 | static void s_mips_ent (int); | |
1027 | static void s_mips_end (int); | |
1028 | static void s_mips_frame (int); | |
1029 | static void s_mips_mask (int reg_type); | |
1030 | static void s_mips_stab (int); | |
1031 | static void s_mips_weakext (int); | |
1032 | static void s_mips_file (int); | |
1033 | static void s_mips_loc (int); | |
1034 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1035 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1036 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1037 | |
1038 | /* Table and functions used to map between CPU/ISA names, and | |
1039 | ISA levels, and CPU numbers. */ | |
1040 | ||
e972090a NC |
1041 | struct mips_cpu_info |
1042 | { | |
e7af610e | 1043 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1044 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1045 | int isa; /* ISA level. */ |
1046 | int cpu; /* CPU number (default CPU if ISA). */ | |
1047 | }; | |
1048 | ||
ad3fea08 TS |
1049 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1050 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1051 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1052 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1053 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1054 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
1055 | ||
17a2f251 TS |
1056 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1057 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1058 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1059 | \f |
1060 | /* Pseudo-op table. | |
1061 | ||
1062 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1063 | should be defined here, but are currently unsupported: .alias, | |
1064 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1065 | ||
1066 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1067 | specific to the type of debugging information being generated, and | |
1068 | should be defined by the object format: .aent, .begin, .bend, | |
1069 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1070 | .vreg. | |
1071 | ||
1072 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1073 | not MIPS CPU specific, but are also not specific to the object file | |
1074 | format. This file is probably the best place to define them, but | |
1075 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1076 | .struct. */ | |
1077 | ||
e972090a NC |
1078 | static const pseudo_typeS mips_pseudo_table[] = |
1079 | { | |
beae10d5 | 1080 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1081 | {"option", s_option, 0}, |
1082 | {"set", s_mipsset, 0}, | |
1083 | {"rdata", s_change_sec, 'r'}, | |
1084 | {"sdata", s_change_sec, 's'}, | |
1085 | {"livereg", s_ignore, 0}, | |
1086 | {"abicalls", s_abicalls, 0}, | |
1087 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1088 | {"cpsetup", s_cpsetup, 0}, |
1089 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1090 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1091 | {"cpreturn", s_cpreturn, 0}, |
1092 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1093 | {"gpword", s_gpword, 0}, |
10181a0d | 1094 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1095 | {"cpadd", s_cpadd, 0}, |
1096 | {"insn", s_insn, 0}, | |
1097 | ||
beae10d5 | 1098 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1099 | chips. */ |
1100 | {"asciiz", stringer, 1}, | |
1101 | {"bss", s_change_sec, 'b'}, | |
1102 | {"err", s_err, 0}, | |
1103 | {"half", s_cons, 1}, | |
1104 | {"dword", s_cons, 3}, | |
1105 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1106 | {"origin", s_org, 0}, |
1107 | {"repeat", s_rept, 0}, | |
252b5132 | 1108 | |
beae10d5 | 1109 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1110 | here for one reason or another. */ |
1111 | {"align", s_align, 0}, | |
1112 | {"byte", s_cons, 0}, | |
1113 | {"data", s_change_sec, 'd'}, | |
1114 | {"double", s_float_cons, 'd'}, | |
1115 | {"float", s_float_cons, 'f'}, | |
1116 | {"globl", s_mips_globl, 0}, | |
1117 | {"global", s_mips_globl, 0}, | |
1118 | {"hword", s_cons, 1}, | |
1119 | {"int", s_cons, 2}, | |
1120 | {"long", s_cons, 2}, | |
1121 | {"octa", s_cons, 4}, | |
1122 | {"quad", s_cons, 3}, | |
cca86cc8 | 1123 | {"section", s_change_section, 0}, |
252b5132 RH |
1124 | {"short", s_cons, 1}, |
1125 | {"single", s_float_cons, 'f'}, | |
1126 | {"stabn", s_mips_stab, 'n'}, | |
1127 | {"text", s_change_sec, 't'}, | |
1128 | {"word", s_cons, 2}, | |
add56521 | 1129 | |
add56521 | 1130 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1131 | |
43841e91 | 1132 | { NULL, NULL, 0 }, |
252b5132 RH |
1133 | }; |
1134 | ||
e972090a NC |
1135 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1136 | { | |
beae10d5 KH |
1137 | /* These pseudo-ops should be defined by the object file format. |
1138 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1139 | {"aent", s_mips_ent, 1}, |
1140 | {"bgnb", s_ignore, 0}, | |
1141 | {"end", s_mips_end, 0}, | |
1142 | {"endb", s_ignore, 0}, | |
1143 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1144 | {"file", s_mips_file, 0}, |
252b5132 RH |
1145 | {"fmask", s_mips_mask, 'F'}, |
1146 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1147 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1148 | {"mask", s_mips_mask, 'R'}, |
1149 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1150 | { NULL, NULL, 0 }, |
252b5132 RH |
1151 | }; |
1152 | ||
17a2f251 | 1153 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1154 | |
1155 | void | |
17a2f251 | 1156 | mips_pop_insert (void) |
252b5132 RH |
1157 | { |
1158 | pop_insert (mips_pseudo_table); | |
1159 | if (! ECOFF_DEBUGGING) | |
1160 | pop_insert (mips_nonecoff_pseudo_table); | |
1161 | } | |
1162 | \f | |
1163 | /* Symbols labelling the current insn. */ | |
1164 | ||
e972090a NC |
1165 | struct insn_label_list |
1166 | { | |
252b5132 RH |
1167 | struct insn_label_list *next; |
1168 | symbolS *label; | |
1169 | }; | |
1170 | ||
252b5132 | 1171 | static struct insn_label_list *free_insn_labels; |
a8dbcb85 | 1172 | #define label_list tc_segment_info_data |
252b5132 | 1173 | |
17a2f251 | 1174 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1175 | |
1176 | static inline void | |
17a2f251 | 1177 | mips_clear_insn_labels (void) |
252b5132 RH |
1178 | { |
1179 | register struct insn_label_list **pl; | |
a8dbcb85 | 1180 | segment_info_type *si; |
252b5132 | 1181 | |
a8dbcb85 TS |
1182 | if (now_seg) |
1183 | { | |
1184 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1185 | ; | |
1186 | ||
1187 | si = seg_info (now_seg); | |
1188 | *pl = si->label_list; | |
1189 | si->label_list = NULL; | |
1190 | } | |
252b5132 | 1191 | } |
a8dbcb85 | 1192 | |
252b5132 RH |
1193 | \f |
1194 | static char *expr_end; | |
1195 | ||
1196 | /* Expressions which appear in instructions. These are set by | |
1197 | mips_ip. */ | |
1198 | ||
1199 | static expressionS imm_expr; | |
5f74bc13 | 1200 | static expressionS imm2_expr; |
252b5132 RH |
1201 | static expressionS offset_expr; |
1202 | ||
1203 | /* Relocs associated with imm_expr and offset_expr. */ | |
1204 | ||
f6688943 TS |
1205 | static bfd_reloc_code_real_type imm_reloc[3] |
1206 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1207 | static bfd_reloc_code_real_type offset_reloc[3] | |
1208 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1209 | |
252b5132 RH |
1210 | /* These are set by mips16_ip if an explicit extension is used. */ |
1211 | ||
b34976b6 | 1212 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1213 | |
7ed4a06a | 1214 | #ifdef OBJ_ELF |
ecb4347a DJ |
1215 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1216 | ECOFF debugging. */ | |
252b5132 RH |
1217 | |
1218 | static segT pdr_seg; | |
7ed4a06a | 1219 | #endif |
252b5132 | 1220 | |
e013f690 TS |
1221 | /* The default target format to use. */ |
1222 | ||
1223 | const char * | |
17a2f251 | 1224 | mips_target_format (void) |
e013f690 TS |
1225 | { |
1226 | switch (OUTPUT_FLAVOR) | |
1227 | { | |
e013f690 TS |
1228 | case bfd_target_ecoff_flavour: |
1229 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1230 | case bfd_target_coff_flavour: | |
1231 | return "pe-mips"; | |
1232 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1233 | #ifdef TE_VXWORKS |
1234 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1235 | return (target_big_endian | |
1236 | ? "elf32-bigmips-vxworks" | |
1237 | : "elf32-littlemips-vxworks"); | |
1238 | #endif | |
e013f690 | 1239 | #ifdef TE_TMIPS |
cfe86eaa | 1240 | /* This is traditional mips. */ |
e013f690 | 1241 | return (target_big_endian |
cfe86eaa TS |
1242 | ? (HAVE_64BIT_OBJECTS |
1243 | ? "elf64-tradbigmips" | |
1244 | : (HAVE_NEWABI | |
1245 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1246 | : (HAVE_64BIT_OBJECTS | |
1247 | ? "elf64-tradlittlemips" | |
1248 | : (HAVE_NEWABI | |
1249 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1250 | #else |
1251 | return (target_big_endian | |
cfe86eaa TS |
1252 | ? (HAVE_64BIT_OBJECTS |
1253 | ? "elf64-bigmips" | |
1254 | : (HAVE_NEWABI | |
1255 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1256 | : (HAVE_64BIT_OBJECTS | |
1257 | ? "elf64-littlemips" | |
1258 | : (HAVE_NEWABI | |
1259 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1260 | #endif |
1261 | default: | |
1262 | abort (); | |
1263 | return NULL; | |
1264 | } | |
1265 | } | |
1266 | ||
1e915849 RS |
1267 | /* Return the length of instruction INSN. */ |
1268 | ||
1269 | static inline unsigned int | |
1270 | insn_length (const struct mips_cl_insn *insn) | |
1271 | { | |
1272 | if (!mips_opts.mips16) | |
1273 | return 4; | |
1274 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1275 | } | |
1276 | ||
1277 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1278 | ||
1279 | static void | |
1280 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1281 | { | |
1282 | size_t i; | |
1283 | ||
1284 | insn->insn_mo = mo; | |
1285 | insn->use_extend = FALSE; | |
1286 | insn->extend = 0; | |
1287 | insn->insn_opcode = mo->match; | |
1288 | insn->frag = NULL; | |
1289 | insn->where = 0; | |
1290 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1291 | insn->fixp[i] = NULL; | |
1292 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1293 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1294 | insn->mips16_absolute_jump_p = 0; | |
1295 | } | |
1296 | ||
1297 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1298 | ||
1299 | static void | |
1300 | install_insn (const struct mips_cl_insn *insn) | |
1301 | { | |
1302 | char *f = insn->frag->fr_literal + insn->where; | |
1303 | if (!mips_opts.mips16) | |
1304 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1305 | else if (insn->mips16_absolute_jump_p) | |
1306 | { | |
1307 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1308 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1309 | } | |
1310 | else | |
1311 | { | |
1312 | if (insn->use_extend) | |
1313 | { | |
1314 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1315 | f += 2; | |
1316 | } | |
1317 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1322 | and install the opcode in the new location. */ | |
1323 | ||
1324 | static void | |
1325 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1326 | { | |
1327 | size_t i; | |
1328 | ||
1329 | insn->frag = frag; | |
1330 | insn->where = where; | |
1331 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1332 | if (insn->fixp[i] != NULL) | |
1333 | { | |
1334 | insn->fixp[i]->fx_frag = frag; | |
1335 | insn->fixp[i]->fx_where = where; | |
1336 | } | |
1337 | install_insn (insn); | |
1338 | } | |
1339 | ||
1340 | /* Add INSN to the end of the output. */ | |
1341 | ||
1342 | static void | |
1343 | add_fixed_insn (struct mips_cl_insn *insn) | |
1344 | { | |
1345 | char *f = frag_more (insn_length (insn)); | |
1346 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1347 | } | |
1348 | ||
1349 | /* Start a variant frag and move INSN to the start of the variant part, | |
1350 | marking it as fixed. The other arguments are as for frag_var. */ | |
1351 | ||
1352 | static void | |
1353 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1354 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1355 | { | |
1356 | frag_grow (max_chars); | |
1357 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1358 | insn->fixed_p = 1; | |
1359 | frag_var (rs_machine_dependent, max_chars, var, | |
1360 | subtype, symbol, offset, NULL); | |
1361 | } | |
1362 | ||
1363 | /* Insert N copies of INSN into the history buffer, starting at | |
1364 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1365 | ||
1366 | static void | |
1367 | insert_into_history (unsigned int first, unsigned int n, | |
1368 | const struct mips_cl_insn *insn) | |
1369 | { | |
1370 | if (mips_relax.sequence != 2) | |
1371 | { | |
1372 | unsigned int i; | |
1373 | ||
1374 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1375 | if (i >= first + n) | |
1376 | history[i] = history[i - n]; | |
1377 | else | |
1378 | history[i] = *insn; | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1383 | ||
1384 | static void | |
1385 | emit_nop (void) | |
1386 | { | |
1387 | add_fixed_insn (NOP_INSN); | |
1388 | insert_into_history (0, 1, NOP_INSN); | |
1389 | } | |
1390 | ||
71400594 RS |
1391 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1392 | the idea is to make it obvious at a glance that each errata is | |
1393 | included. */ | |
1394 | ||
1395 | static void | |
1396 | init_vr4120_conflicts (void) | |
1397 | { | |
1398 | #define CONFLICT(FIRST, SECOND) \ | |
1399 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1400 | ||
1401 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1402 | CONFLICT (MACC, DIV); | |
1403 | CONFLICT (DMACC, DIV); | |
1404 | ||
1405 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1406 | CONFLICT (DMULT, DMULT); | |
1407 | CONFLICT (DMULT, DMACC); | |
1408 | CONFLICT (DMACC, DMULT); | |
1409 | CONFLICT (DMACC, DMACC); | |
1410 | ||
1411 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1412 | CONFLICT (MACC, MTHILO); | |
1413 | CONFLICT (DMACC, MTHILO); | |
1414 | ||
1415 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1416 | instruction is executed immediately after a MACC or DMACC | |
1417 | instruction, the result of [either instruction] is incorrect." */ | |
1418 | CONFLICT (MACC, MULT); | |
1419 | CONFLICT (MACC, DMULT); | |
1420 | CONFLICT (DMACC, MULT); | |
1421 | CONFLICT (DMACC, DMULT); | |
1422 | ||
1423 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1424 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1425 | DDIV or DDIVU instruction, the result of the MACC or | |
1426 | DMACC instruction is incorrect.". */ | |
1427 | CONFLICT (DMULT, MACC); | |
1428 | CONFLICT (DMULT, DMACC); | |
1429 | CONFLICT (DIV, MACC); | |
1430 | CONFLICT (DIV, DMACC); | |
1431 | ||
1432 | #undef CONFLICT | |
1433 | } | |
1434 | ||
707bfff6 TS |
1435 | struct regname { |
1436 | const char *name; | |
1437 | unsigned int num; | |
1438 | }; | |
1439 | ||
1440 | #define RTYPE_MASK 0x1ff00 | |
1441 | #define RTYPE_NUM 0x00100 | |
1442 | #define RTYPE_FPU 0x00200 | |
1443 | #define RTYPE_FCC 0x00400 | |
1444 | #define RTYPE_VEC 0x00800 | |
1445 | #define RTYPE_GP 0x01000 | |
1446 | #define RTYPE_CP0 0x02000 | |
1447 | #define RTYPE_PC 0x04000 | |
1448 | #define RTYPE_ACC 0x08000 | |
1449 | #define RTYPE_CCC 0x10000 | |
1450 | #define RNUM_MASK 0x000ff | |
1451 | #define RWARN 0x80000 | |
1452 | ||
1453 | #define GENERIC_REGISTER_NUMBERS \ | |
1454 | {"$0", RTYPE_NUM | 0}, \ | |
1455 | {"$1", RTYPE_NUM | 1}, \ | |
1456 | {"$2", RTYPE_NUM | 2}, \ | |
1457 | {"$3", RTYPE_NUM | 3}, \ | |
1458 | {"$4", RTYPE_NUM | 4}, \ | |
1459 | {"$5", RTYPE_NUM | 5}, \ | |
1460 | {"$6", RTYPE_NUM | 6}, \ | |
1461 | {"$7", RTYPE_NUM | 7}, \ | |
1462 | {"$8", RTYPE_NUM | 8}, \ | |
1463 | {"$9", RTYPE_NUM | 9}, \ | |
1464 | {"$10", RTYPE_NUM | 10}, \ | |
1465 | {"$11", RTYPE_NUM | 11}, \ | |
1466 | {"$12", RTYPE_NUM | 12}, \ | |
1467 | {"$13", RTYPE_NUM | 13}, \ | |
1468 | {"$14", RTYPE_NUM | 14}, \ | |
1469 | {"$15", RTYPE_NUM | 15}, \ | |
1470 | {"$16", RTYPE_NUM | 16}, \ | |
1471 | {"$17", RTYPE_NUM | 17}, \ | |
1472 | {"$18", RTYPE_NUM | 18}, \ | |
1473 | {"$19", RTYPE_NUM | 19}, \ | |
1474 | {"$20", RTYPE_NUM | 20}, \ | |
1475 | {"$21", RTYPE_NUM | 21}, \ | |
1476 | {"$22", RTYPE_NUM | 22}, \ | |
1477 | {"$23", RTYPE_NUM | 23}, \ | |
1478 | {"$24", RTYPE_NUM | 24}, \ | |
1479 | {"$25", RTYPE_NUM | 25}, \ | |
1480 | {"$26", RTYPE_NUM | 26}, \ | |
1481 | {"$27", RTYPE_NUM | 27}, \ | |
1482 | {"$28", RTYPE_NUM | 28}, \ | |
1483 | {"$29", RTYPE_NUM | 29}, \ | |
1484 | {"$30", RTYPE_NUM | 30}, \ | |
1485 | {"$31", RTYPE_NUM | 31} | |
1486 | ||
1487 | #define FPU_REGISTER_NAMES \ | |
1488 | {"$f0", RTYPE_FPU | 0}, \ | |
1489 | {"$f1", RTYPE_FPU | 1}, \ | |
1490 | {"$f2", RTYPE_FPU | 2}, \ | |
1491 | {"$f3", RTYPE_FPU | 3}, \ | |
1492 | {"$f4", RTYPE_FPU | 4}, \ | |
1493 | {"$f5", RTYPE_FPU | 5}, \ | |
1494 | {"$f6", RTYPE_FPU | 6}, \ | |
1495 | {"$f7", RTYPE_FPU | 7}, \ | |
1496 | {"$f8", RTYPE_FPU | 8}, \ | |
1497 | {"$f9", RTYPE_FPU | 9}, \ | |
1498 | {"$f10", RTYPE_FPU | 10}, \ | |
1499 | {"$f11", RTYPE_FPU | 11}, \ | |
1500 | {"$f12", RTYPE_FPU | 12}, \ | |
1501 | {"$f13", RTYPE_FPU | 13}, \ | |
1502 | {"$f14", RTYPE_FPU | 14}, \ | |
1503 | {"$f15", RTYPE_FPU | 15}, \ | |
1504 | {"$f16", RTYPE_FPU | 16}, \ | |
1505 | {"$f17", RTYPE_FPU | 17}, \ | |
1506 | {"$f18", RTYPE_FPU | 18}, \ | |
1507 | {"$f19", RTYPE_FPU | 19}, \ | |
1508 | {"$f20", RTYPE_FPU | 20}, \ | |
1509 | {"$f21", RTYPE_FPU | 21}, \ | |
1510 | {"$f22", RTYPE_FPU | 22}, \ | |
1511 | {"$f23", RTYPE_FPU | 23}, \ | |
1512 | {"$f24", RTYPE_FPU | 24}, \ | |
1513 | {"$f25", RTYPE_FPU | 25}, \ | |
1514 | {"$f26", RTYPE_FPU | 26}, \ | |
1515 | {"$f27", RTYPE_FPU | 27}, \ | |
1516 | {"$f28", RTYPE_FPU | 28}, \ | |
1517 | {"$f29", RTYPE_FPU | 29}, \ | |
1518 | {"$f30", RTYPE_FPU | 30}, \ | |
1519 | {"$f31", RTYPE_FPU | 31} | |
1520 | ||
1521 | #define FPU_CONDITION_CODE_NAMES \ | |
1522 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1523 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1524 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1525 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1526 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1527 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1528 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1529 | {"$fcc7", RTYPE_FCC | 7} | |
1530 | ||
1531 | #define COPROC_CONDITION_CODE_NAMES \ | |
1532 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1533 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1534 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1535 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1536 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1537 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1538 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1539 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1540 | ||
1541 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1542 | {"$a4", RTYPE_GP | 8}, \ | |
1543 | {"$a5", RTYPE_GP | 9}, \ | |
1544 | {"$a6", RTYPE_GP | 10}, \ | |
1545 | {"$a7", RTYPE_GP | 11}, \ | |
1546 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1547 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1548 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1549 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1550 | {"$t0", RTYPE_GP | 12}, \ | |
1551 | {"$t1", RTYPE_GP | 13}, \ | |
1552 | {"$t2", RTYPE_GP | 14}, \ | |
1553 | {"$t3", RTYPE_GP | 15} | |
1554 | ||
1555 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1556 | {"$t0", RTYPE_GP | 8}, \ | |
1557 | {"$t1", RTYPE_GP | 9}, \ | |
1558 | {"$t2", RTYPE_GP | 10}, \ | |
1559 | {"$t3", RTYPE_GP | 11}, \ | |
1560 | {"$t4", RTYPE_GP | 12}, \ | |
1561 | {"$t5", RTYPE_GP | 13}, \ | |
1562 | {"$t6", RTYPE_GP | 14}, \ | |
1563 | {"$t7", RTYPE_GP | 15}, \ | |
1564 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1565 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1566 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1567 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1568 | ||
1569 | /* Remaining symbolic register names */ | |
1570 | #define SYMBOLIC_REGISTER_NAMES \ | |
1571 | {"$zero", RTYPE_GP | 0}, \ | |
1572 | {"$at", RTYPE_GP | 1}, \ | |
1573 | {"$AT", RTYPE_GP | 1}, \ | |
1574 | {"$v0", RTYPE_GP | 2}, \ | |
1575 | {"$v1", RTYPE_GP | 3}, \ | |
1576 | {"$a0", RTYPE_GP | 4}, \ | |
1577 | {"$a1", RTYPE_GP | 5}, \ | |
1578 | {"$a2", RTYPE_GP | 6}, \ | |
1579 | {"$a3", RTYPE_GP | 7}, \ | |
1580 | {"$s0", RTYPE_GP | 16}, \ | |
1581 | {"$s1", RTYPE_GP | 17}, \ | |
1582 | {"$s2", RTYPE_GP | 18}, \ | |
1583 | {"$s3", RTYPE_GP | 19}, \ | |
1584 | {"$s4", RTYPE_GP | 20}, \ | |
1585 | {"$s5", RTYPE_GP | 21}, \ | |
1586 | {"$s6", RTYPE_GP | 22}, \ | |
1587 | {"$s7", RTYPE_GP | 23}, \ | |
1588 | {"$t8", RTYPE_GP | 24}, \ | |
1589 | {"$t9", RTYPE_GP | 25}, \ | |
1590 | {"$k0", RTYPE_GP | 26}, \ | |
1591 | {"$kt0", RTYPE_GP | 26}, \ | |
1592 | {"$k1", RTYPE_GP | 27}, \ | |
1593 | {"$kt1", RTYPE_GP | 27}, \ | |
1594 | {"$gp", RTYPE_GP | 28}, \ | |
1595 | {"$sp", RTYPE_GP | 29}, \ | |
1596 | {"$s8", RTYPE_GP | 30}, \ | |
1597 | {"$fp", RTYPE_GP | 30}, \ | |
1598 | {"$ra", RTYPE_GP | 31} | |
1599 | ||
1600 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1601 | {"$pc", RTYPE_PC | 0} | |
1602 | ||
1603 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1604 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1605 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1606 | {"$v2", RTYPE_VEC | 2}, \ | |
1607 | {"$v3", RTYPE_VEC | 3}, \ | |
1608 | {"$v4", RTYPE_VEC | 4}, \ | |
1609 | {"$v5", RTYPE_VEC | 5}, \ | |
1610 | {"$v6", RTYPE_VEC | 6}, \ | |
1611 | {"$v7", RTYPE_VEC | 7}, \ | |
1612 | {"$v8", RTYPE_VEC | 8}, \ | |
1613 | {"$v9", RTYPE_VEC | 9}, \ | |
1614 | {"$v10", RTYPE_VEC | 10}, \ | |
1615 | {"$v11", RTYPE_VEC | 11}, \ | |
1616 | {"$v12", RTYPE_VEC | 12}, \ | |
1617 | {"$v13", RTYPE_VEC | 13}, \ | |
1618 | {"$v14", RTYPE_VEC | 14}, \ | |
1619 | {"$v15", RTYPE_VEC | 15}, \ | |
1620 | {"$v16", RTYPE_VEC | 16}, \ | |
1621 | {"$v17", RTYPE_VEC | 17}, \ | |
1622 | {"$v18", RTYPE_VEC | 18}, \ | |
1623 | {"$v19", RTYPE_VEC | 19}, \ | |
1624 | {"$v20", RTYPE_VEC | 20}, \ | |
1625 | {"$v21", RTYPE_VEC | 21}, \ | |
1626 | {"$v22", RTYPE_VEC | 22}, \ | |
1627 | {"$v23", RTYPE_VEC | 23}, \ | |
1628 | {"$v24", RTYPE_VEC | 24}, \ | |
1629 | {"$v25", RTYPE_VEC | 25}, \ | |
1630 | {"$v26", RTYPE_VEC | 26}, \ | |
1631 | {"$v27", RTYPE_VEC | 27}, \ | |
1632 | {"$v28", RTYPE_VEC | 28}, \ | |
1633 | {"$v29", RTYPE_VEC | 29}, \ | |
1634 | {"$v30", RTYPE_VEC | 30}, \ | |
1635 | {"$v31", RTYPE_VEC | 31} | |
1636 | ||
1637 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1638 | {"$ac0", RTYPE_ACC | 0}, \ | |
1639 | {"$ac1", RTYPE_ACC | 1}, \ | |
1640 | {"$ac2", RTYPE_ACC | 2}, \ | |
1641 | {"$ac3", RTYPE_ACC | 3} | |
1642 | ||
1643 | static const struct regname reg_names[] = { | |
1644 | GENERIC_REGISTER_NUMBERS, | |
1645 | FPU_REGISTER_NAMES, | |
1646 | FPU_CONDITION_CODE_NAMES, | |
1647 | COPROC_CONDITION_CODE_NAMES, | |
1648 | ||
1649 | /* The $txx registers depends on the abi, | |
1650 | these will be added later into the symbol table from | |
1651 | one of the tables below once mips_abi is set after | |
1652 | parsing of arguments from the command line. */ | |
1653 | SYMBOLIC_REGISTER_NAMES, | |
1654 | ||
1655 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1656 | MDMX_VECTOR_REGISTER_NAMES, | |
1657 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1658 | {0, 0} | |
1659 | }; | |
1660 | ||
1661 | static const struct regname reg_names_o32[] = { | |
1662 | O32_SYMBOLIC_REGISTER_NAMES, | |
1663 | {0, 0} | |
1664 | }; | |
1665 | ||
1666 | static const struct regname reg_names_n32n64[] = { | |
1667 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1668 | {0, 0} | |
1669 | }; | |
1670 | ||
1671 | static int | |
1672 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1673 | { | |
1674 | symbolS *symbolP; | |
1675 | char *e; | |
1676 | char save_c; | |
1677 | int reg = -1; | |
1678 | ||
1679 | /* Find end of name. */ | |
1680 | e = *s; | |
1681 | if (is_name_beginner (*e)) | |
1682 | ++e; | |
1683 | while (is_part_of_name (*e)) | |
1684 | ++e; | |
1685 | ||
1686 | /* Terminate name. */ | |
1687 | save_c = *e; | |
1688 | *e = '\0'; | |
1689 | ||
1690 | /* Look for a register symbol. */ | |
1691 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1692 | { | |
1693 | int r = S_GET_VALUE (symbolP); | |
1694 | if (r & types) | |
1695 | reg = r & RNUM_MASK; | |
1696 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1697 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1698 | reg = (r & RNUM_MASK) - 2; | |
1699 | } | |
1700 | /* Else see if this is a register defined in an itbl entry. */ | |
1701 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1702 | { | |
1703 | char *n = *s; | |
1704 | unsigned long r; | |
1705 | ||
1706 | if (*n == '$') | |
1707 | ++n; | |
1708 | if (itbl_get_reg_val (n, &r)) | |
1709 | reg = r & RNUM_MASK; | |
1710 | } | |
1711 | ||
1712 | /* Advance to next token if a register was recognised. */ | |
1713 | if (reg >= 0) | |
1714 | *s = e; | |
1715 | else if (types & RWARN) | |
1716 | as_warn ("Unrecognized register name `%s'", *s); | |
1717 | ||
1718 | *e = save_c; | |
1719 | if (regnop) | |
1720 | *regnop = reg; | |
1721 | return reg >= 0; | |
1722 | } | |
1723 | ||
1724 | /* This function is called once, at assembler startup time. It should set up | |
1725 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1726 | |
252b5132 | 1727 | void |
17a2f251 | 1728 | md_begin (void) |
252b5132 | 1729 | { |
3994f87e | 1730 | const char *retval = NULL; |
156c2f8b | 1731 | int i = 0; |
252b5132 | 1732 | int broken = 0; |
1f25f5d3 | 1733 | |
0a44bf69 RS |
1734 | if (mips_pic != NO_PIC) |
1735 | { | |
1736 | if (g_switch_seen && g_switch_value != 0) | |
1737 | as_bad (_("-G may not be used in position-independent code")); | |
1738 | g_switch_value = 0; | |
1739 | } | |
1740 | ||
fef14a42 | 1741 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1742 | as_warn (_("Could not set architecture and machine")); |
1743 | ||
252b5132 RH |
1744 | op_hash = hash_new (); |
1745 | ||
1746 | for (i = 0; i < NUMOPCODES;) | |
1747 | { | |
1748 | const char *name = mips_opcodes[i].name; | |
1749 | ||
17a2f251 | 1750 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1751 | if (retval != NULL) |
1752 | { | |
1753 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1754 | mips_opcodes[i].name, retval); | |
1755 | /* Probably a memory allocation problem? Give up now. */ | |
1756 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1757 | } | |
1758 | do | |
1759 | { | |
1760 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1761 | { | |
1762 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1763 | broken = 1; | |
1e915849 RS |
1764 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1765 | { | |
1766 | create_insn (&nop_insn, mips_opcodes + i); | |
1767 | nop_insn.fixed_p = 1; | |
1768 | } | |
252b5132 RH |
1769 | } |
1770 | ++i; | |
1771 | } | |
1772 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1773 | } | |
1774 | ||
1775 | mips16_op_hash = hash_new (); | |
1776 | ||
1777 | i = 0; | |
1778 | while (i < bfd_mips16_num_opcodes) | |
1779 | { | |
1780 | const char *name = mips16_opcodes[i].name; | |
1781 | ||
17a2f251 | 1782 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1783 | if (retval != NULL) |
1784 | as_fatal (_("internal: can't hash `%s': %s"), | |
1785 | mips16_opcodes[i].name, retval); | |
1786 | do | |
1787 | { | |
1788 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1789 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1790 | != mips16_opcodes[i].match)) | |
1791 | { | |
1792 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1793 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1794 | broken = 1; | |
1795 | } | |
1e915849 RS |
1796 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1797 | { | |
1798 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1799 | mips16_nop_insn.fixed_p = 1; | |
1800 | } | |
252b5132 RH |
1801 | ++i; |
1802 | } | |
1803 | while (i < bfd_mips16_num_opcodes | |
1804 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1805 | } | |
1806 | ||
1807 | if (broken) | |
1808 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1809 | ||
1810 | /* We add all the general register names to the symbol table. This | |
1811 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1812 | for (i = 0; reg_names[i].name; i++) |
1813 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
1814 | reg_names[i].num, // & RNUM_MASK, | |
1815 | &zero_address_frag)); | |
1816 | if (HAVE_NEWABI) | |
1817 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1818 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
1819 | reg_names_n32n64[i].num, // & RNUM_MASK, | |
252b5132 | 1820 | &zero_address_frag)); |
707bfff6 TS |
1821 | else |
1822 | for (i = 0; reg_names_o32[i].name; i++) | |
1823 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
1824 | reg_names_o32[i].num, // & RNUM_MASK, | |
6047c971 | 1825 | &zero_address_frag)); |
6047c971 | 1826 | |
7d10b47d | 1827 | mips_no_prev_insn (); |
252b5132 RH |
1828 | |
1829 | mips_gprmask = 0; | |
1830 | mips_cprmask[0] = 0; | |
1831 | mips_cprmask[1] = 0; | |
1832 | mips_cprmask[2] = 0; | |
1833 | mips_cprmask[3] = 0; | |
1834 | ||
1835 | /* set the default alignment for the text section (2**2) */ | |
1836 | record_alignment (text_section, 2); | |
1837 | ||
4d0d148d | 1838 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 1839 | |
707bfff6 | 1840 | #ifdef OBJ_ELF |
252b5132 RH |
1841 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1842 | { | |
0a44bf69 RS |
1843 | /* On a native system other than VxWorks, sections must be aligned |
1844 | to 16 byte boundaries. When configured for an embedded ELF | |
1845 | target, we don't bother. */ | |
1846 | if (strcmp (TARGET_OS, "elf") != 0 | |
1847 | && strcmp (TARGET_OS, "vxworks") != 0) | |
252b5132 RH |
1848 | { |
1849 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1850 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1851 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1852 | } | |
1853 | ||
1854 | /* Create a .reginfo section for register masks and a .mdebug | |
1855 | section for debugging information. */ | |
1856 | { | |
1857 | segT seg; | |
1858 | subsegT subseg; | |
1859 | flagword flags; | |
1860 | segT sec; | |
1861 | ||
1862 | seg = now_seg; | |
1863 | subseg = now_subseg; | |
1864 | ||
1865 | /* The ABI says this section should be loaded so that the | |
1866 | running program can access it. However, we don't load it | |
1867 | if we are configured for an embedded target */ | |
1868 | flags = SEC_READONLY | SEC_DATA; | |
1869 | if (strcmp (TARGET_OS, "elf") != 0) | |
1870 | flags |= SEC_ALLOC | SEC_LOAD; | |
1871 | ||
316f5878 | 1872 | if (mips_abi != N64_ABI) |
252b5132 RH |
1873 | { |
1874 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1875 | ||
195325d2 TS |
1876 | bfd_set_section_flags (stdoutput, sec, flags); |
1877 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1878 | |
252b5132 | 1879 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
1880 | } |
1881 | else | |
1882 | { | |
1883 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1884 | .reginfo section. */ | |
1885 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1886 | bfd_set_section_flags (stdoutput, sec, flags); |
1887 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 1888 | |
252b5132 RH |
1889 | /* Set up the option header. */ |
1890 | { | |
1891 | Elf_Internal_Options opthdr; | |
1892 | char *f; | |
1893 | ||
1894 | opthdr.kind = ODK_REGINFO; | |
1895 | opthdr.size = (sizeof (Elf_External_Options) | |
1896 | + sizeof (Elf64_External_RegInfo)); | |
1897 | opthdr.section = 0; | |
1898 | opthdr.info = 0; | |
1899 | f = frag_more (sizeof (Elf_External_Options)); | |
1900 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1901 | (Elf_External_Options *) f); | |
1902 | ||
1903 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1904 | } | |
252b5132 RH |
1905 | } |
1906 | ||
1907 | if (ECOFF_DEBUGGING) | |
1908 | { | |
1909 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1910 | (void) bfd_set_section_flags (stdoutput, sec, | |
1911 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1912 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1913 | } | |
dcd410fe | 1914 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1915 | { |
1916 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1917 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1918 | SEC_READONLY | SEC_RELOC | |
1919 | | SEC_DEBUGGING); | |
1920 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1921 | } | |
252b5132 RH |
1922 | |
1923 | subseg_set (seg, subseg); | |
1924 | } | |
1925 | } | |
707bfff6 | 1926 | #endif /* OBJ_ELF */ |
252b5132 RH |
1927 | |
1928 | if (! ECOFF_DEBUGGING) | |
1929 | md_obj_begin (); | |
71400594 RS |
1930 | |
1931 | if (mips_fix_vr4120) | |
1932 | init_vr4120_conflicts (); | |
252b5132 RH |
1933 | } |
1934 | ||
1935 | void | |
17a2f251 | 1936 | md_mips_end (void) |
252b5132 RH |
1937 | { |
1938 | if (! ECOFF_DEBUGGING) | |
1939 | md_obj_end (); | |
1940 | } | |
1941 | ||
1942 | void | |
17a2f251 | 1943 | md_assemble (char *str) |
252b5132 RH |
1944 | { |
1945 | struct mips_cl_insn insn; | |
f6688943 TS |
1946 | bfd_reloc_code_real_type unused_reloc[3] |
1947 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1948 | |
1949 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1950 | imm2_expr.X_op = O_absent; |
252b5132 | 1951 | offset_expr.X_op = O_absent; |
f6688943 TS |
1952 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1953 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1954 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1955 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1956 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1957 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1958 | |
1959 | if (mips_opts.mips16) | |
1960 | mips16_ip (str, &insn); | |
1961 | else | |
1962 | { | |
1963 | mips_ip (str, &insn); | |
beae10d5 KH |
1964 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1965 | str, insn.insn_opcode)); | |
252b5132 RH |
1966 | } |
1967 | ||
1968 | if (insn_error) | |
1969 | { | |
1970 | as_bad ("%s `%s'", insn_error, str); | |
1971 | return; | |
1972 | } | |
1973 | ||
1974 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1975 | { | |
584892a6 | 1976 | macro_start (); |
252b5132 RH |
1977 | if (mips_opts.mips16) |
1978 | mips16_macro (&insn); | |
1979 | else | |
1980 | macro (&insn); | |
584892a6 | 1981 | macro_end (); |
252b5132 RH |
1982 | } |
1983 | else | |
1984 | { | |
1985 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1986 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1987 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1988 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1989 | else |
4d7206a2 | 1990 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1991 | } |
1992 | } | |
1993 | ||
5919d012 | 1994 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
1995 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
1996 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
1997 | |
1998 | static inline bfd_boolean | |
17a2f251 | 1999 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2000 | { |
3b91255e RS |
2001 | return (HAVE_IN_PLACE_ADDENDS |
2002 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
2003 | || reloc == BFD_RELOC_MIPS16_HI16_S |
2004 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
2005 | all GOT16 relocations evaluate to "G". */ | |
2006 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
2007 | } |
2008 | ||
2009 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2010 | relocation. */ | |
2011 | ||
2012 | static inline bfd_boolean | |
17a2f251 | 2013 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2014 | { |
2015 | return (fixp->fx_next != NULL | |
d6f16593 MR |
2016 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
2017 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
2018 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2019 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2020 | } | |
2021 | ||
252b5132 RH |
2022 | /* See whether instruction IP reads register REG. CLASS is the type |
2023 | of register. */ | |
2024 | ||
2025 | static int | |
71400594 | 2026 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 2027 | enum mips_regclass class) |
252b5132 RH |
2028 | { |
2029 | if (class == MIPS16_REG) | |
2030 | { | |
2031 | assert (mips_opts.mips16); | |
2032 | reg = mips16_to_32_reg_map[reg]; | |
2033 | class = MIPS_GR_REG; | |
2034 | } | |
2035 | ||
85b51719 TS |
2036 | /* Don't report on general register ZERO, since it never changes. */ |
2037 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
2038 | return 0; |
2039 | ||
2040 | if (class == MIPS_FP_REG) | |
2041 | { | |
2042 | assert (! mips_opts.mips16); | |
2043 | /* If we are called with either $f0 or $f1, we must check $f0. | |
2044 | This is not optimal, because it will introduce an unnecessary | |
2045 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2046 | need to distinguish reading both $f0 and $f1 or just one of | |
2047 | them. Note that we don't have to check the other way, | |
2048 | because there is no instruction that sets both $f0 and $f1 | |
2049 | and requires a delay. */ | |
2050 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2051 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2052 | == (reg &~ (unsigned) 1))) |
2053 | return 1; | |
2054 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2055 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2056 | == (reg &~ (unsigned) 1))) |
2057 | return 1; | |
2058 | } | |
2059 | else if (! mips_opts.mips16) | |
2060 | { | |
2061 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2062 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2063 | return 1; |
2064 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2065 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2066 | return 1; |
2067 | } | |
2068 | else | |
2069 | { | |
2070 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2071 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2072 | return 1; |
2073 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2074 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2075 | return 1; |
2076 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2077 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2078 | == reg)) |
2079 | return 1; | |
2080 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2081 | return 1; | |
2082 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2083 | return 1; | |
2084 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2085 | return 1; | |
2086 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2087 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2088 | return 1; |
2089 | } | |
2090 | ||
2091 | return 0; | |
2092 | } | |
2093 | ||
2094 | /* This function returns true if modifying a register requires a | |
2095 | delay. */ | |
2096 | ||
2097 | static int | |
17a2f251 | 2098 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2099 | { |
2100 | unsigned long prev_pinfo; | |
2101 | ||
47e39b9d | 2102 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2103 | if (! mips_opts.noreorder |
81912461 ILT |
2104 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2105 | && ! gpr_interlocks) | |
2106 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2107 | && ! cop_interlocks))) | |
252b5132 | 2108 | { |
81912461 ILT |
2109 | /* A load from a coprocessor or from memory. All load delays |
2110 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2111 | /* Itbl support may require additional care here. */ |
252b5132 | 2112 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2113 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2114 | return 1; |
2115 | } | |
2116 | ||
2117 | return 0; | |
2118 | } | |
2119 | ||
404a8071 RS |
2120 | /* Move all labels in insn_labels to the current insertion point. */ |
2121 | ||
2122 | static void | |
2123 | mips_move_labels (void) | |
2124 | { | |
a8dbcb85 | 2125 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2126 | struct insn_label_list *l; |
2127 | valueT val; | |
2128 | ||
a8dbcb85 | 2129 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 RS |
2130 | { |
2131 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
2132 | symbol_set_frag (l->label, frag_now); | |
2133 | val = (valueT) frag_now_fix (); | |
2134 | /* mips16 text labels are stored as odd. */ | |
2135 | if (mips_opts.mips16) | |
2136 | ++val; | |
2137 | S_SET_VALUE (l->label, val); | |
2138 | } | |
2139 | } | |
2140 | ||
252b5132 RH |
2141 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2142 | handle them specially, such as generating jalx instructions when | |
2143 | needed. We also make them odd for the duration of the assembly, in | |
2144 | order to generate the right sort of code. We will make them even | |
2145 | in the adjust_symtab routine, while leaving them marked. This is | |
2146 | convenient for the debugger and the disassembler. The linker knows | |
2147 | to make them odd again. */ | |
2148 | ||
2149 | static void | |
17a2f251 | 2150 | mips16_mark_labels (void) |
252b5132 | 2151 | { |
a8dbcb85 TS |
2152 | segment_info_type *si = seg_info (now_seg); |
2153 | struct insn_label_list *l; | |
252b5132 | 2154 | |
a8dbcb85 TS |
2155 | if (!mips_opts.mips16) |
2156 | return; | |
2157 | ||
2158 | for (l = si->label_list; l != NULL; l = l->next) | |
2159 | { | |
2160 | symbolS *label = l->label; | |
2161 | ||
2162 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
2163 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2164 | S_SET_OTHER (label, STO_MIPS16); | |
252b5132 | 2165 | #endif |
a8dbcb85 TS |
2166 | if ((S_GET_VALUE (label) & 1) == 0) |
2167 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
252b5132 RH |
2168 | } |
2169 | } | |
2170 | ||
4d7206a2 RS |
2171 | /* End the current frag. Make it a variant frag and record the |
2172 | relaxation info. */ | |
2173 | ||
2174 | static void | |
2175 | relax_close_frag (void) | |
2176 | { | |
584892a6 | 2177 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2178 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2179 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2180 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2181 | ||
2182 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2183 | mips_relax.first_fixup = 0; | |
2184 | } | |
2185 | ||
2186 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2187 | See the comment above RELAX_ENCODE for more details. */ | |
2188 | ||
2189 | static void | |
2190 | relax_start (symbolS *symbol) | |
2191 | { | |
2192 | assert (mips_relax.sequence == 0); | |
2193 | mips_relax.sequence = 1; | |
2194 | mips_relax.symbol = symbol; | |
2195 | } | |
2196 | ||
2197 | /* Start generating the second version of a relaxable sequence. | |
2198 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2199 | |
2200 | static void | |
4d7206a2 RS |
2201 | relax_switch (void) |
2202 | { | |
2203 | assert (mips_relax.sequence == 1); | |
2204 | mips_relax.sequence = 2; | |
2205 | } | |
2206 | ||
2207 | /* End the current relaxable sequence. */ | |
2208 | ||
2209 | static void | |
2210 | relax_end (void) | |
2211 | { | |
2212 | assert (mips_relax.sequence == 2); | |
2213 | relax_close_frag (); | |
2214 | mips_relax.sequence = 0; | |
2215 | } | |
2216 | ||
71400594 RS |
2217 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2218 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2219 | by VR4120 errata. */ | |
4d7206a2 | 2220 | |
71400594 RS |
2221 | static unsigned int |
2222 | classify_vr4120_insn (const char *name) | |
252b5132 | 2223 | { |
71400594 RS |
2224 | if (strncmp (name, "macc", 4) == 0) |
2225 | return FIX_VR4120_MACC; | |
2226 | if (strncmp (name, "dmacc", 5) == 0) | |
2227 | return FIX_VR4120_DMACC; | |
2228 | if (strncmp (name, "mult", 4) == 0) | |
2229 | return FIX_VR4120_MULT; | |
2230 | if (strncmp (name, "dmult", 5) == 0) | |
2231 | return FIX_VR4120_DMULT; | |
2232 | if (strstr (name, "div")) | |
2233 | return FIX_VR4120_DIV; | |
2234 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2235 | return FIX_VR4120_MTHILO; | |
2236 | return NUM_FIX_VR4120_CLASSES; | |
2237 | } | |
252b5132 | 2238 | |
71400594 RS |
2239 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2240 | where INSN1 is the earlier instruction. Return the worst-case value | |
2241 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2242 | |
71400594 RS |
2243 | static unsigned int |
2244 | insns_between (const struct mips_cl_insn *insn1, | |
2245 | const struct mips_cl_insn *insn2) | |
2246 | { | |
2247 | unsigned long pinfo1, pinfo2; | |
2248 | ||
2249 | /* This function needs to know which pinfo flags are set for INSN2 | |
2250 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2251 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2252 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2253 | pinfo1 = insn1->insn_mo->pinfo; | |
2254 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2255 | |
71400594 RS |
2256 | #define INSN2_USES_REG(REG, CLASS) \ |
2257 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2258 | ||
2259 | /* For most targets, write-after-read dependencies on the HI and LO | |
2260 | registers must be separated by at least two instructions. */ | |
2261 | if (!hilo_interlocks) | |
252b5132 | 2262 | { |
71400594 RS |
2263 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2264 | return 2; | |
2265 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2266 | return 2; | |
2267 | } | |
2268 | ||
2269 | /* If we're working around r7000 errata, there must be two instructions | |
2270 | between an mfhi or mflo and any instruction that uses the result. */ | |
2271 | if (mips_7000_hilo_fix | |
2272 | && MF_HILO_INSN (pinfo1) | |
2273 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2274 | return 2; | |
2275 | ||
2276 | /* If working around VR4120 errata, check for combinations that need | |
2277 | a single intervening instruction. */ | |
2278 | if (mips_fix_vr4120) | |
2279 | { | |
2280 | unsigned int class1, class2; | |
252b5132 | 2281 | |
71400594 RS |
2282 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2283 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2284 | { |
71400594 RS |
2285 | if (insn2 == NULL) |
2286 | return 1; | |
2287 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2288 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2289 | return 1; | |
252b5132 | 2290 | } |
71400594 RS |
2291 | } |
2292 | ||
2293 | if (!mips_opts.mips16) | |
2294 | { | |
2295 | /* Check for GPR or coprocessor load delays. All such delays | |
2296 | are on the RT register. */ | |
2297 | /* Itbl support may require additional care here. */ | |
2298 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2299 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2300 | { |
71400594 RS |
2301 | know (pinfo1 & INSN_WRITE_GPR_T); |
2302 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2303 | return 1; | |
2304 | } | |
2305 | ||
2306 | /* Check for generic coprocessor hazards. | |
2307 | ||
2308 | This case is not handled very well. There is no special | |
2309 | knowledge of CP0 handling, and the coprocessors other than | |
2310 | the floating point unit are not distinguished at all. */ | |
2311 | /* Itbl support may require additional care here. FIXME! | |
2312 | Need to modify this to include knowledge about | |
2313 | user specified delays! */ | |
2314 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2315 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2316 | { | |
2317 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2318 | register. There must be a one instruction delay before INSN2 | |
2319 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2320 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2321 | { |
71400594 RS |
2322 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2323 | return 1; | |
252b5132 | 2324 | } |
71400594 | 2325 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2326 | { |
71400594 RS |
2327 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2328 | return 1; | |
252b5132 RH |
2329 | } |
2330 | else | |
2331 | { | |
71400594 RS |
2332 | /* Read-after-write dependencies on the control registers |
2333 | require a two-instruction gap. */ | |
2334 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2335 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2336 | return 2; | |
2337 | ||
2338 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2339 | also a coprocessor instruction, assume there must be | |
2340 | a one instruction gap. */ | |
2341 | if (pinfo2 & INSN_COP) | |
2342 | return 1; | |
252b5132 RH |
2343 | } |
2344 | } | |
6b76fefe | 2345 | |
71400594 RS |
2346 | /* Check for read-after-write dependencies on the coprocessor |
2347 | control registers in cases where INSN1 does not need a general | |
2348 | coprocessor delay. This means that INSN1 is a floating point | |
2349 | comparison instruction. */ | |
2350 | /* Itbl support may require additional care here. */ | |
2351 | else if (!cop_interlocks | |
2352 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2353 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2354 | return 1; | |
2355 | } | |
6b76fefe | 2356 | |
71400594 | 2357 | #undef INSN2_USES_REG |
6b76fefe | 2358 | |
71400594 RS |
2359 | return 0; |
2360 | } | |
6b76fefe | 2361 | |
7d8e00cf RS |
2362 | /* Return the number of nops that would be needed to work around the |
2363 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2364 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2365 | ||
2366 | static int | |
2367 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2368 | const struct mips_cl_insn *insn) | |
2369 | { | |
2370 | int i, j, reg; | |
2371 | ||
2372 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2373 | are not affected by the errata. */ | |
2374 | if (insn != 0 | |
2375 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2376 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2377 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2378 | return 0; | |
2379 | ||
2380 | /* Search for the first MFLO or MFHI. */ | |
2381 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2382 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2383 | { | |
2384 | /* Extract the destination register. */ | |
2385 | if (mips_opts.mips16) | |
2386 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2387 | else | |
2388 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2389 | ||
2390 | /* No nops are needed if INSN reads that register. */ | |
2391 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2392 | return 0; | |
2393 | ||
2394 | /* ...or if any of the intervening instructions do. */ | |
2395 | for (j = 0; j < i; j++) | |
2396 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2397 | return 0; | |
2398 | ||
2399 | return MAX_VR4130_NOPS - i; | |
2400 | } | |
2401 | return 0; | |
2402 | } | |
2403 | ||
71400594 RS |
2404 | /* Return the number of nops that would be needed if instruction INSN |
2405 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2406 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2407 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2408 | |
71400594 RS |
2409 | static int |
2410 | nops_for_insn (const struct mips_cl_insn *history, | |
2411 | const struct mips_cl_insn *insn) | |
2412 | { | |
2413 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2414 | |
71400594 | 2415 | nops = 0; |
7d8e00cf | 2416 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2417 | if (!history[i].noreorder_p) |
2418 | { | |
2419 | tmp_nops = insns_between (history + i, insn) - i; | |
2420 | if (tmp_nops > nops) | |
2421 | nops = tmp_nops; | |
2422 | } | |
7d8e00cf RS |
2423 | |
2424 | if (mips_fix_vr4130) | |
2425 | { | |
2426 | tmp_nops = nops_for_vr4130 (history, insn); | |
2427 | if (tmp_nops > nops) | |
2428 | nops = tmp_nops; | |
2429 | } | |
2430 | ||
71400594 RS |
2431 | return nops; |
2432 | } | |
252b5132 | 2433 | |
71400594 RS |
2434 | /* The variable arguments provide NUM_INSNS extra instructions that |
2435 | might be added to HISTORY. Return the largest number of nops that | |
2436 | would be needed after the extended sequence. */ | |
252b5132 | 2437 | |
71400594 RS |
2438 | static int |
2439 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2440 | { | |
2441 | va_list args; | |
2442 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2443 | struct mips_cl_insn *cursor; | |
2444 | int nops; | |
2445 | ||
2446 | va_start (args, history); | |
2447 | cursor = buffer + num_insns; | |
2448 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2449 | while (cursor > buffer) | |
2450 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2451 | ||
2452 | nops = nops_for_insn (buffer, NULL); | |
2453 | va_end (args); | |
2454 | return nops; | |
2455 | } | |
252b5132 | 2456 | |
71400594 RS |
2457 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2458 | worst-case delay for the branch target. */ | |
252b5132 | 2459 | |
71400594 RS |
2460 | static int |
2461 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2462 | const struct mips_cl_insn *insn) | |
2463 | { | |
2464 | int nops, tmp_nops; | |
60b63b72 | 2465 | |
71400594 RS |
2466 | nops = nops_for_insn (history, insn); |
2467 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2468 | | INSN_COND_BRANCH_DELAY | |
2469 | | INSN_COND_BRANCH_LIKELY)) | |
2470 | { | |
2471 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2472 | if (tmp_nops > nops) | |
2473 | nops = tmp_nops; | |
2474 | } | |
2475 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2476 | { | |
2477 | tmp_nops = nops_for_sequence (1, history, insn); | |
2478 | if (tmp_nops > nops) | |
2479 | nops = tmp_nops; | |
2480 | } | |
2481 | return nops; | |
2482 | } | |
2483 | ||
2484 | /* Output an instruction. IP is the instruction information. | |
2485 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2486 | RELOC_TYPE. */ | |
2487 | ||
2488 | static void | |
2489 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2490 | bfd_reloc_code_real_type *reloc_type) | |
2491 | { | |
3994f87e | 2492 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2493 | relax_stateT prev_insn_frag_type = 0; |
2494 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2495 | segment_info_type *si = seg_info (now_seg); |
71400594 RS |
2496 | |
2497 | /* Mark instruction labels in mips16 mode. */ | |
2498 | mips16_mark_labels (); | |
2499 | ||
2500 | prev_pinfo = history[0].insn_mo->pinfo; | |
2501 | pinfo = ip->insn_mo->pinfo; | |
2502 | ||
2503 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2504 | { | |
2505 | /* There are a lot of optimizations we could do that we don't. | |
2506 | In particular, we do not, in general, reorder instructions. | |
2507 | If you use gcc with optimization, it will reorder | |
2508 | instructions and generally do much more optimization then we | |
2509 | do here; repeating all that work in the assembler would only | |
2510 | benefit hand written assembly code, and does not seem worth | |
2511 | it. */ | |
2512 | int nops = (mips_optimize == 0 | |
2513 | ? nops_for_insn (history, NULL) | |
2514 | : nops_for_insn_or_target (history, ip)); | |
2515 | if (nops > 0) | |
252b5132 RH |
2516 | { |
2517 | fragS *old_frag; | |
2518 | unsigned long old_frag_offset; | |
2519 | int i; | |
252b5132 RH |
2520 | |
2521 | old_frag = frag_now; | |
2522 | old_frag_offset = frag_now_fix (); | |
2523 | ||
2524 | for (i = 0; i < nops; i++) | |
2525 | emit_nop (); | |
2526 | ||
2527 | if (listing) | |
2528 | { | |
2529 | listing_prev_line (); | |
2530 | /* We may be at the start of a variant frag. In case we | |
2531 | are, make sure there is enough space for the frag | |
2532 | after the frags created by listing_prev_line. The | |
2533 | argument to frag_grow here must be at least as large | |
2534 | as the argument to all other calls to frag_grow in | |
2535 | this file. We don't have to worry about being in the | |
2536 | middle of a variant frag, because the variants insert | |
2537 | all needed nop instructions themselves. */ | |
2538 | frag_grow (40); | |
2539 | } | |
2540 | ||
404a8071 | 2541 | mips_move_labels (); |
252b5132 RH |
2542 | |
2543 | #ifndef NO_ECOFF_DEBUGGING | |
2544 | if (ECOFF_DEBUGGING) | |
2545 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2546 | #endif | |
2547 | } | |
71400594 RS |
2548 | } |
2549 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2550 | { | |
2551 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2552 | int nops = nops_for_insn_or_target (history, ip); | |
2553 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2554 | |
71400594 RS |
2555 | /* Enforce NOPS as a minimum. */ |
2556 | if (nops > prev_nop_frag_required) | |
2557 | prev_nop_frag_required = nops; | |
252b5132 | 2558 | |
71400594 RS |
2559 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2560 | { | |
2561 | /* Settle for the current number of nops. Update the history | |
2562 | accordingly (for the benefit of any future .set reorder code). */ | |
2563 | prev_nop_frag = NULL; | |
2564 | insert_into_history (prev_nop_frag_since, | |
2565 | prev_nop_frag_holds, NOP_INSN); | |
2566 | } | |
2567 | else | |
2568 | { | |
2569 | /* Allow this instruction to replace one of the nops that was | |
2570 | tentatively added to prev_nop_frag. */ | |
2571 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2572 | prev_nop_frag_holds--; | |
2573 | prev_nop_frag_since++; | |
252b5132 RH |
2574 | } |
2575 | } | |
2576 | ||
58e2ea4d MR |
2577 | #ifdef OBJ_ELF |
2578 | /* The value passed to dwarf2_emit_insn is the distance between | |
2579 | the beginning of the current instruction and the address that | |
2580 | should be recorded in the debug tables. For MIPS16 debug info | |
2581 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2582 | address higher by one than the current. */ | |
2583 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2584 | #endif | |
2585 | ||
895921c9 | 2586 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2587 | if (history[0].frag) |
2588 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2589 | |
4d7206a2 | 2590 | if (address_expr |
0b25d3e6 | 2591 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2592 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2593 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2594 | && mips_relax_branch | |
2595 | /* Don't try branch relaxation within .set nomacro, or within | |
2596 | .set noat if we use $at for PIC computations. If it turns | |
2597 | out that the branch was out-of-range, we'll get an error. */ | |
2598 | && !mips_opts.warn_about_macros | |
2599 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2600 | && !mips_opts.mips16) | |
2601 | { | |
895921c9 | 2602 | relaxed_branch = TRUE; |
1e915849 RS |
2603 | add_relaxed_insn (ip, (relaxed_branch_length |
2604 | (NULL, NULL, | |
2605 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2606 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2607 | : 0)), 4, | |
2608 | RELAX_BRANCH_ENCODE | |
2609 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2610 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2611 | pinfo & INSN_WRITE_GPR_31, | |
2612 | 0), | |
2613 | address_expr->X_add_symbol, | |
2614 | address_expr->X_add_number); | |
4a6a3df4 AO |
2615 | *reloc_type = BFD_RELOC_UNUSED; |
2616 | } | |
2617 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2618 | { |
2619 | /* We need to set up a variant frag. */ | |
2620 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2621 | add_relaxed_insn (ip, 4, 0, |
2622 | RELAX_MIPS16_ENCODE | |
2623 | (*reloc_type - BFD_RELOC_UNUSED, | |
2624 | mips16_small, mips16_ext, | |
2625 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2626 | history[0].mips16_absolute_jump_p), | |
2627 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2628 | } |
252b5132 RH |
2629 | else if (mips_opts.mips16 |
2630 | && ! ip->use_extend | |
f6688943 | 2631 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2632 | { |
b8ee1a6e DU |
2633 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2634 | /* Make sure there is enough room to swap this instruction with | |
2635 | a following jump instruction. */ | |
2636 | frag_grow (6); | |
1e915849 | 2637 | add_fixed_insn (ip); |
252b5132 RH |
2638 | } |
2639 | else | |
2640 | { | |
2641 | if (mips_opts.mips16 | |
2642 | && mips_opts.noreorder | |
2643 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2644 | as_warn (_("extended instruction in delay slot")); | |
2645 | ||
4d7206a2 RS |
2646 | if (mips_relax.sequence) |
2647 | { | |
2648 | /* If we've reached the end of this frag, turn it into a variant | |
2649 | frag and record the information for the instructions we've | |
2650 | written so far. */ | |
2651 | if (frag_room () < 4) | |
2652 | relax_close_frag (); | |
2653 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2654 | } | |
2655 | ||
584892a6 RS |
2656 | if (mips_relax.sequence != 2) |
2657 | mips_macro_warning.sizes[0] += 4; | |
2658 | if (mips_relax.sequence != 1) | |
2659 | mips_macro_warning.sizes[1] += 4; | |
2660 | ||
1e915849 RS |
2661 | if (mips_opts.mips16) |
2662 | { | |
2663 | ip->fixed_p = 1; | |
2664 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2665 | } | |
2666 | add_fixed_insn (ip); | |
252b5132 RH |
2667 | } |
2668 | ||
01a3f561 | 2669 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2670 | { |
2671 | if (address_expr->X_op == O_constant) | |
2672 | { | |
f17c130b | 2673 | unsigned int tmp; |
f6688943 TS |
2674 | |
2675 | switch (*reloc_type) | |
252b5132 RH |
2676 | { |
2677 | case BFD_RELOC_32: | |
2678 | ip->insn_opcode |= address_expr->X_add_number; | |
2679 | break; | |
2680 | ||
f6688943 | 2681 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2682 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2683 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2684 | break; |
2685 | ||
2686 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2687 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2688 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2689 | break; |
2690 | ||
2691 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2692 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2693 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2694 | break; |
2695 | ||
2696 | case BFD_RELOC_HI16: | |
2697 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2698 | break; | |
2699 | ||
01a3f561 | 2700 | case BFD_RELOC_UNUSED: |
252b5132 | 2701 | case BFD_RELOC_LO16: |
ed6fb7bd | 2702 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2703 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2704 | break; | |
2705 | ||
2706 | case BFD_RELOC_MIPS_JMP: | |
2707 | if ((address_expr->X_add_number & 3) != 0) | |
2708 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2709 | (unsigned long) address_expr->X_add_number); | |
2710 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2711 | break; | |
2712 | ||
2713 | case BFD_RELOC_MIPS16_JMP: | |
2714 | if ((address_expr->X_add_number & 3) != 0) | |
2715 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2716 | (unsigned long) address_expr->X_add_number); | |
2717 | ip->insn_opcode |= | |
2718 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2719 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2720 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2721 | break; | |
2722 | ||
252b5132 | 2723 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2724 | if ((address_expr->X_add_number & 3) != 0) |
2725 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2726 | (unsigned long) address_expr->X_add_number); | |
2727 | if (mips_relax_branch) | |
2728 | goto need_reloc; | |
2729 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2730 | as_bad (_("branch address range overflow (0x%lx)"), | |
2731 | (unsigned long) address_expr->X_add_number); | |
2732 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2733 | break; | |
252b5132 RH |
2734 | |
2735 | default: | |
2736 | internalError (); | |
2737 | } | |
2738 | } | |
01a3f561 | 2739 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2740 | need_reloc: |
4d7206a2 RS |
2741 | { |
2742 | reloc_howto_type *howto; | |
2743 | int i; | |
34ce925e | 2744 | |
4d7206a2 RS |
2745 | /* In a compound relocation, it is the final (outermost) |
2746 | operator that determines the relocated field. */ | |
2747 | for (i = 1; i < 3; i++) | |
2748 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2749 | break; | |
34ce925e | 2750 | |
4d7206a2 | 2751 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2752 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2753 | bfd_get_reloc_size (howto), | |
2754 | address_expr, | |
2755 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2756 | reloc_type[0]); | |
4d7206a2 RS |
2757 | |
2758 | /* These relocations can have an addend that won't fit in | |
2759 | 4 octets for 64bit assembly. */ | |
2760 | if (HAVE_64BIT_GPRS | |
2761 | && ! howto->partial_inplace | |
2762 | && (reloc_type[0] == BFD_RELOC_16 | |
2763 | || reloc_type[0] == BFD_RELOC_32 | |
2764 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2765 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2766 | || reloc_type[0] == BFD_RELOC_LO16 | |
2767 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2768 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2769 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2770 | || reloc_type[0] == BFD_RELOC_64 | |
2771 | || reloc_type[0] == BFD_RELOC_CTOR | |
2772 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2773 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2774 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2775 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2776 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2777 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2778 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2779 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2780 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2781 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2782 | |
2783 | if (mips_relax.sequence) | |
2784 | { | |
2785 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2786 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2787 | } |
2788 | else if (reloc_needs_lo_p (*reloc_type)) | |
2789 | { | |
2790 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2791 | |
4d7206a2 RS |
2792 | /* Reuse the last entry if it already has a matching %lo. */ |
2793 | hi_fixup = mips_hi_fixup_list; | |
2794 | if (hi_fixup == 0 | |
2795 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2796 | { | |
2797 | hi_fixup = ((struct mips_hi_fixup *) | |
2798 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2799 | hi_fixup->next = mips_hi_fixup_list; | |
2800 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2801 | } |
1e915849 | 2802 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2803 | hi_fixup->seg = now_seg; |
2804 | } | |
f6688943 | 2805 | |
4d7206a2 RS |
2806 | /* Add fixups for the second and third relocations, if given. |
2807 | Note that the ABI allows the second relocation to be | |
2808 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2809 | moment we only use RSS_UNDEF, but we could add support | |
2810 | for the others if it ever becomes necessary. */ | |
2811 | for (i = 1; i < 3; i++) | |
2812 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2813 | { | |
1e915849 RS |
2814 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2815 | ip->fixp[0]->fx_size, NULL, 0, | |
2816 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2817 | |
2818 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2819 | ip->fixp[0]->fx_tcbit = 1; |
2820 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2821 | } |
252b5132 RH |
2822 | } |
2823 | } | |
1e915849 | 2824 | install_insn (ip); |
252b5132 RH |
2825 | |
2826 | /* Update the register mask information. */ | |
2827 | if (! mips_opts.mips16) | |
2828 | { | |
2829 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2830 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2831 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2832 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2833 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2834 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2835 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2836 | mips_gprmask |= 1 << RA; |
252b5132 | 2837 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2838 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2839 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2840 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2841 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2842 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2843 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2844 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2845 | if (pinfo & INSN_COP) |
2846 | { | |
bdaaa2e1 KH |
2847 | /* We don't keep enough information to sort these cases out. |
2848 | The itbl support does keep this information however, although | |
2849 | we currently don't support itbl fprmats as part of the cop | |
2850 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2851 | } |
2852 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2853 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2854 | } |
2855 | else | |
2856 | { | |
2857 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2858 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2859 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2860 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2861 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2862 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2863 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2864 | mips_gprmask |= 1 << TREG; | |
2865 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2866 | mips_gprmask |= 1 << SP; | |
2867 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2868 | mips_gprmask |= 1 << RA; | |
2869 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2870 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2871 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2872 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2873 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2874 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2875 | } |
2876 | ||
4d7206a2 | 2877 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2878 | { |
2879 | /* Filling the branch delay slot is more complex. We try to | |
2880 | switch the branch with the previous instruction, which we can | |
2881 | do if the previous instruction does not set up a condition | |
2882 | that the branch tests and if the branch is not itself the | |
2883 | target of any branch. */ | |
2884 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2885 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2886 | { | |
2887 | if (mips_optimize < 2 | |
2888 | /* If we have seen .set volatile or .set nomove, don't | |
2889 | optimize. */ | |
2890 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2891 | /* We can't swap if the previous instruction's position |
2892 | is fixed. */ | |
2893 | || history[0].fixed_p | |
252b5132 RH |
2894 | /* If the previous previous insn was in a .set |
2895 | noreorder, we can't swap. Actually, the MIPS | |
2896 | assembler will swap in this situation. However, gcc | |
2897 | configured -with-gnu-as will generate code like | |
2898 | .set noreorder | |
2899 | lw $4,XXX | |
2900 | .set reorder | |
2901 | INSN | |
2902 | bne $4,$0,foo | |
2903 | in which we can not swap the bne and INSN. If gcc is | |
2904 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2905 | .set pseudo-ops. */ |
47e39b9d | 2906 | || history[1].noreorder_p |
252b5132 RH |
2907 | /* If the branch is itself the target of a branch, we |
2908 | can not swap. We cheat on this; all we check for is | |
2909 | whether there is a label on this instruction. If | |
2910 | there are any branches to anything other than a | |
2911 | label, users must use .set noreorder. */ | |
a8dbcb85 | 2912 | || si->label_list != NULL |
895921c9 MR |
2913 | /* If the previous instruction is in a variant frag |
2914 | other than this branch's one, we cannot do the swap. | |
2915 | This does not apply to the mips16, which uses variant | |
2916 | frags for different purposes. */ | |
252b5132 | 2917 | || (! mips_opts.mips16 |
895921c9 | 2918 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2919 | /* Check for conflicts between the branch and the instructions |
2920 | before the candidate delay slot. */ | |
2921 | || nops_for_insn (history + 1, ip) > 0 | |
2922 | /* Check for conflicts between the swapped sequence and the | |
2923 | target of the branch. */ | |
2924 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2925 | /* We do not swap with a trap instruction, since it |
2926 | complicates trap handlers to have the trap | |
2927 | instruction be in a delay slot. */ | |
2928 | || (prev_pinfo & INSN_TRAP) | |
2929 | /* If the branch reads a register that the previous | |
2930 | instruction sets, we can not swap. */ | |
2931 | || (! mips_opts.mips16 | |
2932 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2933 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2934 | MIPS_GR_REG)) |
2935 | || (! mips_opts.mips16 | |
2936 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2937 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2938 | MIPS_GR_REG)) |
2939 | || (mips_opts.mips16 | |
2940 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2941 | && (insn_uses_reg |
2942 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2943 | MIPS16_REG))) | |
252b5132 | 2944 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2945 | && (insn_uses_reg |
2946 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2947 | MIPS16_REG))) | |
252b5132 | 2948 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2949 | && (insn_uses_reg |
2950 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2951 | MIPS16_REG))) | |
252b5132 RH |
2952 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2953 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2954 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2955 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2956 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2957 | && insn_uses_reg (ip, | |
47e39b9d RS |
2958 | MIPS16OP_EXTRACT_REG32R |
2959 | (history[0].insn_opcode), | |
252b5132 RH |
2960 | MIPS_GR_REG)))) |
2961 | /* If the branch writes a register that the previous | |
2962 | instruction sets, we can not swap (we know that | |
2963 | branches write only to RD or to $31). */ | |
2964 | || (! mips_opts.mips16 | |
2965 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2966 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2967 | && (EXTRACT_OPERAND (RT, history[0]) |
2968 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2969 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2970 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2971 | || (! mips_opts.mips16 |
2972 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2973 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2974 | && (EXTRACT_OPERAND (RD, history[0]) |
2975 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2976 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2977 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2978 | || (mips_opts.mips16 |
2979 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2980 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2981 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2982 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2983 | == RA)))) |
2984 | /* If the branch writes a register that the previous | |
2985 | instruction reads, we can not swap (we know that | |
2986 | branches only write to RD or to $31). */ | |
2987 | || (! mips_opts.mips16 | |
2988 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2989 | && insn_uses_reg (&history[0], |
bf12938e | 2990 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2991 | MIPS_GR_REG)) |
2992 | || (! mips_opts.mips16 | |
2993 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2994 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2995 | || (mips_opts.mips16 |
2996 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2997 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2998 | /* If one instruction sets a condition code and the |
2999 | other one uses a condition code, we can not swap. */ | |
3000 | || ((pinfo & INSN_READ_COND_CODE) | |
3001 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3002 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3003 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3004 | /* If the previous instruction uses the PC, we can not | |
3005 | swap. */ | |
3006 | || (mips_opts.mips16 | |
3007 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3008 | /* If the previous instruction had a fixup in mips16 |
3009 | mode, we can not swap. This normally means that the | |
3010 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3011 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3012 | /* If the previous instruction is a sync, sync.l, or |
3013 | sync.p, we can not swap. */ | |
f173e82e | 3014 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 3015 | { |
29024861 DU |
3016 | if (mips_opts.mips16 |
3017 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3018 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3019 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3020 | { |
3021 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3022 | ip->insn_opcode |= 0x0080; | |
3023 | install_insn (ip); | |
3024 | insert_into_history (0, 1, ip); | |
3025 | } | |
3026 | else | |
3027 | { | |
3028 | /* We could do even better for unconditional branches to | |
3029 | portions of this object file; we could pick up the | |
3030 | instruction at the destination, put it in the delay | |
3031 | slot, and bump the destination address. */ | |
3032 | insert_into_history (0, 1, ip); | |
3033 | emit_nop (); | |
3034 | } | |
3035 | ||
dd22970f ILT |
3036 | if (mips_relax.sequence) |
3037 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3038 | } |
3039 | else | |
3040 | { | |
3041 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3042 | struct mips_cl_insn delay = history[0]; |
3043 | if (mips_opts.mips16) | |
252b5132 | 3044 | { |
b8ee1a6e DU |
3045 | know (delay.frag == ip->frag); |
3046 | move_insn (ip, delay.frag, delay.where); | |
3047 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3048 | } |
3049 | else if (relaxed_branch) | |
3050 | { | |
3051 | /* Add the delay slot instruction to the end of the | |
3052 | current frag and shrink the fixed part of the | |
3053 | original frag. If the branch occupies the tail of | |
3054 | the latter, move it backwards to cover the gap. */ | |
3055 | delay.frag->fr_fix -= 4; | |
3056 | if (delay.frag == ip->frag) | |
3057 | move_insn (ip, ip->frag, ip->where - 4); | |
3058 | add_fixed_insn (&delay); | |
252b5132 RH |
3059 | } |
3060 | else | |
3061 | { | |
1e915849 RS |
3062 | move_insn (&delay, ip->frag, ip->where); |
3063 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3064 | } |
1e915849 RS |
3065 | history[0] = *ip; |
3066 | delay.fixed_p = 1; | |
3067 | insert_into_history (0, 1, &delay); | |
252b5132 | 3068 | } |
252b5132 RH |
3069 | |
3070 | /* If that was an unconditional branch, forget the previous | |
3071 | insn information. */ | |
3072 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 3073 | mips_no_prev_insn (); |
252b5132 RH |
3074 | } |
3075 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3076 | { | |
3077 | /* We don't yet optimize a branch likely. What we should do | |
3078 | is look at the target, copy the instruction found there | |
3079 | into the delay slot, and increment the branch to jump to | |
3080 | the next instruction. */ | |
1e915849 | 3081 | insert_into_history (0, 1, ip); |
252b5132 | 3082 | emit_nop (); |
252b5132 RH |
3083 | } |
3084 | else | |
1e915849 | 3085 | insert_into_history (0, 1, ip); |
252b5132 | 3086 | } |
1e915849 RS |
3087 | else |
3088 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3089 | |
3090 | /* We just output an insn, so the next one doesn't have a label. */ | |
3091 | mips_clear_insn_labels (); | |
252b5132 RH |
3092 | } |
3093 | ||
7d10b47d | 3094 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3095 | |
3096 | static void | |
7d10b47d | 3097 | mips_no_prev_insn (void) |
252b5132 | 3098 | { |
7d10b47d RS |
3099 | prev_nop_frag = NULL; |
3100 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3101 | mips_clear_insn_labels (); |
3102 | } | |
3103 | ||
7d10b47d RS |
3104 | /* This function must be called before we emit something other than |
3105 | instructions. It is like mips_no_prev_insn except that it inserts | |
3106 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3107 | |
7d10b47d RS |
3108 | void |
3109 | mips_emit_delays (void) | |
252b5132 RH |
3110 | { |
3111 | if (! mips_opts.noreorder) | |
3112 | { | |
71400594 | 3113 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3114 | if (nops > 0) |
3115 | { | |
7d10b47d RS |
3116 | while (nops-- > 0) |
3117 | add_fixed_insn (NOP_INSN); | |
3118 | mips_move_labels (); | |
3119 | } | |
3120 | } | |
3121 | mips_no_prev_insn (); | |
3122 | } | |
3123 | ||
3124 | /* Start a (possibly nested) noreorder block. */ | |
3125 | ||
3126 | static void | |
3127 | start_noreorder (void) | |
3128 | { | |
3129 | if (mips_opts.noreorder == 0) | |
3130 | { | |
3131 | unsigned int i; | |
3132 | int nops; | |
3133 | ||
3134 | /* None of the instructions before the .set noreorder can be moved. */ | |
3135 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3136 | history[i].fixed_p = 1; | |
3137 | ||
3138 | /* Insert any nops that might be needed between the .set noreorder | |
3139 | block and the previous instructions. We will later remove any | |
3140 | nops that turn out not to be needed. */ | |
3141 | nops = nops_for_insn (history, NULL); | |
3142 | if (nops > 0) | |
3143 | { | |
3144 | if (mips_optimize != 0) | |
252b5132 RH |
3145 | { |
3146 | /* Record the frag which holds the nop instructions, so | |
3147 | that we can remove them if we don't need them. */ | |
3148 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3149 | prev_nop_frag = frag_now; | |
3150 | prev_nop_frag_holds = nops; | |
3151 | prev_nop_frag_required = 0; | |
3152 | prev_nop_frag_since = 0; | |
3153 | } | |
3154 | ||
3155 | for (; nops > 0; --nops) | |
1e915849 | 3156 | add_fixed_insn (NOP_INSN); |
252b5132 | 3157 | |
7d10b47d RS |
3158 | /* Move on to a new frag, so that it is safe to simply |
3159 | decrease the size of prev_nop_frag. */ | |
3160 | frag_wane (frag_now); | |
3161 | frag_new (0); | |
404a8071 | 3162 | mips_move_labels (); |
252b5132 | 3163 | } |
7d10b47d RS |
3164 | mips16_mark_labels (); |
3165 | mips_clear_insn_labels (); | |
252b5132 | 3166 | } |
7d10b47d RS |
3167 | mips_opts.noreorder++; |
3168 | mips_any_noreorder = 1; | |
3169 | } | |
252b5132 | 3170 | |
7d10b47d | 3171 | /* End a nested noreorder block. */ |
252b5132 | 3172 | |
7d10b47d RS |
3173 | static void |
3174 | end_noreorder (void) | |
3175 | { | |
3176 | mips_opts.noreorder--; | |
3177 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3178 | { | |
3179 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3180 | handling nop insertion the .set reorder way. */ | |
3181 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3182 | * (mips_opts.mips16 ? 2 : 4)); | |
3183 | insert_into_history (prev_nop_frag_since, | |
3184 | prev_nop_frag_required, NOP_INSN); | |
3185 | prev_nop_frag = NULL; | |
3186 | } | |
252b5132 RH |
3187 | } |
3188 | ||
584892a6 RS |
3189 | /* Set up global variables for the start of a new macro. */ |
3190 | ||
3191 | static void | |
3192 | macro_start (void) | |
3193 | { | |
3194 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3195 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3196 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3197 | & (INSN_UNCOND_BRANCH_DELAY |
3198 | | INSN_COND_BRANCH_DELAY | |
3199 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3200 | } | |
3201 | ||
3202 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3203 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3204 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3205 | ||
3206 | static const char * | |
3207 | macro_warning (relax_substateT subtype) | |
3208 | { | |
3209 | if (subtype & RELAX_DELAY_SLOT) | |
3210 | return _("Macro instruction expanded into multiple instructions" | |
3211 | " in a branch delay slot"); | |
3212 | else if (subtype & RELAX_NOMACRO) | |
3213 | return _("Macro instruction expanded into multiple instructions"); | |
3214 | else | |
3215 | return 0; | |
3216 | } | |
3217 | ||
3218 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3219 | ||
3220 | static void | |
3221 | macro_end (void) | |
3222 | { | |
3223 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3224 | { | |
3225 | relax_substateT subtype; | |
3226 | ||
3227 | /* Set up the relaxation warning flags. */ | |
3228 | subtype = 0; | |
3229 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3230 | subtype |= RELAX_SECOND_LONGER; | |
3231 | if (mips_opts.warn_about_macros) | |
3232 | subtype |= RELAX_NOMACRO; | |
3233 | if (mips_macro_warning.delay_slot_p) | |
3234 | subtype |= RELAX_DELAY_SLOT; | |
3235 | ||
3236 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3237 | { | |
3238 | /* Either the macro has a single implementation or both | |
3239 | implementations are longer than 4 bytes. Emit the | |
3240 | warning now. */ | |
3241 | const char *msg = macro_warning (subtype); | |
3242 | if (msg != 0) | |
3243 | as_warn (msg); | |
3244 | } | |
3245 | else | |
3246 | { | |
3247 | /* One implementation might need a warning but the other | |
3248 | definitely doesn't. */ | |
3249 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3250 | } | |
3251 | } | |
3252 | } | |
3253 | ||
6e1304d8 RS |
3254 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3255 | The first argument in *ARGS will be either the code for a single | |
3256 | relocation or -1 followed by the three codes that make up a | |
3257 | composite relocation. */ | |
3258 | ||
3259 | static void | |
3260 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3261 | { | |
3262 | int i, next; | |
3263 | ||
3264 | next = va_arg (*args, int); | |
3265 | if (next >= 0) | |
3266 | r[0] = (bfd_reloc_code_real_type) next; | |
3267 | else | |
3268 | for (i = 0; i < 3; i++) | |
3269 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3270 | } | |
3271 | ||
252b5132 RH |
3272 | /* Build an instruction created by a macro expansion. This is passed |
3273 | a pointer to the count of instructions created so far, an | |
3274 | expression, the name of the instruction to build, an operand format | |
3275 | string, and corresponding arguments. */ | |
3276 | ||
252b5132 | 3277 | static void |
67c0d1eb | 3278 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3279 | { |
1e915849 | 3280 | const struct mips_opcode *mo; |
252b5132 | 3281 | struct mips_cl_insn insn; |
f6688943 | 3282 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3283 | va_list args; |
252b5132 | 3284 | |
252b5132 | 3285 | va_start (args, fmt); |
252b5132 | 3286 | |
252b5132 RH |
3287 | if (mips_opts.mips16) |
3288 | { | |
67c0d1eb | 3289 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3290 | va_end (args); |
3291 | return; | |
3292 | } | |
3293 | ||
f6688943 TS |
3294 | r[0] = BFD_RELOC_UNUSED; |
3295 | r[1] = BFD_RELOC_UNUSED; | |
3296 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3297 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3298 | assert (mo); | |
3299 | assert (strcmp (name, mo->name) == 0); | |
3300 | ||
3301 | /* Search until we get a match for NAME. It is assumed here that | |
65263ce3 | 3302 | macros will never generate MDMX, MIPS-3D, DSP or MT instructions. */ |
1e915849 RS |
3303 | while (strcmp (fmt, mo->args) != 0 |
3304 | || mo->pinfo == INSN_MACRO | |
3305 | || !OPCODE_IS_MEMBER (mo, | |
3306 | (mips_opts.isa | |
9b3f89ee | 3307 | | (mips_opts.mips16 ? INSN_MIPS16 : 0) |
e16bfa71 | 3308 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), |
fef14a42 | 3309 | mips_opts.arch) |
1e915849 RS |
3310 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
3311 | { | |
3312 | ++mo; | |
3313 | assert (mo->name); | |
3314 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3315 | } |
3316 | ||
1e915849 | 3317 | create_insn (&insn, mo); |
252b5132 RH |
3318 | for (;;) |
3319 | { | |
3320 | switch (*fmt++) | |
3321 | { | |
3322 | case '\0': | |
3323 | break; | |
3324 | ||
3325 | case ',': | |
3326 | case '(': | |
3327 | case ')': | |
3328 | continue; | |
3329 | ||
5f74bc13 CD |
3330 | case '+': |
3331 | switch (*fmt++) | |
3332 | { | |
3333 | case 'A': | |
3334 | case 'E': | |
bf12938e | 3335 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3336 | continue; |
3337 | ||
3338 | case 'B': | |
3339 | case 'F': | |
3340 | /* Note that in the macro case, these arguments are already | |
3341 | in MSB form. (When handling the instruction in the | |
3342 | non-macro case, these arguments are sizes from which | |
3343 | MSB values must be calculated.) */ | |
bf12938e | 3344 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3345 | continue; |
3346 | ||
3347 | case 'C': | |
3348 | case 'G': | |
3349 | case 'H': | |
3350 | /* Note that in the macro case, these arguments are already | |
3351 | in MSBD form. (When handling the instruction in the | |
3352 | non-macro case, these arguments are sizes from which | |
3353 | MSBD values must be calculated.) */ | |
bf12938e | 3354 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3355 | continue; |
3356 | ||
3357 | default: | |
3358 | internalError (); | |
3359 | } | |
3360 | continue; | |
3361 | ||
252b5132 RH |
3362 | case 't': |
3363 | case 'w': | |
3364 | case 'E': | |
bf12938e | 3365 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3366 | continue; |
3367 | ||
3368 | case 'c': | |
bf12938e | 3369 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3370 | continue; |
3371 | ||
252b5132 RH |
3372 | case 'T': |
3373 | case 'W': | |
bf12938e | 3374 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3375 | continue; |
3376 | ||
3377 | case 'd': | |
3378 | case 'G': | |
af7ee8bf | 3379 | case 'K': |
bf12938e | 3380 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3381 | continue; |
3382 | ||
4372b673 NC |
3383 | case 'U': |
3384 | { | |
3385 | int tmp = va_arg (args, int); | |
3386 | ||
bf12938e RS |
3387 | INSERT_OPERAND (RT, insn, tmp); |
3388 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3389 | continue; |
4372b673 NC |
3390 | } |
3391 | ||
252b5132 RH |
3392 | case 'V': |
3393 | case 'S': | |
bf12938e | 3394 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3395 | continue; |
3396 | ||
3397 | case 'z': | |
3398 | continue; | |
3399 | ||
3400 | case '<': | |
bf12938e | 3401 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3402 | continue; |
3403 | ||
3404 | case 'D': | |
bf12938e | 3405 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3406 | continue; |
3407 | ||
3408 | case 'B': | |
bf12938e | 3409 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3410 | continue; |
3411 | ||
4372b673 | 3412 | case 'J': |
bf12938e | 3413 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3414 | continue; |
3415 | ||
252b5132 | 3416 | case 'q': |
bf12938e | 3417 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3418 | continue; |
3419 | ||
3420 | case 'b': | |
3421 | case 's': | |
3422 | case 'r': | |
3423 | case 'v': | |
bf12938e | 3424 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3425 | continue; |
3426 | ||
3427 | case 'i': | |
3428 | case 'j': | |
3429 | case 'o': | |
6e1304d8 | 3430 | macro_read_relocs (&args, r); |
cdf6fd85 | 3431 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3432 | || *r == BFD_RELOC_MIPS_LITERAL |
3433 | || *r == BFD_RELOC_MIPS_HIGHER | |
3434 | || *r == BFD_RELOC_HI16_S | |
3435 | || *r == BFD_RELOC_LO16 | |
3436 | || *r == BFD_RELOC_MIPS_GOT16 | |
3437 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3438 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3439 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3440 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3441 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3442 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3443 | continue; |
3444 | ||
3445 | case 'u': | |
6e1304d8 | 3446 | macro_read_relocs (&args, r); |
252b5132 RH |
3447 | assert (ep != NULL |
3448 | && (ep->X_op == O_constant | |
3449 | || (ep->X_op == O_symbol | |
f6688943 TS |
3450 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3451 | || *r == BFD_RELOC_HI16_S | |
3452 | || *r == BFD_RELOC_HI16 | |
3453 | || *r == BFD_RELOC_GPREL16 | |
3454 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3455 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3456 | continue; |
3457 | ||
3458 | case 'p': | |
3459 | assert (ep != NULL); | |
bad36eac | 3460 | |
252b5132 RH |
3461 | /* |
3462 | * This allows macro() to pass an immediate expression for | |
3463 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3464 | * |
3465 | * We don't allow branch relaxation for these branches, as | |
3466 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3467 | */ |
3468 | if (ep->X_op == O_constant) | |
3469 | { | |
bad36eac DJ |
3470 | if ((ep->X_add_number & 3) != 0) |
3471 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3472 | (unsigned long) ep->X_add_number); | |
3473 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3474 | as_bad (_("branch address range overflow (0x%lx)"), | |
3475 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3476 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3477 | ep = NULL; | |
3478 | } | |
3479 | else | |
0b25d3e6 | 3480 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3481 | continue; |
3482 | ||
3483 | case 'a': | |
3484 | assert (ep != NULL); | |
f6688943 | 3485 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3486 | continue; |
3487 | ||
3488 | case 'C': | |
a9e24354 | 3489 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3490 | continue; |
3491 | ||
d43b4baf | 3492 | case 'k': |
a9e24354 | 3493 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3494 | continue; |
3495 | ||
252b5132 RH |
3496 | default: |
3497 | internalError (); | |
3498 | } | |
3499 | break; | |
3500 | } | |
3501 | va_end (args); | |
f6688943 | 3502 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3503 | |
4d7206a2 | 3504 | append_insn (&insn, ep, r); |
252b5132 RH |
3505 | } |
3506 | ||
3507 | static void | |
67c0d1eb | 3508 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3509 | va_list args) |
252b5132 | 3510 | { |
1e915849 | 3511 | struct mips_opcode *mo; |
252b5132 | 3512 | struct mips_cl_insn insn; |
f6688943 TS |
3513 | bfd_reloc_code_real_type r[3] |
3514 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3515 | |
1e915849 RS |
3516 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3517 | assert (mo); | |
3518 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3519 | |
1e915849 | 3520 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3521 | { |
1e915849 RS |
3522 | ++mo; |
3523 | assert (mo->name); | |
3524 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3525 | } |
3526 | ||
1e915849 | 3527 | create_insn (&insn, mo); |
252b5132 RH |
3528 | for (;;) |
3529 | { | |
3530 | int c; | |
3531 | ||
3532 | c = *fmt++; | |
3533 | switch (c) | |
3534 | { | |
3535 | case '\0': | |
3536 | break; | |
3537 | ||
3538 | case ',': | |
3539 | case '(': | |
3540 | case ')': | |
3541 | continue; | |
3542 | ||
3543 | case 'y': | |
3544 | case 'w': | |
bf12938e | 3545 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3546 | continue; |
3547 | ||
3548 | case 'x': | |
3549 | case 'v': | |
bf12938e | 3550 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3551 | continue; |
3552 | ||
3553 | case 'z': | |
bf12938e | 3554 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3555 | continue; |
3556 | ||
3557 | case 'Z': | |
bf12938e | 3558 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3559 | continue; |
3560 | ||
3561 | case '0': | |
3562 | case 'S': | |
3563 | case 'P': | |
3564 | case 'R': | |
3565 | continue; | |
3566 | ||
3567 | case 'X': | |
bf12938e | 3568 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3569 | continue; |
3570 | ||
3571 | case 'Y': | |
3572 | { | |
3573 | int regno; | |
3574 | ||
3575 | regno = va_arg (args, int); | |
3576 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3577 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3578 | } |
3579 | continue; | |
3580 | ||
3581 | case '<': | |
3582 | case '>': | |
3583 | case '4': | |
3584 | case '5': | |
3585 | case 'H': | |
3586 | case 'W': | |
3587 | case 'D': | |
3588 | case 'j': | |
3589 | case '8': | |
3590 | case 'V': | |
3591 | case 'C': | |
3592 | case 'U': | |
3593 | case 'k': | |
3594 | case 'K': | |
3595 | case 'p': | |
3596 | case 'q': | |
3597 | { | |
3598 | assert (ep != NULL); | |
3599 | ||
3600 | if (ep->X_op != O_constant) | |
874e8986 | 3601 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3602 | else |
3603 | { | |
b34976b6 AM |
3604 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3605 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3606 | &insn.extend); |
252b5132 | 3607 | ep = NULL; |
f6688943 | 3608 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3609 | } |
3610 | } | |
3611 | continue; | |
3612 | ||
3613 | case '6': | |
bf12938e | 3614 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3615 | continue; |
3616 | } | |
3617 | ||
3618 | break; | |
3619 | } | |
3620 | ||
f6688943 | 3621 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3622 | |
4d7206a2 | 3623 | append_insn (&insn, ep, r); |
252b5132 RH |
3624 | } |
3625 | ||
2051e8c4 MR |
3626 | /* |
3627 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3628 | * higher bits unset. | |
3629 | */ | |
9f872bbe | 3630 | static void |
2051e8c4 MR |
3631 | normalize_constant_expr (expressionS *ex) |
3632 | { | |
9ee2a2d4 | 3633 | if (ex->X_op == O_constant |
2051e8c4 MR |
3634 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3635 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3636 | - 0x80000000); | |
3637 | } | |
3638 | ||
3639 | /* | |
3640 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3641 | * all higher bits unset. | |
3642 | */ | |
3643 | static void | |
3644 | normalize_address_expr (expressionS *ex) | |
3645 | { | |
3646 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3647 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3648 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3649 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3650 | - 0x80000000); | |
3651 | } | |
3652 | ||
438c16b8 TS |
3653 | /* |
3654 | * Generate a "jalr" instruction with a relocation hint to the called | |
3655 | * function. This occurs in NewABI PIC code. | |
3656 | */ | |
3657 | static void | |
67c0d1eb | 3658 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3659 | { |
685736be | 3660 | char *f = NULL; |
b34976b6 | 3661 | |
438c16b8 | 3662 | if (HAVE_NEWABI) |
f21f8242 | 3663 | { |
cc3d92a5 | 3664 | frag_grow (8); |
f21f8242 AO |
3665 | f = frag_more (0); |
3666 | } | |
67c0d1eb | 3667 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3668 | if (HAVE_NEWABI) |
f21f8242 | 3669 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3670 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3671 | } |
3672 | ||
252b5132 RH |
3673 | /* |
3674 | * Generate a "lui" instruction. | |
3675 | */ | |
3676 | static void | |
67c0d1eb | 3677 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3678 | { |
3679 | expressionS high_expr; | |
1e915849 | 3680 | const struct mips_opcode *mo; |
252b5132 | 3681 | struct mips_cl_insn insn; |
f6688943 TS |
3682 | bfd_reloc_code_real_type r[3] |
3683 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3684 | const char *name = "lui"; |
3685 | const char *fmt = "t,u"; | |
252b5132 RH |
3686 | |
3687 | assert (! mips_opts.mips16); | |
3688 | ||
4d7206a2 | 3689 | high_expr = *ep; |
252b5132 RH |
3690 | |
3691 | if (high_expr.X_op == O_constant) | |
3692 | { | |
3693 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3694 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3695 | >> 16) & 0xffff; | |
f6688943 | 3696 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3697 | } |
78e1bb40 | 3698 | else |
252b5132 RH |
3699 | { |
3700 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3701 | /* _gp_disp is a special case, used from s_cpload. |
3702 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3703 | assert (mips_pic == NO_PIC |
78e1bb40 | 3704 | || (! HAVE_NEWABI |
aa6975fb ILT |
3705 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3706 | || (! mips_in_shared | |
bbe506e8 TS |
3707 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3708 | "__gnu_local_gp") == 0)); | |
f6688943 | 3709 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3710 | } |
3711 | ||
1e915849 RS |
3712 | mo = hash_find (op_hash, name); |
3713 | assert (strcmp (name, mo->name) == 0); | |
3714 | assert (strcmp (fmt, mo->args) == 0); | |
3715 | create_insn (&insn, mo); | |
252b5132 | 3716 | |
bf12938e RS |
3717 | insn.insn_opcode = insn.insn_mo->match; |
3718 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3719 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3720 | { |
3721 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3722 | append_insn (&insn, NULL, r); |
252b5132 RH |
3723 | } |
3724 | else | |
4d7206a2 | 3725 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3726 | } |
3727 | ||
885add95 CD |
3728 | /* Generate a sequence of instructions to do a load or store from a constant |
3729 | offset off of a base register (breg) into/from a target register (treg), | |
3730 | using AT if necessary. */ | |
3731 | static void | |
67c0d1eb RS |
3732 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3733 | int treg, int breg, int dbl) | |
885add95 CD |
3734 | { |
3735 | assert (ep->X_op == O_constant); | |
3736 | ||
256ab948 | 3737 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3738 | if (!dbl) |
3739 | normalize_constant_expr (ep); | |
256ab948 | 3740 | |
67c1ffbe | 3741 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3742 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3743 | as_warn (_("operand overflow")); |
3744 | ||
3745 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3746 | { | |
3747 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3748 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3749 | } |
3750 | else | |
3751 | { | |
3752 | /* 32-bit offset, need multiple instructions and AT, like: | |
3753 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3754 | addu $tempreg,$tempreg,$breg | |
3755 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3756 | to handle the complete offset. */ | |
67c0d1eb RS |
3757 | macro_build_lui (ep, AT); |
3758 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3759 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3760 | |
3761 | if (mips_opts.noat) | |
8fc2e39e | 3762 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3763 | } |
3764 | } | |
3765 | ||
252b5132 RH |
3766 | /* set_at() |
3767 | * Generates code to set the $at register to true (one) | |
3768 | * if reg is less than the immediate expression. | |
3769 | */ | |
3770 | static void | |
67c0d1eb | 3771 | set_at (int reg, int unsignedp) |
252b5132 RH |
3772 | { |
3773 | if (imm_expr.X_op == O_constant | |
3774 | && imm_expr.X_add_number >= -0x8000 | |
3775 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3776 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3777 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3778 | else |
3779 | { | |
67c0d1eb RS |
3780 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3781 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3782 | } |
3783 | } | |
3784 | ||
3785 | /* Warn if an expression is not a constant. */ | |
3786 | ||
3787 | static void | |
17a2f251 | 3788 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3789 | { |
3790 | if (ex->X_op == O_big) | |
3791 | as_bad (_("unsupported large constant")); | |
3792 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3793 | as_bad (_("Instruction %s requires absolute expression"), |
3794 | ip->insn_mo->name); | |
13757d0c | 3795 | |
9ee2a2d4 MR |
3796 | if (HAVE_32BIT_GPRS) |
3797 | normalize_constant_expr (ex); | |
252b5132 RH |
3798 | } |
3799 | ||
3800 | /* Count the leading zeroes by performing a binary chop. This is a | |
3801 | bulky bit of source, but performance is a LOT better for the | |
3802 | majority of values than a simple loop to count the bits: | |
3803 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3804 | if ((v) & (1 << (31 - lcnt))) | |
3805 | break; | |
3806 | However it is not code size friendly, and the gain will drop a bit | |
3807 | on certain cached systems. | |
3808 | */ | |
3809 | #define COUNT_TOP_ZEROES(v) \ | |
3810 | (((v) & ~0xffff) == 0 \ | |
3811 | ? ((v) & ~0xff) == 0 \ | |
3812 | ? ((v) & ~0xf) == 0 \ | |
3813 | ? ((v) & ~0x3) == 0 \ | |
3814 | ? ((v) & ~0x1) == 0 \ | |
3815 | ? !(v) \ | |
3816 | ? 32 \ | |
3817 | : 31 \ | |
3818 | : 30 \ | |
3819 | : ((v) & ~0x7) == 0 \ | |
3820 | ? 29 \ | |
3821 | : 28 \ | |
3822 | : ((v) & ~0x3f) == 0 \ | |
3823 | ? ((v) & ~0x1f) == 0 \ | |
3824 | ? 27 \ | |
3825 | : 26 \ | |
3826 | : ((v) & ~0x7f) == 0 \ | |
3827 | ? 25 \ | |
3828 | : 24 \ | |
3829 | : ((v) & ~0xfff) == 0 \ | |
3830 | ? ((v) & ~0x3ff) == 0 \ | |
3831 | ? ((v) & ~0x1ff) == 0 \ | |
3832 | ? 23 \ | |
3833 | : 22 \ | |
3834 | : ((v) & ~0x7ff) == 0 \ | |
3835 | ? 21 \ | |
3836 | : 20 \ | |
3837 | : ((v) & ~0x3fff) == 0 \ | |
3838 | ? ((v) & ~0x1fff) == 0 \ | |
3839 | ? 19 \ | |
3840 | : 18 \ | |
3841 | : ((v) & ~0x7fff) == 0 \ | |
3842 | ? 17 \ | |
3843 | : 16 \ | |
3844 | : ((v) & ~0xffffff) == 0 \ | |
3845 | ? ((v) & ~0xfffff) == 0 \ | |
3846 | ? ((v) & ~0x3ffff) == 0 \ | |
3847 | ? ((v) & ~0x1ffff) == 0 \ | |
3848 | ? 15 \ | |
3849 | : 14 \ | |
3850 | : ((v) & ~0x7ffff) == 0 \ | |
3851 | ? 13 \ | |
3852 | : 12 \ | |
3853 | : ((v) & ~0x3fffff) == 0 \ | |
3854 | ? ((v) & ~0x1fffff) == 0 \ | |
3855 | ? 11 \ | |
3856 | : 10 \ | |
3857 | : ((v) & ~0x7fffff) == 0 \ | |
3858 | ? 9 \ | |
3859 | : 8 \ | |
3860 | : ((v) & ~0xfffffff) == 0 \ | |
3861 | ? ((v) & ~0x3ffffff) == 0 \ | |
3862 | ? ((v) & ~0x1ffffff) == 0 \ | |
3863 | ? 7 \ | |
3864 | : 6 \ | |
3865 | : ((v) & ~0x7ffffff) == 0 \ | |
3866 | ? 5 \ | |
3867 | : 4 \ | |
3868 | : ((v) & ~0x3fffffff) == 0 \ | |
3869 | ? ((v) & ~0x1fffffff) == 0 \ | |
3870 | ? 3 \ | |
3871 | : 2 \ | |
3872 | : ((v) & ~0x7fffffff) == 0 \ | |
3873 | ? 1 \ | |
3874 | : 0) | |
3875 | ||
3876 | /* load_register() | |
67c1ffbe | 3877 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3878 | * an absolute expression value into a register. |
3879 | */ | |
3880 | static void | |
67c0d1eb | 3881 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3882 | { |
3883 | int freg; | |
3884 | expressionS hi32, lo32; | |
3885 | ||
3886 | if (ep->X_op != O_big) | |
3887 | { | |
3888 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3889 | |
3890 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3891 | if (!dbl) |
3892 | normalize_constant_expr (ep); | |
256ab948 TS |
3893 | |
3894 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3895 | { |
3896 | /* We can handle 16 bit signed values with an addiu to | |
3897 | $zero. No need to ever use daddiu here, since $zero and | |
3898 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3899 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3900 | return; |
3901 | } | |
3902 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3903 | { | |
3904 | /* We can handle 16 bit unsigned values with an ori to | |
3905 | $zero. */ | |
67c0d1eb | 3906 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3907 | return; |
3908 | } | |
256ab948 | 3909 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3910 | { |
3911 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3912 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3913 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3914 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3915 | return; |
3916 | } | |
3917 | } | |
3918 | ||
3919 | /* The value is larger than 32 bits. */ | |
3920 | ||
2051e8c4 | 3921 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3922 | { |
55e08f71 NC |
3923 | char value[32]; |
3924 | ||
3925 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 3926 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 3927 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3928 | return; |
3929 | } | |
3930 | ||
3931 | if (ep->X_op != O_big) | |
3932 | { | |
3933 | hi32 = *ep; | |
3934 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3935 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3936 | hi32.X_add_number &= 0xffffffff; | |
3937 | lo32 = *ep; | |
3938 | lo32.X_add_number &= 0xffffffff; | |
3939 | } | |
3940 | else | |
3941 | { | |
3942 | assert (ep->X_add_number > 2); | |
3943 | if (ep->X_add_number == 3) | |
3944 | generic_bignum[3] = 0; | |
3945 | else if (ep->X_add_number > 4) | |
3946 | as_bad (_("Number larger than 64 bits")); | |
3947 | lo32.X_op = O_constant; | |
3948 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3949 | hi32.X_op = O_constant; | |
3950 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3951 | } | |
3952 | ||
3953 | if (hi32.X_add_number == 0) | |
3954 | freg = 0; | |
3955 | else | |
3956 | { | |
3957 | int shift, bit; | |
3958 | unsigned long hi, lo; | |
3959 | ||
956cd1d6 | 3960 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3961 | { |
3962 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3963 | { | |
67c0d1eb | 3964 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3965 | return; |
3966 | } | |
3967 | if (lo32.X_add_number & 0x80000000) | |
3968 | { | |
67c0d1eb | 3969 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3970 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3971 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3972 | return; |
3973 | } | |
3974 | } | |
252b5132 RH |
3975 | |
3976 | /* Check for 16bit shifted constant. We know that hi32 is | |
3977 | non-zero, so start the mask on the first bit of the hi32 | |
3978 | value. */ | |
3979 | shift = 17; | |
3980 | do | |
beae10d5 KH |
3981 | { |
3982 | unsigned long himask, lomask; | |
3983 | ||
3984 | if (shift < 32) | |
3985 | { | |
3986 | himask = 0xffff >> (32 - shift); | |
3987 | lomask = (0xffff << shift) & 0xffffffff; | |
3988 | } | |
3989 | else | |
3990 | { | |
3991 | himask = 0xffff << (shift - 32); | |
3992 | lomask = 0; | |
3993 | } | |
3994 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3995 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3996 | { | |
3997 | expressionS tmp; | |
3998 | ||
3999 | tmp.X_op = O_constant; | |
4000 | if (shift < 32) | |
4001 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4002 | | (lo32.X_add_number >> shift)); | |
4003 | else | |
4004 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4005 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4006 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4007 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4008 | return; |
4009 | } | |
f9419b05 | 4010 | ++shift; |
beae10d5 KH |
4011 | } |
4012 | while (shift <= (64 - 16)); | |
252b5132 RH |
4013 | |
4014 | /* Find the bit number of the lowest one bit, and store the | |
4015 | shifted value in hi/lo. */ | |
4016 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4017 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4018 | if (lo != 0) | |
4019 | { | |
4020 | bit = 0; | |
4021 | while ((lo & 1) == 0) | |
4022 | { | |
4023 | lo >>= 1; | |
4024 | ++bit; | |
4025 | } | |
4026 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4027 | hi >>= bit; | |
4028 | } | |
4029 | else | |
4030 | { | |
4031 | bit = 32; | |
4032 | while ((hi & 1) == 0) | |
4033 | { | |
4034 | hi >>= 1; | |
4035 | ++bit; | |
4036 | } | |
4037 | lo = hi; | |
4038 | hi = 0; | |
4039 | } | |
4040 | ||
4041 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4042 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4043 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4044 | { |
4045 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4046 | if (shift != 0) |
beae10d5 | 4047 | { |
252b5132 RH |
4048 | expressionS tmp; |
4049 | ||
4050 | /* This instruction will set the register to be all | |
4051 | ones. */ | |
beae10d5 KH |
4052 | tmp.X_op = O_constant; |
4053 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4054 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4055 | if (bit != 0) |
4056 | { | |
4057 | bit += shift; | |
67c0d1eb RS |
4058 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4059 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4060 | } |
67c0d1eb RS |
4061 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4062 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4063 | return; |
4064 | } | |
4065 | } | |
252b5132 RH |
4066 | |
4067 | /* Sign extend hi32 before calling load_register, because we can | |
4068 | generally get better code when we load a sign extended value. */ | |
4069 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4070 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4071 | load_register (reg, &hi32, 0); |
252b5132 RH |
4072 | freg = reg; |
4073 | } | |
4074 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4075 | { | |
4076 | if (freg != 0) | |
4077 | { | |
67c0d1eb | 4078 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4079 | freg = reg; |
4080 | } | |
4081 | } | |
4082 | else | |
4083 | { | |
4084 | expressionS mid16; | |
4085 | ||
956cd1d6 | 4086 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4087 | { |
67c0d1eb RS |
4088 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4089 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4090 | return; |
4091 | } | |
252b5132 RH |
4092 | |
4093 | if (freg != 0) | |
4094 | { | |
67c0d1eb | 4095 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4096 | freg = reg; |
4097 | } | |
4098 | mid16 = lo32; | |
4099 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4100 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4101 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4102 | freg = reg; |
4103 | } | |
4104 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4105 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4106 | } |
4107 | ||
269137b2 TS |
4108 | static inline void |
4109 | load_delay_nop (void) | |
4110 | { | |
4111 | if (!gpr_interlocks) | |
4112 | macro_build (NULL, "nop", ""); | |
4113 | } | |
4114 | ||
252b5132 RH |
4115 | /* Load an address into a register. */ |
4116 | ||
4117 | static void | |
67c0d1eb | 4118 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4119 | { |
252b5132 RH |
4120 | if (ep->X_op != O_constant |
4121 | && ep->X_op != O_symbol) | |
4122 | { | |
4123 | as_bad (_("expression too complex")); | |
4124 | ep->X_op = O_constant; | |
4125 | } | |
4126 | ||
4127 | if (ep->X_op == O_constant) | |
4128 | { | |
67c0d1eb | 4129 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4130 | return; |
4131 | } | |
4132 | ||
4133 | if (mips_pic == NO_PIC) | |
4134 | { | |
4135 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4136 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4137 | Otherwise we want |
4138 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4139 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4140 | If we have an addend, we always use the latter form. |
76b3015f | 4141 | |
d6bc6245 TS |
4142 | With 64bit address space and a usable $at we want |
4143 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4144 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4145 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4146 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4147 | dsll32 $reg,0 | |
3a482fd5 | 4148 | daddu $reg,$reg,$at |
76b3015f | 4149 | |
c03099e6 | 4150 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4151 | on superscalar processors. |
4152 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4153 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4154 | dsll $reg,16 | |
4155 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4156 | dsll $reg,16 | |
4157 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4158 | |
4159 | For GP relative symbols in 64bit address space we can use | |
4160 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4161 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4162 | { |
6caf9ef4 TS |
4163 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4164 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4165 | { | |
4166 | relax_start (ep->X_add_symbol); | |
4167 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4168 | mips_gp_register, BFD_RELOC_GPREL16); | |
4169 | relax_switch (); | |
4170 | } | |
d6bc6245 | 4171 | |
b8285c27 | 4172 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 4173 | { |
67c0d1eb RS |
4174 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4175 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4176 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4177 | BFD_RELOC_MIPS_HIGHER); | |
4178 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4179 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4180 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4181 | *used_at = 1; |
4182 | } | |
4183 | else | |
4184 | { | |
67c0d1eb RS |
4185 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4186 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4187 | BFD_RELOC_MIPS_HIGHER); | |
4188 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4189 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4190 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4191 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4192 | } |
6caf9ef4 TS |
4193 | |
4194 | if (mips_relax.sequence) | |
4195 | relax_end (); | |
d6bc6245 | 4196 | } |
252b5132 RH |
4197 | else |
4198 | { | |
d6bc6245 | 4199 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4200 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4201 | { |
4d7206a2 | 4202 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4203 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4204 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4205 | relax_switch (); |
d6bc6245 | 4206 | } |
67c0d1eb RS |
4207 | macro_build_lui (ep, reg); |
4208 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4209 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4210 | if (mips_relax.sequence) |
4211 | relax_end (); | |
d6bc6245 | 4212 | } |
252b5132 | 4213 | } |
0a44bf69 | 4214 | else if (!mips_big_got) |
252b5132 RH |
4215 | { |
4216 | expressionS ex; | |
4217 | ||
4218 | /* If this is a reference to an external symbol, we want | |
4219 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4220 | Otherwise we want | |
4221 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4222 | nop | |
4223 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4224 | If there is a constant, it must be added in after. |
4225 | ||
ed6fb7bd | 4226 | If we have NewABI, we want |
f5040a92 AO |
4227 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4228 | unless we're referencing a global symbol with a non-zero | |
4229 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4230 | if (HAVE_NEWABI) |
4231 | { | |
f5040a92 AO |
4232 | if (ep->X_add_number) |
4233 | { | |
4d7206a2 | 4234 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4235 | ep->X_add_number = 0; |
4d7206a2 | 4236 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4237 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4238 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4239 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4240 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4241 | ex.X_op = O_constant; | |
67c0d1eb | 4242 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4243 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4244 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4245 | relax_switch (); |
f5040a92 | 4246 | } |
67c0d1eb | 4247 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4248 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4249 | if (mips_relax.sequence) |
4250 | relax_end (); | |
ed6fb7bd SC |
4251 | } |
4252 | else | |
4253 | { | |
f5040a92 AO |
4254 | ex.X_add_number = ep->X_add_number; |
4255 | ep->X_add_number = 0; | |
67c0d1eb RS |
4256 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4257 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4258 | load_delay_nop (); |
4d7206a2 RS |
4259 | relax_start (ep->X_add_symbol); |
4260 | relax_switch (); | |
67c0d1eb | 4261 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4262 | BFD_RELOC_LO16); |
4d7206a2 | 4263 | relax_end (); |
ed6fb7bd | 4264 | |
f5040a92 AO |
4265 | if (ex.X_add_number != 0) |
4266 | { | |
4267 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4268 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4269 | ex.X_op = O_constant; | |
67c0d1eb | 4270 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4271 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4272 | } |
252b5132 RH |
4273 | } |
4274 | } | |
0a44bf69 | 4275 | else if (mips_big_got) |
252b5132 RH |
4276 | { |
4277 | expressionS ex; | |
252b5132 RH |
4278 | |
4279 | /* This is the large GOT case. If this is a reference to an | |
4280 | external symbol, we want | |
4281 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4282 | addu $reg,$reg,$gp | |
4283 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4284 | |
4285 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4286 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4287 | nop | |
4288 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4289 | If there is a constant, it must be added in after. |
f5040a92 AO |
4290 | |
4291 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4292 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4293 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4294 | */ |
438c16b8 TS |
4295 | if (HAVE_NEWABI) |
4296 | { | |
4d7206a2 | 4297 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4298 | ep->X_add_number = 0; |
4d7206a2 | 4299 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4300 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4301 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4302 | reg, reg, mips_gp_register); | |
4303 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4304 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4305 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4306 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4307 | else if (ex.X_add_number) | |
4308 | { | |
4309 | ex.X_op = O_constant; | |
67c0d1eb RS |
4310 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4311 | BFD_RELOC_LO16); | |
f5040a92 AO |
4312 | } |
4313 | ||
4314 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4315 | relax_switch (); |
67c0d1eb | 4316 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4317 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4318 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4319 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4320 | relax_end (); |
438c16b8 | 4321 | } |
252b5132 | 4322 | else |
438c16b8 | 4323 | { |
f5040a92 AO |
4324 | ex.X_add_number = ep->X_add_number; |
4325 | ep->X_add_number = 0; | |
4d7206a2 | 4326 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4327 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4328 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4329 | reg, reg, mips_gp_register); | |
4330 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4331 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4332 | relax_switch (); |
4333 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4334 | { |
4335 | /* We need a nop before loading from $gp. This special | |
4336 | check is required because the lui which starts the main | |
4337 | instruction stream does not refer to $gp, and so will not | |
4338 | insert the nop which may be required. */ | |
67c0d1eb | 4339 | macro_build (NULL, "nop", ""); |
438c16b8 | 4340 | } |
67c0d1eb | 4341 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4342 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4343 | load_delay_nop (); |
67c0d1eb | 4344 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4345 | BFD_RELOC_LO16); |
4d7206a2 | 4346 | relax_end (); |
438c16b8 | 4347 | |
f5040a92 AO |
4348 | if (ex.X_add_number != 0) |
4349 | { | |
4350 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4351 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4352 | ex.X_op = O_constant; | |
67c0d1eb RS |
4353 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4354 | BFD_RELOC_LO16); | |
f5040a92 | 4355 | } |
252b5132 RH |
4356 | } |
4357 | } | |
252b5132 RH |
4358 | else |
4359 | abort (); | |
8fc2e39e TS |
4360 | |
4361 | if (mips_opts.noat && *used_at == 1) | |
4362 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4363 | } |
4364 | ||
ea1fb5dc RS |
4365 | /* Move the contents of register SOURCE into register DEST. */ |
4366 | ||
4367 | static void | |
67c0d1eb | 4368 | move_register (int dest, int source) |
ea1fb5dc | 4369 | { |
67c0d1eb RS |
4370 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4371 | dest, source, 0); | |
ea1fb5dc RS |
4372 | } |
4373 | ||
4d7206a2 | 4374 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4375 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4376 | The two alternatives are: | |
4d7206a2 RS |
4377 | |
4378 | Global symbol Local sybmol | |
4379 | ------------- ------------ | |
4380 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4381 | ... ... | |
4382 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4383 | ||
4384 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4385 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4386 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4387 | |
4388 | static void | |
67c0d1eb | 4389 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4390 | { |
4391 | expressionS global; | |
4392 | ||
4393 | global = *local; | |
4394 | global.X_add_number = 0; | |
4395 | ||
4396 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4397 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4398 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4399 | relax_switch (); |
67c0d1eb RS |
4400 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4401 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4402 | relax_end (); |
4403 | } | |
4404 | ||
4405 | static void | |
67c0d1eb | 4406 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4407 | { |
4408 | expressionS global; | |
4409 | ||
4410 | global.X_op = O_constant; | |
4411 | global.X_op_symbol = NULL; | |
4412 | global.X_add_symbol = NULL; | |
4413 | global.X_add_number = local->X_add_number; | |
4414 | ||
4415 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4416 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4417 | dest, dest, BFD_RELOC_LO16); |
4418 | relax_switch (); | |
67c0d1eb | 4419 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4420 | relax_end (); |
4421 | } | |
4422 | ||
f6a22291 MR |
4423 | static void |
4424 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4425 | { | |
4426 | expressionS global; | |
4427 | int hold_mips_optimize; | |
4428 | ||
4429 | global.X_op = O_constant; | |
4430 | global.X_op_symbol = NULL; | |
4431 | global.X_add_symbol = NULL; | |
4432 | global.X_add_number = local->X_add_number; | |
4433 | ||
4434 | relax_start (local->X_add_symbol); | |
4435 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4436 | relax_switch (); | |
4437 | /* Set mips_optimize around the lui instruction to avoid | |
4438 | inserting an unnecessary nop after the lw. */ | |
4439 | hold_mips_optimize = mips_optimize; | |
4440 | mips_optimize = 2; | |
4441 | macro_build_lui (&global, tmp); | |
4442 | mips_optimize = hold_mips_optimize; | |
4443 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4444 | relax_end (); | |
4445 | ||
4446 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4447 | } | |
4448 | ||
252b5132 RH |
4449 | /* |
4450 | * Build macros | |
4451 | * This routine implements the seemingly endless macro or synthesized | |
4452 | * instructions and addressing modes in the mips assembly language. Many | |
4453 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4454 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4455 | * this verbose method. Others are not simple macros but are more like |
4456 | * optimizing code generation. | |
4457 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4458 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4459 | * The ensuing load upper instructions are ommited. This implies some kind |
4460 | * of global optimization. We currently only optimize within a single macro. | |
4461 | * For many of the load and store macros if the address is specified as a | |
4462 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4463 | * first load register 'at' with zero and use it as the base register. The | |
4464 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4465 | * we're missing. | |
4466 | */ | |
4467 | static void | |
17a2f251 | 4468 | macro (struct mips_cl_insn *ip) |
252b5132 | 4469 | { |
3994f87e | 4470 | int treg, sreg, dreg, breg; |
252b5132 RH |
4471 | int tempreg; |
4472 | int mask; | |
43841e91 | 4473 | int used_at = 0; |
252b5132 RH |
4474 | expressionS expr1; |
4475 | const char *s; | |
4476 | const char *s2; | |
4477 | const char *fmt; | |
4478 | int likely = 0; | |
4479 | int dbl = 0; | |
4480 | int coproc = 0; | |
4481 | int lr = 0; | |
4482 | int imm = 0; | |
1abe91b1 | 4483 | int call = 0; |
252b5132 | 4484 | int off; |
67c0d1eb | 4485 | offsetT maxnum; |
252b5132 | 4486 | bfd_reloc_code_real_type r; |
252b5132 RH |
4487 | int hold_mips_optimize; |
4488 | ||
4489 | assert (! mips_opts.mips16); | |
4490 | ||
4491 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4492 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4493 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4494 | mask = ip->insn_mo->mask; | |
4495 | ||
4496 | expr1.X_op = O_constant; | |
4497 | expr1.X_op_symbol = NULL; | |
4498 | expr1.X_add_symbol = NULL; | |
4499 | expr1.X_add_number = 1; | |
4500 | ||
4501 | switch (mask) | |
4502 | { | |
4503 | case M_DABS: | |
4504 | dbl = 1; | |
4505 | case M_ABS: | |
4506 | /* bgez $a0,.+12 | |
4507 | move v0,$a0 | |
4508 | sub v0,$zero,$a0 | |
4509 | */ | |
4510 | ||
7d10b47d | 4511 | start_noreorder (); |
252b5132 RH |
4512 | |
4513 | expr1.X_add_number = 8; | |
67c0d1eb | 4514 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4515 | if (dreg == sreg) |
67c0d1eb | 4516 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4517 | else |
67c0d1eb RS |
4518 | move_register (dreg, sreg); |
4519 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4520 | |
7d10b47d | 4521 | end_noreorder (); |
8fc2e39e | 4522 | break; |
252b5132 RH |
4523 | |
4524 | case M_ADD_I: | |
4525 | s = "addi"; | |
4526 | s2 = "add"; | |
4527 | goto do_addi; | |
4528 | case M_ADDU_I: | |
4529 | s = "addiu"; | |
4530 | s2 = "addu"; | |
4531 | goto do_addi; | |
4532 | case M_DADD_I: | |
4533 | dbl = 1; | |
4534 | s = "daddi"; | |
4535 | s2 = "dadd"; | |
4536 | goto do_addi; | |
4537 | case M_DADDU_I: | |
4538 | dbl = 1; | |
4539 | s = "daddiu"; | |
4540 | s2 = "daddu"; | |
4541 | do_addi: | |
4542 | if (imm_expr.X_op == O_constant | |
4543 | && imm_expr.X_add_number >= -0x8000 | |
4544 | && imm_expr.X_add_number < 0x8000) | |
4545 | { | |
67c0d1eb | 4546 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4547 | break; |
252b5132 | 4548 | } |
8fc2e39e | 4549 | used_at = 1; |
67c0d1eb RS |
4550 | load_register (AT, &imm_expr, dbl); |
4551 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4552 | break; |
4553 | ||
4554 | case M_AND_I: | |
4555 | s = "andi"; | |
4556 | s2 = "and"; | |
4557 | goto do_bit; | |
4558 | case M_OR_I: | |
4559 | s = "ori"; | |
4560 | s2 = "or"; | |
4561 | goto do_bit; | |
4562 | case M_NOR_I: | |
4563 | s = ""; | |
4564 | s2 = "nor"; | |
4565 | goto do_bit; | |
4566 | case M_XOR_I: | |
4567 | s = "xori"; | |
4568 | s2 = "xor"; | |
4569 | do_bit: | |
4570 | if (imm_expr.X_op == O_constant | |
4571 | && imm_expr.X_add_number >= 0 | |
4572 | && imm_expr.X_add_number < 0x10000) | |
4573 | { | |
4574 | if (mask != M_NOR_I) | |
67c0d1eb | 4575 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4576 | else |
4577 | { | |
67c0d1eb RS |
4578 | macro_build (&imm_expr, "ori", "t,r,i", |
4579 | treg, sreg, BFD_RELOC_LO16); | |
4580 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4581 | } |
8fc2e39e | 4582 | break; |
252b5132 RH |
4583 | } |
4584 | ||
8fc2e39e | 4585 | used_at = 1; |
67c0d1eb RS |
4586 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4587 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4588 | break; |
4589 | ||
4590 | case M_BEQ_I: | |
4591 | s = "beq"; | |
4592 | goto beq_i; | |
4593 | case M_BEQL_I: | |
4594 | s = "beql"; | |
4595 | likely = 1; | |
4596 | goto beq_i; | |
4597 | case M_BNE_I: | |
4598 | s = "bne"; | |
4599 | goto beq_i; | |
4600 | case M_BNEL_I: | |
4601 | s = "bnel"; | |
4602 | likely = 1; | |
4603 | beq_i: | |
4604 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4605 | { | |
67c0d1eb | 4606 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4607 | break; |
252b5132 | 4608 | } |
8fc2e39e | 4609 | used_at = 1; |
67c0d1eb RS |
4610 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4611 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4612 | break; |
4613 | ||
4614 | case M_BGEL: | |
4615 | likely = 1; | |
4616 | case M_BGE: | |
4617 | if (treg == 0) | |
4618 | { | |
67c0d1eb | 4619 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4620 | break; |
252b5132 RH |
4621 | } |
4622 | if (sreg == 0) | |
4623 | { | |
67c0d1eb | 4624 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4625 | break; |
252b5132 | 4626 | } |
8fc2e39e | 4627 | used_at = 1; |
67c0d1eb RS |
4628 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4629 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4630 | break; |
4631 | ||
4632 | case M_BGTL_I: | |
4633 | likely = 1; | |
4634 | case M_BGT_I: | |
4635 | /* check for > max integer */ | |
4636 | maxnum = 0x7fffffff; | |
ca4e0257 | 4637 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4638 | { |
4639 | maxnum <<= 16; | |
4640 | maxnum |= 0xffff; | |
4641 | maxnum <<= 16; | |
4642 | maxnum |= 0xffff; | |
4643 | } | |
4644 | if (imm_expr.X_op == O_constant | |
4645 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4646 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4647 | { |
4648 | do_false: | |
4649 | /* result is always false */ | |
4650 | if (! likely) | |
67c0d1eb | 4651 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4652 | else |
67c0d1eb | 4653 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4654 | break; |
252b5132 RH |
4655 | } |
4656 | if (imm_expr.X_op != O_constant) | |
4657 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4658 | ++imm_expr.X_add_number; |
252b5132 RH |
4659 | /* FALLTHROUGH */ |
4660 | case M_BGE_I: | |
4661 | case M_BGEL_I: | |
4662 | if (mask == M_BGEL_I) | |
4663 | likely = 1; | |
4664 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4665 | { | |
67c0d1eb | 4666 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4667 | break; |
252b5132 RH |
4668 | } |
4669 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4670 | { | |
67c0d1eb | 4671 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4672 | break; |
252b5132 RH |
4673 | } |
4674 | maxnum = 0x7fffffff; | |
ca4e0257 | 4675 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4676 | { |
4677 | maxnum <<= 16; | |
4678 | maxnum |= 0xffff; | |
4679 | maxnum <<= 16; | |
4680 | maxnum |= 0xffff; | |
4681 | } | |
4682 | maxnum = - maxnum - 1; | |
4683 | if (imm_expr.X_op == O_constant | |
4684 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4685 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4686 | { |
4687 | do_true: | |
4688 | /* result is always true */ | |
4689 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4690 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4691 | break; |
252b5132 | 4692 | } |
8fc2e39e | 4693 | used_at = 1; |
67c0d1eb RS |
4694 | set_at (sreg, 0); |
4695 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4696 | break; |
4697 | ||
4698 | case M_BGEUL: | |
4699 | likely = 1; | |
4700 | case M_BGEU: | |
4701 | if (treg == 0) | |
4702 | goto do_true; | |
4703 | if (sreg == 0) | |
4704 | { | |
67c0d1eb | 4705 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4706 | "s,t,p", 0, treg); |
8fc2e39e | 4707 | break; |
252b5132 | 4708 | } |
8fc2e39e | 4709 | used_at = 1; |
67c0d1eb RS |
4710 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4711 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4712 | break; |
4713 | ||
4714 | case M_BGTUL_I: | |
4715 | likely = 1; | |
4716 | case M_BGTU_I: | |
4717 | if (sreg == 0 | |
ca4e0257 | 4718 | || (HAVE_32BIT_GPRS |
252b5132 | 4719 | && imm_expr.X_op == O_constant |
956cd1d6 | 4720 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4721 | goto do_false; |
4722 | if (imm_expr.X_op != O_constant) | |
4723 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4724 | ++imm_expr.X_add_number; |
252b5132 RH |
4725 | /* FALLTHROUGH */ |
4726 | case M_BGEU_I: | |
4727 | case M_BGEUL_I: | |
4728 | if (mask == M_BGEUL_I) | |
4729 | likely = 1; | |
4730 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4731 | goto do_true; | |
4732 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4733 | { | |
67c0d1eb | 4734 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4735 | "s,t,p", sreg, 0); |
8fc2e39e | 4736 | break; |
252b5132 | 4737 | } |
8fc2e39e | 4738 | used_at = 1; |
67c0d1eb RS |
4739 | set_at (sreg, 1); |
4740 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4741 | break; |
4742 | ||
4743 | case M_BGTL: | |
4744 | likely = 1; | |
4745 | case M_BGT: | |
4746 | if (treg == 0) | |
4747 | { | |
67c0d1eb | 4748 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4749 | break; |
252b5132 RH |
4750 | } |
4751 | if (sreg == 0) | |
4752 | { | |
67c0d1eb | 4753 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4754 | break; |
252b5132 | 4755 | } |
8fc2e39e | 4756 | used_at = 1; |
67c0d1eb RS |
4757 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4758 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4759 | break; |
4760 | ||
4761 | case M_BGTUL: | |
4762 | likely = 1; | |
4763 | case M_BGTU: | |
4764 | if (treg == 0) | |
4765 | { | |
67c0d1eb | 4766 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4767 | "s,t,p", sreg, 0); |
8fc2e39e | 4768 | break; |
252b5132 RH |
4769 | } |
4770 | if (sreg == 0) | |
4771 | goto do_false; | |
8fc2e39e | 4772 | used_at = 1; |
67c0d1eb RS |
4773 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4774 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4775 | break; |
4776 | ||
4777 | case M_BLEL: | |
4778 | likely = 1; | |
4779 | case M_BLE: | |
4780 | if (treg == 0) | |
4781 | { | |
67c0d1eb | 4782 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4783 | break; |
252b5132 RH |
4784 | } |
4785 | if (sreg == 0) | |
4786 | { | |
67c0d1eb | 4787 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4788 | break; |
252b5132 | 4789 | } |
8fc2e39e | 4790 | used_at = 1; |
67c0d1eb RS |
4791 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4792 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4793 | break; |
4794 | ||
4795 | case M_BLEL_I: | |
4796 | likely = 1; | |
4797 | case M_BLE_I: | |
4798 | maxnum = 0x7fffffff; | |
ca4e0257 | 4799 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4800 | { |
4801 | maxnum <<= 16; | |
4802 | maxnum |= 0xffff; | |
4803 | maxnum <<= 16; | |
4804 | maxnum |= 0xffff; | |
4805 | } | |
4806 | if (imm_expr.X_op == O_constant | |
4807 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4808 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4809 | goto do_true; |
4810 | if (imm_expr.X_op != O_constant) | |
4811 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4812 | ++imm_expr.X_add_number; |
252b5132 RH |
4813 | /* FALLTHROUGH */ |
4814 | case M_BLT_I: | |
4815 | case M_BLTL_I: | |
4816 | if (mask == M_BLTL_I) | |
4817 | likely = 1; | |
4818 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4819 | { | |
67c0d1eb | 4820 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4821 | break; |
252b5132 RH |
4822 | } |
4823 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4824 | { | |
67c0d1eb | 4825 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4826 | break; |
252b5132 | 4827 | } |
8fc2e39e | 4828 | used_at = 1; |
67c0d1eb RS |
4829 | set_at (sreg, 0); |
4830 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4831 | break; |
4832 | ||
4833 | case M_BLEUL: | |
4834 | likely = 1; | |
4835 | case M_BLEU: | |
4836 | if (treg == 0) | |
4837 | { | |
67c0d1eb | 4838 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4839 | "s,t,p", sreg, 0); |
8fc2e39e | 4840 | break; |
252b5132 RH |
4841 | } |
4842 | if (sreg == 0) | |
4843 | goto do_true; | |
8fc2e39e | 4844 | used_at = 1; |
67c0d1eb RS |
4845 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4846 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4847 | break; |
4848 | ||
4849 | case M_BLEUL_I: | |
4850 | likely = 1; | |
4851 | case M_BLEU_I: | |
4852 | if (sreg == 0 | |
ca4e0257 | 4853 | || (HAVE_32BIT_GPRS |
252b5132 | 4854 | && imm_expr.X_op == O_constant |
956cd1d6 | 4855 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4856 | goto do_true; |
4857 | if (imm_expr.X_op != O_constant) | |
4858 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4859 | ++imm_expr.X_add_number; |
252b5132 RH |
4860 | /* FALLTHROUGH */ |
4861 | case M_BLTU_I: | |
4862 | case M_BLTUL_I: | |
4863 | if (mask == M_BLTUL_I) | |
4864 | likely = 1; | |
4865 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4866 | goto do_false; | |
4867 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4868 | { | |
67c0d1eb | 4869 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4870 | "s,t,p", sreg, 0); |
8fc2e39e | 4871 | break; |
252b5132 | 4872 | } |
8fc2e39e | 4873 | used_at = 1; |
67c0d1eb RS |
4874 | set_at (sreg, 1); |
4875 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4876 | break; |
4877 | ||
4878 | case M_BLTL: | |
4879 | likely = 1; | |
4880 | case M_BLT: | |
4881 | if (treg == 0) | |
4882 | { | |
67c0d1eb | 4883 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4884 | break; |
252b5132 RH |
4885 | } |
4886 | if (sreg == 0) | |
4887 | { | |
67c0d1eb | 4888 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4889 | break; |
252b5132 | 4890 | } |
8fc2e39e | 4891 | used_at = 1; |
67c0d1eb RS |
4892 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4893 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4894 | break; |
4895 | ||
4896 | case M_BLTUL: | |
4897 | likely = 1; | |
4898 | case M_BLTU: | |
4899 | if (treg == 0) | |
4900 | goto do_false; | |
4901 | if (sreg == 0) | |
4902 | { | |
67c0d1eb | 4903 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4904 | "s,t,p", 0, treg); |
8fc2e39e | 4905 | break; |
252b5132 | 4906 | } |
8fc2e39e | 4907 | used_at = 1; |
67c0d1eb RS |
4908 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4909 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4910 | break; |
4911 | ||
5f74bc13 CD |
4912 | case M_DEXT: |
4913 | { | |
4914 | unsigned long pos; | |
4915 | unsigned long size; | |
4916 | ||
4917 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4918 | { | |
4919 | as_bad (_("Unsupported large constant")); | |
4920 | pos = size = 1; | |
4921 | } | |
4922 | else | |
4923 | { | |
4924 | pos = (unsigned long) imm_expr.X_add_number; | |
4925 | size = (unsigned long) imm2_expr.X_add_number; | |
4926 | } | |
4927 | ||
4928 | if (pos > 63) | |
4929 | { | |
4930 | as_bad (_("Improper position (%lu)"), pos); | |
4931 | pos = 1; | |
4932 | } | |
4933 | if (size == 0 || size > 64 | |
4934 | || (pos + size - 1) > 63) | |
4935 | { | |
4936 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4937 | size, pos); | |
4938 | size = 1; | |
4939 | } | |
4940 | ||
4941 | if (size <= 32 && pos < 32) | |
4942 | { | |
4943 | s = "dext"; | |
4944 | fmt = "t,r,+A,+C"; | |
4945 | } | |
4946 | else if (size <= 32) | |
4947 | { | |
4948 | s = "dextu"; | |
4949 | fmt = "t,r,+E,+H"; | |
4950 | } | |
4951 | else | |
4952 | { | |
4953 | s = "dextm"; | |
4954 | fmt = "t,r,+A,+G"; | |
4955 | } | |
67c0d1eb | 4956 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4957 | } |
8fc2e39e | 4958 | break; |
5f74bc13 CD |
4959 | |
4960 | case M_DINS: | |
4961 | { | |
4962 | unsigned long pos; | |
4963 | unsigned long size; | |
4964 | ||
4965 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4966 | { | |
4967 | as_bad (_("Unsupported large constant")); | |
4968 | pos = size = 1; | |
4969 | } | |
4970 | else | |
4971 | { | |
4972 | pos = (unsigned long) imm_expr.X_add_number; | |
4973 | size = (unsigned long) imm2_expr.X_add_number; | |
4974 | } | |
4975 | ||
4976 | if (pos > 63) | |
4977 | { | |
4978 | as_bad (_("Improper position (%lu)"), pos); | |
4979 | pos = 1; | |
4980 | } | |
4981 | if (size == 0 || size > 64 | |
4982 | || (pos + size - 1) > 63) | |
4983 | { | |
4984 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4985 | size, pos); | |
4986 | size = 1; | |
4987 | } | |
4988 | ||
4989 | if (pos < 32 && (pos + size - 1) < 32) | |
4990 | { | |
4991 | s = "dins"; | |
4992 | fmt = "t,r,+A,+B"; | |
4993 | } | |
4994 | else if (pos >= 32) | |
4995 | { | |
4996 | s = "dinsu"; | |
4997 | fmt = "t,r,+E,+F"; | |
4998 | } | |
4999 | else | |
5000 | { | |
5001 | s = "dinsm"; | |
5002 | fmt = "t,r,+A,+F"; | |
5003 | } | |
67c0d1eb RS |
5004 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
5005 | pos + size - 1); | |
5f74bc13 | 5006 | } |
8fc2e39e | 5007 | break; |
5f74bc13 | 5008 | |
252b5132 RH |
5009 | case M_DDIV_3: |
5010 | dbl = 1; | |
5011 | case M_DIV_3: | |
5012 | s = "mflo"; | |
5013 | goto do_div3; | |
5014 | case M_DREM_3: | |
5015 | dbl = 1; | |
5016 | case M_REM_3: | |
5017 | s = "mfhi"; | |
5018 | do_div3: | |
5019 | if (treg == 0) | |
5020 | { | |
5021 | as_warn (_("Divide by zero.")); | |
5022 | if (mips_trap) | |
67c0d1eb | 5023 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5024 | else |
67c0d1eb | 5025 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5026 | break; |
252b5132 RH |
5027 | } |
5028 | ||
7d10b47d | 5029 | start_noreorder (); |
252b5132 RH |
5030 | if (mips_trap) |
5031 | { | |
67c0d1eb RS |
5032 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5033 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5034 | } |
5035 | else | |
5036 | { | |
5037 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5038 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5039 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5040 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5041 | } |
5042 | expr1.X_add_number = -1; | |
8fc2e39e | 5043 | used_at = 1; |
f6a22291 | 5044 | load_register (AT, &expr1, dbl); |
252b5132 | 5045 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5046 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5047 | if (dbl) |
5048 | { | |
5049 | expr1.X_add_number = 1; | |
f6a22291 | 5050 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5051 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5052 | } |
5053 | else | |
5054 | { | |
5055 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5056 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5057 | } |
5058 | if (mips_trap) | |
5059 | { | |
67c0d1eb | 5060 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5061 | /* We want to close the noreorder block as soon as possible, so |
5062 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5063 | end_noreorder (); |
252b5132 RH |
5064 | } |
5065 | else | |
5066 | { | |
5067 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5068 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5069 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5070 | |
5071 | /* We want to close the noreorder block as soon as possible, so | |
5072 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5073 | end_noreorder (); |
252b5132 | 5074 | |
67c0d1eb | 5075 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5076 | } |
67c0d1eb | 5077 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5078 | break; |
5079 | ||
5080 | case M_DIV_3I: | |
5081 | s = "div"; | |
5082 | s2 = "mflo"; | |
5083 | goto do_divi; | |
5084 | case M_DIVU_3I: | |
5085 | s = "divu"; | |
5086 | s2 = "mflo"; | |
5087 | goto do_divi; | |
5088 | case M_REM_3I: | |
5089 | s = "div"; | |
5090 | s2 = "mfhi"; | |
5091 | goto do_divi; | |
5092 | case M_REMU_3I: | |
5093 | s = "divu"; | |
5094 | s2 = "mfhi"; | |
5095 | goto do_divi; | |
5096 | case M_DDIV_3I: | |
5097 | dbl = 1; | |
5098 | s = "ddiv"; | |
5099 | s2 = "mflo"; | |
5100 | goto do_divi; | |
5101 | case M_DDIVU_3I: | |
5102 | dbl = 1; | |
5103 | s = "ddivu"; | |
5104 | s2 = "mflo"; | |
5105 | goto do_divi; | |
5106 | case M_DREM_3I: | |
5107 | dbl = 1; | |
5108 | s = "ddiv"; | |
5109 | s2 = "mfhi"; | |
5110 | goto do_divi; | |
5111 | case M_DREMU_3I: | |
5112 | dbl = 1; | |
5113 | s = "ddivu"; | |
5114 | s2 = "mfhi"; | |
5115 | do_divi: | |
5116 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5117 | { | |
5118 | as_warn (_("Divide by zero.")); | |
5119 | if (mips_trap) | |
67c0d1eb | 5120 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5121 | else |
67c0d1eb | 5122 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5123 | break; |
252b5132 RH |
5124 | } |
5125 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5126 | { | |
5127 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5128 | move_register (dreg, sreg); |
252b5132 | 5129 | else |
67c0d1eb | 5130 | move_register (dreg, 0); |
8fc2e39e | 5131 | break; |
252b5132 RH |
5132 | } |
5133 | if (imm_expr.X_op == O_constant | |
5134 | && imm_expr.X_add_number == -1 | |
5135 | && s[strlen (s) - 1] != 'u') | |
5136 | { | |
5137 | if (strcmp (s2, "mflo") == 0) | |
5138 | { | |
67c0d1eb | 5139 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5140 | } |
5141 | else | |
67c0d1eb | 5142 | move_register (dreg, 0); |
8fc2e39e | 5143 | break; |
252b5132 RH |
5144 | } |
5145 | ||
8fc2e39e | 5146 | used_at = 1; |
67c0d1eb RS |
5147 | load_register (AT, &imm_expr, dbl); |
5148 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5149 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5150 | break; |
5151 | ||
5152 | case M_DIVU_3: | |
5153 | s = "divu"; | |
5154 | s2 = "mflo"; | |
5155 | goto do_divu3; | |
5156 | case M_REMU_3: | |
5157 | s = "divu"; | |
5158 | s2 = "mfhi"; | |
5159 | goto do_divu3; | |
5160 | case M_DDIVU_3: | |
5161 | s = "ddivu"; | |
5162 | s2 = "mflo"; | |
5163 | goto do_divu3; | |
5164 | case M_DREMU_3: | |
5165 | s = "ddivu"; | |
5166 | s2 = "mfhi"; | |
5167 | do_divu3: | |
7d10b47d | 5168 | start_noreorder (); |
252b5132 RH |
5169 | if (mips_trap) |
5170 | { | |
67c0d1eb RS |
5171 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5172 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5173 | /* We want to close the noreorder block as soon as possible, so |
5174 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5175 | end_noreorder (); |
252b5132 RH |
5176 | } |
5177 | else | |
5178 | { | |
5179 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5180 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5181 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5182 | |
5183 | /* We want to close the noreorder block as soon as possible, so | |
5184 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5185 | end_noreorder (); |
67c0d1eb | 5186 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5187 | } |
67c0d1eb | 5188 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5189 | break; |
252b5132 | 5190 | |
1abe91b1 MR |
5191 | case M_DLCA_AB: |
5192 | dbl = 1; | |
5193 | case M_LCA_AB: | |
5194 | call = 1; | |
5195 | goto do_la; | |
252b5132 RH |
5196 | case M_DLA_AB: |
5197 | dbl = 1; | |
5198 | case M_LA_AB: | |
1abe91b1 | 5199 | do_la: |
252b5132 RH |
5200 | /* Load the address of a symbol into a register. If breg is not |
5201 | zero, we then add a base register to it. */ | |
5202 | ||
3bec30a8 TS |
5203 | if (dbl && HAVE_32BIT_GPRS) |
5204 | as_warn (_("dla used to load 32-bit register")); | |
5205 | ||
c90bbe5b | 5206 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5207 | as_warn (_("la used to load 64-bit address")); |
5208 | ||
0c11417f MR |
5209 | if (offset_expr.X_op == O_constant |
5210 | && offset_expr.X_add_number >= -0x8000 | |
5211 | && offset_expr.X_add_number < 0x8000) | |
5212 | { | |
aed1a261 | 5213 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5214 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5215 | break; |
0c11417f MR |
5216 | } |
5217 | ||
b8285c27 | 5218 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
5219 | { |
5220 | tempreg = AT; | |
5221 | used_at = 1; | |
5222 | } | |
5223 | else | |
5224 | { | |
5225 | tempreg = treg; | |
afdbd6d0 CD |
5226 | } |
5227 | ||
252b5132 RH |
5228 | if (offset_expr.X_op != O_symbol |
5229 | && offset_expr.X_op != O_constant) | |
5230 | { | |
5231 | as_bad (_("expression too complex")); | |
5232 | offset_expr.X_op = O_constant; | |
5233 | } | |
5234 | ||
252b5132 | 5235 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5236 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5237 | else if (mips_pic == NO_PIC) |
5238 | { | |
d6bc6245 | 5239 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5240 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5241 | Otherwise we want |
5242 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5243 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5244 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5245 | so we may as well always use the latter form. |
76b3015f | 5246 | |
6caf9ef4 TS |
5247 | With 64bit address space and a usable $at we want |
5248 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5249 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5250 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5251 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5252 | dsll32 $tempreg,0 | |
5253 | daddu $tempreg,$tempreg,$at | |
5254 | ||
5255 | If $at is already in use, we use a path which is suboptimal | |
5256 | on superscalar processors. | |
5257 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5258 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5259 | dsll $tempreg,16 | |
5260 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5261 | dsll $tempreg,16 | |
5262 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5263 | ||
5264 | For GP relative symbols in 64bit address space we can use | |
5265 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5266 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5267 | { |
6caf9ef4 TS |
5268 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5269 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5270 | { | |
5271 | relax_start (offset_expr.X_add_symbol); | |
5272 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5273 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5274 | relax_switch (); | |
5275 | } | |
d6bc6245 | 5276 | |
b8285c27 | 5277 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 5278 | { |
67c0d1eb | 5279 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5280 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5281 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5282 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5283 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5284 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5285 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5286 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5287 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5288 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5289 | used_at = 1; |
5290 | } | |
5291 | else | |
5292 | { | |
67c0d1eb | 5293 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5294 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5295 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5296 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5297 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5298 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5299 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5300 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5301 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5302 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5303 | } |
6caf9ef4 TS |
5304 | |
5305 | if (mips_relax.sequence) | |
5306 | relax_end (); | |
98d3f06f KH |
5307 | } |
5308 | else | |
5309 | { | |
5310 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5311 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5312 | { |
4d7206a2 | 5313 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5314 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5315 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5316 | relax_switch (); |
98d3f06f | 5317 | } |
6943caf0 ILT |
5318 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5319 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5320 | macro_build_lui (&offset_expr, tempreg); |
5321 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5322 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5323 | if (mips_relax.sequence) |
5324 | relax_end (); | |
98d3f06f | 5325 | } |
252b5132 | 5326 | } |
0a44bf69 | 5327 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5328 | { |
9117d219 NC |
5329 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5330 | ||
252b5132 RH |
5331 | /* If this is a reference to an external symbol, and there |
5332 | is no constant, we want | |
5333 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5334 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5335 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5336 | For a local symbol, we want |
5337 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5338 | nop | |
5339 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5340 | ||
5341 | If we have a small constant, and this is a reference to | |
5342 | an external symbol, we want | |
5343 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5344 | nop | |
5345 | addiu $tempreg,$tempreg,<constant> | |
5346 | For a local symbol, we want the same instruction | |
5347 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5348 | addiu instruction. | |
5349 | ||
5350 | If we have a large constant, and this is a reference to | |
5351 | an external symbol, we want | |
5352 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5353 | lui $at,<hiconstant> | |
5354 | addiu $at,$at,<loconstant> | |
5355 | addu $tempreg,$tempreg,$at | |
5356 | For a local symbol, we want the same instruction | |
5357 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5358 | addiu instruction. |
ed6fb7bd SC |
5359 | */ |
5360 | ||
4d7206a2 | 5361 | if (offset_expr.X_add_number == 0) |
252b5132 | 5362 | { |
0a44bf69 RS |
5363 | if (mips_pic == SVR4_PIC |
5364 | && breg == 0 | |
5365 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5366 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5367 | ||
5368 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5369 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5370 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5371 | if (breg != 0) |
252b5132 RH |
5372 | { |
5373 | /* We're going to put in an addu instruction using | |
5374 | tempreg, so we may as well insert the nop right | |
5375 | now. */ | |
269137b2 | 5376 | load_delay_nop (); |
252b5132 | 5377 | } |
4d7206a2 | 5378 | relax_switch (); |
67c0d1eb RS |
5379 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5380 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5381 | load_delay_nop (); |
67c0d1eb RS |
5382 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5383 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5384 | relax_end (); |
252b5132 RH |
5385 | /* FIXME: If breg == 0, and the next instruction uses |
5386 | $tempreg, then if this variant case is used an extra | |
5387 | nop will be generated. */ | |
5388 | } | |
4d7206a2 RS |
5389 | else if (offset_expr.X_add_number >= -0x8000 |
5390 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5391 | { |
67c0d1eb | 5392 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5393 | load_delay_nop (); |
67c0d1eb | 5394 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5395 | } |
5396 | else | |
5397 | { | |
4d7206a2 RS |
5398 | expr1.X_add_number = offset_expr.X_add_number; |
5399 | offset_expr.X_add_number = | |
5400 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5401 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5402 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5403 | /* If we are going to add in a base register, and the |
5404 | target register and the base register are the same, | |
5405 | then we are using AT as a temporary register. Since | |
5406 | we want to load the constant into AT, we add our | |
5407 | current AT (from the global offset table) and the | |
5408 | register into the register now, and pretend we were | |
5409 | not using a base register. */ | |
67c0d1eb | 5410 | if (breg == treg) |
252b5132 | 5411 | { |
269137b2 | 5412 | load_delay_nop (); |
67c0d1eb | 5413 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5414 | treg, AT, breg); |
252b5132 RH |
5415 | breg = 0; |
5416 | tempreg = treg; | |
252b5132 | 5417 | } |
f6a22291 | 5418 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5419 | used_at = 1; |
5420 | } | |
5421 | } | |
0a44bf69 | 5422 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5423 | { |
67c0d1eb | 5424 | int add_breg_early = 0; |
f5040a92 AO |
5425 | |
5426 | /* If this is a reference to an external, and there is no | |
5427 | constant, or local symbol (*), with or without a | |
5428 | constant, we want | |
5429 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5430 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5431 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5432 | ||
5433 | If we have a small constant, and this is a reference to | |
5434 | an external symbol, we want | |
5435 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5436 | addiu $tempreg,$tempreg,<constant> | |
5437 | ||
5438 | If we have a large constant, and this is a reference to | |
5439 | an external symbol, we want | |
5440 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5441 | lui $at,<hiconstant> | |
5442 | addiu $at,$at,<loconstant> | |
5443 | addu $tempreg,$tempreg,$at | |
5444 | ||
5445 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5446 | local symbols, even though it introduces an additional | |
5447 | instruction. */ | |
5448 | ||
f5040a92 AO |
5449 | if (offset_expr.X_add_number) |
5450 | { | |
4d7206a2 | 5451 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5452 | offset_expr.X_add_number = 0; |
5453 | ||
4d7206a2 | 5454 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5455 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5456 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5457 | |
5458 | if (expr1.X_add_number >= -0x8000 | |
5459 | && expr1.X_add_number < 0x8000) | |
5460 | { | |
67c0d1eb RS |
5461 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5462 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5463 | } |
ecd13cd3 | 5464 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5465 | { |
5466 | int dreg; | |
5467 | ||
5468 | /* If we are going to add in a base register, and the | |
5469 | target register and the base register are the same, | |
5470 | then we are using AT as a temporary register. Since | |
5471 | we want to load the constant into AT, we add our | |
5472 | current AT (from the global offset table) and the | |
5473 | register into the register now, and pretend we were | |
5474 | not using a base register. */ | |
5475 | if (breg != treg) | |
5476 | dreg = tempreg; | |
5477 | else | |
5478 | { | |
5479 | assert (tempreg == AT); | |
67c0d1eb RS |
5480 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5481 | treg, AT, breg); | |
f5040a92 | 5482 | dreg = treg; |
67c0d1eb | 5483 | add_breg_early = 1; |
f5040a92 AO |
5484 | } |
5485 | ||
f6a22291 | 5486 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5487 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5488 | dreg, dreg, AT); |
f5040a92 | 5489 | |
f5040a92 AO |
5490 | used_at = 1; |
5491 | } | |
5492 | else | |
5493 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5494 | ||
4d7206a2 | 5495 | relax_switch (); |
f5040a92 AO |
5496 | offset_expr.X_add_number = expr1.X_add_number; |
5497 | ||
67c0d1eb RS |
5498 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5499 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5500 | if (add_breg_early) | |
f5040a92 | 5501 | { |
67c0d1eb | 5502 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5503 | treg, tempreg, breg); |
f5040a92 AO |
5504 | breg = 0; |
5505 | tempreg = treg; | |
5506 | } | |
4d7206a2 | 5507 | relax_end (); |
f5040a92 | 5508 | } |
4d7206a2 | 5509 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5510 | { |
4d7206a2 | 5511 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5512 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5513 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5514 | relax_switch (); |
67c0d1eb RS |
5515 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5516 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5517 | relax_end (); |
f5040a92 | 5518 | } |
4d7206a2 | 5519 | else |
f5040a92 | 5520 | { |
67c0d1eb RS |
5521 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5522 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5523 | } |
5524 | } | |
0a44bf69 | 5525 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5526 | { |
67c0d1eb | 5527 | int gpdelay; |
9117d219 NC |
5528 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5529 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5530 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5531 | |
5532 | /* This is the large GOT case. If this is a reference to an | |
5533 | external symbol, and there is no constant, we want | |
5534 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5535 | addu $tempreg,$tempreg,$gp | |
5536 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5537 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5538 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5539 | addu $tempreg,$tempreg,$gp | |
5540 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5541 | For a local symbol, we want |
5542 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5543 | nop | |
5544 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5545 | ||
5546 | If we have a small constant, and this is a reference to | |
5547 | an external symbol, we want | |
5548 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5549 | addu $tempreg,$tempreg,$gp | |
5550 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5551 | nop | |
5552 | addiu $tempreg,$tempreg,<constant> | |
5553 | For a local symbol, we want | |
5554 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5555 | nop | |
5556 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5557 | ||
5558 | If we have a large constant, and this is a reference to | |
5559 | an external symbol, we want | |
5560 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5561 | addu $tempreg,$tempreg,$gp | |
5562 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5563 | lui $at,<hiconstant> | |
5564 | addiu $at,$at,<loconstant> | |
5565 | addu $tempreg,$tempreg,$at | |
5566 | For a local symbol, we want | |
5567 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5568 | lui $at,<hiconstant> | |
5569 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5570 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5571 | */ |
438c16b8 | 5572 | |
252b5132 RH |
5573 | expr1.X_add_number = offset_expr.X_add_number; |
5574 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5575 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5576 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5577 | if (expr1.X_add_number == 0 && breg == 0 |
5578 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5579 | { |
5580 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5581 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5582 | } | |
67c0d1eb RS |
5583 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5584 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5585 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5586 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5587 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5588 | if (expr1.X_add_number == 0) |
5589 | { | |
67c0d1eb | 5590 | if (breg != 0) |
252b5132 RH |
5591 | { |
5592 | /* We're going to put in an addu instruction using | |
5593 | tempreg, so we may as well insert the nop right | |
5594 | now. */ | |
269137b2 | 5595 | load_delay_nop (); |
252b5132 | 5596 | } |
252b5132 RH |
5597 | } |
5598 | else if (expr1.X_add_number >= -0x8000 | |
5599 | && expr1.X_add_number < 0x8000) | |
5600 | { | |
269137b2 | 5601 | load_delay_nop (); |
67c0d1eb | 5602 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5603 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5604 | } |
5605 | else | |
5606 | { | |
67c0d1eb | 5607 | int dreg; |
252b5132 RH |
5608 | |
5609 | /* If we are going to add in a base register, and the | |
5610 | target register and the base register are the same, | |
5611 | then we are using AT as a temporary register. Since | |
5612 | we want to load the constant into AT, we add our | |
5613 | current AT (from the global offset table) and the | |
5614 | register into the register now, and pretend we were | |
5615 | not using a base register. */ | |
5616 | if (breg != treg) | |
67c0d1eb | 5617 | dreg = tempreg; |
252b5132 RH |
5618 | else |
5619 | { | |
5620 | assert (tempreg == AT); | |
269137b2 | 5621 | load_delay_nop (); |
67c0d1eb | 5622 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5623 | treg, AT, breg); |
252b5132 | 5624 | dreg = treg; |
252b5132 RH |
5625 | } |
5626 | ||
f6a22291 | 5627 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5628 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5629 | |
252b5132 RH |
5630 | used_at = 1; |
5631 | } | |
4d7206a2 RS |
5632 | offset_expr.X_add_number = |
5633 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5634 | relax_switch (); | |
252b5132 | 5635 | |
67c0d1eb | 5636 | if (gpdelay) |
252b5132 RH |
5637 | { |
5638 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5639 | the first instruction on the main stream does not. */ |
67c0d1eb | 5640 | macro_build (NULL, "nop", ""); |
252b5132 | 5641 | } |
ed6fb7bd | 5642 | |
67c0d1eb RS |
5643 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5644 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5645 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5646 | && expr1.X_add_number < 0x8000) |
5647 | { | |
269137b2 | 5648 | load_delay_nop (); |
67c0d1eb RS |
5649 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5650 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5651 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5652 | register, the external symbol case ended with a load, |
5653 | so if the symbol turns out to not be external, and | |
5654 | the next instruction uses tempreg, an unnecessary nop | |
5655 | will be inserted. */ | |
252b5132 RH |
5656 | } |
5657 | else | |
5658 | { | |
5659 | if (breg == treg) | |
5660 | { | |
5661 | /* We must add in the base register now, as in the | |
f5040a92 | 5662 | external symbol case. */ |
252b5132 | 5663 | assert (tempreg == AT); |
269137b2 | 5664 | load_delay_nop (); |
67c0d1eb | 5665 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5666 | treg, AT, breg); |
252b5132 RH |
5667 | tempreg = treg; |
5668 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5669 | it in in both cases. */ |
252b5132 RH |
5670 | breg = 0; |
5671 | } | |
5672 | ||
67c0d1eb RS |
5673 | macro_build_lui (&expr1, AT); |
5674 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5675 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5676 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5677 | tempreg, tempreg, AT); |
8fc2e39e | 5678 | used_at = 1; |
252b5132 | 5679 | } |
4d7206a2 | 5680 | relax_end (); |
252b5132 | 5681 | } |
0a44bf69 | 5682 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5683 | { |
f5040a92 AO |
5684 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5685 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5686 | int add_breg_early = 0; |
f5040a92 AO |
5687 | |
5688 | /* This is the large GOT case. If this is a reference to an | |
5689 | external symbol, and there is no constant, we want | |
5690 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5691 | add $tempreg,$tempreg,$gp | |
5692 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5693 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5694 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5695 | add $tempreg,$tempreg,$gp | |
5696 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5697 | ||
5698 | If we have a small constant, and this is a reference to | |
5699 | an external symbol, we want | |
5700 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5701 | add $tempreg,$tempreg,$gp | |
5702 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5703 | addi $tempreg,$tempreg,<constant> | |
5704 | ||
5705 | If we have a large constant, and this is a reference to | |
5706 | an external symbol, we want | |
5707 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5708 | addu $tempreg,$tempreg,$gp | |
5709 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5710 | lui $at,<hiconstant> | |
5711 | addi $at,$at,<loconstant> | |
5712 | add $tempreg,$tempreg,$at | |
5713 | ||
5714 | If we have NewABI, and we know it's a local symbol, we want | |
5715 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5716 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5717 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5718 | ||
4d7206a2 | 5719 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5720 | |
4d7206a2 | 5721 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5722 | offset_expr.X_add_number = 0; |
5723 | ||
1abe91b1 MR |
5724 | if (expr1.X_add_number == 0 && breg == 0 |
5725 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5726 | { |
5727 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5728 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5729 | } | |
67c0d1eb RS |
5730 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5731 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5732 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5733 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5734 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5735 | |
5736 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5737 | ; |
f5040a92 AO |
5738 | else if (expr1.X_add_number >= -0x8000 |
5739 | && expr1.X_add_number < 0x8000) | |
5740 | { | |
67c0d1eb | 5741 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5742 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5743 | } |
ecd13cd3 | 5744 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5745 | { |
5746 | int dreg; | |
5747 | ||
5748 | /* If we are going to add in a base register, and the | |
5749 | target register and the base register are the same, | |
5750 | then we are using AT as a temporary register. Since | |
5751 | we want to load the constant into AT, we add our | |
5752 | current AT (from the global offset table) and the | |
5753 | register into the register now, and pretend we were | |
5754 | not using a base register. */ | |
5755 | if (breg != treg) | |
5756 | dreg = tempreg; | |
5757 | else | |
5758 | { | |
5759 | assert (tempreg == AT); | |
67c0d1eb | 5760 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5761 | treg, AT, breg); |
f5040a92 | 5762 | dreg = treg; |
67c0d1eb | 5763 | add_breg_early = 1; |
f5040a92 AO |
5764 | } |
5765 | ||
f6a22291 | 5766 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5767 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5768 | |
f5040a92 AO |
5769 | used_at = 1; |
5770 | } | |
5771 | else | |
5772 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5773 | ||
4d7206a2 | 5774 | relax_switch (); |
f5040a92 | 5775 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5776 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5777 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5778 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5779 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5780 | if (add_breg_early) | |
f5040a92 | 5781 | { |
67c0d1eb | 5782 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5783 | treg, tempreg, breg); |
f5040a92 AO |
5784 | breg = 0; |
5785 | tempreg = treg; | |
5786 | } | |
4d7206a2 | 5787 | relax_end (); |
f5040a92 | 5788 | } |
252b5132 RH |
5789 | else |
5790 | abort (); | |
5791 | ||
5792 | if (breg != 0) | |
aed1a261 | 5793 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5794 | break; |
5795 | ||
5796 | case M_J_A: | |
5797 | /* The j instruction may not be used in PIC code, since it | |
5798 | requires an absolute address. We convert it to a b | |
5799 | instruction. */ | |
5800 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5801 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5802 | else |
67c0d1eb | 5803 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5804 | break; |
252b5132 RH |
5805 | |
5806 | /* The jal instructions must be handled as macros because when | |
5807 | generating PIC code they expand to multi-instruction | |
5808 | sequences. Normally they are simple instructions. */ | |
5809 | case M_JAL_1: | |
5810 | dreg = RA; | |
5811 | /* Fall through. */ | |
5812 | case M_JAL_2: | |
3e722fb5 | 5813 | if (mips_pic == NO_PIC) |
67c0d1eb | 5814 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5815 | else |
252b5132 RH |
5816 | { |
5817 | if (sreg != PIC_CALL_REG) | |
5818 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5819 | |
67c0d1eb | 5820 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5821 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5822 | { |
6478892d TS |
5823 | if (mips_cprestore_offset < 0) |
5824 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5825 | else | |
5826 | { | |
7a621144 DJ |
5827 | if (! mips_frame_reg_valid) |
5828 | { | |
5829 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5830 | /* Quiet this warning. */ | |
5831 | mips_frame_reg_valid = 1; | |
5832 | } | |
5833 | if (! mips_cprestore_valid) | |
5834 | { | |
5835 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5836 | /* Quiet this warning. */ | |
5837 | mips_cprestore_valid = 1; | |
5838 | } | |
6478892d | 5839 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5840 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5841 | mips_gp_register, |
256ab948 TS |
5842 | mips_frame_reg, |
5843 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5844 | } |
252b5132 RH |
5845 | } |
5846 | } | |
252b5132 | 5847 | |
8fc2e39e | 5848 | break; |
252b5132 RH |
5849 | |
5850 | case M_JAL_A: | |
5851 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5852 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5853 | else if (mips_pic == SVR4_PIC) |
5854 | { | |
5855 | /* If this is a reference to an external symbol, and we are | |
5856 | using a small GOT, we want | |
5857 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5858 | nop | |
f9419b05 | 5859 | jalr $ra,$25 |
252b5132 RH |
5860 | nop |
5861 | lw $gp,cprestore($sp) | |
5862 | The cprestore value is set using the .cprestore | |
5863 | pseudo-op. If we are using a big GOT, we want | |
5864 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5865 | addu $25,$25,$gp | |
5866 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5867 | nop | |
f9419b05 | 5868 | jalr $ra,$25 |
252b5132 RH |
5869 | nop |
5870 | lw $gp,cprestore($sp) | |
5871 | If the symbol is not external, we want | |
5872 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5873 | nop | |
5874 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5875 | jalr $ra,$25 |
252b5132 | 5876 | nop |
438c16b8 | 5877 | lw $gp,cprestore($sp) |
f5040a92 AO |
5878 | |
5879 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5880 | sequences above, minus nops, unless the symbol is local, | |
5881 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5882 | GOT_DISP. */ | |
438c16b8 | 5883 | if (HAVE_NEWABI) |
252b5132 | 5884 | { |
f5040a92 AO |
5885 | if (! mips_big_got) |
5886 | { | |
4d7206a2 | 5887 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5888 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5889 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5890 | mips_gp_register); |
4d7206a2 | 5891 | relax_switch (); |
67c0d1eb RS |
5892 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5893 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5894 | mips_gp_register); |
5895 | relax_end (); | |
f5040a92 AO |
5896 | } |
5897 | else | |
5898 | { | |
4d7206a2 | 5899 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5900 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5901 | BFD_RELOC_MIPS_CALL_HI16); | |
5902 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5903 | PIC_CALL_REG, mips_gp_register); | |
5904 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5905 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5906 | PIC_CALL_REG); | |
4d7206a2 | 5907 | relax_switch (); |
67c0d1eb RS |
5908 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5909 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5910 | mips_gp_register); | |
5911 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5912 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5913 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5914 | relax_end (); |
f5040a92 | 5915 | } |
684022ea | 5916 | |
67c0d1eb | 5917 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5918 | } |
5919 | else | |
5920 | { | |
4d7206a2 | 5921 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5922 | if (! mips_big_got) |
5923 | { | |
67c0d1eb RS |
5924 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5925 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5926 | mips_gp_register); |
269137b2 | 5927 | load_delay_nop (); |
4d7206a2 | 5928 | relax_switch (); |
438c16b8 | 5929 | } |
252b5132 | 5930 | else |
252b5132 | 5931 | { |
67c0d1eb RS |
5932 | int gpdelay; |
5933 | ||
5934 | gpdelay = reg_needs_delay (mips_gp_register); | |
5935 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5936 | BFD_RELOC_MIPS_CALL_HI16); | |
5937 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5938 | PIC_CALL_REG, mips_gp_register); | |
5939 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5940 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5941 | PIC_CALL_REG); | |
269137b2 | 5942 | load_delay_nop (); |
4d7206a2 | 5943 | relax_switch (); |
67c0d1eb RS |
5944 | if (gpdelay) |
5945 | macro_build (NULL, "nop", ""); | |
252b5132 | 5946 | } |
67c0d1eb RS |
5947 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5948 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5949 | mips_gp_register); |
269137b2 | 5950 | load_delay_nop (); |
67c0d1eb RS |
5951 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5952 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5953 | relax_end (); |
67c0d1eb | 5954 | macro_build_jalr (&offset_expr); |
438c16b8 | 5955 | |
6478892d TS |
5956 | if (mips_cprestore_offset < 0) |
5957 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5958 | else | |
5959 | { | |
7a621144 DJ |
5960 | if (! mips_frame_reg_valid) |
5961 | { | |
5962 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5963 | /* Quiet this warning. */ | |
5964 | mips_frame_reg_valid = 1; | |
5965 | } | |
5966 | if (! mips_cprestore_valid) | |
5967 | { | |
5968 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5969 | /* Quiet this warning. */ | |
5970 | mips_cprestore_valid = 1; | |
5971 | } | |
6478892d | 5972 | if (mips_opts.noreorder) |
67c0d1eb | 5973 | macro_build (NULL, "nop", ""); |
6478892d | 5974 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5975 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5976 | mips_gp_register, |
256ab948 TS |
5977 | mips_frame_reg, |
5978 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5979 | } |
252b5132 RH |
5980 | } |
5981 | } | |
0a44bf69 RS |
5982 | else if (mips_pic == VXWORKS_PIC) |
5983 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
5984 | else |
5985 | abort (); | |
5986 | ||
8fc2e39e | 5987 | break; |
252b5132 RH |
5988 | |
5989 | case M_LB_AB: | |
5990 | s = "lb"; | |
5991 | goto ld; | |
5992 | case M_LBU_AB: | |
5993 | s = "lbu"; | |
5994 | goto ld; | |
5995 | case M_LH_AB: | |
5996 | s = "lh"; | |
5997 | goto ld; | |
5998 | case M_LHU_AB: | |
5999 | s = "lhu"; | |
6000 | goto ld; | |
6001 | case M_LW_AB: | |
6002 | s = "lw"; | |
6003 | goto ld; | |
6004 | case M_LWC0_AB: | |
6005 | s = "lwc0"; | |
bdaaa2e1 | 6006 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6007 | coproc = 1; |
6008 | goto ld; | |
6009 | case M_LWC1_AB: | |
6010 | s = "lwc1"; | |
bdaaa2e1 | 6011 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6012 | coproc = 1; |
6013 | goto ld; | |
6014 | case M_LWC2_AB: | |
6015 | s = "lwc2"; | |
bdaaa2e1 | 6016 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6017 | coproc = 1; |
6018 | goto ld; | |
6019 | case M_LWC3_AB: | |
6020 | s = "lwc3"; | |
bdaaa2e1 | 6021 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6022 | coproc = 1; |
6023 | goto ld; | |
6024 | case M_LWL_AB: | |
6025 | s = "lwl"; | |
6026 | lr = 1; | |
6027 | goto ld; | |
6028 | case M_LWR_AB: | |
6029 | s = "lwr"; | |
6030 | lr = 1; | |
6031 | goto ld; | |
6032 | case M_LDC1_AB: | |
fef14a42 | 6033 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6034 | { |
6035 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6036 | break; |
252b5132 RH |
6037 | } |
6038 | s = "ldc1"; | |
bdaaa2e1 | 6039 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6040 | coproc = 1; |
6041 | goto ld; | |
6042 | case M_LDC2_AB: | |
6043 | s = "ldc2"; | |
bdaaa2e1 | 6044 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6045 | coproc = 1; |
6046 | goto ld; | |
6047 | case M_LDC3_AB: | |
6048 | s = "ldc3"; | |
bdaaa2e1 | 6049 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6050 | coproc = 1; |
6051 | goto ld; | |
6052 | case M_LDL_AB: | |
6053 | s = "ldl"; | |
6054 | lr = 1; | |
6055 | goto ld; | |
6056 | case M_LDR_AB: | |
6057 | s = "ldr"; | |
6058 | lr = 1; | |
6059 | goto ld; | |
6060 | case M_LL_AB: | |
6061 | s = "ll"; | |
6062 | goto ld; | |
6063 | case M_LLD_AB: | |
6064 | s = "lld"; | |
6065 | goto ld; | |
6066 | case M_LWU_AB: | |
6067 | s = "lwu"; | |
6068 | ld: | |
8fc2e39e | 6069 | if (breg == treg || coproc || lr) |
252b5132 RH |
6070 | { |
6071 | tempreg = AT; | |
6072 | used_at = 1; | |
6073 | } | |
6074 | else | |
6075 | { | |
6076 | tempreg = treg; | |
252b5132 RH |
6077 | } |
6078 | goto ld_st; | |
6079 | case M_SB_AB: | |
6080 | s = "sb"; | |
6081 | goto st; | |
6082 | case M_SH_AB: | |
6083 | s = "sh"; | |
6084 | goto st; | |
6085 | case M_SW_AB: | |
6086 | s = "sw"; | |
6087 | goto st; | |
6088 | case M_SWC0_AB: | |
6089 | s = "swc0"; | |
bdaaa2e1 | 6090 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6091 | coproc = 1; |
6092 | goto st; | |
6093 | case M_SWC1_AB: | |
6094 | s = "swc1"; | |
bdaaa2e1 | 6095 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6096 | coproc = 1; |
6097 | goto st; | |
6098 | case M_SWC2_AB: | |
6099 | s = "swc2"; | |
bdaaa2e1 | 6100 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6101 | coproc = 1; |
6102 | goto st; | |
6103 | case M_SWC3_AB: | |
6104 | s = "swc3"; | |
bdaaa2e1 | 6105 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6106 | coproc = 1; |
6107 | goto st; | |
6108 | case M_SWL_AB: | |
6109 | s = "swl"; | |
6110 | goto st; | |
6111 | case M_SWR_AB: | |
6112 | s = "swr"; | |
6113 | goto st; | |
6114 | case M_SC_AB: | |
6115 | s = "sc"; | |
6116 | goto st; | |
6117 | case M_SCD_AB: | |
6118 | s = "scd"; | |
6119 | goto st; | |
d43b4baf TS |
6120 | case M_CACHE_AB: |
6121 | s = "cache"; | |
6122 | goto st; | |
252b5132 | 6123 | case M_SDC1_AB: |
fef14a42 | 6124 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6125 | { |
6126 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6127 | break; |
252b5132 RH |
6128 | } |
6129 | s = "sdc1"; | |
6130 | coproc = 1; | |
bdaaa2e1 | 6131 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6132 | goto st; |
6133 | case M_SDC2_AB: | |
6134 | s = "sdc2"; | |
bdaaa2e1 | 6135 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6136 | coproc = 1; |
6137 | goto st; | |
6138 | case M_SDC3_AB: | |
6139 | s = "sdc3"; | |
bdaaa2e1 | 6140 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6141 | coproc = 1; |
6142 | goto st; | |
6143 | case M_SDL_AB: | |
6144 | s = "sdl"; | |
6145 | goto st; | |
6146 | case M_SDR_AB: | |
6147 | s = "sdr"; | |
6148 | st: | |
8fc2e39e TS |
6149 | tempreg = AT; |
6150 | used_at = 1; | |
252b5132 | 6151 | ld_st: |
bdaaa2e1 | 6152 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6153 | if (mask == M_LWC1_AB |
6154 | || mask == M_SWC1_AB | |
6155 | || mask == M_LDC1_AB | |
6156 | || mask == M_SDC1_AB | |
6157 | || mask == M_L_DAB | |
6158 | || mask == M_S_DAB) | |
6159 | fmt = "T,o(b)"; | |
d43b4baf TS |
6160 | else if (mask == M_CACHE_AB) |
6161 | fmt = "k,o(b)"; | |
252b5132 RH |
6162 | else if (coproc) |
6163 | fmt = "E,o(b)"; | |
6164 | else | |
6165 | fmt = "t,o(b)"; | |
6166 | ||
6167 | if (offset_expr.X_op != O_constant | |
6168 | && offset_expr.X_op != O_symbol) | |
6169 | { | |
6170 | as_bad (_("expression too complex")); | |
6171 | offset_expr.X_op = O_constant; | |
6172 | } | |
6173 | ||
2051e8c4 MR |
6174 | if (HAVE_32BIT_ADDRESSES |
6175 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6176 | { |
6177 | char value [32]; | |
6178 | ||
6179 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6180 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6181 | } |
2051e8c4 | 6182 | |
252b5132 RH |
6183 | /* A constant expression in PIC code can be handled just as it |
6184 | is in non PIC code. */ | |
aed1a261 RS |
6185 | if (offset_expr.X_op == O_constant) |
6186 | { | |
aed1a261 RS |
6187 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6188 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6189 | normalize_address_expr (&expr1); |
aed1a261 RS |
6190 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6191 | if (breg != 0) | |
6192 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6193 | tempreg, tempreg, breg); | |
6194 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6195 | } | |
6196 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6197 | { |
6198 | /* If this is a reference to a GP relative symbol, and there | |
6199 | is no base register, we want | |
cdf6fd85 | 6200 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6201 | Otherwise, if there is no base register, we want |
6202 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6203 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6204 | If we have a constant, we need two instructions anyhow, | |
6205 | so we always use the latter form. | |
6206 | ||
6207 | If we have a base register, and this is a reference to a | |
6208 | GP relative symbol, we want | |
6209 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6210 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6211 | Otherwise we want |
6212 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6213 | addu $tempreg,$tempreg,$breg | |
6214 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6215 | With a constant we always use the latter case. |
76b3015f | 6216 | |
d6bc6245 TS |
6217 | With 64bit address space and no base register and $at usable, |
6218 | we want | |
6219 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6220 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6221 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6222 | dsll32 $tempreg,0 | |
6223 | daddu $tempreg,$at | |
6224 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6225 | If we have a base register, we want | |
6226 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6227 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6228 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6229 | daddu $at,$breg | |
6230 | dsll32 $tempreg,0 | |
6231 | daddu $tempreg,$at | |
6232 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6233 | ||
6234 | Without $at we can't generate the optimal path for superscalar | |
6235 | processors here since this would require two temporary registers. | |
6236 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6237 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6238 | dsll $tempreg,16 | |
6239 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6240 | dsll $tempreg,16 | |
6241 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6242 | If we have a base register, we want | |
6243 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6244 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6245 | dsll $tempreg,16 | |
6246 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6247 | dsll $tempreg,16 | |
6248 | daddu $tempreg,$tempreg,$breg | |
6249 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6250 | |
6caf9ef4 | 6251 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6252 | the same sequence as in 32bit address space. */ |
6253 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6254 | { |
aed1a261 | 6255 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6256 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6257 | { | |
6258 | relax_start (offset_expr.X_add_symbol); | |
6259 | if (breg == 0) | |
6260 | { | |
6261 | macro_build (&offset_expr, s, fmt, treg, | |
6262 | BFD_RELOC_GPREL16, mips_gp_register); | |
6263 | } | |
6264 | else | |
6265 | { | |
6266 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6267 | tempreg, breg, mips_gp_register); | |
6268 | macro_build (&offset_expr, s, fmt, treg, | |
6269 | BFD_RELOC_GPREL16, tempreg); | |
6270 | } | |
6271 | relax_switch (); | |
6272 | } | |
d6bc6245 | 6273 | |
b8285c27 | 6274 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 6275 | { |
67c0d1eb RS |
6276 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6277 | BFD_RELOC_MIPS_HIGHEST); | |
6278 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6279 | BFD_RELOC_HI16_S); | |
6280 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6281 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6282 | if (breg != 0) |
67c0d1eb RS |
6283 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6284 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6285 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6286 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6287 | tempreg); | |
d6bc6245 TS |
6288 | used_at = 1; |
6289 | } | |
6290 | else | |
6291 | { | |
67c0d1eb RS |
6292 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6293 | BFD_RELOC_MIPS_HIGHEST); | |
6294 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6295 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6296 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6297 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6298 | tempreg, BFD_RELOC_HI16_S); | |
6299 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6300 | if (breg != 0) |
67c0d1eb | 6301 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6302 | tempreg, tempreg, breg); |
67c0d1eb | 6303 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6304 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6305 | } |
6caf9ef4 TS |
6306 | |
6307 | if (mips_relax.sequence) | |
6308 | relax_end (); | |
8fc2e39e | 6309 | break; |
d6bc6245 | 6310 | } |
256ab948 | 6311 | |
252b5132 RH |
6312 | if (breg == 0) |
6313 | { | |
67c0d1eb | 6314 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6315 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6316 | { |
4d7206a2 | 6317 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6318 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6319 | mips_gp_register); | |
4d7206a2 | 6320 | relax_switch (); |
252b5132 | 6321 | } |
67c0d1eb RS |
6322 | macro_build_lui (&offset_expr, tempreg); |
6323 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6324 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6325 | if (mips_relax.sequence) |
6326 | relax_end (); | |
252b5132 RH |
6327 | } |
6328 | else | |
6329 | { | |
67c0d1eb | 6330 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6331 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6332 | { |
4d7206a2 | 6333 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6334 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6335 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6336 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6337 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6338 | relax_switch (); |
252b5132 | 6339 | } |
67c0d1eb RS |
6340 | macro_build_lui (&offset_expr, tempreg); |
6341 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6342 | tempreg, tempreg, breg); |
67c0d1eb | 6343 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6344 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6345 | if (mips_relax.sequence) |
6346 | relax_end (); | |
252b5132 RH |
6347 | } |
6348 | } | |
0a44bf69 | 6349 | else if (!mips_big_got) |
252b5132 | 6350 | { |
ed6fb7bd | 6351 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6352 | |
252b5132 RH |
6353 | /* If this is a reference to an external symbol, we want |
6354 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6355 | nop | |
6356 | <op> $treg,0($tempreg) | |
6357 | Otherwise we want | |
6358 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6359 | nop | |
6360 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6361 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6362 | |
6363 | For NewABI, we want | |
6364 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6365 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6366 | ||
252b5132 RH |
6367 | If there is a base register, we add it to $tempreg before |
6368 | the <op>. If there is a constant, we stick it in the | |
6369 | <op> instruction. We don't handle constants larger than | |
6370 | 16 bits, because we have no way to load the upper 16 bits | |
6371 | (actually, we could handle them for the subset of cases | |
6372 | in which we are not using $at). */ | |
6373 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6374 | if (HAVE_NEWABI) |
6375 | { | |
67c0d1eb RS |
6376 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6377 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6378 | if (breg != 0) |
67c0d1eb | 6379 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6380 | tempreg, tempreg, breg); |
67c0d1eb | 6381 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6382 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6383 | break; |
6384 | } | |
252b5132 RH |
6385 | expr1.X_add_number = offset_expr.X_add_number; |
6386 | offset_expr.X_add_number = 0; | |
6387 | if (expr1.X_add_number < -0x8000 | |
6388 | || expr1.X_add_number >= 0x8000) | |
6389 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6390 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6391 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6392 | load_delay_nop (); |
4d7206a2 RS |
6393 | relax_start (offset_expr.X_add_symbol); |
6394 | relax_switch (); | |
67c0d1eb RS |
6395 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6396 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6397 | relax_end (); |
252b5132 | 6398 | if (breg != 0) |
67c0d1eb | 6399 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6400 | tempreg, tempreg, breg); |
67c0d1eb | 6401 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6402 | } |
0a44bf69 | 6403 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6404 | { |
67c0d1eb | 6405 | int gpdelay; |
252b5132 RH |
6406 | |
6407 | /* If this is a reference to an external symbol, we want | |
6408 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6409 | addu $tempreg,$tempreg,$gp | |
6410 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6411 | <op> $treg,0($tempreg) | |
6412 | Otherwise we want | |
6413 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6414 | nop | |
6415 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6416 | <op> $treg,0($tempreg) | |
6417 | If there is a base register, we add it to $tempreg before | |
6418 | the <op>. If there is a constant, we stick it in the | |
6419 | <op> instruction. We don't handle constants larger than | |
6420 | 16 bits, because we have no way to load the upper 16 bits | |
6421 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6422 | in which we are not using $at). */ |
252b5132 RH |
6423 | assert (offset_expr.X_op == O_symbol); |
6424 | expr1.X_add_number = offset_expr.X_add_number; | |
6425 | offset_expr.X_add_number = 0; | |
6426 | if (expr1.X_add_number < -0x8000 | |
6427 | || expr1.X_add_number >= 0x8000) | |
6428 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6429 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6430 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6431 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6432 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6433 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6434 | mips_gp_register); | |
6435 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6436 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6437 | relax_switch (); |
67c0d1eb RS |
6438 | if (gpdelay) |
6439 | macro_build (NULL, "nop", ""); | |
6440 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6441 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6442 | load_delay_nop (); |
67c0d1eb RS |
6443 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6444 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6445 | relax_end (); |
6446 | ||
252b5132 | 6447 | if (breg != 0) |
67c0d1eb | 6448 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6449 | tempreg, tempreg, breg); |
67c0d1eb | 6450 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6451 | } |
0a44bf69 | 6452 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6453 | { |
f5040a92 AO |
6454 | /* If this is a reference to an external symbol, we want |
6455 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6456 | add $tempreg,$tempreg,$gp | |
6457 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6458 | <op> $treg,<ofst>($tempreg) | |
6459 | Otherwise, for local symbols, we want: | |
6460 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6461 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6462 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6463 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6464 | offset_expr.X_add_number = 0; |
6465 | if (expr1.X_add_number < -0x8000 | |
6466 | || expr1.X_add_number >= 0x8000) | |
6467 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6468 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6469 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6470 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6471 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6472 | mips_gp_register); | |
6473 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6474 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6475 | if (breg != 0) |
67c0d1eb | 6476 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6477 | tempreg, tempreg, breg); |
67c0d1eb | 6478 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6479 | |
4d7206a2 | 6480 | relax_switch (); |
f5040a92 | 6481 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6482 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6483 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6484 | if (breg != 0) |
67c0d1eb | 6485 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6486 | tempreg, tempreg, breg); |
67c0d1eb | 6487 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6488 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6489 | relax_end (); |
f5040a92 | 6490 | } |
252b5132 RH |
6491 | else |
6492 | abort (); | |
6493 | ||
252b5132 RH |
6494 | break; |
6495 | ||
6496 | case M_LI: | |
6497 | case M_LI_S: | |
67c0d1eb | 6498 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6499 | break; |
252b5132 RH |
6500 | |
6501 | case M_DLI: | |
67c0d1eb | 6502 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6503 | break; |
252b5132 RH |
6504 | |
6505 | case M_LI_SS: | |
6506 | if (imm_expr.X_op == O_constant) | |
6507 | { | |
8fc2e39e | 6508 | used_at = 1; |
67c0d1eb RS |
6509 | load_register (AT, &imm_expr, 0); |
6510 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6511 | break; |
6512 | } | |
6513 | else | |
6514 | { | |
6515 | assert (offset_expr.X_op == O_symbol | |
6516 | && strcmp (segment_name (S_GET_SEGMENT | |
6517 | (offset_expr.X_add_symbol)), | |
6518 | ".lit4") == 0 | |
6519 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6520 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6521 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6522 | break; |
252b5132 RH |
6523 | } |
6524 | ||
6525 | case M_LI_D: | |
ca4e0257 RS |
6526 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6527 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6528 | order 32 bits of the value and the low order 32 bits are either | |
6529 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6530 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6531 | { | |
ca4e0257 | 6532 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6533 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6534 | else |
6535 | { | |
6536 | int hreg, lreg; | |
6537 | ||
6538 | if (target_big_endian) | |
6539 | { | |
6540 | hreg = treg; | |
6541 | lreg = treg + 1; | |
6542 | } | |
6543 | else | |
6544 | { | |
6545 | hreg = treg + 1; | |
6546 | lreg = treg; | |
6547 | } | |
6548 | ||
6549 | if (hreg <= 31) | |
67c0d1eb | 6550 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6551 | if (lreg <= 31) |
6552 | { | |
6553 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6554 | move_register (lreg, 0); |
252b5132 RH |
6555 | else |
6556 | { | |
6557 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6558 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6559 | } |
6560 | } | |
6561 | } | |
8fc2e39e | 6562 | break; |
252b5132 RH |
6563 | } |
6564 | ||
6565 | /* We know that sym is in the .rdata section. First we get the | |
6566 | upper 16 bits of the address. */ | |
6567 | if (mips_pic == NO_PIC) | |
6568 | { | |
67c0d1eb | 6569 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6570 | used_at = 1; |
252b5132 | 6571 | } |
0a44bf69 | 6572 | else |
252b5132 | 6573 | { |
67c0d1eb RS |
6574 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6575 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6576 | used_at = 1; |
252b5132 | 6577 | } |
bdaaa2e1 | 6578 | |
252b5132 | 6579 | /* Now we load the register(s). */ |
ca4e0257 | 6580 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6581 | { |
6582 | used_at = 1; | |
6583 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6584 | } | |
252b5132 RH |
6585 | else |
6586 | { | |
8fc2e39e | 6587 | used_at = 1; |
67c0d1eb | 6588 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6589 | if (treg != RA) |
252b5132 RH |
6590 | { |
6591 | /* FIXME: How in the world do we deal with the possible | |
6592 | overflow here? */ | |
6593 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6594 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6595 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6596 | } |
6597 | } | |
252b5132 RH |
6598 | break; |
6599 | ||
6600 | case M_LI_DD: | |
ca4e0257 RS |
6601 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6602 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6603 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6604 | the value and the low order 32 bits are either zero or in | |
6605 | OFFSET_EXPR. */ | |
252b5132 RH |
6606 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6607 | { | |
8fc2e39e | 6608 | used_at = 1; |
67c0d1eb | 6609 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6610 | if (HAVE_64BIT_FPRS) |
6611 | { | |
6612 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6613 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6614 | } |
252b5132 RH |
6615 | else |
6616 | { | |
67c0d1eb | 6617 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6618 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6619 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6620 | else |
6621 | { | |
6622 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6623 | load_register (AT, &offset_expr, 0); |
6624 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6625 | } |
6626 | } | |
6627 | break; | |
6628 | } | |
6629 | ||
6630 | assert (offset_expr.X_op == O_symbol | |
6631 | && offset_expr.X_add_number == 0); | |
6632 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6633 | if (strcmp (s, ".lit8") == 0) | |
6634 | { | |
e7af610e | 6635 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6636 | { |
67c0d1eb | 6637 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6638 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6639 | break; |
252b5132 | 6640 | } |
c9914766 | 6641 | breg = mips_gp_register; |
252b5132 RH |
6642 | r = BFD_RELOC_MIPS_LITERAL; |
6643 | goto dob; | |
6644 | } | |
6645 | else | |
6646 | { | |
6647 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6648 | used_at = 1; |
0a44bf69 | 6649 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6650 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6651 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6652 | else |
6653 | { | |
6654 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6655 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6656 | } |
bdaaa2e1 | 6657 | |
e7af610e | 6658 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6659 | { |
67c0d1eb RS |
6660 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6661 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6662 | break; |
6663 | } | |
6664 | breg = AT; | |
6665 | r = BFD_RELOC_LO16; | |
6666 | goto dob; | |
6667 | } | |
6668 | ||
6669 | case M_L_DOB: | |
fef14a42 | 6670 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6671 | { |
6672 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6673 | break; |
252b5132 RH |
6674 | } |
6675 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6676 | to adjust when loading from memory. */ | |
6677 | r = BFD_RELOC_LO16; | |
6678 | dob: | |
e7af610e | 6679 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6680 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6681 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6682 | /* FIXME: A possible overflow which I don't know how to deal |
6683 | with. */ | |
6684 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6685 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6686 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6687 | break; |
6688 | ||
6689 | case M_L_DAB: | |
6690 | /* | |
6691 | * The MIPS assembler seems to check for X_add_number not | |
6692 | * being double aligned and generating: | |
6693 | * lui at,%hi(foo+1) | |
6694 | * addu at,at,v1 | |
6695 | * addiu at,at,%lo(foo+1) | |
6696 | * lwc1 f2,0(at) | |
6697 | * lwc1 f3,4(at) | |
6698 | * But, the resulting address is the same after relocation so why | |
6699 | * generate the extra instruction? | |
6700 | */ | |
fef14a42 | 6701 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6702 | { |
6703 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6704 | break; |
252b5132 | 6705 | } |
bdaaa2e1 | 6706 | /* Itbl support may require additional care here. */ |
252b5132 | 6707 | coproc = 1; |
e7af610e | 6708 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6709 | { |
6710 | s = "ldc1"; | |
6711 | goto ld; | |
6712 | } | |
6713 | ||
6714 | s = "lwc1"; | |
6715 | fmt = "T,o(b)"; | |
6716 | goto ldd_std; | |
6717 | ||
6718 | case M_S_DAB: | |
fef14a42 | 6719 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6720 | { |
6721 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6722 | break; |
252b5132 RH |
6723 | } |
6724 | ||
e7af610e | 6725 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6726 | { |
6727 | s = "sdc1"; | |
6728 | goto st; | |
6729 | } | |
6730 | ||
6731 | s = "swc1"; | |
6732 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6733 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6734 | coproc = 1; |
6735 | goto ldd_std; | |
6736 | ||
6737 | case M_LD_AB: | |
ca4e0257 | 6738 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6739 | { |
6740 | s = "ld"; | |
6741 | goto ld; | |
6742 | } | |
6743 | ||
6744 | s = "lw"; | |
6745 | fmt = "t,o(b)"; | |
6746 | goto ldd_std; | |
6747 | ||
6748 | case M_SD_AB: | |
ca4e0257 | 6749 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6750 | { |
6751 | s = "sd"; | |
6752 | goto st; | |
6753 | } | |
6754 | ||
6755 | s = "sw"; | |
6756 | fmt = "t,o(b)"; | |
6757 | ||
6758 | ldd_std: | |
6759 | if (offset_expr.X_op != O_symbol | |
6760 | && offset_expr.X_op != O_constant) | |
6761 | { | |
6762 | as_bad (_("expression too complex")); | |
6763 | offset_expr.X_op = O_constant; | |
6764 | } | |
6765 | ||
2051e8c4 MR |
6766 | if (HAVE_32BIT_ADDRESSES |
6767 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6768 | { |
6769 | char value [32]; | |
6770 | ||
6771 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6772 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6773 | } |
2051e8c4 | 6774 | |
252b5132 RH |
6775 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6776 | to adjust when loading from memory. We set coproc if we must | |
6777 | load $fn+1 first. */ | |
bdaaa2e1 | 6778 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6779 | if (! target_big_endian) |
6780 | coproc = 0; | |
6781 | ||
6782 | if (mips_pic == NO_PIC | |
6783 | || offset_expr.X_op == O_constant) | |
6784 | { | |
6785 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6786 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6787 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6788 | If we have a base register, we use this |
6789 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6790 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6791 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6792 | If this is not a GP relative symbol, we want |
6793 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6794 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6795 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6796 | If there is a base register, we add it to $at after the | |
6797 | lui instruction. If there is a constant, we always use | |
6798 | the last case. */ | |
39a59cf8 MR |
6799 | if (offset_expr.X_op == O_symbol |
6800 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6801 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6802 | { |
4d7206a2 | 6803 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6804 | if (breg == 0) |
6805 | { | |
c9914766 | 6806 | tempreg = mips_gp_register; |
252b5132 RH |
6807 | } |
6808 | else | |
6809 | { | |
67c0d1eb | 6810 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6811 | AT, breg, mips_gp_register); |
252b5132 | 6812 | tempreg = AT; |
252b5132 RH |
6813 | used_at = 1; |
6814 | } | |
6815 | ||
beae10d5 | 6816 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6817 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6818 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6819 | offset_expr.X_add_number += 4; |
6820 | ||
6821 | /* Set mips_optimize to 2 to avoid inserting an | |
6822 | undesired nop. */ | |
6823 | hold_mips_optimize = mips_optimize; | |
6824 | mips_optimize = 2; | |
beae10d5 | 6825 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6826 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6827 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6828 | mips_optimize = hold_mips_optimize; |
6829 | ||
4d7206a2 | 6830 | relax_switch (); |
252b5132 RH |
6831 | |
6832 | /* We just generated two relocs. When tc_gen_reloc | |
6833 | handles this case, it will skip the first reloc and | |
6834 | handle the second. The second reloc already has an | |
6835 | extra addend of 4, which we added above. We must | |
6836 | subtract it out, and then subtract another 4 to make | |
6837 | the first reloc come out right. The second reloc | |
6838 | will come out right because we are going to add 4 to | |
6839 | offset_expr when we build its instruction below. | |
6840 | ||
6841 | If we have a symbol, then we don't want to include | |
6842 | the offset, because it will wind up being included | |
6843 | when we generate the reloc. */ | |
6844 | ||
6845 | if (offset_expr.X_op == O_constant) | |
6846 | offset_expr.X_add_number -= 8; | |
6847 | else | |
6848 | { | |
6849 | offset_expr.X_add_number = -4; | |
6850 | offset_expr.X_op = O_constant; | |
6851 | } | |
6852 | } | |
8fc2e39e | 6853 | used_at = 1; |
67c0d1eb | 6854 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6855 | if (breg != 0) |
67c0d1eb | 6856 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6857 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6858 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6859 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6860 | /* FIXME: How do we handle overflow here? */ |
6861 | offset_expr.X_add_number += 4; | |
beae10d5 | 6862 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6863 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6864 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6865 | if (mips_relax.sequence) |
6866 | relax_end (); | |
bdaaa2e1 | 6867 | } |
0a44bf69 | 6868 | else if (!mips_big_got) |
252b5132 | 6869 | { |
252b5132 RH |
6870 | /* If this is a reference to an external symbol, we want |
6871 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6872 | nop | |
6873 | <op> $treg,0($at) | |
6874 | <op> $treg+1,4($at) | |
6875 | Otherwise we want | |
6876 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6877 | nop | |
6878 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6879 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6880 | If there is a base register we add it to $at before the | |
6881 | lwc1 instructions. If there is a constant we include it | |
6882 | in the lwc1 instructions. */ | |
6883 | used_at = 1; | |
6884 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6885 | if (expr1.X_add_number < -0x8000 |
6886 | || expr1.X_add_number >= 0x8000 - 4) | |
6887 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6888 | load_got_offset (AT, &offset_expr); |
269137b2 | 6889 | load_delay_nop (); |
252b5132 | 6890 | if (breg != 0) |
67c0d1eb | 6891 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6892 | |
6893 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6894 | nop. */ | |
6895 | hold_mips_optimize = mips_optimize; | |
6896 | mips_optimize = 2; | |
4d7206a2 | 6897 | |
beae10d5 | 6898 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6899 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6900 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6901 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6902 | expr1.X_add_number += 4; |
67c0d1eb RS |
6903 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6904 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6905 | relax_switch (); |
67c0d1eb RS |
6906 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6907 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6908 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6909 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6910 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6911 | relax_end (); |
252b5132 | 6912 | |
4d7206a2 | 6913 | mips_optimize = hold_mips_optimize; |
252b5132 | 6914 | } |
0a44bf69 | 6915 | else if (mips_big_got) |
252b5132 | 6916 | { |
67c0d1eb | 6917 | int gpdelay; |
252b5132 RH |
6918 | |
6919 | /* If this is a reference to an external symbol, we want | |
6920 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6921 | addu $at,$at,$gp | |
6922 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6923 | nop | |
6924 | <op> $treg,0($at) | |
6925 | <op> $treg+1,4($at) | |
6926 | Otherwise we want | |
6927 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6928 | nop | |
6929 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6930 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6931 | If there is a base register we add it to $at before the | |
6932 | lwc1 instructions. If there is a constant we include it | |
6933 | in the lwc1 instructions. */ | |
6934 | used_at = 1; | |
6935 | expr1.X_add_number = offset_expr.X_add_number; | |
6936 | offset_expr.X_add_number = 0; | |
6937 | if (expr1.X_add_number < -0x8000 | |
6938 | || expr1.X_add_number >= 0x8000 - 4) | |
6939 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6940 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6941 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6942 | macro_build (&offset_expr, "lui", "t,u", |
6943 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6944 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6945 | AT, AT, mips_gp_register); |
67c0d1eb | 6946 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6947 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6948 | load_delay_nop (); |
252b5132 | 6949 | if (breg != 0) |
67c0d1eb | 6950 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6951 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6952 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6953 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6954 | expr1.X_add_number += 4; |
6955 | ||
6956 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6957 | nop. */ | |
6958 | hold_mips_optimize = mips_optimize; | |
6959 | mips_optimize = 2; | |
beae10d5 | 6960 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6961 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6962 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6963 | mips_optimize = hold_mips_optimize; |
6964 | expr1.X_add_number -= 4; | |
6965 | ||
4d7206a2 RS |
6966 | relax_switch (); |
6967 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6968 | if (gpdelay) |
6969 | macro_build (NULL, "nop", ""); | |
6970 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6971 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6972 | load_delay_nop (); |
252b5132 | 6973 | if (breg != 0) |
67c0d1eb | 6974 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6975 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6976 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6977 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6978 | offset_expr.X_add_number += 4; |
252b5132 RH |
6979 | |
6980 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6981 | nop. */ | |
6982 | hold_mips_optimize = mips_optimize; | |
6983 | mips_optimize = 2; | |
beae10d5 | 6984 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6985 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6986 | BFD_RELOC_LO16, AT); | |
252b5132 | 6987 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6988 | relax_end (); |
252b5132 | 6989 | } |
252b5132 RH |
6990 | else |
6991 | abort (); | |
6992 | ||
252b5132 RH |
6993 | break; |
6994 | ||
6995 | case M_LD_OB: | |
6996 | s = "lw"; | |
6997 | goto sd_ob; | |
6998 | case M_SD_OB: | |
6999 | s = "sw"; | |
7000 | sd_ob: | |
ca4e0257 | 7001 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7002 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7003 | offset_expr.X_add_number += 4; |
67c0d1eb | 7004 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7005 | break; |
252b5132 RH |
7006 | |
7007 | /* New code added to support COPZ instructions. | |
7008 | This code builds table entries out of the macros in mip_opcodes. | |
7009 | R4000 uses interlocks to handle coproc delays. | |
7010 | Other chips (like the R3000) require nops to be inserted for delays. | |
7011 | ||
f72c8c98 | 7012 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7013 | In order to fill delay slots for non-interlocked chips, |
7014 | we must have a way to specify delays based on the coprocessor. | |
7015 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7016 | What are the side-effects of the cop instruction? | |
7017 | What cache support might we have and what are its effects? | |
7018 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7019 | What registers are read/set/modified? |
252b5132 RH |
7020 | |
7021 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7022 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7023 | |
7024 | case M_COP0: | |
7025 | s = "c0"; | |
7026 | goto copz; | |
7027 | case M_COP1: | |
7028 | s = "c1"; | |
7029 | goto copz; | |
7030 | case M_COP2: | |
7031 | s = "c2"; | |
7032 | goto copz; | |
7033 | case M_COP3: | |
7034 | s = "c3"; | |
7035 | copz: | |
7036 | /* For now we just do C (same as Cz). The parameter will be | |
7037 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7038 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7039 | break; |
252b5132 | 7040 | |
ea1fb5dc | 7041 | case M_MOVE: |
67c0d1eb | 7042 | move_register (dreg, sreg); |
8fc2e39e | 7043 | break; |
ea1fb5dc | 7044 | |
252b5132 RH |
7045 | #ifdef LOSING_COMPILER |
7046 | default: | |
7047 | /* Try and see if this is a new itbl instruction. | |
7048 | This code builds table entries out of the macros in mip_opcodes. | |
7049 | FIXME: For now we just assemble the expression and pass it's | |
7050 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7051 | We may want to have the assembler assemble this value, |
252b5132 RH |
7052 | so that we gain the assembler's knowledge of delay slots, |
7053 | symbols, etc. | |
7054 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7055 | if (itbl_have_entries |
252b5132 | 7056 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7057 | { |
252b5132 RH |
7058 | s = ip->insn_mo->name; |
7059 | s2 = "cop3"; | |
7060 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7061 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7062 | break; |
beae10d5 | 7063 | } |
252b5132 | 7064 | macro2 (ip); |
8fc2e39e | 7065 | break; |
252b5132 | 7066 | } |
8fc2e39e TS |
7067 | if (mips_opts.noat && used_at) |
7068 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 7069 | } |
bdaaa2e1 | 7070 | |
252b5132 | 7071 | static void |
17a2f251 | 7072 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7073 | { |
3994f87e | 7074 | int treg, sreg, dreg, breg; |
252b5132 RH |
7075 | int tempreg; |
7076 | int mask; | |
252b5132 RH |
7077 | int used_at; |
7078 | expressionS expr1; | |
7079 | const char *s; | |
7080 | const char *s2; | |
7081 | const char *fmt; | |
7082 | int likely = 0; | |
7083 | int dbl = 0; | |
7084 | int coproc = 0; | |
7085 | int lr = 0; | |
7086 | int imm = 0; | |
7087 | int off; | |
7088 | offsetT maxnum; | |
7089 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7090 | |
252b5132 RH |
7091 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7092 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7093 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7094 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7095 | |
252b5132 RH |
7096 | expr1.X_op = O_constant; |
7097 | expr1.X_op_symbol = NULL; | |
7098 | expr1.X_add_symbol = NULL; | |
7099 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7100 | |
252b5132 RH |
7101 | switch (mask) |
7102 | { | |
7103 | #endif /* LOSING_COMPILER */ | |
7104 | ||
7105 | case M_DMUL: | |
7106 | dbl = 1; | |
7107 | case M_MUL: | |
67c0d1eb RS |
7108 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7109 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7110 | break; |
252b5132 RH |
7111 | |
7112 | case M_DMUL_I: | |
7113 | dbl = 1; | |
7114 | case M_MUL_I: | |
7115 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7116 | not trying to be that fancy. GCC should do this for us | |
7117 | anyway. */ | |
8fc2e39e | 7118 | used_at = 1; |
67c0d1eb RS |
7119 | load_register (AT, &imm_expr, dbl); |
7120 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7121 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7122 | break; |
7123 | ||
7124 | case M_DMULO_I: | |
7125 | dbl = 1; | |
7126 | case M_MULO_I: | |
7127 | imm = 1; | |
7128 | goto do_mulo; | |
7129 | ||
7130 | case M_DMULO: | |
7131 | dbl = 1; | |
7132 | case M_MULO: | |
7133 | do_mulo: | |
7d10b47d | 7134 | start_noreorder (); |
8fc2e39e | 7135 | used_at = 1; |
252b5132 | 7136 | if (imm) |
67c0d1eb RS |
7137 | load_register (AT, &imm_expr, dbl); |
7138 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7139 | macro_build (NULL, "mflo", "d", dreg); | |
7140 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7141 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7142 | if (mips_trap) |
67c0d1eb | 7143 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7144 | else |
7145 | { | |
7146 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7147 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7148 | macro_build (NULL, "nop", "", 0); | |
7149 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7150 | } |
7d10b47d | 7151 | end_noreorder (); |
67c0d1eb | 7152 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7153 | break; |
7154 | ||
7155 | case M_DMULOU_I: | |
7156 | dbl = 1; | |
7157 | case M_MULOU_I: | |
7158 | imm = 1; | |
7159 | goto do_mulou; | |
7160 | ||
7161 | case M_DMULOU: | |
7162 | dbl = 1; | |
7163 | case M_MULOU: | |
7164 | do_mulou: | |
7d10b47d | 7165 | start_noreorder (); |
8fc2e39e | 7166 | used_at = 1; |
252b5132 | 7167 | if (imm) |
67c0d1eb RS |
7168 | load_register (AT, &imm_expr, dbl); |
7169 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7170 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7171 | macro_build (NULL, "mfhi", "d", AT); |
7172 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7173 | if (mips_trap) |
67c0d1eb | 7174 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7175 | else |
7176 | { | |
7177 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7178 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7179 | macro_build (NULL, "nop", "", 0); | |
7180 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7181 | } |
7d10b47d | 7182 | end_noreorder (); |
252b5132 RH |
7183 | break; |
7184 | ||
771c7ce4 | 7185 | case M_DROL: |
fef14a42 | 7186 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7187 | { |
7188 | if (dreg == sreg) | |
7189 | { | |
7190 | tempreg = AT; | |
7191 | used_at = 1; | |
7192 | } | |
7193 | else | |
7194 | { | |
7195 | tempreg = dreg; | |
82dd0097 | 7196 | } |
67c0d1eb RS |
7197 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7198 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7199 | break; |
82dd0097 | 7200 | } |
8fc2e39e | 7201 | used_at = 1; |
67c0d1eb RS |
7202 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7203 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7204 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7205 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7206 | break; |
7207 | ||
252b5132 | 7208 | case M_ROL: |
fef14a42 | 7209 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7210 | { |
7211 | if (dreg == sreg) | |
7212 | { | |
7213 | tempreg = AT; | |
7214 | used_at = 1; | |
7215 | } | |
7216 | else | |
7217 | { | |
7218 | tempreg = dreg; | |
82dd0097 | 7219 | } |
67c0d1eb RS |
7220 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7221 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7222 | break; |
82dd0097 | 7223 | } |
8fc2e39e | 7224 | used_at = 1; |
67c0d1eb RS |
7225 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7226 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7227 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7228 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7229 | break; |
7230 | ||
771c7ce4 TS |
7231 | case M_DROL_I: |
7232 | { | |
7233 | unsigned int rot; | |
82dd0097 | 7234 | char *l, *r; |
771c7ce4 TS |
7235 | |
7236 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7237 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7238 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7239 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7240 | { |
7241 | rot = (64 - rot) & 0x3f; | |
7242 | if (rot >= 32) | |
67c0d1eb | 7243 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7244 | else |
67c0d1eb | 7245 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7246 | break; |
60b63b72 | 7247 | } |
483fc7cd | 7248 | if (rot == 0) |
483fc7cd | 7249 | { |
67c0d1eb | 7250 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7251 | break; |
483fc7cd | 7252 | } |
82dd0097 CD |
7253 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7254 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7255 | rot &= 0x1f; | |
8fc2e39e | 7256 | used_at = 1; |
67c0d1eb RS |
7257 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7258 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7259 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7260 | } |
7261 | break; | |
7262 | ||
252b5132 | 7263 | case M_ROL_I: |
771c7ce4 TS |
7264 | { |
7265 | unsigned int rot; | |
7266 | ||
7267 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7268 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7269 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7270 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7271 | { |
67c0d1eb | 7272 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7273 | break; |
60b63b72 | 7274 | } |
483fc7cd | 7275 | if (rot == 0) |
483fc7cd | 7276 | { |
67c0d1eb | 7277 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7278 | break; |
483fc7cd | 7279 | } |
8fc2e39e | 7280 | used_at = 1; |
67c0d1eb RS |
7281 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7282 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7283 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7284 | } |
7285 | break; | |
7286 | ||
7287 | case M_DROR: | |
fef14a42 | 7288 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7289 | { |
67c0d1eb | 7290 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7291 | break; |
82dd0097 | 7292 | } |
8fc2e39e | 7293 | used_at = 1; |
67c0d1eb RS |
7294 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7295 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7296 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7297 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7298 | break; |
7299 | ||
7300 | case M_ROR: | |
fef14a42 | 7301 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7302 | { |
67c0d1eb | 7303 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7304 | break; |
82dd0097 | 7305 | } |
8fc2e39e | 7306 | used_at = 1; |
67c0d1eb RS |
7307 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7308 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7309 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7310 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7311 | break; |
7312 | ||
771c7ce4 TS |
7313 | case M_DROR_I: |
7314 | { | |
7315 | unsigned int rot; | |
82dd0097 | 7316 | char *l, *r; |
771c7ce4 TS |
7317 | |
7318 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7319 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7320 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7321 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7322 | { |
7323 | if (rot >= 32) | |
67c0d1eb | 7324 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7325 | else |
67c0d1eb | 7326 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7327 | break; |
82dd0097 | 7328 | } |
483fc7cd | 7329 | if (rot == 0) |
483fc7cd | 7330 | { |
67c0d1eb | 7331 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7332 | break; |
483fc7cd | 7333 | } |
82dd0097 CD |
7334 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7335 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7336 | rot &= 0x1f; | |
8fc2e39e | 7337 | used_at = 1; |
67c0d1eb RS |
7338 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7339 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7340 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7341 | } |
7342 | break; | |
7343 | ||
252b5132 | 7344 | case M_ROR_I: |
771c7ce4 TS |
7345 | { |
7346 | unsigned int rot; | |
7347 | ||
7348 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7349 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7350 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7351 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7352 | { |
67c0d1eb | 7353 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7354 | break; |
82dd0097 | 7355 | } |
483fc7cd | 7356 | if (rot == 0) |
483fc7cd | 7357 | { |
67c0d1eb | 7358 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7359 | break; |
483fc7cd | 7360 | } |
8fc2e39e | 7361 | used_at = 1; |
67c0d1eb RS |
7362 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7363 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7364 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7365 | } |
252b5132 RH |
7366 | break; |
7367 | ||
7368 | case M_S_DOB: | |
fef14a42 | 7369 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7370 | { |
7371 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7372 | break; |
252b5132 | 7373 | } |
e7af610e | 7374 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7375 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7376 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7377 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7378 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7379 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7380 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7381 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7382 | break; |
252b5132 RH |
7383 | |
7384 | case M_SEQ: | |
7385 | if (sreg == 0) | |
67c0d1eb | 7386 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7387 | else if (treg == 0) |
67c0d1eb | 7388 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7389 | else |
7390 | { | |
67c0d1eb RS |
7391 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7392 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7393 | } |
8fc2e39e | 7394 | break; |
252b5132 RH |
7395 | |
7396 | case M_SEQ_I: | |
7397 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7398 | { | |
67c0d1eb | 7399 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7400 | break; |
252b5132 RH |
7401 | } |
7402 | if (sreg == 0) | |
7403 | { | |
7404 | as_warn (_("Instruction %s: result is always false"), | |
7405 | ip->insn_mo->name); | |
67c0d1eb | 7406 | move_register (dreg, 0); |
8fc2e39e | 7407 | break; |
252b5132 RH |
7408 | } |
7409 | if (imm_expr.X_op == O_constant | |
7410 | && imm_expr.X_add_number >= 0 | |
7411 | && imm_expr.X_add_number < 0x10000) | |
7412 | { | |
67c0d1eb | 7413 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7414 | } |
7415 | else if (imm_expr.X_op == O_constant | |
7416 | && imm_expr.X_add_number > -0x8000 | |
7417 | && imm_expr.X_add_number < 0) | |
7418 | { | |
7419 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7420 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7421 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7422 | } |
7423 | else | |
7424 | { | |
67c0d1eb RS |
7425 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7426 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7427 | used_at = 1; |
7428 | } | |
67c0d1eb | 7429 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7430 | break; |
252b5132 RH |
7431 | |
7432 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7433 | s = "slt"; | |
7434 | goto sge; | |
7435 | case M_SGEU: | |
7436 | s = "sltu"; | |
7437 | sge: | |
67c0d1eb RS |
7438 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7439 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7440 | break; |
252b5132 RH |
7441 | |
7442 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7443 | case M_SGEU_I: | |
7444 | if (imm_expr.X_op == O_constant | |
7445 | && imm_expr.X_add_number >= -0x8000 | |
7446 | && imm_expr.X_add_number < 0x8000) | |
7447 | { | |
67c0d1eb RS |
7448 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7449 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7450 | } |
7451 | else | |
7452 | { | |
67c0d1eb RS |
7453 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7454 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7455 | dreg, sreg, AT); | |
252b5132 RH |
7456 | used_at = 1; |
7457 | } | |
67c0d1eb | 7458 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7459 | break; |
252b5132 RH |
7460 | |
7461 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7462 | s = "slt"; | |
7463 | goto sgt; | |
7464 | case M_SGTU: | |
7465 | s = "sltu"; | |
7466 | sgt: | |
67c0d1eb | 7467 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7468 | break; |
252b5132 RH |
7469 | |
7470 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7471 | s = "slt"; | |
7472 | goto sgti; | |
7473 | case M_SGTU_I: | |
7474 | s = "sltu"; | |
7475 | sgti: | |
8fc2e39e | 7476 | used_at = 1; |
67c0d1eb RS |
7477 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7478 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7479 | break; |
7480 | ||
2396cfb9 | 7481 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7482 | s = "slt"; |
7483 | goto sle; | |
7484 | case M_SLEU: | |
7485 | s = "sltu"; | |
7486 | sle: | |
67c0d1eb RS |
7487 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7488 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7489 | break; |
252b5132 | 7490 | |
2396cfb9 | 7491 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7492 | s = "slt"; |
7493 | goto slei; | |
7494 | case M_SLEU_I: | |
7495 | s = "sltu"; | |
7496 | slei: | |
8fc2e39e | 7497 | used_at = 1; |
67c0d1eb RS |
7498 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7499 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7500 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7501 | break; |
7502 | ||
7503 | case M_SLT_I: | |
7504 | if (imm_expr.X_op == O_constant | |
7505 | && imm_expr.X_add_number >= -0x8000 | |
7506 | && imm_expr.X_add_number < 0x8000) | |
7507 | { | |
67c0d1eb | 7508 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7509 | break; |
252b5132 | 7510 | } |
8fc2e39e | 7511 | used_at = 1; |
67c0d1eb RS |
7512 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7513 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7514 | break; |
7515 | ||
7516 | case M_SLTU_I: | |
7517 | if (imm_expr.X_op == O_constant | |
7518 | && imm_expr.X_add_number >= -0x8000 | |
7519 | && imm_expr.X_add_number < 0x8000) | |
7520 | { | |
67c0d1eb | 7521 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7522 | BFD_RELOC_LO16); |
8fc2e39e | 7523 | break; |
252b5132 | 7524 | } |
8fc2e39e | 7525 | used_at = 1; |
67c0d1eb RS |
7526 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7527 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7528 | break; |
7529 | ||
7530 | case M_SNE: | |
7531 | if (sreg == 0) | |
67c0d1eb | 7532 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7533 | else if (treg == 0) |
67c0d1eb | 7534 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7535 | else |
7536 | { | |
67c0d1eb RS |
7537 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7538 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7539 | } |
8fc2e39e | 7540 | break; |
252b5132 RH |
7541 | |
7542 | case M_SNE_I: | |
7543 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7544 | { | |
67c0d1eb | 7545 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7546 | break; |
252b5132 RH |
7547 | } |
7548 | if (sreg == 0) | |
7549 | { | |
7550 | as_warn (_("Instruction %s: result is always true"), | |
7551 | ip->insn_mo->name); | |
67c0d1eb RS |
7552 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7553 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7554 | break; |
252b5132 RH |
7555 | } |
7556 | if (imm_expr.X_op == O_constant | |
7557 | && imm_expr.X_add_number >= 0 | |
7558 | && imm_expr.X_add_number < 0x10000) | |
7559 | { | |
67c0d1eb | 7560 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7561 | } |
7562 | else if (imm_expr.X_op == O_constant | |
7563 | && imm_expr.X_add_number > -0x8000 | |
7564 | && imm_expr.X_add_number < 0) | |
7565 | { | |
7566 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7567 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7568 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7569 | } |
7570 | else | |
7571 | { | |
67c0d1eb RS |
7572 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7573 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7574 | used_at = 1; |
7575 | } | |
67c0d1eb | 7576 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7577 | break; |
252b5132 RH |
7578 | |
7579 | case M_DSUB_I: | |
7580 | dbl = 1; | |
7581 | case M_SUB_I: | |
7582 | if (imm_expr.X_op == O_constant | |
7583 | && imm_expr.X_add_number > -0x8000 | |
7584 | && imm_expr.X_add_number <= 0x8000) | |
7585 | { | |
7586 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7587 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7588 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7589 | break; |
252b5132 | 7590 | } |
8fc2e39e | 7591 | used_at = 1; |
67c0d1eb RS |
7592 | load_register (AT, &imm_expr, dbl); |
7593 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7594 | break; |
7595 | ||
7596 | case M_DSUBU_I: | |
7597 | dbl = 1; | |
7598 | case M_SUBU_I: | |
7599 | if (imm_expr.X_op == O_constant | |
7600 | && imm_expr.X_add_number > -0x8000 | |
7601 | && imm_expr.X_add_number <= 0x8000) | |
7602 | { | |
7603 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7604 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7605 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7606 | break; |
252b5132 | 7607 | } |
8fc2e39e | 7608 | used_at = 1; |
67c0d1eb RS |
7609 | load_register (AT, &imm_expr, dbl); |
7610 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7611 | break; |
7612 | ||
7613 | case M_TEQ_I: | |
7614 | s = "teq"; | |
7615 | goto trap; | |
7616 | case M_TGE_I: | |
7617 | s = "tge"; | |
7618 | goto trap; | |
7619 | case M_TGEU_I: | |
7620 | s = "tgeu"; | |
7621 | goto trap; | |
7622 | case M_TLT_I: | |
7623 | s = "tlt"; | |
7624 | goto trap; | |
7625 | case M_TLTU_I: | |
7626 | s = "tltu"; | |
7627 | goto trap; | |
7628 | case M_TNE_I: | |
7629 | s = "tne"; | |
7630 | trap: | |
8fc2e39e | 7631 | used_at = 1; |
67c0d1eb RS |
7632 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7633 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7634 | break; |
7635 | ||
252b5132 | 7636 | case M_TRUNCWS: |
43841e91 | 7637 | case M_TRUNCWD: |
e7af610e | 7638 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7639 | used_at = 1; |
252b5132 RH |
7640 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7641 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7642 | ||
7643 | /* | |
7644 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7645 | * or is there a reason for it? | |
7646 | */ | |
7d10b47d | 7647 | start_noreorder (); |
67c0d1eb RS |
7648 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7649 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7650 | macro_build (NULL, "nop", ""); | |
252b5132 | 7651 | expr1.X_add_number = 3; |
67c0d1eb | 7652 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7653 | expr1.X_add_number = 2; |
67c0d1eb RS |
7654 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7655 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7656 | macro_build (NULL, "nop", ""); | |
7657 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7658 | dreg, sreg); | |
7659 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7660 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7661 | end_noreorder (); |
252b5132 RH |
7662 | break; |
7663 | ||
7664 | case M_ULH: | |
7665 | s = "lb"; | |
7666 | goto ulh; | |
7667 | case M_ULHU: | |
7668 | s = "lbu"; | |
7669 | ulh: | |
8fc2e39e | 7670 | used_at = 1; |
252b5132 RH |
7671 | if (offset_expr.X_add_number >= 0x7fff) |
7672 | as_bad (_("operand overflow")); | |
252b5132 | 7673 | if (! target_big_endian) |
f9419b05 | 7674 | ++offset_expr.X_add_number; |
67c0d1eb | 7675 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7676 | if (! target_big_endian) |
f9419b05 | 7677 | --offset_expr.X_add_number; |
252b5132 | 7678 | else |
f9419b05 | 7679 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7680 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7681 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7682 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7683 | break; |
7684 | ||
7685 | case M_ULD: | |
7686 | s = "ldl"; | |
7687 | s2 = "ldr"; | |
7688 | off = 7; | |
7689 | goto ulw; | |
7690 | case M_ULW: | |
7691 | s = "lwl"; | |
7692 | s2 = "lwr"; | |
7693 | off = 3; | |
7694 | ulw: | |
7695 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7696 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7697 | if (treg != breg) |
7698 | tempreg = treg; | |
7699 | else | |
8fc2e39e TS |
7700 | { |
7701 | used_at = 1; | |
7702 | tempreg = AT; | |
7703 | } | |
252b5132 RH |
7704 | if (! target_big_endian) |
7705 | offset_expr.X_add_number += off; | |
67c0d1eb | 7706 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7707 | if (! target_big_endian) |
7708 | offset_expr.X_add_number -= off; | |
7709 | else | |
7710 | offset_expr.X_add_number += off; | |
67c0d1eb | 7711 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7712 | |
7713 | /* If necessary, move the result in tempreg the final destination. */ | |
7714 | if (treg == tempreg) | |
8fc2e39e | 7715 | break; |
af22f5b2 | 7716 | /* Protect second load's delay slot. */ |
017315e4 | 7717 | load_delay_nop (); |
67c0d1eb | 7718 | move_register (treg, tempreg); |
af22f5b2 | 7719 | break; |
252b5132 RH |
7720 | |
7721 | case M_ULD_A: | |
7722 | s = "ldl"; | |
7723 | s2 = "ldr"; | |
7724 | off = 7; | |
7725 | goto ulwa; | |
7726 | case M_ULW_A: | |
7727 | s = "lwl"; | |
7728 | s2 = "lwr"; | |
7729 | off = 3; | |
7730 | ulwa: | |
d6bc6245 | 7731 | used_at = 1; |
67c0d1eb | 7732 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7733 | if (breg != 0) |
67c0d1eb | 7734 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7735 | if (! target_big_endian) |
7736 | expr1.X_add_number = off; | |
7737 | else | |
7738 | expr1.X_add_number = 0; | |
67c0d1eb | 7739 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7740 | if (! target_big_endian) |
7741 | expr1.X_add_number = 0; | |
7742 | else | |
7743 | expr1.X_add_number = off; | |
67c0d1eb | 7744 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7745 | break; |
7746 | ||
7747 | case M_ULH_A: | |
7748 | case M_ULHU_A: | |
d6bc6245 | 7749 | used_at = 1; |
67c0d1eb | 7750 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7751 | if (breg != 0) |
67c0d1eb | 7752 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7753 | if (target_big_endian) |
7754 | expr1.X_add_number = 0; | |
67c0d1eb | 7755 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7756 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7757 | if (target_big_endian) |
7758 | expr1.X_add_number = 1; | |
7759 | else | |
7760 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7761 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7762 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7763 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7764 | break; |
7765 | ||
7766 | case M_USH: | |
8fc2e39e | 7767 | used_at = 1; |
252b5132 RH |
7768 | if (offset_expr.X_add_number >= 0x7fff) |
7769 | as_bad (_("operand overflow")); | |
7770 | if (target_big_endian) | |
f9419b05 | 7771 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7772 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7773 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7774 | if (target_big_endian) |
f9419b05 | 7775 | --offset_expr.X_add_number; |
252b5132 | 7776 | else |
f9419b05 | 7777 | ++offset_expr.X_add_number; |
67c0d1eb | 7778 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7779 | break; |
7780 | ||
7781 | case M_USD: | |
7782 | s = "sdl"; | |
7783 | s2 = "sdr"; | |
7784 | off = 7; | |
7785 | goto usw; | |
7786 | case M_USW: | |
7787 | s = "swl"; | |
7788 | s2 = "swr"; | |
7789 | off = 3; | |
7790 | usw: | |
7791 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7792 | as_bad (_("operand overflow")); | |
7793 | if (! target_big_endian) | |
7794 | offset_expr.X_add_number += off; | |
67c0d1eb | 7795 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7796 | if (! target_big_endian) |
7797 | offset_expr.X_add_number -= off; | |
7798 | else | |
7799 | offset_expr.X_add_number += off; | |
67c0d1eb | 7800 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7801 | break; |
252b5132 RH |
7802 | |
7803 | case M_USD_A: | |
7804 | s = "sdl"; | |
7805 | s2 = "sdr"; | |
7806 | off = 7; | |
7807 | goto uswa; | |
7808 | case M_USW_A: | |
7809 | s = "swl"; | |
7810 | s2 = "swr"; | |
7811 | off = 3; | |
7812 | uswa: | |
d6bc6245 | 7813 | used_at = 1; |
67c0d1eb | 7814 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7815 | if (breg != 0) |
67c0d1eb | 7816 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7817 | if (! target_big_endian) |
7818 | expr1.X_add_number = off; | |
7819 | else | |
7820 | expr1.X_add_number = 0; | |
67c0d1eb | 7821 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7822 | if (! target_big_endian) |
7823 | expr1.X_add_number = 0; | |
7824 | else | |
7825 | expr1.X_add_number = off; | |
67c0d1eb | 7826 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7827 | break; |
7828 | ||
7829 | case M_USH_A: | |
d6bc6245 | 7830 | used_at = 1; |
67c0d1eb | 7831 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7832 | if (breg != 0) |
67c0d1eb | 7833 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7834 | if (! target_big_endian) |
7835 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7836 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7837 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7838 | if (! target_big_endian) |
7839 | expr1.X_add_number = 1; | |
7840 | else | |
7841 | expr1.X_add_number = 0; | |
67c0d1eb | 7842 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7843 | if (! target_big_endian) |
7844 | expr1.X_add_number = 0; | |
7845 | else | |
7846 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7847 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7848 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7849 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7850 | break; |
7851 | ||
7852 | default: | |
7853 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7854 | are added dynamically. */ |
252b5132 RH |
7855 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7856 | break; | |
7857 | } | |
8fc2e39e TS |
7858 | if (mips_opts.noat && used_at) |
7859 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7860 | } |
7861 | ||
7862 | /* Implement macros in mips16 mode. */ | |
7863 | ||
7864 | static void | |
17a2f251 | 7865 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7866 | { |
7867 | int mask; | |
7868 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7869 | expressionS expr1; |
7870 | int dbl; | |
7871 | const char *s, *s2, *s3; | |
7872 | ||
7873 | mask = ip->insn_mo->mask; | |
7874 | ||
bf12938e RS |
7875 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7876 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7877 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7878 | |
252b5132 RH |
7879 | expr1.X_op = O_constant; |
7880 | expr1.X_op_symbol = NULL; | |
7881 | expr1.X_add_symbol = NULL; | |
7882 | expr1.X_add_number = 1; | |
7883 | ||
7884 | dbl = 0; | |
7885 | ||
7886 | switch (mask) | |
7887 | { | |
7888 | default: | |
7889 | internalError (); | |
7890 | ||
7891 | case M_DDIV_3: | |
7892 | dbl = 1; | |
7893 | case M_DIV_3: | |
7894 | s = "mflo"; | |
7895 | goto do_div3; | |
7896 | case M_DREM_3: | |
7897 | dbl = 1; | |
7898 | case M_REM_3: | |
7899 | s = "mfhi"; | |
7900 | do_div3: | |
7d10b47d | 7901 | start_noreorder (); |
67c0d1eb | 7902 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7903 | expr1.X_add_number = 2; |
67c0d1eb RS |
7904 | macro_build (&expr1, "bnez", "x,p", yreg); |
7905 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7906 | |
252b5132 RH |
7907 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7908 | since that causes an overflow. We should do that as well, | |
7909 | but I don't see how to do the comparisons without a temporary | |
7910 | register. */ | |
7d10b47d | 7911 | end_noreorder (); |
67c0d1eb | 7912 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7913 | break; |
7914 | ||
7915 | case M_DIVU_3: | |
7916 | s = "divu"; | |
7917 | s2 = "mflo"; | |
7918 | goto do_divu3; | |
7919 | case M_REMU_3: | |
7920 | s = "divu"; | |
7921 | s2 = "mfhi"; | |
7922 | goto do_divu3; | |
7923 | case M_DDIVU_3: | |
7924 | s = "ddivu"; | |
7925 | s2 = "mflo"; | |
7926 | goto do_divu3; | |
7927 | case M_DREMU_3: | |
7928 | s = "ddivu"; | |
7929 | s2 = "mfhi"; | |
7930 | do_divu3: | |
7d10b47d | 7931 | start_noreorder (); |
67c0d1eb | 7932 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7933 | expr1.X_add_number = 2; |
67c0d1eb RS |
7934 | macro_build (&expr1, "bnez", "x,p", yreg); |
7935 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 7936 | end_noreorder (); |
67c0d1eb | 7937 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7938 | break; |
7939 | ||
7940 | case M_DMUL: | |
7941 | dbl = 1; | |
7942 | case M_MUL: | |
67c0d1eb RS |
7943 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7944 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7945 | break; |
252b5132 RH |
7946 | |
7947 | case M_DSUBU_I: | |
7948 | dbl = 1; | |
7949 | goto do_subu; | |
7950 | case M_SUBU_I: | |
7951 | do_subu: | |
7952 | if (imm_expr.X_op != O_constant) | |
7953 | as_bad (_("Unsupported large constant")); | |
7954 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7955 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7956 | break; |
7957 | ||
7958 | case M_SUBU_I_2: | |
7959 | if (imm_expr.X_op != O_constant) | |
7960 | as_bad (_("Unsupported large constant")); | |
7961 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7962 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7963 | break; |
7964 | ||
7965 | case M_DSUBU_I_2: | |
7966 | if (imm_expr.X_op != O_constant) | |
7967 | as_bad (_("Unsupported large constant")); | |
7968 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7969 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7970 | break; |
7971 | ||
7972 | case M_BEQ: | |
7973 | s = "cmp"; | |
7974 | s2 = "bteqz"; | |
7975 | goto do_branch; | |
7976 | case M_BNE: | |
7977 | s = "cmp"; | |
7978 | s2 = "btnez"; | |
7979 | goto do_branch; | |
7980 | case M_BLT: | |
7981 | s = "slt"; | |
7982 | s2 = "btnez"; | |
7983 | goto do_branch; | |
7984 | case M_BLTU: | |
7985 | s = "sltu"; | |
7986 | s2 = "btnez"; | |
7987 | goto do_branch; | |
7988 | case M_BLE: | |
7989 | s = "slt"; | |
7990 | s2 = "bteqz"; | |
7991 | goto do_reverse_branch; | |
7992 | case M_BLEU: | |
7993 | s = "sltu"; | |
7994 | s2 = "bteqz"; | |
7995 | goto do_reverse_branch; | |
7996 | case M_BGE: | |
7997 | s = "slt"; | |
7998 | s2 = "bteqz"; | |
7999 | goto do_branch; | |
8000 | case M_BGEU: | |
8001 | s = "sltu"; | |
8002 | s2 = "bteqz"; | |
8003 | goto do_branch; | |
8004 | case M_BGT: | |
8005 | s = "slt"; | |
8006 | s2 = "btnez"; | |
8007 | goto do_reverse_branch; | |
8008 | case M_BGTU: | |
8009 | s = "sltu"; | |
8010 | s2 = "btnez"; | |
8011 | ||
8012 | do_reverse_branch: | |
8013 | tmp = xreg; | |
8014 | xreg = yreg; | |
8015 | yreg = tmp; | |
8016 | ||
8017 | do_branch: | |
67c0d1eb RS |
8018 | macro_build (NULL, s, "x,y", xreg, yreg); |
8019 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8020 | break; |
8021 | ||
8022 | case M_BEQ_I: | |
8023 | s = "cmpi"; | |
8024 | s2 = "bteqz"; | |
8025 | s3 = "x,U"; | |
8026 | goto do_branch_i; | |
8027 | case M_BNE_I: | |
8028 | s = "cmpi"; | |
8029 | s2 = "btnez"; | |
8030 | s3 = "x,U"; | |
8031 | goto do_branch_i; | |
8032 | case M_BLT_I: | |
8033 | s = "slti"; | |
8034 | s2 = "btnez"; | |
8035 | s3 = "x,8"; | |
8036 | goto do_branch_i; | |
8037 | case M_BLTU_I: | |
8038 | s = "sltiu"; | |
8039 | s2 = "btnez"; | |
8040 | s3 = "x,8"; | |
8041 | goto do_branch_i; | |
8042 | case M_BLE_I: | |
8043 | s = "slti"; | |
8044 | s2 = "btnez"; | |
8045 | s3 = "x,8"; | |
8046 | goto do_addone_branch_i; | |
8047 | case M_BLEU_I: | |
8048 | s = "sltiu"; | |
8049 | s2 = "btnez"; | |
8050 | s3 = "x,8"; | |
8051 | goto do_addone_branch_i; | |
8052 | case M_BGE_I: | |
8053 | s = "slti"; | |
8054 | s2 = "bteqz"; | |
8055 | s3 = "x,8"; | |
8056 | goto do_branch_i; | |
8057 | case M_BGEU_I: | |
8058 | s = "sltiu"; | |
8059 | s2 = "bteqz"; | |
8060 | s3 = "x,8"; | |
8061 | goto do_branch_i; | |
8062 | case M_BGT_I: | |
8063 | s = "slti"; | |
8064 | s2 = "bteqz"; | |
8065 | s3 = "x,8"; | |
8066 | goto do_addone_branch_i; | |
8067 | case M_BGTU_I: | |
8068 | s = "sltiu"; | |
8069 | s2 = "bteqz"; | |
8070 | s3 = "x,8"; | |
8071 | ||
8072 | do_addone_branch_i: | |
8073 | if (imm_expr.X_op != O_constant) | |
8074 | as_bad (_("Unsupported large constant")); | |
8075 | ++imm_expr.X_add_number; | |
8076 | ||
8077 | do_branch_i: | |
67c0d1eb RS |
8078 | macro_build (&imm_expr, s, s3, xreg); |
8079 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8080 | break; |
8081 | ||
8082 | case M_ABS: | |
8083 | expr1.X_add_number = 0; | |
67c0d1eb | 8084 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8085 | if (xreg != yreg) |
67c0d1eb | 8086 | move_register (xreg, yreg); |
252b5132 | 8087 | expr1.X_add_number = 2; |
67c0d1eb RS |
8088 | macro_build (&expr1, "bteqz", "p"); |
8089 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8090 | } |
8091 | } | |
8092 | ||
8093 | /* For consistency checking, verify that all bits are specified either | |
8094 | by the match/mask part of the instruction definition, or by the | |
8095 | operand list. */ | |
8096 | static int | |
17a2f251 | 8097 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8098 | { |
8099 | const char *p = opc->args; | |
8100 | char c; | |
8101 | unsigned long used_bits = opc->mask; | |
8102 | ||
8103 | if ((used_bits & opc->match) != opc->match) | |
8104 | { | |
8105 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8106 | opc->name, opc->args); | |
8107 | return 0; | |
8108 | } | |
8109 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8110 | while (*p) | |
8111 | switch (c = *p++) | |
8112 | { | |
8113 | case ',': break; | |
8114 | case '(': break; | |
8115 | case ')': break; | |
af7ee8bf CD |
8116 | case '+': |
8117 | switch (c = *p++) | |
8118 | { | |
9bcd4f99 TS |
8119 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8120 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8121 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8122 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8123 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8124 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8125 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8126 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8127 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8128 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8129 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8130 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8131 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8132 | case 'I': break; | |
ef2e4d86 CF |
8133 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8134 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8135 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8136 | default: |
8137 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8138 | c, opc->name, opc->args); | |
8139 | return 0; | |
8140 | } | |
8141 | break; | |
252b5132 RH |
8142 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8143 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8144 | case 'A': break; | |
4372b673 | 8145 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8146 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8147 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8148 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8149 | case 'F': break; | |
8150 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8151 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8152 | case 'I': break; |
e972090a | 8153 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8154 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8155 | case 'L': break; |
8156 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8157 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8158 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8159 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8160 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8161 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8162 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8163 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8164 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8165 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8166 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8167 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8168 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8169 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8170 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8171 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8172 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8173 | case 'f': break; | |
8174 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8175 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8176 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8177 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8178 | case 'l': break; | |
8179 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8180 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8181 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8182 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8183 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8184 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8185 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8186 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8187 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8188 | case 'x': break; | |
8189 | case 'z': break; | |
8190 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8191 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8192 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8193 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8194 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8195 | case '[': break; | |
8196 | case ']': break; | |
74cd071d CF |
8197 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8198 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8199 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8200 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8201 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8202 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8203 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8204 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8205 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8206 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8207 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8208 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8209 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8210 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8211 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8212 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8213 | default: |
8214 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8215 | c, opc->name, opc->args); | |
8216 | return 0; | |
8217 | } | |
8218 | #undef USE_BITS | |
8219 | if (used_bits != 0xffffffff) | |
8220 | { | |
8221 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8222 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8223 | return 0; | |
8224 | } | |
8225 | return 1; | |
8226 | } | |
8227 | ||
9bcd4f99 TS |
8228 | /* UDI immediates. */ |
8229 | struct mips_immed { | |
8230 | char type; | |
8231 | unsigned int shift; | |
8232 | unsigned long mask; | |
8233 | const char * desc; | |
8234 | }; | |
8235 | ||
8236 | static const struct mips_immed mips_immed[] = { | |
8237 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8238 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8239 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8240 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8241 | { 0,0,0,0 } | |
8242 | }; | |
8243 | ||
7455baf8 TS |
8244 | /* Check whether an odd floating-point register is allowed. */ |
8245 | static int | |
8246 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8247 | { | |
8248 | const char *s = insn->name; | |
8249 | ||
8250 | if (insn->pinfo == INSN_MACRO) | |
8251 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8252 | return 1; | |
8253 | ||
8254 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8255 | { | |
8256 | /* Allow odd registers for single-precision ops. */ | |
8257 | switch (insn->pinfo & (FP_S | FP_D)) | |
8258 | { | |
8259 | case FP_S: | |
8260 | case 0: | |
8261 | return 1; /* both single precision - ok */ | |
8262 | case FP_D: | |
8263 | return 0; /* both double precision - fail */ | |
8264 | default: | |
8265 | break; | |
8266 | } | |
8267 | ||
8268 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8269 | s = strchr (insn->name, '.'); | |
8270 | if (argnum == 2) | |
8271 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8272 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8273 | } | |
8274 | ||
8275 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8276 | if ((insn->pinfo & FP_S) | |
8277 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8278 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8279 | return 1; | |
8280 | ||
8281 | return 0; | |
8282 | } | |
8283 | ||
252b5132 RH |
8284 | /* This routine assembles an instruction into its binary format. As a |
8285 | side effect, it sets one of the global variables imm_reloc or | |
8286 | offset_reloc to the type of relocation to do if one of the operands | |
8287 | is an address expression. */ | |
8288 | ||
8289 | static void | |
17a2f251 | 8290 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8291 | { |
8292 | char *s; | |
8293 | const char *args; | |
43841e91 | 8294 | char c = 0; |
252b5132 RH |
8295 | struct mips_opcode *insn; |
8296 | char *argsStart; | |
8297 | unsigned int regno; | |
8298 | unsigned int lastregno = 0; | |
af7ee8bf | 8299 | unsigned int lastpos = 0; |
071742cf | 8300 | unsigned int limlo, limhi; |
252b5132 RH |
8301 | char *s_reset; |
8302 | char save_c = 0; | |
74cd071d | 8303 | offsetT min_range, max_range; |
707bfff6 TS |
8304 | int argnum; |
8305 | unsigned int rtype; | |
252b5132 RH |
8306 | |
8307 | insn_error = NULL; | |
8308 | ||
8309 | /* If the instruction contains a '.', we first try to match an instruction | |
8310 | including the '.'. Then we try again without the '.'. */ | |
8311 | insn = NULL; | |
3882b010 | 8312 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8313 | continue; |
8314 | ||
8315 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8316 | the call to hash_find. Save the character we replaced just in case we | |
8317 | have to re-parse the instruction. */ | |
3882b010 | 8318 | if (ISSPACE (*s)) |
252b5132 RH |
8319 | { |
8320 | save_c = *s; | |
8321 | *s++ = '\0'; | |
8322 | } | |
bdaaa2e1 | 8323 | |
252b5132 RH |
8324 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8325 | ||
8326 | /* If we didn't find the instruction in the opcode table, try again, but | |
8327 | this time with just the instruction up to, but not including the | |
8328 | first '.'. */ | |
8329 | if (insn == NULL) | |
8330 | { | |
bdaaa2e1 | 8331 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8332 | if (save_c) |
8333 | *(--s) = save_c; | |
8334 | ||
8335 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8336 | for (s = str; |
8337 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8338 | ++s) | |
252b5132 RH |
8339 | continue; |
8340 | ||
8341 | /* If we did not find a '.', then we can quit now. */ | |
8342 | if (*s != '.') | |
8343 | { | |
8344 | insn_error = "unrecognized opcode"; | |
8345 | return; | |
8346 | } | |
8347 | ||
8348 | /* Lookup the instruction in the hash table. */ | |
8349 | *s++ = '\0'; | |
8350 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8351 | { | |
8352 | insn_error = "unrecognized opcode"; | |
8353 | return; | |
8354 | } | |
252b5132 RH |
8355 | } |
8356 | ||
8357 | argsStart = s; | |
8358 | for (;;) | |
8359 | { | |
b34976b6 | 8360 | bfd_boolean ok; |
252b5132 RH |
8361 | |
8362 | assert (strcmp (insn->name, str) == 0); | |
8363 | ||
1f25f5d3 CD |
8364 | if (OPCODE_IS_MEMBER (insn, |
8365 | (mips_opts.isa | |
9b3f89ee TS |
8366 | /* We don't check for mips_opts.mips16 here since |
8367 | we want to allow jalx if -mips16 was specified | |
8368 | on the command line. */ | |
3396de36 | 8369 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8370 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 8371 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
65263ce3 TS |
8372 | | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) |
8373 | ? INSN_DSP64 : 0) | |
ef2e4d86 | 8374 | | (mips_opts.ase_mt ? INSN_MT : 0) |
e16bfa71 TS |
8375 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0) |
8376 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), | |
fef14a42 | 8377 | mips_opts.arch)) |
b34976b6 | 8378 | ok = TRUE; |
bdaaa2e1 | 8379 | else |
b34976b6 | 8380 | ok = FALSE; |
bdaaa2e1 | 8381 | |
252b5132 RH |
8382 | if (insn->pinfo != INSN_MACRO) |
8383 | { | |
fef14a42 | 8384 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8385 | ok = FALSE; |
252b5132 RH |
8386 | } |
8387 | ||
8388 | if (! ok) | |
8389 | { | |
8390 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8391 | && strcmp (insn->name, insn[1].name) == 0) | |
8392 | { | |
8393 | ++insn; | |
8394 | continue; | |
8395 | } | |
252b5132 | 8396 | else |
beae10d5 | 8397 | { |
268f6bed L |
8398 | if (!insn_error) |
8399 | { | |
8400 | static char buf[100]; | |
fef14a42 TS |
8401 | sprintf (buf, |
8402 | _("opcode not supported on this processor: %s (%s)"), | |
8403 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8404 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8405 | insn_error = buf; |
8406 | } | |
8407 | if (save_c) | |
8408 | *(--s) = save_c; | |
2bd7f1f3 | 8409 | return; |
252b5132 | 8410 | } |
252b5132 RH |
8411 | } |
8412 | ||
1e915849 | 8413 | create_insn (ip, insn); |
268f6bed | 8414 | insn_error = NULL; |
707bfff6 | 8415 | argnum = 1; |
252b5132 RH |
8416 | for (args = insn->args;; ++args) |
8417 | { | |
deec1734 CD |
8418 | int is_mdmx; |
8419 | ||
ad8d3bb3 | 8420 | s += strspn (s, " \t"); |
deec1734 | 8421 | is_mdmx = 0; |
252b5132 RH |
8422 | switch (*args) |
8423 | { | |
8424 | case '\0': /* end of args */ | |
8425 | if (*s == '\0') | |
8426 | return; | |
8427 | break; | |
8428 | ||
74cd071d CF |
8429 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8430 | my_getExpression (&imm_expr, s); | |
8431 | check_absolute_expr (ip, &imm_expr); | |
8432 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8433 | { | |
a9e24354 TS |
8434 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8435 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8436 | } |
a9e24354 | 8437 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8438 | imm_expr.X_op = O_absent; |
8439 | s = expr_end; | |
8440 | continue; | |
8441 | ||
8442 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8443 | my_getExpression (&imm_expr, s); | |
8444 | check_absolute_expr (ip, &imm_expr); | |
8445 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8446 | { | |
a9e24354 TS |
8447 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8448 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8449 | } |
a9e24354 | 8450 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8451 | imm_expr.X_op = O_absent; |
8452 | s = expr_end; | |
8453 | continue; | |
8454 | ||
8455 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8456 | my_getExpression (&imm_expr, s); | |
8457 | check_absolute_expr (ip, &imm_expr); | |
8458 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8459 | { | |
a9e24354 TS |
8460 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8461 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8462 | } |
a9e24354 | 8463 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8464 | imm_expr.X_op = O_absent; |
8465 | s = expr_end; | |
8466 | continue; | |
8467 | ||
8468 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8469 | my_getExpression (&imm_expr, s); | |
8470 | check_absolute_expr (ip, &imm_expr); | |
8471 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8472 | { | |
a9e24354 TS |
8473 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8474 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8475 | } |
a9e24354 | 8476 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8477 | imm_expr.X_op = O_absent; |
8478 | s = expr_end; | |
8479 | continue; | |
8480 | ||
8481 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8482 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8483 | s[3] >= '0' && s[3] <= '3') | |
8484 | { | |
8485 | regno = s[3] - '0'; | |
8486 | s += 4; | |
a9e24354 | 8487 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8488 | continue; |
8489 | } | |
8490 | else | |
8491 | as_bad (_("Invalid dsp acc register")); | |
8492 | break; | |
8493 | ||
8494 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8495 | my_getExpression (&imm_expr, s); | |
8496 | check_absolute_expr (ip, &imm_expr); | |
8497 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8498 | { | |
a9e24354 TS |
8499 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8500 | OP_MASK_WRDSP, | |
8501 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8502 | } |
a9e24354 | 8503 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8504 | imm_expr.X_op = O_absent; |
8505 | s = expr_end; | |
8506 | continue; | |
8507 | ||
8508 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8509 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8510 | s[3] >= '0' && s[3] <= '3') | |
8511 | { | |
8512 | regno = s[3] - '0'; | |
8513 | s += 4; | |
a9e24354 | 8514 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8515 | continue; |
8516 | } | |
8517 | else | |
8518 | as_bad (_("Invalid dsp acc register")); | |
8519 | break; | |
8520 | ||
8521 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8522 | my_getExpression (&imm_expr, s); | |
8523 | check_absolute_expr (ip, &imm_expr); | |
8524 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8525 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8526 | if (imm_expr.X_add_number < min_range || | |
8527 | imm_expr.X_add_number > max_range) | |
8528 | { | |
a9e24354 TS |
8529 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8530 | (long) min_range, (long) max_range, | |
8531 | (long) imm_expr.X_add_number); | |
74cd071d | 8532 | } |
a9e24354 | 8533 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8534 | imm_expr.X_op = O_absent; |
8535 | s = expr_end; | |
8536 | continue; | |
8537 | ||
8538 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8539 | my_getExpression (&imm_expr, s); | |
8540 | check_absolute_expr (ip, &imm_expr); | |
8541 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8542 | { | |
a9e24354 TS |
8543 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8544 | OP_MASK_RDDSP, | |
8545 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8546 | } |
a9e24354 | 8547 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8548 | imm_expr.X_op = O_absent; |
8549 | s = expr_end; | |
8550 | continue; | |
8551 | ||
8552 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8553 | my_getExpression (&imm_expr, s); | |
8554 | check_absolute_expr (ip, &imm_expr); | |
8555 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8556 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8557 | if (imm_expr.X_add_number < min_range || | |
8558 | imm_expr.X_add_number > max_range) | |
8559 | { | |
a9e24354 TS |
8560 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8561 | (long) min_range, (long) max_range, | |
8562 | (long) imm_expr.X_add_number); | |
74cd071d | 8563 | } |
a9e24354 | 8564 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8565 | imm_expr.X_op = O_absent; |
8566 | s = expr_end; | |
8567 | continue; | |
8568 | ||
8569 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8570 | my_getExpression (&imm_expr, s); | |
8571 | check_absolute_expr (ip, &imm_expr); | |
8572 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8573 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8574 | if (imm_expr.X_add_number < min_range || | |
8575 | imm_expr.X_add_number > max_range) | |
8576 | { | |
a9e24354 TS |
8577 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8578 | (long) min_range, (long) max_range, | |
8579 | (long) imm_expr.X_add_number); | |
74cd071d | 8580 | } |
a9e24354 | 8581 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8582 | imm_expr.X_op = O_absent; |
8583 | s = expr_end; | |
8584 | continue; | |
8585 | ||
a9e24354 | 8586 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8587 | my_getExpression (&imm_expr, s); |
8588 | check_absolute_expr (ip, &imm_expr); | |
8589 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8590 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8591 | (unsigned long) imm_expr.X_add_number); | |
8592 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8593 | imm_expr.X_op = O_absent; |
8594 | s = expr_end; | |
8595 | continue; | |
8596 | ||
a9e24354 | 8597 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8598 | my_getExpression (&imm_expr, s); |
8599 | check_absolute_expr (ip, &imm_expr); | |
8600 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8601 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8602 | (unsigned long) imm_expr.X_add_number); | |
8603 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8604 | imm_expr.X_op = O_absent; |
8605 | s = expr_end; | |
8606 | continue; | |
8607 | ||
8608 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8609 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8610 | s[3] >= '0' && s[3] <= '3') | |
8611 | { | |
8612 | regno = s[3] - '0'; | |
8613 | s += 4; | |
a9e24354 | 8614 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8615 | continue; |
8616 | } | |
8617 | else | |
8618 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8619 | break; | |
8620 | ||
8621 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8622 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8623 | s[3] >= '0' && s[3] <= '3') | |
8624 | { | |
8625 | regno = s[3] - '0'; | |
8626 | s += 4; | |
a9e24354 | 8627 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8628 | continue; |
8629 | } | |
8630 | else | |
8631 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8632 | break; | |
8633 | ||
252b5132 | 8634 | case ',': |
a339155f | 8635 | ++argnum; |
252b5132 RH |
8636 | if (*s++ == *args) |
8637 | continue; | |
8638 | s--; | |
8639 | switch (*++args) | |
8640 | { | |
8641 | case 'r': | |
8642 | case 'v': | |
bf12938e | 8643 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8644 | continue; |
8645 | ||
8646 | case 'w': | |
bf12938e | 8647 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8648 | continue; |
8649 | ||
252b5132 | 8650 | case 'W': |
bf12938e | 8651 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8652 | continue; |
8653 | ||
8654 | case 'V': | |
bf12938e | 8655 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8656 | continue; |
8657 | } | |
8658 | break; | |
8659 | ||
8660 | case '(': | |
8661 | /* Handle optional base register. | |
8662 | Either the base register is omitted or | |
bdaaa2e1 | 8663 | we must have a left paren. */ |
252b5132 RH |
8664 | /* This is dependent on the next operand specifier |
8665 | is a base register specification. */ | |
8666 | assert (args[1] == 'b' || args[1] == '5' | |
8667 | || args[1] == '-' || args[1] == '4'); | |
8668 | if (*s == '\0') | |
8669 | return; | |
8670 | ||
8671 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8672 | case '[': |
8673 | case ']': | |
252b5132 RH |
8674 | if (*s++ == *args) |
8675 | continue; | |
8676 | break; | |
8677 | ||
af7ee8bf CD |
8678 | case '+': /* Opcode extension character. */ |
8679 | switch (*++args) | |
8680 | { | |
9bcd4f99 TS |
8681 | case '1': /* UDI immediates. */ |
8682 | case '2': | |
8683 | case '3': | |
8684 | case '4': | |
8685 | { | |
8686 | const struct mips_immed *imm = mips_immed; | |
8687 | ||
8688 | while (imm->type && imm->type != *args) | |
8689 | ++imm; | |
8690 | if (! imm->type) | |
8691 | internalError (); | |
8692 | my_getExpression (&imm_expr, s); | |
8693 | check_absolute_expr (ip, &imm_expr); | |
8694 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8695 | { | |
8696 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8697 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8698 | (unsigned long) imm_expr.X_add_number, | |
8699 | (unsigned long) imm_expr.X_add_number); | |
8700 | imm_expr.X_add_number &= imm->mask; | |
8701 | } | |
8702 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8703 | << imm->shift); | |
8704 | imm_expr.X_op = O_absent; | |
8705 | s = expr_end; | |
8706 | } | |
8707 | continue; | |
8708 | ||
071742cf CD |
8709 | case 'A': /* ins/ext position, becomes LSB. */ |
8710 | limlo = 0; | |
8711 | limhi = 31; | |
5f74bc13 CD |
8712 | goto do_lsb; |
8713 | case 'E': | |
8714 | limlo = 32; | |
8715 | limhi = 63; | |
8716 | goto do_lsb; | |
8717 | do_lsb: | |
071742cf CD |
8718 | my_getExpression (&imm_expr, s); |
8719 | check_absolute_expr (ip, &imm_expr); | |
8720 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8721 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8722 | { | |
8723 | as_bad (_("Improper position (%lu)"), | |
8724 | (unsigned long) imm_expr.X_add_number); | |
8725 | imm_expr.X_add_number = limlo; | |
8726 | } | |
8727 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8728 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8729 | imm_expr.X_op = O_absent; |
8730 | s = expr_end; | |
8731 | continue; | |
8732 | ||
8733 | case 'B': /* ins size, becomes MSB. */ | |
8734 | limlo = 1; | |
8735 | limhi = 32; | |
5f74bc13 CD |
8736 | goto do_msb; |
8737 | case 'F': | |
8738 | limlo = 33; | |
8739 | limhi = 64; | |
8740 | goto do_msb; | |
8741 | do_msb: | |
071742cf CD |
8742 | my_getExpression (&imm_expr, s); |
8743 | check_absolute_expr (ip, &imm_expr); | |
8744 | /* Check for negative input so that small negative numbers | |
8745 | will not succeed incorrectly. The checks against | |
8746 | (pos+size) transitively check "size" itself, | |
8747 | assuming that "pos" is reasonable. */ | |
8748 | if ((long) imm_expr.X_add_number < 0 | |
8749 | || ((unsigned long) imm_expr.X_add_number | |
8750 | + lastpos) < limlo | |
8751 | || ((unsigned long) imm_expr.X_add_number | |
8752 | + lastpos) > limhi) | |
8753 | { | |
8754 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8755 | (unsigned long) imm_expr.X_add_number, | |
8756 | (unsigned long) lastpos); | |
8757 | imm_expr.X_add_number = limlo - lastpos; | |
8758 | } | |
bf12938e RS |
8759 | INSERT_OPERAND (INSMSB, *ip, |
8760 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8761 | imm_expr.X_op = O_absent; |
8762 | s = expr_end; | |
8763 | continue; | |
8764 | ||
8765 | case 'C': /* ext size, becomes MSBD. */ | |
8766 | limlo = 1; | |
8767 | limhi = 32; | |
5f74bc13 CD |
8768 | goto do_msbd; |
8769 | case 'G': | |
8770 | limlo = 33; | |
8771 | limhi = 64; | |
8772 | goto do_msbd; | |
8773 | case 'H': | |
8774 | limlo = 33; | |
8775 | limhi = 64; | |
8776 | goto do_msbd; | |
8777 | do_msbd: | |
071742cf CD |
8778 | my_getExpression (&imm_expr, s); |
8779 | check_absolute_expr (ip, &imm_expr); | |
8780 | /* Check for negative input so that small negative numbers | |
8781 | will not succeed incorrectly. The checks against | |
8782 | (pos+size) transitively check "size" itself, | |
8783 | assuming that "pos" is reasonable. */ | |
8784 | if ((long) imm_expr.X_add_number < 0 | |
8785 | || ((unsigned long) imm_expr.X_add_number | |
8786 | + lastpos) < limlo | |
8787 | || ((unsigned long) imm_expr.X_add_number | |
8788 | + lastpos) > limhi) | |
8789 | { | |
8790 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8791 | (unsigned long) imm_expr.X_add_number, | |
8792 | (unsigned long) lastpos); | |
8793 | imm_expr.X_add_number = limlo - lastpos; | |
8794 | } | |
bf12938e | 8795 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8796 | imm_expr.X_op = O_absent; |
8797 | s = expr_end; | |
8798 | continue; | |
af7ee8bf | 8799 | |
bbcc0807 CD |
8800 | case 'D': |
8801 | /* +D is for disassembly only; never match. */ | |
8802 | break; | |
8803 | ||
5f74bc13 CD |
8804 | case 'I': |
8805 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8806 | my_getExpression (&imm2_expr, s); | |
8807 | if (imm2_expr.X_op != O_big | |
8808 | && imm2_expr.X_op != O_constant) | |
8809 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8810 | if (HAVE_32BIT_GPRS) |
8811 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8812 | s = expr_end; |
8813 | continue; | |
8814 | ||
707bfff6 | 8815 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
8816 | /* +T is for disassembly only; never match. */ |
8817 | break; | |
8818 | ||
707bfff6 | 8819 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
8820 | if (s[0] == '$' && ISDIGIT (s[1])) |
8821 | { | |
8822 | ++s; | |
8823 | regno = 0; | |
8824 | do | |
8825 | { | |
8826 | regno *= 10; | |
8827 | regno += *s - '0'; | |
8828 | ++s; | |
8829 | } | |
8830 | while (ISDIGIT (*s)); | |
8831 | if (regno > 31) | |
8832 | as_bad (_("Invalid register number (%d)"), regno); | |
8833 | else | |
8834 | { | |
a9e24354 | 8835 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
8836 | continue; |
8837 | } | |
8838 | } | |
8839 | else | |
8840 | as_bad (_("Invalid coprocessor 0 register number")); | |
8841 | break; | |
8842 | ||
af7ee8bf CD |
8843 | default: |
8844 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8845 | *args, insn->name, insn->args); | |
8846 | /* Further processing is fruitless. */ | |
8847 | return; | |
8848 | } | |
8849 | break; | |
8850 | ||
252b5132 RH |
8851 | case '<': /* must be at least one digit */ |
8852 | /* | |
8853 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8854 | * than 31 or less than 0, then the shift amount should be |
8855 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8856 | * We issue a warning and mask out all but the low 5 bits. |
8857 | */ | |
8858 | my_getExpression (&imm_expr, s); | |
8859 | check_absolute_expr (ip, &imm_expr); | |
8860 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8861 | as_warn (_("Improper shift amount (%lu)"), |
8862 | (unsigned long) imm_expr.X_add_number); | |
8863 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8864 | imm_expr.X_op = O_absent; |
8865 | s = expr_end; | |
8866 | continue; | |
8867 | ||
8868 | case '>': /* shift amount minus 32 */ | |
8869 | my_getExpression (&imm_expr, s); | |
8870 | check_absolute_expr (ip, &imm_expr); | |
8871 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8872 | || (unsigned long) imm_expr.X_add_number > 63) | |
8873 | break; | |
bf12938e | 8874 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8875 | imm_expr.X_op = O_absent; |
8876 | s = expr_end; | |
8877 | continue; | |
8878 | ||
252b5132 RH |
8879 | case 'k': /* cache code */ |
8880 | case 'h': /* prefx code */ | |
8881 | my_getExpression (&imm_expr, s); | |
8882 | check_absolute_expr (ip, &imm_expr); | |
8883 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8884 | as_warn (_("Invalid value for `%s' (%lu)"), |
8885 | ip->insn_mo->name, | |
8886 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8887 | if (*args == 'k') |
bf12938e | 8888 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8889 | else |
bf12938e | 8890 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8891 | imm_expr.X_op = O_absent; |
8892 | s = expr_end; | |
8893 | continue; | |
8894 | ||
8895 | case 'c': /* break code */ | |
8896 | my_getExpression (&imm_expr, s); | |
8897 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8898 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
8899 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
8900 | ip->insn_mo->name, | |
bf12938e RS |
8901 | (unsigned long) imm_expr.X_add_number); |
8902 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8903 | imm_expr.X_op = O_absent; |
8904 | s = expr_end; | |
8905 | continue; | |
8906 | ||
8907 | case 'q': /* lower break code */ | |
8908 | my_getExpression (&imm_expr, s); | |
8909 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8910 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
8911 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
8912 | ip->insn_mo->name, | |
bf12938e RS |
8913 | (unsigned long) imm_expr.X_add_number); |
8914 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8915 | imm_expr.X_op = O_absent; |
8916 | s = expr_end; | |
8917 | continue; | |
8918 | ||
4372b673 | 8919 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8920 | my_getExpression (&imm_expr, s); |
156c2f8b | 8921 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 8922 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
8923 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
8924 | ip->insn_mo->name, | |
793b27f4 | 8925 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 8926 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8927 | imm_expr.X_op = O_absent; |
8928 | s = expr_end; | |
8929 | continue; | |
8930 | ||
98d3f06f | 8931 | case 'C': /* Coprocessor code */ |
beae10d5 | 8932 | my_getExpression (&imm_expr, s); |
252b5132 | 8933 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 8934 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 8935 | { |
793b27f4 TS |
8936 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8937 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 8938 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 8939 | } |
a9e24354 | 8940 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
8941 | imm_expr.X_op = O_absent; |
8942 | s = expr_end; | |
8943 | continue; | |
252b5132 | 8944 | |
4372b673 NC |
8945 | case 'J': /* 19-bit wait code. */ |
8946 | my_getExpression (&imm_expr, s); | |
8947 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8948 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
8949 | { |
8950 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8951 | (unsigned long) imm_expr.X_add_number); | |
8952 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
8953 | } | |
bf12938e | 8954 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8955 | imm_expr.X_op = O_absent; |
8956 | s = expr_end; | |
8957 | continue; | |
8958 | ||
707bfff6 | 8959 | case 'P': /* Performance register. */ |
beae10d5 | 8960 | my_getExpression (&imm_expr, s); |
252b5132 | 8961 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8962 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8963 | as_warn (_("Invalid performance register (%lu)"), |
8964 | (unsigned long) imm_expr.X_add_number); | |
8965 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8966 | imm_expr.X_op = O_absent; |
8967 | s = expr_end; | |
8968 | continue; | |
252b5132 | 8969 | |
707bfff6 TS |
8970 | case 'G': /* Coprocessor destination register. */ |
8971 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
8972 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
8973 | else | |
8974 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 8975 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
8976 | if (ok) |
8977 | { | |
8978 | lastregno = regno; | |
8979 | continue; | |
8980 | } | |
8981 | else | |
8982 | break; | |
8983 | ||
252b5132 RH |
8984 | case 'b': /* base register */ |
8985 | case 'd': /* destination register */ | |
8986 | case 's': /* source register */ | |
8987 | case 't': /* target register */ | |
8988 | case 'r': /* both target and source */ | |
8989 | case 'v': /* both dest and source */ | |
8990 | case 'w': /* both dest and target */ | |
8991 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 8992 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8993 | case 'x': /* ignore register name */ |
8994 | case 'z': /* must be zero register */ | |
4372b673 | 8995 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 8996 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
8997 | s_reset = s; |
8998 | if (*args == 'E' || *args == 'K') | |
8999 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9000 | else | |
9001 | { | |
9002 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
9003 | if (regno == AT && ! mips_opts.noat) | |
9004 | as_warn ("Used $at without \".set noat\""); | |
9005 | } | |
9006 | if (ok) | |
252b5132 | 9007 | { |
252b5132 RH |
9008 | c = *args; |
9009 | if (*s == ' ') | |
f9419b05 | 9010 | ++s; |
252b5132 RH |
9011 | if (args[1] != *s) |
9012 | { | |
9013 | if (c == 'r' || c == 'v' || c == 'w') | |
9014 | { | |
9015 | regno = lastregno; | |
9016 | s = s_reset; | |
f9419b05 | 9017 | ++args; |
252b5132 RH |
9018 | } |
9019 | } | |
9020 | /* 'z' only matches $0. */ | |
9021 | if (c == 'z' && regno != 0) | |
9022 | break; | |
9023 | ||
bdaaa2e1 KH |
9024 | /* Now that we have assembled one operand, we use the args string |
9025 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9026 | switch (c) |
9027 | { | |
9028 | case 'r': | |
9029 | case 's': | |
9030 | case 'v': | |
9031 | case 'b': | |
bf12938e | 9032 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9033 | break; |
9034 | case 'd': | |
9035 | case 'G': | |
af7ee8bf | 9036 | case 'K': |
ef2e4d86 | 9037 | case 'g': |
bf12938e | 9038 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9039 | break; |
4372b673 | 9040 | case 'U': |
bf12938e RS |
9041 | INSERT_OPERAND (RD, *ip, regno); |
9042 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9043 | break; |
252b5132 RH |
9044 | case 'w': |
9045 | case 't': | |
9046 | case 'E': | |
bf12938e | 9047 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9048 | break; |
9049 | case 'x': | |
9050 | /* This case exists because on the r3000 trunc | |
9051 | expands into a macro which requires a gp | |
9052 | register. On the r6000 or r4000 it is | |
9053 | assembled into a single instruction which | |
9054 | ignores the register. Thus the insn version | |
9055 | is MIPS_ISA2 and uses 'x', and the macro | |
9056 | version is MIPS_ISA1 and uses 't'. */ | |
9057 | break; | |
9058 | case 'z': | |
9059 | /* This case is for the div instruction, which | |
9060 | acts differently if the destination argument | |
9061 | is $0. This only matches $0, and is checked | |
9062 | outside the switch. */ | |
9063 | break; | |
9064 | case 'D': | |
9065 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9066 | break; | |
9067 | /* What about all other operands like 'i', which | |
9068 | can be specified in the opcode table? */ | |
9069 | } | |
9070 | lastregno = regno; | |
9071 | continue; | |
9072 | } | |
252b5132 RH |
9073 | switch (*args++) |
9074 | { | |
9075 | case 'r': | |
9076 | case 'v': | |
bf12938e | 9077 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9078 | continue; |
9079 | case 'w': | |
bf12938e | 9080 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9081 | continue; |
9082 | } | |
9083 | break; | |
9084 | ||
deec1734 CD |
9085 | case 'O': /* MDMX alignment immediate constant. */ |
9086 | my_getExpression (&imm_expr, s); | |
9087 | check_absolute_expr (ip, &imm_expr); | |
9088 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
9089 | as_warn ("Improper align amount (%ld), using low bits", |
9090 | (long) imm_expr.X_add_number); | |
9091 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9092 | imm_expr.X_op = O_absent; |
9093 | s = expr_end; | |
9094 | continue; | |
9095 | ||
9096 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9097 | if (s[0] != '$') | |
9098 | { | |
9099 | /* MDMX Immediate. */ | |
9100 | my_getExpression (&imm_expr, s); | |
9101 | check_absolute_expr (ip, &imm_expr); | |
9102 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9103 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9104 | (long) imm_expr.X_add_number); | |
9105 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9106 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9107 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9108 | else | |
9109 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9110 | imm_expr.X_op = O_absent; |
9111 | s = expr_end; | |
9112 | continue; | |
9113 | } | |
9114 | /* Not MDMX Immediate. Fall through. */ | |
9115 | case 'X': /* MDMX destination register. */ | |
9116 | case 'Y': /* MDMX source register. */ | |
9117 | case 'Z': /* MDMX target register. */ | |
9118 | is_mdmx = 1; | |
252b5132 RH |
9119 | case 'D': /* floating point destination register */ |
9120 | case 'S': /* floating point source register */ | |
9121 | case 'T': /* floating point target register */ | |
9122 | case 'R': /* floating point source register */ | |
9123 | case 'V': | |
9124 | case 'W': | |
707bfff6 TS |
9125 | rtype = RTYPE_FPU; |
9126 | if (is_mdmx | |
9127 | || (mips_opts.ase_mdmx | |
9128 | && (ip->insn_mo->pinfo & FP_D) | |
9129 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9130 | | INSN_COPROC_MEMORY_DELAY | |
9131 | | INSN_LOAD_COPROC_DELAY | |
9132 | | INSN_LOAD_MEMORY_DELAY | |
9133 | | INSN_STORE_MEMORY)))) | |
9134 | rtype |= RTYPE_VEC; | |
252b5132 | 9135 | s_reset = s; |
707bfff6 | 9136 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9137 | { |
252b5132 | 9138 | if ((regno & 1) != 0 |
ca4e0257 | 9139 | && HAVE_32BIT_FPRS |
7455baf8 | 9140 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9141 | as_warn (_("Float register should be even, was %d"), |
9142 | regno); | |
9143 | ||
9144 | c = *args; | |
9145 | if (*s == ' ') | |
f9419b05 | 9146 | ++s; |
252b5132 RH |
9147 | if (args[1] != *s) |
9148 | { | |
9149 | if (c == 'V' || c == 'W') | |
9150 | { | |
9151 | regno = lastregno; | |
9152 | s = s_reset; | |
f9419b05 | 9153 | ++args; |
252b5132 RH |
9154 | } |
9155 | } | |
9156 | switch (c) | |
9157 | { | |
9158 | case 'D': | |
deec1734 | 9159 | case 'X': |
bf12938e | 9160 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9161 | break; |
9162 | case 'V': | |
9163 | case 'S': | |
deec1734 | 9164 | case 'Y': |
bf12938e | 9165 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9166 | break; |
deec1734 CD |
9167 | case 'Q': |
9168 | /* This is like 'Z', but also needs to fix the MDMX | |
9169 | vector/scalar select bits. Note that the | |
9170 | scalar immediate case is handled above. */ | |
9171 | if (*s == '[') | |
9172 | { | |
9173 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9174 | int max_el = (is_qh ? 3 : 7); | |
9175 | s++; | |
9176 | my_getExpression(&imm_expr, s); | |
9177 | check_absolute_expr (ip, &imm_expr); | |
9178 | s = expr_end; | |
9179 | if (imm_expr.X_add_number > max_el) | |
9180 | as_bad(_("Bad element selector %ld"), | |
9181 | (long) imm_expr.X_add_number); | |
9182 | imm_expr.X_add_number &= max_el; | |
9183 | ip->insn_opcode |= (imm_expr.X_add_number | |
9184 | << (OP_SH_VSEL + | |
9185 | (is_qh ? 2 : 1))); | |
01a3f561 | 9186 | imm_expr.X_op = O_absent; |
deec1734 CD |
9187 | if (*s != ']') |
9188 | as_warn(_("Expecting ']' found '%s'"), s); | |
9189 | else | |
9190 | s++; | |
9191 | } | |
9192 | else | |
9193 | { | |
9194 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9195 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9196 | << OP_SH_VSEL); | |
9197 | else | |
9198 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9199 | OP_SH_VSEL); | |
9200 | } | |
9201 | /* Fall through */ | |
252b5132 RH |
9202 | case 'W': |
9203 | case 'T': | |
deec1734 | 9204 | case 'Z': |
bf12938e | 9205 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9206 | break; |
9207 | case 'R': | |
bf12938e | 9208 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9209 | break; |
9210 | } | |
9211 | lastregno = regno; | |
9212 | continue; | |
9213 | } | |
9214 | ||
252b5132 RH |
9215 | switch (*args++) |
9216 | { | |
9217 | case 'V': | |
bf12938e | 9218 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9219 | continue; |
9220 | case 'W': | |
bf12938e | 9221 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9222 | continue; |
9223 | } | |
9224 | break; | |
9225 | ||
9226 | case 'I': | |
9227 | my_getExpression (&imm_expr, s); | |
9228 | if (imm_expr.X_op != O_big | |
9229 | && imm_expr.X_op != O_constant) | |
9230 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9231 | if (HAVE_32BIT_GPRS) |
9232 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9233 | s = expr_end; |
9234 | continue; | |
9235 | ||
9236 | case 'A': | |
9237 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9238 | normalize_address_expr (&offset_expr); |
f6688943 | 9239 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9240 | s = expr_end; |
9241 | continue; | |
9242 | ||
9243 | case 'F': | |
9244 | case 'L': | |
9245 | case 'f': | |
9246 | case 'l': | |
9247 | { | |
9248 | int f64; | |
ca4e0257 | 9249 | int using_gprs; |
252b5132 RH |
9250 | char *save_in; |
9251 | char *err; | |
9252 | unsigned char temp[8]; | |
9253 | int len; | |
9254 | unsigned int length; | |
9255 | segT seg; | |
9256 | subsegT subseg; | |
9257 | char *p; | |
9258 | ||
9259 | /* These only appear as the last operand in an | |
9260 | instruction, and every instruction that accepts | |
9261 | them in any variant accepts them in all variants. | |
9262 | This means we don't have to worry about backing out | |
9263 | any changes if the instruction does not match. | |
9264 | ||
9265 | The difference between them is the size of the | |
9266 | floating point constant and where it goes. For 'F' | |
9267 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9268 | is 32 bits. Where the constant is placed is based | |
9269 | on how the MIPS assembler does things: | |
9270 | F -- .rdata | |
9271 | L -- .lit8 | |
9272 | f -- immediate value | |
9273 | l -- .lit4 | |
9274 | ||
9275 | The .lit4 and .lit8 sections are only used if | |
9276 | permitted by the -G argument. | |
9277 | ||
ca4e0257 RS |
9278 | The code below needs to know whether the target register |
9279 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9280 | 'F' are used with GPR-based instructions and 'l' and | |
9281 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9282 | |
9283 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9284 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9285 | |
9286 | save_in = input_line_pointer; | |
9287 | input_line_pointer = s; | |
9288 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9289 | length = len; | |
9290 | s = input_line_pointer; | |
9291 | input_line_pointer = save_in; | |
9292 | if (err != NULL && *err != '\0') | |
9293 | { | |
9294 | as_bad (_("Bad floating point constant: %s"), err); | |
9295 | memset (temp, '\0', sizeof temp); | |
9296 | length = f64 ? 8 : 4; | |
9297 | } | |
9298 | ||
156c2f8b | 9299 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9300 | |
9301 | if (*args == 'f' | |
9302 | || (*args == 'l' | |
3e722fb5 | 9303 | && (g_switch_value < 4 |
252b5132 RH |
9304 | || (temp[0] == 0 && temp[1] == 0) |
9305 | || (temp[2] == 0 && temp[3] == 0)))) | |
9306 | { | |
9307 | imm_expr.X_op = O_constant; | |
9308 | if (! target_big_endian) | |
9309 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9310 | else | |
9311 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9312 | } | |
9313 | else if (length > 4 | |
119d663a | 9314 | && ! mips_disable_float_construction |
ca4e0257 RS |
9315 | /* Constants can only be constructed in GPRs and |
9316 | copied to FPRs if the GPRs are at least as wide | |
9317 | as the FPRs. Force the constant into memory if | |
9318 | we are using 64-bit FPRs but the GPRs are only | |
9319 | 32 bits wide. */ | |
9320 | && (using_gprs | |
9321 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9322 | && ((temp[0] == 0 && temp[1] == 0) |
9323 | || (temp[2] == 0 && temp[3] == 0)) | |
9324 | && ((temp[4] == 0 && temp[5] == 0) | |
9325 | || (temp[6] == 0 && temp[7] == 0))) | |
9326 | { | |
ca4e0257 RS |
9327 | /* The value is simple enough to load with a couple of |
9328 | instructions. If using 32-bit registers, set | |
9329 | imm_expr to the high order 32 bits and offset_expr to | |
9330 | the low order 32 bits. Otherwise, set imm_expr to | |
9331 | the entire 64 bit constant. */ | |
9332 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9333 | { |
9334 | imm_expr.X_op = O_constant; | |
9335 | offset_expr.X_op = O_constant; | |
9336 | if (! target_big_endian) | |
9337 | { | |
9338 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9339 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9340 | } | |
9341 | else | |
9342 | { | |
9343 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9344 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9345 | } | |
9346 | if (offset_expr.X_add_number == 0) | |
9347 | offset_expr.X_op = O_absent; | |
9348 | } | |
9349 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9350 | { | |
9351 | imm_expr.X_op = O_constant; | |
9352 | if (! target_big_endian) | |
9353 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9354 | else | |
9355 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9356 | } | |
9357 | else | |
9358 | { | |
9359 | imm_expr.X_op = O_big; | |
9360 | imm_expr.X_add_number = 4; | |
9361 | if (! target_big_endian) | |
9362 | { | |
9363 | generic_bignum[0] = bfd_getl16 (temp); | |
9364 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9365 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9366 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9367 | } | |
9368 | else | |
9369 | { | |
9370 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9371 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9372 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9373 | generic_bignum[3] = bfd_getb16 (temp); | |
9374 | } | |
9375 | } | |
9376 | } | |
9377 | else | |
9378 | { | |
9379 | const char *newname; | |
9380 | segT new_seg; | |
9381 | ||
9382 | /* Switch to the right section. */ | |
9383 | seg = now_seg; | |
9384 | subseg = now_subseg; | |
9385 | switch (*args) | |
9386 | { | |
9387 | default: /* unused default case avoids warnings. */ | |
9388 | case 'L': | |
9389 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9390 | if (g_switch_value >= 8) |
252b5132 RH |
9391 | newname = ".lit8"; |
9392 | break; | |
9393 | case 'F': | |
3e722fb5 | 9394 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9395 | break; |
9396 | case 'l': | |
4d0d148d | 9397 | assert (g_switch_value >= 4); |
252b5132 RH |
9398 | newname = ".lit4"; |
9399 | break; | |
9400 | } | |
9401 | new_seg = subseg_new (newname, (subsegT) 0); | |
9402 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9403 | bfd_set_section_flags (stdoutput, new_seg, | |
9404 | (SEC_ALLOC | |
9405 | | SEC_LOAD | |
9406 | | SEC_READONLY | |
9407 | | SEC_DATA)); | |
9408 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9409 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9410 | && strcmp (TARGET_OS, "elf") != 0) | |
9411 | record_alignment (new_seg, 4); | |
9412 | else | |
9413 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9414 | if (seg == now_seg) | |
9415 | as_bad (_("Can't use floating point insn in this section")); | |
9416 | ||
9417 | /* Set the argument to the current address in the | |
9418 | section. */ | |
9419 | offset_expr.X_op = O_symbol; | |
9420 | offset_expr.X_add_symbol = | |
9421 | symbol_new ("L0\001", now_seg, | |
9422 | (valueT) frag_now_fix (), frag_now); | |
9423 | offset_expr.X_add_number = 0; | |
9424 | ||
9425 | /* Put the floating point number into the section. */ | |
9426 | p = frag_more ((int) length); | |
9427 | memcpy (p, temp, length); | |
9428 | ||
9429 | /* Switch back to the original section. */ | |
9430 | subseg_set (seg, subseg); | |
9431 | } | |
9432 | } | |
9433 | continue; | |
9434 | ||
9435 | case 'i': /* 16 bit unsigned immediate */ | |
9436 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9437 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9438 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9439 | { |
9440 | int more; | |
5e0116d5 RS |
9441 | offsetT minval, maxval; |
9442 | ||
9443 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9444 | && strcmp (insn->name, insn[1].name) == 0); | |
9445 | ||
9446 | /* If the expression was written as an unsigned number, | |
9447 | only treat it as signed if there are no more | |
9448 | alternatives. */ | |
9449 | if (more | |
9450 | && *args == 'j' | |
9451 | && sizeof (imm_expr.X_add_number) <= 4 | |
9452 | && imm_expr.X_op == O_constant | |
9453 | && imm_expr.X_add_number < 0 | |
9454 | && imm_expr.X_unsigned | |
9455 | && HAVE_64BIT_GPRS) | |
9456 | break; | |
9457 | ||
9458 | /* For compatibility with older assemblers, we accept | |
9459 | 0x8000-0xffff as signed 16-bit numbers when only | |
9460 | signed numbers are allowed. */ | |
9461 | if (*args == 'i') | |
9462 | minval = 0, maxval = 0xffff; | |
9463 | else if (more) | |
9464 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9465 | else |
5e0116d5 RS |
9466 | minval = -0x8000, maxval = 0xffff; |
9467 | ||
9468 | if (imm_expr.X_op != O_constant | |
9469 | || imm_expr.X_add_number < minval | |
9470 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9471 | { |
9472 | if (more) | |
9473 | break; | |
2ae7e77b AH |
9474 | if (imm_expr.X_op == O_constant |
9475 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9476 | as_bad (_("expression out of range")); |
252b5132 RH |
9477 | } |
9478 | } | |
9479 | s = expr_end; | |
9480 | continue; | |
9481 | ||
9482 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9483 | /* Check whether there is only a single bracketed expression |
9484 | left. If so, it must be the base register and the | |
9485 | constant must be zero. */ | |
9486 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9487 | { | |
9488 | offset_expr.X_op = O_constant; | |
9489 | offset_expr.X_add_number = 0; | |
9490 | continue; | |
9491 | } | |
252b5132 RH |
9492 | |
9493 | /* If this value won't fit into a 16 bit offset, then go | |
9494 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9495 | code pattern. */ |
5e0116d5 | 9496 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9497 | && (offset_expr.X_op != O_constant |
9498 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9499 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9500 | break; |
9501 | ||
252b5132 RH |
9502 | s = expr_end; |
9503 | continue; | |
9504 | ||
9505 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9506 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9507 | my_getExpression (&offset_expr, s); |
9508 | s = expr_end; | |
9509 | continue; | |
9510 | ||
9511 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9512 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9513 | && imm_expr.X_op == O_constant | |
9514 | && (imm_expr.X_add_number < 0 | |
9515 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9516 | as_bad (_("lui expression not in range 0..65535")); |
9517 | s = expr_end; | |
9518 | continue; | |
9519 | ||
9520 | case 'a': /* 26 bit address */ | |
9521 | my_getExpression (&offset_expr, s); | |
9522 | s = expr_end; | |
f6688943 | 9523 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9524 | continue; |
9525 | ||
9526 | case 'N': /* 3 bit branch condition code */ | |
9527 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
9528 | rtype = RTYPE_CCC; |
9529 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
9530 | rtype |= RTYPE_FCC; | |
9531 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 9532 | break; |
30c378fd CD |
9533 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
9534 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9535 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9536 | && (regno & 1) != 0) | |
9537 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9538 | str, regno); | |
9539 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9540 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9541 | && (regno & 3) != 0) | |
9542 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9543 | str, regno); | |
252b5132 | 9544 | if (*args == 'N') |
bf12938e | 9545 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9546 | else |
bf12938e | 9547 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9548 | continue; |
252b5132 | 9549 | |
156c2f8b NC |
9550 | case 'H': |
9551 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9552 | s += 2; | |
3882b010 | 9553 | if (ISDIGIT (*s)) |
156c2f8b NC |
9554 | { |
9555 | c = 0; | |
9556 | do | |
9557 | { | |
9558 | c *= 10; | |
9559 | c += *s - '0'; | |
9560 | ++s; | |
9561 | } | |
3882b010 | 9562 | while (ISDIGIT (*s)); |
156c2f8b NC |
9563 | } |
9564 | else | |
9565 | c = 8; /* Invalid sel value. */ | |
9566 | ||
9567 | if (c > 7) | |
9568 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9569 | ip->insn_opcode |= c; | |
9570 | continue; | |
9571 | ||
60b63b72 RS |
9572 | case 'e': |
9573 | /* Must be at least one digit. */ | |
9574 | my_getExpression (&imm_expr, s); | |
9575 | check_absolute_expr (ip, &imm_expr); | |
9576 | ||
9577 | if ((unsigned long) imm_expr.X_add_number | |
9578 | > (unsigned long) OP_MASK_VECBYTE) | |
9579 | { | |
9580 | as_bad (_("bad byte vector index (%ld)"), | |
9581 | (long) imm_expr.X_add_number); | |
9582 | imm_expr.X_add_number = 0; | |
9583 | } | |
9584 | ||
bf12938e | 9585 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9586 | imm_expr.X_op = O_absent; |
9587 | s = expr_end; | |
9588 | continue; | |
9589 | ||
9590 | case '%': | |
9591 | my_getExpression (&imm_expr, s); | |
9592 | check_absolute_expr (ip, &imm_expr); | |
9593 | ||
9594 | if ((unsigned long) imm_expr.X_add_number | |
9595 | > (unsigned long) OP_MASK_VECALIGN) | |
9596 | { | |
9597 | as_bad (_("bad byte vector index (%ld)"), | |
9598 | (long) imm_expr.X_add_number); | |
9599 | imm_expr.X_add_number = 0; | |
9600 | } | |
9601 | ||
bf12938e | 9602 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9603 | imm_expr.X_op = O_absent; |
9604 | s = expr_end; | |
9605 | continue; | |
9606 | ||
252b5132 RH |
9607 | default: |
9608 | as_bad (_("bad char = '%c'\n"), *args); | |
9609 | internalError (); | |
9610 | } | |
9611 | break; | |
9612 | } | |
9613 | /* Args don't match. */ | |
9614 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9615 | !strcmp (insn->name, insn[1].name)) | |
9616 | { | |
9617 | ++insn; | |
9618 | s = argsStart; | |
268f6bed | 9619 | insn_error = _("illegal operands"); |
252b5132 RH |
9620 | continue; |
9621 | } | |
268f6bed L |
9622 | if (save_c) |
9623 | *(--s) = save_c; | |
252b5132 RH |
9624 | insn_error = _("illegal operands"); |
9625 | return; | |
9626 | } | |
9627 | } | |
9628 | ||
0499d65b TS |
9629 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9630 | ||
252b5132 RH |
9631 | /* This routine assembles an instruction into its binary format when |
9632 | assembling for the mips16. As a side effect, it sets one of the | |
9633 | global variables imm_reloc or offset_reloc to the type of | |
9634 | relocation to do if one of the operands is an address expression. | |
9635 | It also sets mips16_small and mips16_ext if the user explicitly | |
9636 | requested a small or extended instruction. */ | |
9637 | ||
9638 | static void | |
17a2f251 | 9639 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9640 | { |
9641 | char *s; | |
9642 | const char *args; | |
9643 | struct mips_opcode *insn; | |
9644 | char *argsstart; | |
9645 | unsigned int regno; | |
9646 | unsigned int lastregno = 0; | |
9647 | char *s_reset; | |
d6f16593 | 9648 | size_t i; |
252b5132 RH |
9649 | |
9650 | insn_error = NULL; | |
9651 | ||
b34976b6 AM |
9652 | mips16_small = FALSE; |
9653 | mips16_ext = FALSE; | |
252b5132 | 9654 | |
3882b010 | 9655 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9656 | ; |
9657 | switch (*s) | |
9658 | { | |
9659 | case '\0': | |
9660 | break; | |
9661 | ||
9662 | case ' ': | |
9663 | *s++ = '\0'; | |
9664 | break; | |
9665 | ||
9666 | case '.': | |
9667 | if (s[1] == 't' && s[2] == ' ') | |
9668 | { | |
9669 | *s = '\0'; | |
b34976b6 | 9670 | mips16_small = TRUE; |
252b5132 RH |
9671 | s += 3; |
9672 | break; | |
9673 | } | |
9674 | else if (s[1] == 'e' && s[2] == ' ') | |
9675 | { | |
9676 | *s = '\0'; | |
b34976b6 | 9677 | mips16_ext = TRUE; |
252b5132 RH |
9678 | s += 3; |
9679 | break; | |
9680 | } | |
9681 | /* Fall through. */ | |
9682 | default: | |
9683 | insn_error = _("unknown opcode"); | |
9684 | return; | |
9685 | } | |
9686 | ||
9687 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9688 | mips16_small = TRUE; |
252b5132 RH |
9689 | |
9690 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9691 | { | |
9692 | insn_error = _("unrecognized opcode"); | |
9693 | return; | |
9694 | } | |
9695 | ||
9696 | argsstart = s; | |
9697 | for (;;) | |
9698 | { | |
9b3f89ee TS |
9699 | bfd_boolean ok; |
9700 | ||
252b5132 RH |
9701 | assert (strcmp (insn->name, str) == 0); |
9702 | ||
9b3f89ee TS |
9703 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch)) |
9704 | ok = TRUE; | |
9705 | else | |
9706 | ok = FALSE; | |
9707 | ||
9708 | if (! ok) | |
9709 | { | |
9710 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
9711 | && strcmp (insn->name, insn[1].name) == 0) | |
9712 | { | |
9713 | ++insn; | |
9714 | continue; | |
9715 | } | |
9716 | else | |
9717 | { | |
9718 | if (!insn_error) | |
9719 | { | |
9720 | static char buf[100]; | |
9721 | sprintf (buf, | |
9722 | _("opcode not supported on this processor: %s (%s)"), | |
9723 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
9724 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
9725 | insn_error = buf; | |
9726 | } | |
9727 | return; | |
9728 | } | |
9729 | } | |
9730 | ||
1e915849 | 9731 | create_insn (ip, insn); |
252b5132 | 9732 | imm_expr.X_op = O_absent; |
f6688943 TS |
9733 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9734 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9735 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9736 | imm2_expr.X_op = O_absent; |
252b5132 | 9737 | offset_expr.X_op = O_absent; |
f6688943 TS |
9738 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9739 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9740 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9741 | for (args = insn->args; 1; ++args) |
9742 | { | |
9743 | int c; | |
9744 | ||
9745 | if (*s == ' ') | |
9746 | ++s; | |
9747 | ||
9748 | /* In this switch statement we call break if we did not find | |
9749 | a match, continue if we did find a match, or return if we | |
9750 | are done. */ | |
9751 | ||
9752 | c = *args; | |
9753 | switch (c) | |
9754 | { | |
9755 | case '\0': | |
9756 | if (*s == '\0') | |
9757 | { | |
9758 | /* Stuff the immediate value in now, if we can. */ | |
9759 | if (imm_expr.X_op == O_constant | |
f6688943 | 9760 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9761 | && insn->pinfo != INSN_MACRO) |
9762 | { | |
d6f16593 MR |
9763 | valueT tmp; |
9764 | ||
9765 | switch (*offset_reloc) | |
9766 | { | |
9767 | case BFD_RELOC_MIPS16_HI16_S: | |
9768 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9769 | break; | |
9770 | ||
9771 | case BFD_RELOC_MIPS16_HI16: | |
9772 | tmp = imm_expr.X_add_number >> 16; | |
9773 | break; | |
9774 | ||
9775 | case BFD_RELOC_MIPS16_LO16: | |
9776 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9777 | - 0x8000; | |
9778 | break; | |
9779 | ||
9780 | case BFD_RELOC_UNUSED: | |
9781 | tmp = imm_expr.X_add_number; | |
9782 | break; | |
9783 | ||
9784 | default: | |
9785 | internalError (); | |
9786 | } | |
9787 | *offset_reloc = BFD_RELOC_UNUSED; | |
9788 | ||
c4e7957c | 9789 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9790 | tmp, TRUE, mips16_small, |
252b5132 RH |
9791 | mips16_ext, &ip->insn_opcode, |
9792 | &ip->use_extend, &ip->extend); | |
9793 | imm_expr.X_op = O_absent; | |
f6688943 | 9794 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9795 | } |
9796 | ||
9797 | return; | |
9798 | } | |
9799 | break; | |
9800 | ||
9801 | case ',': | |
9802 | if (*s++ == c) | |
9803 | continue; | |
9804 | s--; | |
9805 | switch (*++args) | |
9806 | { | |
9807 | case 'v': | |
bf12938e | 9808 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9809 | continue; |
9810 | case 'w': | |
bf12938e | 9811 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9812 | continue; |
9813 | } | |
9814 | break; | |
9815 | ||
9816 | case '(': | |
9817 | case ')': | |
9818 | if (*s++ == c) | |
9819 | continue; | |
9820 | break; | |
9821 | ||
9822 | case 'v': | |
9823 | case 'w': | |
9824 | if (s[0] != '$') | |
9825 | { | |
9826 | if (c == 'v') | |
bf12938e | 9827 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9828 | else |
bf12938e | 9829 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9830 | ++args; |
9831 | continue; | |
9832 | } | |
9833 | /* Fall through. */ | |
9834 | case 'x': | |
9835 | case 'y': | |
9836 | case 'z': | |
9837 | case 'Z': | |
9838 | case '0': | |
9839 | case 'S': | |
9840 | case 'R': | |
9841 | case 'X': | |
9842 | case 'Y': | |
707bfff6 TS |
9843 | s_reset = s; |
9844 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 9845 | { |
707bfff6 | 9846 | if (c == 'v' || c == 'w') |
85b51719 | 9847 | { |
707bfff6 | 9848 | if (c == 'v') |
a9e24354 | 9849 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 9850 | else |
a9e24354 | 9851 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
9852 | ++args; |
9853 | continue; | |
85b51719 | 9854 | } |
707bfff6 | 9855 | break; |
252b5132 RH |
9856 | } |
9857 | ||
9858 | if (*s == ' ') | |
9859 | ++s; | |
9860 | if (args[1] != *s) | |
9861 | { | |
9862 | if (c == 'v' || c == 'w') | |
9863 | { | |
9864 | regno = mips16_to_32_reg_map[lastregno]; | |
9865 | s = s_reset; | |
f9419b05 | 9866 | ++args; |
252b5132 RH |
9867 | } |
9868 | } | |
9869 | ||
9870 | switch (c) | |
9871 | { | |
9872 | case 'x': | |
9873 | case 'y': | |
9874 | case 'z': | |
9875 | case 'v': | |
9876 | case 'w': | |
9877 | case 'Z': | |
9878 | regno = mips32_to_16_reg_map[regno]; | |
9879 | break; | |
9880 | ||
9881 | case '0': | |
9882 | if (regno != 0) | |
9883 | regno = ILLEGAL_REG; | |
9884 | break; | |
9885 | ||
9886 | case 'S': | |
9887 | if (regno != SP) | |
9888 | regno = ILLEGAL_REG; | |
9889 | break; | |
9890 | ||
9891 | case 'R': | |
9892 | if (regno != RA) | |
9893 | regno = ILLEGAL_REG; | |
9894 | break; | |
9895 | ||
9896 | case 'X': | |
9897 | case 'Y': | |
9898 | if (regno == AT && ! mips_opts.noat) | |
9899 | as_warn (_("used $at without \".set noat\"")); | |
9900 | break; | |
9901 | ||
9902 | default: | |
9903 | internalError (); | |
9904 | } | |
9905 | ||
9906 | if (regno == ILLEGAL_REG) | |
9907 | break; | |
9908 | ||
9909 | switch (c) | |
9910 | { | |
9911 | case 'x': | |
9912 | case 'v': | |
bf12938e | 9913 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9914 | break; |
9915 | case 'y': | |
9916 | case 'w': | |
bf12938e | 9917 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9918 | break; |
9919 | case 'z': | |
bf12938e | 9920 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9921 | break; |
9922 | case 'Z': | |
bf12938e | 9923 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9924 | case '0': |
9925 | case 'S': | |
9926 | case 'R': | |
9927 | break; | |
9928 | case 'X': | |
bf12938e | 9929 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9930 | break; |
9931 | case 'Y': | |
9932 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9933 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9934 | break; |
9935 | default: | |
9936 | internalError (); | |
9937 | } | |
9938 | ||
9939 | lastregno = regno; | |
9940 | continue; | |
9941 | ||
9942 | case 'P': | |
9943 | if (strncmp (s, "$pc", 3) == 0) | |
9944 | { | |
9945 | s += 3; | |
9946 | continue; | |
9947 | } | |
9948 | break; | |
9949 | ||
252b5132 RH |
9950 | case '5': |
9951 | case 'H': | |
9952 | case 'W': | |
9953 | case 'D': | |
9954 | case 'j': | |
252b5132 RH |
9955 | case 'V': |
9956 | case 'C': | |
9957 | case 'U': | |
9958 | case 'k': | |
9959 | case 'K': | |
d6f16593 MR |
9960 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9961 | if (i > 0) | |
252b5132 | 9962 | { |
d6f16593 | 9963 | if (imm_expr.X_op != O_constant) |
252b5132 | 9964 | { |
b34976b6 | 9965 | mips16_ext = TRUE; |
b34976b6 | 9966 | ip->use_extend = TRUE; |
252b5132 | 9967 | ip->extend = 0; |
252b5132 | 9968 | } |
d6f16593 MR |
9969 | else |
9970 | { | |
9971 | /* We need to relax this instruction. */ | |
9972 | *offset_reloc = *imm_reloc; | |
9973 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9974 | } | |
9975 | s = expr_end; | |
9976 | continue; | |
252b5132 | 9977 | } |
d6f16593 MR |
9978 | *imm_reloc = BFD_RELOC_UNUSED; |
9979 | /* Fall through. */ | |
9980 | case '<': | |
9981 | case '>': | |
9982 | case '[': | |
9983 | case ']': | |
9984 | case '4': | |
9985 | case '8': | |
9986 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9987 | if (imm_expr.X_op == O_register) |
9988 | { | |
9989 | /* What we thought was an expression turned out to | |
9990 | be a register. */ | |
9991 | ||
9992 | if (s[0] == '(' && args[1] == '(') | |
9993 | { | |
9994 | /* It looks like the expression was omitted | |
9995 | before a register indirection, which means | |
9996 | that the expression is implicitly zero. We | |
9997 | still set up imm_expr, so that we handle | |
9998 | explicit extensions correctly. */ | |
9999 | imm_expr.X_op = O_constant; | |
10000 | imm_expr.X_add_number = 0; | |
f6688943 | 10001 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10002 | continue; |
10003 | } | |
10004 | ||
10005 | break; | |
10006 | } | |
10007 | ||
10008 | /* We need to relax this instruction. */ | |
f6688943 | 10009 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10010 | s = expr_end; |
10011 | continue; | |
10012 | ||
10013 | case 'p': | |
10014 | case 'q': | |
10015 | case 'A': | |
10016 | case 'B': | |
10017 | case 'E': | |
10018 | /* We use offset_reloc rather than imm_reloc for the PC | |
10019 | relative operands. This lets macros with both | |
10020 | immediate and address operands work correctly. */ | |
10021 | my_getExpression (&offset_expr, s); | |
10022 | ||
10023 | if (offset_expr.X_op == O_register) | |
10024 | break; | |
10025 | ||
10026 | /* We need to relax this instruction. */ | |
f6688943 | 10027 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10028 | s = expr_end; |
10029 | continue; | |
10030 | ||
10031 | case '6': /* break code */ | |
10032 | my_getExpression (&imm_expr, s); | |
10033 | check_absolute_expr (ip, &imm_expr); | |
10034 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10035 | as_warn (_("Invalid value for `%s' (%lu)"), |
10036 | ip->insn_mo->name, | |
10037 | (unsigned long) imm_expr.X_add_number); | |
10038 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10039 | imm_expr.X_op = O_absent; |
10040 | s = expr_end; | |
10041 | continue; | |
10042 | ||
10043 | case 'a': /* 26 bit address */ | |
10044 | my_getExpression (&offset_expr, s); | |
10045 | s = expr_end; | |
f6688943 | 10046 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10047 | ip->insn_opcode <<= 16; |
10048 | continue; | |
10049 | ||
10050 | case 'l': /* register list for entry macro */ | |
10051 | case 'L': /* register list for exit macro */ | |
10052 | { | |
10053 | int mask; | |
10054 | ||
10055 | if (c == 'l') | |
10056 | mask = 0; | |
10057 | else | |
10058 | mask = 7 << 3; | |
10059 | while (*s != '\0') | |
10060 | { | |
707bfff6 | 10061 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10062 | |
10063 | while (*s == ' ' || *s == ',') | |
10064 | ++s; | |
707bfff6 | 10065 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10066 | freg = 0; |
707bfff6 TS |
10067 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10068 | freg = 1; | |
252b5132 RH |
10069 | else |
10070 | { | |
707bfff6 TS |
10071 | as_bad (_("can't parse register list")); |
10072 | break; | |
252b5132 RH |
10073 | } |
10074 | if (*s == ' ') | |
10075 | ++s; | |
10076 | if (*s != '-') | |
10077 | reg2 = reg1; | |
10078 | else | |
10079 | { | |
10080 | ++s; | |
707bfff6 TS |
10081 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10082 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10083 | { |
707bfff6 TS |
10084 | as_bad (_("invalid register list")); |
10085 | break; | |
252b5132 RH |
10086 | } |
10087 | } | |
10088 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10089 | { | |
10090 | mask &= ~ (7 << 3); | |
10091 | mask |= 5 << 3; | |
10092 | } | |
10093 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10094 | { | |
10095 | mask &= ~ (7 << 3); | |
10096 | mask |= 6 << 3; | |
10097 | } | |
10098 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10099 | mask |= (reg2 - 3) << 3; | |
10100 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10101 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10102 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10103 | mask |= 1; |
10104 | else | |
10105 | { | |
10106 | as_bad (_("invalid register list")); | |
10107 | break; | |
10108 | } | |
10109 | } | |
10110 | /* The mask is filled in in the opcode table for the | |
10111 | benefit of the disassembler. We remove it before | |
10112 | applying the actual mask. */ | |
10113 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10114 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10115 | } | |
10116 | continue; | |
10117 | ||
0499d65b TS |
10118 | case 'm': /* Register list for save insn. */ |
10119 | case 'M': /* Register list for restore insn. */ | |
10120 | { | |
10121 | int opcode = 0; | |
10122 | int framesz = 0, seen_framesz = 0; | |
10123 | int args = 0, statics = 0, sregs = 0; | |
10124 | ||
10125 | while (*s != '\0') | |
10126 | { | |
10127 | unsigned int reg1, reg2; | |
10128 | ||
10129 | SKIP_SPACE_TABS (s); | |
10130 | while (*s == ',') | |
10131 | ++s; | |
10132 | SKIP_SPACE_TABS (s); | |
10133 | ||
10134 | my_getExpression (&imm_expr, s); | |
10135 | if (imm_expr.X_op == O_constant) | |
10136 | { | |
10137 | /* Handle the frame size. */ | |
10138 | if (seen_framesz) | |
10139 | { | |
10140 | as_bad (_("more than one frame size in list")); | |
10141 | break; | |
10142 | } | |
10143 | seen_framesz = 1; | |
10144 | framesz = imm_expr.X_add_number; | |
10145 | imm_expr.X_op = O_absent; | |
10146 | s = expr_end; | |
10147 | continue; | |
10148 | } | |
10149 | ||
707bfff6 | 10150 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10151 | { |
10152 | as_bad (_("can't parse register list")); | |
10153 | break; | |
10154 | } | |
0499d65b | 10155 | |
707bfff6 TS |
10156 | while (*s == ' ') |
10157 | ++s; | |
10158 | ||
0499d65b TS |
10159 | if (*s != '-') |
10160 | reg2 = reg1; | |
10161 | else | |
10162 | { | |
10163 | ++s; | |
707bfff6 TS |
10164 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10165 | || reg2 < reg1) | |
0499d65b TS |
10166 | { |
10167 | as_bad (_("can't parse register list")); | |
10168 | break; | |
10169 | } | |
0499d65b TS |
10170 | } |
10171 | ||
10172 | while (reg1 <= reg2) | |
10173 | { | |
10174 | if (reg1 >= 4 && reg1 <= 7) | |
10175 | { | |
10176 | if (c == 'm' && !seen_framesz) | |
10177 | /* args $a0-$a3 */ | |
10178 | args |= 1 << (reg1 - 4); | |
10179 | else | |
10180 | /* statics $a0-$a3 */ | |
10181 | statics |= 1 << (reg1 - 4); | |
10182 | } | |
10183 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10184 | { | |
10185 | /* $s0-$s8 */ | |
10186 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10187 | } | |
10188 | else if (reg1 == 31) | |
10189 | { | |
10190 | /* Add $ra to insn. */ | |
10191 | opcode |= 0x40; | |
10192 | } | |
10193 | else | |
10194 | { | |
10195 | as_bad (_("unexpected register in list")); | |
10196 | break; | |
10197 | } | |
10198 | if (++reg1 == 24) | |
10199 | reg1 = 30; | |
10200 | } | |
10201 | } | |
10202 | ||
10203 | /* Encode args/statics combination. */ | |
10204 | if (args & statics) | |
10205 | as_bad (_("arg/static registers overlap")); | |
10206 | else if (args == 0xf) | |
10207 | /* All $a0-$a3 are args. */ | |
10208 | opcode |= MIPS16_ALL_ARGS << 16; | |
10209 | else if (statics == 0xf) | |
10210 | /* All $a0-$a3 are statics. */ | |
10211 | opcode |= MIPS16_ALL_STATICS << 16; | |
10212 | else | |
10213 | { | |
10214 | int narg = 0, nstat = 0; | |
10215 | ||
10216 | /* Count arg registers. */ | |
10217 | while (args & 0x1) | |
10218 | { | |
10219 | args >>= 1; | |
10220 | narg++; | |
10221 | } | |
10222 | if (args != 0) | |
10223 | as_bad (_("invalid arg register list")); | |
10224 | ||
10225 | /* Count static registers. */ | |
10226 | while (statics & 0x8) | |
10227 | { | |
10228 | statics = (statics << 1) & 0xf; | |
10229 | nstat++; | |
10230 | } | |
10231 | if (statics != 0) | |
10232 | as_bad (_("invalid static register list")); | |
10233 | ||
10234 | /* Encode args/statics. */ | |
10235 | opcode |= ((narg << 2) | nstat) << 16; | |
10236 | } | |
10237 | ||
10238 | /* Encode $s0/$s1. */ | |
10239 | if (sregs & (1 << 0)) /* $s0 */ | |
10240 | opcode |= 0x20; | |
10241 | if (sregs & (1 << 1)) /* $s1 */ | |
10242 | opcode |= 0x10; | |
10243 | sregs >>= 2; | |
10244 | ||
10245 | if (sregs != 0) | |
10246 | { | |
10247 | /* Count regs $s2-$s8. */ | |
10248 | int nsreg = 0; | |
10249 | while (sregs & 1) | |
10250 | { | |
10251 | sregs >>= 1; | |
10252 | nsreg++; | |
10253 | } | |
10254 | if (sregs != 0) | |
10255 | as_bad (_("invalid static register list")); | |
10256 | /* Encode $s2-$s8. */ | |
10257 | opcode |= nsreg << 24; | |
10258 | } | |
10259 | ||
10260 | /* Encode frame size. */ | |
10261 | if (!seen_framesz) | |
10262 | as_bad (_("missing frame size")); | |
10263 | else if ((framesz & 7) != 0 || framesz < 0 | |
10264 | || framesz > 0xff * 8) | |
10265 | as_bad (_("invalid frame size")); | |
10266 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10267 | { | |
10268 | framesz /= 8; | |
10269 | opcode |= (((framesz & 0xf0) << 16) | |
10270 | | (framesz & 0x0f)); | |
10271 | } | |
10272 | ||
10273 | /* Finally build the instruction. */ | |
10274 | if ((opcode >> 16) != 0 || framesz == 0) | |
10275 | { | |
10276 | ip->use_extend = TRUE; | |
10277 | ip->extend = opcode >> 16; | |
10278 | } | |
10279 | ip->insn_opcode |= opcode & 0x7f; | |
10280 | } | |
10281 | continue; | |
10282 | ||
252b5132 RH |
10283 | case 'e': /* extend code */ |
10284 | my_getExpression (&imm_expr, s); | |
10285 | check_absolute_expr (ip, &imm_expr); | |
10286 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10287 | { | |
10288 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10289 | ip->insn_mo->name, | |
10290 | (unsigned long) imm_expr.X_add_number); | |
10291 | imm_expr.X_add_number &= 0x7ff; | |
10292 | } | |
10293 | ip->insn_opcode |= imm_expr.X_add_number; | |
10294 | imm_expr.X_op = O_absent; | |
10295 | s = expr_end; | |
10296 | continue; | |
10297 | ||
10298 | default: | |
10299 | internalError (); | |
10300 | } | |
10301 | break; | |
10302 | } | |
10303 | ||
10304 | /* Args don't match. */ | |
10305 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10306 | strcmp (insn->name, insn[1].name) == 0) | |
10307 | { | |
10308 | ++insn; | |
10309 | s = argsstart; | |
10310 | continue; | |
10311 | } | |
10312 | ||
10313 | insn_error = _("illegal operands"); | |
10314 | ||
10315 | return; | |
10316 | } | |
10317 | } | |
10318 | ||
10319 | /* This structure holds information we know about a mips16 immediate | |
10320 | argument type. */ | |
10321 | ||
e972090a NC |
10322 | struct mips16_immed_operand |
10323 | { | |
252b5132 RH |
10324 | /* The type code used in the argument string in the opcode table. */ |
10325 | int type; | |
10326 | /* The number of bits in the short form of the opcode. */ | |
10327 | int nbits; | |
10328 | /* The number of bits in the extended form of the opcode. */ | |
10329 | int extbits; | |
10330 | /* The amount by which the short form is shifted when it is used; | |
10331 | for example, the sw instruction has a shift count of 2. */ | |
10332 | int shift; | |
10333 | /* The amount by which the short form is shifted when it is stored | |
10334 | into the instruction code. */ | |
10335 | int op_shift; | |
10336 | /* Non-zero if the short form is unsigned. */ | |
10337 | int unsp; | |
10338 | /* Non-zero if the extended form is unsigned. */ | |
10339 | int extu; | |
10340 | /* Non-zero if the value is PC relative. */ | |
10341 | int pcrel; | |
10342 | }; | |
10343 | ||
10344 | /* The mips16 immediate operand types. */ | |
10345 | ||
10346 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10347 | { | |
10348 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10349 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10350 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10351 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10352 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10353 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10354 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10355 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10356 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10357 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10358 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10359 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10360 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10361 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10362 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10363 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10364 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10365 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10366 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10367 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10368 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10369 | }; | |
10370 | ||
10371 | #define MIPS16_NUM_IMMED \ | |
10372 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10373 | ||
10374 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10375 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10376 | whether an extended value is needed; if one is needed, it sets | |
10377 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10378 | If SMALL is true, an unextended opcode was explicitly requested. | |
10379 | If EXT is true, an extended opcode was explicitly requested. If | |
10380 | WARN is true, warn if EXT does not match reality. */ | |
10381 | ||
10382 | static void | |
17a2f251 TS |
10383 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10384 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10385 | unsigned long *insn, bfd_boolean *use_extend, | |
10386 | unsigned short *extend) | |
252b5132 | 10387 | { |
3994f87e | 10388 | const struct mips16_immed_operand *op; |
252b5132 | 10389 | int mintiny, maxtiny; |
b34976b6 | 10390 | bfd_boolean needext; |
252b5132 RH |
10391 | |
10392 | op = mips16_immed_operands; | |
10393 | while (op->type != type) | |
10394 | { | |
10395 | ++op; | |
10396 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10397 | } | |
10398 | ||
10399 | if (op->unsp) | |
10400 | { | |
10401 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10402 | { | |
10403 | mintiny = 1; | |
10404 | maxtiny = 1 << op->nbits; | |
10405 | } | |
10406 | else | |
10407 | { | |
10408 | mintiny = 0; | |
10409 | maxtiny = (1 << op->nbits) - 1; | |
10410 | } | |
10411 | } | |
10412 | else | |
10413 | { | |
10414 | mintiny = - (1 << (op->nbits - 1)); | |
10415 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10416 | } | |
10417 | ||
10418 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10419 | if (type == 'p' || type == 'q') | |
10420 | val /= 2; | |
10421 | ||
10422 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10423 | || val < (mintiny << op->shift) | |
10424 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10425 | needext = TRUE; |
252b5132 | 10426 | else |
b34976b6 | 10427 | needext = FALSE; |
252b5132 RH |
10428 | |
10429 | if (warn && ext && ! needext) | |
beae10d5 KH |
10430 | as_warn_where (file, line, |
10431 | _("extended operand requested but not required")); | |
252b5132 RH |
10432 | if (small && needext) |
10433 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10434 | ||
10435 | if (small || (! ext && ! needext)) | |
10436 | { | |
10437 | int insnval; | |
10438 | ||
b34976b6 | 10439 | *use_extend = FALSE; |
252b5132 RH |
10440 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10441 | insnval <<= op->op_shift; | |
10442 | *insn |= insnval; | |
10443 | } | |
10444 | else | |
10445 | { | |
10446 | long minext, maxext; | |
10447 | int extval; | |
10448 | ||
10449 | if (op->extu) | |
10450 | { | |
10451 | minext = 0; | |
10452 | maxext = (1 << op->extbits) - 1; | |
10453 | } | |
10454 | else | |
10455 | { | |
10456 | minext = - (1 << (op->extbits - 1)); | |
10457 | maxext = (1 << (op->extbits - 1)) - 1; | |
10458 | } | |
10459 | if (val < minext || val > maxext) | |
10460 | as_bad_where (file, line, | |
10461 | _("operand value out of range for instruction")); | |
10462 | ||
b34976b6 | 10463 | *use_extend = TRUE; |
252b5132 RH |
10464 | if (op->extbits == 16) |
10465 | { | |
10466 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10467 | val &= 0x1f; | |
10468 | } | |
10469 | else if (op->extbits == 15) | |
10470 | { | |
10471 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10472 | val &= 0xf; | |
10473 | } | |
10474 | else | |
10475 | { | |
10476 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10477 | val = 0; | |
10478 | } | |
10479 | ||
10480 | *extend = (unsigned short) extval; | |
10481 | *insn |= val; | |
10482 | } | |
10483 | } | |
10484 | \f | |
d6f16593 | 10485 | struct percent_op_match |
ad8d3bb3 | 10486 | { |
5e0116d5 RS |
10487 | const char *str; |
10488 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10489 | }; |
10490 | ||
10491 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10492 | { |
5e0116d5 | 10493 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10494 | #ifdef OBJ_ELF |
5e0116d5 RS |
10495 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10496 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10497 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10498 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10499 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10500 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10501 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10502 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10503 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10504 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10505 | {"%half", BFD_RELOC_16}, | |
10506 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10507 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10508 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10509 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10510 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10511 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10512 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10513 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10514 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10515 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10516 | #endif |
5e0116d5 | 10517 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10518 | }; |
10519 | ||
d6f16593 MR |
10520 | static const struct percent_op_match mips16_percent_op[] = |
10521 | { | |
10522 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10523 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10524 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10525 | }; | |
10526 | ||
252b5132 | 10527 | |
5e0116d5 RS |
10528 | /* Return true if *STR points to a relocation operator. When returning true, |
10529 | move *STR over the operator and store its relocation code in *RELOC. | |
10530 | Leave both *STR and *RELOC alone when returning false. */ | |
10531 | ||
10532 | static bfd_boolean | |
17a2f251 | 10533 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10534 | { |
d6f16593 MR |
10535 | const struct percent_op_match *percent_op; |
10536 | size_t limit, i; | |
10537 | ||
10538 | if (mips_opts.mips16) | |
10539 | { | |
10540 | percent_op = mips16_percent_op; | |
10541 | limit = ARRAY_SIZE (mips16_percent_op); | |
10542 | } | |
10543 | else | |
10544 | { | |
10545 | percent_op = mips_percent_op; | |
10546 | limit = ARRAY_SIZE (mips_percent_op); | |
10547 | } | |
76b3015f | 10548 | |
d6f16593 | 10549 | for (i = 0; i < limit; i++) |
5e0116d5 | 10550 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10551 | { |
3f98094e DJ |
10552 | int len = strlen (percent_op[i].str); |
10553 | ||
10554 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10555 | continue; | |
10556 | ||
5e0116d5 RS |
10557 | *str += strlen (percent_op[i].str); |
10558 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10559 | |
5e0116d5 RS |
10560 | /* Check whether the output BFD supports this relocation. |
10561 | If not, issue an error and fall back on something safe. */ | |
10562 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10563 | { |
5e0116d5 RS |
10564 | as_bad ("relocation %s isn't supported by the current ABI", |
10565 | percent_op[i].str); | |
01a3f561 | 10566 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10567 | } |
5e0116d5 | 10568 | return TRUE; |
394f9b3a | 10569 | } |
5e0116d5 | 10570 | return FALSE; |
394f9b3a | 10571 | } |
ad8d3bb3 | 10572 | |
ad8d3bb3 | 10573 | |
5e0116d5 RS |
10574 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10575 | expression in *EP and the relocations in the array starting | |
10576 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10577 | |
01a3f561 | 10578 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10579 | |
5e0116d5 | 10580 | static size_t |
17a2f251 TS |
10581 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10582 | char *str) | |
ad8d3bb3 | 10583 | { |
5e0116d5 RS |
10584 | bfd_reloc_code_real_type reversed_reloc[3]; |
10585 | size_t reloc_index, i; | |
09b8f35a RS |
10586 | int crux_depth, str_depth; |
10587 | char *crux; | |
5e0116d5 RS |
10588 | |
10589 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10590 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10591 | of the main expression and with CRUX_DEPTH containing the number | |
10592 | of open brackets at that point. */ | |
10593 | reloc_index = -1; | |
10594 | str_depth = 0; | |
10595 | do | |
fb1b3232 | 10596 | { |
09b8f35a RS |
10597 | reloc_index++; |
10598 | crux = str; | |
10599 | crux_depth = str_depth; | |
10600 | ||
10601 | /* Skip over whitespace and brackets, keeping count of the number | |
10602 | of brackets. */ | |
10603 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10604 | if (*str++ == '(') | |
10605 | str_depth++; | |
5e0116d5 | 10606 | } |
09b8f35a RS |
10607 | while (*str == '%' |
10608 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10609 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10610 | |
09b8f35a | 10611 | my_getExpression (ep, crux); |
5e0116d5 | 10612 | str = expr_end; |
394f9b3a | 10613 | |
5e0116d5 | 10614 | /* Match every open bracket. */ |
09b8f35a | 10615 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10616 | if (*str++ == ')') |
09b8f35a | 10617 | crux_depth--; |
394f9b3a | 10618 | |
09b8f35a | 10619 | if (crux_depth > 0) |
5e0116d5 | 10620 | as_bad ("unclosed '('"); |
394f9b3a | 10621 | |
5e0116d5 | 10622 | expr_end = str; |
252b5132 | 10623 | |
01a3f561 | 10624 | if (reloc_index != 0) |
64bdfcaf RS |
10625 | { |
10626 | prev_reloc_op_frag = frag_now; | |
10627 | for (i = 0; i < reloc_index; i++) | |
10628 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10629 | } | |
fb1b3232 | 10630 | |
5e0116d5 | 10631 | return reloc_index; |
252b5132 RH |
10632 | } |
10633 | ||
10634 | static void | |
17a2f251 | 10635 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10636 | { |
10637 | char *save_in; | |
98aa84af | 10638 | valueT val; |
252b5132 RH |
10639 | |
10640 | save_in = input_line_pointer; | |
10641 | input_line_pointer = str; | |
10642 | expression (ep); | |
10643 | expr_end = input_line_pointer; | |
10644 | input_line_pointer = save_in; | |
10645 | ||
10646 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10647 | then we bump the value of the symbol by 1 since that is how other | |
10648 | text symbols are handled. We don't bother to handle complex | |
10649 | expressions, just `.' plus or minus a constant. */ | |
10650 | if (mips_opts.mips16 | |
10651 | && ep->X_op == O_symbol | |
10652 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10653 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10654 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10655 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10656 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10657 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10658 | } |
10659 | ||
10660 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10661 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10662 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10663 | returned, or NULL on OK. */ |
10664 | ||
10665 | char * | |
17a2f251 | 10666 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10667 | { |
10668 | int prec; | |
10669 | LITTLENUM_TYPE words[4]; | |
10670 | char *t; | |
10671 | int i; | |
10672 | ||
10673 | switch (type) | |
10674 | { | |
10675 | case 'f': | |
10676 | prec = 2; | |
10677 | break; | |
10678 | ||
10679 | case 'd': | |
10680 | prec = 4; | |
10681 | break; | |
10682 | ||
10683 | default: | |
10684 | *sizeP = 0; | |
10685 | return _("bad call to md_atof"); | |
10686 | } | |
10687 | ||
10688 | t = atof_ieee (input_line_pointer, type, words); | |
10689 | if (t) | |
10690 | input_line_pointer = t; | |
10691 | ||
10692 | *sizeP = prec * 2; | |
10693 | ||
10694 | if (! target_big_endian) | |
10695 | { | |
10696 | for (i = prec - 1; i >= 0; i--) | |
10697 | { | |
17a2f251 | 10698 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10699 | litP += 2; |
10700 | } | |
10701 | } | |
10702 | else | |
10703 | { | |
10704 | for (i = 0; i < prec; i++) | |
10705 | { | |
17a2f251 | 10706 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10707 | litP += 2; |
10708 | } | |
10709 | } | |
bdaaa2e1 | 10710 | |
252b5132 RH |
10711 | return NULL; |
10712 | } | |
10713 | ||
10714 | void | |
17a2f251 | 10715 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10716 | { |
10717 | if (target_big_endian) | |
10718 | number_to_chars_bigendian (buf, val, n); | |
10719 | else | |
10720 | number_to_chars_littleendian (buf, val, n); | |
10721 | } | |
10722 | \f | |
ae948b86 | 10723 | #ifdef OBJ_ELF |
e013f690 TS |
10724 | static int support_64bit_objects(void) |
10725 | { | |
10726 | const char **list, **l; | |
aa3d8fdf | 10727 | int yes; |
e013f690 TS |
10728 | |
10729 | list = bfd_target_list (); | |
10730 | for (l = list; *l != NULL; l++) | |
10731 | #ifdef TE_TMIPS | |
10732 | /* This is traditional mips */ | |
10733 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10734 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10735 | #else | |
10736 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10737 | || strcmp (*l, "elf64-littlemips") == 0) | |
10738 | #endif | |
10739 | break; | |
aa3d8fdf | 10740 | yes = (*l != NULL); |
e013f690 | 10741 | free (list); |
aa3d8fdf | 10742 | return yes; |
e013f690 | 10743 | } |
ae948b86 | 10744 | #endif /* OBJ_ELF */ |
e013f690 | 10745 | |
78849248 | 10746 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10747 | |
e972090a NC |
10748 | struct option md_longopts[] = |
10749 | { | |
f9b4148d CD |
10750 | /* Options which specify architecture. */ |
10751 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10752 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10753 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10754 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10755 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10756 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10757 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10758 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10759 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10760 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10761 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10762 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10763 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10764 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10765 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10766 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10767 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10768 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10769 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10770 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10771 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10772 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10773 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10774 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10775 | |
10776 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10777 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10778 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10779 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10780 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10781 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10782 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10783 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10784 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10785 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10786 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10787 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10788 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10789 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10790 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10791 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10792 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10793 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10794 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10795 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10796 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10797 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
10798 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
10799 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
10800 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
10801 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
f9b4148d CD |
10802 | |
10803 | /* Old-style architecture options. Don't add more of these. */ | |
e16bfa71 | 10804 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12) |
f9b4148d CD |
10805 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10806 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10807 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10808 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10809 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10810 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10811 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10812 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10813 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10814 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10815 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10816 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10817 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10818 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10819 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10820 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10821 | ||
10822 | /* Options which enable bug fixes. */ | |
10823 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10824 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10825 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10826 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10827 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10828 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10829 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10830 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10831 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10832 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10833 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10834 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10835 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10836 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10837 | |
10838 | /* Miscellaneous options. */ | |
7d8e00cf | 10839 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10840 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10841 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10842 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10843 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10844 | {"break", no_argument, NULL, OPTION_BREAK}, |
10845 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10846 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10847 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10848 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10849 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10850 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10851 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10852 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10853 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10854 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10855 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10856 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10857 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10858 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10859 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10860 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10861 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10862 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10863 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10864 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10865 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10866 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10867 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10868 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10869 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10870 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10871 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10872 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10873 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10874 | |
10875 | /* ELF-specific options. */ | |
156c2f8b | 10876 | #ifdef OBJ_ELF |
aed1a261 | 10877 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10878 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10879 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10880 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10881 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10882 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10883 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10884 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10885 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10886 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10887 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10888 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10889 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10890 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10891 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10892 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10893 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10894 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10895 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10896 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10897 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10898 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10899 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10900 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
10901 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
10902 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 10903 | #endif /* OBJ_ELF */ |
f9b4148d | 10904 | |
252b5132 RH |
10905 | {NULL, no_argument, NULL, 0} |
10906 | }; | |
156c2f8b | 10907 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10908 | |
316f5878 RS |
10909 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10910 | NEW_VALUE. Warn if another value was already specified. Note: | |
10911 | we have to defer parsing the -march and -mtune arguments in order | |
10912 | to handle 'from-abi' correctly, since the ABI might be specified | |
10913 | in a later argument. */ | |
10914 | ||
10915 | static void | |
17a2f251 | 10916 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10917 | { |
10918 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10919 | as_warn (_("A different %s was already specified, is now %s"), | |
10920 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10921 | new_value); | |
10922 | ||
10923 | *string_ptr = new_value; | |
10924 | } | |
10925 | ||
252b5132 | 10926 | int |
17a2f251 | 10927 | md_parse_option (int c, char *arg) |
252b5132 RH |
10928 | { |
10929 | switch (c) | |
10930 | { | |
119d663a NC |
10931 | case OPTION_CONSTRUCT_FLOATS: |
10932 | mips_disable_float_construction = 0; | |
10933 | break; | |
bdaaa2e1 | 10934 | |
119d663a NC |
10935 | case OPTION_NO_CONSTRUCT_FLOATS: |
10936 | mips_disable_float_construction = 1; | |
10937 | break; | |
bdaaa2e1 | 10938 | |
252b5132 RH |
10939 | case OPTION_TRAP: |
10940 | mips_trap = 1; | |
10941 | break; | |
10942 | ||
10943 | case OPTION_BREAK: | |
10944 | mips_trap = 0; | |
10945 | break; | |
10946 | ||
10947 | case OPTION_EB: | |
10948 | target_big_endian = 1; | |
10949 | break; | |
10950 | ||
10951 | case OPTION_EL: | |
10952 | target_big_endian = 0; | |
10953 | break; | |
10954 | ||
10955 | case 'O': | |
10956 | if (arg && arg[1] == '0') | |
10957 | mips_optimize = 1; | |
10958 | else | |
10959 | mips_optimize = 2; | |
10960 | break; | |
10961 | ||
10962 | case 'g': | |
10963 | if (arg == NULL) | |
10964 | mips_debug = 2; | |
10965 | else | |
10966 | mips_debug = atoi (arg); | |
10967 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10968 | optimizations which limit full symbolic debugging. We take | |
10969 | that to be equivalent to -O0. */ | |
10970 | if (mips_debug == 2) | |
10971 | mips_optimize = 1; | |
10972 | break; | |
10973 | ||
10974 | case OPTION_MIPS1: | |
316f5878 | 10975 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10976 | break; |
10977 | ||
10978 | case OPTION_MIPS2: | |
316f5878 | 10979 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10980 | break; |
10981 | ||
10982 | case OPTION_MIPS3: | |
316f5878 | 10983 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10984 | break; |
10985 | ||
10986 | case OPTION_MIPS4: | |
316f5878 | 10987 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10988 | break; |
10989 | ||
84ea6cf2 | 10990 | case OPTION_MIPS5: |
316f5878 | 10991 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10992 | break; |
10993 | ||
e7af610e | 10994 | case OPTION_MIPS32: |
316f5878 | 10995 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10996 | break; |
10997 | ||
af7ee8bf CD |
10998 | case OPTION_MIPS32R2: |
10999 | file_mips_isa = ISA_MIPS32R2; | |
11000 | break; | |
11001 | ||
5f74bc13 CD |
11002 | case OPTION_MIPS64R2: |
11003 | file_mips_isa = ISA_MIPS64R2; | |
11004 | break; | |
11005 | ||
84ea6cf2 | 11006 | case OPTION_MIPS64: |
316f5878 | 11007 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11008 | break; |
11009 | ||
ec68c924 | 11010 | case OPTION_MTUNE: |
316f5878 RS |
11011 | mips_set_option_string (&mips_tune_string, arg); |
11012 | break; | |
ec68c924 | 11013 | |
316f5878 RS |
11014 | case OPTION_MARCH: |
11015 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11016 | break; |
11017 | ||
11018 | case OPTION_M4650: | |
316f5878 RS |
11019 | mips_set_option_string (&mips_arch_string, "4650"); |
11020 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11021 | break; |
11022 | ||
11023 | case OPTION_NO_M4650: | |
11024 | break; | |
11025 | ||
11026 | case OPTION_M4010: | |
316f5878 RS |
11027 | mips_set_option_string (&mips_arch_string, "4010"); |
11028 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11029 | break; |
11030 | ||
11031 | case OPTION_NO_M4010: | |
11032 | break; | |
11033 | ||
11034 | case OPTION_M4100: | |
316f5878 RS |
11035 | mips_set_option_string (&mips_arch_string, "4100"); |
11036 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11037 | break; |
11038 | ||
11039 | case OPTION_NO_M4100: | |
11040 | break; | |
11041 | ||
252b5132 | 11042 | case OPTION_M3900: |
316f5878 RS |
11043 | mips_set_option_string (&mips_arch_string, "3900"); |
11044 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11045 | break; |
bdaaa2e1 | 11046 | |
252b5132 RH |
11047 | case OPTION_NO_M3900: |
11048 | break; | |
11049 | ||
deec1734 CD |
11050 | case OPTION_MDMX: |
11051 | mips_opts.ase_mdmx = 1; | |
11052 | break; | |
11053 | ||
11054 | case OPTION_NO_MDMX: | |
11055 | mips_opts.ase_mdmx = 0; | |
11056 | break; | |
11057 | ||
74cd071d CF |
11058 | case OPTION_DSP: |
11059 | mips_opts.ase_dsp = 1; | |
11060 | break; | |
11061 | ||
11062 | case OPTION_NO_DSP: | |
11063 | mips_opts.ase_dsp = 0; | |
11064 | break; | |
11065 | ||
ef2e4d86 CF |
11066 | case OPTION_MT: |
11067 | mips_opts.ase_mt = 1; | |
11068 | break; | |
11069 | ||
11070 | case OPTION_NO_MT: | |
11071 | mips_opts.ase_mt = 0; | |
11072 | break; | |
11073 | ||
252b5132 RH |
11074 | case OPTION_MIPS16: |
11075 | mips_opts.mips16 = 1; | |
7d10b47d | 11076 | mips_no_prev_insn (); |
252b5132 RH |
11077 | break; |
11078 | ||
11079 | case OPTION_NO_MIPS16: | |
11080 | mips_opts.mips16 = 0; | |
7d10b47d | 11081 | mips_no_prev_insn (); |
252b5132 RH |
11082 | break; |
11083 | ||
1f25f5d3 CD |
11084 | case OPTION_MIPS3D: |
11085 | mips_opts.ase_mips3d = 1; | |
11086 | break; | |
11087 | ||
11088 | case OPTION_NO_MIPS3D: | |
11089 | mips_opts.ase_mips3d = 0; | |
11090 | break; | |
11091 | ||
e16bfa71 TS |
11092 | case OPTION_SMARTMIPS: |
11093 | mips_opts.ase_smartmips = 1; | |
11094 | break; | |
11095 | ||
11096 | case OPTION_NO_SMARTMIPS: | |
11097 | mips_opts.ase_smartmips = 0; | |
11098 | break; | |
11099 | ||
d766e8ec RS |
11100 | case OPTION_FIX_VR4120: |
11101 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11102 | break; |
11103 | ||
d766e8ec RS |
11104 | case OPTION_NO_FIX_VR4120: |
11105 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11106 | break; |
11107 | ||
7d8e00cf RS |
11108 | case OPTION_FIX_VR4130: |
11109 | mips_fix_vr4130 = 1; | |
11110 | break; | |
11111 | ||
11112 | case OPTION_NO_FIX_VR4130: | |
11113 | mips_fix_vr4130 = 0; | |
11114 | break; | |
11115 | ||
4a6a3df4 AO |
11116 | case OPTION_RELAX_BRANCH: |
11117 | mips_relax_branch = 1; | |
11118 | break; | |
11119 | ||
11120 | case OPTION_NO_RELAX_BRANCH: | |
11121 | mips_relax_branch = 0; | |
11122 | break; | |
11123 | ||
aa6975fb ILT |
11124 | case OPTION_MSHARED: |
11125 | mips_in_shared = TRUE; | |
11126 | break; | |
11127 | ||
11128 | case OPTION_MNO_SHARED: | |
11129 | mips_in_shared = FALSE; | |
11130 | break; | |
11131 | ||
aed1a261 RS |
11132 | case OPTION_MSYM32: |
11133 | mips_opts.sym32 = TRUE; | |
11134 | break; | |
11135 | ||
11136 | case OPTION_MNO_SYM32: | |
11137 | mips_opts.sym32 = FALSE; | |
11138 | break; | |
11139 | ||
0f074f60 | 11140 | #ifdef OBJ_ELF |
252b5132 RH |
11141 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11142 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11143 | intended to be compatible with Irix 5. */ | |
11144 | case OPTION_CALL_SHARED: | |
11145 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11146 | { | |
11147 | as_bad (_("-call_shared is supported only for ELF format")); | |
11148 | return 0; | |
11149 | } | |
11150 | mips_pic = SVR4_PIC; | |
143d77c5 | 11151 | mips_abicalls = TRUE; |
252b5132 RH |
11152 | break; |
11153 | ||
11154 | case OPTION_NON_SHARED: | |
11155 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11156 | { | |
11157 | as_bad (_("-non_shared is supported only for ELF format")); | |
11158 | return 0; | |
11159 | } | |
11160 | mips_pic = NO_PIC; | |
143d77c5 | 11161 | mips_abicalls = FALSE; |
252b5132 RH |
11162 | break; |
11163 | ||
44075ae2 TS |
11164 | /* The -xgot option tells the assembler to use 32 bit offsets |
11165 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11166 | compatibility. */ |
11167 | case OPTION_XGOT: | |
11168 | mips_big_got = 1; | |
11169 | break; | |
0f074f60 | 11170 | #endif /* OBJ_ELF */ |
252b5132 RH |
11171 | |
11172 | case 'G': | |
6caf9ef4 TS |
11173 | g_switch_value = atoi (arg); |
11174 | g_switch_seen = 1; | |
252b5132 RH |
11175 | break; |
11176 | ||
0f074f60 | 11177 | #ifdef OBJ_ELF |
34ba82a8 TS |
11178 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11179 | and -mabi=64. */ | |
252b5132 | 11180 | case OPTION_32: |
34ba82a8 TS |
11181 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11182 | { | |
11183 | as_bad (_("-32 is supported for ELF format only")); | |
11184 | return 0; | |
11185 | } | |
316f5878 | 11186 | mips_abi = O32_ABI; |
252b5132 RH |
11187 | break; |
11188 | ||
e013f690 | 11189 | case OPTION_N32: |
34ba82a8 TS |
11190 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11191 | { | |
11192 | as_bad (_("-n32 is supported for ELF format only")); | |
11193 | return 0; | |
11194 | } | |
316f5878 | 11195 | mips_abi = N32_ABI; |
e013f690 | 11196 | break; |
252b5132 | 11197 | |
e013f690 | 11198 | case OPTION_64: |
34ba82a8 TS |
11199 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11200 | { | |
11201 | as_bad (_("-64 is supported for ELF format only")); | |
11202 | return 0; | |
11203 | } | |
316f5878 | 11204 | mips_abi = N64_ABI; |
e013f690 TS |
11205 | if (! support_64bit_objects()) |
11206 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 11207 | break; |
ae948b86 | 11208 | #endif /* OBJ_ELF */ |
252b5132 | 11209 | |
c97ef257 | 11210 | case OPTION_GP32: |
a325df1d | 11211 | file_mips_gp32 = 1; |
c97ef257 AH |
11212 | break; |
11213 | ||
11214 | case OPTION_GP64: | |
a325df1d | 11215 | file_mips_gp32 = 0; |
c97ef257 | 11216 | break; |
252b5132 | 11217 | |
ca4e0257 | 11218 | case OPTION_FP32: |
a325df1d | 11219 | file_mips_fp32 = 1; |
316f5878 RS |
11220 | break; |
11221 | ||
11222 | case OPTION_FP64: | |
11223 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11224 | break; |
11225 | ||
ae948b86 | 11226 | #ifdef OBJ_ELF |
252b5132 | 11227 | case OPTION_MABI: |
34ba82a8 TS |
11228 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11229 | { | |
11230 | as_bad (_("-mabi is supported for ELF format only")); | |
11231 | return 0; | |
11232 | } | |
e013f690 | 11233 | if (strcmp (arg, "32") == 0) |
316f5878 | 11234 | mips_abi = O32_ABI; |
e013f690 | 11235 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11236 | mips_abi = O64_ABI; |
e013f690 | 11237 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11238 | mips_abi = N32_ABI; |
e013f690 TS |
11239 | else if (strcmp (arg, "64") == 0) |
11240 | { | |
316f5878 | 11241 | mips_abi = N64_ABI; |
e013f690 TS |
11242 | if (! support_64bit_objects()) |
11243 | as_fatal (_("No compiled in support for 64 bit object file " | |
11244 | "format")); | |
11245 | } | |
11246 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11247 | mips_abi = EABI_ABI; |
e013f690 | 11248 | else |
da0e507f TS |
11249 | { |
11250 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11251 | return 0; | |
11252 | } | |
252b5132 | 11253 | break; |
e013f690 | 11254 | #endif /* OBJ_ELF */ |
252b5132 | 11255 | |
6b76fefe | 11256 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11257 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11258 | break; |
11259 | ||
9ee72ff1 | 11260 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11261 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11262 | break; |
11263 | ||
ecb4347a DJ |
11264 | #ifdef OBJ_ELF |
11265 | case OPTION_MDEBUG: | |
b34976b6 | 11266 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11267 | break; |
11268 | ||
11269 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11270 | mips_flag_mdebug = FALSE; |
ecb4347a | 11271 | break; |
dcd410fe RO |
11272 | |
11273 | case OPTION_PDR: | |
11274 | mips_flag_pdr = TRUE; | |
11275 | break; | |
11276 | ||
11277 | case OPTION_NO_PDR: | |
11278 | mips_flag_pdr = FALSE; | |
11279 | break; | |
0a44bf69 RS |
11280 | |
11281 | case OPTION_MVXWORKS_PIC: | |
11282 | mips_pic = VXWORKS_PIC; | |
11283 | break; | |
ecb4347a DJ |
11284 | #endif /* OBJ_ELF */ |
11285 | ||
252b5132 RH |
11286 | default: |
11287 | return 0; | |
11288 | } | |
11289 | ||
11290 | return 1; | |
11291 | } | |
316f5878 RS |
11292 | \f |
11293 | /* Set up globals to generate code for the ISA or processor | |
11294 | described by INFO. */ | |
252b5132 | 11295 | |
252b5132 | 11296 | static void |
17a2f251 | 11297 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11298 | { |
316f5878 | 11299 | if (info != 0) |
252b5132 | 11300 | { |
fef14a42 TS |
11301 | file_mips_arch = info->cpu; |
11302 | mips_opts.arch = info->cpu; | |
316f5878 | 11303 | mips_opts.isa = info->isa; |
252b5132 | 11304 | } |
252b5132 RH |
11305 | } |
11306 | ||
252b5132 | 11307 | |
316f5878 | 11308 | /* Likewise for tuning. */ |
252b5132 | 11309 | |
316f5878 | 11310 | static void |
17a2f251 | 11311 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11312 | { |
11313 | if (info != 0) | |
fef14a42 | 11314 | mips_tune = info->cpu; |
316f5878 | 11315 | } |
80cc45a5 | 11316 | |
34ba82a8 | 11317 | |
252b5132 | 11318 | void |
17a2f251 | 11319 | mips_after_parse_args (void) |
e9670677 | 11320 | { |
fef14a42 TS |
11321 | const struct mips_cpu_info *arch_info = 0; |
11322 | const struct mips_cpu_info *tune_info = 0; | |
11323 | ||
e9670677 | 11324 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11325 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11326 | { |
6caf9ef4 | 11327 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11328 | as_bad (_("-G not supported in this configuration.")); |
11329 | g_switch_value = 0; | |
11330 | } | |
11331 | ||
cac012d6 AO |
11332 | if (mips_abi == NO_ABI) |
11333 | mips_abi = MIPS_DEFAULT_ABI; | |
11334 | ||
22923709 RS |
11335 | /* The following code determines the architecture and register size. |
11336 | Similar code was added to GCC 3.3 (see override_options() in | |
11337 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11338 | as much as possible. */ | |
e9670677 | 11339 | |
316f5878 | 11340 | if (mips_arch_string != 0) |
fef14a42 | 11341 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11342 | |
316f5878 | 11343 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11344 | { |
316f5878 | 11345 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11346 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11347 | the -march selection (if any). */ |
fef14a42 | 11348 | if (arch_info != 0) |
e9670677 | 11349 | { |
316f5878 RS |
11350 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11351 | There's no harm in specifying both as long as the ISA levels | |
11352 | are the same. */ | |
fef14a42 | 11353 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11354 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11355 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11356 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11357 | } |
316f5878 | 11358 | else |
fef14a42 | 11359 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11360 | } |
11361 | ||
fef14a42 TS |
11362 | if (arch_info == 0) |
11363 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11364 | |
fef14a42 | 11365 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11366 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11367 | arch_info->name); |
11368 | ||
11369 | mips_set_architecture (arch_info); | |
11370 | ||
11371 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11372 | if (mips_tune_string != 0) | |
11373 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11374 | |
fef14a42 TS |
11375 | if (tune_info == 0) |
11376 | mips_set_tune (arch_info); | |
11377 | else | |
11378 | mips_set_tune (tune_info); | |
e9670677 | 11379 | |
316f5878 | 11380 | if (file_mips_gp32 >= 0) |
e9670677 | 11381 | { |
316f5878 RS |
11382 | /* The user specified the size of the integer registers. Make sure |
11383 | it agrees with the ABI and ISA. */ | |
11384 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11385 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11386 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11387 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11388 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11389 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11390 | } |
11391 | else | |
11392 | { | |
316f5878 RS |
11393 | /* Infer the integer register size from the ABI and processor. |
11394 | Restrict ourselves to 32-bit registers if that's all the | |
11395 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11396 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11397 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11398 | } |
11399 | ||
ad3fea08 TS |
11400 | switch (file_mips_fp32) |
11401 | { | |
11402 | default: | |
11403 | case -1: | |
11404 | /* No user specified float register size. | |
11405 | ??? GAS treats single-float processors as though they had 64-bit | |
11406 | float registers (although it complains when double-precision | |
11407 | instructions are used). As things stand, saying they have 32-bit | |
11408 | registers would lead to spurious "register must be even" messages. | |
11409 | So here we assume float registers are never smaller than the | |
11410 | integer ones. */ | |
11411 | if (file_mips_gp32 == 0) | |
11412 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11413 | file_mips_fp32 = 0; | |
11414 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11415 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11416 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11417 | file_mips_fp32 = 0; | |
11418 | else | |
11419 | /* 32-bit float registers. */ | |
11420 | file_mips_fp32 = 1; | |
11421 | break; | |
11422 | ||
11423 | /* The user specified the size of the float registers. Check if it | |
11424 | agrees with the ABI and ISA. */ | |
11425 | case 0: | |
11426 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11427 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11428 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11429 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11430 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11431 | break; | |
11432 | case 1: | |
11433 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11434 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11435 | break; | |
11436 | } | |
e9670677 | 11437 | |
316f5878 | 11438 | /* End of GCC-shared inference code. */ |
e9670677 | 11439 | |
17a2f251 TS |
11440 | /* This flag is set when we have a 64-bit capable CPU but use only |
11441 | 32-bit wide registers. Note that EABI does not use it. */ | |
11442 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11443 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11444 | || mips_abi == O32_ABI)) | |
316f5878 | 11445 | mips_32bitmode = 1; |
e9670677 MR |
11446 | |
11447 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11448 | as_bad (_("trap exception not supported at ISA 1")); | |
11449 | ||
e9670677 MR |
11450 | /* If the selected architecture includes support for ASEs, enable |
11451 | generation of code for them. */ | |
a4672219 | 11452 | if (mips_opts.mips16 == -1) |
fef14a42 | 11453 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11454 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 11455 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
11456 | && file_mips_fp32 == 0) ? 1 : 0; |
11457 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
11458 | as_bad (_("-mfp32 used with -mips3d")); | |
11459 | ||
ffdefa66 | 11460 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 11461 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
11462 | && file_mips_fp32 == 0) ? 1 : 0; |
11463 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
11464 | as_bad (_("-mfp32 used with -mdmx")); | |
11465 | ||
11466 | if (mips_opts.ase_smartmips == -1) | |
11467 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
11468 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
11469 | as_warn ("%s ISA does not support SmartMIPS", | |
11470 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11471 | ||
74cd071d | 11472 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
11473 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
11474 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
11475 | as_warn ("%s ISA does not support DSP ASE", | |
11476 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11477 | ||
ef2e4d86 | 11478 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
11479 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
11480 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
11481 | as_warn ("%s ISA does not support MT ASE", | |
11482 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 11483 | |
e9670677 | 11484 | file_mips_isa = mips_opts.isa; |
a4672219 | 11485 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11486 | file_ase_mips3d = mips_opts.ase_mips3d; |
11487 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11488 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11489 | file_ase_dsp = mips_opts.ase_dsp; |
ef2e4d86 | 11490 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11491 | mips_opts.gp32 = file_mips_gp32; |
11492 | mips_opts.fp32 = file_mips_fp32; | |
11493 | ||
ecb4347a DJ |
11494 | if (mips_flag_mdebug < 0) |
11495 | { | |
11496 | #ifdef OBJ_MAYBE_ECOFF | |
11497 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11498 | mips_flag_mdebug = 1; | |
11499 | else | |
11500 | #endif /* OBJ_MAYBE_ECOFF */ | |
11501 | mips_flag_mdebug = 0; | |
11502 | } | |
e9670677 MR |
11503 | } |
11504 | \f | |
11505 | void | |
17a2f251 | 11506 | mips_init_after_args (void) |
252b5132 RH |
11507 | { |
11508 | /* initialize opcodes */ | |
11509 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11510 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11511 | } |
11512 | ||
11513 | long | |
17a2f251 | 11514 | md_pcrel_from (fixS *fixP) |
252b5132 | 11515 | { |
a7ebbfdf TS |
11516 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11517 | switch (fixP->fx_r_type) | |
11518 | { | |
11519 | case BFD_RELOC_16_PCREL_S2: | |
11520 | case BFD_RELOC_MIPS_JMP: | |
11521 | /* Return the address of the delay slot. */ | |
11522 | return addr + 4; | |
11523 | default: | |
11524 | return addr; | |
11525 | } | |
252b5132 RH |
11526 | } |
11527 | ||
252b5132 RH |
11528 | /* This is called before the symbol table is processed. In order to |
11529 | work with gcc when using mips-tfile, we must keep all local labels. | |
11530 | However, in other cases, we want to discard them. If we were | |
11531 | called with -g, but we didn't see any debugging information, it may | |
11532 | mean that gcc is smuggling debugging information through to | |
11533 | mips-tfile, in which case we must generate all local labels. */ | |
11534 | ||
11535 | void | |
17a2f251 | 11536 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11537 | { |
11538 | #ifndef NO_ECOFF_DEBUGGING | |
11539 | if (ECOFF_DEBUGGING | |
11540 | && mips_debug != 0 | |
11541 | && ! ecoff_debugging_seen) | |
11542 | flag_keep_locals = 1; | |
11543 | #endif | |
11544 | } | |
11545 | ||
3b91255e | 11546 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11547 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11548 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11549 | relocation operators. | |
11550 | ||
11551 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11552 | expression if: | |
11553 | ||
11554 | (a) it refers to the same symbol; and | |
11555 | (b) the offset applied in the %lo() expression is no lower than | |
11556 | the offset applied in the %got() or %hi(). | |
11557 | ||
11558 | (b) allows us to cope with code like: | |
11559 | ||
11560 | lui $4,%hi(foo) | |
11561 | lh $4,%lo(foo+2)($4) | |
11562 | ||
11563 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11564 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11565 | the high 16 bits. | |
11566 | ||
11567 | When several %lo()s match a particular %got() or %hi(), we use the | |
11568 | following rules to distinguish them: | |
11569 | ||
11570 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11571 | higher offsets. | |
11572 | ||
11573 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11574 | that already have a matching %got() or %hi(). | |
11575 | ||
11576 | (3) later %lo()s are better than earlier %lo()s. | |
11577 | ||
11578 | These rules are applied in order. | |
11579 | ||
11580 | (1) means, among other things, that %lo()s with identical offsets are | |
11581 | chosen if they exist. | |
11582 | ||
11583 | (2) means that we won't associate several high-part relocations with | |
11584 | the same low-part relocation unless there's no alternative. Having | |
11585 | several high parts for the same low part is a GNU extension; this rule | |
11586 | allows careful users to avoid it. | |
11587 | ||
11588 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11589 | with the last high-part relocation being at the front of the list. | |
11590 | It therefore makes sense to choose the last matching low-part | |
11591 | relocation, all other things being equal. It's also easier | |
11592 | to code that way. */ | |
252b5132 RH |
11593 | |
11594 | void | |
17a2f251 | 11595 | mips_frob_file (void) |
252b5132 RH |
11596 | { |
11597 | struct mips_hi_fixup *l; | |
11598 | ||
11599 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11600 | { | |
11601 | segment_info_type *seginfo; | |
3b91255e RS |
11602 | bfd_boolean matched_lo_p; |
11603 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11604 | |
5919d012 | 11605 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11606 | |
5919d012 RS |
11607 | /* If a GOT16 relocation turns out to be against a global symbol, |
11608 | there isn't supposed to be a matching LO. */ | |
11609 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11610 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11611 | continue; | |
11612 | ||
11613 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11614 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11615 | continue; |
11616 | ||
252b5132 | 11617 | seginfo = seg_info (l->seg); |
252b5132 | 11618 | |
3b91255e RS |
11619 | /* Set HI_POS to the position of this relocation in the chain. |
11620 | Set LO_POS to the position of the chosen low-part relocation. | |
11621 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11622 | relocation that matches an immediately-preceding high-part | |
11623 | relocation. */ | |
11624 | hi_pos = NULL; | |
11625 | lo_pos = NULL; | |
11626 | matched_lo_p = FALSE; | |
11627 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
11628 | { | |
11629 | if (*pos == l->fixp) | |
11630 | hi_pos = pos; | |
11631 | ||
704803a9 MR |
11632 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
11633 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
11634 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11635 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11636 | && (lo_pos == NULL | |
11637 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11638 | || (!matched_lo_p | |
11639 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11640 | lo_pos = pos; | |
11641 | ||
11642 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11643 | && fixup_has_matching_lo_p (*pos)); | |
11644 | } | |
11645 | ||
11646 | /* If we found a match, remove the high-part relocation from its | |
11647 | current position and insert it before the low-part relocation. | |
11648 | Make the offsets match so that fixup_has_matching_lo_p() | |
11649 | will return true. | |
11650 | ||
11651 | We don't warn about unmatched high-part relocations since some | |
11652 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11653 | instructions. */ | |
11654 | if (lo_pos != NULL) | |
11655 | { | |
11656 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11657 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11658 | { |
3b91255e RS |
11659 | *hi_pos = l->fixp->fx_next; |
11660 | l->fixp->fx_next = *lo_pos; | |
11661 | *lo_pos = l->fixp; | |
252b5132 | 11662 | } |
252b5132 RH |
11663 | } |
11664 | } | |
11665 | } | |
11666 | ||
3e722fb5 | 11667 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11668 | We have to prevent gas from dropping them. */ |
252b5132 | 11669 | |
252b5132 | 11670 | int |
17a2f251 | 11671 | mips_force_relocation (fixS *fixp) |
252b5132 | 11672 | { |
ae6063d4 | 11673 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11674 | return 1; |
11675 | ||
f6688943 TS |
11676 | if (HAVE_NEWABI |
11677 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11678 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11679 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11680 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11681 | return 1; | |
11682 | ||
3e722fb5 | 11683 | return 0; |
252b5132 RH |
11684 | } |
11685 | ||
11686 | /* Apply a fixup to the object file. */ | |
11687 | ||
94f592af | 11688 | void |
55cf6793 | 11689 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11690 | { |
874e8986 | 11691 | bfd_byte *buf; |
98aa84af | 11692 | long insn; |
a7ebbfdf | 11693 | reloc_howto_type *howto; |
252b5132 | 11694 | |
a7ebbfdf TS |
11695 | /* We ignore generic BFD relocations we don't know about. */ |
11696 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11697 | if (! howto) | |
11698 | return; | |
65551fa4 | 11699 | |
252b5132 RH |
11700 | assert (fixP->fx_size == 4 |
11701 | || fixP->fx_r_type == BFD_RELOC_16 | |
11702 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11703 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11704 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11705 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11706 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11707 | |
a7ebbfdf | 11708 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11709 | |
3994f87e | 11710 | assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
11711 | |
11712 | /* Don't treat parts of a composite relocation as done. There are two | |
11713 | reasons for this: | |
11714 | ||
11715 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11716 | should nevertheless be emitted if the first part is. | |
11717 | ||
11718 | (2) In normal usage, composite relocations are never assembly-time | |
11719 | constants. The easiest way of dealing with the pathological | |
11720 | exceptions is to generate a relocation against STN_UNDEF and | |
11721 | leave everything up to the linker. */ | |
3994f87e | 11722 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
11723 | fixP->fx_done = 1; |
11724 | ||
11725 | switch (fixP->fx_r_type) | |
11726 | { | |
3f98094e DJ |
11727 | case BFD_RELOC_MIPS_TLS_GD: |
11728 | case BFD_RELOC_MIPS_TLS_LDM: | |
11729 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11730 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11731 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11732 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11733 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11734 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11735 | /* fall through */ | |
11736 | ||
252b5132 | 11737 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11738 | case BFD_RELOC_MIPS_SHIFT5: |
11739 | case BFD_RELOC_MIPS_SHIFT6: | |
11740 | case BFD_RELOC_MIPS_GOT_DISP: | |
11741 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11742 | case BFD_RELOC_MIPS_GOT_OFST: | |
11743 | case BFD_RELOC_MIPS_SUB: | |
11744 | case BFD_RELOC_MIPS_INSERT_A: | |
11745 | case BFD_RELOC_MIPS_INSERT_B: | |
11746 | case BFD_RELOC_MIPS_DELETE: | |
11747 | case BFD_RELOC_MIPS_HIGHEST: | |
11748 | case BFD_RELOC_MIPS_HIGHER: | |
11749 | case BFD_RELOC_MIPS_SCN_DISP: | |
11750 | case BFD_RELOC_MIPS_REL16: | |
11751 | case BFD_RELOC_MIPS_RELGOT: | |
11752 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11753 | case BFD_RELOC_HI16: |
11754 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11755 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11756 | case BFD_RELOC_MIPS_LITERAL: |
11757 | case BFD_RELOC_MIPS_CALL16: | |
11758 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11759 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11760 | case BFD_RELOC_MIPS_GOT_HI16: |
11761 | case BFD_RELOC_MIPS_GOT_LO16: | |
11762 | case BFD_RELOC_MIPS_CALL_HI16: | |
11763 | case BFD_RELOC_MIPS_CALL_LO16: | |
11764 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11765 | case BFD_RELOC_MIPS16_HI16: |
11766 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 RH |
11767 | /* Nothing needed to do. The value comes from the reloc entry */ |
11768 | break; | |
11769 | ||
11770 | case BFD_RELOC_MIPS16_JMP: | |
11771 | /* We currently always generate a reloc against a symbol, which | |
11772 | means that we don't want an addend even if the symbol is | |
11773 | defined. */ | |
a7ebbfdf | 11774 | *valP = 0; |
252b5132 RH |
11775 | break; |
11776 | ||
252b5132 RH |
11777 | case BFD_RELOC_64: |
11778 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11779 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11780 | if (fixP->fx_done) |
252b5132 RH |
11781 | { |
11782 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11783 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11784 | else |
11785 | { | |
a7ebbfdf | 11786 | valueT hiv; |
252b5132 | 11787 | |
a7ebbfdf | 11788 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11789 | hiv = 0xffffffff; |
11790 | else | |
11791 | hiv = 0; | |
b215186b | 11792 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11793 | *valP, 4); |
b215186b | 11794 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11795 | hiv, 4); |
252b5132 RH |
11796 | } |
11797 | } | |
11798 | break; | |
11799 | ||
056350c6 | 11800 | case BFD_RELOC_RVA: |
252b5132 RH |
11801 | case BFD_RELOC_32: |
11802 | /* If we are deleting this reloc entry, we must fill in the | |
11803 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11804 | resolved when it appears but is later defined. */ |
11805 | if (fixP->fx_done) | |
2132e3a3 | 11806 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11807 | break; |
11808 | ||
11809 | case BFD_RELOC_16: | |
11810 | /* If we are deleting this reloc entry, we must fill in the | |
11811 | value now. */ | |
252b5132 | 11812 | if (fixP->fx_done) |
2132e3a3 | 11813 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11814 | break; |
11815 | ||
11816 | case BFD_RELOC_LO16: | |
d6f16593 | 11817 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11818 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11819 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11820 | /* When handling an embedded PIC switch statement, we can wind |
11821 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11822 | if (fixP->fx_done) | |
11823 | { | |
a7ebbfdf | 11824 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11825 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11826 | _("relocation overflow")); | |
252b5132 RH |
11827 | if (target_big_endian) |
11828 | buf += 2; | |
2132e3a3 | 11829 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11830 | } |
11831 | break; | |
11832 | ||
11833 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11834 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11835 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 11836 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 11837 | |
252b5132 RH |
11838 | /* |
11839 | * We need to save the bits in the instruction since fixup_segment() | |
11840 | * might be deleting the relocation entry (i.e., a branch within | |
11841 | * the current segment). | |
11842 | */ | |
a7ebbfdf | 11843 | if (! fixP->fx_done) |
bb2d6cd7 | 11844 | break; |
252b5132 RH |
11845 | |
11846 | /* update old instruction data */ | |
252b5132 RH |
11847 | if (target_big_endian) |
11848 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11849 | else | |
11850 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11851 | ||
a7ebbfdf TS |
11852 | if (*valP + 0x20000 <= 0x3ffff) |
11853 | { | |
11854 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11855 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11856 | } |
11857 | else if (mips_pic == NO_PIC | |
11858 | && fixP->fx_done | |
11859 | && fixP->fx_frag->fr_address >= text_section->vma | |
11860 | && (fixP->fx_frag->fr_address | |
587aac4e | 11861 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11862 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11863 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11864 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11865 | { |
11866 | /* The branch offset is too large. If this is an | |
11867 | unconditional branch, and we are not generating PIC code, | |
11868 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11869 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11870 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11871 | else |
a7ebbfdf TS |
11872 | insn = 0x08000000; /* j */ |
11873 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11874 | fixP->fx_done = 0; | |
11875 | fixP->fx_addsy = section_symbol (text_section); | |
11876 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11877 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11878 | } |
11879 | else | |
11880 | { | |
11881 | /* If we got here, we have branch-relaxation disabled, | |
11882 | and there's nothing we can do to fix this instruction | |
11883 | without turning it into a longer sequence. */ | |
11884 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11885 | _("Branch out of range")); | |
252b5132 | 11886 | } |
252b5132 RH |
11887 | break; |
11888 | ||
11889 | case BFD_RELOC_VTABLE_INHERIT: | |
11890 | fixP->fx_done = 0; | |
11891 | if (fixP->fx_addsy | |
11892 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11893 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11894 | S_SET_WEAK (fixP->fx_addsy); | |
11895 | break; | |
11896 | ||
11897 | case BFD_RELOC_VTABLE_ENTRY: | |
11898 | fixP->fx_done = 0; | |
11899 | break; | |
11900 | ||
11901 | default: | |
11902 | internalError (); | |
11903 | } | |
a7ebbfdf TS |
11904 | |
11905 | /* Remember value for tc_gen_reloc. */ | |
11906 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11907 | } |
11908 | ||
252b5132 | 11909 | static symbolS * |
17a2f251 | 11910 | get_symbol (void) |
252b5132 RH |
11911 | { |
11912 | int c; | |
11913 | char *name; | |
11914 | symbolS *p; | |
11915 | ||
11916 | name = input_line_pointer; | |
11917 | c = get_symbol_end (); | |
11918 | p = (symbolS *) symbol_find_or_make (name); | |
11919 | *input_line_pointer = c; | |
11920 | return p; | |
11921 | } | |
11922 | ||
11923 | /* Align the current frag to a given power of two. The MIPS assembler | |
11924 | also automatically adjusts any preceding label. */ | |
11925 | ||
11926 | static void | |
17a2f251 | 11927 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11928 | { |
7d10b47d | 11929 | mips_emit_delays (); |
252b5132 RH |
11930 | frag_align (to, fill, 0); |
11931 | record_alignment (now_seg, to); | |
11932 | if (label != NULL) | |
11933 | { | |
11934 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11935 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11936 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11937 | } | |
11938 | } | |
11939 | ||
11940 | /* Align to a given power of two. .align 0 turns off the automatic | |
11941 | alignment used by the data creating pseudo-ops. */ | |
11942 | ||
11943 | static void | |
17a2f251 | 11944 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 11945 | { |
3994f87e TS |
11946 | int temp; |
11947 | long temp_fill; | |
252b5132 RH |
11948 | long max_alignment = 15; |
11949 | ||
11950 | /* | |
11951 | ||
67c1ffbe | 11952 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11953 | to the aligned address. |
11954 | o It's not documented but auto alignment is reinstated by | |
11955 | a .align pseudo instruction. | |
11956 | o Note also that after auto alignment is turned off the mips assembler | |
11957 | issues an error on attempt to assemble an improperly aligned data item. | |
11958 | We don't. | |
11959 | ||
11960 | */ | |
11961 | ||
11962 | temp = get_absolute_expression (); | |
11963 | if (temp > max_alignment) | |
11964 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11965 | else if (temp < 0) | |
11966 | { | |
11967 | as_warn (_("Alignment negative: 0 assumed.")); | |
11968 | temp = 0; | |
11969 | } | |
11970 | if (*input_line_pointer == ',') | |
11971 | { | |
f9419b05 | 11972 | ++input_line_pointer; |
252b5132 RH |
11973 | temp_fill = get_absolute_expression (); |
11974 | } | |
11975 | else | |
11976 | temp_fill = 0; | |
11977 | if (temp) | |
11978 | { | |
a8dbcb85 TS |
11979 | segment_info_type *si = seg_info (now_seg); |
11980 | struct insn_label_list *l = si->label_list; | |
11981 | /* Auto alignment should be switched on by next section change */ | |
252b5132 | 11982 | auto_align = 1; |
a8dbcb85 | 11983 | mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL); |
252b5132 RH |
11984 | } |
11985 | else | |
11986 | { | |
11987 | auto_align = 0; | |
11988 | } | |
11989 | ||
11990 | demand_empty_rest_of_line (); | |
11991 | } | |
11992 | ||
252b5132 | 11993 | static void |
17a2f251 | 11994 | s_change_sec (int sec) |
252b5132 RH |
11995 | { |
11996 | segT seg; | |
11997 | ||
252b5132 RH |
11998 | #ifdef OBJ_ELF |
11999 | /* The ELF backend needs to know that we are changing sections, so | |
12000 | that .previous works correctly. We could do something like check | |
b6ff326e | 12001 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12002 | as it would not be appropriate to use it in the section changing |
12003 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12004 | This should be cleaner, somehow. */ | |
12005 | obj_elf_section_change_hook (); | |
12006 | #endif | |
12007 | ||
7d10b47d | 12008 | mips_emit_delays (); |
252b5132 RH |
12009 | switch (sec) |
12010 | { | |
12011 | case 't': | |
12012 | s_text (0); | |
12013 | break; | |
12014 | case 'd': | |
12015 | s_data (0); | |
12016 | break; | |
12017 | case 'b': | |
12018 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12019 | demand_empty_rest_of_line (); | |
12020 | break; | |
12021 | ||
12022 | case 'r': | |
4d0d148d TS |
12023 | seg = subseg_new (RDATA_SECTION_NAME, |
12024 | (subsegT) get_absolute_expression ()); | |
12025 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 12026 | { |
4d0d148d TS |
12027 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12028 | | SEC_READONLY | SEC_RELOC | |
12029 | | SEC_DATA)); | |
12030 | if (strcmp (TARGET_OS, "elf") != 0) | |
12031 | record_alignment (seg, 4); | |
252b5132 | 12032 | } |
4d0d148d | 12033 | demand_empty_rest_of_line (); |
252b5132 RH |
12034 | break; |
12035 | ||
12036 | case 's': | |
4d0d148d TS |
12037 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
12038 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 12039 | { |
4d0d148d TS |
12040 | bfd_set_section_flags (stdoutput, seg, |
12041 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
12042 | if (strcmp (TARGET_OS, "elf") != 0) | |
12043 | record_alignment (seg, 4); | |
252b5132 | 12044 | } |
4d0d148d TS |
12045 | demand_empty_rest_of_line (); |
12046 | break; | |
252b5132 RH |
12047 | } |
12048 | ||
12049 | auto_align = 1; | |
12050 | } | |
b34976b6 | 12051 | |
cca86cc8 | 12052 | void |
17a2f251 | 12053 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12054 | { |
7ed4a06a | 12055 | #ifdef OBJ_ELF |
cca86cc8 SC |
12056 | char *section_name; |
12057 | char c; | |
684022ea | 12058 | char next_c = 0; |
cca86cc8 SC |
12059 | int section_type; |
12060 | int section_flag; | |
12061 | int section_entry_size; | |
12062 | int section_alignment; | |
b34976b6 | 12063 | |
7ed4a06a TS |
12064 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
12065 | return; | |
12066 | ||
cca86cc8 SC |
12067 | section_name = input_line_pointer; |
12068 | c = get_symbol_end (); | |
a816d1ed AO |
12069 | if (c) |
12070 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12071 | |
4cf0dd0d TS |
12072 | /* Do we have .section Name<,"flags">? */ |
12073 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12074 | { |
4cf0dd0d TS |
12075 | /* just after name is now '\0'. */ |
12076 | *input_line_pointer = c; | |
cca86cc8 SC |
12077 | input_line_pointer = section_name; |
12078 | obj_elf_section (ignore); | |
12079 | return; | |
12080 | } | |
12081 | input_line_pointer++; | |
12082 | ||
12083 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12084 | if (c == ',') | |
12085 | section_type = get_absolute_expression (); | |
12086 | else | |
12087 | section_type = 0; | |
12088 | if (*input_line_pointer++ == ',') | |
12089 | section_flag = get_absolute_expression (); | |
12090 | else | |
12091 | section_flag = 0; | |
12092 | if (*input_line_pointer++ == ',') | |
12093 | section_entry_size = get_absolute_expression (); | |
12094 | else | |
12095 | section_entry_size = 0; | |
12096 | if (*input_line_pointer++ == ',') | |
12097 | section_alignment = get_absolute_expression (); | |
12098 | else | |
12099 | section_alignment = 0; | |
12100 | ||
a816d1ed AO |
12101 | section_name = xstrdup (section_name); |
12102 | ||
8ab8a5c8 RS |
12103 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12104 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12105 | traditionally had to fall back on the more common @progbits instead. | |
12106 | ||
12107 | There's nothing really harmful in this, since bfd will correct | |
12108 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12109 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12110 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12111 | ||
12112 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12113 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12114 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12115 | generic type-checking code. */ | |
12116 | if (section_type == SHT_MIPS_DWARF) | |
12117 | section_type = SHT_PROGBITS; | |
12118 | ||
cca86cc8 SC |
12119 | obj_elf_change_section (section_name, section_type, section_flag, |
12120 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12121 | |
12122 | if (now_seg->name != section_name) | |
12123 | free (section_name); | |
7ed4a06a | 12124 | #endif /* OBJ_ELF */ |
cca86cc8 | 12125 | } |
252b5132 RH |
12126 | |
12127 | void | |
17a2f251 | 12128 | mips_enable_auto_align (void) |
252b5132 RH |
12129 | { |
12130 | auto_align = 1; | |
12131 | } | |
12132 | ||
12133 | static void | |
17a2f251 | 12134 | s_cons (int log_size) |
252b5132 | 12135 | { |
a8dbcb85 TS |
12136 | segment_info_type *si = seg_info (now_seg); |
12137 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12138 | symbolS *label; |
12139 | ||
a8dbcb85 | 12140 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12141 | mips_emit_delays (); |
252b5132 RH |
12142 | if (log_size > 0 && auto_align) |
12143 | mips_align (log_size, 0, label); | |
12144 | mips_clear_insn_labels (); | |
12145 | cons (1 << log_size); | |
12146 | } | |
12147 | ||
12148 | static void | |
17a2f251 | 12149 | s_float_cons (int type) |
252b5132 | 12150 | { |
a8dbcb85 TS |
12151 | segment_info_type *si = seg_info (now_seg); |
12152 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12153 | symbolS *label; |
12154 | ||
a8dbcb85 | 12155 | label = l != NULL ? l->label : NULL; |
252b5132 | 12156 | |
7d10b47d | 12157 | mips_emit_delays (); |
252b5132 RH |
12158 | |
12159 | if (auto_align) | |
49309057 ILT |
12160 | { |
12161 | if (type == 'd') | |
12162 | mips_align (3, 0, label); | |
12163 | else | |
12164 | mips_align (2, 0, label); | |
12165 | } | |
252b5132 RH |
12166 | |
12167 | mips_clear_insn_labels (); | |
12168 | ||
12169 | float_cons (type); | |
12170 | } | |
12171 | ||
12172 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12173 | permitted to say | |
12174 | .globl foo .text | |
12175 | where foo is an undefined symbol, to mean that foo should be | |
12176 | considered to be the address of a function. */ | |
12177 | ||
12178 | static void | |
17a2f251 | 12179 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12180 | { |
12181 | char *name; | |
12182 | int c; | |
12183 | symbolS *symbolP; | |
12184 | flagword flag; | |
12185 | ||
8a06b769 | 12186 | do |
252b5132 | 12187 | { |
8a06b769 | 12188 | name = input_line_pointer; |
252b5132 | 12189 | c = get_symbol_end (); |
8a06b769 TS |
12190 | symbolP = symbol_find_or_make (name); |
12191 | S_SET_EXTERNAL (symbolP); | |
12192 | ||
252b5132 | 12193 | *input_line_pointer = c; |
8a06b769 | 12194 | SKIP_WHITESPACE (); |
252b5132 | 12195 | |
8a06b769 TS |
12196 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12197 | being a function is apparently labelled as being an object. */ | |
12198 | flag = BSF_OBJECT; | |
252b5132 | 12199 | |
8a06b769 TS |
12200 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12201 | && (*input_line_pointer != ',')) | |
12202 | { | |
12203 | char *secname; | |
12204 | asection *sec; | |
12205 | ||
12206 | secname = input_line_pointer; | |
12207 | c = get_symbol_end (); | |
12208 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12209 | if (sec == NULL) | |
12210 | as_bad (_("%s: no such section"), secname); | |
12211 | *input_line_pointer = c; | |
12212 | ||
12213 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12214 | flag = BSF_FUNCTION; | |
12215 | } | |
12216 | ||
12217 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12218 | ||
12219 | c = *input_line_pointer; | |
12220 | if (c == ',') | |
12221 | { | |
12222 | input_line_pointer++; | |
12223 | SKIP_WHITESPACE (); | |
12224 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12225 | c = '\n'; | |
12226 | } | |
12227 | } | |
12228 | while (c == ','); | |
252b5132 | 12229 | |
252b5132 RH |
12230 | demand_empty_rest_of_line (); |
12231 | } | |
12232 | ||
12233 | static void | |
17a2f251 | 12234 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12235 | { |
12236 | char *opt; | |
12237 | char c; | |
12238 | ||
12239 | opt = input_line_pointer; | |
12240 | c = get_symbol_end (); | |
12241 | ||
12242 | if (*opt == 'O') | |
12243 | { | |
12244 | /* FIXME: What does this mean? */ | |
12245 | } | |
12246 | else if (strncmp (opt, "pic", 3) == 0) | |
12247 | { | |
12248 | int i; | |
12249 | ||
12250 | i = atoi (opt + 3); | |
12251 | if (i == 0) | |
12252 | mips_pic = NO_PIC; | |
12253 | else if (i == 2) | |
143d77c5 | 12254 | { |
252b5132 | 12255 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12256 | mips_abicalls = TRUE; |
12257 | } | |
252b5132 RH |
12258 | else |
12259 | as_bad (_(".option pic%d not supported"), i); | |
12260 | ||
4d0d148d | 12261 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12262 | { |
12263 | if (g_switch_seen && g_switch_value != 0) | |
12264 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12265 | g_switch_value = 0; | |
12266 | bfd_set_gp_size (stdoutput, 0); | |
12267 | } | |
12268 | } | |
12269 | else | |
12270 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12271 | ||
12272 | *input_line_pointer = c; | |
12273 | demand_empty_rest_of_line (); | |
12274 | } | |
12275 | ||
12276 | /* This structure is used to hold a stack of .set values. */ | |
12277 | ||
e972090a NC |
12278 | struct mips_option_stack |
12279 | { | |
252b5132 RH |
12280 | struct mips_option_stack *next; |
12281 | struct mips_set_options options; | |
12282 | }; | |
12283 | ||
12284 | static struct mips_option_stack *mips_opts_stack; | |
12285 | ||
12286 | /* Handle the .set pseudo-op. */ | |
12287 | ||
12288 | static void | |
17a2f251 | 12289 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12290 | { |
12291 | char *name = input_line_pointer, ch; | |
12292 | ||
12293 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12294 | ++input_line_pointer; |
252b5132 RH |
12295 | ch = *input_line_pointer; |
12296 | *input_line_pointer = '\0'; | |
12297 | ||
12298 | if (strcmp (name, "reorder") == 0) | |
12299 | { | |
7d10b47d RS |
12300 | if (mips_opts.noreorder) |
12301 | end_noreorder (); | |
252b5132 RH |
12302 | } |
12303 | else if (strcmp (name, "noreorder") == 0) | |
12304 | { | |
7d10b47d RS |
12305 | if (!mips_opts.noreorder) |
12306 | start_noreorder (); | |
252b5132 RH |
12307 | } |
12308 | else if (strcmp (name, "at") == 0) | |
12309 | { | |
12310 | mips_opts.noat = 0; | |
12311 | } | |
12312 | else if (strcmp (name, "noat") == 0) | |
12313 | { | |
12314 | mips_opts.noat = 1; | |
12315 | } | |
12316 | else if (strcmp (name, "macro") == 0) | |
12317 | { | |
12318 | mips_opts.warn_about_macros = 0; | |
12319 | } | |
12320 | else if (strcmp (name, "nomacro") == 0) | |
12321 | { | |
12322 | if (mips_opts.noreorder == 0) | |
12323 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12324 | mips_opts.warn_about_macros = 1; | |
12325 | } | |
12326 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12327 | { | |
12328 | mips_opts.nomove = 0; | |
12329 | } | |
12330 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12331 | { | |
12332 | mips_opts.nomove = 1; | |
12333 | } | |
12334 | else if (strcmp (name, "bopt") == 0) | |
12335 | { | |
12336 | mips_opts.nobopt = 0; | |
12337 | } | |
12338 | else if (strcmp (name, "nobopt") == 0) | |
12339 | { | |
12340 | mips_opts.nobopt = 1; | |
12341 | } | |
ad3fea08 TS |
12342 | else if (strcmp (name, "gp=default") == 0) |
12343 | mips_opts.gp32 = file_mips_gp32; | |
12344 | else if (strcmp (name, "gp=32") == 0) | |
12345 | mips_opts.gp32 = 1; | |
12346 | else if (strcmp (name, "gp=64") == 0) | |
12347 | { | |
12348 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12349 | as_warn ("%s isa does not support 64-bit registers", | |
12350 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12351 | mips_opts.gp32 = 0; | |
12352 | } | |
12353 | else if (strcmp (name, "fp=default") == 0) | |
12354 | mips_opts.fp32 = file_mips_fp32; | |
12355 | else if (strcmp (name, "fp=32") == 0) | |
12356 | mips_opts.fp32 = 1; | |
12357 | else if (strcmp (name, "fp=64") == 0) | |
12358 | { | |
12359 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12360 | as_warn ("%s isa does not support 64-bit floating point registers", | |
12361 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12362 | mips_opts.fp32 = 0; | |
12363 | } | |
252b5132 RH |
12364 | else if (strcmp (name, "mips16") == 0 |
12365 | || strcmp (name, "MIPS-16") == 0) | |
12366 | mips_opts.mips16 = 1; | |
12367 | else if (strcmp (name, "nomips16") == 0 | |
12368 | || strcmp (name, "noMIPS-16") == 0) | |
12369 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12370 | else if (strcmp (name, "smartmips") == 0) |
12371 | { | |
ad3fea08 | 12372 | if (!ISA_SUPPORTS_SMARTMIPS) |
e16bfa71 TS |
12373 | as_warn ("%s ISA does not support SmartMIPS ASE", |
12374 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12375 | mips_opts.ase_smartmips = 1; | |
12376 | } | |
12377 | else if (strcmp (name, "nosmartmips") == 0) | |
12378 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12379 | else if (strcmp (name, "mips3d") == 0) |
12380 | mips_opts.ase_mips3d = 1; | |
12381 | else if (strcmp (name, "nomips3d") == 0) | |
12382 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12383 | else if (strcmp (name, "mdmx") == 0) |
12384 | mips_opts.ase_mdmx = 1; | |
12385 | else if (strcmp (name, "nomdmx") == 0) | |
12386 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12387 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12388 | { |
12389 | if (!ISA_SUPPORTS_DSP_ASE) | |
12390 | as_warn ("%s ISA does not support DSP ASE", | |
12391 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12392 | mips_opts.ase_dsp = 1; | |
12393 | } | |
74cd071d CF |
12394 | else if (strcmp (name, "nodsp") == 0) |
12395 | mips_opts.ase_dsp = 0; | |
ef2e4d86 | 12396 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
12397 | { |
12398 | if (!ISA_SUPPORTS_MT_ASE) | |
12399 | as_warn ("%s ISA does not support MT ASE", | |
12400 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12401 | mips_opts.ase_mt = 1; | |
12402 | } | |
ef2e4d86 CF |
12403 | else if (strcmp (name, "nomt") == 0) |
12404 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12405 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12406 | { |
af7ee8bf | 12407 | int reset = 0; |
252b5132 | 12408 | |
1a2c1fad CD |
12409 | /* Permit the user to change the ISA and architecture on the fly. |
12410 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12411 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12412 | { |
12413 | reset = 1; | |
12414 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12415 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12416 | } |
12417 | else if (strncmp (name, "arch=", 5) == 0) | |
12418 | { | |
12419 | const struct mips_cpu_info *p; | |
12420 | ||
12421 | p = mips_parse_cpu("internal use", name + 5); | |
12422 | if (!p) | |
12423 | as_bad (_("unknown architecture %s"), name + 5); | |
12424 | else | |
12425 | { | |
12426 | mips_opts.arch = p->cpu; | |
12427 | mips_opts.isa = p->isa; | |
12428 | } | |
12429 | } | |
81a21e38 TS |
12430 | else if (strncmp (name, "mips", 4) == 0) |
12431 | { | |
12432 | const struct mips_cpu_info *p; | |
12433 | ||
12434 | p = mips_parse_cpu("internal use", name); | |
12435 | if (!p) | |
12436 | as_bad (_("unknown ISA level %s"), name + 4); | |
12437 | else | |
12438 | { | |
12439 | mips_opts.arch = p->cpu; | |
12440 | mips_opts.isa = p->isa; | |
12441 | } | |
12442 | } | |
af7ee8bf | 12443 | else |
81a21e38 | 12444 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12445 | |
12446 | switch (mips_opts.isa) | |
98d3f06f KH |
12447 | { |
12448 | case 0: | |
98d3f06f | 12449 | break; |
af7ee8bf CD |
12450 | case ISA_MIPS1: |
12451 | case ISA_MIPS2: | |
12452 | case ISA_MIPS32: | |
12453 | case ISA_MIPS32R2: | |
98d3f06f KH |
12454 | mips_opts.gp32 = 1; |
12455 | mips_opts.fp32 = 1; | |
12456 | break; | |
af7ee8bf CD |
12457 | case ISA_MIPS3: |
12458 | case ISA_MIPS4: | |
12459 | case ISA_MIPS5: | |
12460 | case ISA_MIPS64: | |
5f74bc13 | 12461 | case ISA_MIPS64R2: |
98d3f06f KH |
12462 | mips_opts.gp32 = 0; |
12463 | mips_opts.fp32 = 0; | |
12464 | break; | |
12465 | default: | |
12466 | as_bad (_("unknown ISA level %s"), name + 4); | |
12467 | break; | |
12468 | } | |
af7ee8bf | 12469 | if (reset) |
98d3f06f | 12470 | { |
af7ee8bf CD |
12471 | mips_opts.gp32 = file_mips_gp32; |
12472 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12473 | } |
252b5132 RH |
12474 | } |
12475 | else if (strcmp (name, "autoextend") == 0) | |
12476 | mips_opts.noautoextend = 0; | |
12477 | else if (strcmp (name, "noautoextend") == 0) | |
12478 | mips_opts.noautoextend = 1; | |
12479 | else if (strcmp (name, "push") == 0) | |
12480 | { | |
12481 | struct mips_option_stack *s; | |
12482 | ||
12483 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12484 | s->next = mips_opts_stack; | |
12485 | s->options = mips_opts; | |
12486 | mips_opts_stack = s; | |
12487 | } | |
12488 | else if (strcmp (name, "pop") == 0) | |
12489 | { | |
12490 | struct mips_option_stack *s; | |
12491 | ||
12492 | s = mips_opts_stack; | |
12493 | if (s == NULL) | |
12494 | as_bad (_(".set pop with no .set push")); | |
12495 | else | |
12496 | { | |
12497 | /* If we're changing the reorder mode we need to handle | |
12498 | delay slots correctly. */ | |
12499 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12500 | start_noreorder (); |
252b5132 | 12501 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12502 | end_noreorder (); |
252b5132 RH |
12503 | |
12504 | mips_opts = s->options; | |
12505 | mips_opts_stack = s->next; | |
12506 | free (s); | |
12507 | } | |
12508 | } | |
aed1a261 RS |
12509 | else if (strcmp (name, "sym32") == 0) |
12510 | mips_opts.sym32 = TRUE; | |
12511 | else if (strcmp (name, "nosym32") == 0) | |
12512 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
12513 | else |
12514 | { | |
12515 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12516 | } | |
12517 | *input_line_pointer = ch; | |
12518 | demand_empty_rest_of_line (); | |
12519 | } | |
12520 | ||
12521 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12522 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12523 | ||
12524 | static void | |
17a2f251 | 12525 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12526 | { |
12527 | mips_pic = SVR4_PIC; | |
143d77c5 | 12528 | mips_abicalls = TRUE; |
4d0d148d TS |
12529 | |
12530 | if (g_switch_seen && g_switch_value != 0) | |
12531 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12532 | g_switch_value = 0; | |
12533 | ||
252b5132 RH |
12534 | bfd_set_gp_size (stdoutput, 0); |
12535 | demand_empty_rest_of_line (); | |
12536 | } | |
12537 | ||
12538 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12539 | PIC code. It sets the $gp register for the function based on the | |
12540 | function address, which is in the register named in the argument. | |
12541 | This uses a relocation against _gp_disp, which is handled specially | |
12542 | by the linker. The result is: | |
12543 | lui $gp,%hi(_gp_disp) | |
12544 | addiu $gp,$gp,%lo(_gp_disp) | |
12545 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12546 | The .cpload argument is normally $25 == $t9. |
12547 | ||
12548 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12549 | lui $gp,%hi(__gnu_local_gp) |
12550 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12551 | and the argument is ignored. This saves an instruction, but the |
12552 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12553 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12554 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12555 | |
12556 | static void | |
17a2f251 | 12557 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12558 | { |
12559 | expressionS ex; | |
aa6975fb ILT |
12560 | int reg; |
12561 | int in_shared; | |
252b5132 | 12562 | |
6478892d TS |
12563 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12564 | .cpload is ignored. */ | |
12565 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12566 | { |
12567 | s_ignore (0); | |
12568 | return; | |
12569 | } | |
12570 | ||
d3ecfc59 | 12571 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12572 | if (mips_opts.noreorder == 0) |
12573 | as_warn (_(".cpload not in noreorder section")); | |
12574 | ||
aa6975fb ILT |
12575 | reg = tc_get_register (0); |
12576 | ||
12577 | /* If we need to produce a 64-bit address, we are better off using | |
12578 | the default instruction sequence. */ | |
aed1a261 | 12579 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12580 | |
252b5132 | 12581 | ex.X_op = O_symbol; |
bbe506e8 TS |
12582 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12583 | "__gnu_local_gp"); | |
252b5132 RH |
12584 | ex.X_op_symbol = NULL; |
12585 | ex.X_add_number = 0; | |
12586 | ||
12587 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12588 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12589 | |
584892a6 | 12590 | macro_start (); |
67c0d1eb RS |
12591 | macro_build_lui (&ex, mips_gp_register); |
12592 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12593 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12594 | if (in_shared) |
12595 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12596 | mips_gp_register, reg); | |
584892a6 | 12597 | macro_end (); |
252b5132 RH |
12598 | |
12599 | demand_empty_rest_of_line (); | |
12600 | } | |
12601 | ||
6478892d TS |
12602 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12603 | .cpsetup $reg1, offset|$reg2, label | |
12604 | ||
12605 | If offset is given, this results in: | |
12606 | sd $gp, offset($sp) | |
956cd1d6 | 12607 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12608 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12609 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12610 | |
12611 | If $reg2 is given, this results in: | |
12612 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12613 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12614 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12615 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12616 | $reg1 is normally $25 == $t9. |
12617 | ||
12618 | The -mno-shared option replaces the last three instructions with | |
12619 | lui $gp,%hi(_gp) | |
12620 | addiu $gp,$gp,%lo(_gp) | |
12621 | */ | |
12622 | ||
6478892d | 12623 | static void |
17a2f251 | 12624 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12625 | { |
12626 | expressionS ex_off; | |
12627 | expressionS ex_sym; | |
12628 | int reg1; | |
6478892d | 12629 | |
8586fc66 | 12630 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12631 | We also need NewABI support. */ |
12632 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12633 | { | |
12634 | s_ignore (0); | |
12635 | return; | |
12636 | } | |
12637 | ||
12638 | reg1 = tc_get_register (0); | |
12639 | SKIP_WHITESPACE (); | |
12640 | if (*input_line_pointer != ',') | |
12641 | { | |
12642 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12643 | return; | |
12644 | } | |
12645 | else | |
80245285 | 12646 | ++input_line_pointer; |
6478892d TS |
12647 | SKIP_WHITESPACE (); |
12648 | if (*input_line_pointer == '$') | |
80245285 TS |
12649 | { |
12650 | mips_cpreturn_register = tc_get_register (0); | |
12651 | mips_cpreturn_offset = -1; | |
12652 | } | |
6478892d | 12653 | else |
80245285 TS |
12654 | { |
12655 | mips_cpreturn_offset = get_absolute_expression (); | |
12656 | mips_cpreturn_register = -1; | |
12657 | } | |
6478892d TS |
12658 | SKIP_WHITESPACE (); |
12659 | if (*input_line_pointer != ',') | |
12660 | { | |
12661 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12662 | return; | |
12663 | } | |
12664 | else | |
f9419b05 | 12665 | ++input_line_pointer; |
6478892d | 12666 | SKIP_WHITESPACE (); |
f21f8242 | 12667 | expression (&ex_sym); |
6478892d | 12668 | |
584892a6 | 12669 | macro_start (); |
6478892d TS |
12670 | if (mips_cpreturn_register == -1) |
12671 | { | |
12672 | ex_off.X_op = O_constant; | |
12673 | ex_off.X_add_symbol = NULL; | |
12674 | ex_off.X_op_symbol = NULL; | |
12675 | ex_off.X_add_number = mips_cpreturn_offset; | |
12676 | ||
67c0d1eb | 12677 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12678 | BFD_RELOC_LO16, SP); |
6478892d TS |
12679 | } |
12680 | else | |
67c0d1eb | 12681 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12682 | mips_gp_register, 0); |
6478892d | 12683 | |
aed1a261 | 12684 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12685 | { |
12686 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12687 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12688 | BFD_RELOC_HI16_S); | |
12689 | ||
12690 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12691 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12692 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12693 | ||
12694 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12695 | mips_gp_register, reg1); | |
12696 | } | |
12697 | else | |
12698 | { | |
12699 | expressionS ex; | |
12700 | ||
12701 | ex.X_op = O_symbol; | |
4184909a | 12702 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12703 | ex.X_op_symbol = NULL; |
12704 | ex.X_add_number = 0; | |
6e1304d8 | 12705 | |
aa6975fb ILT |
12706 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12707 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12708 | ||
12709 | macro_build_lui (&ex, mips_gp_register); | |
12710 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12711 | mips_gp_register, BFD_RELOC_LO16); | |
12712 | } | |
f21f8242 | 12713 | |
584892a6 | 12714 | macro_end (); |
6478892d TS |
12715 | |
12716 | demand_empty_rest_of_line (); | |
12717 | } | |
12718 | ||
12719 | static void | |
17a2f251 | 12720 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12721 | { |
12722 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12723 | .cplocal is ignored. */ | |
12724 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12725 | { | |
12726 | s_ignore (0); | |
12727 | return; | |
12728 | } | |
12729 | ||
12730 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12731 | demand_empty_rest_of_line (); |
6478892d TS |
12732 | } |
12733 | ||
252b5132 RH |
12734 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12735 | offset from $sp. The offset is remembered, and after making a PIC | |
12736 | call $gp is restored from that location. */ | |
12737 | ||
12738 | static void | |
17a2f251 | 12739 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12740 | { |
12741 | expressionS ex; | |
252b5132 | 12742 | |
6478892d | 12743 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12744 | .cprestore is ignored. */ |
6478892d | 12745 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12746 | { |
12747 | s_ignore (0); | |
12748 | return; | |
12749 | } | |
12750 | ||
12751 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12752 | mips_cprestore_valid = 1; |
252b5132 RH |
12753 | |
12754 | ex.X_op = O_constant; | |
12755 | ex.X_add_symbol = NULL; | |
12756 | ex.X_op_symbol = NULL; | |
12757 | ex.X_add_number = mips_cprestore_offset; | |
12758 | ||
584892a6 | 12759 | macro_start (); |
67c0d1eb RS |
12760 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12761 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12762 | macro_end (); |
252b5132 RH |
12763 | |
12764 | demand_empty_rest_of_line (); | |
12765 | } | |
12766 | ||
6478892d | 12767 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12768 | was given in the preceding .cpsetup, it results in: |
6478892d | 12769 | ld $gp, offset($sp) |
76b3015f | 12770 | |
6478892d | 12771 | If a register $reg2 was given there, it results in: |
609f23f4 | 12772 | daddu $gp, $reg2, $0 |
6478892d TS |
12773 | */ |
12774 | static void | |
17a2f251 | 12775 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12776 | { |
12777 | expressionS ex; | |
6478892d TS |
12778 | |
12779 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12780 | We also need NewABI support. */ | |
12781 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12782 | { | |
12783 | s_ignore (0); | |
12784 | return; | |
12785 | } | |
12786 | ||
584892a6 | 12787 | macro_start (); |
6478892d TS |
12788 | if (mips_cpreturn_register == -1) |
12789 | { | |
12790 | ex.X_op = O_constant; | |
12791 | ex.X_add_symbol = NULL; | |
12792 | ex.X_op_symbol = NULL; | |
12793 | ex.X_add_number = mips_cpreturn_offset; | |
12794 | ||
67c0d1eb | 12795 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12796 | } |
12797 | else | |
67c0d1eb | 12798 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12799 | mips_cpreturn_register, 0); |
584892a6 | 12800 | macro_end (); |
6478892d TS |
12801 | |
12802 | demand_empty_rest_of_line (); | |
12803 | } | |
12804 | ||
12805 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12806 | code. It sets the offset to use in gp_rel relocations. */ | |
12807 | ||
12808 | static void | |
17a2f251 | 12809 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12810 | { |
12811 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12812 | We also need NewABI support. */ | |
12813 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12814 | { | |
12815 | s_ignore (0); | |
12816 | return; | |
12817 | } | |
12818 | ||
def2e0dd | 12819 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12820 | |
12821 | demand_empty_rest_of_line (); | |
12822 | } | |
12823 | ||
252b5132 RH |
12824 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12825 | code. It generates a 32 bit GP relative reloc. */ | |
12826 | ||
12827 | static void | |
17a2f251 | 12828 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12829 | { |
a8dbcb85 TS |
12830 | segment_info_type *si; |
12831 | struct insn_label_list *l; | |
252b5132 RH |
12832 | symbolS *label; |
12833 | expressionS ex; | |
12834 | char *p; | |
12835 | ||
12836 | /* When not generating PIC code, this is treated as .word. */ | |
12837 | if (mips_pic != SVR4_PIC) | |
12838 | { | |
12839 | s_cons (2); | |
12840 | return; | |
12841 | } | |
12842 | ||
a8dbcb85 TS |
12843 | si = seg_info (now_seg); |
12844 | l = si->label_list; | |
12845 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 12846 | mips_emit_delays (); |
252b5132 RH |
12847 | if (auto_align) |
12848 | mips_align (2, 0, label); | |
12849 | mips_clear_insn_labels (); | |
12850 | ||
12851 | expression (&ex); | |
12852 | ||
12853 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12854 | { | |
12855 | as_bad (_("Unsupported use of .gpword")); | |
12856 | ignore_rest_of_line (); | |
12857 | } | |
12858 | ||
12859 | p = frag_more (4); | |
17a2f251 | 12860 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12861 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12862 | BFD_RELOC_GPREL32); |
252b5132 RH |
12863 | |
12864 | demand_empty_rest_of_line (); | |
12865 | } | |
12866 | ||
10181a0d | 12867 | static void |
17a2f251 | 12868 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 12869 | { |
a8dbcb85 TS |
12870 | segment_info_type *si; |
12871 | struct insn_label_list *l; | |
10181a0d AO |
12872 | symbolS *label; |
12873 | expressionS ex; | |
12874 | char *p; | |
12875 | ||
12876 | /* When not generating PIC code, this is treated as .dword. */ | |
12877 | if (mips_pic != SVR4_PIC) | |
12878 | { | |
12879 | s_cons (3); | |
12880 | return; | |
12881 | } | |
12882 | ||
a8dbcb85 TS |
12883 | si = seg_info (now_seg); |
12884 | l = si->label_list; | |
12885 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 12886 | mips_emit_delays (); |
10181a0d AO |
12887 | if (auto_align) |
12888 | mips_align (3, 0, label); | |
12889 | mips_clear_insn_labels (); | |
12890 | ||
12891 | expression (&ex); | |
12892 | ||
12893 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12894 | { | |
12895 | as_bad (_("Unsupported use of .gpdword")); | |
12896 | ignore_rest_of_line (); | |
12897 | } | |
12898 | ||
12899 | p = frag_more (8); | |
17a2f251 | 12900 | md_number_to_chars (p, 0, 8); |
a105a300 | 12901 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12902 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12903 | |
12904 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12905 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12906 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12907 | |
12908 | demand_empty_rest_of_line (); | |
12909 | } | |
12910 | ||
252b5132 RH |
12911 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12912 | tables in SVR4 PIC code. */ | |
12913 | ||
12914 | static void | |
17a2f251 | 12915 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12916 | { |
252b5132 RH |
12917 | int reg; |
12918 | ||
10181a0d AO |
12919 | /* This is ignored when not generating SVR4 PIC code. */ |
12920 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12921 | { |
12922 | s_ignore (0); | |
12923 | return; | |
12924 | } | |
12925 | ||
12926 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12927 | macro_start (); |
252b5132 | 12928 | reg = tc_get_register (0); |
67c0d1eb | 12929 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12930 | macro_end (); |
252b5132 | 12931 | |
bdaaa2e1 | 12932 | demand_empty_rest_of_line (); |
252b5132 RH |
12933 | } |
12934 | ||
12935 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12936 | mips16 mode. This permits the linker to handle them specially, | |
12937 | such as generating jalx instructions when needed. We also make | |
12938 | them odd for the duration of the assembly, in order to generate the | |
12939 | right sort of code. We will make them even in the adjust_symtab | |
12940 | routine, while leaving them marked. This is convenient for the | |
12941 | debugger and the disassembler. The linker knows to make them odd | |
12942 | again. */ | |
12943 | ||
12944 | static void | |
17a2f251 | 12945 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12946 | { |
f9419b05 | 12947 | mips16_mark_labels (); |
252b5132 RH |
12948 | |
12949 | demand_empty_rest_of_line (); | |
12950 | } | |
12951 | ||
12952 | /* Handle a .stabn directive. We need these in order to mark a label | |
12953 | as being a mips16 text label correctly. Sometimes the compiler | |
12954 | will emit a label, followed by a .stabn, and then switch sections. | |
12955 | If the label and .stabn are in mips16 mode, then the label is | |
12956 | really a mips16 text label. */ | |
12957 | ||
12958 | static void | |
17a2f251 | 12959 | s_mips_stab (int type) |
252b5132 | 12960 | { |
f9419b05 | 12961 | if (type == 'n') |
252b5132 RH |
12962 | mips16_mark_labels (); |
12963 | ||
12964 | s_stab (type); | |
12965 | } | |
12966 | ||
12967 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12968 | */ | |
12969 | ||
12970 | static void | |
17a2f251 | 12971 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12972 | { |
12973 | char *name; | |
12974 | int c; | |
12975 | symbolS *symbolP; | |
12976 | expressionS exp; | |
12977 | ||
12978 | name = input_line_pointer; | |
12979 | c = get_symbol_end (); | |
12980 | symbolP = symbol_find_or_make (name); | |
12981 | S_SET_WEAK (symbolP); | |
12982 | *input_line_pointer = c; | |
12983 | ||
12984 | SKIP_WHITESPACE (); | |
12985 | ||
12986 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12987 | { | |
12988 | if (S_IS_DEFINED (symbolP)) | |
12989 | { | |
956cd1d6 | 12990 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12991 | S_GET_NAME (symbolP)); |
12992 | ignore_rest_of_line (); | |
12993 | return; | |
12994 | } | |
bdaaa2e1 | 12995 | |
252b5132 RH |
12996 | if (*input_line_pointer == ',') |
12997 | { | |
12998 | ++input_line_pointer; | |
12999 | SKIP_WHITESPACE (); | |
13000 | } | |
bdaaa2e1 | 13001 | |
252b5132 RH |
13002 | expression (&exp); |
13003 | if (exp.X_op != O_symbol) | |
13004 | { | |
13005 | as_bad ("bad .weakext directive"); | |
98d3f06f | 13006 | ignore_rest_of_line (); |
252b5132 RH |
13007 | return; |
13008 | } | |
49309057 | 13009 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13010 | } |
13011 | ||
13012 | demand_empty_rest_of_line (); | |
13013 | } | |
13014 | ||
13015 | /* Parse a register string into a number. Called from the ECOFF code | |
13016 | to parse .frame. The argument is non-zero if this is the frame | |
13017 | register, so that we can record it in mips_frame_reg. */ | |
13018 | ||
13019 | int | |
17a2f251 | 13020 | tc_get_register (int frame) |
252b5132 | 13021 | { |
707bfff6 | 13022 | unsigned int reg; |
252b5132 RH |
13023 | |
13024 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13025 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13026 | reg = 0; | |
252b5132 | 13027 | if (frame) |
7a621144 DJ |
13028 | { |
13029 | mips_frame_reg = reg != 0 ? reg : SP; | |
13030 | mips_frame_reg_valid = 1; | |
13031 | mips_cprestore_valid = 0; | |
13032 | } | |
252b5132 RH |
13033 | return reg; |
13034 | } | |
13035 | ||
13036 | valueT | |
17a2f251 | 13037 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13038 | { |
13039 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13040 | ||
13041 | #ifdef OBJ_ELF | |
13042 | /* We don't need to align ELF sections to the full alignment. | |
13043 | However, Irix 5 may prefer that we align them at least to a 16 | |
13044 | byte boundary. We don't bother to align the sections if we are | |
13045 | targeted for an embedded system. */ | |
13046 | if (strcmp (TARGET_OS, "elf") == 0) | |
13047 | return addr; | |
13048 | if (align > 4) | |
13049 | align = 4; | |
13050 | #endif | |
13051 | ||
13052 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13053 | } | |
13054 | ||
13055 | /* Utility routine, called from above as well. If called while the | |
13056 | input file is still being read, it's only an approximation. (For | |
13057 | example, a symbol may later become defined which appeared to be | |
13058 | undefined earlier.) */ | |
13059 | ||
13060 | static int | |
17a2f251 | 13061 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13062 | { |
13063 | if (sym == 0) | |
13064 | return 0; | |
13065 | ||
4d0d148d | 13066 | if (g_switch_value > 0) |
252b5132 RH |
13067 | { |
13068 | const char *symname; | |
13069 | int change; | |
13070 | ||
c9914766 | 13071 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13072 | register. It can be if it is smaller than the -G size or if |
13073 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13074 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13075 | they can. */ |
13076 | symname = S_GET_NAME (sym); | |
13077 | if (symname != (const char *) NULL | |
13078 | && (strcmp (symname, "eprol") == 0 | |
13079 | || strcmp (symname, "etext") == 0 | |
13080 | || strcmp (symname, "_gp") == 0 | |
13081 | || strcmp (symname, "edata") == 0 | |
13082 | || strcmp (symname, "_fbss") == 0 | |
13083 | || strcmp (symname, "_fdata") == 0 | |
13084 | || strcmp (symname, "_ftext") == 0 | |
13085 | || strcmp (symname, "end") == 0 | |
13086 | || strcmp (symname, "_gp_disp") == 0)) | |
13087 | change = 1; | |
13088 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13089 | && (0 | |
13090 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13091 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13092 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13093 | <= g_switch_value)) | |
252b5132 RH |
13094 | #endif |
13095 | /* We must defer this decision until after the whole | |
13096 | file has been read, since there might be a .extern | |
13097 | after the first use of this symbol. */ | |
13098 | || (before_relaxing | |
13099 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13100 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13101 | #endif |
13102 | && S_GET_VALUE (sym) == 0) | |
13103 | || (S_GET_VALUE (sym) != 0 | |
13104 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13105 | change = 0; | |
13106 | else | |
13107 | { | |
13108 | const char *segname; | |
13109 | ||
13110 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13111 | assert (strcmp (segname, ".lit8") != 0 | |
13112 | && strcmp (segname, ".lit4") != 0); | |
13113 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13114 | && strcmp (segname, ".sbss") != 0 |
13115 | && strncmp (segname, ".sdata.", 7) != 0 | |
13116 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
13117 | } |
13118 | return change; | |
13119 | } | |
13120 | else | |
c9914766 | 13121 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13122 | return 1; |
13123 | } | |
13124 | ||
5919d012 RS |
13125 | |
13126 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13127 | ||
13128 | static bfd_boolean | |
17a2f251 | 13129 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13130 | { |
13131 | asection *symsec; | |
13132 | bfd_boolean linkonce; | |
13133 | ||
13134 | /* Handle the case of a symbol equated to another symbol. */ | |
13135 | while (symbol_equated_reloc_p (sym)) | |
13136 | { | |
13137 | symbolS *n; | |
13138 | ||
13139 | /* It's possible to get a loop here in a badly written | |
13140 | program. */ | |
13141 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
13142 | if (n == sym) | |
13143 | break; | |
13144 | sym = n; | |
13145 | } | |
13146 | ||
13147 | symsec = S_GET_SEGMENT (sym); | |
13148 | ||
13149 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
13150 | linkonce = FALSE; | |
13151 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
13152 | { | |
13153 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
13154 | != 0) | |
13155 | linkonce = TRUE; | |
13156 | ||
13157 | /* The GNU toolchain uses an extension for ELF: a section | |
13158 | beginning with the magic string .gnu.linkonce is a linkonce | |
13159 | section. */ | |
13160 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
13161 | sizeof ".gnu.linkonce" - 1) == 0) | |
13162 | linkonce = TRUE; | |
13163 | } | |
13164 | ||
13165 | /* This must duplicate the test in adjust_reloc_syms. */ | |
13166 | return (symsec != &bfd_und_section | |
13167 | && symsec != &bfd_abs_section | |
13168 | && ! bfd_is_com_section (symsec) | |
13169 | && !linkonce | |
13170 | #ifdef OBJ_ELF | |
13171 | /* A global or weak symbol is treated as external. */ | |
13172 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 13173 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13174 | #endif |
13175 | ); | |
13176 | } | |
13177 | ||
13178 | ||
252b5132 RH |
13179 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13180 | extended opcode. SEC is the section the frag is in. */ | |
13181 | ||
13182 | static int | |
17a2f251 | 13183 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13184 | { |
13185 | int type; | |
3994f87e | 13186 | const struct mips16_immed_operand *op; |
252b5132 RH |
13187 | offsetT val; |
13188 | int mintiny, maxtiny; | |
13189 | segT symsec; | |
98aa84af | 13190 | fragS *sym_frag; |
252b5132 RH |
13191 | |
13192 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13193 | return 0; | |
13194 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13195 | return 1; | |
13196 | ||
13197 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13198 | op = mips16_immed_operands; | |
13199 | while (op->type != type) | |
13200 | { | |
13201 | ++op; | |
13202 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13203 | } | |
13204 | ||
13205 | if (op->unsp) | |
13206 | { | |
13207 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13208 | { | |
13209 | mintiny = 1; | |
13210 | maxtiny = 1 << op->nbits; | |
13211 | } | |
13212 | else | |
13213 | { | |
13214 | mintiny = 0; | |
13215 | maxtiny = (1 << op->nbits) - 1; | |
13216 | } | |
13217 | } | |
13218 | else | |
13219 | { | |
13220 | mintiny = - (1 << (op->nbits - 1)); | |
13221 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13222 | } | |
13223 | ||
98aa84af | 13224 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13225 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13226 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13227 | |
13228 | if (op->pcrel) | |
13229 | { | |
13230 | addressT addr; | |
13231 | ||
13232 | /* We won't have the section when we are called from | |
13233 | mips_relax_frag. However, we will always have been called | |
13234 | from md_estimate_size_before_relax first. If this is a | |
13235 | branch to a different section, we mark it as such. If SEC is | |
13236 | NULL, and the frag is not marked, then it must be a branch to | |
13237 | the same section. */ | |
13238 | if (sec == NULL) | |
13239 | { | |
13240 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13241 | return 1; | |
13242 | } | |
13243 | else | |
13244 | { | |
98aa84af | 13245 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13246 | if (symsec != sec) |
13247 | { | |
13248 | fragp->fr_subtype = | |
13249 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13250 | ||
13251 | /* FIXME: We should support this, and let the linker | |
13252 | catch branches and loads that are out of range. */ | |
13253 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13254 | _("unsupported PC relative reference to different section")); | |
13255 | ||
13256 | return 1; | |
13257 | } | |
98aa84af AM |
13258 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13259 | /* Assume non-extended on the first relaxation pass. | |
13260 | The address we have calculated will be bogus if this is | |
13261 | a forward branch to another frag, as the forward frag | |
13262 | will have fr_address == 0. */ | |
13263 | return 0; | |
252b5132 RH |
13264 | } |
13265 | ||
13266 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13267 | the same section. If the relax_marker of the symbol fragment |
13268 | differs from the relax_marker of this fragment, we have not | |
13269 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13270 | in STRETCH in order to get a better estimate of the address. |
13271 | This particularly matters because of the shift bits. */ | |
13272 | if (stretch != 0 | |
98aa84af | 13273 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13274 | { |
13275 | fragS *f; | |
13276 | ||
13277 | /* Adjust stretch for any alignment frag. Note that if have | |
13278 | been expanding the earlier code, the symbol may be | |
13279 | defined in what appears to be an earlier frag. FIXME: | |
13280 | This doesn't handle the fr_subtype field, which specifies | |
13281 | a maximum number of bytes to skip when doing an | |
13282 | alignment. */ | |
98aa84af | 13283 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13284 | { |
13285 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13286 | { | |
13287 | if (stretch < 0) | |
13288 | stretch = - ((- stretch) | |
13289 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13290 | else | |
13291 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13292 | if (stretch == 0) | |
13293 | break; | |
13294 | } | |
13295 | } | |
13296 | if (f != NULL) | |
13297 | val += stretch; | |
13298 | } | |
13299 | ||
13300 | addr = fragp->fr_address + fragp->fr_fix; | |
13301 | ||
13302 | /* The base address rules are complicated. The base address of | |
13303 | a branch is the following instruction. The base address of a | |
13304 | PC relative load or add is the instruction itself, but if it | |
13305 | is in a delay slot (in which case it can not be extended) use | |
13306 | the address of the instruction whose delay slot it is in. */ | |
13307 | if (type == 'p' || type == 'q') | |
13308 | { | |
13309 | addr += 2; | |
13310 | ||
13311 | /* If we are currently assuming that this frag should be | |
13312 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13313 | higher. */ |
252b5132 RH |
13314 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13315 | addr += 2; | |
13316 | ||
13317 | /* Ignore the low bit in the target, since it will be set | |
13318 | for a text label. */ | |
13319 | if ((val & 1) != 0) | |
13320 | --val; | |
13321 | } | |
13322 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13323 | addr -= 4; | |
13324 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13325 | addr -= 2; | |
13326 | ||
13327 | val -= addr & ~ ((1 << op->shift) - 1); | |
13328 | ||
13329 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13330 | if (type == 'p' || type == 'q') | |
13331 | val /= 2; | |
13332 | ||
13333 | /* If any of the shifted bits are set, we must use an extended | |
13334 | opcode. If the address depends on the size of this | |
13335 | instruction, this can lead to a loop, so we arrange to always | |
13336 | use an extended opcode. We only check this when we are in | |
13337 | the main relaxation loop, when SEC is NULL. */ | |
13338 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13339 | { | |
13340 | fragp->fr_subtype = | |
13341 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13342 | return 1; | |
13343 | } | |
13344 | ||
13345 | /* If we are about to mark a frag as extended because the value | |
13346 | is precisely maxtiny + 1, then there is a chance of an | |
13347 | infinite loop as in the following code: | |
13348 | la $4,foo | |
13349 | .skip 1020 | |
13350 | .align 2 | |
13351 | foo: | |
13352 | In this case when the la is extended, foo is 0x3fc bytes | |
13353 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13354 | the la must be extended. To avoid this loop, we mark the | |
13355 | frag as extended if it was small, and is about to become | |
13356 | extended with a value of maxtiny + 1. */ | |
13357 | if (val == ((maxtiny + 1) << op->shift) | |
13358 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13359 | && sec == NULL) | |
13360 | { | |
13361 | fragp->fr_subtype = | |
13362 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13363 | return 1; | |
13364 | } | |
13365 | } | |
13366 | else if (symsec != absolute_section && sec != NULL) | |
13367 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13368 | ||
13369 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13370 | || val < (mintiny << op->shift) | |
13371 | || val > (maxtiny << op->shift)) | |
13372 | return 1; | |
13373 | else | |
13374 | return 0; | |
13375 | } | |
13376 | ||
4a6a3df4 AO |
13377 | /* Compute the length of a branch sequence, and adjust the |
13378 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13379 | worst-case length is computed, with UPDATE being used to indicate | |
13380 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13381 | branch is to be computed. */ | |
13382 | static int | |
17a2f251 | 13383 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13384 | { |
b34976b6 | 13385 | bfd_boolean toofar; |
4a6a3df4 AO |
13386 | int length; |
13387 | ||
13388 | if (fragp | |
13389 | && S_IS_DEFINED (fragp->fr_symbol) | |
13390 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13391 | { | |
13392 | addressT addr; | |
13393 | offsetT val; | |
13394 | ||
13395 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13396 | ||
13397 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13398 | ||
13399 | val -= addr; | |
13400 | ||
13401 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13402 | } | |
13403 | else if (fragp) | |
13404 | /* If the symbol is not defined or it's in a different segment, | |
13405 | assume the user knows what's going on and emit a short | |
13406 | branch. */ | |
b34976b6 | 13407 | toofar = FALSE; |
4a6a3df4 | 13408 | else |
b34976b6 | 13409 | toofar = TRUE; |
4a6a3df4 AO |
13410 | |
13411 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13412 | fragp->fr_subtype | |
af6ae2ad | 13413 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13414 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13415 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13416 | toofar); | |
13417 | ||
13418 | length = 4; | |
13419 | if (toofar) | |
13420 | { | |
13421 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13422 | length += 8; | |
13423 | ||
13424 | if (mips_pic != NO_PIC) | |
13425 | { | |
13426 | /* Additional space for PIC loading of target address. */ | |
13427 | length += 8; | |
13428 | if (mips_opts.isa == ISA_MIPS1) | |
13429 | /* Additional space for $at-stabilizing nop. */ | |
13430 | length += 4; | |
13431 | } | |
13432 | ||
13433 | /* If branch is conditional. */ | |
13434 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13435 | length += 8; | |
13436 | } | |
b34976b6 | 13437 | |
4a6a3df4 AO |
13438 | return length; |
13439 | } | |
13440 | ||
252b5132 RH |
13441 | /* Estimate the size of a frag before relaxing. Unless this is the |
13442 | mips16, we are not really relaxing here, and the final size is | |
13443 | encoded in the subtype information. For the mips16, we have to | |
13444 | decide whether we are using an extended opcode or not. */ | |
13445 | ||
252b5132 | 13446 | int |
17a2f251 | 13447 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13448 | { |
5919d012 | 13449 | int change; |
252b5132 | 13450 | |
4a6a3df4 AO |
13451 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13452 | { | |
13453 | ||
b34976b6 AM |
13454 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13455 | ||
4a6a3df4 AO |
13456 | return fragp->fr_var; |
13457 | } | |
13458 | ||
252b5132 | 13459 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13460 | /* We don't want to modify the EXTENDED bit here; it might get us |
13461 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13462 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13463 | |
13464 | if (mips_pic == NO_PIC) | |
5919d012 | 13465 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13466 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13467 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13468 | else if (mips_pic == VXWORKS_PIC) |
13469 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13470 | change = 0; | |
252b5132 RH |
13471 | else |
13472 | abort (); | |
13473 | ||
13474 | if (change) | |
13475 | { | |
4d7206a2 | 13476 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13477 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13478 | } |
4d7206a2 RS |
13479 | else |
13480 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13481 | } |
13482 | ||
13483 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13484 | should be converted into a reloc against a section. */ |
252b5132 RH |
13485 | |
13486 | int | |
17a2f251 | 13487 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13488 | { |
de7e6852 RS |
13489 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
13490 | about the format of the offset in the .o file. */ | |
252b5132 RH |
13491 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
13492 | return 0; | |
a161fe53 | 13493 | |
252b5132 RH |
13494 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13495 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13496 | return 0; | |
a161fe53 | 13497 | |
252b5132 RH |
13498 | if (fixp->fx_addsy == NULL) |
13499 | return 1; | |
a161fe53 | 13500 | |
de7e6852 RS |
13501 | /* If symbol SYM is in a mergeable section, relocations of the form |
13502 | SYM + 0 can usually be made section-relative. The mergeable data | |
13503 | is then identified by the section offset rather than by the symbol. | |
13504 | ||
13505 | However, if we're generating REL LO16 relocations, the offset is split | |
13506 | between the LO16 and parterning high part relocation. The linker will | |
13507 | need to recalculate the complete offset in order to correctly identify | |
13508 | the merge data. | |
13509 | ||
13510 | The linker has traditionally not looked for the parterning high part | |
13511 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13512 | placed anywhere. Rather than break backwards compatibility by changing | |
13513 | this, it seems better not to force the issue, and instead keep the | |
13514 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13515 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13516 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13517 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13518 | && HAVE_IN_PLACE_ADDENDS |
13519 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13520 | return 0; | |
13521 | ||
252b5132 | 13522 | #ifdef OBJ_ELF |
de7e6852 RS |
13523 | /* Don't adjust relocations against mips16 symbols, so that the linker |
13524 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
13525 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
13526 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13527 | && fixp->fx_subsy == NULL) | |
13528 | return 0; | |
13529 | #endif | |
a161fe53 | 13530 | |
252b5132 RH |
13531 | return 1; |
13532 | } | |
13533 | ||
13534 | /* Translate internal representation of relocation info to BFD target | |
13535 | format. */ | |
13536 | ||
13537 | arelent ** | |
17a2f251 | 13538 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13539 | { |
13540 | static arelent *retval[4]; | |
13541 | arelent *reloc; | |
13542 | bfd_reloc_code_real_type code; | |
13543 | ||
4b0cff4e TS |
13544 | memset (retval, 0, sizeof(retval)); |
13545 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13546 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13547 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13548 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13549 | ||
bad36eac DJ |
13550 | if (fixp->fx_pcrel) |
13551 | { | |
13552 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13553 | ||
13554 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13555 | Relocations want only the symbol offset. */ | |
13556 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13557 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13558 | { | |
13559 | /* A gruesome hack which is a result of the gruesome gas | |
13560 | reloc handling. What's worse, for COFF (as opposed to | |
13561 | ECOFF), we might need yet another copy of reloc->address. | |
13562 | See bfd_install_relocation. */ | |
13563 | reloc->addend += reloc->address; | |
13564 | } | |
13565 | } | |
13566 | else | |
13567 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13568 | |
438c16b8 TS |
13569 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13570 | entry to be used in the relocation's section offset. */ | |
13571 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13572 | { |
13573 | reloc->address = reloc->addend; | |
13574 | reloc->addend = 0; | |
13575 | } | |
13576 | ||
252b5132 | 13577 | code = fixp->fx_r_type; |
252b5132 | 13578 | |
bad36eac | 13579 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13580 | if (reloc->howto == NULL) |
13581 | { | |
13582 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13583 | _("Can not represent %s relocation in this object file format"), | |
13584 | bfd_get_reloc_code_name (code)); | |
13585 | retval[0] = NULL; | |
13586 | } | |
13587 | ||
13588 | return retval; | |
13589 | } | |
13590 | ||
13591 | /* Relax a machine dependent frag. This returns the amount by which | |
13592 | the current size of the frag should change. */ | |
13593 | ||
13594 | int | |
17a2f251 | 13595 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13596 | { |
4a6a3df4 AO |
13597 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13598 | { | |
13599 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13600 | |
13601 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13602 | |
13603 | return fragp->fr_var - old_var; | |
13604 | } | |
13605 | ||
252b5132 RH |
13606 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13607 | return 0; | |
13608 | ||
c4e7957c | 13609 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13610 | { |
13611 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13612 | return 0; | |
13613 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13614 | return 2; | |
13615 | } | |
13616 | else | |
13617 | { | |
13618 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13619 | return 0; | |
13620 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13621 | return -2; | |
13622 | } | |
13623 | ||
13624 | return 0; | |
13625 | } | |
13626 | ||
13627 | /* Convert a machine dependent frag. */ | |
13628 | ||
13629 | void | |
17a2f251 | 13630 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13631 | { |
4a6a3df4 AO |
13632 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13633 | { | |
13634 | bfd_byte *buf; | |
13635 | unsigned long insn; | |
13636 | expressionS exp; | |
13637 | fixS *fixp; | |
b34976b6 | 13638 | |
4a6a3df4 AO |
13639 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13640 | ||
13641 | if (target_big_endian) | |
13642 | insn = bfd_getb32 (buf); | |
13643 | else | |
13644 | insn = bfd_getl32 (buf); | |
b34976b6 | 13645 | |
4a6a3df4 AO |
13646 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13647 | { | |
13648 | /* We generate a fixup instead of applying it right now | |
13649 | because, if there are linker relaxations, we're going to | |
13650 | need the relocations. */ | |
13651 | exp.X_op = O_symbol; | |
13652 | exp.X_add_symbol = fragp->fr_symbol; | |
13653 | exp.X_add_number = fragp->fr_offset; | |
13654 | ||
13655 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13656 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13657 | fixp->fx_file = fragp->fr_file; |
13658 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13659 | |
2132e3a3 | 13660 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13661 | buf += 4; |
13662 | } | |
13663 | else | |
13664 | { | |
13665 | int i; | |
13666 | ||
13667 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13668 | _("relaxed out-of-range branch into a jump")); | |
13669 | ||
13670 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13671 | goto uncond; | |
13672 | ||
13673 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13674 | { | |
13675 | /* Reverse the branch. */ | |
13676 | switch ((insn >> 28) & 0xf) | |
13677 | { | |
13678 | case 4: | |
13679 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13680 | have the condition reversed by tweaking a single | |
13681 | bit, and their opcodes all have 0x4???????. */ | |
13682 | assert ((insn & 0xf1000000) == 0x41000000); | |
13683 | insn ^= 0x00010000; | |
13684 | break; | |
13685 | ||
13686 | case 0: | |
13687 | /* bltz 0x04000000 bgez 0x04010000 | |
13688 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13689 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13690 | insn ^= 0x00010000; | |
13691 | break; | |
b34976b6 | 13692 | |
4a6a3df4 AO |
13693 | case 1: |
13694 | /* beq 0x10000000 bne 0x14000000 | |
13695 | blez 0x18000000 bgtz 0x1c000000 */ | |
13696 | insn ^= 0x04000000; | |
13697 | break; | |
13698 | ||
13699 | default: | |
13700 | abort (); | |
13701 | } | |
13702 | } | |
13703 | ||
13704 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13705 | { | |
13706 | /* Clear the and-link bit. */ | |
13707 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13708 | ||
13709 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13710 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13711 | insn &= ~0x00100000; | |
13712 | } | |
13713 | ||
13714 | /* Branch over the branch (if the branch was likely) or the | |
13715 | full jump (not likely case). Compute the offset from the | |
13716 | current instruction to branch to. */ | |
13717 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13718 | i = 16; | |
13719 | else | |
13720 | { | |
13721 | /* How many bytes in instructions we've already emitted? */ | |
13722 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13723 | /* How many bytes in instructions from here to the end? */ | |
13724 | i = fragp->fr_var - i; | |
13725 | } | |
13726 | /* Convert to instruction count. */ | |
13727 | i >>= 2; | |
13728 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13729 | i--; |
4a6a3df4 AO |
13730 | insn |= i; |
13731 | /* Branch over the jump. */ | |
2132e3a3 | 13732 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13733 | buf += 4; |
13734 | ||
13735 | /* Nop */ | |
2132e3a3 | 13736 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13737 | buf += 4; |
13738 | ||
13739 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13740 | { | |
13741 | /* beql $0, $0, 2f */ | |
13742 | insn = 0x50000000; | |
13743 | /* Compute the PC offset from the current instruction to | |
13744 | the end of the variable frag. */ | |
13745 | /* How many bytes in instructions we've already emitted? */ | |
13746 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13747 | /* How many bytes in instructions from here to the end? */ | |
13748 | i = fragp->fr_var - i; | |
13749 | /* Convert to instruction count. */ | |
13750 | i >>= 2; | |
13751 | /* Don't decrement i, because we want to branch over the | |
13752 | delay slot. */ | |
13753 | ||
13754 | insn |= i; | |
2132e3a3 | 13755 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13756 | buf += 4; |
13757 | ||
2132e3a3 | 13758 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13759 | buf += 4; |
13760 | } | |
13761 | ||
13762 | uncond: | |
13763 | if (mips_pic == NO_PIC) | |
13764 | { | |
13765 | /* j or jal. */ | |
13766 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13767 | ? 0x0c000000 : 0x08000000); | |
13768 | exp.X_op = O_symbol; | |
13769 | exp.X_add_symbol = fragp->fr_symbol; | |
13770 | exp.X_add_number = fragp->fr_offset; | |
13771 | ||
13772 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13773 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
13774 | fixp->fx_file = fragp->fr_file; |
13775 | fixp->fx_line = fragp->fr_line; | |
13776 | ||
2132e3a3 | 13777 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13778 | buf += 4; |
13779 | } | |
13780 | else | |
13781 | { | |
13782 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13783 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13784 | exp.X_op = O_symbol; | |
13785 | exp.X_add_symbol = fragp->fr_symbol; | |
13786 | exp.X_add_number = fragp->fr_offset; | |
13787 | ||
13788 | if (fragp->fr_offset) | |
13789 | { | |
13790 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13791 | exp.X_add_number = 0; | |
13792 | } | |
13793 | ||
13794 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13795 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
13796 | fixp->fx_file = fragp->fr_file; |
13797 | fixp->fx_line = fragp->fr_line; | |
13798 | ||
2132e3a3 | 13799 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13800 | buf += 4; |
b34976b6 | 13801 | |
4a6a3df4 AO |
13802 | if (mips_opts.isa == ISA_MIPS1) |
13803 | { | |
13804 | /* nop */ | |
2132e3a3 | 13805 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13806 | buf += 4; |
13807 | } | |
13808 | ||
13809 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13810 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13811 | ||
13812 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13813 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
13814 | fixp->fx_file = fragp->fr_file; |
13815 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13816 | |
2132e3a3 | 13817 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13818 | buf += 4; |
13819 | ||
13820 | /* j(al)r $at. */ | |
13821 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13822 | insn = 0x0020f809; | |
13823 | else | |
13824 | insn = 0x00200008; | |
13825 | ||
2132e3a3 | 13826 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13827 | buf += 4; |
13828 | } | |
13829 | } | |
13830 | ||
13831 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13832 | + fragp->fr_fix + fragp->fr_var); | |
13833 | ||
13834 | fragp->fr_fix += fragp->fr_var; | |
13835 | ||
13836 | return; | |
13837 | } | |
13838 | ||
252b5132 RH |
13839 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13840 | { | |
13841 | int type; | |
3994f87e | 13842 | const struct mips16_immed_operand *op; |
b34976b6 | 13843 | bfd_boolean small, ext; |
252b5132 RH |
13844 | offsetT val; |
13845 | bfd_byte *buf; | |
13846 | unsigned long insn; | |
b34976b6 | 13847 | bfd_boolean use_extend; |
252b5132 RH |
13848 | unsigned short extend; |
13849 | ||
13850 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13851 | op = mips16_immed_operands; | |
13852 | while (op->type != type) | |
13853 | ++op; | |
13854 | ||
13855 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13856 | { | |
b34976b6 AM |
13857 | small = FALSE; |
13858 | ext = TRUE; | |
252b5132 RH |
13859 | } |
13860 | else | |
13861 | { | |
b34976b6 AM |
13862 | small = TRUE; |
13863 | ext = FALSE; | |
252b5132 RH |
13864 | } |
13865 | ||
6386f3a7 | 13866 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13867 | val = S_GET_VALUE (fragp->fr_symbol); |
13868 | if (op->pcrel) | |
13869 | { | |
13870 | addressT addr; | |
13871 | ||
13872 | addr = fragp->fr_address + fragp->fr_fix; | |
13873 | ||
13874 | /* The rules for the base address of a PC relative reloc are | |
13875 | complicated; see mips16_extended_frag. */ | |
13876 | if (type == 'p' || type == 'q') | |
13877 | { | |
13878 | addr += 2; | |
13879 | if (ext) | |
13880 | addr += 2; | |
13881 | /* Ignore the low bit in the target, since it will be | |
13882 | set for a text label. */ | |
13883 | if ((val & 1) != 0) | |
13884 | --val; | |
13885 | } | |
13886 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13887 | addr -= 4; | |
13888 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13889 | addr -= 2; | |
13890 | ||
13891 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13892 | val -= addr; | |
13893 | ||
13894 | /* Make sure the section winds up with the alignment we have | |
13895 | assumed. */ | |
13896 | if (op->shift > 0) | |
13897 | record_alignment (asec, op->shift); | |
13898 | } | |
13899 | ||
13900 | if (ext | |
13901 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13902 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13903 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13904 | _("extended instruction in delay slot")); | |
13905 | ||
13906 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13907 | ||
13908 | if (target_big_endian) | |
13909 | insn = bfd_getb16 (buf); | |
13910 | else | |
13911 | insn = bfd_getl16 (buf); | |
13912 | ||
13913 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13914 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13915 | small, ext, &insn, &use_extend, &extend); | |
13916 | ||
13917 | if (use_extend) | |
13918 | { | |
2132e3a3 | 13919 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13920 | fragp->fr_fix += 2; |
13921 | buf += 2; | |
13922 | } | |
13923 | ||
2132e3a3 | 13924 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13925 | fragp->fr_fix += 2; |
13926 | buf += 2; | |
13927 | } | |
13928 | else | |
13929 | { | |
4d7206a2 RS |
13930 | int first, second; |
13931 | fixS *fixp; | |
252b5132 | 13932 | |
4d7206a2 RS |
13933 | first = RELAX_FIRST (fragp->fr_subtype); |
13934 | second = RELAX_SECOND (fragp->fr_subtype); | |
13935 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13936 | |
584892a6 RS |
13937 | /* Possibly emit a warning if we've chosen the longer option. */ |
13938 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13939 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13940 | { | |
13941 | const char *msg = macro_warning (fragp->fr_subtype); | |
13942 | if (msg != 0) | |
13943 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13944 | } | |
13945 | ||
4d7206a2 RS |
13946 | /* Go through all the fixups for the first sequence. Disable them |
13947 | (by marking them as done) if we're going to use the second | |
13948 | sequence instead. */ | |
13949 | while (fixp | |
13950 | && fixp->fx_frag == fragp | |
13951 | && fixp->fx_where < fragp->fr_fix - second) | |
13952 | { | |
13953 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13954 | fixp->fx_done = 1; | |
13955 | fixp = fixp->fx_next; | |
13956 | } | |
252b5132 | 13957 | |
4d7206a2 RS |
13958 | /* Go through the fixups for the second sequence. Disable them if |
13959 | we're going to use the first sequence, otherwise adjust their | |
13960 | addresses to account for the relaxation. */ | |
13961 | while (fixp && fixp->fx_frag == fragp) | |
13962 | { | |
13963 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13964 | fixp->fx_where -= first; | |
13965 | else | |
13966 | fixp->fx_done = 1; | |
13967 | fixp = fixp->fx_next; | |
13968 | } | |
13969 | ||
13970 | /* Now modify the frag contents. */ | |
13971 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13972 | { | |
13973 | char *start; | |
13974 | ||
13975 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13976 | memmove (start, start + first, second); | |
13977 | fragp->fr_fix -= first; | |
13978 | } | |
13979 | else | |
13980 | fragp->fr_fix -= second; | |
252b5132 RH |
13981 | } |
13982 | } | |
13983 | ||
13984 | #ifdef OBJ_ELF | |
13985 | ||
13986 | /* This function is called after the relocs have been generated. | |
13987 | We've been storing mips16 text labels as odd. Here we convert them | |
13988 | back to even for the convenience of the debugger. */ | |
13989 | ||
13990 | void | |
17a2f251 | 13991 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13992 | { |
13993 | asymbol **syms; | |
13994 | unsigned int count, i; | |
13995 | ||
13996 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13997 | return; | |
13998 | ||
13999 | syms = bfd_get_outsymbols (stdoutput); | |
14000 | count = bfd_get_symcount (stdoutput); | |
14001 | for (i = 0; i < count; i++, syms++) | |
14002 | { | |
14003 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
14004 | && ((*syms)->value & 1) != 0) | |
14005 | { | |
14006 | (*syms)->value &= ~1; | |
14007 | /* If the symbol has an odd size, it was probably computed | |
14008 | incorrectly, so adjust that as well. */ | |
14009 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14010 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14011 | } | |
14012 | } | |
14013 | } | |
14014 | ||
14015 | #endif | |
14016 | ||
14017 | /* This function is called whenever a label is defined. It is used | |
14018 | when handling branch delays; if a branch has a label, we assume we | |
14019 | can not move it. */ | |
14020 | ||
14021 | void | |
17a2f251 | 14022 | mips_define_label (symbolS *sym) |
252b5132 | 14023 | { |
a8dbcb85 | 14024 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14025 | struct insn_label_list *l; |
14026 | ||
14027 | if (free_insn_labels == NULL) | |
14028 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14029 | else | |
14030 | { | |
14031 | l = free_insn_labels; | |
14032 | free_insn_labels = l->next; | |
14033 | } | |
14034 | ||
14035 | l->label = sym; | |
a8dbcb85 TS |
14036 | l->next = si->label_list; |
14037 | si->label_list = l; | |
07a53e5c RH |
14038 | |
14039 | #ifdef OBJ_ELF | |
14040 | dwarf2_emit_label (sym); | |
14041 | #endif | |
252b5132 RH |
14042 | } |
14043 | \f | |
14044 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14045 | ||
14046 | /* Some special processing for a MIPS ELF file. */ | |
14047 | ||
14048 | void | |
17a2f251 | 14049 | mips_elf_final_processing (void) |
252b5132 RH |
14050 | { |
14051 | /* Write out the register information. */ | |
316f5878 | 14052 | if (mips_abi != N64_ABI) |
252b5132 RH |
14053 | { |
14054 | Elf32_RegInfo s; | |
14055 | ||
14056 | s.ri_gprmask = mips_gprmask; | |
14057 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14058 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14059 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14060 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14061 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14062 | ||
14063 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14064 | ((Elf32_External_RegInfo *) | |
14065 | mips_regmask_frag)); | |
14066 | } | |
14067 | else | |
14068 | { | |
14069 | Elf64_Internal_RegInfo s; | |
14070 | ||
14071 | s.ri_gprmask = mips_gprmask; | |
14072 | s.ri_pad = 0; | |
14073 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14074 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14075 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14076 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14077 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14078 | ||
14079 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14080 | ((Elf64_External_RegInfo *) | |
14081 | mips_regmask_frag)); | |
14082 | } | |
14083 | ||
14084 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14085 | sort of BFD interface for this. */ | |
14086 | if (mips_any_noreorder) | |
14087 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14088 | if (mips_pic != NO_PIC) | |
143d77c5 | 14089 | { |
252b5132 | 14090 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14091 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14092 | } | |
14093 | if (mips_abicalls) | |
14094 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14095 | |
98d3f06f | 14096 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14097 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14098 | file_ase_dsp is true. */ | |
ef2e4d86 CF |
14099 | /* We may need to define a new flag for MT ASE, and set this flag when |
14100 | file_ase_mt is true. */ | |
a4672219 TS |
14101 | if (file_ase_mips16) |
14102 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14103 | #if 0 /* XXX FIXME */ |
14104 | if (file_ase_mips3d) | |
14105 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14106 | #endif | |
deec1734 CD |
14107 | if (file_ase_mdmx) |
14108 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14109 | |
bdaaa2e1 | 14110 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14111 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14112 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14113 | else if (mips_abi == O64_ABI) |
252b5132 | 14114 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14115 | else if (mips_abi == EABI_ABI) |
252b5132 | 14116 | { |
316f5878 | 14117 | if (!file_mips_gp32) |
252b5132 RH |
14118 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14119 | else | |
14120 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14121 | } | |
316f5878 | 14122 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14123 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14124 | ||
c9914766 | 14125 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14126 | |
14127 | if (mips_32bitmode) | |
14128 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14129 | |
14130 | #if 0 /* XXX FIXME */ | |
14131 | /* 32 bit code with 64 bit FP registers. */ | |
14132 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14133 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14134 | #endif | |
252b5132 RH |
14135 | } |
14136 | ||
14137 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14138 | \f | |
beae10d5 | 14139 | typedef struct proc { |
9b2f1d35 EC |
14140 | symbolS *func_sym; |
14141 | symbolS *func_end_sym; | |
beae10d5 KH |
14142 | unsigned long reg_mask; |
14143 | unsigned long reg_offset; | |
14144 | unsigned long fpreg_mask; | |
14145 | unsigned long fpreg_offset; | |
14146 | unsigned long frame_offset; | |
14147 | unsigned long frame_reg; | |
14148 | unsigned long pc_reg; | |
14149 | } procS; | |
252b5132 RH |
14150 | |
14151 | static procS cur_proc; | |
14152 | static procS *cur_proc_ptr; | |
14153 | static int numprocs; | |
14154 | ||
0a9ef439 | 14155 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 14156 | |
0a9ef439 | 14157 | void |
17a2f251 | 14158 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14159 | { |
0a9ef439 RH |
14160 | if (fragp->fr_type != rs_align_code) |
14161 | return; | |
14162 | ||
14163 | if (mips_opts.mips16) | |
a19d8eb0 CP |
14164 | { |
14165 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
14166 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
14167 | ||
0a9ef439 RH |
14168 | int bytes; |
14169 | char *p; | |
a19d8eb0 | 14170 | |
0a9ef439 RH |
14171 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14172 | p = fragp->fr_literal + fragp->fr_fix; | |
14173 | ||
14174 | if (bytes & 1) | |
14175 | { | |
14176 | *p++ = 0; | |
f9419b05 | 14177 | fragp->fr_fix++; |
0a9ef439 RH |
14178 | } |
14179 | ||
14180 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14181 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14182 | } |
14183 | ||
0a9ef439 | 14184 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14185 | } |
14186 | ||
252b5132 | 14187 | static void |
17a2f251 | 14188 | md_obj_begin (void) |
252b5132 RH |
14189 | { |
14190 | } | |
14191 | ||
14192 | static void | |
17a2f251 | 14193 | md_obj_end (void) |
252b5132 RH |
14194 | { |
14195 | /* check for premature end, nesting errors, etc */ | |
14196 | if (cur_proc_ptr) | |
9a41af64 | 14197 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14198 | } |
14199 | ||
14200 | static long | |
17a2f251 | 14201 | get_number (void) |
252b5132 RH |
14202 | { |
14203 | int negative = 0; | |
14204 | long val = 0; | |
14205 | ||
14206 | if (*input_line_pointer == '-') | |
14207 | { | |
14208 | ++input_line_pointer; | |
14209 | negative = 1; | |
14210 | } | |
3882b010 | 14211 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14212 | as_bad (_("expected simple number")); |
252b5132 RH |
14213 | if (input_line_pointer[0] == '0') |
14214 | { | |
14215 | if (input_line_pointer[1] == 'x') | |
14216 | { | |
14217 | input_line_pointer += 2; | |
3882b010 | 14218 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14219 | { |
14220 | val <<= 4; | |
14221 | val |= hex_value (*input_line_pointer++); | |
14222 | } | |
14223 | return negative ? -val : val; | |
14224 | } | |
14225 | else | |
14226 | { | |
14227 | ++input_line_pointer; | |
3882b010 | 14228 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14229 | { |
14230 | val <<= 3; | |
14231 | val |= *input_line_pointer++ - '0'; | |
14232 | } | |
14233 | return negative ? -val : val; | |
14234 | } | |
14235 | } | |
3882b010 | 14236 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14237 | { |
14238 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14239 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14240 | as_warn (_("invalid number")); |
252b5132 RH |
14241 | return -1; |
14242 | } | |
3882b010 | 14243 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14244 | { |
14245 | val *= 10; | |
14246 | val += *input_line_pointer++ - '0'; | |
14247 | } | |
14248 | return negative ? -val : val; | |
14249 | } | |
14250 | ||
14251 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14252 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14253 | case .file implies DWARF-2. */ | |
14254 | ||
14255 | static void | |
17a2f251 | 14256 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14257 | { |
ecb4347a DJ |
14258 | static int first_file_directive = 0; |
14259 | ||
c5dd6aab DJ |
14260 | if (ECOFF_DEBUGGING) |
14261 | { | |
14262 | get_number (); | |
14263 | s_app_file (0); | |
14264 | } | |
14265 | else | |
ecb4347a DJ |
14266 | { |
14267 | char *filename; | |
14268 | ||
14269 | filename = dwarf2_directive_file (0); | |
14270 | ||
14271 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14272 | directive even for stabs output. Make sure that this | |
14273 | ".file" is handled. Note that you need a version of GCC | |
14274 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14275 | if (filename != NULL && ! first_file_directive) | |
14276 | { | |
14277 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14278 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14279 | } |
14280 | first_file_directive = 1; | |
14281 | } | |
c5dd6aab DJ |
14282 | } |
14283 | ||
14284 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14285 | |
14286 | static void | |
17a2f251 | 14287 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14288 | { |
c5dd6aab DJ |
14289 | if (!ECOFF_DEBUGGING) |
14290 | dwarf2_directive_loc (0); | |
252b5132 RH |
14291 | } |
14292 | ||
252b5132 RH |
14293 | /* The .end directive. */ |
14294 | ||
14295 | static void | |
17a2f251 | 14296 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14297 | { |
14298 | symbolS *p; | |
252b5132 | 14299 | |
7a621144 DJ |
14300 | /* Following functions need their own .frame and .cprestore directives. */ |
14301 | mips_frame_reg_valid = 0; | |
14302 | mips_cprestore_valid = 0; | |
14303 | ||
252b5132 RH |
14304 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14305 | { | |
14306 | p = get_symbol (); | |
14307 | demand_empty_rest_of_line (); | |
14308 | } | |
14309 | else | |
14310 | p = NULL; | |
14311 | ||
14949570 | 14312 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14313 | as_warn (_(".end not in text section")); |
14314 | ||
14315 | if (!cur_proc_ptr) | |
14316 | { | |
14317 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14318 | demand_empty_rest_of_line (); | |
14319 | return; | |
14320 | } | |
14321 | ||
14322 | if (p != NULL) | |
14323 | { | |
14324 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14325 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14326 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14327 | |
14328 | if (debug_type == DEBUG_STABS) | |
14329 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14330 | S_GET_NAME (p)); | |
252b5132 RH |
14331 | } |
14332 | else | |
14333 | as_warn (_(".end directive missing or unknown symbol")); | |
14334 | ||
2132e3a3 | 14335 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14336 | /* Create an expression to calculate the size of the function. */ |
14337 | if (p && cur_proc_ptr) | |
14338 | { | |
14339 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14340 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14341 | ||
14342 | obj->size = exp; | |
14343 | exp->X_op = O_subtract; | |
14344 | exp->X_add_symbol = symbol_temp_new_now (); | |
14345 | exp->X_op_symbol = p; | |
14346 | exp->X_add_number = 0; | |
14347 | ||
14348 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14349 | } | |
14350 | ||
ecb4347a | 14351 | /* Generate a .pdr section. */ |
dcd410fe RO |
14352 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
14353 | && mips_flag_pdr) | |
ecb4347a DJ |
14354 | { |
14355 | segT saved_seg = now_seg; | |
14356 | subsegT saved_subseg = now_subseg; | |
14357 | valueT dot; | |
14358 | expressionS exp; | |
14359 | char *fragp; | |
252b5132 | 14360 | |
ecb4347a | 14361 | dot = frag_now_fix (); |
252b5132 RH |
14362 | |
14363 | #ifdef md_flush_pending_output | |
ecb4347a | 14364 | md_flush_pending_output (); |
252b5132 RH |
14365 | #endif |
14366 | ||
ecb4347a DJ |
14367 | assert (pdr_seg); |
14368 | subseg_set (pdr_seg, 0); | |
252b5132 | 14369 | |
ecb4347a DJ |
14370 | /* Write the symbol. */ |
14371 | exp.X_op = O_symbol; | |
14372 | exp.X_add_symbol = p; | |
14373 | exp.X_add_number = 0; | |
14374 | emit_expr (&exp, 4); | |
252b5132 | 14375 | |
ecb4347a | 14376 | fragp = frag_more (7 * 4); |
252b5132 | 14377 | |
17a2f251 TS |
14378 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14379 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14380 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14381 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14382 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14383 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14384 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14385 | |
ecb4347a DJ |
14386 | subseg_set (saved_seg, saved_subseg); |
14387 | } | |
14388 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14389 | |
14390 | cur_proc_ptr = NULL; | |
14391 | } | |
14392 | ||
14393 | /* The .aent and .ent directives. */ | |
14394 | ||
14395 | static void | |
17a2f251 | 14396 | s_mips_ent (int aent) |
252b5132 | 14397 | { |
252b5132 | 14398 | symbolS *symbolP; |
252b5132 RH |
14399 | |
14400 | symbolP = get_symbol (); | |
14401 | if (*input_line_pointer == ',') | |
f9419b05 | 14402 | ++input_line_pointer; |
252b5132 | 14403 | SKIP_WHITESPACE (); |
3882b010 | 14404 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14405 | || *input_line_pointer == '-') |
874e8986 | 14406 | get_number (); |
252b5132 | 14407 | |
14949570 | 14408 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14409 | as_warn (_(".ent or .aent not in text section.")); |
14410 | ||
14411 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14412 | as_warn (_("missing .end")); |
252b5132 RH |
14413 | |
14414 | if (!aent) | |
14415 | { | |
7a621144 DJ |
14416 | /* This function needs its own .frame and .cprestore directives. */ |
14417 | mips_frame_reg_valid = 0; | |
14418 | mips_cprestore_valid = 0; | |
14419 | ||
252b5132 RH |
14420 | cur_proc_ptr = &cur_proc; |
14421 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14422 | ||
9b2f1d35 | 14423 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14424 | |
49309057 | 14425 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14426 | |
f9419b05 | 14427 | ++numprocs; |
ecb4347a DJ |
14428 | |
14429 | if (debug_type == DEBUG_STABS) | |
14430 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14431 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14432 | } |
14433 | ||
14434 | demand_empty_rest_of_line (); | |
14435 | } | |
14436 | ||
14437 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14438 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14439 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14440 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14441 | symbol table (in the mdebug section). */ |
14442 | ||
14443 | static void | |
17a2f251 | 14444 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14445 | { |
ecb4347a DJ |
14446 | #ifdef OBJ_ELF |
14447 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14448 | { | |
14449 | long val; | |
252b5132 | 14450 | |
ecb4347a DJ |
14451 | if (cur_proc_ptr == (procS *) NULL) |
14452 | { | |
14453 | as_warn (_(".frame outside of .ent")); | |
14454 | demand_empty_rest_of_line (); | |
14455 | return; | |
14456 | } | |
252b5132 | 14457 | |
ecb4347a DJ |
14458 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14459 | ||
14460 | SKIP_WHITESPACE (); | |
14461 | if (*input_line_pointer++ != ',' | |
14462 | || get_absolute_expression_and_terminator (&val) != ',') | |
14463 | { | |
14464 | as_warn (_("Bad .frame directive")); | |
14465 | --input_line_pointer; | |
14466 | demand_empty_rest_of_line (); | |
14467 | return; | |
14468 | } | |
252b5132 | 14469 | |
ecb4347a DJ |
14470 | cur_proc_ptr->frame_offset = val; |
14471 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14472 | |
252b5132 | 14473 | demand_empty_rest_of_line (); |
252b5132 | 14474 | } |
ecb4347a DJ |
14475 | else |
14476 | #endif /* OBJ_ELF */ | |
14477 | s_ignore (ignore); | |
252b5132 RH |
14478 | } |
14479 | ||
bdaaa2e1 KH |
14480 | /* The .fmask and .mask directives. If the mdebug section is present |
14481 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14482 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14483 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14484 | make reference to the ecoff symbol table (in the mdebug section). */ |
14485 | ||
14486 | static void | |
17a2f251 | 14487 | s_mips_mask (int reg_type) |
252b5132 | 14488 | { |
ecb4347a DJ |
14489 | #ifdef OBJ_ELF |
14490 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14491 | { |
ecb4347a | 14492 | long mask, off; |
252b5132 | 14493 | |
ecb4347a DJ |
14494 | if (cur_proc_ptr == (procS *) NULL) |
14495 | { | |
14496 | as_warn (_(".mask/.fmask outside of .ent")); | |
14497 | demand_empty_rest_of_line (); | |
14498 | return; | |
14499 | } | |
252b5132 | 14500 | |
ecb4347a DJ |
14501 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14502 | { | |
14503 | as_warn (_("Bad .mask/.fmask directive")); | |
14504 | --input_line_pointer; | |
14505 | demand_empty_rest_of_line (); | |
14506 | return; | |
14507 | } | |
252b5132 | 14508 | |
ecb4347a DJ |
14509 | off = get_absolute_expression (); |
14510 | ||
14511 | if (reg_type == 'F') | |
14512 | { | |
14513 | cur_proc_ptr->fpreg_mask = mask; | |
14514 | cur_proc_ptr->fpreg_offset = off; | |
14515 | } | |
14516 | else | |
14517 | { | |
14518 | cur_proc_ptr->reg_mask = mask; | |
14519 | cur_proc_ptr->reg_offset = off; | |
14520 | } | |
14521 | ||
14522 | demand_empty_rest_of_line (); | |
252b5132 RH |
14523 | } |
14524 | else | |
ecb4347a DJ |
14525 | #endif /* OBJ_ELF */ |
14526 | s_ignore (reg_type); | |
252b5132 RH |
14527 | } |
14528 | ||
316f5878 RS |
14529 | /* A table describing all the processors gas knows about. Names are |
14530 | matched in the order listed. | |
e7af610e | 14531 | |
316f5878 RS |
14532 | To ease comparison, please keep this table in the same order as |
14533 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14534 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14535 | { | |
316f5878 | 14536 | /* Entries for generic ISAs */ |
ad3fea08 TS |
14537 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
14538 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
14539 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
14540 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
14541 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
14542 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
14543 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14544 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
14545 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
14546 | |
14547 | /* MIPS I */ | |
ad3fea08 TS |
14548 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
14549 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14550 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
14551 | |
14552 | /* MIPS II */ | |
ad3fea08 | 14553 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
14554 | |
14555 | /* MIPS III */ | |
ad3fea08 TS |
14556 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
14557 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14558 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14559 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
14560 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
14561 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14562 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
14563 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
14564 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14565 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14566 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14567 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
316f5878 RS |
14568 | |
14569 | /* MIPS IV */ | |
ad3fea08 TS |
14570 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
14571 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14572 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14573 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
14574 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
14575 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
14576 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
14577 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14578 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14579 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14580 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14581 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
14582 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
14583 | |
14584 | /* MIPS 32 */ | |
ad3fea08 TS |
14585 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
14586 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14587 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14588 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
14589 | ||
14590 | /* MIPS 32 Release 2 */ | |
14591 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14592 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14593 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14594 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14595 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14596 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14597 | { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14598 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14599 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14600 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14601 | /* 24ke is a 24k with DSP ASE, other ASEs are optional. */ | |
14602 | { "24ke", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14603 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14604 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 14605 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 TS |
14606 | /* 34k is a 24k with MT ASE, other ASEs are optional. */ |
14607 | { "34kc", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14608 | { "34kf", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 14609 | { "34kx", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
32b26a03 | 14610 | |
316f5878 | 14611 | /* MIPS 64 */ |
ad3fea08 TS |
14612 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
14613 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14614 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
14615 | ||
14616 | /* MIPS 64 Release 2 */ | |
14617 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
e7af610e | 14618 | |
c7a23324 | 14619 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
14620 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
14621 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 14622 | |
316f5878 RS |
14623 | /* End marker */ |
14624 | { NULL, 0, 0, 0 } | |
14625 | }; | |
e7af610e | 14626 | |
84ea6cf2 | 14627 | |
316f5878 RS |
14628 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14629 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14630 | |
316f5878 | 14631 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14632 | |
b34976b6 | 14633 | static bfd_boolean |
17a2f251 | 14634 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14635 | { |
14636 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14637 | given++, canonical++; | |
14638 | ||
14639 | return ((*given == 0 && *canonical == 0) | |
14640 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14641 | } | |
14642 | ||
14643 | ||
14644 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14645 | CPU name. We've traditionally allowed a lot of variation here. | |
14646 | ||
14647 | Note: this function is shared between GCC and GAS. */ | |
14648 | ||
b34976b6 | 14649 | static bfd_boolean |
17a2f251 | 14650 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14651 | { |
14652 | /* First see if the name matches exactly, or with a final "000" | |
14653 | turned into "k". */ | |
14654 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14655 | return TRUE; |
316f5878 RS |
14656 | |
14657 | /* If not, try comparing based on numerical designation alone. | |
14658 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14659 | if (TOLOWER (*given) == 'r') | |
14660 | given++; | |
14661 | if (!ISDIGIT (*given)) | |
b34976b6 | 14662 | return FALSE; |
316f5878 RS |
14663 | |
14664 | /* Skip over some well-known prefixes in the canonical name, | |
14665 | hoping to find a number there too. */ | |
14666 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14667 | canonical += 2; | |
14668 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14669 | canonical += 2; | |
14670 | else if (TOLOWER (canonical[0]) == 'r') | |
14671 | canonical += 1; | |
14672 | ||
14673 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14674 | } | |
14675 | ||
14676 | ||
14677 | /* Parse an option that takes the name of a processor as its argument. | |
14678 | OPTION is the name of the option and CPU_STRING is the argument. | |
14679 | Return the corresponding processor enumeration if the CPU_STRING is | |
14680 | recognized, otherwise report an error and return null. | |
14681 | ||
14682 | A similar function exists in GCC. */ | |
e7af610e NC |
14683 | |
14684 | static const struct mips_cpu_info * | |
17a2f251 | 14685 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14686 | { |
316f5878 | 14687 | const struct mips_cpu_info *p; |
e7af610e | 14688 | |
316f5878 RS |
14689 | /* 'from-abi' selects the most compatible architecture for the given |
14690 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14691 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14692 | version. Look first at the -mgp options, if given, otherwise base | |
14693 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14694 | |
316f5878 RS |
14695 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14696 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14697 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14698 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14699 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14700 | { | |
14701 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14702 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14703 | ||
14704 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14705 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14706 | ||
14707 | if (file_mips_gp32 >= 0) | |
14708 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14709 | ||
14710 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14711 | ? ISA_MIPS3 | |
14712 | : ISA_MIPS1); | |
14713 | } | |
14714 | ||
14715 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14716 | if (strcasecmp (cpu_string, "default") == 0) | |
14717 | return 0; | |
14718 | ||
14719 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14720 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14721 | return p; | |
14722 | ||
14723 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14724 | return 0; | |
e7af610e NC |
14725 | } |
14726 | ||
316f5878 RS |
14727 | /* Return the canonical processor information for ISA (a member of the |
14728 | ISA_MIPS* enumeration). */ | |
14729 | ||
e7af610e | 14730 | static const struct mips_cpu_info * |
17a2f251 | 14731 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14732 | { |
14733 | int i; | |
14734 | ||
14735 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 14736 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 14737 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14738 | return (&mips_cpu_info_table[i]); |
14739 | ||
e972090a | 14740 | return NULL; |
e7af610e | 14741 | } |
fef14a42 TS |
14742 | |
14743 | static const struct mips_cpu_info * | |
17a2f251 | 14744 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14745 | { |
14746 | int i; | |
14747 | ||
14748 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14749 | if (arch == mips_cpu_info_table[i].cpu) | |
14750 | return (&mips_cpu_info_table[i]); | |
14751 | ||
14752 | return NULL; | |
14753 | } | |
316f5878 RS |
14754 | \f |
14755 | static void | |
17a2f251 | 14756 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14757 | { |
14758 | if (*first_p) | |
14759 | { | |
14760 | fprintf (stream, "%24s", ""); | |
14761 | *col_p = 24; | |
14762 | } | |
14763 | else | |
14764 | { | |
14765 | fprintf (stream, ", "); | |
14766 | *col_p += 2; | |
14767 | } | |
e7af610e | 14768 | |
316f5878 RS |
14769 | if (*col_p + strlen (string) > 72) |
14770 | { | |
14771 | fprintf (stream, "\n%24s", ""); | |
14772 | *col_p = 24; | |
14773 | } | |
14774 | ||
14775 | fprintf (stream, "%s", string); | |
14776 | *col_p += strlen (string); | |
14777 | ||
14778 | *first_p = 0; | |
14779 | } | |
14780 | ||
14781 | void | |
17a2f251 | 14782 | md_show_usage (FILE *stream) |
e7af610e | 14783 | { |
316f5878 RS |
14784 | int column, first; |
14785 | size_t i; | |
14786 | ||
14787 | fprintf (stream, _("\ | |
14788 | MIPS options:\n\ | |
316f5878 RS |
14789 | -EB generate big endian output\n\ |
14790 | -EL generate little endian output\n\ | |
14791 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14792 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14793 | implicitly with the gp register [default 8]\n")); | |
14794 | fprintf (stream, _("\ | |
14795 | -mips1 generate MIPS ISA I instructions\n\ | |
14796 | -mips2 generate MIPS ISA II instructions\n\ | |
14797 | -mips3 generate MIPS ISA III instructions\n\ | |
14798 | -mips4 generate MIPS ISA IV instructions\n\ | |
14799 | -mips5 generate MIPS ISA V instructions\n\ | |
14800 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14801 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14802 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14803 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14804 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14805 | ||
14806 | first = 1; | |
e7af610e NC |
14807 | |
14808 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14809 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14810 | show (stream, "from-abi", &column, &first); | |
14811 | fputc ('\n', stream); | |
e7af610e | 14812 | |
316f5878 RS |
14813 | fprintf (stream, _("\ |
14814 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14815 | -no-mCPU don't generate code specific to CPU.\n\ | |
14816 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14817 | ||
14818 | first = 1; | |
14819 | ||
14820 | show (stream, "3900", &column, &first); | |
14821 | show (stream, "4010", &column, &first); | |
14822 | show (stream, "4100", &column, &first); | |
14823 | show (stream, "4650", &column, &first); | |
14824 | fputc ('\n', stream); | |
14825 | ||
14826 | fprintf (stream, _("\ | |
14827 | -mips16 generate mips16 instructions\n\ | |
14828 | -no-mips16 do not generate mips16 instructions\n")); | |
14829 | fprintf (stream, _("\ | |
e16bfa71 TS |
14830 | -msmartmips generate smartmips instructions\n\ |
14831 | -mno-smartmips do not generate smartmips instructions\n")); | |
14832 | fprintf (stream, _("\ | |
74cd071d CF |
14833 | -mdsp generate DSP instructions\n\ |
14834 | -mno-dsp do not generate DSP instructions\n")); | |
14835 | fprintf (stream, _("\ | |
ef2e4d86 CF |
14836 | -mmt generate MT instructions\n\ |
14837 | -mno-mt do not generate MT instructions\n")); | |
14838 | fprintf (stream, _("\ | |
d766e8ec | 14839 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 14840 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
14841 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14842 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
14843 | -mno-shared optimize output for executables\n\ |
14844 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
14845 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14846 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14847 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14848 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14849 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14850 | #ifdef OBJ_ELF | |
14851 | fprintf (stream, _("\ | |
14852 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14853 | -non_shared do not generate position independent code\n\ | |
14854 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14855 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14856 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14857 | non-shared code\n\ | |
316f5878 RS |
14858 | -mabi=ABI create ABI conformant object file for:\n")); |
14859 | ||
14860 | first = 1; | |
14861 | ||
14862 | show (stream, "32", &column, &first); | |
14863 | show (stream, "o64", &column, &first); | |
14864 | show (stream, "n32", &column, &first); | |
14865 | show (stream, "64", &column, &first); | |
14866 | show (stream, "eabi", &column, &first); | |
14867 | ||
14868 | fputc ('\n', stream); | |
14869 | ||
14870 | fprintf (stream, _("\ | |
14871 | -32 create o32 ABI object file (default)\n\ | |
14872 | -n32 create n32 ABI object file\n\ | |
14873 | -64 create 64 ABI object file\n")); | |
14874 | #endif | |
e7af610e | 14875 | } |
14e777e0 KB |
14876 | |
14877 | enum dwarf2_format | |
17a2f251 | 14878 | mips_dwarf2_format (void) |
14e777e0 KB |
14879 | { |
14880 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14881 | { |
14882 | #ifdef TE_IRIX | |
14883 | return dwarf2_format_64bit_irix; | |
14884 | #else | |
14885 | return dwarf2_format_64bit; | |
14886 | #endif | |
14887 | } | |
14e777e0 KB |
14888 | else |
14889 | return dwarf2_format_32bit; | |
14890 | } | |
73369e65 EC |
14891 | |
14892 | int | |
14893 | mips_dwarf2_addr_size (void) | |
14894 | { | |
14895 | if (mips_abi == N64_ABI) | |
14896 | return 8; | |
73369e65 EC |
14897 | else |
14898 | return 4; | |
14899 | } | |
5862107c EC |
14900 | |
14901 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
14902 | void | |
14903 | mips_cfi_frame_initial_instructions (void) | |
14904 | { | |
14905 | cfi_add_CFA_def_cfa_register (SP); | |
14906 | } | |
14907 | ||
707bfff6 TS |
14908 | int |
14909 | tc_mips_regname_to_dw2regnum (char *regname) | |
14910 | { | |
14911 | unsigned int regnum = -1; | |
14912 | unsigned int reg; | |
14913 | ||
14914 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
14915 | regnum = reg; | |
14916 | ||
14917 | return regnum; | |
14918 | } |