gas/
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
CommitLineData
252b5132 1/* tc-mips.c -- assemble code for a MIPS chip.
81912461 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
e407c74b 3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
c67a084a 4 Free Software Foundation, Inc.
252b5132
RH
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 Support.
9
10 This file is part of GAS.
11
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
ec2655a6 14 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH
15 any later version.
16
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 02110-1301, USA. */
252b5132
RH
26
27#include "as.h"
28#include "config.h"
29#include "subsegs.h"
3882b010 30#include "safe-ctype.h"
252b5132 31
252b5132
RH
32#include "opcode/mips.h"
33#include "itbl-ops.h"
c5dd6aab 34#include "dwarf2dbg.h"
5862107c 35#include "dw2gencfi.h"
252b5132 36
42429eac
RS
37/* Check assumptions made in this file. */
38typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40
252b5132
RH
41#ifdef DEBUG
42#define DBG(x) printf x
43#else
44#define DBG(x)
45#endif
46
9e12b7a2
RS
47#define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
49
252b5132 50/* Clean up namespace so we can include obj-elf.h too. */
17a2f251
TS
51static int mips_output_flavor (void);
52static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
252b5132
RH
53#undef OBJ_PROCESS_STAB
54#undef OUTPUT_FLAVOR
55#undef S_GET_ALIGN
56#undef S_GET_SIZE
57#undef S_SET_ALIGN
58#undef S_SET_SIZE
252b5132
RH
59#undef obj_frob_file
60#undef obj_frob_file_after_relocs
61#undef obj_frob_symbol
62#undef obj_pop_insert
63#undef obj_sec_sym_ok_for_reloc
64#undef OBJ_COPY_SYMBOL_ATTRIBUTES
65
66#include "obj-elf.h"
67/* Fix any of them that we actually care about. */
68#undef OUTPUT_FLAVOR
69#define OUTPUT_FLAVOR mips_output_flavor()
252b5132 70
252b5132 71#include "elf/mips.h"
252b5132
RH
72
73#ifndef ECOFF_DEBUGGING
74#define NO_ECOFF_DEBUGGING
75#define ECOFF_DEBUGGING 0
76#endif
77
ecb4347a
DJ
78int mips_flag_mdebug = -1;
79
dcd410fe
RO
80/* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
83#ifdef TE_IRIX
84int mips_flag_pdr = FALSE;
85#else
86int mips_flag_pdr = TRUE;
87#endif
88
252b5132
RH
89#include "ecoff.h"
90
252b5132 91static char *mips_regmask_frag;
252b5132 92
85b51719 93#define ZERO 0
741fe287 94#define ATREG 1
df58fc94
RS
95#define S0 16
96#define S7 23
252b5132
RH
97#define TREG 24
98#define PIC_CALL_REG 25
99#define KT0 26
100#define KT1 27
101#define GP 28
102#define SP 29
103#define FP 30
104#define RA 31
105
106#define ILLEGAL_REG (32)
107
741fe287
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108#define AT mips_opts.at
109
252b5132
RH
110extern int target_big_endian;
111
252b5132 112/* The name of the readonly data section. */
e8044f35 113#define RDATA_SECTION_NAME ".rodata"
252b5132 114
a4e06468
RS
115/* Ways in which an instruction can be "appended" to the output. */
116enum append_method {
117 /* Just add it normally. */
118 APPEND_ADD,
119
120 /* Add it normally and then add a nop. */
121 APPEND_ADD_WITH_NOP,
122
123 /* Turn an instruction with a delay slot into a "compact" version. */
124 APPEND_ADD_COMPACT,
125
126 /* Insert the instruction before the last one. */
127 APPEND_SWAP
128};
129
47e39b9d
RS
130/* Information about an instruction, including its format, operands
131 and fixups. */
132struct mips_cl_insn
133{
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
136
47e39b9d 137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
5c04167a
RS
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
140 extension. */
47e39b9d
RS
141 unsigned long insn_opcode;
142
143 /* The frag that contains the instruction. */
144 struct frag *frag;
145
146 /* The offset into FRAG of the first instruction byte. */
147 long where;
148
149 /* The relocs associated with the instruction, if any. */
150 fixS *fixp[3];
151
a38419a5
RS
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
47e39b9d 154
708587a4 155 /* True if this instruction occurred in a .set noreorder block. */
47e39b9d
RS
156 unsigned int noreorder_p : 1;
157
2fa15973
RS
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
15be625d
CM
160
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
e407c74b
NC
163
164 /* True if this instruction is cleared from history by unconditional
165 branch. */
166 unsigned int cleared_p : 1;
47e39b9d
RS
167};
168
a325df1d
TS
169/* The ABI to use. */
170enum mips_abi_level
171{
172 NO_ABI = 0,
173 O32_ABI,
174 O64_ABI,
175 N32_ABI,
176 N64_ABI,
177 EABI_ABI
178};
179
180/* MIPS ABI we are using for this output file. */
316f5878 181static enum mips_abi_level mips_abi = NO_ABI;
a325df1d 182
143d77c5
EC
183/* Whether or not we have code that can call pic code. */
184int mips_abicalls = FALSE;
185
aa6975fb
ILT
186/* Whether or not we have code which can be put into a shared
187 library. */
188static bfd_boolean mips_in_shared = TRUE;
189
252b5132
RH
190/* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
192 reliable. */
193
e972090a
NC
194struct mips_set_options
195{
252b5132
RH
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
199 int isa;
846ef2d0
RS
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
202 architecture. */
203 int ase;
252b5132
RH
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
208 int mips16;
df58fc94
RS
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
213 int micromips;
252b5132
RH
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
216 int noreorder;
741fe287
MR
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
221 unsigned int at;
252b5132
RH
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
224 `.set macro'. */
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
228 int nomove;
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
232 nobopt'. */
233 int nobopt;
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
236 int noautoextend;
833794fc
MR
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
240 bfd_boolean insn32;
a325df1d
TS
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
244 int gp32;
245 int fp32;
fef14a42
TS
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
248 int arch;
aed1a261
RS
249 /* True if ".set sym32" is in effect. */
250 bfd_boolean sym32;
037b32b9
AN
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
255
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
252b5132
RH
260};
261
037b32b9
AN
262/* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
265
a325df1d 266/* True if -mgp32 was passed. */
a8e8e863 267static int file_mips_gp32 = -1;
a325df1d
TS
268
269/* True if -mfp32 was passed. */
a8e8e863 270static int file_mips_fp32 = -1;
a325df1d 271
037b32b9
AN
272/* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273static int file_mips_soft_float = 0;
274
275/* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276static int file_mips_single_float = 0;
252b5132 277
ba92f887
MR
278/* True if -mnan=2008, false if -mnan=legacy. */
279static bfd_boolean mips_flag_nan2008 = FALSE;
280
e972090a
NC
281static struct mips_set_options mips_opts =
282{
846ef2d0 283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
b015e599 284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
833794fc
MR
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
b015e599 287 /* soft_float */ FALSE, /* single_float */ FALSE
e7af610e 288};
252b5132 289
846ef2d0
RS
290/* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292static unsigned int file_ase;
293
294/* Which bits of file_ase were explicitly set or cleared by ASE options. */
295static unsigned int file_ase_explicit;
296
252b5132
RH
297/* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
299 place. */
300unsigned long mips_gprmask;
301unsigned long mips_cprmask[4];
302
303/* MIPS ISA we are using for this output file. */
e7af610e 304static int file_mips_isa = ISA_UNKNOWN;
252b5132 305
738f4d98 306/* True if any MIPS16 code was produced. */
a4672219
TS
307static int file_ase_mips16;
308
3994f87e
TS
309#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
313
df58fc94
RS
314/* True if any microMIPS code was produced. */
315static int file_ase_micromips;
316
b12dd2e4
CF
317/* True if we want to create R_MIPS_JALR for jalr $25. */
318#ifdef TE_IRIX
1180b5a4 319#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
b12dd2e4 320#else
1180b5a4
RS
321/* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324#define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
b12dd2e4
CF
327#endif
328
ec68c924 329/* The argument of the -march= flag. The architecture we are assembling. */
fef14a42 330static int file_mips_arch = CPU_UNKNOWN;
316f5878 331static const char *mips_arch_string;
ec68c924
EC
332
333/* The argument of the -mtune= flag. The architecture for which we
334 are optimizing. */
335static int mips_tune = CPU_UNKNOWN;
316f5878 336static const char *mips_tune_string;
ec68c924 337
316f5878 338/* True when generating 32-bit code for a 64-bit processor. */
252b5132
RH
339static int mips_32bitmode = 0;
340
316f5878
RS
341/* True if the given ABI requires 32-bit registers. */
342#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
343
344/* Likewise 64-bit registers. */
707bfff6
TS
345#define ABI_NEEDS_64BIT_REGS(ABI) \
346 ((ABI) == N32_ABI \
347 || (ABI) == N64_ABI \
316f5878
RS
348 || (ABI) == O64_ABI)
349
ad3fea08 350/* Return true if ISA supports 64 bit wide gp registers. */
707bfff6
TS
351#define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
9ce8a5dd 357
ad3fea08
TS
358/* Return true if ISA supports 64 bit wide float registers. */
359#define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
366
af7ee8bf
CD
367/* Return true if ISA supports 64-bit right rotate (dror et al.)
368 instructions. */
707bfff6 369#define ISA_HAS_DROR(ISA) \
df58fc94
RS
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
373 )
af7ee8bf
CD
374
375/* Return true if ISA supports 32-bit right rotate (ror et al.)
376 instructions. */
707bfff6
TS
377#define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
846ef2d0 380 || (mips_opts.ase & ASE_SMARTMIPS) \
df58fc94
RS
381 || mips_opts.micromips \
382 )
707bfff6 383
7455baf8
TS
384/* Return true if ISA supports single-precision floats in odd registers. */
385#define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
af7ee8bf 390
ad3fea08
TS
391/* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393#define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
396
e013f690 397#define HAVE_32BIT_GPRS \
ad3fea08 398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
ca4e0257 399
e013f690 400#define HAVE_32BIT_FPRS \
ad3fea08 401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
ca4e0257 402
ad3fea08
TS
403#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
ca4e0257 405
316f5878 406#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
e013f690 407
316f5878 408#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
e013f690 409
3b91255e
RS
410/* True if relocations are stored in-place. */
411#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
412
aed1a261
RS
413/* The ABI-derived address size. */
414#define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
e013f690 417
aed1a261
RS
418/* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420#define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
ca4e0257 423
b7c7d6c1
TS
424/* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
f899b4b8 427#define ADDRESS_ADD_INSN \
b7c7d6c1 428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
f899b4b8
TS
429
430#define ADDRESS_ADDI_INSN \
b7c7d6c1 431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
f899b4b8
TS
432
433#define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
435
436#define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
438
a4672219 439/* Return true if the given CPU supports the MIPS16 ASE. */
3396de36
TS
440#define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
a4672219 443
2309ddf2 444/* Return true if the given CPU supports the microMIPS ASE. */
df58fc94
RS
445#define CPU_HAS_MICROMIPS(cpu) 0
446
60b63b72
RS
447/* True if CPU has a dror instruction. */
448#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
449
450/* True if CPU has a ror instruction. */
451#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
452
dd6a37e7 453/* True if CPU is in the Octeon family */
432233b3 454#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
dd6a37e7 455
dd3cbb7e 456/* True if CPU has seq/sne and seqi/snei instructions. */
dd6a37e7 457#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
dd3cbb7e 458
0aa27725
RS
459/* True, if CPU has support for ldc1 and sdc1. */
460#define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
462
c8978940
CD
463/* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
465
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475#define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
e407c74b 481 || mips_opts.arch == CPU_R5900 \
c8978940
CD
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
3aa3176b
TS
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
c8978940 486 || mips_opts.arch == CPU_RM7000 \
c8978940 487 || mips_opts.arch == CPU_VR5500 \
df58fc94 488 || mips_opts.micromips \
c8978940 489 )
252b5132
RH
490
491/* Whether the processor uses hardware interlocks to protect reads
81912461
ILT
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
df58fc94
RS
495 level I and microMIPS mode instructions are always interlocked. */
496#define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
e407c74b 499 || mips_opts.arch == CPU_R5900 \
df58fc94
RS
500 || mips_opts.micromips \
501 )
252b5132 502
81912461
ILT
503/* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
df58fc94
RS
509 levels I, II, and III and microMIPS mode instructions are always
510 interlocked. */
bdaaa2e1 511/* Itbl support may require additional care here. */
81912461
ILT
512#define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
df58fc94 517 || mips_opts.micromips \
81912461
ILT
518 )
519
520/* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
df58fc94
RS
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526#define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
529 )
252b5132 530
6b76fefe
CM
531/* Is this a mfhi or mflo instruction? */
532#define MF_HILO_INSN(PINFO) \
b19e8a9b
AN
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
534
df58fc94
RS
535/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538#define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
540
42429eac
RS
541/* The minimum and maximum signed values that can be stored in a GPR. */
542#define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543#define GPR_SMIN (-GPR_SMAX - 1)
544
252b5132
RH
545/* MIPS PIC level. */
546
a161fe53 547enum mips_pic_level mips_pic;
252b5132 548
c9914766 549/* 1 if we should generate 32 bit offsets from the $gp register in
252b5132 550 SVR4_PIC mode. Currently has no meaning in other modes. */
c9914766 551static int mips_big_got = 0;
252b5132
RH
552
553/* 1 if trap instructions should used for overflow rather than break
554 instructions. */
c9914766 555static int mips_trap = 0;
252b5132 556
119d663a 557/* 1 if double width floating point constants should not be constructed
b6ff326e 558 by assembling two single width halves into two single width floating
119d663a
NC
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
d547a75e 561 in the status register, and the setting of this bit cannot be determined
119d663a
NC
562 automatically at assemble time. */
563static int mips_disable_float_construction;
564
252b5132
RH
565/* Non-zero if any .set noreorder directives were used. */
566
567static int mips_any_noreorder;
568
6b76fefe
CM
569/* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571static int mips_7000_hilo_fix;
572
02ffd3e4 573/* The size of objects in the small data section. */
156c2f8b 574static unsigned int g_switch_value = 8;
252b5132
RH
575/* Whether the -G option was used. */
576static int g_switch_seen = 0;
577
578#define N_RMASK 0xc4
579#define N_VFP 0xd4
580
581/* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
584 better.
585
586 This function can only provide a guess, but it seems to work for
fba2b7f9
GK
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
589 delay slot.
252b5132
RH
590
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
17a2f251 593static int nopic_need_relax (symbolS *, int);
252b5132
RH
594
595/* handle of the OPCODE hash table */
596static struct hash_control *op_hash = NULL;
597
598/* The opcode hash table we use for the mips16. */
599static struct hash_control *mips16_op_hash = NULL;
600
df58fc94
RS
601/* The opcode hash table we use for the microMIPS ASE. */
602static struct hash_control *micromips_op_hash = NULL;
603
252b5132
RH
604/* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606const char comment_chars[] = "#";
607
608/* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611/* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
bdaaa2e1 613 #NO_APP at the beginning of its output. */
252b5132
RH
614/* Also note that C style comments are always supported. */
615const char line_comment_chars[] = "#";
616
bdaaa2e1 617/* This array holds machine specific line separator characters. */
63a0b638 618const char line_separator_chars[] = ";";
252b5132
RH
619
620/* Chars that can be used to separate mant from exp in floating point nums */
621const char EXP_CHARS[] = "eE";
622
623/* Chars that mean this number is a floating point constant */
624/* As in 0f12.456 */
625/* or 0d1.2345e12 */
626const char FLT_CHARS[] = "rRsSfFdDxXpP";
627
628/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
631 */
632
e3de51ce
RS
633/* Types of printf format used for instruction-related error messages.
634 "I" means int ("%d") and "S" means string ("%s"). */
635enum mips_insn_error_format {
636 ERR_FMT_PLAIN,
637 ERR_FMT_I,
638 ERR_FMT_SS,
639};
640
641/* Information about an error that was found while assembling the current
642 instruction. */
643struct mips_insn_error {
644 /* We sometimes need to match an instruction against more than one
645 opcode table entry. Errors found during this matching are reported
646 against a particular syntactic argument rather than against the
647 instruction as a whole. We grade these messages so that errors
648 against argument N have a greater priority than an error against
649 any argument < N, since the former implies that arguments up to N
650 were acceptable and that the opcode entry was therefore a closer match.
651 If several matches report an error against the same argument,
652 we only use that error if it is the same in all cases.
653
654 min_argnum is the minimum argument number for which an error message
655 should be accepted. It is 0 if MSG is against the instruction as
656 a whole. */
657 int min_argnum;
658
659 /* The printf()-style message, including its format and arguments. */
660 enum mips_insn_error_format format;
661 const char *msg;
662 union {
663 int i;
664 const char *ss[2];
665 } u;
666};
667
668/* The error that should be reported for the current instruction. */
669static struct mips_insn_error insn_error;
252b5132
RH
670
671static int auto_align = 1;
672
673/* When outputting SVR4 PIC code, the assembler needs to know the
674 offset in the stack frame from which to restore the $gp register.
675 This is set by the .cprestore pseudo-op, and saved in this
676 variable. */
677static offsetT mips_cprestore_offset = -1;
678
67c1ffbe 679/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
6478892d 680 more optimizations, it can use a register value instead of a memory-saved
956cd1d6 681 offset and even an other register than $gp as global pointer. */
6478892d
TS
682static offsetT mips_cpreturn_offset = -1;
683static int mips_cpreturn_register = -1;
684static int mips_gp_register = GP;
def2e0dd 685static int mips_gprel_offset = 0;
6478892d 686
7a621144
DJ
687/* Whether mips_cprestore_offset has been set in the current function
688 (or whether it has already been warned about, if not). */
689static int mips_cprestore_valid = 0;
690
252b5132
RH
691/* This is the register which holds the stack frame, as set by the
692 .frame pseudo-op. This is needed to implement .cprestore. */
693static int mips_frame_reg = SP;
694
7a621144
DJ
695/* Whether mips_frame_reg has been set in the current function
696 (or whether it has already been warned about, if not). */
697static int mips_frame_reg_valid = 0;
698
252b5132
RH
699/* To output NOP instructions correctly, we need to keep information
700 about the previous two instructions. */
701
702/* Whether we are optimizing. The default value of 2 means to remove
703 unneeded NOPs and swap branch instructions when possible. A value
704 of 1 means to not swap branches. A value of 0 means to always
705 insert NOPs. */
706static int mips_optimize = 2;
707
708/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
709 equivalent to seeing no -g option at all. */
710static int mips_debug = 0;
711
7d8e00cf
RS
712/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
713#define MAX_VR4130_NOPS 4
714
715/* The maximum number of NOPs needed to fill delay slots. */
716#define MAX_DELAY_NOPS 2
717
718/* The maximum number of NOPs needed for any purpose. */
719#define MAX_NOPS 4
71400594
RS
720
721/* A list of previous instructions, with index 0 being the most recent.
722 We need to look back MAX_NOPS instructions when filling delay slots
723 or working around processor errata. We need to look back one
724 instruction further if we're thinking about using history[0] to
725 fill a branch delay slot. */
726static struct mips_cl_insn history[1 + MAX_NOPS];
252b5132 727
fc76e730 728/* Arrays of operands for each instruction. */
14daeee3 729#define MAX_OPERANDS 6
fc76e730
RS
730struct mips_operand_array {
731 const struct mips_operand *operand[MAX_OPERANDS];
732};
733static struct mips_operand_array *mips_operands;
734static struct mips_operand_array *mips16_operands;
735static struct mips_operand_array *micromips_operands;
736
1e915849 737/* Nop instructions used by emit_nop. */
df58fc94
RS
738static struct mips_cl_insn nop_insn;
739static struct mips_cl_insn mips16_nop_insn;
740static struct mips_cl_insn micromips_nop16_insn;
741static struct mips_cl_insn micromips_nop32_insn;
1e915849
RS
742
743/* The appropriate nop for the current mode. */
833794fc
MR
744#define NOP_INSN (mips_opts.mips16 \
745 ? &mips16_nop_insn \
746 : (mips_opts.micromips \
747 ? (mips_opts.insn32 \
748 ? &micromips_nop32_insn \
749 : &micromips_nop16_insn) \
750 : &nop_insn))
df58fc94
RS
751
752/* The size of NOP_INSN in bytes. */
833794fc
MR
753#define NOP_INSN_SIZE ((mips_opts.mips16 \
754 || (mips_opts.micromips && !mips_opts.insn32)) \
755 ? 2 : 4)
252b5132 756
252b5132
RH
757/* If this is set, it points to a frag holding nop instructions which
758 were inserted before the start of a noreorder section. If those
759 nops turn out to be unnecessary, the size of the frag can be
760 decreased. */
761static fragS *prev_nop_frag;
762
763/* The number of nop instructions we created in prev_nop_frag. */
764static int prev_nop_frag_holds;
765
766/* The number of nop instructions that we know we need in
bdaaa2e1 767 prev_nop_frag. */
252b5132
RH
768static int prev_nop_frag_required;
769
770/* The number of instructions we've seen since prev_nop_frag. */
771static int prev_nop_frag_since;
772
e8044f35
RS
773/* Relocations against symbols are sometimes done in two parts, with a HI
774 relocation and a LO relocation. Each relocation has only 16 bits of
775 space to store an addend. This means that in order for the linker to
776 handle carries correctly, it must be able to locate both the HI and
777 the LO relocation. This means that the relocations must appear in
778 order in the relocation table.
252b5132
RH
779
780 In order to implement this, we keep track of each unmatched HI
781 relocation. We then sort them so that they immediately precede the
bdaaa2e1 782 corresponding LO relocation. */
252b5132 783
e972090a
NC
784struct mips_hi_fixup
785{
252b5132
RH
786 /* Next HI fixup. */
787 struct mips_hi_fixup *next;
788 /* This fixup. */
789 fixS *fixp;
790 /* The section this fixup is in. */
791 segT seg;
792};
793
794/* The list of unmatched HI relocs. */
795
796static struct mips_hi_fixup *mips_hi_fixup_list;
797
64bdfcaf
RS
798/* The frag containing the last explicit relocation operator.
799 Null if explicit relocations have not been used. */
800
801static fragS *prev_reloc_op_frag;
802
252b5132
RH
803/* Map mips16 register numbers to normal MIPS register numbers. */
804
e972090a
NC
805static const unsigned int mips16_to_32_reg_map[] =
806{
252b5132
RH
807 16, 17, 2, 3, 4, 5, 6, 7
808};
60b63b72 809
df58fc94
RS
810/* Map microMIPS register numbers to normal MIPS register numbers. */
811
df58fc94 812#define micromips_to_32_reg_d_map mips16_to_32_reg_map
df58fc94
RS
813
814/* The microMIPS registers with type h. */
e76ff5ab 815static const unsigned int micromips_to_32_reg_h_map1[] =
df58fc94
RS
816{
817 5, 5, 6, 4, 4, 4, 4, 4
818};
e76ff5ab 819static const unsigned int micromips_to_32_reg_h_map2[] =
df58fc94
RS
820{
821 6, 7, 7, 21, 22, 5, 6, 7
822};
823
df58fc94
RS
824/* The microMIPS registers with type m. */
825static const unsigned int micromips_to_32_reg_m_map[] =
826{
827 0, 17, 2, 3, 16, 18, 19, 20
828};
829
830#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
831
71400594
RS
832/* Classifies the kind of instructions we're interested in when
833 implementing -mfix-vr4120. */
c67a084a
NC
834enum fix_vr4120_class
835{
71400594
RS
836 FIX_VR4120_MACC,
837 FIX_VR4120_DMACC,
838 FIX_VR4120_MULT,
839 FIX_VR4120_DMULT,
840 FIX_VR4120_DIV,
841 FIX_VR4120_MTHILO,
842 NUM_FIX_VR4120_CLASSES
843};
844
c67a084a
NC
845/* ...likewise -mfix-loongson2f-jump. */
846static bfd_boolean mips_fix_loongson2f_jump;
847
848/* ...likewise -mfix-loongson2f-nop. */
849static bfd_boolean mips_fix_loongson2f_nop;
850
851/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
852static bfd_boolean mips_fix_loongson2f;
853
71400594
RS
854/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
855 there must be at least one other instruction between an instruction
856 of type X and an instruction of type Y. */
857static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
858
859/* True if -mfix-vr4120 is in force. */
d766e8ec 860static int mips_fix_vr4120;
4a6a3df4 861
7d8e00cf
RS
862/* ...likewise -mfix-vr4130. */
863static int mips_fix_vr4130;
864
6a32d874
CM
865/* ...likewise -mfix-24k. */
866static int mips_fix_24k;
867
d954098f
DD
868/* ...likewise -mfix-cn63xxp1 */
869static bfd_boolean mips_fix_cn63xxp1;
870
4a6a3df4
AO
871/* We don't relax branches by default, since this causes us to expand
872 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
873 fail to compute the offset before expanding the macro to the most
874 efficient expansion. */
875
876static int mips_relax_branch;
252b5132 877\f
4d7206a2
RS
878/* The expansion of many macros depends on the type of symbol that
879 they refer to. For example, when generating position-dependent code,
880 a macro that refers to a symbol may have two different expansions,
881 one which uses GP-relative addresses and one which uses absolute
882 addresses. When generating SVR4-style PIC, a macro may have
883 different expansions for local and global symbols.
884
885 We handle these situations by generating both sequences and putting
886 them in variant frags. In position-dependent code, the first sequence
887 will be the GP-relative one and the second sequence will be the
888 absolute one. In SVR4 PIC, the first sequence will be for global
889 symbols and the second will be for local symbols.
890
584892a6
RS
891 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
892 SECOND are the lengths of the two sequences in bytes. These fields
893 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
894 the subtype has the following flags:
4d7206a2 895
584892a6
RS
896 RELAX_USE_SECOND
897 Set if it has been decided that we should use the second
898 sequence instead of the first.
899
900 RELAX_SECOND_LONGER
901 Set in the first variant frag if the macro's second implementation
902 is longer than its first. This refers to the macro as a whole,
903 not an individual relaxation.
904
905 RELAX_NOMACRO
906 Set in the first variant frag if the macro appeared in a .set nomacro
907 block and if one alternative requires a warning but the other does not.
908
909 RELAX_DELAY_SLOT
910 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
911 delay slot.
4d7206a2 912
df58fc94
RS
913 RELAX_DELAY_SLOT_16BIT
914 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
915 16-bit instruction.
916
917 RELAX_DELAY_SLOT_SIZE_FIRST
918 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
919 the macro is of the wrong size for the branch delay slot.
920
921 RELAX_DELAY_SLOT_SIZE_SECOND
922 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
923 the macro is of the wrong size for the branch delay slot.
924
4d7206a2
RS
925 The frag's "opcode" points to the first fixup for relaxable code.
926
927 Relaxable macros are generated using a sequence such as:
928
929 relax_start (SYMBOL);
930 ... generate first expansion ...
931 relax_switch ();
932 ... generate second expansion ...
933 relax_end ();
934
935 The code and fixups for the unwanted alternative are discarded
936 by md_convert_frag. */
584892a6 937#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
4d7206a2 938
584892a6
RS
939#define RELAX_FIRST(X) (((X) >> 8) & 0xff)
940#define RELAX_SECOND(X) ((X) & 0xff)
941#define RELAX_USE_SECOND 0x10000
942#define RELAX_SECOND_LONGER 0x20000
943#define RELAX_NOMACRO 0x40000
944#define RELAX_DELAY_SLOT 0x80000
df58fc94
RS
945#define RELAX_DELAY_SLOT_16BIT 0x100000
946#define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
947#define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
252b5132 948
4a6a3df4
AO
949/* Branch without likely bit. If label is out of range, we turn:
950
951 beq reg1, reg2, label
952 delay slot
953
954 into
955
956 bne reg1, reg2, 0f
957 nop
958 j label
959 0: delay slot
960
961 with the following opcode replacements:
962
963 beq <-> bne
964 blez <-> bgtz
965 bltz <-> bgez
966 bc1f <-> bc1t
967
968 bltzal <-> bgezal (with jal label instead of j label)
969
970 Even though keeping the delay slot instruction in the delay slot of
971 the branch would be more efficient, it would be very tricky to do
972 correctly, because we'd have to introduce a variable frag *after*
973 the delay slot instruction, and expand that instead. Let's do it
974 the easy way for now, even if the branch-not-taken case now costs
975 one additional instruction. Out-of-range branches are not supposed
976 to be common, anyway.
977
978 Branch likely. If label is out of range, we turn:
979
980 beql reg1, reg2, label
981 delay slot (annulled if branch not taken)
982
983 into
984
985 beql reg1, reg2, 1f
986 nop
987 beql $0, $0, 2f
988 nop
989 1: j[al] label
990 delay slot (executed only if branch taken)
991 2:
992
993 It would be possible to generate a shorter sequence by losing the
994 likely bit, generating something like:
b34976b6 995
4a6a3df4
AO
996 bne reg1, reg2, 0f
997 nop
998 j[al] label
999 delay slot (executed only if branch taken)
1000 0:
1001
1002 beql -> bne
1003 bnel -> beq
1004 blezl -> bgtz
1005 bgtzl -> blez
1006 bltzl -> bgez
1007 bgezl -> bltz
1008 bc1fl -> bc1t
1009 bc1tl -> bc1f
1010
1011 bltzall -> bgezal (with jal label instead of j label)
1012 bgezall -> bltzal (ditto)
1013
1014
1015 but it's not clear that it would actually improve performance. */
66b3e8da
MR
1016#define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1017 ((relax_substateT) \
1018 (0xc0000000 \
1019 | ((at) & 0x1f) \
1020 | ((toofar) ? 0x20 : 0) \
1021 | ((link) ? 0x40 : 0) \
1022 | ((likely) ? 0x80 : 0) \
1023 | ((uncond) ? 0x100 : 0)))
4a6a3df4 1024#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
66b3e8da
MR
1025#define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1026#define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1027#define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1028#define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1029#define RELAX_BRANCH_AT(i) ((i) & 0x1f)
4a6a3df4 1030
252b5132
RH
1031/* For mips16 code, we use an entirely different form of relaxation.
1032 mips16 supports two versions of most instructions which take
1033 immediate values: a small one which takes some small value, and a
1034 larger one which takes a 16 bit value. Since branches also follow
1035 this pattern, relaxing these values is required.
1036
1037 We can assemble both mips16 and normal MIPS code in a single
1038 object. Therefore, we need to support this type of relaxation at
1039 the same time that we support the relaxation described above. We
1040 use the high bit of the subtype field to distinguish these cases.
1041
1042 The information we store for this type of relaxation is the
1043 argument code found in the opcode file for this relocation, whether
1044 the user explicitly requested a small or extended form, and whether
1045 the relocation is in a jump or jal delay slot. That tells us the
1046 size of the value, and how it should be stored. We also store
1047 whether the fragment is considered to be extended or not. We also
1048 store whether this is known to be a branch to a different section,
1049 whether we have tried to relax this frag yet, and whether we have
1050 ever extended a PC relative fragment because of a shift count. */
1051#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1052 (0x80000000 \
1053 | ((type) & 0xff) \
1054 | ((small) ? 0x100 : 0) \
1055 | ((ext) ? 0x200 : 0) \
1056 | ((dslot) ? 0x400 : 0) \
1057 | ((jal_dslot) ? 0x800 : 0))
4a6a3df4 1058#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
252b5132
RH
1059#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1060#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1061#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1062#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1063#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1064#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1065#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1066#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1067#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1068#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1069#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
885add95 1070
df58fc94
RS
1071/* For microMIPS code, we use relaxation similar to one we use for
1072 MIPS16 code. Some instructions that take immediate values support
1073 two encodings: a small one which takes some small value, and a
1074 larger one which takes a 16 bit value. As some branches also follow
1075 this pattern, relaxing these values is required.
1076
1077 We can assemble both microMIPS and normal MIPS code in a single
1078 object. Therefore, we need to support this type of relaxation at
1079 the same time that we support the relaxation described above. We
1080 use one of the high bits of the subtype field to distinguish these
1081 cases.
1082
1083 The information we store for this type of relaxation is the argument
1084 code found in the opcode file for this relocation, the register
40209cad
MR
1085 selected as the assembler temporary, whether the branch is
1086 unconditional, whether it is compact, whether it stores the link
1087 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1088 branches to a sequence of instructions is enabled, and whether the
1089 displacement of a branch is too large to fit as an immediate argument
1090 of a 16-bit and a 32-bit branch, respectively. */
1091#define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1092 relax32, toofar16, toofar32) \
1093 (0x40000000 \
1094 | ((type) & 0xff) \
1095 | (((at) & 0x1f) << 8) \
1096 | ((uncond) ? 0x2000 : 0) \
1097 | ((compact) ? 0x4000 : 0) \
1098 | ((link) ? 0x8000 : 0) \
1099 | ((relax32) ? 0x10000 : 0) \
1100 | ((toofar16) ? 0x20000 : 0) \
1101 | ((toofar32) ? 0x40000 : 0))
df58fc94
RS
1102#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1103#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1104#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
40209cad
MR
1105#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1106#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1107#define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1108#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1109
1110#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1111#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1112#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1113#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1114#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1115#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
df58fc94 1116
43c0598f
RS
1117/* Sign-extend 16-bit value X. */
1118#define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1119
885add95
CD
1120/* Is the given value a sign-extended 32-bit value? */
1121#define IS_SEXT_32BIT_NUM(x) \
1122 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1123 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1124
1125/* Is the given value a sign-extended 16-bit value? */
1126#define IS_SEXT_16BIT_NUM(x) \
1127 (((x) &~ (offsetT) 0x7fff) == 0 \
1128 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1129
df58fc94
RS
1130/* Is the given value a sign-extended 12-bit value? */
1131#define IS_SEXT_12BIT_NUM(x) \
1132 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1133
7f3c4072
CM
1134/* Is the given value a sign-extended 9-bit value? */
1135#define IS_SEXT_9BIT_NUM(x) \
1136 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1137
2051e8c4
MR
1138/* Is the given value a zero-extended 32-bit value? Or a negated one? */
1139#define IS_ZEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0xffffffff) == 0 \
1141 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1142
bf12938e
RS
1143/* Extract bits MASK << SHIFT from STRUCT and shift them right
1144 SHIFT places. */
1145#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1146 (((STRUCT) >> (SHIFT)) & (MASK))
1147
bf12938e 1148/* Extract the operand given by FIELD from mips_cl_insn INSN. */
df58fc94
RS
1149#define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1150 (!(MICROMIPS) \
1151 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1152 : EXTRACT_BITS ((INSN).insn_opcode, \
1153 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
bf12938e
RS
1154#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1155 EXTRACT_BITS ((INSN).insn_opcode, \
1156 MIPS16OP_MASK_##FIELD, \
1157 MIPS16OP_SH_##FIELD)
5c04167a
RS
1158
1159/* The MIPS16 EXTEND opcode, shifted left 16 places. */
1160#define MIPS16_EXTEND (0xf000U << 16)
4d7206a2 1161\f
df58fc94
RS
1162/* Whether or not we are emitting a branch-likely macro. */
1163static bfd_boolean emit_branch_likely_macro = FALSE;
1164
4d7206a2
RS
1165/* Global variables used when generating relaxable macros. See the
1166 comment above RELAX_ENCODE for more details about how relaxation
1167 is used. */
1168static struct {
1169 /* 0 if we're not emitting a relaxable macro.
1170 1 if we're emitting the first of the two relaxation alternatives.
1171 2 if we're emitting the second alternative. */
1172 int sequence;
1173
1174 /* The first relaxable fixup in the current frag. (In other words,
1175 the first fixup that refers to relaxable code.) */
1176 fixS *first_fixup;
1177
1178 /* sizes[0] says how many bytes of the first alternative are stored in
1179 the current frag. Likewise sizes[1] for the second alternative. */
1180 unsigned int sizes[2];
1181
1182 /* The symbol on which the choice of sequence depends. */
1183 symbolS *symbol;
1184} mips_relax;
252b5132 1185\f
584892a6
RS
1186/* Global variables used to decide whether a macro needs a warning. */
1187static struct {
1188 /* True if the macro is in a branch delay slot. */
1189 bfd_boolean delay_slot_p;
1190
df58fc94
RS
1191 /* Set to the length in bytes required if the macro is in a delay slot
1192 that requires a specific length of instruction, otherwise zero. */
1193 unsigned int delay_slot_length;
1194
584892a6
RS
1195 /* For relaxable macros, sizes[0] is the length of the first alternative
1196 in bytes and sizes[1] is the length of the second alternative.
1197 For non-relaxable macros, both elements give the length of the
1198 macro in bytes. */
1199 unsigned int sizes[2];
1200
df58fc94
RS
1201 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1202 instruction of the first alternative in bytes and first_insn_sizes[1]
1203 is the length of the first instruction of the second alternative.
1204 For non-relaxable macros, both elements give the length of the first
1205 instruction in bytes.
1206
1207 Set to zero if we haven't yet seen the first instruction. */
1208 unsigned int first_insn_sizes[2];
1209
1210 /* For relaxable macros, insns[0] is the number of instructions for the
1211 first alternative and insns[1] is the number of instructions for the
1212 second alternative.
1213
1214 For non-relaxable macros, both elements give the number of
1215 instructions for the macro. */
1216 unsigned int insns[2];
1217
584892a6
RS
1218 /* The first variant frag for this macro. */
1219 fragS *first_frag;
1220} mips_macro_warning;
1221\f
252b5132
RH
1222/* Prototypes for static functions. */
1223
252b5132
RH
1224enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1225
b34976b6 1226static void append_insn
df58fc94
RS
1227 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1228 bfd_boolean expansionp);
7d10b47d 1229static void mips_no_prev_insn (void);
c67a084a 1230static void macro_build (expressionS *, const char *, const char *, ...);
b34976b6 1231static void mips16_macro_build
03ea81db 1232 (expressionS *, const char *, const char *, va_list *);
67c0d1eb 1233static void load_register (int, expressionS *, int);
584892a6
RS
1234static void macro_start (void);
1235static void macro_end (void);
833794fc 1236static void macro (struct mips_cl_insn *ip, char *str);
17a2f251 1237static void mips16_macro (struct mips_cl_insn * ip);
17a2f251
TS
1238static void mips_ip (char *str, struct mips_cl_insn * ip);
1239static void mips16_ip (char *str, struct mips_cl_insn * ip);
b34976b6 1240static void mips16_immed
43c0598f
RS
1241 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1242 unsigned int, unsigned long *);
5e0116d5 1243static size_t my_getSmallExpression
17a2f251
TS
1244 (expressionS *, bfd_reloc_code_real_type *, char *);
1245static void my_getExpression (expressionS *, char *);
1246static void s_align (int);
1247static void s_change_sec (int);
1248static void s_change_section (int);
1249static void s_cons (int);
1250static void s_float_cons (int);
1251static void s_mips_globl (int);
1252static void s_option (int);
1253static void s_mipsset (int);
1254static void s_abicalls (int);
1255static void s_cpload (int);
1256static void s_cpsetup (int);
1257static void s_cplocal (int);
1258static void s_cprestore (int);
1259static void s_cpreturn (int);
741d6ea8
JM
1260static void s_dtprelword (int);
1261static void s_dtpreldword (int);
d0f13682
CLT
1262static void s_tprelword (int);
1263static void s_tpreldword (int);
17a2f251
TS
1264static void s_gpvalue (int);
1265static void s_gpword (int);
1266static void s_gpdword (int);
a3f278e2 1267static void s_ehword (int);
17a2f251
TS
1268static void s_cpadd (int);
1269static void s_insn (int);
ba92f887 1270static void s_nan (int);
17a2f251
TS
1271static void md_obj_begin (void);
1272static void md_obj_end (void);
1273static void s_mips_ent (int);
1274static void s_mips_end (int);
1275static void s_mips_frame (int);
1276static void s_mips_mask (int reg_type);
1277static void s_mips_stab (int);
1278static void s_mips_weakext (int);
1279static void s_mips_file (int);
1280static void s_mips_loc (int);
1281static bfd_boolean pic_need_relax (symbolS *, asection *);
4a6a3df4 1282static int relaxed_branch_length (fragS *, asection *, int);
df58fc94
RS
1283static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1284static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
e7af610e
NC
1285
1286/* Table and functions used to map between CPU/ISA names, and
1287 ISA levels, and CPU numbers. */
1288
e972090a
NC
1289struct mips_cpu_info
1290{
e7af610e 1291 const char *name; /* CPU or ISA name. */
d16afab6
RS
1292 int flags; /* MIPS_CPU_* flags. */
1293 int ase; /* Set of ASEs implemented by the CPU. */
e7af610e
NC
1294 int isa; /* ISA level. */
1295 int cpu; /* CPU number (default CPU if ISA). */
1296};
1297
ad3fea08 1298#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
ad3fea08 1299
17a2f251
TS
1300static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1301static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1302static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
252b5132 1303\f
c31f3936
RS
1304/* Command-line options. */
1305const char *md_shortopts = "O::g::G:";
1306
1307enum options
1308 {
1309 OPTION_MARCH = OPTION_MD_BASE,
1310 OPTION_MTUNE,
1311 OPTION_MIPS1,
1312 OPTION_MIPS2,
1313 OPTION_MIPS3,
1314 OPTION_MIPS4,
1315 OPTION_MIPS5,
1316 OPTION_MIPS32,
1317 OPTION_MIPS64,
1318 OPTION_MIPS32R2,
1319 OPTION_MIPS64R2,
1320 OPTION_MIPS16,
1321 OPTION_NO_MIPS16,
1322 OPTION_MIPS3D,
1323 OPTION_NO_MIPS3D,
1324 OPTION_MDMX,
1325 OPTION_NO_MDMX,
1326 OPTION_DSP,
1327 OPTION_NO_DSP,
1328 OPTION_MT,
1329 OPTION_NO_MT,
1330 OPTION_VIRT,
1331 OPTION_NO_VIRT,
1332 OPTION_SMARTMIPS,
1333 OPTION_NO_SMARTMIPS,
1334 OPTION_DSPR2,
1335 OPTION_NO_DSPR2,
1336 OPTION_EVA,
1337 OPTION_NO_EVA,
1338 OPTION_MICROMIPS,
1339 OPTION_NO_MICROMIPS,
1340 OPTION_MCU,
1341 OPTION_NO_MCU,
1342 OPTION_COMPAT_ARCH_BASE,
1343 OPTION_M4650,
1344 OPTION_NO_M4650,
1345 OPTION_M4010,
1346 OPTION_NO_M4010,
1347 OPTION_M4100,
1348 OPTION_NO_M4100,
1349 OPTION_M3900,
1350 OPTION_NO_M3900,
1351 OPTION_M7000_HILO_FIX,
1352 OPTION_MNO_7000_HILO_FIX,
1353 OPTION_FIX_24K,
1354 OPTION_NO_FIX_24K,
1355 OPTION_FIX_LOONGSON2F_JUMP,
1356 OPTION_NO_FIX_LOONGSON2F_JUMP,
1357 OPTION_FIX_LOONGSON2F_NOP,
1358 OPTION_NO_FIX_LOONGSON2F_NOP,
1359 OPTION_FIX_VR4120,
1360 OPTION_NO_FIX_VR4120,
1361 OPTION_FIX_VR4130,
1362 OPTION_NO_FIX_VR4130,
1363 OPTION_FIX_CN63XXP1,
1364 OPTION_NO_FIX_CN63XXP1,
1365 OPTION_TRAP,
1366 OPTION_BREAK,
1367 OPTION_EB,
1368 OPTION_EL,
1369 OPTION_FP32,
1370 OPTION_GP32,
1371 OPTION_CONSTRUCT_FLOATS,
1372 OPTION_NO_CONSTRUCT_FLOATS,
1373 OPTION_FP64,
1374 OPTION_GP64,
1375 OPTION_RELAX_BRANCH,
1376 OPTION_NO_RELAX_BRANCH,
833794fc
MR
1377 OPTION_INSN32,
1378 OPTION_NO_INSN32,
c31f3936
RS
1379 OPTION_MSHARED,
1380 OPTION_MNO_SHARED,
1381 OPTION_MSYM32,
1382 OPTION_MNO_SYM32,
1383 OPTION_SOFT_FLOAT,
1384 OPTION_HARD_FLOAT,
1385 OPTION_SINGLE_FLOAT,
1386 OPTION_DOUBLE_FLOAT,
1387 OPTION_32,
c31f3936
RS
1388 OPTION_CALL_SHARED,
1389 OPTION_CALL_NONPIC,
1390 OPTION_NON_SHARED,
1391 OPTION_XGOT,
1392 OPTION_MABI,
1393 OPTION_N32,
1394 OPTION_64,
1395 OPTION_MDEBUG,
1396 OPTION_NO_MDEBUG,
1397 OPTION_PDR,
1398 OPTION_NO_PDR,
1399 OPTION_MVXWORKS_PIC,
ba92f887 1400 OPTION_NAN,
c31f3936
RS
1401 OPTION_END_OF_ENUM
1402 };
1403
1404struct option md_longopts[] =
1405{
1406 /* Options which specify architecture. */
1407 {"march", required_argument, NULL, OPTION_MARCH},
1408 {"mtune", required_argument, NULL, OPTION_MTUNE},
1409 {"mips0", no_argument, NULL, OPTION_MIPS1},
1410 {"mips1", no_argument, NULL, OPTION_MIPS1},
1411 {"mips2", no_argument, NULL, OPTION_MIPS2},
1412 {"mips3", no_argument, NULL, OPTION_MIPS3},
1413 {"mips4", no_argument, NULL, OPTION_MIPS4},
1414 {"mips5", no_argument, NULL, OPTION_MIPS5},
1415 {"mips32", no_argument, NULL, OPTION_MIPS32},
1416 {"mips64", no_argument, NULL, OPTION_MIPS64},
1417 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1418 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1419
1420 /* Options which specify Application Specific Extensions (ASEs). */
1421 {"mips16", no_argument, NULL, OPTION_MIPS16},
1422 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1423 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1424 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1425 {"mdmx", no_argument, NULL, OPTION_MDMX},
1426 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1427 {"mdsp", no_argument, NULL, OPTION_DSP},
1428 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1429 {"mmt", no_argument, NULL, OPTION_MT},
1430 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1431 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1432 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1433 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1434 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1435 {"meva", no_argument, NULL, OPTION_EVA},
1436 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1437 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1438 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1439 {"mmcu", no_argument, NULL, OPTION_MCU},
1440 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1441 {"mvirt", no_argument, NULL, OPTION_VIRT},
1442 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1443
1444 /* Old-style architecture options. Don't add more of these. */
1445 {"m4650", no_argument, NULL, OPTION_M4650},
1446 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1447 {"m4010", no_argument, NULL, OPTION_M4010},
1448 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1449 {"m4100", no_argument, NULL, OPTION_M4100},
1450 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1451 {"m3900", no_argument, NULL, OPTION_M3900},
1452 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1453
1454 /* Options which enable bug fixes. */
1455 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1456 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1457 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1458 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1459 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1460 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1461 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1462 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1463 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1464 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1465 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1466 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1467 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1468 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1469 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1470
1471 /* Miscellaneous options. */
1472 {"trap", no_argument, NULL, OPTION_TRAP},
1473 {"no-break", no_argument, NULL, OPTION_TRAP},
1474 {"break", no_argument, NULL, OPTION_BREAK},
1475 {"no-trap", no_argument, NULL, OPTION_BREAK},
1476 {"EB", no_argument, NULL, OPTION_EB},
1477 {"EL", no_argument, NULL, OPTION_EL},
1478 {"mfp32", no_argument, NULL, OPTION_FP32},
1479 {"mgp32", no_argument, NULL, OPTION_GP32},
1480 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1481 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1482 {"mfp64", no_argument, NULL, OPTION_FP64},
1483 {"mgp64", no_argument, NULL, OPTION_GP64},
1484 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1485 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
833794fc
MR
1486 {"minsn32", no_argument, NULL, OPTION_INSN32},
1487 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
c31f3936
RS
1488 {"mshared", no_argument, NULL, OPTION_MSHARED},
1489 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1490 {"msym32", no_argument, NULL, OPTION_MSYM32},
1491 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1492 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1493 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1494 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1495 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1496
1497 /* Strictly speaking this next option is ELF specific,
1498 but we allow it for other ports as well in order to
1499 make testing easier. */
1500 {"32", no_argument, NULL, OPTION_32},
1501
1502 /* ELF-specific options. */
c31f3936
RS
1503 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1504 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1505 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1506 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1507 {"xgot", no_argument, NULL, OPTION_XGOT},
1508 {"mabi", required_argument, NULL, OPTION_MABI},
1509 {"n32", no_argument, NULL, OPTION_N32},
1510 {"64", no_argument, NULL, OPTION_64},
1511 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1512 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1513 {"mpdr", no_argument, NULL, OPTION_PDR},
1514 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1515 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
ba92f887 1516 {"mnan", required_argument, NULL, OPTION_NAN},
c31f3936
RS
1517
1518 {NULL, no_argument, NULL, 0}
1519};
1520size_t md_longopts_size = sizeof (md_longopts);
1521\f
c6278170
RS
1522/* Information about either an Application Specific Extension or an
1523 optional architecture feature that, for simplicity, we treat in the
1524 same way as an ASE. */
1525struct mips_ase
1526{
1527 /* The name of the ASE, used in both the command-line and .set options. */
1528 const char *name;
1529
1530 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1531 and 64-bit architectures, the flags here refer to the subset that
1532 is available on both. */
1533 unsigned int flags;
1534
1535 /* The ASE_* flag used for instructions that are available on 64-bit
1536 architectures but that are not included in FLAGS. */
1537 unsigned int flags64;
1538
1539 /* The command-line options that turn the ASE on and off. */
1540 int option_on;
1541 int option_off;
1542
1543 /* The minimum required architecture revisions for MIPS32, MIPS64,
1544 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1545 int mips32_rev;
1546 int mips64_rev;
1547 int micromips32_rev;
1548 int micromips64_rev;
1549};
1550
1551/* A table of all supported ASEs. */
1552static const struct mips_ase mips_ases[] = {
1553 { "dsp", ASE_DSP, ASE_DSP64,
1554 OPTION_DSP, OPTION_NO_DSP,
1555 2, 2, 2, 2 },
1556
1557 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1558 OPTION_DSPR2, OPTION_NO_DSPR2,
1559 2, 2, 2, 2 },
1560
1561 { "eva", ASE_EVA, 0,
1562 OPTION_EVA, OPTION_NO_EVA,
1563 2, 2, 2, 2 },
1564
1565 { "mcu", ASE_MCU, 0,
1566 OPTION_MCU, OPTION_NO_MCU,
1567 2, 2, 2, 2 },
1568
1569 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1570 { "mdmx", ASE_MDMX, 0,
1571 OPTION_MDMX, OPTION_NO_MDMX,
1572 -1, 1, -1, -1 },
1573
1574 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1575 { "mips3d", ASE_MIPS3D, 0,
1576 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1577 2, 1, -1, -1 },
1578
1579 { "mt", ASE_MT, 0,
1580 OPTION_MT, OPTION_NO_MT,
1581 2, 2, -1, -1 },
1582
1583 { "smartmips", ASE_SMARTMIPS, 0,
1584 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1585 1, -1, -1, -1 },
1586
1587 { "virt", ASE_VIRT, ASE_VIRT64,
1588 OPTION_VIRT, OPTION_NO_VIRT,
1589 2, 2, 2, 2 }
1590};
1591
1592/* The set of ASEs that require -mfp64. */
1593#define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1594
1595/* Groups of ASE_* flags that represent different revisions of an ASE. */
1596static const unsigned int mips_ase_groups[] = {
1597 ASE_DSP | ASE_DSPR2
1598};
1599\f
252b5132
RH
1600/* Pseudo-op table.
1601
1602 The following pseudo-ops from the Kane and Heinrich MIPS book
1603 should be defined here, but are currently unsupported: .alias,
1604 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1605
1606 The following pseudo-ops from the Kane and Heinrich MIPS book are
1607 specific to the type of debugging information being generated, and
1608 should be defined by the object format: .aent, .begin, .bend,
1609 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1610 .vreg.
1611
1612 The following pseudo-ops from the Kane and Heinrich MIPS book are
1613 not MIPS CPU specific, but are also not specific to the object file
1614 format. This file is probably the best place to define them, but
d84bcf09 1615 they are not currently supported: .asm0, .endr, .lab, .struct. */
252b5132 1616
e972090a
NC
1617static const pseudo_typeS mips_pseudo_table[] =
1618{
beae10d5 1619 /* MIPS specific pseudo-ops. */
252b5132
RH
1620 {"option", s_option, 0},
1621 {"set", s_mipsset, 0},
1622 {"rdata", s_change_sec, 'r'},
1623 {"sdata", s_change_sec, 's'},
1624 {"livereg", s_ignore, 0},
1625 {"abicalls", s_abicalls, 0},
1626 {"cpload", s_cpload, 0},
6478892d
TS
1627 {"cpsetup", s_cpsetup, 0},
1628 {"cplocal", s_cplocal, 0},
252b5132 1629 {"cprestore", s_cprestore, 0},
6478892d 1630 {"cpreturn", s_cpreturn, 0},
741d6ea8
JM
1631 {"dtprelword", s_dtprelword, 0},
1632 {"dtpreldword", s_dtpreldword, 0},
d0f13682
CLT
1633 {"tprelword", s_tprelword, 0},
1634 {"tpreldword", s_tpreldword, 0},
6478892d 1635 {"gpvalue", s_gpvalue, 0},
252b5132 1636 {"gpword", s_gpword, 0},
10181a0d 1637 {"gpdword", s_gpdword, 0},
a3f278e2 1638 {"ehword", s_ehword, 0},
252b5132
RH
1639 {"cpadd", s_cpadd, 0},
1640 {"insn", s_insn, 0},
ba92f887 1641 {"nan", s_nan, 0},
252b5132 1642
beae10d5 1643 /* Relatively generic pseudo-ops that happen to be used on MIPS
252b5132 1644 chips. */
38a57ae7 1645 {"asciiz", stringer, 8 + 1},
252b5132
RH
1646 {"bss", s_change_sec, 'b'},
1647 {"err", s_err, 0},
1648 {"half", s_cons, 1},
1649 {"dword", s_cons, 3},
1650 {"weakext", s_mips_weakext, 0},
7c752c2a
TS
1651 {"origin", s_org, 0},
1652 {"repeat", s_rept, 0},
252b5132 1653
998b3c36
MR
1654 /* For MIPS this is non-standard, but we define it for consistency. */
1655 {"sbss", s_change_sec, 'B'},
1656
beae10d5 1657 /* These pseudo-ops are defined in read.c, but must be overridden
252b5132
RH
1658 here for one reason or another. */
1659 {"align", s_align, 0},
1660 {"byte", s_cons, 0},
1661 {"data", s_change_sec, 'd'},
1662 {"double", s_float_cons, 'd'},
1663 {"float", s_float_cons, 'f'},
1664 {"globl", s_mips_globl, 0},
1665 {"global", s_mips_globl, 0},
1666 {"hword", s_cons, 1},
1667 {"int", s_cons, 2},
1668 {"long", s_cons, 2},
1669 {"octa", s_cons, 4},
1670 {"quad", s_cons, 3},
cca86cc8 1671 {"section", s_change_section, 0},
252b5132
RH
1672 {"short", s_cons, 1},
1673 {"single", s_float_cons, 'f'},
754e2bb9 1674 {"stabd", s_mips_stab, 'd'},
252b5132 1675 {"stabn", s_mips_stab, 'n'},
754e2bb9 1676 {"stabs", s_mips_stab, 's'},
252b5132
RH
1677 {"text", s_change_sec, 't'},
1678 {"word", s_cons, 2},
add56521 1679
add56521 1680 { "extern", ecoff_directive_extern, 0},
add56521 1681
43841e91 1682 { NULL, NULL, 0 },
252b5132
RH
1683};
1684
e972090a
NC
1685static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1686{
beae10d5
KH
1687 /* These pseudo-ops should be defined by the object file format.
1688 However, a.out doesn't support them, so we have versions here. */
252b5132
RH
1689 {"aent", s_mips_ent, 1},
1690 {"bgnb", s_ignore, 0},
1691 {"end", s_mips_end, 0},
1692 {"endb", s_ignore, 0},
1693 {"ent", s_mips_ent, 0},
c5dd6aab 1694 {"file", s_mips_file, 0},
252b5132
RH
1695 {"fmask", s_mips_mask, 'F'},
1696 {"frame", s_mips_frame, 0},
c5dd6aab 1697 {"loc", s_mips_loc, 0},
252b5132
RH
1698 {"mask", s_mips_mask, 'R'},
1699 {"verstamp", s_ignore, 0},
43841e91 1700 { NULL, NULL, 0 },
252b5132
RH
1701};
1702
3ae8dd8d
MR
1703/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1704 purpose of the `.dc.a' internal pseudo-op. */
1705
1706int
1707mips_address_bytes (void)
1708{
1709 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1710}
1711
17a2f251 1712extern void pop_insert (const pseudo_typeS *);
252b5132
RH
1713
1714void
17a2f251 1715mips_pop_insert (void)
252b5132
RH
1716{
1717 pop_insert (mips_pseudo_table);
1718 if (! ECOFF_DEBUGGING)
1719 pop_insert (mips_nonecoff_pseudo_table);
1720}
1721\f
1722/* Symbols labelling the current insn. */
1723
e972090a
NC
1724struct insn_label_list
1725{
252b5132
RH
1726 struct insn_label_list *next;
1727 symbolS *label;
1728};
1729
252b5132 1730static struct insn_label_list *free_insn_labels;
742a56fe 1731#define label_list tc_segment_info_data.labels
252b5132 1732
17a2f251 1733static void mips_clear_insn_labels (void);
df58fc94
RS
1734static void mips_mark_labels (void);
1735static void mips_compressed_mark_labels (void);
252b5132
RH
1736
1737static inline void
17a2f251 1738mips_clear_insn_labels (void)
252b5132
RH
1739{
1740 register struct insn_label_list **pl;
a8dbcb85 1741 segment_info_type *si;
252b5132 1742
a8dbcb85
TS
1743 if (now_seg)
1744 {
1745 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1746 ;
1747
1748 si = seg_info (now_seg);
1749 *pl = si->label_list;
1750 si->label_list = NULL;
1751 }
252b5132 1752}
a8dbcb85 1753
df58fc94
RS
1754/* Mark instruction labels in MIPS16/microMIPS mode. */
1755
1756static inline void
1757mips_mark_labels (void)
1758{
1759 if (HAVE_CODE_COMPRESSION)
1760 mips_compressed_mark_labels ();
1761}
252b5132
RH
1762\f
1763static char *expr_end;
1764
77bd4346
RS
1765/* Expressions which appear in macro instructions. These are set by
1766 mips_ip and read by macro. */
252b5132
RH
1767
1768static expressionS imm_expr;
5f74bc13 1769static expressionS imm2_expr;
252b5132 1770
77bd4346
RS
1771/* The relocatable field in an instruction and the relocs associated
1772 with it. These variables are used for instructions like LUI and
1773 JAL as well as true offsets. They are also used for address
1774 operands in macros. */
252b5132 1775
77bd4346 1776static expressionS offset_expr;
f6688943
TS
1777static bfd_reloc_code_real_type offset_reloc[3]
1778 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 1779
df58fc94
RS
1780/* This is set to the resulting size of the instruction to be produced
1781 by mips16_ip if an explicit extension is used or by mips_ip if an
1782 explicit size is supplied. */
252b5132 1783
df58fc94 1784static unsigned int forced_insn_length;
252b5132 1785
e1b47bd5
RS
1786/* True if we are assembling an instruction. All dot symbols defined during
1787 this time should be treated as code labels. */
1788
1789static bfd_boolean mips_assembling_insn;
1790
ecb4347a
DJ
1791/* The pdr segment for per procedure frame/regmask info. Not used for
1792 ECOFF debugging. */
252b5132
RH
1793
1794static segT pdr_seg;
252b5132 1795
e013f690
TS
1796/* The default target format to use. */
1797
aeffff67
RS
1798#if defined (TE_FreeBSD)
1799#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1800#elif defined (TE_TMIPS)
1801#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1802#else
1803#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1804#endif
1805
e013f690 1806const char *
17a2f251 1807mips_target_format (void)
e013f690
TS
1808{
1809 switch (OUTPUT_FLAVOR)
1810 {
e013f690 1811 case bfd_target_elf_flavour:
0a44bf69
RS
1812#ifdef TE_VXWORKS
1813 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1814 return (target_big_endian
1815 ? "elf32-bigmips-vxworks"
1816 : "elf32-littlemips-vxworks");
1817#endif
e013f690 1818 return (target_big_endian
cfe86eaa 1819 ? (HAVE_64BIT_OBJECTS
aeffff67 1820 ? ELF_TARGET ("elf64-", "big")
cfe86eaa 1821 : (HAVE_NEWABI
aeffff67
RS
1822 ? ELF_TARGET ("elf32-n", "big")
1823 : ELF_TARGET ("elf32-", "big")))
cfe86eaa 1824 : (HAVE_64BIT_OBJECTS
aeffff67 1825 ? ELF_TARGET ("elf64-", "little")
cfe86eaa 1826 : (HAVE_NEWABI
aeffff67
RS
1827 ? ELF_TARGET ("elf32-n", "little")
1828 : ELF_TARGET ("elf32-", "little"))));
e013f690
TS
1829 default:
1830 abort ();
1831 return NULL;
1832 }
1833}
1834
c6278170
RS
1835/* Return the ISA revision that is currently in use, or 0 if we are
1836 generating code for MIPS V or below. */
1837
1838static int
1839mips_isa_rev (void)
1840{
1841 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1842 return 2;
1843
1844 /* microMIPS implies revision 2 or above. */
1845 if (mips_opts.micromips)
1846 return 2;
1847
1848 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1849 return 1;
1850
1851 return 0;
1852}
1853
1854/* Return the mask of all ASEs that are revisions of those in FLAGS. */
1855
1856static unsigned int
1857mips_ase_mask (unsigned int flags)
1858{
1859 unsigned int i;
1860
1861 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1862 if (flags & mips_ase_groups[i])
1863 flags |= mips_ase_groups[i];
1864 return flags;
1865}
1866
1867/* Check whether the current ISA supports ASE. Issue a warning if
1868 appropriate. */
1869
1870static void
1871mips_check_isa_supports_ase (const struct mips_ase *ase)
1872{
1873 const char *base;
1874 int min_rev, size;
1875 static unsigned int warned_isa;
1876 static unsigned int warned_fp32;
1877
1878 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1879 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1880 else
1881 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1882 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1883 && (warned_isa & ase->flags) != ase->flags)
1884 {
1885 warned_isa |= ase->flags;
1886 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1887 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1888 if (min_rev < 0)
1889 as_warn (_("The %d-bit %s architecture does not support the"
1890 " `%s' extension"), size, base, ase->name);
1891 else
1892 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1893 ase->name, base, size, min_rev);
1894 }
1895 if ((ase->flags & FP64_ASES)
1896 && mips_opts.fp32
1897 && (warned_fp32 & ase->flags) != ase->flags)
1898 {
1899 warned_fp32 |= ase->flags;
1900 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1901 }
1902}
1903
1904/* Check all enabled ASEs to see whether they are supported by the
1905 chosen architecture. */
1906
1907static void
1908mips_check_isa_supports_ases (void)
1909{
1910 unsigned int i, mask;
1911
1912 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1913 {
1914 mask = mips_ase_mask (mips_ases[i].flags);
1915 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1916 mips_check_isa_supports_ase (&mips_ases[i]);
1917 }
1918}
1919
1920/* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1921 that were affected. */
1922
1923static unsigned int
1924mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1925{
1926 unsigned int mask;
1927
1928 mask = mips_ase_mask (ase->flags);
1929 mips_opts.ase &= ~mask;
1930 if (enabled_p)
1931 mips_opts.ase |= ase->flags;
1932 return mask;
1933}
1934
1935/* Return the ASE called NAME, or null if none. */
1936
1937static const struct mips_ase *
1938mips_lookup_ase (const char *name)
1939{
1940 unsigned int i;
1941
1942 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1943 if (strcmp (name, mips_ases[i].name) == 0)
1944 return &mips_ases[i];
1945 return NULL;
1946}
1947
df58fc94
RS
1948/* Return the length of a microMIPS instruction in bytes. If bits of
1949 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1950 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1951 major opcode) will require further modifications to the opcode
1952 table. */
1953
1954static inline unsigned int
1955micromips_insn_length (const struct mips_opcode *mo)
1956{
1957 return (mo->mask >> 16) == 0 ? 2 : 4;
1958}
1959
5c04167a
RS
1960/* Return the length of MIPS16 instruction OPCODE. */
1961
1962static inline unsigned int
1963mips16_opcode_length (unsigned long opcode)
1964{
1965 return (opcode >> 16) == 0 ? 2 : 4;
1966}
1967
1e915849
RS
1968/* Return the length of instruction INSN. */
1969
1970static inline unsigned int
1971insn_length (const struct mips_cl_insn *insn)
1972{
df58fc94
RS
1973 if (mips_opts.micromips)
1974 return micromips_insn_length (insn->insn_mo);
1975 else if (mips_opts.mips16)
5c04167a 1976 return mips16_opcode_length (insn->insn_opcode);
df58fc94 1977 else
1e915849 1978 return 4;
1e915849
RS
1979}
1980
1981/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1982
1983static void
1984create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1985{
1986 size_t i;
1987
1988 insn->insn_mo = mo;
1e915849
RS
1989 insn->insn_opcode = mo->match;
1990 insn->frag = NULL;
1991 insn->where = 0;
1992 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1993 insn->fixp[i] = NULL;
1994 insn->fixed_p = (mips_opts.noreorder > 0);
1995 insn->noreorder_p = (mips_opts.noreorder > 0);
1996 insn->mips16_absolute_jump_p = 0;
15be625d 1997 insn->complete_p = 0;
e407c74b 1998 insn->cleared_p = 0;
1e915849
RS
1999}
2000
fc76e730
RS
2001/* Get a list of all the operands in INSN. */
2002
2003static const struct mips_operand_array *
2004insn_operands (const struct mips_cl_insn *insn)
2005{
2006 if (insn->insn_mo >= &mips_opcodes[0]
2007 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2008 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2009
2010 if (insn->insn_mo >= &mips16_opcodes[0]
2011 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2012 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2013
2014 if (insn->insn_mo >= &micromips_opcodes[0]
2015 && insn->insn_mo < &micromips_opcodes[bfd_micromips_num_opcodes])
2016 return &micromips_operands[insn->insn_mo - &micromips_opcodes[0]];
2017
2018 abort ();
2019}
2020
2021/* Get a description of operand OPNO of INSN. */
2022
2023static const struct mips_operand *
2024insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2025{
2026 const struct mips_operand_array *operands;
2027
2028 operands = insn_operands (insn);
2029 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2030 abort ();
2031 return operands->operand[opno];
2032}
2033
e077a1c8
RS
2034/* Install UVAL as the value of OPERAND in INSN. */
2035
2036static inline void
2037insn_insert_operand (struct mips_cl_insn *insn,
2038 const struct mips_operand *operand, unsigned int uval)
2039{
2040 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2041}
2042
fc76e730
RS
2043/* Extract the value of OPERAND from INSN. */
2044
2045static inline unsigned
2046insn_extract_operand (const struct mips_cl_insn *insn,
2047 const struct mips_operand *operand)
2048{
2049 return mips_extract_operand (operand, insn->insn_opcode);
2050}
2051
df58fc94 2052/* Record the current MIPS16/microMIPS mode in now_seg. */
742a56fe
RS
2053
2054static void
df58fc94 2055mips_record_compressed_mode (void)
742a56fe
RS
2056{
2057 segment_info_type *si;
2058
2059 si = seg_info (now_seg);
2060 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2061 si->tc_segment_info_data.mips16 = mips_opts.mips16;
df58fc94
RS
2062 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2063 si->tc_segment_info_data.micromips = mips_opts.micromips;
742a56fe
RS
2064}
2065
4d68580a
RS
2066/* Read a standard MIPS instruction from BUF. */
2067
2068static unsigned long
2069read_insn (char *buf)
2070{
2071 if (target_big_endian)
2072 return bfd_getb32 ((bfd_byte *) buf);
2073 else
2074 return bfd_getl32 ((bfd_byte *) buf);
2075}
2076
2077/* Write standard MIPS instruction INSN to BUF. Return a pointer to
2078 the next byte. */
2079
2080static char *
2081write_insn (char *buf, unsigned int insn)
2082{
2083 md_number_to_chars (buf, insn, 4);
2084 return buf + 4;
2085}
2086
2087/* Read a microMIPS or MIPS16 opcode from BUF, given that it
2088 has length LENGTH. */
2089
2090static unsigned long
2091read_compressed_insn (char *buf, unsigned int length)
2092{
2093 unsigned long insn;
2094 unsigned int i;
2095
2096 insn = 0;
2097 for (i = 0; i < length; i += 2)
2098 {
2099 insn <<= 16;
2100 if (target_big_endian)
2101 insn |= bfd_getb16 ((char *) buf);
2102 else
2103 insn |= bfd_getl16 ((char *) buf);
2104 buf += 2;
2105 }
2106 return insn;
2107}
2108
5c04167a
RS
2109/* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2110 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2111
2112static char *
2113write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2114{
2115 unsigned int i;
2116
2117 for (i = 0; i < length; i += 2)
2118 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2119 return buf + length;
2120}
2121
1e915849
RS
2122/* Install INSN at the location specified by its "frag" and "where" fields. */
2123
2124static void
2125install_insn (const struct mips_cl_insn *insn)
2126{
2127 char *f = insn->frag->fr_literal + insn->where;
5c04167a
RS
2128 if (HAVE_CODE_COMPRESSION)
2129 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1e915849 2130 else
4d68580a 2131 write_insn (f, insn->insn_opcode);
df58fc94 2132 mips_record_compressed_mode ();
1e915849
RS
2133}
2134
2135/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2136 and install the opcode in the new location. */
2137
2138static void
2139move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2140{
2141 size_t i;
2142
2143 insn->frag = frag;
2144 insn->where = where;
2145 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2146 if (insn->fixp[i] != NULL)
2147 {
2148 insn->fixp[i]->fx_frag = frag;
2149 insn->fixp[i]->fx_where = where;
2150 }
2151 install_insn (insn);
2152}
2153
2154/* Add INSN to the end of the output. */
2155
2156static void
2157add_fixed_insn (struct mips_cl_insn *insn)
2158{
2159 char *f = frag_more (insn_length (insn));
2160 move_insn (insn, frag_now, f - frag_now->fr_literal);
2161}
2162
2163/* Start a variant frag and move INSN to the start of the variant part,
2164 marking it as fixed. The other arguments are as for frag_var. */
2165
2166static void
2167add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2168 relax_substateT subtype, symbolS *symbol, offsetT offset)
2169{
2170 frag_grow (max_chars);
2171 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2172 insn->fixed_p = 1;
2173 frag_var (rs_machine_dependent, max_chars, var,
2174 subtype, symbol, offset, NULL);
2175}
2176
2177/* Insert N copies of INSN into the history buffer, starting at
2178 position FIRST. Neither FIRST nor N need to be clipped. */
2179
2180static void
2181insert_into_history (unsigned int first, unsigned int n,
2182 const struct mips_cl_insn *insn)
2183{
2184 if (mips_relax.sequence != 2)
2185 {
2186 unsigned int i;
2187
2188 for (i = ARRAY_SIZE (history); i-- > first;)
2189 if (i >= first + n)
2190 history[i] = history[i - n];
2191 else
2192 history[i] = *insn;
2193 }
2194}
2195
e3de51ce
RS
2196/* Clear the error in insn_error. */
2197
2198static void
2199clear_insn_error (void)
2200{
2201 memset (&insn_error, 0, sizeof (insn_error));
2202}
2203
2204/* Possibly record error message MSG for the current instruction.
2205 If the error is about a particular argument, ARGNUM is the 1-based
2206 number of that argument, otherwise it is 0. FORMAT is the format
2207 of MSG. Return true if MSG was used, false if the current message
2208 was kept. */
2209
2210static bfd_boolean
2211set_insn_error_format (int argnum, enum mips_insn_error_format format,
2212 const char *msg)
2213{
2214 if (argnum == 0)
2215 {
2216 /* Give priority to errors against specific arguments, and to
2217 the first whole-instruction message. */
2218 if (insn_error.msg)
2219 return FALSE;
2220 }
2221 else
2222 {
2223 /* Keep insn_error if it is against a later argument. */
2224 if (argnum < insn_error.min_argnum)
2225 return FALSE;
2226
2227 /* If both errors are against the same argument but are different,
2228 give up on reporting a specific error for this argument.
2229 See the comment about mips_insn_error for details. */
2230 if (argnum == insn_error.min_argnum
2231 && insn_error.msg
2232 && strcmp (insn_error.msg, msg) != 0)
2233 {
2234 insn_error.msg = 0;
2235 insn_error.min_argnum += 1;
2236 return FALSE;
2237 }
2238 }
2239 insn_error.min_argnum = argnum;
2240 insn_error.format = format;
2241 insn_error.msg = msg;
2242 return TRUE;
2243}
2244
2245/* Record an instruction error with no % format fields. ARGNUM and MSG are
2246 as for set_insn_error_format. */
2247
2248static void
2249set_insn_error (int argnum, const char *msg)
2250{
2251 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2252}
2253
2254/* Record an instruction error with one %d field I. ARGNUM and MSG are
2255 as for set_insn_error_format. */
2256
2257static void
2258set_insn_error_i (int argnum, const char *msg, int i)
2259{
2260 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2261 insn_error.u.i = i;
2262}
2263
2264/* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2265 are as for set_insn_error_format. */
2266
2267static void
2268set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2269{
2270 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2271 {
2272 insn_error.u.ss[0] = s1;
2273 insn_error.u.ss[1] = s2;
2274 }
2275}
2276
2277/* Report the error in insn_error, which is against assembly code STR. */
2278
2279static void
2280report_insn_error (const char *str)
2281{
2282 const char *msg;
2283
2284 msg = ACONCAT ((insn_error.msg, " `%s'", NULL));
2285 switch (insn_error.format)
2286 {
2287 case ERR_FMT_PLAIN:
2288 as_bad (msg, str);
2289 break;
2290
2291 case ERR_FMT_I:
2292 as_bad (msg, insn_error.u.i, str);
2293 break;
2294
2295 case ERR_FMT_SS:
2296 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2297 break;
2298 }
2299}
2300
71400594
RS
2301/* Initialize vr4120_conflicts. There is a bit of duplication here:
2302 the idea is to make it obvious at a glance that each errata is
2303 included. */
2304
2305static void
2306init_vr4120_conflicts (void)
2307{
2308#define CONFLICT(FIRST, SECOND) \
2309 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2310
2311 /* Errata 21 - [D]DIV[U] after [D]MACC */
2312 CONFLICT (MACC, DIV);
2313 CONFLICT (DMACC, DIV);
2314
2315 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2316 CONFLICT (DMULT, DMULT);
2317 CONFLICT (DMULT, DMACC);
2318 CONFLICT (DMACC, DMULT);
2319 CONFLICT (DMACC, DMACC);
2320
2321 /* Errata 24 - MT{LO,HI} after [D]MACC */
2322 CONFLICT (MACC, MTHILO);
2323 CONFLICT (DMACC, MTHILO);
2324
2325 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2326 instruction is executed immediately after a MACC or DMACC
2327 instruction, the result of [either instruction] is incorrect." */
2328 CONFLICT (MACC, MULT);
2329 CONFLICT (MACC, DMULT);
2330 CONFLICT (DMACC, MULT);
2331 CONFLICT (DMACC, DMULT);
2332
2333 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2334 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2335 DDIV or DDIVU instruction, the result of the MACC or
2336 DMACC instruction is incorrect.". */
2337 CONFLICT (DMULT, MACC);
2338 CONFLICT (DMULT, DMACC);
2339 CONFLICT (DIV, MACC);
2340 CONFLICT (DIV, DMACC);
2341
2342#undef CONFLICT
2343}
2344
707bfff6
TS
2345struct regname {
2346 const char *name;
2347 unsigned int num;
2348};
2349
14daeee3
RS
2350#define RNUM_MASK 0x00000ff
2351#define RTYPE_MASK 0x0efff00
2352#define RTYPE_NUM 0x0000100
2353#define RTYPE_FPU 0x0000200
2354#define RTYPE_FCC 0x0000400
2355#define RTYPE_VEC 0x0000800
2356#define RTYPE_GP 0x0001000
2357#define RTYPE_CP0 0x0002000
2358#define RTYPE_PC 0x0004000
2359#define RTYPE_ACC 0x0008000
2360#define RTYPE_CCC 0x0010000
2361#define RTYPE_VI 0x0020000
2362#define RTYPE_VF 0x0040000
2363#define RTYPE_R5900_I 0x0080000
2364#define RTYPE_R5900_Q 0x0100000
2365#define RTYPE_R5900_R 0x0200000
2366#define RTYPE_R5900_ACC 0x0400000
2367#define RWARN 0x8000000
707bfff6
TS
2368
2369#define GENERIC_REGISTER_NUMBERS \
2370 {"$0", RTYPE_NUM | 0}, \
2371 {"$1", RTYPE_NUM | 1}, \
2372 {"$2", RTYPE_NUM | 2}, \
2373 {"$3", RTYPE_NUM | 3}, \
2374 {"$4", RTYPE_NUM | 4}, \
2375 {"$5", RTYPE_NUM | 5}, \
2376 {"$6", RTYPE_NUM | 6}, \
2377 {"$7", RTYPE_NUM | 7}, \
2378 {"$8", RTYPE_NUM | 8}, \
2379 {"$9", RTYPE_NUM | 9}, \
2380 {"$10", RTYPE_NUM | 10}, \
2381 {"$11", RTYPE_NUM | 11}, \
2382 {"$12", RTYPE_NUM | 12}, \
2383 {"$13", RTYPE_NUM | 13}, \
2384 {"$14", RTYPE_NUM | 14}, \
2385 {"$15", RTYPE_NUM | 15}, \
2386 {"$16", RTYPE_NUM | 16}, \
2387 {"$17", RTYPE_NUM | 17}, \
2388 {"$18", RTYPE_NUM | 18}, \
2389 {"$19", RTYPE_NUM | 19}, \
2390 {"$20", RTYPE_NUM | 20}, \
2391 {"$21", RTYPE_NUM | 21}, \
2392 {"$22", RTYPE_NUM | 22}, \
2393 {"$23", RTYPE_NUM | 23}, \
2394 {"$24", RTYPE_NUM | 24}, \
2395 {"$25", RTYPE_NUM | 25}, \
2396 {"$26", RTYPE_NUM | 26}, \
2397 {"$27", RTYPE_NUM | 27}, \
2398 {"$28", RTYPE_NUM | 28}, \
2399 {"$29", RTYPE_NUM | 29}, \
2400 {"$30", RTYPE_NUM | 30}, \
2401 {"$31", RTYPE_NUM | 31}
2402
2403#define FPU_REGISTER_NAMES \
2404 {"$f0", RTYPE_FPU | 0}, \
2405 {"$f1", RTYPE_FPU | 1}, \
2406 {"$f2", RTYPE_FPU | 2}, \
2407 {"$f3", RTYPE_FPU | 3}, \
2408 {"$f4", RTYPE_FPU | 4}, \
2409 {"$f5", RTYPE_FPU | 5}, \
2410 {"$f6", RTYPE_FPU | 6}, \
2411 {"$f7", RTYPE_FPU | 7}, \
2412 {"$f8", RTYPE_FPU | 8}, \
2413 {"$f9", RTYPE_FPU | 9}, \
2414 {"$f10", RTYPE_FPU | 10}, \
2415 {"$f11", RTYPE_FPU | 11}, \
2416 {"$f12", RTYPE_FPU | 12}, \
2417 {"$f13", RTYPE_FPU | 13}, \
2418 {"$f14", RTYPE_FPU | 14}, \
2419 {"$f15", RTYPE_FPU | 15}, \
2420 {"$f16", RTYPE_FPU | 16}, \
2421 {"$f17", RTYPE_FPU | 17}, \
2422 {"$f18", RTYPE_FPU | 18}, \
2423 {"$f19", RTYPE_FPU | 19}, \
2424 {"$f20", RTYPE_FPU | 20}, \
2425 {"$f21", RTYPE_FPU | 21}, \
2426 {"$f22", RTYPE_FPU | 22}, \
2427 {"$f23", RTYPE_FPU | 23}, \
2428 {"$f24", RTYPE_FPU | 24}, \
2429 {"$f25", RTYPE_FPU | 25}, \
2430 {"$f26", RTYPE_FPU | 26}, \
2431 {"$f27", RTYPE_FPU | 27}, \
2432 {"$f28", RTYPE_FPU | 28}, \
2433 {"$f29", RTYPE_FPU | 29}, \
2434 {"$f30", RTYPE_FPU | 30}, \
2435 {"$f31", RTYPE_FPU | 31}
2436
2437#define FPU_CONDITION_CODE_NAMES \
2438 {"$fcc0", RTYPE_FCC | 0}, \
2439 {"$fcc1", RTYPE_FCC | 1}, \
2440 {"$fcc2", RTYPE_FCC | 2}, \
2441 {"$fcc3", RTYPE_FCC | 3}, \
2442 {"$fcc4", RTYPE_FCC | 4}, \
2443 {"$fcc5", RTYPE_FCC | 5}, \
2444 {"$fcc6", RTYPE_FCC | 6}, \
2445 {"$fcc7", RTYPE_FCC | 7}
2446
2447#define COPROC_CONDITION_CODE_NAMES \
2448 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2449 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2450 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2451 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2452 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2453 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2454 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2455 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2456
2457#define N32N64_SYMBOLIC_REGISTER_NAMES \
2458 {"$a4", RTYPE_GP | 8}, \
2459 {"$a5", RTYPE_GP | 9}, \
2460 {"$a6", RTYPE_GP | 10}, \
2461 {"$a7", RTYPE_GP | 11}, \
2462 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2463 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2464 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2465 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2466 {"$t0", RTYPE_GP | 12}, \
2467 {"$t1", RTYPE_GP | 13}, \
2468 {"$t2", RTYPE_GP | 14}, \
2469 {"$t3", RTYPE_GP | 15}
2470
2471#define O32_SYMBOLIC_REGISTER_NAMES \
2472 {"$t0", RTYPE_GP | 8}, \
2473 {"$t1", RTYPE_GP | 9}, \
2474 {"$t2", RTYPE_GP | 10}, \
2475 {"$t3", RTYPE_GP | 11}, \
2476 {"$t4", RTYPE_GP | 12}, \
2477 {"$t5", RTYPE_GP | 13}, \
2478 {"$t6", RTYPE_GP | 14}, \
2479 {"$t7", RTYPE_GP | 15}, \
2480 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2481 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2482 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2483 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2484
2485/* Remaining symbolic register names */
2486#define SYMBOLIC_REGISTER_NAMES \
2487 {"$zero", RTYPE_GP | 0}, \
2488 {"$at", RTYPE_GP | 1}, \
2489 {"$AT", RTYPE_GP | 1}, \
2490 {"$v0", RTYPE_GP | 2}, \
2491 {"$v1", RTYPE_GP | 3}, \
2492 {"$a0", RTYPE_GP | 4}, \
2493 {"$a1", RTYPE_GP | 5}, \
2494 {"$a2", RTYPE_GP | 6}, \
2495 {"$a3", RTYPE_GP | 7}, \
2496 {"$s0", RTYPE_GP | 16}, \
2497 {"$s1", RTYPE_GP | 17}, \
2498 {"$s2", RTYPE_GP | 18}, \
2499 {"$s3", RTYPE_GP | 19}, \
2500 {"$s4", RTYPE_GP | 20}, \
2501 {"$s5", RTYPE_GP | 21}, \
2502 {"$s6", RTYPE_GP | 22}, \
2503 {"$s7", RTYPE_GP | 23}, \
2504 {"$t8", RTYPE_GP | 24}, \
2505 {"$t9", RTYPE_GP | 25}, \
2506 {"$k0", RTYPE_GP | 26}, \
2507 {"$kt0", RTYPE_GP | 26}, \
2508 {"$k1", RTYPE_GP | 27}, \
2509 {"$kt1", RTYPE_GP | 27}, \
2510 {"$gp", RTYPE_GP | 28}, \
2511 {"$sp", RTYPE_GP | 29}, \
2512 {"$s8", RTYPE_GP | 30}, \
2513 {"$fp", RTYPE_GP | 30}, \
2514 {"$ra", RTYPE_GP | 31}
2515
2516#define MIPS16_SPECIAL_REGISTER_NAMES \
2517 {"$pc", RTYPE_PC | 0}
2518
2519#define MDMX_VECTOR_REGISTER_NAMES \
2520 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2521 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2522 {"$v2", RTYPE_VEC | 2}, \
2523 {"$v3", RTYPE_VEC | 3}, \
2524 {"$v4", RTYPE_VEC | 4}, \
2525 {"$v5", RTYPE_VEC | 5}, \
2526 {"$v6", RTYPE_VEC | 6}, \
2527 {"$v7", RTYPE_VEC | 7}, \
2528 {"$v8", RTYPE_VEC | 8}, \
2529 {"$v9", RTYPE_VEC | 9}, \
2530 {"$v10", RTYPE_VEC | 10}, \
2531 {"$v11", RTYPE_VEC | 11}, \
2532 {"$v12", RTYPE_VEC | 12}, \
2533 {"$v13", RTYPE_VEC | 13}, \
2534 {"$v14", RTYPE_VEC | 14}, \
2535 {"$v15", RTYPE_VEC | 15}, \
2536 {"$v16", RTYPE_VEC | 16}, \
2537 {"$v17", RTYPE_VEC | 17}, \
2538 {"$v18", RTYPE_VEC | 18}, \
2539 {"$v19", RTYPE_VEC | 19}, \
2540 {"$v20", RTYPE_VEC | 20}, \
2541 {"$v21", RTYPE_VEC | 21}, \
2542 {"$v22", RTYPE_VEC | 22}, \
2543 {"$v23", RTYPE_VEC | 23}, \
2544 {"$v24", RTYPE_VEC | 24}, \
2545 {"$v25", RTYPE_VEC | 25}, \
2546 {"$v26", RTYPE_VEC | 26}, \
2547 {"$v27", RTYPE_VEC | 27}, \
2548 {"$v28", RTYPE_VEC | 28}, \
2549 {"$v29", RTYPE_VEC | 29}, \
2550 {"$v30", RTYPE_VEC | 30}, \
2551 {"$v31", RTYPE_VEC | 31}
2552
14daeee3
RS
2553#define R5900_I_NAMES \
2554 {"$I", RTYPE_R5900_I | 0}
2555
2556#define R5900_Q_NAMES \
2557 {"$Q", RTYPE_R5900_Q | 0}
2558
2559#define R5900_R_NAMES \
2560 {"$R", RTYPE_R5900_R | 0}
2561
2562#define R5900_ACC_NAMES \
2563 {"$ACC", RTYPE_R5900_ACC | 0 }
2564
707bfff6
TS
2565#define MIPS_DSP_ACCUMULATOR_NAMES \
2566 {"$ac0", RTYPE_ACC | 0}, \
2567 {"$ac1", RTYPE_ACC | 1}, \
2568 {"$ac2", RTYPE_ACC | 2}, \
2569 {"$ac3", RTYPE_ACC | 3}
2570
2571static const struct regname reg_names[] = {
2572 GENERIC_REGISTER_NUMBERS,
2573 FPU_REGISTER_NAMES,
2574 FPU_CONDITION_CODE_NAMES,
2575 COPROC_CONDITION_CODE_NAMES,
2576
2577 /* The $txx registers depends on the abi,
2578 these will be added later into the symbol table from
2579 one of the tables below once mips_abi is set after
2580 parsing of arguments from the command line. */
2581 SYMBOLIC_REGISTER_NAMES,
2582
2583 MIPS16_SPECIAL_REGISTER_NAMES,
2584 MDMX_VECTOR_REGISTER_NAMES,
14daeee3
RS
2585 R5900_I_NAMES,
2586 R5900_Q_NAMES,
2587 R5900_R_NAMES,
2588 R5900_ACC_NAMES,
707bfff6
TS
2589 MIPS_DSP_ACCUMULATOR_NAMES,
2590 {0, 0}
2591};
2592
2593static const struct regname reg_names_o32[] = {
2594 O32_SYMBOLIC_REGISTER_NAMES,
2595 {0, 0}
2596};
2597
2598static const struct regname reg_names_n32n64[] = {
2599 N32N64_SYMBOLIC_REGISTER_NAMES,
2600 {0, 0}
2601};
2602
a92713e6
RS
2603/* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2604 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2605 of these register symbols, return the associated vector register,
2606 otherwise return SYMVAL itself. */
df58fc94 2607
a92713e6
RS
2608static unsigned int
2609mips_prefer_vec_regno (unsigned int symval)
707bfff6 2610{
a92713e6
RS
2611 if ((symval & -2) == (RTYPE_GP | 2))
2612 return RTYPE_VEC | (symval & 1);
2613 return symval;
2614}
2615
14daeee3
RS
2616/* Return true if string [S, E) is a valid register name, storing its
2617 symbol value in *SYMVAL_PTR if so. */
a92713e6
RS
2618
2619static bfd_boolean
14daeee3 2620mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
a92713e6 2621{
707bfff6 2622 char save_c;
14daeee3 2623 symbolS *symbol;
707bfff6
TS
2624
2625 /* Terminate name. */
2626 save_c = *e;
2627 *e = '\0';
2628
a92713e6
RS
2629 /* Look up the name. */
2630 symbol = symbol_find (s);
2631 *e = save_c;
2632
2633 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2634 return FALSE;
2635
14daeee3
RS
2636 *symval_ptr = S_GET_VALUE (symbol);
2637 return TRUE;
2638}
2639
2640/* Return true if the string at *SPTR is a valid register name. Allow it
2641 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2642 is nonnull.
2643
2644 When returning true, move *SPTR past the register, store the
2645 register's symbol value in *SYMVAL_PTR and the channel mask in
2646 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2647 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2648 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2649
2650static bfd_boolean
2651mips_parse_register (char **sptr, unsigned int *symval_ptr,
2652 unsigned int *channels_ptr)
2653{
2654 char *s, *e, *m;
2655 const char *q;
2656 unsigned int channels, symval, bit;
2657
2658 /* Find end of name. */
2659 s = e = *sptr;
2660 if (is_name_beginner (*e))
2661 ++e;
2662 while (is_part_of_name (*e))
2663 ++e;
2664
2665 channels = 0;
2666 if (!mips_parse_register_1 (s, e, &symval))
2667 {
2668 if (!channels_ptr)
2669 return FALSE;
2670
2671 /* Eat characters from the end of the string that are valid
2672 channel suffixes. The preceding register must be $ACC or
2673 end with a digit, so there is no ambiguity. */
2674 bit = 1;
2675 m = e;
2676 for (q = "wzyx"; *q; q++, bit <<= 1)
2677 if (m > s && m[-1] == *q)
2678 {
2679 --m;
2680 channels |= bit;
2681 }
2682
2683 if (channels == 0
2684 || !mips_parse_register_1 (s, m, &symval)
2685 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2686 return FALSE;
2687 }
2688
a92713e6 2689 *sptr = e;
14daeee3
RS
2690 *symval_ptr = symval;
2691 if (channels_ptr)
2692 *channels_ptr = channels;
a92713e6
RS
2693 return TRUE;
2694}
2695
2696/* Check if SPTR points at a valid register specifier according to TYPES.
2697 If so, then return 1, advance S to consume the specifier and store
2698 the register's number in REGNOP, otherwise return 0. */
2699
2700static int
2701reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2702{
2703 unsigned int regno;
2704
14daeee3 2705 if (mips_parse_register (s, &regno, NULL))
707bfff6 2706 {
a92713e6
RS
2707 if (types & RTYPE_VEC)
2708 regno = mips_prefer_vec_regno (regno);
2709 if (regno & types)
2710 regno &= RNUM_MASK;
2711 else
2712 regno = ~0;
707bfff6 2713 }
a92713e6 2714 else
707bfff6 2715 {
a92713e6
RS
2716 if (types & RWARN)
2717 as_warn (_("Unrecognized register name `%s'"), *s);
2718 regno = ~0;
707bfff6 2719 }
707bfff6 2720 if (regnop)
a92713e6
RS
2721 *regnop = regno;
2722 return regno <= RNUM_MASK;
707bfff6
TS
2723}
2724
14daeee3
RS
2725/* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2726 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2727
2728static char *
2729mips_parse_vu0_channels (char *s, unsigned int *channels)
2730{
2731 unsigned int i;
2732
2733 *channels = 0;
2734 for (i = 0; i < 4; i++)
2735 if (*s == "xyzw"[i])
2736 {
2737 *channels |= 1 << (3 - i);
2738 ++s;
2739 }
2740 return s;
2741}
2742
a92713e6
RS
2743/* Token types for parsed operand lists. */
2744enum mips_operand_token_type {
2745 /* A plain register, e.g. $f2. */
2746 OT_REG,
df58fc94 2747
14daeee3
RS
2748 /* A 4-bit XYZW channel mask. */
2749 OT_CHANNELS,
2750
a92713e6
RS
2751 /* An element of a vector, e.g. $v0[1]. */
2752 OT_REG_ELEMENT,
df58fc94 2753
a92713e6
RS
2754 /* A continuous range of registers, e.g. $s0-$s4. */
2755 OT_REG_RANGE,
2756
2757 /* A (possibly relocated) expression. */
2758 OT_INTEGER,
2759
2760 /* A floating-point value. */
2761 OT_FLOAT,
2762
2763 /* A single character. This can be '(', ')' or ',', but '(' only appears
2764 before OT_REGs. */
2765 OT_CHAR,
2766
14daeee3
RS
2767 /* A doubled character, either "--" or "++". */
2768 OT_DOUBLE_CHAR,
2769
a92713e6
RS
2770 /* The end of the operand list. */
2771 OT_END
2772};
2773
2774/* A parsed operand token. */
2775struct mips_operand_token
2776{
2777 /* The type of token. */
2778 enum mips_operand_token_type type;
2779 union
2780 {
2781 /* The register symbol value for an OT_REG. */
2782 unsigned int regno;
2783
14daeee3
RS
2784 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2785 unsigned int channels;
2786
a92713e6
RS
2787 /* The register symbol value and index for an OT_REG_ELEMENT. */
2788 struct {
2789 unsigned int regno;
2790 addressT index;
2791 } reg_element;
2792
2793 /* The two register symbol values involved in an OT_REG_RANGE. */
2794 struct {
2795 unsigned int regno1;
2796 unsigned int regno2;
2797 } reg_range;
2798
2799 /* The value of an OT_INTEGER. The value is represented as an
2800 expression and the relocation operators that were applied to
2801 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2802 relocation operators were used. */
2803 struct {
2804 expressionS value;
2805 bfd_reloc_code_real_type relocs[3];
2806 } integer;
2807
2808 /* The binary data for an OT_FLOAT constant, and the number of bytes
2809 in the constant. */
2810 struct {
2811 unsigned char data[8];
2812 int length;
2813 } flt;
2814
14daeee3 2815 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
a92713e6
RS
2816 char ch;
2817 } u;
2818};
2819
2820/* An obstack used to construct lists of mips_operand_tokens. */
2821static struct obstack mips_operand_tokens;
2822
2823/* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2824
2825static void
2826mips_add_token (struct mips_operand_token *token,
2827 enum mips_operand_token_type type)
2828{
2829 token->type = type;
2830 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2831}
2832
2833/* Check whether S is '(' followed by a register name. Add OT_CHAR
2834 and OT_REG tokens for them if so, and return a pointer to the first
2835 unconsumed character. Return null otherwise. */
2836
2837static char *
2838mips_parse_base_start (char *s)
2839{
2840 struct mips_operand_token token;
14daeee3
RS
2841 unsigned int regno, channels;
2842 bfd_boolean decrement_p;
df58fc94 2843
a92713e6
RS
2844 if (*s != '(')
2845 return 0;
2846
2847 ++s;
2848 SKIP_SPACE_TABS (s);
14daeee3
RS
2849
2850 /* Only match "--" as part of a base expression. In other contexts "--X"
2851 is a double negative. */
2852 decrement_p = (s[0] == '-' && s[1] == '-');
2853 if (decrement_p)
2854 {
2855 s += 2;
2856 SKIP_SPACE_TABS (s);
2857 }
2858
2859 /* Allow a channel specifier because that leads to better error messages
2860 than treating something like "$vf0x++" as an expression. */
2861 if (!mips_parse_register (&s, &regno, &channels))
a92713e6
RS
2862 return 0;
2863
2864 token.u.ch = '(';
2865 mips_add_token (&token, OT_CHAR);
2866
14daeee3
RS
2867 if (decrement_p)
2868 {
2869 token.u.ch = '-';
2870 mips_add_token (&token, OT_DOUBLE_CHAR);
2871 }
2872
a92713e6
RS
2873 token.u.regno = regno;
2874 mips_add_token (&token, OT_REG);
2875
14daeee3
RS
2876 if (channels)
2877 {
2878 token.u.channels = channels;
2879 mips_add_token (&token, OT_CHANNELS);
2880 }
2881
2882 /* For consistency, only match "++" as part of base expressions too. */
2883 SKIP_SPACE_TABS (s);
2884 if (s[0] == '+' && s[1] == '+')
2885 {
2886 s += 2;
2887 token.u.ch = '+';
2888 mips_add_token (&token, OT_DOUBLE_CHAR);
2889 }
2890
a92713e6
RS
2891 return s;
2892}
2893
2894/* Parse one or more tokens from S. Return a pointer to the first
2895 unconsumed character on success. Return null if an error was found
2896 and store the error text in insn_error. FLOAT_FORMAT is as for
2897 mips_parse_arguments. */
2898
2899static char *
2900mips_parse_argument_token (char *s, char float_format)
2901{
2902 char *end, *save_in, *err;
14daeee3 2903 unsigned int regno1, regno2, channels;
a92713e6
RS
2904 struct mips_operand_token token;
2905
2906 /* First look for "($reg", since we want to treat that as an
2907 OT_CHAR and OT_REG rather than an expression. */
2908 end = mips_parse_base_start (s);
2909 if (end)
2910 return end;
2911
2912 /* Handle other characters that end up as OT_CHARs. */
2913 if (*s == ')' || *s == ',')
2914 {
2915 token.u.ch = *s;
2916 mips_add_token (&token, OT_CHAR);
2917 ++s;
2918 return s;
2919 }
2920
2921 /* Handle tokens that start with a register. */
14daeee3 2922 if (mips_parse_register (&s, &regno1, &channels))
df58fc94 2923 {
14daeee3
RS
2924 if (channels)
2925 {
2926 /* A register and a VU0 channel suffix. */
2927 token.u.regno = regno1;
2928 mips_add_token (&token, OT_REG);
2929
2930 token.u.channels = channels;
2931 mips_add_token (&token, OT_CHANNELS);
2932 return s;
2933 }
2934
a92713e6
RS
2935 SKIP_SPACE_TABS (s);
2936 if (*s == '-')
df58fc94 2937 {
a92713e6
RS
2938 /* A register range. */
2939 ++s;
2940 SKIP_SPACE_TABS (s);
14daeee3 2941 if (!mips_parse_register (&s, &regno2, NULL))
a92713e6 2942 {
e3de51ce 2943 set_insn_error (0, _("Invalid register range"));
a92713e6
RS
2944 return 0;
2945 }
df58fc94 2946
a92713e6
RS
2947 token.u.reg_range.regno1 = regno1;
2948 token.u.reg_range.regno2 = regno2;
2949 mips_add_token (&token, OT_REG_RANGE);
2950 return s;
2951 }
2952 else if (*s == '[')
df58fc94 2953 {
a92713e6
RS
2954 /* A vector element. */
2955 expressionS element;
2956
2957 ++s;
2958 SKIP_SPACE_TABS (s);
2959 my_getExpression (&element, s);
2960 if (element.X_op != O_constant)
2961 {
e3de51ce 2962 set_insn_error (0, _("Vector element must be constant"));
a92713e6
RS
2963 return 0;
2964 }
2965 s = expr_end;
2966 SKIP_SPACE_TABS (s);
2967 if (*s != ']')
2968 {
e3de51ce 2969 set_insn_error (0, _("Missing `]'"));
a92713e6
RS
2970 return 0;
2971 }
2972 ++s;
2973
2974 token.u.reg_element.regno = regno1;
2975 token.u.reg_element.index = element.X_add_number;
2976 mips_add_token (&token, OT_REG_ELEMENT);
2977 return s;
df58fc94 2978 }
df58fc94 2979
a92713e6
RS
2980 /* Looks like just a plain register. */
2981 token.u.regno = regno1;
2982 mips_add_token (&token, OT_REG);
2983 return s;
df58fc94
RS
2984 }
2985
a92713e6
RS
2986 if (float_format)
2987 {
2988 /* First try to treat expressions as floats. */
2989 save_in = input_line_pointer;
2990 input_line_pointer = s;
2991 err = md_atof (float_format, (char *) token.u.flt.data,
2992 &token.u.flt.length);
2993 end = input_line_pointer;
2994 input_line_pointer = save_in;
2995 if (err && *err)
2996 {
e3de51ce 2997 set_insn_error (0, err);
a92713e6
RS
2998 return 0;
2999 }
3000 if (s != end)
3001 {
3002 mips_add_token (&token, OT_FLOAT);
3003 return end;
3004 }
3005 }
3006
3007 /* Treat everything else as an integer expression. */
3008 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3009 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3010 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3011 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3012 s = expr_end;
3013 mips_add_token (&token, OT_INTEGER);
3014 return s;
3015}
3016
3017/* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3018 if expressions should be treated as 32-bit floating-point constants,
3019 'd' if they should be treated as 64-bit floating-point constants,
3020 or 0 if they should be treated as integer expressions (the usual case).
3021
3022 Return a list of tokens on success, otherwise return 0. The caller
3023 must obstack_free the list after use. */
3024
3025static struct mips_operand_token *
3026mips_parse_arguments (char *s, char float_format)
3027{
3028 struct mips_operand_token token;
3029
3030 SKIP_SPACE_TABS (s);
3031 while (*s)
3032 {
3033 s = mips_parse_argument_token (s, float_format);
3034 if (!s)
3035 {
3036 obstack_free (&mips_operand_tokens,
3037 obstack_finish (&mips_operand_tokens));
3038 return 0;
3039 }
3040 SKIP_SPACE_TABS (s);
3041 }
3042 mips_add_token (&token, OT_END);
3043 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
df58fc94
RS
3044}
3045
d301a56b
RS
3046/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3047 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
037b32b9
AN
3048
3049static bfd_boolean
f79e2745 3050is_opcode_valid (const struct mips_opcode *mo)
037b32b9
AN
3051{
3052 int isa = mips_opts.isa;
846ef2d0 3053 int ase = mips_opts.ase;
037b32b9 3054 int fp_s, fp_d;
c6278170 3055 unsigned int i;
037b32b9 3056
c6278170
RS
3057 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3058 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3059 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3060 ase |= mips_ases[i].flags64;
037b32b9 3061
d301a56b 3062 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
037b32b9
AN
3063 return FALSE;
3064
3065 /* Check whether the instruction or macro requires single-precision or
3066 double-precision floating-point support. Note that this information is
3067 stored differently in the opcode table for insns and macros. */
3068 if (mo->pinfo == INSN_MACRO)
3069 {
3070 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3071 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3072 }
3073 else
3074 {
3075 fp_s = mo->pinfo & FP_S;
3076 fp_d = mo->pinfo & FP_D;
3077 }
3078
3079 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3080 return FALSE;
3081
3082 if (fp_s && mips_opts.soft_float)
3083 return FALSE;
3084
3085 return TRUE;
3086}
3087
3088/* Return TRUE if the MIPS16 opcode MO is valid on the currently
3089 selected ISA and architecture. */
3090
3091static bfd_boolean
3092is_opcode_valid_16 (const struct mips_opcode *mo)
3093{
d301a56b 3094 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
037b32b9
AN
3095}
3096
df58fc94
RS
3097/* Return TRUE if the size of the microMIPS opcode MO matches one
3098 explicitly requested. Always TRUE in the standard MIPS mode. */
3099
3100static bfd_boolean
3101is_size_valid (const struct mips_opcode *mo)
3102{
3103 if (!mips_opts.micromips)
3104 return TRUE;
3105
833794fc
MR
3106 if (mips_opts.insn32)
3107 {
3108 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3109 return FALSE;
3110 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3111 return FALSE;
3112 }
df58fc94
RS
3113 if (!forced_insn_length)
3114 return TRUE;
3115 if (mo->pinfo == INSN_MACRO)
3116 return FALSE;
3117 return forced_insn_length == micromips_insn_length (mo);
3118}
3119
3120/* Return TRUE if the microMIPS opcode MO is valid for the delay slot
e64af278
MR
3121 of the preceding instruction. Always TRUE in the standard MIPS mode.
3122
3123 We don't accept macros in 16-bit delay slots to avoid a case where
3124 a macro expansion fails because it relies on a preceding 32-bit real
3125 instruction to have matched and does not handle the operands correctly.
3126 The only macros that may expand to 16-bit instructions are JAL that
3127 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3128 and BGT (that likewise cannot be placed in a delay slot) that decay to
3129 a NOP. In all these cases the macros precede any corresponding real
3130 instruction definitions in the opcode table, so they will match in the
3131 second pass where the size of the delay slot is ignored and therefore
3132 produce correct code. */
df58fc94
RS
3133
3134static bfd_boolean
3135is_delay_slot_valid (const struct mips_opcode *mo)
3136{
3137 if (!mips_opts.micromips)
3138 return TRUE;
3139
3140 if (mo->pinfo == INSN_MACRO)
c06dec14 3141 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
df58fc94
RS
3142 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3143 && micromips_insn_length (mo) != 4)
3144 return FALSE;
3145 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3146 && micromips_insn_length (mo) != 2)
3147 return FALSE;
3148
3149 return TRUE;
3150}
3151
fc76e730
RS
3152/* For consistency checking, verify that all bits of OPCODE are specified
3153 either by the match/mask part of the instruction definition, or by the
3154 operand list. Also build up a list of operands in OPERANDS.
3155
3156 INSN_BITS says which bits of the instruction are significant.
3157 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3158 provides the mips_operand description of each operand. DECODE_OPERAND
3159 is null for MIPS16 instructions. */
ab902481
RS
3160
3161static int
3162validate_mips_insn (const struct mips_opcode *opcode,
3163 unsigned long insn_bits,
fc76e730
RS
3164 const struct mips_operand *(*decode_operand) (const char *),
3165 struct mips_operand_array *operands)
ab902481
RS
3166{
3167 const char *s;
fc76e730 3168 unsigned long used_bits, doubled, undefined, opno, mask;
ab902481
RS
3169 const struct mips_operand *operand;
3170
fc76e730
RS
3171 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3172 if ((mask & opcode->match) != opcode->match)
ab902481
RS
3173 {
3174 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3175 opcode->name, opcode->args);
3176 return 0;
3177 }
3178 used_bits = 0;
fc76e730 3179 opno = 0;
14daeee3
RS
3180 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3181 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
ab902481
RS
3182 for (s = opcode->args; *s; ++s)
3183 switch (*s)
3184 {
3185 case ',':
3186 case '(':
3187 case ')':
3188 break;
3189
14daeee3
RS
3190 case '#':
3191 s++;
3192 break;
3193
ab902481 3194 default:
fc76e730
RS
3195 if (!decode_operand)
3196 operand = decode_mips16_operand (*s, FALSE);
3197 else
3198 operand = decode_operand (s);
3199 if (!operand && opcode->pinfo != INSN_MACRO)
ab902481
RS
3200 {
3201 as_bad (_("internal: unknown operand type: %s %s"),
3202 opcode->name, opcode->args);
3203 return 0;
3204 }
fc76e730
RS
3205 gas_assert (opno < MAX_OPERANDS);
3206 operands->operand[opno] = operand;
14daeee3 3207 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
fc76e730 3208 {
14daeee3 3209 used_bits = mips_insert_operand (operand, used_bits, -1);
fc76e730
RS
3210 if (operand->type == OP_MDMX_IMM_REG)
3211 /* Bit 5 is the format selector (OB vs QH). The opcode table
3212 has separate entries for each format. */
3213 used_bits &= ~(1 << (operand->lsb + 5));
3214 if (operand->type == OP_ENTRY_EXIT_LIST)
3215 used_bits &= ~(mask & 0x700);
3216 }
ab902481 3217 /* Skip prefix characters. */
fc76e730 3218 if (decode_operand && (*s == '+' || *s == 'm'))
ab902481 3219 ++s;
fc76e730 3220 opno += 1;
ab902481
RS
3221 break;
3222 }
fc76e730 3223 doubled = used_bits & mask & insn_bits;
ab902481
RS
3224 if (doubled)
3225 {
3226 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3227 " %s %s"), doubled, opcode->name, opcode->args);
3228 return 0;
3229 }
fc76e730 3230 used_bits |= mask;
ab902481 3231 undefined = ~used_bits & insn_bits;
fc76e730 3232 if (opcode->pinfo != INSN_MACRO && undefined)
ab902481
RS
3233 {
3234 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3235 undefined, opcode->name, opcode->args);
3236 return 0;
3237 }
3238 used_bits &= ~insn_bits;
3239 if (used_bits)
3240 {
3241 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3242 used_bits, opcode->name, opcode->args);
3243 return 0;
3244 }
3245 return 1;
3246}
3247
fc76e730
RS
3248/* The MIPS16 version of validate_mips_insn. */
3249
3250static int
3251validate_mips16_insn (const struct mips_opcode *opcode,
3252 struct mips_operand_array *operands)
3253{
3254 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3255 {
3256 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3257 instruction. Use TMP to describe the full instruction. */
3258 struct mips_opcode tmp;
3259
3260 tmp = *opcode;
3261 tmp.match <<= 16;
3262 tmp.mask <<= 16;
3263 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3264 }
3265 return validate_mips_insn (opcode, 0xffff, 0, operands);
3266}
3267
ab902481
RS
3268/* The microMIPS version of validate_mips_insn. */
3269
3270static int
fc76e730
RS
3271validate_micromips_insn (const struct mips_opcode *opc,
3272 struct mips_operand_array *operands)
ab902481
RS
3273{
3274 unsigned long insn_bits;
3275 unsigned long major;
3276 unsigned int length;
3277
fc76e730
RS
3278 if (opc->pinfo == INSN_MACRO)
3279 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3280 operands);
3281
ab902481
RS
3282 length = micromips_insn_length (opc);
3283 if (length != 2 && length != 4)
3284 {
3285 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3286 "%s %s"), length, opc->name, opc->args);
3287 return 0;
3288 }
3289 major = opc->match >> (10 + 8 * (length - 2));
3290 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3291 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3292 {
3293 as_bad (_("Internal error: bad microMIPS opcode "
3294 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3295 return 0;
3296 }
3297
3298 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3299 insn_bits = 1 << 4 * length;
3300 insn_bits <<= 4 * length;
3301 insn_bits -= 1;
fc76e730
RS
3302 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3303 operands);
ab902481
RS
3304}
3305
707bfff6
TS
3306/* This function is called once, at assembler startup time. It should set up
3307 all the tables, etc. that the MD part of the assembler will need. */
156c2f8b 3308
252b5132 3309void
17a2f251 3310md_begin (void)
252b5132 3311{
3994f87e 3312 const char *retval = NULL;
156c2f8b 3313 int i = 0;
252b5132 3314 int broken = 0;
1f25f5d3 3315
0a44bf69
RS
3316 if (mips_pic != NO_PIC)
3317 {
3318 if (g_switch_seen && g_switch_value != 0)
3319 as_bad (_("-G may not be used in position-independent code"));
3320 g_switch_value = 0;
3321 }
3322
fef14a42 3323 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
252b5132
RH
3324 as_warn (_("Could not set architecture and machine"));
3325
252b5132
RH
3326 op_hash = hash_new ();
3327
fc76e730 3328 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
252b5132
RH
3329 for (i = 0; i < NUMOPCODES;)
3330 {
3331 const char *name = mips_opcodes[i].name;
3332
17a2f251 3333 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
252b5132
RH
3334 if (retval != NULL)
3335 {
3336 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3337 mips_opcodes[i].name, retval);
3338 /* Probably a memory allocation problem? Give up now. */
3339 as_fatal (_("Broken assembler. No assembly attempted."));
3340 }
3341 do
3342 {
fc76e730
RS
3343 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3344 decode_mips_operand, &mips_operands[i]))
3345 broken = 1;
3346 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
252b5132 3347 {
fc76e730
RS
3348 create_insn (&nop_insn, mips_opcodes + i);
3349 if (mips_fix_loongson2f_nop)
3350 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3351 nop_insn.fixed_p = 1;
252b5132
RH
3352 }
3353 ++i;
3354 }
3355 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3356 }
3357
3358 mips16_op_hash = hash_new ();
fc76e730
RS
3359 mips16_operands = XCNEWVEC (struct mips_operand_array,
3360 bfd_mips16_num_opcodes);
252b5132
RH
3361
3362 i = 0;
3363 while (i < bfd_mips16_num_opcodes)
3364 {
3365 const char *name = mips16_opcodes[i].name;
3366
17a2f251 3367 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
252b5132
RH
3368 if (retval != NULL)
3369 as_fatal (_("internal: can't hash `%s': %s"),
3370 mips16_opcodes[i].name, retval);
3371 do
3372 {
fc76e730
RS
3373 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3374 broken = 1;
1e915849
RS
3375 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3376 {
3377 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3378 mips16_nop_insn.fixed_p = 1;
3379 }
252b5132
RH
3380 ++i;
3381 }
3382 while (i < bfd_mips16_num_opcodes
3383 && strcmp (mips16_opcodes[i].name, name) == 0);
3384 }
3385
df58fc94 3386 micromips_op_hash = hash_new ();
fc76e730
RS
3387 micromips_operands = XCNEWVEC (struct mips_operand_array,
3388 bfd_micromips_num_opcodes);
df58fc94
RS
3389
3390 i = 0;
3391 while (i < bfd_micromips_num_opcodes)
3392 {
3393 const char *name = micromips_opcodes[i].name;
3394
3395 retval = hash_insert (micromips_op_hash, name,
3396 (void *) &micromips_opcodes[i]);
3397 if (retval != NULL)
3398 as_fatal (_("internal: can't hash `%s': %s"),
3399 micromips_opcodes[i].name, retval);
3400 do
fc76e730
RS
3401 {
3402 struct mips_cl_insn *micromips_nop_insn;
3403
3404 if (!validate_micromips_insn (&micromips_opcodes[i],
3405 &micromips_operands[i]))
3406 broken = 1;
3407
3408 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3409 {
3410 if (micromips_insn_length (micromips_opcodes + i) == 2)
3411 micromips_nop_insn = &micromips_nop16_insn;
3412 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3413 micromips_nop_insn = &micromips_nop32_insn;
3414 else
3415 continue;
3416
3417 if (micromips_nop_insn->insn_mo == NULL
3418 && strcmp (name, "nop") == 0)
3419 {
3420 create_insn (micromips_nop_insn, micromips_opcodes + i);
3421 micromips_nop_insn->fixed_p = 1;
3422 }
3423 }
3424 }
df58fc94
RS
3425 while (++i < bfd_micromips_num_opcodes
3426 && strcmp (micromips_opcodes[i].name, name) == 0);
3427 }
3428
252b5132
RH
3429 if (broken)
3430 as_fatal (_("Broken assembler. No assembly attempted."));
3431
3432 /* We add all the general register names to the symbol table. This
3433 helps us detect invalid uses of them. */
707bfff6
TS
3434 for (i = 0; reg_names[i].name; i++)
3435 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
8fc4ee9b 3436 reg_names[i].num, /* & RNUM_MASK, */
707bfff6
TS
3437 &zero_address_frag));
3438 if (HAVE_NEWABI)
3439 for (i = 0; reg_names_n32n64[i].name; i++)
3440 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
8fc4ee9b 3441 reg_names_n32n64[i].num, /* & RNUM_MASK, */
252b5132 3442 &zero_address_frag));
707bfff6
TS
3443 else
3444 for (i = 0; reg_names_o32[i].name; i++)
3445 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
8fc4ee9b 3446 reg_names_o32[i].num, /* & RNUM_MASK, */
6047c971 3447 &zero_address_frag));
6047c971 3448
14daeee3
RS
3449 for (i = 0; i < 32; i++)
3450 {
3451 char regname[7];
3452
3453 /* R5900 VU0 floating-point register. */
3454 regname[sizeof (rename) - 1] = 0;
3455 snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
3456 symbol_table_insert (symbol_new (regname, reg_section,
3457 RTYPE_VF | i, &zero_address_frag));
3458
3459 /* R5900 VU0 integer register. */
3460 snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
3461 symbol_table_insert (symbol_new (regname, reg_section,
3462 RTYPE_VI | i, &zero_address_frag));
3463
3464 }
3465
a92713e6
RS
3466 obstack_init (&mips_operand_tokens);
3467
7d10b47d 3468 mips_no_prev_insn ();
252b5132
RH
3469
3470 mips_gprmask = 0;
3471 mips_cprmask[0] = 0;
3472 mips_cprmask[1] = 0;
3473 mips_cprmask[2] = 0;
3474 mips_cprmask[3] = 0;
3475
3476 /* set the default alignment for the text section (2**2) */
3477 record_alignment (text_section, 2);
3478
4d0d148d 3479 bfd_set_gp_size (stdoutput, g_switch_value);
252b5132 3480
f3ded42a
RS
3481 /* On a native system other than VxWorks, sections must be aligned
3482 to 16 byte boundaries. When configured for an embedded ELF
3483 target, we don't bother. */
3484 if (strncmp (TARGET_OS, "elf", 3) != 0
3485 && strncmp (TARGET_OS, "vxworks", 7) != 0)
252b5132 3486 {
f3ded42a
RS
3487 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3488 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3489 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3490 }
252b5132 3491
f3ded42a
RS
3492 /* Create a .reginfo section for register masks and a .mdebug
3493 section for debugging information. */
3494 {
3495 segT seg;
3496 subsegT subseg;
3497 flagword flags;
3498 segT sec;
3499
3500 seg = now_seg;
3501 subseg = now_subseg;
3502
3503 /* The ABI says this section should be loaded so that the
3504 running program can access it. However, we don't load it
3505 if we are configured for an embedded target */
3506 flags = SEC_READONLY | SEC_DATA;
3507 if (strncmp (TARGET_OS, "elf", 3) != 0)
3508 flags |= SEC_ALLOC | SEC_LOAD;
3509
3510 if (mips_abi != N64_ABI)
252b5132 3511 {
f3ded42a 3512 sec = subseg_new (".reginfo", (subsegT) 0);
bdaaa2e1 3513
f3ded42a
RS
3514 bfd_set_section_flags (stdoutput, sec, flags);
3515 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
252b5132 3516
f3ded42a
RS
3517 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3518 }
3519 else
3520 {
3521 /* The 64-bit ABI uses a .MIPS.options section rather than
3522 .reginfo section. */
3523 sec = subseg_new (".MIPS.options", (subsegT) 0);
3524 bfd_set_section_flags (stdoutput, sec, flags);
3525 bfd_set_section_alignment (stdoutput, sec, 3);
252b5132 3526
f3ded42a
RS
3527 /* Set up the option header. */
3528 {
3529 Elf_Internal_Options opthdr;
3530 char *f;
3531
3532 opthdr.kind = ODK_REGINFO;
3533 opthdr.size = (sizeof (Elf_External_Options)
3534 + sizeof (Elf64_External_RegInfo));
3535 opthdr.section = 0;
3536 opthdr.info = 0;
3537 f = frag_more (sizeof (Elf_External_Options));
3538 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3539 (Elf_External_Options *) f);
3540
3541 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3542 }
3543 }
252b5132 3544
f3ded42a
RS
3545 if (ECOFF_DEBUGGING)
3546 {
3547 sec = subseg_new (".mdebug", (subsegT) 0);
3548 (void) bfd_set_section_flags (stdoutput, sec,
3549 SEC_HAS_CONTENTS | SEC_READONLY);
3550 (void) bfd_set_section_alignment (stdoutput, sec, 2);
252b5132 3551 }
f3ded42a
RS
3552 else if (mips_flag_pdr)
3553 {
3554 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3555 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3556 SEC_READONLY | SEC_RELOC
3557 | SEC_DEBUGGING);
3558 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3559 }
3560
3561 subseg_set (seg, subseg);
3562 }
252b5132
RH
3563
3564 if (! ECOFF_DEBUGGING)
3565 md_obj_begin ();
71400594
RS
3566
3567 if (mips_fix_vr4120)
3568 init_vr4120_conflicts ();
252b5132
RH
3569}
3570
3571void
17a2f251 3572md_mips_end (void)
252b5132 3573{
02b1ab82 3574 mips_emit_delays ();
252b5132
RH
3575 if (! ECOFF_DEBUGGING)
3576 md_obj_end ();
3577}
3578
3579void
17a2f251 3580md_assemble (char *str)
252b5132
RH
3581{
3582 struct mips_cl_insn insn;
f6688943
TS
3583 bfd_reloc_code_real_type unused_reloc[3]
3584 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132
RH
3585
3586 imm_expr.X_op = O_absent;
5f74bc13 3587 imm2_expr.X_op = O_absent;
252b5132 3588 offset_expr.X_op = O_absent;
f6688943
TS
3589 offset_reloc[0] = BFD_RELOC_UNUSED;
3590 offset_reloc[1] = BFD_RELOC_UNUSED;
3591 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132 3592
e1b47bd5
RS
3593 mips_mark_labels ();
3594 mips_assembling_insn = TRUE;
e3de51ce 3595 clear_insn_error ();
e1b47bd5 3596
252b5132
RH
3597 if (mips_opts.mips16)
3598 mips16_ip (str, &insn);
3599 else
3600 {
3601 mips_ip (str, &insn);
beae10d5
KH
3602 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3603 str, insn.insn_opcode));
252b5132
RH
3604 }
3605
e3de51ce
RS
3606 if (insn_error.msg)
3607 report_insn_error (str);
e1b47bd5 3608 else if (insn.insn_mo->pinfo == INSN_MACRO)
252b5132 3609 {
584892a6 3610 macro_start ();
252b5132
RH
3611 if (mips_opts.mips16)
3612 mips16_macro (&insn);
3613 else
833794fc 3614 macro (&insn, str);
584892a6 3615 macro_end ();
252b5132
RH
3616 }
3617 else
3618 {
77bd4346 3619 if (offset_expr.X_op != O_absent)
df58fc94 3620 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
252b5132 3621 else
df58fc94 3622 append_insn (&insn, NULL, unused_reloc, FALSE);
252b5132 3623 }
e1b47bd5
RS
3624
3625 mips_assembling_insn = FALSE;
252b5132
RH
3626}
3627
738e5348
RS
3628/* Convenience functions for abstracting away the differences between
3629 MIPS16 and non-MIPS16 relocations. */
3630
3631static inline bfd_boolean
3632mips16_reloc_p (bfd_reloc_code_real_type reloc)
3633{
3634 switch (reloc)
3635 {
3636 case BFD_RELOC_MIPS16_JMP:
3637 case BFD_RELOC_MIPS16_GPREL:
3638 case BFD_RELOC_MIPS16_GOT16:
3639 case BFD_RELOC_MIPS16_CALL16:
3640 case BFD_RELOC_MIPS16_HI16_S:
3641 case BFD_RELOC_MIPS16_HI16:
3642 case BFD_RELOC_MIPS16_LO16:
3643 return TRUE;
3644
3645 default:
3646 return FALSE;
3647 }
3648}
3649
df58fc94
RS
3650static inline bfd_boolean
3651micromips_reloc_p (bfd_reloc_code_real_type reloc)
3652{
3653 switch (reloc)
3654 {
3655 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3656 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3657 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3658 case BFD_RELOC_MICROMIPS_GPREL16:
3659 case BFD_RELOC_MICROMIPS_JMP:
3660 case BFD_RELOC_MICROMIPS_HI16:
3661 case BFD_RELOC_MICROMIPS_HI16_S:
3662 case BFD_RELOC_MICROMIPS_LO16:
3663 case BFD_RELOC_MICROMIPS_LITERAL:
3664 case BFD_RELOC_MICROMIPS_GOT16:
3665 case BFD_RELOC_MICROMIPS_CALL16:
3666 case BFD_RELOC_MICROMIPS_GOT_HI16:
3667 case BFD_RELOC_MICROMIPS_GOT_LO16:
3668 case BFD_RELOC_MICROMIPS_CALL_HI16:
3669 case BFD_RELOC_MICROMIPS_CALL_LO16:
3670 case BFD_RELOC_MICROMIPS_SUB:
3671 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3672 case BFD_RELOC_MICROMIPS_GOT_OFST:
3673 case BFD_RELOC_MICROMIPS_GOT_DISP:
3674 case BFD_RELOC_MICROMIPS_HIGHEST:
3675 case BFD_RELOC_MICROMIPS_HIGHER:
3676 case BFD_RELOC_MICROMIPS_SCN_DISP:
3677 case BFD_RELOC_MICROMIPS_JALR:
3678 return TRUE;
3679
3680 default:
3681 return FALSE;
3682 }
3683}
3684
2309ddf2
MR
3685static inline bfd_boolean
3686jmp_reloc_p (bfd_reloc_code_real_type reloc)
3687{
3688 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3689}
3690
738e5348
RS
3691static inline bfd_boolean
3692got16_reloc_p (bfd_reloc_code_real_type reloc)
3693{
2309ddf2 3694 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
df58fc94 3695 || reloc == BFD_RELOC_MICROMIPS_GOT16);
738e5348
RS
3696}
3697
3698static inline bfd_boolean
3699hi16_reloc_p (bfd_reloc_code_real_type reloc)
3700{
2309ddf2 3701 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
df58fc94 3702 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
738e5348
RS
3703}
3704
3705static inline bfd_boolean
3706lo16_reloc_p (bfd_reloc_code_real_type reloc)
3707{
2309ddf2 3708 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
df58fc94
RS
3709 || reloc == BFD_RELOC_MICROMIPS_LO16);
3710}
3711
df58fc94
RS
3712static inline bfd_boolean
3713jalr_reloc_p (bfd_reloc_code_real_type reloc)
3714{
2309ddf2 3715 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
738e5348
RS
3716}
3717
f2ae14a1
RS
3718static inline bfd_boolean
3719gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3720{
3721 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3722 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3723}
3724
2de39019
CM
3725/* Return true if RELOC is a PC-relative relocation that does not have
3726 full address range. */
3727
3728static inline bfd_boolean
3729limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3730{
3731 switch (reloc)
3732 {
3733 case BFD_RELOC_16_PCREL_S2:
3734 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3735 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3736 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3737 return TRUE;
3738
b47468a6
CM
3739 case BFD_RELOC_32_PCREL:
3740 return HAVE_64BIT_ADDRESSES;
3741
2de39019
CM
3742 default:
3743 return FALSE;
3744 }
3745}
b47468a6 3746
5919d012 3747/* Return true if the given relocation might need a matching %lo().
0a44bf69
RS
3748 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3749 need a matching %lo() when applied to local symbols. */
5919d012
RS
3750
3751static inline bfd_boolean
17a2f251 3752reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
5919d012 3753{
3b91255e 3754 return (HAVE_IN_PLACE_ADDENDS
738e5348 3755 && (hi16_reloc_p (reloc)
0a44bf69
RS
3756 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3757 all GOT16 relocations evaluate to "G". */
738e5348
RS
3758 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3759}
3760
3761/* Return the type of %lo() reloc needed by RELOC, given that
3762 reloc_needs_lo_p. */
3763
3764static inline bfd_reloc_code_real_type
3765matching_lo_reloc (bfd_reloc_code_real_type reloc)
3766{
df58fc94
RS
3767 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3768 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3769 : BFD_RELOC_LO16));
5919d012
RS
3770}
3771
3772/* Return true if the given fixup is followed by a matching R_MIPS_LO16
3773 relocation. */
3774
3775static inline bfd_boolean
17a2f251 3776fixup_has_matching_lo_p (fixS *fixp)
5919d012
RS
3777{
3778 return (fixp->fx_next != NULL
738e5348 3779 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
5919d012
RS
3780 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3781 && fixp->fx_offset == fixp->fx_next->fx_offset);
3782}
3783
462427c4
RS
3784/* Move all labels in LABELS to the current insertion point. TEXT_P
3785 says whether the labels refer to text or data. */
404a8071
RS
3786
3787static void
462427c4 3788mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
404a8071
RS
3789{
3790 struct insn_label_list *l;
3791 valueT val;
3792
462427c4 3793 for (l = labels; l != NULL; l = l->next)
404a8071 3794 {
9c2799c2 3795 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
404a8071
RS
3796 symbol_set_frag (l->label, frag_now);
3797 val = (valueT) frag_now_fix ();
df58fc94 3798 /* MIPS16/microMIPS text labels are stored as odd. */
462427c4 3799 if (text_p && HAVE_CODE_COMPRESSION)
404a8071
RS
3800 ++val;
3801 S_SET_VALUE (l->label, val);
3802 }
3803}
3804
462427c4
RS
3805/* Move all labels in insn_labels to the current insertion point
3806 and treat them as text labels. */
3807
3808static void
3809mips_move_text_labels (void)
3810{
3811 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3812}
3813
5f0fe04b
TS
3814static bfd_boolean
3815s_is_linkonce (symbolS *sym, segT from_seg)
3816{
3817 bfd_boolean linkonce = FALSE;
3818 segT symseg = S_GET_SEGMENT (sym);
3819
3820 if (symseg != from_seg && !S_IS_LOCAL (sym))
3821 {
3822 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3823 linkonce = TRUE;
5f0fe04b
TS
3824 /* The GNU toolchain uses an extension for ELF: a section
3825 beginning with the magic string .gnu.linkonce is a
3826 linkonce section. */
3827 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3828 sizeof ".gnu.linkonce" - 1) == 0)
3829 linkonce = TRUE;
5f0fe04b
TS
3830 }
3831 return linkonce;
3832}
3833
e1b47bd5 3834/* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
df58fc94
RS
3835 linker to handle them specially, such as generating jalx instructions
3836 when needed. We also make them odd for the duration of the assembly,
3837 in order to generate the right sort of code. We will make them even
252b5132
RH
3838 in the adjust_symtab routine, while leaving them marked. This is
3839 convenient for the debugger and the disassembler. The linker knows
3840 to make them odd again. */
3841
3842static void
e1b47bd5 3843mips_compressed_mark_label (symbolS *label)
252b5132 3844{
df58fc94 3845 gas_assert (HAVE_CODE_COMPRESSION);
a8dbcb85 3846
f3ded42a
RS
3847 if (mips_opts.mips16)
3848 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3849 else
3850 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
e1b47bd5
RS
3851 if ((S_GET_VALUE (label) & 1) == 0
3852 /* Don't adjust the address if the label is global or weak, or
3853 in a link-once section, since we'll be emitting symbol reloc
3854 references to it which will be patched up by the linker, and
3855 the final value of the symbol may or may not be MIPS16/microMIPS. */
3856 && !S_IS_WEAK (label)
3857 && !S_IS_EXTERNAL (label)
3858 && !s_is_linkonce (label, now_seg))
3859 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3860}
3861
3862/* Mark preceding MIPS16 or microMIPS instruction labels. */
3863
3864static void
3865mips_compressed_mark_labels (void)
3866{
3867 struct insn_label_list *l;
3868
3869 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3870 mips_compressed_mark_label (l->label);
252b5132
RH
3871}
3872
4d7206a2
RS
3873/* End the current frag. Make it a variant frag and record the
3874 relaxation info. */
3875
3876static void
3877relax_close_frag (void)
3878{
584892a6 3879 mips_macro_warning.first_frag = frag_now;
4d7206a2 3880 frag_var (rs_machine_dependent, 0, 0,
584892a6 3881 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4d7206a2
RS
3882 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3883
3884 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3885 mips_relax.first_fixup = 0;
3886}
3887
3888/* Start a new relaxation sequence whose expansion depends on SYMBOL.
3889 See the comment above RELAX_ENCODE for more details. */
3890
3891static void
3892relax_start (symbolS *symbol)
3893{
9c2799c2 3894 gas_assert (mips_relax.sequence == 0);
4d7206a2
RS
3895 mips_relax.sequence = 1;
3896 mips_relax.symbol = symbol;
3897}
3898
3899/* Start generating the second version of a relaxable sequence.
3900 See the comment above RELAX_ENCODE for more details. */
252b5132
RH
3901
3902static void
4d7206a2
RS
3903relax_switch (void)
3904{
9c2799c2 3905 gas_assert (mips_relax.sequence == 1);
4d7206a2
RS
3906 mips_relax.sequence = 2;
3907}
3908
3909/* End the current relaxable sequence. */
3910
3911static void
3912relax_end (void)
3913{
9c2799c2 3914 gas_assert (mips_relax.sequence == 2);
4d7206a2
RS
3915 relax_close_frag ();
3916 mips_relax.sequence = 0;
3917}
3918
11625dd8
RS
3919/* Return true if IP is a delayed branch or jump. */
3920
3921static inline bfd_boolean
3922delayed_branch_p (const struct mips_cl_insn *ip)
3923{
3924 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3925 | INSN_COND_BRANCH_DELAY
3926 | INSN_COND_BRANCH_LIKELY)) != 0;
3927}
3928
3929/* Return true if IP is a compact branch or jump. */
3930
3931static inline bfd_boolean
3932compact_branch_p (const struct mips_cl_insn *ip)
3933{
26545944
RS
3934 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3935 | INSN2_COND_BRANCH)) != 0;
11625dd8
RS
3936}
3937
3938/* Return true if IP is an unconditional branch or jump. */
3939
3940static inline bfd_boolean
3941uncond_branch_p (const struct mips_cl_insn *ip)
3942{
3943 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
26545944 3944 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
11625dd8
RS
3945}
3946
3947/* Return true if IP is a branch-likely instruction. */
3948
3949static inline bfd_boolean
3950branch_likely_p (const struct mips_cl_insn *ip)
3951{
3952 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3953}
3954
14fe068b
RS
3955/* Return the type of nop that should be used to fill the delay slot
3956 of delayed branch IP. */
3957
3958static struct mips_cl_insn *
3959get_delay_slot_nop (const struct mips_cl_insn *ip)
3960{
3961 if (mips_opts.micromips
3962 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3963 return &micromips_nop32_insn;
3964 return NOP_INSN;
3965}
3966
fc76e730
RS
3967/* Return a mask that has bit N set if OPCODE reads the register(s)
3968 in operand N. */
df58fc94
RS
3969
3970static unsigned int
fc76e730 3971insn_read_mask (const struct mips_opcode *opcode)
df58fc94 3972{
fc76e730
RS
3973 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
3974}
df58fc94 3975
fc76e730
RS
3976/* Return a mask that has bit N set if OPCODE writes to the register(s)
3977 in operand N. */
3978
3979static unsigned int
3980insn_write_mask (const struct mips_opcode *opcode)
3981{
3982 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
3983}
3984
3985/* Return a mask of the registers specified by operand OPERAND of INSN.
3986 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3987 is set. */
3988
3989static unsigned int
3990operand_reg_mask (const struct mips_cl_insn *insn,
3991 const struct mips_operand *operand,
3992 unsigned int type_mask)
3993{
3994 unsigned int uval, vsel;
3995
3996 switch (operand->type)
df58fc94 3997 {
fc76e730
RS
3998 case OP_INT:
3999 case OP_MAPPED_INT:
4000 case OP_MSB:
4001 case OP_PCREL:
4002 case OP_PERF_REG:
4003 case OP_ADDIUSP_INT:
4004 case OP_ENTRY_EXIT_LIST:
4005 case OP_REPEAT_DEST_REG:
4006 case OP_REPEAT_PREV_REG:
4007 case OP_PC:
14daeee3
RS
4008 case OP_VU0_SUFFIX:
4009 case OP_VU0_MATCH_SUFFIX:
fc76e730
RS
4010 abort ();
4011
4012 case OP_REG:
0f35dbc4 4013 case OP_OPTIONAL_REG:
fc76e730
RS
4014 {
4015 const struct mips_reg_operand *reg_op;
4016
4017 reg_op = (const struct mips_reg_operand *) operand;
4018 if (!(type_mask & (1 << reg_op->reg_type)))
4019 return 0;
4020 uval = insn_extract_operand (insn, operand);
4021 return 1 << mips_decode_reg_operand (reg_op, uval);
4022 }
4023
4024 case OP_REG_PAIR:
4025 {
4026 const struct mips_reg_pair_operand *pair_op;
4027
4028 pair_op = (const struct mips_reg_pair_operand *) operand;
4029 if (!(type_mask & (1 << pair_op->reg_type)))
4030 return 0;
4031 uval = insn_extract_operand (insn, operand);
4032 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4033 }
4034
4035 case OP_CLO_CLZ_DEST:
4036 if (!(type_mask & (1 << OP_REG_GP)))
4037 return 0;
4038 uval = insn_extract_operand (insn, operand);
4039 return (1 << (uval & 31)) | (1 << (uval >> 5));
4040
4041 case OP_LWM_SWM_LIST:
4042 abort ();
4043
4044 case OP_SAVE_RESTORE_LIST:
4045 abort ();
4046
4047 case OP_MDMX_IMM_REG:
4048 if (!(type_mask & (1 << OP_REG_VEC)))
4049 return 0;
4050 uval = insn_extract_operand (insn, operand);
4051 vsel = uval >> 5;
4052 if ((vsel & 0x18) == 0x18)
4053 return 0;
4054 return 1 << (uval & 31);
df58fc94 4055 }
fc76e730
RS
4056 abort ();
4057}
4058
4059/* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4060 where bit N of OPNO_MASK is set if operand N should be included.
4061 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4062 is set. */
4063
4064static unsigned int
4065insn_reg_mask (const struct mips_cl_insn *insn,
4066 unsigned int type_mask, unsigned int opno_mask)
4067{
4068 unsigned int opno, reg_mask;
4069
4070 opno = 0;
4071 reg_mask = 0;
4072 while (opno_mask != 0)
4073 {
4074 if (opno_mask & 1)
4075 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4076 opno_mask >>= 1;
4077 opno += 1;
4078 }
4079 return reg_mask;
df58fc94
RS
4080}
4081
4c260379
RS
4082/* Return the mask of core registers that IP reads. */
4083
4084static unsigned int
4085gpr_read_mask (const struct mips_cl_insn *ip)
4086{
4087 unsigned long pinfo, pinfo2;
4088 unsigned int mask;
4089
fc76e730 4090 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4c260379
RS
4091 pinfo = ip->insn_mo->pinfo;
4092 pinfo2 = ip->insn_mo->pinfo2;
fc76e730 4093 if (pinfo & INSN_UDI)
4c260379 4094 {
fc76e730
RS
4095 /* UDI instructions have traditionally been assumed to read RS
4096 and RT. */
4097 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4098 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4c260379 4099 }
fc76e730
RS
4100 if (pinfo & INSN_READ_GPR_24)
4101 mask |= 1 << 24;
4102 if (pinfo2 & INSN2_READ_GPR_16)
4103 mask |= 1 << 16;
4104 if (pinfo2 & INSN2_READ_SP)
4105 mask |= 1 << SP;
26545944 4106 if (pinfo2 & INSN2_READ_GPR_31)
fc76e730 4107 mask |= 1 << 31;
fe35f09f
RS
4108 /* Don't include register 0. */
4109 return mask & ~1;
4c260379
RS
4110}
4111
4112/* Return the mask of core registers that IP writes. */
4113
4114static unsigned int
4115gpr_write_mask (const struct mips_cl_insn *ip)
4116{
4117 unsigned long pinfo, pinfo2;
4118 unsigned int mask;
4119
fc76e730 4120 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4c260379
RS
4121 pinfo = ip->insn_mo->pinfo;
4122 pinfo2 = ip->insn_mo->pinfo2;
fc76e730
RS
4123 if (pinfo & INSN_WRITE_GPR_24)
4124 mask |= 1 << 24;
4125 if (pinfo & INSN_WRITE_GPR_31)
4126 mask |= 1 << 31;
4127 if (pinfo & INSN_UDI)
4128 /* UDI instructions have traditionally been assumed to write to RD. */
4129 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4130 if (pinfo2 & INSN2_WRITE_SP)
4131 mask |= 1 << SP;
fe35f09f
RS
4132 /* Don't include register 0. */
4133 return mask & ~1;
4c260379
RS
4134}
4135
4136/* Return the mask of floating-point registers that IP reads. */
4137
4138static unsigned int
4139fpr_read_mask (const struct mips_cl_insn *ip)
4140{
fc76e730 4141 unsigned long pinfo;
4c260379
RS
4142 unsigned int mask;
4143
fc76e730
RS
4144 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4145 insn_read_mask (ip->insn_mo));
4c260379 4146 pinfo = ip->insn_mo->pinfo;
4c260379
RS
4147 /* Conservatively treat all operands to an FP_D instruction are doubles.
4148 (This is overly pessimistic for things like cvt.d.s.) */
4149 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4150 mask |= mask << 1;
4151 return mask;
4152}
4153
4154/* Return the mask of floating-point registers that IP writes. */
4155
4156static unsigned int
4157fpr_write_mask (const struct mips_cl_insn *ip)
4158{
fc76e730 4159 unsigned long pinfo;
4c260379
RS
4160 unsigned int mask;
4161
fc76e730
RS
4162 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4163 insn_write_mask (ip->insn_mo));
4c260379 4164 pinfo = ip->insn_mo->pinfo;
4c260379
RS
4165 /* Conservatively treat all operands to an FP_D instruction are doubles.
4166 (This is overly pessimistic for things like cvt.s.d.) */
4167 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4168 mask |= mask << 1;
4169 return mask;
4170}
4171
a1d78564
RS
4172/* Operand OPNUM of INSN is an odd-numbered floating-point register.
4173 Check whether that is allowed. */
4174
4175static bfd_boolean
4176mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4177{
4178 const char *s = insn->name;
4179
4180 if (insn->pinfo == INSN_MACRO)
4181 /* Let a macro pass, we'll catch it later when it is expanded. */
4182 return TRUE;
4183
4184 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
4185 {
4186 /* Allow odd registers for single-precision ops. */
4187 switch (insn->pinfo & (FP_S | FP_D))
4188 {
4189 case FP_S:
4190 case 0:
4191 return TRUE;
4192 case FP_D:
4193 return FALSE;
4194 default:
4195 break;
4196 }
4197
4198 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4199 s = strchr (insn->name, '.');
4200 if (s != NULL && opnum == 2)
4201 s = strchr (s + 1, '.');
4202 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
4203 }
4204
4205 /* Single-precision coprocessor loads and moves are OK too. */
4206 if ((insn->pinfo & FP_S)
4207 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
4208 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
4209 return TRUE;
4210
4211 return FALSE;
4212}
4213
a1d78564
RS
4214/* Report that user-supplied argument ARGNUM for INSN was VAL, but should
4215 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
4216 this operand is normally printed in hex or decimal. */
4217
4218static void
4219report_bad_range (struct mips_cl_insn *insn, int argnum,
4220 offsetT val, int min_val, int max_val,
4221 bfd_boolean print_hex)
4222{
4223 if (print_hex && val >= 0)
4224 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4225 " was 0x%lx."),
4226 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4227 else if (print_hex)
4228 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4229 " was %ld."),
4230 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4231 else
4232 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
4233 " was %ld."),
4234 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4235}
4236
4237/* Report an invalid combination of position and size operands for a bitfield
4238 operation. POS and SIZE are the values that were given. */
4239
4240static void
4241report_bad_field (offsetT pos, offsetT size)
4242{
4243 as_bad (_("Invalid field specification (position %ld, size %ld)"),
4244 (unsigned long) pos, (unsigned long) size);
4245}
4246
4247/* Information about an instruction argument that we're trying to match. */
4248struct mips_arg_info
4249{
4250 /* The instruction so far. */
4251 struct mips_cl_insn *insn;
4252
a92713e6
RS
4253 /* The first unconsumed operand token. */
4254 struct mips_operand_token *token;
4255
a1d78564
RS
4256 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4257 int opnum;
4258
4259 /* The 1-based argument number, for error reporting. This does not
4260 count elided optional registers, etc.. */
4261 int argnum;
4262
4263 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4264 unsigned int last_regno;
4265
4266 /* If the first operand was an OP_REG, this is the register that it
4267 specified, otherwise it is ILLEGAL_REG. */
4268 unsigned int dest_regno;
4269
4270 /* The value of the last OP_INT operand. Only used for OP_MSB,
4271 where it gives the lsb position. */
4272 unsigned int last_op_int;
4273
a1d78564
RS
4274 /* If true, the OP_INT match routine should treat plain symbolic operands
4275 as if a relocation operator like %lo(...) had been used. This is only
4276 ever true if the operand can be relocated. */
4277 bfd_boolean allow_nonconst;
4278
4279 /* When true, the OP_INT match routine should allow unsigned N-bit
4280 arguments to be used where a signed N-bit operand is expected. */
4281 bfd_boolean lax_max;
4282
a1d78564
RS
4283 /* True if a reference to the current AT register was seen. */
4284 bfd_boolean seen_at;
4285};
4286
1a00e612
RS
4287/* Record that the argument is out of range. */
4288
4289static void
4290match_out_of_range (struct mips_arg_info *arg)
4291{
4292 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4293}
4294
4295/* Record that the argument isn't constant but needs to be. */
4296
4297static void
4298match_not_constant (struct mips_arg_info *arg)
4299{
4300 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4301 arg->argnum);
4302}
4303
a92713e6
RS
4304/* Try to match an OT_CHAR token for character CH. Consume the token
4305 and return true on success, otherwise return false. */
a1d78564 4306
a92713e6
RS
4307static bfd_boolean
4308match_char (struct mips_arg_info *arg, char ch)
a1d78564 4309{
a92713e6
RS
4310 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4311 {
4312 ++arg->token;
4313 if (ch == ',')
4314 arg->argnum += 1;
4315 return TRUE;
4316 }
4317 return FALSE;
4318}
a1d78564 4319
a92713e6
RS
4320/* Try to get an expression from the next tokens in ARG. Consume the
4321 tokens and return true on success, storing the expression value in
4322 VALUE and relocation types in R. */
4323
4324static bfd_boolean
4325match_expression (struct mips_arg_info *arg, expressionS *value,
4326 bfd_reloc_code_real_type *r)
4327{
4328 if (arg->token->type == OT_INTEGER)
a1d78564 4329 {
a92713e6
RS
4330 *value = arg->token->u.integer.value;
4331 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4332 ++arg->token;
4333 return TRUE;
4334 }
4335
4336 /* Error-reporting is more consistent if we treat registers as O_register
4337 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
4338 then handled in the same way. */
4339 if (arg->token->type == OT_REG)
4340 {
4341 value->X_add_number = arg->token->u.regno;
4342 ++arg->token;
a1d78564 4343 }
a92713e6
RS
4344 else if (arg->token[0].type == OT_CHAR
4345 && arg->token[0].u.ch == '('
4346 && arg->token[1].type == OT_REG
4347 && arg->token[2].type == OT_CHAR
4348 && arg->token[2].u.ch == ')')
4349 {
4350 value->X_add_number = arg->token[1].u.regno;
4351 arg->token += 3;
4352 }
4353 else
4354 return FALSE;
4355
4356 value->X_op = O_register;
4357 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4358 return TRUE;
4359}
4360
4361/* Try to get a constant expression from the next tokens in ARG. Consume
4362 the tokens and return return true on success, storing the constant value
4363 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4364 error. */
4365
4366static bfd_boolean
1a00e612 4367match_const_int (struct mips_arg_info *arg, offsetT *value)
a92713e6
RS
4368{
4369 expressionS ex;
4370 bfd_reloc_code_real_type r[3];
a1d78564 4371
a92713e6
RS
4372 if (!match_expression (arg, &ex, r))
4373 return FALSE;
4374
4375 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
a1d78564
RS
4376 *value = ex.X_add_number;
4377 else
4378 {
1a00e612
RS
4379 match_not_constant (arg);
4380 return FALSE;
a1d78564 4381 }
a92713e6 4382 return TRUE;
a1d78564
RS
4383}
4384
4385/* Return the RTYPE_* flags for a register operand of type TYPE that
4386 appears in instruction OPCODE. */
4387
4388static unsigned int
4389convert_reg_type (const struct mips_opcode *opcode,
4390 enum mips_reg_operand_type type)
4391{
4392 switch (type)
4393 {
4394 case OP_REG_GP:
4395 return RTYPE_NUM | RTYPE_GP;
4396
4397 case OP_REG_FP:
4398 /* Allow vector register names for MDMX if the instruction is a 64-bit
4399 FPR load, store or move (including moves to and from GPRs). */
4400 if ((mips_opts.ase & ASE_MDMX)
4401 && (opcode->pinfo & FP_D)
4402 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4403 | INSN_COPROC_MEMORY_DELAY
4404 | INSN_LOAD_COPROC_DELAY
4405 | INSN_LOAD_MEMORY_DELAY
4406 | INSN_STORE_MEMORY)))
4407 return RTYPE_FPU | RTYPE_VEC;
4408 return RTYPE_FPU;
4409
4410 case OP_REG_CCC:
4411 if (opcode->pinfo & (FP_D | FP_S))
4412 return RTYPE_CCC | RTYPE_FCC;
4413 return RTYPE_CCC;
4414
4415 case OP_REG_VEC:
4416 if (opcode->membership & INSN_5400)
4417 return RTYPE_FPU;
4418 return RTYPE_FPU | RTYPE_VEC;
4419
4420 case OP_REG_ACC:
4421 return RTYPE_ACC;
4422
4423 case OP_REG_COPRO:
4424 if (opcode->name[strlen (opcode->name) - 1] == '0')
4425 return RTYPE_NUM | RTYPE_CP0;
4426 return RTYPE_NUM;
4427
4428 case OP_REG_HW:
4429 return RTYPE_NUM;
14daeee3
RS
4430
4431 case OP_REG_VI:
4432 return RTYPE_NUM | RTYPE_VI;
4433
4434 case OP_REG_VF:
4435 return RTYPE_NUM | RTYPE_VF;
4436
4437 case OP_REG_R5900_I:
4438 return RTYPE_R5900_I;
4439
4440 case OP_REG_R5900_Q:
4441 return RTYPE_R5900_Q;
4442
4443 case OP_REG_R5900_R:
4444 return RTYPE_R5900_R;
4445
4446 case OP_REG_R5900_ACC:
4447 return RTYPE_R5900_ACC;
a1d78564
RS
4448 }
4449 abort ();
4450}
4451
4452/* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4453
4454static void
4455check_regno (struct mips_arg_info *arg,
4456 enum mips_reg_operand_type type, unsigned int regno)
4457{
4458 if (AT && type == OP_REG_GP && regno == AT)
4459 arg->seen_at = TRUE;
4460
4461 if (type == OP_REG_FP
4462 && (regno & 1) != 0
4463 && HAVE_32BIT_FPRS
4464 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4465 as_warn (_("Float register should be even, was %d"), regno);
4466
4467 if (type == OP_REG_CCC)
4468 {
4469 const char *name;
4470 size_t length;
4471
4472 name = arg->insn->insn_mo->name;
4473 length = strlen (name);
4474 if ((regno & 1) != 0
4475 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4476 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4477 as_warn (_("Condition code register should be even for %s, was %d"),
4478 name, regno);
4479
4480 if ((regno & 3) != 0
4481 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4482 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4483 name, regno);
4484 }
4485}
4486
a92713e6
RS
4487/* ARG is a register with symbol value SYMVAL. Try to interpret it as
4488 a register of type TYPE. Return true on success, storing the register
4489 number in *REGNO and warning about any dubious uses. */
4490
4491static bfd_boolean
4492match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4493 unsigned int symval, unsigned int *regno)
4494{
4495 if (type == OP_REG_VEC)
4496 symval = mips_prefer_vec_regno (symval);
4497 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4498 return FALSE;
4499
4500 *regno = symval & RNUM_MASK;
4501 check_regno (arg, type, *regno);
4502 return TRUE;
4503}
4504
4505/* Try to interpret the next token in ARG as a register of type TYPE.
4506 Consume the token and return true on success, storing the register
4507 number in *REGNO. Return false on failure. */
4508
4509static bfd_boolean
4510match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4511 unsigned int *regno)
4512{
4513 if (arg->token->type == OT_REG
4514 && match_regno (arg, type, arg->token->u.regno, regno))
4515 {
4516 ++arg->token;
4517 return TRUE;
4518 }
4519 return FALSE;
4520}
4521
4522/* Try to interpret the next token in ARG as a range of registers of type TYPE.
4523 Consume the token and return true on success, storing the register numbers
4524 in *REGNO1 and *REGNO2. Return false on failure. */
4525
4526static bfd_boolean
4527match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4528 unsigned int *regno1, unsigned int *regno2)
4529{
4530 if (match_reg (arg, type, regno1))
4531 {
4532 *regno2 = *regno1;
4533 return TRUE;
4534 }
4535 if (arg->token->type == OT_REG_RANGE
4536 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4537 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4538 && *regno1 <= *regno2)
4539 {
4540 ++arg->token;
4541 return TRUE;
4542 }
4543 return FALSE;
4544}
4545
a1d78564
RS
4546/* OP_INT matcher. */
4547
a92713e6 4548static bfd_boolean
a1d78564 4549match_int_operand (struct mips_arg_info *arg,
a92713e6 4550 const struct mips_operand *operand_base)
a1d78564
RS
4551{
4552 const struct mips_int_operand *operand;
3ccad066 4553 unsigned int uval;
a1d78564
RS
4554 int min_val, max_val, factor;
4555 offsetT sval;
a1d78564
RS
4556
4557 operand = (const struct mips_int_operand *) operand_base;
4558 factor = 1 << operand->shift;
3ccad066
RS
4559 min_val = mips_int_operand_min (operand);
4560 max_val = mips_int_operand_max (operand);
a1d78564 4561 if (arg->lax_max)
3ccad066 4562 max_val = ((1 << operand_base->size) - 1) << operand->shift;
a1d78564 4563
a92713e6
RS
4564 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4565 /* Assume we have an elided offset. The later match will fail
4566 if this turns out to be wrong. */
4567 sval = 0;
4568 else if (operand_base->lsb == 0
4569 && operand_base->size == 16
4570 && operand->shift == 0
4571 && operand->bias == 0
4572 && (operand->max_val == 32767 || operand->max_val == 65535))
a1d78564
RS
4573 {
4574 /* The operand can be relocated. */
a92713e6
RS
4575 if (!match_expression (arg, &offset_expr, offset_reloc))
4576 return FALSE;
4577
4578 if (offset_reloc[0] != BFD_RELOC_UNUSED)
a1d78564
RS
4579 /* Relocation operators were used. Accept the arguent and
4580 leave the relocation value in offset_expr and offset_relocs
4581 for the caller to process. */
a92713e6
RS
4582 return TRUE;
4583
4584 if (offset_expr.X_op != O_constant)
a1d78564 4585 {
a92713e6
RS
4586 /* If non-constant operands are allowed then leave them for
4587 the caller to process, otherwise fail the match. */
4588 if (!arg->allow_nonconst)
1a00e612
RS
4589 {
4590 match_not_constant (arg);
4591 return FALSE;
4592 }
a92713e6
RS
4593 offset_reloc[0] = BFD_RELOC_LO16;
4594 return TRUE;
a1d78564 4595 }
a92713e6 4596
a1d78564
RS
4597 /* Clear the global state; we're going to install the operand
4598 ourselves. */
a92713e6 4599 sval = offset_expr.X_add_number;
a1d78564
RS
4600 offset_expr.X_op = O_absent;
4601 }
4602 else
4603 {
1a00e612 4604 if (!match_const_int (arg, &sval))
a92713e6 4605 return FALSE;
a1d78564
RS
4606 }
4607
4608 arg->last_op_int = sval;
4609
1a00e612 4610 if (sval < min_val || sval > max_val || sval % factor)
a1d78564 4611 {
1a00e612
RS
4612 match_out_of_range (arg);
4613 return FALSE;
a1d78564
RS
4614 }
4615
4616 uval = (unsigned int) sval >> operand->shift;
4617 uval -= operand->bias;
4618
4619 /* Handle -mfix-cn63xxp1. */
4620 if (arg->opnum == 1
4621 && mips_fix_cn63xxp1
4622 && !mips_opts.micromips
4623 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4624 switch (uval)
4625 {
4626 case 5:
4627 case 25:
4628 case 26:
4629 case 27:
4630 case 28:
4631 case 29:
4632 case 30:
4633 case 31:
4634 /* These are ok. */
4635 break;
4636
4637 default:
4638 /* The rest must be changed to 28. */
4639 uval = 28;
4640 break;
4641 }
4642
4643 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4644 return TRUE;
a1d78564
RS
4645}
4646
4647/* OP_MAPPED_INT matcher. */
4648
a92713e6 4649static bfd_boolean
a1d78564 4650match_mapped_int_operand (struct mips_arg_info *arg,
a92713e6 4651 const struct mips_operand *operand_base)
a1d78564
RS
4652{
4653 const struct mips_mapped_int_operand *operand;
4654 unsigned int uval, num_vals;
4655 offsetT sval;
4656
4657 operand = (const struct mips_mapped_int_operand *) operand_base;
1a00e612 4658 if (!match_const_int (arg, &sval))
a92713e6 4659 return FALSE;
a1d78564
RS
4660
4661 num_vals = 1 << operand_base->size;
4662 for (uval = 0; uval < num_vals; uval++)
4663 if (operand->int_map[uval] == sval)
4664 break;
4665 if (uval == num_vals)
1a00e612
RS
4666 {
4667 match_out_of_range (arg);
4668 return FALSE;
4669 }
a1d78564
RS
4670
4671 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4672 return TRUE;
a1d78564
RS
4673}
4674
4675/* OP_MSB matcher. */
4676
a92713e6 4677static bfd_boolean
a1d78564 4678match_msb_operand (struct mips_arg_info *arg,
a92713e6 4679 const struct mips_operand *operand_base)
a1d78564
RS
4680{
4681 const struct mips_msb_operand *operand;
4682 int min_val, max_val, max_high;
4683 offsetT size, sval, high;
4684
4685 operand = (const struct mips_msb_operand *) operand_base;
4686 min_val = operand->bias;
4687 max_val = min_val + (1 << operand_base->size) - 1;
4688 max_high = operand->opsize;
4689
1a00e612 4690 if (!match_const_int (arg, &size))
a92713e6 4691 return FALSE;
a1d78564
RS
4692
4693 high = size + arg->last_op_int;
4694 sval = operand->add_lsb ? high : size;
4695
4696 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4697 {
1a00e612
RS
4698 match_out_of_range (arg);
4699 return FALSE;
a1d78564
RS
4700 }
4701 insn_insert_operand (arg->insn, operand_base, sval - min_val);
a92713e6 4702 return TRUE;
a1d78564
RS
4703}
4704
4705/* OP_REG matcher. */
4706
a92713e6 4707static bfd_boolean
a1d78564 4708match_reg_operand (struct mips_arg_info *arg,
a92713e6 4709 const struct mips_operand *operand_base)
a1d78564
RS
4710{
4711 const struct mips_reg_operand *operand;
a92713e6 4712 unsigned int regno, uval, num_vals;
a1d78564
RS
4713
4714 operand = (const struct mips_reg_operand *) operand_base;
a92713e6
RS
4715 if (!match_reg (arg, operand->reg_type, &regno))
4716 return FALSE;
a1d78564
RS
4717
4718 if (operand->reg_map)
4719 {
4720 num_vals = 1 << operand->root.size;
4721 for (uval = 0; uval < num_vals; uval++)
4722 if (operand->reg_map[uval] == regno)
4723 break;
4724 if (num_vals == uval)
a92713e6 4725 return FALSE;
a1d78564
RS
4726 }
4727 else
4728 uval = regno;
4729
a1d78564
RS
4730 arg->last_regno = regno;
4731 if (arg->opnum == 1)
4732 arg->dest_regno = regno;
4733 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4734 return TRUE;
a1d78564
RS
4735}
4736
4737/* OP_REG_PAIR matcher. */
4738
a92713e6 4739static bfd_boolean
a1d78564 4740match_reg_pair_operand (struct mips_arg_info *arg,
a92713e6 4741 const struct mips_operand *operand_base)
a1d78564
RS
4742{
4743 const struct mips_reg_pair_operand *operand;
a92713e6 4744 unsigned int regno1, regno2, uval, num_vals;
a1d78564
RS
4745
4746 operand = (const struct mips_reg_pair_operand *) operand_base;
a92713e6
RS
4747 if (!match_reg (arg, operand->reg_type, &regno1)
4748 || !match_char (arg, ',')
4749 || !match_reg (arg, operand->reg_type, &regno2))
4750 return FALSE;
a1d78564
RS
4751
4752 num_vals = 1 << operand_base->size;
4753 for (uval = 0; uval < num_vals; uval++)
4754 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4755 break;
4756 if (uval == num_vals)
a92713e6 4757 return FALSE;
a1d78564 4758
a1d78564 4759 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 4760 return TRUE;
a1d78564
RS
4761}
4762
4763/* OP_PCREL matcher. The caller chooses the relocation type. */
4764
a92713e6
RS
4765static bfd_boolean
4766match_pcrel_operand (struct mips_arg_info *arg)
a1d78564 4767{
a92713e6
RS
4768 bfd_reloc_code_real_type r[3];
4769
4770 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
a1d78564
RS
4771}
4772
4773/* OP_PERF_REG matcher. */
4774
a92713e6 4775static bfd_boolean
a1d78564 4776match_perf_reg_operand (struct mips_arg_info *arg,
a92713e6 4777 const struct mips_operand *operand)
a1d78564
RS
4778{
4779 offsetT sval;
4780
1a00e612 4781 if (!match_const_int (arg, &sval))
a92713e6 4782 return FALSE;
a1d78564
RS
4783
4784 if (sval != 0
4785 && (sval != 1
4786 || (mips_opts.arch == CPU_R5900
4787 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4788 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4789 {
1a00e612
RS
4790 set_insn_error (arg->argnum, _("invalid performance register"));
4791 return FALSE;
a1d78564
RS
4792 }
4793
4794 insn_insert_operand (arg->insn, operand, sval);
a92713e6 4795 return TRUE;
a1d78564
RS
4796}
4797
4798/* OP_ADDIUSP matcher. */
4799
a92713e6 4800static bfd_boolean
a1d78564 4801match_addiusp_operand (struct mips_arg_info *arg,
a92713e6 4802 const struct mips_operand *operand)
a1d78564
RS
4803{
4804 offsetT sval;
4805 unsigned int uval;
4806
1a00e612 4807 if (!match_const_int (arg, &sval))
a92713e6 4808 return FALSE;
a1d78564
RS
4809
4810 if (sval % 4)
1a00e612
RS
4811 {
4812 match_out_of_range (arg);
4813 return FALSE;
4814 }
a1d78564
RS
4815
4816 sval /= 4;
4817 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
1a00e612
RS
4818 {
4819 match_out_of_range (arg);
4820 return FALSE;
4821 }
a1d78564
RS
4822
4823 uval = (unsigned int) sval;
4824 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4825 insn_insert_operand (arg->insn, operand, uval);
a92713e6 4826 return TRUE;
a1d78564
RS
4827}
4828
4829/* OP_CLO_CLZ_DEST matcher. */
4830
a92713e6 4831static bfd_boolean
a1d78564 4832match_clo_clz_dest_operand (struct mips_arg_info *arg,
a92713e6 4833 const struct mips_operand *operand)
a1d78564
RS
4834{
4835 unsigned int regno;
4836
a92713e6
RS
4837 if (!match_reg (arg, OP_REG_GP, &regno))
4838 return FALSE;
a1d78564 4839
a1d78564 4840 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
a92713e6 4841 return TRUE;
a1d78564
RS
4842}
4843
4844/* OP_LWM_SWM_LIST matcher. */
4845
a92713e6 4846static bfd_boolean
a1d78564 4847match_lwm_swm_list_operand (struct mips_arg_info *arg,
a92713e6 4848 const struct mips_operand *operand)
a1d78564 4849{
a92713e6
RS
4850 unsigned int reglist, sregs, ra, regno1, regno2;
4851 struct mips_arg_info reset;
a1d78564 4852
a92713e6
RS
4853 reglist = 0;
4854 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
4855 return FALSE;
4856 do
4857 {
4858 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4859 {
4860 reglist |= 1 << FP;
4861 regno2 = S7;
4862 }
4863 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4864 reset = *arg;
4865 }
4866 while (match_char (arg, ',')
4867 && match_reg_range (arg, OP_REG_GP, &regno1, &regno2));
4868 *arg = reset;
a1d78564
RS
4869
4870 if (operand->size == 2)
4871 {
4872 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4873
4874 s0, ra
4875 s0, s1, ra, s2, s3
4876 s0-s2, ra
4877
4878 and any permutations of these. */
4879 if ((reglist & 0xfff1ffff) != 0x80010000)
a92713e6 4880 return FALSE;
a1d78564
RS
4881
4882 sregs = (reglist >> 17) & 7;
4883 ra = 0;
4884 }
4885 else
4886 {
4887 /* The list must include at least one of ra and s0-sN,
4888 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4889 which are $23 and $30 respectively.) E.g.:
4890
4891 ra
4892 s0
4893 ra, s0, s1, s2
4894 s0-s8
4895 s0-s5, ra
4896
4897 and any permutations of these. */
4898 if ((reglist & 0x3f00ffff) != 0)
a92713e6 4899 return FALSE;
a1d78564
RS
4900
4901 ra = (reglist >> 27) & 0x10;
4902 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4903 }
4904 sregs += 1;
4905 if ((sregs & -sregs) != sregs)
a92713e6 4906 return FALSE;
a1d78564
RS
4907
4908 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
a92713e6 4909 return TRUE;
a1d78564
RS
4910}
4911
364215c8
RS
4912/* OP_ENTRY_EXIT_LIST matcher. */
4913
a92713e6 4914static unsigned int
364215c8 4915match_entry_exit_operand (struct mips_arg_info *arg,
a92713e6 4916 const struct mips_operand *operand)
364215c8
RS
4917{
4918 unsigned int mask;
4919 bfd_boolean is_exit;
4920
4921 /* The format is the same for both ENTRY and EXIT, but the constraints
4922 are different. */
4923 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4924 mask = (is_exit ? 7 << 3 : 0);
a92713e6 4925 do
364215c8
RS
4926 {
4927 unsigned int regno1, regno2;
4928 bfd_boolean is_freg;
4929
a92713e6 4930 if (match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
364215c8 4931 is_freg = FALSE;
a92713e6 4932 else if (match_reg_range (arg, OP_REG_FP, &regno1, &regno2))
364215c8
RS
4933 is_freg = TRUE;
4934 else
a92713e6 4935 return FALSE;
364215c8
RS
4936
4937 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4938 {
4939 mask &= ~(7 << 3);
4940 mask |= (5 + regno2) << 3;
4941 }
4942 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4943 mask |= (regno2 - 3) << 3;
4944 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4945 mask |= (regno2 - 15) << 1;
4946 else if (regno1 == RA && regno2 == RA)
4947 mask |= 1;
4948 else
a92713e6 4949 return FALSE;
364215c8 4950 }
a92713e6
RS
4951 while (match_char (arg, ','));
4952
364215c8 4953 insn_insert_operand (arg->insn, operand, mask);
a92713e6 4954 return TRUE;
364215c8
RS
4955}
4956
4957/* OP_SAVE_RESTORE_LIST matcher. */
4958
a92713e6
RS
4959static bfd_boolean
4960match_save_restore_list_operand (struct mips_arg_info *arg)
364215c8
RS
4961{
4962 unsigned int opcode, args, statics, sregs;
4963 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
364215c8 4964 offsetT frame_size;
364215c8 4965
364215c8
RS
4966 opcode = arg->insn->insn_opcode;
4967 frame_size = 0;
4968 num_frame_sizes = 0;
4969 args = 0;
4970 statics = 0;
4971 sregs = 0;
a92713e6 4972 do
364215c8
RS
4973 {
4974 unsigned int regno1, regno2;
4975
a92713e6 4976 if (arg->token->type == OT_INTEGER)
364215c8
RS
4977 {
4978 /* Handle the frame size. */
1a00e612 4979 if (!match_const_int (arg, &frame_size))
a92713e6 4980 return FALSE;
364215c8 4981 num_frame_sizes += 1;
364215c8
RS
4982 }
4983 else
4984 {
a92713e6
RS
4985 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
4986 return FALSE;
364215c8
RS
4987
4988 while (regno1 <= regno2)
4989 {
4990 if (regno1 >= 4 && regno1 <= 7)
4991 {
4992 if (num_frame_sizes == 0)
4993 /* args $a0-$a3 */
4994 args |= 1 << (regno1 - 4);
4995 else
4996 /* statics $a0-$a3 */
4997 statics |= 1 << (regno1 - 4);
4998 }
4999 else if (regno1 >= 16 && regno1 <= 23)
5000 /* $s0-$s7 */
5001 sregs |= 1 << (regno1 - 16);
5002 else if (regno1 == 30)
5003 /* $s8 */
5004 sregs |= 1 << 8;
5005 else if (regno1 == 31)
5006 /* Add $ra to insn. */
5007 opcode |= 0x40;
5008 else
a92713e6 5009 return FALSE;
364215c8
RS
5010 regno1 += 1;
5011 if (regno1 == 24)
5012 regno1 = 30;
5013 }
5014 }
364215c8 5015 }
a92713e6 5016 while (match_char (arg, ','));
364215c8
RS
5017
5018 /* Encode args/statics combination. */
5019 if (args & statics)
a92713e6 5020 return FALSE;
364215c8
RS
5021 else if (args == 0xf)
5022 /* All $a0-$a3 are args. */
5023 opcode |= MIPS16_ALL_ARGS << 16;
5024 else if (statics == 0xf)
5025 /* All $a0-$a3 are statics. */
5026 opcode |= MIPS16_ALL_STATICS << 16;
5027 else
5028 {
5029 /* Count arg registers. */
5030 num_args = 0;
5031 while (args & 0x1)
5032 {
5033 args >>= 1;
5034 num_args += 1;
5035 }
5036 if (args != 0)
a92713e6 5037 return FALSE;
364215c8
RS
5038
5039 /* Count static registers. */
5040 num_statics = 0;
5041 while (statics & 0x8)
5042 {
5043 statics = (statics << 1) & 0xf;
5044 num_statics += 1;
5045 }
5046 if (statics != 0)
a92713e6 5047 return FALSE;
364215c8
RS
5048
5049 /* Encode args/statics. */
5050 opcode |= ((num_args << 2) | num_statics) << 16;
5051 }
5052
5053 /* Encode $s0/$s1. */
5054 if (sregs & (1 << 0)) /* $s0 */
5055 opcode |= 0x20;
5056 if (sregs & (1 << 1)) /* $s1 */
5057 opcode |= 0x10;
5058 sregs >>= 2;
5059
5060 /* Encode $s2-$s8. */
5061 num_sregs = 0;
5062 while (sregs & 1)
5063 {
5064 sregs >>= 1;
5065 num_sregs += 1;
5066 }
5067 if (sregs != 0)
a92713e6 5068 return FALSE;
364215c8
RS
5069 opcode |= num_sregs << 24;
5070
5071 /* Encode frame size. */
5072 if (num_frame_sizes == 0)
1a00e612
RS
5073 {
5074 set_insn_error (arg->argnum, _("missing frame size"));
5075 return FALSE;
5076 }
5077 if (num_frame_sizes > 1)
5078 {
5079 set_insn_error (arg->argnum, _("frame size specified twice"));
5080 return FALSE;
5081 }
5082 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5083 {
5084 set_insn_error (arg->argnum, _("invalid frame size"));
5085 return FALSE;
5086 }
5087 if (frame_size != 128 || (opcode >> 16) != 0)
364215c8
RS
5088 {
5089 frame_size /= 8;
5090 opcode |= (((frame_size & 0xf0) << 16)
5091 | (frame_size & 0x0f));
5092 }
5093
364215c8
RS
5094 /* Finally build the instruction. */
5095 if ((opcode >> 16) != 0 || frame_size == 0)
5096 opcode |= MIPS16_EXTEND;
5097 arg->insn->insn_opcode = opcode;
a92713e6 5098 return TRUE;
364215c8
RS
5099}
5100
a1d78564
RS
5101/* OP_MDMX_IMM_REG matcher. */
5102
a92713e6 5103static bfd_boolean
a1d78564 5104match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
a92713e6 5105 const struct mips_operand *operand)
a1d78564 5106{
a92713e6 5107 unsigned int regno, uval;
a1d78564
RS
5108 bfd_boolean is_qh;
5109 const struct mips_opcode *opcode;
5110
5111 /* The mips_opcode records whether this is an octobyte or quadhalf
5112 instruction. Start out with that bit in place. */
5113 opcode = arg->insn->insn_mo;
5114 uval = mips_extract_operand (operand, opcode->match);
5115 is_qh = (uval != 0);
5116
a92713e6 5117 if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT)
a1d78564
RS
5118 {
5119 if ((opcode->membership & INSN_5400)
5120 && strcmp (opcode->name, "rzu.ob") == 0)
5121 {
1a00e612
RS
5122 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5123 arg->argnum);
5124 return FALSE;
a1d78564
RS
5125 }
5126
5127 /* Check whether this is a vector register or a broadcast of
5128 a single element. */
a92713e6 5129 if (arg->token->type == OT_REG_ELEMENT)
a1d78564 5130 {
a92713e6
RS
5131 if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno,
5132 &regno))
5133 return FALSE;
5134 if (arg->token->u.reg_element.index > (is_qh ? 3 : 7))
a1d78564 5135 {
1a00e612
RS
5136 set_insn_error (arg->argnum, _("invalid element selector"));
5137 return FALSE;
a1d78564 5138 }
a1d78564 5139 else
a92713e6 5140 uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5;
a1d78564
RS
5141 }
5142 else
5143 {
5144 /* A full vector. */
5145 if ((opcode->membership & INSN_5400)
5146 && (strcmp (opcode->name, "sll.ob") == 0
5147 || strcmp (opcode->name, "srl.ob") == 0))
5148 {
1a00e612
RS
5149 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5150 arg->argnum);
5151 return FALSE;
a1d78564
RS
5152 }
5153
a92713e6
RS
5154 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, &regno))
5155 return FALSE;
a1d78564
RS
5156 if (is_qh)
5157 uval |= MDMX_FMTSEL_VEC_QH << 5;
5158 else
5159 uval |= MDMX_FMTSEL_VEC_OB << 5;
5160 }
a1d78564 5161 uval |= regno;
a92713e6 5162 ++arg->token;
a1d78564
RS
5163 }
5164 else
5165 {
5166 offsetT sval;
5167
1a00e612 5168 if (!match_const_int (arg, &sval))
a92713e6 5169 return FALSE;
a1d78564
RS
5170 if (sval < 0 || sval > 31)
5171 {
1a00e612
RS
5172 match_out_of_range (arg);
5173 return FALSE;
a1d78564
RS
5174 }
5175 uval |= (sval & 31);
5176 if (is_qh)
5177 uval |= MDMX_FMTSEL_IMM_QH << 5;
5178 else
5179 uval |= MDMX_FMTSEL_IMM_OB << 5;
5180 }
5181 insn_insert_operand (arg->insn, operand, uval);
a92713e6 5182 return TRUE;
a1d78564
RS
5183}
5184
5185/* OP_PC matcher. */
5186
a92713e6
RS
5187static bfd_boolean
5188match_pc_operand (struct mips_arg_info *arg)
a1d78564 5189{
a92713e6
RS
5190 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5191 {
5192 ++arg->token;
5193 return TRUE;
5194 }
5195 return FALSE;
a1d78564
RS
5196}
5197
5198/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5199 register that we need to match. */
5200
a92713e6
RS
5201static bfd_boolean
5202match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
a1d78564
RS
5203{
5204 unsigned int regno;
5205
a92713e6 5206 return match_reg (arg, OP_REG_GP, &regno) && regno == other_regno;
a1d78564
RS
5207}
5208
89565f1b
RS
5209/* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5210 the length of the value in bytes (4 for float, 8 for double) and
5211 USING_GPRS says whether the destination is a GPR rather than an FPR.
5212
5213 Return the constant in IMM and OFFSET as follows:
5214
5215 - If the constant should be loaded via memory, set IMM to O_absent and
5216 OFFSET to the memory address.
5217
5218 - Otherwise, if the constant should be loaded into two 32-bit registers,
5219 set IMM to the O_constant to load into the high register and OFFSET
5220 to the corresponding value for the low register.
5221
5222 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5223
5224 These constants only appear as the last operand in an instruction,
5225 and every instruction that accepts them in any variant accepts them
5226 in all variants. This means we don't have to worry about backing out
5227 any changes if the instruction does not match. We just match
5228 unconditionally and report an error if the constant is invalid. */
5229
a92713e6
RS
5230static bfd_boolean
5231match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5232 expressionS *offset, int length, bfd_boolean using_gprs)
89565f1b 5233{
a92713e6 5234 char *p;
89565f1b
RS
5235 segT seg, new_seg;
5236 subsegT subseg;
5237 const char *newname;
a92713e6 5238 unsigned char *data;
89565f1b
RS
5239
5240 /* Where the constant is placed is based on how the MIPS assembler
5241 does things:
5242
5243 length == 4 && using_gprs -- immediate value only
5244 length == 8 && using_gprs -- .rdata or immediate value
5245 length == 4 && !using_gprs -- .lit4 or immediate value
5246 length == 8 && !using_gprs -- .lit8 or immediate value
5247
5248 The .lit4 and .lit8 sections are only used if permitted by the
5249 -G argument. */
a92713e6 5250 if (arg->token->type != OT_FLOAT)
1a00e612
RS
5251 {
5252 set_insn_error (arg->argnum, _("floating-point expression required"));
5253 return FALSE;
5254 }
a92713e6
RS
5255
5256 gas_assert (arg->token->u.flt.length == length);
5257 data = arg->token->u.flt.data;
5258 ++arg->token;
89565f1b
RS
5259
5260 /* Handle 32-bit constants for which an immediate value is best. */
5261 if (length == 4
5262 && (using_gprs
5263 || g_switch_value < 4
5264 || (data[0] == 0 && data[1] == 0)
5265 || (data[2] == 0 && data[3] == 0)))
5266 {
5267 imm->X_op = O_constant;
5268 if (!target_big_endian)
5269 imm->X_add_number = bfd_getl32 (data);
5270 else
5271 imm->X_add_number = bfd_getb32 (data);
5272 offset->X_op = O_absent;
a92713e6 5273 return TRUE;
89565f1b
RS
5274 }
5275
5276 /* Handle 64-bit constants for which an immediate value is best. */
5277 if (length == 8
5278 && !mips_disable_float_construction
5279 /* Constants can only be constructed in GPRs and copied
5280 to FPRs if the GPRs are at least as wide as the FPRs.
5281 Force the constant into memory if we are using 64-bit FPRs
5282 but the GPRs are only 32 bits wide. */
5283 /* ??? No longer true with the addition of MTHC1, but this
5284 is legacy code... */
5285 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
5286 && ((data[0] == 0 && data[1] == 0)
5287 || (data[2] == 0 && data[3] == 0))
5288 && ((data[4] == 0 && data[5] == 0)
5289 || (data[6] == 0 && data[7] == 0)))
5290 {
5291 /* The value is simple enough to load with a couple of instructions.
5292 If using 32-bit registers, set IMM to the high order 32 bits and
5293 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5294 64 bit constant. */
5295 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
5296 {
5297 imm->X_op = O_constant;
5298 offset->X_op = O_constant;
5299 if (!target_big_endian)
5300 {
5301 imm->X_add_number = bfd_getl32 (data + 4);
5302 offset->X_add_number = bfd_getl32 (data);
5303 }
5304 else
5305 {
5306 imm->X_add_number = bfd_getb32 (data);
5307 offset->X_add_number = bfd_getb32 (data + 4);
5308 }
5309 if (offset->X_add_number == 0)
5310 offset->X_op = O_absent;
5311 }
5312 else
5313 {
5314 imm->X_op = O_constant;
5315 if (!target_big_endian)
5316 imm->X_add_number = bfd_getl64 (data);
5317 else
5318 imm->X_add_number = bfd_getb64 (data);
5319 offset->X_op = O_absent;
5320 }
a92713e6 5321 return TRUE;
89565f1b
RS
5322 }
5323
5324 /* Switch to the right section. */
5325 seg = now_seg;
5326 subseg = now_subseg;
5327 if (length == 4)
5328 {
5329 gas_assert (!using_gprs && g_switch_value >= 4);
5330 newname = ".lit4";
5331 }
5332 else
5333 {
5334 if (using_gprs || g_switch_value < 8)
5335 newname = RDATA_SECTION_NAME;
5336 else
5337 newname = ".lit8";
5338 }
5339
5340 new_seg = subseg_new (newname, (subsegT) 0);
5341 bfd_set_section_flags (stdoutput, new_seg,
5342 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5343 frag_align (length == 4 ? 2 : 3, 0, 0);
5344 if (strncmp (TARGET_OS, "elf", 3) != 0)
5345 record_alignment (new_seg, 4);
5346 else
5347 record_alignment (new_seg, length == 4 ? 2 : 3);
5348 if (seg == now_seg)
5349 as_bad (_("Can't use floating point insn in this section"));
5350
5351 /* Set the argument to the current address in the section. */
5352 imm->X_op = O_absent;
5353 offset->X_op = O_symbol;
5354 offset->X_add_symbol = symbol_temp_new_now ();
5355 offset->X_add_number = 0;
5356
5357 /* Put the floating point number into the section. */
5358 p = frag_more (length);
5359 memcpy (p, data, length);
5360
5361 /* Switch back to the original section. */
5362 subseg_set (seg, subseg);
a92713e6 5363 return TRUE;
89565f1b
RS
5364}
5365
14daeee3
RS
5366/* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5367 them. */
5368
5369static bfd_boolean
5370match_vu0_suffix_operand (struct mips_arg_info *arg,
5371 const struct mips_operand *operand,
5372 bfd_boolean match_p)
5373{
5374 unsigned int uval;
5375
5376 /* The operand can be an XYZW mask or a single 2-bit channel index
5377 (with X being 0). */
5378 gas_assert (operand->size == 2 || operand->size == 4);
5379
ee5734f0 5380 /* The suffix can be omitted when it is already part of the opcode. */
14daeee3 5381 if (arg->token->type != OT_CHANNELS)
ee5734f0 5382 return match_p;
14daeee3
RS
5383
5384 uval = arg->token->u.channels;
5385 if (operand->size == 2)
5386 {
5387 /* Check that a single bit is set and convert it into a 2-bit index. */
5388 if ((uval & -uval) != uval)
5389 return FALSE;
5390 uval = 4 - ffs (uval);
5391 }
5392
5393 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5394 return FALSE;
5395
5396 ++arg->token;
5397 if (!match_p)
5398 insn_insert_operand (arg->insn, operand, uval);
5399 return TRUE;
5400}
5401
a1d78564
RS
5402/* S is the text seen for ARG. Match it against OPERAND. Return the end
5403 of the argument text if the match is successful, otherwise return null. */
5404
a92713e6 5405static bfd_boolean
a1d78564 5406match_operand (struct mips_arg_info *arg,
a92713e6 5407 const struct mips_operand *operand)
a1d78564
RS
5408{
5409 switch (operand->type)
5410 {
5411 case OP_INT:
a92713e6 5412 return match_int_operand (arg, operand);
a1d78564
RS
5413
5414 case OP_MAPPED_INT:
a92713e6 5415 return match_mapped_int_operand (arg, operand);
a1d78564
RS
5416
5417 case OP_MSB:
a92713e6 5418 return match_msb_operand (arg, operand);
a1d78564
RS
5419
5420 case OP_REG:
0f35dbc4 5421 case OP_OPTIONAL_REG:
a92713e6 5422 return match_reg_operand (arg, operand);
a1d78564
RS
5423
5424 case OP_REG_PAIR:
a92713e6 5425 return match_reg_pair_operand (arg, operand);
a1d78564
RS
5426
5427 case OP_PCREL:
a92713e6 5428 return match_pcrel_operand (arg);
a1d78564
RS
5429
5430 case OP_PERF_REG:
a92713e6 5431 return match_perf_reg_operand (arg, operand);
a1d78564
RS
5432
5433 case OP_ADDIUSP_INT:
a92713e6 5434 return match_addiusp_operand (arg, operand);
a1d78564
RS
5435
5436 case OP_CLO_CLZ_DEST:
a92713e6 5437 return match_clo_clz_dest_operand (arg, operand);
a1d78564
RS
5438
5439 case OP_LWM_SWM_LIST:
a92713e6 5440 return match_lwm_swm_list_operand (arg, operand);
a1d78564
RS
5441
5442 case OP_ENTRY_EXIT_LIST:
a92713e6 5443 return match_entry_exit_operand (arg, operand);
364215c8 5444
a1d78564 5445 case OP_SAVE_RESTORE_LIST:
a92713e6 5446 return match_save_restore_list_operand (arg);
a1d78564
RS
5447
5448 case OP_MDMX_IMM_REG:
a92713e6 5449 return match_mdmx_imm_reg_operand (arg, operand);
a1d78564
RS
5450
5451 case OP_REPEAT_DEST_REG:
a92713e6 5452 return match_tied_reg_operand (arg, arg->dest_regno);
a1d78564
RS
5453
5454 case OP_REPEAT_PREV_REG:
a92713e6 5455 return match_tied_reg_operand (arg, arg->last_regno);
a1d78564
RS
5456
5457 case OP_PC:
a92713e6 5458 return match_pc_operand (arg);
14daeee3
RS
5459
5460 case OP_VU0_SUFFIX:
5461 return match_vu0_suffix_operand (arg, operand, FALSE);
5462
5463 case OP_VU0_MATCH_SUFFIX:
5464 return match_vu0_suffix_operand (arg, operand, TRUE);
a1d78564
RS
5465 }
5466 abort ();
5467}
5468
5469/* ARG is the state after successfully matching an instruction.
5470 Issue any queued-up warnings. */
5471
5472static void
5473check_completed_insn (struct mips_arg_info *arg)
5474{
5475 if (arg->seen_at)
5476 {
5477 if (AT == ATREG)
5478 as_warn (_("Used $at without \".set noat\""));
5479 else
5480 as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
5481 }
5482}
a1d78564 5483
85fcb30f
RS
5484/* Return true if modifying general-purpose register REG needs a delay. */
5485
5486static bfd_boolean
5487reg_needs_delay (unsigned int reg)
5488{
5489 unsigned long prev_pinfo;
5490
5491 prev_pinfo = history[0].insn_mo->pinfo;
5492 if (!mips_opts.noreorder
5493 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5494 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5495 && (gpr_write_mask (&history[0]) & (1 << reg)))
5496 return TRUE;
5497
5498 return FALSE;
5499}
5500
71400594
RS
5501/* Classify an instruction according to the FIX_VR4120_* enumeration.
5502 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5503 by VR4120 errata. */
4d7206a2 5504
71400594
RS
5505static unsigned int
5506classify_vr4120_insn (const char *name)
252b5132 5507{
71400594
RS
5508 if (strncmp (name, "macc", 4) == 0)
5509 return FIX_VR4120_MACC;
5510 if (strncmp (name, "dmacc", 5) == 0)
5511 return FIX_VR4120_DMACC;
5512 if (strncmp (name, "mult", 4) == 0)
5513 return FIX_VR4120_MULT;
5514 if (strncmp (name, "dmult", 5) == 0)
5515 return FIX_VR4120_DMULT;
5516 if (strstr (name, "div"))
5517 return FIX_VR4120_DIV;
5518 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5519 return FIX_VR4120_MTHILO;
5520 return NUM_FIX_VR4120_CLASSES;
5521}
252b5132 5522
ff239038
CM
5523#define INSN_ERET 0x42000018
5524#define INSN_DERET 0x4200001f
5525
71400594
RS
5526/* Return the number of instructions that must separate INSN1 and INSN2,
5527 where INSN1 is the earlier instruction. Return the worst-case value
5528 for any INSN2 if INSN2 is null. */
252b5132 5529
71400594
RS
5530static unsigned int
5531insns_between (const struct mips_cl_insn *insn1,
5532 const struct mips_cl_insn *insn2)
5533{
5534 unsigned long pinfo1, pinfo2;
4c260379 5535 unsigned int mask;
71400594 5536
85fcb30f
RS
5537 /* If INFO2 is null, pessimistically assume that all flags are set for
5538 the second instruction. */
71400594
RS
5539 pinfo1 = insn1->insn_mo->pinfo;
5540 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
252b5132 5541
71400594
RS
5542 /* For most targets, write-after-read dependencies on the HI and LO
5543 registers must be separated by at least two instructions. */
5544 if (!hilo_interlocks)
252b5132 5545 {
71400594
RS
5546 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5547 return 2;
5548 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5549 return 2;
5550 }
5551
5552 /* If we're working around r7000 errata, there must be two instructions
5553 between an mfhi or mflo and any instruction that uses the result. */
5554 if (mips_7000_hilo_fix
df58fc94 5555 && !mips_opts.micromips
71400594 5556 && MF_HILO_INSN (pinfo1)
85fcb30f 5557 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
71400594
RS
5558 return 2;
5559
ff239038
CM
5560 /* If we're working around 24K errata, one instruction is required
5561 if an ERET or DERET is followed by a branch instruction. */
df58fc94 5562 if (mips_fix_24k && !mips_opts.micromips)
ff239038
CM
5563 {
5564 if (insn1->insn_opcode == INSN_ERET
5565 || insn1->insn_opcode == INSN_DERET)
5566 {
5567 if (insn2 == NULL
5568 || insn2->insn_opcode == INSN_ERET
5569 || insn2->insn_opcode == INSN_DERET
11625dd8 5570 || delayed_branch_p (insn2))
ff239038
CM
5571 return 1;
5572 }
5573 }
5574
71400594
RS
5575 /* If working around VR4120 errata, check for combinations that need
5576 a single intervening instruction. */
df58fc94 5577 if (mips_fix_vr4120 && !mips_opts.micromips)
71400594
RS
5578 {
5579 unsigned int class1, class2;
252b5132 5580
71400594
RS
5581 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5582 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
252b5132 5583 {
71400594
RS
5584 if (insn2 == NULL)
5585 return 1;
5586 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5587 if (vr4120_conflicts[class1] & (1 << class2))
5588 return 1;
252b5132 5589 }
71400594
RS
5590 }
5591
df58fc94 5592 if (!HAVE_CODE_COMPRESSION)
71400594
RS
5593 {
5594 /* Check for GPR or coprocessor load delays. All such delays
5595 are on the RT register. */
5596 /* Itbl support may require additional care here. */
5597 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5598 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
252b5132 5599 {
85fcb30f 5600 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
71400594
RS
5601 return 1;
5602 }
5603
5604 /* Check for generic coprocessor hazards.
5605
5606 This case is not handled very well. There is no special
5607 knowledge of CP0 handling, and the coprocessors other than
5608 the floating point unit are not distinguished at all. */
5609 /* Itbl support may require additional care here. FIXME!
5610 Need to modify this to include knowledge about
5611 user specified delays! */
5612 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5613 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5614 {
5615 /* Handle cases where INSN1 writes to a known general coprocessor
5616 register. There must be a one instruction delay before INSN2
5617 if INSN2 reads that register, otherwise no delay is needed. */
4c260379
RS
5618 mask = fpr_write_mask (insn1);
5619 if (mask != 0)
252b5132 5620 {
4c260379 5621 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
71400594 5622 return 1;
252b5132
RH
5623 }
5624 else
5625 {
71400594
RS
5626 /* Read-after-write dependencies on the control registers
5627 require a two-instruction gap. */
5628 if ((pinfo1 & INSN_WRITE_COND_CODE)
5629 && (pinfo2 & INSN_READ_COND_CODE))
5630 return 2;
5631
5632 /* We don't know exactly what INSN1 does. If INSN2 is
5633 also a coprocessor instruction, assume there must be
5634 a one instruction gap. */
5635 if (pinfo2 & INSN_COP)
5636 return 1;
252b5132
RH
5637 }
5638 }
6b76fefe 5639
71400594
RS
5640 /* Check for read-after-write dependencies on the coprocessor
5641 control registers in cases where INSN1 does not need a general
5642 coprocessor delay. This means that INSN1 is a floating point
5643 comparison instruction. */
5644 /* Itbl support may require additional care here. */
5645 else if (!cop_interlocks
5646 && (pinfo1 & INSN_WRITE_COND_CODE)
5647 && (pinfo2 & INSN_READ_COND_CODE))
5648 return 1;
5649 }
6b76fefe 5650
71400594
RS
5651 return 0;
5652}
6b76fefe 5653
7d8e00cf
RS
5654/* Return the number of nops that would be needed to work around the
5655 VR4130 mflo/mfhi errata if instruction INSN immediately followed
932d1a1b
RS
5656 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5657 that are contained within the first IGNORE instructions of HIST. */
7d8e00cf
RS
5658
5659static int
932d1a1b 5660nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
7d8e00cf
RS
5661 const struct mips_cl_insn *insn)
5662{
4c260379
RS
5663 int i, j;
5664 unsigned int mask;
7d8e00cf
RS
5665
5666 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5667 are not affected by the errata. */
5668 if (insn != 0
5669 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5670 || strcmp (insn->insn_mo->name, "mtlo") == 0
5671 || strcmp (insn->insn_mo->name, "mthi") == 0))
5672 return 0;
5673
5674 /* Search for the first MFLO or MFHI. */
5675 for (i = 0; i < MAX_VR4130_NOPS; i++)
91d6fa6a 5676 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
7d8e00cf
RS
5677 {
5678 /* Extract the destination register. */
4c260379 5679 mask = gpr_write_mask (&hist[i]);
7d8e00cf
RS
5680
5681 /* No nops are needed if INSN reads that register. */
4c260379 5682 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
7d8e00cf
RS
5683 return 0;
5684
5685 /* ...or if any of the intervening instructions do. */
5686 for (j = 0; j < i; j++)
4c260379 5687 if (gpr_read_mask (&hist[j]) & mask)
7d8e00cf
RS
5688 return 0;
5689
932d1a1b
RS
5690 if (i >= ignore)
5691 return MAX_VR4130_NOPS - i;
7d8e00cf
RS
5692 }
5693 return 0;
5694}
5695
15be625d
CM
5696#define BASE_REG_EQ(INSN1, INSN2) \
5697 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5698 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5699
5700/* Return the minimum alignment for this store instruction. */
5701
5702static int
5703fix_24k_align_to (const struct mips_opcode *mo)
5704{
5705 if (strcmp (mo->name, "sh") == 0)
5706 return 2;
5707
5708 if (strcmp (mo->name, "swc1") == 0
5709 || strcmp (mo->name, "swc2") == 0
5710 || strcmp (mo->name, "sw") == 0
5711 || strcmp (mo->name, "sc") == 0
5712 || strcmp (mo->name, "s.s") == 0)
5713 return 4;
5714
5715 if (strcmp (mo->name, "sdc1") == 0
5716 || strcmp (mo->name, "sdc2") == 0
5717 || strcmp (mo->name, "s.d") == 0)
5718 return 8;
5719
5720 /* sb, swl, swr */
5721 return 1;
5722}
5723
5724struct fix_24k_store_info
5725 {
5726 /* Immediate offset, if any, for this store instruction. */
5727 short off;
5728 /* Alignment required by this store instruction. */
5729 int align_to;
5730 /* True for register offsets. */
5731 int register_offset;
5732 };
5733
5734/* Comparison function used by qsort. */
5735
5736static int
5737fix_24k_sort (const void *a, const void *b)
5738{
5739 const struct fix_24k_store_info *pos1 = a;
5740 const struct fix_24k_store_info *pos2 = b;
5741
5742 return (pos1->off - pos2->off);
5743}
5744
5745/* INSN is a store instruction. Try to record the store information
5746 in STINFO. Return false if the information isn't known. */
5747
5748static bfd_boolean
5749fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
ab9794cf 5750 const struct mips_cl_insn *insn)
15be625d
CM
5751{
5752 /* The instruction must have a known offset. */
5753 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5754 return FALSE;
5755
5756 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5757 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5758 return TRUE;
5759}
5760
932d1a1b
RS
5761/* Return the number of nops that would be needed to work around the 24k
5762 "lost data on stores during refill" errata if instruction INSN
5763 immediately followed the 2 instructions described by HIST.
5764 Ignore hazards that are contained within the first IGNORE
5765 instructions of HIST.
5766
5767 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5768 for the data cache refills and store data. The following describes
5769 the scenario where the store data could be lost.
5770
5771 * A data cache miss, due to either a load or a store, causing fill
5772 data to be supplied by the memory subsystem
5773 * The first three doublewords of fill data are returned and written
5774 into the cache
5775 * A sequence of four stores occurs in consecutive cycles around the
5776 final doubleword of the fill:
5777 * Store A
5778 * Store B
5779 * Store C
5780 * Zero, One or more instructions
5781 * Store D
5782
5783 The four stores A-D must be to different doublewords of the line that
5784 is being filled. The fourth instruction in the sequence above permits
5785 the fill of the final doubleword to be transferred from the FSB into
5786 the cache. In the sequence above, the stores may be either integer
5787 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5788 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5789 different doublewords on the line. If the floating point unit is
5790 running in 1:2 mode, it is not possible to create the sequence above
5791 using only floating point store instructions.
15be625d
CM
5792
5793 In this case, the cache line being filled is incorrectly marked
5794 invalid, thereby losing the data from any store to the line that
5795 occurs between the original miss and the completion of the five
5796 cycle sequence shown above.
5797
932d1a1b 5798 The workarounds are:
15be625d 5799
932d1a1b
RS
5800 * Run the data cache in write-through mode.
5801 * Insert a non-store instruction between
5802 Store A and Store B or Store B and Store C. */
15be625d
CM
5803
5804static int
932d1a1b 5805nops_for_24k (int ignore, const struct mips_cl_insn *hist,
15be625d
CM
5806 const struct mips_cl_insn *insn)
5807{
5808 struct fix_24k_store_info pos[3];
5809 int align, i, base_offset;
5810
932d1a1b
RS
5811 if (ignore >= 2)
5812 return 0;
5813
ab9794cf
RS
5814 /* If the previous instruction wasn't a store, there's nothing to
5815 worry about. */
15be625d
CM
5816 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5817 return 0;
5818
ab9794cf
RS
5819 /* If the instructions after the previous one are unknown, we have
5820 to assume the worst. */
5821 if (!insn)
15be625d
CM
5822 return 1;
5823
ab9794cf
RS
5824 /* Check whether we are dealing with three consecutive stores. */
5825 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5826 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
15be625d
CM
5827 return 0;
5828
5829 /* If we don't know the relationship between the store addresses,
5830 assume the worst. */
ab9794cf 5831 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
15be625d
CM
5832 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5833 return 1;
5834
5835 if (!fix_24k_record_store_info (&pos[0], insn)
5836 || !fix_24k_record_store_info (&pos[1], &hist[0])
5837 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5838 return 1;
5839
5840 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5841
5842 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5843 X bytes and such that the base register + X is known to be aligned
5844 to align bytes. */
5845
5846 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5847 align = 8;
5848 else
5849 {
5850 align = pos[0].align_to;
5851 base_offset = pos[0].off;
5852 for (i = 1; i < 3; i++)
5853 if (align < pos[i].align_to)
5854 {
5855 align = pos[i].align_to;
5856 base_offset = pos[i].off;
5857 }
5858 for (i = 0; i < 3; i++)
5859 pos[i].off -= base_offset;
5860 }
5861
5862 pos[0].off &= ~align + 1;
5863 pos[1].off &= ~align + 1;
5864 pos[2].off &= ~align + 1;
5865
5866 /* If any two stores write to the same chunk, they also write to the
5867 same doubleword. The offsets are still sorted at this point. */
5868 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5869 return 0;
5870
5871 /* A range of at least 9 bytes is needed for the stores to be in
5872 non-overlapping doublewords. */
5873 if (pos[2].off - pos[0].off <= 8)
5874 return 0;
5875
5876 if (pos[2].off - pos[1].off >= 24
5877 || pos[1].off - pos[0].off >= 24
5878 || pos[2].off - pos[0].off >= 32)
5879 return 0;
5880
5881 return 1;
5882}
5883
71400594 5884/* Return the number of nops that would be needed if instruction INSN
91d6fa6a 5885 immediately followed the MAX_NOPS instructions given by HIST,
932d1a1b
RS
5886 where HIST[0] is the most recent instruction. Ignore hazards
5887 between INSN and the first IGNORE instructions in HIST.
5888
5889 If INSN is null, return the worse-case number of nops for any
5890 instruction. */
bdaaa2e1 5891
71400594 5892static int
932d1a1b 5893nops_for_insn (int ignore, const struct mips_cl_insn *hist,
71400594
RS
5894 const struct mips_cl_insn *insn)
5895{
5896 int i, nops, tmp_nops;
bdaaa2e1 5897
71400594 5898 nops = 0;
932d1a1b 5899 for (i = ignore; i < MAX_DELAY_NOPS; i++)
65b02341 5900 {
91d6fa6a 5901 tmp_nops = insns_between (hist + i, insn) - i;
65b02341
RS
5902 if (tmp_nops > nops)
5903 nops = tmp_nops;
5904 }
7d8e00cf 5905
df58fc94 5906 if (mips_fix_vr4130 && !mips_opts.micromips)
7d8e00cf 5907 {
932d1a1b 5908 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
7d8e00cf
RS
5909 if (tmp_nops > nops)
5910 nops = tmp_nops;
5911 }
5912
df58fc94 5913 if (mips_fix_24k && !mips_opts.micromips)
15be625d 5914 {
932d1a1b 5915 tmp_nops = nops_for_24k (ignore, hist, insn);
15be625d
CM
5916 if (tmp_nops > nops)
5917 nops = tmp_nops;
5918 }
5919
71400594
RS
5920 return nops;
5921}
252b5132 5922
71400594 5923/* The variable arguments provide NUM_INSNS extra instructions that
91d6fa6a 5924 might be added to HIST. Return the largest number of nops that
932d1a1b
RS
5925 would be needed after the extended sequence, ignoring hazards
5926 in the first IGNORE instructions. */
252b5132 5927
71400594 5928static int
932d1a1b
RS
5929nops_for_sequence (int num_insns, int ignore,
5930 const struct mips_cl_insn *hist, ...)
71400594
RS
5931{
5932 va_list args;
5933 struct mips_cl_insn buffer[MAX_NOPS];
5934 struct mips_cl_insn *cursor;
5935 int nops;
5936
91d6fa6a 5937 va_start (args, hist);
71400594 5938 cursor = buffer + num_insns;
91d6fa6a 5939 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
71400594
RS
5940 while (cursor > buffer)
5941 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5942
932d1a1b 5943 nops = nops_for_insn (ignore, buffer, NULL);
71400594
RS
5944 va_end (args);
5945 return nops;
5946}
252b5132 5947
71400594
RS
5948/* Like nops_for_insn, but if INSN is a branch, take into account the
5949 worst-case delay for the branch target. */
252b5132 5950
71400594 5951static int
932d1a1b 5952nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
71400594
RS
5953 const struct mips_cl_insn *insn)
5954{
5955 int nops, tmp_nops;
60b63b72 5956
932d1a1b 5957 nops = nops_for_insn (ignore, hist, insn);
11625dd8 5958 if (delayed_branch_p (insn))
71400594 5959 {
932d1a1b 5960 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
14fe068b 5961 hist, insn, get_delay_slot_nop (insn));
71400594
RS
5962 if (tmp_nops > nops)
5963 nops = tmp_nops;
5964 }
11625dd8 5965 else if (compact_branch_p (insn))
71400594 5966 {
932d1a1b 5967 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
71400594
RS
5968 if (tmp_nops > nops)
5969 nops = tmp_nops;
5970 }
5971 return nops;
5972}
5973
c67a084a
NC
5974/* Fix NOP issue: Replace nops by "or at,at,zero". */
5975
5976static void
5977fix_loongson2f_nop (struct mips_cl_insn * ip)
5978{
df58fc94 5979 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
5980 if (strcmp (ip->insn_mo->name, "nop") == 0)
5981 ip->insn_opcode = LOONGSON2F_NOP_INSN;
5982}
5983
5984/* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5985 jr target pc &= 'hffff_ffff_cfff_ffff. */
5986
5987static void
5988fix_loongson2f_jump (struct mips_cl_insn * ip)
5989{
df58fc94 5990 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
5991 if (strcmp (ip->insn_mo->name, "j") == 0
5992 || strcmp (ip->insn_mo->name, "jr") == 0
5993 || strcmp (ip->insn_mo->name, "jalr") == 0)
5994 {
5995 int sreg;
5996 expressionS ep;
5997
5998 if (! mips_opts.at)
5999 return;
6000
df58fc94 6001 sreg = EXTRACT_OPERAND (0, RS, *ip);
c67a084a
NC
6002 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6003 return;
6004
6005 ep.X_op = O_constant;
6006 ep.X_add_number = 0xcfff0000;
6007 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6008 ep.X_add_number = 0xffff;
6009 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6010 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6011 }
6012}
6013
6014static void
6015fix_loongson2f (struct mips_cl_insn * ip)
6016{
6017 if (mips_fix_loongson2f_nop)
6018 fix_loongson2f_nop (ip);
6019
6020 if (mips_fix_loongson2f_jump)
6021 fix_loongson2f_jump (ip);
6022}
6023
a4e06468
RS
6024/* IP is a branch that has a delay slot, and we need to fill it
6025 automatically. Return true if we can do that by swapping IP
e407c74b
NC
6026 with the previous instruction.
6027 ADDRESS_EXPR is an operand of the instruction to be used with
6028 RELOC_TYPE. */
a4e06468
RS
6029
6030static bfd_boolean
e407c74b 6031can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
26545944 6032 bfd_reloc_code_real_type *reloc_type)
a4e06468 6033{
2b0c8b40 6034 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
a4e06468
RS
6035 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6036
6037 /* -O2 and above is required for this optimization. */
6038 if (mips_optimize < 2)
6039 return FALSE;
6040
6041 /* If we have seen .set volatile or .set nomove, don't optimize. */
6042 if (mips_opts.nomove)
6043 return FALSE;
6044
6045 /* We can't swap if the previous instruction's position is fixed. */
6046 if (history[0].fixed_p)
6047 return FALSE;
6048
6049 /* If the previous previous insn was in a .set noreorder, we can't
6050 swap. Actually, the MIPS assembler will swap in this situation.
6051 However, gcc configured -with-gnu-as will generate code like
6052
6053 .set noreorder
6054 lw $4,XXX
6055 .set reorder
6056 INSN
6057 bne $4,$0,foo
6058
6059 in which we can not swap the bne and INSN. If gcc is not configured
6060 -with-gnu-as, it does not output the .set pseudo-ops. */
6061 if (history[1].noreorder_p)
6062 return FALSE;
6063
87333bb7
MR
6064 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6065 This means that the previous instruction was a 4-byte one anyhow. */
a4e06468
RS
6066 if (mips_opts.mips16 && history[0].fixp[0])
6067 return FALSE;
6068
6069 /* If the branch is itself the target of a branch, we can not swap.
6070 We cheat on this; all we check for is whether there is a label on
6071 this instruction. If there are any branches to anything other than
6072 a label, users must use .set noreorder. */
6073 if (seg_info (now_seg)->label_list)
6074 return FALSE;
6075
6076 /* If the previous instruction is in a variant frag other than this
2309ddf2 6077 branch's one, we cannot do the swap. This does not apply to
9301f9c3
MR
6078 MIPS16 code, which uses variant frags for different purposes. */
6079 if (!mips_opts.mips16
a4e06468
RS
6080 && history[0].frag
6081 && history[0].frag->fr_type == rs_machine_dependent)
6082 return FALSE;
6083
bcd530a7
RS
6084 /* We do not swap with instructions that cannot architecturally
6085 be placed in a branch delay slot, such as SYNC or ERET. We
6086 also refrain from swapping with a trap instruction, since it
6087 complicates trap handlers to have the trap instruction be in
6088 a delay slot. */
a4e06468 6089 prev_pinfo = history[0].insn_mo->pinfo;
bcd530a7 6090 if (prev_pinfo & INSN_NO_DELAY_SLOT)
a4e06468
RS
6091 return FALSE;
6092
6093 /* Check for conflicts between the branch and the instructions
6094 before the candidate delay slot. */
6095 if (nops_for_insn (0, history + 1, ip) > 0)
6096 return FALSE;
6097
6098 /* Check for conflicts between the swapped sequence and the
6099 target of the branch. */
6100 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6101 return FALSE;
6102
6103 /* If the branch reads a register that the previous
6104 instruction sets, we can not swap. */
6105 gpr_read = gpr_read_mask (ip);
6106 prev_gpr_write = gpr_write_mask (&history[0]);
6107 if (gpr_read & prev_gpr_write)
6108 return FALSE;
6109
6110 /* If the branch writes a register that the previous
6111 instruction sets, we can not swap. */
6112 gpr_write = gpr_write_mask (ip);
6113 if (gpr_write & prev_gpr_write)
6114 return FALSE;
6115
6116 /* If the branch writes a register that the previous
6117 instruction reads, we can not swap. */
6118 prev_gpr_read = gpr_read_mask (&history[0]);
6119 if (gpr_write & prev_gpr_read)
6120 return FALSE;
6121
6122 /* If one instruction sets a condition code and the
6123 other one uses a condition code, we can not swap. */
6124 pinfo = ip->insn_mo->pinfo;
6125 if ((pinfo & INSN_READ_COND_CODE)
6126 && (prev_pinfo & INSN_WRITE_COND_CODE))
6127 return FALSE;
6128 if ((pinfo & INSN_WRITE_COND_CODE)
6129 && (prev_pinfo & INSN_READ_COND_CODE))
6130 return FALSE;
6131
6132 /* If the previous instruction uses the PC, we can not swap. */
2b0c8b40 6133 prev_pinfo2 = history[0].insn_mo->pinfo2;
26545944 6134 if (prev_pinfo2 & INSN2_READ_PC)
2b0c8b40 6135 return FALSE;
a4e06468 6136
df58fc94
RS
6137 /* If the previous instruction has an incorrect size for a fixed
6138 branch delay slot in microMIPS mode, we cannot swap. */
2309ddf2
MR
6139 pinfo2 = ip->insn_mo->pinfo2;
6140 if (mips_opts.micromips
6141 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6142 && insn_length (history) != 2)
6143 return FALSE;
6144 if (mips_opts.micromips
6145 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6146 && insn_length (history) != 4)
6147 return FALSE;
6148
e407c74b
NC
6149 /* On R5900 short loops need to be fixed by inserting a nop in
6150 the branch delay slots.
6151 A short loop can be terminated too early. */
6152 if (mips_opts.arch == CPU_R5900
6153 /* Check if instruction has a parameter, ignore "j $31". */
6154 && (address_expr != NULL)
6155 /* Parameter must be 16 bit. */
6156 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6157 /* Branch to same segment. */
6158 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
6159 /* Branch to same code fragment. */
6160 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
6161 /* Can only calculate branch offset if value is known. */
6162 && symbol_constant_p(address_expr->X_add_symbol)
6163 /* Check if branch is really conditional. */
6164 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6165 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6166 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6167 {
6168 int distance;
6169 /* Check if loop is shorter than 6 instructions including
6170 branch and delay slot. */
6171 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
6172 if (distance <= 20)
6173 {
6174 int i;
6175 int rv;
6176
6177 rv = FALSE;
6178 /* When the loop includes branches or jumps,
6179 it is not a short loop. */
6180 for (i = 0; i < (distance / 4); i++)
6181 {
6182 if ((history[i].cleared_p)
6183 || delayed_branch_p(&history[i]))
6184 {
6185 rv = TRUE;
6186 break;
6187 }
6188 }
6189 if (rv == FALSE)
6190 {
6191 /* Insert nop after branch to fix short loop. */
6192 return FALSE;
6193 }
6194 }
6195 }
6196
a4e06468
RS
6197 return TRUE;
6198}
6199
e407c74b
NC
6200/* Decide how we should add IP to the instruction stream.
6201 ADDRESS_EXPR is an operand of the instruction to be used with
6202 RELOC_TYPE. */
a4e06468
RS
6203
6204static enum append_method
e407c74b 6205get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
26545944 6206 bfd_reloc_code_real_type *reloc_type)
a4e06468 6207{
a4e06468
RS
6208 /* The relaxed version of a macro sequence must be inherently
6209 hazard-free. */
6210 if (mips_relax.sequence == 2)
6211 return APPEND_ADD;
6212
6213 /* We must not dabble with instructions in a ".set norerorder" block. */
6214 if (mips_opts.noreorder)
6215 return APPEND_ADD;
6216
6217 /* Otherwise, it's our responsibility to fill branch delay slots. */
11625dd8 6218 if (delayed_branch_p (ip))
a4e06468 6219 {
e407c74b
NC
6220 if (!branch_likely_p (ip)
6221 && can_swap_branch_p (ip, address_expr, reloc_type))
a4e06468
RS
6222 return APPEND_SWAP;
6223
6224 if (mips_opts.mips16
6225 && ISA_SUPPORTS_MIPS16E
fc76e730 6226 && gpr_read_mask (ip) != 0)
a4e06468
RS
6227 return APPEND_ADD_COMPACT;
6228
6229 return APPEND_ADD_WITH_NOP;
6230 }
6231
a4e06468
RS
6232 return APPEND_ADD;
6233}
6234
ceb94aa5
RS
6235/* IP is a MIPS16 instruction whose opcode we have just changed.
6236 Point IP->insn_mo to the new opcode's definition. */
6237
6238static void
6239find_altered_mips16_opcode (struct mips_cl_insn *ip)
6240{
6241 const struct mips_opcode *mo, *end;
6242
6243 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6244 for (mo = ip->insn_mo; mo < end; mo++)
6245 if ((ip->insn_opcode & mo->mask) == mo->match)
6246 {
6247 ip->insn_mo = mo;
6248 return;
6249 }
6250 abort ();
6251}
6252
df58fc94
RS
6253/* For microMIPS macros, we need to generate a local number label
6254 as the target of branches. */
6255#define MICROMIPS_LABEL_CHAR '\037'
6256static unsigned long micromips_target_label;
6257static char micromips_target_name[32];
6258
6259static char *
6260micromips_label_name (void)
6261{
6262 char *p = micromips_target_name;
6263 char symbol_name_temporary[24];
6264 unsigned long l;
6265 int i;
6266
6267 if (*p)
6268 return p;
6269
6270 i = 0;
6271 l = micromips_target_label;
6272#ifdef LOCAL_LABEL_PREFIX
6273 *p++ = LOCAL_LABEL_PREFIX;
6274#endif
6275 *p++ = 'L';
6276 *p++ = MICROMIPS_LABEL_CHAR;
6277 do
6278 {
6279 symbol_name_temporary[i++] = l % 10 + '0';
6280 l /= 10;
6281 }
6282 while (l != 0);
6283 while (i > 0)
6284 *p++ = symbol_name_temporary[--i];
6285 *p = '\0';
6286
6287 return micromips_target_name;
6288}
6289
6290static void
6291micromips_label_expr (expressionS *label_expr)
6292{
6293 label_expr->X_op = O_symbol;
6294 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6295 label_expr->X_add_number = 0;
6296}
6297
6298static void
6299micromips_label_inc (void)
6300{
6301 micromips_target_label++;
6302 *micromips_target_name = '\0';
6303}
6304
6305static void
6306micromips_add_label (void)
6307{
6308 symbolS *s;
6309
6310 s = colon (micromips_label_name ());
6311 micromips_label_inc ();
f3ded42a 6312 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
df58fc94
RS
6313}
6314
6315/* If assembling microMIPS code, then return the microMIPS reloc
6316 corresponding to the requested one if any. Otherwise return
6317 the reloc unchanged. */
6318
6319static bfd_reloc_code_real_type
6320micromips_map_reloc (bfd_reloc_code_real_type reloc)
6321{
6322 static const bfd_reloc_code_real_type relocs[][2] =
6323 {
6324 /* Keep sorted incrementally by the left-hand key. */
6325 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6326 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6327 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6328 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6329 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6330 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6331 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6332 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6333 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6334 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6335 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6336 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6337 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6338 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6339 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6340 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6341 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6342 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6343 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6344 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6345 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6346 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6347 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6348 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6349 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6350 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6351 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6352 };
6353 bfd_reloc_code_real_type r;
6354 size_t i;
6355
6356 if (!mips_opts.micromips)
6357 return reloc;
6358 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6359 {
6360 r = relocs[i][0];
6361 if (r > reloc)
6362 return reloc;
6363 if (r == reloc)
6364 return relocs[i][1];
6365 }
6366 return reloc;
6367}
6368
b886a2ab
RS
6369/* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6370 Return true on success, storing the resolved value in RESULT. */
6371
6372static bfd_boolean
6373calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6374 offsetT *result)
6375{
6376 switch (reloc)
6377 {
6378 case BFD_RELOC_MIPS_HIGHEST:
6379 case BFD_RELOC_MICROMIPS_HIGHEST:
6380 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6381 return TRUE;
6382
6383 case BFD_RELOC_MIPS_HIGHER:
6384 case BFD_RELOC_MICROMIPS_HIGHER:
6385 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6386 return TRUE;
6387
6388 case BFD_RELOC_HI16_S:
6389 case BFD_RELOC_MICROMIPS_HI16_S:
6390 case BFD_RELOC_MIPS16_HI16_S:
6391 *result = ((operand + 0x8000) >> 16) & 0xffff;
6392 return TRUE;
6393
6394 case BFD_RELOC_HI16:
6395 case BFD_RELOC_MICROMIPS_HI16:
6396 case BFD_RELOC_MIPS16_HI16:
6397 *result = (operand >> 16) & 0xffff;
6398 return TRUE;
6399
6400 case BFD_RELOC_LO16:
6401 case BFD_RELOC_MICROMIPS_LO16:
6402 case BFD_RELOC_MIPS16_LO16:
6403 *result = operand & 0xffff;
6404 return TRUE;
6405
6406 case BFD_RELOC_UNUSED:
6407 *result = operand;
6408 return TRUE;
6409
6410 default:
6411 return FALSE;
6412 }
6413}
6414
71400594
RS
6415/* Output an instruction. IP is the instruction information.
6416 ADDRESS_EXPR is an operand of the instruction to be used with
df58fc94
RS
6417 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6418 a macro expansion. */
71400594
RS
6419
6420static void
6421append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
df58fc94 6422 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
71400594 6423{
14fe068b 6424 unsigned long prev_pinfo2, pinfo;
71400594 6425 bfd_boolean relaxed_branch = FALSE;
a4e06468 6426 enum append_method method;
2309ddf2 6427 bfd_boolean relax32;
2b0c8b40 6428 int branch_disp;
71400594 6429
2309ddf2 6430 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
c67a084a
NC
6431 fix_loongson2f (ip);
6432
738f4d98 6433 file_ase_mips16 |= mips_opts.mips16;
df58fc94 6434 file_ase_micromips |= mips_opts.micromips;
738f4d98 6435
df58fc94 6436 prev_pinfo2 = history[0].insn_mo->pinfo2;
71400594 6437 pinfo = ip->insn_mo->pinfo;
df58fc94
RS
6438
6439 if (mips_opts.micromips
6440 && !expansionp
6441 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6442 && micromips_insn_length (ip->insn_mo) != 2)
6443 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6444 && micromips_insn_length (ip->insn_mo) != 4)))
6445 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6446 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
71400594 6447
15be625d
CM
6448 if (address_expr == NULL)
6449 ip->complete_p = 1;
b886a2ab
RS
6450 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6451 && reloc_type[1] == BFD_RELOC_UNUSED
6452 && reloc_type[2] == BFD_RELOC_UNUSED
15be625d
CM
6453 && address_expr->X_op == O_constant)
6454 {
15be625d
CM
6455 switch (*reloc_type)
6456 {
15be625d 6457 case BFD_RELOC_MIPS_JMP:
df58fc94
RS
6458 {
6459 int shift;
6460
6461 shift = mips_opts.micromips ? 1 : 2;
6462 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6463 as_bad (_("jump to misaligned address (0x%lx)"),
6464 (unsigned long) address_expr->X_add_number);
6465 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6466 & 0x3ffffff);
335574df 6467 ip->complete_p = 1;
df58fc94 6468 }
15be625d
CM
6469 break;
6470
6471 case BFD_RELOC_MIPS16_JMP:
6472 if ((address_expr->X_add_number & 3) != 0)
6473 as_bad (_("jump to misaligned address (0x%lx)"),
6474 (unsigned long) address_expr->X_add_number);
6475 ip->insn_opcode |=
6476 (((address_expr->X_add_number & 0x7c0000) << 3)
6477 | ((address_expr->X_add_number & 0xf800000) >> 7)
6478 | ((address_expr->X_add_number & 0x3fffc) >> 2));
335574df 6479 ip->complete_p = 1;
15be625d
CM
6480 break;
6481
6482 case BFD_RELOC_16_PCREL_S2:
df58fc94
RS
6483 {
6484 int shift;
6485
6486 shift = mips_opts.micromips ? 1 : 2;
6487 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6488 as_bad (_("branch to misaligned address (0x%lx)"),
6489 (unsigned long) address_expr->X_add_number);
6490 if (!mips_relax_branch)
6491 {
6492 if ((address_expr->X_add_number + (1 << (shift + 15)))
6493 & ~((1 << (shift + 16)) - 1))
6494 as_bad (_("branch address range overflow (0x%lx)"),
6495 (unsigned long) address_expr->X_add_number);
6496 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6497 & 0xffff);
6498 }
df58fc94 6499 }
15be625d
CM
6500 break;
6501
6502 default:
b886a2ab
RS
6503 {
6504 offsetT value;
6505
6506 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6507 &value))
6508 {
6509 ip->insn_opcode |= value & 0xffff;
6510 ip->complete_p = 1;
6511 }
6512 }
6513 break;
6514 }
15be625d
CM
6515 }
6516
71400594
RS
6517 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6518 {
6519 /* There are a lot of optimizations we could do that we don't.
6520 In particular, we do not, in general, reorder instructions.
6521 If you use gcc with optimization, it will reorder
6522 instructions and generally do much more optimization then we
6523 do here; repeating all that work in the assembler would only
6524 benefit hand written assembly code, and does not seem worth
6525 it. */
6526 int nops = (mips_optimize == 0
932d1a1b
RS
6527 ? nops_for_insn (0, history, NULL)
6528 : nops_for_insn_or_target (0, history, ip));
71400594 6529 if (nops > 0)
252b5132
RH
6530 {
6531 fragS *old_frag;
6532 unsigned long old_frag_offset;
6533 int i;
252b5132
RH
6534
6535 old_frag = frag_now;
6536 old_frag_offset = frag_now_fix ();
6537
6538 for (i = 0; i < nops; i++)
14fe068b
RS
6539 add_fixed_insn (NOP_INSN);
6540 insert_into_history (0, nops, NOP_INSN);
252b5132
RH
6541
6542 if (listing)
6543 {
6544 listing_prev_line ();
6545 /* We may be at the start of a variant frag. In case we
6546 are, make sure there is enough space for the frag
6547 after the frags created by listing_prev_line. The
6548 argument to frag_grow here must be at least as large
6549 as the argument to all other calls to frag_grow in
6550 this file. We don't have to worry about being in the
6551 middle of a variant frag, because the variants insert
6552 all needed nop instructions themselves. */
6553 frag_grow (40);
6554 }
6555
462427c4 6556 mips_move_text_labels ();
252b5132
RH
6557
6558#ifndef NO_ECOFF_DEBUGGING
6559 if (ECOFF_DEBUGGING)
6560 ecoff_fix_loc (old_frag, old_frag_offset);
6561#endif
6562 }
71400594
RS
6563 }
6564 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6565 {
932d1a1b
RS
6566 int nops;
6567
6568 /* Work out how many nops in prev_nop_frag are needed by IP,
6569 ignoring hazards generated by the first prev_nop_frag_since
6570 instructions. */
6571 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
9c2799c2 6572 gas_assert (nops <= prev_nop_frag_holds);
252b5132 6573
71400594
RS
6574 /* Enforce NOPS as a minimum. */
6575 if (nops > prev_nop_frag_required)
6576 prev_nop_frag_required = nops;
252b5132 6577
71400594
RS
6578 if (prev_nop_frag_holds == prev_nop_frag_required)
6579 {
6580 /* Settle for the current number of nops. Update the history
6581 accordingly (for the benefit of any future .set reorder code). */
6582 prev_nop_frag = NULL;
6583 insert_into_history (prev_nop_frag_since,
6584 prev_nop_frag_holds, NOP_INSN);
6585 }
6586 else
6587 {
6588 /* Allow this instruction to replace one of the nops that was
6589 tentatively added to prev_nop_frag. */
df58fc94 6590 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
71400594
RS
6591 prev_nop_frag_holds--;
6592 prev_nop_frag_since++;
252b5132
RH
6593 }
6594 }
6595
e407c74b 6596 method = get_append_method (ip, address_expr, reloc_type);
2b0c8b40 6597 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
a4e06468 6598
e410add4
RS
6599 dwarf2_emit_insn (0);
6600 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6601 so "move" the instruction address accordingly.
6602
6603 Also, it doesn't seem appropriate for the assembler to reorder .loc
6604 entries. If this instruction is a branch that we are going to swap
6605 with the previous instruction, the two instructions should be
6606 treated as a unit, and the debug information for both instructions
6607 should refer to the start of the branch sequence. Using the
6608 current position is certainly wrong when swapping a 32-bit branch
6609 and a 16-bit delay slot, since the current position would then be
6610 in the middle of a branch. */
6611 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
58e2ea4d 6612
df58fc94
RS
6613 relax32 = (mips_relax_branch
6614 /* Don't try branch relaxation within .set nomacro, or within
6615 .set noat if we use $at for PIC computations. If it turns
6616 out that the branch was out-of-range, we'll get an error. */
6617 && !mips_opts.warn_about_macros
6618 && (mips_opts.at || mips_pic == NO_PIC)
3bf0dbfb
MR
6619 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6620 as they have no complementing branches. */
6621 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
df58fc94
RS
6622
6623 if (!HAVE_CODE_COMPRESSION
6624 && address_expr
6625 && relax32
0b25d3e6 6626 && *reloc_type == BFD_RELOC_16_PCREL_S2
11625dd8 6627 && delayed_branch_p (ip))
4a6a3df4 6628 {
895921c9 6629 relaxed_branch = TRUE;
1e915849
RS
6630 add_relaxed_insn (ip, (relaxed_branch_length
6631 (NULL, NULL,
11625dd8
RS
6632 uncond_branch_p (ip) ? -1
6633 : branch_likely_p (ip) ? 1
1e915849
RS
6634 : 0)), 4,
6635 RELAX_BRANCH_ENCODE
66b3e8da 6636 (AT,
11625dd8
RS
6637 uncond_branch_p (ip),
6638 branch_likely_p (ip),
1e915849
RS
6639 pinfo & INSN_WRITE_GPR_31,
6640 0),
6641 address_expr->X_add_symbol,
6642 address_expr->X_add_number);
4a6a3df4
AO
6643 *reloc_type = BFD_RELOC_UNUSED;
6644 }
df58fc94
RS
6645 else if (mips_opts.micromips
6646 && address_expr
6647 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6648 || *reloc_type > BFD_RELOC_UNUSED)
40209cad
MR
6649 && (delayed_branch_p (ip) || compact_branch_p (ip))
6650 /* Don't try branch relaxation when users specify
6651 16-bit/32-bit instructions. */
6652 && !forced_insn_length)
df58fc94
RS
6653 {
6654 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6655 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
11625dd8
RS
6656 int uncond = uncond_branch_p (ip) ? -1 : 0;
6657 int compact = compact_branch_p (ip);
df58fc94
RS
6658 int al = pinfo & INSN_WRITE_GPR_31;
6659 int length32;
6660
6661 gas_assert (address_expr != NULL);
6662 gas_assert (!mips_relax.sequence);
6663
2b0c8b40 6664 relaxed_branch = TRUE;
df58fc94
RS
6665 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6666 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
40209cad
MR
6667 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6668 relax32, 0, 0),
df58fc94
RS
6669 address_expr->X_add_symbol,
6670 address_expr->X_add_number);
6671 *reloc_type = BFD_RELOC_UNUSED;
6672 }
6673 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
252b5132
RH
6674 {
6675 /* We need to set up a variant frag. */
df58fc94 6676 gas_assert (address_expr != NULL);
1e915849
RS
6677 add_relaxed_insn (ip, 4, 0,
6678 RELAX_MIPS16_ENCODE
6679 (*reloc_type - BFD_RELOC_UNUSED,
df58fc94 6680 forced_insn_length == 2, forced_insn_length == 4,
11625dd8 6681 delayed_branch_p (&history[0]),
1e915849
RS
6682 history[0].mips16_absolute_jump_p),
6683 make_expr_symbol (address_expr), 0);
252b5132 6684 }
5c04167a 6685 else if (mips_opts.mips16 && insn_length (ip) == 2)
9497f5ac 6686 {
11625dd8 6687 if (!delayed_branch_p (ip))
b8ee1a6e
DU
6688 /* Make sure there is enough room to swap this instruction with
6689 a following jump instruction. */
6690 frag_grow (6);
1e915849 6691 add_fixed_insn (ip);
252b5132
RH
6692 }
6693 else
6694 {
6695 if (mips_opts.mips16
6696 && mips_opts.noreorder
11625dd8 6697 && delayed_branch_p (&history[0]))
252b5132
RH
6698 as_warn (_("extended instruction in delay slot"));
6699
4d7206a2
RS
6700 if (mips_relax.sequence)
6701 {
6702 /* If we've reached the end of this frag, turn it into a variant
6703 frag and record the information for the instructions we've
6704 written so far. */
6705 if (frag_room () < 4)
6706 relax_close_frag ();
df58fc94 6707 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4d7206a2
RS
6708 }
6709
584892a6 6710 if (mips_relax.sequence != 2)
df58fc94
RS
6711 {
6712 if (mips_macro_warning.first_insn_sizes[0] == 0)
6713 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6714 mips_macro_warning.sizes[0] += insn_length (ip);
6715 mips_macro_warning.insns[0]++;
6716 }
584892a6 6717 if (mips_relax.sequence != 1)
df58fc94
RS
6718 {
6719 if (mips_macro_warning.first_insn_sizes[1] == 0)
6720 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6721 mips_macro_warning.sizes[1] += insn_length (ip);
6722 mips_macro_warning.insns[1]++;
6723 }
584892a6 6724
1e915849
RS
6725 if (mips_opts.mips16)
6726 {
6727 ip->fixed_p = 1;
6728 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6729 }
6730 add_fixed_insn (ip);
252b5132
RH
6731 }
6732
9fe77896 6733 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
252b5132 6734 {
df58fc94 6735 bfd_reloc_code_real_type final_type[3];
2309ddf2 6736 reloc_howto_type *howto0;
9fe77896
RS
6737 reloc_howto_type *howto;
6738 int i;
34ce925e 6739
df58fc94
RS
6740 /* Perform any necessary conversion to microMIPS relocations
6741 and find out how many relocations there actually are. */
6742 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6743 final_type[i] = micromips_map_reloc (reloc_type[i]);
6744
9fe77896
RS
6745 /* In a compound relocation, it is the final (outermost)
6746 operator that determines the relocated field. */
2309ddf2 6747 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
e8044f35
RS
6748 if (!howto)
6749 abort ();
2309ddf2
MR
6750
6751 if (i > 1)
6752 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
9fe77896
RS
6753 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6754 bfd_get_reloc_size (howto),
6755 address_expr,
2309ddf2
MR
6756 howto0 && howto0->pc_relative,
6757 final_type[0]);
9fe77896
RS
6758
6759 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2309ddf2 6760 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
9fe77896
RS
6761 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6762
6763 /* These relocations can have an addend that won't fit in
6764 4 octets for 64bit assembly. */
6765 if (HAVE_64BIT_GPRS
6766 && ! howto->partial_inplace
6767 && (reloc_type[0] == BFD_RELOC_16
6768 || reloc_type[0] == BFD_RELOC_32
6769 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6770 || reloc_type[0] == BFD_RELOC_GPREL16
6771 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6772 || reloc_type[0] == BFD_RELOC_GPREL32
6773 || reloc_type[0] == BFD_RELOC_64
6774 || reloc_type[0] == BFD_RELOC_CTOR
6775 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6776 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6777 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6778 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6779 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6780 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6781 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6782 || hi16_reloc_p (reloc_type[0])
6783 || lo16_reloc_p (reloc_type[0])))
6784 ip->fixp[0]->fx_no_overflow = 1;
6785
ddaf2c41
MR
6786 /* These relocations can have an addend that won't fit in 2 octets. */
6787 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6788 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6789 ip->fixp[0]->fx_no_overflow = 1;
6790
9fe77896
RS
6791 if (mips_relax.sequence)
6792 {
6793 if (mips_relax.first_fixup == 0)
6794 mips_relax.first_fixup = ip->fixp[0];
6795 }
6796 else if (reloc_needs_lo_p (*reloc_type))
6797 {
6798 struct mips_hi_fixup *hi_fixup;
6799
6800 /* Reuse the last entry if it already has a matching %lo. */
6801 hi_fixup = mips_hi_fixup_list;
6802 if (hi_fixup == 0
6803 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4d7206a2 6804 {
9fe77896
RS
6805 hi_fixup = ((struct mips_hi_fixup *)
6806 xmalloc (sizeof (struct mips_hi_fixup)));
6807 hi_fixup->next = mips_hi_fixup_list;
6808 mips_hi_fixup_list = hi_fixup;
4d7206a2 6809 }
9fe77896
RS
6810 hi_fixup->fixp = ip->fixp[0];
6811 hi_fixup->seg = now_seg;
6812 }
252b5132 6813
9fe77896
RS
6814 /* Add fixups for the second and third relocations, if given.
6815 Note that the ABI allows the second relocation to be
6816 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6817 moment we only use RSS_UNDEF, but we could add support
6818 for the others if it ever becomes necessary. */
6819 for (i = 1; i < 3; i++)
6820 if (reloc_type[i] != BFD_RELOC_UNUSED)
6821 {
6822 ip->fixp[i] = fix_new (ip->frag, ip->where,
6823 ip->fixp[0]->fx_size, NULL, 0,
df58fc94 6824 FALSE, final_type[i]);
f6688943 6825
9fe77896
RS
6826 /* Use fx_tcbit to mark compound relocs. */
6827 ip->fixp[0]->fx_tcbit = 1;
6828 ip->fixp[i]->fx_tcbit = 1;
6829 }
252b5132 6830 }
1e915849 6831 install_insn (ip);
252b5132
RH
6832
6833 /* Update the register mask information. */
4c260379
RS
6834 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6835 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
252b5132 6836
a4e06468 6837 switch (method)
252b5132 6838 {
a4e06468
RS
6839 case APPEND_ADD:
6840 insert_into_history (0, 1, ip);
6841 break;
6842
6843 case APPEND_ADD_WITH_NOP:
14fe068b
RS
6844 {
6845 struct mips_cl_insn *nop;
6846
6847 insert_into_history (0, 1, ip);
6848 nop = get_delay_slot_nop (ip);
6849 add_fixed_insn (nop);
6850 insert_into_history (0, 1, nop);
6851 if (mips_relax.sequence)
6852 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6853 }
a4e06468
RS
6854 break;
6855
6856 case APPEND_ADD_COMPACT:
6857 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6858 gas_assert (mips_opts.mips16);
6859 ip->insn_opcode |= 0x0080;
6860 find_altered_mips16_opcode (ip);
6861 install_insn (ip);
6862 insert_into_history (0, 1, ip);
6863 break;
6864
6865 case APPEND_SWAP:
6866 {
6867 struct mips_cl_insn delay = history[0];
6868 if (mips_opts.mips16)
6869 {
6870 know (delay.frag == ip->frag);
6871 move_insn (ip, delay.frag, delay.where);
6872 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6873 }
464ab0e5 6874 else if (relaxed_branch || delay.frag != ip->frag)
a4e06468
RS
6875 {
6876 /* Add the delay slot instruction to the end of the
6877 current frag and shrink the fixed part of the
6878 original frag. If the branch occupies the tail of
6879 the latter, move it backwards to cover the gap. */
2b0c8b40 6880 delay.frag->fr_fix -= branch_disp;
a4e06468 6881 if (delay.frag == ip->frag)
2b0c8b40 6882 move_insn (ip, ip->frag, ip->where - branch_disp);
a4e06468
RS
6883 add_fixed_insn (&delay);
6884 }
6885 else
6886 {
2b0c8b40
MR
6887 move_insn (&delay, ip->frag,
6888 ip->where - branch_disp + insn_length (ip));
a4e06468
RS
6889 move_insn (ip, history[0].frag, history[0].where);
6890 }
6891 history[0] = *ip;
6892 delay.fixed_p = 1;
6893 insert_into_history (0, 1, &delay);
6894 }
6895 break;
252b5132
RH
6896 }
6897
13408f1e 6898 /* If we have just completed an unconditional branch, clear the history. */
11625dd8
RS
6899 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6900 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
e407c74b
NC
6901 {
6902 unsigned int i;
6903
79850f26 6904 mips_no_prev_insn ();
13408f1e 6905
e407c74b 6906 for (i = 0; i < ARRAY_SIZE (history); i++)
79850f26 6907 history[i].cleared_p = 1;
e407c74b
NC
6908 }
6909
df58fc94
RS
6910 /* We need to emit a label at the end of branch-likely macros. */
6911 if (emit_branch_likely_macro)
6912 {
6913 emit_branch_likely_macro = FALSE;
6914 micromips_add_label ();
6915 }
6916
252b5132
RH
6917 /* We just output an insn, so the next one doesn't have a label. */
6918 mips_clear_insn_labels ();
252b5132
RH
6919}
6920
e407c74b
NC
6921/* Forget that there was any previous instruction or label.
6922 When BRANCH is true, the branch history is also flushed. */
252b5132
RH
6923
6924static void
7d10b47d 6925mips_no_prev_insn (void)
252b5132 6926{
7d10b47d
RS
6927 prev_nop_frag = NULL;
6928 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
252b5132
RH
6929 mips_clear_insn_labels ();
6930}
6931
7d10b47d
RS
6932/* This function must be called before we emit something other than
6933 instructions. It is like mips_no_prev_insn except that it inserts
6934 any NOPS that might be needed by previous instructions. */
252b5132 6935
7d10b47d
RS
6936void
6937mips_emit_delays (void)
252b5132
RH
6938{
6939 if (! mips_opts.noreorder)
6940 {
932d1a1b 6941 int nops = nops_for_insn (0, history, NULL);
252b5132
RH
6942 if (nops > 0)
6943 {
7d10b47d
RS
6944 while (nops-- > 0)
6945 add_fixed_insn (NOP_INSN);
462427c4 6946 mips_move_text_labels ();
7d10b47d
RS
6947 }
6948 }
6949 mips_no_prev_insn ();
6950}
6951
6952/* Start a (possibly nested) noreorder block. */
6953
6954static void
6955start_noreorder (void)
6956{
6957 if (mips_opts.noreorder == 0)
6958 {
6959 unsigned int i;
6960 int nops;
6961
6962 /* None of the instructions before the .set noreorder can be moved. */
6963 for (i = 0; i < ARRAY_SIZE (history); i++)
6964 history[i].fixed_p = 1;
6965
6966 /* Insert any nops that might be needed between the .set noreorder
6967 block and the previous instructions. We will later remove any
6968 nops that turn out not to be needed. */
932d1a1b 6969 nops = nops_for_insn (0, history, NULL);
7d10b47d
RS
6970 if (nops > 0)
6971 {
6972 if (mips_optimize != 0)
252b5132
RH
6973 {
6974 /* Record the frag which holds the nop instructions, so
6975 that we can remove them if we don't need them. */
df58fc94 6976 frag_grow (nops * NOP_INSN_SIZE);
252b5132
RH
6977 prev_nop_frag = frag_now;
6978 prev_nop_frag_holds = nops;
6979 prev_nop_frag_required = 0;
6980 prev_nop_frag_since = 0;
6981 }
6982
6983 for (; nops > 0; --nops)
1e915849 6984 add_fixed_insn (NOP_INSN);
252b5132 6985
7d10b47d
RS
6986 /* Move on to a new frag, so that it is safe to simply
6987 decrease the size of prev_nop_frag. */
6988 frag_wane (frag_now);
6989 frag_new (0);
462427c4 6990 mips_move_text_labels ();
252b5132 6991 }
df58fc94 6992 mips_mark_labels ();
7d10b47d 6993 mips_clear_insn_labels ();
252b5132 6994 }
7d10b47d
RS
6995 mips_opts.noreorder++;
6996 mips_any_noreorder = 1;
6997}
252b5132 6998
7d10b47d 6999/* End a nested noreorder block. */
252b5132 7000
7d10b47d
RS
7001static void
7002end_noreorder (void)
7003{
7004 mips_opts.noreorder--;
7005 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7006 {
7007 /* Commit to inserting prev_nop_frag_required nops and go back to
7008 handling nop insertion the .set reorder way. */
7009 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
df58fc94 7010 * NOP_INSN_SIZE);
7d10b47d
RS
7011 insert_into_history (prev_nop_frag_since,
7012 prev_nop_frag_required, NOP_INSN);
7013 prev_nop_frag = NULL;
7014 }
252b5132
RH
7015}
7016
97d87491
RS
7017/* Sign-extend 32-bit mode constants that have bit 31 set and all
7018 higher bits unset. */
7019
7020static void
7021normalize_constant_expr (expressionS *ex)
7022{
7023 if (ex->X_op == O_constant
7024 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7025 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7026 - 0x80000000);
7027}
7028
7029/* Sign-extend 32-bit mode address offsets that have bit 31 set and
7030 all higher bits unset. */
7031
7032static void
7033normalize_address_expr (expressionS *ex)
7034{
7035 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7036 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7037 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7038 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7039 - 0x80000000);
7040}
7041
7042/* Try to match TOKENS against OPCODE, storing the result in INSN.
7043 Return true if the match was successful.
7044
7045 OPCODE_EXTRA is a value that should be ORed into the opcode
7046 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7047 there are more alternatives after OPCODE and SOFT_MATCH is
7048 as for mips_arg_info. */
7049
7050static bfd_boolean
7051match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7052 struct mips_operand_token *tokens, unsigned int opcode_extra,
1a00e612 7053 bfd_boolean more_alts)
97d87491
RS
7054{
7055 const char *args;
7056 struct mips_arg_info arg;
7057 const struct mips_operand *operand;
7058 char c;
7059
7060 imm_expr.X_op = O_absent;
7061 imm2_expr.X_op = O_absent;
7062 offset_expr.X_op = O_absent;
7063 offset_reloc[0] = BFD_RELOC_UNUSED;
7064 offset_reloc[1] = BFD_RELOC_UNUSED;
7065 offset_reloc[2] = BFD_RELOC_UNUSED;
7066
7067 create_insn (insn, opcode);
7068 insn->insn_opcode |= opcode_extra;
97d87491
RS
7069 memset (&arg, 0, sizeof (arg));
7070 arg.insn = insn;
7071 arg.token = tokens;
7072 arg.argnum = 1;
7073 arg.last_regno = ILLEGAL_REG;
7074 arg.dest_regno = ILLEGAL_REG;
97d87491
RS
7075 for (args = opcode->args;; ++args)
7076 {
7077 if (arg.token->type == OT_END)
7078 {
7079 /* Handle unary instructions in which only one operand is given.
7080 The source is then the same as the destination. */
7081 if (arg.opnum == 1 && *args == ',')
7082 {
7083 operand = (mips_opts.micromips
7084 ? decode_micromips_operand (args + 1)
7085 : decode_mips_operand (args + 1));
7086 if (operand && mips_optional_operand_p (operand))
7087 {
7088 arg.token = tokens;
7089 arg.argnum = 1;
7090 continue;
7091 }
7092 }
7093
7094 /* Treat elided base registers as $0. */
7095 if (strcmp (args, "(b)") == 0)
7096 args += 3;
7097
7098 if (args[0] == '+')
7099 switch (args[1])
7100 {
7101 case 'K':
7102 case 'N':
7103 /* The register suffix is optional. */
7104 args += 2;
7105 break;
7106 }
7107
7108 /* Fail the match if there were too few operands. */
7109 if (*args)
7110 return FALSE;
7111
7112 /* Successful match. */
e3de51ce 7113 clear_insn_error ();
97d87491
RS
7114 if (arg.dest_regno == arg.last_regno
7115 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7116 {
7117 if (arg.opnum == 2)
e3de51ce
RS
7118 set_insn_error
7119 (0, _("Source and destination must be different"));
97d87491 7120 else if (arg.last_regno == 31)
e3de51ce
RS
7121 set_insn_error
7122 (0, _("A destination register must be supplied"));
97d87491
RS
7123 }
7124 check_completed_insn (&arg);
7125 return TRUE;
7126 }
7127
7128 /* Fail the match if the line has too many operands. */
7129 if (*args == 0)
7130 return FALSE;
7131
7132 /* Handle characters that need to match exactly. */
7133 if (*args == '(' || *args == ')' || *args == ',')
7134 {
7135 if (match_char (&arg, *args))
7136 continue;
7137 return FALSE;
7138 }
7139 if (*args == '#')
7140 {
7141 ++args;
7142 if (arg.token->type == OT_DOUBLE_CHAR
7143 && arg.token->u.ch == *args)
7144 {
7145 ++arg.token;
7146 continue;
7147 }
7148 return FALSE;
7149 }
7150
7151 /* Handle special macro operands. Work out the properties of
7152 other operands. */
7153 arg.opnum += 1;
7154 arg.lax_max = FALSE;
7155 switch (*args)
7156 {
7157 case '+':
7158 switch (args[1])
7159 {
97d87491
RS
7160 case 'I':
7161 /* "+I" is like "I", except that imm2_expr is used. */
1a00e612
RS
7162 if (!match_const_int (&arg, &imm2_expr.X_add_number))
7163 return FALSE;
7164 imm2_expr.X_op = O_constant;
97d87491
RS
7165 if (HAVE_32BIT_GPRS)
7166 normalize_constant_expr (&imm2_expr);
7167 ++args;
7168 continue;
7169
7170 case 'i':
7171 *offset_reloc = BFD_RELOC_MIPS_JMP;
7172 break;
7173 }
7174 break;
7175
97d87491 7176 case 'I':
1a00e612
RS
7177 if (!match_const_int (&arg, &imm_expr.X_add_number))
7178 return FALSE;
7179 imm_expr.X_op = O_constant;
97d87491
RS
7180 if (HAVE_32BIT_GPRS)
7181 normalize_constant_expr (&imm_expr);
7182 continue;
7183
7184 case 'A':
7185 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7186 {
7187 /* Assume that the offset has been elided and that what
7188 we saw was a base register. The match will fail later
7189 if that assumption turns out to be wrong. */
7190 offset_expr.X_op = O_constant;
7191 offset_expr.X_add_number = 0;
7192 }
97d87491 7193 else
1a00e612
RS
7194 {
7195 if (!match_expression (&arg, &offset_expr, offset_reloc))
7196 return FALSE;
7197 normalize_address_expr (&offset_expr);
7198 }
97d87491
RS
7199 continue;
7200
7201 case 'F':
7202 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7203 8, TRUE))
1a00e612 7204 return FALSE;
97d87491
RS
7205 continue;
7206
7207 case 'L':
7208 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7209 8, FALSE))
1a00e612 7210 return FALSE;
97d87491
RS
7211 continue;
7212
7213 case 'f':
7214 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7215 4, TRUE))
1a00e612 7216 return FALSE;
97d87491
RS
7217 continue;
7218
7219 case 'l':
7220 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7221 4, FALSE))
1a00e612 7222 return FALSE;
97d87491
RS
7223 continue;
7224
7225 /* ??? This is the traditional behavior, but is flaky if
7226 there are alternative versions of the same instruction
7227 for different subarchitectures. The next alternative
7228 might not be suitable. */
7229 case 'j':
7230 /* For compatibility with older assemblers, we accept
7231 0x8000-0xffff as signed 16-bit numbers when only
7232 signed numbers are allowed. */
7233 arg.lax_max = !more_alts;
7234 case 'i':
7235 /* Only accept non-constant operands if this is the
7236 final alternative. Later alternatives might include
7237 a macro implementation. */
7238 arg.allow_nonconst = !more_alts;
7239 break;
7240
7241 case 'u':
7242 /* There are no macro implementations for out-of-range values. */
7243 arg.allow_nonconst = TRUE;
7244 break;
7245
7246 case 'o':
7247 /* There should always be a macro implementation. */
7248 arg.allow_nonconst = FALSE;
7249 break;
7250
7251 case 'p':
7252 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7253 break;
7254
7255 case 'a':
7256 *offset_reloc = BFD_RELOC_MIPS_JMP;
7257 break;
7258
7259 case 'm':
7260 gas_assert (mips_opts.micromips);
7261 c = args[1];
7262 switch (c)
7263 {
7264 case 'D':
7265 case 'E':
7266 if (!forced_insn_length)
7267 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7268 else if (c == 'D')
7269 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7270 else
7271 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7272 break;
7273 }
7274 break;
7275 }
7276
7277 operand = (mips_opts.micromips
7278 ? decode_micromips_operand (args)
7279 : decode_mips_operand (args));
7280 if (!operand)
7281 abort ();
7282
7283 /* Skip prefixes. */
7284 if (*args == '+' || *args == 'm')
7285 args++;
7286
7287 if (mips_optional_operand_p (operand)
7288 && args[1] == ','
7289 && (arg.token[0].type != OT_REG
7290 || arg.token[1].type == OT_END))
7291 {
7292 /* Assume that the register has been elided and is the
7293 same as the first operand. */
7294 arg.token = tokens;
7295 arg.argnum = 1;
7296 }
7297
7298 if (!match_operand (&arg, operand))
7299 return FALSE;
7300 }
7301}
7302
7303/* Like match_insn, but for MIPS16. */
7304
7305static bfd_boolean
7306match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
1a00e612 7307 struct mips_operand_token *tokens)
97d87491
RS
7308{
7309 const char *args;
7310 const struct mips_operand *operand;
7311 const struct mips_operand *ext_operand;
7312 struct mips_arg_info arg;
7313 int relax_char;
7314
7315 create_insn (insn, opcode);
7316 imm_expr.X_op = O_absent;
7317 imm2_expr.X_op = O_absent;
7318 offset_expr.X_op = O_absent;
7319 offset_reloc[0] = BFD_RELOC_UNUSED;
7320 offset_reloc[1] = BFD_RELOC_UNUSED;
7321 offset_reloc[2] = BFD_RELOC_UNUSED;
7322 relax_char = 0;
7323
7324 memset (&arg, 0, sizeof (arg));
7325 arg.insn = insn;
7326 arg.token = tokens;
7327 arg.argnum = 1;
7328 arg.last_regno = ILLEGAL_REG;
7329 arg.dest_regno = ILLEGAL_REG;
97d87491
RS
7330 relax_char = 0;
7331 for (args = opcode->args;; ++args)
7332 {
7333 int c;
7334
7335 if (arg.token->type == OT_END)
7336 {
7337 offsetT value;
7338
7339 /* Handle unary instructions in which only one operand is given.
7340 The source is then the same as the destination. */
7341 if (arg.opnum == 1 && *args == ',')
7342 {
7343 operand = decode_mips16_operand (args[1], FALSE);
7344 if (operand && mips_optional_operand_p (operand))
7345 {
7346 arg.token = tokens;
7347 arg.argnum = 1;
7348 continue;
7349 }
7350 }
7351
7352 /* Fail the match if there were too few operands. */
7353 if (*args)
7354 return FALSE;
7355
7356 /* Successful match. Stuff the immediate value in now, if
7357 we can. */
e3de51ce 7358 clear_insn_error ();
97d87491
RS
7359 if (opcode->pinfo == INSN_MACRO)
7360 {
7361 gas_assert (relax_char == 0 || relax_char == 'p');
7362 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7363 }
7364 else if (relax_char
7365 && offset_expr.X_op == O_constant
7366 && calculate_reloc (*offset_reloc,
7367 offset_expr.X_add_number,
7368 &value))
7369 {
7370 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7371 forced_insn_length, &insn->insn_opcode);
7372 offset_expr.X_op = O_absent;
7373 *offset_reloc = BFD_RELOC_UNUSED;
7374 }
7375 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7376 {
7377 if (forced_insn_length == 2)
e3de51ce 7378 set_insn_error (0, _("invalid unextended operand value"));
97d87491
RS
7379 forced_insn_length = 4;
7380 insn->insn_opcode |= MIPS16_EXTEND;
7381 }
7382 else if (relax_char)
7383 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7384
7385 check_completed_insn (&arg);
7386 return TRUE;
7387 }
7388
7389 /* Fail the match if the line has too many operands. */
7390 if (*args == 0)
7391 return FALSE;
7392
7393 /* Handle characters that need to match exactly. */
7394 if (*args == '(' || *args == ')' || *args == ',')
7395 {
7396 if (match_char (&arg, *args))
7397 continue;
7398 return FALSE;
7399 }
7400
7401 arg.opnum += 1;
7402 c = *args;
7403 switch (c)
7404 {
7405 case 'p':
7406 case 'q':
7407 case 'A':
7408 case 'B':
7409 case 'E':
7410 relax_char = c;
7411 break;
7412
7413 case 'I':
1a00e612
RS
7414 if (!match_const_int (&arg, &imm_expr.X_add_number))
7415 return FALSE;
7416 imm_expr.X_op = O_constant;
97d87491
RS
7417 if (HAVE_32BIT_GPRS)
7418 normalize_constant_expr (&imm_expr);
7419 continue;
7420
7421 case 'a':
7422 case 'i':
7423 *offset_reloc = BFD_RELOC_MIPS16_JMP;
7424 insn->insn_opcode <<= 16;
7425 break;
7426 }
7427
7428 operand = decode_mips16_operand (c, FALSE);
7429 if (!operand)
7430 abort ();
7431
7432 /* '6' is a special case. It is used for BREAK and SDBBP,
7433 whose operands are only meaningful to the software that decodes
7434 them. This means that there is no architectural reason why
7435 they cannot be prefixed by EXTEND, but in practice,
7436 exception handlers will only look at the instruction
7437 itself. We therefore allow '6' to be extended when
7438 disassembling but not when assembling. */
7439 if (operand->type != OP_PCREL && c != '6')
7440 {
7441 ext_operand = decode_mips16_operand (c, TRUE);
7442 if (operand != ext_operand)
7443 {
7444 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7445 {
7446 offset_expr.X_op = O_constant;
7447 offset_expr.X_add_number = 0;
7448 relax_char = c;
7449 continue;
7450 }
7451
7452 /* We need the OT_INTEGER check because some MIPS16
7453 immediate variants are listed before the register ones. */
7454 if (arg.token->type != OT_INTEGER
7455 || !match_expression (&arg, &offset_expr, offset_reloc))
7456 return FALSE;
7457
7458 /* '8' is used for SLTI(U) and has traditionally not
7459 been allowed to take relocation operators. */
7460 if (offset_reloc[0] != BFD_RELOC_UNUSED
7461 && (ext_operand->size != 16 || c == '8'))
7462 return FALSE;
7463
7464 relax_char = c;
7465 continue;
7466 }
7467 }
7468
7469 if (mips_optional_operand_p (operand)
7470 && args[1] == ','
7471 && (arg.token[0].type != OT_REG
7472 || arg.token[1].type == OT_END))
7473 {
7474 /* Assume that the register has been elided and is the
7475 same as the first operand. */
7476 arg.token = tokens;
7477 arg.argnum = 1;
7478 }
7479
7480 if (!match_operand (&arg, operand))
7481 return FALSE;
7482 }
7483}
7484
584892a6
RS
7485/* Set up global variables for the start of a new macro. */
7486
7487static void
7488macro_start (void)
7489{
7490 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
df58fc94
RS
7491 memset (&mips_macro_warning.first_insn_sizes, 0,
7492 sizeof (mips_macro_warning.first_insn_sizes));
7493 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
584892a6 7494 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
11625dd8 7495 && delayed_branch_p (&history[0]));
df58fc94
RS
7496 switch (history[0].insn_mo->pinfo2
7497 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
7498 {
7499 case INSN2_BRANCH_DELAY_32BIT:
7500 mips_macro_warning.delay_slot_length = 4;
7501 break;
7502 case INSN2_BRANCH_DELAY_16BIT:
7503 mips_macro_warning.delay_slot_length = 2;
7504 break;
7505 default:
7506 mips_macro_warning.delay_slot_length = 0;
7507 break;
7508 }
7509 mips_macro_warning.first_frag = NULL;
584892a6
RS
7510}
7511
df58fc94
RS
7512/* Given that a macro is longer than one instruction or of the wrong size,
7513 return the appropriate warning for it. Return null if no warning is
7514 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7515 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7516 and RELAX_NOMACRO. */
584892a6
RS
7517
7518static const char *
7519macro_warning (relax_substateT subtype)
7520{
7521 if (subtype & RELAX_DELAY_SLOT)
7522 return _("Macro instruction expanded into multiple instructions"
7523 " in a branch delay slot");
7524 else if (subtype & RELAX_NOMACRO)
7525 return _("Macro instruction expanded into multiple instructions");
df58fc94
RS
7526 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
7527 | RELAX_DELAY_SLOT_SIZE_SECOND))
7528 return ((subtype & RELAX_DELAY_SLOT_16BIT)
7529 ? _("Macro instruction expanded into a wrong size instruction"
7530 " in a 16-bit branch delay slot")
7531 : _("Macro instruction expanded into a wrong size instruction"
7532 " in a 32-bit branch delay slot"));
584892a6
RS
7533 else
7534 return 0;
7535}
7536
7537/* Finish up a macro. Emit warnings as appropriate. */
7538
7539static void
7540macro_end (void)
7541{
df58fc94
RS
7542 /* Relaxation warning flags. */
7543 relax_substateT subtype = 0;
7544
7545 /* Check delay slot size requirements. */
7546 if (mips_macro_warning.delay_slot_length == 2)
7547 subtype |= RELAX_DELAY_SLOT_16BIT;
7548 if (mips_macro_warning.delay_slot_length != 0)
584892a6 7549 {
df58fc94
RS
7550 if (mips_macro_warning.delay_slot_length
7551 != mips_macro_warning.first_insn_sizes[0])
7552 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
7553 if (mips_macro_warning.delay_slot_length
7554 != mips_macro_warning.first_insn_sizes[1])
7555 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
7556 }
584892a6 7557
df58fc94
RS
7558 /* Check instruction count requirements. */
7559 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
7560 {
7561 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
584892a6
RS
7562 subtype |= RELAX_SECOND_LONGER;
7563 if (mips_opts.warn_about_macros)
7564 subtype |= RELAX_NOMACRO;
7565 if (mips_macro_warning.delay_slot_p)
7566 subtype |= RELAX_DELAY_SLOT;
df58fc94 7567 }
584892a6 7568
df58fc94
RS
7569 /* If both alternatives fail to fill a delay slot correctly,
7570 emit the warning now. */
7571 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
7572 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
7573 {
7574 relax_substateT s;
7575 const char *msg;
7576
7577 s = subtype & (RELAX_DELAY_SLOT_16BIT
7578 | RELAX_DELAY_SLOT_SIZE_FIRST
7579 | RELAX_DELAY_SLOT_SIZE_SECOND);
7580 msg = macro_warning (s);
7581 if (msg != NULL)
7582 as_warn ("%s", msg);
7583 subtype &= ~s;
7584 }
7585
7586 /* If both implementations are longer than 1 instruction, then emit the
7587 warning now. */
7588 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
7589 {
7590 relax_substateT s;
7591 const char *msg;
7592
7593 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
7594 msg = macro_warning (s);
7595 if (msg != NULL)
7596 as_warn ("%s", msg);
7597 subtype &= ~s;
584892a6 7598 }
df58fc94
RS
7599
7600 /* If any flags still set, then one implementation might need a warning
7601 and the other either will need one of a different kind or none at all.
7602 Pass any remaining flags over to relaxation. */
7603 if (mips_macro_warning.first_frag != NULL)
7604 mips_macro_warning.first_frag->fr_subtype |= subtype;
584892a6
RS
7605}
7606
df58fc94
RS
7607/* Instruction operand formats used in macros that vary between
7608 standard MIPS and microMIPS code. */
7609
833794fc 7610static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
df58fc94
RS
7611static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
7612static const char * const jalr_fmt[2] = { "d,s", "t,s" };
7613static const char * const lui_fmt[2] = { "t,u", "s,u" };
7614static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
833794fc 7615static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
df58fc94
RS
7616static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
7617static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
7618
833794fc 7619#define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
df58fc94
RS
7620#define COP12_FMT (cop12_fmt[mips_opts.micromips])
7621#define JALR_FMT (jalr_fmt[mips_opts.micromips])
7622#define LUI_FMT (lui_fmt[mips_opts.micromips])
7623#define MEM12_FMT (mem12_fmt[mips_opts.micromips])
833794fc 7624#define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
df58fc94
RS
7625#define SHFT_FMT (shft_fmt[mips_opts.micromips])
7626#define TRAP_FMT (trap_fmt[mips_opts.micromips])
7627
6e1304d8
RS
7628/* Read a macro's relocation codes from *ARGS and store them in *R.
7629 The first argument in *ARGS will be either the code for a single
7630 relocation or -1 followed by the three codes that make up a
7631 composite relocation. */
7632
7633static void
7634macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
7635{
7636 int i, next;
7637
7638 next = va_arg (*args, int);
7639 if (next >= 0)
7640 r[0] = (bfd_reloc_code_real_type) next;
7641 else
f2ae14a1
RS
7642 {
7643 for (i = 0; i < 3; i++)
7644 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
7645 /* This function is only used for 16-bit relocation fields.
7646 To make the macro code simpler, treat an unrelocated value
7647 in the same way as BFD_RELOC_LO16. */
7648 if (r[0] == BFD_RELOC_UNUSED)
7649 r[0] = BFD_RELOC_LO16;
7650 }
6e1304d8
RS
7651}
7652
252b5132
RH
7653/* Build an instruction created by a macro expansion. This is passed
7654 a pointer to the count of instructions created so far, an
7655 expression, the name of the instruction to build, an operand format
7656 string, and corresponding arguments. */
7657
252b5132 7658static void
67c0d1eb 7659macro_build (expressionS *ep, const char *name, const char *fmt, ...)
252b5132 7660{
df58fc94 7661 const struct mips_opcode *mo = NULL;
f6688943 7662 bfd_reloc_code_real_type r[3];
df58fc94 7663 const struct mips_opcode *amo;
e077a1c8 7664 const struct mips_operand *operand;
df58fc94
RS
7665 struct hash_control *hash;
7666 struct mips_cl_insn insn;
252b5132 7667 va_list args;
e077a1c8 7668 unsigned int uval;
252b5132 7669
252b5132 7670 va_start (args, fmt);
252b5132 7671
252b5132
RH
7672 if (mips_opts.mips16)
7673 {
03ea81db 7674 mips16_macro_build (ep, name, fmt, &args);
252b5132
RH
7675 va_end (args);
7676 return;
7677 }
7678
f6688943
TS
7679 r[0] = BFD_RELOC_UNUSED;
7680 r[1] = BFD_RELOC_UNUSED;
7681 r[2] = BFD_RELOC_UNUSED;
df58fc94
RS
7682 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
7683 amo = (struct mips_opcode *) hash_find (hash, name);
7684 gas_assert (amo);
7685 gas_assert (strcmp (name, amo->name) == 0);
1e915849 7686
df58fc94 7687 do
8b082fb1
TS
7688 {
7689 /* Search until we get a match for NAME. It is assumed here that
df58fc94
RS
7690 macros will never generate MDMX, MIPS-3D, or MT instructions.
7691 We try to match an instruction that fulfils the branch delay
7692 slot instruction length requirement (if any) of the previous
7693 instruction. While doing this we record the first instruction
7694 seen that matches all the other conditions and use it anyway
7695 if the requirement cannot be met; we will issue an appropriate
7696 warning later on. */
7697 if (strcmp (fmt, amo->args) == 0
7698 && amo->pinfo != INSN_MACRO
7699 && is_opcode_valid (amo)
7700 && is_size_valid (amo))
7701 {
7702 if (is_delay_slot_valid (amo))
7703 {
7704 mo = amo;
7705 break;
7706 }
7707 else if (!mo)
7708 mo = amo;
7709 }
8b082fb1 7710
df58fc94
RS
7711 ++amo;
7712 gas_assert (amo->name);
252b5132 7713 }
df58fc94 7714 while (strcmp (name, amo->name) == 0);
252b5132 7715
df58fc94 7716 gas_assert (mo);
1e915849 7717 create_insn (&insn, mo);
e077a1c8 7718 for (; *fmt; ++fmt)
252b5132 7719 {
e077a1c8 7720 switch (*fmt)
252b5132 7721 {
252b5132
RH
7722 case ',':
7723 case '(':
7724 case ')':
252b5132 7725 case 'z':
e077a1c8 7726 break;
252b5132
RH
7727
7728 case 'i':
7729 case 'j':
6e1304d8 7730 macro_read_relocs (&args, r);
9c2799c2 7731 gas_assert (*r == BFD_RELOC_GPREL16
e391c024
RS
7732 || *r == BFD_RELOC_MIPS_HIGHER
7733 || *r == BFD_RELOC_HI16_S
7734 || *r == BFD_RELOC_LO16
7735 || *r == BFD_RELOC_MIPS_GOT_OFST);
e077a1c8 7736 break;
e391c024
RS
7737
7738 case 'o':
7739 macro_read_relocs (&args, r);
e077a1c8 7740 break;
252b5132
RH
7741
7742 case 'u':
6e1304d8 7743 macro_read_relocs (&args, r);
9c2799c2 7744 gas_assert (ep != NULL
90ecf173
MR
7745 && (ep->X_op == O_constant
7746 || (ep->X_op == O_symbol
7747 && (*r == BFD_RELOC_MIPS_HIGHEST
7748 || *r == BFD_RELOC_HI16_S
7749 || *r == BFD_RELOC_HI16
7750 || *r == BFD_RELOC_GPREL16
7751 || *r == BFD_RELOC_MIPS_GOT_HI16
7752 || *r == BFD_RELOC_MIPS_CALL_HI16))));
e077a1c8 7753 break;
252b5132
RH
7754
7755 case 'p':
9c2799c2 7756 gas_assert (ep != NULL);
bad36eac 7757
252b5132
RH
7758 /*
7759 * This allows macro() to pass an immediate expression for
7760 * creating short branches without creating a symbol.
bad36eac
DJ
7761 *
7762 * We don't allow branch relaxation for these branches, as
7763 * they should only appear in ".set nomacro" anyway.
252b5132
RH
7764 */
7765 if (ep->X_op == O_constant)
7766 {
df58fc94
RS
7767 /* For microMIPS we always use relocations for branches.
7768 So we should not resolve immediate values. */
7769 gas_assert (!mips_opts.micromips);
7770
bad36eac
DJ
7771 if ((ep->X_add_number & 3) != 0)
7772 as_bad (_("branch to misaligned address (0x%lx)"),
7773 (unsigned long) ep->X_add_number);
7774 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
7775 as_bad (_("branch address range overflow (0x%lx)"),
7776 (unsigned long) ep->X_add_number);
252b5132
RH
7777 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
7778 ep = NULL;
7779 }
7780 else
0b25d3e6 7781 *r = BFD_RELOC_16_PCREL_S2;
e077a1c8 7782 break;
252b5132
RH
7783
7784 case 'a':
9c2799c2 7785 gas_assert (ep != NULL);
f6688943 7786 *r = BFD_RELOC_MIPS_JMP;
e077a1c8 7787 break;
d43b4baf 7788
252b5132 7789 default:
e077a1c8
RS
7790 operand = (mips_opts.micromips
7791 ? decode_micromips_operand (fmt)
7792 : decode_mips_operand (fmt));
7793 if (!operand)
7794 abort ();
7795
7796 uval = va_arg (args, int);
7797 if (operand->type == OP_CLO_CLZ_DEST)
7798 uval |= (uval << 5);
7799 insn_insert_operand (&insn, operand, uval);
7800
7801 if (*fmt == '+' || *fmt == 'm')
7802 ++fmt;
7803 break;
252b5132 7804 }
252b5132
RH
7805 }
7806 va_end (args);
9c2799c2 7807 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 7808
df58fc94 7809 append_insn (&insn, ep, r, TRUE);
252b5132
RH
7810}
7811
7812static void
67c0d1eb 7813mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
03ea81db 7814 va_list *args)
252b5132 7815{
1e915849 7816 struct mips_opcode *mo;
252b5132 7817 struct mips_cl_insn insn;
e077a1c8 7818 const struct mips_operand *operand;
f6688943
TS
7819 bfd_reloc_code_real_type r[3]
7820 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 7821
1e915849 7822 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
9c2799c2
NC
7823 gas_assert (mo);
7824 gas_assert (strcmp (name, mo->name) == 0);
252b5132 7825
1e915849 7826 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
252b5132 7827 {
1e915849 7828 ++mo;
9c2799c2
NC
7829 gas_assert (mo->name);
7830 gas_assert (strcmp (name, mo->name) == 0);
252b5132
RH
7831 }
7832
1e915849 7833 create_insn (&insn, mo);
e077a1c8 7834 for (; *fmt; ++fmt)
252b5132
RH
7835 {
7836 int c;
7837
e077a1c8 7838 c = *fmt;
252b5132
RH
7839 switch (c)
7840 {
252b5132
RH
7841 case ',':
7842 case '(':
7843 case ')':
e077a1c8 7844 break;
252b5132
RH
7845
7846 case '0':
7847 case 'S':
7848 case 'P':
7849 case 'R':
e077a1c8 7850 break;
252b5132
RH
7851
7852 case '<':
7853 case '>':
7854 case '4':
7855 case '5':
7856 case 'H':
7857 case 'W':
7858 case 'D':
7859 case 'j':
7860 case '8':
7861 case 'V':
7862 case 'C':
7863 case 'U':
7864 case 'k':
7865 case 'K':
7866 case 'p':
7867 case 'q':
7868 {
b886a2ab
RS
7869 offsetT value;
7870
9c2799c2 7871 gas_assert (ep != NULL);
252b5132
RH
7872
7873 if (ep->X_op != O_constant)
874e8986 7874 *r = (int) BFD_RELOC_UNUSED + c;
b886a2ab 7875 else if (calculate_reloc (*r, ep->X_add_number, &value))
252b5132 7876 {
b886a2ab 7877 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
252b5132 7878 ep = NULL;
f6688943 7879 *r = BFD_RELOC_UNUSED;
252b5132
RH
7880 }
7881 }
e077a1c8 7882 break;
252b5132 7883
e077a1c8
RS
7884 default:
7885 operand = decode_mips16_operand (c, FALSE);
7886 if (!operand)
7887 abort ();
252b5132 7888
4a06e5a2 7889 insn_insert_operand (&insn, operand, va_arg (*args, int));
e077a1c8
RS
7890 break;
7891 }
252b5132
RH
7892 }
7893
9c2799c2 7894 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 7895
df58fc94 7896 append_insn (&insn, ep, r, TRUE);
252b5132
RH
7897}
7898
438c16b8
TS
7899/*
7900 * Generate a "jalr" instruction with a relocation hint to the called
7901 * function. This occurs in NewABI PIC code.
7902 */
7903static void
df58fc94 7904macro_build_jalr (expressionS *ep, int cprestore)
438c16b8 7905{
df58fc94
RS
7906 static const bfd_reloc_code_real_type jalr_relocs[2]
7907 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
7908 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
7909 const char *jalr;
685736be 7910 char *f = NULL;
b34976b6 7911
1180b5a4 7912 if (MIPS_JALR_HINT_P (ep))
f21f8242 7913 {
cc3d92a5 7914 frag_grow (8);
f21f8242
AO
7915 f = frag_more (0);
7916 }
2906b037 7917 if (mips_opts.micromips)
df58fc94 7918 {
833794fc
MR
7919 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
7920 ? "jalr" : "jalrs");
e64af278 7921 if (MIPS_JALR_HINT_P (ep)
833794fc 7922 || mips_opts.insn32
e64af278 7923 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
df58fc94
RS
7924 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
7925 else
7926 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
7927 }
2906b037
MR
7928 else
7929 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
1180b5a4 7930 if (MIPS_JALR_HINT_P (ep))
df58fc94 7931 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
438c16b8
TS
7932}
7933
252b5132
RH
7934/*
7935 * Generate a "lui" instruction.
7936 */
7937static void
67c0d1eb 7938macro_build_lui (expressionS *ep, int regnum)
252b5132 7939{
9c2799c2 7940 gas_assert (! mips_opts.mips16);
252b5132 7941
df58fc94 7942 if (ep->X_op != O_constant)
252b5132 7943 {
9c2799c2 7944 gas_assert (ep->X_op == O_symbol);
bbe506e8
TS
7945 /* _gp_disp is a special case, used from s_cpload.
7946 __gnu_local_gp is used if mips_no_shared. */
9c2799c2 7947 gas_assert (mips_pic == NO_PIC
78e1bb40 7948 || (! HAVE_NEWABI
aa6975fb
ILT
7949 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
7950 || (! mips_in_shared
bbe506e8
TS
7951 && strcmp (S_GET_NAME (ep->X_add_symbol),
7952 "__gnu_local_gp") == 0));
252b5132
RH
7953 }
7954
df58fc94 7955 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
252b5132
RH
7956}
7957
885add95
CD
7958/* Generate a sequence of instructions to do a load or store from a constant
7959 offset off of a base register (breg) into/from a target register (treg),
7960 using AT if necessary. */
7961static void
67c0d1eb
RS
7962macro_build_ldst_constoffset (expressionS *ep, const char *op,
7963 int treg, int breg, int dbl)
885add95 7964{
9c2799c2 7965 gas_assert (ep->X_op == O_constant);
885add95 7966
256ab948 7967 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
7968 if (!dbl)
7969 normalize_constant_expr (ep);
256ab948 7970
67c1ffbe 7971 /* Right now, this routine can only handle signed 32-bit constants. */
ecd13cd3 7972 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
885add95
CD
7973 as_warn (_("operand overflow"));
7974
7975 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
7976 {
7977 /* Signed 16-bit offset will fit in the op. Easy! */
67c0d1eb 7978 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
885add95
CD
7979 }
7980 else
7981 {
7982 /* 32-bit offset, need multiple instructions and AT, like:
7983 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7984 addu $tempreg,$tempreg,$breg
7985 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7986 to handle the complete offset. */
67c0d1eb
RS
7987 macro_build_lui (ep, AT);
7988 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7989 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
885add95 7990
741fe287 7991 if (!mips_opts.at)
8fc2e39e 7992 as_bad (_("Macro used $at after \".set noat\""));
885add95
CD
7993 }
7994}
7995
252b5132
RH
7996/* set_at()
7997 * Generates code to set the $at register to true (one)
7998 * if reg is less than the immediate expression.
7999 */
8000static void
67c0d1eb 8001set_at (int reg, int unsignedp)
252b5132
RH
8002{
8003 if (imm_expr.X_op == O_constant
8004 && imm_expr.X_add_number >= -0x8000
8005 && imm_expr.X_add_number < 0x8000)
67c0d1eb
RS
8006 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8007 AT, reg, BFD_RELOC_LO16);
252b5132
RH
8008 else
8009 {
67c0d1eb
RS
8010 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8011 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
252b5132
RH
8012 }
8013}
8014
252b5132
RH
8015/* Count the leading zeroes by performing a binary chop. This is a
8016 bulky bit of source, but performance is a LOT better for the
8017 majority of values than a simple loop to count the bits:
8018 for (lcnt = 0; (lcnt < 32); lcnt++)
8019 if ((v) & (1 << (31 - lcnt)))
8020 break;
8021 However it is not code size friendly, and the gain will drop a bit
8022 on certain cached systems.
8023*/
8024#define COUNT_TOP_ZEROES(v) \
8025 (((v) & ~0xffff) == 0 \
8026 ? ((v) & ~0xff) == 0 \
8027 ? ((v) & ~0xf) == 0 \
8028 ? ((v) & ~0x3) == 0 \
8029 ? ((v) & ~0x1) == 0 \
8030 ? !(v) \
8031 ? 32 \
8032 : 31 \
8033 : 30 \
8034 : ((v) & ~0x7) == 0 \
8035 ? 29 \
8036 : 28 \
8037 : ((v) & ~0x3f) == 0 \
8038 ? ((v) & ~0x1f) == 0 \
8039 ? 27 \
8040 : 26 \
8041 : ((v) & ~0x7f) == 0 \
8042 ? 25 \
8043 : 24 \
8044 : ((v) & ~0xfff) == 0 \
8045 ? ((v) & ~0x3ff) == 0 \
8046 ? ((v) & ~0x1ff) == 0 \
8047 ? 23 \
8048 : 22 \
8049 : ((v) & ~0x7ff) == 0 \
8050 ? 21 \
8051 : 20 \
8052 : ((v) & ~0x3fff) == 0 \
8053 ? ((v) & ~0x1fff) == 0 \
8054 ? 19 \
8055 : 18 \
8056 : ((v) & ~0x7fff) == 0 \
8057 ? 17 \
8058 : 16 \
8059 : ((v) & ~0xffffff) == 0 \
8060 ? ((v) & ~0xfffff) == 0 \
8061 ? ((v) & ~0x3ffff) == 0 \
8062 ? ((v) & ~0x1ffff) == 0 \
8063 ? 15 \
8064 : 14 \
8065 : ((v) & ~0x7ffff) == 0 \
8066 ? 13 \
8067 : 12 \
8068 : ((v) & ~0x3fffff) == 0 \
8069 ? ((v) & ~0x1fffff) == 0 \
8070 ? 11 \
8071 : 10 \
8072 : ((v) & ~0x7fffff) == 0 \
8073 ? 9 \
8074 : 8 \
8075 : ((v) & ~0xfffffff) == 0 \
8076 ? ((v) & ~0x3ffffff) == 0 \
8077 ? ((v) & ~0x1ffffff) == 0 \
8078 ? 7 \
8079 : 6 \
8080 : ((v) & ~0x7ffffff) == 0 \
8081 ? 5 \
8082 : 4 \
8083 : ((v) & ~0x3fffffff) == 0 \
8084 ? ((v) & ~0x1fffffff) == 0 \
8085 ? 3 \
8086 : 2 \
8087 : ((v) & ~0x7fffffff) == 0 \
8088 ? 1 \
8089 : 0)
8090
8091/* load_register()
67c1ffbe 8092 * This routine generates the least number of instructions necessary to load
252b5132
RH
8093 * an absolute expression value into a register.
8094 */
8095static void
67c0d1eb 8096load_register (int reg, expressionS *ep, int dbl)
252b5132
RH
8097{
8098 int freg;
8099 expressionS hi32, lo32;
8100
8101 if (ep->X_op != O_big)
8102 {
9c2799c2 8103 gas_assert (ep->X_op == O_constant);
256ab948
TS
8104
8105 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
8106 if (!dbl)
8107 normalize_constant_expr (ep);
256ab948
TS
8108
8109 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
252b5132
RH
8110 {
8111 /* We can handle 16 bit signed values with an addiu to
8112 $zero. No need to ever use daddiu here, since $zero and
8113 the result are always correct in 32 bit mode. */
67c0d1eb 8114 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8115 return;
8116 }
8117 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8118 {
8119 /* We can handle 16 bit unsigned values with an ori to
8120 $zero. */
67c0d1eb 8121 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8122 return;
8123 }
256ab948 8124 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
252b5132
RH
8125 {
8126 /* 32 bit values require an lui. */
df58fc94 8127 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 8128 if ((ep->X_add_number & 0xffff) != 0)
67c0d1eb 8129 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
252b5132
RH
8130 return;
8131 }
8132 }
8133
8134 /* The value is larger than 32 bits. */
8135
2051e8c4 8136 if (!dbl || HAVE_32BIT_GPRS)
252b5132 8137 {
55e08f71
NC
8138 char value[32];
8139
8140 sprintf_vma (value, ep->X_add_number);
20e1fcfd 8141 as_bad (_("Number (0x%s) larger than 32 bits"), value);
67c0d1eb 8142 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8143 return;
8144 }
8145
8146 if (ep->X_op != O_big)
8147 {
8148 hi32 = *ep;
8149 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8150 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8151 hi32.X_add_number &= 0xffffffff;
8152 lo32 = *ep;
8153 lo32.X_add_number &= 0xffffffff;
8154 }
8155 else
8156 {
9c2799c2 8157 gas_assert (ep->X_add_number > 2);
252b5132
RH
8158 if (ep->X_add_number == 3)
8159 generic_bignum[3] = 0;
8160 else if (ep->X_add_number > 4)
8161 as_bad (_("Number larger than 64 bits"));
8162 lo32.X_op = O_constant;
8163 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8164 hi32.X_op = O_constant;
8165 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8166 }
8167
8168 if (hi32.X_add_number == 0)
8169 freg = 0;
8170 else
8171 {
8172 int shift, bit;
8173 unsigned long hi, lo;
8174
956cd1d6 8175 if (hi32.X_add_number == (offsetT) 0xffffffff)
beae10d5
KH
8176 {
8177 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8178 {
67c0d1eb 8179 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
8180 return;
8181 }
8182 if (lo32.X_add_number & 0x80000000)
8183 {
df58fc94 8184 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 8185 if (lo32.X_add_number & 0xffff)
67c0d1eb 8186 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
beae10d5
KH
8187 return;
8188 }
8189 }
252b5132
RH
8190
8191 /* Check for 16bit shifted constant. We know that hi32 is
8192 non-zero, so start the mask on the first bit of the hi32
8193 value. */
8194 shift = 17;
8195 do
beae10d5
KH
8196 {
8197 unsigned long himask, lomask;
8198
8199 if (shift < 32)
8200 {
8201 himask = 0xffff >> (32 - shift);
8202 lomask = (0xffff << shift) & 0xffffffff;
8203 }
8204 else
8205 {
8206 himask = 0xffff << (shift - 32);
8207 lomask = 0;
8208 }
8209 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8210 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8211 {
8212 expressionS tmp;
8213
8214 tmp.X_op = O_constant;
8215 if (shift < 32)
8216 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8217 | (lo32.X_add_number >> shift));
8218 else
8219 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
67c0d1eb 8220 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
df58fc94 8221 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 8222 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
8223 return;
8224 }
f9419b05 8225 ++shift;
beae10d5
KH
8226 }
8227 while (shift <= (64 - 16));
252b5132
RH
8228
8229 /* Find the bit number of the lowest one bit, and store the
8230 shifted value in hi/lo. */
8231 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8232 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8233 if (lo != 0)
8234 {
8235 bit = 0;
8236 while ((lo & 1) == 0)
8237 {
8238 lo >>= 1;
8239 ++bit;
8240 }
8241 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8242 hi >>= bit;
8243 }
8244 else
8245 {
8246 bit = 32;
8247 while ((hi & 1) == 0)
8248 {
8249 hi >>= 1;
8250 ++bit;
8251 }
8252 lo = hi;
8253 hi = 0;
8254 }
8255
8256 /* Optimize if the shifted value is a (power of 2) - 1. */
8257 if ((hi == 0 && ((lo + 1) & lo) == 0)
8258 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
beae10d5
KH
8259 {
8260 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
252b5132 8261 if (shift != 0)
beae10d5 8262 {
252b5132
RH
8263 expressionS tmp;
8264
8265 /* This instruction will set the register to be all
8266 ones. */
beae10d5
KH
8267 tmp.X_op = O_constant;
8268 tmp.X_add_number = (offsetT) -1;
67c0d1eb 8269 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
8270 if (bit != 0)
8271 {
8272 bit += shift;
df58fc94 8273 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 8274 reg, reg, (bit >= 32) ? bit - 32 : bit);
beae10d5 8275 }
df58fc94 8276 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
67c0d1eb 8277 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
8278 return;
8279 }
8280 }
252b5132
RH
8281
8282 /* Sign extend hi32 before calling load_register, because we can
8283 generally get better code when we load a sign extended value. */
8284 if ((hi32.X_add_number & 0x80000000) != 0)
beae10d5 8285 hi32.X_add_number |= ~(offsetT) 0xffffffff;
67c0d1eb 8286 load_register (reg, &hi32, 0);
252b5132
RH
8287 freg = reg;
8288 }
8289 if ((lo32.X_add_number & 0xffff0000) == 0)
8290 {
8291 if (freg != 0)
8292 {
df58fc94 8293 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
252b5132
RH
8294 freg = reg;
8295 }
8296 }
8297 else
8298 {
8299 expressionS mid16;
8300
956cd1d6 8301 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
beae10d5 8302 {
df58fc94
RS
8303 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8304 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
beae10d5
KH
8305 return;
8306 }
252b5132
RH
8307
8308 if (freg != 0)
8309 {
df58fc94 8310 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
252b5132
RH
8311 freg = reg;
8312 }
8313 mid16 = lo32;
8314 mid16.X_add_number >>= 16;
67c0d1eb 8315 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
df58fc94 8316 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
252b5132
RH
8317 freg = reg;
8318 }
8319 if ((lo32.X_add_number & 0xffff) != 0)
67c0d1eb 8320 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
252b5132
RH
8321}
8322
269137b2
TS
8323static inline void
8324load_delay_nop (void)
8325{
8326 if (!gpr_interlocks)
8327 macro_build (NULL, "nop", "");
8328}
8329
252b5132
RH
8330/* Load an address into a register. */
8331
8332static void
67c0d1eb 8333load_address (int reg, expressionS *ep, int *used_at)
252b5132 8334{
252b5132
RH
8335 if (ep->X_op != O_constant
8336 && ep->X_op != O_symbol)
8337 {
8338 as_bad (_("expression too complex"));
8339 ep->X_op = O_constant;
8340 }
8341
8342 if (ep->X_op == O_constant)
8343 {
67c0d1eb 8344 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
252b5132
RH
8345 return;
8346 }
8347
8348 if (mips_pic == NO_PIC)
8349 {
8350 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 8351 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
8352 Otherwise we want
8353 lui $reg,<sym> (BFD_RELOC_HI16_S)
8354 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
d6bc6245 8355 If we have an addend, we always use the latter form.
76b3015f 8356
d6bc6245
TS
8357 With 64bit address space and a usable $at we want
8358 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8359 lui $at,<sym> (BFD_RELOC_HI16_S)
8360 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8361 daddiu $at,<sym> (BFD_RELOC_LO16)
8362 dsll32 $reg,0
3a482fd5 8363 daddu $reg,$reg,$at
76b3015f 8364
c03099e6 8365 If $at is already in use, we use a path which is suboptimal
d6bc6245
TS
8366 on superscalar processors.
8367 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8368 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8369 dsll $reg,16
8370 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8371 dsll $reg,16
8372 daddiu $reg,<sym> (BFD_RELOC_LO16)
6caf9ef4
TS
8373
8374 For GP relative symbols in 64bit address space we can use
8375 the same sequence as in 32bit address space. */
aed1a261 8376 if (HAVE_64BIT_SYMBOLS)
d6bc6245 8377 {
6caf9ef4
TS
8378 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8379 && !nopic_need_relax (ep->X_add_symbol, 1))
8380 {
8381 relax_start (ep->X_add_symbol);
8382 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8383 mips_gp_register, BFD_RELOC_GPREL16);
8384 relax_switch ();
8385 }
d6bc6245 8386
741fe287 8387 if (*used_at == 0 && mips_opts.at)
d6bc6245 8388 {
df58fc94
RS
8389 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8390 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
67c0d1eb
RS
8391 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8392 BFD_RELOC_MIPS_HIGHER);
8393 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
df58fc94 8394 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
67c0d1eb 8395 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
d6bc6245
TS
8396 *used_at = 1;
8397 }
8398 else
8399 {
df58fc94 8400 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb
RS
8401 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8402 BFD_RELOC_MIPS_HIGHER);
df58fc94 8403 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 8404 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
df58fc94 8405 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 8406 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
d6bc6245 8407 }
6caf9ef4
TS
8408
8409 if (mips_relax.sequence)
8410 relax_end ();
d6bc6245 8411 }
252b5132
RH
8412 else
8413 {
d6bc6245 8414 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 8415 && !nopic_need_relax (ep->X_add_symbol, 1))
d6bc6245 8416 {
4d7206a2 8417 relax_start (ep->X_add_symbol);
67c0d1eb 8418 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
17a2f251 8419 mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 8420 relax_switch ();
d6bc6245 8421 }
67c0d1eb
RS
8422 macro_build_lui (ep, reg);
8423 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
8424 reg, reg, BFD_RELOC_LO16);
4d7206a2
RS
8425 if (mips_relax.sequence)
8426 relax_end ();
d6bc6245 8427 }
252b5132 8428 }
0a44bf69 8429 else if (!mips_big_got)
252b5132
RH
8430 {
8431 expressionS ex;
8432
8433 /* If this is a reference to an external symbol, we want
8434 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8435 Otherwise we want
8436 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8437 nop
8438 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
f5040a92
AO
8439 If there is a constant, it must be added in after.
8440
ed6fb7bd 8441 If we have NewABI, we want
f5040a92
AO
8442 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8443 unless we're referencing a global symbol with a non-zero
8444 offset, in which case cst must be added separately. */
ed6fb7bd
SC
8445 if (HAVE_NEWABI)
8446 {
f5040a92
AO
8447 if (ep->X_add_number)
8448 {
4d7206a2 8449 ex.X_add_number = ep->X_add_number;
f5040a92 8450 ep->X_add_number = 0;
4d7206a2 8451 relax_start (ep->X_add_symbol);
67c0d1eb
RS
8452 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8453 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
8454 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8455 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8456 ex.X_op = O_constant;
67c0d1eb 8457 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 8458 reg, reg, BFD_RELOC_LO16);
f5040a92 8459 ep->X_add_number = ex.X_add_number;
4d7206a2 8460 relax_switch ();
f5040a92 8461 }
67c0d1eb 8462 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 8463 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2
RS
8464 if (mips_relax.sequence)
8465 relax_end ();
ed6fb7bd
SC
8466 }
8467 else
8468 {
f5040a92
AO
8469 ex.X_add_number = ep->X_add_number;
8470 ep->X_add_number = 0;
67c0d1eb
RS
8471 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8472 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 8473 load_delay_nop ();
4d7206a2
RS
8474 relax_start (ep->X_add_symbol);
8475 relax_switch ();
67c0d1eb 8476 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 8477 BFD_RELOC_LO16);
4d7206a2 8478 relax_end ();
ed6fb7bd 8479
f5040a92
AO
8480 if (ex.X_add_number != 0)
8481 {
8482 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8483 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8484 ex.X_op = O_constant;
67c0d1eb 8485 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 8486 reg, reg, BFD_RELOC_LO16);
f5040a92 8487 }
252b5132
RH
8488 }
8489 }
0a44bf69 8490 else if (mips_big_got)
252b5132
RH
8491 {
8492 expressionS ex;
252b5132
RH
8493
8494 /* This is the large GOT case. If this is a reference to an
8495 external symbol, we want
8496 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8497 addu $reg,$reg,$gp
8498 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
f5040a92
AO
8499
8500 Otherwise, for a reference to a local symbol in old ABI, we want
252b5132
RH
8501 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8502 nop
8503 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
684022ea 8504 If there is a constant, it must be added in after.
f5040a92
AO
8505
8506 In the NewABI, for local symbols, with or without offsets, we want:
438c16b8
TS
8507 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8508 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 8509 */
438c16b8
TS
8510 if (HAVE_NEWABI)
8511 {
4d7206a2 8512 ex.X_add_number = ep->X_add_number;
f5040a92 8513 ep->X_add_number = 0;
4d7206a2 8514 relax_start (ep->X_add_symbol);
df58fc94 8515 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
8516 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8517 reg, reg, mips_gp_register);
8518 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8519 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
f5040a92
AO
8520 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8521 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8522 else if (ex.X_add_number)
8523 {
8524 ex.X_op = O_constant;
67c0d1eb
RS
8525 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8526 BFD_RELOC_LO16);
f5040a92
AO
8527 }
8528
8529 ep->X_add_number = ex.X_add_number;
4d7206a2 8530 relax_switch ();
67c0d1eb 8531 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 8532 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
67c0d1eb
RS
8533 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8534 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 8535 relax_end ();
438c16b8 8536 }
252b5132 8537 else
438c16b8 8538 {
f5040a92
AO
8539 ex.X_add_number = ep->X_add_number;
8540 ep->X_add_number = 0;
4d7206a2 8541 relax_start (ep->X_add_symbol);
df58fc94 8542 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
8543 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8544 reg, reg, mips_gp_register);
8545 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8546 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4d7206a2
RS
8547 relax_switch ();
8548 if (reg_needs_delay (mips_gp_register))
438c16b8
TS
8549 {
8550 /* We need a nop before loading from $gp. This special
8551 check is required because the lui which starts the main
8552 instruction stream does not refer to $gp, and so will not
8553 insert the nop which may be required. */
67c0d1eb 8554 macro_build (NULL, "nop", "");
438c16b8 8555 }
67c0d1eb 8556 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 8557 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 8558 load_delay_nop ();
67c0d1eb 8559 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 8560 BFD_RELOC_LO16);
4d7206a2 8561 relax_end ();
438c16b8 8562
f5040a92
AO
8563 if (ex.X_add_number != 0)
8564 {
8565 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8566 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8567 ex.X_op = O_constant;
67c0d1eb
RS
8568 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8569 BFD_RELOC_LO16);
f5040a92 8570 }
252b5132
RH
8571 }
8572 }
252b5132
RH
8573 else
8574 abort ();
8fc2e39e 8575
741fe287 8576 if (!mips_opts.at && *used_at == 1)
8fc2e39e 8577 as_bad (_("Macro used $at after \".set noat\""));
252b5132
RH
8578}
8579
ea1fb5dc
RS
8580/* Move the contents of register SOURCE into register DEST. */
8581
8582static void
67c0d1eb 8583move_register (int dest, int source)
ea1fb5dc 8584{
df58fc94
RS
8585 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8586 instruction specifically requires a 32-bit one. */
8587 if (mips_opts.micromips
833794fc 8588 && !mips_opts.insn32
df58fc94 8589 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7951ca42 8590 macro_build (NULL, "move", "mp,mj", dest, source);
df58fc94
RS
8591 else
8592 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
8593 dest, source, 0);
ea1fb5dc
RS
8594}
8595
4d7206a2 8596/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
f6a22291
MR
8597 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8598 The two alternatives are:
4d7206a2
RS
8599
8600 Global symbol Local sybmol
8601 ------------- ------------
8602 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8603 ... ...
8604 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8605
8606 load_got_offset emits the first instruction and add_got_offset
f6a22291
MR
8607 emits the second for a 16-bit offset or add_got_offset_hilo emits
8608 a sequence to add a 32-bit offset using a scratch register. */
4d7206a2
RS
8609
8610static void
67c0d1eb 8611load_got_offset (int dest, expressionS *local)
4d7206a2
RS
8612{
8613 expressionS global;
8614
8615 global = *local;
8616 global.X_add_number = 0;
8617
8618 relax_start (local->X_add_symbol);
67c0d1eb
RS
8619 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8620 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2 8621 relax_switch ();
67c0d1eb
RS
8622 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8623 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2
RS
8624 relax_end ();
8625}
8626
8627static void
67c0d1eb 8628add_got_offset (int dest, expressionS *local)
4d7206a2
RS
8629{
8630 expressionS global;
8631
8632 global.X_op = O_constant;
8633 global.X_op_symbol = NULL;
8634 global.X_add_symbol = NULL;
8635 global.X_add_number = local->X_add_number;
8636
8637 relax_start (local->X_add_symbol);
67c0d1eb 8638 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4d7206a2
RS
8639 dest, dest, BFD_RELOC_LO16);
8640 relax_switch ();
67c0d1eb 8641 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4d7206a2
RS
8642 relax_end ();
8643}
8644
f6a22291
MR
8645static void
8646add_got_offset_hilo (int dest, expressionS *local, int tmp)
8647{
8648 expressionS global;
8649 int hold_mips_optimize;
8650
8651 global.X_op = O_constant;
8652 global.X_op_symbol = NULL;
8653 global.X_add_symbol = NULL;
8654 global.X_add_number = local->X_add_number;
8655
8656 relax_start (local->X_add_symbol);
8657 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
8658 relax_switch ();
8659 /* Set mips_optimize around the lui instruction to avoid
8660 inserting an unnecessary nop after the lw. */
8661 hold_mips_optimize = mips_optimize;
8662 mips_optimize = 2;
8663 macro_build_lui (&global, tmp);
8664 mips_optimize = hold_mips_optimize;
8665 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
8666 relax_end ();
8667
8668 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
8669}
8670
df58fc94
RS
8671/* Emit a sequence of instructions to emulate a branch likely operation.
8672 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8673 is its complementing branch with the original condition negated.
8674 CALL is set if the original branch specified the link operation.
8675 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8676
8677 Code like this is produced in the noreorder mode:
8678
8679 BRNEG <args>, 1f
8680 nop
8681 b <sym>
8682 delay slot (executed only if branch taken)
8683 1:
8684
8685 or, if CALL is set:
8686
8687 BRNEG <args>, 1f
8688 nop
8689 bal <sym>
8690 delay slot (executed only if branch taken)
8691 1:
8692
8693 In the reorder mode the delay slot would be filled with a nop anyway,
8694 so code produced is simply:
8695
8696 BR <args>, <sym>
8697 nop
8698
8699 This function is used when producing code for the microMIPS ASE that
8700 does not implement branch likely instructions in hardware. */
8701
8702static void
8703macro_build_branch_likely (const char *br, const char *brneg,
8704 int call, expressionS *ep, const char *fmt,
8705 unsigned int sreg, unsigned int treg)
8706{
8707 int noreorder = mips_opts.noreorder;
8708 expressionS expr1;
8709
8710 gas_assert (mips_opts.micromips);
8711 start_noreorder ();
8712 if (noreorder)
8713 {
8714 micromips_label_expr (&expr1);
8715 macro_build (&expr1, brneg, fmt, sreg, treg);
8716 macro_build (NULL, "nop", "");
8717 macro_build (ep, call ? "bal" : "b", "p");
8718
8719 /* Set to true so that append_insn adds a label. */
8720 emit_branch_likely_macro = TRUE;
8721 }
8722 else
8723 {
8724 macro_build (ep, br, fmt, sreg, treg);
8725 macro_build (NULL, "nop", "");
8726 }
8727 end_noreorder ();
8728}
8729
8730/* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8731 the condition code tested. EP specifies the branch target. */
8732
8733static void
8734macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
8735{
8736 const int call = 0;
8737 const char *brneg;
8738 const char *br;
8739
8740 switch (type)
8741 {
8742 case M_BC1FL:
8743 br = "bc1f";
8744 brneg = "bc1t";
8745 break;
8746 case M_BC1TL:
8747 br = "bc1t";
8748 brneg = "bc1f";
8749 break;
8750 case M_BC2FL:
8751 br = "bc2f";
8752 brneg = "bc2t";
8753 break;
8754 case M_BC2TL:
8755 br = "bc2t";
8756 brneg = "bc2f";
8757 break;
8758 default:
8759 abort ();
8760 }
8761 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
8762}
8763
8764/* Emit a two-argument branch macro specified by TYPE, using SREG as
8765 the register tested. EP specifies the branch target. */
8766
8767static void
8768macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
8769{
8770 const char *brneg = NULL;
8771 const char *br;
8772 int call = 0;
8773
8774 switch (type)
8775 {
8776 case M_BGEZ:
8777 br = "bgez";
8778 break;
8779 case M_BGEZL:
8780 br = mips_opts.micromips ? "bgez" : "bgezl";
8781 brneg = "bltz";
8782 break;
8783 case M_BGEZALL:
8784 gas_assert (mips_opts.micromips);
833794fc 8785 br = mips_opts.insn32 ? "bgezal" : "bgezals";
df58fc94
RS
8786 brneg = "bltz";
8787 call = 1;
8788 break;
8789 case M_BGTZ:
8790 br = "bgtz";
8791 break;
8792 case M_BGTZL:
8793 br = mips_opts.micromips ? "bgtz" : "bgtzl";
8794 brneg = "blez";
8795 break;
8796 case M_BLEZ:
8797 br = "blez";
8798 break;
8799 case M_BLEZL:
8800 br = mips_opts.micromips ? "blez" : "blezl";
8801 brneg = "bgtz";
8802 break;
8803 case M_BLTZ:
8804 br = "bltz";
8805 break;
8806 case M_BLTZL:
8807 br = mips_opts.micromips ? "bltz" : "bltzl";
8808 brneg = "bgez";
8809 break;
8810 case M_BLTZALL:
8811 gas_assert (mips_opts.micromips);
833794fc 8812 br = mips_opts.insn32 ? "bltzal" : "bltzals";
df58fc94
RS
8813 brneg = "bgez";
8814 call = 1;
8815 break;
8816 default:
8817 abort ();
8818 }
8819 if (mips_opts.micromips && brneg)
8820 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
8821 else
8822 macro_build (ep, br, "s,p", sreg);
8823}
8824
8825/* Emit a three-argument branch macro specified by TYPE, using SREG and
8826 TREG as the registers tested. EP specifies the branch target. */
8827
8828static void
8829macro_build_branch_rsrt (int type, expressionS *ep,
8830 unsigned int sreg, unsigned int treg)
8831{
8832 const char *brneg = NULL;
8833 const int call = 0;
8834 const char *br;
8835
8836 switch (type)
8837 {
8838 case M_BEQ:
8839 case M_BEQ_I:
8840 br = "beq";
8841 break;
8842 case M_BEQL:
8843 case M_BEQL_I:
8844 br = mips_opts.micromips ? "beq" : "beql";
8845 brneg = "bne";
8846 break;
8847 case M_BNE:
8848 case M_BNE_I:
8849 br = "bne";
8850 break;
8851 case M_BNEL:
8852 case M_BNEL_I:
8853 br = mips_opts.micromips ? "bne" : "bnel";
8854 brneg = "beq";
8855 break;
8856 default:
8857 abort ();
8858 }
8859 if (mips_opts.micromips && brneg)
8860 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
8861 else
8862 macro_build (ep, br, "s,t,p", sreg, treg);
8863}
8864
f2ae14a1
RS
8865/* Return the high part that should be loaded in order to make the low
8866 part of VALUE accessible using an offset of OFFBITS bits. */
8867
8868static offsetT
8869offset_high_part (offsetT value, unsigned int offbits)
8870{
8871 offsetT bias;
8872 addressT low_mask;
8873
8874 if (offbits == 0)
8875 return value;
8876 bias = 1 << (offbits - 1);
8877 low_mask = bias * 2 - 1;
8878 return (value + bias) & ~low_mask;
8879}
8880
8881/* Return true if the value stored in offset_expr and offset_reloc
8882 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8883 amount that the caller wants to add without inducing overflow
8884 and ALIGN is the known alignment of the value in bytes. */
8885
8886static bfd_boolean
8887small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
8888{
8889 if (offbits == 16)
8890 {
8891 /* Accept any relocation operator if overflow isn't a concern. */
8892 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
8893 return TRUE;
8894
8895 /* These relocations are guaranteed not to overflow in correct links. */
8896 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
8897 || gprel16_reloc_p (*offset_reloc))
8898 return TRUE;
8899 }
8900 if (offset_expr.X_op == O_constant
8901 && offset_high_part (offset_expr.X_add_number, offbits) == 0
8902 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
8903 return TRUE;
8904 return FALSE;
8905}
8906
252b5132
RH
8907/*
8908 * Build macros
8909 * This routine implements the seemingly endless macro or synthesized
8910 * instructions and addressing modes in the mips assembly language. Many
8911 * of these macros are simple and are similar to each other. These could
67c1ffbe 8912 * probably be handled by some kind of table or grammar approach instead of
252b5132
RH
8913 * this verbose method. Others are not simple macros but are more like
8914 * optimizing code generation.
8915 * One interesting optimization is when several store macros appear
67c1ffbe 8916 * consecutively that would load AT with the upper half of the same address.
252b5132
RH
8917 * The ensuing load upper instructions are ommited. This implies some kind
8918 * of global optimization. We currently only optimize within a single macro.
8919 * For many of the load and store macros if the address is specified as a
8920 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8921 * first load register 'at' with zero and use it as the base register. The
8922 * mips assembler simply uses register $zero. Just one tiny optimization
8923 * we're missing.
8924 */
8925static void
833794fc 8926macro (struct mips_cl_insn *ip, char *str)
252b5132 8927{
c0ebe874
RS
8928 const struct mips_operand_array *operands;
8929 unsigned int breg, i;
741fe287 8930 unsigned int tempreg;
252b5132 8931 int mask;
43841e91 8932 int used_at = 0;
df58fc94 8933 expressionS label_expr;
252b5132 8934 expressionS expr1;
df58fc94 8935 expressionS *ep;
252b5132
RH
8936 const char *s;
8937 const char *s2;
8938 const char *fmt;
8939 int likely = 0;
252b5132 8940 int coproc = 0;
7f3c4072 8941 int offbits = 16;
1abe91b1 8942 int call = 0;
df58fc94
RS
8943 int jals = 0;
8944 int dbl = 0;
8945 int imm = 0;
8946 int ust = 0;
8947 int lp = 0;
f2ae14a1 8948 bfd_boolean large_offset;
252b5132 8949 int off;
252b5132 8950 int hold_mips_optimize;
f2ae14a1 8951 unsigned int align;
c0ebe874 8952 unsigned int op[MAX_OPERANDS];
252b5132 8953
9c2799c2 8954 gas_assert (! mips_opts.mips16);
252b5132 8955
c0ebe874
RS
8956 operands = insn_operands (ip);
8957 for (i = 0; i < MAX_OPERANDS; i++)
8958 if (operands->operand[i])
8959 op[i] = insn_extract_operand (ip, operands->operand[i]);
8960 else
8961 op[i] = -1;
8962
252b5132
RH
8963 mask = ip->insn_mo->mask;
8964
df58fc94
RS
8965 label_expr.X_op = O_constant;
8966 label_expr.X_op_symbol = NULL;
8967 label_expr.X_add_symbol = NULL;
8968 label_expr.X_add_number = 0;
8969
252b5132
RH
8970 expr1.X_op = O_constant;
8971 expr1.X_op_symbol = NULL;
8972 expr1.X_add_symbol = NULL;
8973 expr1.X_add_number = 1;
f2ae14a1 8974 align = 1;
252b5132
RH
8975
8976 switch (mask)
8977 {
8978 case M_DABS:
8979 dbl = 1;
8980 case M_ABS:
df58fc94
RS
8981 /* bgez $a0,1f
8982 move v0,$a0
8983 sub v0,$zero,$a0
8984 1:
8985 */
252b5132 8986
7d10b47d 8987 start_noreorder ();
252b5132 8988
df58fc94
RS
8989 if (mips_opts.micromips)
8990 micromips_label_expr (&label_expr);
8991 else
8992 label_expr.X_add_number = 8;
c0ebe874
RS
8993 macro_build (&label_expr, "bgez", "s,p", op[1]);
8994 if (op[0] == op[1])
a605d2b3 8995 macro_build (NULL, "nop", "");
252b5132 8996 else
c0ebe874
RS
8997 move_register (op[0], op[1]);
8998 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
df58fc94
RS
8999 if (mips_opts.micromips)
9000 micromips_add_label ();
252b5132 9001
7d10b47d 9002 end_noreorder ();
8fc2e39e 9003 break;
252b5132
RH
9004
9005 case M_ADD_I:
9006 s = "addi";
9007 s2 = "add";
9008 goto do_addi;
9009 case M_ADDU_I:
9010 s = "addiu";
9011 s2 = "addu";
9012 goto do_addi;
9013 case M_DADD_I:
9014 dbl = 1;
9015 s = "daddi";
9016 s2 = "dadd";
df58fc94
RS
9017 if (!mips_opts.micromips)
9018 goto do_addi;
9019 if (imm_expr.X_op == O_constant
9020 && imm_expr.X_add_number >= -0x200
9021 && imm_expr.X_add_number < 0x200)
9022 {
c0ebe874 9023 macro_build (NULL, s, "t,r,.", op[0], op[1], imm_expr.X_add_number);
df58fc94
RS
9024 break;
9025 }
9026 goto do_addi_i;
252b5132
RH
9027 case M_DADDU_I:
9028 dbl = 1;
9029 s = "daddiu";
9030 s2 = "daddu";
9031 do_addi:
9032 if (imm_expr.X_op == O_constant
9033 && imm_expr.X_add_number >= -0x8000
9034 && imm_expr.X_add_number < 0x8000)
9035 {
c0ebe874 9036 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 9037 break;
252b5132 9038 }
df58fc94 9039 do_addi_i:
8fc2e39e 9040 used_at = 1;
67c0d1eb 9041 load_register (AT, &imm_expr, dbl);
c0ebe874 9042 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
9043 break;
9044
9045 case M_AND_I:
9046 s = "andi";
9047 s2 = "and";
9048 goto do_bit;
9049 case M_OR_I:
9050 s = "ori";
9051 s2 = "or";
9052 goto do_bit;
9053 case M_NOR_I:
9054 s = "";
9055 s2 = "nor";
9056 goto do_bit;
9057 case M_XOR_I:
9058 s = "xori";
9059 s2 = "xor";
9060 do_bit:
9061 if (imm_expr.X_op == O_constant
9062 && imm_expr.X_add_number >= 0
9063 && imm_expr.X_add_number < 0x10000)
9064 {
9065 if (mask != M_NOR_I)
c0ebe874 9066 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
9067 else
9068 {
67c0d1eb 9069 macro_build (&imm_expr, "ori", "t,r,i",
c0ebe874
RS
9070 op[0], op[1], BFD_RELOC_LO16);
9071 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
252b5132 9072 }
8fc2e39e 9073 break;
252b5132
RH
9074 }
9075
8fc2e39e 9076 used_at = 1;
67c0d1eb 9077 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 9078 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
9079 break;
9080
8b082fb1
TS
9081 case M_BALIGN:
9082 switch (imm_expr.X_add_number)
9083 {
9084 case 0:
9085 macro_build (NULL, "nop", "");
9086 break;
9087 case 2:
c0ebe874 9088 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
8b082fb1 9089 break;
03f66e8a
MR
9090 case 1:
9091 case 3:
c0ebe874 9092 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
90ecf173 9093 (int) imm_expr.X_add_number);
8b082fb1 9094 break;
03f66e8a
MR
9095 default:
9096 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9097 (unsigned long) imm_expr.X_add_number);
9098 break;
8b082fb1
TS
9099 }
9100 break;
9101
df58fc94
RS
9102 case M_BC1FL:
9103 case M_BC1TL:
9104 case M_BC2FL:
9105 case M_BC2TL:
9106 gas_assert (mips_opts.micromips);
9107 macro_build_branch_ccl (mask, &offset_expr,
9108 EXTRACT_OPERAND (1, BCC, *ip));
9109 break;
9110
252b5132 9111 case M_BEQ_I:
252b5132 9112 case M_BEQL_I:
252b5132 9113 case M_BNE_I:
252b5132 9114 case M_BNEL_I:
252b5132 9115 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
c0ebe874 9116 op[1] = 0;
df58fc94 9117 else
252b5132 9118 {
c0ebe874 9119 op[1] = AT;
df58fc94 9120 used_at = 1;
c0ebe874 9121 load_register (op[1], &imm_expr, HAVE_64BIT_GPRS);
252b5132 9122 }
df58fc94
RS
9123 /* Fall through. */
9124 case M_BEQL:
9125 case M_BNEL:
c0ebe874 9126 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
252b5132
RH
9127 break;
9128
9129 case M_BGEL:
9130 likely = 1;
9131 case M_BGE:
c0ebe874
RS
9132 if (op[1] == 0)
9133 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9134 else if (op[0] == 0)
9135 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
df58fc94 9136 else
252b5132 9137 {
df58fc94 9138 used_at = 1;
c0ebe874 9139 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9140 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9141 &offset_expr, AT, ZERO);
252b5132 9142 }
df58fc94
RS
9143 break;
9144
9145 case M_BGEZL:
9146 case M_BGEZALL:
9147 case M_BGTZL:
9148 case M_BLEZL:
9149 case M_BLTZL:
9150 case M_BLTZALL:
c0ebe874 9151 macro_build_branch_rs (mask, &offset_expr, op[0]);
252b5132
RH
9152 break;
9153
9154 case M_BGTL_I:
9155 likely = 1;
9156 case M_BGT_I:
90ecf173 9157 /* Check for > max integer. */
42429eac 9158 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
252b5132
RH
9159 {
9160 do_false:
90ecf173 9161 /* Result is always false. */
252b5132 9162 if (! likely)
a605d2b3 9163 macro_build (NULL, "nop", "");
252b5132 9164 else
df58fc94 9165 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8fc2e39e 9166 break;
252b5132
RH
9167 }
9168 if (imm_expr.X_op != O_constant)
9169 as_bad (_("Unsupported large constant"));
f9419b05 9170 ++imm_expr.X_add_number;
252b5132
RH
9171 /* FALLTHROUGH */
9172 case M_BGE_I:
9173 case M_BGEL_I:
9174 if (mask == M_BGEL_I)
9175 likely = 1;
9176 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9177 {
df58fc94 9178 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
c0ebe874 9179 &offset_expr, op[0]);
8fc2e39e 9180 break;
252b5132
RH
9181 }
9182 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9183 {
df58fc94 9184 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
c0ebe874 9185 &offset_expr, op[0]);
8fc2e39e 9186 break;
252b5132 9187 }
42429eac 9188 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
252b5132
RH
9189 {
9190 do_true:
9191 /* result is always true */
9192 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
67c0d1eb 9193 macro_build (&offset_expr, "b", "p");
8fc2e39e 9194 break;
252b5132 9195 }
8fc2e39e 9196 used_at = 1;
c0ebe874 9197 set_at (op[0], 0);
df58fc94
RS
9198 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9199 &offset_expr, AT, ZERO);
252b5132
RH
9200 break;
9201
9202 case M_BGEUL:
9203 likely = 1;
9204 case M_BGEU:
c0ebe874 9205 if (op[1] == 0)
252b5132 9206 goto do_true;
c0ebe874 9207 else if (op[0] == 0)
df58fc94 9208 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874 9209 &offset_expr, ZERO, op[1]);
df58fc94 9210 else
252b5132 9211 {
df58fc94 9212 used_at = 1;
c0ebe874 9213 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9214 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9215 &offset_expr, AT, ZERO);
252b5132 9216 }
252b5132
RH
9217 break;
9218
9219 case M_BGTUL_I:
9220 likely = 1;
9221 case M_BGTU_I:
c0ebe874 9222 if (op[0] == 0
ca4e0257 9223 || (HAVE_32BIT_GPRS
252b5132 9224 && imm_expr.X_op == O_constant
f01dc953 9225 && imm_expr.X_add_number == -1))
252b5132
RH
9226 goto do_false;
9227 if (imm_expr.X_op != O_constant)
9228 as_bad (_("Unsupported large constant"));
f9419b05 9229 ++imm_expr.X_add_number;
252b5132
RH
9230 /* FALLTHROUGH */
9231 case M_BGEU_I:
9232 case M_BGEUL_I:
9233 if (mask == M_BGEUL_I)
9234 likely = 1;
9235 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9236 goto do_true;
df58fc94
RS
9237 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9238 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874 9239 &offset_expr, op[0], ZERO);
df58fc94 9240 else
252b5132 9241 {
df58fc94 9242 used_at = 1;
c0ebe874 9243 set_at (op[0], 1);
df58fc94
RS
9244 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9245 &offset_expr, AT, ZERO);
252b5132 9246 }
252b5132
RH
9247 break;
9248
9249 case M_BGTL:
9250 likely = 1;
9251 case M_BGT:
c0ebe874
RS
9252 if (op[1] == 0)
9253 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9254 else if (op[0] == 0)
9255 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
df58fc94 9256 else
252b5132 9257 {
df58fc94 9258 used_at = 1;
c0ebe874 9259 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
9260 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9261 &offset_expr, AT, ZERO);
252b5132 9262 }
252b5132
RH
9263 break;
9264
9265 case M_BGTUL:
9266 likely = 1;
9267 case M_BGTU:
c0ebe874 9268 if (op[1] == 0)
df58fc94 9269 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874
RS
9270 &offset_expr, op[0], ZERO);
9271 else if (op[0] == 0)
df58fc94
RS
9272 goto do_false;
9273 else
252b5132 9274 {
df58fc94 9275 used_at = 1;
c0ebe874 9276 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
9277 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9278 &offset_expr, AT, ZERO);
252b5132 9279 }
252b5132
RH
9280 break;
9281
9282 case M_BLEL:
9283 likely = 1;
9284 case M_BLE:
c0ebe874
RS
9285 if (op[1] == 0)
9286 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9287 else if (op[0] == 0)
9288 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
df58fc94 9289 else
252b5132 9290 {
df58fc94 9291 used_at = 1;
c0ebe874 9292 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
9293 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9294 &offset_expr, AT, ZERO);
252b5132 9295 }
252b5132
RH
9296 break;
9297
9298 case M_BLEL_I:
9299 likely = 1;
9300 case M_BLE_I:
42429eac 9301 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
252b5132
RH
9302 goto do_true;
9303 if (imm_expr.X_op != O_constant)
9304 as_bad (_("Unsupported large constant"));
f9419b05 9305 ++imm_expr.X_add_number;
252b5132
RH
9306 /* FALLTHROUGH */
9307 case M_BLT_I:
9308 case M_BLTL_I:
9309 if (mask == M_BLTL_I)
9310 likely = 1;
9311 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
c0ebe874 9312 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
df58fc94 9313 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
c0ebe874 9314 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
df58fc94 9315 else
252b5132 9316 {
df58fc94 9317 used_at = 1;
c0ebe874 9318 set_at (op[0], 0);
df58fc94
RS
9319 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9320 &offset_expr, AT, ZERO);
252b5132 9321 }
252b5132
RH
9322 break;
9323
9324 case M_BLEUL:
9325 likely = 1;
9326 case M_BLEU:
c0ebe874 9327 if (op[1] == 0)
df58fc94 9328 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874
RS
9329 &offset_expr, op[0], ZERO);
9330 else if (op[0] == 0)
df58fc94
RS
9331 goto do_true;
9332 else
252b5132 9333 {
df58fc94 9334 used_at = 1;
c0ebe874 9335 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
9336 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9337 &offset_expr, AT, ZERO);
252b5132 9338 }
252b5132
RH
9339 break;
9340
9341 case M_BLEUL_I:
9342 likely = 1;
9343 case M_BLEU_I:
c0ebe874 9344 if (op[0] == 0
ca4e0257 9345 || (HAVE_32BIT_GPRS
252b5132 9346 && imm_expr.X_op == O_constant
f01dc953 9347 && imm_expr.X_add_number == -1))
252b5132
RH
9348 goto do_true;
9349 if (imm_expr.X_op != O_constant)
9350 as_bad (_("Unsupported large constant"));
f9419b05 9351 ++imm_expr.X_add_number;
252b5132
RH
9352 /* FALLTHROUGH */
9353 case M_BLTU_I:
9354 case M_BLTUL_I:
9355 if (mask == M_BLTUL_I)
9356 likely = 1;
9357 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9358 goto do_false;
df58fc94
RS
9359 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9360 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874 9361 &offset_expr, op[0], ZERO);
df58fc94 9362 else
252b5132 9363 {
df58fc94 9364 used_at = 1;
c0ebe874 9365 set_at (op[0], 1);
df58fc94
RS
9366 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9367 &offset_expr, AT, ZERO);
252b5132 9368 }
252b5132
RH
9369 break;
9370
9371 case M_BLTL:
9372 likely = 1;
9373 case M_BLT:
c0ebe874
RS
9374 if (op[1] == 0)
9375 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9376 else if (op[0] == 0)
9377 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
df58fc94 9378 else
252b5132 9379 {
df58fc94 9380 used_at = 1;
c0ebe874 9381 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9382 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9383 &offset_expr, AT, ZERO);
252b5132 9384 }
252b5132
RH
9385 break;
9386
9387 case M_BLTUL:
9388 likely = 1;
9389 case M_BLTU:
c0ebe874 9390 if (op[1] == 0)
252b5132 9391 goto do_false;
c0ebe874 9392 else if (op[0] == 0)
df58fc94 9393 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874 9394 &offset_expr, ZERO, op[1]);
df58fc94 9395 else
252b5132 9396 {
df58fc94 9397 used_at = 1;
c0ebe874 9398 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
9399 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9400 &offset_expr, AT, ZERO);
252b5132 9401 }
252b5132
RH
9402 break;
9403
5f74bc13
CD
9404 case M_DEXT:
9405 {
d5818fca
MR
9406 /* Use unsigned arithmetic. */
9407 addressT pos;
9408 addressT size;
5f74bc13 9409
90ecf173 9410 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5f74bc13
CD
9411 {
9412 as_bad (_("Unsupported large constant"));
9413 pos = size = 1;
9414 }
9415 else
9416 {
d5818fca
MR
9417 pos = imm_expr.X_add_number;
9418 size = imm2_expr.X_add_number;
5f74bc13
CD
9419 }
9420
9421 if (pos > 63)
9422 {
9e12b7a2 9423 report_bad_range (ip, 3, pos, 0, 63, FALSE);
5f74bc13
CD
9424 pos = 1;
9425 }
90ecf173 9426 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5f74bc13 9427 {
9e12b7a2 9428 report_bad_field (pos, size);
5f74bc13
CD
9429 size = 1;
9430 }
9431
9432 if (size <= 32 && pos < 32)
9433 {
9434 s = "dext";
9435 fmt = "t,r,+A,+C";
9436 }
9437 else if (size <= 32)
9438 {
9439 s = "dextu";
9440 fmt = "t,r,+E,+H";
9441 }
9442 else
9443 {
9444 s = "dextm";
9445 fmt = "t,r,+A,+G";
9446 }
c0ebe874 9447 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
d5818fca 9448 (int) (size - 1));
5f74bc13 9449 }
8fc2e39e 9450 break;
5f74bc13
CD
9451
9452 case M_DINS:
9453 {
d5818fca
MR
9454 /* Use unsigned arithmetic. */
9455 addressT pos;
9456 addressT size;
5f74bc13 9457
90ecf173 9458 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5f74bc13
CD
9459 {
9460 as_bad (_("Unsupported large constant"));
9461 pos = size = 1;
9462 }
9463 else
9464 {
d5818fca
MR
9465 pos = imm_expr.X_add_number;
9466 size = imm2_expr.X_add_number;
5f74bc13
CD
9467 }
9468
9469 if (pos > 63)
9470 {
9e12b7a2 9471 report_bad_range (ip, 3, pos, 0, 63, FALSE);
5f74bc13
CD
9472 pos = 1;
9473 }
90ecf173 9474 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5f74bc13 9475 {
9e12b7a2 9476 report_bad_field (pos, size);
5f74bc13
CD
9477 size = 1;
9478 }
9479
9480 if (pos < 32 && (pos + size - 1) < 32)
9481 {
9482 s = "dins";
9483 fmt = "t,r,+A,+B";
9484 }
9485 else if (pos >= 32)
9486 {
9487 s = "dinsu";
9488 fmt = "t,r,+E,+F";
9489 }
9490 else
9491 {
9492 s = "dinsm";
9493 fmt = "t,r,+A,+F";
9494 }
c0ebe874 9495 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
750bdd57 9496 (int) (pos + size - 1));
5f74bc13 9497 }
8fc2e39e 9498 break;
5f74bc13 9499
252b5132
RH
9500 case M_DDIV_3:
9501 dbl = 1;
9502 case M_DIV_3:
9503 s = "mflo";
9504 goto do_div3;
9505 case M_DREM_3:
9506 dbl = 1;
9507 case M_REM_3:
9508 s = "mfhi";
9509 do_div3:
c0ebe874 9510 if (op[2] == 0)
252b5132
RH
9511 {
9512 as_warn (_("Divide by zero."));
9513 if (mips_trap)
df58fc94 9514 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 9515 else
df58fc94 9516 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 9517 break;
252b5132
RH
9518 }
9519
7d10b47d 9520 start_noreorder ();
252b5132
RH
9521 if (mips_trap)
9522 {
c0ebe874
RS
9523 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9524 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
252b5132
RH
9525 }
9526 else
9527 {
df58fc94
RS
9528 if (mips_opts.micromips)
9529 micromips_label_expr (&label_expr);
9530 else
9531 label_expr.X_add_number = 8;
c0ebe874
RS
9532 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9533 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
df58fc94
RS
9534 macro_build (NULL, "break", BRK_FMT, 7);
9535 if (mips_opts.micromips)
9536 micromips_add_label ();
252b5132
RH
9537 }
9538 expr1.X_add_number = -1;
8fc2e39e 9539 used_at = 1;
f6a22291 9540 load_register (AT, &expr1, dbl);
df58fc94
RS
9541 if (mips_opts.micromips)
9542 micromips_label_expr (&label_expr);
9543 else
9544 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
c0ebe874 9545 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
252b5132
RH
9546 if (dbl)
9547 {
9548 expr1.X_add_number = 1;
f6a22291 9549 load_register (AT, &expr1, dbl);
df58fc94 9550 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
252b5132
RH
9551 }
9552 else
9553 {
9554 expr1.X_add_number = 0x80000000;
df58fc94 9555 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
252b5132
RH
9556 }
9557 if (mips_trap)
9558 {
c0ebe874 9559 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
252b5132
RH
9560 /* We want to close the noreorder block as soon as possible, so
9561 that later insns are available for delay slot filling. */
7d10b47d 9562 end_noreorder ();
252b5132
RH
9563 }
9564 else
9565 {
df58fc94
RS
9566 if (mips_opts.micromips)
9567 micromips_label_expr (&label_expr);
9568 else
9569 label_expr.X_add_number = 8;
c0ebe874 9570 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
a605d2b3 9571 macro_build (NULL, "nop", "");
252b5132
RH
9572
9573 /* We want to close the noreorder block as soon as possible, so
9574 that later insns are available for delay slot filling. */
7d10b47d 9575 end_noreorder ();
252b5132 9576
df58fc94 9577 macro_build (NULL, "break", BRK_FMT, 6);
252b5132 9578 }
df58fc94
RS
9579 if (mips_opts.micromips)
9580 micromips_add_label ();
c0ebe874 9581 macro_build (NULL, s, MFHL_FMT, op[0]);
252b5132
RH
9582 break;
9583
9584 case M_DIV_3I:
9585 s = "div";
9586 s2 = "mflo";
9587 goto do_divi;
9588 case M_DIVU_3I:
9589 s = "divu";
9590 s2 = "mflo";
9591 goto do_divi;
9592 case M_REM_3I:
9593 s = "div";
9594 s2 = "mfhi";
9595 goto do_divi;
9596 case M_REMU_3I:
9597 s = "divu";
9598 s2 = "mfhi";
9599 goto do_divi;
9600 case M_DDIV_3I:
9601 dbl = 1;
9602 s = "ddiv";
9603 s2 = "mflo";
9604 goto do_divi;
9605 case M_DDIVU_3I:
9606 dbl = 1;
9607 s = "ddivu";
9608 s2 = "mflo";
9609 goto do_divi;
9610 case M_DREM_3I:
9611 dbl = 1;
9612 s = "ddiv";
9613 s2 = "mfhi";
9614 goto do_divi;
9615 case M_DREMU_3I:
9616 dbl = 1;
9617 s = "ddivu";
9618 s2 = "mfhi";
9619 do_divi:
9620 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9621 {
9622 as_warn (_("Divide by zero."));
9623 if (mips_trap)
df58fc94 9624 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 9625 else
df58fc94 9626 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 9627 break;
252b5132
RH
9628 }
9629 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9630 {
9631 if (strcmp (s2, "mflo") == 0)
c0ebe874 9632 move_register (op[0], op[1]);
252b5132 9633 else
c0ebe874 9634 move_register (op[0], ZERO);
8fc2e39e 9635 break;
252b5132
RH
9636 }
9637 if (imm_expr.X_op == O_constant
9638 && imm_expr.X_add_number == -1
9639 && s[strlen (s) - 1] != 'u')
9640 {
9641 if (strcmp (s2, "mflo") == 0)
c0ebe874 9642 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
252b5132 9643 else
c0ebe874 9644 move_register (op[0], ZERO);
8fc2e39e 9645 break;
252b5132
RH
9646 }
9647
8fc2e39e 9648 used_at = 1;
67c0d1eb 9649 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
9650 macro_build (NULL, s, "z,s,t", op[1], AT);
9651 macro_build (NULL, s2, MFHL_FMT, op[0]);
252b5132
RH
9652 break;
9653
9654 case M_DIVU_3:
9655 s = "divu";
9656 s2 = "mflo";
9657 goto do_divu3;
9658 case M_REMU_3:
9659 s = "divu";
9660 s2 = "mfhi";
9661 goto do_divu3;
9662 case M_DDIVU_3:
9663 s = "ddivu";
9664 s2 = "mflo";
9665 goto do_divu3;
9666 case M_DREMU_3:
9667 s = "ddivu";
9668 s2 = "mfhi";
9669 do_divu3:
7d10b47d 9670 start_noreorder ();
252b5132
RH
9671 if (mips_trap)
9672 {
c0ebe874
RS
9673 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9674 macro_build (NULL, s, "z,s,t", op[1], op[2]);
252b5132
RH
9675 /* We want to close the noreorder block as soon as possible, so
9676 that later insns are available for delay slot filling. */
7d10b47d 9677 end_noreorder ();
252b5132
RH
9678 }
9679 else
9680 {
df58fc94
RS
9681 if (mips_opts.micromips)
9682 micromips_label_expr (&label_expr);
9683 else
9684 label_expr.X_add_number = 8;
c0ebe874
RS
9685 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9686 macro_build (NULL, s, "z,s,t", op[1], op[2]);
252b5132
RH
9687
9688 /* We want to close the noreorder block as soon as possible, so
9689 that later insns are available for delay slot filling. */
7d10b47d 9690 end_noreorder ();
df58fc94
RS
9691 macro_build (NULL, "break", BRK_FMT, 7);
9692 if (mips_opts.micromips)
9693 micromips_add_label ();
252b5132 9694 }
c0ebe874 9695 macro_build (NULL, s2, MFHL_FMT, op[0]);
8fc2e39e 9696 break;
252b5132 9697
1abe91b1
MR
9698 case M_DLCA_AB:
9699 dbl = 1;
9700 case M_LCA_AB:
9701 call = 1;
9702 goto do_la;
252b5132
RH
9703 case M_DLA_AB:
9704 dbl = 1;
9705 case M_LA_AB:
1abe91b1 9706 do_la:
252b5132
RH
9707 /* Load the address of a symbol into a register. If breg is not
9708 zero, we then add a base register to it. */
9709
c0ebe874 9710 breg = op[2];
3bec30a8
TS
9711 if (dbl && HAVE_32BIT_GPRS)
9712 as_warn (_("dla used to load 32-bit register"));
9713
90ecf173 9714 if (!dbl && HAVE_64BIT_OBJECTS)
3bec30a8
TS
9715 as_warn (_("la used to load 64-bit address"));
9716
f2ae14a1 9717 if (small_offset_p (0, align, 16))
0c11417f 9718 {
c0ebe874 9719 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
f2ae14a1 9720 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8fc2e39e 9721 break;
0c11417f
MR
9722 }
9723
c0ebe874 9724 if (mips_opts.at && (op[0] == breg))
afdbd6d0
CD
9725 {
9726 tempreg = AT;
9727 used_at = 1;
9728 }
9729 else
c0ebe874 9730 tempreg = op[0];
afdbd6d0 9731
252b5132
RH
9732 if (offset_expr.X_op != O_symbol
9733 && offset_expr.X_op != O_constant)
9734 {
f71d0d44 9735 as_bad (_("Expression too complex"));
252b5132
RH
9736 offset_expr.X_op = O_constant;
9737 }
9738
252b5132 9739 if (offset_expr.X_op == O_constant)
aed1a261 9740 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
252b5132
RH
9741 else if (mips_pic == NO_PIC)
9742 {
d6bc6245 9743 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 9744 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
9745 Otherwise we want
9746 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9747 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9748 If we have a constant, we need two instructions anyhow,
d6bc6245 9749 so we may as well always use the latter form.
76b3015f 9750
6caf9ef4
TS
9751 With 64bit address space and a usable $at we want
9752 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9753 lui $at,<sym> (BFD_RELOC_HI16_S)
9754 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9755 daddiu $at,<sym> (BFD_RELOC_LO16)
9756 dsll32 $tempreg,0
9757 daddu $tempreg,$tempreg,$at
9758
9759 If $at is already in use, we use a path which is suboptimal
9760 on superscalar processors.
9761 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9762 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9763 dsll $tempreg,16
9764 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9765 dsll $tempreg,16
9766 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9767
9768 For GP relative symbols in 64bit address space we can use
9769 the same sequence as in 32bit address space. */
aed1a261 9770 if (HAVE_64BIT_SYMBOLS)
252b5132 9771 {
6caf9ef4
TS
9772 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9773 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9774 {
9775 relax_start (offset_expr.X_add_symbol);
9776 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9777 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9778 relax_switch ();
9779 }
d6bc6245 9780
741fe287 9781 if (used_at == 0 && mips_opts.at)
98d3f06f 9782 {
df58fc94 9783 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 9784 tempreg, BFD_RELOC_MIPS_HIGHEST);
df58fc94 9785 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 9786 AT, BFD_RELOC_HI16_S);
67c0d1eb 9787 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9788 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
67c0d1eb 9789 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9790 AT, AT, BFD_RELOC_LO16);
df58fc94 9791 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 9792 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
98d3f06f
KH
9793 used_at = 1;
9794 }
9795 else
9796 {
df58fc94 9797 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 9798 tempreg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb 9799 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9800 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 9801 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 9802 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9803 tempreg, tempreg, BFD_RELOC_HI16_S);
df58fc94 9804 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 9805 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 9806 tempreg, tempreg, BFD_RELOC_LO16);
98d3f06f 9807 }
6caf9ef4
TS
9808
9809 if (mips_relax.sequence)
9810 relax_end ();
98d3f06f
KH
9811 }
9812 else
9813 {
9814 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 9815 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
98d3f06f 9816 {
4d7206a2 9817 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9818 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9819 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 9820 relax_switch ();
98d3f06f 9821 }
6943caf0 9822 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
f71d0d44 9823 as_bad (_("Offset too large"));
67c0d1eb
RS
9824 macro_build_lui (&offset_expr, tempreg);
9825 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9826 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2
RS
9827 if (mips_relax.sequence)
9828 relax_end ();
98d3f06f 9829 }
252b5132 9830 }
0a44bf69 9831 else if (!mips_big_got && !HAVE_NEWABI)
252b5132 9832 {
9117d219
NC
9833 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9834
252b5132
RH
9835 /* If this is a reference to an external symbol, and there
9836 is no constant, we want
9837 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1abe91b1 9838 or for lca or if tempreg is PIC_CALL_REG
9117d219 9839 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
252b5132
RH
9840 For a local symbol, we want
9841 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9842 nop
9843 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9844
9845 If we have a small constant, and this is a reference to
9846 an external symbol, we want
9847 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9848 nop
9849 addiu $tempreg,$tempreg,<constant>
9850 For a local symbol, we want the same instruction
9851 sequence, but we output a BFD_RELOC_LO16 reloc on the
9852 addiu instruction.
9853
9854 If we have a large constant, and this is a reference to
9855 an external symbol, we want
9856 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9857 lui $at,<hiconstant>
9858 addiu $at,$at,<loconstant>
9859 addu $tempreg,$tempreg,$at
9860 For a local symbol, we want the same instruction
9861 sequence, but we output a BFD_RELOC_LO16 reloc on the
ed6fb7bd 9862 addiu instruction.
ed6fb7bd
SC
9863 */
9864
4d7206a2 9865 if (offset_expr.X_add_number == 0)
252b5132 9866 {
0a44bf69
RS
9867 if (mips_pic == SVR4_PIC
9868 && breg == 0
9869 && (call || tempreg == PIC_CALL_REG))
4d7206a2
RS
9870 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
9871
9872 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9873 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9874 lw_reloc_type, mips_gp_register);
4d7206a2 9875 if (breg != 0)
252b5132
RH
9876 {
9877 /* We're going to put in an addu instruction using
9878 tempreg, so we may as well insert the nop right
9879 now. */
269137b2 9880 load_delay_nop ();
252b5132 9881 }
4d7206a2 9882 relax_switch ();
67c0d1eb
RS
9883 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9884 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 9885 load_delay_nop ();
67c0d1eb
RS
9886 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9887 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2 9888 relax_end ();
252b5132
RH
9889 /* FIXME: If breg == 0, and the next instruction uses
9890 $tempreg, then if this variant case is used an extra
9891 nop will be generated. */
9892 }
4d7206a2
RS
9893 else if (offset_expr.X_add_number >= -0x8000
9894 && offset_expr.X_add_number < 0x8000)
252b5132 9895 {
67c0d1eb 9896 load_got_offset (tempreg, &offset_expr);
269137b2 9897 load_delay_nop ();
67c0d1eb 9898 add_got_offset (tempreg, &offset_expr);
252b5132
RH
9899 }
9900 else
9901 {
4d7206a2
RS
9902 expr1.X_add_number = offset_expr.X_add_number;
9903 offset_expr.X_add_number =
43c0598f 9904 SEXT_16BIT (offset_expr.X_add_number);
67c0d1eb 9905 load_got_offset (tempreg, &offset_expr);
f6a22291 9906 offset_expr.X_add_number = expr1.X_add_number;
252b5132
RH
9907 /* If we are going to add in a base register, and the
9908 target register and the base register are the same,
9909 then we are using AT as a temporary register. Since
9910 we want to load the constant into AT, we add our
9911 current AT (from the global offset table) and the
9912 register into the register now, and pretend we were
9913 not using a base register. */
c0ebe874 9914 if (breg == op[0])
252b5132 9915 {
269137b2 9916 load_delay_nop ();
67c0d1eb 9917 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 9918 op[0], AT, breg);
252b5132 9919 breg = 0;
c0ebe874 9920 tempreg = op[0];
252b5132 9921 }
f6a22291 9922 add_got_offset_hilo (tempreg, &offset_expr, AT);
252b5132
RH
9923 used_at = 1;
9924 }
9925 }
0a44bf69 9926 else if (!mips_big_got && HAVE_NEWABI)
f5040a92 9927 {
67c0d1eb 9928 int add_breg_early = 0;
f5040a92
AO
9929
9930 /* If this is a reference to an external, and there is no
9931 constant, or local symbol (*), with or without a
9932 constant, we want
9933 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
1abe91b1 9934 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
9935 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9936
9937 If we have a small constant, and this is a reference to
9938 an external symbol, we want
9939 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9940 addiu $tempreg,$tempreg,<constant>
9941
9942 If we have a large constant, and this is a reference to
9943 an external symbol, we want
9944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9945 lui $at,<hiconstant>
9946 addiu $at,$at,<loconstant>
9947 addu $tempreg,$tempreg,$at
9948
9949 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9950 local symbols, even though it introduces an additional
9951 instruction. */
9952
f5040a92
AO
9953 if (offset_expr.X_add_number)
9954 {
4d7206a2 9955 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
9956 offset_expr.X_add_number = 0;
9957
4d7206a2 9958 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
9959 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9960 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
9961
9962 if (expr1.X_add_number >= -0x8000
9963 && expr1.X_add_number < 0x8000)
9964 {
67c0d1eb
RS
9965 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9966 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 9967 }
ecd13cd3 9968 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 9969 {
c0ebe874
RS
9970 unsigned int dreg;
9971
f5040a92
AO
9972 /* If we are going to add in a base register, and the
9973 target register and the base register are the same,
9974 then we are using AT as a temporary register. Since
9975 we want to load the constant into AT, we add our
9976 current AT (from the global offset table) and the
9977 register into the register now, and pretend we were
9978 not using a base register. */
c0ebe874 9979 if (breg != op[0])
f5040a92
AO
9980 dreg = tempreg;
9981 else
9982 {
9c2799c2 9983 gas_assert (tempreg == AT);
67c0d1eb 9984 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
9985 op[0], AT, breg);
9986 dreg = op[0];
67c0d1eb 9987 add_breg_early = 1;
f5040a92
AO
9988 }
9989
f6a22291 9990 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 9991 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 9992 dreg, dreg, AT);
f5040a92 9993
f5040a92
AO
9994 used_at = 1;
9995 }
9996 else
9997 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9998
4d7206a2 9999 relax_switch ();
f5040a92
AO
10000 offset_expr.X_add_number = expr1.X_add_number;
10001
67c0d1eb
RS
10002 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10003 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10004 if (add_breg_early)
f5040a92 10005 {
67c0d1eb 10006 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 10007 op[0], tempreg, breg);
f5040a92 10008 breg = 0;
c0ebe874 10009 tempreg = op[0];
f5040a92 10010 }
4d7206a2 10011 relax_end ();
f5040a92 10012 }
4d7206a2 10013 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
f5040a92 10014 {
4d7206a2 10015 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10016 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10017 BFD_RELOC_MIPS_CALL16, mips_gp_register);
4d7206a2 10018 relax_switch ();
67c0d1eb
RS
10019 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10020 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2 10021 relax_end ();
f5040a92 10022 }
4d7206a2 10023 else
f5040a92 10024 {
67c0d1eb
RS
10025 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10026 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
10027 }
10028 }
0a44bf69 10029 else if (mips_big_got && !HAVE_NEWABI)
252b5132 10030 {
67c0d1eb 10031 int gpdelay;
9117d219
NC
10032 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10033 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
ed6fb7bd 10034 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
252b5132
RH
10035
10036 /* This is the large GOT case. If this is a reference to an
10037 external symbol, and there is no constant, we want
10038 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10039 addu $tempreg,$tempreg,$gp
10040 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 10041 or for lca or if tempreg is PIC_CALL_REG
9117d219
NC
10042 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10043 addu $tempreg,$tempreg,$gp
10044 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
252b5132
RH
10045 For a local symbol, we want
10046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10047 nop
10048 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10049
10050 If we have a small constant, and this is a reference to
10051 an external symbol, we want
10052 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10053 addu $tempreg,$tempreg,$gp
10054 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10055 nop
10056 addiu $tempreg,$tempreg,<constant>
10057 For a local symbol, we want
10058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10059 nop
10060 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10061
10062 If we have a large constant, and this is a reference to
10063 an external symbol, we want
10064 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10065 addu $tempreg,$tempreg,$gp
10066 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10067 lui $at,<hiconstant>
10068 addiu $at,$at,<loconstant>
10069 addu $tempreg,$tempreg,$at
10070 For a local symbol, we want
10071 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10072 lui $at,<hiconstant>
10073 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10074 addu $tempreg,$tempreg,$at
f5040a92 10075 */
438c16b8 10076
252b5132
RH
10077 expr1.X_add_number = offset_expr.X_add_number;
10078 offset_expr.X_add_number = 0;
4d7206a2 10079 relax_start (offset_expr.X_add_symbol);
67c0d1eb 10080 gpdelay = reg_needs_delay (mips_gp_register);
1abe91b1
MR
10081 if (expr1.X_add_number == 0 && breg == 0
10082 && (call || tempreg == PIC_CALL_REG))
9117d219
NC
10083 {
10084 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10085 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10086 }
df58fc94 10087 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 10088 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10089 tempreg, tempreg, mips_gp_register);
67c0d1eb 10090 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 10091 tempreg, lw_reloc_type, tempreg);
252b5132
RH
10092 if (expr1.X_add_number == 0)
10093 {
67c0d1eb 10094 if (breg != 0)
252b5132
RH
10095 {
10096 /* We're going to put in an addu instruction using
10097 tempreg, so we may as well insert the nop right
10098 now. */
269137b2 10099 load_delay_nop ();
252b5132 10100 }
252b5132
RH
10101 }
10102 else if (expr1.X_add_number >= -0x8000
10103 && expr1.X_add_number < 0x8000)
10104 {
269137b2 10105 load_delay_nop ();
67c0d1eb 10106 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10107 tempreg, tempreg, BFD_RELOC_LO16);
252b5132
RH
10108 }
10109 else
10110 {
c0ebe874
RS
10111 unsigned int dreg;
10112
252b5132
RH
10113 /* If we are going to add in a base register, and the
10114 target register and the base register are the same,
10115 then we are using AT as a temporary register. Since
10116 we want to load the constant into AT, we add our
10117 current AT (from the global offset table) and the
10118 register into the register now, and pretend we were
10119 not using a base register. */
c0ebe874 10120 if (breg != op[0])
67c0d1eb 10121 dreg = tempreg;
252b5132
RH
10122 else
10123 {
9c2799c2 10124 gas_assert (tempreg == AT);
269137b2 10125 load_delay_nop ();
67c0d1eb 10126 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10127 op[0], AT, breg);
10128 dreg = op[0];
252b5132
RH
10129 }
10130
f6a22291 10131 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10132 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
252b5132 10133
252b5132
RH
10134 used_at = 1;
10135 }
43c0598f 10136 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
4d7206a2 10137 relax_switch ();
252b5132 10138
67c0d1eb 10139 if (gpdelay)
252b5132
RH
10140 {
10141 /* This is needed because this instruction uses $gp, but
f5040a92 10142 the first instruction on the main stream does not. */
67c0d1eb 10143 macro_build (NULL, "nop", "");
252b5132 10144 }
ed6fb7bd 10145
67c0d1eb
RS
10146 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10147 local_reloc_type, mips_gp_register);
f5040a92 10148 if (expr1.X_add_number >= -0x8000
252b5132
RH
10149 && expr1.X_add_number < 0x8000)
10150 {
269137b2 10151 load_delay_nop ();
67c0d1eb
RS
10152 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10153 tempreg, tempreg, BFD_RELOC_LO16);
252b5132 10154 /* FIXME: If add_number is 0, and there was no base
f5040a92
AO
10155 register, the external symbol case ended with a load,
10156 so if the symbol turns out to not be external, and
10157 the next instruction uses tempreg, an unnecessary nop
10158 will be inserted. */
252b5132
RH
10159 }
10160 else
10161 {
c0ebe874 10162 if (breg == op[0])
252b5132
RH
10163 {
10164 /* We must add in the base register now, as in the
f5040a92 10165 external symbol case. */
9c2799c2 10166 gas_assert (tempreg == AT);
269137b2 10167 load_delay_nop ();
67c0d1eb 10168 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10169 op[0], AT, breg);
10170 tempreg = op[0];
252b5132 10171 /* We set breg to 0 because we have arranged to add
f5040a92 10172 it in in both cases. */
252b5132
RH
10173 breg = 0;
10174 }
10175
67c0d1eb
RS
10176 macro_build_lui (&expr1, AT);
10177 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10178 AT, AT, BFD_RELOC_LO16);
67c0d1eb 10179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10180 tempreg, tempreg, AT);
8fc2e39e 10181 used_at = 1;
252b5132 10182 }
4d7206a2 10183 relax_end ();
252b5132 10184 }
0a44bf69 10185 else if (mips_big_got && HAVE_NEWABI)
f5040a92 10186 {
f5040a92
AO
10187 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10188 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
67c0d1eb 10189 int add_breg_early = 0;
f5040a92
AO
10190
10191 /* This is the large GOT case. If this is a reference to an
10192 external symbol, and there is no constant, we want
10193 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10194 add $tempreg,$tempreg,$gp
10195 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 10196 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
10197 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10198 add $tempreg,$tempreg,$gp
10199 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10200
10201 If we have a small constant, and this is a reference to
10202 an external symbol, we want
10203 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10204 add $tempreg,$tempreg,$gp
10205 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10206 addi $tempreg,$tempreg,<constant>
10207
10208 If we have a large constant, and this is a reference to
10209 an external symbol, we want
10210 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10211 addu $tempreg,$tempreg,$gp
10212 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10213 lui $at,<hiconstant>
10214 addi $at,$at,<loconstant>
10215 add $tempreg,$tempreg,$at
10216
10217 If we have NewABI, and we know it's a local symbol, we want
10218 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10219 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10220 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10221
4d7206a2 10222 relax_start (offset_expr.X_add_symbol);
f5040a92 10223
4d7206a2 10224 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
10225 offset_expr.X_add_number = 0;
10226
1abe91b1
MR
10227 if (expr1.X_add_number == 0 && breg == 0
10228 && (call || tempreg == PIC_CALL_REG))
f5040a92
AO
10229 {
10230 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10231 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10232 }
df58fc94 10233 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 10234 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10235 tempreg, tempreg, mips_gp_register);
67c0d1eb
RS
10236 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10237 tempreg, lw_reloc_type, tempreg);
f5040a92
AO
10238
10239 if (expr1.X_add_number == 0)
4d7206a2 10240 ;
f5040a92
AO
10241 else if (expr1.X_add_number >= -0x8000
10242 && expr1.X_add_number < 0x8000)
10243 {
67c0d1eb 10244 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10245 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 10246 }
ecd13cd3 10247 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 10248 {
c0ebe874
RS
10249 unsigned int dreg;
10250
f5040a92
AO
10251 /* If we are going to add in a base register, and the
10252 target register and the base register are the same,
10253 then we are using AT as a temporary register. Since
10254 we want to load the constant into AT, we add our
10255 current AT (from the global offset table) and the
10256 register into the register now, and pretend we were
10257 not using a base register. */
c0ebe874 10258 if (breg != op[0])
f5040a92
AO
10259 dreg = tempreg;
10260 else
10261 {
9c2799c2 10262 gas_assert (tempreg == AT);
67c0d1eb 10263 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10264 op[0], AT, breg);
10265 dreg = op[0];
67c0d1eb 10266 add_breg_early = 1;
f5040a92
AO
10267 }
10268
f6a22291 10269 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10270 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
f5040a92 10271
f5040a92
AO
10272 used_at = 1;
10273 }
10274 else
10275 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10276
4d7206a2 10277 relax_switch ();
f5040a92 10278 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
10279 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10280 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10281 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10282 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10283 if (add_breg_early)
f5040a92 10284 {
67c0d1eb 10285 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 10286 op[0], tempreg, breg);
f5040a92 10287 breg = 0;
c0ebe874 10288 tempreg = op[0];
f5040a92 10289 }
4d7206a2 10290 relax_end ();
f5040a92 10291 }
252b5132
RH
10292 else
10293 abort ();
10294
10295 if (breg != 0)
c0ebe874 10296 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
252b5132
RH
10297 break;
10298
52b6b6b9 10299 case M_MSGSND:
df58fc94 10300 gas_assert (!mips_opts.micromips);
c0ebe874 10301 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
c7af4273 10302 break;
52b6b6b9
JM
10303
10304 case M_MSGLD:
df58fc94 10305 gas_assert (!mips_opts.micromips);
c8276761 10306 macro_build (NULL, "c2", "C", 0x02);
c7af4273 10307 break;
52b6b6b9
JM
10308
10309 case M_MSGLD_T:
df58fc94 10310 gas_assert (!mips_opts.micromips);
c0ebe874 10311 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
c7af4273 10312 break;
52b6b6b9
JM
10313
10314 case M_MSGWAIT:
df58fc94 10315 gas_assert (!mips_opts.micromips);
52b6b6b9 10316 macro_build (NULL, "c2", "C", 3);
c7af4273 10317 break;
52b6b6b9
JM
10318
10319 case M_MSGWAIT_T:
df58fc94 10320 gas_assert (!mips_opts.micromips);
c0ebe874 10321 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
c7af4273 10322 break;
52b6b6b9 10323
252b5132
RH
10324 case M_J_A:
10325 /* The j instruction may not be used in PIC code, since it
10326 requires an absolute address. We convert it to a b
10327 instruction. */
10328 if (mips_pic == NO_PIC)
67c0d1eb 10329 macro_build (&offset_expr, "j", "a");
252b5132 10330 else
67c0d1eb 10331 macro_build (&offset_expr, "b", "p");
8fc2e39e 10332 break;
252b5132
RH
10333
10334 /* The jal instructions must be handled as macros because when
10335 generating PIC code they expand to multi-instruction
10336 sequences. Normally they are simple instructions. */
df58fc94 10337 case M_JALS_1:
c0ebe874
RS
10338 op[1] = op[0];
10339 op[0] = RA;
df58fc94
RS
10340 /* Fall through. */
10341 case M_JALS_2:
10342 gas_assert (mips_opts.micromips);
833794fc
MR
10343 if (mips_opts.insn32)
10344 {
10345 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
10346 break;
10347 }
df58fc94
RS
10348 jals = 1;
10349 goto jal;
252b5132 10350 case M_JAL_1:
c0ebe874
RS
10351 op[1] = op[0];
10352 op[0] = RA;
252b5132
RH
10353 /* Fall through. */
10354 case M_JAL_2:
df58fc94 10355 jal:
3e722fb5 10356 if (mips_pic == NO_PIC)
df58fc94
RS
10357 {
10358 s = jals ? "jalrs" : "jalr";
e64af278 10359 if (mips_opts.micromips
833794fc 10360 && !mips_opts.insn32
c0ebe874 10361 && op[0] == RA
e64af278 10362 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
c0ebe874 10363 macro_build (NULL, s, "mj", op[1]);
df58fc94 10364 else
c0ebe874 10365 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
df58fc94 10366 }
0a44bf69 10367 else
252b5132 10368 {
df58fc94
RS
10369 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
10370 && mips_cprestore_offset >= 0);
10371
c0ebe874 10372 if (op[1] != PIC_CALL_REG)
252b5132 10373 as_warn (_("MIPS PIC call to register other than $25"));
bdaaa2e1 10374
833794fc
MR
10375 s = ((mips_opts.micromips
10376 && !mips_opts.insn32
10377 && (!mips_opts.noreorder || cprestore))
df58fc94 10378 ? "jalrs" : "jalr");
e64af278 10379 if (mips_opts.micromips
833794fc 10380 && !mips_opts.insn32
c0ebe874 10381 && op[0] == RA
e64af278 10382 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
c0ebe874 10383 macro_build (NULL, s, "mj", op[1]);
df58fc94 10384 else
c0ebe874 10385 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
0a44bf69 10386 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
252b5132 10387 {
6478892d
TS
10388 if (mips_cprestore_offset < 0)
10389 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10390 else
10391 {
90ecf173 10392 if (!mips_frame_reg_valid)
7a621144
DJ
10393 {
10394 as_warn (_("No .frame pseudo-op used in PIC code"));
10395 /* Quiet this warning. */
10396 mips_frame_reg_valid = 1;
10397 }
90ecf173 10398 if (!mips_cprestore_valid)
7a621144
DJ
10399 {
10400 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10401 /* Quiet this warning. */
10402 mips_cprestore_valid = 1;
10403 }
d3fca0b5
MR
10404 if (mips_opts.noreorder)
10405 macro_build (NULL, "nop", "");
6478892d 10406 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 10407 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 10408 mips_gp_register,
256ab948
TS
10409 mips_frame_reg,
10410 HAVE_64BIT_ADDRESSES);
6478892d 10411 }
252b5132
RH
10412 }
10413 }
252b5132 10414
8fc2e39e 10415 break;
252b5132 10416
df58fc94
RS
10417 case M_JALS_A:
10418 gas_assert (mips_opts.micromips);
833794fc
MR
10419 if (mips_opts.insn32)
10420 {
10421 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
10422 break;
10423 }
df58fc94
RS
10424 jals = 1;
10425 /* Fall through. */
252b5132
RH
10426 case M_JAL_A:
10427 if (mips_pic == NO_PIC)
df58fc94 10428 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
252b5132
RH
10429 else if (mips_pic == SVR4_PIC)
10430 {
10431 /* If this is a reference to an external symbol, and we are
10432 using a small GOT, we want
10433 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10434 nop
f9419b05 10435 jalr $ra,$25
252b5132
RH
10436 nop
10437 lw $gp,cprestore($sp)
10438 The cprestore value is set using the .cprestore
10439 pseudo-op. If we are using a big GOT, we want
10440 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10441 addu $25,$25,$gp
10442 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10443 nop
f9419b05 10444 jalr $ra,$25
252b5132
RH
10445 nop
10446 lw $gp,cprestore($sp)
10447 If the symbol is not external, we want
10448 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10449 nop
10450 addiu $25,$25,<sym> (BFD_RELOC_LO16)
f9419b05 10451 jalr $ra,$25
252b5132 10452 nop
438c16b8 10453 lw $gp,cprestore($sp)
f5040a92
AO
10454
10455 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10456 sequences above, minus nops, unless the symbol is local,
10457 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10458 GOT_DISP. */
438c16b8 10459 if (HAVE_NEWABI)
252b5132 10460 {
90ecf173 10461 if (!mips_big_got)
f5040a92 10462 {
4d7206a2 10463 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10464 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10465 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
f5040a92 10466 mips_gp_register);
4d7206a2 10467 relax_switch ();
67c0d1eb
RS
10468 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10469 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
4d7206a2
RS
10470 mips_gp_register);
10471 relax_end ();
f5040a92
AO
10472 }
10473 else
10474 {
4d7206a2 10475 relax_start (offset_expr.X_add_symbol);
df58fc94 10476 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
10477 BFD_RELOC_MIPS_CALL_HI16);
10478 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10479 PIC_CALL_REG, mips_gp_register);
10480 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10481 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10482 PIC_CALL_REG);
4d7206a2 10483 relax_switch ();
67c0d1eb
RS
10484 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10485 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
10486 mips_gp_register);
10487 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10488 PIC_CALL_REG, PIC_CALL_REG,
17a2f251 10489 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 10490 relax_end ();
f5040a92 10491 }
684022ea 10492
df58fc94 10493 macro_build_jalr (&offset_expr, 0);
252b5132
RH
10494 }
10495 else
10496 {
4d7206a2 10497 relax_start (offset_expr.X_add_symbol);
90ecf173 10498 if (!mips_big_got)
438c16b8 10499 {
67c0d1eb
RS
10500 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10501 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
17a2f251 10502 mips_gp_register);
269137b2 10503 load_delay_nop ();
4d7206a2 10504 relax_switch ();
438c16b8 10505 }
252b5132 10506 else
252b5132 10507 {
67c0d1eb
RS
10508 int gpdelay;
10509
10510 gpdelay = reg_needs_delay (mips_gp_register);
df58fc94 10511 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
10512 BFD_RELOC_MIPS_CALL_HI16);
10513 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10514 PIC_CALL_REG, mips_gp_register);
10515 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10516 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10517 PIC_CALL_REG);
269137b2 10518 load_delay_nop ();
4d7206a2 10519 relax_switch ();
67c0d1eb
RS
10520 if (gpdelay)
10521 macro_build (NULL, "nop", "");
252b5132 10522 }
67c0d1eb
RS
10523 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10524 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
4d7206a2 10525 mips_gp_register);
269137b2 10526 load_delay_nop ();
67c0d1eb
RS
10527 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10528 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
4d7206a2 10529 relax_end ();
df58fc94 10530 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
438c16b8 10531
6478892d
TS
10532 if (mips_cprestore_offset < 0)
10533 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10534 else
10535 {
90ecf173 10536 if (!mips_frame_reg_valid)
7a621144
DJ
10537 {
10538 as_warn (_("No .frame pseudo-op used in PIC code"));
10539 /* Quiet this warning. */
10540 mips_frame_reg_valid = 1;
10541 }
90ecf173 10542 if (!mips_cprestore_valid)
7a621144
DJ
10543 {
10544 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10545 /* Quiet this warning. */
10546 mips_cprestore_valid = 1;
10547 }
6478892d 10548 if (mips_opts.noreorder)
67c0d1eb 10549 macro_build (NULL, "nop", "");
6478892d 10550 expr1.X_add_number = mips_cprestore_offset;
67c0d1eb 10551 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 10552 mips_gp_register,
256ab948
TS
10553 mips_frame_reg,
10554 HAVE_64BIT_ADDRESSES);
6478892d 10555 }
252b5132
RH
10556 }
10557 }
0a44bf69
RS
10558 else if (mips_pic == VXWORKS_PIC)
10559 as_bad (_("Non-PIC jump used in PIC library"));
252b5132
RH
10560 else
10561 abort ();
10562
8fc2e39e 10563 break;
252b5132 10564
7f3c4072 10565 case M_LBUE_AB:
7f3c4072
CM
10566 s = "lbue";
10567 fmt = "t,+j(b)";
10568 offbits = 9;
10569 goto ld_st;
10570 case M_LHUE_AB:
7f3c4072
CM
10571 s = "lhue";
10572 fmt = "t,+j(b)";
10573 offbits = 9;
10574 goto ld_st;
10575 case M_LBE_AB:
7f3c4072
CM
10576 s = "lbe";
10577 fmt = "t,+j(b)";
10578 offbits = 9;
10579 goto ld_st;
10580 case M_LHE_AB:
7f3c4072
CM
10581 s = "lhe";
10582 fmt = "t,+j(b)";
10583 offbits = 9;
10584 goto ld_st;
10585 case M_LLE_AB:
7f3c4072
CM
10586 s = "lle";
10587 fmt = "t,+j(b)";
10588 offbits = 9;
10589 goto ld_st;
10590 case M_LWE_AB:
7f3c4072
CM
10591 s = "lwe";
10592 fmt = "t,+j(b)";
10593 offbits = 9;
10594 goto ld_st;
10595 case M_LWLE_AB:
7f3c4072
CM
10596 s = "lwle";
10597 fmt = "t,+j(b)";
10598 offbits = 9;
10599 goto ld_st;
10600 case M_LWRE_AB:
7f3c4072
CM
10601 s = "lwre";
10602 fmt = "t,+j(b)";
10603 offbits = 9;
10604 goto ld_st;
10605 case M_SBE_AB:
7f3c4072
CM
10606 s = "sbe";
10607 fmt = "t,+j(b)";
10608 offbits = 9;
10609 goto ld_st;
10610 case M_SCE_AB:
7f3c4072
CM
10611 s = "sce";
10612 fmt = "t,+j(b)";
10613 offbits = 9;
10614 goto ld_st;
10615 case M_SHE_AB:
7f3c4072
CM
10616 s = "she";
10617 fmt = "t,+j(b)";
10618 offbits = 9;
10619 goto ld_st;
10620 case M_SWE_AB:
7f3c4072
CM
10621 s = "swe";
10622 fmt = "t,+j(b)";
10623 offbits = 9;
10624 goto ld_st;
10625 case M_SWLE_AB:
7f3c4072
CM
10626 s = "swle";
10627 fmt = "t,+j(b)";
10628 offbits = 9;
10629 goto ld_st;
10630 case M_SWRE_AB:
7f3c4072
CM
10631 s = "swre";
10632 fmt = "t,+j(b)";
10633 offbits = 9;
10634 goto ld_st;
dec0624d 10635 case M_ACLR_AB:
dec0624d 10636 s = "aclr";
dec0624d 10637 fmt = "\\,~(b)";
7f3c4072 10638 offbits = 12;
dec0624d
MR
10639 goto ld_st;
10640 case M_ASET_AB:
dec0624d 10641 s = "aset";
dec0624d 10642 fmt = "\\,~(b)";
7f3c4072 10643 offbits = 12;
dec0624d 10644 goto ld_st;
252b5132
RH
10645 case M_LB_AB:
10646 s = "lb";
df58fc94 10647 fmt = "t,o(b)";
252b5132
RH
10648 goto ld;
10649 case M_LBU_AB:
10650 s = "lbu";
df58fc94 10651 fmt = "t,o(b)";
252b5132
RH
10652 goto ld;
10653 case M_LH_AB:
10654 s = "lh";
df58fc94 10655 fmt = "t,o(b)";
252b5132
RH
10656 goto ld;
10657 case M_LHU_AB:
10658 s = "lhu";
df58fc94 10659 fmt = "t,o(b)";
252b5132
RH
10660 goto ld;
10661 case M_LW_AB:
10662 s = "lw";
df58fc94 10663 fmt = "t,o(b)";
252b5132
RH
10664 goto ld;
10665 case M_LWC0_AB:
df58fc94 10666 gas_assert (!mips_opts.micromips);
252b5132 10667 s = "lwc0";
df58fc94 10668 fmt = "E,o(b)";
bdaaa2e1 10669 /* Itbl support may require additional care here. */
252b5132 10670 coproc = 1;
df58fc94 10671 goto ld_st;
252b5132
RH
10672 case M_LWC1_AB:
10673 s = "lwc1";
df58fc94 10674 fmt = "T,o(b)";
bdaaa2e1 10675 /* Itbl support may require additional care here. */
252b5132 10676 coproc = 1;
df58fc94 10677 goto ld_st;
252b5132
RH
10678 case M_LWC2_AB:
10679 s = "lwc2";
df58fc94 10680 fmt = COP12_FMT;
7f3c4072 10681 offbits = (mips_opts.micromips ? 12 : 16);
bdaaa2e1 10682 /* Itbl support may require additional care here. */
252b5132 10683 coproc = 1;
df58fc94 10684 goto ld_st;
252b5132 10685 case M_LWC3_AB:
df58fc94 10686 gas_assert (!mips_opts.micromips);
252b5132 10687 s = "lwc3";
df58fc94 10688 fmt = "E,o(b)";
bdaaa2e1 10689 /* Itbl support may require additional care here. */
252b5132 10690 coproc = 1;
df58fc94 10691 goto ld_st;
252b5132
RH
10692 case M_LWL_AB:
10693 s = "lwl";
df58fc94 10694 fmt = MEM12_FMT;
7f3c4072 10695 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10696 goto ld_st;
252b5132
RH
10697 case M_LWR_AB:
10698 s = "lwr";
df58fc94 10699 fmt = MEM12_FMT;
7f3c4072 10700 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10701 goto ld_st;
252b5132 10702 case M_LDC1_AB:
252b5132 10703 s = "ldc1";
df58fc94 10704 fmt = "T,o(b)";
bdaaa2e1 10705 /* Itbl support may require additional care here. */
252b5132 10706 coproc = 1;
df58fc94 10707 goto ld_st;
252b5132
RH
10708 case M_LDC2_AB:
10709 s = "ldc2";
df58fc94 10710 fmt = COP12_FMT;
7f3c4072 10711 offbits = (mips_opts.micromips ? 12 : 16);
bdaaa2e1 10712 /* Itbl support may require additional care here. */
252b5132 10713 coproc = 1;
df58fc94 10714 goto ld_st;
c77c0862 10715 case M_LQC2_AB:
c77c0862 10716 s = "lqc2";
14daeee3 10717 fmt = "+7,o(b)";
c77c0862
RS
10718 /* Itbl support may require additional care here. */
10719 coproc = 1;
10720 goto ld_st;
252b5132
RH
10721 case M_LDC3_AB:
10722 s = "ldc3";
df58fc94 10723 fmt = "E,o(b)";
bdaaa2e1 10724 /* Itbl support may require additional care here. */
252b5132 10725 coproc = 1;
df58fc94 10726 goto ld_st;
252b5132
RH
10727 case M_LDL_AB:
10728 s = "ldl";
df58fc94 10729 fmt = MEM12_FMT;
7f3c4072 10730 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10731 goto ld_st;
252b5132
RH
10732 case M_LDR_AB:
10733 s = "ldr";
df58fc94 10734 fmt = MEM12_FMT;
7f3c4072 10735 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10736 goto ld_st;
252b5132
RH
10737 case M_LL_AB:
10738 s = "ll";
df58fc94 10739 fmt = MEM12_FMT;
7f3c4072 10740 offbits = (mips_opts.micromips ? 12 : 16);
252b5132
RH
10741 goto ld;
10742 case M_LLD_AB:
10743 s = "lld";
df58fc94 10744 fmt = MEM12_FMT;
7f3c4072 10745 offbits = (mips_opts.micromips ? 12 : 16);
252b5132
RH
10746 goto ld;
10747 case M_LWU_AB:
10748 s = "lwu";
df58fc94 10749 fmt = MEM12_FMT;
7f3c4072 10750 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
10751 goto ld;
10752 case M_LWP_AB:
df58fc94
RS
10753 gas_assert (mips_opts.micromips);
10754 s = "lwp";
10755 fmt = "t,~(b)";
7f3c4072 10756 offbits = 12;
df58fc94
RS
10757 lp = 1;
10758 goto ld;
10759 case M_LDP_AB:
df58fc94
RS
10760 gas_assert (mips_opts.micromips);
10761 s = "ldp";
10762 fmt = "t,~(b)";
7f3c4072 10763 offbits = 12;
df58fc94
RS
10764 lp = 1;
10765 goto ld;
10766 case M_LWM_AB:
df58fc94
RS
10767 gas_assert (mips_opts.micromips);
10768 s = "lwm";
10769 fmt = "n,~(b)";
7f3c4072 10770 offbits = 12;
df58fc94
RS
10771 goto ld_st;
10772 case M_LDM_AB:
df58fc94
RS
10773 gas_assert (mips_opts.micromips);
10774 s = "ldm";
10775 fmt = "n,~(b)";
7f3c4072 10776 offbits = 12;
df58fc94
RS
10777 goto ld_st;
10778
252b5132 10779 ld:
f19ccbda 10780 /* We don't want to use $0 as tempreg. */
c0ebe874 10781 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
df58fc94 10782 goto ld_st;
252b5132 10783 else
c0ebe874 10784 tempreg = op[0] + lp;
df58fc94
RS
10785 goto ld_noat;
10786
252b5132
RH
10787 case M_SB_AB:
10788 s = "sb";
df58fc94
RS
10789 fmt = "t,o(b)";
10790 goto ld_st;
252b5132
RH
10791 case M_SH_AB:
10792 s = "sh";
df58fc94
RS
10793 fmt = "t,o(b)";
10794 goto ld_st;
252b5132
RH
10795 case M_SW_AB:
10796 s = "sw";
df58fc94
RS
10797 fmt = "t,o(b)";
10798 goto ld_st;
252b5132 10799 case M_SWC0_AB:
df58fc94 10800 gas_assert (!mips_opts.micromips);
252b5132 10801 s = "swc0";
df58fc94 10802 fmt = "E,o(b)";
bdaaa2e1 10803 /* Itbl support may require additional care here. */
252b5132 10804 coproc = 1;
df58fc94 10805 goto ld_st;
252b5132
RH
10806 case M_SWC1_AB:
10807 s = "swc1";
df58fc94 10808 fmt = "T,o(b)";
bdaaa2e1 10809 /* Itbl support may require additional care here. */
252b5132 10810 coproc = 1;
df58fc94 10811 goto ld_st;
252b5132
RH
10812 case M_SWC2_AB:
10813 s = "swc2";
df58fc94 10814 fmt = COP12_FMT;
7f3c4072 10815 offbits = (mips_opts.micromips ? 12 : 16);
bdaaa2e1 10816 /* Itbl support may require additional care here. */
252b5132 10817 coproc = 1;
df58fc94 10818 goto ld_st;
252b5132 10819 case M_SWC3_AB:
df58fc94 10820 gas_assert (!mips_opts.micromips);
252b5132 10821 s = "swc3";
df58fc94 10822 fmt = "E,o(b)";
bdaaa2e1 10823 /* Itbl support may require additional care here. */
252b5132 10824 coproc = 1;
df58fc94 10825 goto ld_st;
252b5132
RH
10826 case M_SWL_AB:
10827 s = "swl";
df58fc94 10828 fmt = MEM12_FMT;
7f3c4072 10829 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10830 goto ld_st;
252b5132
RH
10831 case M_SWR_AB:
10832 s = "swr";
df58fc94 10833 fmt = MEM12_FMT;
7f3c4072 10834 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10835 goto ld_st;
252b5132
RH
10836 case M_SC_AB:
10837 s = "sc";
df58fc94 10838 fmt = MEM12_FMT;
7f3c4072 10839 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10840 goto ld_st;
252b5132
RH
10841 case M_SCD_AB:
10842 s = "scd";
df58fc94 10843 fmt = MEM12_FMT;
7f3c4072 10844 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10845 goto ld_st;
d43b4baf
TS
10846 case M_CACHE_AB:
10847 s = "cache";
df58fc94 10848 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
7f3c4072
CM
10849 offbits = (mips_opts.micromips ? 12 : 16);
10850 goto ld_st;
10851 case M_CACHEE_AB:
7f3c4072
CM
10852 s = "cachee";
10853 fmt = "k,+j(b)";
10854 offbits = 9;
df58fc94 10855 goto ld_st;
3eebd5eb
MR
10856 case M_PREF_AB:
10857 s = "pref";
df58fc94 10858 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
7f3c4072
CM
10859 offbits = (mips_opts.micromips ? 12 : 16);
10860 goto ld_st;
10861 case M_PREFE_AB:
7f3c4072
CM
10862 s = "prefe";
10863 fmt = "k,+j(b)";
10864 offbits = 9;
df58fc94 10865 goto ld_st;
252b5132 10866 case M_SDC1_AB:
252b5132 10867 s = "sdc1";
df58fc94 10868 fmt = "T,o(b)";
252b5132 10869 coproc = 1;
bdaaa2e1 10870 /* Itbl support may require additional care here. */
df58fc94 10871 goto ld_st;
252b5132
RH
10872 case M_SDC2_AB:
10873 s = "sdc2";
df58fc94 10874 fmt = COP12_FMT;
7f3c4072 10875 offbits = (mips_opts.micromips ? 12 : 16);
c77c0862
RS
10876 /* Itbl support may require additional care here. */
10877 coproc = 1;
10878 goto ld_st;
10879 case M_SQC2_AB:
c77c0862 10880 s = "sqc2";
14daeee3 10881 fmt = "+7,o(b)";
bdaaa2e1 10882 /* Itbl support may require additional care here. */
252b5132 10883 coproc = 1;
df58fc94 10884 goto ld_st;
252b5132 10885 case M_SDC3_AB:
df58fc94 10886 gas_assert (!mips_opts.micromips);
252b5132 10887 s = "sdc3";
df58fc94 10888 fmt = "E,o(b)";
bdaaa2e1 10889 /* Itbl support may require additional care here. */
252b5132 10890 coproc = 1;
df58fc94 10891 goto ld_st;
252b5132
RH
10892 case M_SDL_AB:
10893 s = "sdl";
df58fc94 10894 fmt = MEM12_FMT;
7f3c4072 10895 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 10896 goto ld_st;
252b5132
RH
10897 case M_SDR_AB:
10898 s = "sdr";
df58fc94 10899 fmt = MEM12_FMT;
7f3c4072 10900 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
10901 goto ld_st;
10902 case M_SWP_AB:
df58fc94
RS
10903 gas_assert (mips_opts.micromips);
10904 s = "swp";
10905 fmt = "t,~(b)";
7f3c4072 10906 offbits = 12;
df58fc94
RS
10907 goto ld_st;
10908 case M_SDP_AB:
df58fc94
RS
10909 gas_assert (mips_opts.micromips);
10910 s = "sdp";
10911 fmt = "t,~(b)";
7f3c4072 10912 offbits = 12;
df58fc94
RS
10913 goto ld_st;
10914 case M_SWM_AB:
df58fc94
RS
10915 gas_assert (mips_opts.micromips);
10916 s = "swm";
10917 fmt = "n,~(b)";
7f3c4072 10918 offbits = 12;
df58fc94
RS
10919 goto ld_st;
10920 case M_SDM_AB:
df58fc94
RS
10921 gas_assert (mips_opts.micromips);
10922 s = "sdm";
10923 fmt = "n,~(b)";
7f3c4072 10924 offbits = 12;
df58fc94
RS
10925
10926 ld_st:
8fc2e39e 10927 tempreg = AT;
df58fc94 10928 ld_noat:
c0ebe874 10929 breg = op[2];
f2ae14a1
RS
10930 if (small_offset_p (0, align, 16))
10931 {
10932 /* The first case exists for M_LD_AB and M_SD_AB, which are
10933 macros for o32 but which should act like normal instructions
10934 otherwise. */
10935 if (offbits == 16)
c0ebe874 10936 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
f2ae14a1
RS
10937 offset_reloc[1], offset_reloc[2], breg);
10938 else if (small_offset_p (0, align, offbits))
10939 {
10940 if (offbits == 0)
c0ebe874 10941 macro_build (NULL, s, fmt, op[0], breg);
f2ae14a1 10942 else
c0ebe874 10943 macro_build (NULL, s, fmt, op[0],
c8276761 10944 (int) offset_expr.X_add_number, breg);
f2ae14a1
RS
10945 }
10946 else
10947 {
10948 if (tempreg == AT)
10949 used_at = 1;
10950 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10951 tempreg, breg, -1, offset_reloc[0],
10952 offset_reloc[1], offset_reloc[2]);
10953 if (offbits == 0)
c0ebe874 10954 macro_build (NULL, s, fmt, op[0], tempreg);
f2ae14a1 10955 else
c0ebe874 10956 macro_build (NULL, s, fmt, op[0], 0, tempreg);
f2ae14a1
RS
10957 }
10958 break;
10959 }
10960
10961 if (tempreg == AT)
10962 used_at = 1;
10963
252b5132
RH
10964 if (offset_expr.X_op != O_constant
10965 && offset_expr.X_op != O_symbol)
10966 {
f71d0d44 10967 as_bad (_("Expression too complex"));
252b5132
RH
10968 offset_expr.X_op = O_constant;
10969 }
10970
2051e8c4
MR
10971 if (HAVE_32BIT_ADDRESSES
10972 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
10973 {
10974 char value [32];
10975
10976 sprintf_vma (value, offset_expr.X_add_number);
20e1fcfd 10977 as_bad (_("Number (0x%s) larger than 32 bits"), value);
55e08f71 10978 }
2051e8c4 10979
252b5132
RH
10980 /* A constant expression in PIC code can be handled just as it
10981 is in non PIC code. */
aed1a261
RS
10982 if (offset_expr.X_op == O_constant)
10983 {
f2ae14a1
RS
10984 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
10985 offbits == 0 ? 16 : offbits);
10986 offset_expr.X_add_number -= expr1.X_add_number;
df58fc94 10987
f2ae14a1
RS
10988 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
10989 if (breg != 0)
10990 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10991 tempreg, tempreg, breg);
7f3c4072 10992 if (offbits == 0)
dd6a37e7 10993 {
f2ae14a1 10994 if (offset_expr.X_add_number != 0)
dd6a37e7 10995 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
f2ae14a1 10996 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
c0ebe874 10997 macro_build (NULL, s, fmt, op[0], tempreg);
dd6a37e7 10998 }
7f3c4072 10999 else if (offbits == 16)
c0ebe874 11000 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
df58fc94 11001 else
c0ebe874 11002 macro_build (NULL, s, fmt, op[0],
c8276761 11003 (int) offset_expr.X_add_number, tempreg);
df58fc94 11004 }
7f3c4072 11005 else if (offbits != 16)
df58fc94 11006 {
7f3c4072
CM
11007 /* The offset field is too narrow to be used for a low-part
11008 relocation, so load the whole address into the auxillary
f2ae14a1
RS
11009 register. */
11010 load_address (tempreg, &offset_expr, &used_at);
11011 if (breg != 0)
11012 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11013 tempreg, tempreg, breg);
7f3c4072 11014 if (offbits == 0)
c0ebe874 11015 macro_build (NULL, s, fmt, op[0], tempreg);
dd6a37e7 11016 else
c0ebe874 11017 macro_build (NULL, s, fmt, op[0], 0, tempreg);
aed1a261
RS
11018 }
11019 else if (mips_pic == NO_PIC)
252b5132
RH
11020 {
11021 /* If this is a reference to a GP relative symbol, and there
11022 is no base register, we want
c0ebe874 11023 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
252b5132
RH
11024 Otherwise, if there is no base register, we want
11025 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
c0ebe874 11026 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
252b5132
RH
11027 If we have a constant, we need two instructions anyhow,
11028 so we always use the latter form.
11029
11030 If we have a base register, and this is a reference to a
11031 GP relative symbol, we want
11032 addu $tempreg,$breg,$gp
c0ebe874 11033 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
252b5132
RH
11034 Otherwise we want
11035 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11036 addu $tempreg,$tempreg,$breg
c0ebe874 11037 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245 11038 With a constant we always use the latter case.
76b3015f 11039
d6bc6245
TS
11040 With 64bit address space and no base register and $at usable,
11041 we want
11042 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11043 lui $at,<sym> (BFD_RELOC_HI16_S)
11044 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11045 dsll32 $tempreg,0
11046 daddu $tempreg,$at
c0ebe874 11047 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11048 If we have a base register, we want
11049 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11050 lui $at,<sym> (BFD_RELOC_HI16_S)
11051 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11052 daddu $at,$breg
11053 dsll32 $tempreg,0
11054 daddu $tempreg,$at
c0ebe874 11055 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11056
11057 Without $at we can't generate the optimal path for superscalar
11058 processors here since this would require two temporary registers.
11059 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11060 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11061 dsll $tempreg,16
11062 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11063 dsll $tempreg,16
c0ebe874 11064 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11065 If we have a base register, we want
11066 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11067 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11068 dsll $tempreg,16
11069 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11070 dsll $tempreg,16
11071 daddu $tempreg,$tempreg,$breg
c0ebe874 11072 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
6373ee54 11073
6caf9ef4 11074 For GP relative symbols in 64bit address space we can use
aed1a261
RS
11075 the same sequence as in 32bit address space. */
11076 if (HAVE_64BIT_SYMBOLS)
d6bc6245 11077 {
aed1a261 11078 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4
TS
11079 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11080 {
11081 relax_start (offset_expr.X_add_symbol);
11082 if (breg == 0)
11083 {
c0ebe874 11084 macro_build (&offset_expr, s, fmt, op[0],
6caf9ef4
TS
11085 BFD_RELOC_GPREL16, mips_gp_register);
11086 }
11087 else
11088 {
11089 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11090 tempreg, breg, mips_gp_register);
c0ebe874 11091 macro_build (&offset_expr, s, fmt, op[0],
6caf9ef4
TS
11092 BFD_RELOC_GPREL16, tempreg);
11093 }
11094 relax_switch ();
11095 }
d6bc6245 11096
741fe287 11097 if (used_at == 0 && mips_opts.at)
d6bc6245 11098 {
df58fc94 11099 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb 11100 BFD_RELOC_MIPS_HIGHEST);
df58fc94 11101 macro_build (&offset_expr, "lui", LUI_FMT, AT,
67c0d1eb
RS
11102 BFD_RELOC_HI16_S);
11103 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11104 tempreg, BFD_RELOC_MIPS_HIGHER);
d6bc6245 11105 if (breg != 0)
67c0d1eb 11106 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
df58fc94 11107 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 11108 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
c0ebe874 11109 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
67c0d1eb 11110 tempreg);
d6bc6245
TS
11111 used_at = 1;
11112 }
11113 else
11114 {
df58fc94 11115 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb
RS
11116 BFD_RELOC_MIPS_HIGHEST);
11117 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11118 tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 11119 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb
RS
11120 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11121 tempreg, BFD_RELOC_HI16_S);
df58fc94 11122 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
d6bc6245 11123 if (breg != 0)
67c0d1eb 11124 macro_build (NULL, "daddu", "d,v,t",
17a2f251 11125 tempreg, tempreg, breg);
c0ebe874 11126 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11127 BFD_RELOC_LO16, tempreg);
d6bc6245 11128 }
6caf9ef4
TS
11129
11130 if (mips_relax.sequence)
11131 relax_end ();
8fc2e39e 11132 break;
d6bc6245 11133 }
256ab948 11134
252b5132
RH
11135 if (breg == 0)
11136 {
67c0d1eb 11137 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11138 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11139 {
4d7206a2 11140 relax_start (offset_expr.X_add_symbol);
c0ebe874 11141 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
67c0d1eb 11142 mips_gp_register);
4d7206a2 11143 relax_switch ();
252b5132 11144 }
67c0d1eb 11145 macro_build_lui (&offset_expr, tempreg);
c0ebe874 11146 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11147 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
11148 if (mips_relax.sequence)
11149 relax_end ();
252b5132
RH
11150 }
11151 else
11152 {
67c0d1eb 11153 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11154 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11155 {
4d7206a2 11156 relax_start (offset_expr.X_add_symbol);
67c0d1eb 11157 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11158 tempreg, breg, mips_gp_register);
c0ebe874 11159 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11160 BFD_RELOC_GPREL16, tempreg);
4d7206a2 11161 relax_switch ();
252b5132 11162 }
67c0d1eb
RS
11163 macro_build_lui (&offset_expr, tempreg);
11164 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11165 tempreg, tempreg, breg);
c0ebe874 11166 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11167 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
11168 if (mips_relax.sequence)
11169 relax_end ();
252b5132
RH
11170 }
11171 }
0a44bf69 11172 else if (!mips_big_got)
252b5132 11173 {
ed6fb7bd 11174 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
f9419b05 11175
252b5132
RH
11176 /* If this is a reference to an external symbol, we want
11177 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11178 nop
c0ebe874 11179 <op> op[0],0($tempreg)
252b5132
RH
11180 Otherwise we want
11181 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11182 nop
11183 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
c0ebe874 11184 <op> op[0],0($tempreg)
f5040a92
AO
11185
11186 For NewABI, we want
11187 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
c0ebe874 11188 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 11189
252b5132
RH
11190 If there is a base register, we add it to $tempreg before
11191 the <op>. If there is a constant, we stick it in the
11192 <op> instruction. We don't handle constants larger than
11193 16 bits, because we have no way to load the upper 16 bits
11194 (actually, we could handle them for the subset of cases
11195 in which we are not using $at). */
9c2799c2 11196 gas_assert (offset_expr.X_op == O_symbol);
f5040a92
AO
11197 if (HAVE_NEWABI)
11198 {
67c0d1eb
RS
11199 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11200 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 11201 if (breg != 0)
67c0d1eb 11202 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11203 tempreg, tempreg, breg);
c0ebe874 11204 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11205 BFD_RELOC_MIPS_GOT_OFST, tempreg);
f5040a92
AO
11206 break;
11207 }
252b5132
RH
11208 expr1.X_add_number = offset_expr.X_add_number;
11209 offset_expr.X_add_number = 0;
11210 if (expr1.X_add_number < -0x8000
11211 || expr1.X_add_number >= 0x8000)
11212 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb
RS
11213 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11214 lw_reloc_type, mips_gp_register);
269137b2 11215 load_delay_nop ();
4d7206a2
RS
11216 relax_start (offset_expr.X_add_symbol);
11217 relax_switch ();
67c0d1eb
RS
11218 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11219 tempreg, BFD_RELOC_LO16);
4d7206a2 11220 relax_end ();
252b5132 11221 if (breg != 0)
67c0d1eb 11222 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11223 tempreg, tempreg, breg);
c0ebe874 11224 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
252b5132 11225 }
0a44bf69 11226 else if (mips_big_got && !HAVE_NEWABI)
252b5132 11227 {
67c0d1eb 11228 int gpdelay;
252b5132
RH
11229
11230 /* If this is a reference to an external symbol, we want
11231 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11232 addu $tempreg,$tempreg,$gp
11233 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
c0ebe874 11234 <op> op[0],0($tempreg)
252b5132
RH
11235 Otherwise we want
11236 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11237 nop
11238 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
c0ebe874 11239 <op> op[0],0($tempreg)
252b5132
RH
11240 If there is a base register, we add it to $tempreg before
11241 the <op>. If there is a constant, we stick it in the
11242 <op> instruction. We don't handle constants larger than
11243 16 bits, because we have no way to load the upper 16 bits
11244 (actually, we could handle them for the subset of cases
f5040a92 11245 in which we are not using $at). */
9c2799c2 11246 gas_assert (offset_expr.X_op == O_symbol);
252b5132
RH
11247 expr1.X_add_number = offset_expr.X_add_number;
11248 offset_expr.X_add_number = 0;
11249 if (expr1.X_add_number < -0x8000
11250 || expr1.X_add_number >= 0x8000)
11251 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 11252 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 11253 relax_start (offset_expr.X_add_symbol);
df58fc94 11254 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 11255 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
11256 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11257 mips_gp_register);
11258 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11259 BFD_RELOC_MIPS_GOT_LO16, tempreg);
4d7206a2 11260 relax_switch ();
67c0d1eb
RS
11261 if (gpdelay)
11262 macro_build (NULL, "nop", "");
11263 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11264 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 11265 load_delay_nop ();
67c0d1eb
RS
11266 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11267 tempreg, BFD_RELOC_LO16);
4d7206a2
RS
11268 relax_end ();
11269
252b5132 11270 if (breg != 0)
67c0d1eb 11271 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11272 tempreg, tempreg, breg);
c0ebe874 11273 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
252b5132 11274 }
0a44bf69 11275 else if (mips_big_got && HAVE_NEWABI)
f5040a92 11276 {
f5040a92
AO
11277 /* If this is a reference to an external symbol, we want
11278 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11279 add $tempreg,$tempreg,$gp
11280 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
c0ebe874 11281 <op> op[0],<ofst>($tempreg)
f5040a92
AO
11282 Otherwise, for local symbols, we want:
11283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
c0ebe874 11284 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9c2799c2 11285 gas_assert (offset_expr.X_op == O_symbol);
4d7206a2 11286 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
11287 offset_expr.X_add_number = 0;
11288 if (expr1.X_add_number < -0x8000
11289 || expr1.X_add_number >= 0x8000)
11290 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4d7206a2 11291 relax_start (offset_expr.X_add_symbol);
df58fc94 11292 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 11293 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
11294 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11295 mips_gp_register);
11296 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11297 BFD_RELOC_MIPS_GOT_LO16, tempreg);
f5040a92 11298 if (breg != 0)
67c0d1eb 11299 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11300 tempreg, tempreg, breg);
c0ebe874 11301 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
684022ea 11302
4d7206a2 11303 relax_switch ();
f5040a92 11304 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
11305 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11306 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 11307 if (breg != 0)
67c0d1eb 11308 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11309 tempreg, tempreg, breg);
c0ebe874 11310 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11311 BFD_RELOC_MIPS_GOT_OFST, tempreg);
4d7206a2 11312 relax_end ();
f5040a92 11313 }
252b5132
RH
11314 else
11315 abort ();
11316
252b5132
RH
11317 break;
11318
833794fc
MR
11319 case M_JRADDIUSP:
11320 gas_assert (mips_opts.micromips);
11321 gas_assert (mips_opts.insn32);
11322 start_noreorder ();
11323 macro_build (NULL, "jr", "s", RA);
c0ebe874 11324 expr1.X_add_number = op[0] << 2;
833794fc
MR
11325 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11326 end_noreorder ();
11327 break;
11328
11329 case M_JRC:
11330 gas_assert (mips_opts.micromips);
11331 gas_assert (mips_opts.insn32);
c0ebe874 11332 macro_build (NULL, "jr", "s", op[0]);
833794fc
MR
11333 if (mips_opts.noreorder)
11334 macro_build (NULL, "nop", "");
11335 break;
11336
252b5132
RH
11337 case M_LI:
11338 case M_LI_S:
c0ebe874 11339 load_register (op[0], &imm_expr, 0);
8fc2e39e 11340 break;
252b5132
RH
11341
11342 case M_DLI:
c0ebe874 11343 load_register (op[0], &imm_expr, 1);
8fc2e39e 11344 break;
252b5132
RH
11345
11346 case M_LI_SS:
11347 if (imm_expr.X_op == O_constant)
11348 {
8fc2e39e 11349 used_at = 1;
67c0d1eb 11350 load_register (AT, &imm_expr, 0);
c0ebe874 11351 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
252b5132
RH
11352 break;
11353 }
11354 else
11355 {
9c2799c2 11356 gas_assert (offset_expr.X_op == O_symbol
90ecf173
MR
11357 && strcmp (segment_name (S_GET_SEGMENT
11358 (offset_expr.X_add_symbol)),
11359 ".lit4") == 0
11360 && offset_expr.X_add_number == 0);
c0ebe874 11361 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
17a2f251 11362 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8fc2e39e 11363 break;
252b5132
RH
11364 }
11365
11366 case M_LI_D:
ca4e0257
RS
11367 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11368 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11369 order 32 bits of the value and the low order 32 bits are either
11370 zero or in OFFSET_EXPR. */
252b5132
RH
11371 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
11372 {
ca4e0257 11373 if (HAVE_64BIT_GPRS)
c0ebe874 11374 load_register (op[0], &imm_expr, 1);
252b5132
RH
11375 else
11376 {
11377 int hreg, lreg;
11378
11379 if (target_big_endian)
11380 {
c0ebe874
RS
11381 hreg = op[0];
11382 lreg = op[0] + 1;
252b5132
RH
11383 }
11384 else
11385 {
c0ebe874
RS
11386 hreg = op[0] + 1;
11387 lreg = op[0];
252b5132
RH
11388 }
11389
11390 if (hreg <= 31)
67c0d1eb 11391 load_register (hreg, &imm_expr, 0);
252b5132
RH
11392 if (lreg <= 31)
11393 {
11394 if (offset_expr.X_op == O_absent)
67c0d1eb 11395 move_register (lreg, 0);
252b5132
RH
11396 else
11397 {
9c2799c2 11398 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 11399 load_register (lreg, &offset_expr, 0);
252b5132
RH
11400 }
11401 }
11402 }
8fc2e39e 11403 break;
252b5132
RH
11404 }
11405
11406 /* We know that sym is in the .rdata section. First we get the
11407 upper 16 bits of the address. */
11408 if (mips_pic == NO_PIC)
11409 {
67c0d1eb 11410 macro_build_lui (&offset_expr, AT);
8fc2e39e 11411 used_at = 1;
252b5132 11412 }
0a44bf69 11413 else
252b5132 11414 {
67c0d1eb
RS
11415 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11416 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8fc2e39e 11417 used_at = 1;
252b5132 11418 }
bdaaa2e1 11419
252b5132 11420 /* Now we load the register(s). */
ca4e0257 11421 if (HAVE_64BIT_GPRS)
8fc2e39e
TS
11422 {
11423 used_at = 1;
c0ebe874
RS
11424 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
11425 BFD_RELOC_LO16, AT);
8fc2e39e 11426 }
252b5132
RH
11427 else
11428 {
8fc2e39e 11429 used_at = 1;
c0ebe874
RS
11430 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
11431 BFD_RELOC_LO16, AT);
11432 if (op[0] != RA)
252b5132
RH
11433 {
11434 /* FIXME: How in the world do we deal with the possible
11435 overflow here? */
11436 offset_expr.X_add_number += 4;
67c0d1eb 11437 macro_build (&offset_expr, "lw", "t,o(b)",
c0ebe874 11438 op[0] + 1, BFD_RELOC_LO16, AT);
252b5132
RH
11439 }
11440 }
252b5132
RH
11441 break;
11442
11443 case M_LI_DD:
ca4e0257
RS
11444 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11445 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11446 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11447 the value and the low order 32 bits are either zero or in
11448 OFFSET_EXPR. */
252b5132
RH
11449 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
11450 {
8fc2e39e 11451 used_at = 1;
67c0d1eb 11452 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
ca4e0257
RS
11453 if (HAVE_64BIT_FPRS)
11454 {
9c2799c2 11455 gas_assert (HAVE_64BIT_GPRS);
c0ebe874 11456 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
ca4e0257 11457 }
252b5132
RH
11458 else
11459 {
c0ebe874 11460 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
252b5132 11461 if (offset_expr.X_op == O_absent)
c0ebe874 11462 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
252b5132
RH
11463 else
11464 {
9c2799c2 11465 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 11466 load_register (AT, &offset_expr, 0);
c0ebe874 11467 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
252b5132
RH
11468 }
11469 }
11470 break;
11471 }
11472
9c2799c2 11473 gas_assert (offset_expr.X_op == O_symbol
90ecf173 11474 && offset_expr.X_add_number == 0);
252b5132
RH
11475 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
11476 if (strcmp (s, ".lit8") == 0)
f2ae14a1 11477 {
c0ebe874 11478 op[2] = mips_gp_register;
f2ae14a1
RS
11479 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
11480 offset_reloc[1] = BFD_RELOC_UNUSED;
11481 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132
RH
11482 }
11483 else
11484 {
9c2799c2 11485 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8fc2e39e 11486 used_at = 1;
0a44bf69 11487 if (mips_pic != NO_PIC)
67c0d1eb
RS
11488 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11489 BFD_RELOC_MIPS_GOT16, mips_gp_register);
252b5132
RH
11490 else
11491 {
11492 /* FIXME: This won't work for a 64 bit address. */
67c0d1eb 11493 macro_build_lui (&offset_expr, AT);
252b5132 11494 }
bdaaa2e1 11495
c0ebe874 11496 op[2] = AT;
f2ae14a1
RS
11497 offset_reloc[0] = BFD_RELOC_LO16;
11498 offset_reloc[1] = BFD_RELOC_UNUSED;
11499 offset_reloc[2] = BFD_RELOC_UNUSED;
11500 }
11501 align = 8;
11502 /* Fall through */
c4a68bea 11503
252b5132
RH
11504 case M_L_DAB:
11505 /*
11506 * The MIPS assembler seems to check for X_add_number not
11507 * being double aligned and generating:
11508 * lui at,%hi(foo+1)
11509 * addu at,at,v1
11510 * addiu at,at,%lo(foo+1)
11511 * lwc1 f2,0(at)
11512 * lwc1 f3,4(at)
11513 * But, the resulting address is the same after relocation so why
11514 * generate the extra instruction?
11515 */
bdaaa2e1 11516 /* Itbl support may require additional care here. */
252b5132 11517 coproc = 1;
df58fc94 11518 fmt = "T,o(b)";
0aa27725 11519 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
11520 {
11521 s = "ldc1";
df58fc94 11522 goto ld_st;
252b5132 11523 }
252b5132 11524 s = "lwc1";
252b5132
RH
11525 goto ldd_std;
11526
11527 case M_S_DAB:
df58fc94
RS
11528 gas_assert (!mips_opts.micromips);
11529 /* Itbl support may require additional care here. */
11530 coproc = 1;
11531 fmt = "T,o(b)";
0aa27725 11532 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
11533 {
11534 s = "sdc1";
df58fc94 11535 goto ld_st;
252b5132 11536 }
252b5132 11537 s = "swc1";
252b5132
RH
11538 goto ldd_std;
11539
e407c74b
NC
11540 case M_LQ_AB:
11541 fmt = "t,o(b)";
11542 s = "lq";
11543 goto ld;
11544
11545 case M_SQ_AB:
11546 fmt = "t,o(b)";
11547 s = "sq";
11548 goto ld_st;
11549
252b5132 11550 case M_LD_AB:
df58fc94 11551 fmt = "t,o(b)";
ca4e0257 11552 if (HAVE_64BIT_GPRS)
252b5132
RH
11553 {
11554 s = "ld";
11555 goto ld;
11556 }
252b5132 11557 s = "lw";
252b5132
RH
11558 goto ldd_std;
11559
11560 case M_SD_AB:
df58fc94 11561 fmt = "t,o(b)";
ca4e0257 11562 if (HAVE_64BIT_GPRS)
252b5132
RH
11563 {
11564 s = "sd";
df58fc94 11565 goto ld_st;
252b5132 11566 }
252b5132 11567 s = "sw";
252b5132
RH
11568
11569 ldd_std:
f2ae14a1
RS
11570 /* Even on a big endian machine $fn comes before $fn+1. We have
11571 to adjust when loading from memory. We set coproc if we must
11572 load $fn+1 first. */
11573 /* Itbl support may require additional care here. */
11574 if (!target_big_endian)
11575 coproc = 0;
11576
c0ebe874 11577 breg = op[2];
f2ae14a1
RS
11578 if (small_offset_p (0, align, 16))
11579 {
11580 ep = &offset_expr;
11581 if (!small_offset_p (4, align, 16))
11582 {
11583 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
11584 -1, offset_reloc[0], offset_reloc[1],
11585 offset_reloc[2]);
11586 expr1.X_add_number = 0;
11587 ep = &expr1;
11588 breg = AT;
11589 used_at = 1;
11590 offset_reloc[0] = BFD_RELOC_LO16;
11591 offset_reloc[1] = BFD_RELOC_UNUSED;
11592 offset_reloc[2] = BFD_RELOC_UNUSED;
11593 }
c0ebe874 11594 if (strcmp (s, "lw") == 0 && op[0] == breg)
f2ae14a1
RS
11595 {
11596 ep->X_add_number += 4;
c0ebe874 11597 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
f2ae14a1
RS
11598 offset_reloc[1], offset_reloc[2], breg);
11599 ep->X_add_number -= 4;
c0ebe874 11600 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
f2ae14a1
RS
11601 offset_reloc[1], offset_reloc[2], breg);
11602 }
11603 else
11604 {
c0ebe874 11605 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
f2ae14a1
RS
11606 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11607 breg);
11608 ep->X_add_number += 4;
c0ebe874 11609 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
f2ae14a1
RS
11610 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11611 breg);
11612 }
11613 break;
11614 }
11615
252b5132
RH
11616 if (offset_expr.X_op != O_symbol
11617 && offset_expr.X_op != O_constant)
11618 {
f71d0d44 11619 as_bad (_("Expression too complex"));
252b5132
RH
11620 offset_expr.X_op = O_constant;
11621 }
11622
2051e8c4
MR
11623 if (HAVE_32BIT_ADDRESSES
11624 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
11625 {
11626 char value [32];
11627
11628 sprintf_vma (value, offset_expr.X_add_number);
20e1fcfd 11629 as_bad (_("Number (0x%s) larger than 32 bits"), value);
55e08f71 11630 }
2051e8c4 11631
90ecf173 11632 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
252b5132
RH
11633 {
11634 /* If this is a reference to a GP relative symbol, we want
c0ebe874
RS
11635 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11636 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
252b5132
RH
11637 If we have a base register, we use this
11638 addu $at,$breg,$gp
c0ebe874
RS
11639 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11640 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
252b5132
RH
11641 If this is not a GP relative symbol, we want
11642 lui $at,<sym> (BFD_RELOC_HI16_S)
c0ebe874
RS
11643 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11644 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
11645 If there is a base register, we add it to $at after the
11646 lui instruction. If there is a constant, we always use
11647 the last case. */
39a59cf8
MR
11648 if (offset_expr.X_op == O_symbol
11649 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11650 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11651 {
4d7206a2 11652 relax_start (offset_expr.X_add_symbol);
252b5132
RH
11653 if (breg == 0)
11654 {
c9914766 11655 tempreg = mips_gp_register;
252b5132
RH
11656 }
11657 else
11658 {
67c0d1eb 11659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11660 AT, breg, mips_gp_register);
252b5132 11661 tempreg = AT;
252b5132
RH
11662 used_at = 1;
11663 }
11664
beae10d5 11665 /* Itbl support may require additional care here. */
c0ebe874 11666 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 11667 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
11668 offset_expr.X_add_number += 4;
11669
11670 /* Set mips_optimize to 2 to avoid inserting an
11671 undesired nop. */
11672 hold_mips_optimize = mips_optimize;
11673 mips_optimize = 2;
beae10d5 11674 /* Itbl support may require additional care here. */
c0ebe874 11675 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 11676 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
11677 mips_optimize = hold_mips_optimize;
11678
4d7206a2 11679 relax_switch ();
252b5132 11680
0970e49e 11681 offset_expr.X_add_number -= 4;
252b5132 11682 }
8fc2e39e 11683 used_at = 1;
f2ae14a1
RS
11684 if (offset_high_part (offset_expr.X_add_number, 16)
11685 != offset_high_part (offset_expr.X_add_number + 4, 16))
11686 {
11687 load_address (AT, &offset_expr, &used_at);
11688 offset_expr.X_op = O_constant;
11689 offset_expr.X_add_number = 0;
11690 }
11691 else
11692 macro_build_lui (&offset_expr, AT);
252b5132 11693 if (breg != 0)
67c0d1eb 11694 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 11695 /* Itbl support may require additional care here. */
c0ebe874 11696 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 11697 BFD_RELOC_LO16, AT);
252b5132
RH
11698 /* FIXME: How do we handle overflow here? */
11699 offset_expr.X_add_number += 4;
beae10d5 11700 /* Itbl support may require additional care here. */
c0ebe874 11701 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 11702 BFD_RELOC_LO16, AT);
4d7206a2
RS
11703 if (mips_relax.sequence)
11704 relax_end ();
bdaaa2e1 11705 }
0a44bf69 11706 else if (!mips_big_got)
252b5132 11707 {
252b5132
RH
11708 /* If this is a reference to an external symbol, we want
11709 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11710 nop
c0ebe874
RS
11711 <op> op[0],0($at)
11712 <op> op[0]+1,4($at)
252b5132
RH
11713 Otherwise we want
11714 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11715 nop
c0ebe874
RS
11716 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11717 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
11718 If there is a base register we add it to $at before the
11719 lwc1 instructions. If there is a constant we include it
11720 in the lwc1 instructions. */
11721 used_at = 1;
11722 expr1.X_add_number = offset_expr.X_add_number;
252b5132
RH
11723 if (expr1.X_add_number < -0x8000
11724 || expr1.X_add_number >= 0x8000 - 4)
11725 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 11726 load_got_offset (AT, &offset_expr);
269137b2 11727 load_delay_nop ();
252b5132 11728 if (breg != 0)
67c0d1eb 11729 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
252b5132
RH
11730
11731 /* Set mips_optimize to 2 to avoid inserting an undesired
11732 nop. */
11733 hold_mips_optimize = mips_optimize;
11734 mips_optimize = 2;
4d7206a2 11735
beae10d5 11736 /* Itbl support may require additional care here. */
4d7206a2 11737 relax_start (offset_expr.X_add_symbol);
c0ebe874 11738 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 11739 BFD_RELOC_LO16, AT);
4d7206a2 11740 expr1.X_add_number += 4;
c0ebe874 11741 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 11742 BFD_RELOC_LO16, AT);
4d7206a2 11743 relax_switch ();
c0ebe874 11744 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 11745 BFD_RELOC_LO16, AT);
4d7206a2 11746 offset_expr.X_add_number += 4;
c0ebe874 11747 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 11748 BFD_RELOC_LO16, AT);
4d7206a2 11749 relax_end ();
252b5132 11750
4d7206a2 11751 mips_optimize = hold_mips_optimize;
252b5132 11752 }
0a44bf69 11753 else if (mips_big_got)
252b5132 11754 {
67c0d1eb 11755 int gpdelay;
252b5132
RH
11756
11757 /* If this is a reference to an external symbol, we want
11758 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11759 addu $at,$at,$gp
11760 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11761 nop
c0ebe874
RS
11762 <op> op[0],0($at)
11763 <op> op[0]+1,4($at)
252b5132
RH
11764 Otherwise we want
11765 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11766 nop
c0ebe874
RS
11767 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11768 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
11769 If there is a base register we add it to $at before the
11770 lwc1 instructions. If there is a constant we include it
11771 in the lwc1 instructions. */
11772 used_at = 1;
11773 expr1.X_add_number = offset_expr.X_add_number;
11774 offset_expr.X_add_number = 0;
11775 if (expr1.X_add_number < -0x8000
11776 || expr1.X_add_number >= 0x8000 - 4)
11777 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 11778 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 11779 relax_start (offset_expr.X_add_symbol);
df58fc94 11780 macro_build (&offset_expr, "lui", LUI_FMT,
67c0d1eb
RS
11781 AT, BFD_RELOC_MIPS_GOT_HI16);
11782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11783 AT, AT, mips_gp_register);
67c0d1eb 11784 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 11785 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
269137b2 11786 load_delay_nop ();
252b5132 11787 if (breg != 0)
67c0d1eb 11788 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 11789 /* Itbl support may require additional care here. */
c0ebe874 11790 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 11791 BFD_RELOC_LO16, AT);
252b5132
RH
11792 expr1.X_add_number += 4;
11793
11794 /* Set mips_optimize to 2 to avoid inserting an undesired
11795 nop. */
11796 hold_mips_optimize = mips_optimize;
11797 mips_optimize = 2;
beae10d5 11798 /* Itbl support may require additional care here. */
c0ebe874 11799 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 11800 BFD_RELOC_LO16, AT);
252b5132
RH
11801 mips_optimize = hold_mips_optimize;
11802 expr1.X_add_number -= 4;
11803
4d7206a2
RS
11804 relax_switch ();
11805 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
11806 if (gpdelay)
11807 macro_build (NULL, "nop", "");
11808 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11809 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 11810 load_delay_nop ();
252b5132 11811 if (breg != 0)
67c0d1eb 11812 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 11813 /* Itbl support may require additional care here. */
c0ebe874 11814 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 11815 BFD_RELOC_LO16, AT);
4d7206a2 11816 offset_expr.X_add_number += 4;
252b5132
RH
11817
11818 /* Set mips_optimize to 2 to avoid inserting an undesired
11819 nop. */
11820 hold_mips_optimize = mips_optimize;
11821 mips_optimize = 2;
beae10d5 11822 /* Itbl support may require additional care here. */
c0ebe874 11823 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 11824 BFD_RELOC_LO16, AT);
252b5132 11825 mips_optimize = hold_mips_optimize;
4d7206a2 11826 relax_end ();
252b5132 11827 }
252b5132
RH
11828 else
11829 abort ();
11830
252b5132 11831 break;
dd6a37e7
AP
11832
11833 case M_SAA_AB:
dd6a37e7 11834 s = "saa";
7f3c4072 11835 offbits = 0;
dd6a37e7
AP
11836 fmt = "t,(b)";
11837 goto ld_st;
11838 case M_SAAD_AB:
dd6a37e7 11839 s = "saad";
7f3c4072 11840 offbits = 0;
dd6a37e7
AP
11841 fmt = "t,(b)";
11842 goto ld_st;
11843
252b5132
RH
11844 /* New code added to support COPZ instructions.
11845 This code builds table entries out of the macros in mip_opcodes.
11846 R4000 uses interlocks to handle coproc delays.
11847 Other chips (like the R3000) require nops to be inserted for delays.
11848
f72c8c98 11849 FIXME: Currently, we require that the user handle delays.
252b5132
RH
11850 In order to fill delay slots for non-interlocked chips,
11851 we must have a way to specify delays based on the coprocessor.
11852 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11853 What are the side-effects of the cop instruction?
11854 What cache support might we have and what are its effects?
11855 Both coprocessor & memory require delays. how long???
bdaaa2e1 11856 What registers are read/set/modified?
252b5132
RH
11857
11858 If an itbl is provided to interpret cop instructions,
bdaaa2e1 11859 this knowledge can be encoded in the itbl spec. */
252b5132
RH
11860
11861 case M_COP0:
11862 s = "c0";
11863 goto copz;
11864 case M_COP1:
11865 s = "c1";
11866 goto copz;
11867 case M_COP2:
11868 s = "c2";
11869 goto copz;
11870 case M_COP3:
11871 s = "c3";
11872 copz:
df58fc94 11873 gas_assert (!mips_opts.micromips);
252b5132
RH
11874 /* For now we just do C (same as Cz). The parameter will be
11875 stored in insn_opcode by mips_ip. */
c8276761 11876 macro_build (NULL, s, "C", (int) ip->insn_opcode);
8fc2e39e 11877 break;
252b5132 11878
ea1fb5dc 11879 case M_MOVE:
c0ebe874 11880 move_register (op[0], op[1]);
8fc2e39e 11881 break;
ea1fb5dc 11882
833794fc
MR
11883 case M_MOVEP:
11884 gas_assert (mips_opts.micromips);
11885 gas_assert (mips_opts.insn32);
c0ebe874
RS
11886 move_register (micromips_to_32_reg_h_map1[op[0]],
11887 micromips_to_32_reg_m_map[op[1]]);
11888 move_register (micromips_to_32_reg_h_map2[op[0]],
11889 micromips_to_32_reg_n_map[op[2]]);
833794fc
MR
11890 break;
11891
252b5132
RH
11892 case M_DMUL:
11893 dbl = 1;
11894 case M_MUL:
e407c74b 11895 if (mips_opts.arch == CPU_R5900)
c0ebe874
RS
11896 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
11897 op[2]);
e407c74b
NC
11898 else
11899 {
c0ebe874
RS
11900 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
11901 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
e407c74b 11902 }
8fc2e39e 11903 break;
252b5132
RH
11904
11905 case M_DMUL_I:
11906 dbl = 1;
11907 case M_MUL_I:
11908 /* The MIPS assembler some times generates shifts and adds. I'm
11909 not trying to be that fancy. GCC should do this for us
11910 anyway. */
8fc2e39e 11911 used_at = 1;
67c0d1eb 11912 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
11913 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
11914 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132
RH
11915 break;
11916
11917 case M_DMULO_I:
11918 dbl = 1;
11919 case M_MULO_I:
11920 imm = 1;
11921 goto do_mulo;
11922
11923 case M_DMULO:
11924 dbl = 1;
11925 case M_MULO:
11926 do_mulo:
7d10b47d 11927 start_noreorder ();
8fc2e39e 11928 used_at = 1;
252b5132 11929 if (imm)
67c0d1eb 11930 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
11931 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
11932 op[1], imm ? AT : op[2]);
11933 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11934 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
df58fc94 11935 macro_build (NULL, "mfhi", MFHL_FMT, AT);
252b5132 11936 if (mips_trap)
c0ebe874 11937 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
252b5132
RH
11938 else
11939 {
df58fc94
RS
11940 if (mips_opts.micromips)
11941 micromips_label_expr (&label_expr);
11942 else
11943 label_expr.X_add_number = 8;
c0ebe874 11944 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
a605d2b3 11945 macro_build (NULL, "nop", "");
df58fc94
RS
11946 macro_build (NULL, "break", BRK_FMT, 6);
11947 if (mips_opts.micromips)
11948 micromips_add_label ();
252b5132 11949 }
7d10b47d 11950 end_noreorder ();
c0ebe874 11951 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132
RH
11952 break;
11953
11954 case M_DMULOU_I:
11955 dbl = 1;
11956 case M_MULOU_I:
11957 imm = 1;
11958 goto do_mulou;
11959
11960 case M_DMULOU:
11961 dbl = 1;
11962 case M_MULOU:
11963 do_mulou:
7d10b47d 11964 start_noreorder ();
8fc2e39e 11965 used_at = 1;
252b5132 11966 if (imm)
67c0d1eb
RS
11967 load_register (AT, &imm_expr, dbl);
11968 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
c0ebe874 11969 op[1], imm ? AT : op[2]);
df58fc94 11970 macro_build (NULL, "mfhi", MFHL_FMT, AT);
c0ebe874 11971 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132 11972 if (mips_trap)
df58fc94 11973 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
252b5132
RH
11974 else
11975 {
df58fc94
RS
11976 if (mips_opts.micromips)
11977 micromips_label_expr (&label_expr);
11978 else
11979 label_expr.X_add_number = 8;
11980 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
a605d2b3 11981 macro_build (NULL, "nop", "");
df58fc94
RS
11982 macro_build (NULL, "break", BRK_FMT, 6);
11983 if (mips_opts.micromips)
11984 micromips_add_label ();
252b5132 11985 }
7d10b47d 11986 end_noreorder ();
252b5132
RH
11987 break;
11988
771c7ce4 11989 case M_DROL:
fef14a42 11990 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 11991 {
c0ebe874 11992 if (op[0] == op[1])
82dd0097
CD
11993 {
11994 tempreg = AT;
11995 used_at = 1;
11996 }
11997 else
c0ebe874
RS
11998 tempreg = op[0];
11999 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12000 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
8fc2e39e 12001 break;
82dd0097 12002 }
8fc2e39e 12003 used_at = 1;
c0ebe874
RS
12004 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12005 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12006 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12007 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12008 break;
12009
252b5132 12010 case M_ROL:
fef14a42 12011 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12012 {
c0ebe874 12013 if (op[0] == op[1])
82dd0097
CD
12014 {
12015 tempreg = AT;
12016 used_at = 1;
12017 }
12018 else
c0ebe874
RS
12019 tempreg = op[0];
12020 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12021 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
8fc2e39e 12022 break;
82dd0097 12023 }
8fc2e39e 12024 used_at = 1;
c0ebe874
RS
12025 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12026 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12027 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12028 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12029 break;
12030
771c7ce4
TS
12031 case M_DROL_I:
12032 {
12033 unsigned int rot;
91d6fa6a
NC
12034 char *l;
12035 char *rr;
771c7ce4
TS
12036
12037 if (imm_expr.X_op != O_constant)
82dd0097 12038 as_bad (_("Improper rotate count"));
771c7ce4 12039 rot = imm_expr.X_add_number & 0x3f;
fef14a42 12040 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
60b63b72
RS
12041 {
12042 rot = (64 - rot) & 0x3f;
12043 if (rot >= 32)
c0ebe874 12044 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
60b63b72 12045 else
c0ebe874 12046 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12047 break;
60b63b72 12048 }
483fc7cd 12049 if (rot == 0)
483fc7cd 12050 {
c0ebe874 12051 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12052 break;
483fc7cd 12053 }
82dd0097 12054 l = (rot < 0x20) ? "dsll" : "dsll32";
91d6fa6a 12055 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
82dd0097 12056 rot &= 0x1f;
8fc2e39e 12057 used_at = 1;
c0ebe874
RS
12058 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12059 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12060 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12061 }
12062 break;
12063
252b5132 12064 case M_ROL_I:
771c7ce4
TS
12065 {
12066 unsigned int rot;
12067
12068 if (imm_expr.X_op != O_constant)
82dd0097 12069 as_bad (_("Improper rotate count"));
771c7ce4 12070 rot = imm_expr.X_add_number & 0x1f;
fef14a42 12071 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
60b63b72 12072 {
c0ebe874
RS
12073 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12074 (32 - rot) & 0x1f);
8fc2e39e 12075 break;
60b63b72 12076 }
483fc7cd 12077 if (rot == 0)
483fc7cd 12078 {
c0ebe874 12079 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12080 break;
483fc7cd 12081 }
8fc2e39e 12082 used_at = 1;
c0ebe874
RS
12083 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12084 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12085 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12086 }
12087 break;
12088
12089 case M_DROR:
fef14a42 12090 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 12091 {
c0ebe874 12092 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
8fc2e39e 12093 break;
82dd0097 12094 }
8fc2e39e 12095 used_at = 1;
c0ebe874
RS
12096 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12097 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12098 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12099 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12100 break;
12101
12102 case M_ROR:
fef14a42 12103 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12104 {
c0ebe874 12105 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
8fc2e39e 12106 break;
82dd0097 12107 }
8fc2e39e 12108 used_at = 1;
c0ebe874
RS
12109 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12110 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12111 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12112 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12113 break;
12114
771c7ce4
TS
12115 case M_DROR_I:
12116 {
12117 unsigned int rot;
91d6fa6a
NC
12118 char *l;
12119 char *rr;
771c7ce4
TS
12120
12121 if (imm_expr.X_op != O_constant)
82dd0097 12122 as_bad (_("Improper rotate count"));
771c7ce4 12123 rot = imm_expr.X_add_number & 0x3f;
fef14a42 12124 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097
CD
12125 {
12126 if (rot >= 32)
c0ebe874 12127 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
82dd0097 12128 else
c0ebe874 12129 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12130 break;
82dd0097 12131 }
483fc7cd 12132 if (rot == 0)
483fc7cd 12133 {
c0ebe874 12134 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12135 break;
483fc7cd 12136 }
91d6fa6a 12137 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
82dd0097
CD
12138 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12139 rot &= 0x1f;
8fc2e39e 12140 used_at = 1;
c0ebe874
RS
12141 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12142 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12143 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12144 }
12145 break;
12146
252b5132 12147 case M_ROR_I:
771c7ce4
TS
12148 {
12149 unsigned int rot;
12150
12151 if (imm_expr.X_op != O_constant)
82dd0097 12152 as_bad (_("Improper rotate count"));
771c7ce4 12153 rot = imm_expr.X_add_number & 0x1f;
fef14a42 12154 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12155 {
c0ebe874 12156 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12157 break;
82dd0097 12158 }
483fc7cd 12159 if (rot == 0)
483fc7cd 12160 {
c0ebe874 12161 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12162 break;
483fc7cd 12163 }
8fc2e39e 12164 used_at = 1;
c0ebe874
RS
12165 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12166 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12167 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4 12168 }
252b5132
RH
12169 break;
12170
252b5132 12171 case M_SEQ:
c0ebe874
RS
12172 if (op[1] == 0)
12173 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12174 else if (op[2] == 0)
12175 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
12176 else
12177 {
c0ebe874
RS
12178 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12179 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
252b5132 12180 }
8fc2e39e 12181 break;
252b5132
RH
12182
12183 case M_SEQ_I:
12184 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
12185 {
c0ebe874 12186 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 12187 break;
252b5132 12188 }
c0ebe874 12189 if (op[1] == 0)
252b5132
RH
12190 {
12191 as_warn (_("Instruction %s: result is always false"),
12192 ip->insn_mo->name);
c0ebe874 12193 move_register (op[0], 0);
8fc2e39e 12194 break;
252b5132 12195 }
dd3cbb7e
NC
12196 if (CPU_HAS_SEQ (mips_opts.arch)
12197 && -512 <= imm_expr.X_add_number
12198 && imm_expr.X_add_number < 512)
12199 {
c0ebe874 12200 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
750bdd57 12201 (int) imm_expr.X_add_number);
dd3cbb7e
NC
12202 break;
12203 }
252b5132
RH
12204 if (imm_expr.X_op == O_constant
12205 && imm_expr.X_add_number >= 0
12206 && imm_expr.X_add_number < 0x10000)
c0ebe874 12207 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
12208 else if (imm_expr.X_op == O_constant
12209 && imm_expr.X_add_number > -0x8000
12210 && imm_expr.X_add_number < 0)
12211 {
12212 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 12213 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
c0ebe874 12214 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132 12215 }
dd3cbb7e
NC
12216 else if (CPU_HAS_SEQ (mips_opts.arch))
12217 {
12218 used_at = 1;
12219 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12220 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
dd3cbb7e
NC
12221 break;
12222 }
252b5132
RH
12223 else
12224 {
67c0d1eb 12225 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12226 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
252b5132
RH
12227 used_at = 1;
12228 }
c0ebe874 12229 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12230 break;
252b5132 12231
c0ebe874 12232 case M_SGE: /* X >= Y <==> not (X < Y) */
252b5132
RH
12233 s = "slt";
12234 goto sge;
12235 case M_SGEU:
12236 s = "sltu";
12237 sge:
c0ebe874
RS
12238 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12239 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12240 break;
252b5132 12241
c0ebe874 12242 case M_SGE_I: /* X >= I <==> not (X < I) */
252b5132
RH
12243 case M_SGEU_I:
12244 if (imm_expr.X_op == O_constant
12245 && imm_expr.X_add_number >= -0x8000
12246 && imm_expr.X_add_number < 0x8000)
c0ebe874
RS
12247 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12248 op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
12249 else
12250 {
67c0d1eb
RS
12251 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12252 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
c0ebe874 12253 op[0], op[1], AT);
252b5132
RH
12254 used_at = 1;
12255 }
c0ebe874 12256 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12257 break;
252b5132 12258
c0ebe874 12259 case M_SGT: /* X > Y <==> Y < X */
252b5132
RH
12260 s = "slt";
12261 goto sgt;
12262 case M_SGTU:
12263 s = "sltu";
12264 sgt:
c0ebe874 12265 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
8fc2e39e 12266 break;
252b5132 12267
c0ebe874 12268 case M_SGT_I: /* X > I <==> I < X */
252b5132
RH
12269 s = "slt";
12270 goto sgti;
12271 case M_SGTU_I:
12272 s = "sltu";
12273 sgti:
8fc2e39e 12274 used_at = 1;
67c0d1eb 12275 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12276 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
252b5132
RH
12277 break;
12278
c0ebe874 12279 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
252b5132
RH
12280 s = "slt";
12281 goto sle;
12282 case M_SLEU:
12283 s = "sltu";
12284 sle:
c0ebe874
RS
12285 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12286 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 12287 break;
252b5132 12288
c0ebe874 12289 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
252b5132
RH
12290 s = "slt";
12291 goto slei;
12292 case M_SLEU_I:
12293 s = "sltu";
12294 slei:
8fc2e39e 12295 used_at = 1;
67c0d1eb 12296 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874
RS
12297 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12298 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
252b5132
RH
12299 break;
12300
12301 case M_SLT_I:
12302 if (imm_expr.X_op == O_constant
12303 && imm_expr.X_add_number >= -0x8000
12304 && imm_expr.X_add_number < 0x8000)
12305 {
c0ebe874
RS
12306 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12307 BFD_RELOC_LO16);
8fc2e39e 12308 break;
252b5132 12309 }
8fc2e39e 12310 used_at = 1;
67c0d1eb 12311 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12312 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
252b5132
RH
12313 break;
12314
12315 case M_SLTU_I:
12316 if (imm_expr.X_op == O_constant
12317 && imm_expr.X_add_number >= -0x8000
12318 && imm_expr.X_add_number < 0x8000)
12319 {
c0ebe874 12320 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
17a2f251 12321 BFD_RELOC_LO16);
8fc2e39e 12322 break;
252b5132 12323 }
8fc2e39e 12324 used_at = 1;
67c0d1eb 12325 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12326 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
252b5132
RH
12327 break;
12328
12329 case M_SNE:
c0ebe874
RS
12330 if (op[1] == 0)
12331 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12332 else if (op[2] == 0)
12333 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
252b5132
RH
12334 else
12335 {
c0ebe874
RS
12336 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12337 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
252b5132 12338 }
8fc2e39e 12339 break;
252b5132
RH
12340
12341 case M_SNE_I:
12342 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
12343 {
c0ebe874 12344 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
8fc2e39e 12345 break;
252b5132 12346 }
c0ebe874 12347 if (op[1] == 0)
252b5132
RH
12348 {
12349 as_warn (_("Instruction %s: result is always true"),
12350 ip->insn_mo->name);
67c0d1eb 12351 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
c0ebe874 12352 op[0], 0, BFD_RELOC_LO16);
8fc2e39e 12353 break;
252b5132 12354 }
dd3cbb7e
NC
12355 if (CPU_HAS_SEQ (mips_opts.arch)
12356 && -512 <= imm_expr.X_add_number
12357 && imm_expr.X_add_number < 512)
12358 {
c0ebe874 12359 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
750bdd57 12360 (int) imm_expr.X_add_number);
dd3cbb7e
NC
12361 break;
12362 }
252b5132
RH
12363 if (imm_expr.X_op == O_constant
12364 && imm_expr.X_add_number >= 0
12365 && imm_expr.X_add_number < 0x10000)
12366 {
c0ebe874
RS
12367 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
12368 BFD_RELOC_LO16);
252b5132
RH
12369 }
12370 else if (imm_expr.X_op == O_constant
12371 && imm_expr.X_add_number > -0x8000
12372 && imm_expr.X_add_number < 0)
12373 {
12374 imm_expr.X_add_number = -imm_expr.X_add_number;
67c0d1eb 12375 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
c0ebe874 12376 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132 12377 }
dd3cbb7e
NC
12378 else if (CPU_HAS_SEQ (mips_opts.arch))
12379 {
12380 used_at = 1;
12381 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12382 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
dd3cbb7e
NC
12383 break;
12384 }
252b5132
RH
12385 else
12386 {
67c0d1eb 12387 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12388 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
252b5132
RH
12389 used_at = 1;
12390 }
c0ebe874 12391 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
8fc2e39e 12392 break;
252b5132 12393
df58fc94
RS
12394 case M_SUB_I:
12395 s = "addi";
12396 s2 = "sub";
12397 goto do_subi;
12398 case M_SUBU_I:
12399 s = "addiu";
12400 s2 = "subu";
12401 goto do_subi;
252b5132
RH
12402 case M_DSUB_I:
12403 dbl = 1;
df58fc94
RS
12404 s = "daddi";
12405 s2 = "dsub";
12406 if (!mips_opts.micromips)
12407 goto do_subi;
252b5132 12408 if (imm_expr.X_op == O_constant
df58fc94
RS
12409 && imm_expr.X_add_number > -0x200
12410 && imm_expr.X_add_number <= 0x200)
252b5132 12411 {
c0ebe874 12412 macro_build (NULL, s, "t,r,.", op[0], op[1], -imm_expr.X_add_number);
8fc2e39e 12413 break;
252b5132 12414 }
df58fc94 12415 goto do_subi_i;
252b5132
RH
12416 case M_DSUBU_I:
12417 dbl = 1;
df58fc94
RS
12418 s = "daddiu";
12419 s2 = "dsubu";
12420 do_subi:
252b5132
RH
12421 if (imm_expr.X_op == O_constant
12422 && imm_expr.X_add_number > -0x8000
12423 && imm_expr.X_add_number <= 0x8000)
12424 {
12425 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 12426 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 12427 break;
252b5132 12428 }
df58fc94 12429 do_subi_i:
8fc2e39e 12430 used_at = 1;
67c0d1eb 12431 load_register (AT, &imm_expr, dbl);
c0ebe874 12432 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
12433 break;
12434
12435 case M_TEQ_I:
12436 s = "teq";
12437 goto trap;
12438 case M_TGE_I:
12439 s = "tge";
12440 goto trap;
12441 case M_TGEU_I:
12442 s = "tgeu";
12443 goto trap;
12444 case M_TLT_I:
12445 s = "tlt";
12446 goto trap;
12447 case M_TLTU_I:
12448 s = "tltu";
12449 goto trap;
12450 case M_TNE_I:
12451 s = "tne";
12452 trap:
8fc2e39e 12453 used_at = 1;
67c0d1eb 12454 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
c0ebe874 12455 macro_build (NULL, s, "s,t", op[0], AT);
252b5132
RH
12456 break;
12457
252b5132 12458 case M_TRUNCWS:
43841e91 12459 case M_TRUNCWD:
df58fc94 12460 gas_assert (!mips_opts.micromips);
0aa27725 12461 gas_assert (mips_opts.isa == ISA_MIPS1);
8fc2e39e 12462 used_at = 1;
252b5132
RH
12463
12464 /*
12465 * Is the double cfc1 instruction a bug in the mips assembler;
12466 * or is there a reason for it?
12467 */
7d10b47d 12468 start_noreorder ();
c0ebe874
RS
12469 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12470 macro_build (NULL, "cfc1", "t,G", op[2], RA);
67c0d1eb 12471 macro_build (NULL, "nop", "");
252b5132 12472 expr1.X_add_number = 3;
c0ebe874 12473 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
252b5132 12474 expr1.X_add_number = 2;
67c0d1eb
RS
12475 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
12476 macro_build (NULL, "ctc1", "t,G", AT, RA);
12477 macro_build (NULL, "nop", "");
12478 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
c0ebe874
RS
12479 op[0], op[1]);
12480 macro_build (NULL, "ctc1", "t,G", op[2], RA);
67c0d1eb 12481 macro_build (NULL, "nop", "");
7d10b47d 12482 end_noreorder ();
252b5132
RH
12483 break;
12484
f2ae14a1 12485 case M_ULH_AB:
252b5132 12486 s = "lb";
df58fc94
RS
12487 s2 = "lbu";
12488 off = 1;
12489 goto uld_st;
f2ae14a1 12490 case M_ULHU_AB:
252b5132 12491 s = "lbu";
df58fc94
RS
12492 s2 = "lbu";
12493 off = 1;
12494 goto uld_st;
f2ae14a1 12495 case M_ULW_AB:
df58fc94
RS
12496 s = "lwl";
12497 s2 = "lwr";
7f3c4072 12498 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
12499 off = 3;
12500 goto uld_st;
f2ae14a1 12501 case M_ULD_AB:
252b5132
RH
12502 s = "ldl";
12503 s2 = "ldr";
7f3c4072 12504 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 12505 off = 7;
df58fc94 12506 goto uld_st;
f2ae14a1 12507 case M_USH_AB:
df58fc94
RS
12508 s = "sb";
12509 s2 = "sb";
12510 off = 1;
12511 ust = 1;
12512 goto uld_st;
f2ae14a1 12513 case M_USW_AB:
df58fc94
RS
12514 s = "swl";
12515 s2 = "swr";
7f3c4072 12516 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 12517 off = 3;
df58fc94
RS
12518 ust = 1;
12519 goto uld_st;
f2ae14a1 12520 case M_USD_AB:
df58fc94
RS
12521 s = "sdl";
12522 s2 = "sdr";
7f3c4072 12523 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
12524 off = 7;
12525 ust = 1;
12526
12527 uld_st:
c0ebe874 12528 breg = op[2];
f2ae14a1 12529 large_offset = !small_offset_p (off, align, offbits);
df58fc94
RS
12530 ep = &offset_expr;
12531 expr1.X_add_number = 0;
f2ae14a1 12532 if (large_offset)
df58fc94
RS
12533 {
12534 used_at = 1;
12535 tempreg = AT;
f2ae14a1
RS
12536 if (small_offset_p (0, align, 16))
12537 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
12538 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
12539 else
12540 {
12541 load_address (tempreg, ep, &used_at);
12542 if (breg != 0)
12543 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12544 tempreg, tempreg, breg);
12545 }
12546 offset_reloc[0] = BFD_RELOC_LO16;
12547 offset_reloc[1] = BFD_RELOC_UNUSED;
12548 offset_reloc[2] = BFD_RELOC_UNUSED;
df58fc94 12549 breg = tempreg;
c0ebe874 12550 tempreg = op[0];
df58fc94
RS
12551 ep = &expr1;
12552 }
c0ebe874 12553 else if (!ust && op[0] == breg)
8fc2e39e
TS
12554 {
12555 used_at = 1;
12556 tempreg = AT;
12557 }
252b5132 12558 else
c0ebe874 12559 tempreg = op[0];
af22f5b2 12560
df58fc94
RS
12561 if (off == 1)
12562 goto ulh_sh;
252b5132 12563
90ecf173 12564 if (!target_big_endian)
df58fc94 12565 ep->X_add_number += off;
f2ae14a1 12566 if (offbits == 12)
c8276761 12567 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
12568 else
12569 macro_build (ep, s, "t,o(b)", tempreg, -1,
12570 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94 12571
90ecf173 12572 if (!target_big_endian)
df58fc94 12573 ep->X_add_number -= off;
252b5132 12574 else
df58fc94 12575 ep->X_add_number += off;
f2ae14a1 12576 if (offbits == 12)
df58fc94 12577 macro_build (NULL, s2, "t,~(b)",
c8276761 12578 tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
12579 else
12580 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12581 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 12582
df58fc94 12583 /* If necessary, move the result in tempreg to the final destination. */
c0ebe874 12584 if (!ust && op[0] != tempreg)
df58fc94
RS
12585 {
12586 /* Protect second load's delay slot. */
12587 load_delay_nop ();
c0ebe874 12588 move_register (op[0], tempreg);
df58fc94 12589 }
8fc2e39e 12590 break;
252b5132 12591
df58fc94 12592 ulh_sh:
d6bc6245 12593 used_at = 1;
df58fc94
RS
12594 if (target_big_endian == ust)
12595 ep->X_add_number += off;
c0ebe874 12596 tempreg = ust || large_offset ? op[0] : AT;
f2ae14a1
RS
12597 macro_build (ep, s, "t,o(b)", tempreg, -1,
12598 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94
RS
12599
12600 /* For halfword transfers we need a temporary register to shuffle
12601 bytes. Unfortunately for M_USH_A we have none available before
12602 the next store as AT holds the base address. We deal with this
12603 case by clobbering TREG and then restoring it as with ULH. */
c0ebe874 12604 tempreg = ust == large_offset ? op[0] : AT;
df58fc94 12605 if (ust)
c0ebe874 12606 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
df58fc94
RS
12607
12608 if (target_big_endian == ust)
12609 ep->X_add_number -= off;
252b5132 12610 else
df58fc94 12611 ep->X_add_number += off;
f2ae14a1
RS
12612 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12613 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 12614
df58fc94 12615 /* For M_USH_A re-retrieve the LSB. */
f2ae14a1 12616 if (ust && large_offset)
df58fc94
RS
12617 {
12618 if (target_big_endian)
12619 ep->X_add_number += off;
12620 else
12621 ep->X_add_number -= off;
f2ae14a1
RS
12622 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
12623 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
df58fc94
RS
12624 }
12625 /* For ULH and M_USH_A OR the LSB in. */
f2ae14a1 12626 if (!ust || large_offset)
df58fc94 12627 {
c0ebe874 12628 tempreg = !large_offset ? AT : op[0];
df58fc94 12629 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
c0ebe874 12630 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
df58fc94 12631 }
252b5132
RH
12632 break;
12633
12634 default:
12635 /* FIXME: Check if this is one of the itbl macros, since they
bdaaa2e1 12636 are added dynamically. */
252b5132
RH
12637 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
12638 break;
12639 }
741fe287 12640 if (!mips_opts.at && used_at)
8fc2e39e 12641 as_bad (_("Macro used $at after \".set noat\""));
252b5132
RH
12642}
12643
12644/* Implement macros in mips16 mode. */
12645
12646static void
17a2f251 12647mips16_macro (struct mips_cl_insn *ip)
252b5132 12648{
c0ebe874 12649 const struct mips_operand_array *operands;
252b5132 12650 int mask;
c0ebe874 12651 int tmp;
252b5132
RH
12652 expressionS expr1;
12653 int dbl;
12654 const char *s, *s2, *s3;
c0ebe874
RS
12655 unsigned int op[MAX_OPERANDS];
12656 unsigned int i;
252b5132
RH
12657
12658 mask = ip->insn_mo->mask;
12659
c0ebe874
RS
12660 operands = insn_operands (ip);
12661 for (i = 0; i < MAX_OPERANDS; i++)
12662 if (operands->operand[i])
12663 op[i] = insn_extract_operand (ip, operands->operand[i]);
12664 else
12665 op[i] = -1;
252b5132 12666
252b5132
RH
12667 expr1.X_op = O_constant;
12668 expr1.X_op_symbol = NULL;
12669 expr1.X_add_symbol = NULL;
12670 expr1.X_add_number = 1;
12671
12672 dbl = 0;
12673
12674 switch (mask)
12675 {
12676 default:
b37df7c4 12677 abort ();
252b5132
RH
12678
12679 case M_DDIV_3:
12680 dbl = 1;
12681 case M_DIV_3:
12682 s = "mflo";
12683 goto do_div3;
12684 case M_DREM_3:
12685 dbl = 1;
12686 case M_REM_3:
12687 s = "mfhi";
12688 do_div3:
7d10b47d 12689 start_noreorder ();
c0ebe874 12690 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
252b5132 12691 expr1.X_add_number = 2;
c0ebe874 12692 macro_build (&expr1, "bnez", "x,p", op[2]);
67c0d1eb 12693 macro_build (NULL, "break", "6", 7);
bdaaa2e1 12694
252b5132
RH
12695 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12696 since that causes an overflow. We should do that as well,
12697 but I don't see how to do the comparisons without a temporary
12698 register. */
7d10b47d 12699 end_noreorder ();
c0ebe874 12700 macro_build (NULL, s, "x", op[0]);
252b5132
RH
12701 break;
12702
12703 case M_DIVU_3:
12704 s = "divu";
12705 s2 = "mflo";
12706 goto do_divu3;
12707 case M_REMU_3:
12708 s = "divu";
12709 s2 = "mfhi";
12710 goto do_divu3;
12711 case M_DDIVU_3:
12712 s = "ddivu";
12713 s2 = "mflo";
12714 goto do_divu3;
12715 case M_DREMU_3:
12716 s = "ddivu";
12717 s2 = "mfhi";
12718 do_divu3:
7d10b47d 12719 start_noreorder ();
c0ebe874 12720 macro_build (NULL, s, "0,x,y", op[1], op[2]);
252b5132 12721 expr1.X_add_number = 2;
c0ebe874 12722 macro_build (&expr1, "bnez", "x,p", op[2]);
67c0d1eb 12723 macro_build (NULL, "break", "6", 7);
7d10b47d 12724 end_noreorder ();
c0ebe874 12725 macro_build (NULL, s2, "x", op[0]);
252b5132
RH
12726 break;
12727
12728 case M_DMUL:
12729 dbl = 1;
12730 case M_MUL:
c0ebe874
RS
12731 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
12732 macro_build (NULL, "mflo", "x", op[0]);
8fc2e39e 12733 break;
252b5132
RH
12734
12735 case M_DSUBU_I:
12736 dbl = 1;
12737 goto do_subu;
12738 case M_SUBU_I:
12739 do_subu:
12740 if (imm_expr.X_op != O_constant)
12741 as_bad (_("Unsupported large constant"));
12742 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 12743 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
252b5132
RH
12744 break;
12745
12746 case M_SUBU_I_2:
12747 if (imm_expr.X_op != O_constant)
12748 as_bad (_("Unsupported large constant"));
12749 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 12750 macro_build (&imm_expr, "addiu", "x,k", op[0]);
252b5132
RH
12751 break;
12752
12753 case M_DSUBU_I_2:
12754 if (imm_expr.X_op != O_constant)
12755 as_bad (_("Unsupported large constant"));
12756 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 12757 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
252b5132
RH
12758 break;
12759
12760 case M_BEQ:
12761 s = "cmp";
12762 s2 = "bteqz";
12763 goto do_branch;
12764 case M_BNE:
12765 s = "cmp";
12766 s2 = "btnez";
12767 goto do_branch;
12768 case M_BLT:
12769 s = "slt";
12770 s2 = "btnez";
12771 goto do_branch;
12772 case M_BLTU:
12773 s = "sltu";
12774 s2 = "btnez";
12775 goto do_branch;
12776 case M_BLE:
12777 s = "slt";
12778 s2 = "bteqz";
12779 goto do_reverse_branch;
12780 case M_BLEU:
12781 s = "sltu";
12782 s2 = "bteqz";
12783 goto do_reverse_branch;
12784 case M_BGE:
12785 s = "slt";
12786 s2 = "bteqz";
12787 goto do_branch;
12788 case M_BGEU:
12789 s = "sltu";
12790 s2 = "bteqz";
12791 goto do_branch;
12792 case M_BGT:
12793 s = "slt";
12794 s2 = "btnez";
12795 goto do_reverse_branch;
12796 case M_BGTU:
12797 s = "sltu";
12798 s2 = "btnez";
12799
12800 do_reverse_branch:
c0ebe874
RS
12801 tmp = op[1];
12802 op[1] = op[0];
12803 op[0] = tmp;
252b5132
RH
12804
12805 do_branch:
c0ebe874 12806 macro_build (NULL, s, "x,y", op[0], op[1]);
67c0d1eb 12807 macro_build (&offset_expr, s2, "p");
252b5132
RH
12808 break;
12809
12810 case M_BEQ_I:
12811 s = "cmpi";
12812 s2 = "bteqz";
12813 s3 = "x,U";
12814 goto do_branch_i;
12815 case M_BNE_I:
12816 s = "cmpi";
12817 s2 = "btnez";
12818 s3 = "x,U";
12819 goto do_branch_i;
12820 case M_BLT_I:
12821 s = "slti";
12822 s2 = "btnez";
12823 s3 = "x,8";
12824 goto do_branch_i;
12825 case M_BLTU_I:
12826 s = "sltiu";
12827 s2 = "btnez";
12828 s3 = "x,8";
12829 goto do_branch_i;
12830 case M_BLE_I:
12831 s = "slti";
12832 s2 = "btnez";
12833 s3 = "x,8";
12834 goto do_addone_branch_i;
12835 case M_BLEU_I:
12836 s = "sltiu";
12837 s2 = "btnez";
12838 s3 = "x,8";
12839 goto do_addone_branch_i;
12840 case M_BGE_I:
12841 s = "slti";
12842 s2 = "bteqz";
12843 s3 = "x,8";
12844 goto do_branch_i;
12845 case M_BGEU_I:
12846 s = "sltiu";
12847 s2 = "bteqz";
12848 s3 = "x,8";
12849 goto do_branch_i;
12850 case M_BGT_I:
12851 s = "slti";
12852 s2 = "bteqz";
12853 s3 = "x,8";
12854 goto do_addone_branch_i;
12855 case M_BGTU_I:
12856 s = "sltiu";
12857 s2 = "bteqz";
12858 s3 = "x,8";
12859
12860 do_addone_branch_i:
12861 if (imm_expr.X_op != O_constant)
12862 as_bad (_("Unsupported large constant"));
12863 ++imm_expr.X_add_number;
12864
12865 do_branch_i:
c0ebe874 12866 macro_build (&imm_expr, s, s3, op[0]);
67c0d1eb 12867 macro_build (&offset_expr, s2, "p");
252b5132
RH
12868 break;
12869
12870 case M_ABS:
12871 expr1.X_add_number = 0;
c0ebe874
RS
12872 macro_build (&expr1, "slti", "x,8", op[1]);
12873 if (op[0] != op[1])
12874 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
252b5132 12875 expr1.X_add_number = 2;
67c0d1eb 12876 macro_build (&expr1, "bteqz", "p");
c0ebe874 12877 macro_build (NULL, "neg", "x,w", op[0], op[0]);
0acfaea6 12878 break;
252b5132
RH
12879 }
12880}
12881
14daeee3
RS
12882/* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12883 opcode bits in *OPCODE_EXTRA. */
12884
12885static struct mips_opcode *
12886mips_lookup_insn (struct hash_control *hash, const char *start,
da8bca91 12887 ssize_t length, unsigned int *opcode_extra)
14daeee3
RS
12888{
12889 char *name, *dot, *p;
12890 unsigned int mask, suffix;
da8bca91 12891 ssize_t opend;
14daeee3
RS
12892 struct mips_opcode *insn;
12893
12894 /* Make a copy of the instruction so that we can fiddle with it. */
12895 name = alloca (length + 1);
12896 memcpy (name, start, length);
12897 name[length] = '\0';
12898
12899 /* Look up the instruction as-is. */
12900 insn = (struct mips_opcode *) hash_find (hash, name);
ee5734f0 12901 if (insn)
14daeee3
RS
12902 return insn;
12903
12904 dot = strchr (name, '.');
12905 if (dot && dot[1])
12906 {
12907 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12908 p = mips_parse_vu0_channels (dot + 1, &mask);
12909 if (*p == 0 && mask != 0)
12910 {
12911 *dot = 0;
12912 insn = (struct mips_opcode *) hash_find (hash, name);
12913 *dot = '.';
12914 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
12915 {
12916 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
12917 return insn;
12918 }
12919 }
12920 }
12921
12922 if (mips_opts.micromips)
12923 {
12924 /* See if there's an instruction size override suffix,
12925 either `16' or `32', at the end of the mnemonic proper,
12926 that defines the operation, i.e. before the first `.'
12927 character if any. Strip it and retry. */
12928 opend = dot != NULL ? dot - name : length;
12929 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
12930 suffix = 2;
12931 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12932 suffix = 4;
12933 else
12934 suffix = 0;
12935 if (suffix)
12936 {
12937 memcpy (name + opend - 2, name + opend, length - opend + 1);
12938 insn = (struct mips_opcode *) hash_find (hash, name);
ee5734f0 12939 if (insn)
14daeee3
RS
12940 {
12941 forced_insn_length = suffix;
12942 return insn;
12943 }
12944 }
12945 }
12946
12947 return NULL;
12948}
12949
77bd4346
RS
12950/* Assemble an instruction into its binary format. If the instruction
12951 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12952 associated with "I", "+I" and "A" operands respectively. Otherwise
12953 store the value of the relocatable field (if any) in offset_expr.
12954 In both cases set offset_reloc to the relocation operators applied
12955 to offset_expr. */
252b5132
RH
12956
12957static void
17a2f251 12958mips_ip (char *str, struct mips_cl_insn *ip)
252b5132 12959{
df58fc94
RS
12960 bfd_boolean wrong_delay_slot_insns = FALSE;
12961 bfd_boolean need_delay_slot_ok = TRUE;
12962 struct mips_opcode *firstinsn = NULL;
12963 const struct mips_opcode *past;
12964 struct hash_control *hash;
14daeee3 12965 struct mips_opcode *first, *insn;
a92713e6 12966 char format;
14daeee3 12967 size_t end;
a92713e6 12968 struct mips_operand_token *tokens;
14daeee3 12969 unsigned int opcode_extra;
252b5132 12970
df58fc94
RS
12971 if (mips_opts.micromips)
12972 {
12973 hash = micromips_op_hash;
12974 past = &micromips_opcodes[bfd_micromips_num_opcodes];
12975 }
12976 else
12977 {
12978 hash = op_hash;
12979 past = &mips_opcodes[NUMOPCODES];
12980 }
12981 forced_insn_length = 0;
252b5132 12982 insn = NULL;
14daeee3 12983 opcode_extra = 0;
252b5132 12984
df58fc94 12985 /* We first try to match an instruction up to a space or to the end. */
a40bc9dd
RS
12986 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12987 continue;
bdaaa2e1 12988
14daeee3 12989 first = insn = mips_lookup_insn (hash, str, end, &opcode_extra);
252b5132
RH
12990 if (insn == NULL)
12991 {
e3de51ce 12992 set_insn_error (0, _("Unrecognized opcode"));
a40bc9dd 12993 return;
252b5132 12994 }
ee5734f0
RS
12995 /* When no opcode suffix is specified, assume ".xyzw". */
12996 if ((insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
12997 opcode_extra = 0xf << mips_vu0_channel_mask.lsb;
252b5132 12998
14daeee3 12999 if (strcmp (insn->name, "li.s") == 0)
a92713e6 13000 format = 'f';
14daeee3 13001 else if (strcmp (insn->name, "li.d") == 0)
a92713e6
RS
13002 format = 'd';
13003 else
13004 format = 0;
13005 tokens = mips_parse_arguments (str + end, format);
13006 if (!tokens)
13007 return;
13008
df58fc94
RS
13009 /* For microMIPS instructions placed in a fixed-length branch delay slot
13010 we make up to two passes over the relevant fragment of the opcode
13011 table. First we try instructions that meet the delay slot's length
13012 requirement. If none matched, then we retry with the remaining ones
13013 and if one matches, then we use it and then issue an appropriate
13014 warning later on. */
252b5132
RH
13015 for (;;)
13016 {
df58fc94
RS
13017 bfd_boolean delay_slot_ok;
13018 bfd_boolean size_ok;
b34976b6 13019 bfd_boolean ok;
9e12b7a2 13020 bfd_boolean more_alts;
252b5132 13021
14daeee3 13022 gas_assert (strcmp (insn->name, first->name) == 0);
252b5132 13023
f79e2745 13024 ok = is_opcode_valid (insn);
df58fc94
RS
13025 size_ok = is_size_valid (insn);
13026 delay_slot_ok = is_delay_slot_valid (insn);
13027 if (!delay_slot_ok && !wrong_delay_slot_insns)
252b5132 13028 {
df58fc94
RS
13029 firstinsn = insn;
13030 wrong_delay_slot_insns = TRUE;
13031 }
9e12b7a2
RS
13032 more_alts = (insn + 1 < past
13033 && strcmp (insn[0].name, insn[1].name) == 0);
df58fc94
RS
13034 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
13035 {
9e12b7a2 13036 if (more_alts)
252b5132
RH
13037 {
13038 ++insn;
13039 continue;
13040 }
df58fc94 13041 if (wrong_delay_slot_insns && need_delay_slot_ok)
beae10d5 13042 {
df58fc94
RS
13043 gas_assert (firstinsn);
13044 need_delay_slot_ok = FALSE;
13045 past = insn + 1;
13046 insn = firstinsn;
13047 continue;
252b5132 13048 }
df58fc94 13049
df58fc94 13050 if (!ok)
e3de51ce
RS
13051 set_insn_error_ss
13052 (0, _("Opcode not supported on this processor: %s (%s)"),
13053 mips_cpu_info_from_arch (mips_opts.arch)->name,
13054 mips_cpu_info_from_isa (mips_opts.isa)->name);
833794fc 13055 else if (mips_opts.insn32)
e3de51ce
RS
13056 set_insn_error
13057 (0, _("Opcode not supported in the `insn32' mode"));
df58fc94 13058 else
e3de51ce
RS
13059 set_insn_error_i
13060 (0, _("Unrecognized %d-bit version of microMIPS opcode"),
13061 8 * forced_insn_length);
13062 break;
252b5132
RH
13063 }
13064
1a00e612 13065 if (match_insn (ip, insn, tokens, opcode_extra,
97d87491
RS
13066 more_alts || (wrong_delay_slot_insns
13067 && need_delay_slot_ok)))
e3de51ce 13068 break;
97d87491 13069
252b5132 13070 /* Args don't match. */
e3de51ce 13071 set_insn_error (0, _("Illegal operands"));
9e12b7a2 13072 if (more_alts)
252b5132
RH
13073 {
13074 ++insn;
252b5132
RH
13075 continue;
13076 }
9e12b7a2 13077 if (wrong_delay_slot_insns && need_delay_slot_ok)
df58fc94
RS
13078 {
13079 gas_assert (firstinsn);
13080 need_delay_slot_ok = FALSE;
13081 past = insn + 1;
13082 insn = firstinsn;
13083 continue;
13084 }
e3de51ce 13085 break;
252b5132 13086 }
e3de51ce 13087 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
13088}
13089
77bd4346
RS
13090/* As for mips_ip, but used when assembling MIPS16 code.
13091 Also set forced_insn_length to the resulting instruction size in
13092 bytes if the user explicitly requested a small or extended instruction. */
252b5132
RH
13093
13094static void
17a2f251 13095mips16_ip (char *str, struct mips_cl_insn *ip)
252b5132 13096{
1a00e612
RS
13097 char *end, *s, c;
13098 struct mips_opcode *insn, *first;
a92713e6 13099 struct mips_operand_token *tokens;
252b5132 13100
df58fc94 13101 forced_insn_length = 0;
252b5132 13102
3882b010 13103 for (s = str; ISLOWER (*s); ++s)
252b5132 13104 ;
1a00e612
RS
13105 end = s;
13106 c = *end;
13107 switch (c)
252b5132
RH
13108 {
13109 case '\0':
13110 break;
13111
13112 case ' ':
1a00e612 13113 s++;
252b5132
RH
13114 break;
13115
13116 case '.':
13117 if (s[1] == 't' && s[2] == ' ')
13118 {
df58fc94 13119 forced_insn_length = 2;
252b5132
RH
13120 s += 3;
13121 break;
13122 }
13123 else if (s[1] == 'e' && s[2] == ' ')
13124 {
df58fc94 13125 forced_insn_length = 4;
252b5132
RH
13126 s += 3;
13127 break;
13128 }
13129 /* Fall through. */
13130 default:
e3de51ce 13131 set_insn_error (0, _("Unrecognized opcode"));
252b5132
RH
13132 return;
13133 }
13134
df58fc94
RS
13135 if (mips_opts.noautoextend && !forced_insn_length)
13136 forced_insn_length = 2;
252b5132 13137
1a00e612
RS
13138 *end = 0;
13139 first = insn = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13140 *end = c;
13141
13142 if (!insn)
252b5132 13143 {
e3de51ce 13144 set_insn_error (0, _("Unrecognized opcode"));
252b5132
RH
13145 return;
13146 }
13147
a92713e6
RS
13148 tokens = mips_parse_arguments (s, 0);
13149 if (!tokens)
13150 return;
13151
252b5132
RH
13152 for (;;)
13153 {
9b3f89ee 13154 bfd_boolean ok;
364215c8 13155 bfd_boolean more_alts;
9b3f89ee 13156
1a00e612 13157 gas_assert (strcmp (insn->name, first->name) == 0);
252b5132 13158
037b32b9 13159 ok = is_opcode_valid_16 (insn);
364215c8
RS
13160 more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13161 && strcmp (insn[0].name, insn[1].name) == 0);
9b3f89ee
TS
13162 if (! ok)
13163 {
364215c8 13164 if (more_alts)
9b3f89ee
TS
13165 {
13166 ++insn;
13167 continue;
13168 }
13169 else
13170 {
e3de51ce
RS
13171 set_insn_error_ss
13172 (0, _("Opcode not supported on this processor: %s (%s)"),
13173 mips_cpu_info_from_arch (mips_opts.arch)->name,
13174 mips_cpu_info_from_isa (mips_opts.isa)->name);
13175 break;
9b3f89ee
TS
13176 }
13177 }
13178
1a00e612 13179 if (match_mips16_insn (ip, insn, tokens))
e3de51ce 13180 break;
252b5132
RH
13181
13182 /* Args don't match. */
e3de51ce 13183 set_insn_error (0, _("Illegal operands"));
364215c8 13184 if (more_alts)
252b5132
RH
13185 {
13186 ++insn;
252b5132
RH
13187 continue;
13188 }
e3de51ce 13189 break;
252b5132 13190 }
e3de51ce 13191 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
13192}
13193
b886a2ab
RS
13194/* Marshal immediate value VAL for an extended MIPS16 instruction.
13195 NBITS is the number of significant bits in VAL. */
13196
13197static unsigned long
13198mips16_immed_extend (offsetT val, unsigned int nbits)
13199{
13200 int extval;
13201 if (nbits == 16)
13202 {
13203 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13204 val &= 0x1f;
13205 }
13206 else if (nbits == 15)
13207 {
13208 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13209 val &= 0xf;
13210 }
13211 else
13212 {
13213 extval = ((val & 0x1f) << 6) | (val & 0x20);
13214 val = 0;
13215 }
13216 return (extval << 16) | val;
13217}
13218
3ccad066
RS
13219/* Like decode_mips16_operand, but require the operand to be defined and
13220 require it to be an integer. */
13221
13222static const struct mips_int_operand *
13223mips16_immed_operand (int type, bfd_boolean extended_p)
13224{
13225 const struct mips_operand *operand;
13226
13227 operand = decode_mips16_operand (type, extended_p);
13228 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13229 abort ();
13230 return (const struct mips_int_operand *) operand;
13231}
13232
13233/* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13234
13235static bfd_boolean
13236mips16_immed_in_range_p (const struct mips_int_operand *operand,
13237 bfd_reloc_code_real_type reloc, offsetT sval)
13238{
13239 int min_val, max_val;
13240
13241 min_val = mips_int_operand_min (operand);
13242 max_val = mips_int_operand_max (operand);
13243 if (reloc != BFD_RELOC_UNUSED)
13244 {
13245 if (min_val < 0)
13246 sval = SEXT_16BIT (sval);
13247 else
13248 sval &= 0xffff;
13249 }
13250
13251 return (sval >= min_val
13252 && sval <= max_val
13253 && (sval & ((1 << operand->shift) - 1)) == 0);
13254}
13255
5c04167a
RS
13256/* Install immediate value VAL into MIPS16 instruction *INSN,
13257 extending it if necessary. The instruction in *INSN may
13258 already be extended.
13259
43c0598f
RS
13260 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13261 if none. In the former case, VAL is a 16-bit number with no
13262 defined signedness.
13263
13264 TYPE is the type of the immediate field. USER_INSN_LENGTH
13265 is the length that the user requested, or 0 if none. */
252b5132
RH
13266
13267static void
43c0598f
RS
13268mips16_immed (char *file, unsigned int line, int type,
13269 bfd_reloc_code_real_type reloc, offsetT val,
5c04167a 13270 unsigned int user_insn_length, unsigned long *insn)
252b5132 13271{
3ccad066
RS
13272 const struct mips_int_operand *operand;
13273 unsigned int uval, length;
252b5132 13274
3ccad066
RS
13275 operand = mips16_immed_operand (type, FALSE);
13276 if (!mips16_immed_in_range_p (operand, reloc, val))
5c04167a
RS
13277 {
13278 /* We need an extended instruction. */
13279 if (user_insn_length == 2)
13280 as_bad_where (file, line, _("invalid unextended operand value"));
13281 else
13282 *insn |= MIPS16_EXTEND;
13283 }
13284 else if (user_insn_length == 4)
13285 {
13286 /* The operand doesn't force an unextended instruction to be extended.
13287 Warn if the user wanted an extended instruction anyway. */
13288 *insn |= MIPS16_EXTEND;
13289 as_warn_where (file, line,
13290 _("extended operand requested but not required"));
13291 }
252b5132 13292
3ccad066
RS
13293 length = mips16_opcode_length (*insn);
13294 if (length == 4)
252b5132 13295 {
3ccad066
RS
13296 operand = mips16_immed_operand (type, TRUE);
13297 if (!mips16_immed_in_range_p (operand, reloc, val))
13298 as_bad_where (file, line,
13299 _("operand value out of range for instruction"));
252b5132 13300 }
3ccad066
RS
13301 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13302 if (length == 2)
13303 *insn = mips_insert_operand (&operand->root, *insn, uval);
252b5132 13304 else
3ccad066 13305 *insn |= mips16_immed_extend (uval, operand->root.size);
252b5132
RH
13306}
13307\f
d6f16593 13308struct percent_op_match
ad8d3bb3 13309{
5e0116d5
RS
13310 const char *str;
13311 bfd_reloc_code_real_type reloc;
d6f16593
MR
13312};
13313
13314static const struct percent_op_match mips_percent_op[] =
ad8d3bb3 13315{
5e0116d5 13316 {"%lo", BFD_RELOC_LO16},
5e0116d5
RS
13317 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13318 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13319 {"%call16", BFD_RELOC_MIPS_CALL16},
13320 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13321 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13322 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13323 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13324 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13325 {"%got", BFD_RELOC_MIPS_GOT16},
13326 {"%gp_rel", BFD_RELOC_GPREL16},
13327 {"%half", BFD_RELOC_16},
13328 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13329 {"%higher", BFD_RELOC_MIPS_HIGHER},
13330 {"%neg", BFD_RELOC_MIPS_SUB},
3f98094e
DJ
13331 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13332 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13333 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13334 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13335 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13336 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13337 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
5e0116d5 13338 {"%hi", BFD_RELOC_HI16_S}
ad8d3bb3
TS
13339};
13340
d6f16593
MR
13341static const struct percent_op_match mips16_percent_op[] =
13342{
13343 {"%lo", BFD_RELOC_MIPS16_LO16},
13344 {"%gprel", BFD_RELOC_MIPS16_GPREL},
738e5348
RS
13345 {"%got", BFD_RELOC_MIPS16_GOT16},
13346 {"%call16", BFD_RELOC_MIPS16_CALL16},
d0f13682
CLT
13347 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13348 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13349 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13350 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13351 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13352 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13353 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13354 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
d6f16593
MR
13355};
13356
252b5132 13357
5e0116d5
RS
13358/* Return true if *STR points to a relocation operator. When returning true,
13359 move *STR over the operator and store its relocation code in *RELOC.
13360 Leave both *STR and *RELOC alone when returning false. */
13361
13362static bfd_boolean
17a2f251 13363parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
252b5132 13364{
d6f16593
MR
13365 const struct percent_op_match *percent_op;
13366 size_t limit, i;
13367
13368 if (mips_opts.mips16)
13369 {
13370 percent_op = mips16_percent_op;
13371 limit = ARRAY_SIZE (mips16_percent_op);
13372 }
13373 else
13374 {
13375 percent_op = mips_percent_op;
13376 limit = ARRAY_SIZE (mips_percent_op);
13377 }
76b3015f 13378
d6f16593 13379 for (i = 0; i < limit; i++)
5e0116d5 13380 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
394f9b3a 13381 {
3f98094e
DJ
13382 int len = strlen (percent_op[i].str);
13383
13384 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13385 continue;
13386
5e0116d5
RS
13387 *str += strlen (percent_op[i].str);
13388 *reloc = percent_op[i].reloc;
394f9b3a 13389
5e0116d5
RS
13390 /* Check whether the output BFD supports this relocation.
13391 If not, issue an error and fall back on something safe. */
13392 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
394f9b3a 13393 {
20203fb9 13394 as_bad (_("relocation %s isn't supported by the current ABI"),
5e0116d5 13395 percent_op[i].str);
01a3f561 13396 *reloc = BFD_RELOC_UNUSED;
394f9b3a 13397 }
5e0116d5 13398 return TRUE;
394f9b3a 13399 }
5e0116d5 13400 return FALSE;
394f9b3a 13401}
ad8d3bb3 13402
ad8d3bb3 13403
5e0116d5
RS
13404/* Parse string STR as a 16-bit relocatable operand. Store the
13405 expression in *EP and the relocations in the array starting
13406 at RELOC. Return the number of relocation operators used.
ad8d3bb3 13407
01a3f561 13408 On exit, EXPR_END points to the first character after the expression. */
ad8d3bb3 13409
5e0116d5 13410static size_t
17a2f251
TS
13411my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13412 char *str)
ad8d3bb3 13413{
5e0116d5
RS
13414 bfd_reloc_code_real_type reversed_reloc[3];
13415 size_t reloc_index, i;
09b8f35a
RS
13416 int crux_depth, str_depth;
13417 char *crux;
5e0116d5
RS
13418
13419 /* Search for the start of the main expression, recoding relocations
09b8f35a
RS
13420 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13421 of the main expression and with CRUX_DEPTH containing the number
13422 of open brackets at that point. */
13423 reloc_index = -1;
13424 str_depth = 0;
13425 do
fb1b3232 13426 {
09b8f35a
RS
13427 reloc_index++;
13428 crux = str;
13429 crux_depth = str_depth;
13430
13431 /* Skip over whitespace and brackets, keeping count of the number
13432 of brackets. */
13433 while (*str == ' ' || *str == '\t' || *str == '(')
13434 if (*str++ == '(')
13435 str_depth++;
5e0116d5 13436 }
09b8f35a
RS
13437 while (*str == '%'
13438 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13439 && parse_relocation (&str, &reversed_reloc[reloc_index]));
ad8d3bb3 13440
09b8f35a 13441 my_getExpression (ep, crux);
5e0116d5 13442 str = expr_end;
394f9b3a 13443
5e0116d5 13444 /* Match every open bracket. */
09b8f35a 13445 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
5e0116d5 13446 if (*str++ == ')')
09b8f35a 13447 crux_depth--;
394f9b3a 13448
09b8f35a 13449 if (crux_depth > 0)
20203fb9 13450 as_bad (_("unclosed '('"));
394f9b3a 13451
5e0116d5 13452 expr_end = str;
252b5132 13453
01a3f561 13454 if (reloc_index != 0)
64bdfcaf
RS
13455 {
13456 prev_reloc_op_frag = frag_now;
13457 for (i = 0; i < reloc_index; i++)
13458 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13459 }
fb1b3232 13460
5e0116d5 13461 return reloc_index;
252b5132
RH
13462}
13463
13464static void
17a2f251 13465my_getExpression (expressionS *ep, char *str)
252b5132
RH
13466{
13467 char *save_in;
13468
13469 save_in = input_line_pointer;
13470 input_line_pointer = str;
13471 expression (ep);
13472 expr_end = input_line_pointer;
13473 input_line_pointer = save_in;
252b5132
RH
13474}
13475
252b5132 13476char *
17a2f251 13477md_atof (int type, char *litP, int *sizeP)
252b5132 13478{
499ac353 13479 return ieee_md_atof (type, litP, sizeP, target_big_endian);
252b5132
RH
13480}
13481
13482void
17a2f251 13483md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH
13484{
13485 if (target_big_endian)
13486 number_to_chars_bigendian (buf, val, n);
13487 else
13488 number_to_chars_littleendian (buf, val, n);
13489}
13490\f
e013f690
TS
13491static int support_64bit_objects(void)
13492{
13493 const char **list, **l;
aa3d8fdf 13494 int yes;
e013f690
TS
13495
13496 list = bfd_target_list ();
13497 for (l = list; *l != NULL; l++)
aeffff67
RS
13498 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13499 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
e013f690 13500 break;
aa3d8fdf 13501 yes = (*l != NULL);
e013f690 13502 free (list);
aa3d8fdf 13503 return yes;
e013f690
TS
13504}
13505
316f5878
RS
13506/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13507 NEW_VALUE. Warn if another value was already specified. Note:
13508 we have to defer parsing the -march and -mtune arguments in order
13509 to handle 'from-abi' correctly, since the ABI might be specified
13510 in a later argument. */
13511
13512static void
17a2f251 13513mips_set_option_string (const char **string_ptr, const char *new_value)
316f5878
RS
13514{
13515 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
13516 as_warn (_("A different %s was already specified, is now %s"),
13517 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13518 new_value);
13519
13520 *string_ptr = new_value;
13521}
13522
252b5132 13523int
17a2f251 13524md_parse_option (int c, char *arg)
252b5132 13525{
c6278170
RS
13526 unsigned int i;
13527
13528 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13529 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13530 {
13531 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13532 c == mips_ases[i].option_on);
13533 return 1;
13534 }
13535
252b5132
RH
13536 switch (c)
13537 {
119d663a
NC
13538 case OPTION_CONSTRUCT_FLOATS:
13539 mips_disable_float_construction = 0;
13540 break;
bdaaa2e1 13541
119d663a
NC
13542 case OPTION_NO_CONSTRUCT_FLOATS:
13543 mips_disable_float_construction = 1;
13544 break;
bdaaa2e1 13545
252b5132
RH
13546 case OPTION_TRAP:
13547 mips_trap = 1;
13548 break;
13549
13550 case OPTION_BREAK:
13551 mips_trap = 0;
13552 break;
13553
13554 case OPTION_EB:
13555 target_big_endian = 1;
13556 break;
13557
13558 case OPTION_EL:
13559 target_big_endian = 0;
13560 break;
13561
13562 case 'O':
4ffff32f
TS
13563 if (arg == NULL)
13564 mips_optimize = 1;
13565 else if (arg[0] == '0')
13566 mips_optimize = 0;
13567 else if (arg[0] == '1')
252b5132
RH
13568 mips_optimize = 1;
13569 else
13570 mips_optimize = 2;
13571 break;
13572
13573 case 'g':
13574 if (arg == NULL)
13575 mips_debug = 2;
13576 else
13577 mips_debug = atoi (arg);
252b5132
RH
13578 break;
13579
13580 case OPTION_MIPS1:
316f5878 13581 file_mips_isa = ISA_MIPS1;
252b5132
RH
13582 break;
13583
13584 case OPTION_MIPS2:
316f5878 13585 file_mips_isa = ISA_MIPS2;
252b5132
RH
13586 break;
13587
13588 case OPTION_MIPS3:
316f5878 13589 file_mips_isa = ISA_MIPS3;
252b5132
RH
13590 break;
13591
13592 case OPTION_MIPS4:
316f5878 13593 file_mips_isa = ISA_MIPS4;
e7af610e
NC
13594 break;
13595
84ea6cf2 13596 case OPTION_MIPS5:
316f5878 13597 file_mips_isa = ISA_MIPS5;
84ea6cf2
NC
13598 break;
13599
e7af610e 13600 case OPTION_MIPS32:
316f5878 13601 file_mips_isa = ISA_MIPS32;
252b5132
RH
13602 break;
13603
af7ee8bf
CD
13604 case OPTION_MIPS32R2:
13605 file_mips_isa = ISA_MIPS32R2;
13606 break;
13607
5f74bc13
CD
13608 case OPTION_MIPS64R2:
13609 file_mips_isa = ISA_MIPS64R2;
13610 break;
13611
84ea6cf2 13612 case OPTION_MIPS64:
316f5878 13613 file_mips_isa = ISA_MIPS64;
84ea6cf2
NC
13614 break;
13615
ec68c924 13616 case OPTION_MTUNE:
316f5878
RS
13617 mips_set_option_string (&mips_tune_string, arg);
13618 break;
ec68c924 13619
316f5878
RS
13620 case OPTION_MARCH:
13621 mips_set_option_string (&mips_arch_string, arg);
252b5132
RH
13622 break;
13623
13624 case OPTION_M4650:
316f5878
RS
13625 mips_set_option_string (&mips_arch_string, "4650");
13626 mips_set_option_string (&mips_tune_string, "4650");
252b5132
RH
13627 break;
13628
13629 case OPTION_NO_M4650:
13630 break;
13631
13632 case OPTION_M4010:
316f5878
RS
13633 mips_set_option_string (&mips_arch_string, "4010");
13634 mips_set_option_string (&mips_tune_string, "4010");
252b5132
RH
13635 break;
13636
13637 case OPTION_NO_M4010:
13638 break;
13639
13640 case OPTION_M4100:
316f5878
RS
13641 mips_set_option_string (&mips_arch_string, "4100");
13642 mips_set_option_string (&mips_tune_string, "4100");
252b5132
RH
13643 break;
13644
13645 case OPTION_NO_M4100:
13646 break;
13647
252b5132 13648 case OPTION_M3900:
316f5878
RS
13649 mips_set_option_string (&mips_arch_string, "3900");
13650 mips_set_option_string (&mips_tune_string, "3900");
252b5132 13651 break;
bdaaa2e1 13652
252b5132
RH
13653 case OPTION_NO_M3900:
13654 break;
13655
df58fc94
RS
13656 case OPTION_MICROMIPS:
13657 if (mips_opts.mips16 == 1)
13658 {
13659 as_bad (_("-mmicromips cannot be used with -mips16"));
13660 return 0;
13661 }
13662 mips_opts.micromips = 1;
13663 mips_no_prev_insn ();
13664 break;
13665
13666 case OPTION_NO_MICROMIPS:
13667 mips_opts.micromips = 0;
13668 mips_no_prev_insn ();
13669 break;
13670
252b5132 13671 case OPTION_MIPS16:
df58fc94
RS
13672 if (mips_opts.micromips == 1)
13673 {
13674 as_bad (_("-mips16 cannot be used with -micromips"));
13675 return 0;
13676 }
252b5132 13677 mips_opts.mips16 = 1;
7d10b47d 13678 mips_no_prev_insn ();
252b5132
RH
13679 break;
13680
13681 case OPTION_NO_MIPS16:
13682 mips_opts.mips16 = 0;
7d10b47d 13683 mips_no_prev_insn ();
252b5132
RH
13684 break;
13685
6a32d874
CM
13686 case OPTION_FIX_24K:
13687 mips_fix_24k = 1;
13688 break;
13689
13690 case OPTION_NO_FIX_24K:
13691 mips_fix_24k = 0;
13692 break;
13693
c67a084a
NC
13694 case OPTION_FIX_LOONGSON2F_JUMP:
13695 mips_fix_loongson2f_jump = TRUE;
13696 break;
13697
13698 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13699 mips_fix_loongson2f_jump = FALSE;
13700 break;
13701
13702 case OPTION_FIX_LOONGSON2F_NOP:
13703 mips_fix_loongson2f_nop = TRUE;
13704 break;
13705
13706 case OPTION_NO_FIX_LOONGSON2F_NOP:
13707 mips_fix_loongson2f_nop = FALSE;
13708 break;
13709
d766e8ec
RS
13710 case OPTION_FIX_VR4120:
13711 mips_fix_vr4120 = 1;
60b63b72
RS
13712 break;
13713
d766e8ec
RS
13714 case OPTION_NO_FIX_VR4120:
13715 mips_fix_vr4120 = 0;
60b63b72
RS
13716 break;
13717
7d8e00cf
RS
13718 case OPTION_FIX_VR4130:
13719 mips_fix_vr4130 = 1;
13720 break;
13721
13722 case OPTION_NO_FIX_VR4130:
13723 mips_fix_vr4130 = 0;
13724 break;
13725
d954098f
DD
13726 case OPTION_FIX_CN63XXP1:
13727 mips_fix_cn63xxp1 = TRUE;
13728 break;
13729
13730 case OPTION_NO_FIX_CN63XXP1:
13731 mips_fix_cn63xxp1 = FALSE;
13732 break;
13733
4a6a3df4
AO
13734 case OPTION_RELAX_BRANCH:
13735 mips_relax_branch = 1;
13736 break;
13737
13738 case OPTION_NO_RELAX_BRANCH:
13739 mips_relax_branch = 0;
13740 break;
13741
833794fc
MR
13742 case OPTION_INSN32:
13743 mips_opts.insn32 = TRUE;
13744 break;
13745
13746 case OPTION_NO_INSN32:
13747 mips_opts.insn32 = FALSE;
13748 break;
13749
aa6975fb
ILT
13750 case OPTION_MSHARED:
13751 mips_in_shared = TRUE;
13752 break;
13753
13754 case OPTION_MNO_SHARED:
13755 mips_in_shared = FALSE;
13756 break;
13757
aed1a261
RS
13758 case OPTION_MSYM32:
13759 mips_opts.sym32 = TRUE;
13760 break;
13761
13762 case OPTION_MNO_SYM32:
13763 mips_opts.sym32 = FALSE;
13764 break;
13765
252b5132
RH
13766 /* When generating ELF code, we permit -KPIC and -call_shared to
13767 select SVR4_PIC, and -non_shared to select no PIC. This is
13768 intended to be compatible with Irix 5. */
13769 case OPTION_CALL_SHARED:
252b5132 13770 mips_pic = SVR4_PIC;
143d77c5 13771 mips_abicalls = TRUE;
252b5132
RH
13772 break;
13773
861fb55a 13774 case OPTION_CALL_NONPIC:
861fb55a
DJ
13775 mips_pic = NO_PIC;
13776 mips_abicalls = TRUE;
13777 break;
13778
252b5132 13779 case OPTION_NON_SHARED:
252b5132 13780 mips_pic = NO_PIC;
143d77c5 13781 mips_abicalls = FALSE;
252b5132
RH
13782 break;
13783
44075ae2
TS
13784 /* The -xgot option tells the assembler to use 32 bit offsets
13785 when accessing the got in SVR4_PIC mode. It is for Irix
252b5132
RH
13786 compatibility. */
13787 case OPTION_XGOT:
13788 mips_big_got = 1;
13789 break;
13790
13791 case 'G':
6caf9ef4
TS
13792 g_switch_value = atoi (arg);
13793 g_switch_seen = 1;
252b5132
RH
13794 break;
13795
34ba82a8
TS
13796 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13797 and -mabi=64. */
252b5132 13798 case OPTION_32:
f3ded42a 13799 mips_abi = O32_ABI;
252b5132
RH
13800 break;
13801
e013f690 13802 case OPTION_N32:
316f5878 13803 mips_abi = N32_ABI;
e013f690 13804 break;
252b5132 13805
e013f690 13806 case OPTION_64:
316f5878 13807 mips_abi = N64_ABI;
f43abd2b 13808 if (!support_64bit_objects())
e013f690 13809 as_fatal (_("No compiled in support for 64 bit object file format"));
252b5132
RH
13810 break;
13811
c97ef257 13812 case OPTION_GP32:
a325df1d 13813 file_mips_gp32 = 1;
c97ef257
AH
13814 break;
13815
13816 case OPTION_GP64:
a325df1d 13817 file_mips_gp32 = 0;
c97ef257 13818 break;
252b5132 13819
ca4e0257 13820 case OPTION_FP32:
a325df1d 13821 file_mips_fp32 = 1;
316f5878
RS
13822 break;
13823
13824 case OPTION_FP64:
13825 file_mips_fp32 = 0;
ca4e0257
RS
13826 break;
13827
037b32b9
AN
13828 case OPTION_SINGLE_FLOAT:
13829 file_mips_single_float = 1;
13830 break;
13831
13832 case OPTION_DOUBLE_FLOAT:
13833 file_mips_single_float = 0;
13834 break;
13835
13836 case OPTION_SOFT_FLOAT:
13837 file_mips_soft_float = 1;
13838 break;
13839
13840 case OPTION_HARD_FLOAT:
13841 file_mips_soft_float = 0;
13842 break;
13843
252b5132 13844 case OPTION_MABI:
e013f690 13845 if (strcmp (arg, "32") == 0)
316f5878 13846 mips_abi = O32_ABI;
e013f690 13847 else if (strcmp (arg, "o64") == 0)
316f5878 13848 mips_abi = O64_ABI;
e013f690 13849 else if (strcmp (arg, "n32") == 0)
316f5878 13850 mips_abi = N32_ABI;
e013f690
TS
13851 else if (strcmp (arg, "64") == 0)
13852 {
316f5878 13853 mips_abi = N64_ABI;
e013f690
TS
13854 if (! support_64bit_objects())
13855 as_fatal (_("No compiled in support for 64 bit object file "
13856 "format"));
13857 }
13858 else if (strcmp (arg, "eabi") == 0)
316f5878 13859 mips_abi = EABI_ABI;
e013f690 13860 else
da0e507f
TS
13861 {
13862 as_fatal (_("invalid abi -mabi=%s"), arg);
13863 return 0;
13864 }
252b5132
RH
13865 break;
13866
6b76fefe 13867 case OPTION_M7000_HILO_FIX:
b34976b6 13868 mips_7000_hilo_fix = TRUE;
6b76fefe
CM
13869 break;
13870
9ee72ff1 13871 case OPTION_MNO_7000_HILO_FIX:
b34976b6 13872 mips_7000_hilo_fix = FALSE;
6b76fefe
CM
13873 break;
13874
ecb4347a 13875 case OPTION_MDEBUG:
b34976b6 13876 mips_flag_mdebug = TRUE;
ecb4347a
DJ
13877 break;
13878
13879 case OPTION_NO_MDEBUG:
b34976b6 13880 mips_flag_mdebug = FALSE;
ecb4347a 13881 break;
dcd410fe
RO
13882
13883 case OPTION_PDR:
13884 mips_flag_pdr = TRUE;
13885 break;
13886
13887 case OPTION_NO_PDR:
13888 mips_flag_pdr = FALSE;
13889 break;
0a44bf69
RS
13890
13891 case OPTION_MVXWORKS_PIC:
13892 mips_pic = VXWORKS_PIC;
13893 break;
ecb4347a 13894
ba92f887
MR
13895 case OPTION_NAN:
13896 if (strcmp (arg, "2008") == 0)
13897 mips_flag_nan2008 = TRUE;
13898 else if (strcmp (arg, "legacy") == 0)
13899 mips_flag_nan2008 = FALSE;
13900 else
13901 {
13902 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
13903 return 0;
13904 }
13905 break;
13906
252b5132
RH
13907 default:
13908 return 0;
13909 }
13910
c67a084a
NC
13911 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13912
252b5132
RH
13913 return 1;
13914}
316f5878
RS
13915\f
13916/* Set up globals to generate code for the ISA or processor
13917 described by INFO. */
252b5132 13918
252b5132 13919static void
17a2f251 13920mips_set_architecture (const struct mips_cpu_info *info)
252b5132 13921{
316f5878 13922 if (info != 0)
252b5132 13923 {
fef14a42
TS
13924 file_mips_arch = info->cpu;
13925 mips_opts.arch = info->cpu;
316f5878 13926 mips_opts.isa = info->isa;
252b5132 13927 }
252b5132
RH
13928}
13929
252b5132 13930
316f5878 13931/* Likewise for tuning. */
252b5132 13932
316f5878 13933static void
17a2f251 13934mips_set_tune (const struct mips_cpu_info *info)
316f5878
RS
13935{
13936 if (info != 0)
fef14a42 13937 mips_tune = info->cpu;
316f5878 13938}
80cc45a5 13939
34ba82a8 13940
252b5132 13941void
17a2f251 13942mips_after_parse_args (void)
e9670677 13943{
fef14a42
TS
13944 const struct mips_cpu_info *arch_info = 0;
13945 const struct mips_cpu_info *tune_info = 0;
13946
e9670677 13947 /* GP relative stuff not working for PE */
6caf9ef4 13948 if (strncmp (TARGET_OS, "pe", 2) == 0)
e9670677 13949 {
6caf9ef4 13950 if (g_switch_seen && g_switch_value != 0)
e9670677
MR
13951 as_bad (_("-G not supported in this configuration."));
13952 g_switch_value = 0;
13953 }
13954
cac012d6
AO
13955 if (mips_abi == NO_ABI)
13956 mips_abi = MIPS_DEFAULT_ABI;
13957
22923709
RS
13958 /* The following code determines the architecture and register size.
13959 Similar code was added to GCC 3.3 (see override_options() in
13960 config/mips/mips.c). The GAS and GCC code should be kept in sync
13961 as much as possible. */
e9670677 13962
316f5878 13963 if (mips_arch_string != 0)
fef14a42 13964 arch_info = mips_parse_cpu ("-march", mips_arch_string);
e9670677 13965
316f5878 13966 if (file_mips_isa != ISA_UNKNOWN)
e9670677 13967 {
316f5878 13968 /* Handle -mipsN. At this point, file_mips_isa contains the
fef14a42 13969 ISA level specified by -mipsN, while arch_info->isa contains
316f5878 13970 the -march selection (if any). */
fef14a42 13971 if (arch_info != 0)
e9670677 13972 {
316f5878
RS
13973 /* -march takes precedence over -mipsN, since it is more descriptive.
13974 There's no harm in specifying both as long as the ISA levels
13975 are the same. */
fef14a42 13976 if (file_mips_isa != arch_info->isa)
316f5878
RS
13977 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13978 mips_cpu_info_from_isa (file_mips_isa)->name,
fef14a42 13979 mips_cpu_info_from_isa (arch_info->isa)->name);
e9670677 13980 }
316f5878 13981 else
fef14a42 13982 arch_info = mips_cpu_info_from_isa (file_mips_isa);
e9670677
MR
13983 }
13984
fef14a42 13985 if (arch_info == 0)
95bfe26e
MF
13986 {
13987 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13988 gas_assert (arch_info);
13989 }
e9670677 13990
fef14a42 13991 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
20203fb9 13992 as_bad (_("-march=%s is not compatible with the selected ABI"),
fef14a42
TS
13993 arch_info->name);
13994
13995 mips_set_architecture (arch_info);
13996
13997 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13998 if (mips_tune_string != 0)
13999 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
e9670677 14000
fef14a42
TS
14001 if (tune_info == 0)
14002 mips_set_tune (arch_info);
14003 else
14004 mips_set_tune (tune_info);
e9670677 14005
316f5878 14006 if (file_mips_gp32 >= 0)
e9670677 14007 {
316f5878
RS
14008 /* The user specified the size of the integer registers. Make sure
14009 it agrees with the ABI and ISA. */
14010 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
14011 as_bad (_("-mgp64 used with a 32-bit processor"));
14012 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
14013 as_bad (_("-mgp32 used with a 64-bit ABI"));
14014 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
14015 as_bad (_("-mgp64 used with a 32-bit ABI"));
e9670677
MR
14016 }
14017 else
14018 {
316f5878
RS
14019 /* Infer the integer register size from the ABI and processor.
14020 Restrict ourselves to 32-bit registers if that's all the
14021 processor has, or if the ABI cannot handle 64-bit registers. */
14022 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
14023 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
e9670677
MR
14024 }
14025
ad3fea08
TS
14026 switch (file_mips_fp32)
14027 {
14028 default:
14029 case -1:
14030 /* No user specified float register size.
14031 ??? GAS treats single-float processors as though they had 64-bit
14032 float registers (although it complains when double-precision
14033 instructions are used). As things stand, saying they have 32-bit
14034 registers would lead to spurious "register must be even" messages.
14035 So here we assume float registers are never smaller than the
14036 integer ones. */
14037 if (file_mips_gp32 == 0)
14038 /* 64-bit integer registers implies 64-bit float registers. */
14039 file_mips_fp32 = 0;
c6278170 14040 else if ((mips_opts.ase & FP64_ASES)
ad3fea08
TS
14041 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
14042 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14043 file_mips_fp32 = 0;
14044 else
14045 /* 32-bit float registers. */
14046 file_mips_fp32 = 1;
14047 break;
14048
14049 /* The user specified the size of the float registers. Check if it
14050 agrees with the ABI and ISA. */
14051 case 0:
14052 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14053 as_bad (_("-mfp64 used with a 32-bit fpu"));
14054 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
14055 && !ISA_HAS_MXHC1 (mips_opts.isa))
14056 as_warn (_("-mfp64 used with a 32-bit ABI"));
14057 break;
14058 case 1:
14059 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14060 as_warn (_("-mfp32 used with a 64-bit ABI"));
14061 break;
14062 }
e9670677 14063
316f5878 14064 /* End of GCC-shared inference code. */
e9670677 14065
17a2f251
TS
14066 /* This flag is set when we have a 64-bit capable CPU but use only
14067 32-bit wide registers. Note that EABI does not use it. */
14068 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
14069 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
14070 || mips_abi == O32_ABI))
316f5878 14071 mips_32bitmode = 1;
e9670677
MR
14072
14073 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
14074 as_bad (_("trap exception not supported at ISA 1"));
14075
e9670677
MR
14076 /* If the selected architecture includes support for ASEs, enable
14077 generation of code for them. */
a4672219 14078 if (mips_opts.mips16 == -1)
fef14a42 14079 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
df58fc94
RS
14080 if (mips_opts.micromips == -1)
14081 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
846ef2d0
RS
14082
14083 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14084 ASEs from being selected implicitly. */
14085 if (file_mips_fp32 == 1)
14086 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
14087
14088 /* If the user didn't explicitly select or deselect a particular ASE,
14089 use the default setting for the CPU. */
14090 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
14091
e9670677 14092 file_mips_isa = mips_opts.isa;
846ef2d0 14093 file_ase = mips_opts.ase;
e9670677
MR
14094 mips_opts.gp32 = file_mips_gp32;
14095 mips_opts.fp32 = file_mips_fp32;
037b32b9
AN
14096 mips_opts.soft_float = file_mips_soft_float;
14097 mips_opts.single_float = file_mips_single_float;
e9670677 14098
c6278170
RS
14099 mips_check_isa_supports_ases ();
14100
ecb4347a 14101 if (mips_flag_mdebug < 0)
e8044f35 14102 mips_flag_mdebug = 0;
e9670677
MR
14103}
14104\f
14105void
17a2f251 14106mips_init_after_args (void)
252b5132
RH
14107{
14108 /* initialize opcodes */
14109 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
beae10d5 14110 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
252b5132
RH
14111}
14112
14113long
17a2f251 14114md_pcrel_from (fixS *fixP)
252b5132 14115{
a7ebbfdf
TS
14116 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14117 switch (fixP->fx_r_type)
14118 {
df58fc94
RS
14119 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14120 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14121 /* Return the address of the delay slot. */
14122 return addr + 2;
14123
14124 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14125 case BFD_RELOC_MICROMIPS_JMP:
a7ebbfdf
TS
14126 case BFD_RELOC_16_PCREL_S2:
14127 case BFD_RELOC_MIPS_JMP:
14128 /* Return the address of the delay slot. */
14129 return addr + 4;
df58fc94 14130
b47468a6
CM
14131 case BFD_RELOC_32_PCREL:
14132 return addr;
14133
a7ebbfdf 14134 default:
58ea3d6a 14135 /* We have no relocation type for PC relative MIPS16 instructions. */
64817874
TS
14136 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
14137 as_bad_where (fixP->fx_file, fixP->fx_line,
14138 _("PC relative MIPS16 instruction references a different section"));
a7ebbfdf
TS
14139 return addr;
14140 }
252b5132
RH
14141}
14142
252b5132
RH
14143/* This is called before the symbol table is processed. In order to
14144 work with gcc when using mips-tfile, we must keep all local labels.
14145 However, in other cases, we want to discard them. If we were
14146 called with -g, but we didn't see any debugging information, it may
14147 mean that gcc is smuggling debugging information through to
14148 mips-tfile, in which case we must generate all local labels. */
14149
14150void
17a2f251 14151mips_frob_file_before_adjust (void)
252b5132
RH
14152{
14153#ifndef NO_ECOFF_DEBUGGING
14154 if (ECOFF_DEBUGGING
14155 && mips_debug != 0
14156 && ! ecoff_debugging_seen)
14157 flag_keep_locals = 1;
14158#endif
14159}
14160
3b91255e 14161/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
55cf6793 14162 the corresponding LO16 reloc. This is called before md_apply_fix and
3b91255e
RS
14163 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14164 relocation operators.
14165
14166 For our purposes, a %lo() expression matches a %got() or %hi()
14167 expression if:
14168
14169 (a) it refers to the same symbol; and
14170 (b) the offset applied in the %lo() expression is no lower than
14171 the offset applied in the %got() or %hi().
14172
14173 (b) allows us to cope with code like:
14174
14175 lui $4,%hi(foo)
14176 lh $4,%lo(foo+2)($4)
14177
14178 ...which is legal on RELA targets, and has a well-defined behaviour
14179 if the user knows that adding 2 to "foo" will not induce a carry to
14180 the high 16 bits.
14181
14182 When several %lo()s match a particular %got() or %hi(), we use the
14183 following rules to distinguish them:
14184
14185 (1) %lo()s with smaller offsets are a better match than %lo()s with
14186 higher offsets.
14187
14188 (2) %lo()s with no matching %got() or %hi() are better than those
14189 that already have a matching %got() or %hi().
14190
14191 (3) later %lo()s are better than earlier %lo()s.
14192
14193 These rules are applied in order.
14194
14195 (1) means, among other things, that %lo()s with identical offsets are
14196 chosen if they exist.
14197
14198 (2) means that we won't associate several high-part relocations with
14199 the same low-part relocation unless there's no alternative. Having
14200 several high parts for the same low part is a GNU extension; this rule
14201 allows careful users to avoid it.
14202
14203 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14204 with the last high-part relocation being at the front of the list.
14205 It therefore makes sense to choose the last matching low-part
14206 relocation, all other things being equal. It's also easier
14207 to code that way. */
252b5132
RH
14208
14209void
17a2f251 14210mips_frob_file (void)
252b5132
RH
14211{
14212 struct mips_hi_fixup *l;
35903be0 14213 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
252b5132
RH
14214
14215 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14216 {
14217 segment_info_type *seginfo;
3b91255e
RS
14218 bfd_boolean matched_lo_p;
14219 fixS **hi_pos, **lo_pos, **pos;
252b5132 14220
9c2799c2 14221 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
252b5132 14222
5919d012 14223 /* If a GOT16 relocation turns out to be against a global symbol,
b886a2ab
RS
14224 there isn't supposed to be a matching LO. Ignore %gots against
14225 constants; we'll report an error for those later. */
738e5348 14226 if (got16_reloc_p (l->fixp->fx_r_type)
b886a2ab
RS
14227 && !(l->fixp->fx_addsy
14228 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
5919d012
RS
14229 continue;
14230
14231 /* Check quickly whether the next fixup happens to be a matching %lo. */
14232 if (fixup_has_matching_lo_p (l->fixp))
252b5132
RH
14233 continue;
14234
252b5132 14235 seginfo = seg_info (l->seg);
252b5132 14236
3b91255e
RS
14237 /* Set HI_POS to the position of this relocation in the chain.
14238 Set LO_POS to the position of the chosen low-part relocation.
14239 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14240 relocation that matches an immediately-preceding high-part
14241 relocation. */
14242 hi_pos = NULL;
14243 lo_pos = NULL;
14244 matched_lo_p = FALSE;
738e5348 14245 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
35903be0 14246
3b91255e
RS
14247 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14248 {
14249 if (*pos == l->fixp)
14250 hi_pos = pos;
14251
35903be0 14252 if ((*pos)->fx_r_type == looking_for_rtype
30cfc97a 14253 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
3b91255e
RS
14254 && (*pos)->fx_offset >= l->fixp->fx_offset
14255 && (lo_pos == NULL
14256 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14257 || (!matched_lo_p
14258 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14259 lo_pos = pos;
14260
14261 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14262 && fixup_has_matching_lo_p (*pos));
14263 }
14264
14265 /* If we found a match, remove the high-part relocation from its
14266 current position and insert it before the low-part relocation.
14267 Make the offsets match so that fixup_has_matching_lo_p()
14268 will return true.
14269
14270 We don't warn about unmatched high-part relocations since some
14271 versions of gcc have been known to emit dead "lui ...%hi(...)"
14272 instructions. */
14273 if (lo_pos != NULL)
14274 {
14275 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14276 if (l->fixp->fx_next != *lo_pos)
252b5132 14277 {
3b91255e
RS
14278 *hi_pos = l->fixp->fx_next;
14279 l->fixp->fx_next = *lo_pos;
14280 *lo_pos = l->fixp;
252b5132 14281 }
252b5132
RH
14282 }
14283 }
14284}
14285
252b5132 14286int
17a2f251 14287mips_force_relocation (fixS *fixp)
252b5132 14288{
ae6063d4 14289 if (generic_force_reloc (fixp))
252b5132
RH
14290 return 1;
14291
df58fc94
RS
14292 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14293 so that the linker relaxation can update targets. */
14294 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14295 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14296 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14297 return 1;
14298
3e722fb5 14299 return 0;
252b5132
RH
14300}
14301
b886a2ab
RS
14302/* Read the instruction associated with RELOC from BUF. */
14303
14304static unsigned int
14305read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14306{
14307 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14308 return read_compressed_insn (buf, 4);
14309 else
14310 return read_insn (buf);
14311}
14312
14313/* Write instruction INSN to BUF, given that it has been relocated
14314 by RELOC. */
14315
14316static void
14317write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14318 unsigned long insn)
14319{
14320 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14321 write_compressed_insn (buf, insn, 4);
14322 else
14323 write_insn (buf, insn);
14324}
14325
252b5132
RH
14326/* Apply a fixup to the object file. */
14327
94f592af 14328void
55cf6793 14329md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 14330{
4d68580a 14331 char *buf;
b886a2ab 14332 unsigned long insn;
a7ebbfdf 14333 reloc_howto_type *howto;
252b5132 14334
a7ebbfdf
TS
14335 /* We ignore generic BFD relocations we don't know about. */
14336 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14337 if (! howto)
14338 return;
65551fa4 14339
df58fc94
RS
14340 gas_assert (fixP->fx_size == 2
14341 || fixP->fx_size == 4
90ecf173
MR
14342 || fixP->fx_r_type == BFD_RELOC_16
14343 || fixP->fx_r_type == BFD_RELOC_64
14344 || fixP->fx_r_type == BFD_RELOC_CTOR
14345 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
df58fc94 14346 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
90ecf173
MR
14347 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14348 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14349 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
252b5132 14350
4d68580a 14351 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
252b5132 14352
df58fc94
RS
14353 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
14354 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14355 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
b47468a6
CM
14356 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
14357 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
b1dca8ee
RS
14358
14359 /* Don't treat parts of a composite relocation as done. There are two
14360 reasons for this:
14361
14362 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14363 should nevertheless be emitted if the first part is.
14364
14365 (2) In normal usage, composite relocations are never assembly-time
14366 constants. The easiest way of dealing with the pathological
14367 exceptions is to generate a relocation against STN_UNDEF and
14368 leave everything up to the linker. */
3994f87e 14369 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
252b5132
RH
14370 fixP->fx_done = 1;
14371
14372 switch (fixP->fx_r_type)
14373 {
3f98094e
DJ
14374 case BFD_RELOC_MIPS_TLS_GD:
14375 case BFD_RELOC_MIPS_TLS_LDM:
741d6ea8
JM
14376 case BFD_RELOC_MIPS_TLS_DTPREL32:
14377 case BFD_RELOC_MIPS_TLS_DTPREL64:
3f98094e
DJ
14378 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14379 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14380 case BFD_RELOC_MIPS_TLS_GOTTPREL:
d0f13682
CLT
14381 case BFD_RELOC_MIPS_TLS_TPREL32:
14382 case BFD_RELOC_MIPS_TLS_TPREL64:
3f98094e
DJ
14383 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14384 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
df58fc94
RS
14385 case BFD_RELOC_MICROMIPS_TLS_GD:
14386 case BFD_RELOC_MICROMIPS_TLS_LDM:
14387 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14388 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14389 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14390 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14391 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
d0f13682
CLT
14392 case BFD_RELOC_MIPS16_TLS_GD:
14393 case BFD_RELOC_MIPS16_TLS_LDM:
14394 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14395 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14396 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14397 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14398 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
b886a2ab
RS
14399 if (!fixP->fx_addsy)
14400 {
14401 as_bad_where (fixP->fx_file, fixP->fx_line,
14402 _("TLS relocation against a constant"));
14403 break;
14404 }
3f98094e
DJ
14405 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14406 /* fall through */
14407
252b5132 14408 case BFD_RELOC_MIPS_JMP:
e369bcce
TS
14409 case BFD_RELOC_MIPS_SHIFT5:
14410 case BFD_RELOC_MIPS_SHIFT6:
14411 case BFD_RELOC_MIPS_GOT_DISP:
14412 case BFD_RELOC_MIPS_GOT_PAGE:
14413 case BFD_RELOC_MIPS_GOT_OFST:
14414 case BFD_RELOC_MIPS_SUB:
14415 case BFD_RELOC_MIPS_INSERT_A:
14416 case BFD_RELOC_MIPS_INSERT_B:
14417 case BFD_RELOC_MIPS_DELETE:
14418 case BFD_RELOC_MIPS_HIGHEST:
14419 case BFD_RELOC_MIPS_HIGHER:
14420 case BFD_RELOC_MIPS_SCN_DISP:
14421 case BFD_RELOC_MIPS_REL16:
14422 case BFD_RELOC_MIPS_RELGOT:
14423 case BFD_RELOC_MIPS_JALR:
252b5132
RH
14424 case BFD_RELOC_HI16:
14425 case BFD_RELOC_HI16_S:
b886a2ab 14426 case BFD_RELOC_LO16:
cdf6fd85 14427 case BFD_RELOC_GPREL16:
252b5132
RH
14428 case BFD_RELOC_MIPS_LITERAL:
14429 case BFD_RELOC_MIPS_CALL16:
14430 case BFD_RELOC_MIPS_GOT16:
cdf6fd85 14431 case BFD_RELOC_GPREL32:
252b5132
RH
14432 case BFD_RELOC_MIPS_GOT_HI16:
14433 case BFD_RELOC_MIPS_GOT_LO16:
14434 case BFD_RELOC_MIPS_CALL_HI16:
14435 case BFD_RELOC_MIPS_CALL_LO16:
14436 case BFD_RELOC_MIPS16_GPREL:
738e5348
RS
14437 case BFD_RELOC_MIPS16_GOT16:
14438 case BFD_RELOC_MIPS16_CALL16:
d6f16593
MR
14439 case BFD_RELOC_MIPS16_HI16:
14440 case BFD_RELOC_MIPS16_HI16_S:
b886a2ab 14441 case BFD_RELOC_MIPS16_LO16:
252b5132 14442 case BFD_RELOC_MIPS16_JMP:
df58fc94
RS
14443 case BFD_RELOC_MICROMIPS_JMP:
14444 case BFD_RELOC_MICROMIPS_GOT_DISP:
14445 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14446 case BFD_RELOC_MICROMIPS_GOT_OFST:
14447 case BFD_RELOC_MICROMIPS_SUB:
14448 case BFD_RELOC_MICROMIPS_HIGHEST:
14449 case BFD_RELOC_MICROMIPS_HIGHER:
14450 case BFD_RELOC_MICROMIPS_SCN_DISP:
14451 case BFD_RELOC_MICROMIPS_JALR:
14452 case BFD_RELOC_MICROMIPS_HI16:
14453 case BFD_RELOC_MICROMIPS_HI16_S:
b886a2ab 14454 case BFD_RELOC_MICROMIPS_LO16:
df58fc94
RS
14455 case BFD_RELOC_MICROMIPS_GPREL16:
14456 case BFD_RELOC_MICROMIPS_LITERAL:
14457 case BFD_RELOC_MICROMIPS_CALL16:
14458 case BFD_RELOC_MICROMIPS_GOT16:
14459 case BFD_RELOC_MICROMIPS_GOT_HI16:
14460 case BFD_RELOC_MICROMIPS_GOT_LO16:
14461 case BFD_RELOC_MICROMIPS_CALL_HI16:
14462 case BFD_RELOC_MICROMIPS_CALL_LO16:
067ec077 14463 case BFD_RELOC_MIPS_EH:
b886a2ab
RS
14464 if (fixP->fx_done)
14465 {
14466 offsetT value;
14467
14468 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14469 {
14470 insn = read_reloc_insn (buf, fixP->fx_r_type);
14471 if (mips16_reloc_p (fixP->fx_r_type))
14472 insn |= mips16_immed_extend (value, 16);
14473 else
14474 insn |= (value & 0xffff);
14475 write_reloc_insn (buf, fixP->fx_r_type, insn);
14476 }
14477 else
14478 as_bad_where (fixP->fx_file, fixP->fx_line,
14479 _("Unsupported constant in relocation"));
14480 }
252b5132
RH
14481 break;
14482
252b5132
RH
14483 case BFD_RELOC_64:
14484 /* This is handled like BFD_RELOC_32, but we output a sign
14485 extended value if we are only 32 bits. */
3e722fb5 14486 if (fixP->fx_done)
252b5132
RH
14487 {
14488 if (8 <= sizeof (valueT))
4d68580a 14489 md_number_to_chars (buf, *valP, 8);
252b5132
RH
14490 else
14491 {
a7ebbfdf 14492 valueT hiv;
252b5132 14493
a7ebbfdf 14494 if ((*valP & 0x80000000) != 0)
252b5132
RH
14495 hiv = 0xffffffff;
14496 else
14497 hiv = 0;
4d68580a
RS
14498 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14499 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
252b5132
RH
14500 }
14501 }
14502 break;
14503
056350c6 14504 case BFD_RELOC_RVA:
252b5132 14505 case BFD_RELOC_32:
b47468a6 14506 case BFD_RELOC_32_PCREL:
252b5132
RH
14507 case BFD_RELOC_16:
14508 /* If we are deleting this reloc entry, we must fill in the
54f4ddb3
TS
14509 value now. This can happen if we have a .word which is not
14510 resolved when it appears but is later defined. */
252b5132 14511 if (fixP->fx_done)
4d68580a 14512 md_number_to_chars (buf, *valP, fixP->fx_size);
252b5132
RH
14513 break;
14514
252b5132 14515 case BFD_RELOC_16_PCREL_S2:
a7ebbfdf 14516 if ((*valP & 0x3) != 0)
cb56d3d3 14517 as_bad_where (fixP->fx_file, fixP->fx_line,
bad36eac 14518 _("Branch to misaligned address (%lx)"), (long) *valP);
cb56d3d3 14519
54f4ddb3
TS
14520 /* We need to save the bits in the instruction since fixup_segment()
14521 might be deleting the relocation entry (i.e., a branch within
14522 the current segment). */
a7ebbfdf 14523 if (! fixP->fx_done)
bb2d6cd7 14524 break;
252b5132 14525
54f4ddb3 14526 /* Update old instruction data. */
4d68580a 14527 insn = read_insn (buf);
252b5132 14528
a7ebbfdf
TS
14529 if (*valP + 0x20000 <= 0x3ffff)
14530 {
14531 insn |= (*valP >> 2) & 0xffff;
4d68580a 14532 write_insn (buf, insn);
a7ebbfdf
TS
14533 }
14534 else if (mips_pic == NO_PIC
14535 && fixP->fx_done
14536 && fixP->fx_frag->fr_address >= text_section->vma
14537 && (fixP->fx_frag->fr_address
587aac4e 14538 < text_section->vma + bfd_get_section_size (text_section))
a7ebbfdf
TS
14539 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14540 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14541 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
252b5132
RH
14542 {
14543 /* The branch offset is too large. If this is an
14544 unconditional branch, and we are not generating PIC code,
14545 we can convert it to an absolute jump instruction. */
a7ebbfdf
TS
14546 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14547 insn = 0x0c000000; /* jal */
252b5132 14548 else
a7ebbfdf
TS
14549 insn = 0x08000000; /* j */
14550 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14551 fixP->fx_done = 0;
14552 fixP->fx_addsy = section_symbol (text_section);
14553 *valP += md_pcrel_from (fixP);
4d68580a 14554 write_insn (buf, insn);
a7ebbfdf
TS
14555 }
14556 else
14557 {
14558 /* If we got here, we have branch-relaxation disabled,
14559 and there's nothing we can do to fix this instruction
14560 without turning it into a longer sequence. */
14561 as_bad_where (fixP->fx_file, fixP->fx_line,
14562 _("Branch out of range"));
252b5132 14563 }
252b5132
RH
14564 break;
14565
df58fc94
RS
14566 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14567 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14568 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14569 /* We adjust the offset back to even. */
14570 if ((*valP & 0x1) != 0)
14571 --(*valP);
14572
14573 if (! fixP->fx_done)
14574 break;
14575
14576 /* Should never visit here, because we keep the relocation. */
14577 abort ();
14578 break;
14579
252b5132
RH
14580 case BFD_RELOC_VTABLE_INHERIT:
14581 fixP->fx_done = 0;
14582 if (fixP->fx_addsy
14583 && !S_IS_DEFINED (fixP->fx_addsy)
14584 && !S_IS_WEAK (fixP->fx_addsy))
14585 S_SET_WEAK (fixP->fx_addsy);
14586 break;
14587
14588 case BFD_RELOC_VTABLE_ENTRY:
14589 fixP->fx_done = 0;
14590 break;
14591
14592 default:
b37df7c4 14593 abort ();
252b5132 14594 }
a7ebbfdf
TS
14595
14596 /* Remember value for tc_gen_reloc. */
14597 fixP->fx_addnumber = *valP;
252b5132
RH
14598}
14599
252b5132 14600static symbolS *
17a2f251 14601get_symbol (void)
252b5132
RH
14602{
14603 int c;
14604 char *name;
14605 symbolS *p;
14606
14607 name = input_line_pointer;
14608 c = get_symbol_end ();
14609 p = (symbolS *) symbol_find_or_make (name);
14610 *input_line_pointer = c;
14611 return p;
14612}
14613
742a56fe
RS
14614/* Align the current frag to a given power of two. If a particular
14615 fill byte should be used, FILL points to an integer that contains
14616 that byte, otherwise FILL is null.
14617
462427c4
RS
14618 This function used to have the comment:
14619
14620 The MIPS assembler also automatically adjusts any preceding label.
14621
14622 The implementation therefore applied the adjustment to a maximum of
14623 one label. However, other label adjustments are applied to batches
14624 of labels, and adjusting just one caused problems when new labels
14625 were added for the sake of debugging or unwind information.
14626 We therefore adjust all preceding labels (given as LABELS) instead. */
252b5132
RH
14627
14628static void
462427c4 14629mips_align (int to, int *fill, struct insn_label_list *labels)
252b5132 14630{
7d10b47d 14631 mips_emit_delays ();
df58fc94 14632 mips_record_compressed_mode ();
742a56fe
RS
14633 if (fill == NULL && subseg_text_p (now_seg))
14634 frag_align_code (to, 0);
14635 else
14636 frag_align (to, fill ? *fill : 0, 0);
252b5132 14637 record_alignment (now_seg, to);
462427c4 14638 mips_move_labels (labels, FALSE);
252b5132
RH
14639}
14640
14641/* Align to a given power of two. .align 0 turns off the automatic
14642 alignment used by the data creating pseudo-ops. */
14643
14644static void
17a2f251 14645s_align (int x ATTRIBUTE_UNUSED)
252b5132 14646{
742a56fe 14647 int temp, fill_value, *fill_ptr;
49954fb4 14648 long max_alignment = 28;
252b5132 14649
54f4ddb3 14650 /* o Note that the assembler pulls down any immediately preceding label
252b5132 14651 to the aligned address.
54f4ddb3 14652 o It's not documented but auto alignment is reinstated by
252b5132 14653 a .align pseudo instruction.
54f4ddb3 14654 o Note also that after auto alignment is turned off the mips assembler
252b5132 14655 issues an error on attempt to assemble an improperly aligned data item.
54f4ddb3 14656 We don't. */
252b5132
RH
14657
14658 temp = get_absolute_expression ();
14659 if (temp > max_alignment)
14660 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
14661 else if (temp < 0)
14662 {
14663 as_warn (_("Alignment negative: 0 assumed."));
14664 temp = 0;
14665 }
14666 if (*input_line_pointer == ',')
14667 {
f9419b05 14668 ++input_line_pointer;
742a56fe
RS
14669 fill_value = get_absolute_expression ();
14670 fill_ptr = &fill_value;
252b5132
RH
14671 }
14672 else
742a56fe 14673 fill_ptr = 0;
252b5132
RH
14674 if (temp)
14675 {
a8dbcb85
TS
14676 segment_info_type *si = seg_info (now_seg);
14677 struct insn_label_list *l = si->label_list;
54f4ddb3 14678 /* Auto alignment should be switched on by next section change. */
252b5132 14679 auto_align = 1;
462427c4 14680 mips_align (temp, fill_ptr, l);
252b5132
RH
14681 }
14682 else
14683 {
14684 auto_align = 0;
14685 }
14686
14687 demand_empty_rest_of_line ();
14688}
14689
252b5132 14690static void
17a2f251 14691s_change_sec (int sec)
252b5132
RH
14692{
14693 segT seg;
14694
252b5132
RH
14695 /* The ELF backend needs to know that we are changing sections, so
14696 that .previous works correctly. We could do something like check
b6ff326e 14697 for an obj_section_change_hook macro, but that might be confusing
252b5132
RH
14698 as it would not be appropriate to use it in the section changing
14699 functions in read.c, since obj-elf.c intercepts those. FIXME:
14700 This should be cleaner, somehow. */
f3ded42a 14701 obj_elf_section_change_hook ();
252b5132 14702
7d10b47d 14703 mips_emit_delays ();
6a32d874 14704
252b5132
RH
14705 switch (sec)
14706 {
14707 case 't':
14708 s_text (0);
14709 break;
14710 case 'd':
14711 s_data (0);
14712 break;
14713 case 'b':
14714 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14715 demand_empty_rest_of_line ();
14716 break;
14717
14718 case 'r':
4d0d148d
TS
14719 seg = subseg_new (RDATA_SECTION_NAME,
14720 (subsegT) get_absolute_expression ());
f3ded42a
RS
14721 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14722 | SEC_READONLY | SEC_RELOC
14723 | SEC_DATA));
14724 if (strncmp (TARGET_OS, "elf", 3) != 0)
14725 record_alignment (seg, 4);
4d0d148d 14726 demand_empty_rest_of_line ();
252b5132
RH
14727 break;
14728
14729 case 's':
4d0d148d 14730 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
f3ded42a
RS
14731 bfd_set_section_flags (stdoutput, seg,
14732 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14733 if (strncmp (TARGET_OS, "elf", 3) != 0)
14734 record_alignment (seg, 4);
4d0d148d
TS
14735 demand_empty_rest_of_line ();
14736 break;
998b3c36
MR
14737
14738 case 'B':
14739 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
f3ded42a
RS
14740 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14741 if (strncmp (TARGET_OS, "elf", 3) != 0)
14742 record_alignment (seg, 4);
998b3c36
MR
14743 demand_empty_rest_of_line ();
14744 break;
252b5132
RH
14745 }
14746
14747 auto_align = 1;
14748}
b34976b6 14749
cca86cc8 14750void
17a2f251 14751s_change_section (int ignore ATTRIBUTE_UNUSED)
cca86cc8 14752{
cca86cc8
SC
14753 char *section_name;
14754 char c;
684022ea 14755 char next_c = 0;
cca86cc8
SC
14756 int section_type;
14757 int section_flag;
14758 int section_entry_size;
14759 int section_alignment;
b34976b6 14760
cca86cc8
SC
14761 section_name = input_line_pointer;
14762 c = get_symbol_end ();
a816d1ed
AO
14763 if (c)
14764 next_c = *(input_line_pointer + 1);
cca86cc8 14765
4cf0dd0d
TS
14766 /* Do we have .section Name<,"flags">? */
14767 if (c != ',' || (c == ',' && next_c == '"'))
cca86cc8 14768 {
4cf0dd0d
TS
14769 /* just after name is now '\0'. */
14770 *input_line_pointer = c;
cca86cc8
SC
14771 input_line_pointer = section_name;
14772 obj_elf_section (ignore);
14773 return;
14774 }
14775 input_line_pointer++;
14776
14777 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14778 if (c == ',')
14779 section_type = get_absolute_expression ();
14780 else
14781 section_type = 0;
14782 if (*input_line_pointer++ == ',')
14783 section_flag = get_absolute_expression ();
14784 else
14785 section_flag = 0;
14786 if (*input_line_pointer++ == ',')
14787 section_entry_size = get_absolute_expression ();
14788 else
14789 section_entry_size = 0;
14790 if (*input_line_pointer++ == ',')
14791 section_alignment = get_absolute_expression ();
14792 else
14793 section_alignment = 0;
87975d2a
AM
14794 /* FIXME: really ignore? */
14795 (void) section_alignment;
cca86cc8 14796
a816d1ed
AO
14797 section_name = xstrdup (section_name);
14798
8ab8a5c8
RS
14799 /* When using the generic form of .section (as implemented by obj-elf.c),
14800 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14801 traditionally had to fall back on the more common @progbits instead.
14802
14803 There's nothing really harmful in this, since bfd will correct
14804 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
708587a4 14805 means that, for backwards compatibility, the special_section entries
8ab8a5c8
RS
14806 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14807
14808 Even so, we shouldn't force users of the MIPS .section syntax to
14809 incorrectly label the sections as SHT_PROGBITS. The best compromise
14810 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14811 generic type-checking code. */
14812 if (section_type == SHT_MIPS_DWARF)
14813 section_type = SHT_PROGBITS;
14814
cca86cc8
SC
14815 obj_elf_change_section (section_name, section_type, section_flag,
14816 section_entry_size, 0, 0, 0);
a816d1ed
AO
14817
14818 if (now_seg->name != section_name)
14819 free (section_name);
cca86cc8 14820}
252b5132
RH
14821
14822void
17a2f251 14823mips_enable_auto_align (void)
252b5132
RH
14824{
14825 auto_align = 1;
14826}
14827
14828static void
17a2f251 14829s_cons (int log_size)
252b5132 14830{
a8dbcb85
TS
14831 segment_info_type *si = seg_info (now_seg);
14832 struct insn_label_list *l = si->label_list;
252b5132 14833
7d10b47d 14834 mips_emit_delays ();
252b5132 14835 if (log_size > 0 && auto_align)
462427c4 14836 mips_align (log_size, 0, l);
252b5132 14837 cons (1 << log_size);
a1facbec 14838 mips_clear_insn_labels ();
252b5132
RH
14839}
14840
14841static void
17a2f251 14842s_float_cons (int type)
252b5132 14843{
a8dbcb85
TS
14844 segment_info_type *si = seg_info (now_seg);
14845 struct insn_label_list *l = si->label_list;
252b5132 14846
7d10b47d 14847 mips_emit_delays ();
252b5132
RH
14848
14849 if (auto_align)
49309057
ILT
14850 {
14851 if (type == 'd')
462427c4 14852 mips_align (3, 0, l);
49309057 14853 else
462427c4 14854 mips_align (2, 0, l);
49309057 14855 }
252b5132 14856
252b5132 14857 float_cons (type);
a1facbec 14858 mips_clear_insn_labels ();
252b5132
RH
14859}
14860
14861/* Handle .globl. We need to override it because on Irix 5 you are
14862 permitted to say
14863 .globl foo .text
14864 where foo is an undefined symbol, to mean that foo should be
14865 considered to be the address of a function. */
14866
14867static void
17a2f251 14868s_mips_globl (int x ATTRIBUTE_UNUSED)
252b5132
RH
14869{
14870 char *name;
14871 int c;
14872 symbolS *symbolP;
14873 flagword flag;
14874
8a06b769 14875 do
252b5132 14876 {
8a06b769 14877 name = input_line_pointer;
252b5132 14878 c = get_symbol_end ();
8a06b769
TS
14879 symbolP = symbol_find_or_make (name);
14880 S_SET_EXTERNAL (symbolP);
14881
252b5132 14882 *input_line_pointer = c;
8a06b769 14883 SKIP_WHITESPACE ();
252b5132 14884
8a06b769
TS
14885 /* On Irix 5, every global symbol that is not explicitly labelled as
14886 being a function is apparently labelled as being an object. */
14887 flag = BSF_OBJECT;
252b5132 14888
8a06b769
TS
14889 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14890 && (*input_line_pointer != ','))
14891 {
14892 char *secname;
14893 asection *sec;
14894
14895 secname = input_line_pointer;
14896 c = get_symbol_end ();
14897 sec = bfd_get_section_by_name (stdoutput, secname);
14898 if (sec == NULL)
14899 as_bad (_("%s: no such section"), secname);
14900 *input_line_pointer = c;
14901
14902 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14903 flag = BSF_FUNCTION;
14904 }
14905
14906 symbol_get_bfdsym (symbolP)->flags |= flag;
14907
14908 c = *input_line_pointer;
14909 if (c == ',')
14910 {
14911 input_line_pointer++;
14912 SKIP_WHITESPACE ();
14913 if (is_end_of_line[(unsigned char) *input_line_pointer])
14914 c = '\n';
14915 }
14916 }
14917 while (c == ',');
252b5132 14918
252b5132
RH
14919 demand_empty_rest_of_line ();
14920}
14921
14922static void
17a2f251 14923s_option (int x ATTRIBUTE_UNUSED)
252b5132
RH
14924{
14925 char *opt;
14926 char c;
14927
14928 opt = input_line_pointer;
14929 c = get_symbol_end ();
14930
14931 if (*opt == 'O')
14932 {
14933 /* FIXME: What does this mean? */
14934 }
14935 else if (strncmp (opt, "pic", 3) == 0)
14936 {
14937 int i;
14938
14939 i = atoi (opt + 3);
14940 if (i == 0)
14941 mips_pic = NO_PIC;
14942 else if (i == 2)
143d77c5 14943 {
8b828383 14944 mips_pic = SVR4_PIC;
143d77c5
EC
14945 mips_abicalls = TRUE;
14946 }
252b5132
RH
14947 else
14948 as_bad (_(".option pic%d not supported"), i);
14949
4d0d148d 14950 if (mips_pic == SVR4_PIC)
252b5132
RH
14951 {
14952 if (g_switch_seen && g_switch_value != 0)
14953 as_warn (_("-G may not be used with SVR4 PIC code"));
14954 g_switch_value = 0;
14955 bfd_set_gp_size (stdoutput, 0);
14956 }
14957 }
14958 else
14959 as_warn (_("Unrecognized option \"%s\""), opt);
14960
14961 *input_line_pointer = c;
14962 demand_empty_rest_of_line ();
14963}
14964
14965/* This structure is used to hold a stack of .set values. */
14966
e972090a
NC
14967struct mips_option_stack
14968{
252b5132
RH
14969 struct mips_option_stack *next;
14970 struct mips_set_options options;
14971};
14972
14973static struct mips_option_stack *mips_opts_stack;
14974
14975/* Handle the .set pseudo-op. */
14976
14977static void
17a2f251 14978s_mipsset (int x ATTRIBUTE_UNUSED)
252b5132
RH
14979{
14980 char *name = input_line_pointer, ch;
c6278170 14981 const struct mips_ase *ase;
252b5132
RH
14982
14983 while (!is_end_of_line[(unsigned char) *input_line_pointer])
f9419b05 14984 ++input_line_pointer;
252b5132
RH
14985 ch = *input_line_pointer;
14986 *input_line_pointer = '\0';
14987
14988 if (strcmp (name, "reorder") == 0)
14989 {
7d10b47d
RS
14990 if (mips_opts.noreorder)
14991 end_noreorder ();
252b5132
RH
14992 }
14993 else if (strcmp (name, "noreorder") == 0)
14994 {
7d10b47d
RS
14995 if (!mips_opts.noreorder)
14996 start_noreorder ();
252b5132 14997 }
741fe287
MR
14998 else if (strncmp (name, "at=", 3) == 0)
14999 {
15000 char *s = name + 3;
15001
15002 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15003 as_bad (_("Unrecognized register name `%s'"), s);
15004 }
252b5132
RH
15005 else if (strcmp (name, "at") == 0)
15006 {
741fe287 15007 mips_opts.at = ATREG;
252b5132
RH
15008 }
15009 else if (strcmp (name, "noat") == 0)
15010 {
741fe287 15011 mips_opts.at = ZERO;
252b5132
RH
15012 }
15013 else if (strcmp (name, "macro") == 0)
15014 {
15015 mips_opts.warn_about_macros = 0;
15016 }
15017 else if (strcmp (name, "nomacro") == 0)
15018 {
15019 if (mips_opts.noreorder == 0)
15020 as_bad (_("`noreorder' must be set before `nomacro'"));
15021 mips_opts.warn_about_macros = 1;
15022 }
15023 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15024 {
15025 mips_opts.nomove = 0;
15026 }
15027 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15028 {
15029 mips_opts.nomove = 1;
15030 }
15031 else if (strcmp (name, "bopt") == 0)
15032 {
15033 mips_opts.nobopt = 0;
15034 }
15035 else if (strcmp (name, "nobopt") == 0)
15036 {
15037 mips_opts.nobopt = 1;
15038 }
ad3fea08
TS
15039 else if (strcmp (name, "gp=default") == 0)
15040 mips_opts.gp32 = file_mips_gp32;
15041 else if (strcmp (name, "gp=32") == 0)
15042 mips_opts.gp32 = 1;
15043 else if (strcmp (name, "gp=64") == 0)
15044 {
15045 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
20203fb9 15046 as_warn (_("%s isa does not support 64-bit registers"),
ad3fea08
TS
15047 mips_cpu_info_from_isa (mips_opts.isa)->name);
15048 mips_opts.gp32 = 0;
15049 }
15050 else if (strcmp (name, "fp=default") == 0)
15051 mips_opts.fp32 = file_mips_fp32;
15052 else if (strcmp (name, "fp=32") == 0)
15053 mips_opts.fp32 = 1;
15054 else if (strcmp (name, "fp=64") == 0)
15055 {
15056 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
20203fb9 15057 as_warn (_("%s isa does not support 64-bit floating point registers"),
ad3fea08
TS
15058 mips_cpu_info_from_isa (mips_opts.isa)->name);
15059 mips_opts.fp32 = 0;
15060 }
037b32b9
AN
15061 else if (strcmp (name, "softfloat") == 0)
15062 mips_opts.soft_float = 1;
15063 else if (strcmp (name, "hardfloat") == 0)
15064 mips_opts.soft_float = 0;
15065 else if (strcmp (name, "singlefloat") == 0)
15066 mips_opts.single_float = 1;
15067 else if (strcmp (name, "doublefloat") == 0)
15068 mips_opts.single_float = 0;
252b5132
RH
15069 else if (strcmp (name, "mips16") == 0
15070 || strcmp (name, "MIPS-16") == 0)
df58fc94
RS
15071 {
15072 if (mips_opts.micromips == 1)
15073 as_fatal (_("`mips16' cannot be used with `micromips'"));
15074 mips_opts.mips16 = 1;
15075 }
252b5132
RH
15076 else if (strcmp (name, "nomips16") == 0
15077 || strcmp (name, "noMIPS-16") == 0)
15078 mips_opts.mips16 = 0;
df58fc94
RS
15079 else if (strcmp (name, "micromips") == 0)
15080 {
15081 if (mips_opts.mips16 == 1)
15082 as_fatal (_("`micromips' cannot be used with `mips16'"));
15083 mips_opts.micromips = 1;
15084 }
15085 else if (strcmp (name, "nomicromips") == 0)
15086 mips_opts.micromips = 0;
c6278170
RS
15087 else if (name[0] == 'n'
15088 && name[1] == 'o'
15089 && (ase = mips_lookup_ase (name + 2)))
15090 mips_set_ase (ase, FALSE);
15091 else if ((ase = mips_lookup_ase (name)))
15092 mips_set_ase (ase, TRUE);
1a2c1fad 15093 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
252b5132 15094 {
af7ee8bf 15095 int reset = 0;
252b5132 15096
1a2c1fad
CD
15097 /* Permit the user to change the ISA and architecture on the fly.
15098 Needless to say, misuse can cause serious problems. */
81a21e38 15099 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
af7ee8bf
CD
15100 {
15101 reset = 1;
15102 mips_opts.isa = file_mips_isa;
1a2c1fad 15103 mips_opts.arch = file_mips_arch;
1a2c1fad
CD
15104 }
15105 else if (strncmp (name, "arch=", 5) == 0)
15106 {
15107 const struct mips_cpu_info *p;
15108
15109 p = mips_parse_cpu("internal use", name + 5);
15110 if (!p)
15111 as_bad (_("unknown architecture %s"), name + 5);
15112 else
15113 {
15114 mips_opts.arch = p->cpu;
15115 mips_opts.isa = p->isa;
15116 }
15117 }
81a21e38
TS
15118 else if (strncmp (name, "mips", 4) == 0)
15119 {
15120 const struct mips_cpu_info *p;
15121
15122 p = mips_parse_cpu("internal use", name);
15123 if (!p)
15124 as_bad (_("unknown ISA level %s"), name + 4);
15125 else
15126 {
15127 mips_opts.arch = p->cpu;
15128 mips_opts.isa = p->isa;
15129 }
15130 }
af7ee8bf 15131 else
81a21e38 15132 as_bad (_("unknown ISA or architecture %s"), name);
af7ee8bf
CD
15133
15134 switch (mips_opts.isa)
98d3f06f
KH
15135 {
15136 case 0:
98d3f06f 15137 break;
af7ee8bf
CD
15138 case ISA_MIPS1:
15139 case ISA_MIPS2:
15140 case ISA_MIPS32:
15141 case ISA_MIPS32R2:
98d3f06f
KH
15142 mips_opts.gp32 = 1;
15143 mips_opts.fp32 = 1;
15144 break;
af7ee8bf
CD
15145 case ISA_MIPS3:
15146 case ISA_MIPS4:
15147 case ISA_MIPS5:
15148 case ISA_MIPS64:
5f74bc13 15149 case ISA_MIPS64R2:
98d3f06f 15150 mips_opts.gp32 = 0;
e407c74b
NC
15151 if (mips_opts.arch == CPU_R5900)
15152 {
15153 mips_opts.fp32 = 1;
15154 }
15155 else
15156 {
98d3f06f 15157 mips_opts.fp32 = 0;
e407c74b 15158 }
98d3f06f
KH
15159 break;
15160 default:
15161 as_bad (_("unknown ISA level %s"), name + 4);
15162 break;
15163 }
af7ee8bf 15164 if (reset)
98d3f06f 15165 {
af7ee8bf
CD
15166 mips_opts.gp32 = file_mips_gp32;
15167 mips_opts.fp32 = file_mips_fp32;
98d3f06f 15168 }
252b5132
RH
15169 }
15170 else if (strcmp (name, "autoextend") == 0)
15171 mips_opts.noautoextend = 0;
15172 else if (strcmp (name, "noautoextend") == 0)
15173 mips_opts.noautoextend = 1;
833794fc
MR
15174 else if (strcmp (name, "insn32") == 0)
15175 mips_opts.insn32 = TRUE;
15176 else if (strcmp (name, "noinsn32") == 0)
15177 mips_opts.insn32 = FALSE;
252b5132
RH
15178 else if (strcmp (name, "push") == 0)
15179 {
15180 struct mips_option_stack *s;
15181
15182 s = (struct mips_option_stack *) xmalloc (sizeof *s);
15183 s->next = mips_opts_stack;
15184 s->options = mips_opts;
15185 mips_opts_stack = s;
15186 }
15187 else if (strcmp (name, "pop") == 0)
15188 {
15189 struct mips_option_stack *s;
15190
15191 s = mips_opts_stack;
15192 if (s == NULL)
15193 as_bad (_(".set pop with no .set push"));
15194 else
15195 {
15196 /* If we're changing the reorder mode we need to handle
15197 delay slots correctly. */
15198 if (s->options.noreorder && ! mips_opts.noreorder)
7d10b47d 15199 start_noreorder ();
252b5132 15200 else if (! s->options.noreorder && mips_opts.noreorder)
7d10b47d 15201 end_noreorder ();
252b5132
RH
15202
15203 mips_opts = s->options;
15204 mips_opts_stack = s->next;
15205 free (s);
15206 }
15207 }
aed1a261
RS
15208 else if (strcmp (name, "sym32") == 0)
15209 mips_opts.sym32 = TRUE;
15210 else if (strcmp (name, "nosym32") == 0)
15211 mips_opts.sym32 = FALSE;
e6559e01
JM
15212 else if (strchr (name, ','))
15213 {
15214 /* Generic ".set" directive; use the generic handler. */
15215 *input_line_pointer = ch;
15216 input_line_pointer = name;
15217 s_set (0);
15218 return;
15219 }
252b5132
RH
15220 else
15221 {
15222 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
15223 }
c6278170 15224 mips_check_isa_supports_ases ();
252b5132
RH
15225 *input_line_pointer = ch;
15226 demand_empty_rest_of_line ();
15227}
15228
15229/* Handle the .abicalls pseudo-op. I believe this is equivalent to
15230 .option pic2. It means to generate SVR4 PIC calls. */
15231
15232static void
17a2f251 15233s_abicalls (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15234{
15235 mips_pic = SVR4_PIC;
143d77c5 15236 mips_abicalls = TRUE;
4d0d148d
TS
15237
15238 if (g_switch_seen && g_switch_value != 0)
15239 as_warn (_("-G may not be used with SVR4 PIC code"));
15240 g_switch_value = 0;
15241
252b5132
RH
15242 bfd_set_gp_size (stdoutput, 0);
15243 demand_empty_rest_of_line ();
15244}
15245
15246/* Handle the .cpload pseudo-op. This is used when generating SVR4
15247 PIC code. It sets the $gp register for the function based on the
15248 function address, which is in the register named in the argument.
15249 This uses a relocation against _gp_disp, which is handled specially
15250 by the linker. The result is:
15251 lui $gp,%hi(_gp_disp)
15252 addiu $gp,$gp,%lo(_gp_disp)
15253 addu $gp,$gp,.cpload argument
aa6975fb
ILT
15254 The .cpload argument is normally $25 == $t9.
15255
15256 The -mno-shared option changes this to:
bbe506e8
TS
15257 lui $gp,%hi(__gnu_local_gp)
15258 addiu $gp,$gp,%lo(__gnu_local_gp)
aa6975fb
ILT
15259 and the argument is ignored. This saves an instruction, but the
15260 resulting code is not position independent; it uses an absolute
bbe506e8
TS
15261 address for __gnu_local_gp. Thus code assembled with -mno-shared
15262 can go into an ordinary executable, but not into a shared library. */
252b5132
RH
15263
15264static void
17a2f251 15265s_cpload (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15266{
15267 expressionS ex;
aa6975fb
ILT
15268 int reg;
15269 int in_shared;
252b5132 15270
6478892d
TS
15271 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15272 .cpload is ignored. */
15273 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
15274 {
15275 s_ignore (0);
15276 return;
15277 }
15278
a276b80c
MR
15279 if (mips_opts.mips16)
15280 {
15281 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15282 ignore_rest_of_line ();
15283 return;
15284 }
15285
d3ecfc59 15286 /* .cpload should be in a .set noreorder section. */
252b5132
RH
15287 if (mips_opts.noreorder == 0)
15288 as_warn (_(".cpload not in noreorder section"));
15289
aa6975fb
ILT
15290 reg = tc_get_register (0);
15291
15292 /* If we need to produce a 64-bit address, we are better off using
15293 the default instruction sequence. */
aed1a261 15294 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
aa6975fb 15295
252b5132 15296 ex.X_op = O_symbol;
bbe506e8
TS
15297 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15298 "__gnu_local_gp");
252b5132
RH
15299 ex.X_op_symbol = NULL;
15300 ex.X_add_number = 0;
15301
15302 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
49309057 15303 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
252b5132 15304
8a75745d
MR
15305 mips_mark_labels ();
15306 mips_assembling_insn = TRUE;
15307
584892a6 15308 macro_start ();
67c0d1eb
RS
15309 macro_build_lui (&ex, mips_gp_register);
15310 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
17a2f251 15311 mips_gp_register, BFD_RELOC_LO16);
aa6975fb
ILT
15312 if (in_shared)
15313 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15314 mips_gp_register, reg);
584892a6 15315 macro_end ();
252b5132 15316
8a75745d 15317 mips_assembling_insn = FALSE;
252b5132
RH
15318 demand_empty_rest_of_line ();
15319}
15320
6478892d
TS
15321/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15322 .cpsetup $reg1, offset|$reg2, label
15323
15324 If offset is given, this results in:
15325 sd $gp, offset($sp)
956cd1d6 15326 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
15327 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15328 daddu $gp, $gp, $reg1
6478892d
TS
15329
15330 If $reg2 is given, this results in:
15331 daddu $reg2, $gp, $0
956cd1d6 15332 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
15333 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15334 daddu $gp, $gp, $reg1
aa6975fb
ILT
15335 $reg1 is normally $25 == $t9.
15336
15337 The -mno-shared option replaces the last three instructions with
15338 lui $gp,%hi(_gp)
54f4ddb3 15339 addiu $gp,$gp,%lo(_gp) */
aa6975fb 15340
6478892d 15341static void
17a2f251 15342s_cpsetup (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15343{
15344 expressionS ex_off;
15345 expressionS ex_sym;
15346 int reg1;
6478892d 15347
8586fc66 15348 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
6478892d
TS
15349 We also need NewABI support. */
15350 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15351 {
15352 s_ignore (0);
15353 return;
15354 }
15355
a276b80c
MR
15356 if (mips_opts.mips16)
15357 {
15358 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15359 ignore_rest_of_line ();
15360 return;
15361 }
15362
6478892d
TS
15363 reg1 = tc_get_register (0);
15364 SKIP_WHITESPACE ();
15365 if (*input_line_pointer != ',')
15366 {
15367 as_bad (_("missing argument separator ',' for .cpsetup"));
15368 return;
15369 }
15370 else
80245285 15371 ++input_line_pointer;
6478892d
TS
15372 SKIP_WHITESPACE ();
15373 if (*input_line_pointer == '$')
80245285
TS
15374 {
15375 mips_cpreturn_register = tc_get_register (0);
15376 mips_cpreturn_offset = -1;
15377 }
6478892d 15378 else
80245285
TS
15379 {
15380 mips_cpreturn_offset = get_absolute_expression ();
15381 mips_cpreturn_register = -1;
15382 }
6478892d
TS
15383 SKIP_WHITESPACE ();
15384 if (*input_line_pointer != ',')
15385 {
15386 as_bad (_("missing argument separator ',' for .cpsetup"));
15387 return;
15388 }
15389 else
f9419b05 15390 ++input_line_pointer;
6478892d 15391 SKIP_WHITESPACE ();
f21f8242 15392 expression (&ex_sym);
6478892d 15393
8a75745d
MR
15394 mips_mark_labels ();
15395 mips_assembling_insn = TRUE;
15396
584892a6 15397 macro_start ();
6478892d
TS
15398 if (mips_cpreturn_register == -1)
15399 {
15400 ex_off.X_op = O_constant;
15401 ex_off.X_add_symbol = NULL;
15402 ex_off.X_op_symbol = NULL;
15403 ex_off.X_add_number = mips_cpreturn_offset;
15404
67c0d1eb 15405 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
17a2f251 15406 BFD_RELOC_LO16, SP);
6478892d
TS
15407 }
15408 else
67c0d1eb 15409 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
17a2f251 15410 mips_gp_register, 0);
6478892d 15411
aed1a261 15412 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
aa6975fb 15413 {
df58fc94 15414 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
aa6975fb
ILT
15415 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15416 BFD_RELOC_HI16_S);
15417
15418 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15419 mips_gp_register, -1, BFD_RELOC_GPREL16,
15420 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15421
15422 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15423 mips_gp_register, reg1);
15424 }
15425 else
15426 {
15427 expressionS ex;
15428
15429 ex.X_op = O_symbol;
4184909a 15430 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
aa6975fb
ILT
15431 ex.X_op_symbol = NULL;
15432 ex.X_add_number = 0;
6e1304d8 15433
aa6975fb
ILT
15434 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15435 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15436
15437 macro_build_lui (&ex, mips_gp_register);
15438 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15439 mips_gp_register, BFD_RELOC_LO16);
15440 }
f21f8242 15441
584892a6 15442 macro_end ();
6478892d 15443
8a75745d 15444 mips_assembling_insn = FALSE;
6478892d
TS
15445 demand_empty_rest_of_line ();
15446}
15447
15448static void
17a2f251 15449s_cplocal (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15450{
15451 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
54f4ddb3 15452 .cplocal is ignored. */
6478892d
TS
15453 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15454 {
15455 s_ignore (0);
15456 return;
15457 }
15458
a276b80c
MR
15459 if (mips_opts.mips16)
15460 {
15461 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15462 ignore_rest_of_line ();
15463 return;
15464 }
15465
6478892d 15466 mips_gp_register = tc_get_register (0);
85b51719 15467 demand_empty_rest_of_line ();
6478892d
TS
15468}
15469
252b5132
RH
15470/* Handle the .cprestore pseudo-op. This stores $gp into a given
15471 offset from $sp. The offset is remembered, and after making a PIC
15472 call $gp is restored from that location. */
15473
15474static void
17a2f251 15475s_cprestore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15476{
15477 expressionS ex;
252b5132 15478
6478892d 15479 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
c9914766 15480 .cprestore is ignored. */
6478892d 15481 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
15482 {
15483 s_ignore (0);
15484 return;
15485 }
15486
a276b80c
MR
15487 if (mips_opts.mips16)
15488 {
15489 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15490 ignore_rest_of_line ();
15491 return;
15492 }
15493
252b5132 15494 mips_cprestore_offset = get_absolute_expression ();
7a621144 15495 mips_cprestore_valid = 1;
252b5132
RH
15496
15497 ex.X_op = O_constant;
15498 ex.X_add_symbol = NULL;
15499 ex.X_op_symbol = NULL;
15500 ex.X_add_number = mips_cprestore_offset;
15501
8a75745d
MR
15502 mips_mark_labels ();
15503 mips_assembling_insn = TRUE;
15504
584892a6 15505 macro_start ();
67c0d1eb
RS
15506 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15507 SP, HAVE_64BIT_ADDRESSES);
584892a6 15508 macro_end ();
252b5132 15509
8a75745d 15510 mips_assembling_insn = FALSE;
252b5132
RH
15511 demand_empty_rest_of_line ();
15512}
15513
6478892d 15514/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
67c1ffbe 15515 was given in the preceding .cpsetup, it results in:
6478892d 15516 ld $gp, offset($sp)
76b3015f 15517
6478892d 15518 If a register $reg2 was given there, it results in:
54f4ddb3
TS
15519 daddu $gp, $reg2, $0 */
15520
6478892d 15521static void
17a2f251 15522s_cpreturn (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15523{
15524 expressionS ex;
6478892d
TS
15525
15526 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15527 We also need NewABI support. */
15528 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15529 {
15530 s_ignore (0);
15531 return;
15532 }
15533
a276b80c
MR
15534 if (mips_opts.mips16)
15535 {
15536 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15537 ignore_rest_of_line ();
15538 return;
15539 }
15540
8a75745d
MR
15541 mips_mark_labels ();
15542 mips_assembling_insn = TRUE;
15543
584892a6 15544 macro_start ();
6478892d
TS
15545 if (mips_cpreturn_register == -1)
15546 {
15547 ex.X_op = O_constant;
15548 ex.X_add_symbol = NULL;
15549 ex.X_op_symbol = NULL;
15550 ex.X_add_number = mips_cpreturn_offset;
15551
67c0d1eb 15552 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
6478892d
TS
15553 }
15554 else
67c0d1eb 15555 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
17a2f251 15556 mips_cpreturn_register, 0);
584892a6 15557 macro_end ();
6478892d 15558
8a75745d 15559 mips_assembling_insn = FALSE;
6478892d
TS
15560 demand_empty_rest_of_line ();
15561}
15562
d0f13682
CLT
15563/* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15564 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15565 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15566 debug information or MIPS16 TLS. */
741d6ea8
JM
15567
15568static void
d0f13682
CLT
15569s_tls_rel_directive (const size_t bytes, const char *dirstr,
15570 bfd_reloc_code_real_type rtype)
741d6ea8
JM
15571{
15572 expressionS ex;
15573 char *p;
15574
15575 expression (&ex);
15576
15577 if (ex.X_op != O_symbol)
15578 {
d0f13682 15579 as_bad (_("Unsupported use of %s"), dirstr);
741d6ea8
JM
15580 ignore_rest_of_line ();
15581 }
15582
15583 p = frag_more (bytes);
15584 md_number_to_chars (p, 0, bytes);
d0f13682 15585 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
741d6ea8 15586 demand_empty_rest_of_line ();
de64cffd 15587 mips_clear_insn_labels ();
741d6ea8
JM
15588}
15589
15590/* Handle .dtprelword. */
15591
15592static void
15593s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15594{
d0f13682 15595 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
741d6ea8
JM
15596}
15597
15598/* Handle .dtpreldword. */
15599
15600static void
15601s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15602{
d0f13682
CLT
15603 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15604}
15605
15606/* Handle .tprelword. */
15607
15608static void
15609s_tprelword (int ignore ATTRIBUTE_UNUSED)
15610{
15611 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15612}
15613
15614/* Handle .tpreldword. */
15615
15616static void
15617s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15618{
15619 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
741d6ea8
JM
15620}
15621
6478892d
TS
15622/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15623 code. It sets the offset to use in gp_rel relocations. */
15624
15625static void
17a2f251 15626s_gpvalue (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
15627{
15628 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15629 We also need NewABI support. */
15630 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15631 {
15632 s_ignore (0);
15633 return;
15634 }
15635
def2e0dd 15636 mips_gprel_offset = get_absolute_expression ();
6478892d
TS
15637
15638 demand_empty_rest_of_line ();
15639}
15640
252b5132
RH
15641/* Handle the .gpword pseudo-op. This is used when generating PIC
15642 code. It generates a 32 bit GP relative reloc. */
15643
15644static void
17a2f251 15645s_gpword (int ignore ATTRIBUTE_UNUSED)
252b5132 15646{
a8dbcb85
TS
15647 segment_info_type *si;
15648 struct insn_label_list *l;
252b5132
RH
15649 expressionS ex;
15650 char *p;
15651
15652 /* When not generating PIC code, this is treated as .word. */
15653 if (mips_pic != SVR4_PIC)
15654 {
15655 s_cons (2);
15656 return;
15657 }
15658
a8dbcb85
TS
15659 si = seg_info (now_seg);
15660 l = si->label_list;
7d10b47d 15661 mips_emit_delays ();
252b5132 15662 if (auto_align)
462427c4 15663 mips_align (2, 0, l);
252b5132
RH
15664
15665 expression (&ex);
a1facbec 15666 mips_clear_insn_labels ();
252b5132
RH
15667
15668 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15669 {
15670 as_bad (_("Unsupported use of .gpword"));
15671 ignore_rest_of_line ();
15672 }
15673
15674 p = frag_more (4);
17a2f251 15675 md_number_to_chars (p, 0, 4);
b34976b6 15676 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
cdf6fd85 15677 BFD_RELOC_GPREL32);
252b5132
RH
15678
15679 demand_empty_rest_of_line ();
15680}
15681
10181a0d 15682static void
17a2f251 15683s_gpdword (int ignore ATTRIBUTE_UNUSED)
10181a0d 15684{
a8dbcb85
TS
15685 segment_info_type *si;
15686 struct insn_label_list *l;
10181a0d
AO
15687 expressionS ex;
15688 char *p;
15689
15690 /* When not generating PIC code, this is treated as .dword. */
15691 if (mips_pic != SVR4_PIC)
15692 {
15693 s_cons (3);
15694 return;
15695 }
15696
a8dbcb85
TS
15697 si = seg_info (now_seg);
15698 l = si->label_list;
7d10b47d 15699 mips_emit_delays ();
10181a0d 15700 if (auto_align)
462427c4 15701 mips_align (3, 0, l);
10181a0d
AO
15702
15703 expression (&ex);
a1facbec 15704 mips_clear_insn_labels ();
10181a0d
AO
15705
15706 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15707 {
15708 as_bad (_("Unsupported use of .gpdword"));
15709 ignore_rest_of_line ();
15710 }
15711
15712 p = frag_more (8);
17a2f251 15713 md_number_to_chars (p, 0, 8);
a105a300 15714 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
6e1304d8 15715 BFD_RELOC_GPREL32)->fx_tcbit = 1;
10181a0d
AO
15716
15717 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
6e1304d8
RS
15718 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15719 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
10181a0d
AO
15720
15721 demand_empty_rest_of_line ();
15722}
15723
a3f278e2
CM
15724/* Handle the .ehword pseudo-op. This is used when generating unwinding
15725 tables. It generates a R_MIPS_EH reloc. */
15726
15727static void
15728s_ehword (int ignore ATTRIBUTE_UNUSED)
15729{
15730 expressionS ex;
15731 char *p;
15732
15733 mips_emit_delays ();
15734
15735 expression (&ex);
15736 mips_clear_insn_labels ();
15737
15738 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15739 {
15740 as_bad (_("Unsupported use of .ehword"));
15741 ignore_rest_of_line ();
15742 }
15743
15744 p = frag_more (4);
15745 md_number_to_chars (p, 0, 4);
15746 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15747 BFD_RELOC_MIPS_EH);
15748
15749 demand_empty_rest_of_line ();
15750}
15751
252b5132
RH
15752/* Handle the .cpadd pseudo-op. This is used when dealing with switch
15753 tables in SVR4 PIC code. */
15754
15755static void
17a2f251 15756s_cpadd (int ignore ATTRIBUTE_UNUSED)
252b5132 15757{
252b5132
RH
15758 int reg;
15759
10181a0d
AO
15760 /* This is ignored when not generating SVR4 PIC code. */
15761 if (mips_pic != SVR4_PIC)
252b5132
RH
15762 {
15763 s_ignore (0);
15764 return;
15765 }
15766
8a75745d
MR
15767 mips_mark_labels ();
15768 mips_assembling_insn = TRUE;
15769
252b5132 15770 /* Add $gp to the register named as an argument. */
584892a6 15771 macro_start ();
252b5132 15772 reg = tc_get_register (0);
67c0d1eb 15773 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
584892a6 15774 macro_end ();
252b5132 15775
8a75745d 15776 mips_assembling_insn = FALSE;
bdaaa2e1 15777 demand_empty_rest_of_line ();
252b5132
RH
15778}
15779
15780/* Handle the .insn pseudo-op. This marks instruction labels in
df58fc94 15781 mips16/micromips mode. This permits the linker to handle them specially,
252b5132
RH
15782 such as generating jalx instructions when needed. We also make
15783 them odd for the duration of the assembly, in order to generate the
15784 right sort of code. We will make them even in the adjust_symtab
15785 routine, while leaving them marked. This is convenient for the
15786 debugger and the disassembler. The linker knows to make them odd
15787 again. */
15788
15789static void
17a2f251 15790s_insn (int ignore ATTRIBUTE_UNUSED)
252b5132 15791{
df58fc94 15792 mips_mark_labels ();
252b5132
RH
15793
15794 demand_empty_rest_of_line ();
15795}
15796
ba92f887
MR
15797/* Handle the .nan pseudo-op. */
15798
15799static void
15800s_nan (int ignore ATTRIBUTE_UNUSED)
15801{
15802 static const char str_legacy[] = "legacy";
15803 static const char str_2008[] = "2008";
15804 size_t i;
15805
15806 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15807
15808 if (i == sizeof (str_2008) - 1
15809 && memcmp (input_line_pointer, str_2008, i) == 0)
15810 mips_flag_nan2008 = TRUE;
15811 else if (i == sizeof (str_legacy) - 1
15812 && memcmp (input_line_pointer, str_legacy, i) == 0)
15813 mips_flag_nan2008 = FALSE;
15814 else
15815 as_bad (_("Bad .nan directive"));
15816
15817 input_line_pointer += i;
15818 demand_empty_rest_of_line ();
15819}
15820
754e2bb9
RS
15821/* Handle a .stab[snd] directive. Ideally these directives would be
15822 implemented in a transparent way, so that removing them would not
15823 have any effect on the generated instructions. However, s_stab
15824 internally changes the section, so in practice we need to decide
15825 now whether the preceding label marks compressed code. We do not
15826 support changing the compression mode of a label after a .stab*
15827 directive, such as in:
15828
15829 foo:
15830 .stabs ...
15831 .set mips16
15832
15833 so the current mode wins. */
252b5132
RH
15834
15835static void
17a2f251 15836s_mips_stab (int type)
252b5132 15837{
754e2bb9 15838 mips_mark_labels ();
252b5132
RH
15839 s_stab (type);
15840}
15841
54f4ddb3 15842/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
252b5132
RH
15843
15844static void
17a2f251 15845s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
15846{
15847 char *name;
15848 int c;
15849 symbolS *symbolP;
15850 expressionS exp;
15851
15852 name = input_line_pointer;
15853 c = get_symbol_end ();
15854 symbolP = symbol_find_or_make (name);
15855 S_SET_WEAK (symbolP);
15856 *input_line_pointer = c;
15857
15858 SKIP_WHITESPACE ();
15859
15860 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15861 {
15862 if (S_IS_DEFINED (symbolP))
15863 {
20203fb9 15864 as_bad (_("ignoring attempt to redefine symbol %s"),
252b5132
RH
15865 S_GET_NAME (symbolP));
15866 ignore_rest_of_line ();
15867 return;
15868 }
bdaaa2e1 15869
252b5132
RH
15870 if (*input_line_pointer == ',')
15871 {
15872 ++input_line_pointer;
15873 SKIP_WHITESPACE ();
15874 }
bdaaa2e1 15875
252b5132
RH
15876 expression (&exp);
15877 if (exp.X_op != O_symbol)
15878 {
20203fb9 15879 as_bad (_("bad .weakext directive"));
98d3f06f 15880 ignore_rest_of_line ();
252b5132
RH
15881 return;
15882 }
49309057 15883 symbol_set_value_expression (symbolP, &exp);
252b5132
RH
15884 }
15885
15886 demand_empty_rest_of_line ();
15887}
15888
15889/* Parse a register string into a number. Called from the ECOFF code
15890 to parse .frame. The argument is non-zero if this is the frame
15891 register, so that we can record it in mips_frame_reg. */
15892
15893int
17a2f251 15894tc_get_register (int frame)
252b5132 15895{
707bfff6 15896 unsigned int reg;
252b5132
RH
15897
15898 SKIP_WHITESPACE ();
707bfff6
TS
15899 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
15900 reg = 0;
252b5132 15901 if (frame)
7a621144
DJ
15902 {
15903 mips_frame_reg = reg != 0 ? reg : SP;
15904 mips_frame_reg_valid = 1;
15905 mips_cprestore_valid = 0;
15906 }
252b5132
RH
15907 return reg;
15908}
15909
15910valueT
17a2f251 15911md_section_align (asection *seg, valueT addr)
252b5132
RH
15912{
15913 int align = bfd_get_section_alignment (stdoutput, seg);
15914
f3ded42a
RS
15915 /* We don't need to align ELF sections to the full alignment.
15916 However, Irix 5 may prefer that we align them at least to a 16
15917 byte boundary. We don't bother to align the sections if we
15918 are targeted for an embedded system. */
15919 if (strncmp (TARGET_OS, "elf", 3) == 0)
15920 return addr;
15921 if (align > 4)
15922 align = 4;
252b5132
RH
15923
15924 return ((addr + (1 << align) - 1) & (-1 << align));
15925}
15926
15927/* Utility routine, called from above as well. If called while the
15928 input file is still being read, it's only an approximation. (For
15929 example, a symbol may later become defined which appeared to be
15930 undefined earlier.) */
15931
15932static int
17a2f251 15933nopic_need_relax (symbolS *sym, int before_relaxing)
252b5132
RH
15934{
15935 if (sym == 0)
15936 return 0;
15937
4d0d148d 15938 if (g_switch_value > 0)
252b5132
RH
15939 {
15940 const char *symname;
15941 int change;
15942
c9914766 15943 /* Find out whether this symbol can be referenced off the $gp
252b5132
RH
15944 register. It can be if it is smaller than the -G size or if
15945 it is in the .sdata or .sbss section. Certain symbols can
c9914766 15946 not be referenced off the $gp, although it appears as though
252b5132
RH
15947 they can. */
15948 symname = S_GET_NAME (sym);
15949 if (symname != (const char *) NULL
15950 && (strcmp (symname, "eprol") == 0
15951 || strcmp (symname, "etext") == 0
15952 || strcmp (symname, "_gp") == 0
15953 || strcmp (symname, "edata") == 0
15954 || strcmp (symname, "_fbss") == 0
15955 || strcmp (symname, "_fdata") == 0
15956 || strcmp (symname, "_ftext") == 0
15957 || strcmp (symname, "end") == 0
15958 || strcmp (symname, "_gp_disp") == 0))
15959 change = 1;
15960 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15961 && (0
15962#ifndef NO_ECOFF_DEBUGGING
49309057
ILT
15963 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15964 && (symbol_get_obj (sym)->ecoff_extern_size
15965 <= g_switch_value))
252b5132
RH
15966#endif
15967 /* We must defer this decision until after the whole
15968 file has been read, since there might be a .extern
15969 after the first use of this symbol. */
15970 || (before_relaxing
15971#ifndef NO_ECOFF_DEBUGGING
49309057 15972 && symbol_get_obj (sym)->ecoff_extern_size == 0
252b5132
RH
15973#endif
15974 && S_GET_VALUE (sym) == 0)
15975 || (S_GET_VALUE (sym) != 0
15976 && S_GET_VALUE (sym) <= g_switch_value)))
15977 change = 0;
15978 else
15979 {
15980 const char *segname;
15981
15982 segname = segment_name (S_GET_SEGMENT (sym));
9c2799c2 15983 gas_assert (strcmp (segname, ".lit8") != 0
252b5132
RH
15984 && strcmp (segname, ".lit4") != 0);
15985 change = (strcmp (segname, ".sdata") != 0
fba2b7f9
GK
15986 && strcmp (segname, ".sbss") != 0
15987 && strncmp (segname, ".sdata.", 7) != 0
d4dc2f22
TS
15988 && strncmp (segname, ".sbss.", 6) != 0
15989 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
fba2b7f9 15990 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
252b5132
RH
15991 }
15992 return change;
15993 }
15994 else
c9914766 15995 /* We are not optimizing for the $gp register. */
252b5132
RH
15996 return 1;
15997}
15998
5919d012
RS
15999
16000/* Return true if the given symbol should be considered local for SVR4 PIC. */
16001
16002static bfd_boolean
17a2f251 16003pic_need_relax (symbolS *sym, asection *segtype)
5919d012
RS
16004{
16005 asection *symsec;
5919d012
RS
16006
16007 /* Handle the case of a symbol equated to another symbol. */
16008 while (symbol_equated_reloc_p (sym))
16009 {
16010 symbolS *n;
16011
5f0fe04b 16012 /* It's possible to get a loop here in a badly written program. */
5919d012
RS
16013 n = symbol_get_value_expression (sym)->X_add_symbol;
16014 if (n == sym)
16015 break;
16016 sym = n;
16017 }
16018
df1f3cda
DD
16019 if (symbol_section_p (sym))
16020 return TRUE;
16021
5919d012
RS
16022 symsec = S_GET_SEGMENT (sym);
16023
5919d012 16024 /* This must duplicate the test in adjust_reloc_syms. */
45dfa85a
AM
16025 return (!bfd_is_und_section (symsec)
16026 && !bfd_is_abs_section (symsec)
5f0fe04b
TS
16027 && !bfd_is_com_section (symsec)
16028 && !s_is_linkonce (sym, segtype)
5919d012 16029 /* A global or weak symbol is treated as external. */
f3ded42a 16030 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
5919d012
RS
16031}
16032
16033
252b5132
RH
16034/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16035 extended opcode. SEC is the section the frag is in. */
16036
16037static int
17a2f251 16038mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
252b5132
RH
16039{
16040 int type;
3ccad066 16041 const struct mips_int_operand *operand;
252b5132 16042 offsetT val;
252b5132 16043 segT symsec;
98aa84af 16044 fragS *sym_frag;
252b5132
RH
16045
16046 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16047 return 0;
16048 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16049 return 1;
16050
16051 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
3ccad066 16052 operand = mips16_immed_operand (type, FALSE);
252b5132 16053
98aa84af 16054 sym_frag = symbol_get_frag (fragp->fr_symbol);
ac62c346 16055 val = S_GET_VALUE (fragp->fr_symbol);
98aa84af 16056 symsec = S_GET_SEGMENT (fragp->fr_symbol);
252b5132 16057
3ccad066 16058 if (operand->root.type == OP_PCREL)
252b5132 16059 {
3ccad066 16060 const struct mips_pcrel_operand *pcrel_op;
252b5132 16061 addressT addr;
3ccad066 16062 offsetT maxtiny;
252b5132
RH
16063
16064 /* We won't have the section when we are called from
16065 mips_relax_frag. However, we will always have been called
16066 from md_estimate_size_before_relax first. If this is a
16067 branch to a different section, we mark it as such. If SEC is
16068 NULL, and the frag is not marked, then it must be a branch to
16069 the same section. */
3ccad066 16070 pcrel_op = (const struct mips_pcrel_operand *) operand;
252b5132
RH
16071 if (sec == NULL)
16072 {
16073 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16074 return 1;
16075 }
16076 else
16077 {
98aa84af 16078 /* Must have been called from md_estimate_size_before_relax. */
252b5132
RH
16079 if (symsec != sec)
16080 {
16081 fragp->fr_subtype =
16082 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16083
16084 /* FIXME: We should support this, and let the linker
16085 catch branches and loads that are out of range. */
16086 as_bad_where (fragp->fr_file, fragp->fr_line,
16087 _("unsupported PC relative reference to different section"));
16088
16089 return 1;
16090 }
98aa84af
AM
16091 if (fragp != sym_frag && sym_frag->fr_address == 0)
16092 /* Assume non-extended on the first relaxation pass.
16093 The address we have calculated will be bogus if this is
16094 a forward branch to another frag, as the forward frag
16095 will have fr_address == 0. */
16096 return 0;
252b5132
RH
16097 }
16098
16099 /* In this case, we know for sure that the symbol fragment is in
98aa84af
AM
16100 the same section. If the relax_marker of the symbol fragment
16101 differs from the relax_marker of this fragment, we have not
16102 yet adjusted the symbol fragment fr_address. We want to add
252b5132
RH
16103 in STRETCH in order to get a better estimate of the address.
16104 This particularly matters because of the shift bits. */
16105 if (stretch != 0
98aa84af 16106 && sym_frag->relax_marker != fragp->relax_marker)
252b5132
RH
16107 {
16108 fragS *f;
16109
16110 /* Adjust stretch for any alignment frag. Note that if have
16111 been expanding the earlier code, the symbol may be
16112 defined in what appears to be an earlier frag. FIXME:
16113 This doesn't handle the fr_subtype field, which specifies
16114 a maximum number of bytes to skip when doing an
16115 alignment. */
98aa84af 16116 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
252b5132
RH
16117 {
16118 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16119 {
16120 if (stretch < 0)
16121 stretch = - ((- stretch)
16122 & ~ ((1 << (int) f->fr_offset) - 1));
16123 else
16124 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16125 if (stretch == 0)
16126 break;
16127 }
16128 }
16129 if (f != NULL)
16130 val += stretch;
16131 }
16132
16133 addr = fragp->fr_address + fragp->fr_fix;
16134
16135 /* The base address rules are complicated. The base address of
16136 a branch is the following instruction. The base address of a
16137 PC relative load or add is the instruction itself, but if it
16138 is in a delay slot (in which case it can not be extended) use
16139 the address of the instruction whose delay slot it is in. */
3ccad066 16140 if (pcrel_op->include_isa_bit)
252b5132
RH
16141 {
16142 addr += 2;
16143
16144 /* If we are currently assuming that this frag should be
16145 extended, then, the current address is two bytes
bdaaa2e1 16146 higher. */
252b5132
RH
16147 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16148 addr += 2;
16149
16150 /* Ignore the low bit in the target, since it will be set
16151 for a text label. */
3ccad066 16152 val &= -2;
252b5132
RH
16153 }
16154 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16155 addr -= 4;
16156 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16157 addr -= 2;
16158
3ccad066 16159 val -= addr & -(1 << pcrel_op->align_log2);
252b5132
RH
16160
16161 /* If any of the shifted bits are set, we must use an extended
16162 opcode. If the address depends on the size of this
16163 instruction, this can lead to a loop, so we arrange to always
16164 use an extended opcode. We only check this when we are in
16165 the main relaxation loop, when SEC is NULL. */
3ccad066 16166 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
252b5132
RH
16167 {
16168 fragp->fr_subtype =
16169 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16170 return 1;
16171 }
16172
16173 /* If we are about to mark a frag as extended because the value
3ccad066
RS
16174 is precisely the next value above maxtiny, then there is a
16175 chance of an infinite loop as in the following code:
252b5132
RH
16176 la $4,foo
16177 .skip 1020
16178 .align 2
16179 foo:
16180 In this case when the la is extended, foo is 0x3fc bytes
16181 away, so the la can be shrunk, but then foo is 0x400 away, so
16182 the la must be extended. To avoid this loop, we mark the
16183 frag as extended if it was small, and is about to become
3ccad066
RS
16184 extended with the next value above maxtiny. */
16185 maxtiny = mips_int_operand_max (operand);
16186 if (val == maxtiny + (1 << operand->shift)
252b5132
RH
16187 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16188 && sec == NULL)
16189 {
16190 fragp->fr_subtype =
16191 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16192 return 1;
16193 }
16194 }
16195 else if (symsec != absolute_section && sec != NULL)
16196 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16197
3ccad066 16198 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
252b5132
RH
16199}
16200
4a6a3df4
AO
16201/* Compute the length of a branch sequence, and adjust the
16202 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16203 worst-case length is computed, with UPDATE being used to indicate
16204 whether an unconditional (-1), branch-likely (+1) or regular (0)
16205 branch is to be computed. */
16206static int
17a2f251 16207relaxed_branch_length (fragS *fragp, asection *sec, int update)
4a6a3df4 16208{
b34976b6 16209 bfd_boolean toofar;
4a6a3df4
AO
16210 int length;
16211
16212 if (fragp
16213 && S_IS_DEFINED (fragp->fr_symbol)
16214 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16215 {
16216 addressT addr;
16217 offsetT val;
16218
16219 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16220
16221 addr = fragp->fr_address + fragp->fr_fix + 4;
16222
16223 val -= addr;
16224
16225 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16226 }
16227 else if (fragp)
16228 /* If the symbol is not defined or it's in a different segment,
16229 assume the user knows what's going on and emit a short
16230 branch. */
b34976b6 16231 toofar = FALSE;
4a6a3df4 16232 else
b34976b6 16233 toofar = TRUE;
4a6a3df4
AO
16234
16235 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16236 fragp->fr_subtype
66b3e8da
MR
16237 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16238 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
4a6a3df4
AO
16239 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16240 RELAX_BRANCH_LINK (fragp->fr_subtype),
16241 toofar);
16242
16243 length = 4;
16244 if (toofar)
16245 {
16246 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16247 length += 8;
16248
16249 if (mips_pic != NO_PIC)
16250 {
16251 /* Additional space for PIC loading of target address. */
16252 length += 8;
16253 if (mips_opts.isa == ISA_MIPS1)
16254 /* Additional space for $at-stabilizing nop. */
16255 length += 4;
16256 }
16257
16258 /* If branch is conditional. */
16259 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16260 length += 8;
16261 }
b34976b6 16262
4a6a3df4
AO
16263 return length;
16264}
16265
df58fc94
RS
16266/* Compute the length of a branch sequence, and adjust the
16267 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16268 worst-case length is computed, with UPDATE being used to indicate
16269 whether an unconditional (-1), or regular (0) branch is to be
16270 computed. */
16271
16272static int
16273relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16274{
16275 bfd_boolean toofar;
16276 int length;
16277
16278 if (fragp
16279 && S_IS_DEFINED (fragp->fr_symbol)
16280 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16281 {
16282 addressT addr;
16283 offsetT val;
16284
16285 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16286 /* Ignore the low bit in the target, since it will be set
16287 for a text label. */
16288 if ((val & 1) != 0)
16289 --val;
16290
16291 addr = fragp->fr_address + fragp->fr_fix + 4;
16292
16293 val -= addr;
16294
16295 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16296 }
16297 else if (fragp)
16298 /* If the symbol is not defined or it's in a different segment,
16299 assume the user knows what's going on and emit a short
16300 branch. */
16301 toofar = FALSE;
16302 else
16303 toofar = TRUE;
16304
16305 if (fragp && update
16306 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16307 fragp->fr_subtype = (toofar
16308 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16309 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16310
16311 length = 4;
16312 if (toofar)
16313 {
16314 bfd_boolean compact_known = fragp != NULL;
16315 bfd_boolean compact = FALSE;
16316 bfd_boolean uncond;
16317
16318 if (compact_known)
16319 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16320 if (fragp)
16321 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16322 else
16323 uncond = update < 0;
16324
16325 /* If label is out of range, we turn branch <br>:
16326
16327 <br> label # 4 bytes
16328 0:
16329
16330 into:
16331
16332 j label # 4 bytes
16333 nop # 2 bytes if compact && !PIC
16334 0:
16335 */
16336 if (mips_pic == NO_PIC && (!compact_known || compact))
16337 length += 2;
16338
16339 /* If assembling PIC code, we further turn:
16340
16341 j label # 4 bytes
16342
16343 into:
16344
16345 lw/ld at, %got(label)(gp) # 4 bytes
16346 d/addiu at, %lo(label) # 4 bytes
16347 jr/c at # 2 bytes
16348 */
16349 if (mips_pic != NO_PIC)
16350 length += 6;
16351
16352 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16353
16354 <brneg> 0f # 4 bytes
16355 nop # 2 bytes if !compact
16356 */
16357 if (!uncond)
16358 length += (compact_known && compact) ? 4 : 6;
16359 }
16360
16361 return length;
16362}
16363
16364/* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16365 bit accordingly. */
16366
16367static int
16368relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16369{
16370 bfd_boolean toofar;
16371
df58fc94
RS
16372 if (fragp
16373 && S_IS_DEFINED (fragp->fr_symbol)
16374 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16375 {
16376 addressT addr;
16377 offsetT val;
16378 int type;
16379
16380 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16381 /* Ignore the low bit in the target, since it will be set
16382 for a text label. */
16383 if ((val & 1) != 0)
16384 --val;
16385
16386 /* Assume this is a 2-byte branch. */
16387 addr = fragp->fr_address + fragp->fr_fix + 2;
16388
16389 /* We try to avoid the infinite loop by not adding 2 more bytes for
16390 long branches. */
16391
16392 val -= addr;
16393
16394 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16395 if (type == 'D')
16396 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16397 else if (type == 'E')
16398 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16399 else
16400 abort ();
16401 }
16402 else
16403 /* If the symbol is not defined or it's in a different segment,
16404 we emit a normal 32-bit branch. */
16405 toofar = TRUE;
16406
16407 if (fragp && update
16408 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16409 fragp->fr_subtype
16410 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16411 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16412
16413 if (toofar)
16414 return 4;
16415
16416 return 2;
16417}
16418
252b5132
RH
16419/* Estimate the size of a frag before relaxing. Unless this is the
16420 mips16, we are not really relaxing here, and the final size is
16421 encoded in the subtype information. For the mips16, we have to
16422 decide whether we are using an extended opcode or not. */
16423
252b5132 16424int
17a2f251 16425md_estimate_size_before_relax (fragS *fragp, asection *segtype)
252b5132 16426{
5919d012 16427 int change;
252b5132 16428
4a6a3df4
AO
16429 if (RELAX_BRANCH_P (fragp->fr_subtype))
16430 {
16431
b34976b6
AM
16432 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16433
4a6a3df4
AO
16434 return fragp->fr_var;
16435 }
16436
252b5132 16437 if (RELAX_MIPS16_P (fragp->fr_subtype))
177b4a6a
AO
16438 /* We don't want to modify the EXTENDED bit here; it might get us
16439 into infinite loops. We change it only in mips_relax_frag(). */
16440 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
252b5132 16441
df58fc94
RS
16442 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16443 {
16444 int length = 4;
16445
16446 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16447 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16448 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16449 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16450 fragp->fr_var = length;
16451
16452 return length;
16453 }
16454
252b5132 16455 if (mips_pic == NO_PIC)
5919d012 16456 change = nopic_need_relax (fragp->fr_symbol, 0);
252b5132 16457 else if (mips_pic == SVR4_PIC)
5919d012 16458 change = pic_need_relax (fragp->fr_symbol, segtype);
0a44bf69
RS
16459 else if (mips_pic == VXWORKS_PIC)
16460 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16461 change = 0;
252b5132
RH
16462 else
16463 abort ();
16464
16465 if (change)
16466 {
4d7206a2 16467 fragp->fr_subtype |= RELAX_USE_SECOND;
4d7206a2 16468 return -RELAX_FIRST (fragp->fr_subtype);
252b5132 16469 }
4d7206a2
RS
16470 else
16471 return -RELAX_SECOND (fragp->fr_subtype);
252b5132
RH
16472}
16473
16474/* This is called to see whether a reloc against a defined symbol
de7e6852 16475 should be converted into a reloc against a section. */
252b5132
RH
16476
16477int
17a2f251 16478mips_fix_adjustable (fixS *fixp)
252b5132 16479{
252b5132
RH
16480 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16481 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16482 return 0;
a161fe53 16483
252b5132
RH
16484 if (fixp->fx_addsy == NULL)
16485 return 1;
a161fe53 16486
de7e6852
RS
16487 /* If symbol SYM is in a mergeable section, relocations of the form
16488 SYM + 0 can usually be made section-relative. The mergeable data
16489 is then identified by the section offset rather than by the symbol.
16490
16491 However, if we're generating REL LO16 relocations, the offset is split
16492 between the LO16 and parterning high part relocation. The linker will
16493 need to recalculate the complete offset in order to correctly identify
16494 the merge data.
16495
16496 The linker has traditionally not looked for the parterning high part
16497 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16498 placed anywhere. Rather than break backwards compatibility by changing
16499 this, it seems better not to force the issue, and instead keep the
16500 original symbol. This will work with either linker behavior. */
738e5348 16501 if ((lo16_reloc_p (fixp->fx_r_type)
704803a9 16502 || reloc_needs_lo_p (fixp->fx_r_type))
de7e6852
RS
16503 && HAVE_IN_PLACE_ADDENDS
16504 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16505 return 0;
16506
ce70d90a 16507 /* There is no place to store an in-place offset for JALR relocations.
2de39019
CM
16508 Likewise an in-range offset of limited PC-relative relocations may
16509 overflow the in-place relocatable field if recalculated against the
16510 start address of the symbol's containing section. */
ce70d90a 16511 if (HAVE_IN_PLACE_ADDENDS
2de39019
CM
16512 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16513 || jalr_reloc_p (fixp->fx_r_type)))
1180b5a4
RS
16514 return 0;
16515
b314ec0e
RS
16516 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16517 to a floating-point stub. The same is true for non-R_MIPS16_26
16518 relocations against MIPS16 functions; in this case, the stub becomes
16519 the function's canonical address.
16520
16521 Floating-point stubs are stored in unique .mips16.call.* or
16522 .mips16.fn.* sections. If a stub T for function F is in section S,
16523 the first relocation in section S must be against F; this is how the
16524 linker determines the target function. All relocations that might
16525 resolve to T must also be against F. We therefore have the following
16526 restrictions, which are given in an intentionally-redundant way:
16527
16528 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16529 symbols.
16530
16531 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16532 if that stub might be used.
16533
16534 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16535 symbols.
16536
16537 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16538 that stub might be used.
16539
16540 There is a further restriction:
16541
df58fc94
RS
16542 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16543 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16544 targets with in-place addends; the relocation field cannot
b314ec0e
RS
16545 encode the low bit.
16546
df58fc94
RS
16547 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16548 against a MIPS16 symbol. We deal with (5) by by not reducing any
16549 such relocations on REL targets.
b314ec0e
RS
16550
16551 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16552 relocation against some symbol R, no relocation against R may be
16553 reduced. (Note that this deals with (2) as well as (1) because
16554 relocations against global symbols will never be reduced on ELF
16555 targets.) This approach is a little simpler than trying to detect
16556 stub sections, and gives the "all or nothing" per-symbol consistency
16557 that we have for MIPS16 symbols. */
f3ded42a 16558 if (fixp->fx_subsy == NULL
30c09090 16559 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
df58fc94
RS
16560 || *symbol_get_tc (fixp->fx_addsy)
16561 || (HAVE_IN_PLACE_ADDENDS
16562 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16563 && jmp_reloc_p (fixp->fx_r_type))))
252b5132 16564 return 0;
a161fe53 16565
252b5132
RH
16566 return 1;
16567}
16568
16569/* Translate internal representation of relocation info to BFD target
16570 format. */
16571
16572arelent **
17a2f251 16573tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH
16574{
16575 static arelent *retval[4];
16576 arelent *reloc;
16577 bfd_reloc_code_real_type code;
16578
4b0cff4e
TS
16579 memset (retval, 0, sizeof(retval));
16580 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
49309057
ILT
16581 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16582 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH
16583 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16584
bad36eac
DJ
16585 if (fixp->fx_pcrel)
16586 {
df58fc94
RS
16587 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16588 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16589 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
b47468a6
CM
16590 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16591 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
bad36eac
DJ
16592
16593 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16594 Relocations want only the symbol offset. */
16595 reloc->addend = fixp->fx_addnumber + reloc->address;
bad36eac
DJ
16596 }
16597 else
16598 reloc->addend = fixp->fx_addnumber;
252b5132 16599
438c16b8
TS
16600 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16601 entry to be used in the relocation's section offset. */
16602 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
252b5132
RH
16603 {
16604 reloc->address = reloc->addend;
16605 reloc->addend = 0;
16606 }
16607
252b5132 16608 code = fixp->fx_r_type;
252b5132 16609
bad36eac 16610 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH
16611 if (reloc->howto == NULL)
16612 {
16613 as_bad_where (fixp->fx_file, fixp->fx_line,
16614 _("Can not represent %s relocation in this object file format"),
16615 bfd_get_reloc_code_name (code));
16616 retval[0] = NULL;
16617 }
16618
16619 return retval;
16620}
16621
16622/* Relax a machine dependent frag. This returns the amount by which
16623 the current size of the frag should change. */
16624
16625int
17a2f251 16626mips_relax_frag (asection *sec, fragS *fragp, long stretch)
252b5132 16627{
4a6a3df4
AO
16628 if (RELAX_BRANCH_P (fragp->fr_subtype))
16629 {
16630 offsetT old_var = fragp->fr_var;
b34976b6
AM
16631
16632 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
4a6a3df4
AO
16633
16634 return fragp->fr_var - old_var;
16635 }
16636
df58fc94
RS
16637 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16638 {
16639 offsetT old_var = fragp->fr_var;
16640 offsetT new_var = 4;
16641
16642 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16643 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16644 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16645 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16646 fragp->fr_var = new_var;
16647
16648 return new_var - old_var;
16649 }
16650
252b5132
RH
16651 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16652 return 0;
16653
c4e7957c 16654 if (mips16_extended_frag (fragp, NULL, stretch))
252b5132
RH
16655 {
16656 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16657 return 0;
16658 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16659 return 2;
16660 }
16661 else
16662 {
16663 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16664 return 0;
16665 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16666 return -2;
16667 }
16668
16669 return 0;
16670}
16671
16672/* Convert a machine dependent frag. */
16673
16674void
17a2f251 16675md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
252b5132 16676{
4a6a3df4
AO
16677 if (RELAX_BRANCH_P (fragp->fr_subtype))
16678 {
4d68580a 16679 char *buf;
4a6a3df4
AO
16680 unsigned long insn;
16681 expressionS exp;
16682 fixS *fixp;
b34976b6 16683
4d68580a
RS
16684 buf = fragp->fr_literal + fragp->fr_fix;
16685 insn = read_insn (buf);
b34976b6 16686
4a6a3df4
AO
16687 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16688 {
16689 /* We generate a fixup instead of applying it right now
16690 because, if there are linker relaxations, we're going to
16691 need the relocations. */
16692 exp.X_op = O_symbol;
16693 exp.X_add_symbol = fragp->fr_symbol;
16694 exp.X_add_number = fragp->fr_offset;
16695
4d68580a
RS
16696 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16697 BFD_RELOC_16_PCREL_S2);
4a6a3df4
AO
16698 fixp->fx_file = fragp->fr_file;
16699 fixp->fx_line = fragp->fr_line;
b34976b6 16700
4d68580a 16701 buf = write_insn (buf, insn);
4a6a3df4
AO
16702 }
16703 else
16704 {
16705 int i;
16706
16707 as_warn_where (fragp->fr_file, fragp->fr_line,
5c4f07ba 16708 _("Relaxed out-of-range branch into a jump"));
4a6a3df4
AO
16709
16710 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16711 goto uncond;
16712
16713 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16714 {
16715 /* Reverse the branch. */
16716 switch ((insn >> 28) & 0xf)
16717 {
16718 case 4:
3bf0dbfb
MR
16719 /* bc[0-3][tf]l? instructions can have the condition
16720 reversed by tweaking a single TF bit, and their
16721 opcodes all have 0x4???????. */
16722 gas_assert ((insn & 0xf3e00000) == 0x41000000);
4a6a3df4
AO
16723 insn ^= 0x00010000;
16724 break;
16725
16726 case 0:
16727 /* bltz 0x04000000 bgez 0x04010000
54f4ddb3 16728 bltzal 0x04100000 bgezal 0x04110000 */
9c2799c2 16729 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
4a6a3df4
AO
16730 insn ^= 0x00010000;
16731 break;
b34976b6 16732
4a6a3df4
AO
16733 case 1:
16734 /* beq 0x10000000 bne 0x14000000
54f4ddb3 16735 blez 0x18000000 bgtz 0x1c000000 */
4a6a3df4
AO
16736 insn ^= 0x04000000;
16737 break;
16738
16739 default:
16740 abort ();
16741 }
16742 }
16743
16744 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16745 {
16746 /* Clear the and-link bit. */
9c2799c2 16747 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
4a6a3df4 16748
54f4ddb3
TS
16749 /* bltzal 0x04100000 bgezal 0x04110000
16750 bltzall 0x04120000 bgezall 0x04130000 */
4a6a3df4
AO
16751 insn &= ~0x00100000;
16752 }
16753
16754 /* Branch over the branch (if the branch was likely) or the
16755 full jump (not likely case). Compute the offset from the
16756 current instruction to branch to. */
16757 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16758 i = 16;
16759 else
16760 {
16761 /* How many bytes in instructions we've already emitted? */
4d68580a 16762 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
16763 /* How many bytes in instructions from here to the end? */
16764 i = fragp->fr_var - i;
16765 }
16766 /* Convert to instruction count. */
16767 i >>= 2;
16768 /* Branch counts from the next instruction. */
b34976b6 16769 i--;
4a6a3df4
AO
16770 insn |= i;
16771 /* Branch over the jump. */
4d68580a 16772 buf = write_insn (buf, insn);
4a6a3df4 16773
54f4ddb3 16774 /* nop */
4d68580a 16775 buf = write_insn (buf, 0);
4a6a3df4
AO
16776
16777 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16778 {
16779 /* beql $0, $0, 2f */
16780 insn = 0x50000000;
16781 /* Compute the PC offset from the current instruction to
16782 the end of the variable frag. */
16783 /* How many bytes in instructions we've already emitted? */
4d68580a 16784 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
16785 /* How many bytes in instructions from here to the end? */
16786 i = fragp->fr_var - i;
16787 /* Convert to instruction count. */
16788 i >>= 2;
16789 /* Don't decrement i, because we want to branch over the
16790 delay slot. */
4a6a3df4 16791 insn |= i;
4a6a3df4 16792
4d68580a
RS
16793 buf = write_insn (buf, insn);
16794 buf = write_insn (buf, 0);
4a6a3df4
AO
16795 }
16796
16797 uncond:
16798 if (mips_pic == NO_PIC)
16799 {
16800 /* j or jal. */
16801 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16802 ? 0x0c000000 : 0x08000000);
16803 exp.X_op = O_symbol;
16804 exp.X_add_symbol = fragp->fr_symbol;
16805 exp.X_add_number = fragp->fr_offset;
16806
4d68580a
RS
16807 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16808 FALSE, BFD_RELOC_MIPS_JMP);
4a6a3df4
AO
16809 fixp->fx_file = fragp->fr_file;
16810 fixp->fx_line = fragp->fr_line;
16811
4d68580a 16812 buf = write_insn (buf, insn);
4a6a3df4
AO
16813 }
16814 else
16815 {
66b3e8da
MR
16816 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16817
4a6a3df4 16818 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
66b3e8da
MR
16819 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16820 insn |= at << OP_SH_RT;
4a6a3df4
AO
16821 exp.X_op = O_symbol;
16822 exp.X_add_symbol = fragp->fr_symbol;
16823 exp.X_add_number = fragp->fr_offset;
16824
16825 if (fragp->fr_offset)
16826 {
16827 exp.X_add_symbol = make_expr_symbol (&exp);
16828 exp.X_add_number = 0;
16829 }
16830
4d68580a
RS
16831 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16832 FALSE, BFD_RELOC_MIPS_GOT16);
4a6a3df4
AO
16833 fixp->fx_file = fragp->fr_file;
16834 fixp->fx_line = fragp->fr_line;
16835
4d68580a 16836 buf = write_insn (buf, insn);
b34976b6 16837
4a6a3df4 16838 if (mips_opts.isa == ISA_MIPS1)
4d68580a
RS
16839 /* nop */
16840 buf = write_insn (buf, 0);
4a6a3df4
AO
16841
16842 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
66b3e8da
MR
16843 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16844 insn |= at << OP_SH_RS | at << OP_SH_RT;
4a6a3df4 16845
4d68580a
RS
16846 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16847 FALSE, BFD_RELOC_LO16);
4a6a3df4
AO
16848 fixp->fx_file = fragp->fr_file;
16849 fixp->fx_line = fragp->fr_line;
b34976b6 16850
4d68580a 16851 buf = write_insn (buf, insn);
4a6a3df4
AO
16852
16853 /* j(al)r $at. */
16854 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
66b3e8da 16855 insn = 0x0000f809;
4a6a3df4 16856 else
66b3e8da
MR
16857 insn = 0x00000008;
16858 insn |= at << OP_SH_RS;
4a6a3df4 16859
4d68580a 16860 buf = write_insn (buf, insn);
4a6a3df4
AO
16861 }
16862 }
16863
4a6a3df4 16864 fragp->fr_fix += fragp->fr_var;
4d68580a 16865 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
4a6a3df4
AO
16866 return;
16867 }
16868
df58fc94
RS
16869 /* Relax microMIPS branches. */
16870 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16871 {
4d68580a 16872 char *buf = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
16873 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16874 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16875 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
2309ddf2 16876 bfd_boolean short_ds;
df58fc94
RS
16877 unsigned long insn;
16878 expressionS exp;
16879 fixS *fixp;
16880
16881 exp.X_op = O_symbol;
16882 exp.X_add_symbol = fragp->fr_symbol;
16883 exp.X_add_number = fragp->fr_offset;
16884
16885 fragp->fr_fix += fragp->fr_var;
16886
16887 /* Handle 16-bit branches that fit or are forced to fit. */
16888 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16889 {
16890 /* We generate a fixup instead of applying it right now,
16891 because if there is linker relaxation, we're going to
16892 need the relocations. */
16893 if (type == 'D')
4d68580a 16894 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
16895 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16896 else if (type == 'E')
4d68580a 16897 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
16898 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16899 else
16900 abort ();
16901
16902 fixp->fx_file = fragp->fr_file;
16903 fixp->fx_line = fragp->fr_line;
16904
16905 /* These relocations can have an addend that won't fit in
16906 2 octets. */
16907 fixp->fx_no_overflow = 1;
16908
16909 return;
16910 }
16911
2309ddf2 16912 /* Handle 32-bit branches that fit or are forced to fit. */
df58fc94
RS
16913 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16914 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16915 {
16916 /* We generate a fixup instead of applying it right now,
16917 because if there is linker relaxation, we're going to
16918 need the relocations. */
4d68580a
RS
16919 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16920 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
16921 fixp->fx_file = fragp->fr_file;
16922 fixp->fx_line = fragp->fr_line;
16923
16924 if (type == 0)
16925 return;
16926 }
16927
16928 /* Relax 16-bit branches to 32-bit branches. */
16929 if (type != 0)
16930 {
4d68580a 16931 insn = read_compressed_insn (buf, 2);
df58fc94
RS
16932
16933 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16934 insn = 0x94000000; /* beq */
16935 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16936 {
16937 unsigned long regno;
16938
16939 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16940 regno = micromips_to_32_reg_d_map [regno];
16941 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16942 insn |= regno << MICROMIPSOP_SH_RS;
16943 }
16944 else
16945 abort ();
16946
16947 /* Nothing else to do, just write it out. */
16948 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16949 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16950 {
4d68580a
RS
16951 buf = write_compressed_insn (buf, insn, 4);
16952 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
16953 return;
16954 }
16955 }
16956 else
4d68580a 16957 insn = read_compressed_insn (buf, 4);
df58fc94
RS
16958
16959 /* Relax 32-bit branches to a sequence of instructions. */
16960 as_warn_where (fragp->fr_file, fragp->fr_line,
16961 _("Relaxed out-of-range branch into a jump"));
16962
2309ddf2
MR
16963 /* Set the short-delay-slot bit. */
16964 short_ds = al && (insn & 0x02000000) != 0;
df58fc94
RS
16965
16966 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16967 {
16968 symbolS *l;
16969
16970 /* Reverse the branch. */
16971 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16972 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16973 insn ^= 0x20000000;
16974 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16975 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16976 || (insn & 0xffe00000) == 0x40800000 /* blez */
16977 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16978 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16979 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16980 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16981 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16982 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16983 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16984 insn ^= 0x00400000;
16985 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16986 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16987 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16988 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16989 insn ^= 0x00200000;
16990 else
16991 abort ();
16992
16993 if (al)
16994 {
16995 /* Clear the and-link and short-delay-slot bits. */
16996 gas_assert ((insn & 0xfda00000) == 0x40200000);
16997
16998 /* bltzal 0x40200000 bgezal 0x40600000 */
16999 /* bltzals 0x42200000 bgezals 0x42600000 */
17000 insn &= ~0x02200000;
17001 }
17002
17003 /* Make a label at the end for use with the branch. */
17004 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17005 micromips_label_inc ();
f3ded42a 17006 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
df58fc94
RS
17007
17008 /* Refer to it. */
4d68580a
RS
17009 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
17010 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
17011 fixp->fx_file = fragp->fr_file;
17012 fixp->fx_line = fragp->fr_line;
17013
17014 /* Branch over the jump. */
4d68580a 17015 buf = write_compressed_insn (buf, insn, 4);
df58fc94 17016 if (!compact)
4d68580a
RS
17017 /* nop */
17018 buf = write_compressed_insn (buf, 0x0c00, 2);
df58fc94
RS
17019 }
17020
17021 if (mips_pic == NO_PIC)
17022 {
2309ddf2
MR
17023 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17024
df58fc94
RS
17025 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17026 insn = al ? jal : 0xd4000000;
17027
4d68580a
RS
17028 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17029 BFD_RELOC_MICROMIPS_JMP);
df58fc94
RS
17030 fixp->fx_file = fragp->fr_file;
17031 fixp->fx_line = fragp->fr_line;
17032
4d68580a 17033 buf = write_compressed_insn (buf, insn, 4);
df58fc94 17034 if (compact)
4d68580a
RS
17035 /* nop */
17036 buf = write_compressed_insn (buf, 0x0c00, 2);
df58fc94
RS
17037 }
17038 else
17039 {
17040 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
2309ddf2
MR
17041 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17042 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
df58fc94
RS
17043
17044 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17045 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17046 insn |= at << MICROMIPSOP_SH_RT;
17047
17048 if (exp.X_add_number)
17049 {
17050 exp.X_add_symbol = make_expr_symbol (&exp);
17051 exp.X_add_number = 0;
17052 }
17053
4d68580a
RS
17054 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17055 BFD_RELOC_MICROMIPS_GOT16);
df58fc94
RS
17056 fixp->fx_file = fragp->fr_file;
17057 fixp->fx_line = fragp->fr_line;
17058
4d68580a 17059 buf = write_compressed_insn (buf, insn, 4);
df58fc94
RS
17060
17061 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17062 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17063 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17064
4d68580a
RS
17065 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17066 BFD_RELOC_MICROMIPS_LO16);
df58fc94
RS
17067 fixp->fx_file = fragp->fr_file;
17068 fixp->fx_line = fragp->fr_line;
17069
4d68580a 17070 buf = write_compressed_insn (buf, insn, 4);
df58fc94
RS
17071
17072 /* jr/jrc/jalr/jalrs $at */
17073 insn = al ? jalr : jr;
17074 insn |= at << MICROMIPSOP_SH_MJ;
17075
4d68580a 17076 buf = write_compressed_insn (buf, insn, 2);
df58fc94
RS
17077 }
17078
4d68580a 17079 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
17080 return;
17081 }
17082
252b5132
RH
17083 if (RELAX_MIPS16_P (fragp->fr_subtype))
17084 {
17085 int type;
3ccad066 17086 const struct mips_int_operand *operand;
252b5132 17087 offsetT val;
5c04167a
RS
17088 char *buf;
17089 unsigned int user_length, length;
252b5132 17090 unsigned long insn;
5c04167a 17091 bfd_boolean ext;
252b5132
RH
17092
17093 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
3ccad066 17094 operand = mips16_immed_operand (type, FALSE);
252b5132 17095
5c04167a 17096 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
5f5f22c0 17097 val = resolve_symbol_value (fragp->fr_symbol);
3ccad066 17098 if (operand->root.type == OP_PCREL)
252b5132 17099 {
3ccad066 17100 const struct mips_pcrel_operand *pcrel_op;
252b5132
RH
17101 addressT addr;
17102
3ccad066 17103 pcrel_op = (const struct mips_pcrel_operand *) operand;
252b5132
RH
17104 addr = fragp->fr_address + fragp->fr_fix;
17105
17106 /* The rules for the base address of a PC relative reloc are
17107 complicated; see mips16_extended_frag. */
3ccad066 17108 if (pcrel_op->include_isa_bit)
252b5132
RH
17109 {
17110 addr += 2;
17111 if (ext)
17112 addr += 2;
17113 /* Ignore the low bit in the target, since it will be
17114 set for a text label. */
3ccad066 17115 val &= -2;
252b5132
RH
17116 }
17117 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17118 addr -= 4;
17119 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17120 addr -= 2;
17121
3ccad066 17122 addr &= -(1 << pcrel_op->align_log2);
252b5132
RH
17123 val -= addr;
17124
17125 /* Make sure the section winds up with the alignment we have
17126 assumed. */
3ccad066
RS
17127 if (operand->shift > 0)
17128 record_alignment (asec, operand->shift);
252b5132
RH
17129 }
17130
17131 if (ext
17132 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17133 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17134 as_warn_where (fragp->fr_file, fragp->fr_line,
17135 _("extended instruction in delay slot"));
17136
5c04167a 17137 buf = fragp->fr_literal + fragp->fr_fix;
252b5132 17138
4d68580a 17139 insn = read_compressed_insn (buf, 2);
5c04167a
RS
17140 if (ext)
17141 insn |= MIPS16_EXTEND;
252b5132 17142
5c04167a
RS
17143 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17144 user_length = 4;
17145 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17146 user_length = 2;
17147 else
17148 user_length = 0;
17149
43c0598f 17150 mips16_immed (fragp->fr_file, fragp->fr_line, type,
c150d1d2 17151 BFD_RELOC_UNUSED, val, user_length, &insn);
252b5132 17152
5c04167a
RS
17153 length = (ext ? 4 : 2);
17154 gas_assert (mips16_opcode_length (insn) == length);
17155 write_compressed_insn (buf, insn, length);
17156 fragp->fr_fix += length;
252b5132
RH
17157 }
17158 else
17159 {
df58fc94
RS
17160 relax_substateT subtype = fragp->fr_subtype;
17161 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17162 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
4d7206a2
RS
17163 int first, second;
17164 fixS *fixp;
252b5132 17165
df58fc94
RS
17166 first = RELAX_FIRST (subtype);
17167 second = RELAX_SECOND (subtype);
4d7206a2 17168 fixp = (fixS *) fragp->fr_opcode;
252b5132 17169
df58fc94
RS
17170 /* If the delay slot chosen does not match the size of the instruction,
17171 then emit a warning. */
17172 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17173 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17174 {
17175 relax_substateT s;
17176 const char *msg;
17177
17178 s = subtype & (RELAX_DELAY_SLOT_16BIT
17179 | RELAX_DELAY_SLOT_SIZE_FIRST
17180 | RELAX_DELAY_SLOT_SIZE_SECOND);
17181 msg = macro_warning (s);
17182 if (msg != NULL)
db9b2be4 17183 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94
RS
17184 subtype &= ~s;
17185 }
17186
584892a6 17187 /* Possibly emit a warning if we've chosen the longer option. */
df58fc94 17188 if (use_second == second_longer)
584892a6 17189 {
df58fc94
RS
17190 relax_substateT s;
17191 const char *msg;
17192
17193 s = (subtype
17194 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17195 msg = macro_warning (s);
17196 if (msg != NULL)
db9b2be4 17197 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94 17198 subtype &= ~s;
584892a6
RS
17199 }
17200
4d7206a2
RS
17201 /* Go through all the fixups for the first sequence. Disable them
17202 (by marking them as done) if we're going to use the second
17203 sequence instead. */
17204 while (fixp
17205 && fixp->fx_frag == fragp
17206 && fixp->fx_where < fragp->fr_fix - second)
17207 {
df58fc94 17208 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
17209 fixp->fx_done = 1;
17210 fixp = fixp->fx_next;
17211 }
252b5132 17212
4d7206a2
RS
17213 /* Go through the fixups for the second sequence. Disable them if
17214 we're going to use the first sequence, otherwise adjust their
17215 addresses to account for the relaxation. */
17216 while (fixp && fixp->fx_frag == fragp)
17217 {
df58fc94 17218 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
17219 fixp->fx_where -= first;
17220 else
17221 fixp->fx_done = 1;
17222 fixp = fixp->fx_next;
17223 }
17224
17225 /* Now modify the frag contents. */
df58fc94 17226 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
17227 {
17228 char *start;
17229
17230 start = fragp->fr_literal + fragp->fr_fix - first - second;
17231 memmove (start, start + first, second);
17232 fragp->fr_fix -= first;
17233 }
17234 else
17235 fragp->fr_fix -= second;
252b5132
RH
17236 }
17237}
17238
252b5132
RH
17239/* This function is called after the relocs have been generated.
17240 We've been storing mips16 text labels as odd. Here we convert them
17241 back to even for the convenience of the debugger. */
17242
17243void
17a2f251 17244mips_frob_file_after_relocs (void)
252b5132
RH
17245{
17246 asymbol **syms;
17247 unsigned int count, i;
17248
252b5132
RH
17249 syms = bfd_get_outsymbols (stdoutput);
17250 count = bfd_get_symcount (stdoutput);
17251 for (i = 0; i < count; i++, syms++)
df58fc94
RS
17252 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17253 && ((*syms)->value & 1) != 0)
17254 {
17255 (*syms)->value &= ~1;
17256 /* If the symbol has an odd size, it was probably computed
17257 incorrectly, so adjust that as well. */
17258 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17259 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17260 }
252b5132
RH
17261}
17262
a1facbec
MR
17263/* This function is called whenever a label is defined, including fake
17264 labels instantiated off the dot special symbol. It is used when
17265 handling branch delays; if a branch has a label, we assume we cannot
17266 move it. This also bumps the value of the symbol by 1 in compressed
17267 code. */
252b5132 17268
e1b47bd5 17269static void
a1facbec 17270mips_record_label (symbolS *sym)
252b5132 17271{
a8dbcb85 17272 segment_info_type *si = seg_info (now_seg);
252b5132
RH
17273 struct insn_label_list *l;
17274
17275 if (free_insn_labels == NULL)
17276 l = (struct insn_label_list *) xmalloc (sizeof *l);
17277 else
17278 {
17279 l = free_insn_labels;
17280 free_insn_labels = l->next;
17281 }
17282
17283 l->label = sym;
a8dbcb85
TS
17284 l->next = si->label_list;
17285 si->label_list = l;
a1facbec 17286}
07a53e5c 17287
a1facbec
MR
17288/* This function is called as tc_frob_label() whenever a label is defined
17289 and adds a DWARF-2 record we only want for true labels. */
17290
17291void
17292mips_define_label (symbolS *sym)
17293{
17294 mips_record_label (sym);
07a53e5c 17295 dwarf2_emit_label (sym);
252b5132 17296}
e1b47bd5
RS
17297
17298/* This function is called by tc_new_dot_label whenever a new dot symbol
17299 is defined. */
17300
17301void
17302mips_add_dot_label (symbolS *sym)
17303{
17304 mips_record_label (sym);
17305 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17306 mips_compressed_mark_label (sym);
17307}
252b5132 17308\f
252b5132
RH
17309/* Some special processing for a MIPS ELF file. */
17310
17311void
17a2f251 17312mips_elf_final_processing (void)
252b5132
RH
17313{
17314 /* Write out the register information. */
316f5878 17315 if (mips_abi != N64_ABI)
252b5132
RH
17316 {
17317 Elf32_RegInfo s;
17318
17319 s.ri_gprmask = mips_gprmask;
17320 s.ri_cprmask[0] = mips_cprmask[0];
17321 s.ri_cprmask[1] = mips_cprmask[1];
17322 s.ri_cprmask[2] = mips_cprmask[2];
17323 s.ri_cprmask[3] = mips_cprmask[3];
17324 /* The gp_value field is set by the MIPS ELF backend. */
17325
17326 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
17327 ((Elf32_External_RegInfo *)
17328 mips_regmask_frag));
17329 }
17330 else
17331 {
17332 Elf64_Internal_RegInfo s;
17333
17334 s.ri_gprmask = mips_gprmask;
17335 s.ri_pad = 0;
17336 s.ri_cprmask[0] = mips_cprmask[0];
17337 s.ri_cprmask[1] = mips_cprmask[1];
17338 s.ri_cprmask[2] = mips_cprmask[2];
17339 s.ri_cprmask[3] = mips_cprmask[3];
17340 /* The gp_value field is set by the MIPS ELF backend. */
17341
17342 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
17343 ((Elf64_External_RegInfo *)
17344 mips_regmask_frag));
17345 }
17346
17347 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17348 sort of BFD interface for this. */
17349 if (mips_any_noreorder)
17350 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
17351 if (mips_pic != NO_PIC)
143d77c5 17352 {
8b828383 17353 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
143d77c5
EC
17354 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17355 }
17356 if (mips_abicalls)
17357 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
252b5132 17358
b015e599
AP
17359 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17360 defined at present; this might need to change in future. */
a4672219
TS
17361 if (file_ase_mips16)
17362 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
df58fc94
RS
17363 if (file_ase_micromips)
17364 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
846ef2d0 17365 if (file_ase & ASE_MDMX)
deec1734 17366 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
1f25f5d3 17367
bdaaa2e1 17368 /* Set the MIPS ELF ABI flags. */
316f5878 17369 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
252b5132 17370 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
316f5878 17371 else if (mips_abi == O64_ABI)
252b5132 17372 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
316f5878 17373 else if (mips_abi == EABI_ABI)
252b5132 17374 {
316f5878 17375 if (!file_mips_gp32)
252b5132
RH
17376 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17377 else
17378 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17379 }
316f5878 17380 else if (mips_abi == N32_ABI)
be00bddd
TS
17381 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17382
c9914766 17383 /* Nothing to do for N64_ABI. */
252b5132
RH
17384
17385 if (mips_32bitmode)
17386 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
ad3fea08 17387
ba92f887
MR
17388 if (mips_flag_nan2008)
17389 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17390
ad3fea08
TS
17391#if 0 /* XXX FIXME */
17392 /* 32 bit code with 64 bit FP registers. */
17393 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
17394 elf_elfheader (stdoutput)->e_flags |= ???;
17395#endif
252b5132 17396}
252b5132 17397\f
beae10d5 17398typedef struct proc {
9b2f1d35
EC
17399 symbolS *func_sym;
17400 symbolS *func_end_sym;
beae10d5
KH
17401 unsigned long reg_mask;
17402 unsigned long reg_offset;
17403 unsigned long fpreg_mask;
17404 unsigned long fpreg_offset;
17405 unsigned long frame_offset;
17406 unsigned long frame_reg;
17407 unsigned long pc_reg;
17408} procS;
252b5132
RH
17409
17410static procS cur_proc;
17411static procS *cur_proc_ptr;
17412static int numprocs;
17413
df58fc94
RS
17414/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17415 as "2", and a normal nop as "0". */
17416
17417#define NOP_OPCODE_MIPS 0
17418#define NOP_OPCODE_MIPS16 1
17419#define NOP_OPCODE_MICROMIPS 2
742a56fe
RS
17420
17421char
17422mips_nop_opcode (void)
17423{
df58fc94
RS
17424 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17425 return NOP_OPCODE_MICROMIPS;
17426 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17427 return NOP_OPCODE_MIPS16;
17428 else
17429 return NOP_OPCODE_MIPS;
742a56fe
RS
17430}
17431
df58fc94
RS
17432/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17433 32-bit microMIPS NOPs here (if applicable). */
a19d8eb0 17434
0a9ef439 17435void
17a2f251 17436mips_handle_align (fragS *fragp)
a19d8eb0 17437{
df58fc94 17438 char nop_opcode;
742a56fe 17439 char *p;
c67a084a
NC
17440 int bytes, size, excess;
17441 valueT opcode;
742a56fe 17442
0a9ef439
RH
17443 if (fragp->fr_type != rs_align_code)
17444 return;
17445
742a56fe 17446 p = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
17447 nop_opcode = *p;
17448 switch (nop_opcode)
a19d8eb0 17449 {
df58fc94
RS
17450 case NOP_OPCODE_MICROMIPS:
17451 opcode = micromips_nop32_insn.insn_opcode;
17452 size = 4;
17453 break;
17454 case NOP_OPCODE_MIPS16:
c67a084a
NC
17455 opcode = mips16_nop_insn.insn_opcode;
17456 size = 2;
df58fc94
RS
17457 break;
17458 case NOP_OPCODE_MIPS:
17459 default:
c67a084a
NC
17460 opcode = nop_insn.insn_opcode;
17461 size = 4;
df58fc94 17462 break;
c67a084a 17463 }
a19d8eb0 17464
c67a084a
NC
17465 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17466 excess = bytes % size;
df58fc94
RS
17467
17468 /* Handle the leading part if we're not inserting a whole number of
17469 instructions, and make it the end of the fixed part of the frag.
17470 Try to fit in a short microMIPS NOP if applicable and possible,
17471 and use zeroes otherwise. */
17472 gas_assert (excess < 4);
17473 fragp->fr_fix += excess;
17474 switch (excess)
c67a084a 17475 {
df58fc94
RS
17476 case 3:
17477 *p++ = '\0';
17478 /* Fall through. */
17479 case 2:
833794fc 17480 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
df58fc94 17481 {
4d68580a 17482 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
df58fc94
RS
17483 break;
17484 }
17485 *p++ = '\0';
17486 /* Fall through. */
17487 case 1:
17488 *p++ = '\0';
17489 /* Fall through. */
17490 case 0:
17491 break;
a19d8eb0 17492 }
c67a084a
NC
17493
17494 md_number_to_chars (p, opcode, size);
17495 fragp->fr_var = size;
a19d8eb0
CP
17496}
17497
252b5132 17498static void
17a2f251 17499md_obj_begin (void)
252b5132
RH
17500{
17501}
17502
17503static void
17a2f251 17504md_obj_end (void)
252b5132 17505{
54f4ddb3 17506 /* Check for premature end, nesting errors, etc. */
252b5132 17507 if (cur_proc_ptr)
9a41af64 17508 as_warn (_("missing .end at end of assembly"));
252b5132
RH
17509}
17510
17511static long
17a2f251 17512get_number (void)
252b5132
RH
17513{
17514 int negative = 0;
17515 long val = 0;
17516
17517 if (*input_line_pointer == '-')
17518 {
17519 ++input_line_pointer;
17520 negative = 1;
17521 }
3882b010 17522 if (!ISDIGIT (*input_line_pointer))
956cd1d6 17523 as_bad (_("expected simple number"));
252b5132
RH
17524 if (input_line_pointer[0] == '0')
17525 {
17526 if (input_line_pointer[1] == 'x')
17527 {
17528 input_line_pointer += 2;
3882b010 17529 while (ISXDIGIT (*input_line_pointer))
252b5132
RH
17530 {
17531 val <<= 4;
17532 val |= hex_value (*input_line_pointer++);
17533 }
17534 return negative ? -val : val;
17535 }
17536 else
17537 {
17538 ++input_line_pointer;
3882b010 17539 while (ISDIGIT (*input_line_pointer))
252b5132
RH
17540 {
17541 val <<= 3;
17542 val |= *input_line_pointer++ - '0';
17543 }
17544 return negative ? -val : val;
17545 }
17546 }
3882b010 17547 if (!ISDIGIT (*input_line_pointer))
252b5132
RH
17548 {
17549 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17550 *input_line_pointer, *input_line_pointer);
956cd1d6 17551 as_warn (_("invalid number"));
252b5132
RH
17552 return -1;
17553 }
3882b010 17554 while (ISDIGIT (*input_line_pointer))
252b5132
RH
17555 {
17556 val *= 10;
17557 val += *input_line_pointer++ - '0';
17558 }
17559 return negative ? -val : val;
17560}
17561
17562/* The .file directive; just like the usual .file directive, but there
c5dd6aab
DJ
17563 is an initial number which is the ECOFF file index. In the non-ECOFF
17564 case .file implies DWARF-2. */
17565
17566static void
17a2f251 17567s_mips_file (int x ATTRIBUTE_UNUSED)
c5dd6aab 17568{
ecb4347a
DJ
17569 static int first_file_directive = 0;
17570
c5dd6aab
DJ
17571 if (ECOFF_DEBUGGING)
17572 {
17573 get_number ();
17574 s_app_file (0);
17575 }
17576 else
ecb4347a
DJ
17577 {
17578 char *filename;
17579
17580 filename = dwarf2_directive_file (0);
17581
17582 /* Versions of GCC up to 3.1 start files with a ".file"
17583 directive even for stabs output. Make sure that this
17584 ".file" is handled. Note that you need a version of GCC
17585 after 3.1 in order to support DWARF-2 on MIPS. */
17586 if (filename != NULL && ! first_file_directive)
17587 {
17588 (void) new_logical_line (filename, -1);
c04f5787 17589 s_app_file_string (filename, 0);
ecb4347a
DJ
17590 }
17591 first_file_directive = 1;
17592 }
c5dd6aab
DJ
17593}
17594
17595/* The .loc directive, implying DWARF-2. */
252b5132
RH
17596
17597static void
17a2f251 17598s_mips_loc (int x ATTRIBUTE_UNUSED)
252b5132 17599{
c5dd6aab
DJ
17600 if (!ECOFF_DEBUGGING)
17601 dwarf2_directive_loc (0);
252b5132
RH
17602}
17603
252b5132
RH
17604/* The .end directive. */
17605
17606static void
17a2f251 17607s_mips_end (int x ATTRIBUTE_UNUSED)
252b5132
RH
17608{
17609 symbolS *p;
252b5132 17610
7a621144
DJ
17611 /* Following functions need their own .frame and .cprestore directives. */
17612 mips_frame_reg_valid = 0;
17613 mips_cprestore_valid = 0;
17614
252b5132
RH
17615 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17616 {
17617 p = get_symbol ();
17618 demand_empty_rest_of_line ();
17619 }
17620 else
17621 p = NULL;
17622
14949570 17623 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
252b5132
RH
17624 as_warn (_(".end not in text section"));
17625
17626 if (!cur_proc_ptr)
17627 {
17628 as_warn (_(".end directive without a preceding .ent directive."));
17629 demand_empty_rest_of_line ();
17630 return;
17631 }
17632
17633 if (p != NULL)
17634 {
9c2799c2 17635 gas_assert (S_GET_NAME (p));
9b2f1d35 17636 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
252b5132 17637 as_warn (_(".end symbol does not match .ent symbol."));
ecb4347a
DJ
17638
17639 if (debug_type == DEBUG_STABS)
17640 stabs_generate_asm_endfunc (S_GET_NAME (p),
17641 S_GET_NAME (p));
252b5132
RH
17642 }
17643 else
17644 as_warn (_(".end directive missing or unknown symbol"));
17645
9b2f1d35
EC
17646 /* Create an expression to calculate the size of the function. */
17647 if (p && cur_proc_ptr)
17648 {
17649 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17650 expressionS *exp = xmalloc (sizeof (expressionS));
17651
17652 obj->size = exp;
17653 exp->X_op = O_subtract;
17654 exp->X_add_symbol = symbol_temp_new_now ();
17655 exp->X_op_symbol = p;
17656 exp->X_add_number = 0;
17657
17658 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17659 }
17660
ecb4347a 17661 /* Generate a .pdr section. */
f3ded42a 17662 if (!ECOFF_DEBUGGING && mips_flag_pdr)
ecb4347a
DJ
17663 {
17664 segT saved_seg = now_seg;
17665 subsegT saved_subseg = now_subseg;
ecb4347a
DJ
17666 expressionS exp;
17667 char *fragp;
252b5132 17668
252b5132 17669#ifdef md_flush_pending_output
ecb4347a 17670 md_flush_pending_output ();
252b5132
RH
17671#endif
17672
9c2799c2 17673 gas_assert (pdr_seg);
ecb4347a 17674 subseg_set (pdr_seg, 0);
252b5132 17675
ecb4347a
DJ
17676 /* Write the symbol. */
17677 exp.X_op = O_symbol;
17678 exp.X_add_symbol = p;
17679 exp.X_add_number = 0;
17680 emit_expr (&exp, 4);
252b5132 17681
ecb4347a 17682 fragp = frag_more (7 * 4);
252b5132 17683
17a2f251
TS
17684 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17685 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17686 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17687 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17688 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17689 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17690 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
252b5132 17691
ecb4347a
DJ
17692 subseg_set (saved_seg, saved_subseg);
17693 }
252b5132
RH
17694
17695 cur_proc_ptr = NULL;
17696}
17697
17698/* The .aent and .ent directives. */
17699
17700static void
17a2f251 17701s_mips_ent (int aent)
252b5132 17702{
252b5132 17703 symbolS *symbolP;
252b5132
RH
17704
17705 symbolP = get_symbol ();
17706 if (*input_line_pointer == ',')
f9419b05 17707 ++input_line_pointer;
252b5132 17708 SKIP_WHITESPACE ();
3882b010 17709 if (ISDIGIT (*input_line_pointer)
d9a62219 17710 || *input_line_pointer == '-')
874e8986 17711 get_number ();
252b5132 17712
14949570 17713 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
252b5132
RH
17714 as_warn (_(".ent or .aent not in text section."));
17715
17716 if (!aent && cur_proc_ptr)
9a41af64 17717 as_warn (_("missing .end"));
252b5132
RH
17718
17719 if (!aent)
17720 {
7a621144
DJ
17721 /* This function needs its own .frame and .cprestore directives. */
17722 mips_frame_reg_valid = 0;
17723 mips_cprestore_valid = 0;
17724
252b5132
RH
17725 cur_proc_ptr = &cur_proc;
17726 memset (cur_proc_ptr, '\0', sizeof (procS));
17727
9b2f1d35 17728 cur_proc_ptr->func_sym = symbolP;
252b5132 17729
f9419b05 17730 ++numprocs;
ecb4347a
DJ
17731
17732 if (debug_type == DEBUG_STABS)
17733 stabs_generate_asm_func (S_GET_NAME (symbolP),
17734 S_GET_NAME (symbolP));
252b5132
RH
17735 }
17736
7c0fc524
MR
17737 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17738
252b5132
RH
17739 demand_empty_rest_of_line ();
17740}
17741
17742/* The .frame directive. If the mdebug section is present (IRIX 5 native)
bdaaa2e1 17743 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
252b5132 17744 s_mips_frame is used so that we can set the PDR information correctly.
bdaaa2e1 17745 We can't use the ecoff routines because they make reference to the ecoff
252b5132
RH
17746 symbol table (in the mdebug section). */
17747
17748static void
17a2f251 17749s_mips_frame (int ignore ATTRIBUTE_UNUSED)
252b5132 17750{
f3ded42a
RS
17751 if (ECOFF_DEBUGGING)
17752 s_ignore (ignore);
17753 else
ecb4347a
DJ
17754 {
17755 long val;
252b5132 17756
ecb4347a
DJ
17757 if (cur_proc_ptr == (procS *) NULL)
17758 {
17759 as_warn (_(".frame outside of .ent"));
17760 demand_empty_rest_of_line ();
17761 return;
17762 }
252b5132 17763
ecb4347a
DJ
17764 cur_proc_ptr->frame_reg = tc_get_register (1);
17765
17766 SKIP_WHITESPACE ();
17767 if (*input_line_pointer++ != ','
17768 || get_absolute_expression_and_terminator (&val) != ',')
17769 {
17770 as_warn (_("Bad .frame directive"));
17771 --input_line_pointer;
17772 demand_empty_rest_of_line ();
17773 return;
17774 }
252b5132 17775
ecb4347a
DJ
17776 cur_proc_ptr->frame_offset = val;
17777 cur_proc_ptr->pc_reg = tc_get_register (0);
252b5132 17778
252b5132 17779 demand_empty_rest_of_line ();
252b5132 17780 }
252b5132
RH
17781}
17782
bdaaa2e1
KH
17783/* The .fmask and .mask directives. If the mdebug section is present
17784 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
252b5132 17785 embedded targets, s_mips_mask is used so that we can set the PDR
bdaaa2e1 17786 information correctly. We can't use the ecoff routines because they
252b5132
RH
17787 make reference to the ecoff symbol table (in the mdebug section). */
17788
17789static void
17a2f251 17790s_mips_mask (int reg_type)
252b5132 17791{
f3ded42a
RS
17792 if (ECOFF_DEBUGGING)
17793 s_ignore (reg_type);
17794 else
252b5132 17795 {
ecb4347a 17796 long mask, off;
252b5132 17797
ecb4347a
DJ
17798 if (cur_proc_ptr == (procS *) NULL)
17799 {
17800 as_warn (_(".mask/.fmask outside of .ent"));
17801 demand_empty_rest_of_line ();
17802 return;
17803 }
252b5132 17804
ecb4347a
DJ
17805 if (get_absolute_expression_and_terminator (&mask) != ',')
17806 {
17807 as_warn (_("Bad .mask/.fmask directive"));
17808 --input_line_pointer;
17809 demand_empty_rest_of_line ();
17810 return;
17811 }
252b5132 17812
ecb4347a
DJ
17813 off = get_absolute_expression ();
17814
17815 if (reg_type == 'F')
17816 {
17817 cur_proc_ptr->fpreg_mask = mask;
17818 cur_proc_ptr->fpreg_offset = off;
17819 }
17820 else
17821 {
17822 cur_proc_ptr->reg_mask = mask;
17823 cur_proc_ptr->reg_offset = off;
17824 }
17825
17826 demand_empty_rest_of_line ();
252b5132 17827 }
252b5132
RH
17828}
17829
316f5878
RS
17830/* A table describing all the processors gas knows about. Names are
17831 matched in the order listed.
e7af610e 17832
316f5878
RS
17833 To ease comparison, please keep this table in the same order as
17834 gcc's mips_cpu_info_table[]. */
e972090a
NC
17835static const struct mips_cpu_info mips_cpu_info_table[] =
17836{
316f5878 17837 /* Entries for generic ISAs */
d16afab6
RS
17838 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17839 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17840 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17841 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17842 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17843 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17844 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17845 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17846 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
316f5878
RS
17847
17848 /* MIPS I */
d16afab6
RS
17849 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17850 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17851 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
316f5878
RS
17852
17853 /* MIPS II */
d16afab6 17854 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
316f5878
RS
17855
17856 /* MIPS III */
d16afab6
RS
17857 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17858 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17859 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17860 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17861 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17862 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17863 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17864 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17865 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17866 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17867 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17868 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17869 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
b15591bb 17870 /* ST Microelectronics Loongson 2E and 2F cores */
d16afab6
RS
17871 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17872 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
316f5878
RS
17873
17874 /* MIPS IV */
d16afab6
RS
17875 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17876 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17877 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17878 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17879 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17880 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17881 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17882 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17883 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17884 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17885 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17886 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17887 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17888 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17889 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
316f5878
RS
17890
17891 /* MIPS 32 */
d16afab6
RS
17892 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17893 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17894 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17895 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
ad3fea08
TS
17896
17897 /* MIPS 32 Release 2 */
d16afab6
RS
17898 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17899 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17900 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17901 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17902 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17903 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17904 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17905 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17906 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17907 ISA_MIPS32R2, CPU_MIPS32R2 },
17908 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17909 ISA_MIPS32R2, CPU_MIPS32R2 },
17910 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17911 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17912 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17913 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17914 /* Deprecated forms of the above. */
d16afab6
RS
17915 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17916 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 17917 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
d16afab6
RS
17918 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17919 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17920 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17921 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17922 /* Deprecated forms of the above. */
d16afab6
RS
17923 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17924 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 17925 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
d16afab6
RS
17926 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17927 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17928 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17929 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17930 /* Deprecated forms of the above. */
d16afab6
RS
17931 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17932 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
711eefe4 17933 /* 34Kn is a 34kc without DSP. */
d16afab6 17934 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 17935 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
d16afab6
RS
17936 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17937 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17938 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17939 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17940 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 17941 /* Deprecated forms of the above. */
d16afab6
RS
17942 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17943 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
30f8113a 17944 /* 1004K cores are multiprocessor versions of the 34K. */
d16afab6
RS
17945 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17946 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17947 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17948 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
32b26a03 17949
316f5878 17950 /* MIPS 64 */
d16afab6
RS
17951 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17952 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17953 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17954 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
ad3fea08 17955
c7a23324 17956 /* Broadcom SB-1 CPU core */
d16afab6 17957 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
1e85aad8 17958 /* Broadcom SB-1A CPU core */
d16afab6 17959 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
d051516a 17960
d16afab6 17961 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
e7af610e 17962
ed163775
MR
17963 /* MIPS 64 Release 2 */
17964
967344c6 17965 /* Cavium Networks Octeon CPU core */
d16afab6
RS
17966 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17967 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17968 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
967344c6 17969
52b6b6b9 17970 /* RMI Xlr */
d16afab6 17971 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
52b6b6b9 17972
55a36193
MK
17973 /* Broadcom XLP.
17974 XLP is mostly like XLR, with the prominent exception that it is
17975 MIPS64R2 rather than MIPS64. */
d16afab6 17976 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
55a36193 17977
316f5878 17978 /* End marker */
d16afab6 17979 { NULL, 0, 0, 0, 0 }
316f5878 17980};
e7af610e 17981
84ea6cf2 17982
316f5878
RS
17983/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17984 with a final "000" replaced by "k". Ignore case.
e7af610e 17985
316f5878 17986 Note: this function is shared between GCC and GAS. */
c6c98b38 17987
b34976b6 17988static bfd_boolean
17a2f251 17989mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
17990{
17991 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17992 given++, canonical++;
17993
17994 return ((*given == 0 && *canonical == 0)
17995 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17996}
17997
17998
17999/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18000 CPU name. We've traditionally allowed a lot of variation here.
18001
18002 Note: this function is shared between GCC and GAS. */
18003
b34976b6 18004static bfd_boolean
17a2f251 18005mips_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
18006{
18007 /* First see if the name matches exactly, or with a final "000"
18008 turned into "k". */
18009 if (mips_strict_matching_cpu_name_p (canonical, given))
b34976b6 18010 return TRUE;
316f5878
RS
18011
18012 /* If not, try comparing based on numerical designation alone.
18013 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18014 if (TOLOWER (*given) == 'r')
18015 given++;
18016 if (!ISDIGIT (*given))
b34976b6 18017 return FALSE;
316f5878
RS
18018
18019 /* Skip over some well-known prefixes in the canonical name,
18020 hoping to find a number there too. */
18021 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18022 canonical += 2;
18023 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18024 canonical += 2;
18025 else if (TOLOWER (canonical[0]) == 'r')
18026 canonical += 1;
18027
18028 return mips_strict_matching_cpu_name_p (canonical, given);
18029}
18030
18031
18032/* Parse an option that takes the name of a processor as its argument.
18033 OPTION is the name of the option and CPU_STRING is the argument.
18034 Return the corresponding processor enumeration if the CPU_STRING is
18035 recognized, otherwise report an error and return null.
18036
18037 A similar function exists in GCC. */
e7af610e
NC
18038
18039static const struct mips_cpu_info *
17a2f251 18040mips_parse_cpu (const char *option, const char *cpu_string)
e7af610e 18041{
316f5878 18042 const struct mips_cpu_info *p;
e7af610e 18043
316f5878
RS
18044 /* 'from-abi' selects the most compatible architecture for the given
18045 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18046 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18047 version. Look first at the -mgp options, if given, otherwise base
18048 the choice on MIPS_DEFAULT_64BIT.
e7af610e 18049
316f5878
RS
18050 Treat NO_ABI like the EABIs. One reason to do this is that the
18051 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18052 architecture. This code picks MIPS I for 'mips' and MIPS III for
18053 'mips64', just as we did in the days before 'from-abi'. */
18054 if (strcasecmp (cpu_string, "from-abi") == 0)
18055 {
18056 if (ABI_NEEDS_32BIT_REGS (mips_abi))
18057 return mips_cpu_info_from_isa (ISA_MIPS1);
18058
18059 if (ABI_NEEDS_64BIT_REGS (mips_abi))
18060 return mips_cpu_info_from_isa (ISA_MIPS3);
18061
18062 if (file_mips_gp32 >= 0)
18063 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
18064
18065 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18066 ? ISA_MIPS3
18067 : ISA_MIPS1);
18068 }
18069
18070 /* 'default' has traditionally been a no-op. Probably not very useful. */
18071 if (strcasecmp (cpu_string, "default") == 0)
18072 return 0;
18073
18074 for (p = mips_cpu_info_table; p->name != 0; p++)
18075 if (mips_matching_cpu_name_p (p->name, cpu_string))
18076 return p;
18077
20203fb9 18078 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
316f5878 18079 return 0;
e7af610e
NC
18080}
18081
316f5878
RS
18082/* Return the canonical processor information for ISA (a member of the
18083 ISA_MIPS* enumeration). */
18084
e7af610e 18085static const struct mips_cpu_info *
17a2f251 18086mips_cpu_info_from_isa (int isa)
e7af610e
NC
18087{
18088 int i;
18089
18090 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
ad3fea08 18091 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
316f5878 18092 && isa == mips_cpu_info_table[i].isa)
e7af610e
NC
18093 return (&mips_cpu_info_table[i]);
18094
e972090a 18095 return NULL;
e7af610e 18096}
fef14a42
TS
18097
18098static const struct mips_cpu_info *
17a2f251 18099mips_cpu_info_from_arch (int arch)
fef14a42
TS
18100{
18101 int i;
18102
18103 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18104 if (arch == mips_cpu_info_table[i].cpu)
18105 return (&mips_cpu_info_table[i]);
18106
18107 return NULL;
18108}
316f5878
RS
18109\f
18110static void
17a2f251 18111show (FILE *stream, const char *string, int *col_p, int *first_p)
316f5878
RS
18112{
18113 if (*first_p)
18114 {
18115 fprintf (stream, "%24s", "");
18116 *col_p = 24;
18117 }
18118 else
18119 {
18120 fprintf (stream, ", ");
18121 *col_p += 2;
18122 }
e7af610e 18123
316f5878
RS
18124 if (*col_p + strlen (string) > 72)
18125 {
18126 fprintf (stream, "\n%24s", "");
18127 *col_p = 24;
18128 }
18129
18130 fprintf (stream, "%s", string);
18131 *col_p += strlen (string);
18132
18133 *first_p = 0;
18134}
18135
18136void
17a2f251 18137md_show_usage (FILE *stream)
e7af610e 18138{
316f5878
RS
18139 int column, first;
18140 size_t i;
18141
18142 fprintf (stream, _("\
18143MIPS options:\n\
316f5878
RS
18144-EB generate big endian output\n\
18145-EL generate little endian output\n\
18146-g, -g2 do not remove unneeded NOPs or swap branches\n\
18147-G NUM allow referencing objects up to NUM bytes\n\
18148 implicitly with the gp register [default 8]\n"));
18149 fprintf (stream, _("\
18150-mips1 generate MIPS ISA I instructions\n\
18151-mips2 generate MIPS ISA II instructions\n\
18152-mips3 generate MIPS ISA III instructions\n\
18153-mips4 generate MIPS ISA IV instructions\n\
18154-mips5 generate MIPS ISA V instructions\n\
18155-mips32 generate MIPS32 ISA instructions\n\
af7ee8bf 18156-mips32r2 generate MIPS32 release 2 ISA instructions\n\
316f5878 18157-mips64 generate MIPS64 ISA instructions\n\
5f74bc13 18158-mips64r2 generate MIPS64 release 2 ISA instructions\n\
316f5878
RS
18159-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18160
18161 first = 1;
e7af610e
NC
18162
18163 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
316f5878
RS
18164 show (stream, mips_cpu_info_table[i].name, &column, &first);
18165 show (stream, "from-abi", &column, &first);
18166 fputc ('\n', stream);
e7af610e 18167
316f5878
RS
18168 fprintf (stream, _("\
18169-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18170-no-mCPU don't generate code specific to CPU.\n\
18171 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18172
18173 first = 1;
18174
18175 show (stream, "3900", &column, &first);
18176 show (stream, "4010", &column, &first);
18177 show (stream, "4100", &column, &first);
18178 show (stream, "4650", &column, &first);
18179 fputc ('\n', stream);
18180
18181 fprintf (stream, _("\
18182-mips16 generate mips16 instructions\n\
18183-no-mips16 do not generate mips16 instructions\n"));
18184 fprintf (stream, _("\
df58fc94
RS
18185-mmicromips generate microMIPS instructions\n\
18186-mno-micromips do not generate microMIPS instructions\n"));
18187 fprintf (stream, _("\
e16bfa71
TS
18188-msmartmips generate smartmips instructions\n\
18189-mno-smartmips do not generate smartmips instructions\n"));
18190 fprintf (stream, _("\
74cd071d
CF
18191-mdsp generate DSP instructions\n\
18192-mno-dsp do not generate DSP instructions\n"));
18193 fprintf (stream, _("\
8b082fb1
TS
18194-mdspr2 generate DSP R2 instructions\n\
18195-mno-dspr2 do not generate DSP R2 instructions\n"));
18196 fprintf (stream, _("\
ef2e4d86
CF
18197-mmt generate MT instructions\n\
18198-mno-mt do not generate MT instructions\n"));
18199 fprintf (stream, _("\
dec0624d
MR
18200-mmcu generate MCU instructions\n\
18201-mno-mcu do not generate MCU instructions\n"));
18202 fprintf (stream, _("\
b015e599
AP
18203-mvirt generate Virtualization instructions\n\
18204-mno-virt do not generate Virtualization instructions\n"));
18205 fprintf (stream, _("\
833794fc
MR
18206-minsn32 only generate 32-bit microMIPS instructions\n\
18207-mno-insn32 generate all microMIPS instructions\n"));
18208 fprintf (stream, _("\
c67a084a
NC
18209-mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18210-mfix-loongson2f-nop work around Loongson2F NOP errata\n\
d766e8ec 18211-mfix-vr4120 work around certain VR4120 errata\n\
7d8e00cf 18212-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
6a32d874 18213-mfix-24k insert a nop after ERET and DERET instructions\n\
d954098f 18214-mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
316f5878
RS
18215-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18216-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
aed1a261 18217-msym32 assume all symbols have 32-bit values\n\
316f5878
RS
18218-O0 remove unneeded NOPs, do not swap branches\n\
18219-O remove unneeded NOPs and swap branches\n\
316f5878
RS
18220--trap, --no-break trap exception on div by 0 and mult overflow\n\
18221--break, --no-trap break exception on div by 0 and mult overflow\n"));
037b32b9
AN
18222 fprintf (stream, _("\
18223-mhard-float allow floating-point instructions\n\
18224-msoft-float do not allow floating-point instructions\n\
18225-msingle-float only allow 32-bit floating-point operations\n\
18226-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
3bf0dbfb 18227--[no-]construct-floats [dis]allow floating point values to be constructed\n\
ba92f887
MR
18228--[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18229-mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18230
18231 first = 1;
18232
18233 show (stream, "legacy", &column, &first);
18234 show (stream, "2008", &column, &first);
18235
18236 fputc ('\n', stream);
18237
316f5878
RS
18238 fprintf (stream, _("\
18239-KPIC, -call_shared generate SVR4 position independent code\n\
861fb55a 18240-call_nonpic generate non-PIC code that can operate with DSOs\n\
0c000745 18241-mvxworks-pic generate VxWorks position independent code\n\
861fb55a 18242-non_shared do not generate code that can operate with DSOs\n\
316f5878 18243-xgot assume a 32 bit GOT\n\
dcd410fe 18244-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
bbe506e8 18245-mshared, -mno-shared disable/enable .cpload optimization for\n\
d821e36b 18246 position dependent (non shared) code\n\
316f5878
RS
18247-mabi=ABI create ABI conformant object file for:\n"));
18248
18249 first = 1;
18250
18251 show (stream, "32", &column, &first);
18252 show (stream, "o64", &column, &first);
18253 show (stream, "n32", &column, &first);
18254 show (stream, "64", &column, &first);
18255 show (stream, "eabi", &column, &first);
18256
18257 fputc ('\n', stream);
18258
18259 fprintf (stream, _("\
18260-32 create o32 ABI object file (default)\n\
18261-n32 create n32 ABI object file\n\
18262-64 create 64 ABI object file\n"));
e7af610e 18263}
14e777e0 18264
1575952e 18265#ifdef TE_IRIX
14e777e0 18266enum dwarf2_format
413a266c 18267mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
14e777e0 18268{
369943fe 18269 if (HAVE_64BIT_SYMBOLS)
1575952e 18270 return dwarf2_format_64bit_irix;
14e777e0
KB
18271 else
18272 return dwarf2_format_32bit;
18273}
1575952e 18274#endif
73369e65
EC
18275
18276int
18277mips_dwarf2_addr_size (void)
18278{
6b6b3450 18279 if (HAVE_64BIT_OBJECTS)
73369e65 18280 return 8;
73369e65
EC
18281 else
18282 return 4;
18283}
5862107c
EC
18284
18285/* Standard calling conventions leave the CFA at SP on entry. */
18286void
18287mips_cfi_frame_initial_instructions (void)
18288{
18289 cfi_add_CFA_def_cfa_register (SP);
18290}
18291
707bfff6
TS
18292int
18293tc_mips_regname_to_dw2regnum (char *regname)
18294{
18295 unsigned int regnum = -1;
18296 unsigned int reg;
18297
18298 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
18299 regnum = reg;
18300
18301 return regnum;
18302}
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