Fix spelling in comments in C source files (binutils)
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
CommitLineData
252b5132 1/* tc-mips.c -- assemble code for a MIPS chip.
6f2750fe 2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
252b5132
RH
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
6 Support.
7
8 This file is part of GAS.
9
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
ec2655a6 12 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH
13 any later version.
14
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 02110-1301, USA. */
252b5132
RH
24
25#include "as.h"
26#include "config.h"
27#include "subsegs.h"
3882b010 28#include "safe-ctype.h"
252b5132 29
252b5132
RH
30#include "opcode/mips.h"
31#include "itbl-ops.h"
c5dd6aab 32#include "dwarf2dbg.h"
5862107c 33#include "dw2gencfi.h"
252b5132 34
42429eac
RS
35/* Check assumptions made in this file. */
36typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
38
252b5132
RH
39#ifdef DEBUG
40#define DBG(x) printf x
41#else
42#define DBG(x)
43#endif
44
263b2574 45#define streq(a, b) (strcmp (a, b) == 0)
46
9e12b7a2
RS
47#define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
49
252b5132 50/* Clean up namespace so we can include obj-elf.h too. */
17a2f251
TS
51static int mips_output_flavor (void);
52static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
252b5132
RH
53#undef OBJ_PROCESS_STAB
54#undef OUTPUT_FLAVOR
55#undef S_GET_ALIGN
56#undef S_GET_SIZE
57#undef S_SET_ALIGN
58#undef S_SET_SIZE
252b5132
RH
59#undef obj_frob_file
60#undef obj_frob_file_after_relocs
61#undef obj_frob_symbol
62#undef obj_pop_insert
63#undef obj_sec_sym_ok_for_reloc
64#undef OBJ_COPY_SYMBOL_ATTRIBUTES
65
66#include "obj-elf.h"
67/* Fix any of them that we actually care about. */
68#undef OUTPUT_FLAVOR
69#define OUTPUT_FLAVOR mips_output_flavor()
252b5132 70
252b5132 71#include "elf/mips.h"
252b5132
RH
72
73#ifndef ECOFF_DEBUGGING
74#define NO_ECOFF_DEBUGGING
75#define ECOFF_DEBUGGING 0
76#endif
77
ecb4347a
DJ
78int mips_flag_mdebug = -1;
79
dcd410fe
RO
80/* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
83#ifdef TE_IRIX
84int mips_flag_pdr = FALSE;
85#else
86int mips_flag_pdr = TRUE;
87#endif
88
252b5132
RH
89#include "ecoff.h"
90
252b5132 91static char *mips_regmask_frag;
351cdf24 92static char *mips_flags_frag;
252b5132 93
85b51719 94#define ZERO 0
741fe287 95#define ATREG 1
df58fc94
RS
96#define S0 16
97#define S7 23
252b5132
RH
98#define TREG 24
99#define PIC_CALL_REG 25
100#define KT0 26
101#define KT1 27
102#define GP 28
103#define SP 29
104#define FP 30
105#define RA 31
106
107#define ILLEGAL_REG (32)
108
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109#define AT mips_opts.at
110
252b5132
RH
111extern int target_big_endian;
112
252b5132 113/* The name of the readonly data section. */
e8044f35 114#define RDATA_SECTION_NAME ".rodata"
252b5132 115
a4e06468
RS
116/* Ways in which an instruction can be "appended" to the output. */
117enum append_method {
118 /* Just add it normally. */
119 APPEND_ADD,
120
121 /* Add it normally and then add a nop. */
122 APPEND_ADD_WITH_NOP,
123
124 /* Turn an instruction with a delay slot into a "compact" version. */
125 APPEND_ADD_COMPACT,
126
127 /* Insert the instruction before the last one. */
128 APPEND_SWAP
129};
130
47e39b9d
RS
131/* Information about an instruction, including its format, operands
132 and fixups. */
133struct mips_cl_insn
134{
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
137
47e39b9d 138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
5c04167a
RS
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
141 extension. */
47e39b9d
RS
142 unsigned long insn_opcode;
143
144 /* The frag that contains the instruction. */
145 struct frag *frag;
146
147 /* The offset into FRAG of the first instruction byte. */
148 long where;
149
150 /* The relocs associated with the instruction, if any. */
151 fixS *fixp[3];
152
a38419a5
RS
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
47e39b9d 155
708587a4 156 /* True if this instruction occurred in a .set noreorder block. */
47e39b9d
RS
157 unsigned int noreorder_p : 1;
158
2fa15973
RS
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
15be625d
CM
161
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
e407c74b
NC
164
165 /* True if this instruction is cleared from history by unconditional
166 branch. */
167 unsigned int cleared_p : 1;
47e39b9d
RS
168};
169
a325df1d
TS
170/* The ABI to use. */
171enum mips_abi_level
172{
173 NO_ABI = 0,
174 O32_ABI,
175 O64_ABI,
176 N32_ABI,
177 N64_ABI,
178 EABI_ABI
179};
180
181/* MIPS ABI we are using for this output file. */
316f5878 182static enum mips_abi_level mips_abi = NO_ABI;
a325df1d 183
143d77c5
EC
184/* Whether or not we have code that can call pic code. */
185int mips_abicalls = FALSE;
186
aa6975fb
ILT
187/* Whether or not we have code which can be put into a shared
188 library. */
189static bfd_boolean mips_in_shared = TRUE;
190
252b5132
RH
191/* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
193 reliable. */
194
e972090a
NC
195struct mips_set_options
196{
252b5132
RH
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
200 int isa;
846ef2d0
RS
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
203 architecture. */
204 int ase;
252b5132
RH
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
209 int mips16;
df58fc94
RS
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
214 int micromips;
252b5132
RH
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
217 int noreorder;
741fe287
MR
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 unsigned int at;
252b5132
RH
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
225 `.set macro'. */
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 int nomove;
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
233 nobopt'. */
234 int nobopt;
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
237 int noautoextend;
833794fc
MR
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
241 bfd_boolean insn32;
a325df1d
TS
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
bad1aba3 245 int gp;
0b35dfee 246 int fp;
fef14a42
TS
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
249 int arch;
aed1a261
RS
250 /* True if ".set sym32" is in effect. */
251 bfd_boolean sym32;
037b32b9
AN
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
256
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
351cdf24
MF
261
262 /* 1 if single-precision operations on odd-numbered registers are
263 allowed. */
264 int oddspreg;
252b5132
RH
265};
266
919731af 267/* Specifies whether module level options have been checked yet. */
268static bfd_boolean file_mips_opts_checked = FALSE;
269
7361da2c
AB
270/* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274static int mips_nan2008 = -1;
a325df1d 275
0b35dfee 276/* This is the struct we use to hold the module level set of options.
bad1aba3 277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
0b35dfee 278 fp fields to -1 to indicate that they have not been initialized. */
037b32b9 279
0b35dfee 280static struct mips_set_options file_mips_opts =
281{
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
bad1aba3 285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
351cdf24 286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
0b35dfee 287};
252b5132 288
0b35dfee 289/* This is similar to file_mips_opts, but for the current set of options. */
ba92f887 290
e972090a
NC
291static struct mips_set_options mips_opts =
292{
846ef2d0 293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
b015e599 294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
833794fc 295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
bad1aba3 296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
351cdf24 297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
e7af610e 298};
252b5132 299
846ef2d0
RS
300/* Which bits of file_ase were explicitly set or cleared by ASE options. */
301static unsigned int file_ase_explicit;
302
252b5132
RH
303/* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
305 place. */
306unsigned long mips_gprmask;
307unsigned long mips_cprmask[4];
308
738f4d98 309/* True if any MIPS16 code was produced. */
a4672219
TS
310static int file_ase_mips16;
311
3994f87e
TS
312#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
ae52f483
AB
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
3994f87e 316 || mips_opts.isa == ISA_MIPS64 \
ae52f483
AB
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
3994f87e 320
df58fc94
RS
321/* True if any microMIPS code was produced. */
322static int file_ase_micromips;
323
b12dd2e4
CF
324/* True if we want to create R_MIPS_JALR for jalr $25. */
325#ifdef TE_IRIX
1180b5a4 326#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
b12dd2e4 327#else
1180b5a4
RS
328/* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331#define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
b12dd2e4
CF
334#endif
335
ec68c924 336/* The argument of the -march= flag. The architecture we are assembling. */
316f5878 337static const char *mips_arch_string;
ec68c924
EC
338
339/* The argument of the -mtune= flag. The architecture for which we
340 are optimizing. */
341static int mips_tune = CPU_UNKNOWN;
316f5878 342static const char *mips_tune_string;
ec68c924 343
316f5878 344/* True when generating 32-bit code for a 64-bit processor. */
252b5132
RH
345static int mips_32bitmode = 0;
346
316f5878
RS
347/* True if the given ABI requires 32-bit registers. */
348#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
349
350/* Likewise 64-bit registers. */
707bfff6 351#define ABI_NEEDS_64BIT_REGS(ABI) \
134c0c8b 352 ((ABI) == N32_ABI \
707bfff6 353 || (ABI) == N64_ABI \
316f5878
RS
354 || (ABI) == O64_ABI)
355
7361da2c
AB
356#define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
359
ad3fea08 360/* Return true if ISA supports 64 bit wide gp registers. */
707bfff6
TS
361#define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
ae52f483
AB
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
7361da2c
AB
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
9ce8a5dd 370
ad3fea08
TS
371/* Return true if ISA supports 64 bit wide float registers. */
372#define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
ae52f483
AB
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
7361da2c 379 || (ISA) == ISA_MIPS32R6 \
ad3fea08 380 || (ISA) == ISA_MIPS64 \
ae52f483
AB
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
7361da2c
AB
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
ad3fea08 385
af7ee8bf
CD
386/* Return true if ISA supports 64-bit right rotate (dror et al.)
387 instructions. */
707bfff6 388#define ISA_HAS_DROR(ISA) \
df58fc94 389 ((ISA) == ISA_MIPS64R2 \
ae52f483
AB
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
7361da2c 392 || (ISA) == ISA_MIPS64R6 \
df58fc94
RS
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
395 )
af7ee8bf
CD
396
397/* Return true if ISA supports 32-bit right rotate (ror et al.)
398 instructions. */
707bfff6
TS
399#define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
ae52f483
AB
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
7361da2c 403 || (ISA) == ISA_MIPS32R6 \
707bfff6 404 || (ISA) == ISA_MIPS64R2 \
ae52f483
AB
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
7361da2c 407 || (ISA) == ISA_MIPS64R6 \
846ef2d0 408 || (mips_opts.ase & ASE_SMARTMIPS) \
df58fc94
RS
409 || mips_opts.micromips \
410 )
707bfff6 411
7455baf8 412/* Return true if ISA supports single-precision floats in odd registers. */
351cdf24
MF
413#define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
7361da2c 418 || (ISA) == ISA_MIPS32R6 \
351cdf24
MF
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
7361da2c 423 || (ISA) == ISA_MIPS64R6 \
351cdf24
MF
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
af7ee8bf 426
ad3fea08
TS
427/* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429#define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
ae52f483
AB
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
7361da2c
AB
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
438
439/* Return true if ISA supports legacy NAN. */
440#define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
ae52f483
AB
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
ad3fea08 454
bad1aba3 455#define GPR_SIZE \
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
457 ? 32 \
458 : mips_opts.gp)
ca4e0257 459
bad1aba3 460#define FPR_SIZE \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
462 ? 32 \
463 : mips_opts.fp)
ca4e0257 464
316f5878 465#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
e013f690 466
316f5878 467#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
e013f690 468
3b91255e
RS
469/* True if relocations are stored in-place. */
470#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
471
aed1a261
RS
472/* The ABI-derived address size. */
473#define HAVE_64BIT_ADDRESSES \
bad1aba3 474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
aed1a261 475#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
e013f690 476
aed1a261
RS
477/* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479#define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
ca4e0257 482
b7c7d6c1
TS
483/* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
f899b4b8 486#define ADDRESS_ADD_INSN \
b7c7d6c1 487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
f899b4b8
TS
488
489#define ADDRESS_ADDI_INSN \
b7c7d6c1 490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
f899b4b8
TS
491
492#define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
494
495#define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
497
a4672219 498/* Return true if the given CPU supports the MIPS16 ASE. */
3396de36
TS
499#define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
a4672219 502
2309ddf2 503/* Return true if the given CPU supports the microMIPS ASE. */
df58fc94
RS
504#define CPU_HAS_MICROMIPS(cpu) 0
505
60b63b72
RS
506/* True if CPU has a dror instruction. */
507#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
508
509/* True if CPU has a ror instruction. */
510#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
511
dd6a37e7 512/* True if CPU is in the Octeon family */
2c629856
N
513#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
dd6a37e7 515
dd3cbb7e 516/* True if CPU has seq/sne and seqi/snei instructions. */
dd6a37e7 517#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
dd3cbb7e 518
0aa27725
RS
519/* True, if CPU has support for ldc1 and sdc1. */
520#define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
522
c8978940
CD
523/* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
525
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535#define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
ae52f483
AB
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
7361da2c 540 || mips_opts.isa == ISA_MIPS32R6 \
c8978940
CD
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
ae52f483
AB
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
7361da2c 545 || mips_opts.isa == ISA_MIPS64R6 \
c8978940 546 || mips_opts.arch == CPU_R4010 \
e407c74b 547 || mips_opts.arch == CPU_R5900 \
c8978940
CD
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
3aa3176b
TS
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
c8978940 552 || mips_opts.arch == CPU_RM7000 \
c8978940 553 || mips_opts.arch == CPU_VR5500 \
df58fc94 554 || mips_opts.micromips \
c8978940 555 )
252b5132
RH
556
557/* Whether the processor uses hardware interlocks to protect reads
81912461
ILT
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
67dc82bc 560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
df58fc94
RS
561 level I and microMIPS mode instructions are always interlocked. */
562#define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
e407c74b 565 || mips_opts.arch == CPU_R5900 \
df58fc94
RS
566 || mips_opts.micromips \
567 )
252b5132 568
81912461
ILT
569/* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
43885403
MF
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
81912461 574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
df58fc94
RS
575 levels I, II, and III and microMIPS mode instructions are always
576 interlocked. */
bdaaa2e1 577/* Itbl support may require additional care here. */
81912461
ILT
578#define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
df58fc94 583 || mips_opts.micromips \
81912461
ILT
584 )
585
586/* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
df58fc94
RS
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592#define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
595 )
252b5132 596
6b76fefe
CM
597/* Is this a mfhi or mflo instruction? */
598#define MF_HILO_INSN(PINFO) \
b19e8a9b
AN
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
600
df58fc94
RS
601/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604#define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
606
42429eac 607/* The minimum and maximum signed values that can be stored in a GPR. */
bad1aba3 608#define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
42429eac
RS
609#define GPR_SMIN (-GPR_SMAX - 1)
610
252b5132
RH
611/* MIPS PIC level. */
612
a161fe53 613enum mips_pic_level mips_pic;
252b5132 614
c9914766 615/* 1 if we should generate 32 bit offsets from the $gp register in
252b5132 616 SVR4_PIC mode. Currently has no meaning in other modes. */
c9914766 617static int mips_big_got = 0;
252b5132
RH
618
619/* 1 if trap instructions should used for overflow rather than break
620 instructions. */
c9914766 621static int mips_trap = 0;
252b5132 622
119d663a 623/* 1 if double width floating point constants should not be constructed
b6ff326e 624 by assembling two single width halves into two single width floating
119d663a
NC
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
d547a75e 627 in the status register, and the setting of this bit cannot be determined
119d663a
NC
628 automatically at assemble time. */
629static int mips_disable_float_construction;
630
252b5132
RH
631/* Non-zero if any .set noreorder directives were used. */
632
633static int mips_any_noreorder;
634
6b76fefe
CM
635/* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637static int mips_7000_hilo_fix;
638
02ffd3e4 639/* The size of objects in the small data section. */
156c2f8b 640static unsigned int g_switch_value = 8;
252b5132
RH
641/* Whether the -G option was used. */
642static int g_switch_seen = 0;
643
644#define N_RMASK 0xc4
645#define N_VFP 0xd4
646
647/* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
650 better.
651
652 This function can only provide a guess, but it seems to work for
fba2b7f9
GK
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
655 delay slot.
252b5132
RH
656
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
17a2f251 659static int nopic_need_relax (symbolS *, int);
252b5132
RH
660
661/* handle of the OPCODE hash table */
662static struct hash_control *op_hash = NULL;
663
664/* The opcode hash table we use for the mips16. */
665static struct hash_control *mips16_op_hash = NULL;
666
df58fc94
RS
667/* The opcode hash table we use for the microMIPS ASE. */
668static struct hash_control *micromips_op_hash = NULL;
669
252b5132
RH
670/* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672const char comment_chars[] = "#";
673
674/* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677/* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
bdaaa2e1 679 #NO_APP at the beginning of its output. */
252b5132
RH
680/* Also note that C style comments are always supported. */
681const char line_comment_chars[] = "#";
682
bdaaa2e1 683/* This array holds machine specific line separator characters. */
63a0b638 684const char line_separator_chars[] = ";";
252b5132
RH
685
686/* Chars that can be used to separate mant from exp in floating point nums */
687const char EXP_CHARS[] = "eE";
688
689/* Chars that mean this number is a floating point constant */
690/* As in 0f12.456 */
691/* or 0d1.2345e12 */
692const char FLT_CHARS[] = "rRsSfFdDxXpP";
693
694/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
697 */
698
e3de51ce
RS
699/* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701enum mips_insn_error_format {
702 ERR_FMT_PLAIN,
703 ERR_FMT_I,
704 ERR_FMT_SS,
705};
706
707/* Information about an error that was found while assembling the current
708 instruction. */
709struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
719
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
722 a whole. */
723 int min_argnum;
724
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
727 const char *msg;
728 union {
729 int i;
730 const char *ss[2];
731 } u;
732};
733
734/* The error that should be reported for the current instruction. */
735static struct mips_insn_error insn_error;
252b5132
RH
736
737static int auto_align = 1;
738
739/* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
742 variable. */
743static offsetT mips_cprestore_offset = -1;
744
67c1ffbe 745/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
6478892d 746 more optimizations, it can use a register value instead of a memory-saved
956cd1d6 747 offset and even an other register than $gp as global pointer. */
6478892d
TS
748static offsetT mips_cpreturn_offset = -1;
749static int mips_cpreturn_register = -1;
750static int mips_gp_register = GP;
def2e0dd 751static int mips_gprel_offset = 0;
6478892d 752
7a621144
DJ
753/* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755static int mips_cprestore_valid = 0;
756
252b5132
RH
757/* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759static int mips_frame_reg = SP;
760
7a621144
DJ
761/* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763static int mips_frame_reg_valid = 0;
764
252b5132
RH
765/* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
767
768/* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
771 insert NOPs. */
772static int mips_optimize = 2;
773
774/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776static int mips_debug = 0;
777
7d8e00cf
RS
778/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779#define MAX_VR4130_NOPS 4
780
781/* The maximum number of NOPs needed to fill delay slots. */
782#define MAX_DELAY_NOPS 2
783
784/* The maximum number of NOPs needed for any purpose. */
785#define MAX_NOPS 4
71400594
RS
786
787/* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792static struct mips_cl_insn history[1 + MAX_NOPS];
252b5132 793
fc76e730 794/* Arrays of operands for each instruction. */
14daeee3 795#define MAX_OPERANDS 6
fc76e730
RS
796struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
798};
799static struct mips_operand_array *mips_operands;
800static struct mips_operand_array *mips16_operands;
801static struct mips_operand_array *micromips_operands;
802
1e915849 803/* Nop instructions used by emit_nop. */
df58fc94
RS
804static struct mips_cl_insn nop_insn;
805static struct mips_cl_insn mips16_nop_insn;
806static struct mips_cl_insn micromips_nop16_insn;
807static struct mips_cl_insn micromips_nop32_insn;
1e915849
RS
808
809/* The appropriate nop for the current mode. */
833794fc
MR
810#define NOP_INSN (mips_opts.mips16 \
811 ? &mips16_nop_insn \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? &micromips_nop32_insn \
815 : &micromips_nop16_insn) \
816 : &nop_insn))
df58fc94
RS
817
818/* The size of NOP_INSN in bytes. */
833794fc
MR
819#define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
821 ? 2 : 4)
252b5132 822
252b5132
RH
823/* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
826 decreased. */
827static fragS *prev_nop_frag;
828
829/* The number of nop instructions we created in prev_nop_frag. */
830static int prev_nop_frag_holds;
831
832/* The number of nop instructions that we know we need in
bdaaa2e1 833 prev_nop_frag. */
252b5132
RH
834static int prev_nop_frag_required;
835
836/* The number of instructions we've seen since prev_nop_frag. */
837static int prev_nop_frag_since;
838
e8044f35
RS
839/* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
252b5132
RH
845
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
bdaaa2e1 848 corresponding LO relocation. */
252b5132 849
e972090a
NC
850struct mips_hi_fixup
851{
252b5132
RH
852 /* Next HI fixup. */
853 struct mips_hi_fixup *next;
854 /* This fixup. */
855 fixS *fixp;
856 /* The section this fixup is in. */
857 segT seg;
858};
859
860/* The list of unmatched HI relocs. */
861
862static struct mips_hi_fixup *mips_hi_fixup_list;
863
64bdfcaf
RS
864/* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
866
867static fragS *prev_reloc_op_frag;
868
252b5132
RH
869/* Map mips16 register numbers to normal MIPS register numbers. */
870
e972090a
NC
871static const unsigned int mips16_to_32_reg_map[] =
872{
252b5132
RH
873 16, 17, 2, 3, 4, 5, 6, 7
874};
60b63b72 875
df58fc94
RS
876/* Map microMIPS register numbers to normal MIPS register numbers. */
877
df58fc94 878#define micromips_to_32_reg_d_map mips16_to_32_reg_map
df58fc94
RS
879
880/* The microMIPS registers with type h. */
e76ff5ab 881static const unsigned int micromips_to_32_reg_h_map1[] =
df58fc94
RS
882{
883 5, 5, 6, 4, 4, 4, 4, 4
884};
e76ff5ab 885static const unsigned int micromips_to_32_reg_h_map2[] =
df58fc94
RS
886{
887 6, 7, 7, 21, 22, 5, 6, 7
888};
889
df58fc94
RS
890/* The microMIPS registers with type m. */
891static const unsigned int micromips_to_32_reg_m_map[] =
892{
893 0, 17, 2, 3, 16, 18, 19, 20
894};
895
896#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
897
71400594
RS
898/* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
c67a084a
NC
900enum fix_vr4120_class
901{
71400594
RS
902 FIX_VR4120_MACC,
903 FIX_VR4120_DMACC,
904 FIX_VR4120_MULT,
905 FIX_VR4120_DMULT,
906 FIX_VR4120_DIV,
907 FIX_VR4120_MTHILO,
908 NUM_FIX_VR4120_CLASSES
909};
910
c67a084a
NC
911/* ...likewise -mfix-loongson2f-jump. */
912static bfd_boolean mips_fix_loongson2f_jump;
913
914/* ...likewise -mfix-loongson2f-nop. */
915static bfd_boolean mips_fix_loongson2f_nop;
916
917/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918static bfd_boolean mips_fix_loongson2f;
919
71400594
RS
920/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
924
925/* True if -mfix-vr4120 is in force. */
d766e8ec 926static int mips_fix_vr4120;
4a6a3df4 927
7d8e00cf
RS
928/* ...likewise -mfix-vr4130. */
929static int mips_fix_vr4130;
930
6a32d874
CM
931/* ...likewise -mfix-24k. */
932static int mips_fix_24k;
933
a8d14a88
CM
934/* ...likewise -mfix-rm7000 */
935static int mips_fix_rm7000;
936
d954098f
DD
937/* ...likewise -mfix-cn63xxp1 */
938static bfd_boolean mips_fix_cn63xxp1;
939
4a6a3df4
AO
940/* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
944
945static int mips_relax_branch;
252b5132 946\f
4d7206a2
RS
947/* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
953
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
959
584892a6
RS
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
4d7206a2 964
584892a6
RS
965 RELAX_USE_SECOND
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
968
969 RELAX_SECOND_LONGER
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
973
974 RELAX_NOMACRO
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
977
978 RELAX_DELAY_SLOT
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
980 delay slot.
4d7206a2 981
df58fc94
RS
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
984 16-bit instruction.
985
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
989
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
993
4d7206a2
RS
994 The frag's "opcode" points to the first fixup for relaxable code.
995
996 Relaxable macros are generated using a sequence such as:
997
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1000 relax_switch ();
1001 ... generate second expansion ...
1002 relax_end ();
1003
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
584892a6 1006#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
4d7206a2 1007
584892a6
RS
1008#define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009#define RELAX_SECOND(X) ((X) & 0xff)
1010#define RELAX_USE_SECOND 0x10000
1011#define RELAX_SECOND_LONGER 0x20000
1012#define RELAX_NOMACRO 0x40000
1013#define RELAX_DELAY_SLOT 0x80000
df58fc94
RS
1014#define RELAX_DELAY_SLOT_16BIT 0x100000
1015#define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016#define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
252b5132 1017
4a6a3df4
AO
1018/* Branch without likely bit. If label is out of range, we turn:
1019
134c0c8b 1020 beq reg1, reg2, label
4a6a3df4
AO
1021 delay slot
1022
1023 into
1024
1025 bne reg1, reg2, 0f
1026 nop
1027 j label
1028 0: delay slot
1029
1030 with the following opcode replacements:
1031
1032 beq <-> bne
1033 blez <-> bgtz
1034 bltz <-> bgez
1035 bc1f <-> bc1t
1036
1037 bltzal <-> bgezal (with jal label instead of j label)
1038
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1046
1047 Branch likely. If label is out of range, we turn:
1048
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1051
1052 into
1053
1054 beql reg1, reg2, 1f
1055 nop
1056 beql $0, $0, 2f
1057 nop
1058 1: j[al] label
1059 delay slot (executed only if branch taken)
1060 2:
1061
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
b34976b6 1064
4a6a3df4
AO
1065 bne reg1, reg2, 0f
1066 nop
1067 j[al] label
1068 delay slot (executed only if branch taken)
1069 0:
1070
1071 beql -> bne
1072 bnel -> beq
1073 blezl -> bgtz
1074 bgtzl -> blez
1075 bltzl -> bgez
1076 bgezl -> bltz
1077 bc1fl -> bc1t
1078 bc1tl -> bc1f
1079
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1082
1083
1084 but it's not clear that it would actually improve performance. */
66b3e8da
MR
1085#define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1087 (0xc0000000 \
1088 | ((at) & 0x1f) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
4a6a3df4 1093#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
66b3e8da
MR
1094#define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095#define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096#define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097#define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098#define RELAX_BRANCH_AT(i) ((i) & 0x1f)
4a6a3df4 1099
252b5132
RH
1100/* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1105
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1110
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1121 (0x80000000 \
1122 | ((type) & 0xff) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
4a6a3df4 1127#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
252b5132
RH
1128#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
885add95 1139
df58fc94
RS
1140/* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1145
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1150 cases.
1151
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
8484fb75
MR
1154 selected as the assembler temporary, whether in the 32-bit
1155 instruction mode, whether the branch is unconditional, whether it is
7bd374a4
MR
1156 compact, whether there is no delay-slot instruction available to fill
1157 in, whether it stores the link address implicitly in $ra, whether
1158 relaxation of out-of-range 32-bit branches to a sequence of
8484fb75
MR
1159 instructions is enabled, and whether the displacement of a branch is
1160 too large to fit as an immediate argument of a 16-bit and a 32-bit
1161 branch, respectively. */
1162#define RELAX_MICROMIPS_ENCODE(type, at, insn32, \
7bd374a4 1163 uncond, compact, link, nods, \
40209cad
MR
1164 relax32, toofar16, toofar32) \
1165 (0x40000000 \
1166 | ((type) & 0xff) \
1167 | (((at) & 0x1f) << 8) \
8484fb75
MR
1168 | ((insn32) ? 0x2000 : 0) \
1169 | ((uncond) ? 0x4000 : 0) \
1170 | ((compact) ? 0x8000 : 0) \
1171 | ((link) ? 0x10000 : 0) \
7bd374a4
MR
1172 | ((nods) ? 0x20000 : 0) \
1173 | ((relax32) ? 0x40000 : 0) \
1174 | ((toofar16) ? 0x80000 : 0) \
1175 | ((toofar32) ? 0x100000 : 0))
df58fc94
RS
1176#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1177#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1178#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
8484fb75
MR
1179#define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1180#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0)
1181#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0)
1182#define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0)
7bd374a4
MR
1183#define RELAX_MICROMIPS_NODS(i) (((i) & 0x20000) != 0)
1184#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x40000) != 0)
8484fb75 1185
7bd374a4
MR
1186#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x80000) != 0)
1187#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x80000)
1188#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x80000)
1189#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x100000) != 0)
1190#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x100000)
1191#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x100000)
df58fc94 1192
43c0598f
RS
1193/* Sign-extend 16-bit value X. */
1194#define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1195
885add95
CD
1196/* Is the given value a sign-extended 32-bit value? */
1197#define IS_SEXT_32BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1199 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1200
1201/* Is the given value a sign-extended 16-bit value? */
1202#define IS_SEXT_16BIT_NUM(x) \
1203 (((x) &~ (offsetT) 0x7fff) == 0 \
1204 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1205
df58fc94
RS
1206/* Is the given value a sign-extended 12-bit value? */
1207#define IS_SEXT_12BIT_NUM(x) \
1208 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1209
7f3c4072
CM
1210/* Is the given value a sign-extended 9-bit value? */
1211#define IS_SEXT_9BIT_NUM(x) \
1212 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1213
2051e8c4
MR
1214/* Is the given value a zero-extended 32-bit value? Or a negated one? */
1215#define IS_ZEXT_32BIT_NUM(x) \
1216 (((x) &~ (offsetT) 0xffffffff) == 0 \
1217 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1218
bf12938e
RS
1219/* Extract bits MASK << SHIFT from STRUCT and shift them right
1220 SHIFT places. */
1221#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1222 (((STRUCT) >> (SHIFT)) & (MASK))
1223
bf12938e 1224/* Extract the operand given by FIELD from mips_cl_insn INSN. */
df58fc94
RS
1225#define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1226 (!(MICROMIPS) \
1227 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1228 : EXTRACT_BITS ((INSN).insn_opcode, \
1229 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
bf12938e
RS
1230#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1231 EXTRACT_BITS ((INSN).insn_opcode, \
1232 MIPS16OP_MASK_##FIELD, \
1233 MIPS16OP_SH_##FIELD)
5c04167a
RS
1234
1235/* The MIPS16 EXTEND opcode, shifted left 16 places. */
1236#define MIPS16_EXTEND (0xf000U << 16)
4d7206a2 1237\f
df58fc94
RS
1238/* Whether or not we are emitting a branch-likely macro. */
1239static bfd_boolean emit_branch_likely_macro = FALSE;
1240
4d7206a2
RS
1241/* Global variables used when generating relaxable macros. See the
1242 comment above RELAX_ENCODE for more details about how relaxation
1243 is used. */
1244static struct {
1245 /* 0 if we're not emitting a relaxable macro.
1246 1 if we're emitting the first of the two relaxation alternatives.
1247 2 if we're emitting the second alternative. */
1248 int sequence;
1249
1250 /* The first relaxable fixup in the current frag. (In other words,
1251 the first fixup that refers to relaxable code.) */
1252 fixS *first_fixup;
1253
1254 /* sizes[0] says how many bytes of the first alternative are stored in
1255 the current frag. Likewise sizes[1] for the second alternative. */
1256 unsigned int sizes[2];
1257
1258 /* The symbol on which the choice of sequence depends. */
1259 symbolS *symbol;
1260} mips_relax;
252b5132 1261\f
584892a6
RS
1262/* Global variables used to decide whether a macro needs a warning. */
1263static struct {
1264 /* True if the macro is in a branch delay slot. */
1265 bfd_boolean delay_slot_p;
1266
df58fc94
RS
1267 /* Set to the length in bytes required if the macro is in a delay slot
1268 that requires a specific length of instruction, otherwise zero. */
1269 unsigned int delay_slot_length;
1270
584892a6
RS
1271 /* For relaxable macros, sizes[0] is the length of the first alternative
1272 in bytes and sizes[1] is the length of the second alternative.
1273 For non-relaxable macros, both elements give the length of the
1274 macro in bytes. */
1275 unsigned int sizes[2];
1276
df58fc94
RS
1277 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1278 instruction of the first alternative in bytes and first_insn_sizes[1]
1279 is the length of the first instruction of the second alternative.
1280 For non-relaxable macros, both elements give the length of the first
1281 instruction in bytes.
1282
1283 Set to zero if we haven't yet seen the first instruction. */
1284 unsigned int first_insn_sizes[2];
1285
1286 /* For relaxable macros, insns[0] is the number of instructions for the
1287 first alternative and insns[1] is the number of instructions for the
1288 second alternative.
1289
1290 For non-relaxable macros, both elements give the number of
1291 instructions for the macro. */
1292 unsigned int insns[2];
1293
584892a6
RS
1294 /* The first variant frag for this macro. */
1295 fragS *first_frag;
1296} mips_macro_warning;
1297\f
252b5132
RH
1298/* Prototypes for static functions. */
1299
252b5132
RH
1300enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1301
b34976b6 1302static void append_insn
df58fc94
RS
1303 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1304 bfd_boolean expansionp);
7d10b47d 1305static void mips_no_prev_insn (void);
c67a084a 1306static void macro_build (expressionS *, const char *, const char *, ...);
b34976b6 1307static void mips16_macro_build
03ea81db 1308 (expressionS *, const char *, const char *, va_list *);
67c0d1eb 1309static void load_register (int, expressionS *, int);
584892a6
RS
1310static void macro_start (void);
1311static void macro_end (void);
833794fc 1312static void macro (struct mips_cl_insn *ip, char *str);
17a2f251 1313static void mips16_macro (struct mips_cl_insn * ip);
17a2f251
TS
1314static void mips_ip (char *str, struct mips_cl_insn * ip);
1315static void mips16_ip (char *str, struct mips_cl_insn * ip);
b34976b6 1316static void mips16_immed
3b4dbbbf 1317 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
43c0598f 1318 unsigned int, unsigned long *);
5e0116d5 1319static size_t my_getSmallExpression
17a2f251
TS
1320 (expressionS *, bfd_reloc_code_real_type *, char *);
1321static void my_getExpression (expressionS *, char *);
1322static void s_align (int);
1323static void s_change_sec (int);
1324static void s_change_section (int);
1325static void s_cons (int);
1326static void s_float_cons (int);
1327static void s_mips_globl (int);
1328static void s_option (int);
1329static void s_mipsset (int);
1330static void s_abicalls (int);
1331static void s_cpload (int);
1332static void s_cpsetup (int);
1333static void s_cplocal (int);
1334static void s_cprestore (int);
1335static void s_cpreturn (int);
741d6ea8
JM
1336static void s_dtprelword (int);
1337static void s_dtpreldword (int);
d0f13682
CLT
1338static void s_tprelword (int);
1339static void s_tpreldword (int);
17a2f251
TS
1340static void s_gpvalue (int);
1341static void s_gpword (int);
1342static void s_gpdword (int);
a3f278e2 1343static void s_ehword (int);
17a2f251
TS
1344static void s_cpadd (int);
1345static void s_insn (int);
ba92f887 1346static void s_nan (int);
919731af 1347static void s_module (int);
17a2f251
TS
1348static void s_mips_ent (int);
1349static void s_mips_end (int);
1350static void s_mips_frame (int);
1351static void s_mips_mask (int reg_type);
1352static void s_mips_stab (int);
1353static void s_mips_weakext (int);
1354static void s_mips_file (int);
1355static void s_mips_loc (int);
1356static bfd_boolean pic_need_relax (symbolS *, asection *);
4a6a3df4 1357static int relaxed_branch_length (fragS *, asection *, int);
df58fc94
RS
1358static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1359static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
919731af 1360static void file_mips_check_options (void);
e7af610e
NC
1361
1362/* Table and functions used to map between CPU/ISA names, and
1363 ISA levels, and CPU numbers. */
1364
e972090a
NC
1365struct mips_cpu_info
1366{
e7af610e 1367 const char *name; /* CPU or ISA name. */
d16afab6
RS
1368 int flags; /* MIPS_CPU_* flags. */
1369 int ase; /* Set of ASEs implemented by the CPU. */
e7af610e
NC
1370 int isa; /* ISA level. */
1371 int cpu; /* CPU number (default CPU if ISA). */
1372};
1373
ad3fea08 1374#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
ad3fea08 1375
17a2f251
TS
1376static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1377static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1378static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
252b5132 1379\f
c31f3936
RS
1380/* Command-line options. */
1381const char *md_shortopts = "O::g::G:";
1382
1383enum options
1384 {
1385 OPTION_MARCH = OPTION_MD_BASE,
1386 OPTION_MTUNE,
1387 OPTION_MIPS1,
1388 OPTION_MIPS2,
1389 OPTION_MIPS3,
1390 OPTION_MIPS4,
1391 OPTION_MIPS5,
1392 OPTION_MIPS32,
1393 OPTION_MIPS64,
1394 OPTION_MIPS32R2,
ae52f483
AB
1395 OPTION_MIPS32R3,
1396 OPTION_MIPS32R5,
7361da2c 1397 OPTION_MIPS32R6,
c31f3936 1398 OPTION_MIPS64R2,
ae52f483
AB
1399 OPTION_MIPS64R3,
1400 OPTION_MIPS64R5,
7361da2c 1401 OPTION_MIPS64R6,
c31f3936
RS
1402 OPTION_MIPS16,
1403 OPTION_NO_MIPS16,
1404 OPTION_MIPS3D,
1405 OPTION_NO_MIPS3D,
1406 OPTION_MDMX,
1407 OPTION_NO_MDMX,
1408 OPTION_DSP,
1409 OPTION_NO_DSP,
1410 OPTION_MT,
1411 OPTION_NO_MT,
1412 OPTION_VIRT,
1413 OPTION_NO_VIRT,
56d438b1
CF
1414 OPTION_MSA,
1415 OPTION_NO_MSA,
c31f3936
RS
1416 OPTION_SMARTMIPS,
1417 OPTION_NO_SMARTMIPS,
1418 OPTION_DSPR2,
1419 OPTION_NO_DSPR2,
8f4f9071
MF
1420 OPTION_DSPR3,
1421 OPTION_NO_DSPR3,
c31f3936
RS
1422 OPTION_EVA,
1423 OPTION_NO_EVA,
7d64c587
AB
1424 OPTION_XPA,
1425 OPTION_NO_XPA,
c31f3936
RS
1426 OPTION_MICROMIPS,
1427 OPTION_NO_MICROMIPS,
1428 OPTION_MCU,
1429 OPTION_NO_MCU,
1430 OPTION_COMPAT_ARCH_BASE,
1431 OPTION_M4650,
1432 OPTION_NO_M4650,
1433 OPTION_M4010,
1434 OPTION_NO_M4010,
1435 OPTION_M4100,
1436 OPTION_NO_M4100,
1437 OPTION_M3900,
1438 OPTION_NO_M3900,
1439 OPTION_M7000_HILO_FIX,
1440 OPTION_MNO_7000_HILO_FIX,
1441 OPTION_FIX_24K,
1442 OPTION_NO_FIX_24K,
a8d14a88
CM
1443 OPTION_FIX_RM7000,
1444 OPTION_NO_FIX_RM7000,
c31f3936
RS
1445 OPTION_FIX_LOONGSON2F_JUMP,
1446 OPTION_NO_FIX_LOONGSON2F_JUMP,
1447 OPTION_FIX_LOONGSON2F_NOP,
1448 OPTION_NO_FIX_LOONGSON2F_NOP,
1449 OPTION_FIX_VR4120,
1450 OPTION_NO_FIX_VR4120,
1451 OPTION_FIX_VR4130,
1452 OPTION_NO_FIX_VR4130,
1453 OPTION_FIX_CN63XXP1,
1454 OPTION_NO_FIX_CN63XXP1,
1455 OPTION_TRAP,
1456 OPTION_BREAK,
1457 OPTION_EB,
1458 OPTION_EL,
1459 OPTION_FP32,
1460 OPTION_GP32,
1461 OPTION_CONSTRUCT_FLOATS,
1462 OPTION_NO_CONSTRUCT_FLOATS,
1463 OPTION_FP64,
351cdf24 1464 OPTION_FPXX,
c31f3936
RS
1465 OPTION_GP64,
1466 OPTION_RELAX_BRANCH,
1467 OPTION_NO_RELAX_BRANCH,
833794fc
MR
1468 OPTION_INSN32,
1469 OPTION_NO_INSN32,
c31f3936
RS
1470 OPTION_MSHARED,
1471 OPTION_MNO_SHARED,
1472 OPTION_MSYM32,
1473 OPTION_MNO_SYM32,
1474 OPTION_SOFT_FLOAT,
1475 OPTION_HARD_FLOAT,
1476 OPTION_SINGLE_FLOAT,
1477 OPTION_DOUBLE_FLOAT,
1478 OPTION_32,
c31f3936
RS
1479 OPTION_CALL_SHARED,
1480 OPTION_CALL_NONPIC,
1481 OPTION_NON_SHARED,
1482 OPTION_XGOT,
1483 OPTION_MABI,
1484 OPTION_N32,
1485 OPTION_64,
1486 OPTION_MDEBUG,
1487 OPTION_NO_MDEBUG,
1488 OPTION_PDR,
1489 OPTION_NO_PDR,
1490 OPTION_MVXWORKS_PIC,
ba92f887 1491 OPTION_NAN,
351cdf24
MF
1492 OPTION_ODD_SPREG,
1493 OPTION_NO_ODD_SPREG,
c31f3936
RS
1494 OPTION_END_OF_ENUM
1495 };
1496
1497struct option md_longopts[] =
1498{
1499 /* Options which specify architecture. */
1500 {"march", required_argument, NULL, OPTION_MARCH},
1501 {"mtune", required_argument, NULL, OPTION_MTUNE},
1502 {"mips0", no_argument, NULL, OPTION_MIPS1},
1503 {"mips1", no_argument, NULL, OPTION_MIPS1},
1504 {"mips2", no_argument, NULL, OPTION_MIPS2},
1505 {"mips3", no_argument, NULL, OPTION_MIPS3},
1506 {"mips4", no_argument, NULL, OPTION_MIPS4},
1507 {"mips5", no_argument, NULL, OPTION_MIPS5},
1508 {"mips32", no_argument, NULL, OPTION_MIPS32},
1509 {"mips64", no_argument, NULL, OPTION_MIPS64},
1510 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
ae52f483
AB
1511 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1512 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
7361da2c 1513 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
c31f3936 1514 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
ae52f483
AB
1515 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1516 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
7361da2c 1517 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
c31f3936
RS
1518
1519 /* Options which specify Application Specific Extensions (ASEs). */
1520 {"mips16", no_argument, NULL, OPTION_MIPS16},
1521 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1522 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1523 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1524 {"mdmx", no_argument, NULL, OPTION_MDMX},
1525 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1526 {"mdsp", no_argument, NULL, OPTION_DSP},
1527 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1528 {"mmt", no_argument, NULL, OPTION_MT},
1529 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1530 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1531 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1532 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1533 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
8f4f9071
MF
1534 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1535 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
c31f3936
RS
1536 {"meva", no_argument, NULL, OPTION_EVA},
1537 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1538 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1539 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1540 {"mmcu", no_argument, NULL, OPTION_MCU},
1541 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1542 {"mvirt", no_argument, NULL, OPTION_VIRT},
1543 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
56d438b1
CF
1544 {"mmsa", no_argument, NULL, OPTION_MSA},
1545 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
7d64c587
AB
1546 {"mxpa", no_argument, NULL, OPTION_XPA},
1547 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
c31f3936
RS
1548
1549 /* Old-style architecture options. Don't add more of these. */
1550 {"m4650", no_argument, NULL, OPTION_M4650},
1551 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1552 {"m4010", no_argument, NULL, OPTION_M4010},
1553 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1554 {"m4100", no_argument, NULL, OPTION_M4100},
1555 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1556 {"m3900", no_argument, NULL, OPTION_M3900},
1557 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1558
1559 /* Options which enable bug fixes. */
1560 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1561 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1562 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1563 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1564 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1565 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1566 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1567 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1568 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1569 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1570 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1571 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1572 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
a8d14a88
CM
1573 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1574 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
c31f3936
RS
1575 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1576 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1577
1578 /* Miscellaneous options. */
1579 {"trap", no_argument, NULL, OPTION_TRAP},
1580 {"no-break", no_argument, NULL, OPTION_TRAP},
1581 {"break", no_argument, NULL, OPTION_BREAK},
1582 {"no-trap", no_argument, NULL, OPTION_BREAK},
1583 {"EB", no_argument, NULL, OPTION_EB},
1584 {"EL", no_argument, NULL, OPTION_EL},
1585 {"mfp32", no_argument, NULL, OPTION_FP32},
1586 {"mgp32", no_argument, NULL, OPTION_GP32},
1587 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1588 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1589 {"mfp64", no_argument, NULL, OPTION_FP64},
351cdf24 1590 {"mfpxx", no_argument, NULL, OPTION_FPXX},
c31f3936
RS
1591 {"mgp64", no_argument, NULL, OPTION_GP64},
1592 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1593 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
833794fc
MR
1594 {"minsn32", no_argument, NULL, OPTION_INSN32},
1595 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
c31f3936
RS
1596 {"mshared", no_argument, NULL, OPTION_MSHARED},
1597 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1598 {"msym32", no_argument, NULL, OPTION_MSYM32},
1599 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1600 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1601 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1602 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1603 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
351cdf24
MF
1604 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1605 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
c31f3936
RS
1606
1607 /* Strictly speaking this next option is ELF specific,
1608 but we allow it for other ports as well in order to
1609 make testing easier. */
1610 {"32", no_argument, NULL, OPTION_32},
1611
1612 /* ELF-specific options. */
c31f3936
RS
1613 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1614 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1615 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1616 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1617 {"xgot", no_argument, NULL, OPTION_XGOT},
1618 {"mabi", required_argument, NULL, OPTION_MABI},
1619 {"n32", no_argument, NULL, OPTION_N32},
1620 {"64", no_argument, NULL, OPTION_64},
1621 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1622 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1623 {"mpdr", no_argument, NULL, OPTION_PDR},
1624 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1625 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
ba92f887 1626 {"mnan", required_argument, NULL, OPTION_NAN},
c31f3936
RS
1627
1628 {NULL, no_argument, NULL, 0}
1629};
1630size_t md_longopts_size = sizeof (md_longopts);
1631\f
c6278170
RS
1632/* Information about either an Application Specific Extension or an
1633 optional architecture feature that, for simplicity, we treat in the
1634 same way as an ASE. */
1635struct mips_ase
1636{
1637 /* The name of the ASE, used in both the command-line and .set options. */
1638 const char *name;
1639
1640 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1641 and 64-bit architectures, the flags here refer to the subset that
1642 is available on both. */
1643 unsigned int flags;
1644
1645 /* The ASE_* flag used for instructions that are available on 64-bit
1646 architectures but that are not included in FLAGS. */
1647 unsigned int flags64;
1648
1649 /* The command-line options that turn the ASE on and off. */
1650 int option_on;
1651 int option_off;
1652
1653 /* The minimum required architecture revisions for MIPS32, MIPS64,
1654 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1655 int mips32_rev;
1656 int mips64_rev;
1657 int micromips32_rev;
1658 int micromips64_rev;
7361da2c
AB
1659
1660 /* The architecture where the ASE was removed or -1 if the extension has not
1661 been removed. */
1662 int rem_rev;
c6278170
RS
1663};
1664
1665/* A table of all supported ASEs. */
1666static const struct mips_ase mips_ases[] = {
1667 { "dsp", ASE_DSP, ASE_DSP64,
1668 OPTION_DSP, OPTION_NO_DSP,
7361da2c
AB
1669 2, 2, 2, 2,
1670 -1 },
c6278170
RS
1671
1672 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1673 OPTION_DSPR2, OPTION_NO_DSPR2,
7361da2c
AB
1674 2, 2, 2, 2,
1675 -1 },
c6278170 1676
8f4f9071
MF
1677 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1678 OPTION_DSPR3, OPTION_NO_DSPR3,
1679 6, 6, -1, -1,
1680 -1 },
1681
c6278170
RS
1682 { "eva", ASE_EVA, 0,
1683 OPTION_EVA, OPTION_NO_EVA,
7361da2c
AB
1684 2, 2, 2, 2,
1685 -1 },
c6278170
RS
1686
1687 { "mcu", ASE_MCU, 0,
1688 OPTION_MCU, OPTION_NO_MCU,
7361da2c
AB
1689 2, 2, 2, 2,
1690 -1 },
c6278170
RS
1691
1692 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1693 { "mdmx", ASE_MDMX, 0,
1694 OPTION_MDMX, OPTION_NO_MDMX,
7361da2c
AB
1695 -1, 1, -1, -1,
1696 6 },
c6278170
RS
1697
1698 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1699 { "mips3d", ASE_MIPS3D, 0,
1700 OPTION_MIPS3D, OPTION_NO_MIPS3D,
7361da2c
AB
1701 2, 1, -1, -1,
1702 6 },
c6278170
RS
1703
1704 { "mt", ASE_MT, 0,
1705 OPTION_MT, OPTION_NO_MT,
7361da2c
AB
1706 2, 2, -1, -1,
1707 -1 },
c6278170
RS
1708
1709 { "smartmips", ASE_SMARTMIPS, 0,
1710 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
7361da2c
AB
1711 1, -1, -1, -1,
1712 6 },
c6278170
RS
1713
1714 { "virt", ASE_VIRT, ASE_VIRT64,
1715 OPTION_VIRT, OPTION_NO_VIRT,
7361da2c
AB
1716 2, 2, 2, 2,
1717 -1 },
56d438b1
CF
1718
1719 { "msa", ASE_MSA, ASE_MSA64,
1720 OPTION_MSA, OPTION_NO_MSA,
7361da2c
AB
1721 2, 2, 2, 2,
1722 -1 },
7d64c587
AB
1723
1724 { "xpa", ASE_XPA, 0,
1725 OPTION_XPA, OPTION_NO_XPA,
7361da2c
AB
1726 2, 2, -1, -1,
1727 -1 },
c6278170
RS
1728};
1729
1730/* The set of ASEs that require -mfp64. */
82bda27b 1731#define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
c6278170
RS
1732
1733/* Groups of ASE_* flags that represent different revisions of an ASE. */
1734static const unsigned int mips_ase_groups[] = {
8f4f9071 1735 ASE_DSP | ASE_DSPR2 | ASE_DSPR3
c6278170
RS
1736};
1737\f
252b5132
RH
1738/* Pseudo-op table.
1739
1740 The following pseudo-ops from the Kane and Heinrich MIPS book
1741 should be defined here, but are currently unsupported: .alias,
1742 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1743
1744 The following pseudo-ops from the Kane and Heinrich MIPS book are
1745 specific to the type of debugging information being generated, and
1746 should be defined by the object format: .aent, .begin, .bend,
1747 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1748 .vreg.
1749
1750 The following pseudo-ops from the Kane and Heinrich MIPS book are
1751 not MIPS CPU specific, but are also not specific to the object file
1752 format. This file is probably the best place to define them, but
d84bcf09 1753 they are not currently supported: .asm0, .endr, .lab, .struct. */
252b5132 1754
e972090a
NC
1755static const pseudo_typeS mips_pseudo_table[] =
1756{
beae10d5 1757 /* MIPS specific pseudo-ops. */
252b5132
RH
1758 {"option", s_option, 0},
1759 {"set", s_mipsset, 0},
1760 {"rdata", s_change_sec, 'r'},
1761 {"sdata", s_change_sec, 's'},
1762 {"livereg", s_ignore, 0},
1763 {"abicalls", s_abicalls, 0},
1764 {"cpload", s_cpload, 0},
6478892d
TS
1765 {"cpsetup", s_cpsetup, 0},
1766 {"cplocal", s_cplocal, 0},
252b5132 1767 {"cprestore", s_cprestore, 0},
6478892d 1768 {"cpreturn", s_cpreturn, 0},
741d6ea8
JM
1769 {"dtprelword", s_dtprelword, 0},
1770 {"dtpreldword", s_dtpreldword, 0},
d0f13682
CLT
1771 {"tprelword", s_tprelword, 0},
1772 {"tpreldword", s_tpreldword, 0},
6478892d 1773 {"gpvalue", s_gpvalue, 0},
252b5132 1774 {"gpword", s_gpword, 0},
10181a0d 1775 {"gpdword", s_gpdword, 0},
a3f278e2 1776 {"ehword", s_ehword, 0},
252b5132
RH
1777 {"cpadd", s_cpadd, 0},
1778 {"insn", s_insn, 0},
ba92f887 1779 {"nan", s_nan, 0},
919731af 1780 {"module", s_module, 0},
252b5132 1781
beae10d5 1782 /* Relatively generic pseudo-ops that happen to be used on MIPS
252b5132 1783 chips. */
38a57ae7 1784 {"asciiz", stringer, 8 + 1},
252b5132
RH
1785 {"bss", s_change_sec, 'b'},
1786 {"err", s_err, 0},
1787 {"half", s_cons, 1},
1788 {"dword", s_cons, 3},
1789 {"weakext", s_mips_weakext, 0},
7c752c2a
TS
1790 {"origin", s_org, 0},
1791 {"repeat", s_rept, 0},
252b5132 1792
998b3c36
MR
1793 /* For MIPS this is non-standard, but we define it for consistency. */
1794 {"sbss", s_change_sec, 'B'},
1795
beae10d5 1796 /* These pseudo-ops are defined in read.c, but must be overridden
252b5132
RH
1797 here for one reason or another. */
1798 {"align", s_align, 0},
1799 {"byte", s_cons, 0},
1800 {"data", s_change_sec, 'd'},
1801 {"double", s_float_cons, 'd'},
1802 {"float", s_float_cons, 'f'},
1803 {"globl", s_mips_globl, 0},
1804 {"global", s_mips_globl, 0},
1805 {"hword", s_cons, 1},
1806 {"int", s_cons, 2},
1807 {"long", s_cons, 2},
1808 {"octa", s_cons, 4},
1809 {"quad", s_cons, 3},
cca86cc8 1810 {"section", s_change_section, 0},
252b5132
RH
1811 {"short", s_cons, 1},
1812 {"single", s_float_cons, 'f'},
754e2bb9 1813 {"stabd", s_mips_stab, 'd'},
252b5132 1814 {"stabn", s_mips_stab, 'n'},
754e2bb9 1815 {"stabs", s_mips_stab, 's'},
252b5132
RH
1816 {"text", s_change_sec, 't'},
1817 {"word", s_cons, 2},
add56521 1818
add56521 1819 { "extern", ecoff_directive_extern, 0},
add56521 1820
43841e91 1821 { NULL, NULL, 0 },
252b5132
RH
1822};
1823
e972090a
NC
1824static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1825{
beae10d5
KH
1826 /* These pseudo-ops should be defined by the object file format.
1827 However, a.out doesn't support them, so we have versions here. */
252b5132
RH
1828 {"aent", s_mips_ent, 1},
1829 {"bgnb", s_ignore, 0},
1830 {"end", s_mips_end, 0},
1831 {"endb", s_ignore, 0},
1832 {"ent", s_mips_ent, 0},
c5dd6aab 1833 {"file", s_mips_file, 0},
252b5132
RH
1834 {"fmask", s_mips_mask, 'F'},
1835 {"frame", s_mips_frame, 0},
c5dd6aab 1836 {"loc", s_mips_loc, 0},
252b5132
RH
1837 {"mask", s_mips_mask, 'R'},
1838 {"verstamp", s_ignore, 0},
43841e91 1839 { NULL, NULL, 0 },
252b5132
RH
1840};
1841
3ae8dd8d
MR
1842/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1843 purpose of the `.dc.a' internal pseudo-op. */
1844
1845int
1846mips_address_bytes (void)
1847{
919731af 1848 file_mips_check_options ();
3ae8dd8d
MR
1849 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1850}
1851
17a2f251 1852extern void pop_insert (const pseudo_typeS *);
252b5132
RH
1853
1854void
17a2f251 1855mips_pop_insert (void)
252b5132
RH
1856{
1857 pop_insert (mips_pseudo_table);
1858 if (! ECOFF_DEBUGGING)
1859 pop_insert (mips_nonecoff_pseudo_table);
1860}
1861\f
1862/* Symbols labelling the current insn. */
1863
e972090a
NC
1864struct insn_label_list
1865{
252b5132
RH
1866 struct insn_label_list *next;
1867 symbolS *label;
1868};
1869
252b5132 1870static struct insn_label_list *free_insn_labels;
742a56fe 1871#define label_list tc_segment_info_data.labels
252b5132 1872
17a2f251 1873static void mips_clear_insn_labels (void);
df58fc94
RS
1874static void mips_mark_labels (void);
1875static void mips_compressed_mark_labels (void);
252b5132
RH
1876
1877static inline void
17a2f251 1878mips_clear_insn_labels (void)
252b5132 1879{
ed9e98c2 1880 struct insn_label_list **pl;
a8dbcb85 1881 segment_info_type *si;
252b5132 1882
a8dbcb85
TS
1883 if (now_seg)
1884 {
1885 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1886 ;
3739860c 1887
a8dbcb85
TS
1888 si = seg_info (now_seg);
1889 *pl = si->label_list;
1890 si->label_list = NULL;
1891 }
252b5132 1892}
a8dbcb85 1893
df58fc94
RS
1894/* Mark instruction labels in MIPS16/microMIPS mode. */
1895
1896static inline void
1897mips_mark_labels (void)
1898{
1899 if (HAVE_CODE_COMPRESSION)
1900 mips_compressed_mark_labels ();
1901}
252b5132
RH
1902\f
1903static char *expr_end;
1904
e423441d 1905/* An expression in a macro instruction. This is set by mips_ip and
b0e6f033 1906 mips16_ip and when populated is always an O_constant. */
252b5132
RH
1907
1908static expressionS imm_expr;
252b5132 1909
77bd4346
RS
1910/* The relocatable field in an instruction and the relocs associated
1911 with it. These variables are used for instructions like LUI and
1912 JAL as well as true offsets. They are also used for address
1913 operands in macros. */
252b5132 1914
77bd4346 1915static expressionS offset_expr;
f6688943
TS
1916static bfd_reloc_code_real_type offset_reloc[3]
1917 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 1918
df58fc94
RS
1919/* This is set to the resulting size of the instruction to be produced
1920 by mips16_ip if an explicit extension is used or by mips_ip if an
1921 explicit size is supplied. */
252b5132 1922
df58fc94 1923static unsigned int forced_insn_length;
252b5132 1924
e1b47bd5
RS
1925/* True if we are assembling an instruction. All dot symbols defined during
1926 this time should be treated as code labels. */
1927
1928static bfd_boolean mips_assembling_insn;
1929
ecb4347a
DJ
1930/* The pdr segment for per procedure frame/regmask info. Not used for
1931 ECOFF debugging. */
252b5132
RH
1932
1933static segT pdr_seg;
252b5132 1934
e013f690
TS
1935/* The default target format to use. */
1936
aeffff67
RS
1937#if defined (TE_FreeBSD)
1938#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1939#elif defined (TE_TMIPS)
1940#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1941#else
1942#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1943#endif
1944
e013f690 1945const char *
17a2f251 1946mips_target_format (void)
e013f690
TS
1947{
1948 switch (OUTPUT_FLAVOR)
1949 {
e013f690 1950 case bfd_target_elf_flavour:
0a44bf69
RS
1951#ifdef TE_VXWORKS
1952 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1953 return (target_big_endian
1954 ? "elf32-bigmips-vxworks"
1955 : "elf32-littlemips-vxworks");
1956#endif
e013f690 1957 return (target_big_endian
cfe86eaa 1958 ? (HAVE_64BIT_OBJECTS
aeffff67 1959 ? ELF_TARGET ("elf64-", "big")
cfe86eaa 1960 : (HAVE_NEWABI
aeffff67
RS
1961 ? ELF_TARGET ("elf32-n", "big")
1962 : ELF_TARGET ("elf32-", "big")))
cfe86eaa 1963 : (HAVE_64BIT_OBJECTS
aeffff67 1964 ? ELF_TARGET ("elf64-", "little")
cfe86eaa 1965 : (HAVE_NEWABI
aeffff67
RS
1966 ? ELF_TARGET ("elf32-n", "little")
1967 : ELF_TARGET ("elf32-", "little"))));
e013f690
TS
1968 default:
1969 abort ();
1970 return NULL;
1971 }
1972}
1973
c6278170
RS
1974/* Return the ISA revision that is currently in use, or 0 if we are
1975 generating code for MIPS V or below. */
1976
1977static int
1978mips_isa_rev (void)
1979{
1980 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1981 return 2;
1982
ae52f483
AB
1983 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1984 return 3;
1985
1986 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
1987 return 5;
1988
7361da2c
AB
1989 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
1990 return 6;
1991
c6278170
RS
1992 /* microMIPS implies revision 2 or above. */
1993 if (mips_opts.micromips)
1994 return 2;
1995
1996 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1997 return 1;
1998
1999 return 0;
2000}
2001
2002/* Return the mask of all ASEs that are revisions of those in FLAGS. */
2003
2004static unsigned int
2005mips_ase_mask (unsigned int flags)
2006{
2007 unsigned int i;
2008
2009 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2010 if (flags & mips_ase_groups[i])
2011 flags |= mips_ase_groups[i];
2012 return flags;
2013}
2014
2015/* Check whether the current ISA supports ASE. Issue a warning if
2016 appropriate. */
2017
2018static void
2019mips_check_isa_supports_ase (const struct mips_ase *ase)
2020{
2021 const char *base;
2022 int min_rev, size;
2023 static unsigned int warned_isa;
2024 static unsigned int warned_fp32;
2025
2026 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2027 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2028 else
2029 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2030 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2031 && (warned_isa & ase->flags) != ase->flags)
2032 {
2033 warned_isa |= ase->flags;
2034 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2035 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2036 if (min_rev < 0)
1661c76c 2037 as_warn (_("the %d-bit %s architecture does not support the"
c6278170
RS
2038 " `%s' extension"), size, base, ase->name);
2039 else
1661c76c 2040 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
c6278170
RS
2041 ase->name, base, size, min_rev);
2042 }
7361da2c
AB
2043 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2044 && (warned_isa & ase->flags) != ase->flags)
2045 {
2046 warned_isa |= ase->flags;
2047 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2048 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2049 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2050 ase->name, base, size, ase->rem_rev);
2051 }
2052
c6278170 2053 if ((ase->flags & FP64_ASES)
0b35dfee 2054 && mips_opts.fp != 64
c6278170
RS
2055 && (warned_fp32 & ase->flags) != ase->flags)
2056 {
2057 warned_fp32 |= ase->flags;
1661c76c 2058 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
c6278170
RS
2059 }
2060}
2061
2062/* Check all enabled ASEs to see whether they are supported by the
2063 chosen architecture. */
2064
2065static void
2066mips_check_isa_supports_ases (void)
2067{
2068 unsigned int i, mask;
2069
2070 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2071 {
2072 mask = mips_ase_mask (mips_ases[i].flags);
2073 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2074 mips_check_isa_supports_ase (&mips_ases[i]);
2075 }
2076}
2077
2078/* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2079 that were affected. */
2080
2081static unsigned int
919731af 2082mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2083 bfd_boolean enabled_p)
c6278170
RS
2084{
2085 unsigned int mask;
2086
2087 mask = mips_ase_mask (ase->flags);
919731af 2088 opts->ase &= ~mask;
c6278170 2089 if (enabled_p)
919731af 2090 opts->ase |= ase->flags;
c6278170
RS
2091 return mask;
2092}
2093
2094/* Return the ASE called NAME, or null if none. */
2095
2096static const struct mips_ase *
2097mips_lookup_ase (const char *name)
2098{
2099 unsigned int i;
2100
2101 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2102 if (strcmp (name, mips_ases[i].name) == 0)
2103 return &mips_ases[i];
2104 return NULL;
2105}
2106
df58fc94 2107/* Return the length of a microMIPS instruction in bytes. If bits of
100b4f2e
MR
2108 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2109 otherwise it is a 32-bit instruction. */
df58fc94
RS
2110
2111static inline unsigned int
2112micromips_insn_length (const struct mips_opcode *mo)
2113{
2114 return (mo->mask >> 16) == 0 ? 2 : 4;
2115}
2116
5c04167a
RS
2117/* Return the length of MIPS16 instruction OPCODE. */
2118
2119static inline unsigned int
2120mips16_opcode_length (unsigned long opcode)
2121{
2122 return (opcode >> 16) == 0 ? 2 : 4;
2123}
2124
1e915849
RS
2125/* Return the length of instruction INSN. */
2126
2127static inline unsigned int
2128insn_length (const struct mips_cl_insn *insn)
2129{
df58fc94
RS
2130 if (mips_opts.micromips)
2131 return micromips_insn_length (insn->insn_mo);
2132 else if (mips_opts.mips16)
5c04167a 2133 return mips16_opcode_length (insn->insn_opcode);
df58fc94 2134 else
1e915849 2135 return 4;
1e915849
RS
2136}
2137
2138/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2139
2140static void
2141create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2142{
2143 size_t i;
2144
2145 insn->insn_mo = mo;
1e915849
RS
2146 insn->insn_opcode = mo->match;
2147 insn->frag = NULL;
2148 insn->where = 0;
2149 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2150 insn->fixp[i] = NULL;
2151 insn->fixed_p = (mips_opts.noreorder > 0);
2152 insn->noreorder_p = (mips_opts.noreorder > 0);
2153 insn->mips16_absolute_jump_p = 0;
15be625d 2154 insn->complete_p = 0;
e407c74b 2155 insn->cleared_p = 0;
1e915849
RS
2156}
2157
fc76e730
RS
2158/* Get a list of all the operands in INSN. */
2159
2160static const struct mips_operand_array *
2161insn_operands (const struct mips_cl_insn *insn)
2162{
2163 if (insn->insn_mo >= &mips_opcodes[0]
2164 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2165 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2166
2167 if (insn->insn_mo >= &mips16_opcodes[0]
2168 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2169 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2170
2171 if (insn->insn_mo >= &micromips_opcodes[0]
2172 && insn->insn_mo < &micromips_opcodes[bfd_micromips_num_opcodes])
2173 return &micromips_operands[insn->insn_mo - &micromips_opcodes[0]];
2174
2175 abort ();
2176}
2177
2178/* Get a description of operand OPNO of INSN. */
2179
2180static const struct mips_operand *
2181insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2182{
2183 const struct mips_operand_array *operands;
2184
2185 operands = insn_operands (insn);
2186 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2187 abort ();
2188 return operands->operand[opno];
2189}
2190
e077a1c8
RS
2191/* Install UVAL as the value of OPERAND in INSN. */
2192
2193static inline void
2194insn_insert_operand (struct mips_cl_insn *insn,
2195 const struct mips_operand *operand, unsigned int uval)
2196{
2197 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2198}
2199
fc76e730
RS
2200/* Extract the value of OPERAND from INSN. */
2201
2202static inline unsigned
2203insn_extract_operand (const struct mips_cl_insn *insn,
2204 const struct mips_operand *operand)
2205{
2206 return mips_extract_operand (operand, insn->insn_opcode);
2207}
2208
df58fc94 2209/* Record the current MIPS16/microMIPS mode in now_seg. */
742a56fe
RS
2210
2211static void
df58fc94 2212mips_record_compressed_mode (void)
742a56fe
RS
2213{
2214 segment_info_type *si;
2215
2216 si = seg_info (now_seg);
2217 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2218 si->tc_segment_info_data.mips16 = mips_opts.mips16;
df58fc94
RS
2219 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2220 si->tc_segment_info_data.micromips = mips_opts.micromips;
742a56fe
RS
2221}
2222
4d68580a
RS
2223/* Read a standard MIPS instruction from BUF. */
2224
2225static unsigned long
2226read_insn (char *buf)
2227{
2228 if (target_big_endian)
2229 return bfd_getb32 ((bfd_byte *) buf);
2230 else
2231 return bfd_getl32 ((bfd_byte *) buf);
2232}
2233
2234/* Write standard MIPS instruction INSN to BUF. Return a pointer to
2235 the next byte. */
2236
2237static char *
2238write_insn (char *buf, unsigned int insn)
2239{
2240 md_number_to_chars (buf, insn, 4);
2241 return buf + 4;
2242}
2243
2244/* Read a microMIPS or MIPS16 opcode from BUF, given that it
2245 has length LENGTH. */
2246
2247static unsigned long
2248read_compressed_insn (char *buf, unsigned int length)
2249{
2250 unsigned long insn;
2251 unsigned int i;
2252
2253 insn = 0;
2254 for (i = 0; i < length; i += 2)
2255 {
2256 insn <<= 16;
2257 if (target_big_endian)
2258 insn |= bfd_getb16 ((char *) buf);
2259 else
2260 insn |= bfd_getl16 ((char *) buf);
2261 buf += 2;
2262 }
2263 return insn;
2264}
2265
5c04167a
RS
2266/* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2267 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2268
2269static char *
2270write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2271{
2272 unsigned int i;
2273
2274 for (i = 0; i < length; i += 2)
2275 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2276 return buf + length;
2277}
2278
1e915849
RS
2279/* Install INSN at the location specified by its "frag" and "where" fields. */
2280
2281static void
2282install_insn (const struct mips_cl_insn *insn)
2283{
2284 char *f = insn->frag->fr_literal + insn->where;
5c04167a
RS
2285 if (HAVE_CODE_COMPRESSION)
2286 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1e915849 2287 else
4d68580a 2288 write_insn (f, insn->insn_opcode);
df58fc94 2289 mips_record_compressed_mode ();
1e915849
RS
2290}
2291
2292/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2293 and install the opcode in the new location. */
2294
2295static void
2296move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2297{
2298 size_t i;
2299
2300 insn->frag = frag;
2301 insn->where = where;
2302 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2303 if (insn->fixp[i] != NULL)
2304 {
2305 insn->fixp[i]->fx_frag = frag;
2306 insn->fixp[i]->fx_where = where;
2307 }
2308 install_insn (insn);
2309}
2310
2311/* Add INSN to the end of the output. */
2312
2313static void
2314add_fixed_insn (struct mips_cl_insn *insn)
2315{
2316 char *f = frag_more (insn_length (insn));
2317 move_insn (insn, frag_now, f - frag_now->fr_literal);
2318}
2319
2320/* Start a variant frag and move INSN to the start of the variant part,
2321 marking it as fixed. The other arguments are as for frag_var. */
2322
2323static void
2324add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2325 relax_substateT subtype, symbolS *symbol, offsetT offset)
2326{
2327 frag_grow (max_chars);
2328 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2329 insn->fixed_p = 1;
2330 frag_var (rs_machine_dependent, max_chars, var,
2331 subtype, symbol, offset, NULL);
2332}
2333
2334/* Insert N copies of INSN into the history buffer, starting at
2335 position FIRST. Neither FIRST nor N need to be clipped. */
2336
2337static void
2338insert_into_history (unsigned int first, unsigned int n,
2339 const struct mips_cl_insn *insn)
2340{
2341 if (mips_relax.sequence != 2)
2342 {
2343 unsigned int i;
2344
2345 for (i = ARRAY_SIZE (history); i-- > first;)
2346 if (i >= first + n)
2347 history[i] = history[i - n];
2348 else
2349 history[i] = *insn;
2350 }
2351}
2352
e3de51ce
RS
2353/* Clear the error in insn_error. */
2354
2355static void
2356clear_insn_error (void)
2357{
2358 memset (&insn_error, 0, sizeof (insn_error));
2359}
2360
2361/* Possibly record error message MSG for the current instruction.
2362 If the error is about a particular argument, ARGNUM is the 1-based
2363 number of that argument, otherwise it is 0. FORMAT is the format
2364 of MSG. Return true if MSG was used, false if the current message
2365 was kept. */
2366
2367static bfd_boolean
2368set_insn_error_format (int argnum, enum mips_insn_error_format format,
2369 const char *msg)
2370{
2371 if (argnum == 0)
2372 {
2373 /* Give priority to errors against specific arguments, and to
2374 the first whole-instruction message. */
2375 if (insn_error.msg)
2376 return FALSE;
2377 }
2378 else
2379 {
2380 /* Keep insn_error if it is against a later argument. */
2381 if (argnum < insn_error.min_argnum)
2382 return FALSE;
2383
2384 /* If both errors are against the same argument but are different,
2385 give up on reporting a specific error for this argument.
2386 See the comment about mips_insn_error for details. */
2387 if (argnum == insn_error.min_argnum
2388 && insn_error.msg
2389 && strcmp (insn_error.msg, msg) != 0)
2390 {
2391 insn_error.msg = 0;
2392 insn_error.min_argnum += 1;
2393 return FALSE;
2394 }
2395 }
2396 insn_error.min_argnum = argnum;
2397 insn_error.format = format;
2398 insn_error.msg = msg;
2399 return TRUE;
2400}
2401
2402/* Record an instruction error with no % format fields. ARGNUM and MSG are
2403 as for set_insn_error_format. */
2404
2405static void
2406set_insn_error (int argnum, const char *msg)
2407{
2408 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2409}
2410
2411/* Record an instruction error with one %d field I. ARGNUM and MSG are
2412 as for set_insn_error_format. */
2413
2414static void
2415set_insn_error_i (int argnum, const char *msg, int i)
2416{
2417 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2418 insn_error.u.i = i;
2419}
2420
2421/* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2422 are as for set_insn_error_format. */
2423
2424static void
2425set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2426{
2427 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2428 {
2429 insn_error.u.ss[0] = s1;
2430 insn_error.u.ss[1] = s2;
2431 }
2432}
2433
2434/* Report the error in insn_error, which is against assembly code STR. */
2435
2436static void
2437report_insn_error (const char *str)
2438{
e1fa0163 2439 const char *msg = concat (insn_error.msg, " `%s'", NULL);
e3de51ce 2440
e3de51ce
RS
2441 switch (insn_error.format)
2442 {
2443 case ERR_FMT_PLAIN:
2444 as_bad (msg, str);
2445 break;
2446
2447 case ERR_FMT_I:
2448 as_bad (msg, insn_error.u.i, str);
2449 break;
2450
2451 case ERR_FMT_SS:
2452 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2453 break;
2454 }
e1fa0163
NC
2455
2456 free ((char *) msg);
e3de51ce
RS
2457}
2458
71400594
RS
2459/* Initialize vr4120_conflicts. There is a bit of duplication here:
2460 the idea is to make it obvious at a glance that each errata is
2461 included. */
2462
2463static void
2464init_vr4120_conflicts (void)
2465{
2466#define CONFLICT(FIRST, SECOND) \
2467 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2468
2469 /* Errata 21 - [D]DIV[U] after [D]MACC */
2470 CONFLICT (MACC, DIV);
2471 CONFLICT (DMACC, DIV);
2472
2473 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2474 CONFLICT (DMULT, DMULT);
2475 CONFLICT (DMULT, DMACC);
2476 CONFLICT (DMACC, DMULT);
2477 CONFLICT (DMACC, DMACC);
2478
2479 /* Errata 24 - MT{LO,HI} after [D]MACC */
2480 CONFLICT (MACC, MTHILO);
2481 CONFLICT (DMACC, MTHILO);
2482
2483 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2484 instruction is executed immediately after a MACC or DMACC
2485 instruction, the result of [either instruction] is incorrect." */
2486 CONFLICT (MACC, MULT);
2487 CONFLICT (MACC, DMULT);
2488 CONFLICT (DMACC, MULT);
2489 CONFLICT (DMACC, DMULT);
2490
2491 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2492 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2493 DDIV or DDIVU instruction, the result of the MACC or
2494 DMACC instruction is incorrect.". */
2495 CONFLICT (DMULT, MACC);
2496 CONFLICT (DMULT, DMACC);
2497 CONFLICT (DIV, MACC);
2498 CONFLICT (DIV, DMACC);
2499
2500#undef CONFLICT
2501}
2502
707bfff6
TS
2503struct regname {
2504 const char *name;
2505 unsigned int num;
2506};
2507
14daeee3 2508#define RNUM_MASK 0x00000ff
56d438b1 2509#define RTYPE_MASK 0x0ffff00
14daeee3
RS
2510#define RTYPE_NUM 0x0000100
2511#define RTYPE_FPU 0x0000200
2512#define RTYPE_FCC 0x0000400
2513#define RTYPE_VEC 0x0000800
2514#define RTYPE_GP 0x0001000
2515#define RTYPE_CP0 0x0002000
2516#define RTYPE_PC 0x0004000
2517#define RTYPE_ACC 0x0008000
2518#define RTYPE_CCC 0x0010000
2519#define RTYPE_VI 0x0020000
2520#define RTYPE_VF 0x0040000
2521#define RTYPE_R5900_I 0x0080000
2522#define RTYPE_R5900_Q 0x0100000
2523#define RTYPE_R5900_R 0x0200000
2524#define RTYPE_R5900_ACC 0x0400000
56d438b1 2525#define RTYPE_MSA 0x0800000
14daeee3 2526#define RWARN 0x8000000
707bfff6
TS
2527
2528#define GENERIC_REGISTER_NUMBERS \
2529 {"$0", RTYPE_NUM | 0}, \
2530 {"$1", RTYPE_NUM | 1}, \
2531 {"$2", RTYPE_NUM | 2}, \
2532 {"$3", RTYPE_NUM | 3}, \
2533 {"$4", RTYPE_NUM | 4}, \
2534 {"$5", RTYPE_NUM | 5}, \
2535 {"$6", RTYPE_NUM | 6}, \
2536 {"$7", RTYPE_NUM | 7}, \
2537 {"$8", RTYPE_NUM | 8}, \
2538 {"$9", RTYPE_NUM | 9}, \
2539 {"$10", RTYPE_NUM | 10}, \
2540 {"$11", RTYPE_NUM | 11}, \
2541 {"$12", RTYPE_NUM | 12}, \
2542 {"$13", RTYPE_NUM | 13}, \
2543 {"$14", RTYPE_NUM | 14}, \
2544 {"$15", RTYPE_NUM | 15}, \
2545 {"$16", RTYPE_NUM | 16}, \
2546 {"$17", RTYPE_NUM | 17}, \
2547 {"$18", RTYPE_NUM | 18}, \
2548 {"$19", RTYPE_NUM | 19}, \
2549 {"$20", RTYPE_NUM | 20}, \
2550 {"$21", RTYPE_NUM | 21}, \
2551 {"$22", RTYPE_NUM | 22}, \
2552 {"$23", RTYPE_NUM | 23}, \
2553 {"$24", RTYPE_NUM | 24}, \
2554 {"$25", RTYPE_NUM | 25}, \
2555 {"$26", RTYPE_NUM | 26}, \
2556 {"$27", RTYPE_NUM | 27}, \
2557 {"$28", RTYPE_NUM | 28}, \
2558 {"$29", RTYPE_NUM | 29}, \
2559 {"$30", RTYPE_NUM | 30}, \
3739860c 2560 {"$31", RTYPE_NUM | 31}
707bfff6
TS
2561
2562#define FPU_REGISTER_NAMES \
2563 {"$f0", RTYPE_FPU | 0}, \
2564 {"$f1", RTYPE_FPU | 1}, \
2565 {"$f2", RTYPE_FPU | 2}, \
2566 {"$f3", RTYPE_FPU | 3}, \
2567 {"$f4", RTYPE_FPU | 4}, \
2568 {"$f5", RTYPE_FPU | 5}, \
2569 {"$f6", RTYPE_FPU | 6}, \
2570 {"$f7", RTYPE_FPU | 7}, \
2571 {"$f8", RTYPE_FPU | 8}, \
2572 {"$f9", RTYPE_FPU | 9}, \
2573 {"$f10", RTYPE_FPU | 10}, \
2574 {"$f11", RTYPE_FPU | 11}, \
2575 {"$f12", RTYPE_FPU | 12}, \
2576 {"$f13", RTYPE_FPU | 13}, \
2577 {"$f14", RTYPE_FPU | 14}, \
2578 {"$f15", RTYPE_FPU | 15}, \
2579 {"$f16", RTYPE_FPU | 16}, \
2580 {"$f17", RTYPE_FPU | 17}, \
2581 {"$f18", RTYPE_FPU | 18}, \
2582 {"$f19", RTYPE_FPU | 19}, \
2583 {"$f20", RTYPE_FPU | 20}, \
2584 {"$f21", RTYPE_FPU | 21}, \
2585 {"$f22", RTYPE_FPU | 22}, \
2586 {"$f23", RTYPE_FPU | 23}, \
2587 {"$f24", RTYPE_FPU | 24}, \
2588 {"$f25", RTYPE_FPU | 25}, \
2589 {"$f26", RTYPE_FPU | 26}, \
2590 {"$f27", RTYPE_FPU | 27}, \
2591 {"$f28", RTYPE_FPU | 28}, \
2592 {"$f29", RTYPE_FPU | 29}, \
2593 {"$f30", RTYPE_FPU | 30}, \
2594 {"$f31", RTYPE_FPU | 31}
2595
2596#define FPU_CONDITION_CODE_NAMES \
2597 {"$fcc0", RTYPE_FCC | 0}, \
2598 {"$fcc1", RTYPE_FCC | 1}, \
2599 {"$fcc2", RTYPE_FCC | 2}, \
2600 {"$fcc3", RTYPE_FCC | 3}, \
2601 {"$fcc4", RTYPE_FCC | 4}, \
2602 {"$fcc5", RTYPE_FCC | 5}, \
2603 {"$fcc6", RTYPE_FCC | 6}, \
2604 {"$fcc7", RTYPE_FCC | 7}
2605
2606#define COPROC_CONDITION_CODE_NAMES \
2607 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2608 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2609 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2610 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2611 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2612 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2613 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2614 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2615
2616#define N32N64_SYMBOLIC_REGISTER_NAMES \
2617 {"$a4", RTYPE_GP | 8}, \
2618 {"$a5", RTYPE_GP | 9}, \
2619 {"$a6", RTYPE_GP | 10}, \
2620 {"$a7", RTYPE_GP | 11}, \
2621 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2622 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2623 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2624 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2625 {"$t0", RTYPE_GP | 12}, \
2626 {"$t1", RTYPE_GP | 13}, \
2627 {"$t2", RTYPE_GP | 14}, \
2628 {"$t3", RTYPE_GP | 15}
2629
2630#define O32_SYMBOLIC_REGISTER_NAMES \
2631 {"$t0", RTYPE_GP | 8}, \
2632 {"$t1", RTYPE_GP | 9}, \
2633 {"$t2", RTYPE_GP | 10}, \
2634 {"$t3", RTYPE_GP | 11}, \
2635 {"$t4", RTYPE_GP | 12}, \
2636 {"$t5", RTYPE_GP | 13}, \
2637 {"$t6", RTYPE_GP | 14}, \
2638 {"$t7", RTYPE_GP | 15}, \
2639 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2640 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2641 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
3739860c 2642 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
707bfff6
TS
2643
2644/* Remaining symbolic register names */
2645#define SYMBOLIC_REGISTER_NAMES \
2646 {"$zero", RTYPE_GP | 0}, \
2647 {"$at", RTYPE_GP | 1}, \
2648 {"$AT", RTYPE_GP | 1}, \
2649 {"$v0", RTYPE_GP | 2}, \
2650 {"$v1", RTYPE_GP | 3}, \
2651 {"$a0", RTYPE_GP | 4}, \
2652 {"$a1", RTYPE_GP | 5}, \
2653 {"$a2", RTYPE_GP | 6}, \
2654 {"$a3", RTYPE_GP | 7}, \
2655 {"$s0", RTYPE_GP | 16}, \
2656 {"$s1", RTYPE_GP | 17}, \
2657 {"$s2", RTYPE_GP | 18}, \
2658 {"$s3", RTYPE_GP | 19}, \
2659 {"$s4", RTYPE_GP | 20}, \
2660 {"$s5", RTYPE_GP | 21}, \
2661 {"$s6", RTYPE_GP | 22}, \
2662 {"$s7", RTYPE_GP | 23}, \
2663 {"$t8", RTYPE_GP | 24}, \
2664 {"$t9", RTYPE_GP | 25}, \
2665 {"$k0", RTYPE_GP | 26}, \
2666 {"$kt0", RTYPE_GP | 26}, \
2667 {"$k1", RTYPE_GP | 27}, \
2668 {"$kt1", RTYPE_GP | 27}, \
2669 {"$gp", RTYPE_GP | 28}, \
2670 {"$sp", RTYPE_GP | 29}, \
2671 {"$s8", RTYPE_GP | 30}, \
2672 {"$fp", RTYPE_GP | 30}, \
2673 {"$ra", RTYPE_GP | 31}
2674
2675#define MIPS16_SPECIAL_REGISTER_NAMES \
2676 {"$pc", RTYPE_PC | 0}
2677
2678#define MDMX_VECTOR_REGISTER_NAMES \
2679 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2680 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2681 {"$v2", RTYPE_VEC | 2}, \
2682 {"$v3", RTYPE_VEC | 3}, \
2683 {"$v4", RTYPE_VEC | 4}, \
2684 {"$v5", RTYPE_VEC | 5}, \
2685 {"$v6", RTYPE_VEC | 6}, \
2686 {"$v7", RTYPE_VEC | 7}, \
2687 {"$v8", RTYPE_VEC | 8}, \
2688 {"$v9", RTYPE_VEC | 9}, \
2689 {"$v10", RTYPE_VEC | 10}, \
2690 {"$v11", RTYPE_VEC | 11}, \
2691 {"$v12", RTYPE_VEC | 12}, \
2692 {"$v13", RTYPE_VEC | 13}, \
2693 {"$v14", RTYPE_VEC | 14}, \
2694 {"$v15", RTYPE_VEC | 15}, \
2695 {"$v16", RTYPE_VEC | 16}, \
2696 {"$v17", RTYPE_VEC | 17}, \
2697 {"$v18", RTYPE_VEC | 18}, \
2698 {"$v19", RTYPE_VEC | 19}, \
2699 {"$v20", RTYPE_VEC | 20}, \
2700 {"$v21", RTYPE_VEC | 21}, \
2701 {"$v22", RTYPE_VEC | 22}, \
2702 {"$v23", RTYPE_VEC | 23}, \
2703 {"$v24", RTYPE_VEC | 24}, \
2704 {"$v25", RTYPE_VEC | 25}, \
2705 {"$v26", RTYPE_VEC | 26}, \
2706 {"$v27", RTYPE_VEC | 27}, \
2707 {"$v28", RTYPE_VEC | 28}, \
2708 {"$v29", RTYPE_VEC | 29}, \
2709 {"$v30", RTYPE_VEC | 30}, \
2710 {"$v31", RTYPE_VEC | 31}
2711
14daeee3
RS
2712#define R5900_I_NAMES \
2713 {"$I", RTYPE_R5900_I | 0}
2714
2715#define R5900_Q_NAMES \
2716 {"$Q", RTYPE_R5900_Q | 0}
2717
2718#define R5900_R_NAMES \
2719 {"$R", RTYPE_R5900_R | 0}
2720
2721#define R5900_ACC_NAMES \
2722 {"$ACC", RTYPE_R5900_ACC | 0 }
2723
707bfff6
TS
2724#define MIPS_DSP_ACCUMULATOR_NAMES \
2725 {"$ac0", RTYPE_ACC | 0}, \
2726 {"$ac1", RTYPE_ACC | 1}, \
2727 {"$ac2", RTYPE_ACC | 2}, \
2728 {"$ac3", RTYPE_ACC | 3}
2729
2730static const struct regname reg_names[] = {
2731 GENERIC_REGISTER_NUMBERS,
2732 FPU_REGISTER_NAMES,
2733 FPU_CONDITION_CODE_NAMES,
2734 COPROC_CONDITION_CODE_NAMES,
2735
2736 /* The $txx registers depends on the abi,
2737 these will be added later into the symbol table from
3739860c 2738 one of the tables below once mips_abi is set after
707bfff6
TS
2739 parsing of arguments from the command line. */
2740 SYMBOLIC_REGISTER_NAMES,
2741
2742 MIPS16_SPECIAL_REGISTER_NAMES,
2743 MDMX_VECTOR_REGISTER_NAMES,
14daeee3
RS
2744 R5900_I_NAMES,
2745 R5900_Q_NAMES,
2746 R5900_R_NAMES,
2747 R5900_ACC_NAMES,
707bfff6
TS
2748 MIPS_DSP_ACCUMULATOR_NAMES,
2749 {0, 0}
2750};
2751
2752static const struct regname reg_names_o32[] = {
2753 O32_SYMBOLIC_REGISTER_NAMES,
2754 {0, 0}
2755};
2756
2757static const struct regname reg_names_n32n64[] = {
2758 N32N64_SYMBOLIC_REGISTER_NAMES,
2759 {0, 0}
2760};
2761
a92713e6
RS
2762/* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2763 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2764 of these register symbols, return the associated vector register,
2765 otherwise return SYMVAL itself. */
df58fc94 2766
a92713e6
RS
2767static unsigned int
2768mips_prefer_vec_regno (unsigned int symval)
707bfff6 2769{
a92713e6
RS
2770 if ((symval & -2) == (RTYPE_GP | 2))
2771 return RTYPE_VEC | (symval & 1);
2772 return symval;
2773}
2774
14daeee3
RS
2775/* Return true if string [S, E) is a valid register name, storing its
2776 symbol value in *SYMVAL_PTR if so. */
a92713e6
RS
2777
2778static bfd_boolean
14daeee3 2779mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
a92713e6 2780{
707bfff6 2781 char save_c;
14daeee3 2782 symbolS *symbol;
707bfff6
TS
2783
2784 /* Terminate name. */
2785 save_c = *e;
2786 *e = '\0';
2787
a92713e6
RS
2788 /* Look up the name. */
2789 symbol = symbol_find (s);
2790 *e = save_c;
2791
2792 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2793 return FALSE;
2794
14daeee3
RS
2795 *symval_ptr = S_GET_VALUE (symbol);
2796 return TRUE;
2797}
2798
2799/* Return true if the string at *SPTR is a valid register name. Allow it
2800 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2801 is nonnull.
2802
2803 When returning true, move *SPTR past the register, store the
2804 register's symbol value in *SYMVAL_PTR and the channel mask in
2805 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2806 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2807 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2808
2809static bfd_boolean
2810mips_parse_register (char **sptr, unsigned int *symval_ptr,
2811 unsigned int *channels_ptr)
2812{
2813 char *s, *e, *m;
2814 const char *q;
2815 unsigned int channels, symval, bit;
2816
2817 /* Find end of name. */
2818 s = e = *sptr;
2819 if (is_name_beginner (*e))
2820 ++e;
2821 while (is_part_of_name (*e))
2822 ++e;
2823
2824 channels = 0;
2825 if (!mips_parse_register_1 (s, e, &symval))
2826 {
2827 if (!channels_ptr)
2828 return FALSE;
2829
2830 /* Eat characters from the end of the string that are valid
2831 channel suffixes. The preceding register must be $ACC or
2832 end with a digit, so there is no ambiguity. */
2833 bit = 1;
2834 m = e;
2835 for (q = "wzyx"; *q; q++, bit <<= 1)
2836 if (m > s && m[-1] == *q)
2837 {
2838 --m;
2839 channels |= bit;
2840 }
2841
2842 if (channels == 0
2843 || !mips_parse_register_1 (s, m, &symval)
2844 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2845 return FALSE;
2846 }
2847
a92713e6 2848 *sptr = e;
14daeee3
RS
2849 *symval_ptr = symval;
2850 if (channels_ptr)
2851 *channels_ptr = channels;
a92713e6
RS
2852 return TRUE;
2853}
2854
2855/* Check if SPTR points at a valid register specifier according to TYPES.
2856 If so, then return 1, advance S to consume the specifier and store
2857 the register's number in REGNOP, otherwise return 0. */
2858
2859static int
2860reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2861{
2862 unsigned int regno;
2863
14daeee3 2864 if (mips_parse_register (s, &regno, NULL))
707bfff6 2865 {
a92713e6
RS
2866 if (types & RTYPE_VEC)
2867 regno = mips_prefer_vec_regno (regno);
2868 if (regno & types)
2869 regno &= RNUM_MASK;
2870 else
2871 regno = ~0;
707bfff6 2872 }
a92713e6 2873 else
707bfff6 2874 {
a92713e6 2875 if (types & RWARN)
1661c76c 2876 as_warn (_("unrecognized register name `%s'"), *s);
a92713e6 2877 regno = ~0;
707bfff6 2878 }
707bfff6 2879 if (regnop)
a92713e6
RS
2880 *regnop = regno;
2881 return regno <= RNUM_MASK;
707bfff6
TS
2882}
2883
14daeee3
RS
2884/* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2885 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2886
2887static char *
2888mips_parse_vu0_channels (char *s, unsigned int *channels)
2889{
2890 unsigned int i;
2891
2892 *channels = 0;
2893 for (i = 0; i < 4; i++)
2894 if (*s == "xyzw"[i])
2895 {
2896 *channels |= 1 << (3 - i);
2897 ++s;
2898 }
2899 return s;
2900}
2901
a92713e6
RS
2902/* Token types for parsed operand lists. */
2903enum mips_operand_token_type {
2904 /* A plain register, e.g. $f2. */
2905 OT_REG,
df58fc94 2906
14daeee3
RS
2907 /* A 4-bit XYZW channel mask. */
2908 OT_CHANNELS,
2909
56d438b1
CF
2910 /* A constant vector index, e.g. [1]. */
2911 OT_INTEGER_INDEX,
2912
2913 /* A register vector index, e.g. [$2]. */
2914 OT_REG_INDEX,
df58fc94 2915
a92713e6
RS
2916 /* A continuous range of registers, e.g. $s0-$s4. */
2917 OT_REG_RANGE,
2918
2919 /* A (possibly relocated) expression. */
2920 OT_INTEGER,
2921
2922 /* A floating-point value. */
2923 OT_FLOAT,
2924
2925 /* A single character. This can be '(', ')' or ',', but '(' only appears
2926 before OT_REGs. */
2927 OT_CHAR,
2928
14daeee3
RS
2929 /* A doubled character, either "--" or "++". */
2930 OT_DOUBLE_CHAR,
2931
a92713e6
RS
2932 /* The end of the operand list. */
2933 OT_END
2934};
2935
2936/* A parsed operand token. */
2937struct mips_operand_token
2938{
2939 /* The type of token. */
2940 enum mips_operand_token_type type;
2941 union
2942 {
56d438b1 2943 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
a92713e6
RS
2944 unsigned int regno;
2945
14daeee3
RS
2946 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2947 unsigned int channels;
2948
56d438b1
CF
2949 /* The integer value of an OT_INTEGER_INDEX. */
2950 addressT index;
a92713e6
RS
2951
2952 /* The two register symbol values involved in an OT_REG_RANGE. */
2953 struct {
2954 unsigned int regno1;
2955 unsigned int regno2;
2956 } reg_range;
2957
2958 /* The value of an OT_INTEGER. The value is represented as an
2959 expression and the relocation operators that were applied to
2960 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2961 relocation operators were used. */
2962 struct {
2963 expressionS value;
2964 bfd_reloc_code_real_type relocs[3];
2965 } integer;
2966
2967 /* The binary data for an OT_FLOAT constant, and the number of bytes
2968 in the constant. */
2969 struct {
2970 unsigned char data[8];
2971 int length;
2972 } flt;
2973
14daeee3 2974 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
a92713e6
RS
2975 char ch;
2976 } u;
2977};
2978
2979/* An obstack used to construct lists of mips_operand_tokens. */
2980static struct obstack mips_operand_tokens;
2981
2982/* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2983
2984static void
2985mips_add_token (struct mips_operand_token *token,
2986 enum mips_operand_token_type type)
2987{
2988 token->type = type;
2989 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2990}
2991
2992/* Check whether S is '(' followed by a register name. Add OT_CHAR
2993 and OT_REG tokens for them if so, and return a pointer to the first
2994 unconsumed character. Return null otherwise. */
2995
2996static char *
2997mips_parse_base_start (char *s)
2998{
2999 struct mips_operand_token token;
14daeee3
RS
3000 unsigned int regno, channels;
3001 bfd_boolean decrement_p;
df58fc94 3002
a92713e6
RS
3003 if (*s != '(')
3004 return 0;
3005
3006 ++s;
3007 SKIP_SPACE_TABS (s);
14daeee3
RS
3008
3009 /* Only match "--" as part of a base expression. In other contexts "--X"
3010 is a double negative. */
3011 decrement_p = (s[0] == '-' && s[1] == '-');
3012 if (decrement_p)
3013 {
3014 s += 2;
3015 SKIP_SPACE_TABS (s);
3016 }
3017
3018 /* Allow a channel specifier because that leads to better error messages
3019 than treating something like "$vf0x++" as an expression. */
3020 if (!mips_parse_register (&s, &regno, &channels))
a92713e6
RS
3021 return 0;
3022
3023 token.u.ch = '(';
3024 mips_add_token (&token, OT_CHAR);
3025
14daeee3
RS
3026 if (decrement_p)
3027 {
3028 token.u.ch = '-';
3029 mips_add_token (&token, OT_DOUBLE_CHAR);
3030 }
3031
a92713e6
RS
3032 token.u.regno = regno;
3033 mips_add_token (&token, OT_REG);
3034
14daeee3
RS
3035 if (channels)
3036 {
3037 token.u.channels = channels;
3038 mips_add_token (&token, OT_CHANNELS);
3039 }
3040
3041 /* For consistency, only match "++" as part of base expressions too. */
3042 SKIP_SPACE_TABS (s);
3043 if (s[0] == '+' && s[1] == '+')
3044 {
3045 s += 2;
3046 token.u.ch = '+';
3047 mips_add_token (&token, OT_DOUBLE_CHAR);
3048 }
3049
a92713e6
RS
3050 return s;
3051}
3052
3053/* Parse one or more tokens from S. Return a pointer to the first
3054 unconsumed character on success. Return null if an error was found
3055 and store the error text in insn_error. FLOAT_FORMAT is as for
3056 mips_parse_arguments. */
3057
3058static char *
3059mips_parse_argument_token (char *s, char float_format)
3060{
6d4af3c2
AM
3061 char *end, *save_in;
3062 const char *err;
14daeee3 3063 unsigned int regno1, regno2, channels;
a92713e6
RS
3064 struct mips_operand_token token;
3065
3066 /* First look for "($reg", since we want to treat that as an
3067 OT_CHAR and OT_REG rather than an expression. */
3068 end = mips_parse_base_start (s);
3069 if (end)
3070 return end;
3071
3072 /* Handle other characters that end up as OT_CHARs. */
3073 if (*s == ')' || *s == ',')
3074 {
3075 token.u.ch = *s;
3076 mips_add_token (&token, OT_CHAR);
3077 ++s;
3078 return s;
3079 }
3080
3081 /* Handle tokens that start with a register. */
14daeee3 3082 if (mips_parse_register (&s, &regno1, &channels))
df58fc94 3083 {
14daeee3
RS
3084 if (channels)
3085 {
3086 /* A register and a VU0 channel suffix. */
3087 token.u.regno = regno1;
3088 mips_add_token (&token, OT_REG);
3089
3090 token.u.channels = channels;
3091 mips_add_token (&token, OT_CHANNELS);
3092 return s;
3093 }
3094
a92713e6
RS
3095 SKIP_SPACE_TABS (s);
3096 if (*s == '-')
df58fc94 3097 {
a92713e6
RS
3098 /* A register range. */
3099 ++s;
3100 SKIP_SPACE_TABS (s);
14daeee3 3101 if (!mips_parse_register (&s, &regno2, NULL))
a92713e6 3102 {
1661c76c 3103 set_insn_error (0, _("invalid register range"));
a92713e6
RS
3104 return 0;
3105 }
df58fc94 3106
a92713e6
RS
3107 token.u.reg_range.regno1 = regno1;
3108 token.u.reg_range.regno2 = regno2;
3109 mips_add_token (&token, OT_REG_RANGE);
3110 return s;
3111 }
a92713e6 3112
56d438b1
CF
3113 /* Add the register itself. */
3114 token.u.regno = regno1;
3115 mips_add_token (&token, OT_REG);
3116
3117 /* Check for a vector index. */
3118 if (*s == '[')
3119 {
a92713e6
RS
3120 ++s;
3121 SKIP_SPACE_TABS (s);
56d438b1
CF
3122 if (mips_parse_register (&s, &token.u.regno, NULL))
3123 mips_add_token (&token, OT_REG_INDEX);
3124 else
a92713e6 3125 {
56d438b1
CF
3126 expressionS element;
3127
3128 my_getExpression (&element, s);
3129 if (element.X_op != O_constant)
3130 {
3131 set_insn_error (0, _("vector element must be constant"));
3132 return 0;
3133 }
3134 s = expr_end;
3135 token.u.index = element.X_add_number;
3136 mips_add_token (&token, OT_INTEGER_INDEX);
a92713e6 3137 }
a92713e6
RS
3138 SKIP_SPACE_TABS (s);
3139 if (*s != ']')
3140 {
1661c76c 3141 set_insn_error (0, _("missing `]'"));
a92713e6
RS
3142 return 0;
3143 }
3144 ++s;
df58fc94 3145 }
a92713e6 3146 return s;
df58fc94
RS
3147 }
3148
a92713e6
RS
3149 if (float_format)
3150 {
3151 /* First try to treat expressions as floats. */
3152 save_in = input_line_pointer;
3153 input_line_pointer = s;
3154 err = md_atof (float_format, (char *) token.u.flt.data,
3155 &token.u.flt.length);
3156 end = input_line_pointer;
3157 input_line_pointer = save_in;
3158 if (err && *err)
3159 {
e3de51ce 3160 set_insn_error (0, err);
a92713e6
RS
3161 return 0;
3162 }
3163 if (s != end)
3164 {
3165 mips_add_token (&token, OT_FLOAT);
3166 return end;
3167 }
3168 }
3169
3170 /* Treat everything else as an integer expression. */
3171 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3172 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3173 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3174 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3175 s = expr_end;
3176 mips_add_token (&token, OT_INTEGER);
3177 return s;
3178}
3179
3180/* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3181 if expressions should be treated as 32-bit floating-point constants,
3182 'd' if they should be treated as 64-bit floating-point constants,
3183 or 0 if they should be treated as integer expressions (the usual case).
3184
3185 Return a list of tokens on success, otherwise return 0. The caller
3186 must obstack_free the list after use. */
3187
3188static struct mips_operand_token *
3189mips_parse_arguments (char *s, char float_format)
3190{
3191 struct mips_operand_token token;
3192
3193 SKIP_SPACE_TABS (s);
3194 while (*s)
3195 {
3196 s = mips_parse_argument_token (s, float_format);
3197 if (!s)
3198 {
3199 obstack_free (&mips_operand_tokens,
3200 obstack_finish (&mips_operand_tokens));
3201 return 0;
3202 }
3203 SKIP_SPACE_TABS (s);
3204 }
3205 mips_add_token (&token, OT_END);
3206 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
df58fc94
RS
3207}
3208
d301a56b
RS
3209/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3210 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
037b32b9
AN
3211
3212static bfd_boolean
f79e2745 3213is_opcode_valid (const struct mips_opcode *mo)
037b32b9
AN
3214{
3215 int isa = mips_opts.isa;
846ef2d0 3216 int ase = mips_opts.ase;
037b32b9 3217 int fp_s, fp_d;
c6278170 3218 unsigned int i;
037b32b9 3219
c6278170
RS
3220 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3221 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3222 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3223 ase |= mips_ases[i].flags64;
037b32b9 3224
d301a56b 3225 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
037b32b9
AN
3226 return FALSE;
3227
3228 /* Check whether the instruction or macro requires single-precision or
3229 double-precision floating-point support. Note that this information is
3230 stored differently in the opcode table for insns and macros. */
3231 if (mo->pinfo == INSN_MACRO)
3232 {
3233 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3234 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3235 }
3236 else
3237 {
3238 fp_s = mo->pinfo & FP_S;
3239 fp_d = mo->pinfo & FP_D;
3240 }
3241
3242 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3243 return FALSE;
3244
3245 if (fp_s && mips_opts.soft_float)
3246 return FALSE;
3247
3248 return TRUE;
3249}
3250
3251/* Return TRUE if the MIPS16 opcode MO is valid on the currently
3252 selected ISA and architecture. */
3253
3254static bfd_boolean
3255is_opcode_valid_16 (const struct mips_opcode *mo)
3256{
d301a56b 3257 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
037b32b9
AN
3258}
3259
df58fc94
RS
3260/* Return TRUE if the size of the microMIPS opcode MO matches one
3261 explicitly requested. Always TRUE in the standard MIPS mode. */
3262
3263static bfd_boolean
3264is_size_valid (const struct mips_opcode *mo)
3265{
3266 if (!mips_opts.micromips)
3267 return TRUE;
3268
833794fc
MR
3269 if (mips_opts.insn32)
3270 {
3271 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3272 return FALSE;
3273 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3274 return FALSE;
3275 }
df58fc94
RS
3276 if (!forced_insn_length)
3277 return TRUE;
3278 if (mo->pinfo == INSN_MACRO)
3279 return FALSE;
3280 return forced_insn_length == micromips_insn_length (mo);
3281}
3282
3283/* Return TRUE if the microMIPS opcode MO is valid for the delay slot
e64af278
MR
3284 of the preceding instruction. Always TRUE in the standard MIPS mode.
3285
3286 We don't accept macros in 16-bit delay slots to avoid a case where
3287 a macro expansion fails because it relies on a preceding 32-bit real
3288 instruction to have matched and does not handle the operands correctly.
3289 The only macros that may expand to 16-bit instructions are JAL that
3290 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3291 and BGT (that likewise cannot be placed in a delay slot) that decay to
3292 a NOP. In all these cases the macros precede any corresponding real
3293 instruction definitions in the opcode table, so they will match in the
3294 second pass where the size of the delay slot is ignored and therefore
3295 produce correct code. */
df58fc94
RS
3296
3297static bfd_boolean
3298is_delay_slot_valid (const struct mips_opcode *mo)
3299{
3300 if (!mips_opts.micromips)
3301 return TRUE;
3302
3303 if (mo->pinfo == INSN_MACRO)
c06dec14 3304 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
df58fc94
RS
3305 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3306 && micromips_insn_length (mo) != 4)
3307 return FALSE;
3308 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3309 && micromips_insn_length (mo) != 2)
3310 return FALSE;
3311
3312 return TRUE;
3313}
3314
fc76e730
RS
3315/* For consistency checking, verify that all bits of OPCODE are specified
3316 either by the match/mask part of the instruction definition, or by the
3317 operand list. Also build up a list of operands in OPERANDS.
3318
3319 INSN_BITS says which bits of the instruction are significant.
3320 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3321 provides the mips_operand description of each operand. DECODE_OPERAND
3322 is null for MIPS16 instructions. */
ab902481
RS
3323
3324static int
3325validate_mips_insn (const struct mips_opcode *opcode,
3326 unsigned long insn_bits,
fc76e730
RS
3327 const struct mips_operand *(*decode_operand) (const char *),
3328 struct mips_operand_array *operands)
ab902481
RS
3329{
3330 const char *s;
fc76e730 3331 unsigned long used_bits, doubled, undefined, opno, mask;
ab902481
RS
3332 const struct mips_operand *operand;
3333
fc76e730
RS
3334 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3335 if ((mask & opcode->match) != opcode->match)
ab902481
RS
3336 {
3337 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3338 opcode->name, opcode->args);
3339 return 0;
3340 }
3341 used_bits = 0;
fc76e730 3342 opno = 0;
14daeee3
RS
3343 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3344 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
ab902481
RS
3345 for (s = opcode->args; *s; ++s)
3346 switch (*s)
3347 {
3348 case ',':
3349 case '(':
3350 case ')':
3351 break;
3352
14daeee3
RS
3353 case '#':
3354 s++;
3355 break;
3356
ab902481 3357 default:
fc76e730
RS
3358 if (!decode_operand)
3359 operand = decode_mips16_operand (*s, FALSE);
3360 else
3361 operand = decode_operand (s);
3362 if (!operand && opcode->pinfo != INSN_MACRO)
ab902481
RS
3363 {
3364 as_bad (_("internal: unknown operand type: %s %s"),
3365 opcode->name, opcode->args);
3366 return 0;
3367 }
fc76e730
RS
3368 gas_assert (opno < MAX_OPERANDS);
3369 operands->operand[opno] = operand;
14daeee3 3370 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
fc76e730 3371 {
14daeee3 3372 used_bits = mips_insert_operand (operand, used_bits, -1);
fc76e730
RS
3373 if (operand->type == OP_MDMX_IMM_REG)
3374 /* Bit 5 is the format selector (OB vs QH). The opcode table
3375 has separate entries for each format. */
3376 used_bits &= ~(1 << (operand->lsb + 5));
3377 if (operand->type == OP_ENTRY_EXIT_LIST)
3378 used_bits &= ~(mask & 0x700);
3379 }
ab902481 3380 /* Skip prefix characters. */
7361da2c 3381 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
ab902481 3382 ++s;
fc76e730 3383 opno += 1;
ab902481
RS
3384 break;
3385 }
fc76e730 3386 doubled = used_bits & mask & insn_bits;
ab902481
RS
3387 if (doubled)
3388 {
3389 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3390 " %s %s"), doubled, opcode->name, opcode->args);
3391 return 0;
3392 }
fc76e730 3393 used_bits |= mask;
ab902481 3394 undefined = ~used_bits & insn_bits;
fc76e730 3395 if (opcode->pinfo != INSN_MACRO && undefined)
ab902481
RS
3396 {
3397 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3398 undefined, opcode->name, opcode->args);
3399 return 0;
3400 }
3401 used_bits &= ~insn_bits;
3402 if (used_bits)
3403 {
3404 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3405 used_bits, opcode->name, opcode->args);
3406 return 0;
3407 }
3408 return 1;
3409}
3410
fc76e730
RS
3411/* The MIPS16 version of validate_mips_insn. */
3412
3413static int
3414validate_mips16_insn (const struct mips_opcode *opcode,
3415 struct mips_operand_array *operands)
3416{
3417 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3418 {
3419 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3420 instruction. Use TMP to describe the full instruction. */
3421 struct mips_opcode tmp;
3422
3423 tmp = *opcode;
3424 tmp.match <<= 16;
3425 tmp.mask <<= 16;
3426 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3427 }
3428 return validate_mips_insn (opcode, 0xffff, 0, operands);
3429}
3430
ab902481
RS
3431/* The microMIPS version of validate_mips_insn. */
3432
3433static int
fc76e730
RS
3434validate_micromips_insn (const struct mips_opcode *opc,
3435 struct mips_operand_array *operands)
ab902481
RS
3436{
3437 unsigned long insn_bits;
3438 unsigned long major;
3439 unsigned int length;
3440
fc76e730
RS
3441 if (opc->pinfo == INSN_MACRO)
3442 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3443 operands);
3444
ab902481
RS
3445 length = micromips_insn_length (opc);
3446 if (length != 2 && length != 4)
3447 {
1661c76c 3448 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
ab902481
RS
3449 "%s %s"), length, opc->name, opc->args);
3450 return 0;
3451 }
3452 major = opc->match >> (10 + 8 * (length - 2));
3453 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3454 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3455 {
1661c76c 3456 as_bad (_("internal error: bad microMIPS opcode "
ab902481
RS
3457 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3458 return 0;
3459 }
3460
3461 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3462 insn_bits = 1 << 4 * length;
3463 insn_bits <<= 4 * length;
3464 insn_bits -= 1;
fc76e730
RS
3465 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3466 operands);
ab902481
RS
3467}
3468
707bfff6
TS
3469/* This function is called once, at assembler startup time. It should set up
3470 all the tables, etc. that the MD part of the assembler will need. */
156c2f8b 3471
252b5132 3472void
17a2f251 3473md_begin (void)
252b5132 3474{
3994f87e 3475 const char *retval = NULL;
156c2f8b 3476 int i = 0;
252b5132 3477 int broken = 0;
1f25f5d3 3478
0a44bf69
RS
3479 if (mips_pic != NO_PIC)
3480 {
3481 if (g_switch_seen && g_switch_value != 0)
3482 as_bad (_("-G may not be used in position-independent code"));
3483 g_switch_value = 0;
3484 }
00acd688
CM
3485 else if (mips_abicalls)
3486 {
3487 if (g_switch_seen && g_switch_value != 0)
3488 as_bad (_("-G may not be used with abicalls"));
3489 g_switch_value = 0;
3490 }
0a44bf69 3491
0b35dfee 3492 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
1661c76c 3493 as_warn (_("could not set architecture and machine"));
252b5132 3494
252b5132
RH
3495 op_hash = hash_new ();
3496
fc76e730 3497 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
252b5132
RH
3498 for (i = 0; i < NUMOPCODES;)
3499 {
3500 const char *name = mips_opcodes[i].name;
3501
17a2f251 3502 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
252b5132
RH
3503 if (retval != NULL)
3504 {
3505 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3506 mips_opcodes[i].name, retval);
3507 /* Probably a memory allocation problem? Give up now. */
1661c76c 3508 as_fatal (_("broken assembler, no assembly attempted"));
252b5132
RH
3509 }
3510 do
3511 {
fc76e730
RS
3512 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3513 decode_mips_operand, &mips_operands[i]))
3514 broken = 1;
3515 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
252b5132 3516 {
fc76e730
RS
3517 create_insn (&nop_insn, mips_opcodes + i);
3518 if (mips_fix_loongson2f_nop)
3519 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3520 nop_insn.fixed_p = 1;
252b5132
RH
3521 }
3522 ++i;
3523 }
3524 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3525 }
3526
3527 mips16_op_hash = hash_new ();
fc76e730
RS
3528 mips16_operands = XCNEWVEC (struct mips_operand_array,
3529 bfd_mips16_num_opcodes);
252b5132
RH
3530
3531 i = 0;
3532 while (i < bfd_mips16_num_opcodes)
3533 {
3534 const char *name = mips16_opcodes[i].name;
3535
17a2f251 3536 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
252b5132
RH
3537 if (retval != NULL)
3538 as_fatal (_("internal: can't hash `%s': %s"),
3539 mips16_opcodes[i].name, retval);
3540 do
3541 {
fc76e730
RS
3542 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3543 broken = 1;
1e915849
RS
3544 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3545 {
3546 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3547 mips16_nop_insn.fixed_p = 1;
3548 }
252b5132
RH
3549 ++i;
3550 }
3551 while (i < bfd_mips16_num_opcodes
3552 && strcmp (mips16_opcodes[i].name, name) == 0);
3553 }
3554
df58fc94 3555 micromips_op_hash = hash_new ();
fc76e730
RS
3556 micromips_operands = XCNEWVEC (struct mips_operand_array,
3557 bfd_micromips_num_opcodes);
df58fc94
RS
3558
3559 i = 0;
3560 while (i < bfd_micromips_num_opcodes)
3561 {
3562 const char *name = micromips_opcodes[i].name;
3563
3564 retval = hash_insert (micromips_op_hash, name,
3565 (void *) &micromips_opcodes[i]);
3566 if (retval != NULL)
3567 as_fatal (_("internal: can't hash `%s': %s"),
3568 micromips_opcodes[i].name, retval);
3569 do
fc76e730
RS
3570 {
3571 struct mips_cl_insn *micromips_nop_insn;
3572
3573 if (!validate_micromips_insn (&micromips_opcodes[i],
3574 &micromips_operands[i]))
3575 broken = 1;
3576
3577 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3578 {
3579 if (micromips_insn_length (micromips_opcodes + i) == 2)
3580 micromips_nop_insn = &micromips_nop16_insn;
3581 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3582 micromips_nop_insn = &micromips_nop32_insn;
3583 else
3584 continue;
3585
3586 if (micromips_nop_insn->insn_mo == NULL
3587 && strcmp (name, "nop") == 0)
3588 {
3589 create_insn (micromips_nop_insn, micromips_opcodes + i);
3590 micromips_nop_insn->fixed_p = 1;
3591 }
3592 }
3593 }
df58fc94
RS
3594 while (++i < bfd_micromips_num_opcodes
3595 && strcmp (micromips_opcodes[i].name, name) == 0);
3596 }
3597
252b5132 3598 if (broken)
1661c76c 3599 as_fatal (_("broken assembler, no assembly attempted"));
252b5132
RH
3600
3601 /* We add all the general register names to the symbol table. This
3602 helps us detect invalid uses of them. */
3739860c 3603 for (i = 0; reg_names[i].name; i++)
707bfff6 3604 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
8fc4ee9b 3605 reg_names[i].num, /* & RNUM_MASK, */
707bfff6
TS
3606 &zero_address_frag));
3607 if (HAVE_NEWABI)
3739860c 3608 for (i = 0; reg_names_n32n64[i].name; i++)
707bfff6 3609 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
8fc4ee9b 3610 reg_names_n32n64[i].num, /* & RNUM_MASK, */
252b5132 3611 &zero_address_frag));
707bfff6 3612 else
3739860c 3613 for (i = 0; reg_names_o32[i].name; i++)
707bfff6 3614 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
8fc4ee9b 3615 reg_names_o32[i].num, /* & RNUM_MASK, */
6047c971 3616 &zero_address_frag));
6047c971 3617
14daeee3
RS
3618 for (i = 0; i < 32; i++)
3619 {
92fce9bd 3620 char regname[6];
14daeee3
RS
3621
3622 /* R5900 VU0 floating-point register. */
92fce9bd 3623 sprintf (regname, "$vf%d", i);
14daeee3
RS
3624 symbol_table_insert (symbol_new (regname, reg_section,
3625 RTYPE_VF | i, &zero_address_frag));
3626
3627 /* R5900 VU0 integer register. */
92fce9bd 3628 sprintf (regname, "$vi%d", i);
14daeee3
RS
3629 symbol_table_insert (symbol_new (regname, reg_section,
3630 RTYPE_VI | i, &zero_address_frag));
3631
56d438b1 3632 /* MSA register. */
92fce9bd 3633 sprintf (regname, "$w%d", i);
56d438b1
CF
3634 symbol_table_insert (symbol_new (regname, reg_section,
3635 RTYPE_MSA | i, &zero_address_frag));
14daeee3
RS
3636 }
3637
a92713e6
RS
3638 obstack_init (&mips_operand_tokens);
3639
7d10b47d 3640 mips_no_prev_insn ();
252b5132
RH
3641
3642 mips_gprmask = 0;
3643 mips_cprmask[0] = 0;
3644 mips_cprmask[1] = 0;
3645 mips_cprmask[2] = 0;
3646 mips_cprmask[3] = 0;
3647
3648 /* set the default alignment for the text section (2**2) */
3649 record_alignment (text_section, 2);
3650
4d0d148d 3651 bfd_set_gp_size (stdoutput, g_switch_value);
252b5132 3652
f3ded42a
RS
3653 /* On a native system other than VxWorks, sections must be aligned
3654 to 16 byte boundaries. When configured for an embedded ELF
3655 target, we don't bother. */
3656 if (strncmp (TARGET_OS, "elf", 3) != 0
3657 && strncmp (TARGET_OS, "vxworks", 7) != 0)
252b5132 3658 {
f3ded42a
RS
3659 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3660 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3661 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3662 }
252b5132 3663
f3ded42a
RS
3664 /* Create a .reginfo section for register masks and a .mdebug
3665 section for debugging information. */
3666 {
3667 segT seg;
3668 subsegT subseg;
3669 flagword flags;
3670 segT sec;
3671
3672 seg = now_seg;
3673 subseg = now_subseg;
3674
3675 /* The ABI says this section should be loaded so that the
3676 running program can access it. However, we don't load it
3677 if we are configured for an embedded target */
3678 flags = SEC_READONLY | SEC_DATA;
3679 if (strncmp (TARGET_OS, "elf", 3) != 0)
3680 flags |= SEC_ALLOC | SEC_LOAD;
3681
3682 if (mips_abi != N64_ABI)
252b5132 3683 {
f3ded42a 3684 sec = subseg_new (".reginfo", (subsegT) 0);
bdaaa2e1 3685
f3ded42a
RS
3686 bfd_set_section_flags (stdoutput, sec, flags);
3687 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
252b5132 3688
f3ded42a
RS
3689 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3690 }
3691 else
3692 {
3693 /* The 64-bit ABI uses a .MIPS.options section rather than
3694 .reginfo section. */
3695 sec = subseg_new (".MIPS.options", (subsegT) 0);
3696 bfd_set_section_flags (stdoutput, sec, flags);
3697 bfd_set_section_alignment (stdoutput, sec, 3);
252b5132 3698
f3ded42a
RS
3699 /* Set up the option header. */
3700 {
3701 Elf_Internal_Options opthdr;
3702 char *f;
3703
3704 opthdr.kind = ODK_REGINFO;
3705 opthdr.size = (sizeof (Elf_External_Options)
3706 + sizeof (Elf64_External_RegInfo));
3707 opthdr.section = 0;
3708 opthdr.info = 0;
3709 f = frag_more (sizeof (Elf_External_Options));
3710 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3711 (Elf_External_Options *) f);
3712
3713 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3714 }
3715 }
252b5132 3716
351cdf24
MF
3717 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3718 bfd_set_section_flags (stdoutput, sec,
3719 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3720 bfd_set_section_alignment (stdoutput, sec, 3);
3721 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3722
f3ded42a
RS
3723 if (ECOFF_DEBUGGING)
3724 {
3725 sec = subseg_new (".mdebug", (subsegT) 0);
3726 (void) bfd_set_section_flags (stdoutput, sec,
3727 SEC_HAS_CONTENTS | SEC_READONLY);
3728 (void) bfd_set_section_alignment (stdoutput, sec, 2);
252b5132 3729 }
f3ded42a
RS
3730 else if (mips_flag_pdr)
3731 {
3732 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3733 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3734 SEC_READONLY | SEC_RELOC
3735 | SEC_DEBUGGING);
3736 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3737 }
3738
3739 subseg_set (seg, subseg);
3740 }
252b5132 3741
71400594
RS
3742 if (mips_fix_vr4120)
3743 init_vr4120_conflicts ();
252b5132
RH
3744}
3745
351cdf24
MF
3746static inline void
3747fpabi_incompatible_with (int fpabi, const char *what)
3748{
3749 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3750 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3751}
3752
3753static inline void
3754fpabi_requires (int fpabi, const char *what)
3755{
3756 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3757 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3758}
3759
3760/* Check -mabi and register sizes against the specified FP ABI. */
3761static void
3762check_fpabi (int fpabi)
3763{
351cdf24
MF
3764 switch (fpabi)
3765 {
3766 case Val_GNU_MIPS_ABI_FP_DOUBLE:
ea79f94a
MF
3767 if (file_mips_opts.soft_float)
3768 fpabi_incompatible_with (fpabi, "softfloat");
3769 else if (file_mips_opts.single_float)
3770 fpabi_incompatible_with (fpabi, "singlefloat");
351cdf24
MF
3771 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3772 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3773 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3774 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
351cdf24
MF
3775 break;
3776
3777 case Val_GNU_MIPS_ABI_FP_XX:
3778 if (mips_abi != O32_ABI)
3779 fpabi_requires (fpabi, "-mabi=32");
ea79f94a
MF
3780 else if (file_mips_opts.soft_float)
3781 fpabi_incompatible_with (fpabi, "softfloat");
3782 else if (file_mips_opts.single_float)
3783 fpabi_incompatible_with (fpabi, "singlefloat");
351cdf24
MF
3784 else if (file_mips_opts.fp != 0)
3785 fpabi_requires (fpabi, "fp=xx");
351cdf24
MF
3786 break;
3787
3788 case Val_GNU_MIPS_ABI_FP_64A:
3789 case Val_GNU_MIPS_ABI_FP_64:
3790 if (mips_abi != O32_ABI)
3791 fpabi_requires (fpabi, "-mabi=32");
ea79f94a
MF
3792 else if (file_mips_opts.soft_float)
3793 fpabi_incompatible_with (fpabi, "softfloat");
3794 else if (file_mips_opts.single_float)
3795 fpabi_incompatible_with (fpabi, "singlefloat");
351cdf24
MF
3796 else if (file_mips_opts.fp != 64)
3797 fpabi_requires (fpabi, "fp=64");
3798 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3799 fpabi_incompatible_with (fpabi, "nooddspreg");
3800 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3801 fpabi_requires (fpabi, "nooddspreg");
351cdf24
MF
3802 break;
3803
3804 case Val_GNU_MIPS_ABI_FP_SINGLE:
3805 if (file_mips_opts.soft_float)
3806 fpabi_incompatible_with (fpabi, "softfloat");
3807 else if (!file_mips_opts.single_float)
3808 fpabi_requires (fpabi, "singlefloat");
3809 break;
3810
3811 case Val_GNU_MIPS_ABI_FP_SOFT:
3812 if (!file_mips_opts.soft_float)
3813 fpabi_requires (fpabi, "softfloat");
3814 break;
3815
3816 case Val_GNU_MIPS_ABI_FP_OLD_64:
3817 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3818 Tag_GNU_MIPS_ABI_FP, fpabi);
3819 break;
3820
3350cc01
CM
3821 case Val_GNU_MIPS_ABI_FP_NAN2008:
3822 /* Silently ignore compatibility value. */
3823 break;
3824
351cdf24
MF
3825 default:
3826 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3827 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3828 break;
3829 }
351cdf24
MF
3830}
3831
919731af 3832/* Perform consistency checks on the current options. */
3833
3834static void
3835mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3836{
3837 /* Check the size of integer registers agrees with the ABI and ISA. */
3838 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3839 as_bad (_("`gp=64' used with a 32-bit processor"));
3840 else if (abi_checks
3841 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3842 as_bad (_("`gp=32' used with a 64-bit ABI"));
3843 else if (abi_checks
3844 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3845 as_bad (_("`gp=64' used with a 32-bit ABI"));
3846
3847 /* Check the size of the float registers agrees with the ABI and ISA. */
3848 switch (opts->fp)
3849 {
351cdf24
MF
3850 case 0:
3851 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3852 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3853 else if (opts->single_float == 1)
3854 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3855 break;
919731af 3856 case 64:
3857 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3858 as_bad (_("`fp=64' used with a 32-bit fpu"));
3859 else if (abi_checks
3860 && ABI_NEEDS_32BIT_REGS (mips_abi)
3861 && !ISA_HAS_MXHC1 (opts->isa))
3862 as_warn (_("`fp=64' used with a 32-bit ABI"));
3863 break;
3864 case 32:
3865 if (abi_checks
3866 && ABI_NEEDS_64BIT_REGS (mips_abi))
3867 as_warn (_("`fp=32' used with a 64-bit ABI"));
5f4678bb 3868 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
7361da2c 3869 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
919731af 3870 break;
3871 default:
3872 as_bad (_("Unknown size of floating point registers"));
3873 break;
3874 }
3875
351cdf24
MF
3876 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3877 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3878
919731af 3879 if (opts->micromips == 1 && opts->mips16 == 1)
1357373c 3880 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
5f4678bb 3881 else if (ISA_IS_R6 (opts->isa)
7361da2c
AB
3882 && (opts->micromips == 1
3883 || opts->mips16 == 1))
1357373c 3884 as_fatal (_("`%s' cannot be used with `%s'"),
7361da2c 3885 opts->micromips ? "micromips" : "mips16",
5f4678bb 3886 mips_cpu_info_from_isa (opts->isa)->name);
7361da2c
AB
3887
3888 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3889 as_fatal (_("branch relaxation is not supported in `%s'"),
3890 mips_cpu_info_from_isa (opts->isa)->name);
919731af 3891}
3892
3893/* Perform consistency checks on the module level options exactly once.
3894 This is a deferred check that happens:
3895 at the first .set directive
3896 or, at the first pseudo op that generates code (inc .dc.a)
3897 or, at the first instruction
3898 or, at the end. */
3899
3900static void
3901file_mips_check_options (void)
3902{
3903 const struct mips_cpu_info *arch_info = 0;
3904
3905 if (file_mips_opts_checked)
3906 return;
3907
3908 /* The following code determines the register size.
3909 Similar code was added to GCC 3.3 (see override_options() in
3910 config/mips/mips.c). The GAS and GCC code should be kept in sync
3911 as much as possible. */
3912
3913 if (file_mips_opts.gp < 0)
3914 {
3915 /* Infer the integer register size from the ABI and processor.
3916 Restrict ourselves to 32-bit registers if that's all the
3917 processor has, or if the ABI cannot handle 64-bit registers. */
3918 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
3919 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3920 ? 32 : 64;
3921 }
3922
3923 if (file_mips_opts.fp < 0)
3924 {
3925 /* No user specified float register size.
3926 ??? GAS treats single-float processors as though they had 64-bit
3927 float registers (although it complains when double-precision
3928 instructions are used). As things stand, saying they have 32-bit
3929 registers would lead to spurious "register must be even" messages.
3930 So here we assume float registers are never smaller than the
3931 integer ones. */
3932 if (file_mips_opts.gp == 64)
3933 /* 64-bit integer registers implies 64-bit float registers. */
3934 file_mips_opts.fp = 64;
3935 else if ((file_mips_opts.ase & FP64_ASES)
3936 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3937 /* Handle ASEs that require 64-bit float registers, if possible. */
3938 file_mips_opts.fp = 64;
7361da2c
AB
3939 else if (ISA_IS_R6 (mips_opts.isa))
3940 /* R6 implies 64-bit float registers. */
3941 file_mips_opts.fp = 64;
919731af 3942 else
3943 /* 32-bit float registers. */
3944 file_mips_opts.fp = 32;
3945 }
3946
3947 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
3948
351cdf24
MF
3949 /* Disable operations on odd-numbered floating-point registers by default
3950 when using the FPXX ABI. */
3951 if (file_mips_opts.oddspreg < 0)
3952 {
3953 if (file_mips_opts.fp == 0)
3954 file_mips_opts.oddspreg = 0;
3955 else
3956 file_mips_opts.oddspreg = 1;
3957 }
3958
919731af 3959 /* End of GCC-shared inference code. */
3960
3961 /* This flag is set when we have a 64-bit capable CPU but use only
3962 32-bit wide registers. Note that EABI does not use it. */
3963 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3964 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
3965 || mips_abi == O32_ABI))
3966 mips_32bitmode = 1;
3967
3968 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3969 as_bad (_("trap exception not supported at ISA 1"));
3970
3971 /* If the selected architecture includes support for ASEs, enable
3972 generation of code for them. */
3973 if (file_mips_opts.mips16 == -1)
3974 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
3975 if (file_mips_opts.micromips == -1)
3976 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
3977 ? 1 : 0;
3978
7361da2c
AB
3979 if (mips_nan2008 == -1)
3980 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
3981 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
3982 as_fatal (_("`%s' does not support legacy NaN"),
3983 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
3984
919731af 3985 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3986 being selected implicitly. */
3987 if (file_mips_opts.fp != 64)
3988 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
3989
3990 /* If the user didn't explicitly select or deselect a particular ASE,
3991 use the default setting for the CPU. */
3992 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
3993
3994 /* Set up the current options. These may change throughout assembly. */
3995 mips_opts = file_mips_opts;
3996
3997 mips_check_isa_supports_ases ();
3998 mips_check_options (&file_mips_opts, TRUE);
3999 file_mips_opts_checked = TRUE;
4000
4001 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
4002 as_warn (_("could not set architecture and machine"));
4003}
4004
252b5132 4005void
17a2f251 4006md_assemble (char *str)
252b5132
RH
4007{
4008 struct mips_cl_insn insn;
f6688943
TS
4009 bfd_reloc_code_real_type unused_reloc[3]
4010 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 4011
919731af 4012 file_mips_check_options ();
4013
252b5132 4014 imm_expr.X_op = O_absent;
252b5132 4015 offset_expr.X_op = O_absent;
f6688943
TS
4016 offset_reloc[0] = BFD_RELOC_UNUSED;
4017 offset_reloc[1] = BFD_RELOC_UNUSED;
4018 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132 4019
e1b47bd5
RS
4020 mips_mark_labels ();
4021 mips_assembling_insn = TRUE;
e3de51ce 4022 clear_insn_error ();
e1b47bd5 4023
252b5132
RH
4024 if (mips_opts.mips16)
4025 mips16_ip (str, &insn);
4026 else
4027 {
4028 mips_ip (str, &insn);
beae10d5
KH
4029 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4030 str, insn.insn_opcode));
252b5132
RH
4031 }
4032
e3de51ce
RS
4033 if (insn_error.msg)
4034 report_insn_error (str);
e1b47bd5 4035 else if (insn.insn_mo->pinfo == INSN_MACRO)
252b5132 4036 {
584892a6 4037 macro_start ();
252b5132
RH
4038 if (mips_opts.mips16)
4039 mips16_macro (&insn);
4040 else
833794fc 4041 macro (&insn, str);
584892a6 4042 macro_end ();
252b5132
RH
4043 }
4044 else
4045 {
77bd4346 4046 if (offset_expr.X_op != O_absent)
df58fc94 4047 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
252b5132 4048 else
df58fc94 4049 append_insn (&insn, NULL, unused_reloc, FALSE);
252b5132 4050 }
e1b47bd5
RS
4051
4052 mips_assembling_insn = FALSE;
252b5132
RH
4053}
4054
738e5348
RS
4055/* Convenience functions for abstracting away the differences between
4056 MIPS16 and non-MIPS16 relocations. */
4057
4058static inline bfd_boolean
4059mips16_reloc_p (bfd_reloc_code_real_type reloc)
4060{
4061 switch (reloc)
4062 {
4063 case BFD_RELOC_MIPS16_JMP:
4064 case BFD_RELOC_MIPS16_GPREL:
4065 case BFD_RELOC_MIPS16_GOT16:
4066 case BFD_RELOC_MIPS16_CALL16:
4067 case BFD_RELOC_MIPS16_HI16_S:
4068 case BFD_RELOC_MIPS16_HI16:
4069 case BFD_RELOC_MIPS16_LO16:
c9775dde 4070 case BFD_RELOC_MIPS16_16_PCREL_S1:
738e5348
RS
4071 return TRUE;
4072
4073 default:
4074 return FALSE;
4075 }
4076}
4077
df58fc94
RS
4078static inline bfd_boolean
4079micromips_reloc_p (bfd_reloc_code_real_type reloc)
4080{
4081 switch (reloc)
4082 {
4083 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4084 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4085 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4086 case BFD_RELOC_MICROMIPS_GPREL16:
4087 case BFD_RELOC_MICROMIPS_JMP:
4088 case BFD_RELOC_MICROMIPS_HI16:
4089 case BFD_RELOC_MICROMIPS_HI16_S:
4090 case BFD_RELOC_MICROMIPS_LO16:
4091 case BFD_RELOC_MICROMIPS_LITERAL:
4092 case BFD_RELOC_MICROMIPS_GOT16:
4093 case BFD_RELOC_MICROMIPS_CALL16:
4094 case BFD_RELOC_MICROMIPS_GOT_HI16:
4095 case BFD_RELOC_MICROMIPS_GOT_LO16:
4096 case BFD_RELOC_MICROMIPS_CALL_HI16:
4097 case BFD_RELOC_MICROMIPS_CALL_LO16:
4098 case BFD_RELOC_MICROMIPS_SUB:
4099 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4100 case BFD_RELOC_MICROMIPS_GOT_OFST:
4101 case BFD_RELOC_MICROMIPS_GOT_DISP:
4102 case BFD_RELOC_MICROMIPS_HIGHEST:
4103 case BFD_RELOC_MICROMIPS_HIGHER:
4104 case BFD_RELOC_MICROMIPS_SCN_DISP:
4105 case BFD_RELOC_MICROMIPS_JALR:
4106 return TRUE;
4107
4108 default:
4109 return FALSE;
4110 }
4111}
4112
2309ddf2
MR
4113static inline bfd_boolean
4114jmp_reloc_p (bfd_reloc_code_real_type reloc)
4115{
4116 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4117}
4118
0e9c5a5c
MR
4119static inline bfd_boolean
4120b_reloc_p (bfd_reloc_code_real_type reloc)
4121{
4122 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4123 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4124 || reloc == BFD_RELOC_16_PCREL_S2
c9775dde 4125 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1
0e9c5a5c
MR
4126 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4127 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4128 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4129}
4130
738e5348
RS
4131static inline bfd_boolean
4132got16_reloc_p (bfd_reloc_code_real_type reloc)
4133{
2309ddf2 4134 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
df58fc94 4135 || reloc == BFD_RELOC_MICROMIPS_GOT16);
738e5348
RS
4136}
4137
4138static inline bfd_boolean
4139hi16_reloc_p (bfd_reloc_code_real_type reloc)
4140{
2309ddf2 4141 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
df58fc94 4142 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
738e5348
RS
4143}
4144
4145static inline bfd_boolean
4146lo16_reloc_p (bfd_reloc_code_real_type reloc)
4147{
2309ddf2 4148 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
df58fc94
RS
4149 || reloc == BFD_RELOC_MICROMIPS_LO16);
4150}
4151
df58fc94
RS
4152static inline bfd_boolean
4153jalr_reloc_p (bfd_reloc_code_real_type reloc)
4154{
2309ddf2 4155 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
738e5348
RS
4156}
4157
f2ae14a1
RS
4158static inline bfd_boolean
4159gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4160{
4161 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4162 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4163}
4164
2de39019
CM
4165/* Return true if RELOC is a PC-relative relocation that does not have
4166 full address range. */
4167
4168static inline bfd_boolean
4169limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4170{
4171 switch (reloc)
4172 {
4173 case BFD_RELOC_16_PCREL_S2:
c9775dde 4174 case BFD_RELOC_MIPS16_16_PCREL_S1:
2de39019
CM
4175 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4176 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4177 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
7361da2c
AB
4178 case BFD_RELOC_MIPS_21_PCREL_S2:
4179 case BFD_RELOC_MIPS_26_PCREL_S2:
4180 case BFD_RELOC_MIPS_18_PCREL_S3:
4181 case BFD_RELOC_MIPS_19_PCREL_S2:
2de39019
CM
4182 return TRUE;
4183
b47468a6 4184 case BFD_RELOC_32_PCREL:
7361da2c
AB
4185 case BFD_RELOC_HI16_S_PCREL:
4186 case BFD_RELOC_LO16_PCREL:
b47468a6
CM
4187 return HAVE_64BIT_ADDRESSES;
4188
2de39019
CM
4189 default:
4190 return FALSE;
4191 }
4192}
b47468a6 4193
5919d012 4194/* Return true if the given relocation might need a matching %lo().
0a44bf69
RS
4195 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4196 need a matching %lo() when applied to local symbols. */
5919d012
RS
4197
4198static inline bfd_boolean
17a2f251 4199reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
5919d012 4200{
3b91255e 4201 return (HAVE_IN_PLACE_ADDENDS
738e5348 4202 && (hi16_reloc_p (reloc)
0a44bf69
RS
4203 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4204 all GOT16 relocations evaluate to "G". */
738e5348
RS
4205 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4206}
4207
4208/* Return the type of %lo() reloc needed by RELOC, given that
4209 reloc_needs_lo_p. */
4210
4211static inline bfd_reloc_code_real_type
4212matching_lo_reloc (bfd_reloc_code_real_type reloc)
4213{
df58fc94
RS
4214 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4215 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4216 : BFD_RELOC_LO16));
5919d012
RS
4217}
4218
4219/* Return true if the given fixup is followed by a matching R_MIPS_LO16
4220 relocation. */
4221
4222static inline bfd_boolean
17a2f251 4223fixup_has_matching_lo_p (fixS *fixp)
5919d012
RS
4224{
4225 return (fixp->fx_next != NULL
738e5348 4226 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
5919d012
RS
4227 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4228 && fixp->fx_offset == fixp->fx_next->fx_offset);
4229}
4230
462427c4
RS
4231/* Move all labels in LABELS to the current insertion point. TEXT_P
4232 says whether the labels refer to text or data. */
404a8071
RS
4233
4234static void
462427c4 4235mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
404a8071
RS
4236{
4237 struct insn_label_list *l;
4238 valueT val;
4239
462427c4 4240 for (l = labels; l != NULL; l = l->next)
404a8071 4241 {
9c2799c2 4242 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
404a8071
RS
4243 symbol_set_frag (l->label, frag_now);
4244 val = (valueT) frag_now_fix ();
df58fc94 4245 /* MIPS16/microMIPS text labels are stored as odd. */
462427c4 4246 if (text_p && HAVE_CODE_COMPRESSION)
404a8071
RS
4247 ++val;
4248 S_SET_VALUE (l->label, val);
4249 }
4250}
4251
462427c4
RS
4252/* Move all labels in insn_labels to the current insertion point
4253 and treat them as text labels. */
4254
4255static void
4256mips_move_text_labels (void)
4257{
4258 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4259}
4260
5f0fe04b
TS
4261static bfd_boolean
4262s_is_linkonce (symbolS *sym, segT from_seg)
4263{
4264 bfd_boolean linkonce = FALSE;
4265 segT symseg = S_GET_SEGMENT (sym);
4266
4267 if (symseg != from_seg && !S_IS_LOCAL (sym))
4268 {
4269 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4270 linkonce = TRUE;
5f0fe04b
TS
4271 /* The GNU toolchain uses an extension for ELF: a section
4272 beginning with the magic string .gnu.linkonce is a
4273 linkonce section. */
4274 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4275 sizeof ".gnu.linkonce" - 1) == 0)
4276 linkonce = TRUE;
5f0fe04b
TS
4277 }
4278 return linkonce;
4279}
4280
e1b47bd5 4281/* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
df58fc94
RS
4282 linker to handle them specially, such as generating jalx instructions
4283 when needed. We also make them odd for the duration of the assembly,
4284 in order to generate the right sort of code. We will make them even
252b5132
RH
4285 in the adjust_symtab routine, while leaving them marked. This is
4286 convenient for the debugger and the disassembler. The linker knows
4287 to make them odd again. */
4288
4289static void
e1b47bd5 4290mips_compressed_mark_label (symbolS *label)
252b5132 4291{
df58fc94 4292 gas_assert (HAVE_CODE_COMPRESSION);
a8dbcb85 4293
f3ded42a
RS
4294 if (mips_opts.mips16)
4295 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4296 else
4297 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
e1b47bd5
RS
4298 if ((S_GET_VALUE (label) & 1) == 0
4299 /* Don't adjust the address if the label is global or weak, or
4300 in a link-once section, since we'll be emitting symbol reloc
4301 references to it which will be patched up by the linker, and
4302 the final value of the symbol may or may not be MIPS16/microMIPS. */
4303 && !S_IS_WEAK (label)
4304 && !S_IS_EXTERNAL (label)
4305 && !s_is_linkonce (label, now_seg))
4306 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4307}
4308
4309/* Mark preceding MIPS16 or microMIPS instruction labels. */
4310
4311static void
4312mips_compressed_mark_labels (void)
4313{
4314 struct insn_label_list *l;
4315
4316 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4317 mips_compressed_mark_label (l->label);
252b5132
RH
4318}
4319
4d7206a2
RS
4320/* End the current frag. Make it a variant frag and record the
4321 relaxation info. */
4322
4323static void
4324relax_close_frag (void)
4325{
584892a6 4326 mips_macro_warning.first_frag = frag_now;
4d7206a2 4327 frag_var (rs_machine_dependent, 0, 0,
584892a6 4328 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4d7206a2
RS
4329 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4330
4331 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4332 mips_relax.first_fixup = 0;
4333}
4334
4335/* Start a new relaxation sequence whose expansion depends on SYMBOL.
4336 See the comment above RELAX_ENCODE for more details. */
4337
4338static void
4339relax_start (symbolS *symbol)
4340{
9c2799c2 4341 gas_assert (mips_relax.sequence == 0);
4d7206a2
RS
4342 mips_relax.sequence = 1;
4343 mips_relax.symbol = symbol;
4344}
4345
4346/* Start generating the second version of a relaxable sequence.
4347 See the comment above RELAX_ENCODE for more details. */
252b5132
RH
4348
4349static void
4d7206a2
RS
4350relax_switch (void)
4351{
9c2799c2 4352 gas_assert (mips_relax.sequence == 1);
4d7206a2
RS
4353 mips_relax.sequence = 2;
4354}
4355
4356/* End the current relaxable sequence. */
4357
4358static void
4359relax_end (void)
4360{
9c2799c2 4361 gas_assert (mips_relax.sequence == 2);
4d7206a2
RS
4362 relax_close_frag ();
4363 mips_relax.sequence = 0;
4364}
4365
11625dd8
RS
4366/* Return true if IP is a delayed branch or jump. */
4367
4368static inline bfd_boolean
4369delayed_branch_p (const struct mips_cl_insn *ip)
4370{
4371 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4372 | INSN_COND_BRANCH_DELAY
4373 | INSN_COND_BRANCH_LIKELY)) != 0;
4374}
4375
4376/* Return true if IP is a compact branch or jump. */
4377
4378static inline bfd_boolean
4379compact_branch_p (const struct mips_cl_insn *ip)
4380{
26545944
RS
4381 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4382 | INSN2_COND_BRANCH)) != 0;
11625dd8
RS
4383}
4384
4385/* Return true if IP is an unconditional branch or jump. */
4386
4387static inline bfd_boolean
4388uncond_branch_p (const struct mips_cl_insn *ip)
4389{
4390 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
26545944 4391 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
11625dd8
RS
4392}
4393
4394/* Return true if IP is a branch-likely instruction. */
4395
4396static inline bfd_boolean
4397branch_likely_p (const struct mips_cl_insn *ip)
4398{
4399 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4400}
4401
14fe068b
RS
4402/* Return the type of nop that should be used to fill the delay slot
4403 of delayed branch IP. */
4404
4405static struct mips_cl_insn *
4406get_delay_slot_nop (const struct mips_cl_insn *ip)
4407{
4408 if (mips_opts.micromips
4409 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4410 return &micromips_nop32_insn;
4411 return NOP_INSN;
4412}
4413
fc76e730
RS
4414/* Return a mask that has bit N set if OPCODE reads the register(s)
4415 in operand N. */
df58fc94
RS
4416
4417static unsigned int
fc76e730 4418insn_read_mask (const struct mips_opcode *opcode)
df58fc94 4419{
fc76e730
RS
4420 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4421}
df58fc94 4422
fc76e730
RS
4423/* Return a mask that has bit N set if OPCODE writes to the register(s)
4424 in operand N. */
4425
4426static unsigned int
4427insn_write_mask (const struct mips_opcode *opcode)
4428{
4429 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4430}
4431
4432/* Return a mask of the registers specified by operand OPERAND of INSN.
4433 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4434 is set. */
4435
4436static unsigned int
4437operand_reg_mask (const struct mips_cl_insn *insn,
4438 const struct mips_operand *operand,
4439 unsigned int type_mask)
4440{
4441 unsigned int uval, vsel;
4442
4443 switch (operand->type)
df58fc94 4444 {
fc76e730
RS
4445 case OP_INT:
4446 case OP_MAPPED_INT:
4447 case OP_MSB:
4448 case OP_PCREL:
4449 case OP_PERF_REG:
4450 case OP_ADDIUSP_INT:
4451 case OP_ENTRY_EXIT_LIST:
4452 case OP_REPEAT_DEST_REG:
4453 case OP_REPEAT_PREV_REG:
4454 case OP_PC:
14daeee3
RS
4455 case OP_VU0_SUFFIX:
4456 case OP_VU0_MATCH_SUFFIX:
56d438b1 4457 case OP_IMM_INDEX:
fc76e730
RS
4458 abort ();
4459
4460 case OP_REG:
0f35dbc4 4461 case OP_OPTIONAL_REG:
fc76e730
RS
4462 {
4463 const struct mips_reg_operand *reg_op;
4464
4465 reg_op = (const struct mips_reg_operand *) operand;
4466 if (!(type_mask & (1 << reg_op->reg_type)))
4467 return 0;
4468 uval = insn_extract_operand (insn, operand);
4469 return 1 << mips_decode_reg_operand (reg_op, uval);
4470 }
4471
4472 case OP_REG_PAIR:
4473 {
4474 const struct mips_reg_pair_operand *pair_op;
4475
4476 pair_op = (const struct mips_reg_pair_operand *) operand;
4477 if (!(type_mask & (1 << pair_op->reg_type)))
4478 return 0;
4479 uval = insn_extract_operand (insn, operand);
4480 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4481 }
4482
4483 case OP_CLO_CLZ_DEST:
4484 if (!(type_mask & (1 << OP_REG_GP)))
4485 return 0;
4486 uval = insn_extract_operand (insn, operand);
4487 return (1 << (uval & 31)) | (1 << (uval >> 5));
4488
7361da2c
AB
4489 case OP_SAME_RS_RT:
4490 if (!(type_mask & (1 << OP_REG_GP)))
4491 return 0;
4492 uval = insn_extract_operand (insn, operand);
4493 gas_assert ((uval & 31) == (uval >> 5));
4494 return 1 << (uval & 31);
4495
4496 case OP_CHECK_PREV:
4497 case OP_NON_ZERO_REG:
4498 if (!(type_mask & (1 << OP_REG_GP)))
4499 return 0;
4500 uval = insn_extract_operand (insn, operand);
4501 return 1 << (uval & 31);
4502
fc76e730
RS
4503 case OP_LWM_SWM_LIST:
4504 abort ();
4505
4506 case OP_SAVE_RESTORE_LIST:
4507 abort ();
4508
4509 case OP_MDMX_IMM_REG:
4510 if (!(type_mask & (1 << OP_REG_VEC)))
4511 return 0;
4512 uval = insn_extract_operand (insn, operand);
4513 vsel = uval >> 5;
4514 if ((vsel & 0x18) == 0x18)
4515 return 0;
4516 return 1 << (uval & 31);
56d438b1
CF
4517
4518 case OP_REG_INDEX:
4519 if (!(type_mask & (1 << OP_REG_GP)))
4520 return 0;
4521 return 1 << insn_extract_operand (insn, operand);
df58fc94 4522 }
fc76e730
RS
4523 abort ();
4524}
4525
4526/* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4527 where bit N of OPNO_MASK is set if operand N should be included.
4528 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4529 is set. */
4530
4531static unsigned int
4532insn_reg_mask (const struct mips_cl_insn *insn,
4533 unsigned int type_mask, unsigned int opno_mask)
4534{
4535 unsigned int opno, reg_mask;
4536
4537 opno = 0;
4538 reg_mask = 0;
4539 while (opno_mask != 0)
4540 {
4541 if (opno_mask & 1)
4542 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4543 opno_mask >>= 1;
4544 opno += 1;
4545 }
4546 return reg_mask;
df58fc94
RS
4547}
4548
4c260379
RS
4549/* Return the mask of core registers that IP reads. */
4550
4551static unsigned int
4552gpr_read_mask (const struct mips_cl_insn *ip)
4553{
4554 unsigned long pinfo, pinfo2;
4555 unsigned int mask;
4556
fc76e730 4557 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4c260379
RS
4558 pinfo = ip->insn_mo->pinfo;
4559 pinfo2 = ip->insn_mo->pinfo2;
fc76e730 4560 if (pinfo & INSN_UDI)
4c260379 4561 {
fc76e730
RS
4562 /* UDI instructions have traditionally been assumed to read RS
4563 and RT. */
4564 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4565 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4c260379 4566 }
fc76e730
RS
4567 if (pinfo & INSN_READ_GPR_24)
4568 mask |= 1 << 24;
4569 if (pinfo2 & INSN2_READ_GPR_16)
4570 mask |= 1 << 16;
4571 if (pinfo2 & INSN2_READ_SP)
4572 mask |= 1 << SP;
26545944 4573 if (pinfo2 & INSN2_READ_GPR_31)
fc76e730 4574 mask |= 1 << 31;
fe35f09f
RS
4575 /* Don't include register 0. */
4576 return mask & ~1;
4c260379
RS
4577}
4578
4579/* Return the mask of core registers that IP writes. */
4580
4581static unsigned int
4582gpr_write_mask (const struct mips_cl_insn *ip)
4583{
4584 unsigned long pinfo, pinfo2;
4585 unsigned int mask;
4586
fc76e730 4587 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4c260379
RS
4588 pinfo = ip->insn_mo->pinfo;
4589 pinfo2 = ip->insn_mo->pinfo2;
fc76e730
RS
4590 if (pinfo & INSN_WRITE_GPR_24)
4591 mask |= 1 << 24;
4592 if (pinfo & INSN_WRITE_GPR_31)
4593 mask |= 1 << 31;
4594 if (pinfo & INSN_UDI)
4595 /* UDI instructions have traditionally been assumed to write to RD. */
4596 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4597 if (pinfo2 & INSN2_WRITE_SP)
4598 mask |= 1 << SP;
fe35f09f
RS
4599 /* Don't include register 0. */
4600 return mask & ~1;
4c260379
RS
4601}
4602
4603/* Return the mask of floating-point registers that IP reads. */
4604
4605static unsigned int
4606fpr_read_mask (const struct mips_cl_insn *ip)
4607{
fc76e730 4608 unsigned long pinfo;
4c260379
RS
4609 unsigned int mask;
4610
9d5de888
CF
4611 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4612 | (1 << OP_REG_MSA)),
fc76e730 4613 insn_read_mask (ip->insn_mo));
4c260379 4614 pinfo = ip->insn_mo->pinfo;
4c260379
RS
4615 /* Conservatively treat all operands to an FP_D instruction are doubles.
4616 (This is overly pessimistic for things like cvt.d.s.) */
bad1aba3 4617 if (FPR_SIZE != 64 && (pinfo & FP_D))
4c260379
RS
4618 mask |= mask << 1;
4619 return mask;
4620}
4621
4622/* Return the mask of floating-point registers that IP writes. */
4623
4624static unsigned int
4625fpr_write_mask (const struct mips_cl_insn *ip)
4626{
fc76e730 4627 unsigned long pinfo;
4c260379
RS
4628 unsigned int mask;
4629
9d5de888
CF
4630 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4631 | (1 << OP_REG_MSA)),
fc76e730 4632 insn_write_mask (ip->insn_mo));
4c260379 4633 pinfo = ip->insn_mo->pinfo;
4c260379
RS
4634 /* Conservatively treat all operands to an FP_D instruction are doubles.
4635 (This is overly pessimistic for things like cvt.s.d.) */
bad1aba3 4636 if (FPR_SIZE != 64 && (pinfo & FP_D))
4c260379
RS
4637 mask |= mask << 1;
4638 return mask;
4639}
4640
a1d78564
RS
4641/* Operand OPNUM of INSN is an odd-numbered floating-point register.
4642 Check whether that is allowed. */
4643
4644static bfd_boolean
4645mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4646{
4647 const char *s = insn->name;
351cdf24
MF
4648 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4649 || FPR_SIZE == 64)
4650 && mips_opts.oddspreg;
a1d78564
RS
4651
4652 if (insn->pinfo == INSN_MACRO)
4653 /* Let a macro pass, we'll catch it later when it is expanded. */
4654 return TRUE;
4655
351cdf24
MF
4656 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4657 otherwise it depends on oddspreg. */
4658 if ((insn->pinfo & FP_S)
4659 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
43885403 4660 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
351cdf24 4661 return FPR_SIZE == 32 || oddspreg;
a1d78564 4662
351cdf24
MF
4663 /* Allow odd registers for single-precision ops and double-precision if the
4664 floating-point registers are 64-bit wide. */
4665 switch (insn->pinfo & (FP_S | FP_D))
4666 {
4667 case FP_S:
4668 case 0:
4669 return oddspreg;
4670 case FP_D:
4671 return FPR_SIZE == 64;
4672 default:
4673 break;
a1d78564
RS
4674 }
4675
351cdf24
MF
4676 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4677 s = strchr (insn->name, '.');
4678 if (s != NULL && opnum == 2)
4679 s = strchr (s + 1, '.');
4680 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4681 return oddspreg;
a1d78564 4682
351cdf24 4683 return FPR_SIZE == 64;
a1d78564
RS
4684}
4685
a1d78564
RS
4686/* Information about an instruction argument that we're trying to match. */
4687struct mips_arg_info
4688{
4689 /* The instruction so far. */
4690 struct mips_cl_insn *insn;
4691
a92713e6
RS
4692 /* The first unconsumed operand token. */
4693 struct mips_operand_token *token;
4694
a1d78564
RS
4695 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4696 int opnum;
4697
4698 /* The 1-based argument number, for error reporting. This does not
4699 count elided optional registers, etc.. */
4700 int argnum;
4701
4702 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4703 unsigned int last_regno;
4704
4705 /* If the first operand was an OP_REG, this is the register that it
4706 specified, otherwise it is ILLEGAL_REG. */
4707 unsigned int dest_regno;
4708
4709 /* The value of the last OP_INT operand. Only used for OP_MSB,
4710 where it gives the lsb position. */
4711 unsigned int last_op_int;
4712
60f20e8b
RS
4713 /* If true, match routines should assume that no later instruction
4714 alternative matches and should therefore be as accomodating as
4715 possible. Match routines should not report errors if something
4716 is only invalid for !LAX_MATCH. */
4717 bfd_boolean lax_match;
a1d78564 4718
a1d78564
RS
4719 /* True if a reference to the current AT register was seen. */
4720 bfd_boolean seen_at;
4721};
4722
1a00e612
RS
4723/* Record that the argument is out of range. */
4724
4725static void
4726match_out_of_range (struct mips_arg_info *arg)
4727{
4728 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4729}
4730
4731/* Record that the argument isn't constant but needs to be. */
4732
4733static void
4734match_not_constant (struct mips_arg_info *arg)
4735{
4736 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4737 arg->argnum);
4738}
4739
a92713e6
RS
4740/* Try to match an OT_CHAR token for character CH. Consume the token
4741 and return true on success, otherwise return false. */
a1d78564 4742
a92713e6
RS
4743static bfd_boolean
4744match_char (struct mips_arg_info *arg, char ch)
a1d78564 4745{
a92713e6
RS
4746 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4747 {
4748 ++arg->token;
4749 if (ch == ',')
4750 arg->argnum += 1;
4751 return TRUE;
4752 }
4753 return FALSE;
4754}
a1d78564 4755
a92713e6
RS
4756/* Try to get an expression from the next tokens in ARG. Consume the
4757 tokens and return true on success, storing the expression value in
4758 VALUE and relocation types in R. */
4759
4760static bfd_boolean
4761match_expression (struct mips_arg_info *arg, expressionS *value,
4762 bfd_reloc_code_real_type *r)
4763{
d436c1c2
RS
4764 /* If the next token is a '(' that was parsed as being part of a base
4765 expression, assume we have an elided offset. The later match will fail
4766 if this turns out to be wrong. */
4767 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
a1d78564 4768 {
d436c1c2
RS
4769 value->X_op = O_constant;
4770 value->X_add_number = 0;
4771 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
a92713e6
RS
4772 return TRUE;
4773 }
4774
d436c1c2
RS
4775 /* Reject register-based expressions such as "0+$2" and "(($2))".
4776 For plain registers the default error seems more appropriate. */
4777 if (arg->token->type == OT_INTEGER
4778 && arg->token->u.integer.value.X_op == O_register)
a92713e6 4779 {
d436c1c2
RS
4780 set_insn_error (arg->argnum, _("register value used as expression"));
4781 return FALSE;
a1d78564 4782 }
d436c1c2
RS
4783
4784 if (arg->token->type == OT_INTEGER)
a92713e6 4785 {
d436c1c2
RS
4786 *value = arg->token->u.integer.value;
4787 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4788 ++arg->token;
4789 return TRUE;
a92713e6 4790 }
a92713e6 4791
d436c1c2
RS
4792 set_insn_error_i
4793 (arg->argnum, _("operand %d must be an immediate expression"),
4794 arg->argnum);
4795 return FALSE;
a92713e6
RS
4796}
4797
4798/* Try to get a constant expression from the next tokens in ARG. Consume
4799 the tokens and return return true on success, storing the constant value
4800 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4801 error. */
4802
4803static bfd_boolean
1a00e612 4804match_const_int (struct mips_arg_info *arg, offsetT *value)
a92713e6
RS
4805{
4806 expressionS ex;
4807 bfd_reloc_code_real_type r[3];
a1d78564 4808
a92713e6
RS
4809 if (!match_expression (arg, &ex, r))
4810 return FALSE;
4811
4812 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
a1d78564
RS
4813 *value = ex.X_add_number;
4814 else
4815 {
1a00e612
RS
4816 match_not_constant (arg);
4817 return FALSE;
a1d78564 4818 }
a92713e6 4819 return TRUE;
a1d78564
RS
4820}
4821
4822/* Return the RTYPE_* flags for a register operand of type TYPE that
4823 appears in instruction OPCODE. */
4824
4825static unsigned int
4826convert_reg_type (const struct mips_opcode *opcode,
4827 enum mips_reg_operand_type type)
4828{
4829 switch (type)
4830 {
4831 case OP_REG_GP:
4832 return RTYPE_NUM | RTYPE_GP;
4833
4834 case OP_REG_FP:
4835 /* Allow vector register names for MDMX if the instruction is a 64-bit
4836 FPR load, store or move (including moves to and from GPRs). */
4837 if ((mips_opts.ase & ASE_MDMX)
4838 && (opcode->pinfo & FP_D)
43885403 4839 && (opcode->pinfo & (INSN_COPROC_MOVE
a1d78564 4840 | INSN_COPROC_MEMORY_DELAY
43885403 4841 | INSN_LOAD_COPROC
67dc82bc 4842 | INSN_LOAD_MEMORY
a1d78564
RS
4843 | INSN_STORE_MEMORY)))
4844 return RTYPE_FPU | RTYPE_VEC;
4845 return RTYPE_FPU;
4846
4847 case OP_REG_CCC:
4848 if (opcode->pinfo & (FP_D | FP_S))
4849 return RTYPE_CCC | RTYPE_FCC;
4850 return RTYPE_CCC;
4851
4852 case OP_REG_VEC:
4853 if (opcode->membership & INSN_5400)
4854 return RTYPE_FPU;
4855 return RTYPE_FPU | RTYPE_VEC;
4856
4857 case OP_REG_ACC:
4858 return RTYPE_ACC;
4859
4860 case OP_REG_COPRO:
4861 if (opcode->name[strlen (opcode->name) - 1] == '0')
4862 return RTYPE_NUM | RTYPE_CP0;
4863 return RTYPE_NUM;
4864
4865 case OP_REG_HW:
4866 return RTYPE_NUM;
14daeee3
RS
4867
4868 case OP_REG_VI:
4869 return RTYPE_NUM | RTYPE_VI;
4870
4871 case OP_REG_VF:
4872 return RTYPE_NUM | RTYPE_VF;
4873
4874 case OP_REG_R5900_I:
4875 return RTYPE_R5900_I;
4876
4877 case OP_REG_R5900_Q:
4878 return RTYPE_R5900_Q;
4879
4880 case OP_REG_R5900_R:
4881 return RTYPE_R5900_R;
4882
4883 case OP_REG_R5900_ACC:
4884 return RTYPE_R5900_ACC;
56d438b1
CF
4885
4886 case OP_REG_MSA:
4887 return RTYPE_MSA;
4888
4889 case OP_REG_MSA_CTRL:
4890 return RTYPE_NUM;
a1d78564
RS
4891 }
4892 abort ();
4893}
4894
4895/* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4896
4897static void
4898check_regno (struct mips_arg_info *arg,
4899 enum mips_reg_operand_type type, unsigned int regno)
4900{
4901 if (AT && type == OP_REG_GP && regno == AT)
4902 arg->seen_at = TRUE;
4903
4904 if (type == OP_REG_FP
4905 && (regno & 1) != 0
a1d78564 4906 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
351cdf24
MF
4907 {
4908 /* This was a warning prior to introducing O32 FPXX and FP64 support
4909 so maintain a warning for FP32 but raise an error for the new
4910 cases. */
4911 if (FPR_SIZE == 32)
4912 as_warn (_("float register should be even, was %d"), regno);
4913 else
4914 as_bad (_("float register should be even, was %d"), regno);
4915 }
a1d78564
RS
4916
4917 if (type == OP_REG_CCC)
4918 {
4919 const char *name;
4920 size_t length;
4921
4922 name = arg->insn->insn_mo->name;
4923 length = strlen (name);
4924 if ((regno & 1) != 0
4925 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4926 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
1661c76c 4927 as_warn (_("condition code register should be even for %s, was %d"),
a1d78564
RS
4928 name, regno);
4929
4930 if ((regno & 3) != 0
4931 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
1661c76c 4932 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
a1d78564
RS
4933 name, regno);
4934 }
4935}
4936
a92713e6
RS
4937/* ARG is a register with symbol value SYMVAL. Try to interpret it as
4938 a register of type TYPE. Return true on success, storing the register
4939 number in *REGNO and warning about any dubious uses. */
4940
4941static bfd_boolean
4942match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4943 unsigned int symval, unsigned int *regno)
4944{
4945 if (type == OP_REG_VEC)
4946 symval = mips_prefer_vec_regno (symval);
4947 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4948 return FALSE;
4949
4950 *regno = symval & RNUM_MASK;
4951 check_regno (arg, type, *regno);
4952 return TRUE;
4953}
4954
4955/* Try to interpret the next token in ARG as a register of type TYPE.
4956 Consume the token and return true on success, storing the register
4957 number in *REGNO. Return false on failure. */
4958
4959static bfd_boolean
4960match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4961 unsigned int *regno)
4962{
4963 if (arg->token->type == OT_REG
4964 && match_regno (arg, type, arg->token->u.regno, regno))
4965 {
4966 ++arg->token;
4967 return TRUE;
4968 }
4969 return FALSE;
4970}
4971
4972/* Try to interpret the next token in ARG as a range of registers of type TYPE.
4973 Consume the token and return true on success, storing the register numbers
4974 in *REGNO1 and *REGNO2. Return false on failure. */
4975
4976static bfd_boolean
4977match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4978 unsigned int *regno1, unsigned int *regno2)
4979{
4980 if (match_reg (arg, type, regno1))
4981 {
4982 *regno2 = *regno1;
4983 return TRUE;
4984 }
4985 if (arg->token->type == OT_REG_RANGE
4986 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4987 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4988 && *regno1 <= *regno2)
4989 {
4990 ++arg->token;
4991 return TRUE;
4992 }
4993 return FALSE;
4994}
4995
a1d78564
RS
4996/* OP_INT matcher. */
4997
a92713e6 4998static bfd_boolean
a1d78564 4999match_int_operand (struct mips_arg_info *arg,
a92713e6 5000 const struct mips_operand *operand_base)
a1d78564
RS
5001{
5002 const struct mips_int_operand *operand;
3ccad066 5003 unsigned int uval;
a1d78564
RS
5004 int min_val, max_val, factor;
5005 offsetT sval;
a1d78564
RS
5006
5007 operand = (const struct mips_int_operand *) operand_base;
5008 factor = 1 << operand->shift;
3ccad066
RS
5009 min_val = mips_int_operand_min (operand);
5010 max_val = mips_int_operand_max (operand);
a1d78564 5011
d436c1c2
RS
5012 if (operand_base->lsb == 0
5013 && operand_base->size == 16
5014 && operand->shift == 0
5015 && operand->bias == 0
5016 && (operand->max_val == 32767 || operand->max_val == 65535))
a1d78564
RS
5017 {
5018 /* The operand can be relocated. */
a92713e6
RS
5019 if (!match_expression (arg, &offset_expr, offset_reloc))
5020 return FALSE;
5021
5022 if (offset_reloc[0] != BFD_RELOC_UNUSED)
a1d78564
RS
5023 /* Relocation operators were used. Accept the arguent and
5024 leave the relocation value in offset_expr and offset_relocs
5025 for the caller to process. */
a92713e6
RS
5026 return TRUE;
5027
5028 if (offset_expr.X_op != O_constant)
a1d78564 5029 {
60f20e8b
RS
5030 /* Accept non-constant operands if no later alternative matches,
5031 leaving it for the caller to process. */
5032 if (!arg->lax_match)
5033 return FALSE;
a92713e6
RS
5034 offset_reloc[0] = BFD_RELOC_LO16;
5035 return TRUE;
a1d78564 5036 }
a92713e6 5037
a1d78564
RS
5038 /* Clear the global state; we're going to install the operand
5039 ourselves. */
a92713e6 5040 sval = offset_expr.X_add_number;
a1d78564 5041 offset_expr.X_op = O_absent;
60f20e8b
RS
5042
5043 /* For compatibility with older assemblers, we accept
5044 0x8000-0xffff as signed 16-bit numbers when only
5045 signed numbers are allowed. */
5046 if (sval > max_val)
5047 {
5048 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5049 if (!arg->lax_match && sval <= max_val)
5050 return FALSE;
5051 }
a1d78564
RS
5052 }
5053 else
5054 {
1a00e612 5055 if (!match_const_int (arg, &sval))
a92713e6 5056 return FALSE;
a1d78564
RS
5057 }
5058
5059 arg->last_op_int = sval;
5060
1a00e612 5061 if (sval < min_val || sval > max_val || sval % factor)
a1d78564 5062 {
1a00e612
RS
5063 match_out_of_range (arg);
5064 return FALSE;
a1d78564
RS
5065 }
5066
5067 uval = (unsigned int) sval >> operand->shift;
5068 uval -= operand->bias;
5069
5070 /* Handle -mfix-cn63xxp1. */
5071 if (arg->opnum == 1
5072 && mips_fix_cn63xxp1
5073 && !mips_opts.micromips
5074 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5075 switch (uval)
5076 {
5077 case 5:
5078 case 25:
5079 case 26:
5080 case 27:
5081 case 28:
5082 case 29:
5083 case 30:
5084 case 31:
5085 /* These are ok. */
5086 break;
5087
5088 default:
5089 /* The rest must be changed to 28. */
5090 uval = 28;
5091 break;
5092 }
5093
5094 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 5095 return TRUE;
a1d78564
RS
5096}
5097
5098/* OP_MAPPED_INT matcher. */
5099
a92713e6 5100static bfd_boolean
a1d78564 5101match_mapped_int_operand (struct mips_arg_info *arg,
a92713e6 5102 const struct mips_operand *operand_base)
a1d78564
RS
5103{
5104 const struct mips_mapped_int_operand *operand;
5105 unsigned int uval, num_vals;
5106 offsetT sval;
5107
5108 operand = (const struct mips_mapped_int_operand *) operand_base;
1a00e612 5109 if (!match_const_int (arg, &sval))
a92713e6 5110 return FALSE;
a1d78564
RS
5111
5112 num_vals = 1 << operand_base->size;
5113 for (uval = 0; uval < num_vals; uval++)
5114 if (operand->int_map[uval] == sval)
5115 break;
5116 if (uval == num_vals)
1a00e612
RS
5117 {
5118 match_out_of_range (arg);
5119 return FALSE;
5120 }
a1d78564
RS
5121
5122 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 5123 return TRUE;
a1d78564
RS
5124}
5125
5126/* OP_MSB matcher. */
5127
a92713e6 5128static bfd_boolean
a1d78564 5129match_msb_operand (struct mips_arg_info *arg,
a92713e6 5130 const struct mips_operand *operand_base)
a1d78564
RS
5131{
5132 const struct mips_msb_operand *operand;
5133 int min_val, max_val, max_high;
5134 offsetT size, sval, high;
5135
5136 operand = (const struct mips_msb_operand *) operand_base;
5137 min_val = operand->bias;
5138 max_val = min_val + (1 << operand_base->size) - 1;
5139 max_high = operand->opsize;
5140
1a00e612 5141 if (!match_const_int (arg, &size))
a92713e6 5142 return FALSE;
a1d78564
RS
5143
5144 high = size + arg->last_op_int;
5145 sval = operand->add_lsb ? high : size;
5146
5147 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5148 {
1a00e612
RS
5149 match_out_of_range (arg);
5150 return FALSE;
a1d78564
RS
5151 }
5152 insn_insert_operand (arg->insn, operand_base, sval - min_val);
a92713e6 5153 return TRUE;
a1d78564
RS
5154}
5155
5156/* OP_REG matcher. */
5157
a92713e6 5158static bfd_boolean
a1d78564 5159match_reg_operand (struct mips_arg_info *arg,
a92713e6 5160 const struct mips_operand *operand_base)
a1d78564
RS
5161{
5162 const struct mips_reg_operand *operand;
a92713e6 5163 unsigned int regno, uval, num_vals;
a1d78564
RS
5164
5165 operand = (const struct mips_reg_operand *) operand_base;
a92713e6
RS
5166 if (!match_reg (arg, operand->reg_type, &regno))
5167 return FALSE;
a1d78564
RS
5168
5169 if (operand->reg_map)
5170 {
5171 num_vals = 1 << operand->root.size;
5172 for (uval = 0; uval < num_vals; uval++)
5173 if (operand->reg_map[uval] == regno)
5174 break;
5175 if (num_vals == uval)
a92713e6 5176 return FALSE;
a1d78564
RS
5177 }
5178 else
5179 uval = regno;
5180
a1d78564
RS
5181 arg->last_regno = regno;
5182 if (arg->opnum == 1)
5183 arg->dest_regno = regno;
5184 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 5185 return TRUE;
a1d78564
RS
5186}
5187
5188/* OP_REG_PAIR matcher. */
5189
a92713e6 5190static bfd_boolean
a1d78564 5191match_reg_pair_operand (struct mips_arg_info *arg,
a92713e6 5192 const struct mips_operand *operand_base)
a1d78564
RS
5193{
5194 const struct mips_reg_pair_operand *operand;
a92713e6 5195 unsigned int regno1, regno2, uval, num_vals;
a1d78564
RS
5196
5197 operand = (const struct mips_reg_pair_operand *) operand_base;
a92713e6
RS
5198 if (!match_reg (arg, operand->reg_type, &regno1)
5199 || !match_char (arg, ',')
5200 || !match_reg (arg, operand->reg_type, &regno2))
5201 return FALSE;
a1d78564
RS
5202
5203 num_vals = 1 << operand_base->size;
5204 for (uval = 0; uval < num_vals; uval++)
5205 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5206 break;
5207 if (uval == num_vals)
a92713e6 5208 return FALSE;
a1d78564 5209
a1d78564 5210 insn_insert_operand (arg->insn, operand_base, uval);
a92713e6 5211 return TRUE;
a1d78564
RS
5212}
5213
5214/* OP_PCREL matcher. The caller chooses the relocation type. */
5215
a92713e6
RS
5216static bfd_boolean
5217match_pcrel_operand (struct mips_arg_info *arg)
a1d78564 5218{
a92713e6
RS
5219 bfd_reloc_code_real_type r[3];
5220
5221 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
a1d78564
RS
5222}
5223
5224/* OP_PERF_REG matcher. */
5225
a92713e6 5226static bfd_boolean
a1d78564 5227match_perf_reg_operand (struct mips_arg_info *arg,
a92713e6 5228 const struct mips_operand *operand)
a1d78564
RS
5229{
5230 offsetT sval;
5231
1a00e612 5232 if (!match_const_int (arg, &sval))
a92713e6 5233 return FALSE;
a1d78564
RS
5234
5235 if (sval != 0
5236 && (sval != 1
5237 || (mips_opts.arch == CPU_R5900
5238 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5239 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5240 {
1a00e612
RS
5241 set_insn_error (arg->argnum, _("invalid performance register"));
5242 return FALSE;
a1d78564
RS
5243 }
5244
5245 insn_insert_operand (arg->insn, operand, sval);
a92713e6 5246 return TRUE;
a1d78564
RS
5247}
5248
5249/* OP_ADDIUSP matcher. */
5250
a92713e6 5251static bfd_boolean
a1d78564 5252match_addiusp_operand (struct mips_arg_info *arg,
a92713e6 5253 const struct mips_operand *operand)
a1d78564
RS
5254{
5255 offsetT sval;
5256 unsigned int uval;
5257
1a00e612 5258 if (!match_const_int (arg, &sval))
a92713e6 5259 return FALSE;
a1d78564
RS
5260
5261 if (sval % 4)
1a00e612
RS
5262 {
5263 match_out_of_range (arg);
5264 return FALSE;
5265 }
a1d78564
RS
5266
5267 sval /= 4;
5268 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
1a00e612
RS
5269 {
5270 match_out_of_range (arg);
5271 return FALSE;
5272 }
a1d78564
RS
5273
5274 uval = (unsigned int) sval;
5275 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5276 insn_insert_operand (arg->insn, operand, uval);
a92713e6 5277 return TRUE;
a1d78564
RS
5278}
5279
5280/* OP_CLO_CLZ_DEST matcher. */
5281
a92713e6 5282static bfd_boolean
a1d78564 5283match_clo_clz_dest_operand (struct mips_arg_info *arg,
a92713e6 5284 const struct mips_operand *operand)
a1d78564
RS
5285{
5286 unsigned int regno;
5287
a92713e6
RS
5288 if (!match_reg (arg, OP_REG_GP, &regno))
5289 return FALSE;
a1d78564 5290
a1d78564 5291 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
a92713e6 5292 return TRUE;
a1d78564
RS
5293}
5294
7361da2c
AB
5295/* OP_CHECK_PREV matcher. */
5296
5297static bfd_boolean
5298match_check_prev_operand (struct mips_arg_info *arg,
5299 const struct mips_operand *operand_base)
5300{
5301 const struct mips_check_prev_operand *operand;
5302 unsigned int regno;
5303
5304 operand = (const struct mips_check_prev_operand *) operand_base;
5305
5306 if (!match_reg (arg, OP_REG_GP, &regno))
5307 return FALSE;
5308
5309 if (!operand->zero_ok && regno == 0)
5310 return FALSE;
5311
5312 if ((operand->less_than_ok && regno < arg->last_regno)
5313 || (operand->greater_than_ok && regno > arg->last_regno)
5314 || (operand->equal_ok && regno == arg->last_regno))
5315 {
5316 arg->last_regno = regno;
5317 insn_insert_operand (arg->insn, operand_base, regno);
5318 return TRUE;
5319 }
5320
5321 return FALSE;
5322}
5323
5324/* OP_SAME_RS_RT matcher. */
5325
5326static bfd_boolean
5327match_same_rs_rt_operand (struct mips_arg_info *arg,
5328 const struct mips_operand *operand)
5329{
5330 unsigned int regno;
5331
5332 if (!match_reg (arg, OP_REG_GP, &regno))
5333 return FALSE;
5334
5335 if (regno == 0)
5336 {
5337 set_insn_error (arg->argnum, _("the source register must not be $0"));
5338 return FALSE;
5339 }
5340
5341 arg->last_regno = regno;
5342
5343 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5344 return TRUE;
5345}
5346
a1d78564
RS
5347/* OP_LWM_SWM_LIST matcher. */
5348
a92713e6 5349static bfd_boolean
a1d78564 5350match_lwm_swm_list_operand (struct mips_arg_info *arg,
a92713e6 5351 const struct mips_operand *operand)
a1d78564 5352{
a92713e6
RS
5353 unsigned int reglist, sregs, ra, regno1, regno2;
5354 struct mips_arg_info reset;
a1d78564 5355
a92713e6
RS
5356 reglist = 0;
5357 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
5358 return FALSE;
5359 do
5360 {
5361 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5362 {
5363 reglist |= 1 << FP;
5364 regno2 = S7;
5365 }
5366 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5367 reset = *arg;
5368 }
5369 while (match_char (arg, ',')
5370 && match_reg_range (arg, OP_REG_GP, &regno1, &regno2));
5371 *arg = reset;
a1d78564
RS
5372
5373 if (operand->size == 2)
5374 {
5375 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5376
5377 s0, ra
5378 s0, s1, ra, s2, s3
5379 s0-s2, ra
5380
5381 and any permutations of these. */
5382 if ((reglist & 0xfff1ffff) != 0x80010000)
a92713e6 5383 return FALSE;
a1d78564
RS
5384
5385 sregs = (reglist >> 17) & 7;
5386 ra = 0;
5387 }
5388 else
5389 {
5390 /* The list must include at least one of ra and s0-sN,
5391 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5392 which are $23 and $30 respectively.) E.g.:
5393
5394 ra
5395 s0
5396 ra, s0, s1, s2
5397 s0-s8
5398 s0-s5, ra
5399
5400 and any permutations of these. */
5401 if ((reglist & 0x3f00ffff) != 0)
a92713e6 5402 return FALSE;
a1d78564
RS
5403
5404 ra = (reglist >> 27) & 0x10;
5405 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5406 }
5407 sregs += 1;
5408 if ((sregs & -sregs) != sregs)
a92713e6 5409 return FALSE;
a1d78564
RS
5410
5411 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
a92713e6 5412 return TRUE;
a1d78564
RS
5413}
5414
364215c8
RS
5415/* OP_ENTRY_EXIT_LIST matcher. */
5416
a92713e6 5417static unsigned int
364215c8 5418match_entry_exit_operand (struct mips_arg_info *arg,
a92713e6 5419 const struct mips_operand *operand)
364215c8
RS
5420{
5421 unsigned int mask;
5422 bfd_boolean is_exit;
5423
5424 /* The format is the same for both ENTRY and EXIT, but the constraints
5425 are different. */
5426 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5427 mask = (is_exit ? 7 << 3 : 0);
a92713e6 5428 do
364215c8
RS
5429 {
5430 unsigned int regno1, regno2;
5431 bfd_boolean is_freg;
5432
a92713e6 5433 if (match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
364215c8 5434 is_freg = FALSE;
a92713e6 5435 else if (match_reg_range (arg, OP_REG_FP, &regno1, &regno2))
364215c8
RS
5436 is_freg = TRUE;
5437 else
a92713e6 5438 return FALSE;
364215c8
RS
5439
5440 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5441 {
5442 mask &= ~(7 << 3);
5443 mask |= (5 + regno2) << 3;
5444 }
5445 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5446 mask |= (regno2 - 3) << 3;
5447 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5448 mask |= (regno2 - 15) << 1;
5449 else if (regno1 == RA && regno2 == RA)
5450 mask |= 1;
5451 else
a92713e6 5452 return FALSE;
364215c8 5453 }
a92713e6
RS
5454 while (match_char (arg, ','));
5455
364215c8 5456 insn_insert_operand (arg->insn, operand, mask);
a92713e6 5457 return TRUE;
364215c8
RS
5458}
5459
5460/* OP_SAVE_RESTORE_LIST matcher. */
5461
a92713e6
RS
5462static bfd_boolean
5463match_save_restore_list_operand (struct mips_arg_info *arg)
364215c8
RS
5464{
5465 unsigned int opcode, args, statics, sregs;
5466 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
364215c8 5467 offsetT frame_size;
364215c8 5468
364215c8
RS
5469 opcode = arg->insn->insn_opcode;
5470 frame_size = 0;
5471 num_frame_sizes = 0;
5472 args = 0;
5473 statics = 0;
5474 sregs = 0;
a92713e6 5475 do
364215c8
RS
5476 {
5477 unsigned int regno1, regno2;
5478
a92713e6 5479 if (arg->token->type == OT_INTEGER)
364215c8
RS
5480 {
5481 /* Handle the frame size. */
1a00e612 5482 if (!match_const_int (arg, &frame_size))
a92713e6 5483 return FALSE;
364215c8 5484 num_frame_sizes += 1;
364215c8
RS
5485 }
5486 else
5487 {
a92713e6
RS
5488 if (!match_reg_range (arg, OP_REG_GP, &regno1, &regno2))
5489 return FALSE;
364215c8
RS
5490
5491 while (regno1 <= regno2)
5492 {
5493 if (regno1 >= 4 && regno1 <= 7)
5494 {
5495 if (num_frame_sizes == 0)
5496 /* args $a0-$a3 */
5497 args |= 1 << (regno1 - 4);
5498 else
5499 /* statics $a0-$a3 */
5500 statics |= 1 << (regno1 - 4);
5501 }
5502 else if (regno1 >= 16 && regno1 <= 23)
5503 /* $s0-$s7 */
5504 sregs |= 1 << (regno1 - 16);
5505 else if (regno1 == 30)
5506 /* $s8 */
5507 sregs |= 1 << 8;
5508 else if (regno1 == 31)
5509 /* Add $ra to insn. */
5510 opcode |= 0x40;
5511 else
a92713e6 5512 return FALSE;
364215c8
RS
5513 regno1 += 1;
5514 if (regno1 == 24)
5515 regno1 = 30;
5516 }
5517 }
364215c8 5518 }
a92713e6 5519 while (match_char (arg, ','));
364215c8
RS
5520
5521 /* Encode args/statics combination. */
5522 if (args & statics)
a92713e6 5523 return FALSE;
364215c8
RS
5524 else if (args == 0xf)
5525 /* All $a0-$a3 are args. */
5526 opcode |= MIPS16_ALL_ARGS << 16;
5527 else if (statics == 0xf)
5528 /* All $a0-$a3 are statics. */
5529 opcode |= MIPS16_ALL_STATICS << 16;
5530 else
5531 {
5532 /* Count arg registers. */
5533 num_args = 0;
5534 while (args & 0x1)
5535 {
5536 args >>= 1;
5537 num_args += 1;
5538 }
5539 if (args != 0)
a92713e6 5540 return FALSE;
364215c8
RS
5541
5542 /* Count static registers. */
5543 num_statics = 0;
5544 while (statics & 0x8)
5545 {
5546 statics = (statics << 1) & 0xf;
5547 num_statics += 1;
5548 }
5549 if (statics != 0)
a92713e6 5550 return FALSE;
364215c8
RS
5551
5552 /* Encode args/statics. */
5553 opcode |= ((num_args << 2) | num_statics) << 16;
5554 }
5555
5556 /* Encode $s0/$s1. */
5557 if (sregs & (1 << 0)) /* $s0 */
5558 opcode |= 0x20;
5559 if (sregs & (1 << 1)) /* $s1 */
5560 opcode |= 0x10;
5561 sregs >>= 2;
5562
5563 /* Encode $s2-$s8. */
5564 num_sregs = 0;
5565 while (sregs & 1)
5566 {
5567 sregs >>= 1;
5568 num_sregs += 1;
5569 }
5570 if (sregs != 0)
a92713e6 5571 return FALSE;
364215c8
RS
5572 opcode |= num_sregs << 24;
5573
5574 /* Encode frame size. */
5575 if (num_frame_sizes == 0)
1a00e612
RS
5576 {
5577 set_insn_error (arg->argnum, _("missing frame size"));
5578 return FALSE;
5579 }
5580 if (num_frame_sizes > 1)
5581 {
5582 set_insn_error (arg->argnum, _("frame size specified twice"));
5583 return FALSE;
5584 }
5585 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5586 {
5587 set_insn_error (arg->argnum, _("invalid frame size"));
5588 return FALSE;
5589 }
5590 if (frame_size != 128 || (opcode >> 16) != 0)
364215c8
RS
5591 {
5592 frame_size /= 8;
5593 opcode |= (((frame_size & 0xf0) << 16)
5594 | (frame_size & 0x0f));
5595 }
5596
364215c8
RS
5597 /* Finally build the instruction. */
5598 if ((opcode >> 16) != 0 || frame_size == 0)
5599 opcode |= MIPS16_EXTEND;
5600 arg->insn->insn_opcode = opcode;
a92713e6 5601 return TRUE;
364215c8
RS
5602}
5603
a1d78564
RS
5604/* OP_MDMX_IMM_REG matcher. */
5605
a92713e6 5606static bfd_boolean
a1d78564 5607match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
a92713e6 5608 const struct mips_operand *operand)
a1d78564 5609{
a92713e6 5610 unsigned int regno, uval;
a1d78564
RS
5611 bfd_boolean is_qh;
5612 const struct mips_opcode *opcode;
5613
5614 /* The mips_opcode records whether this is an octobyte or quadhalf
5615 instruction. Start out with that bit in place. */
5616 opcode = arg->insn->insn_mo;
5617 uval = mips_extract_operand (operand, opcode->match);
5618 is_qh = (uval != 0);
5619
56d438b1 5620 if (arg->token->type == OT_REG)
a1d78564
RS
5621 {
5622 if ((opcode->membership & INSN_5400)
5623 && strcmp (opcode->name, "rzu.ob") == 0)
5624 {
1a00e612
RS
5625 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5626 arg->argnum);
5627 return FALSE;
a1d78564
RS
5628 }
5629
56d438b1
CF
5630 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, &regno))
5631 return FALSE;
5632 ++arg->token;
5633
a1d78564
RS
5634 /* Check whether this is a vector register or a broadcast of
5635 a single element. */
56d438b1 5636 if (arg->token->type == OT_INTEGER_INDEX)
a1d78564 5637 {
56d438b1 5638 if (arg->token->u.index > (is_qh ? 3 : 7))
a1d78564 5639 {
1a00e612
RS
5640 set_insn_error (arg->argnum, _("invalid element selector"));
5641 return FALSE;
a1d78564 5642 }
56d438b1
CF
5643 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5644 ++arg->token;
a1d78564
RS
5645 }
5646 else
5647 {
5648 /* A full vector. */
5649 if ((opcode->membership & INSN_5400)
5650 && (strcmp (opcode->name, "sll.ob") == 0
5651 || strcmp (opcode->name, "srl.ob") == 0))
5652 {
1a00e612
RS
5653 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5654 arg->argnum);
5655 return FALSE;
a1d78564
RS
5656 }
5657
5658 if (is_qh)
5659 uval |= MDMX_FMTSEL_VEC_QH << 5;
5660 else
5661 uval |= MDMX_FMTSEL_VEC_OB << 5;
5662 }
a1d78564
RS
5663 uval |= regno;
5664 }
5665 else
5666 {
5667 offsetT sval;
5668
1a00e612 5669 if (!match_const_int (arg, &sval))
a92713e6 5670 return FALSE;
a1d78564
RS
5671 if (sval < 0 || sval > 31)
5672 {
1a00e612
RS
5673 match_out_of_range (arg);
5674 return FALSE;
a1d78564
RS
5675 }
5676 uval |= (sval & 31);
5677 if (is_qh)
5678 uval |= MDMX_FMTSEL_IMM_QH << 5;
5679 else
5680 uval |= MDMX_FMTSEL_IMM_OB << 5;
5681 }
5682 insn_insert_operand (arg->insn, operand, uval);
a92713e6 5683 return TRUE;
a1d78564
RS
5684}
5685
56d438b1
CF
5686/* OP_IMM_INDEX matcher. */
5687
5688static bfd_boolean
5689match_imm_index_operand (struct mips_arg_info *arg,
5690 const struct mips_operand *operand)
5691{
5692 unsigned int max_val;
5693
5694 if (arg->token->type != OT_INTEGER_INDEX)
5695 return FALSE;
5696
5697 max_val = (1 << operand->size) - 1;
5698 if (arg->token->u.index > max_val)
5699 {
5700 match_out_of_range (arg);
5701 return FALSE;
5702 }
5703 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5704 ++arg->token;
5705 return TRUE;
5706}
5707
5708/* OP_REG_INDEX matcher. */
5709
5710static bfd_boolean
5711match_reg_index_operand (struct mips_arg_info *arg,
5712 const struct mips_operand *operand)
5713{
5714 unsigned int regno;
5715
5716 if (arg->token->type != OT_REG_INDEX)
5717 return FALSE;
5718
5719 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, &regno))
5720 return FALSE;
5721
5722 insn_insert_operand (arg->insn, operand, regno);
5723 ++arg->token;
5724 return TRUE;
5725}
5726
a1d78564
RS
5727/* OP_PC matcher. */
5728
a92713e6
RS
5729static bfd_boolean
5730match_pc_operand (struct mips_arg_info *arg)
a1d78564 5731{
a92713e6
RS
5732 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5733 {
5734 ++arg->token;
5735 return TRUE;
5736 }
5737 return FALSE;
a1d78564
RS
5738}
5739
7361da2c
AB
5740/* OP_NON_ZERO_REG matcher. */
5741
5742static bfd_boolean
5743match_non_zero_reg_operand (struct mips_arg_info *arg,
5744 const struct mips_operand *operand)
5745{
5746 unsigned int regno;
5747
5748 if (!match_reg (arg, OP_REG_GP, &regno))
5749 return FALSE;
5750
5751 if (regno == 0)
5752 return FALSE;
5753
5754 arg->last_regno = regno;
5755 insn_insert_operand (arg->insn, operand, regno);
5756 return TRUE;
5757}
5758
a1d78564
RS
5759/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5760 register that we need to match. */
5761
a92713e6
RS
5762static bfd_boolean
5763match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
a1d78564
RS
5764{
5765 unsigned int regno;
5766
a92713e6 5767 return match_reg (arg, OP_REG_GP, &regno) && regno == other_regno;
a1d78564
RS
5768}
5769
89565f1b
RS
5770/* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5771 the length of the value in bytes (4 for float, 8 for double) and
5772 USING_GPRS says whether the destination is a GPR rather than an FPR.
5773
5774 Return the constant in IMM and OFFSET as follows:
5775
5776 - If the constant should be loaded via memory, set IMM to O_absent and
5777 OFFSET to the memory address.
5778
5779 - Otherwise, if the constant should be loaded into two 32-bit registers,
5780 set IMM to the O_constant to load into the high register and OFFSET
5781 to the corresponding value for the low register.
5782
5783 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5784
5785 These constants only appear as the last operand in an instruction,
5786 and every instruction that accepts them in any variant accepts them
5787 in all variants. This means we don't have to worry about backing out
5788 any changes if the instruction does not match. We just match
5789 unconditionally and report an error if the constant is invalid. */
5790
a92713e6
RS
5791static bfd_boolean
5792match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5793 expressionS *offset, int length, bfd_boolean using_gprs)
89565f1b 5794{
a92713e6 5795 char *p;
89565f1b
RS
5796 segT seg, new_seg;
5797 subsegT subseg;
5798 const char *newname;
a92713e6 5799 unsigned char *data;
89565f1b
RS
5800
5801 /* Where the constant is placed is based on how the MIPS assembler
5802 does things:
5803
5804 length == 4 && using_gprs -- immediate value only
5805 length == 8 && using_gprs -- .rdata or immediate value
5806 length == 4 && !using_gprs -- .lit4 or immediate value
5807 length == 8 && !using_gprs -- .lit8 or immediate value
5808
5809 The .lit4 and .lit8 sections are only used if permitted by the
5810 -G argument. */
a92713e6 5811 if (arg->token->type != OT_FLOAT)
1a00e612
RS
5812 {
5813 set_insn_error (arg->argnum, _("floating-point expression required"));
5814 return FALSE;
5815 }
a92713e6
RS
5816
5817 gas_assert (arg->token->u.flt.length == length);
5818 data = arg->token->u.flt.data;
5819 ++arg->token;
89565f1b
RS
5820
5821 /* Handle 32-bit constants for which an immediate value is best. */
5822 if (length == 4
5823 && (using_gprs
5824 || g_switch_value < 4
5825 || (data[0] == 0 && data[1] == 0)
5826 || (data[2] == 0 && data[3] == 0)))
5827 {
5828 imm->X_op = O_constant;
5829 if (!target_big_endian)
5830 imm->X_add_number = bfd_getl32 (data);
5831 else
5832 imm->X_add_number = bfd_getb32 (data);
5833 offset->X_op = O_absent;
a92713e6 5834 return TRUE;
89565f1b
RS
5835 }
5836
5837 /* Handle 64-bit constants for which an immediate value is best. */
5838 if (length == 8
5839 && !mips_disable_float_construction
351cdf24
MF
5840 /* Constants can only be constructed in GPRs and copied to FPRs if the
5841 GPRs are at least as wide as the FPRs or MTHC1 is available.
5842 Unlike most tests for 32-bit floating-point registers this check
5843 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5844 permit 64-bit moves without MXHC1.
5845 Force the constant into memory otherwise. */
5846 && (using_gprs
5847 || GPR_SIZE == 64
5848 || ISA_HAS_MXHC1 (mips_opts.isa)
5849 || FPR_SIZE == 32)
89565f1b
RS
5850 && ((data[0] == 0 && data[1] == 0)
5851 || (data[2] == 0 && data[3] == 0))
5852 && ((data[4] == 0 && data[5] == 0)
5853 || (data[6] == 0 && data[7] == 0)))
5854 {
5855 /* The value is simple enough to load with a couple of instructions.
5856 If using 32-bit registers, set IMM to the high order 32 bits and
5857 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5858 64 bit constant. */
351cdf24 5859 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
89565f1b
RS
5860 {
5861 imm->X_op = O_constant;
5862 offset->X_op = O_constant;
5863 if (!target_big_endian)
5864 {
5865 imm->X_add_number = bfd_getl32 (data + 4);
5866 offset->X_add_number = bfd_getl32 (data);
5867 }
5868 else
5869 {
5870 imm->X_add_number = bfd_getb32 (data);
5871 offset->X_add_number = bfd_getb32 (data + 4);
5872 }
5873 if (offset->X_add_number == 0)
5874 offset->X_op = O_absent;
5875 }
5876 else
5877 {
5878 imm->X_op = O_constant;
5879 if (!target_big_endian)
5880 imm->X_add_number = bfd_getl64 (data);
5881 else
5882 imm->X_add_number = bfd_getb64 (data);
5883 offset->X_op = O_absent;
5884 }
a92713e6 5885 return TRUE;
89565f1b
RS
5886 }
5887
5888 /* Switch to the right section. */
5889 seg = now_seg;
5890 subseg = now_subseg;
5891 if (length == 4)
5892 {
5893 gas_assert (!using_gprs && g_switch_value >= 4);
5894 newname = ".lit4";
5895 }
5896 else
5897 {
5898 if (using_gprs || g_switch_value < 8)
5899 newname = RDATA_SECTION_NAME;
5900 else
5901 newname = ".lit8";
5902 }
5903
5904 new_seg = subseg_new (newname, (subsegT) 0);
5905 bfd_set_section_flags (stdoutput, new_seg,
5906 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5907 frag_align (length == 4 ? 2 : 3, 0, 0);
5908 if (strncmp (TARGET_OS, "elf", 3) != 0)
5909 record_alignment (new_seg, 4);
5910 else
5911 record_alignment (new_seg, length == 4 ? 2 : 3);
5912 if (seg == now_seg)
1661c76c 5913 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
89565f1b
RS
5914
5915 /* Set the argument to the current address in the section. */
5916 imm->X_op = O_absent;
5917 offset->X_op = O_symbol;
5918 offset->X_add_symbol = symbol_temp_new_now ();
5919 offset->X_add_number = 0;
5920
5921 /* Put the floating point number into the section. */
5922 p = frag_more (length);
5923 memcpy (p, data, length);
5924
5925 /* Switch back to the original section. */
5926 subseg_set (seg, subseg);
a92713e6 5927 return TRUE;
89565f1b
RS
5928}
5929
14daeee3
RS
5930/* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5931 them. */
5932
5933static bfd_boolean
5934match_vu0_suffix_operand (struct mips_arg_info *arg,
5935 const struct mips_operand *operand,
5936 bfd_boolean match_p)
5937{
5938 unsigned int uval;
5939
5940 /* The operand can be an XYZW mask or a single 2-bit channel index
5941 (with X being 0). */
5942 gas_assert (operand->size == 2 || operand->size == 4);
5943
ee5734f0 5944 /* The suffix can be omitted when it is already part of the opcode. */
14daeee3 5945 if (arg->token->type != OT_CHANNELS)
ee5734f0 5946 return match_p;
14daeee3
RS
5947
5948 uval = arg->token->u.channels;
5949 if (operand->size == 2)
5950 {
5951 /* Check that a single bit is set and convert it into a 2-bit index. */
5952 if ((uval & -uval) != uval)
5953 return FALSE;
5954 uval = 4 - ffs (uval);
5955 }
5956
5957 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5958 return FALSE;
5959
5960 ++arg->token;
5961 if (!match_p)
5962 insn_insert_operand (arg->insn, operand, uval);
5963 return TRUE;
5964}
5965
a1d78564
RS
5966/* S is the text seen for ARG. Match it against OPERAND. Return the end
5967 of the argument text if the match is successful, otherwise return null. */
5968
a92713e6 5969static bfd_boolean
a1d78564 5970match_operand (struct mips_arg_info *arg,
a92713e6 5971 const struct mips_operand *operand)
a1d78564
RS
5972{
5973 switch (operand->type)
5974 {
5975 case OP_INT:
a92713e6 5976 return match_int_operand (arg, operand);
a1d78564
RS
5977
5978 case OP_MAPPED_INT:
a92713e6 5979 return match_mapped_int_operand (arg, operand);
a1d78564
RS
5980
5981 case OP_MSB:
a92713e6 5982 return match_msb_operand (arg, operand);
a1d78564
RS
5983
5984 case OP_REG:
0f35dbc4 5985 case OP_OPTIONAL_REG:
a92713e6 5986 return match_reg_operand (arg, operand);
a1d78564
RS
5987
5988 case OP_REG_PAIR:
a92713e6 5989 return match_reg_pair_operand (arg, operand);
a1d78564
RS
5990
5991 case OP_PCREL:
a92713e6 5992 return match_pcrel_operand (arg);
a1d78564
RS
5993
5994 case OP_PERF_REG:
a92713e6 5995 return match_perf_reg_operand (arg, operand);
a1d78564
RS
5996
5997 case OP_ADDIUSP_INT:
a92713e6 5998 return match_addiusp_operand (arg, operand);
a1d78564
RS
5999
6000 case OP_CLO_CLZ_DEST:
a92713e6 6001 return match_clo_clz_dest_operand (arg, operand);
a1d78564
RS
6002
6003 case OP_LWM_SWM_LIST:
a92713e6 6004 return match_lwm_swm_list_operand (arg, operand);
a1d78564
RS
6005
6006 case OP_ENTRY_EXIT_LIST:
a92713e6 6007 return match_entry_exit_operand (arg, operand);
364215c8 6008
a1d78564 6009 case OP_SAVE_RESTORE_LIST:
a92713e6 6010 return match_save_restore_list_operand (arg);
a1d78564
RS
6011
6012 case OP_MDMX_IMM_REG:
a92713e6 6013 return match_mdmx_imm_reg_operand (arg, operand);
a1d78564
RS
6014
6015 case OP_REPEAT_DEST_REG:
a92713e6 6016 return match_tied_reg_operand (arg, arg->dest_regno);
a1d78564
RS
6017
6018 case OP_REPEAT_PREV_REG:
a92713e6 6019 return match_tied_reg_operand (arg, arg->last_regno);
a1d78564
RS
6020
6021 case OP_PC:
a92713e6 6022 return match_pc_operand (arg);
14daeee3
RS
6023
6024 case OP_VU0_SUFFIX:
6025 return match_vu0_suffix_operand (arg, operand, FALSE);
6026
6027 case OP_VU0_MATCH_SUFFIX:
6028 return match_vu0_suffix_operand (arg, operand, TRUE);
56d438b1
CF
6029
6030 case OP_IMM_INDEX:
6031 return match_imm_index_operand (arg, operand);
6032
6033 case OP_REG_INDEX:
6034 return match_reg_index_operand (arg, operand);
7361da2c
AB
6035
6036 case OP_SAME_RS_RT:
6037 return match_same_rs_rt_operand (arg, operand);
6038
6039 case OP_CHECK_PREV:
6040 return match_check_prev_operand (arg, operand);
6041
6042 case OP_NON_ZERO_REG:
6043 return match_non_zero_reg_operand (arg, operand);
a1d78564
RS
6044 }
6045 abort ();
6046}
6047
6048/* ARG is the state after successfully matching an instruction.
6049 Issue any queued-up warnings. */
6050
6051static void
6052check_completed_insn (struct mips_arg_info *arg)
6053{
6054 if (arg->seen_at)
6055 {
6056 if (AT == ATREG)
1661c76c 6057 as_warn (_("used $at without \".set noat\""));
a1d78564 6058 else
1661c76c 6059 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
a1d78564
RS
6060 }
6061}
a1d78564 6062
85fcb30f
RS
6063/* Return true if modifying general-purpose register REG needs a delay. */
6064
6065static bfd_boolean
6066reg_needs_delay (unsigned int reg)
6067{
6068 unsigned long prev_pinfo;
6069
6070 prev_pinfo = history[0].insn_mo->pinfo;
6071 if (!mips_opts.noreorder
67dc82bc 6072 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
43885403 6073 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
85fcb30f
RS
6074 && (gpr_write_mask (&history[0]) & (1 << reg)))
6075 return TRUE;
6076
6077 return FALSE;
6078}
6079
71400594
RS
6080/* Classify an instruction according to the FIX_VR4120_* enumeration.
6081 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6082 by VR4120 errata. */
4d7206a2 6083
71400594
RS
6084static unsigned int
6085classify_vr4120_insn (const char *name)
252b5132 6086{
71400594
RS
6087 if (strncmp (name, "macc", 4) == 0)
6088 return FIX_VR4120_MACC;
6089 if (strncmp (name, "dmacc", 5) == 0)
6090 return FIX_VR4120_DMACC;
6091 if (strncmp (name, "mult", 4) == 0)
6092 return FIX_VR4120_MULT;
6093 if (strncmp (name, "dmult", 5) == 0)
6094 return FIX_VR4120_DMULT;
6095 if (strstr (name, "div"))
6096 return FIX_VR4120_DIV;
6097 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6098 return FIX_VR4120_MTHILO;
6099 return NUM_FIX_VR4120_CLASSES;
6100}
252b5132 6101
a8d14a88
CM
6102#define INSN_ERET 0x42000018
6103#define INSN_DERET 0x4200001f
6104#define INSN_DMULT 0x1c
6105#define INSN_DMULTU 0x1d
ff239038 6106
71400594
RS
6107/* Return the number of instructions that must separate INSN1 and INSN2,
6108 where INSN1 is the earlier instruction. Return the worst-case value
6109 for any INSN2 if INSN2 is null. */
252b5132 6110
71400594
RS
6111static unsigned int
6112insns_between (const struct mips_cl_insn *insn1,
6113 const struct mips_cl_insn *insn2)
6114{
6115 unsigned long pinfo1, pinfo2;
4c260379 6116 unsigned int mask;
71400594 6117
85fcb30f
RS
6118 /* If INFO2 is null, pessimistically assume that all flags are set for
6119 the second instruction. */
71400594
RS
6120 pinfo1 = insn1->insn_mo->pinfo;
6121 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
252b5132 6122
71400594
RS
6123 /* For most targets, write-after-read dependencies on the HI and LO
6124 registers must be separated by at least two instructions. */
6125 if (!hilo_interlocks)
252b5132 6126 {
71400594
RS
6127 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6128 return 2;
6129 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6130 return 2;
6131 }
6132
6133 /* If we're working around r7000 errata, there must be two instructions
6134 between an mfhi or mflo and any instruction that uses the result. */
6135 if (mips_7000_hilo_fix
df58fc94 6136 && !mips_opts.micromips
71400594 6137 && MF_HILO_INSN (pinfo1)
85fcb30f 6138 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
71400594
RS
6139 return 2;
6140
ff239038
CM
6141 /* If we're working around 24K errata, one instruction is required
6142 if an ERET or DERET is followed by a branch instruction. */
df58fc94 6143 if (mips_fix_24k && !mips_opts.micromips)
ff239038
CM
6144 {
6145 if (insn1->insn_opcode == INSN_ERET
6146 || insn1->insn_opcode == INSN_DERET)
6147 {
6148 if (insn2 == NULL
6149 || insn2->insn_opcode == INSN_ERET
6150 || insn2->insn_opcode == INSN_DERET
11625dd8 6151 || delayed_branch_p (insn2))
ff239038
CM
6152 return 1;
6153 }
6154 }
6155
a8d14a88
CM
6156 /* If we're working around PMC RM7000 errata, there must be three
6157 nops between a dmult and a load instruction. */
6158 if (mips_fix_rm7000 && !mips_opts.micromips)
6159 {
6160 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6161 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6162 {
6163 if (pinfo2 & INSN_LOAD_MEMORY)
6164 return 3;
6165 }
6166 }
6167
71400594
RS
6168 /* If working around VR4120 errata, check for combinations that need
6169 a single intervening instruction. */
df58fc94 6170 if (mips_fix_vr4120 && !mips_opts.micromips)
71400594
RS
6171 {
6172 unsigned int class1, class2;
252b5132 6173
71400594
RS
6174 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6175 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
252b5132 6176 {
71400594
RS
6177 if (insn2 == NULL)
6178 return 1;
6179 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6180 if (vr4120_conflicts[class1] & (1 << class2))
6181 return 1;
252b5132 6182 }
71400594
RS
6183 }
6184
df58fc94 6185 if (!HAVE_CODE_COMPRESSION)
71400594
RS
6186 {
6187 /* Check for GPR or coprocessor load delays. All such delays
6188 are on the RT register. */
6189 /* Itbl support may require additional care here. */
67dc82bc 6190 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
43885403 6191 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
252b5132 6192 {
85fcb30f 6193 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
71400594
RS
6194 return 1;
6195 }
6196
6197 /* Check for generic coprocessor hazards.
6198
6199 This case is not handled very well. There is no special
6200 knowledge of CP0 handling, and the coprocessors other than
6201 the floating point unit are not distinguished at all. */
6202 /* Itbl support may require additional care here. FIXME!
6203 Need to modify this to include knowledge about
6204 user specified delays! */
43885403 6205 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
71400594
RS
6206 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6207 {
6208 /* Handle cases where INSN1 writes to a known general coprocessor
6209 register. There must be a one instruction delay before INSN2
6210 if INSN2 reads that register, otherwise no delay is needed. */
4c260379
RS
6211 mask = fpr_write_mask (insn1);
6212 if (mask != 0)
252b5132 6213 {
4c260379 6214 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
71400594 6215 return 1;
252b5132
RH
6216 }
6217 else
6218 {
71400594
RS
6219 /* Read-after-write dependencies on the control registers
6220 require a two-instruction gap. */
6221 if ((pinfo1 & INSN_WRITE_COND_CODE)
6222 && (pinfo2 & INSN_READ_COND_CODE))
6223 return 2;
6224
6225 /* We don't know exactly what INSN1 does. If INSN2 is
6226 also a coprocessor instruction, assume there must be
6227 a one instruction gap. */
6228 if (pinfo2 & INSN_COP)
6229 return 1;
252b5132
RH
6230 }
6231 }
6b76fefe 6232
71400594
RS
6233 /* Check for read-after-write dependencies on the coprocessor
6234 control registers in cases where INSN1 does not need a general
6235 coprocessor delay. This means that INSN1 is a floating point
6236 comparison instruction. */
6237 /* Itbl support may require additional care here. */
6238 else if (!cop_interlocks
6239 && (pinfo1 & INSN_WRITE_COND_CODE)
6240 && (pinfo2 & INSN_READ_COND_CODE))
6241 return 1;
6242 }
6b76fefe 6243
7361da2c
AB
6244 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6245 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6246 and pause. */
6247 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6248 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6249 || (insn2 && delayed_branch_p (insn2))))
6250 return 1;
6251
71400594
RS
6252 return 0;
6253}
6b76fefe 6254
7d8e00cf
RS
6255/* Return the number of nops that would be needed to work around the
6256 VR4130 mflo/mfhi errata if instruction INSN immediately followed
932d1a1b
RS
6257 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6258 that are contained within the first IGNORE instructions of HIST. */
7d8e00cf
RS
6259
6260static int
932d1a1b 6261nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
7d8e00cf
RS
6262 const struct mips_cl_insn *insn)
6263{
4c260379
RS
6264 int i, j;
6265 unsigned int mask;
7d8e00cf
RS
6266
6267 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6268 are not affected by the errata. */
6269 if (insn != 0
6270 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6271 || strcmp (insn->insn_mo->name, "mtlo") == 0
6272 || strcmp (insn->insn_mo->name, "mthi") == 0))
6273 return 0;
6274
6275 /* Search for the first MFLO or MFHI. */
6276 for (i = 0; i < MAX_VR4130_NOPS; i++)
91d6fa6a 6277 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
7d8e00cf
RS
6278 {
6279 /* Extract the destination register. */
4c260379 6280 mask = gpr_write_mask (&hist[i]);
7d8e00cf
RS
6281
6282 /* No nops are needed if INSN reads that register. */
4c260379 6283 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
7d8e00cf
RS
6284 return 0;
6285
6286 /* ...or if any of the intervening instructions do. */
6287 for (j = 0; j < i; j++)
4c260379 6288 if (gpr_read_mask (&hist[j]) & mask)
7d8e00cf
RS
6289 return 0;
6290
932d1a1b
RS
6291 if (i >= ignore)
6292 return MAX_VR4130_NOPS - i;
7d8e00cf
RS
6293 }
6294 return 0;
6295}
6296
134c0c8b
MR
6297#define BASE_REG_EQ(INSN1, INSN2) \
6298 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
15be625d
CM
6299 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6300
6301/* Return the minimum alignment for this store instruction. */
6302
6303static int
6304fix_24k_align_to (const struct mips_opcode *mo)
6305{
6306 if (strcmp (mo->name, "sh") == 0)
6307 return 2;
6308
6309 if (strcmp (mo->name, "swc1") == 0
6310 || strcmp (mo->name, "swc2") == 0
6311 || strcmp (mo->name, "sw") == 0
6312 || strcmp (mo->name, "sc") == 0
6313 || strcmp (mo->name, "s.s") == 0)
6314 return 4;
6315
6316 if (strcmp (mo->name, "sdc1") == 0
6317 || strcmp (mo->name, "sdc2") == 0
6318 || strcmp (mo->name, "s.d") == 0)
6319 return 8;
6320
6321 /* sb, swl, swr */
6322 return 1;
6323}
6324
6325struct fix_24k_store_info
6326 {
6327 /* Immediate offset, if any, for this store instruction. */
6328 short off;
6329 /* Alignment required by this store instruction. */
6330 int align_to;
6331 /* True for register offsets. */
6332 int register_offset;
6333 };
6334
6335/* Comparison function used by qsort. */
6336
6337static int
6338fix_24k_sort (const void *a, const void *b)
6339{
6340 const struct fix_24k_store_info *pos1 = a;
6341 const struct fix_24k_store_info *pos2 = b;
6342
6343 return (pos1->off - pos2->off);
6344}
6345
6346/* INSN is a store instruction. Try to record the store information
6347 in STINFO. Return false if the information isn't known. */
6348
6349static bfd_boolean
6350fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
ab9794cf 6351 const struct mips_cl_insn *insn)
15be625d
CM
6352{
6353 /* The instruction must have a known offset. */
6354 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6355 return FALSE;
6356
6357 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6358 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6359 return TRUE;
6360}
6361
932d1a1b
RS
6362/* Return the number of nops that would be needed to work around the 24k
6363 "lost data on stores during refill" errata if instruction INSN
6364 immediately followed the 2 instructions described by HIST.
6365 Ignore hazards that are contained within the first IGNORE
6366 instructions of HIST.
6367
6368 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6369 for the data cache refills and store data. The following describes
6370 the scenario where the store data could be lost.
6371
6372 * A data cache miss, due to either a load or a store, causing fill
6373 data to be supplied by the memory subsystem
6374 * The first three doublewords of fill data are returned and written
6375 into the cache
6376 * A sequence of four stores occurs in consecutive cycles around the
6377 final doubleword of the fill:
6378 * Store A
6379 * Store B
6380 * Store C
6381 * Zero, One or more instructions
6382 * Store D
6383
6384 The four stores A-D must be to different doublewords of the line that
6385 is being filled. The fourth instruction in the sequence above permits
6386 the fill of the final doubleword to be transferred from the FSB into
6387 the cache. In the sequence above, the stores may be either integer
6388 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6389 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6390 different doublewords on the line. If the floating point unit is
6391 running in 1:2 mode, it is not possible to create the sequence above
6392 using only floating point store instructions.
15be625d
CM
6393
6394 In this case, the cache line being filled is incorrectly marked
6395 invalid, thereby losing the data from any store to the line that
6396 occurs between the original miss and the completion of the five
6397 cycle sequence shown above.
6398
932d1a1b 6399 The workarounds are:
15be625d 6400
932d1a1b
RS
6401 * Run the data cache in write-through mode.
6402 * Insert a non-store instruction between
6403 Store A and Store B or Store B and Store C. */
3739860c 6404
15be625d 6405static int
932d1a1b 6406nops_for_24k (int ignore, const struct mips_cl_insn *hist,
15be625d
CM
6407 const struct mips_cl_insn *insn)
6408{
6409 struct fix_24k_store_info pos[3];
6410 int align, i, base_offset;
6411
932d1a1b
RS
6412 if (ignore >= 2)
6413 return 0;
6414
ab9794cf
RS
6415 /* If the previous instruction wasn't a store, there's nothing to
6416 worry about. */
15be625d
CM
6417 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6418 return 0;
6419
ab9794cf
RS
6420 /* If the instructions after the previous one are unknown, we have
6421 to assume the worst. */
6422 if (!insn)
15be625d
CM
6423 return 1;
6424
ab9794cf
RS
6425 /* Check whether we are dealing with three consecutive stores. */
6426 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6427 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
15be625d
CM
6428 return 0;
6429
6430 /* If we don't know the relationship between the store addresses,
6431 assume the worst. */
ab9794cf 6432 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
15be625d
CM
6433 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6434 return 1;
6435
6436 if (!fix_24k_record_store_info (&pos[0], insn)
6437 || !fix_24k_record_store_info (&pos[1], &hist[0])
6438 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6439 return 1;
6440
6441 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6442
6443 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6444 X bytes and such that the base register + X is known to be aligned
6445 to align bytes. */
6446
6447 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6448 align = 8;
6449 else
6450 {
6451 align = pos[0].align_to;
6452 base_offset = pos[0].off;
6453 for (i = 1; i < 3; i++)
6454 if (align < pos[i].align_to)
6455 {
6456 align = pos[i].align_to;
6457 base_offset = pos[i].off;
6458 }
6459 for (i = 0; i < 3; i++)
6460 pos[i].off -= base_offset;
6461 }
6462
6463 pos[0].off &= ~align + 1;
6464 pos[1].off &= ~align + 1;
6465 pos[2].off &= ~align + 1;
6466
6467 /* If any two stores write to the same chunk, they also write to the
6468 same doubleword. The offsets are still sorted at this point. */
6469 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6470 return 0;
6471
6472 /* A range of at least 9 bytes is needed for the stores to be in
6473 non-overlapping doublewords. */
6474 if (pos[2].off - pos[0].off <= 8)
6475 return 0;
6476
6477 if (pos[2].off - pos[1].off >= 24
6478 || pos[1].off - pos[0].off >= 24
6479 || pos[2].off - pos[0].off >= 32)
6480 return 0;
6481
6482 return 1;
6483}
6484
71400594 6485/* Return the number of nops that would be needed if instruction INSN
91d6fa6a 6486 immediately followed the MAX_NOPS instructions given by HIST,
932d1a1b
RS
6487 where HIST[0] is the most recent instruction. Ignore hazards
6488 between INSN and the first IGNORE instructions in HIST.
6489
6490 If INSN is null, return the worse-case number of nops for any
6491 instruction. */
bdaaa2e1 6492
71400594 6493static int
932d1a1b 6494nops_for_insn (int ignore, const struct mips_cl_insn *hist,
71400594
RS
6495 const struct mips_cl_insn *insn)
6496{
6497 int i, nops, tmp_nops;
bdaaa2e1 6498
71400594 6499 nops = 0;
932d1a1b 6500 for (i = ignore; i < MAX_DELAY_NOPS; i++)
65b02341 6501 {
91d6fa6a 6502 tmp_nops = insns_between (hist + i, insn) - i;
65b02341
RS
6503 if (tmp_nops > nops)
6504 nops = tmp_nops;
6505 }
7d8e00cf 6506
df58fc94 6507 if (mips_fix_vr4130 && !mips_opts.micromips)
7d8e00cf 6508 {
932d1a1b 6509 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
7d8e00cf
RS
6510 if (tmp_nops > nops)
6511 nops = tmp_nops;
6512 }
6513
df58fc94 6514 if (mips_fix_24k && !mips_opts.micromips)
15be625d 6515 {
932d1a1b 6516 tmp_nops = nops_for_24k (ignore, hist, insn);
15be625d
CM
6517 if (tmp_nops > nops)
6518 nops = tmp_nops;
6519 }
6520
71400594
RS
6521 return nops;
6522}
252b5132 6523
71400594 6524/* The variable arguments provide NUM_INSNS extra instructions that
91d6fa6a 6525 might be added to HIST. Return the largest number of nops that
932d1a1b
RS
6526 would be needed after the extended sequence, ignoring hazards
6527 in the first IGNORE instructions. */
252b5132 6528
71400594 6529static int
932d1a1b
RS
6530nops_for_sequence (int num_insns, int ignore,
6531 const struct mips_cl_insn *hist, ...)
71400594
RS
6532{
6533 va_list args;
6534 struct mips_cl_insn buffer[MAX_NOPS];
6535 struct mips_cl_insn *cursor;
6536 int nops;
6537
91d6fa6a 6538 va_start (args, hist);
71400594 6539 cursor = buffer + num_insns;
91d6fa6a 6540 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
71400594
RS
6541 while (cursor > buffer)
6542 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6543
932d1a1b 6544 nops = nops_for_insn (ignore, buffer, NULL);
71400594
RS
6545 va_end (args);
6546 return nops;
6547}
252b5132 6548
71400594
RS
6549/* Like nops_for_insn, but if INSN is a branch, take into account the
6550 worst-case delay for the branch target. */
252b5132 6551
71400594 6552static int
932d1a1b 6553nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
71400594
RS
6554 const struct mips_cl_insn *insn)
6555{
6556 int nops, tmp_nops;
60b63b72 6557
932d1a1b 6558 nops = nops_for_insn (ignore, hist, insn);
11625dd8 6559 if (delayed_branch_p (insn))
71400594 6560 {
932d1a1b 6561 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
14fe068b 6562 hist, insn, get_delay_slot_nop (insn));
71400594
RS
6563 if (tmp_nops > nops)
6564 nops = tmp_nops;
6565 }
11625dd8 6566 else if (compact_branch_p (insn))
71400594 6567 {
932d1a1b 6568 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
71400594
RS
6569 if (tmp_nops > nops)
6570 nops = tmp_nops;
6571 }
6572 return nops;
6573}
6574
c67a084a
NC
6575/* Fix NOP issue: Replace nops by "or at,at,zero". */
6576
6577static void
6578fix_loongson2f_nop (struct mips_cl_insn * ip)
6579{
df58fc94 6580 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
6581 if (strcmp (ip->insn_mo->name, "nop") == 0)
6582 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6583}
6584
6585/* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6586 jr target pc &= 'hffff_ffff_cfff_ffff. */
6587
6588static void
6589fix_loongson2f_jump (struct mips_cl_insn * ip)
6590{
df58fc94 6591 gas_assert (!HAVE_CODE_COMPRESSION);
c67a084a
NC
6592 if (strcmp (ip->insn_mo->name, "j") == 0
6593 || strcmp (ip->insn_mo->name, "jr") == 0
6594 || strcmp (ip->insn_mo->name, "jalr") == 0)
6595 {
6596 int sreg;
6597 expressionS ep;
6598
6599 if (! mips_opts.at)
6600 return;
6601
df58fc94 6602 sreg = EXTRACT_OPERAND (0, RS, *ip);
c67a084a
NC
6603 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6604 return;
6605
6606 ep.X_op = O_constant;
6607 ep.X_add_number = 0xcfff0000;
6608 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6609 ep.X_add_number = 0xffff;
6610 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6611 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6612 }
6613}
6614
6615static void
6616fix_loongson2f (struct mips_cl_insn * ip)
6617{
6618 if (mips_fix_loongson2f_nop)
6619 fix_loongson2f_nop (ip);
6620
6621 if (mips_fix_loongson2f_jump)
6622 fix_loongson2f_jump (ip);
6623}
6624
a4e06468
RS
6625/* IP is a branch that has a delay slot, and we need to fill it
6626 automatically. Return true if we can do that by swapping IP
e407c74b
NC
6627 with the previous instruction.
6628 ADDRESS_EXPR is an operand of the instruction to be used with
6629 RELOC_TYPE. */
a4e06468
RS
6630
6631static bfd_boolean
e407c74b 6632can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
26545944 6633 bfd_reloc_code_real_type *reloc_type)
a4e06468 6634{
2b0c8b40 6635 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
a4e06468 6636 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
9d5de888 6637 unsigned int fpr_read, prev_fpr_write;
a4e06468
RS
6638
6639 /* -O2 and above is required for this optimization. */
6640 if (mips_optimize < 2)
6641 return FALSE;
6642
6643 /* If we have seen .set volatile or .set nomove, don't optimize. */
6644 if (mips_opts.nomove)
6645 return FALSE;
6646
6647 /* We can't swap if the previous instruction's position is fixed. */
6648 if (history[0].fixed_p)
6649 return FALSE;
6650
6651 /* If the previous previous insn was in a .set noreorder, we can't
6652 swap. Actually, the MIPS assembler will swap in this situation.
6653 However, gcc configured -with-gnu-as will generate code like
6654
6655 .set noreorder
6656 lw $4,XXX
6657 .set reorder
6658 INSN
6659 bne $4,$0,foo
6660
6661 in which we can not swap the bne and INSN. If gcc is not configured
6662 -with-gnu-as, it does not output the .set pseudo-ops. */
6663 if (history[1].noreorder_p)
6664 return FALSE;
6665
87333bb7
MR
6666 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6667 This means that the previous instruction was a 4-byte one anyhow. */
a4e06468
RS
6668 if (mips_opts.mips16 && history[0].fixp[0])
6669 return FALSE;
6670
6671 /* If the branch is itself the target of a branch, we can not swap.
6672 We cheat on this; all we check for is whether there is a label on
6673 this instruction. If there are any branches to anything other than
6674 a label, users must use .set noreorder. */
6675 if (seg_info (now_seg)->label_list)
6676 return FALSE;
6677
6678 /* If the previous instruction is in a variant frag other than this
2309ddf2 6679 branch's one, we cannot do the swap. This does not apply to
9301f9c3
MR
6680 MIPS16 code, which uses variant frags for different purposes. */
6681 if (!mips_opts.mips16
a4e06468
RS
6682 && history[0].frag
6683 && history[0].frag->fr_type == rs_machine_dependent)
6684 return FALSE;
6685
bcd530a7
RS
6686 /* We do not swap with instructions that cannot architecturally
6687 be placed in a branch delay slot, such as SYNC or ERET. We
6688 also refrain from swapping with a trap instruction, since it
6689 complicates trap handlers to have the trap instruction be in
6690 a delay slot. */
a4e06468 6691 prev_pinfo = history[0].insn_mo->pinfo;
bcd530a7 6692 if (prev_pinfo & INSN_NO_DELAY_SLOT)
a4e06468
RS
6693 return FALSE;
6694
6695 /* Check for conflicts between the branch and the instructions
6696 before the candidate delay slot. */
6697 if (nops_for_insn (0, history + 1, ip) > 0)
6698 return FALSE;
6699
6700 /* Check for conflicts between the swapped sequence and the
6701 target of the branch. */
6702 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6703 return FALSE;
6704
6705 /* If the branch reads a register that the previous
6706 instruction sets, we can not swap. */
6707 gpr_read = gpr_read_mask (ip);
6708 prev_gpr_write = gpr_write_mask (&history[0]);
6709 if (gpr_read & prev_gpr_write)
6710 return FALSE;
6711
9d5de888
CF
6712 fpr_read = fpr_read_mask (ip);
6713 prev_fpr_write = fpr_write_mask (&history[0]);
6714 if (fpr_read & prev_fpr_write)
6715 return FALSE;
6716
a4e06468
RS
6717 /* If the branch writes a register that the previous
6718 instruction sets, we can not swap. */
6719 gpr_write = gpr_write_mask (ip);
6720 if (gpr_write & prev_gpr_write)
6721 return FALSE;
6722
6723 /* If the branch writes a register that the previous
6724 instruction reads, we can not swap. */
6725 prev_gpr_read = gpr_read_mask (&history[0]);
6726 if (gpr_write & prev_gpr_read)
6727 return FALSE;
6728
6729 /* If one instruction sets a condition code and the
6730 other one uses a condition code, we can not swap. */
6731 pinfo = ip->insn_mo->pinfo;
6732 if ((pinfo & INSN_READ_COND_CODE)
6733 && (prev_pinfo & INSN_WRITE_COND_CODE))
6734 return FALSE;
6735 if ((pinfo & INSN_WRITE_COND_CODE)
6736 && (prev_pinfo & INSN_READ_COND_CODE))
6737 return FALSE;
6738
6739 /* If the previous instruction uses the PC, we can not swap. */
2b0c8b40 6740 prev_pinfo2 = history[0].insn_mo->pinfo2;
26545944 6741 if (prev_pinfo2 & INSN2_READ_PC)
2b0c8b40 6742 return FALSE;
a4e06468 6743
df58fc94
RS
6744 /* If the previous instruction has an incorrect size for a fixed
6745 branch delay slot in microMIPS mode, we cannot swap. */
2309ddf2
MR
6746 pinfo2 = ip->insn_mo->pinfo2;
6747 if (mips_opts.micromips
6748 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6749 && insn_length (history) != 2)
6750 return FALSE;
6751 if (mips_opts.micromips
6752 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6753 && insn_length (history) != 4)
6754 return FALSE;
6755
e407c74b
NC
6756 /* On R5900 short loops need to be fixed by inserting a nop in
6757 the branch delay slots.
6758 A short loop can be terminated too early. */
6759 if (mips_opts.arch == CPU_R5900
6760 /* Check if instruction has a parameter, ignore "j $31". */
6761 && (address_expr != NULL)
6762 /* Parameter must be 16 bit. */
6763 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6764 /* Branch to same segment. */
41065f5e 6765 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
e407c74b 6766 /* Branch to same code fragment. */
41065f5e 6767 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
e407c74b 6768 /* Can only calculate branch offset if value is known. */
41065f5e 6769 && symbol_constant_p (address_expr->X_add_symbol)
e407c74b
NC
6770 /* Check if branch is really conditional. */
6771 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6772 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6773 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6774 {
6775 int distance;
6776 /* Check if loop is shorter than 6 instructions including
6777 branch and delay slot. */
41065f5e 6778 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
e407c74b
NC
6779 if (distance <= 20)
6780 {
6781 int i;
6782 int rv;
6783
6784 rv = FALSE;
6785 /* When the loop includes branches or jumps,
6786 it is not a short loop. */
6787 for (i = 0; i < (distance / 4); i++)
6788 {
6789 if ((history[i].cleared_p)
41065f5e 6790 || delayed_branch_p (&history[i]))
e407c74b
NC
6791 {
6792 rv = TRUE;
6793 break;
6794 }
6795 }
6796 if (rv == FALSE)
6797 {
6798 /* Insert nop after branch to fix short loop. */
6799 return FALSE;
6800 }
6801 }
6802 }
6803
a4e06468
RS
6804 return TRUE;
6805}
6806
e407c74b
NC
6807/* Decide how we should add IP to the instruction stream.
6808 ADDRESS_EXPR is an operand of the instruction to be used with
6809 RELOC_TYPE. */
a4e06468
RS
6810
6811static enum append_method
e407c74b 6812get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
26545944 6813 bfd_reloc_code_real_type *reloc_type)
a4e06468 6814{
a4e06468
RS
6815 /* The relaxed version of a macro sequence must be inherently
6816 hazard-free. */
6817 if (mips_relax.sequence == 2)
6818 return APPEND_ADD;
6819
3b821a28 6820 /* We must not dabble with instructions in a ".set noreorder" block. */
a4e06468
RS
6821 if (mips_opts.noreorder)
6822 return APPEND_ADD;
6823
6824 /* Otherwise, it's our responsibility to fill branch delay slots. */
11625dd8 6825 if (delayed_branch_p (ip))
a4e06468 6826 {
e407c74b
NC
6827 if (!branch_likely_p (ip)
6828 && can_swap_branch_p (ip, address_expr, reloc_type))
a4e06468
RS
6829 return APPEND_SWAP;
6830
6831 if (mips_opts.mips16
6832 && ISA_SUPPORTS_MIPS16E
fc76e730 6833 && gpr_read_mask (ip) != 0)
a4e06468
RS
6834 return APPEND_ADD_COMPACT;
6835
7bd374a4
MR
6836 if (mips_opts.micromips
6837 && ((ip->insn_opcode & 0xffe0) == 0x4580
6838 || (!forced_insn_length
6839 && ((ip->insn_opcode & 0xfc00) == 0xcc00
6840 || (ip->insn_opcode & 0xdc00) == 0x8c00))
6841 || (ip->insn_opcode & 0xdfe00000) == 0x94000000
6842 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000))
6843 return APPEND_ADD_COMPACT;
6844
a4e06468
RS
6845 return APPEND_ADD_WITH_NOP;
6846 }
6847
a4e06468
RS
6848 return APPEND_ADD;
6849}
6850
7bd374a4
MR
6851/* IP is an instruction whose opcode we have just changed, END points
6852 to the end of the opcode table processed. Point IP->insn_mo to the
6853 new opcode's definition. */
ceb94aa5
RS
6854
6855static void
7bd374a4 6856find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
ceb94aa5 6857{
7bd374a4 6858 const struct mips_opcode *mo;
ceb94aa5 6859
ceb94aa5 6860 for (mo = ip->insn_mo; mo < end; mo++)
7bd374a4
MR
6861 if (mo->pinfo != INSN_MACRO
6862 && (ip->insn_opcode & mo->mask) == mo->match)
ceb94aa5
RS
6863 {
6864 ip->insn_mo = mo;
6865 return;
6866 }
6867 abort ();
6868}
6869
7bd374a4
MR
6870/* IP is a MIPS16 instruction whose opcode we have just changed.
6871 Point IP->insn_mo to the new opcode's definition. */
6872
6873static void
6874find_altered_mips16_opcode (struct mips_cl_insn *ip)
6875{
6876 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]);
6877}
6878
6879/* IP is a microMIPS instruction whose opcode we have just changed.
6880 Point IP->insn_mo to the new opcode's definition. */
6881
6882static void
6883find_altered_micromips_opcode (struct mips_cl_insn *ip)
6884{
6885 find_altered_opcode (ip, &micromips_opcodes[bfd_micromips_num_opcodes]);
6886}
6887
df58fc94
RS
6888/* For microMIPS macros, we need to generate a local number label
6889 as the target of branches. */
6890#define MICROMIPS_LABEL_CHAR '\037'
6891static unsigned long micromips_target_label;
6892static char micromips_target_name[32];
6893
6894static char *
6895micromips_label_name (void)
6896{
6897 char *p = micromips_target_name;
6898 char symbol_name_temporary[24];
6899 unsigned long l;
6900 int i;
6901
6902 if (*p)
6903 return p;
6904
6905 i = 0;
6906 l = micromips_target_label;
6907#ifdef LOCAL_LABEL_PREFIX
6908 *p++ = LOCAL_LABEL_PREFIX;
6909#endif
6910 *p++ = 'L';
6911 *p++ = MICROMIPS_LABEL_CHAR;
6912 do
6913 {
6914 symbol_name_temporary[i++] = l % 10 + '0';
6915 l /= 10;
6916 }
6917 while (l != 0);
6918 while (i > 0)
6919 *p++ = symbol_name_temporary[--i];
6920 *p = '\0';
6921
6922 return micromips_target_name;
6923}
6924
6925static void
6926micromips_label_expr (expressionS *label_expr)
6927{
6928 label_expr->X_op = O_symbol;
6929 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6930 label_expr->X_add_number = 0;
6931}
6932
6933static void
6934micromips_label_inc (void)
6935{
6936 micromips_target_label++;
6937 *micromips_target_name = '\0';
6938}
6939
6940static void
6941micromips_add_label (void)
6942{
6943 symbolS *s;
6944
6945 s = colon (micromips_label_name ());
6946 micromips_label_inc ();
f3ded42a 6947 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
df58fc94
RS
6948}
6949
6950/* If assembling microMIPS code, then return the microMIPS reloc
6951 corresponding to the requested one if any. Otherwise return
6952 the reloc unchanged. */
6953
6954static bfd_reloc_code_real_type
6955micromips_map_reloc (bfd_reloc_code_real_type reloc)
6956{
6957 static const bfd_reloc_code_real_type relocs[][2] =
6958 {
6959 /* Keep sorted incrementally by the left-hand key. */
6960 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6961 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6962 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6963 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6964 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6965 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6966 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6967 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6968 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6969 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6970 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6971 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6972 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6973 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6974 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6975 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6976 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6977 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6978 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6979 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6980 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6981 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6982 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6983 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6984 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6985 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6986 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6987 };
6988 bfd_reloc_code_real_type r;
6989 size_t i;
6990
6991 if (!mips_opts.micromips)
6992 return reloc;
6993 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6994 {
6995 r = relocs[i][0];
6996 if (r > reloc)
6997 return reloc;
6998 if (r == reloc)
6999 return relocs[i][1];
7000 }
7001 return reloc;
7002}
7003
b886a2ab
RS
7004/* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7005 Return true on success, storing the resolved value in RESULT. */
7006
7007static bfd_boolean
7008calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
7009 offsetT *result)
7010{
7011 switch (reloc)
7012 {
7013 case BFD_RELOC_MIPS_HIGHEST:
7014 case BFD_RELOC_MICROMIPS_HIGHEST:
7015 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
7016 return TRUE;
7017
7018 case BFD_RELOC_MIPS_HIGHER:
7019 case BFD_RELOC_MICROMIPS_HIGHER:
7020 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
7021 return TRUE;
7022
7023 case BFD_RELOC_HI16_S:
41947d9e 7024 case BFD_RELOC_HI16_S_PCREL:
b886a2ab
RS
7025 case BFD_RELOC_MICROMIPS_HI16_S:
7026 case BFD_RELOC_MIPS16_HI16_S:
7027 *result = ((operand + 0x8000) >> 16) & 0xffff;
7028 return TRUE;
7029
7030 case BFD_RELOC_HI16:
7031 case BFD_RELOC_MICROMIPS_HI16:
7032 case BFD_RELOC_MIPS16_HI16:
7033 *result = (operand >> 16) & 0xffff;
7034 return TRUE;
7035
7036 case BFD_RELOC_LO16:
41947d9e 7037 case BFD_RELOC_LO16_PCREL:
b886a2ab
RS
7038 case BFD_RELOC_MICROMIPS_LO16:
7039 case BFD_RELOC_MIPS16_LO16:
7040 *result = operand & 0xffff;
7041 return TRUE;
7042
7043 case BFD_RELOC_UNUSED:
7044 *result = operand;
7045 return TRUE;
7046
7047 default:
7048 return FALSE;
7049 }
7050}
7051
71400594
RS
7052/* Output an instruction. IP is the instruction information.
7053 ADDRESS_EXPR is an operand of the instruction to be used with
df58fc94
RS
7054 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7055 a macro expansion. */
71400594
RS
7056
7057static void
7058append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
df58fc94 7059 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
71400594 7060{
14fe068b 7061 unsigned long prev_pinfo2, pinfo;
71400594 7062 bfd_boolean relaxed_branch = FALSE;
a4e06468 7063 enum append_method method;
2309ddf2 7064 bfd_boolean relax32;
2b0c8b40 7065 int branch_disp;
71400594 7066
2309ddf2 7067 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
c67a084a
NC
7068 fix_loongson2f (ip);
7069
738f4d98 7070 file_ase_mips16 |= mips_opts.mips16;
df58fc94 7071 file_ase_micromips |= mips_opts.micromips;
738f4d98 7072
df58fc94 7073 prev_pinfo2 = history[0].insn_mo->pinfo2;
71400594 7074 pinfo = ip->insn_mo->pinfo;
df58fc94 7075
7bd374a4
MR
7076 /* Don't raise alarm about `nods' frags as they'll fill in the right
7077 kind of nop in relaxation if required. */
df58fc94
RS
7078 if (mips_opts.micromips
7079 && !expansionp
7bd374a4
MR
7080 && !(history[0].frag
7081 && history[0].frag->fr_type == rs_machine_dependent
7082 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
7083 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
df58fc94
RS
7084 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7085 && micromips_insn_length (ip->insn_mo) != 2)
7086 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7087 && micromips_insn_length (ip->insn_mo) != 4)))
1661c76c 7088 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
df58fc94 7089 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
71400594 7090
15be625d
CM
7091 if (address_expr == NULL)
7092 ip->complete_p = 1;
b886a2ab
RS
7093 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7094 && reloc_type[1] == BFD_RELOC_UNUSED
7095 && reloc_type[2] == BFD_RELOC_UNUSED
15be625d
CM
7096 && address_expr->X_op == O_constant)
7097 {
15be625d
CM
7098 switch (*reloc_type)
7099 {
15be625d 7100 case BFD_RELOC_MIPS_JMP:
df58fc94
RS
7101 {
7102 int shift;
7103
17c6c9d9
MR
7104 /* Shift is 2, unusually, for microMIPS JALX. */
7105 shift = (mips_opts.micromips
7106 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
df58fc94
RS
7107 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7108 as_bad (_("jump to misaligned address (0x%lx)"),
7109 (unsigned long) address_expr->X_add_number);
7110 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7111 & 0x3ffffff);
335574df 7112 ip->complete_p = 1;
df58fc94 7113 }
15be625d
CM
7114 break;
7115
7116 case BFD_RELOC_MIPS16_JMP:
7117 if ((address_expr->X_add_number & 3) != 0)
7118 as_bad (_("jump to misaligned address (0x%lx)"),
7119 (unsigned long) address_expr->X_add_number);
7120 ip->insn_opcode |=
7121 (((address_expr->X_add_number & 0x7c0000) << 3)
7122 | ((address_expr->X_add_number & 0xf800000) >> 7)
7123 | ((address_expr->X_add_number & 0x3fffc) >> 2));
335574df 7124 ip->complete_p = 1;
15be625d
CM
7125 break;
7126
7127 case BFD_RELOC_16_PCREL_S2:
df58fc94
RS
7128 {
7129 int shift;
7130
7131 shift = mips_opts.micromips ? 1 : 2;
7132 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7133 as_bad (_("branch to misaligned address (0x%lx)"),
7134 (unsigned long) address_expr->X_add_number);
7135 if (!mips_relax_branch)
7136 {
7137 if ((address_expr->X_add_number + (1 << (shift + 15)))
7138 & ~((1 << (shift + 16)) - 1))
7139 as_bad (_("branch address range overflow (0x%lx)"),
7140 (unsigned long) address_expr->X_add_number);
7141 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7142 & 0xffff);
7143 }
df58fc94 7144 }
15be625d
CM
7145 break;
7146
7361da2c
AB
7147 case BFD_RELOC_MIPS_21_PCREL_S2:
7148 {
7149 int shift;
7150
7151 shift = 2;
7152 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7153 as_bad (_("branch to misaligned address (0x%lx)"),
7154 (unsigned long) address_expr->X_add_number);
7155 if ((address_expr->X_add_number + (1 << (shift + 20)))
7156 & ~((1 << (shift + 21)) - 1))
7157 as_bad (_("branch address range overflow (0x%lx)"),
7158 (unsigned long) address_expr->X_add_number);
7159 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7160 & 0x1fffff);
7161 }
7162 break;
7163
7164 case BFD_RELOC_MIPS_26_PCREL_S2:
7165 {
7166 int shift;
7167
7168 shift = 2;
7169 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7170 as_bad (_("branch to misaligned address (0x%lx)"),
7171 (unsigned long) address_expr->X_add_number);
7172 if ((address_expr->X_add_number + (1 << (shift + 25)))
7173 & ~((1 << (shift + 26)) - 1))
7174 as_bad (_("branch address range overflow (0x%lx)"),
7175 (unsigned long) address_expr->X_add_number);
7176 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7177 & 0x3ffffff);
7178 }
7179 break;
7180
15be625d 7181 default:
b886a2ab
RS
7182 {
7183 offsetT value;
7184
7185 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7186 &value))
7187 {
7188 ip->insn_opcode |= value & 0xffff;
7189 ip->complete_p = 1;
7190 }
7191 }
7192 break;
7193 }
15be625d
CM
7194 }
7195
71400594
RS
7196 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7197 {
7198 /* There are a lot of optimizations we could do that we don't.
7199 In particular, we do not, in general, reorder instructions.
7200 If you use gcc with optimization, it will reorder
7201 instructions and generally do much more optimization then we
7202 do here; repeating all that work in the assembler would only
7203 benefit hand written assembly code, and does not seem worth
7204 it. */
7205 int nops = (mips_optimize == 0
932d1a1b
RS
7206 ? nops_for_insn (0, history, NULL)
7207 : nops_for_insn_or_target (0, history, ip));
71400594 7208 if (nops > 0)
252b5132
RH
7209 {
7210 fragS *old_frag;
7211 unsigned long old_frag_offset;
7212 int i;
252b5132
RH
7213
7214 old_frag = frag_now;
7215 old_frag_offset = frag_now_fix ();
7216
7217 for (i = 0; i < nops; i++)
14fe068b
RS
7218 add_fixed_insn (NOP_INSN);
7219 insert_into_history (0, nops, NOP_INSN);
252b5132
RH
7220
7221 if (listing)
7222 {
7223 listing_prev_line ();
7224 /* We may be at the start of a variant frag. In case we
7225 are, make sure there is enough space for the frag
7226 after the frags created by listing_prev_line. The
7227 argument to frag_grow here must be at least as large
7228 as the argument to all other calls to frag_grow in
7229 this file. We don't have to worry about being in the
7230 middle of a variant frag, because the variants insert
7231 all needed nop instructions themselves. */
7232 frag_grow (40);
7233 }
7234
462427c4 7235 mips_move_text_labels ();
252b5132
RH
7236
7237#ifndef NO_ECOFF_DEBUGGING
7238 if (ECOFF_DEBUGGING)
7239 ecoff_fix_loc (old_frag, old_frag_offset);
7240#endif
7241 }
71400594
RS
7242 }
7243 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7244 {
932d1a1b
RS
7245 int nops;
7246
7247 /* Work out how many nops in prev_nop_frag are needed by IP,
7248 ignoring hazards generated by the first prev_nop_frag_since
7249 instructions. */
7250 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
9c2799c2 7251 gas_assert (nops <= prev_nop_frag_holds);
252b5132 7252
71400594
RS
7253 /* Enforce NOPS as a minimum. */
7254 if (nops > prev_nop_frag_required)
7255 prev_nop_frag_required = nops;
252b5132 7256
71400594
RS
7257 if (prev_nop_frag_holds == prev_nop_frag_required)
7258 {
7259 /* Settle for the current number of nops. Update the history
7260 accordingly (for the benefit of any future .set reorder code). */
7261 prev_nop_frag = NULL;
7262 insert_into_history (prev_nop_frag_since,
7263 prev_nop_frag_holds, NOP_INSN);
7264 }
7265 else
7266 {
7267 /* Allow this instruction to replace one of the nops that was
7268 tentatively added to prev_nop_frag. */
df58fc94 7269 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
71400594
RS
7270 prev_nop_frag_holds--;
7271 prev_nop_frag_since++;
252b5132
RH
7272 }
7273 }
7274
e407c74b 7275 method = get_append_method (ip, address_expr, reloc_type);
2b0c8b40 7276 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
a4e06468 7277
e410add4
RS
7278 dwarf2_emit_insn (0);
7279 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7280 so "move" the instruction address accordingly.
7281
7282 Also, it doesn't seem appropriate for the assembler to reorder .loc
7283 entries. If this instruction is a branch that we are going to swap
7284 with the previous instruction, the two instructions should be
7285 treated as a unit, and the debug information for both instructions
7286 should refer to the start of the branch sequence. Using the
7287 current position is certainly wrong when swapping a 32-bit branch
7288 and a 16-bit delay slot, since the current position would then be
7289 in the middle of a branch. */
7290 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
58e2ea4d 7291
df58fc94
RS
7292 relax32 = (mips_relax_branch
7293 /* Don't try branch relaxation within .set nomacro, or within
7294 .set noat if we use $at for PIC computations. If it turns
7295 out that the branch was out-of-range, we'll get an error. */
7296 && !mips_opts.warn_about_macros
7297 && (mips_opts.at || mips_pic == NO_PIC)
3bf0dbfb
MR
7298 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7299 as they have no complementing branches. */
7300 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
df58fc94
RS
7301
7302 if (!HAVE_CODE_COMPRESSION
7303 && address_expr
7304 && relax32
0b25d3e6 7305 && *reloc_type == BFD_RELOC_16_PCREL_S2
11625dd8 7306 && delayed_branch_p (ip))
4a6a3df4 7307 {
895921c9 7308 relaxed_branch = TRUE;
1e915849
RS
7309 add_relaxed_insn (ip, (relaxed_branch_length
7310 (NULL, NULL,
11625dd8
RS
7311 uncond_branch_p (ip) ? -1
7312 : branch_likely_p (ip) ? 1
1e915849
RS
7313 : 0)), 4,
7314 RELAX_BRANCH_ENCODE
66b3e8da 7315 (AT,
11625dd8
RS
7316 uncond_branch_p (ip),
7317 branch_likely_p (ip),
1e915849
RS
7318 pinfo & INSN_WRITE_GPR_31,
7319 0),
7320 address_expr->X_add_symbol,
7321 address_expr->X_add_number);
4a6a3df4
AO
7322 *reloc_type = BFD_RELOC_UNUSED;
7323 }
df58fc94
RS
7324 else if (mips_opts.micromips
7325 && address_expr
7326 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7327 || *reloc_type > BFD_RELOC_UNUSED)
40209cad
MR
7328 && (delayed_branch_p (ip) || compact_branch_p (ip))
7329 /* Don't try branch relaxation when users specify
7330 16-bit/32-bit instructions. */
7331 && !forced_insn_length)
df58fc94 7332 {
7bd374a4
MR
7333 bfd_boolean relax16 = (method != APPEND_ADD_COMPACT
7334 && *reloc_type > BFD_RELOC_UNUSED);
df58fc94 7335 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
11625dd8 7336 int uncond = uncond_branch_p (ip) ? -1 : 0;
7bd374a4
MR
7337 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
7338 int nods = method == APPEND_ADD_WITH_NOP;
df58fc94 7339 int al = pinfo & INSN_WRITE_GPR_31;
7bd374a4 7340 int length32 = nods ? 8 : 4;
df58fc94
RS
7341
7342 gas_assert (address_expr != NULL);
7343 gas_assert (!mips_relax.sequence);
7344
2b0c8b40 7345 relaxed_branch = TRUE;
7bd374a4
MR
7346 if (nods)
7347 method = APPEND_ADD;
7348 if (relax32)
7349 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7350 add_relaxed_insn (ip, length32, relax16 ? 2 : 4,
8484fb75 7351 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32,
7bd374a4 7352 uncond, compact, al, nods,
40209cad 7353 relax32, 0, 0),
df58fc94
RS
7354 address_expr->X_add_symbol,
7355 address_expr->X_add_number);
7356 *reloc_type = BFD_RELOC_UNUSED;
7357 }
7358 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
252b5132 7359 {
88a7ef16
MR
7360 symbolS *symbol;
7361 offsetT offset;
7362
252b5132 7363 /* We need to set up a variant frag. */
df58fc94 7364 gas_assert (address_expr != NULL);
88a7ef16
MR
7365 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7366 symbol created by `make_expr_symbol' may not get a necessary
7367 external relocation produced. */
7368 if (address_expr->X_op == O_symbol)
7369 {
7370 symbol = address_expr->X_add_symbol;
7371 offset = address_expr->X_add_number;
7372 }
7373 else
7374 {
7375 symbol = make_expr_symbol (address_expr);
7376 offset = 0;
7377 }
1e915849
RS
7378 add_relaxed_insn (ip, 4, 0,
7379 RELAX_MIPS16_ENCODE
7380 (*reloc_type - BFD_RELOC_UNUSED,
df58fc94 7381 forced_insn_length == 2, forced_insn_length == 4,
11625dd8 7382 delayed_branch_p (&history[0]),
1e915849 7383 history[0].mips16_absolute_jump_p),
88a7ef16 7384 symbol, offset);
252b5132 7385 }
5c04167a 7386 else if (mips_opts.mips16 && insn_length (ip) == 2)
9497f5ac 7387 {
11625dd8 7388 if (!delayed_branch_p (ip))
b8ee1a6e
DU
7389 /* Make sure there is enough room to swap this instruction with
7390 a following jump instruction. */
7391 frag_grow (6);
1e915849 7392 add_fixed_insn (ip);
252b5132
RH
7393 }
7394 else
7395 {
7396 if (mips_opts.mips16
7397 && mips_opts.noreorder
11625dd8 7398 && delayed_branch_p (&history[0]))
252b5132
RH
7399 as_warn (_("extended instruction in delay slot"));
7400
4d7206a2
RS
7401 if (mips_relax.sequence)
7402 {
7403 /* If we've reached the end of this frag, turn it into a variant
7404 frag and record the information for the instructions we've
7405 written so far. */
7406 if (frag_room () < 4)
7407 relax_close_frag ();
df58fc94 7408 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4d7206a2
RS
7409 }
7410
584892a6 7411 if (mips_relax.sequence != 2)
df58fc94
RS
7412 {
7413 if (mips_macro_warning.first_insn_sizes[0] == 0)
7414 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7415 mips_macro_warning.sizes[0] += insn_length (ip);
7416 mips_macro_warning.insns[0]++;
7417 }
584892a6 7418 if (mips_relax.sequence != 1)
df58fc94
RS
7419 {
7420 if (mips_macro_warning.first_insn_sizes[1] == 0)
7421 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7422 mips_macro_warning.sizes[1] += insn_length (ip);
7423 mips_macro_warning.insns[1]++;
7424 }
584892a6 7425
1e915849
RS
7426 if (mips_opts.mips16)
7427 {
7428 ip->fixed_p = 1;
7429 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7430 }
7431 add_fixed_insn (ip);
252b5132
RH
7432 }
7433
9fe77896 7434 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
252b5132 7435 {
df58fc94 7436 bfd_reloc_code_real_type final_type[3];
2309ddf2 7437 reloc_howto_type *howto0;
9fe77896
RS
7438 reloc_howto_type *howto;
7439 int i;
34ce925e 7440
df58fc94
RS
7441 /* Perform any necessary conversion to microMIPS relocations
7442 and find out how many relocations there actually are. */
7443 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7444 final_type[i] = micromips_map_reloc (reloc_type[i]);
7445
9fe77896
RS
7446 /* In a compound relocation, it is the final (outermost)
7447 operator that determines the relocated field. */
2309ddf2 7448 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
e8044f35
RS
7449 if (!howto)
7450 abort ();
2309ddf2
MR
7451
7452 if (i > 1)
7453 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
9fe77896
RS
7454 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7455 bfd_get_reloc_size (howto),
7456 address_expr,
2309ddf2
MR
7457 howto0 && howto0->pc_relative,
7458 final_type[0]);
9fe77896
RS
7459
7460 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2309ddf2 7461 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
9fe77896
RS
7462 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7463
7464 /* These relocations can have an addend that won't fit in
7465 4 octets for 64bit assembly. */
bad1aba3 7466 if (GPR_SIZE == 64
9fe77896
RS
7467 && ! howto->partial_inplace
7468 && (reloc_type[0] == BFD_RELOC_16
7469 || reloc_type[0] == BFD_RELOC_32
7470 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7471 || reloc_type[0] == BFD_RELOC_GPREL16
7472 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7473 || reloc_type[0] == BFD_RELOC_GPREL32
7474 || reloc_type[0] == BFD_RELOC_64
7475 || reloc_type[0] == BFD_RELOC_CTOR
7476 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7477 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7478 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7479 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7480 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7481 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7482 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7483 || hi16_reloc_p (reloc_type[0])
7484 || lo16_reloc_p (reloc_type[0])))
7485 ip->fixp[0]->fx_no_overflow = 1;
7486
ddaf2c41
MR
7487 /* These relocations can have an addend that won't fit in 2 octets. */
7488 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7489 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7490 ip->fixp[0]->fx_no_overflow = 1;
7491
9fe77896
RS
7492 if (mips_relax.sequence)
7493 {
7494 if (mips_relax.first_fixup == 0)
7495 mips_relax.first_fixup = ip->fixp[0];
7496 }
7497 else if (reloc_needs_lo_p (*reloc_type))
7498 {
7499 struct mips_hi_fixup *hi_fixup;
7500
7501 /* Reuse the last entry if it already has a matching %lo. */
7502 hi_fixup = mips_hi_fixup_list;
7503 if (hi_fixup == 0
7504 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4d7206a2 7505 {
325801bd 7506 hi_fixup = XNEW (struct mips_hi_fixup);
9fe77896
RS
7507 hi_fixup->next = mips_hi_fixup_list;
7508 mips_hi_fixup_list = hi_fixup;
4d7206a2 7509 }
9fe77896
RS
7510 hi_fixup->fixp = ip->fixp[0];
7511 hi_fixup->seg = now_seg;
7512 }
252b5132 7513
9fe77896
RS
7514 /* Add fixups for the second and third relocations, if given.
7515 Note that the ABI allows the second relocation to be
7516 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7517 moment we only use RSS_UNDEF, but we could add support
7518 for the others if it ever becomes necessary. */
7519 for (i = 1; i < 3; i++)
7520 if (reloc_type[i] != BFD_RELOC_UNUSED)
7521 {
7522 ip->fixp[i] = fix_new (ip->frag, ip->where,
7523 ip->fixp[0]->fx_size, NULL, 0,
df58fc94 7524 FALSE, final_type[i]);
f6688943 7525
9fe77896
RS
7526 /* Use fx_tcbit to mark compound relocs. */
7527 ip->fixp[0]->fx_tcbit = 1;
7528 ip->fixp[i]->fx_tcbit = 1;
7529 }
252b5132 7530 }
252b5132
RH
7531
7532 /* Update the register mask information. */
4c260379
RS
7533 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7534 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
252b5132 7535
a4e06468 7536 switch (method)
252b5132 7537 {
a4e06468
RS
7538 case APPEND_ADD:
7539 insert_into_history (0, 1, ip);
7540 break;
7541
7542 case APPEND_ADD_WITH_NOP:
14fe068b
RS
7543 {
7544 struct mips_cl_insn *nop;
7545
7546 insert_into_history (0, 1, ip);
7547 nop = get_delay_slot_nop (ip);
7548 add_fixed_insn (nop);
7549 insert_into_history (0, 1, nop);
7550 if (mips_relax.sequence)
7551 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7552 }
a4e06468
RS
7553 break;
7554
7555 case APPEND_ADD_COMPACT:
7556 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7bd374a4
MR
7557 if (mips_opts.mips16)
7558 {
7559 ip->insn_opcode |= 0x0080;
7560 find_altered_mips16_opcode (ip);
7561 }
7562 /* Convert microMIPS instructions. */
7563 else if (mips_opts.micromips)
7564 {
7565 /* jr16->jrc */
7566 if ((ip->insn_opcode & 0xffe0) == 0x4580)
7567 ip->insn_opcode |= 0x0020;
7568 /* b16->bc */
7569 else if ((ip->insn_opcode & 0xfc00) == 0xcc00)
7570 ip->insn_opcode = 0x40e00000;
7571 /* beqz16->beqzc, bnez16->bnezc */
7572 else if ((ip->insn_opcode & 0xdc00) == 0x8c00)
7573 {
7574 unsigned long regno;
7575
7576 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD;
7577 regno &= MICROMIPSOP_MASK_MD;
7578 regno = micromips_to_32_reg_d_map[regno];
7579 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000)
7580 | (regno << MICROMIPSOP_SH_RS)
7581 | 0x40a00000) ^ 0x00400000;
7582 }
7583 /* beqz->beqzc, bnez->bnezc */
7584 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000)
7585 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000)
7586 | ((ip->insn_opcode >> 7) & 0x00400000)
7587 | 0x40a00000) ^ 0x00400000;
7588 /* beq $0->beqzc, bne $0->bnezc */
7589 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000)
7590 ip->insn_opcode = (((ip->insn_opcode >>
7591 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS))
7592 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))
7593 | ((ip->insn_opcode >> 7) & 0x00400000)
7594 | 0x40a00000) ^ 0x00400000;
7595 else
7596 abort ();
7597 find_altered_micromips_opcode (ip);
7598 }
7599 else
7600 abort ();
a4e06468
RS
7601 install_insn (ip);
7602 insert_into_history (0, 1, ip);
7603 break;
7604
7605 case APPEND_SWAP:
7606 {
7607 struct mips_cl_insn delay = history[0];
99e7978b
MF
7608
7609 if (relaxed_branch || delay.frag != ip->frag)
a4e06468
RS
7610 {
7611 /* Add the delay slot instruction to the end of the
7612 current frag and shrink the fixed part of the
7613 original frag. If the branch occupies the tail of
7614 the latter, move it backwards to cover the gap. */
2b0c8b40 7615 delay.frag->fr_fix -= branch_disp;
a4e06468 7616 if (delay.frag == ip->frag)
2b0c8b40 7617 move_insn (ip, ip->frag, ip->where - branch_disp);
a4e06468
RS
7618 add_fixed_insn (&delay);
7619 }
7620 else
7621 {
5e35670b
MR
7622 /* If this is not a relaxed branch and we are in the
7623 same frag, then just swap the instructions. */
7624 move_insn (ip, delay.frag, delay.where);
7625 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
a4e06468
RS
7626 }
7627 history[0] = *ip;
7628 delay.fixed_p = 1;
7629 insert_into_history (0, 1, &delay);
7630 }
7631 break;
252b5132
RH
7632 }
7633
13408f1e 7634 /* If we have just completed an unconditional branch, clear the history. */
11625dd8
RS
7635 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7636 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
e407c74b
NC
7637 {
7638 unsigned int i;
7639
79850f26 7640 mips_no_prev_insn ();
13408f1e 7641
e407c74b 7642 for (i = 0; i < ARRAY_SIZE (history); i++)
79850f26 7643 history[i].cleared_p = 1;
e407c74b
NC
7644 }
7645
df58fc94
RS
7646 /* We need to emit a label at the end of branch-likely macros. */
7647 if (emit_branch_likely_macro)
7648 {
7649 emit_branch_likely_macro = FALSE;
7650 micromips_add_label ();
7651 }
7652
252b5132
RH
7653 /* We just output an insn, so the next one doesn't have a label. */
7654 mips_clear_insn_labels ();
252b5132
RH
7655}
7656
e407c74b
NC
7657/* Forget that there was any previous instruction or label.
7658 When BRANCH is true, the branch history is also flushed. */
252b5132
RH
7659
7660static void
7d10b47d 7661mips_no_prev_insn (void)
252b5132 7662{
7d10b47d
RS
7663 prev_nop_frag = NULL;
7664 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
252b5132
RH
7665 mips_clear_insn_labels ();
7666}
7667
7d10b47d
RS
7668/* This function must be called before we emit something other than
7669 instructions. It is like mips_no_prev_insn except that it inserts
7670 any NOPS that might be needed by previous instructions. */
252b5132 7671
7d10b47d
RS
7672void
7673mips_emit_delays (void)
252b5132
RH
7674{
7675 if (! mips_opts.noreorder)
7676 {
932d1a1b 7677 int nops = nops_for_insn (0, history, NULL);
252b5132
RH
7678 if (nops > 0)
7679 {
7d10b47d
RS
7680 while (nops-- > 0)
7681 add_fixed_insn (NOP_INSN);
462427c4 7682 mips_move_text_labels ();
7d10b47d
RS
7683 }
7684 }
7685 mips_no_prev_insn ();
7686}
7687
7688/* Start a (possibly nested) noreorder block. */
7689
7690static void
7691start_noreorder (void)
7692{
7693 if (mips_opts.noreorder == 0)
7694 {
7695 unsigned int i;
7696 int nops;
7697
7698 /* None of the instructions before the .set noreorder can be moved. */
7699 for (i = 0; i < ARRAY_SIZE (history); i++)
7700 history[i].fixed_p = 1;
7701
7702 /* Insert any nops that might be needed between the .set noreorder
7703 block and the previous instructions. We will later remove any
7704 nops that turn out not to be needed. */
932d1a1b 7705 nops = nops_for_insn (0, history, NULL);
7d10b47d
RS
7706 if (nops > 0)
7707 {
7708 if (mips_optimize != 0)
252b5132
RH
7709 {
7710 /* Record the frag which holds the nop instructions, so
7711 that we can remove them if we don't need them. */
df58fc94 7712 frag_grow (nops * NOP_INSN_SIZE);
252b5132
RH
7713 prev_nop_frag = frag_now;
7714 prev_nop_frag_holds = nops;
7715 prev_nop_frag_required = 0;
7716 prev_nop_frag_since = 0;
7717 }
7718
7719 for (; nops > 0; --nops)
1e915849 7720 add_fixed_insn (NOP_INSN);
252b5132 7721
7d10b47d
RS
7722 /* Move on to a new frag, so that it is safe to simply
7723 decrease the size of prev_nop_frag. */
7724 frag_wane (frag_now);
7725 frag_new (0);
462427c4 7726 mips_move_text_labels ();
252b5132 7727 }
df58fc94 7728 mips_mark_labels ();
7d10b47d 7729 mips_clear_insn_labels ();
252b5132 7730 }
7d10b47d
RS
7731 mips_opts.noreorder++;
7732 mips_any_noreorder = 1;
7733}
252b5132 7734
7d10b47d 7735/* End a nested noreorder block. */
252b5132 7736
7d10b47d
RS
7737static void
7738end_noreorder (void)
7739{
7740 mips_opts.noreorder--;
7741 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7742 {
7743 /* Commit to inserting prev_nop_frag_required nops and go back to
7744 handling nop insertion the .set reorder way. */
7745 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
df58fc94 7746 * NOP_INSN_SIZE);
7d10b47d
RS
7747 insert_into_history (prev_nop_frag_since,
7748 prev_nop_frag_required, NOP_INSN);
7749 prev_nop_frag = NULL;
7750 }
252b5132
RH
7751}
7752
97d87491
RS
7753/* Sign-extend 32-bit mode constants that have bit 31 set and all
7754 higher bits unset. */
7755
7756static void
7757normalize_constant_expr (expressionS *ex)
7758{
7759 if (ex->X_op == O_constant
7760 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7761 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7762 - 0x80000000);
7763}
7764
7765/* Sign-extend 32-bit mode address offsets that have bit 31 set and
7766 all higher bits unset. */
7767
7768static void
7769normalize_address_expr (expressionS *ex)
7770{
7771 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7772 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7773 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7774 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7775 - 0x80000000);
7776}
7777
7778/* Try to match TOKENS against OPCODE, storing the result in INSN.
7779 Return true if the match was successful.
7780
7781 OPCODE_EXTRA is a value that should be ORed into the opcode
7782 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7783 there are more alternatives after OPCODE and SOFT_MATCH is
7784 as for mips_arg_info. */
7785
7786static bfd_boolean
7787match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7788 struct mips_operand_token *tokens, unsigned int opcode_extra,
60f20e8b 7789 bfd_boolean lax_match, bfd_boolean complete_p)
97d87491
RS
7790{
7791 const char *args;
7792 struct mips_arg_info arg;
7793 const struct mips_operand *operand;
7794 char c;
7795
7796 imm_expr.X_op = O_absent;
97d87491
RS
7797 offset_expr.X_op = O_absent;
7798 offset_reloc[0] = BFD_RELOC_UNUSED;
7799 offset_reloc[1] = BFD_RELOC_UNUSED;
7800 offset_reloc[2] = BFD_RELOC_UNUSED;
7801
7802 create_insn (insn, opcode);
60f20e8b
RS
7803 /* When no opcode suffix is specified, assume ".xyzw". */
7804 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7805 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7806 else
7807 insn->insn_opcode |= opcode_extra;
97d87491
RS
7808 memset (&arg, 0, sizeof (arg));
7809 arg.insn = insn;
7810 arg.token = tokens;
7811 arg.argnum = 1;
7812 arg.last_regno = ILLEGAL_REG;
7813 arg.dest_regno = ILLEGAL_REG;
60f20e8b 7814 arg.lax_match = lax_match;
97d87491
RS
7815 for (args = opcode->args;; ++args)
7816 {
7817 if (arg.token->type == OT_END)
7818 {
7819 /* Handle unary instructions in which only one operand is given.
7820 The source is then the same as the destination. */
7821 if (arg.opnum == 1 && *args == ',')
7822 {
7823 operand = (mips_opts.micromips
7824 ? decode_micromips_operand (args + 1)
7825 : decode_mips_operand (args + 1));
7826 if (operand && mips_optional_operand_p (operand))
7827 {
7828 arg.token = tokens;
7829 arg.argnum = 1;
7830 continue;
7831 }
7832 }
7833
7834 /* Treat elided base registers as $0. */
7835 if (strcmp (args, "(b)") == 0)
7836 args += 3;
7837
7838 if (args[0] == '+')
7839 switch (args[1])
7840 {
7841 case 'K':
7842 case 'N':
7843 /* The register suffix is optional. */
7844 args += 2;
7845 break;
7846 }
7847
7848 /* Fail the match if there were too few operands. */
7849 if (*args)
7850 return FALSE;
7851
7852 /* Successful match. */
60f20e8b
RS
7853 if (!complete_p)
7854 return TRUE;
e3de51ce 7855 clear_insn_error ();
97d87491
RS
7856 if (arg.dest_regno == arg.last_regno
7857 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7858 {
7859 if (arg.opnum == 2)
e3de51ce 7860 set_insn_error
1661c76c 7861 (0, _("source and destination must be different"));
97d87491 7862 else if (arg.last_regno == 31)
e3de51ce 7863 set_insn_error
1661c76c 7864 (0, _("a destination register must be supplied"));
97d87491 7865 }
173d3447
CF
7866 else if (arg.last_regno == 31
7867 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7868 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7869 set_insn_error (0, _("the source register must not be $31"));
97d87491
RS
7870 check_completed_insn (&arg);
7871 return TRUE;
7872 }
7873
7874 /* Fail the match if the line has too many operands. */
7875 if (*args == 0)
7876 return FALSE;
7877
7878 /* Handle characters that need to match exactly. */
7879 if (*args == '(' || *args == ')' || *args == ',')
7880 {
7881 if (match_char (&arg, *args))
7882 continue;
7883 return FALSE;
7884 }
7885 if (*args == '#')
7886 {
7887 ++args;
7888 if (arg.token->type == OT_DOUBLE_CHAR
7889 && arg.token->u.ch == *args)
7890 {
7891 ++arg.token;
7892 continue;
7893 }
7894 return FALSE;
7895 }
7896
7897 /* Handle special macro operands. Work out the properties of
7898 other operands. */
7899 arg.opnum += 1;
97d87491
RS
7900 switch (*args)
7901 {
7361da2c
AB
7902 case '-':
7903 switch (args[1])
7904 {
7905 case 'A':
7906 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
7907 break;
7908
7909 case 'B':
7910 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
7911 break;
7912 }
7913 break;
7914
97d87491
RS
7915 case '+':
7916 switch (args[1])
7917 {
97d87491
RS
7918 case 'i':
7919 *offset_reloc = BFD_RELOC_MIPS_JMP;
7920 break;
7361da2c
AB
7921
7922 case '\'':
7923 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
7924 break;
7925
7926 case '\"':
7927 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
7928 break;
97d87491
RS
7929 }
7930 break;
7931
97d87491 7932 case 'I':
1a00e612
RS
7933 if (!match_const_int (&arg, &imm_expr.X_add_number))
7934 return FALSE;
7935 imm_expr.X_op = O_constant;
bad1aba3 7936 if (GPR_SIZE == 32)
97d87491
RS
7937 normalize_constant_expr (&imm_expr);
7938 continue;
7939
7940 case 'A':
7941 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7942 {
7943 /* Assume that the offset has been elided and that what
7944 we saw was a base register. The match will fail later
7945 if that assumption turns out to be wrong. */
7946 offset_expr.X_op = O_constant;
7947 offset_expr.X_add_number = 0;
7948 }
97d87491 7949 else
1a00e612
RS
7950 {
7951 if (!match_expression (&arg, &offset_expr, offset_reloc))
7952 return FALSE;
7953 normalize_address_expr (&offset_expr);
7954 }
97d87491
RS
7955 continue;
7956
7957 case 'F':
7958 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7959 8, TRUE))
1a00e612 7960 return FALSE;
97d87491
RS
7961 continue;
7962
7963 case 'L':
7964 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7965 8, FALSE))
1a00e612 7966 return FALSE;
97d87491
RS
7967 continue;
7968
7969 case 'f':
7970 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7971 4, TRUE))
1a00e612 7972 return FALSE;
97d87491
RS
7973 continue;
7974
7975 case 'l':
7976 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7977 4, FALSE))
1a00e612 7978 return FALSE;
97d87491
RS
7979 continue;
7980
97d87491
RS
7981 case 'p':
7982 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7983 break;
7984
7985 case 'a':
7986 *offset_reloc = BFD_RELOC_MIPS_JMP;
7987 break;
7988
7989 case 'm':
7990 gas_assert (mips_opts.micromips);
7991 c = args[1];
7992 switch (c)
7993 {
7994 case 'D':
7995 case 'E':
7996 if (!forced_insn_length)
7997 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7998 else if (c == 'D')
7999 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
8000 else
8001 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
8002 break;
8003 }
8004 break;
8005 }
8006
8007 operand = (mips_opts.micromips
8008 ? decode_micromips_operand (args)
8009 : decode_mips_operand (args));
8010 if (!operand)
8011 abort ();
8012
8013 /* Skip prefixes. */
7361da2c 8014 if (*args == '+' || *args == 'm' || *args == '-')
97d87491
RS
8015 args++;
8016
8017 if (mips_optional_operand_p (operand)
8018 && args[1] == ','
8019 && (arg.token[0].type != OT_REG
8020 || arg.token[1].type == OT_END))
8021 {
8022 /* Assume that the register has been elided and is the
8023 same as the first operand. */
8024 arg.token = tokens;
8025 arg.argnum = 1;
8026 }
8027
8028 if (!match_operand (&arg, operand))
8029 return FALSE;
8030 }
8031}
8032
8033/* Like match_insn, but for MIPS16. */
8034
8035static bfd_boolean
8036match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
1a00e612 8037 struct mips_operand_token *tokens)
97d87491
RS
8038{
8039 const char *args;
8040 const struct mips_operand *operand;
8041 const struct mips_operand *ext_operand;
8042 struct mips_arg_info arg;
8043 int relax_char;
8044
8045 create_insn (insn, opcode);
8046 imm_expr.X_op = O_absent;
97d87491
RS
8047 offset_expr.X_op = O_absent;
8048 offset_reloc[0] = BFD_RELOC_UNUSED;
8049 offset_reloc[1] = BFD_RELOC_UNUSED;
8050 offset_reloc[2] = BFD_RELOC_UNUSED;
8051 relax_char = 0;
8052
8053 memset (&arg, 0, sizeof (arg));
8054 arg.insn = insn;
8055 arg.token = tokens;
8056 arg.argnum = 1;
8057 arg.last_regno = ILLEGAL_REG;
8058 arg.dest_regno = ILLEGAL_REG;
97d87491
RS
8059 relax_char = 0;
8060 for (args = opcode->args;; ++args)
8061 {
8062 int c;
8063
8064 if (arg.token->type == OT_END)
8065 {
8066 offsetT value;
8067
8068 /* Handle unary instructions in which only one operand is given.
8069 The source is then the same as the destination. */
8070 if (arg.opnum == 1 && *args == ',')
8071 {
8072 operand = decode_mips16_operand (args[1], FALSE);
8073 if (operand && mips_optional_operand_p (operand))
8074 {
8075 arg.token = tokens;
8076 arg.argnum = 1;
8077 continue;
8078 }
8079 }
8080
8081 /* Fail the match if there were too few operands. */
8082 if (*args)
8083 return FALSE;
8084
8085 /* Successful match. Stuff the immediate value in now, if
8086 we can. */
e3de51ce 8087 clear_insn_error ();
97d87491
RS
8088 if (opcode->pinfo == INSN_MACRO)
8089 {
8090 gas_assert (relax_char == 0 || relax_char == 'p');
8091 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
8092 }
8093 else if (relax_char
8094 && offset_expr.X_op == O_constant
8095 && calculate_reloc (*offset_reloc,
8096 offset_expr.X_add_number,
8097 &value))
8098 {
8099 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
8100 forced_insn_length, &insn->insn_opcode);
8101 offset_expr.X_op = O_absent;
8102 *offset_reloc = BFD_RELOC_UNUSED;
8103 }
8104 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8105 {
8106 if (forced_insn_length == 2)
e3de51ce 8107 set_insn_error (0, _("invalid unextended operand value"));
97d87491
RS
8108 forced_insn_length = 4;
8109 insn->insn_opcode |= MIPS16_EXTEND;
8110 }
8111 else if (relax_char)
8112 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8113
8114 check_completed_insn (&arg);
8115 return TRUE;
8116 }
8117
8118 /* Fail the match if the line has too many operands. */
8119 if (*args == 0)
8120 return FALSE;
8121
8122 /* Handle characters that need to match exactly. */
8123 if (*args == '(' || *args == ')' || *args == ',')
8124 {
8125 if (match_char (&arg, *args))
8126 continue;
8127 return FALSE;
8128 }
8129
8130 arg.opnum += 1;
8131 c = *args;
8132 switch (c)
8133 {
8134 case 'p':
8135 case 'q':
8136 case 'A':
8137 case 'B':
8138 case 'E':
8139 relax_char = c;
8140 break;
8141
8142 case 'I':
1a00e612
RS
8143 if (!match_const_int (&arg, &imm_expr.X_add_number))
8144 return FALSE;
8145 imm_expr.X_op = O_constant;
bad1aba3 8146 if (GPR_SIZE == 32)
97d87491
RS
8147 normalize_constant_expr (&imm_expr);
8148 continue;
8149
8150 case 'a':
8151 case 'i':
8152 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8153 insn->insn_opcode <<= 16;
8154 break;
8155 }
8156
8157 operand = decode_mips16_operand (c, FALSE);
8158 if (!operand)
8159 abort ();
8160
8161 /* '6' is a special case. It is used for BREAK and SDBBP,
8162 whose operands are only meaningful to the software that decodes
8163 them. This means that there is no architectural reason why
8164 they cannot be prefixed by EXTEND, but in practice,
8165 exception handlers will only look at the instruction
8166 itself. We therefore allow '6' to be extended when
8167 disassembling but not when assembling. */
8168 if (operand->type != OP_PCREL && c != '6')
8169 {
8170 ext_operand = decode_mips16_operand (c, TRUE);
8171 if (operand != ext_operand)
8172 {
8173 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8174 {
8175 offset_expr.X_op = O_constant;
8176 offset_expr.X_add_number = 0;
8177 relax_char = c;
8178 continue;
8179 }
8180
8181 /* We need the OT_INTEGER check because some MIPS16
8182 immediate variants are listed before the register ones. */
8183 if (arg.token->type != OT_INTEGER
8184 || !match_expression (&arg, &offset_expr, offset_reloc))
8185 return FALSE;
8186
8187 /* '8' is used for SLTI(U) and has traditionally not
8188 been allowed to take relocation operators. */
8189 if (offset_reloc[0] != BFD_RELOC_UNUSED
8190 && (ext_operand->size != 16 || c == '8'))
8191 return FALSE;
8192
8193 relax_char = c;
8194 continue;
8195 }
8196 }
8197
8198 if (mips_optional_operand_p (operand)
8199 && args[1] == ','
8200 && (arg.token[0].type != OT_REG
8201 || arg.token[1].type == OT_END))
8202 {
8203 /* Assume that the register has been elided and is the
8204 same as the first operand. */
8205 arg.token = tokens;
8206 arg.argnum = 1;
8207 }
8208
8209 if (!match_operand (&arg, operand))
8210 return FALSE;
8211 }
8212}
8213
60f20e8b
RS
8214/* Record that the current instruction is invalid for the current ISA. */
8215
8216static void
8217match_invalid_for_isa (void)
8218{
8219 set_insn_error_ss
1661c76c 8220 (0, _("opcode not supported on this processor: %s (%s)"),
60f20e8b
RS
8221 mips_cpu_info_from_arch (mips_opts.arch)->name,
8222 mips_cpu_info_from_isa (mips_opts.isa)->name);
8223}
8224
8225/* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8226 Return true if a definite match or failure was found, storing any match
8227 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8228 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8229 tried and failed to match under normal conditions and now want to try a
8230 more relaxed match. */
8231
8232static bfd_boolean
8233match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8234 const struct mips_opcode *past, struct mips_operand_token *tokens,
8235 int opcode_extra, bfd_boolean lax_match)
8236{
8237 const struct mips_opcode *opcode;
8238 const struct mips_opcode *invalid_delay_slot;
8239 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8240
8241 /* Search for a match, ignoring alternatives that don't satisfy the
8242 current ISA or forced_length. */
8243 invalid_delay_slot = 0;
8244 seen_valid_for_isa = FALSE;
8245 seen_valid_for_size = FALSE;
8246 opcode = first;
8247 do
8248 {
8249 gas_assert (strcmp (opcode->name, first->name) == 0);
8250 if (is_opcode_valid (opcode))
8251 {
8252 seen_valid_for_isa = TRUE;
8253 if (is_size_valid (opcode))
8254 {
8255 bfd_boolean delay_slot_ok;
8256
8257 seen_valid_for_size = TRUE;
8258 delay_slot_ok = is_delay_slot_valid (opcode);
8259 if (match_insn (insn, opcode, tokens, opcode_extra,
8260 lax_match, delay_slot_ok))
8261 {
8262 if (!delay_slot_ok)
8263 {
8264 if (!invalid_delay_slot)
8265 invalid_delay_slot = opcode;
8266 }
8267 else
8268 return TRUE;
8269 }
8270 }
8271 }
8272 ++opcode;
8273 }
8274 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8275
8276 /* If the only matches we found had the wrong length for the delay slot,
8277 pick the first such match. We'll issue an appropriate warning later. */
8278 if (invalid_delay_slot)
8279 {
8280 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8281 lax_match, TRUE))
8282 return TRUE;
8283 abort ();
8284 }
8285
8286 /* Handle the case where we didn't try to match an instruction because
8287 all the alternatives were incompatible with the current ISA. */
8288 if (!seen_valid_for_isa)
8289 {
8290 match_invalid_for_isa ();
8291 return TRUE;
8292 }
8293
8294 /* Handle the case where we didn't try to match an instruction because
8295 all the alternatives were of the wrong size. */
8296 if (!seen_valid_for_size)
8297 {
8298 if (mips_opts.insn32)
1661c76c 8299 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
60f20e8b
RS
8300 else
8301 set_insn_error_i
1661c76c 8302 (0, _("unrecognized %d-bit version of microMIPS opcode"),
60f20e8b
RS
8303 8 * forced_insn_length);
8304 return TRUE;
8305 }
8306
8307 return FALSE;
8308}
8309
8310/* Like match_insns, but for MIPS16. */
8311
8312static bfd_boolean
8313match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8314 struct mips_operand_token *tokens)
8315{
8316 const struct mips_opcode *opcode;
8317 bfd_boolean seen_valid_for_isa;
8318
8319 /* Search for a match, ignoring alternatives that don't satisfy the
8320 current ISA. There are no separate entries for extended forms so
8321 we deal with forced_length later. */
8322 seen_valid_for_isa = FALSE;
8323 opcode = first;
8324 do
8325 {
8326 gas_assert (strcmp (opcode->name, first->name) == 0);
8327 if (is_opcode_valid_16 (opcode))
8328 {
8329 seen_valid_for_isa = TRUE;
8330 if (match_mips16_insn (insn, opcode, tokens))
8331 return TRUE;
8332 }
8333 ++opcode;
8334 }
8335 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8336 && strcmp (opcode->name, first->name) == 0);
8337
8338 /* Handle the case where we didn't try to match an instruction because
8339 all the alternatives were incompatible with the current ISA. */
8340 if (!seen_valid_for_isa)
8341 {
8342 match_invalid_for_isa ();
8343 return TRUE;
8344 }
8345
8346 return FALSE;
8347}
8348
584892a6
RS
8349/* Set up global variables for the start of a new macro. */
8350
8351static void
8352macro_start (void)
8353{
8354 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
df58fc94
RS
8355 memset (&mips_macro_warning.first_insn_sizes, 0,
8356 sizeof (mips_macro_warning.first_insn_sizes));
8357 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
584892a6 8358 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
11625dd8 8359 && delayed_branch_p (&history[0]));
7bd374a4
MR
8360 if (history[0].frag
8361 && history[0].frag->fr_type == rs_machine_dependent
8362 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
8363 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
8364 mips_macro_warning.delay_slot_length = 0;
8365 else
8366 switch (history[0].insn_mo->pinfo2
8367 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8368 {
8369 case INSN2_BRANCH_DELAY_32BIT:
8370 mips_macro_warning.delay_slot_length = 4;
8371 break;
8372 case INSN2_BRANCH_DELAY_16BIT:
8373 mips_macro_warning.delay_slot_length = 2;
8374 break;
8375 default:
8376 mips_macro_warning.delay_slot_length = 0;
8377 break;
8378 }
df58fc94 8379 mips_macro_warning.first_frag = NULL;
584892a6
RS
8380}
8381
df58fc94
RS
8382/* Given that a macro is longer than one instruction or of the wrong size,
8383 return the appropriate warning for it. Return null if no warning is
8384 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8385 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8386 and RELAX_NOMACRO. */
584892a6
RS
8387
8388static const char *
8389macro_warning (relax_substateT subtype)
8390{
8391 if (subtype & RELAX_DELAY_SLOT)
1661c76c 8392 return _("macro instruction expanded into multiple instructions"
584892a6
RS
8393 " in a branch delay slot");
8394 else if (subtype & RELAX_NOMACRO)
1661c76c 8395 return _("macro instruction expanded into multiple instructions");
df58fc94
RS
8396 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8397 | RELAX_DELAY_SLOT_SIZE_SECOND))
8398 return ((subtype & RELAX_DELAY_SLOT_16BIT)
1661c76c 8399 ? _("macro instruction expanded into a wrong size instruction"
df58fc94 8400 " in a 16-bit branch delay slot")
1661c76c 8401 : _("macro instruction expanded into a wrong size instruction"
df58fc94 8402 " in a 32-bit branch delay slot"));
584892a6
RS
8403 else
8404 return 0;
8405}
8406
8407/* Finish up a macro. Emit warnings as appropriate. */
8408
8409static void
8410macro_end (void)
8411{
df58fc94
RS
8412 /* Relaxation warning flags. */
8413 relax_substateT subtype = 0;
8414
8415 /* Check delay slot size requirements. */
8416 if (mips_macro_warning.delay_slot_length == 2)
8417 subtype |= RELAX_DELAY_SLOT_16BIT;
8418 if (mips_macro_warning.delay_slot_length != 0)
584892a6 8419 {
df58fc94
RS
8420 if (mips_macro_warning.delay_slot_length
8421 != mips_macro_warning.first_insn_sizes[0])
8422 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8423 if (mips_macro_warning.delay_slot_length
8424 != mips_macro_warning.first_insn_sizes[1])
8425 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8426 }
584892a6 8427
df58fc94
RS
8428 /* Check instruction count requirements. */
8429 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8430 {
8431 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
584892a6
RS
8432 subtype |= RELAX_SECOND_LONGER;
8433 if (mips_opts.warn_about_macros)
8434 subtype |= RELAX_NOMACRO;
8435 if (mips_macro_warning.delay_slot_p)
8436 subtype |= RELAX_DELAY_SLOT;
df58fc94 8437 }
584892a6 8438
df58fc94
RS
8439 /* If both alternatives fail to fill a delay slot correctly,
8440 emit the warning now. */
8441 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8442 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8443 {
8444 relax_substateT s;
8445 const char *msg;
8446
8447 s = subtype & (RELAX_DELAY_SLOT_16BIT
8448 | RELAX_DELAY_SLOT_SIZE_FIRST
8449 | RELAX_DELAY_SLOT_SIZE_SECOND);
8450 msg = macro_warning (s);
8451 if (msg != NULL)
8452 as_warn ("%s", msg);
8453 subtype &= ~s;
8454 }
8455
8456 /* If both implementations are longer than 1 instruction, then emit the
8457 warning now. */
8458 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8459 {
8460 relax_substateT s;
8461 const char *msg;
8462
8463 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8464 msg = macro_warning (s);
8465 if (msg != NULL)
8466 as_warn ("%s", msg);
8467 subtype &= ~s;
584892a6 8468 }
df58fc94
RS
8469
8470 /* If any flags still set, then one implementation might need a warning
8471 and the other either will need one of a different kind or none at all.
8472 Pass any remaining flags over to relaxation. */
8473 if (mips_macro_warning.first_frag != NULL)
8474 mips_macro_warning.first_frag->fr_subtype |= subtype;
584892a6
RS
8475}
8476
df58fc94
RS
8477/* Instruction operand formats used in macros that vary between
8478 standard MIPS and microMIPS code. */
8479
833794fc 8480static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
df58fc94
RS
8481static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8482static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8483static const char * const lui_fmt[2] = { "t,u", "s,u" };
8484static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
833794fc 8485static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
df58fc94
RS
8486static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8487static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8488
833794fc 8489#define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7361da2c
AB
8490#define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8491 : cop12_fmt[mips_opts.micromips])
df58fc94
RS
8492#define JALR_FMT (jalr_fmt[mips_opts.micromips])
8493#define LUI_FMT (lui_fmt[mips_opts.micromips])
8494#define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7361da2c
AB
8495#define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8496 : mem12_fmt[mips_opts.micromips])
833794fc 8497#define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
df58fc94
RS
8498#define SHFT_FMT (shft_fmt[mips_opts.micromips])
8499#define TRAP_FMT (trap_fmt[mips_opts.micromips])
8500
6e1304d8
RS
8501/* Read a macro's relocation codes from *ARGS and store them in *R.
8502 The first argument in *ARGS will be either the code for a single
8503 relocation or -1 followed by the three codes that make up a
8504 composite relocation. */
8505
8506static void
8507macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8508{
8509 int i, next;
8510
8511 next = va_arg (*args, int);
8512 if (next >= 0)
8513 r[0] = (bfd_reloc_code_real_type) next;
8514 else
f2ae14a1
RS
8515 {
8516 for (i = 0; i < 3; i++)
8517 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8518 /* This function is only used for 16-bit relocation fields.
8519 To make the macro code simpler, treat an unrelocated value
8520 in the same way as BFD_RELOC_LO16. */
8521 if (r[0] == BFD_RELOC_UNUSED)
8522 r[0] = BFD_RELOC_LO16;
8523 }
6e1304d8
RS
8524}
8525
252b5132
RH
8526/* Build an instruction created by a macro expansion. This is passed
8527 a pointer to the count of instructions created so far, an
8528 expression, the name of the instruction to build, an operand format
8529 string, and corresponding arguments. */
8530
252b5132 8531static void
67c0d1eb 8532macro_build (expressionS *ep, const char *name, const char *fmt, ...)
252b5132 8533{
df58fc94 8534 const struct mips_opcode *mo = NULL;
f6688943 8535 bfd_reloc_code_real_type r[3];
df58fc94 8536 const struct mips_opcode *amo;
e077a1c8 8537 const struct mips_operand *operand;
df58fc94
RS
8538 struct hash_control *hash;
8539 struct mips_cl_insn insn;
252b5132 8540 va_list args;
e077a1c8 8541 unsigned int uval;
252b5132 8542
252b5132 8543 va_start (args, fmt);
252b5132 8544
252b5132
RH
8545 if (mips_opts.mips16)
8546 {
03ea81db 8547 mips16_macro_build (ep, name, fmt, &args);
252b5132
RH
8548 va_end (args);
8549 return;
8550 }
8551
f6688943
TS
8552 r[0] = BFD_RELOC_UNUSED;
8553 r[1] = BFD_RELOC_UNUSED;
8554 r[2] = BFD_RELOC_UNUSED;
df58fc94
RS
8555 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8556 amo = (struct mips_opcode *) hash_find (hash, name);
8557 gas_assert (amo);
8558 gas_assert (strcmp (name, amo->name) == 0);
1e915849 8559
df58fc94 8560 do
8b082fb1
TS
8561 {
8562 /* Search until we get a match for NAME. It is assumed here that
df58fc94
RS
8563 macros will never generate MDMX, MIPS-3D, or MT instructions.
8564 We try to match an instruction that fulfils the branch delay
8565 slot instruction length requirement (if any) of the previous
8566 instruction. While doing this we record the first instruction
8567 seen that matches all the other conditions and use it anyway
8568 if the requirement cannot be met; we will issue an appropriate
8569 warning later on. */
8570 if (strcmp (fmt, amo->args) == 0
8571 && amo->pinfo != INSN_MACRO
8572 && is_opcode_valid (amo)
8573 && is_size_valid (amo))
8574 {
8575 if (is_delay_slot_valid (amo))
8576 {
8577 mo = amo;
8578 break;
8579 }
8580 else if (!mo)
8581 mo = amo;
8582 }
8b082fb1 8583
df58fc94
RS
8584 ++amo;
8585 gas_assert (amo->name);
252b5132 8586 }
df58fc94 8587 while (strcmp (name, amo->name) == 0);
252b5132 8588
df58fc94 8589 gas_assert (mo);
1e915849 8590 create_insn (&insn, mo);
e077a1c8 8591 for (; *fmt; ++fmt)
252b5132 8592 {
e077a1c8 8593 switch (*fmt)
252b5132 8594 {
252b5132
RH
8595 case ',':
8596 case '(':
8597 case ')':
252b5132 8598 case 'z':
e077a1c8 8599 break;
252b5132
RH
8600
8601 case 'i':
8602 case 'j':
6e1304d8 8603 macro_read_relocs (&args, r);
9c2799c2 8604 gas_assert (*r == BFD_RELOC_GPREL16
e391c024
RS
8605 || *r == BFD_RELOC_MIPS_HIGHER
8606 || *r == BFD_RELOC_HI16_S
8607 || *r == BFD_RELOC_LO16
8608 || *r == BFD_RELOC_MIPS_GOT_OFST);
e077a1c8 8609 break;
e391c024
RS
8610
8611 case 'o':
8612 macro_read_relocs (&args, r);
e077a1c8 8613 break;
252b5132
RH
8614
8615 case 'u':
6e1304d8 8616 macro_read_relocs (&args, r);
9c2799c2 8617 gas_assert (ep != NULL
90ecf173
MR
8618 && (ep->X_op == O_constant
8619 || (ep->X_op == O_symbol
8620 && (*r == BFD_RELOC_MIPS_HIGHEST
8621 || *r == BFD_RELOC_HI16_S
8622 || *r == BFD_RELOC_HI16
8623 || *r == BFD_RELOC_GPREL16
8624 || *r == BFD_RELOC_MIPS_GOT_HI16
8625 || *r == BFD_RELOC_MIPS_CALL_HI16))));
e077a1c8 8626 break;
252b5132
RH
8627
8628 case 'p':
9c2799c2 8629 gas_assert (ep != NULL);
bad36eac 8630
252b5132
RH
8631 /*
8632 * This allows macro() to pass an immediate expression for
8633 * creating short branches without creating a symbol.
bad36eac
DJ
8634 *
8635 * We don't allow branch relaxation for these branches, as
8636 * they should only appear in ".set nomacro" anyway.
252b5132
RH
8637 */
8638 if (ep->X_op == O_constant)
8639 {
df58fc94
RS
8640 /* For microMIPS we always use relocations for branches.
8641 So we should not resolve immediate values. */
8642 gas_assert (!mips_opts.micromips);
8643
bad36eac
DJ
8644 if ((ep->X_add_number & 3) != 0)
8645 as_bad (_("branch to misaligned address (0x%lx)"),
8646 (unsigned long) ep->X_add_number);
8647 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8648 as_bad (_("branch address range overflow (0x%lx)"),
8649 (unsigned long) ep->X_add_number);
252b5132
RH
8650 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8651 ep = NULL;
8652 }
8653 else
0b25d3e6 8654 *r = BFD_RELOC_16_PCREL_S2;
e077a1c8 8655 break;
252b5132
RH
8656
8657 case 'a':
9c2799c2 8658 gas_assert (ep != NULL);
f6688943 8659 *r = BFD_RELOC_MIPS_JMP;
e077a1c8 8660 break;
d43b4baf 8661
252b5132 8662 default:
e077a1c8
RS
8663 operand = (mips_opts.micromips
8664 ? decode_micromips_operand (fmt)
8665 : decode_mips_operand (fmt));
8666 if (!operand)
8667 abort ();
8668
8669 uval = va_arg (args, int);
8670 if (operand->type == OP_CLO_CLZ_DEST)
8671 uval |= (uval << 5);
8672 insn_insert_operand (&insn, operand, uval);
8673
7361da2c 8674 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
e077a1c8
RS
8675 ++fmt;
8676 break;
252b5132 8677 }
252b5132
RH
8678 }
8679 va_end (args);
9c2799c2 8680 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 8681
df58fc94 8682 append_insn (&insn, ep, r, TRUE);
252b5132
RH
8683}
8684
8685static void
67c0d1eb 8686mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
03ea81db 8687 va_list *args)
252b5132 8688{
1e915849 8689 struct mips_opcode *mo;
252b5132 8690 struct mips_cl_insn insn;
e077a1c8 8691 const struct mips_operand *operand;
f6688943
TS
8692 bfd_reloc_code_real_type r[3]
8693 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
252b5132 8694
1e915849 8695 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
9c2799c2
NC
8696 gas_assert (mo);
8697 gas_assert (strcmp (name, mo->name) == 0);
252b5132 8698
1e915849 8699 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
252b5132 8700 {
1e915849 8701 ++mo;
9c2799c2
NC
8702 gas_assert (mo->name);
8703 gas_assert (strcmp (name, mo->name) == 0);
252b5132
RH
8704 }
8705
1e915849 8706 create_insn (&insn, mo);
e077a1c8 8707 for (; *fmt; ++fmt)
252b5132
RH
8708 {
8709 int c;
8710
e077a1c8 8711 c = *fmt;
252b5132
RH
8712 switch (c)
8713 {
252b5132
RH
8714 case ',':
8715 case '(':
8716 case ')':
e077a1c8 8717 break;
252b5132
RH
8718
8719 case '0':
8720 case 'S':
8721 case 'P':
8722 case 'R':
e077a1c8 8723 break;
252b5132
RH
8724
8725 case '<':
8726 case '>':
8727 case '4':
8728 case '5':
8729 case 'H':
8730 case 'W':
8731 case 'D':
8732 case 'j':
8733 case '8':
8734 case 'V':
8735 case 'C':
8736 case 'U':
8737 case 'k':
8738 case 'K':
8739 case 'p':
8740 case 'q':
8741 {
b886a2ab
RS
8742 offsetT value;
8743
9c2799c2 8744 gas_assert (ep != NULL);
252b5132
RH
8745
8746 if (ep->X_op != O_constant)
874e8986 8747 *r = (int) BFD_RELOC_UNUSED + c;
b886a2ab 8748 else if (calculate_reloc (*r, ep->X_add_number, &value))
252b5132 8749 {
b886a2ab 8750 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
252b5132 8751 ep = NULL;
f6688943 8752 *r = BFD_RELOC_UNUSED;
252b5132
RH
8753 }
8754 }
e077a1c8 8755 break;
252b5132 8756
e077a1c8
RS
8757 default:
8758 operand = decode_mips16_operand (c, FALSE);
8759 if (!operand)
8760 abort ();
252b5132 8761
4a06e5a2 8762 insn_insert_operand (&insn, operand, va_arg (*args, int));
e077a1c8
RS
8763 break;
8764 }
252b5132
RH
8765 }
8766
9c2799c2 8767 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
252b5132 8768
df58fc94 8769 append_insn (&insn, ep, r, TRUE);
252b5132
RH
8770}
8771
438c16b8
TS
8772/*
8773 * Generate a "jalr" instruction with a relocation hint to the called
8774 * function. This occurs in NewABI PIC code.
8775 */
8776static void
df58fc94 8777macro_build_jalr (expressionS *ep, int cprestore)
438c16b8 8778{
df58fc94
RS
8779 static const bfd_reloc_code_real_type jalr_relocs[2]
8780 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8781 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8782 const char *jalr;
685736be 8783 char *f = NULL;
b34976b6 8784
1180b5a4 8785 if (MIPS_JALR_HINT_P (ep))
f21f8242 8786 {
cc3d92a5 8787 frag_grow (8);
f21f8242
AO
8788 f = frag_more (0);
8789 }
2906b037 8790 if (mips_opts.micromips)
df58fc94 8791 {
833794fc
MR
8792 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8793 ? "jalr" : "jalrs");
e64af278 8794 if (MIPS_JALR_HINT_P (ep)
833794fc 8795 || mips_opts.insn32
e64af278 8796 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
df58fc94
RS
8797 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8798 else
8799 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8800 }
2906b037
MR
8801 else
8802 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
1180b5a4 8803 if (MIPS_JALR_HINT_P (ep))
df58fc94 8804 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
438c16b8
TS
8805}
8806
252b5132
RH
8807/*
8808 * Generate a "lui" instruction.
8809 */
8810static void
67c0d1eb 8811macro_build_lui (expressionS *ep, int regnum)
252b5132 8812{
9c2799c2 8813 gas_assert (! mips_opts.mips16);
252b5132 8814
df58fc94 8815 if (ep->X_op != O_constant)
252b5132 8816 {
9c2799c2 8817 gas_assert (ep->X_op == O_symbol);
bbe506e8
TS
8818 /* _gp_disp is a special case, used from s_cpload.
8819 __gnu_local_gp is used if mips_no_shared. */
9c2799c2 8820 gas_assert (mips_pic == NO_PIC
78e1bb40 8821 || (! HAVE_NEWABI
aa6975fb
ILT
8822 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8823 || (! mips_in_shared
bbe506e8
TS
8824 && strcmp (S_GET_NAME (ep->X_add_symbol),
8825 "__gnu_local_gp") == 0));
252b5132
RH
8826 }
8827
df58fc94 8828 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
252b5132
RH
8829}
8830
885add95
CD
8831/* Generate a sequence of instructions to do a load or store from a constant
8832 offset off of a base register (breg) into/from a target register (treg),
8833 using AT if necessary. */
8834static void
67c0d1eb
RS
8835macro_build_ldst_constoffset (expressionS *ep, const char *op,
8836 int treg, int breg, int dbl)
885add95 8837{
9c2799c2 8838 gas_assert (ep->X_op == O_constant);
885add95 8839
256ab948 8840 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
8841 if (!dbl)
8842 normalize_constant_expr (ep);
256ab948 8843
67c1ffbe 8844 /* Right now, this routine can only handle signed 32-bit constants. */
ecd13cd3 8845 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
885add95
CD
8846 as_warn (_("operand overflow"));
8847
8848 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8849 {
8850 /* Signed 16-bit offset will fit in the op. Easy! */
67c0d1eb 8851 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
885add95
CD
8852 }
8853 else
8854 {
8855 /* 32-bit offset, need multiple instructions and AT, like:
8856 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8857 addu $tempreg,$tempreg,$breg
8858 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8859 to handle the complete offset. */
67c0d1eb
RS
8860 macro_build_lui (ep, AT);
8861 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8862 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
885add95 8863
741fe287 8864 if (!mips_opts.at)
1661c76c 8865 as_bad (_("macro used $at after \".set noat\""));
885add95
CD
8866 }
8867}
8868
252b5132
RH
8869/* set_at()
8870 * Generates code to set the $at register to true (one)
8871 * if reg is less than the immediate expression.
8872 */
8873static void
67c0d1eb 8874set_at (int reg, int unsignedp)
252b5132 8875{
b0e6f033 8876 if (imm_expr.X_add_number >= -0x8000
252b5132 8877 && imm_expr.X_add_number < 0x8000)
67c0d1eb
RS
8878 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8879 AT, reg, BFD_RELOC_LO16);
252b5132
RH
8880 else
8881 {
bad1aba3 8882 load_register (AT, &imm_expr, GPR_SIZE == 64);
67c0d1eb 8883 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
252b5132
RH
8884 }
8885}
8886
252b5132
RH
8887/* Count the leading zeroes by performing a binary chop. This is a
8888 bulky bit of source, but performance is a LOT better for the
8889 majority of values than a simple loop to count the bits:
8890 for (lcnt = 0; (lcnt < 32); lcnt++)
8891 if ((v) & (1 << (31 - lcnt)))
8892 break;
8893 However it is not code size friendly, and the gain will drop a bit
8894 on certain cached systems.
8895*/
8896#define COUNT_TOP_ZEROES(v) \
8897 (((v) & ~0xffff) == 0 \
8898 ? ((v) & ~0xff) == 0 \
8899 ? ((v) & ~0xf) == 0 \
8900 ? ((v) & ~0x3) == 0 \
8901 ? ((v) & ~0x1) == 0 \
8902 ? !(v) \
8903 ? 32 \
8904 : 31 \
8905 : 30 \
8906 : ((v) & ~0x7) == 0 \
8907 ? 29 \
8908 : 28 \
8909 : ((v) & ~0x3f) == 0 \
8910 ? ((v) & ~0x1f) == 0 \
8911 ? 27 \
8912 : 26 \
8913 : ((v) & ~0x7f) == 0 \
8914 ? 25 \
8915 : 24 \
8916 : ((v) & ~0xfff) == 0 \
8917 ? ((v) & ~0x3ff) == 0 \
8918 ? ((v) & ~0x1ff) == 0 \
8919 ? 23 \
8920 : 22 \
8921 : ((v) & ~0x7ff) == 0 \
8922 ? 21 \
8923 : 20 \
8924 : ((v) & ~0x3fff) == 0 \
8925 ? ((v) & ~0x1fff) == 0 \
8926 ? 19 \
8927 : 18 \
8928 : ((v) & ~0x7fff) == 0 \
8929 ? 17 \
8930 : 16 \
8931 : ((v) & ~0xffffff) == 0 \
8932 ? ((v) & ~0xfffff) == 0 \
8933 ? ((v) & ~0x3ffff) == 0 \
8934 ? ((v) & ~0x1ffff) == 0 \
8935 ? 15 \
8936 : 14 \
8937 : ((v) & ~0x7ffff) == 0 \
8938 ? 13 \
8939 : 12 \
8940 : ((v) & ~0x3fffff) == 0 \
8941 ? ((v) & ~0x1fffff) == 0 \
8942 ? 11 \
8943 : 10 \
8944 : ((v) & ~0x7fffff) == 0 \
8945 ? 9 \
8946 : 8 \
8947 : ((v) & ~0xfffffff) == 0 \
8948 ? ((v) & ~0x3ffffff) == 0 \
8949 ? ((v) & ~0x1ffffff) == 0 \
8950 ? 7 \
8951 : 6 \
8952 : ((v) & ~0x7ffffff) == 0 \
8953 ? 5 \
8954 : 4 \
8955 : ((v) & ~0x3fffffff) == 0 \
8956 ? ((v) & ~0x1fffffff) == 0 \
8957 ? 3 \
8958 : 2 \
8959 : ((v) & ~0x7fffffff) == 0 \
8960 ? 1 \
8961 : 0)
8962
8963/* load_register()
67c1ffbe 8964 * This routine generates the least number of instructions necessary to load
252b5132
RH
8965 * an absolute expression value into a register.
8966 */
8967static void
67c0d1eb 8968load_register (int reg, expressionS *ep, int dbl)
252b5132
RH
8969{
8970 int freg;
8971 expressionS hi32, lo32;
8972
8973 if (ep->X_op != O_big)
8974 {
9c2799c2 8975 gas_assert (ep->X_op == O_constant);
256ab948
TS
8976
8977 /* Sign-extending 32-bit constants makes their handling easier. */
2051e8c4
MR
8978 if (!dbl)
8979 normalize_constant_expr (ep);
256ab948
TS
8980
8981 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
252b5132
RH
8982 {
8983 /* We can handle 16 bit signed values with an addiu to
8984 $zero. No need to ever use daddiu here, since $zero and
8985 the result are always correct in 32 bit mode. */
67c0d1eb 8986 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8987 return;
8988 }
8989 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8990 {
8991 /* We can handle 16 bit unsigned values with an ori to
8992 $zero. */
67c0d1eb 8993 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
252b5132
RH
8994 return;
8995 }
256ab948 8996 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
252b5132
RH
8997 {
8998 /* 32 bit values require an lui. */
df58fc94 8999 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 9000 if ((ep->X_add_number & 0xffff) != 0)
67c0d1eb 9001 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
252b5132
RH
9002 return;
9003 }
9004 }
9005
9006 /* The value is larger than 32 bits. */
9007
bad1aba3 9008 if (!dbl || GPR_SIZE == 32)
252b5132 9009 {
55e08f71
NC
9010 char value[32];
9011
9012 sprintf_vma (value, ep->X_add_number);
1661c76c 9013 as_bad (_("number (0x%s) larger than 32 bits"), value);
67c0d1eb 9014 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
252b5132
RH
9015 return;
9016 }
9017
9018 if (ep->X_op != O_big)
9019 {
9020 hi32 = *ep;
9021 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9022 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9023 hi32.X_add_number &= 0xffffffff;
9024 lo32 = *ep;
9025 lo32.X_add_number &= 0xffffffff;
9026 }
9027 else
9028 {
9c2799c2 9029 gas_assert (ep->X_add_number > 2);
252b5132
RH
9030 if (ep->X_add_number == 3)
9031 generic_bignum[3] = 0;
9032 else if (ep->X_add_number > 4)
1661c76c 9033 as_bad (_("number larger than 64 bits"));
252b5132
RH
9034 lo32.X_op = O_constant;
9035 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
9036 hi32.X_op = O_constant;
9037 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
9038 }
9039
9040 if (hi32.X_add_number == 0)
9041 freg = 0;
9042 else
9043 {
9044 int shift, bit;
9045 unsigned long hi, lo;
9046
956cd1d6 9047 if (hi32.X_add_number == (offsetT) 0xffffffff)
beae10d5
KH
9048 {
9049 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
9050 {
67c0d1eb 9051 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
9052 return;
9053 }
9054 if (lo32.X_add_number & 0x80000000)
9055 {
df58fc94 9056 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
252b5132 9057 if (lo32.X_add_number & 0xffff)
67c0d1eb 9058 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
beae10d5
KH
9059 return;
9060 }
9061 }
252b5132
RH
9062
9063 /* Check for 16bit shifted constant. We know that hi32 is
9064 non-zero, so start the mask on the first bit of the hi32
9065 value. */
9066 shift = 17;
9067 do
beae10d5
KH
9068 {
9069 unsigned long himask, lomask;
9070
9071 if (shift < 32)
9072 {
9073 himask = 0xffff >> (32 - shift);
9074 lomask = (0xffff << shift) & 0xffffffff;
9075 }
9076 else
9077 {
9078 himask = 0xffff << (shift - 32);
9079 lomask = 0;
9080 }
9081 if ((hi32.X_add_number & ~(offsetT) himask) == 0
9082 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
9083 {
9084 expressionS tmp;
9085
9086 tmp.X_op = O_constant;
9087 if (shift < 32)
9088 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
9089 | (lo32.X_add_number >> shift));
9090 else
9091 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
67c0d1eb 9092 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
df58fc94 9093 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 9094 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
9095 return;
9096 }
f9419b05 9097 ++shift;
beae10d5
KH
9098 }
9099 while (shift <= (64 - 16));
252b5132
RH
9100
9101 /* Find the bit number of the lowest one bit, and store the
9102 shifted value in hi/lo. */
9103 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
9104 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9105 if (lo != 0)
9106 {
9107 bit = 0;
9108 while ((lo & 1) == 0)
9109 {
9110 lo >>= 1;
9111 ++bit;
9112 }
9113 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
9114 hi >>= bit;
9115 }
9116 else
9117 {
9118 bit = 32;
9119 while ((hi & 1) == 0)
9120 {
9121 hi >>= 1;
9122 ++bit;
9123 }
9124 lo = hi;
9125 hi = 0;
9126 }
9127
9128 /* Optimize if the shifted value is a (power of 2) - 1. */
9129 if ((hi == 0 && ((lo + 1) & lo) == 0)
9130 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
beae10d5
KH
9131 {
9132 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
252b5132 9133 if (shift != 0)
beae10d5 9134 {
252b5132
RH
9135 expressionS tmp;
9136
9137 /* This instruction will set the register to be all
9138 ones. */
beae10d5
KH
9139 tmp.X_op = O_constant;
9140 tmp.X_add_number = (offsetT) -1;
67c0d1eb 9141 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
beae10d5
KH
9142 if (bit != 0)
9143 {
9144 bit += shift;
df58fc94 9145 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
67c0d1eb 9146 reg, reg, (bit >= 32) ? bit - 32 : bit);
beae10d5 9147 }
df58fc94 9148 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
67c0d1eb 9149 reg, reg, (shift >= 32) ? shift - 32 : shift);
beae10d5
KH
9150 return;
9151 }
9152 }
252b5132
RH
9153
9154 /* Sign extend hi32 before calling load_register, because we can
9155 generally get better code when we load a sign extended value. */
9156 if ((hi32.X_add_number & 0x80000000) != 0)
beae10d5 9157 hi32.X_add_number |= ~(offsetT) 0xffffffff;
67c0d1eb 9158 load_register (reg, &hi32, 0);
252b5132
RH
9159 freg = reg;
9160 }
9161 if ((lo32.X_add_number & 0xffff0000) == 0)
9162 {
9163 if (freg != 0)
9164 {
df58fc94 9165 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
252b5132
RH
9166 freg = reg;
9167 }
9168 }
9169 else
9170 {
9171 expressionS mid16;
9172
956cd1d6 9173 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
beae10d5 9174 {
df58fc94
RS
9175 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9176 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
beae10d5
KH
9177 return;
9178 }
252b5132
RH
9179
9180 if (freg != 0)
9181 {
df58fc94 9182 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
252b5132
RH
9183 freg = reg;
9184 }
9185 mid16 = lo32;
9186 mid16.X_add_number >>= 16;
67c0d1eb 9187 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
df58fc94 9188 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
252b5132
RH
9189 freg = reg;
9190 }
9191 if ((lo32.X_add_number & 0xffff) != 0)
67c0d1eb 9192 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
252b5132
RH
9193}
9194
269137b2
TS
9195static inline void
9196load_delay_nop (void)
9197{
9198 if (!gpr_interlocks)
9199 macro_build (NULL, "nop", "");
9200}
9201
252b5132
RH
9202/* Load an address into a register. */
9203
9204static void
67c0d1eb 9205load_address (int reg, expressionS *ep, int *used_at)
252b5132 9206{
252b5132
RH
9207 if (ep->X_op != O_constant
9208 && ep->X_op != O_symbol)
9209 {
9210 as_bad (_("expression too complex"));
9211 ep->X_op = O_constant;
9212 }
9213
9214 if (ep->X_op == O_constant)
9215 {
67c0d1eb 9216 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
252b5132
RH
9217 return;
9218 }
9219
9220 if (mips_pic == NO_PIC)
9221 {
9222 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 9223 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
9224 Otherwise we want
9225 lui $reg,<sym> (BFD_RELOC_HI16_S)
9226 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
d6bc6245 9227 If we have an addend, we always use the latter form.
76b3015f 9228
d6bc6245
TS
9229 With 64bit address space and a usable $at we want
9230 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9231 lui $at,<sym> (BFD_RELOC_HI16_S)
9232 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9233 daddiu $at,<sym> (BFD_RELOC_LO16)
9234 dsll32 $reg,0
3a482fd5 9235 daddu $reg,$reg,$at
76b3015f 9236
c03099e6 9237 If $at is already in use, we use a path which is suboptimal
d6bc6245
TS
9238 on superscalar processors.
9239 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9240 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9241 dsll $reg,16
9242 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9243 dsll $reg,16
9244 daddiu $reg,<sym> (BFD_RELOC_LO16)
6caf9ef4
TS
9245
9246 For GP relative symbols in 64bit address space we can use
9247 the same sequence as in 32bit address space. */
aed1a261 9248 if (HAVE_64BIT_SYMBOLS)
d6bc6245 9249 {
6caf9ef4
TS
9250 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9251 && !nopic_need_relax (ep->X_add_symbol, 1))
9252 {
9253 relax_start (ep->X_add_symbol);
9254 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9255 mips_gp_register, BFD_RELOC_GPREL16);
9256 relax_switch ();
9257 }
d6bc6245 9258
741fe287 9259 if (*used_at == 0 && mips_opts.at)
d6bc6245 9260 {
df58fc94
RS
9261 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9262 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
67c0d1eb
RS
9263 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9264 BFD_RELOC_MIPS_HIGHER);
9265 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
df58fc94 9266 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
67c0d1eb 9267 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
d6bc6245
TS
9268 *used_at = 1;
9269 }
9270 else
9271 {
df58fc94 9272 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb
RS
9273 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9274 BFD_RELOC_MIPS_HIGHER);
df58fc94 9275 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 9276 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
df58fc94 9277 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
67c0d1eb 9278 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
d6bc6245 9279 }
6caf9ef4
TS
9280
9281 if (mips_relax.sequence)
9282 relax_end ();
d6bc6245 9283 }
252b5132
RH
9284 else
9285 {
d6bc6245 9286 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 9287 && !nopic_need_relax (ep->X_add_symbol, 1))
d6bc6245 9288 {
4d7206a2 9289 relax_start (ep->X_add_symbol);
67c0d1eb 9290 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
17a2f251 9291 mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 9292 relax_switch ();
d6bc6245 9293 }
67c0d1eb
RS
9294 macro_build_lui (ep, reg);
9295 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9296 reg, reg, BFD_RELOC_LO16);
4d7206a2
RS
9297 if (mips_relax.sequence)
9298 relax_end ();
d6bc6245 9299 }
252b5132 9300 }
0a44bf69 9301 else if (!mips_big_got)
252b5132
RH
9302 {
9303 expressionS ex;
9304
9305 /* If this is a reference to an external symbol, we want
9306 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9307 Otherwise we want
9308 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9309 nop
9310 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
f5040a92
AO
9311 If there is a constant, it must be added in after.
9312
ed6fb7bd 9313 If we have NewABI, we want
f5040a92
AO
9314 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9315 unless we're referencing a global symbol with a non-zero
9316 offset, in which case cst must be added separately. */
ed6fb7bd
SC
9317 if (HAVE_NEWABI)
9318 {
f5040a92
AO
9319 if (ep->X_add_number)
9320 {
4d7206a2 9321 ex.X_add_number = ep->X_add_number;
f5040a92 9322 ep->X_add_number = 0;
4d7206a2 9323 relax_start (ep->X_add_symbol);
67c0d1eb
RS
9324 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9325 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
9326 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9327 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9328 ex.X_op = O_constant;
67c0d1eb 9329 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 9330 reg, reg, BFD_RELOC_LO16);
f5040a92 9331 ep->X_add_number = ex.X_add_number;
4d7206a2 9332 relax_switch ();
f5040a92 9333 }
67c0d1eb 9334 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 9335 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2
RS
9336 if (mips_relax.sequence)
9337 relax_end ();
ed6fb7bd
SC
9338 }
9339 else
9340 {
f5040a92
AO
9341 ex.X_add_number = ep->X_add_number;
9342 ep->X_add_number = 0;
67c0d1eb
RS
9343 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9344 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 9345 load_delay_nop ();
4d7206a2
RS
9346 relax_start (ep->X_add_symbol);
9347 relax_switch ();
67c0d1eb 9348 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 9349 BFD_RELOC_LO16);
4d7206a2 9350 relax_end ();
ed6fb7bd 9351
f5040a92
AO
9352 if (ex.X_add_number != 0)
9353 {
9354 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9355 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9356 ex.X_op = O_constant;
67c0d1eb 9357 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 9358 reg, reg, BFD_RELOC_LO16);
f5040a92 9359 }
252b5132
RH
9360 }
9361 }
0a44bf69 9362 else if (mips_big_got)
252b5132
RH
9363 {
9364 expressionS ex;
252b5132
RH
9365
9366 /* This is the large GOT case. If this is a reference to an
9367 external symbol, we want
9368 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9369 addu $reg,$reg,$gp
9370 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
f5040a92
AO
9371
9372 Otherwise, for a reference to a local symbol in old ABI, we want
252b5132
RH
9373 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9374 nop
9375 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
684022ea 9376 If there is a constant, it must be added in after.
f5040a92
AO
9377
9378 In the NewABI, for local symbols, with or without offsets, we want:
438c16b8
TS
9379 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9380 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 9381 */
438c16b8
TS
9382 if (HAVE_NEWABI)
9383 {
4d7206a2 9384 ex.X_add_number = ep->X_add_number;
f5040a92 9385 ep->X_add_number = 0;
4d7206a2 9386 relax_start (ep->X_add_symbol);
df58fc94 9387 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
9388 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9389 reg, reg, mips_gp_register);
9390 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9391 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
f5040a92
AO
9392 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9393 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9394 else if (ex.X_add_number)
9395 {
9396 ex.X_op = O_constant;
67c0d1eb
RS
9397 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9398 BFD_RELOC_LO16);
f5040a92
AO
9399 }
9400
9401 ep->X_add_number = ex.X_add_number;
4d7206a2 9402 relax_switch ();
67c0d1eb 9403 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 9404 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
67c0d1eb
RS
9405 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9406 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 9407 relax_end ();
438c16b8 9408 }
252b5132 9409 else
438c16b8 9410 {
f5040a92
AO
9411 ex.X_add_number = ep->X_add_number;
9412 ep->X_add_number = 0;
4d7206a2 9413 relax_start (ep->X_add_symbol);
df58fc94 9414 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
9415 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9416 reg, reg, mips_gp_register);
9417 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9418 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4d7206a2
RS
9419 relax_switch ();
9420 if (reg_needs_delay (mips_gp_register))
438c16b8
TS
9421 {
9422 /* We need a nop before loading from $gp. This special
9423 check is required because the lui which starts the main
9424 instruction stream does not refer to $gp, and so will not
9425 insert the nop which may be required. */
67c0d1eb 9426 macro_build (NULL, "nop", "");
438c16b8 9427 }
67c0d1eb 9428 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
17a2f251 9429 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 9430 load_delay_nop ();
67c0d1eb 9431 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
17a2f251 9432 BFD_RELOC_LO16);
4d7206a2 9433 relax_end ();
438c16b8 9434
f5040a92
AO
9435 if (ex.X_add_number != 0)
9436 {
9437 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9438 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9439 ex.X_op = O_constant;
67c0d1eb
RS
9440 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9441 BFD_RELOC_LO16);
f5040a92 9442 }
252b5132
RH
9443 }
9444 }
252b5132
RH
9445 else
9446 abort ();
8fc2e39e 9447
741fe287 9448 if (!mips_opts.at && *used_at == 1)
1661c76c 9449 as_bad (_("macro used $at after \".set noat\""));
252b5132
RH
9450}
9451
ea1fb5dc
RS
9452/* Move the contents of register SOURCE into register DEST. */
9453
9454static void
67c0d1eb 9455move_register (int dest, int source)
ea1fb5dc 9456{
df58fc94
RS
9457 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9458 instruction specifically requires a 32-bit one. */
9459 if (mips_opts.micromips
833794fc 9460 && !mips_opts.insn32
df58fc94 9461 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7951ca42 9462 macro_build (NULL, "move", "mp,mj", dest, source);
df58fc94 9463 else
40fc1451 9464 macro_build (NULL, "or", "d,v,t", dest, source, 0);
ea1fb5dc
RS
9465}
9466
4d7206a2 9467/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
f6a22291
MR
9468 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9469 The two alternatives are:
4d7206a2
RS
9470
9471 Global symbol Local sybmol
9472 ------------- ------------
9473 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9474 ... ...
9475 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9476
9477 load_got_offset emits the first instruction and add_got_offset
f6a22291
MR
9478 emits the second for a 16-bit offset or add_got_offset_hilo emits
9479 a sequence to add a 32-bit offset using a scratch register. */
4d7206a2
RS
9480
9481static void
67c0d1eb 9482load_got_offset (int dest, expressionS *local)
4d7206a2
RS
9483{
9484 expressionS global;
9485
9486 global = *local;
9487 global.X_add_number = 0;
9488
9489 relax_start (local->X_add_symbol);
67c0d1eb
RS
9490 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9491 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2 9492 relax_switch ();
67c0d1eb
RS
9493 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9494 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4d7206a2
RS
9495 relax_end ();
9496}
9497
9498static void
67c0d1eb 9499add_got_offset (int dest, expressionS *local)
4d7206a2
RS
9500{
9501 expressionS global;
9502
9503 global.X_op = O_constant;
9504 global.X_op_symbol = NULL;
9505 global.X_add_symbol = NULL;
9506 global.X_add_number = local->X_add_number;
9507
9508 relax_start (local->X_add_symbol);
67c0d1eb 9509 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4d7206a2
RS
9510 dest, dest, BFD_RELOC_LO16);
9511 relax_switch ();
67c0d1eb 9512 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4d7206a2
RS
9513 relax_end ();
9514}
9515
f6a22291
MR
9516static void
9517add_got_offset_hilo (int dest, expressionS *local, int tmp)
9518{
9519 expressionS global;
9520 int hold_mips_optimize;
9521
9522 global.X_op = O_constant;
9523 global.X_op_symbol = NULL;
9524 global.X_add_symbol = NULL;
9525 global.X_add_number = local->X_add_number;
9526
9527 relax_start (local->X_add_symbol);
9528 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9529 relax_switch ();
9530 /* Set mips_optimize around the lui instruction to avoid
9531 inserting an unnecessary nop after the lw. */
9532 hold_mips_optimize = mips_optimize;
9533 mips_optimize = 2;
9534 macro_build_lui (&global, tmp);
9535 mips_optimize = hold_mips_optimize;
9536 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9537 relax_end ();
9538
9539 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9540}
9541
df58fc94
RS
9542/* Emit a sequence of instructions to emulate a branch likely operation.
9543 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9544 is its complementing branch with the original condition negated.
9545 CALL is set if the original branch specified the link operation.
9546 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9547
9548 Code like this is produced in the noreorder mode:
9549
9550 BRNEG <args>, 1f
9551 nop
9552 b <sym>
9553 delay slot (executed only if branch taken)
9554 1:
9555
9556 or, if CALL is set:
9557
9558 BRNEG <args>, 1f
9559 nop
9560 bal <sym>
9561 delay slot (executed only if branch taken)
9562 1:
9563
9564 In the reorder mode the delay slot would be filled with a nop anyway,
9565 so code produced is simply:
9566
9567 BR <args>, <sym>
9568 nop
9569
9570 This function is used when producing code for the microMIPS ASE that
9571 does not implement branch likely instructions in hardware. */
9572
9573static void
9574macro_build_branch_likely (const char *br, const char *brneg,
9575 int call, expressionS *ep, const char *fmt,
9576 unsigned int sreg, unsigned int treg)
9577{
9578 int noreorder = mips_opts.noreorder;
9579 expressionS expr1;
9580
9581 gas_assert (mips_opts.micromips);
9582 start_noreorder ();
9583 if (noreorder)
9584 {
9585 micromips_label_expr (&expr1);
9586 macro_build (&expr1, brneg, fmt, sreg, treg);
9587 macro_build (NULL, "nop", "");
9588 macro_build (ep, call ? "bal" : "b", "p");
9589
9590 /* Set to true so that append_insn adds a label. */
9591 emit_branch_likely_macro = TRUE;
9592 }
9593 else
9594 {
9595 macro_build (ep, br, fmt, sreg, treg);
9596 macro_build (NULL, "nop", "");
9597 }
9598 end_noreorder ();
9599}
9600
9601/* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9602 the condition code tested. EP specifies the branch target. */
9603
9604static void
9605macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9606{
9607 const int call = 0;
9608 const char *brneg;
9609 const char *br;
9610
9611 switch (type)
9612 {
9613 case M_BC1FL:
9614 br = "bc1f";
9615 brneg = "bc1t";
9616 break;
9617 case M_BC1TL:
9618 br = "bc1t";
9619 brneg = "bc1f";
9620 break;
9621 case M_BC2FL:
9622 br = "bc2f";
9623 brneg = "bc2t";
9624 break;
9625 case M_BC2TL:
9626 br = "bc2t";
9627 brneg = "bc2f";
9628 break;
9629 default:
9630 abort ();
9631 }
9632 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9633}
9634
9635/* Emit a two-argument branch macro specified by TYPE, using SREG as
9636 the register tested. EP specifies the branch target. */
9637
9638static void
9639macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9640{
9641 const char *brneg = NULL;
9642 const char *br;
9643 int call = 0;
9644
9645 switch (type)
9646 {
9647 case M_BGEZ:
9648 br = "bgez";
9649 break;
9650 case M_BGEZL:
9651 br = mips_opts.micromips ? "bgez" : "bgezl";
9652 brneg = "bltz";
9653 break;
9654 case M_BGEZALL:
9655 gas_assert (mips_opts.micromips);
833794fc 9656 br = mips_opts.insn32 ? "bgezal" : "bgezals";
df58fc94
RS
9657 brneg = "bltz";
9658 call = 1;
9659 break;
9660 case M_BGTZ:
9661 br = "bgtz";
9662 break;
9663 case M_BGTZL:
9664 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9665 brneg = "blez";
9666 break;
9667 case M_BLEZ:
9668 br = "blez";
9669 break;
9670 case M_BLEZL:
9671 br = mips_opts.micromips ? "blez" : "blezl";
9672 brneg = "bgtz";
9673 break;
9674 case M_BLTZ:
9675 br = "bltz";
9676 break;
9677 case M_BLTZL:
9678 br = mips_opts.micromips ? "bltz" : "bltzl";
9679 brneg = "bgez";
9680 break;
9681 case M_BLTZALL:
9682 gas_assert (mips_opts.micromips);
833794fc 9683 br = mips_opts.insn32 ? "bltzal" : "bltzals";
df58fc94
RS
9684 brneg = "bgez";
9685 call = 1;
9686 break;
9687 default:
9688 abort ();
9689 }
9690 if (mips_opts.micromips && brneg)
9691 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9692 else
9693 macro_build (ep, br, "s,p", sreg);
9694}
9695
9696/* Emit a three-argument branch macro specified by TYPE, using SREG and
9697 TREG as the registers tested. EP specifies the branch target. */
9698
9699static void
9700macro_build_branch_rsrt (int type, expressionS *ep,
9701 unsigned int sreg, unsigned int treg)
9702{
9703 const char *brneg = NULL;
9704 const int call = 0;
9705 const char *br;
9706
9707 switch (type)
9708 {
9709 case M_BEQ:
9710 case M_BEQ_I:
9711 br = "beq";
9712 break;
9713 case M_BEQL:
9714 case M_BEQL_I:
9715 br = mips_opts.micromips ? "beq" : "beql";
9716 brneg = "bne";
9717 break;
9718 case M_BNE:
9719 case M_BNE_I:
9720 br = "bne";
9721 break;
9722 case M_BNEL:
9723 case M_BNEL_I:
9724 br = mips_opts.micromips ? "bne" : "bnel";
9725 brneg = "beq";
9726 break;
9727 default:
9728 abort ();
9729 }
9730 if (mips_opts.micromips && brneg)
9731 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9732 else
9733 macro_build (ep, br, "s,t,p", sreg, treg);
9734}
9735
f2ae14a1
RS
9736/* Return the high part that should be loaded in order to make the low
9737 part of VALUE accessible using an offset of OFFBITS bits. */
9738
9739static offsetT
9740offset_high_part (offsetT value, unsigned int offbits)
9741{
9742 offsetT bias;
9743 addressT low_mask;
9744
9745 if (offbits == 0)
9746 return value;
9747 bias = 1 << (offbits - 1);
9748 low_mask = bias * 2 - 1;
9749 return (value + bias) & ~low_mask;
9750}
9751
9752/* Return true if the value stored in offset_expr and offset_reloc
9753 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9754 amount that the caller wants to add without inducing overflow
9755 and ALIGN is the known alignment of the value in bytes. */
9756
9757static bfd_boolean
9758small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9759{
9760 if (offbits == 16)
9761 {
9762 /* Accept any relocation operator if overflow isn't a concern. */
9763 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9764 return TRUE;
9765
9766 /* These relocations are guaranteed not to overflow in correct links. */
9767 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9768 || gprel16_reloc_p (*offset_reloc))
9769 return TRUE;
9770 }
9771 if (offset_expr.X_op == O_constant
9772 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9773 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9774 return TRUE;
9775 return FALSE;
9776}
9777
252b5132
RH
9778/*
9779 * Build macros
9780 * This routine implements the seemingly endless macro or synthesized
9781 * instructions and addressing modes in the mips assembly language. Many
9782 * of these macros are simple and are similar to each other. These could
67c1ffbe 9783 * probably be handled by some kind of table or grammar approach instead of
252b5132
RH
9784 * this verbose method. Others are not simple macros but are more like
9785 * optimizing code generation.
9786 * One interesting optimization is when several store macros appear
67c1ffbe 9787 * consecutively that would load AT with the upper half of the same address.
252b5132
RH
9788 * The ensuing load upper instructions are ommited. This implies some kind
9789 * of global optimization. We currently only optimize within a single macro.
9790 * For many of the load and store macros if the address is specified as a
9791 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9792 * first load register 'at' with zero and use it as the base register. The
9793 * mips assembler simply uses register $zero. Just one tiny optimization
9794 * we're missing.
9795 */
9796static void
833794fc 9797macro (struct mips_cl_insn *ip, char *str)
252b5132 9798{
c0ebe874
RS
9799 const struct mips_operand_array *operands;
9800 unsigned int breg, i;
741fe287 9801 unsigned int tempreg;
252b5132 9802 int mask;
43841e91 9803 int used_at = 0;
df58fc94 9804 expressionS label_expr;
252b5132 9805 expressionS expr1;
df58fc94 9806 expressionS *ep;
252b5132
RH
9807 const char *s;
9808 const char *s2;
9809 const char *fmt;
9810 int likely = 0;
252b5132 9811 int coproc = 0;
7f3c4072 9812 int offbits = 16;
1abe91b1 9813 int call = 0;
df58fc94
RS
9814 int jals = 0;
9815 int dbl = 0;
9816 int imm = 0;
9817 int ust = 0;
9818 int lp = 0;
f2ae14a1 9819 bfd_boolean large_offset;
252b5132 9820 int off;
252b5132 9821 int hold_mips_optimize;
f2ae14a1 9822 unsigned int align;
c0ebe874 9823 unsigned int op[MAX_OPERANDS];
252b5132 9824
9c2799c2 9825 gas_assert (! mips_opts.mips16);
252b5132 9826
c0ebe874
RS
9827 operands = insn_operands (ip);
9828 for (i = 0; i < MAX_OPERANDS; i++)
9829 if (operands->operand[i])
9830 op[i] = insn_extract_operand (ip, operands->operand[i]);
9831 else
9832 op[i] = -1;
9833
252b5132
RH
9834 mask = ip->insn_mo->mask;
9835
df58fc94
RS
9836 label_expr.X_op = O_constant;
9837 label_expr.X_op_symbol = NULL;
9838 label_expr.X_add_symbol = NULL;
9839 label_expr.X_add_number = 0;
9840
252b5132
RH
9841 expr1.X_op = O_constant;
9842 expr1.X_op_symbol = NULL;
9843 expr1.X_add_symbol = NULL;
9844 expr1.X_add_number = 1;
f2ae14a1 9845 align = 1;
252b5132
RH
9846
9847 switch (mask)
9848 {
9849 case M_DABS:
9850 dbl = 1;
1a0670f3 9851 /* Fall through. */
252b5132 9852 case M_ABS:
df58fc94
RS
9853 /* bgez $a0,1f
9854 move v0,$a0
9855 sub v0,$zero,$a0
9856 1:
9857 */
252b5132 9858
7d10b47d 9859 start_noreorder ();
252b5132 9860
df58fc94
RS
9861 if (mips_opts.micromips)
9862 micromips_label_expr (&label_expr);
9863 else
9864 label_expr.X_add_number = 8;
c0ebe874
RS
9865 macro_build (&label_expr, "bgez", "s,p", op[1]);
9866 if (op[0] == op[1])
a605d2b3 9867 macro_build (NULL, "nop", "");
252b5132 9868 else
c0ebe874
RS
9869 move_register (op[0], op[1]);
9870 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
df58fc94
RS
9871 if (mips_opts.micromips)
9872 micromips_add_label ();
252b5132 9873
7d10b47d 9874 end_noreorder ();
8fc2e39e 9875 break;
252b5132
RH
9876
9877 case M_ADD_I:
9878 s = "addi";
9879 s2 = "add";
9880 goto do_addi;
9881 case M_ADDU_I:
9882 s = "addiu";
9883 s2 = "addu";
9884 goto do_addi;
9885 case M_DADD_I:
9886 dbl = 1;
9887 s = "daddi";
9888 s2 = "dadd";
df58fc94
RS
9889 if (!mips_opts.micromips)
9890 goto do_addi;
b0e6f033 9891 if (imm_expr.X_add_number >= -0x200
df58fc94
RS
9892 && imm_expr.X_add_number < 0x200)
9893 {
b0e6f033
RS
9894 macro_build (NULL, s, "t,r,.", op[0], op[1],
9895 (int) imm_expr.X_add_number);
df58fc94
RS
9896 break;
9897 }
9898 goto do_addi_i;
252b5132
RH
9899 case M_DADDU_I:
9900 dbl = 1;
9901 s = "daddiu";
9902 s2 = "daddu";
9903 do_addi:
b0e6f033 9904 if (imm_expr.X_add_number >= -0x8000
252b5132
RH
9905 && imm_expr.X_add_number < 0x8000)
9906 {
c0ebe874 9907 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 9908 break;
252b5132 9909 }
df58fc94 9910 do_addi_i:
8fc2e39e 9911 used_at = 1;
67c0d1eb 9912 load_register (AT, &imm_expr, dbl);
c0ebe874 9913 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
9914 break;
9915
9916 case M_AND_I:
9917 s = "andi";
9918 s2 = "and";
9919 goto do_bit;
9920 case M_OR_I:
9921 s = "ori";
9922 s2 = "or";
9923 goto do_bit;
9924 case M_NOR_I:
9925 s = "";
9926 s2 = "nor";
9927 goto do_bit;
9928 case M_XOR_I:
9929 s = "xori";
9930 s2 = "xor";
9931 do_bit:
b0e6f033 9932 if (imm_expr.X_add_number >= 0
252b5132
RH
9933 && imm_expr.X_add_number < 0x10000)
9934 {
9935 if (mask != M_NOR_I)
c0ebe874 9936 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
9937 else
9938 {
67c0d1eb 9939 macro_build (&imm_expr, "ori", "t,r,i",
c0ebe874
RS
9940 op[0], op[1], BFD_RELOC_LO16);
9941 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
252b5132 9942 }
8fc2e39e 9943 break;
252b5132
RH
9944 }
9945
8fc2e39e 9946 used_at = 1;
bad1aba3 9947 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 9948 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
9949 break;
9950
8b082fb1
TS
9951 case M_BALIGN:
9952 switch (imm_expr.X_add_number)
9953 {
9954 case 0:
9955 macro_build (NULL, "nop", "");
9956 break;
9957 case 2:
c0ebe874 9958 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
8b082fb1 9959 break;
03f66e8a
MR
9960 case 1:
9961 case 3:
c0ebe874 9962 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
90ecf173 9963 (int) imm_expr.X_add_number);
8b082fb1 9964 break;
03f66e8a
MR
9965 default:
9966 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9967 (unsigned long) imm_expr.X_add_number);
9968 break;
8b082fb1
TS
9969 }
9970 break;
9971
df58fc94
RS
9972 case M_BC1FL:
9973 case M_BC1TL:
9974 case M_BC2FL:
9975 case M_BC2TL:
9976 gas_assert (mips_opts.micromips);
9977 macro_build_branch_ccl (mask, &offset_expr,
9978 EXTRACT_OPERAND (1, BCC, *ip));
9979 break;
9980
252b5132 9981 case M_BEQ_I:
252b5132 9982 case M_BEQL_I:
252b5132 9983 case M_BNE_I:
252b5132 9984 case M_BNEL_I:
b0e6f033 9985 if (imm_expr.X_add_number == 0)
c0ebe874 9986 op[1] = 0;
df58fc94 9987 else
252b5132 9988 {
c0ebe874 9989 op[1] = AT;
df58fc94 9990 used_at = 1;
bad1aba3 9991 load_register (op[1], &imm_expr, GPR_SIZE == 64);
252b5132 9992 }
df58fc94
RS
9993 /* Fall through. */
9994 case M_BEQL:
9995 case M_BNEL:
c0ebe874 9996 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
252b5132
RH
9997 break;
9998
9999 case M_BGEL:
10000 likely = 1;
1a0670f3 10001 /* Fall through. */
252b5132 10002 case M_BGE:
c0ebe874
RS
10003 if (op[1] == 0)
10004 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
10005 else if (op[0] == 0)
10006 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
df58fc94 10007 else
252b5132 10008 {
df58fc94 10009 used_at = 1;
c0ebe874 10010 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
10011 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10012 &offset_expr, AT, ZERO);
252b5132 10013 }
df58fc94
RS
10014 break;
10015
10016 case M_BGEZL:
10017 case M_BGEZALL:
10018 case M_BGTZL:
10019 case M_BLEZL:
10020 case M_BLTZL:
10021 case M_BLTZALL:
c0ebe874 10022 macro_build_branch_rs (mask, &offset_expr, op[0]);
252b5132
RH
10023 break;
10024
10025 case M_BGTL_I:
10026 likely = 1;
1a0670f3 10027 /* Fall through. */
252b5132 10028 case M_BGT_I:
90ecf173 10029 /* Check for > max integer. */
b0e6f033 10030 if (imm_expr.X_add_number >= GPR_SMAX)
252b5132
RH
10031 {
10032 do_false:
90ecf173 10033 /* Result is always false. */
252b5132 10034 if (! likely)
a605d2b3 10035 macro_build (NULL, "nop", "");
252b5132 10036 else
df58fc94 10037 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8fc2e39e 10038 break;
252b5132 10039 }
f9419b05 10040 ++imm_expr.X_add_number;
252b5132
RH
10041 /* FALLTHROUGH */
10042 case M_BGE_I:
10043 case M_BGEL_I:
10044 if (mask == M_BGEL_I)
10045 likely = 1;
b0e6f033 10046 if (imm_expr.X_add_number == 0)
252b5132 10047 {
df58fc94 10048 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
c0ebe874 10049 &offset_expr, op[0]);
8fc2e39e 10050 break;
252b5132 10051 }
b0e6f033 10052 if (imm_expr.X_add_number == 1)
252b5132 10053 {
df58fc94 10054 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
c0ebe874 10055 &offset_expr, op[0]);
8fc2e39e 10056 break;
252b5132 10057 }
b0e6f033 10058 if (imm_expr.X_add_number <= GPR_SMIN)
252b5132
RH
10059 {
10060 do_true:
10061 /* result is always true */
1661c76c 10062 as_warn (_("branch %s is always true"), ip->insn_mo->name);
67c0d1eb 10063 macro_build (&offset_expr, "b", "p");
8fc2e39e 10064 break;
252b5132 10065 }
8fc2e39e 10066 used_at = 1;
c0ebe874 10067 set_at (op[0], 0);
df58fc94
RS
10068 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10069 &offset_expr, AT, ZERO);
252b5132
RH
10070 break;
10071
10072 case M_BGEUL:
10073 likely = 1;
1a0670f3 10074 /* Fall through. */
252b5132 10075 case M_BGEU:
c0ebe874 10076 if (op[1] == 0)
252b5132 10077 goto do_true;
c0ebe874 10078 else if (op[0] == 0)
df58fc94 10079 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874 10080 &offset_expr, ZERO, op[1]);
df58fc94 10081 else
252b5132 10082 {
df58fc94 10083 used_at = 1;
c0ebe874 10084 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
10085 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10086 &offset_expr, AT, ZERO);
252b5132 10087 }
252b5132
RH
10088 break;
10089
10090 case M_BGTUL_I:
10091 likely = 1;
1a0670f3 10092 /* Fall through. */
252b5132 10093 case M_BGTU_I:
c0ebe874 10094 if (op[0] == 0
bad1aba3 10095 || (GPR_SIZE == 32
f01dc953 10096 && imm_expr.X_add_number == -1))
252b5132 10097 goto do_false;
f9419b05 10098 ++imm_expr.X_add_number;
252b5132
RH
10099 /* FALLTHROUGH */
10100 case M_BGEU_I:
10101 case M_BGEUL_I:
10102 if (mask == M_BGEUL_I)
10103 likely = 1;
b0e6f033 10104 if (imm_expr.X_add_number == 0)
252b5132 10105 goto do_true;
b0e6f033 10106 else if (imm_expr.X_add_number == 1)
df58fc94 10107 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874 10108 &offset_expr, op[0], ZERO);
df58fc94 10109 else
252b5132 10110 {
df58fc94 10111 used_at = 1;
c0ebe874 10112 set_at (op[0], 1);
df58fc94
RS
10113 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10114 &offset_expr, AT, ZERO);
252b5132 10115 }
252b5132
RH
10116 break;
10117
10118 case M_BGTL:
10119 likely = 1;
1a0670f3 10120 /* Fall through. */
252b5132 10121 case M_BGT:
c0ebe874
RS
10122 if (op[1] == 0)
10123 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10124 else if (op[0] == 0)
10125 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
df58fc94 10126 else
252b5132 10127 {
df58fc94 10128 used_at = 1;
c0ebe874 10129 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
10130 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10131 &offset_expr, AT, ZERO);
252b5132 10132 }
252b5132
RH
10133 break;
10134
10135 case M_BGTUL:
10136 likely = 1;
1a0670f3 10137 /* Fall through. */
252b5132 10138 case M_BGTU:
c0ebe874 10139 if (op[1] == 0)
df58fc94 10140 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874
RS
10141 &offset_expr, op[0], ZERO);
10142 else if (op[0] == 0)
df58fc94
RS
10143 goto do_false;
10144 else
252b5132 10145 {
df58fc94 10146 used_at = 1;
c0ebe874 10147 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
10148 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10149 &offset_expr, AT, ZERO);
252b5132 10150 }
252b5132
RH
10151 break;
10152
10153 case M_BLEL:
10154 likely = 1;
1a0670f3 10155 /* Fall through. */
252b5132 10156 case M_BLE:
c0ebe874
RS
10157 if (op[1] == 0)
10158 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10159 else if (op[0] == 0)
10160 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
df58fc94 10161 else
252b5132 10162 {
df58fc94 10163 used_at = 1;
c0ebe874 10164 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
10165 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10166 &offset_expr, AT, ZERO);
252b5132 10167 }
252b5132
RH
10168 break;
10169
10170 case M_BLEL_I:
10171 likely = 1;
1a0670f3 10172 /* Fall through. */
252b5132 10173 case M_BLE_I:
b0e6f033 10174 if (imm_expr.X_add_number >= GPR_SMAX)
252b5132 10175 goto do_true;
f9419b05 10176 ++imm_expr.X_add_number;
252b5132
RH
10177 /* FALLTHROUGH */
10178 case M_BLT_I:
10179 case M_BLTL_I:
10180 if (mask == M_BLTL_I)
10181 likely = 1;
b0e6f033 10182 if (imm_expr.X_add_number == 0)
c0ebe874 10183 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
b0e6f033 10184 else if (imm_expr.X_add_number == 1)
c0ebe874 10185 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
df58fc94 10186 else
252b5132 10187 {
df58fc94 10188 used_at = 1;
c0ebe874 10189 set_at (op[0], 0);
df58fc94
RS
10190 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10191 &offset_expr, AT, ZERO);
252b5132 10192 }
252b5132
RH
10193 break;
10194
10195 case M_BLEUL:
10196 likely = 1;
1a0670f3 10197 /* Fall through. */
252b5132 10198 case M_BLEU:
c0ebe874 10199 if (op[1] == 0)
df58fc94 10200 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874
RS
10201 &offset_expr, op[0], ZERO);
10202 else if (op[0] == 0)
df58fc94
RS
10203 goto do_true;
10204 else
252b5132 10205 {
df58fc94 10206 used_at = 1;
c0ebe874 10207 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
df58fc94
RS
10208 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10209 &offset_expr, AT, ZERO);
252b5132 10210 }
252b5132
RH
10211 break;
10212
10213 case M_BLEUL_I:
10214 likely = 1;
1a0670f3 10215 /* Fall through. */
252b5132 10216 case M_BLEU_I:
c0ebe874 10217 if (op[0] == 0
bad1aba3 10218 || (GPR_SIZE == 32
f01dc953 10219 && imm_expr.X_add_number == -1))
252b5132 10220 goto do_true;
f9419b05 10221 ++imm_expr.X_add_number;
252b5132
RH
10222 /* FALLTHROUGH */
10223 case M_BLTU_I:
10224 case M_BLTUL_I:
10225 if (mask == M_BLTUL_I)
10226 likely = 1;
b0e6f033 10227 if (imm_expr.X_add_number == 0)
252b5132 10228 goto do_false;
b0e6f033 10229 else if (imm_expr.X_add_number == 1)
df58fc94 10230 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
c0ebe874 10231 &offset_expr, op[0], ZERO);
df58fc94 10232 else
252b5132 10233 {
df58fc94 10234 used_at = 1;
c0ebe874 10235 set_at (op[0], 1);
df58fc94
RS
10236 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10237 &offset_expr, AT, ZERO);
252b5132 10238 }
252b5132
RH
10239 break;
10240
10241 case M_BLTL:
10242 likely = 1;
1a0670f3 10243 /* Fall through. */
252b5132 10244 case M_BLT:
c0ebe874
RS
10245 if (op[1] == 0)
10246 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10247 else if (op[0] == 0)
10248 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
df58fc94 10249 else
252b5132 10250 {
df58fc94 10251 used_at = 1;
c0ebe874 10252 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
10253 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10254 &offset_expr, AT, ZERO);
252b5132 10255 }
252b5132
RH
10256 break;
10257
10258 case M_BLTUL:
10259 likely = 1;
1a0670f3 10260 /* Fall through. */
252b5132 10261 case M_BLTU:
c0ebe874 10262 if (op[1] == 0)
252b5132 10263 goto do_false;
c0ebe874 10264 else if (op[0] == 0)
df58fc94 10265 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
c0ebe874 10266 &offset_expr, ZERO, op[1]);
df58fc94 10267 else
252b5132 10268 {
df58fc94 10269 used_at = 1;
c0ebe874 10270 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
df58fc94
RS
10271 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10272 &offset_expr, AT, ZERO);
252b5132 10273 }
252b5132
RH
10274 break;
10275
10276 case M_DDIV_3:
10277 dbl = 1;
1a0670f3 10278 /* Fall through. */
252b5132
RH
10279 case M_DIV_3:
10280 s = "mflo";
10281 goto do_div3;
10282 case M_DREM_3:
10283 dbl = 1;
1a0670f3 10284 /* Fall through. */
252b5132
RH
10285 case M_REM_3:
10286 s = "mfhi";
10287 do_div3:
c0ebe874 10288 if (op[2] == 0)
252b5132 10289 {
1661c76c 10290 as_warn (_("divide by zero"));
252b5132 10291 if (mips_trap)
df58fc94 10292 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 10293 else
df58fc94 10294 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 10295 break;
252b5132
RH
10296 }
10297
7d10b47d 10298 start_noreorder ();
252b5132
RH
10299 if (mips_trap)
10300 {
c0ebe874
RS
10301 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10302 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
252b5132
RH
10303 }
10304 else
10305 {
df58fc94
RS
10306 if (mips_opts.micromips)
10307 micromips_label_expr (&label_expr);
10308 else
10309 label_expr.X_add_number = 8;
c0ebe874
RS
10310 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10311 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
df58fc94
RS
10312 macro_build (NULL, "break", BRK_FMT, 7);
10313 if (mips_opts.micromips)
10314 micromips_add_label ();
252b5132
RH
10315 }
10316 expr1.X_add_number = -1;
8fc2e39e 10317 used_at = 1;
f6a22291 10318 load_register (AT, &expr1, dbl);
df58fc94
RS
10319 if (mips_opts.micromips)
10320 micromips_label_expr (&label_expr);
10321 else
10322 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
c0ebe874 10323 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
252b5132
RH
10324 if (dbl)
10325 {
10326 expr1.X_add_number = 1;
f6a22291 10327 load_register (AT, &expr1, dbl);
df58fc94 10328 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
252b5132
RH
10329 }
10330 else
10331 {
10332 expr1.X_add_number = 0x80000000;
df58fc94 10333 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
252b5132
RH
10334 }
10335 if (mips_trap)
10336 {
c0ebe874 10337 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
252b5132
RH
10338 /* We want to close the noreorder block as soon as possible, so
10339 that later insns are available for delay slot filling. */
7d10b47d 10340 end_noreorder ();
252b5132
RH
10341 }
10342 else
10343 {
df58fc94
RS
10344 if (mips_opts.micromips)
10345 micromips_label_expr (&label_expr);
10346 else
10347 label_expr.X_add_number = 8;
c0ebe874 10348 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
a605d2b3 10349 macro_build (NULL, "nop", "");
252b5132
RH
10350
10351 /* We want to close the noreorder block as soon as possible, so
10352 that later insns are available for delay slot filling. */
7d10b47d 10353 end_noreorder ();
252b5132 10354
df58fc94 10355 macro_build (NULL, "break", BRK_FMT, 6);
252b5132 10356 }
df58fc94
RS
10357 if (mips_opts.micromips)
10358 micromips_add_label ();
c0ebe874 10359 macro_build (NULL, s, MFHL_FMT, op[0]);
252b5132
RH
10360 break;
10361
10362 case M_DIV_3I:
10363 s = "div";
10364 s2 = "mflo";
10365 goto do_divi;
10366 case M_DIVU_3I:
10367 s = "divu";
10368 s2 = "mflo";
10369 goto do_divi;
10370 case M_REM_3I:
10371 s = "div";
10372 s2 = "mfhi";
10373 goto do_divi;
10374 case M_REMU_3I:
10375 s = "divu";
10376 s2 = "mfhi";
10377 goto do_divi;
10378 case M_DDIV_3I:
10379 dbl = 1;
10380 s = "ddiv";
10381 s2 = "mflo";
10382 goto do_divi;
10383 case M_DDIVU_3I:
10384 dbl = 1;
10385 s = "ddivu";
10386 s2 = "mflo";
10387 goto do_divi;
10388 case M_DREM_3I:
10389 dbl = 1;
10390 s = "ddiv";
10391 s2 = "mfhi";
10392 goto do_divi;
10393 case M_DREMU_3I:
10394 dbl = 1;
10395 s = "ddivu";
10396 s2 = "mfhi";
10397 do_divi:
b0e6f033 10398 if (imm_expr.X_add_number == 0)
252b5132 10399 {
1661c76c 10400 as_warn (_("divide by zero"));
252b5132 10401 if (mips_trap)
df58fc94 10402 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
252b5132 10403 else
df58fc94 10404 macro_build (NULL, "break", BRK_FMT, 7);
8fc2e39e 10405 break;
252b5132 10406 }
b0e6f033 10407 if (imm_expr.X_add_number == 1)
252b5132
RH
10408 {
10409 if (strcmp (s2, "mflo") == 0)
c0ebe874 10410 move_register (op[0], op[1]);
252b5132 10411 else
c0ebe874 10412 move_register (op[0], ZERO);
8fc2e39e 10413 break;
252b5132 10414 }
b0e6f033 10415 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
252b5132
RH
10416 {
10417 if (strcmp (s2, "mflo") == 0)
c0ebe874 10418 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
252b5132 10419 else
c0ebe874 10420 move_register (op[0], ZERO);
8fc2e39e 10421 break;
252b5132
RH
10422 }
10423
8fc2e39e 10424 used_at = 1;
67c0d1eb 10425 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
10426 macro_build (NULL, s, "z,s,t", op[1], AT);
10427 macro_build (NULL, s2, MFHL_FMT, op[0]);
252b5132
RH
10428 break;
10429
10430 case M_DIVU_3:
10431 s = "divu";
10432 s2 = "mflo";
10433 goto do_divu3;
10434 case M_REMU_3:
10435 s = "divu";
10436 s2 = "mfhi";
10437 goto do_divu3;
10438 case M_DDIVU_3:
10439 s = "ddivu";
10440 s2 = "mflo";
10441 goto do_divu3;
10442 case M_DREMU_3:
10443 s = "ddivu";
10444 s2 = "mfhi";
10445 do_divu3:
7d10b47d 10446 start_noreorder ();
252b5132
RH
10447 if (mips_trap)
10448 {
c0ebe874
RS
10449 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10450 macro_build (NULL, s, "z,s,t", op[1], op[2]);
252b5132
RH
10451 /* We want to close the noreorder block as soon as possible, so
10452 that later insns are available for delay slot filling. */
7d10b47d 10453 end_noreorder ();
252b5132
RH
10454 }
10455 else
10456 {
df58fc94
RS
10457 if (mips_opts.micromips)
10458 micromips_label_expr (&label_expr);
10459 else
10460 label_expr.X_add_number = 8;
c0ebe874
RS
10461 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10462 macro_build (NULL, s, "z,s,t", op[1], op[2]);
252b5132
RH
10463
10464 /* We want to close the noreorder block as soon as possible, so
10465 that later insns are available for delay slot filling. */
7d10b47d 10466 end_noreorder ();
df58fc94
RS
10467 macro_build (NULL, "break", BRK_FMT, 7);
10468 if (mips_opts.micromips)
10469 micromips_add_label ();
252b5132 10470 }
c0ebe874 10471 macro_build (NULL, s2, MFHL_FMT, op[0]);
8fc2e39e 10472 break;
252b5132 10473
1abe91b1
MR
10474 case M_DLCA_AB:
10475 dbl = 1;
1a0670f3 10476 /* Fall through. */
1abe91b1
MR
10477 case M_LCA_AB:
10478 call = 1;
10479 goto do_la;
252b5132
RH
10480 case M_DLA_AB:
10481 dbl = 1;
1a0670f3 10482 /* Fall through. */
252b5132 10483 case M_LA_AB:
1abe91b1 10484 do_la:
252b5132
RH
10485 /* Load the address of a symbol into a register. If breg is not
10486 zero, we then add a base register to it. */
10487
c0ebe874 10488 breg = op[2];
bad1aba3 10489 if (dbl && GPR_SIZE == 32)
ece794d9
MF
10490 as_warn (_("dla used to load 32-bit register; recommend using la "
10491 "instead"));
3bec30a8 10492
90ecf173 10493 if (!dbl && HAVE_64BIT_OBJECTS)
ece794d9
MF
10494 as_warn (_("la used to load 64-bit address; recommend using dla "
10495 "instead"));
3bec30a8 10496
f2ae14a1 10497 if (small_offset_p (0, align, 16))
0c11417f 10498 {
c0ebe874 10499 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
f2ae14a1 10500 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8fc2e39e 10501 break;
0c11417f
MR
10502 }
10503
c0ebe874 10504 if (mips_opts.at && (op[0] == breg))
afdbd6d0
CD
10505 {
10506 tempreg = AT;
10507 used_at = 1;
10508 }
10509 else
c0ebe874 10510 tempreg = op[0];
afdbd6d0 10511
252b5132
RH
10512 if (offset_expr.X_op != O_symbol
10513 && offset_expr.X_op != O_constant)
10514 {
1661c76c 10515 as_bad (_("expression too complex"));
252b5132
RH
10516 offset_expr.X_op = O_constant;
10517 }
10518
252b5132 10519 if (offset_expr.X_op == O_constant)
aed1a261 10520 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
252b5132
RH
10521 else if (mips_pic == NO_PIC)
10522 {
d6bc6245 10523 /* If this is a reference to a GP relative symbol, we want
cdf6fd85 10524 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
252b5132
RH
10525 Otherwise we want
10526 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10527 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10528 If we have a constant, we need two instructions anyhow,
d6bc6245 10529 so we may as well always use the latter form.
76b3015f 10530
6caf9ef4
TS
10531 With 64bit address space and a usable $at we want
10532 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10533 lui $at,<sym> (BFD_RELOC_HI16_S)
10534 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10535 daddiu $at,<sym> (BFD_RELOC_LO16)
10536 dsll32 $tempreg,0
10537 daddu $tempreg,$tempreg,$at
10538
10539 If $at is already in use, we use a path which is suboptimal
10540 on superscalar processors.
10541 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10542 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10543 dsll $tempreg,16
10544 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10545 dsll $tempreg,16
10546 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10547
10548 For GP relative symbols in 64bit address space we can use
10549 the same sequence as in 32bit address space. */
aed1a261 10550 if (HAVE_64BIT_SYMBOLS)
252b5132 10551 {
6caf9ef4
TS
10552 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10553 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10554 {
10555 relax_start (offset_expr.X_add_symbol);
10556 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10557 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10558 relax_switch ();
10559 }
d6bc6245 10560
741fe287 10561 if (used_at == 0 && mips_opts.at)
98d3f06f 10562 {
df58fc94 10563 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 10564 tempreg, BFD_RELOC_MIPS_HIGHEST);
df58fc94 10565 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 10566 AT, BFD_RELOC_HI16_S);
67c0d1eb 10567 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10568 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
67c0d1eb 10569 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10570 AT, AT, BFD_RELOC_LO16);
df58fc94 10571 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 10572 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
98d3f06f
KH
10573 used_at = 1;
10574 }
10575 else
10576 {
df58fc94 10577 macro_build (&offset_expr, "lui", LUI_FMT,
17a2f251 10578 tempreg, BFD_RELOC_MIPS_HIGHEST);
67c0d1eb 10579 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10580 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 10581 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 10582 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10583 tempreg, tempreg, BFD_RELOC_HI16_S);
df58fc94 10584 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb 10585 macro_build (&offset_expr, "daddiu", "t,r,j",
17a2f251 10586 tempreg, tempreg, BFD_RELOC_LO16);
98d3f06f 10587 }
6caf9ef4
TS
10588
10589 if (mips_relax.sequence)
10590 relax_end ();
98d3f06f
KH
10591 }
10592 else
10593 {
10594 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 10595 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
98d3f06f 10596 {
4d7206a2 10597 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10598 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10599 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4d7206a2 10600 relax_switch ();
98d3f06f 10601 }
6943caf0 10602 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
1661c76c 10603 as_bad (_("offset too large"));
67c0d1eb
RS
10604 macro_build_lui (&offset_expr, tempreg);
10605 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10606 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2
RS
10607 if (mips_relax.sequence)
10608 relax_end ();
98d3f06f 10609 }
252b5132 10610 }
0a44bf69 10611 else if (!mips_big_got && !HAVE_NEWABI)
252b5132 10612 {
9117d219
NC
10613 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10614
252b5132
RH
10615 /* If this is a reference to an external symbol, and there
10616 is no constant, we want
10617 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1abe91b1 10618 or for lca or if tempreg is PIC_CALL_REG
9117d219 10619 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
252b5132
RH
10620 For a local symbol, we want
10621 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10622 nop
10623 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10624
10625 If we have a small constant, and this is a reference to
10626 an external symbol, we want
10627 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10628 nop
10629 addiu $tempreg,$tempreg,<constant>
10630 For a local symbol, we want the same instruction
10631 sequence, but we output a BFD_RELOC_LO16 reloc on the
10632 addiu instruction.
10633
10634 If we have a large constant, and this is a reference to
10635 an external symbol, we want
10636 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10637 lui $at,<hiconstant>
10638 addiu $at,$at,<loconstant>
10639 addu $tempreg,$tempreg,$at
10640 For a local symbol, we want the same instruction
10641 sequence, but we output a BFD_RELOC_LO16 reloc on the
ed6fb7bd 10642 addiu instruction.
ed6fb7bd
SC
10643 */
10644
4d7206a2 10645 if (offset_expr.X_add_number == 0)
252b5132 10646 {
0a44bf69
RS
10647 if (mips_pic == SVR4_PIC
10648 && breg == 0
10649 && (call || tempreg == PIC_CALL_REG))
4d7206a2
RS
10650 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10651
10652 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10653 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10654 lw_reloc_type, mips_gp_register);
4d7206a2 10655 if (breg != 0)
252b5132
RH
10656 {
10657 /* We're going to put in an addu instruction using
10658 tempreg, so we may as well insert the nop right
10659 now. */
269137b2 10660 load_delay_nop ();
252b5132 10661 }
4d7206a2 10662 relax_switch ();
67c0d1eb
RS
10663 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10664 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 10665 load_delay_nop ();
67c0d1eb
RS
10666 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10667 tempreg, tempreg, BFD_RELOC_LO16);
4d7206a2 10668 relax_end ();
252b5132
RH
10669 /* FIXME: If breg == 0, and the next instruction uses
10670 $tempreg, then if this variant case is used an extra
10671 nop will be generated. */
10672 }
4d7206a2
RS
10673 else if (offset_expr.X_add_number >= -0x8000
10674 && offset_expr.X_add_number < 0x8000)
252b5132 10675 {
67c0d1eb 10676 load_got_offset (tempreg, &offset_expr);
269137b2 10677 load_delay_nop ();
67c0d1eb 10678 add_got_offset (tempreg, &offset_expr);
252b5132
RH
10679 }
10680 else
10681 {
4d7206a2
RS
10682 expr1.X_add_number = offset_expr.X_add_number;
10683 offset_expr.X_add_number =
43c0598f 10684 SEXT_16BIT (offset_expr.X_add_number);
67c0d1eb 10685 load_got_offset (tempreg, &offset_expr);
f6a22291 10686 offset_expr.X_add_number = expr1.X_add_number;
252b5132
RH
10687 /* If we are going to add in a base register, and the
10688 target register and the base register are the same,
10689 then we are using AT as a temporary register. Since
10690 we want to load the constant into AT, we add our
10691 current AT (from the global offset table) and the
10692 register into the register now, and pretend we were
10693 not using a base register. */
c0ebe874 10694 if (breg == op[0])
252b5132 10695 {
269137b2 10696 load_delay_nop ();
67c0d1eb 10697 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 10698 op[0], AT, breg);
252b5132 10699 breg = 0;
c0ebe874 10700 tempreg = op[0];
252b5132 10701 }
f6a22291 10702 add_got_offset_hilo (tempreg, &offset_expr, AT);
252b5132
RH
10703 used_at = 1;
10704 }
10705 }
0a44bf69 10706 else if (!mips_big_got && HAVE_NEWABI)
f5040a92 10707 {
67c0d1eb 10708 int add_breg_early = 0;
f5040a92
AO
10709
10710 /* If this is a reference to an external, and there is no
10711 constant, or local symbol (*), with or without a
10712 constant, we want
10713 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
1abe91b1 10714 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
10715 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10716
10717 If we have a small constant, and this is a reference to
10718 an external symbol, we want
10719 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10720 addiu $tempreg,$tempreg,<constant>
10721
10722 If we have a large constant, and this is a reference to
10723 an external symbol, we want
10724 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10725 lui $at,<hiconstant>
10726 addiu $at,$at,<loconstant>
10727 addu $tempreg,$tempreg,$at
10728
10729 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10730 local symbols, even though it introduces an additional
10731 instruction. */
10732
f5040a92
AO
10733 if (offset_expr.X_add_number)
10734 {
4d7206a2 10735 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
10736 offset_expr.X_add_number = 0;
10737
4d7206a2 10738 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10739 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10740 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
10741
10742 if (expr1.X_add_number >= -0x8000
10743 && expr1.X_add_number < 0x8000)
10744 {
67c0d1eb
RS
10745 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10746 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 10747 }
ecd13cd3 10748 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 10749 {
c0ebe874
RS
10750 unsigned int dreg;
10751
f5040a92
AO
10752 /* If we are going to add in a base register, and the
10753 target register and the base register are the same,
10754 then we are using AT as a temporary register. Since
10755 we want to load the constant into AT, we add our
10756 current AT (from the global offset table) and the
10757 register into the register now, and pretend we were
10758 not using a base register. */
c0ebe874 10759 if (breg != op[0])
f5040a92
AO
10760 dreg = tempreg;
10761 else
10762 {
9c2799c2 10763 gas_assert (tempreg == AT);
67c0d1eb 10764 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10765 op[0], AT, breg);
10766 dreg = op[0];
67c0d1eb 10767 add_breg_early = 1;
f5040a92
AO
10768 }
10769
f6a22291 10770 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10771 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10772 dreg, dreg, AT);
f5040a92 10773
f5040a92
AO
10774 used_at = 1;
10775 }
10776 else
10777 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10778
4d7206a2 10779 relax_switch ();
f5040a92
AO
10780 offset_expr.X_add_number = expr1.X_add_number;
10781
67c0d1eb
RS
10782 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10783 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10784 if (add_breg_early)
f5040a92 10785 {
67c0d1eb 10786 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 10787 op[0], tempreg, breg);
f5040a92 10788 breg = 0;
c0ebe874 10789 tempreg = op[0];
f5040a92 10790 }
4d7206a2 10791 relax_end ();
f5040a92 10792 }
4d7206a2 10793 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
f5040a92 10794 {
4d7206a2 10795 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
10796 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10797 BFD_RELOC_MIPS_CALL16, mips_gp_register);
4d7206a2 10798 relax_switch ();
67c0d1eb
RS
10799 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10800 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4d7206a2 10801 relax_end ();
f5040a92 10802 }
4d7206a2 10803 else
f5040a92 10804 {
67c0d1eb
RS
10805 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10806 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
f5040a92
AO
10807 }
10808 }
0a44bf69 10809 else if (mips_big_got && !HAVE_NEWABI)
252b5132 10810 {
67c0d1eb 10811 int gpdelay;
9117d219
NC
10812 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10813 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
ed6fb7bd 10814 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
252b5132
RH
10815
10816 /* This is the large GOT case. If this is a reference to an
10817 external symbol, and there is no constant, we want
10818 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10819 addu $tempreg,$tempreg,$gp
10820 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 10821 or for lca or if tempreg is PIC_CALL_REG
9117d219
NC
10822 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10823 addu $tempreg,$tempreg,$gp
10824 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
252b5132
RH
10825 For a local symbol, we want
10826 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10827 nop
10828 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10829
10830 If we have a small constant, and this is a reference to
10831 an external symbol, we want
10832 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10833 addu $tempreg,$tempreg,$gp
10834 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10835 nop
10836 addiu $tempreg,$tempreg,<constant>
10837 For a local symbol, we want
10838 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10839 nop
10840 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10841
10842 If we have a large constant, and this is a reference to
10843 an external symbol, we want
10844 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10845 addu $tempreg,$tempreg,$gp
10846 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10847 lui $at,<hiconstant>
10848 addiu $at,$at,<loconstant>
10849 addu $tempreg,$tempreg,$at
10850 For a local symbol, we want
10851 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10852 lui $at,<hiconstant>
10853 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10854 addu $tempreg,$tempreg,$at
f5040a92 10855 */
438c16b8 10856
252b5132
RH
10857 expr1.X_add_number = offset_expr.X_add_number;
10858 offset_expr.X_add_number = 0;
4d7206a2 10859 relax_start (offset_expr.X_add_symbol);
67c0d1eb 10860 gpdelay = reg_needs_delay (mips_gp_register);
1abe91b1
MR
10861 if (expr1.X_add_number == 0 && breg == 0
10862 && (call || tempreg == PIC_CALL_REG))
9117d219
NC
10863 {
10864 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10865 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10866 }
df58fc94 10867 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 10868 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10869 tempreg, tempreg, mips_gp_register);
67c0d1eb 10870 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 10871 tempreg, lw_reloc_type, tempreg);
252b5132
RH
10872 if (expr1.X_add_number == 0)
10873 {
67c0d1eb 10874 if (breg != 0)
252b5132
RH
10875 {
10876 /* We're going to put in an addu instruction using
10877 tempreg, so we may as well insert the nop right
10878 now. */
269137b2 10879 load_delay_nop ();
252b5132 10880 }
252b5132
RH
10881 }
10882 else if (expr1.X_add_number >= -0x8000
10883 && expr1.X_add_number < 0x8000)
10884 {
269137b2 10885 load_delay_nop ();
67c0d1eb 10886 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10887 tempreg, tempreg, BFD_RELOC_LO16);
252b5132
RH
10888 }
10889 else
10890 {
c0ebe874
RS
10891 unsigned int dreg;
10892
252b5132
RH
10893 /* If we are going to add in a base register, and the
10894 target register and the base register are the same,
10895 then we are using AT as a temporary register. Since
10896 we want to load the constant into AT, we add our
10897 current AT (from the global offset table) and the
10898 register into the register now, and pretend we were
10899 not using a base register. */
c0ebe874 10900 if (breg != op[0])
67c0d1eb 10901 dreg = tempreg;
252b5132
RH
10902 else
10903 {
9c2799c2 10904 gas_assert (tempreg == AT);
269137b2 10905 load_delay_nop ();
67c0d1eb 10906 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10907 op[0], AT, breg);
10908 dreg = op[0];
252b5132
RH
10909 }
10910
f6a22291 10911 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 10912 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
252b5132 10913
252b5132
RH
10914 used_at = 1;
10915 }
43c0598f 10916 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
4d7206a2 10917 relax_switch ();
252b5132 10918
67c0d1eb 10919 if (gpdelay)
252b5132
RH
10920 {
10921 /* This is needed because this instruction uses $gp, but
f5040a92 10922 the first instruction on the main stream does not. */
67c0d1eb 10923 macro_build (NULL, "nop", "");
252b5132 10924 }
ed6fb7bd 10925
67c0d1eb
RS
10926 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10927 local_reloc_type, mips_gp_register);
f5040a92 10928 if (expr1.X_add_number >= -0x8000
252b5132
RH
10929 && expr1.X_add_number < 0x8000)
10930 {
269137b2 10931 load_delay_nop ();
67c0d1eb
RS
10932 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10933 tempreg, tempreg, BFD_RELOC_LO16);
252b5132 10934 /* FIXME: If add_number is 0, and there was no base
f5040a92
AO
10935 register, the external symbol case ended with a load,
10936 so if the symbol turns out to not be external, and
10937 the next instruction uses tempreg, an unnecessary nop
10938 will be inserted. */
252b5132
RH
10939 }
10940 else
10941 {
c0ebe874 10942 if (breg == op[0])
252b5132
RH
10943 {
10944 /* We must add in the base register now, as in the
f5040a92 10945 external symbol case. */
9c2799c2 10946 gas_assert (tempreg == AT);
269137b2 10947 load_delay_nop ();
67c0d1eb 10948 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
10949 op[0], AT, breg);
10950 tempreg = op[0];
252b5132 10951 /* We set breg to 0 because we have arranged to add
f5040a92 10952 it in in both cases. */
252b5132
RH
10953 breg = 0;
10954 }
10955
67c0d1eb
RS
10956 macro_build_lui (&expr1, AT);
10957 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 10958 AT, AT, BFD_RELOC_LO16);
67c0d1eb 10959 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 10960 tempreg, tempreg, AT);
8fc2e39e 10961 used_at = 1;
252b5132 10962 }
4d7206a2 10963 relax_end ();
252b5132 10964 }
0a44bf69 10965 else if (mips_big_got && HAVE_NEWABI)
f5040a92 10966 {
f5040a92
AO
10967 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10968 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
67c0d1eb 10969 int add_breg_early = 0;
f5040a92
AO
10970
10971 /* This is the large GOT case. If this is a reference to an
10972 external symbol, and there is no constant, we want
10973 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10974 add $tempreg,$tempreg,$gp
10975 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
1abe91b1 10976 or for lca or if tempreg is PIC_CALL_REG
f5040a92
AO
10977 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10978 add $tempreg,$tempreg,$gp
10979 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10980
10981 If we have a small constant, and this is a reference to
10982 an external symbol, we want
10983 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10984 add $tempreg,$tempreg,$gp
10985 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10986 addi $tempreg,$tempreg,<constant>
10987
10988 If we have a large constant, and this is a reference to
10989 an external symbol, we want
10990 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10991 addu $tempreg,$tempreg,$gp
10992 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10993 lui $at,<hiconstant>
10994 addi $at,$at,<loconstant>
10995 add $tempreg,$tempreg,$at
10996
10997 If we have NewABI, and we know it's a local symbol, we want
10998 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10999 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11000 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11001
4d7206a2 11002 relax_start (offset_expr.X_add_symbol);
f5040a92 11003
4d7206a2 11004 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
11005 offset_expr.X_add_number = 0;
11006
1abe91b1
MR
11007 if (expr1.X_add_number == 0 && breg == 0
11008 && (call || tempreg == PIC_CALL_REG))
f5040a92
AO
11009 {
11010 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11011 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11012 }
df58fc94 11013 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
67c0d1eb 11014 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11015 tempreg, tempreg, mips_gp_register);
67c0d1eb
RS
11016 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11017 tempreg, lw_reloc_type, tempreg);
f5040a92
AO
11018
11019 if (expr1.X_add_number == 0)
4d7206a2 11020 ;
f5040a92
AO
11021 else if (expr1.X_add_number >= -0x8000
11022 && expr1.X_add_number < 0x8000)
11023 {
67c0d1eb 11024 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
17a2f251 11025 tempreg, tempreg, BFD_RELOC_LO16);
f5040a92 11026 }
ecd13cd3 11027 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
f5040a92 11028 {
c0ebe874
RS
11029 unsigned int dreg;
11030
f5040a92
AO
11031 /* If we are going to add in a base register, and the
11032 target register and the base register are the same,
11033 then we are using AT as a temporary register. Since
11034 we want to load the constant into AT, we add our
11035 current AT (from the global offset table) and the
11036 register into the register now, and pretend we were
11037 not using a base register. */
c0ebe874 11038 if (breg != op[0])
f5040a92
AO
11039 dreg = tempreg;
11040 else
11041 {
9c2799c2 11042 gas_assert (tempreg == AT);
67c0d1eb 11043 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874
RS
11044 op[0], AT, breg);
11045 dreg = op[0];
67c0d1eb 11046 add_breg_early = 1;
f5040a92
AO
11047 }
11048
f6a22291 11049 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
67c0d1eb 11050 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
f5040a92 11051
f5040a92
AO
11052 used_at = 1;
11053 }
11054 else
11055 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11056
4d7206a2 11057 relax_switch ();
f5040a92 11058 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
11059 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11060 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11061 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11062 tempreg, BFD_RELOC_MIPS_GOT_OFST);
11063 if (add_breg_early)
f5040a92 11064 {
67c0d1eb 11065 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
c0ebe874 11066 op[0], tempreg, breg);
f5040a92 11067 breg = 0;
c0ebe874 11068 tempreg = op[0];
f5040a92 11069 }
4d7206a2 11070 relax_end ();
f5040a92 11071 }
252b5132
RH
11072 else
11073 abort ();
11074
11075 if (breg != 0)
c0ebe874 11076 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
252b5132
RH
11077 break;
11078
52b6b6b9 11079 case M_MSGSND:
df58fc94 11080 gas_assert (!mips_opts.micromips);
c0ebe874 11081 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
c7af4273 11082 break;
52b6b6b9
JM
11083
11084 case M_MSGLD:
df58fc94 11085 gas_assert (!mips_opts.micromips);
c8276761 11086 macro_build (NULL, "c2", "C", 0x02);
c7af4273 11087 break;
52b6b6b9
JM
11088
11089 case M_MSGLD_T:
df58fc94 11090 gas_assert (!mips_opts.micromips);
c0ebe874 11091 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
c7af4273 11092 break;
52b6b6b9
JM
11093
11094 case M_MSGWAIT:
df58fc94 11095 gas_assert (!mips_opts.micromips);
52b6b6b9 11096 macro_build (NULL, "c2", "C", 3);
c7af4273 11097 break;
52b6b6b9
JM
11098
11099 case M_MSGWAIT_T:
df58fc94 11100 gas_assert (!mips_opts.micromips);
c0ebe874 11101 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
c7af4273 11102 break;
52b6b6b9 11103
252b5132
RH
11104 case M_J_A:
11105 /* The j instruction may not be used in PIC code, since it
11106 requires an absolute address. We convert it to a b
11107 instruction. */
11108 if (mips_pic == NO_PIC)
67c0d1eb 11109 macro_build (&offset_expr, "j", "a");
252b5132 11110 else
67c0d1eb 11111 macro_build (&offset_expr, "b", "p");
8fc2e39e 11112 break;
252b5132
RH
11113
11114 /* The jal instructions must be handled as macros because when
11115 generating PIC code they expand to multi-instruction
11116 sequences. Normally they are simple instructions. */
df58fc94 11117 case M_JALS_1:
c0ebe874
RS
11118 op[1] = op[0];
11119 op[0] = RA;
df58fc94
RS
11120 /* Fall through. */
11121 case M_JALS_2:
11122 gas_assert (mips_opts.micromips);
833794fc
MR
11123 if (mips_opts.insn32)
11124 {
1661c76c 11125 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
833794fc
MR
11126 break;
11127 }
df58fc94
RS
11128 jals = 1;
11129 goto jal;
252b5132 11130 case M_JAL_1:
c0ebe874
RS
11131 op[1] = op[0];
11132 op[0] = RA;
252b5132
RH
11133 /* Fall through. */
11134 case M_JAL_2:
df58fc94 11135 jal:
3e722fb5 11136 if (mips_pic == NO_PIC)
df58fc94
RS
11137 {
11138 s = jals ? "jalrs" : "jalr";
e64af278 11139 if (mips_opts.micromips
833794fc 11140 && !mips_opts.insn32
c0ebe874 11141 && op[0] == RA
e64af278 11142 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
c0ebe874 11143 macro_build (NULL, s, "mj", op[1]);
df58fc94 11144 else
c0ebe874 11145 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
df58fc94 11146 }
0a44bf69 11147 else
252b5132 11148 {
df58fc94
RS
11149 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11150 && mips_cprestore_offset >= 0);
11151
c0ebe874 11152 if (op[1] != PIC_CALL_REG)
252b5132 11153 as_warn (_("MIPS PIC call to register other than $25"));
bdaaa2e1 11154
833794fc
MR
11155 s = ((mips_opts.micromips
11156 && !mips_opts.insn32
11157 && (!mips_opts.noreorder || cprestore))
df58fc94 11158 ? "jalrs" : "jalr");
e64af278 11159 if (mips_opts.micromips
833794fc 11160 && !mips_opts.insn32
c0ebe874 11161 && op[0] == RA
e64af278 11162 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
c0ebe874 11163 macro_build (NULL, s, "mj", op[1]);
df58fc94 11164 else
c0ebe874 11165 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
0a44bf69 11166 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
252b5132 11167 {
6478892d 11168 if (mips_cprestore_offset < 0)
1661c76c 11169 as_warn (_("no .cprestore pseudo-op used in PIC code"));
6478892d
TS
11170 else
11171 {
90ecf173 11172 if (!mips_frame_reg_valid)
7a621144 11173 {
1661c76c 11174 as_warn (_("no .frame pseudo-op used in PIC code"));
7a621144
DJ
11175 /* Quiet this warning. */
11176 mips_frame_reg_valid = 1;
11177 }
90ecf173 11178 if (!mips_cprestore_valid)
7a621144 11179 {
1661c76c 11180 as_warn (_("no .cprestore pseudo-op used in PIC code"));
7a621144
DJ
11181 /* Quiet this warning. */
11182 mips_cprestore_valid = 1;
11183 }
d3fca0b5
MR
11184 if (mips_opts.noreorder)
11185 macro_build (NULL, "nop", "");
6478892d 11186 expr1.X_add_number = mips_cprestore_offset;
134c0c8b 11187 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 11188 mips_gp_register,
256ab948
TS
11189 mips_frame_reg,
11190 HAVE_64BIT_ADDRESSES);
6478892d 11191 }
252b5132
RH
11192 }
11193 }
252b5132 11194
8fc2e39e 11195 break;
252b5132 11196
df58fc94
RS
11197 case M_JALS_A:
11198 gas_assert (mips_opts.micromips);
833794fc
MR
11199 if (mips_opts.insn32)
11200 {
1661c76c 11201 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
833794fc
MR
11202 break;
11203 }
df58fc94
RS
11204 jals = 1;
11205 /* Fall through. */
252b5132
RH
11206 case M_JAL_A:
11207 if (mips_pic == NO_PIC)
df58fc94 11208 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
252b5132
RH
11209 else if (mips_pic == SVR4_PIC)
11210 {
11211 /* If this is a reference to an external symbol, and we are
11212 using a small GOT, we want
11213 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11214 nop
f9419b05 11215 jalr $ra,$25
252b5132
RH
11216 nop
11217 lw $gp,cprestore($sp)
11218 The cprestore value is set using the .cprestore
11219 pseudo-op. If we are using a big GOT, we want
11220 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11221 addu $25,$25,$gp
11222 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11223 nop
f9419b05 11224 jalr $ra,$25
252b5132
RH
11225 nop
11226 lw $gp,cprestore($sp)
11227 If the symbol is not external, we want
11228 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11229 nop
11230 addiu $25,$25,<sym> (BFD_RELOC_LO16)
f9419b05 11231 jalr $ra,$25
252b5132 11232 nop
438c16b8 11233 lw $gp,cprestore($sp)
f5040a92
AO
11234
11235 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11236 sequences above, minus nops, unless the symbol is local,
11237 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11238 GOT_DISP. */
438c16b8 11239 if (HAVE_NEWABI)
252b5132 11240 {
90ecf173 11241 if (!mips_big_got)
f5040a92 11242 {
4d7206a2 11243 relax_start (offset_expr.X_add_symbol);
67c0d1eb
RS
11244 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11245 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
f5040a92 11246 mips_gp_register);
4d7206a2 11247 relax_switch ();
67c0d1eb
RS
11248 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11249 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
4d7206a2
RS
11250 mips_gp_register);
11251 relax_end ();
f5040a92
AO
11252 }
11253 else
11254 {
4d7206a2 11255 relax_start (offset_expr.X_add_symbol);
df58fc94 11256 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
11257 BFD_RELOC_MIPS_CALL_HI16);
11258 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11259 PIC_CALL_REG, mips_gp_register);
11260 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11261 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11262 PIC_CALL_REG);
4d7206a2 11263 relax_switch ();
67c0d1eb
RS
11264 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11265 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11266 mips_gp_register);
11267 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11268 PIC_CALL_REG, PIC_CALL_REG,
17a2f251 11269 BFD_RELOC_MIPS_GOT_OFST);
4d7206a2 11270 relax_end ();
f5040a92 11271 }
684022ea 11272
df58fc94 11273 macro_build_jalr (&offset_expr, 0);
252b5132
RH
11274 }
11275 else
11276 {
4d7206a2 11277 relax_start (offset_expr.X_add_symbol);
90ecf173 11278 if (!mips_big_got)
438c16b8 11279 {
67c0d1eb
RS
11280 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11281 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
17a2f251 11282 mips_gp_register);
269137b2 11283 load_delay_nop ();
4d7206a2 11284 relax_switch ();
438c16b8 11285 }
252b5132 11286 else
252b5132 11287 {
67c0d1eb
RS
11288 int gpdelay;
11289
11290 gpdelay = reg_needs_delay (mips_gp_register);
df58fc94 11291 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
67c0d1eb
RS
11292 BFD_RELOC_MIPS_CALL_HI16);
11293 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11294 PIC_CALL_REG, mips_gp_register);
11295 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11296 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11297 PIC_CALL_REG);
269137b2 11298 load_delay_nop ();
4d7206a2 11299 relax_switch ();
67c0d1eb
RS
11300 if (gpdelay)
11301 macro_build (NULL, "nop", "");
252b5132 11302 }
67c0d1eb
RS
11303 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11304 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
4d7206a2 11305 mips_gp_register);
269137b2 11306 load_delay_nop ();
67c0d1eb
RS
11307 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11308 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
4d7206a2 11309 relax_end ();
df58fc94 11310 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
438c16b8 11311
6478892d 11312 if (mips_cprestore_offset < 0)
1661c76c 11313 as_warn (_("no .cprestore pseudo-op used in PIC code"));
6478892d
TS
11314 else
11315 {
90ecf173 11316 if (!mips_frame_reg_valid)
7a621144 11317 {
1661c76c 11318 as_warn (_("no .frame pseudo-op used in PIC code"));
7a621144
DJ
11319 /* Quiet this warning. */
11320 mips_frame_reg_valid = 1;
11321 }
90ecf173 11322 if (!mips_cprestore_valid)
7a621144 11323 {
1661c76c 11324 as_warn (_("no .cprestore pseudo-op used in PIC code"));
7a621144
DJ
11325 /* Quiet this warning. */
11326 mips_cprestore_valid = 1;
11327 }
6478892d 11328 if (mips_opts.noreorder)
67c0d1eb 11329 macro_build (NULL, "nop", "");
6478892d 11330 expr1.X_add_number = mips_cprestore_offset;
134c0c8b 11331 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
f899b4b8 11332 mips_gp_register,
256ab948
TS
11333 mips_frame_reg,
11334 HAVE_64BIT_ADDRESSES);
6478892d 11335 }
252b5132
RH
11336 }
11337 }
0a44bf69 11338 else if (mips_pic == VXWORKS_PIC)
1661c76c 11339 as_bad (_("non-PIC jump used in PIC library"));
252b5132
RH
11340 else
11341 abort ();
11342
8fc2e39e 11343 break;
252b5132 11344
7f3c4072 11345 case M_LBUE_AB:
7f3c4072
CM
11346 s = "lbue";
11347 fmt = "t,+j(b)";
11348 offbits = 9;
11349 goto ld_st;
11350 case M_LHUE_AB:
7f3c4072
CM
11351 s = "lhue";
11352 fmt = "t,+j(b)";
11353 offbits = 9;
11354 goto ld_st;
11355 case M_LBE_AB:
7f3c4072
CM
11356 s = "lbe";
11357 fmt = "t,+j(b)";
11358 offbits = 9;
11359 goto ld_st;
11360 case M_LHE_AB:
7f3c4072
CM
11361 s = "lhe";
11362 fmt = "t,+j(b)";
11363 offbits = 9;
11364 goto ld_st;
11365 case M_LLE_AB:
7f3c4072
CM
11366 s = "lle";
11367 fmt = "t,+j(b)";
11368 offbits = 9;
11369 goto ld_st;
11370 case M_LWE_AB:
7f3c4072
CM
11371 s = "lwe";
11372 fmt = "t,+j(b)";
11373 offbits = 9;
11374 goto ld_st;
11375 case M_LWLE_AB:
7f3c4072
CM
11376 s = "lwle";
11377 fmt = "t,+j(b)";
11378 offbits = 9;
11379 goto ld_st;
11380 case M_LWRE_AB:
7f3c4072
CM
11381 s = "lwre";
11382 fmt = "t,+j(b)";
11383 offbits = 9;
11384 goto ld_st;
11385 case M_SBE_AB:
7f3c4072
CM
11386 s = "sbe";
11387 fmt = "t,+j(b)";
11388 offbits = 9;
11389 goto ld_st;
11390 case M_SCE_AB:
7f3c4072
CM
11391 s = "sce";
11392 fmt = "t,+j(b)";
11393 offbits = 9;
11394 goto ld_st;
11395 case M_SHE_AB:
7f3c4072
CM
11396 s = "she";
11397 fmt = "t,+j(b)";
11398 offbits = 9;
11399 goto ld_st;
11400 case M_SWE_AB:
7f3c4072
CM
11401 s = "swe";
11402 fmt = "t,+j(b)";
11403 offbits = 9;
11404 goto ld_st;
11405 case M_SWLE_AB:
7f3c4072
CM
11406 s = "swle";
11407 fmt = "t,+j(b)";
11408 offbits = 9;
11409 goto ld_st;
11410 case M_SWRE_AB:
7f3c4072
CM
11411 s = "swre";
11412 fmt = "t,+j(b)";
11413 offbits = 9;
11414 goto ld_st;
dec0624d 11415 case M_ACLR_AB:
dec0624d 11416 s = "aclr";
dec0624d 11417 fmt = "\\,~(b)";
7f3c4072 11418 offbits = 12;
dec0624d
MR
11419 goto ld_st;
11420 case M_ASET_AB:
dec0624d 11421 s = "aset";
dec0624d 11422 fmt = "\\,~(b)";
7f3c4072 11423 offbits = 12;
dec0624d 11424 goto ld_st;
252b5132
RH
11425 case M_LB_AB:
11426 s = "lb";
df58fc94 11427 fmt = "t,o(b)";
252b5132
RH
11428 goto ld;
11429 case M_LBU_AB:
11430 s = "lbu";
df58fc94 11431 fmt = "t,o(b)";
252b5132
RH
11432 goto ld;
11433 case M_LH_AB:
11434 s = "lh";
df58fc94 11435 fmt = "t,o(b)";
252b5132
RH
11436 goto ld;
11437 case M_LHU_AB:
11438 s = "lhu";
df58fc94 11439 fmt = "t,o(b)";
252b5132
RH
11440 goto ld;
11441 case M_LW_AB:
11442 s = "lw";
df58fc94 11443 fmt = "t,o(b)";
252b5132
RH
11444 goto ld;
11445 case M_LWC0_AB:
df58fc94 11446 gas_assert (!mips_opts.micromips);
252b5132 11447 s = "lwc0";
df58fc94 11448 fmt = "E,o(b)";
bdaaa2e1 11449 /* Itbl support may require additional care here. */
252b5132 11450 coproc = 1;
df58fc94 11451 goto ld_st;
252b5132
RH
11452 case M_LWC1_AB:
11453 s = "lwc1";
df58fc94 11454 fmt = "T,o(b)";
bdaaa2e1 11455 /* Itbl support may require additional care here. */
252b5132 11456 coproc = 1;
df58fc94 11457 goto ld_st;
252b5132
RH
11458 case M_LWC2_AB:
11459 s = "lwc2";
df58fc94 11460 fmt = COP12_FMT;
7361da2c
AB
11461 offbits = (mips_opts.micromips ? 12
11462 : ISA_IS_R6 (mips_opts.isa) ? 11
11463 : 16);
bdaaa2e1 11464 /* Itbl support may require additional care here. */
252b5132 11465 coproc = 1;
df58fc94 11466 goto ld_st;
252b5132 11467 case M_LWC3_AB:
df58fc94 11468 gas_assert (!mips_opts.micromips);
252b5132 11469 s = "lwc3";
df58fc94 11470 fmt = "E,o(b)";
bdaaa2e1 11471 /* Itbl support may require additional care here. */
252b5132 11472 coproc = 1;
df58fc94 11473 goto ld_st;
252b5132
RH
11474 case M_LWL_AB:
11475 s = "lwl";
df58fc94 11476 fmt = MEM12_FMT;
7f3c4072 11477 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11478 goto ld_st;
252b5132
RH
11479 case M_LWR_AB:
11480 s = "lwr";
df58fc94 11481 fmt = MEM12_FMT;
7f3c4072 11482 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11483 goto ld_st;
252b5132 11484 case M_LDC1_AB:
252b5132 11485 s = "ldc1";
df58fc94 11486 fmt = "T,o(b)";
bdaaa2e1 11487 /* Itbl support may require additional care here. */
252b5132 11488 coproc = 1;
df58fc94 11489 goto ld_st;
252b5132
RH
11490 case M_LDC2_AB:
11491 s = "ldc2";
df58fc94 11492 fmt = COP12_FMT;
7361da2c
AB
11493 offbits = (mips_opts.micromips ? 12
11494 : ISA_IS_R6 (mips_opts.isa) ? 11
11495 : 16);
bdaaa2e1 11496 /* Itbl support may require additional care here. */
252b5132 11497 coproc = 1;
df58fc94 11498 goto ld_st;
c77c0862 11499 case M_LQC2_AB:
c77c0862 11500 s = "lqc2";
14daeee3 11501 fmt = "+7,o(b)";
c77c0862
RS
11502 /* Itbl support may require additional care here. */
11503 coproc = 1;
11504 goto ld_st;
252b5132
RH
11505 case M_LDC3_AB:
11506 s = "ldc3";
df58fc94 11507 fmt = "E,o(b)";
bdaaa2e1 11508 /* Itbl support may require additional care here. */
252b5132 11509 coproc = 1;
df58fc94 11510 goto ld_st;
252b5132
RH
11511 case M_LDL_AB:
11512 s = "ldl";
df58fc94 11513 fmt = MEM12_FMT;
7f3c4072 11514 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11515 goto ld_st;
252b5132
RH
11516 case M_LDR_AB:
11517 s = "ldr";
df58fc94 11518 fmt = MEM12_FMT;
7f3c4072 11519 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11520 goto ld_st;
252b5132
RH
11521 case M_LL_AB:
11522 s = "ll";
7361da2c
AB
11523 fmt = LL_SC_FMT;
11524 offbits = (mips_opts.micromips ? 12
11525 : ISA_IS_R6 (mips_opts.isa) ? 9
11526 : 16);
252b5132
RH
11527 goto ld;
11528 case M_LLD_AB:
11529 s = "lld";
7361da2c
AB
11530 fmt = LL_SC_FMT;
11531 offbits = (mips_opts.micromips ? 12
11532 : ISA_IS_R6 (mips_opts.isa) ? 9
11533 : 16);
252b5132
RH
11534 goto ld;
11535 case M_LWU_AB:
11536 s = "lwu";
df58fc94 11537 fmt = MEM12_FMT;
7f3c4072 11538 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
11539 goto ld;
11540 case M_LWP_AB:
df58fc94
RS
11541 gas_assert (mips_opts.micromips);
11542 s = "lwp";
11543 fmt = "t,~(b)";
7f3c4072 11544 offbits = 12;
df58fc94
RS
11545 lp = 1;
11546 goto ld;
11547 case M_LDP_AB:
df58fc94
RS
11548 gas_assert (mips_opts.micromips);
11549 s = "ldp";
11550 fmt = "t,~(b)";
7f3c4072 11551 offbits = 12;
df58fc94
RS
11552 lp = 1;
11553 goto ld;
11554 case M_LWM_AB:
df58fc94
RS
11555 gas_assert (mips_opts.micromips);
11556 s = "lwm";
11557 fmt = "n,~(b)";
7f3c4072 11558 offbits = 12;
df58fc94
RS
11559 goto ld_st;
11560 case M_LDM_AB:
df58fc94
RS
11561 gas_assert (mips_opts.micromips);
11562 s = "ldm";
11563 fmt = "n,~(b)";
7f3c4072 11564 offbits = 12;
df58fc94
RS
11565 goto ld_st;
11566
252b5132 11567 ld:
f19ccbda 11568 /* We don't want to use $0 as tempreg. */
c0ebe874 11569 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
df58fc94 11570 goto ld_st;
252b5132 11571 else
c0ebe874 11572 tempreg = op[0] + lp;
df58fc94
RS
11573 goto ld_noat;
11574
252b5132
RH
11575 case M_SB_AB:
11576 s = "sb";
df58fc94
RS
11577 fmt = "t,o(b)";
11578 goto ld_st;
252b5132
RH
11579 case M_SH_AB:
11580 s = "sh";
df58fc94
RS
11581 fmt = "t,o(b)";
11582 goto ld_st;
252b5132
RH
11583 case M_SW_AB:
11584 s = "sw";
df58fc94
RS
11585 fmt = "t,o(b)";
11586 goto ld_st;
252b5132 11587 case M_SWC0_AB:
df58fc94 11588 gas_assert (!mips_opts.micromips);
252b5132 11589 s = "swc0";
df58fc94 11590 fmt = "E,o(b)";
bdaaa2e1 11591 /* Itbl support may require additional care here. */
252b5132 11592 coproc = 1;
df58fc94 11593 goto ld_st;
252b5132
RH
11594 case M_SWC1_AB:
11595 s = "swc1";
df58fc94 11596 fmt = "T,o(b)";
bdaaa2e1 11597 /* Itbl support may require additional care here. */
252b5132 11598 coproc = 1;
df58fc94 11599 goto ld_st;
252b5132
RH
11600 case M_SWC2_AB:
11601 s = "swc2";
df58fc94 11602 fmt = COP12_FMT;
7361da2c
AB
11603 offbits = (mips_opts.micromips ? 12
11604 : ISA_IS_R6 (mips_opts.isa) ? 11
11605 : 16);
bdaaa2e1 11606 /* Itbl support may require additional care here. */
252b5132 11607 coproc = 1;
df58fc94 11608 goto ld_st;
252b5132 11609 case M_SWC3_AB:
df58fc94 11610 gas_assert (!mips_opts.micromips);
252b5132 11611 s = "swc3";
df58fc94 11612 fmt = "E,o(b)";
bdaaa2e1 11613 /* Itbl support may require additional care here. */
252b5132 11614 coproc = 1;
df58fc94 11615 goto ld_st;
252b5132
RH
11616 case M_SWL_AB:
11617 s = "swl";
df58fc94 11618 fmt = MEM12_FMT;
7f3c4072 11619 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11620 goto ld_st;
252b5132
RH
11621 case M_SWR_AB:
11622 s = "swr";
df58fc94 11623 fmt = MEM12_FMT;
7f3c4072 11624 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11625 goto ld_st;
252b5132
RH
11626 case M_SC_AB:
11627 s = "sc";
7361da2c
AB
11628 fmt = LL_SC_FMT;
11629 offbits = (mips_opts.micromips ? 12
11630 : ISA_IS_R6 (mips_opts.isa) ? 9
11631 : 16);
df58fc94 11632 goto ld_st;
252b5132
RH
11633 case M_SCD_AB:
11634 s = "scd";
7361da2c
AB
11635 fmt = LL_SC_FMT;
11636 offbits = (mips_opts.micromips ? 12
11637 : ISA_IS_R6 (mips_opts.isa) ? 9
11638 : 16);
df58fc94 11639 goto ld_st;
d43b4baf
TS
11640 case M_CACHE_AB:
11641 s = "cache";
7361da2c
AB
11642 fmt = (mips_opts.micromips ? "k,~(b)"
11643 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11644 : "k,o(b)");
11645 offbits = (mips_opts.micromips ? 12
11646 : ISA_IS_R6 (mips_opts.isa) ? 9
11647 : 16);
7f3c4072
CM
11648 goto ld_st;
11649 case M_CACHEE_AB:
7f3c4072
CM
11650 s = "cachee";
11651 fmt = "k,+j(b)";
11652 offbits = 9;
df58fc94 11653 goto ld_st;
3eebd5eb
MR
11654 case M_PREF_AB:
11655 s = "pref";
7361da2c
AB
11656 fmt = (mips_opts.micromips ? "k,~(b)"
11657 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11658 : "k,o(b)");
11659 offbits = (mips_opts.micromips ? 12
11660 : ISA_IS_R6 (mips_opts.isa) ? 9
11661 : 16);
7f3c4072
CM
11662 goto ld_st;
11663 case M_PREFE_AB:
7f3c4072
CM
11664 s = "prefe";
11665 fmt = "k,+j(b)";
11666 offbits = 9;
df58fc94 11667 goto ld_st;
252b5132 11668 case M_SDC1_AB:
252b5132 11669 s = "sdc1";
df58fc94 11670 fmt = "T,o(b)";
252b5132 11671 coproc = 1;
bdaaa2e1 11672 /* Itbl support may require additional care here. */
df58fc94 11673 goto ld_st;
252b5132
RH
11674 case M_SDC2_AB:
11675 s = "sdc2";
df58fc94 11676 fmt = COP12_FMT;
7361da2c
AB
11677 offbits = (mips_opts.micromips ? 12
11678 : ISA_IS_R6 (mips_opts.isa) ? 11
11679 : 16);
c77c0862
RS
11680 /* Itbl support may require additional care here. */
11681 coproc = 1;
11682 goto ld_st;
11683 case M_SQC2_AB:
c77c0862 11684 s = "sqc2";
14daeee3 11685 fmt = "+7,o(b)";
bdaaa2e1 11686 /* Itbl support may require additional care here. */
252b5132 11687 coproc = 1;
df58fc94 11688 goto ld_st;
252b5132 11689 case M_SDC3_AB:
df58fc94 11690 gas_assert (!mips_opts.micromips);
252b5132 11691 s = "sdc3";
df58fc94 11692 fmt = "E,o(b)";
bdaaa2e1 11693 /* Itbl support may require additional care here. */
252b5132 11694 coproc = 1;
df58fc94 11695 goto ld_st;
252b5132
RH
11696 case M_SDL_AB:
11697 s = "sdl";
df58fc94 11698 fmt = MEM12_FMT;
7f3c4072 11699 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94 11700 goto ld_st;
252b5132
RH
11701 case M_SDR_AB:
11702 s = "sdr";
df58fc94 11703 fmt = MEM12_FMT;
7f3c4072 11704 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
11705 goto ld_st;
11706 case M_SWP_AB:
df58fc94
RS
11707 gas_assert (mips_opts.micromips);
11708 s = "swp";
11709 fmt = "t,~(b)";
7f3c4072 11710 offbits = 12;
df58fc94
RS
11711 goto ld_st;
11712 case M_SDP_AB:
df58fc94
RS
11713 gas_assert (mips_opts.micromips);
11714 s = "sdp";
11715 fmt = "t,~(b)";
7f3c4072 11716 offbits = 12;
df58fc94
RS
11717 goto ld_st;
11718 case M_SWM_AB:
df58fc94
RS
11719 gas_assert (mips_opts.micromips);
11720 s = "swm";
11721 fmt = "n,~(b)";
7f3c4072 11722 offbits = 12;
df58fc94
RS
11723 goto ld_st;
11724 case M_SDM_AB:
df58fc94
RS
11725 gas_assert (mips_opts.micromips);
11726 s = "sdm";
11727 fmt = "n,~(b)";
7f3c4072 11728 offbits = 12;
df58fc94
RS
11729
11730 ld_st:
8fc2e39e 11731 tempreg = AT;
df58fc94 11732 ld_noat:
c0ebe874 11733 breg = op[2];
f2ae14a1
RS
11734 if (small_offset_p (0, align, 16))
11735 {
11736 /* The first case exists for M_LD_AB and M_SD_AB, which are
11737 macros for o32 but which should act like normal instructions
11738 otherwise. */
11739 if (offbits == 16)
c0ebe874 11740 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
f2ae14a1
RS
11741 offset_reloc[1], offset_reloc[2], breg);
11742 else if (small_offset_p (0, align, offbits))
11743 {
11744 if (offbits == 0)
c0ebe874 11745 macro_build (NULL, s, fmt, op[0], breg);
f2ae14a1 11746 else
c0ebe874 11747 macro_build (NULL, s, fmt, op[0],
c8276761 11748 (int) offset_expr.X_add_number, breg);
f2ae14a1
RS
11749 }
11750 else
11751 {
11752 if (tempreg == AT)
11753 used_at = 1;
11754 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11755 tempreg, breg, -1, offset_reloc[0],
11756 offset_reloc[1], offset_reloc[2]);
11757 if (offbits == 0)
c0ebe874 11758 macro_build (NULL, s, fmt, op[0], tempreg);
f2ae14a1 11759 else
c0ebe874 11760 macro_build (NULL, s, fmt, op[0], 0, tempreg);
f2ae14a1
RS
11761 }
11762 break;
11763 }
11764
11765 if (tempreg == AT)
11766 used_at = 1;
11767
252b5132
RH
11768 if (offset_expr.X_op != O_constant
11769 && offset_expr.X_op != O_symbol)
11770 {
1661c76c 11771 as_bad (_("expression too complex"));
252b5132
RH
11772 offset_expr.X_op = O_constant;
11773 }
11774
2051e8c4
MR
11775 if (HAVE_32BIT_ADDRESSES
11776 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
11777 {
11778 char value [32];
11779
11780 sprintf_vma (value, offset_expr.X_add_number);
1661c76c 11781 as_bad (_("number (0x%s) larger than 32 bits"), value);
55e08f71 11782 }
2051e8c4 11783
252b5132
RH
11784 /* A constant expression in PIC code can be handled just as it
11785 is in non PIC code. */
aed1a261
RS
11786 if (offset_expr.X_op == O_constant)
11787 {
f2ae14a1
RS
11788 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11789 offbits == 0 ? 16 : offbits);
11790 offset_expr.X_add_number -= expr1.X_add_number;
df58fc94 11791
f2ae14a1
RS
11792 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11793 if (breg != 0)
11794 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11795 tempreg, tempreg, breg);
7f3c4072 11796 if (offbits == 0)
dd6a37e7 11797 {
f2ae14a1 11798 if (offset_expr.X_add_number != 0)
dd6a37e7 11799 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
f2ae14a1 11800 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
c0ebe874 11801 macro_build (NULL, s, fmt, op[0], tempreg);
dd6a37e7 11802 }
7f3c4072 11803 else if (offbits == 16)
c0ebe874 11804 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
df58fc94 11805 else
c0ebe874 11806 macro_build (NULL, s, fmt, op[0],
c8276761 11807 (int) offset_expr.X_add_number, tempreg);
df58fc94 11808 }
7f3c4072 11809 else if (offbits != 16)
df58fc94 11810 {
7f3c4072
CM
11811 /* The offset field is too narrow to be used for a low-part
11812 relocation, so load the whole address into the auxillary
f2ae14a1
RS
11813 register. */
11814 load_address (tempreg, &offset_expr, &used_at);
11815 if (breg != 0)
11816 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11817 tempreg, tempreg, breg);
7f3c4072 11818 if (offbits == 0)
c0ebe874 11819 macro_build (NULL, s, fmt, op[0], tempreg);
dd6a37e7 11820 else
c0ebe874 11821 macro_build (NULL, s, fmt, op[0], 0, tempreg);
aed1a261
RS
11822 }
11823 else if (mips_pic == NO_PIC)
252b5132
RH
11824 {
11825 /* If this is a reference to a GP relative symbol, and there
11826 is no base register, we want
c0ebe874 11827 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
252b5132
RH
11828 Otherwise, if there is no base register, we want
11829 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
c0ebe874 11830 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
252b5132
RH
11831 If we have a constant, we need two instructions anyhow,
11832 so we always use the latter form.
11833
11834 If we have a base register, and this is a reference to a
11835 GP relative symbol, we want
11836 addu $tempreg,$breg,$gp
c0ebe874 11837 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
252b5132
RH
11838 Otherwise we want
11839 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11840 addu $tempreg,$tempreg,$breg
c0ebe874 11841 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245 11842 With a constant we always use the latter case.
76b3015f 11843
d6bc6245
TS
11844 With 64bit address space and no base register and $at usable,
11845 we want
11846 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11847 lui $at,<sym> (BFD_RELOC_HI16_S)
11848 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11849 dsll32 $tempreg,0
11850 daddu $tempreg,$at
c0ebe874 11851 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11852 If we have a base register, we want
11853 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11854 lui $at,<sym> (BFD_RELOC_HI16_S)
11855 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11856 daddu $at,$breg
11857 dsll32 $tempreg,0
11858 daddu $tempreg,$at
c0ebe874 11859 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11860
11861 Without $at we can't generate the optimal path for superscalar
11862 processors here since this would require two temporary registers.
11863 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11864 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11865 dsll $tempreg,16
11866 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11867 dsll $tempreg,16
c0ebe874 11868 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
d6bc6245
TS
11869 If we have a base register, we want
11870 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11871 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11872 dsll $tempreg,16
11873 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11874 dsll $tempreg,16
11875 daddu $tempreg,$tempreg,$breg
c0ebe874 11876 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
6373ee54 11877
6caf9ef4 11878 For GP relative symbols in 64bit address space we can use
aed1a261
RS
11879 the same sequence as in 32bit address space. */
11880 if (HAVE_64BIT_SYMBOLS)
d6bc6245 11881 {
aed1a261 11882 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4
TS
11883 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11884 {
11885 relax_start (offset_expr.X_add_symbol);
11886 if (breg == 0)
11887 {
c0ebe874 11888 macro_build (&offset_expr, s, fmt, op[0],
6caf9ef4
TS
11889 BFD_RELOC_GPREL16, mips_gp_register);
11890 }
11891 else
11892 {
11893 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11894 tempreg, breg, mips_gp_register);
c0ebe874 11895 macro_build (&offset_expr, s, fmt, op[0],
6caf9ef4
TS
11896 BFD_RELOC_GPREL16, tempreg);
11897 }
11898 relax_switch ();
11899 }
d6bc6245 11900
741fe287 11901 if (used_at == 0 && mips_opts.at)
d6bc6245 11902 {
df58fc94 11903 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb 11904 BFD_RELOC_MIPS_HIGHEST);
df58fc94 11905 macro_build (&offset_expr, "lui", LUI_FMT, AT,
67c0d1eb
RS
11906 BFD_RELOC_HI16_S);
11907 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11908 tempreg, BFD_RELOC_MIPS_HIGHER);
d6bc6245 11909 if (breg != 0)
67c0d1eb 11910 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
df58fc94 11911 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
67c0d1eb 11912 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
c0ebe874 11913 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
67c0d1eb 11914 tempreg);
d6bc6245
TS
11915 used_at = 1;
11916 }
11917 else
11918 {
df58fc94 11919 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
67c0d1eb
RS
11920 BFD_RELOC_MIPS_HIGHEST);
11921 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11922 tempreg, BFD_RELOC_MIPS_HIGHER);
df58fc94 11923 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
67c0d1eb
RS
11924 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11925 tempreg, BFD_RELOC_HI16_S);
df58fc94 11926 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
d6bc6245 11927 if (breg != 0)
67c0d1eb 11928 macro_build (NULL, "daddu", "d,v,t",
17a2f251 11929 tempreg, tempreg, breg);
c0ebe874 11930 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11931 BFD_RELOC_LO16, tempreg);
d6bc6245 11932 }
6caf9ef4
TS
11933
11934 if (mips_relax.sequence)
11935 relax_end ();
8fc2e39e 11936 break;
d6bc6245 11937 }
256ab948 11938
252b5132
RH
11939 if (breg == 0)
11940 {
67c0d1eb 11941 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11942 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11943 {
4d7206a2 11944 relax_start (offset_expr.X_add_symbol);
c0ebe874 11945 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
67c0d1eb 11946 mips_gp_register);
4d7206a2 11947 relax_switch ();
252b5132 11948 }
67c0d1eb 11949 macro_build_lui (&offset_expr, tempreg);
c0ebe874 11950 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11951 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
11952 if (mips_relax.sequence)
11953 relax_end ();
252b5132
RH
11954 }
11955 else
11956 {
67c0d1eb 11957 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 11958 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 11959 {
4d7206a2 11960 relax_start (offset_expr.X_add_symbol);
67c0d1eb 11961 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11962 tempreg, breg, mips_gp_register);
c0ebe874 11963 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11964 BFD_RELOC_GPREL16, tempreg);
4d7206a2 11965 relax_switch ();
252b5132 11966 }
67c0d1eb
RS
11967 macro_build_lui (&offset_expr, tempreg);
11968 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 11969 tempreg, tempreg, breg);
c0ebe874 11970 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 11971 BFD_RELOC_LO16, tempreg);
4d7206a2
RS
11972 if (mips_relax.sequence)
11973 relax_end ();
252b5132
RH
11974 }
11975 }
0a44bf69 11976 else if (!mips_big_got)
252b5132 11977 {
ed6fb7bd 11978 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
f9419b05 11979
252b5132
RH
11980 /* If this is a reference to an external symbol, we want
11981 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11982 nop
c0ebe874 11983 <op> op[0],0($tempreg)
252b5132
RH
11984 Otherwise we want
11985 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11986 nop
11987 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
c0ebe874 11988 <op> op[0],0($tempreg)
f5040a92
AO
11989
11990 For NewABI, we want
11991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
c0ebe874 11992 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
f5040a92 11993
252b5132
RH
11994 If there is a base register, we add it to $tempreg before
11995 the <op>. If there is a constant, we stick it in the
11996 <op> instruction. We don't handle constants larger than
11997 16 bits, because we have no way to load the upper 16 bits
11998 (actually, we could handle them for the subset of cases
11999 in which we are not using $at). */
9c2799c2 12000 gas_assert (offset_expr.X_op == O_symbol);
f5040a92
AO
12001 if (HAVE_NEWABI)
12002 {
67c0d1eb
RS
12003 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12004 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 12005 if (breg != 0)
67c0d1eb 12006 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 12007 tempreg, tempreg, breg);
c0ebe874 12008 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 12009 BFD_RELOC_MIPS_GOT_OFST, tempreg);
f5040a92
AO
12010 break;
12011 }
252b5132
RH
12012 expr1.X_add_number = offset_expr.X_add_number;
12013 offset_expr.X_add_number = 0;
12014 if (expr1.X_add_number < -0x8000
12015 || expr1.X_add_number >= 0x8000)
12016 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb
RS
12017 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12018 lw_reloc_type, mips_gp_register);
269137b2 12019 load_delay_nop ();
4d7206a2
RS
12020 relax_start (offset_expr.X_add_symbol);
12021 relax_switch ();
67c0d1eb
RS
12022 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12023 tempreg, BFD_RELOC_LO16);
4d7206a2 12024 relax_end ();
252b5132 12025 if (breg != 0)
67c0d1eb 12026 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 12027 tempreg, tempreg, breg);
c0ebe874 12028 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
252b5132 12029 }
0a44bf69 12030 else if (mips_big_got && !HAVE_NEWABI)
252b5132 12031 {
67c0d1eb 12032 int gpdelay;
252b5132
RH
12033
12034 /* If this is a reference to an external symbol, we want
12035 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12036 addu $tempreg,$tempreg,$gp
12037 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
c0ebe874 12038 <op> op[0],0($tempreg)
252b5132
RH
12039 Otherwise we want
12040 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12041 nop
12042 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
c0ebe874 12043 <op> op[0],0($tempreg)
252b5132
RH
12044 If there is a base register, we add it to $tempreg before
12045 the <op>. If there is a constant, we stick it in the
12046 <op> instruction. We don't handle constants larger than
12047 16 bits, because we have no way to load the upper 16 bits
12048 (actually, we could handle them for the subset of cases
f5040a92 12049 in which we are not using $at). */
9c2799c2 12050 gas_assert (offset_expr.X_op == O_symbol);
252b5132
RH
12051 expr1.X_add_number = offset_expr.X_add_number;
12052 offset_expr.X_add_number = 0;
12053 if (expr1.X_add_number < -0x8000
12054 || expr1.X_add_number >= 0x8000)
12055 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 12056 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 12057 relax_start (offset_expr.X_add_symbol);
df58fc94 12058 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 12059 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
12060 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12061 mips_gp_register);
12062 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12063 BFD_RELOC_MIPS_GOT_LO16, tempreg);
4d7206a2 12064 relax_switch ();
67c0d1eb
RS
12065 if (gpdelay)
12066 macro_build (NULL, "nop", "");
12067 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12068 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 12069 load_delay_nop ();
67c0d1eb
RS
12070 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12071 tempreg, BFD_RELOC_LO16);
4d7206a2
RS
12072 relax_end ();
12073
252b5132 12074 if (breg != 0)
67c0d1eb 12075 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 12076 tempreg, tempreg, breg);
c0ebe874 12077 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
252b5132 12078 }
0a44bf69 12079 else if (mips_big_got && HAVE_NEWABI)
f5040a92 12080 {
f5040a92
AO
12081 /* If this is a reference to an external symbol, we want
12082 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12083 add $tempreg,$tempreg,$gp
12084 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
c0ebe874 12085 <op> op[0],<ofst>($tempreg)
f5040a92
AO
12086 Otherwise, for local symbols, we want:
12087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
c0ebe874 12088 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9c2799c2 12089 gas_assert (offset_expr.X_op == O_symbol);
4d7206a2 12090 expr1.X_add_number = offset_expr.X_add_number;
f5040a92
AO
12091 offset_expr.X_add_number = 0;
12092 if (expr1.X_add_number < -0x8000
12093 || expr1.X_add_number >= 0x8000)
12094 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4d7206a2 12095 relax_start (offset_expr.X_add_symbol);
df58fc94 12096 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
17a2f251 12097 BFD_RELOC_MIPS_GOT_HI16);
67c0d1eb
RS
12098 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12099 mips_gp_register);
12100 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12101 BFD_RELOC_MIPS_GOT_LO16, tempreg);
f5040a92 12102 if (breg != 0)
67c0d1eb 12103 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 12104 tempreg, tempreg, breg);
c0ebe874 12105 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
684022ea 12106
4d7206a2 12107 relax_switch ();
f5040a92 12108 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
12109 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12110 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
f5040a92 12111 if (breg != 0)
67c0d1eb 12112 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 12113 tempreg, tempreg, breg);
c0ebe874 12114 macro_build (&offset_expr, s, fmt, op[0],
17a2f251 12115 BFD_RELOC_MIPS_GOT_OFST, tempreg);
4d7206a2 12116 relax_end ();
f5040a92 12117 }
252b5132
RH
12118 else
12119 abort ();
12120
252b5132
RH
12121 break;
12122
833794fc
MR
12123 case M_JRADDIUSP:
12124 gas_assert (mips_opts.micromips);
12125 gas_assert (mips_opts.insn32);
12126 start_noreorder ();
12127 macro_build (NULL, "jr", "s", RA);
c0ebe874 12128 expr1.X_add_number = op[0] << 2;
833794fc
MR
12129 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12130 end_noreorder ();
12131 break;
12132
12133 case M_JRC:
12134 gas_assert (mips_opts.micromips);
12135 gas_assert (mips_opts.insn32);
c0ebe874 12136 macro_build (NULL, "jr", "s", op[0]);
833794fc
MR
12137 if (mips_opts.noreorder)
12138 macro_build (NULL, "nop", "");
12139 break;
12140
252b5132
RH
12141 case M_LI:
12142 case M_LI_S:
c0ebe874 12143 load_register (op[0], &imm_expr, 0);
8fc2e39e 12144 break;
252b5132
RH
12145
12146 case M_DLI:
c0ebe874 12147 load_register (op[0], &imm_expr, 1);
8fc2e39e 12148 break;
252b5132
RH
12149
12150 case M_LI_SS:
12151 if (imm_expr.X_op == O_constant)
12152 {
8fc2e39e 12153 used_at = 1;
67c0d1eb 12154 load_register (AT, &imm_expr, 0);
c0ebe874 12155 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
252b5132
RH
12156 break;
12157 }
12158 else
12159 {
b0e6f033
RS
12160 gas_assert (imm_expr.X_op == O_absent
12161 && offset_expr.X_op == O_symbol
90ecf173
MR
12162 && strcmp (segment_name (S_GET_SEGMENT
12163 (offset_expr.X_add_symbol)),
12164 ".lit4") == 0
12165 && offset_expr.X_add_number == 0);
c0ebe874 12166 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
17a2f251 12167 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8fc2e39e 12168 break;
252b5132
RH
12169 }
12170
12171 case M_LI_D:
ca4e0257
RS
12172 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12173 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12174 order 32 bits of the value and the low order 32 bits are either
12175 zero or in OFFSET_EXPR. */
b0e6f033 12176 if (imm_expr.X_op == O_constant)
252b5132 12177 {
bad1aba3 12178 if (GPR_SIZE == 64)
c0ebe874 12179 load_register (op[0], &imm_expr, 1);
252b5132
RH
12180 else
12181 {
12182 int hreg, lreg;
12183
12184 if (target_big_endian)
12185 {
c0ebe874
RS
12186 hreg = op[0];
12187 lreg = op[0] + 1;
252b5132
RH
12188 }
12189 else
12190 {
c0ebe874
RS
12191 hreg = op[0] + 1;
12192 lreg = op[0];
252b5132
RH
12193 }
12194
12195 if (hreg <= 31)
67c0d1eb 12196 load_register (hreg, &imm_expr, 0);
252b5132
RH
12197 if (lreg <= 31)
12198 {
12199 if (offset_expr.X_op == O_absent)
67c0d1eb 12200 move_register (lreg, 0);
252b5132
RH
12201 else
12202 {
9c2799c2 12203 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 12204 load_register (lreg, &offset_expr, 0);
252b5132
RH
12205 }
12206 }
12207 }
8fc2e39e 12208 break;
252b5132 12209 }
b0e6f033 12210 gas_assert (imm_expr.X_op == O_absent);
252b5132
RH
12211
12212 /* We know that sym is in the .rdata section. First we get the
12213 upper 16 bits of the address. */
12214 if (mips_pic == NO_PIC)
12215 {
67c0d1eb 12216 macro_build_lui (&offset_expr, AT);
8fc2e39e 12217 used_at = 1;
252b5132 12218 }
0a44bf69 12219 else
252b5132 12220 {
67c0d1eb
RS
12221 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12222 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8fc2e39e 12223 used_at = 1;
252b5132 12224 }
bdaaa2e1 12225
252b5132 12226 /* Now we load the register(s). */
bad1aba3 12227 if (GPR_SIZE == 64)
8fc2e39e
TS
12228 {
12229 used_at = 1;
c0ebe874
RS
12230 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12231 BFD_RELOC_LO16, AT);
8fc2e39e 12232 }
252b5132
RH
12233 else
12234 {
8fc2e39e 12235 used_at = 1;
c0ebe874
RS
12236 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12237 BFD_RELOC_LO16, AT);
12238 if (op[0] != RA)
252b5132
RH
12239 {
12240 /* FIXME: How in the world do we deal with the possible
12241 overflow here? */
12242 offset_expr.X_add_number += 4;
67c0d1eb 12243 macro_build (&offset_expr, "lw", "t,o(b)",
c0ebe874 12244 op[0] + 1, BFD_RELOC_LO16, AT);
252b5132
RH
12245 }
12246 }
252b5132
RH
12247 break;
12248
12249 case M_LI_DD:
ca4e0257
RS
12250 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12251 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12252 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12253 the value and the low order 32 bits are either zero or in
12254 OFFSET_EXPR. */
b0e6f033 12255 if (imm_expr.X_op == O_constant)
252b5132 12256 {
8fc2e39e 12257 used_at = 1;
bad1aba3 12258 load_register (AT, &imm_expr, FPR_SIZE == 64);
351cdf24
MF
12259 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12260 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
252b5132
RH
12261 else
12262 {
351cdf24
MF
12263 if (ISA_HAS_MXHC1 (mips_opts.isa))
12264 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12265 else if (FPR_SIZE != 32)
12266 as_bad (_("Unable to generate `%s' compliant code "
12267 "without mthc1"),
12268 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12269 else
12270 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
252b5132 12271 if (offset_expr.X_op == O_absent)
c0ebe874 12272 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
252b5132
RH
12273 else
12274 {
9c2799c2 12275 gas_assert (offset_expr.X_op == O_constant);
67c0d1eb 12276 load_register (AT, &offset_expr, 0);
c0ebe874 12277 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
252b5132
RH
12278 }
12279 }
12280 break;
12281 }
12282
b0e6f033
RS
12283 gas_assert (imm_expr.X_op == O_absent
12284 && offset_expr.X_op == O_symbol
90ecf173 12285 && offset_expr.X_add_number == 0);
252b5132
RH
12286 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12287 if (strcmp (s, ".lit8") == 0)
134c0c8b
MR
12288 {
12289 op[2] = mips_gp_register;
f2ae14a1
RS
12290 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12291 offset_reloc[1] = BFD_RELOC_UNUSED;
12292 offset_reloc[2] = BFD_RELOC_UNUSED;
252b5132
RH
12293 }
12294 else
12295 {
9c2799c2 12296 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8fc2e39e 12297 used_at = 1;
0a44bf69 12298 if (mips_pic != NO_PIC)
67c0d1eb
RS
12299 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12300 BFD_RELOC_MIPS_GOT16, mips_gp_register);
252b5132
RH
12301 else
12302 {
12303 /* FIXME: This won't work for a 64 bit address. */
67c0d1eb 12304 macro_build_lui (&offset_expr, AT);
252b5132 12305 }
bdaaa2e1 12306
c0ebe874 12307 op[2] = AT;
f2ae14a1
RS
12308 offset_reloc[0] = BFD_RELOC_LO16;
12309 offset_reloc[1] = BFD_RELOC_UNUSED;
12310 offset_reloc[2] = BFD_RELOC_UNUSED;
134c0c8b 12311 }
f2ae14a1
RS
12312 align = 8;
12313 /* Fall through */
c4a68bea 12314
252b5132
RH
12315 case M_L_DAB:
12316 /*
12317 * The MIPS assembler seems to check for X_add_number not
12318 * being double aligned and generating:
12319 * lui at,%hi(foo+1)
12320 * addu at,at,v1
12321 * addiu at,at,%lo(foo+1)
12322 * lwc1 f2,0(at)
12323 * lwc1 f3,4(at)
12324 * But, the resulting address is the same after relocation so why
12325 * generate the extra instruction?
12326 */
bdaaa2e1 12327 /* Itbl support may require additional care here. */
252b5132 12328 coproc = 1;
df58fc94 12329 fmt = "T,o(b)";
0aa27725 12330 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
12331 {
12332 s = "ldc1";
df58fc94 12333 goto ld_st;
252b5132 12334 }
252b5132 12335 s = "lwc1";
252b5132
RH
12336 goto ldd_std;
12337
12338 case M_S_DAB:
df58fc94
RS
12339 gas_assert (!mips_opts.micromips);
12340 /* Itbl support may require additional care here. */
12341 coproc = 1;
12342 fmt = "T,o(b)";
0aa27725 12343 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
252b5132
RH
12344 {
12345 s = "sdc1";
df58fc94 12346 goto ld_st;
252b5132 12347 }
252b5132 12348 s = "swc1";
252b5132
RH
12349 goto ldd_std;
12350
e407c74b
NC
12351 case M_LQ_AB:
12352 fmt = "t,o(b)";
12353 s = "lq";
12354 goto ld;
12355
12356 case M_SQ_AB:
12357 fmt = "t,o(b)";
12358 s = "sq";
12359 goto ld_st;
12360
252b5132 12361 case M_LD_AB:
df58fc94 12362 fmt = "t,o(b)";
bad1aba3 12363 if (GPR_SIZE == 64)
252b5132
RH
12364 {
12365 s = "ld";
12366 goto ld;
12367 }
252b5132 12368 s = "lw";
252b5132
RH
12369 goto ldd_std;
12370
12371 case M_SD_AB:
df58fc94 12372 fmt = "t,o(b)";
bad1aba3 12373 if (GPR_SIZE == 64)
252b5132
RH
12374 {
12375 s = "sd";
df58fc94 12376 goto ld_st;
252b5132 12377 }
252b5132 12378 s = "sw";
252b5132
RH
12379
12380 ldd_std:
f2ae14a1
RS
12381 /* Even on a big endian machine $fn comes before $fn+1. We have
12382 to adjust when loading from memory. We set coproc if we must
12383 load $fn+1 first. */
12384 /* Itbl support may require additional care here. */
12385 if (!target_big_endian)
12386 coproc = 0;
12387
c0ebe874 12388 breg = op[2];
f2ae14a1
RS
12389 if (small_offset_p (0, align, 16))
12390 {
12391 ep = &offset_expr;
12392 if (!small_offset_p (4, align, 16))
12393 {
12394 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12395 -1, offset_reloc[0], offset_reloc[1],
12396 offset_reloc[2]);
12397 expr1.X_add_number = 0;
12398 ep = &expr1;
12399 breg = AT;
12400 used_at = 1;
12401 offset_reloc[0] = BFD_RELOC_LO16;
12402 offset_reloc[1] = BFD_RELOC_UNUSED;
12403 offset_reloc[2] = BFD_RELOC_UNUSED;
12404 }
c0ebe874 12405 if (strcmp (s, "lw") == 0 && op[0] == breg)
f2ae14a1
RS
12406 {
12407 ep->X_add_number += 4;
c0ebe874 12408 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
f2ae14a1
RS
12409 offset_reloc[1], offset_reloc[2], breg);
12410 ep->X_add_number -= 4;
c0ebe874 12411 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
f2ae14a1
RS
12412 offset_reloc[1], offset_reloc[2], breg);
12413 }
12414 else
12415 {
c0ebe874 12416 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
f2ae14a1
RS
12417 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12418 breg);
12419 ep->X_add_number += 4;
c0ebe874 12420 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
f2ae14a1
RS
12421 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12422 breg);
12423 }
12424 break;
12425 }
12426
252b5132
RH
12427 if (offset_expr.X_op != O_symbol
12428 && offset_expr.X_op != O_constant)
12429 {
1661c76c 12430 as_bad (_("expression too complex"));
252b5132
RH
12431 offset_expr.X_op = O_constant;
12432 }
12433
2051e8c4
MR
12434 if (HAVE_32BIT_ADDRESSES
12435 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
55e08f71
NC
12436 {
12437 char value [32];
12438
12439 sprintf_vma (value, offset_expr.X_add_number);
1661c76c 12440 as_bad (_("number (0x%s) larger than 32 bits"), value);
55e08f71 12441 }
2051e8c4 12442
90ecf173 12443 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
252b5132
RH
12444 {
12445 /* If this is a reference to a GP relative symbol, we want
c0ebe874
RS
12446 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12447 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
252b5132
RH
12448 If we have a base register, we use this
12449 addu $at,$breg,$gp
c0ebe874
RS
12450 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12451 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
252b5132
RH
12452 If this is not a GP relative symbol, we want
12453 lui $at,<sym> (BFD_RELOC_HI16_S)
c0ebe874
RS
12454 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12455 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
12456 If there is a base register, we add it to $at after the
12457 lui instruction. If there is a constant, we always use
12458 the last case. */
39a59cf8
MR
12459 if (offset_expr.X_op == O_symbol
12460 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6caf9ef4 12461 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
252b5132 12462 {
4d7206a2 12463 relax_start (offset_expr.X_add_symbol);
252b5132
RH
12464 if (breg == 0)
12465 {
c9914766 12466 tempreg = mips_gp_register;
252b5132
RH
12467 }
12468 else
12469 {
67c0d1eb 12470 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 12471 AT, breg, mips_gp_register);
252b5132 12472 tempreg = AT;
252b5132
RH
12473 used_at = 1;
12474 }
12475
beae10d5 12476 /* Itbl support may require additional care here. */
c0ebe874 12477 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 12478 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
12479 offset_expr.X_add_number += 4;
12480
12481 /* Set mips_optimize to 2 to avoid inserting an
12482 undesired nop. */
12483 hold_mips_optimize = mips_optimize;
12484 mips_optimize = 2;
beae10d5 12485 /* Itbl support may require additional care here. */
c0ebe874 12486 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 12487 BFD_RELOC_GPREL16, tempreg);
252b5132
RH
12488 mips_optimize = hold_mips_optimize;
12489
4d7206a2 12490 relax_switch ();
252b5132 12491
0970e49e 12492 offset_expr.X_add_number -= 4;
252b5132 12493 }
8fc2e39e 12494 used_at = 1;
f2ae14a1
RS
12495 if (offset_high_part (offset_expr.X_add_number, 16)
12496 != offset_high_part (offset_expr.X_add_number + 4, 16))
12497 {
12498 load_address (AT, &offset_expr, &used_at);
12499 offset_expr.X_op = O_constant;
12500 offset_expr.X_add_number = 0;
12501 }
12502 else
12503 macro_build_lui (&offset_expr, AT);
252b5132 12504 if (breg != 0)
67c0d1eb 12505 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 12506 /* Itbl support may require additional care here. */
c0ebe874 12507 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 12508 BFD_RELOC_LO16, AT);
252b5132
RH
12509 /* FIXME: How do we handle overflow here? */
12510 offset_expr.X_add_number += 4;
beae10d5 12511 /* Itbl support may require additional care here. */
c0ebe874 12512 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 12513 BFD_RELOC_LO16, AT);
4d7206a2
RS
12514 if (mips_relax.sequence)
12515 relax_end ();
bdaaa2e1 12516 }
0a44bf69 12517 else if (!mips_big_got)
252b5132 12518 {
252b5132
RH
12519 /* If this is a reference to an external symbol, we want
12520 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12521 nop
c0ebe874
RS
12522 <op> op[0],0($at)
12523 <op> op[0]+1,4($at)
252b5132
RH
12524 Otherwise we want
12525 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12526 nop
c0ebe874
RS
12527 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12528 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
12529 If there is a base register we add it to $at before the
12530 lwc1 instructions. If there is a constant we include it
12531 in the lwc1 instructions. */
12532 used_at = 1;
12533 expr1.X_add_number = offset_expr.X_add_number;
252b5132
RH
12534 if (expr1.X_add_number < -0x8000
12535 || expr1.X_add_number >= 0x8000 - 4)
12536 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 12537 load_got_offset (AT, &offset_expr);
269137b2 12538 load_delay_nop ();
252b5132 12539 if (breg != 0)
67c0d1eb 12540 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
252b5132
RH
12541
12542 /* Set mips_optimize to 2 to avoid inserting an undesired
12543 nop. */
12544 hold_mips_optimize = mips_optimize;
12545 mips_optimize = 2;
4d7206a2 12546
beae10d5 12547 /* Itbl support may require additional care here. */
4d7206a2 12548 relax_start (offset_expr.X_add_symbol);
c0ebe874 12549 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 12550 BFD_RELOC_LO16, AT);
4d7206a2 12551 expr1.X_add_number += 4;
c0ebe874 12552 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 12553 BFD_RELOC_LO16, AT);
4d7206a2 12554 relax_switch ();
c0ebe874 12555 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 12556 BFD_RELOC_LO16, AT);
4d7206a2 12557 offset_expr.X_add_number += 4;
c0ebe874 12558 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 12559 BFD_RELOC_LO16, AT);
4d7206a2 12560 relax_end ();
252b5132 12561
4d7206a2 12562 mips_optimize = hold_mips_optimize;
252b5132 12563 }
0a44bf69 12564 else if (mips_big_got)
252b5132 12565 {
67c0d1eb 12566 int gpdelay;
252b5132
RH
12567
12568 /* If this is a reference to an external symbol, we want
12569 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12570 addu $at,$at,$gp
12571 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12572 nop
c0ebe874
RS
12573 <op> op[0],0($at)
12574 <op> op[0]+1,4($at)
252b5132
RH
12575 Otherwise we want
12576 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12577 nop
c0ebe874
RS
12578 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12579 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
252b5132
RH
12580 If there is a base register we add it to $at before the
12581 lwc1 instructions. If there is a constant we include it
12582 in the lwc1 instructions. */
12583 used_at = 1;
12584 expr1.X_add_number = offset_expr.X_add_number;
12585 offset_expr.X_add_number = 0;
12586 if (expr1.X_add_number < -0x8000
12587 || expr1.X_add_number >= 0x8000 - 4)
12588 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
67c0d1eb 12589 gpdelay = reg_needs_delay (mips_gp_register);
4d7206a2 12590 relax_start (offset_expr.X_add_symbol);
df58fc94 12591 macro_build (&offset_expr, "lui", LUI_FMT,
67c0d1eb
RS
12592 AT, BFD_RELOC_MIPS_GOT_HI16);
12593 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
17a2f251 12594 AT, AT, mips_gp_register);
67c0d1eb 12595 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
17a2f251 12596 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
269137b2 12597 load_delay_nop ();
252b5132 12598 if (breg != 0)
67c0d1eb 12599 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 12600 /* Itbl support may require additional care here. */
c0ebe874 12601 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
17a2f251 12602 BFD_RELOC_LO16, AT);
252b5132
RH
12603 expr1.X_add_number += 4;
12604
12605 /* Set mips_optimize to 2 to avoid inserting an undesired
12606 nop. */
12607 hold_mips_optimize = mips_optimize;
12608 mips_optimize = 2;
beae10d5 12609 /* Itbl support may require additional care here. */
c0ebe874 12610 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
17a2f251 12611 BFD_RELOC_LO16, AT);
252b5132
RH
12612 mips_optimize = hold_mips_optimize;
12613 expr1.X_add_number -= 4;
12614
4d7206a2
RS
12615 relax_switch ();
12616 offset_expr.X_add_number = expr1.X_add_number;
67c0d1eb
RS
12617 if (gpdelay)
12618 macro_build (NULL, "nop", "");
12619 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12620 BFD_RELOC_MIPS_GOT16, mips_gp_register);
269137b2 12621 load_delay_nop ();
252b5132 12622 if (breg != 0)
67c0d1eb 12623 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
beae10d5 12624 /* Itbl support may require additional care here. */
c0ebe874 12625 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
67c0d1eb 12626 BFD_RELOC_LO16, AT);
4d7206a2 12627 offset_expr.X_add_number += 4;
252b5132
RH
12628
12629 /* Set mips_optimize to 2 to avoid inserting an undesired
12630 nop. */
12631 hold_mips_optimize = mips_optimize;
12632 mips_optimize = 2;
beae10d5 12633 /* Itbl support may require additional care here. */
c0ebe874 12634 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
67c0d1eb 12635 BFD_RELOC_LO16, AT);
252b5132 12636 mips_optimize = hold_mips_optimize;
4d7206a2 12637 relax_end ();
252b5132 12638 }
252b5132
RH
12639 else
12640 abort ();
12641
252b5132 12642 break;
3739860c 12643
dd6a37e7 12644 case M_SAA_AB:
dd6a37e7 12645 s = "saa";
0db377d0 12646 goto saa_saad;
dd6a37e7 12647 case M_SAAD_AB:
dd6a37e7 12648 s = "saad";
0db377d0
MR
12649 saa_saad:
12650 gas_assert (!mips_opts.micromips);
7f3c4072 12651 offbits = 0;
dd6a37e7
AP
12652 fmt = "t,(b)";
12653 goto ld_st;
12654
252b5132
RH
12655 /* New code added to support COPZ instructions.
12656 This code builds table entries out of the macros in mip_opcodes.
12657 R4000 uses interlocks to handle coproc delays.
12658 Other chips (like the R3000) require nops to be inserted for delays.
12659
f72c8c98 12660 FIXME: Currently, we require that the user handle delays.
252b5132
RH
12661 In order to fill delay slots for non-interlocked chips,
12662 we must have a way to specify delays based on the coprocessor.
12663 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12664 What are the side-effects of the cop instruction?
12665 What cache support might we have and what are its effects?
12666 Both coprocessor & memory require delays. how long???
bdaaa2e1 12667 What registers are read/set/modified?
252b5132
RH
12668
12669 If an itbl is provided to interpret cop instructions,
bdaaa2e1 12670 this knowledge can be encoded in the itbl spec. */
252b5132
RH
12671
12672 case M_COP0:
12673 s = "c0";
12674 goto copz;
12675 case M_COP1:
12676 s = "c1";
12677 goto copz;
12678 case M_COP2:
12679 s = "c2";
12680 goto copz;
12681 case M_COP3:
12682 s = "c3";
12683 copz:
df58fc94 12684 gas_assert (!mips_opts.micromips);
252b5132
RH
12685 /* For now we just do C (same as Cz). The parameter will be
12686 stored in insn_opcode by mips_ip. */
c8276761 12687 macro_build (NULL, s, "C", (int) ip->insn_opcode);
8fc2e39e 12688 break;
252b5132 12689
ea1fb5dc 12690 case M_MOVE:
c0ebe874 12691 move_register (op[0], op[1]);
8fc2e39e 12692 break;
ea1fb5dc 12693
833794fc
MR
12694 case M_MOVEP:
12695 gas_assert (mips_opts.micromips);
12696 gas_assert (mips_opts.insn32);
c0ebe874
RS
12697 move_register (micromips_to_32_reg_h_map1[op[0]],
12698 micromips_to_32_reg_m_map[op[1]]);
12699 move_register (micromips_to_32_reg_h_map2[op[0]],
12700 micromips_to_32_reg_n_map[op[2]]);
833794fc
MR
12701 break;
12702
252b5132
RH
12703 case M_DMUL:
12704 dbl = 1;
1a0670f3 12705 /* Fall through. */
252b5132 12706 case M_MUL:
e407c74b 12707 if (mips_opts.arch == CPU_R5900)
c0ebe874
RS
12708 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12709 op[2]);
e407c74b
NC
12710 else
12711 {
c0ebe874
RS
12712 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12713 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
e407c74b 12714 }
8fc2e39e 12715 break;
252b5132
RH
12716
12717 case M_DMUL_I:
12718 dbl = 1;
1a0670f3 12719 /* Fall through. */
252b5132
RH
12720 case M_MUL_I:
12721 /* The MIPS assembler some times generates shifts and adds. I'm
12722 not trying to be that fancy. GCC should do this for us
12723 anyway. */
8fc2e39e 12724 used_at = 1;
67c0d1eb 12725 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
12726 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12727 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132
RH
12728 break;
12729
12730 case M_DMULO_I:
12731 dbl = 1;
1a0670f3 12732 /* Fall through. */
252b5132
RH
12733 case M_MULO_I:
12734 imm = 1;
12735 goto do_mulo;
12736
12737 case M_DMULO:
12738 dbl = 1;
1a0670f3 12739 /* Fall through. */
252b5132
RH
12740 case M_MULO:
12741 do_mulo:
7d10b47d 12742 start_noreorder ();
8fc2e39e 12743 used_at = 1;
252b5132 12744 if (imm)
67c0d1eb 12745 load_register (AT, &imm_expr, dbl);
c0ebe874
RS
12746 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12747 op[1], imm ? AT : op[2]);
12748 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12749 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
df58fc94 12750 macro_build (NULL, "mfhi", MFHL_FMT, AT);
252b5132 12751 if (mips_trap)
c0ebe874 12752 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
252b5132
RH
12753 else
12754 {
df58fc94
RS
12755 if (mips_opts.micromips)
12756 micromips_label_expr (&label_expr);
12757 else
12758 label_expr.X_add_number = 8;
c0ebe874 12759 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
a605d2b3 12760 macro_build (NULL, "nop", "");
df58fc94
RS
12761 macro_build (NULL, "break", BRK_FMT, 6);
12762 if (mips_opts.micromips)
12763 micromips_add_label ();
252b5132 12764 }
7d10b47d 12765 end_noreorder ();
c0ebe874 12766 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132
RH
12767 break;
12768
12769 case M_DMULOU_I:
12770 dbl = 1;
1a0670f3 12771 /* Fall through. */
252b5132
RH
12772 case M_MULOU_I:
12773 imm = 1;
12774 goto do_mulou;
12775
12776 case M_DMULOU:
12777 dbl = 1;
1a0670f3 12778 /* Fall through. */
252b5132
RH
12779 case M_MULOU:
12780 do_mulou:
7d10b47d 12781 start_noreorder ();
8fc2e39e 12782 used_at = 1;
252b5132 12783 if (imm)
67c0d1eb
RS
12784 load_register (AT, &imm_expr, dbl);
12785 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
c0ebe874 12786 op[1], imm ? AT : op[2]);
df58fc94 12787 macro_build (NULL, "mfhi", MFHL_FMT, AT);
c0ebe874 12788 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
252b5132 12789 if (mips_trap)
df58fc94 12790 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
252b5132
RH
12791 else
12792 {
df58fc94
RS
12793 if (mips_opts.micromips)
12794 micromips_label_expr (&label_expr);
12795 else
12796 label_expr.X_add_number = 8;
12797 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
a605d2b3 12798 macro_build (NULL, "nop", "");
df58fc94
RS
12799 macro_build (NULL, "break", BRK_FMT, 6);
12800 if (mips_opts.micromips)
12801 micromips_add_label ();
252b5132 12802 }
7d10b47d 12803 end_noreorder ();
252b5132
RH
12804 break;
12805
771c7ce4 12806 case M_DROL:
fef14a42 12807 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 12808 {
c0ebe874 12809 if (op[0] == op[1])
82dd0097
CD
12810 {
12811 tempreg = AT;
12812 used_at = 1;
12813 }
12814 else
c0ebe874
RS
12815 tempreg = op[0];
12816 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12817 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
8fc2e39e 12818 break;
82dd0097 12819 }
8fc2e39e 12820 used_at = 1;
c0ebe874
RS
12821 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12822 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12823 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12824 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12825 break;
12826
252b5132 12827 case M_ROL:
fef14a42 12828 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12829 {
c0ebe874 12830 if (op[0] == op[1])
82dd0097
CD
12831 {
12832 tempreg = AT;
12833 used_at = 1;
12834 }
12835 else
c0ebe874
RS
12836 tempreg = op[0];
12837 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12838 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
8fc2e39e 12839 break;
82dd0097 12840 }
8fc2e39e 12841 used_at = 1;
c0ebe874
RS
12842 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12843 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12844 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12845 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12846 break;
12847
771c7ce4
TS
12848 case M_DROL_I:
12849 {
12850 unsigned int rot;
e0471c16
TS
12851 const char *l;
12852 const char *rr;
771c7ce4 12853
771c7ce4 12854 rot = imm_expr.X_add_number & 0x3f;
fef14a42 12855 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
60b63b72
RS
12856 {
12857 rot = (64 - rot) & 0x3f;
12858 if (rot >= 32)
c0ebe874 12859 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
60b63b72 12860 else
c0ebe874 12861 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12862 break;
60b63b72 12863 }
483fc7cd 12864 if (rot == 0)
483fc7cd 12865 {
c0ebe874 12866 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12867 break;
483fc7cd 12868 }
82dd0097 12869 l = (rot < 0x20) ? "dsll" : "dsll32";
91d6fa6a 12870 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
82dd0097 12871 rot &= 0x1f;
8fc2e39e 12872 used_at = 1;
c0ebe874
RS
12873 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12874 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12875 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12876 }
12877 break;
12878
252b5132 12879 case M_ROL_I:
771c7ce4
TS
12880 {
12881 unsigned int rot;
12882
771c7ce4 12883 rot = imm_expr.X_add_number & 0x1f;
fef14a42 12884 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
60b63b72 12885 {
c0ebe874
RS
12886 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12887 (32 - rot) & 0x1f);
8fc2e39e 12888 break;
60b63b72 12889 }
483fc7cd 12890 if (rot == 0)
483fc7cd 12891 {
c0ebe874 12892 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12893 break;
483fc7cd 12894 }
8fc2e39e 12895 used_at = 1;
c0ebe874
RS
12896 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12897 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12898 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12899 }
12900 break;
12901
12902 case M_DROR:
fef14a42 12903 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097 12904 {
c0ebe874 12905 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
8fc2e39e 12906 break;
82dd0097 12907 }
8fc2e39e 12908 used_at = 1;
c0ebe874
RS
12909 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12910 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12911 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12912 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12913 break;
12914
12915 case M_ROR:
fef14a42 12916 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12917 {
c0ebe874 12918 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
8fc2e39e 12919 break;
82dd0097 12920 }
8fc2e39e 12921 used_at = 1;
c0ebe874
RS
12922 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12923 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12924 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12925 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
252b5132
RH
12926 break;
12927
771c7ce4
TS
12928 case M_DROR_I:
12929 {
12930 unsigned int rot;
e0471c16
TS
12931 const char *l;
12932 const char *rr;
771c7ce4 12933
771c7ce4 12934 rot = imm_expr.X_add_number & 0x3f;
fef14a42 12935 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
82dd0097
CD
12936 {
12937 if (rot >= 32)
c0ebe874 12938 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
82dd0097 12939 else
c0ebe874 12940 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12941 break;
82dd0097 12942 }
483fc7cd 12943 if (rot == 0)
483fc7cd 12944 {
c0ebe874 12945 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12946 break;
483fc7cd 12947 }
91d6fa6a 12948 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
82dd0097
CD
12949 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12950 rot &= 0x1f;
8fc2e39e 12951 used_at = 1;
c0ebe874
RS
12952 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12953 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12954 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4
TS
12955 }
12956 break;
12957
252b5132 12958 case M_ROR_I:
771c7ce4
TS
12959 {
12960 unsigned int rot;
12961
771c7ce4 12962 rot = imm_expr.X_add_number & 0x1f;
fef14a42 12963 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
82dd0097 12964 {
c0ebe874 12965 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
8fc2e39e 12966 break;
82dd0097 12967 }
483fc7cd 12968 if (rot == 0)
483fc7cd 12969 {
c0ebe874 12970 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
8fc2e39e 12971 break;
483fc7cd 12972 }
8fc2e39e 12973 used_at = 1;
c0ebe874
RS
12974 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12975 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12976 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
771c7ce4 12977 }
252b5132
RH
12978 break;
12979
252b5132 12980 case M_SEQ:
c0ebe874
RS
12981 if (op[1] == 0)
12982 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12983 else if (op[2] == 0)
12984 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
12985 else
12986 {
c0ebe874
RS
12987 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12988 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
252b5132 12989 }
8fc2e39e 12990 break;
252b5132
RH
12991
12992 case M_SEQ_I:
b0e6f033 12993 if (imm_expr.X_add_number == 0)
252b5132 12994 {
c0ebe874 12995 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 12996 break;
252b5132 12997 }
c0ebe874 12998 if (op[1] == 0)
252b5132 12999 {
1661c76c 13000 as_warn (_("instruction %s: result is always false"),
252b5132 13001 ip->insn_mo->name);
c0ebe874 13002 move_register (op[0], 0);
8fc2e39e 13003 break;
252b5132 13004 }
dd3cbb7e
NC
13005 if (CPU_HAS_SEQ (mips_opts.arch)
13006 && -512 <= imm_expr.X_add_number
13007 && imm_expr.X_add_number < 512)
13008 {
c0ebe874 13009 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
750bdd57 13010 (int) imm_expr.X_add_number);
dd3cbb7e
NC
13011 break;
13012 }
b0e6f033 13013 if (imm_expr.X_add_number >= 0
252b5132 13014 && imm_expr.X_add_number < 0x10000)
c0ebe874 13015 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
b0e6f033 13016 else if (imm_expr.X_add_number > -0x8000
252b5132
RH
13017 && imm_expr.X_add_number < 0)
13018 {
13019 imm_expr.X_add_number = -imm_expr.X_add_number;
bad1aba3 13020 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
c0ebe874 13021 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132 13022 }
dd3cbb7e
NC
13023 else if (CPU_HAS_SEQ (mips_opts.arch))
13024 {
13025 used_at = 1;
bad1aba3 13026 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13027 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
dd3cbb7e
NC
13028 break;
13029 }
252b5132
RH
13030 else
13031 {
bad1aba3 13032 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13033 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
252b5132
RH
13034 used_at = 1;
13035 }
c0ebe874 13036 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 13037 break;
252b5132 13038
c0ebe874 13039 case M_SGE: /* X >= Y <==> not (X < Y) */
252b5132
RH
13040 s = "slt";
13041 goto sge;
13042 case M_SGEU:
13043 s = "sltu";
13044 sge:
c0ebe874
RS
13045 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
13046 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 13047 break;
252b5132 13048
c0ebe874 13049 case M_SGE_I: /* X >= I <==> not (X < I) */
252b5132 13050 case M_SGEU_I:
b0e6f033 13051 if (imm_expr.X_add_number >= -0x8000
252b5132 13052 && imm_expr.X_add_number < 0x8000)
c0ebe874
RS
13053 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
13054 op[0], op[1], BFD_RELOC_LO16);
252b5132
RH
13055 else
13056 {
bad1aba3 13057 load_register (AT, &imm_expr, GPR_SIZE == 64);
67c0d1eb 13058 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
c0ebe874 13059 op[0], op[1], AT);
252b5132
RH
13060 used_at = 1;
13061 }
c0ebe874 13062 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 13063 break;
252b5132 13064
c0ebe874 13065 case M_SGT: /* X > Y <==> Y < X */
252b5132
RH
13066 s = "slt";
13067 goto sgt;
13068 case M_SGTU:
13069 s = "sltu";
13070 sgt:
c0ebe874 13071 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
8fc2e39e 13072 break;
252b5132 13073
c0ebe874 13074 case M_SGT_I: /* X > I <==> I < X */
252b5132
RH
13075 s = "slt";
13076 goto sgti;
13077 case M_SGTU_I:
13078 s = "sltu";
13079 sgti:
8fc2e39e 13080 used_at = 1;
bad1aba3 13081 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13082 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
252b5132
RH
13083 break;
13084
c0ebe874 13085 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
252b5132
RH
13086 s = "slt";
13087 goto sle;
13088 case M_SLEU:
13089 s = "sltu";
13090 sle:
c0ebe874
RS
13091 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13092 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
8fc2e39e 13093 break;
252b5132 13094
c0ebe874 13095 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
252b5132
RH
13096 s = "slt";
13097 goto slei;
13098 case M_SLEU_I:
13099 s = "sltu";
13100 slei:
8fc2e39e 13101 used_at = 1;
bad1aba3 13102 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874
RS
13103 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13104 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
252b5132
RH
13105 break;
13106
13107 case M_SLT_I:
b0e6f033 13108 if (imm_expr.X_add_number >= -0x8000
252b5132
RH
13109 && imm_expr.X_add_number < 0x8000)
13110 {
c0ebe874
RS
13111 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
13112 BFD_RELOC_LO16);
8fc2e39e 13113 break;
252b5132 13114 }
8fc2e39e 13115 used_at = 1;
bad1aba3 13116 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13117 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
252b5132
RH
13118 break;
13119
13120 case M_SLTU_I:
b0e6f033 13121 if (imm_expr.X_add_number >= -0x8000
252b5132
RH
13122 && imm_expr.X_add_number < 0x8000)
13123 {
c0ebe874 13124 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
17a2f251 13125 BFD_RELOC_LO16);
8fc2e39e 13126 break;
252b5132 13127 }
8fc2e39e 13128 used_at = 1;
bad1aba3 13129 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13130 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
252b5132
RH
13131 break;
13132
13133 case M_SNE:
c0ebe874
RS
13134 if (op[1] == 0)
13135 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13136 else if (op[2] == 0)
13137 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
252b5132
RH
13138 else
13139 {
c0ebe874
RS
13140 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13141 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
252b5132 13142 }
8fc2e39e 13143 break;
252b5132
RH
13144
13145 case M_SNE_I:
b0e6f033 13146 if (imm_expr.X_add_number == 0)
252b5132 13147 {
c0ebe874 13148 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
8fc2e39e 13149 break;
252b5132 13150 }
c0ebe874 13151 if (op[1] == 0)
252b5132 13152 {
1661c76c 13153 as_warn (_("instruction %s: result is always true"),
252b5132 13154 ip->insn_mo->name);
bad1aba3 13155 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
c0ebe874 13156 op[0], 0, BFD_RELOC_LO16);
8fc2e39e 13157 break;
252b5132 13158 }
dd3cbb7e
NC
13159 if (CPU_HAS_SEQ (mips_opts.arch)
13160 && -512 <= imm_expr.X_add_number
13161 && imm_expr.X_add_number < 512)
13162 {
c0ebe874 13163 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
750bdd57 13164 (int) imm_expr.X_add_number);
dd3cbb7e
NC
13165 break;
13166 }
b0e6f033 13167 if (imm_expr.X_add_number >= 0
252b5132
RH
13168 && imm_expr.X_add_number < 0x10000)
13169 {
c0ebe874
RS
13170 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13171 BFD_RELOC_LO16);
252b5132 13172 }
b0e6f033 13173 else if (imm_expr.X_add_number > -0x8000
252b5132
RH
13174 && imm_expr.X_add_number < 0)
13175 {
13176 imm_expr.X_add_number = -imm_expr.X_add_number;
bad1aba3 13177 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
c0ebe874 13178 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
252b5132 13179 }
dd3cbb7e
NC
13180 else if (CPU_HAS_SEQ (mips_opts.arch))
13181 {
13182 used_at = 1;
bad1aba3 13183 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13184 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
dd3cbb7e
NC
13185 break;
13186 }
252b5132
RH
13187 else
13188 {
bad1aba3 13189 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13190 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
252b5132
RH
13191 used_at = 1;
13192 }
c0ebe874 13193 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
8fc2e39e 13194 break;
252b5132 13195
df58fc94
RS
13196 case M_SUB_I:
13197 s = "addi";
13198 s2 = "sub";
13199 goto do_subi;
13200 case M_SUBU_I:
13201 s = "addiu";
13202 s2 = "subu";
13203 goto do_subi;
252b5132
RH
13204 case M_DSUB_I:
13205 dbl = 1;
df58fc94
RS
13206 s = "daddi";
13207 s2 = "dsub";
13208 if (!mips_opts.micromips)
13209 goto do_subi;
b0e6f033 13210 if (imm_expr.X_add_number > -0x200
df58fc94 13211 && imm_expr.X_add_number <= 0x200)
252b5132 13212 {
b0e6f033
RS
13213 macro_build (NULL, s, "t,r,.", op[0], op[1],
13214 (int) -imm_expr.X_add_number);
8fc2e39e 13215 break;
252b5132 13216 }
df58fc94 13217 goto do_subi_i;
252b5132
RH
13218 case M_DSUBU_I:
13219 dbl = 1;
df58fc94
RS
13220 s = "daddiu";
13221 s2 = "dsubu";
13222 do_subi:
b0e6f033 13223 if (imm_expr.X_add_number > -0x8000
252b5132
RH
13224 && imm_expr.X_add_number <= 0x8000)
13225 {
13226 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 13227 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
8fc2e39e 13228 break;
252b5132 13229 }
df58fc94 13230 do_subi_i:
8fc2e39e 13231 used_at = 1;
67c0d1eb 13232 load_register (AT, &imm_expr, dbl);
c0ebe874 13233 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
252b5132
RH
13234 break;
13235
13236 case M_TEQ_I:
13237 s = "teq";
13238 goto trap;
13239 case M_TGE_I:
13240 s = "tge";
13241 goto trap;
13242 case M_TGEU_I:
13243 s = "tgeu";
13244 goto trap;
13245 case M_TLT_I:
13246 s = "tlt";
13247 goto trap;
13248 case M_TLTU_I:
13249 s = "tltu";
13250 goto trap;
13251 case M_TNE_I:
13252 s = "tne";
13253 trap:
8fc2e39e 13254 used_at = 1;
bad1aba3 13255 load_register (AT, &imm_expr, GPR_SIZE == 64);
c0ebe874 13256 macro_build (NULL, s, "s,t", op[0], AT);
252b5132
RH
13257 break;
13258
252b5132 13259 case M_TRUNCWS:
43841e91 13260 case M_TRUNCWD:
df58fc94 13261 gas_assert (!mips_opts.micromips);
0aa27725 13262 gas_assert (mips_opts.isa == ISA_MIPS1);
8fc2e39e 13263 used_at = 1;
252b5132
RH
13264
13265 /*
13266 * Is the double cfc1 instruction a bug in the mips assembler;
13267 * or is there a reason for it?
13268 */
7d10b47d 13269 start_noreorder ();
c0ebe874
RS
13270 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13271 macro_build (NULL, "cfc1", "t,G", op[2], RA);
67c0d1eb 13272 macro_build (NULL, "nop", "");
252b5132 13273 expr1.X_add_number = 3;
c0ebe874 13274 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
252b5132 13275 expr1.X_add_number = 2;
67c0d1eb
RS
13276 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13277 macro_build (NULL, "ctc1", "t,G", AT, RA);
13278 macro_build (NULL, "nop", "");
13279 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
c0ebe874
RS
13280 op[0], op[1]);
13281 macro_build (NULL, "ctc1", "t,G", op[2], RA);
67c0d1eb 13282 macro_build (NULL, "nop", "");
7d10b47d 13283 end_noreorder ();
252b5132
RH
13284 break;
13285
f2ae14a1 13286 case M_ULH_AB:
252b5132 13287 s = "lb";
df58fc94
RS
13288 s2 = "lbu";
13289 off = 1;
13290 goto uld_st;
f2ae14a1 13291 case M_ULHU_AB:
252b5132 13292 s = "lbu";
df58fc94
RS
13293 s2 = "lbu";
13294 off = 1;
13295 goto uld_st;
f2ae14a1 13296 case M_ULW_AB:
df58fc94
RS
13297 s = "lwl";
13298 s2 = "lwr";
7f3c4072 13299 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
13300 off = 3;
13301 goto uld_st;
f2ae14a1 13302 case M_ULD_AB:
252b5132
RH
13303 s = "ldl";
13304 s2 = "ldr";
7f3c4072 13305 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 13306 off = 7;
df58fc94 13307 goto uld_st;
f2ae14a1 13308 case M_USH_AB:
df58fc94
RS
13309 s = "sb";
13310 s2 = "sb";
13311 off = 1;
13312 ust = 1;
13313 goto uld_st;
f2ae14a1 13314 case M_USW_AB:
df58fc94
RS
13315 s = "swl";
13316 s2 = "swr";
7f3c4072 13317 offbits = (mips_opts.micromips ? 12 : 16);
252b5132 13318 off = 3;
df58fc94
RS
13319 ust = 1;
13320 goto uld_st;
f2ae14a1 13321 case M_USD_AB:
df58fc94
RS
13322 s = "sdl";
13323 s2 = "sdr";
7f3c4072 13324 offbits = (mips_opts.micromips ? 12 : 16);
df58fc94
RS
13325 off = 7;
13326 ust = 1;
13327
13328 uld_st:
c0ebe874 13329 breg = op[2];
f2ae14a1 13330 large_offset = !small_offset_p (off, align, offbits);
df58fc94
RS
13331 ep = &offset_expr;
13332 expr1.X_add_number = 0;
f2ae14a1 13333 if (large_offset)
df58fc94
RS
13334 {
13335 used_at = 1;
13336 tempreg = AT;
f2ae14a1
RS
13337 if (small_offset_p (0, align, 16))
13338 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13339 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13340 else
13341 {
13342 load_address (tempreg, ep, &used_at);
13343 if (breg != 0)
13344 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13345 tempreg, tempreg, breg);
13346 }
13347 offset_reloc[0] = BFD_RELOC_LO16;
13348 offset_reloc[1] = BFD_RELOC_UNUSED;
13349 offset_reloc[2] = BFD_RELOC_UNUSED;
df58fc94 13350 breg = tempreg;
c0ebe874 13351 tempreg = op[0];
df58fc94
RS
13352 ep = &expr1;
13353 }
c0ebe874 13354 else if (!ust && op[0] == breg)
8fc2e39e
TS
13355 {
13356 used_at = 1;
13357 tempreg = AT;
13358 }
252b5132 13359 else
c0ebe874 13360 tempreg = op[0];
af22f5b2 13361
df58fc94
RS
13362 if (off == 1)
13363 goto ulh_sh;
252b5132 13364
90ecf173 13365 if (!target_big_endian)
df58fc94 13366 ep->X_add_number += off;
f2ae14a1 13367 if (offbits == 12)
c8276761 13368 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
13369 else
13370 macro_build (ep, s, "t,o(b)", tempreg, -1,
13371 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94 13372
90ecf173 13373 if (!target_big_endian)
df58fc94 13374 ep->X_add_number -= off;
252b5132 13375 else
df58fc94 13376 ep->X_add_number += off;
f2ae14a1 13377 if (offbits == 12)
df58fc94 13378 macro_build (NULL, s2, "t,~(b)",
c8276761 13379 tempreg, (int) ep->X_add_number, breg);
f2ae14a1
RS
13380 else
13381 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13382 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 13383
df58fc94 13384 /* If necessary, move the result in tempreg to the final destination. */
c0ebe874 13385 if (!ust && op[0] != tempreg)
df58fc94
RS
13386 {
13387 /* Protect second load's delay slot. */
13388 load_delay_nop ();
c0ebe874 13389 move_register (op[0], tempreg);
df58fc94 13390 }
8fc2e39e 13391 break;
252b5132 13392
df58fc94 13393 ulh_sh:
d6bc6245 13394 used_at = 1;
df58fc94
RS
13395 if (target_big_endian == ust)
13396 ep->X_add_number += off;
c0ebe874 13397 tempreg = ust || large_offset ? op[0] : AT;
f2ae14a1
RS
13398 macro_build (ep, s, "t,o(b)", tempreg, -1,
13399 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
df58fc94
RS
13400
13401 /* For halfword transfers we need a temporary register to shuffle
13402 bytes. Unfortunately for M_USH_A we have none available before
13403 the next store as AT holds the base address. We deal with this
13404 case by clobbering TREG and then restoring it as with ULH. */
c0ebe874 13405 tempreg = ust == large_offset ? op[0] : AT;
df58fc94 13406 if (ust)
c0ebe874 13407 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
df58fc94
RS
13408
13409 if (target_big_endian == ust)
13410 ep->X_add_number -= off;
252b5132 13411 else
df58fc94 13412 ep->X_add_number += off;
f2ae14a1
RS
13413 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13414 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
252b5132 13415
df58fc94 13416 /* For M_USH_A re-retrieve the LSB. */
f2ae14a1 13417 if (ust && large_offset)
df58fc94
RS
13418 {
13419 if (target_big_endian)
13420 ep->X_add_number += off;
13421 else
13422 ep->X_add_number -= off;
f2ae14a1
RS
13423 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13424 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
df58fc94
RS
13425 }
13426 /* For ULH and M_USH_A OR the LSB in. */
f2ae14a1 13427 if (!ust || large_offset)
df58fc94 13428 {
c0ebe874 13429 tempreg = !large_offset ? AT : op[0];
df58fc94 13430 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
c0ebe874 13431 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
df58fc94 13432 }
252b5132
RH
13433 break;
13434
13435 default:
13436 /* FIXME: Check if this is one of the itbl macros, since they
bdaaa2e1 13437 are added dynamically. */
1661c76c 13438 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
252b5132
RH
13439 break;
13440 }
741fe287 13441 if (!mips_opts.at && used_at)
1661c76c 13442 as_bad (_("macro used $at after \".set noat\""));
252b5132
RH
13443}
13444
13445/* Implement macros in mips16 mode. */
13446
13447static void
17a2f251 13448mips16_macro (struct mips_cl_insn *ip)
252b5132 13449{
c0ebe874 13450 const struct mips_operand_array *operands;
252b5132 13451 int mask;
c0ebe874 13452 int tmp;
252b5132
RH
13453 expressionS expr1;
13454 int dbl;
13455 const char *s, *s2, *s3;
c0ebe874
RS
13456 unsigned int op[MAX_OPERANDS];
13457 unsigned int i;
252b5132
RH
13458
13459 mask = ip->insn_mo->mask;
13460
c0ebe874
RS
13461 operands = insn_operands (ip);
13462 for (i = 0; i < MAX_OPERANDS; i++)
13463 if (operands->operand[i])
13464 op[i] = insn_extract_operand (ip, operands->operand[i]);
13465 else
13466 op[i] = -1;
252b5132 13467
252b5132
RH
13468 expr1.X_op = O_constant;
13469 expr1.X_op_symbol = NULL;
13470 expr1.X_add_symbol = NULL;
13471 expr1.X_add_number = 1;
13472
13473 dbl = 0;
13474
13475 switch (mask)
13476 {
13477 default:
b37df7c4 13478 abort ();
252b5132
RH
13479
13480 case M_DDIV_3:
13481 dbl = 1;
1a0670f3 13482 /* Fall through. */
252b5132
RH
13483 case M_DIV_3:
13484 s = "mflo";
13485 goto do_div3;
13486 case M_DREM_3:
13487 dbl = 1;
1a0670f3 13488 /* Fall through. */
252b5132
RH
13489 case M_REM_3:
13490 s = "mfhi";
13491 do_div3:
7d10b47d 13492 start_noreorder ();
c0ebe874 13493 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
252b5132 13494 expr1.X_add_number = 2;
c0ebe874 13495 macro_build (&expr1, "bnez", "x,p", op[2]);
67c0d1eb 13496 macro_build (NULL, "break", "6", 7);
bdaaa2e1 13497
252b5132
RH
13498 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13499 since that causes an overflow. We should do that as well,
13500 but I don't see how to do the comparisons without a temporary
13501 register. */
7d10b47d 13502 end_noreorder ();
c0ebe874 13503 macro_build (NULL, s, "x", op[0]);
252b5132
RH
13504 break;
13505
13506 case M_DIVU_3:
13507 s = "divu";
13508 s2 = "mflo";
13509 goto do_divu3;
13510 case M_REMU_3:
13511 s = "divu";
13512 s2 = "mfhi";
13513 goto do_divu3;
13514 case M_DDIVU_3:
13515 s = "ddivu";
13516 s2 = "mflo";
13517 goto do_divu3;
13518 case M_DREMU_3:
13519 s = "ddivu";
13520 s2 = "mfhi";
13521 do_divu3:
7d10b47d 13522 start_noreorder ();
c0ebe874 13523 macro_build (NULL, s, "0,x,y", op[1], op[2]);
252b5132 13524 expr1.X_add_number = 2;
c0ebe874 13525 macro_build (&expr1, "bnez", "x,p", op[2]);
67c0d1eb 13526 macro_build (NULL, "break", "6", 7);
7d10b47d 13527 end_noreorder ();
c0ebe874 13528 macro_build (NULL, s2, "x", op[0]);
252b5132
RH
13529 break;
13530
13531 case M_DMUL:
13532 dbl = 1;
1a0670f3 13533 /* Fall through. */
252b5132 13534 case M_MUL:
c0ebe874
RS
13535 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13536 macro_build (NULL, "mflo", "x", op[0]);
8fc2e39e 13537 break;
252b5132
RH
13538
13539 case M_DSUBU_I:
13540 dbl = 1;
13541 goto do_subu;
13542 case M_SUBU_I:
13543 do_subu:
252b5132 13544 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 13545 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
252b5132
RH
13546 break;
13547
13548 case M_SUBU_I_2:
252b5132 13549 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 13550 macro_build (&imm_expr, "addiu", "x,k", op[0]);
252b5132
RH
13551 break;
13552
13553 case M_DSUBU_I_2:
252b5132 13554 imm_expr.X_add_number = -imm_expr.X_add_number;
c0ebe874 13555 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
252b5132
RH
13556 break;
13557
13558 case M_BEQ:
13559 s = "cmp";
13560 s2 = "bteqz";
13561 goto do_branch;
13562 case M_BNE:
13563 s = "cmp";
13564 s2 = "btnez";
13565 goto do_branch;
13566 case M_BLT:
13567 s = "slt";
13568 s2 = "btnez";
13569 goto do_branch;
13570 case M_BLTU:
13571 s = "sltu";
13572 s2 = "btnez";
13573 goto do_branch;
13574 case M_BLE:
13575 s = "slt";
13576 s2 = "bteqz";
13577 goto do_reverse_branch;
13578 case M_BLEU:
13579 s = "sltu";
13580 s2 = "bteqz";
13581 goto do_reverse_branch;
13582 case M_BGE:
13583 s = "slt";
13584 s2 = "bteqz";
13585 goto do_branch;
13586 case M_BGEU:
13587 s = "sltu";
13588 s2 = "bteqz";
13589 goto do_branch;
13590 case M_BGT:
13591 s = "slt";
13592 s2 = "btnez";
13593 goto do_reverse_branch;
13594 case M_BGTU:
13595 s = "sltu";
13596 s2 = "btnez";
13597
13598 do_reverse_branch:
c0ebe874
RS
13599 tmp = op[1];
13600 op[1] = op[0];
13601 op[0] = tmp;
252b5132
RH
13602
13603 do_branch:
c0ebe874 13604 macro_build (NULL, s, "x,y", op[0], op[1]);
67c0d1eb 13605 macro_build (&offset_expr, s2, "p");
252b5132
RH
13606 break;
13607
13608 case M_BEQ_I:
13609 s = "cmpi";
13610 s2 = "bteqz";
13611 s3 = "x,U";
13612 goto do_branch_i;
13613 case M_BNE_I:
13614 s = "cmpi";
13615 s2 = "btnez";
13616 s3 = "x,U";
13617 goto do_branch_i;
13618 case M_BLT_I:
13619 s = "slti";
13620 s2 = "btnez";
13621 s3 = "x,8";
13622 goto do_branch_i;
13623 case M_BLTU_I:
13624 s = "sltiu";
13625 s2 = "btnez";
13626 s3 = "x,8";
13627 goto do_branch_i;
13628 case M_BLE_I:
13629 s = "slti";
13630 s2 = "btnez";
13631 s3 = "x,8";
13632 goto do_addone_branch_i;
13633 case M_BLEU_I:
13634 s = "sltiu";
13635 s2 = "btnez";
13636 s3 = "x,8";
13637 goto do_addone_branch_i;
13638 case M_BGE_I:
13639 s = "slti";
13640 s2 = "bteqz";
13641 s3 = "x,8";
13642 goto do_branch_i;
13643 case M_BGEU_I:
13644 s = "sltiu";
13645 s2 = "bteqz";
13646 s3 = "x,8";
13647 goto do_branch_i;
13648 case M_BGT_I:
13649 s = "slti";
13650 s2 = "bteqz";
13651 s3 = "x,8";
13652 goto do_addone_branch_i;
13653 case M_BGTU_I:
13654 s = "sltiu";
13655 s2 = "bteqz";
13656 s3 = "x,8";
13657
13658 do_addone_branch_i:
252b5132
RH
13659 ++imm_expr.X_add_number;
13660
13661 do_branch_i:
c0ebe874 13662 macro_build (&imm_expr, s, s3, op[0]);
67c0d1eb 13663 macro_build (&offset_expr, s2, "p");
252b5132
RH
13664 break;
13665
13666 case M_ABS:
13667 expr1.X_add_number = 0;
c0ebe874
RS
13668 macro_build (&expr1, "slti", "x,8", op[1]);
13669 if (op[0] != op[1])
13670 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
252b5132 13671 expr1.X_add_number = 2;
67c0d1eb 13672 macro_build (&expr1, "bteqz", "p");
c0ebe874 13673 macro_build (NULL, "neg", "x,w", op[0], op[0]);
0acfaea6 13674 break;
252b5132
RH
13675 }
13676}
13677
14daeee3
RS
13678/* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13679 opcode bits in *OPCODE_EXTRA. */
13680
13681static struct mips_opcode *
13682mips_lookup_insn (struct hash_control *hash, const char *start,
da8bca91 13683 ssize_t length, unsigned int *opcode_extra)
14daeee3
RS
13684{
13685 char *name, *dot, *p;
13686 unsigned int mask, suffix;
da8bca91 13687 ssize_t opend;
14daeee3
RS
13688 struct mips_opcode *insn;
13689
13690 /* Make a copy of the instruction so that we can fiddle with it. */
4ec9d7d5 13691 name = xstrndup (start, length);
14daeee3
RS
13692
13693 /* Look up the instruction as-is. */
13694 insn = (struct mips_opcode *) hash_find (hash, name);
ee5734f0 13695 if (insn)
e1fa0163 13696 goto end;
14daeee3
RS
13697
13698 dot = strchr (name, '.');
13699 if (dot && dot[1])
13700 {
13701 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13702 p = mips_parse_vu0_channels (dot + 1, &mask);
13703 if (*p == 0 && mask != 0)
13704 {
13705 *dot = 0;
13706 insn = (struct mips_opcode *) hash_find (hash, name);
13707 *dot = '.';
13708 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13709 {
13710 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
e1fa0163 13711 goto end;
14daeee3
RS
13712 }
13713 }
13714 }
13715
13716 if (mips_opts.micromips)
13717 {
13718 /* See if there's an instruction size override suffix,
13719 either `16' or `32', at the end of the mnemonic proper,
13720 that defines the operation, i.e. before the first `.'
13721 character if any. Strip it and retry. */
13722 opend = dot != NULL ? dot - name : length;
13723 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13724 suffix = 2;
13725 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13726 suffix = 4;
13727 else
13728 suffix = 0;
13729 if (suffix)
13730 {
13731 memcpy (name + opend - 2, name + opend, length - opend + 1);
13732 insn = (struct mips_opcode *) hash_find (hash, name);
ee5734f0 13733 if (insn)
14daeee3
RS
13734 {
13735 forced_insn_length = suffix;
e1fa0163 13736 goto end;
14daeee3
RS
13737 }
13738 }
13739 }
13740
e1fa0163
NC
13741 insn = NULL;
13742 end:
13743 free (name);
13744 return insn;
14daeee3
RS
13745}
13746
77bd4346 13747/* Assemble an instruction into its binary format. If the instruction
e423441d
RS
13748 is a macro, set imm_expr and offset_expr to the values associated
13749 with "I" and "A" operands respectively. Otherwise store the value
13750 of the relocatable field (if any) in offset_expr. In both cases
13751 set offset_reloc to the relocation operators applied to offset_expr. */
252b5132
RH
13752
13753static void
60f20e8b 13754mips_ip (char *str, struct mips_cl_insn *insn)
252b5132 13755{
60f20e8b 13756 const struct mips_opcode *first, *past;
df58fc94 13757 struct hash_control *hash;
a92713e6 13758 char format;
14daeee3 13759 size_t end;
a92713e6 13760 struct mips_operand_token *tokens;
14daeee3 13761 unsigned int opcode_extra;
252b5132 13762
df58fc94
RS
13763 if (mips_opts.micromips)
13764 {
13765 hash = micromips_op_hash;
13766 past = &micromips_opcodes[bfd_micromips_num_opcodes];
13767 }
13768 else
13769 {
13770 hash = op_hash;
13771 past = &mips_opcodes[NUMOPCODES];
13772 }
13773 forced_insn_length = 0;
14daeee3 13774 opcode_extra = 0;
252b5132 13775
df58fc94 13776 /* We first try to match an instruction up to a space or to the end. */
a40bc9dd
RS
13777 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
13778 continue;
bdaaa2e1 13779
60f20e8b
RS
13780 first = mips_lookup_insn (hash, str, end, &opcode_extra);
13781 if (first == NULL)
252b5132 13782 {
1661c76c 13783 set_insn_error (0, _("unrecognized opcode"));
a40bc9dd 13784 return;
252b5132
RH
13785 }
13786
60f20e8b 13787 if (strcmp (first->name, "li.s") == 0)
a92713e6 13788 format = 'f';
60f20e8b 13789 else if (strcmp (first->name, "li.d") == 0)
a92713e6
RS
13790 format = 'd';
13791 else
13792 format = 0;
13793 tokens = mips_parse_arguments (str + end, format);
13794 if (!tokens)
13795 return;
13796
60f20e8b
RS
13797 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13798 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
1661c76c 13799 set_insn_error (0, _("invalid operands"));
df58fc94 13800
e3de51ce 13801 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
13802}
13803
77bd4346
RS
13804/* As for mips_ip, but used when assembling MIPS16 code.
13805 Also set forced_insn_length to the resulting instruction size in
13806 bytes if the user explicitly requested a small or extended instruction. */
252b5132
RH
13807
13808static void
60f20e8b 13809mips16_ip (char *str, struct mips_cl_insn *insn)
252b5132 13810{
1a00e612 13811 char *end, *s, c;
60f20e8b 13812 struct mips_opcode *first;
a92713e6 13813 struct mips_operand_token *tokens;
252b5132 13814
df58fc94 13815 forced_insn_length = 0;
252b5132 13816
3882b010 13817 for (s = str; ISLOWER (*s); ++s)
252b5132 13818 ;
1a00e612
RS
13819 end = s;
13820 c = *end;
13821 switch (c)
252b5132
RH
13822 {
13823 case '\0':
13824 break;
13825
13826 case ' ':
1a00e612 13827 s++;
252b5132
RH
13828 break;
13829
13830 case '.':
13831 if (s[1] == 't' && s[2] == ' ')
13832 {
df58fc94 13833 forced_insn_length = 2;
252b5132
RH
13834 s += 3;
13835 break;
13836 }
13837 else if (s[1] == 'e' && s[2] == ' ')
13838 {
df58fc94 13839 forced_insn_length = 4;
252b5132
RH
13840 s += 3;
13841 break;
13842 }
13843 /* Fall through. */
13844 default:
1661c76c 13845 set_insn_error (0, _("unrecognized opcode"));
252b5132
RH
13846 return;
13847 }
13848
df58fc94
RS
13849 if (mips_opts.noautoextend && !forced_insn_length)
13850 forced_insn_length = 2;
252b5132 13851
1a00e612 13852 *end = 0;
60f20e8b 13853 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
1a00e612
RS
13854 *end = c;
13855
60f20e8b 13856 if (!first)
252b5132 13857 {
1661c76c 13858 set_insn_error (0, _("unrecognized opcode"));
252b5132
RH
13859 return;
13860 }
13861
a92713e6
RS
13862 tokens = mips_parse_arguments (s, 0);
13863 if (!tokens)
13864 return;
13865
60f20e8b 13866 if (!match_mips16_insns (insn, first, tokens))
1661c76c 13867 set_insn_error (0, _("invalid operands"));
252b5132 13868
e3de51ce 13869 obstack_free (&mips_operand_tokens, tokens);
252b5132
RH
13870}
13871
b886a2ab
RS
13872/* Marshal immediate value VAL for an extended MIPS16 instruction.
13873 NBITS is the number of significant bits in VAL. */
13874
13875static unsigned long
13876mips16_immed_extend (offsetT val, unsigned int nbits)
13877{
13878 int extval;
13879 if (nbits == 16)
13880 {
13881 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13882 val &= 0x1f;
13883 }
13884 else if (nbits == 15)
13885 {
13886 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13887 val &= 0xf;
13888 }
13889 else
13890 {
13891 extval = ((val & 0x1f) << 6) | (val & 0x20);
13892 val = 0;
13893 }
13894 return (extval << 16) | val;
13895}
13896
3ccad066
RS
13897/* Like decode_mips16_operand, but require the operand to be defined and
13898 require it to be an integer. */
13899
13900static const struct mips_int_operand *
13901mips16_immed_operand (int type, bfd_boolean extended_p)
13902{
13903 const struct mips_operand *operand;
13904
13905 operand = decode_mips16_operand (type, extended_p);
13906 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13907 abort ();
13908 return (const struct mips_int_operand *) operand;
13909}
13910
13911/* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13912
13913static bfd_boolean
13914mips16_immed_in_range_p (const struct mips_int_operand *operand,
13915 bfd_reloc_code_real_type reloc, offsetT sval)
13916{
13917 int min_val, max_val;
13918
13919 min_val = mips_int_operand_min (operand);
13920 max_val = mips_int_operand_max (operand);
13921 if (reloc != BFD_RELOC_UNUSED)
13922 {
13923 if (min_val < 0)
13924 sval = SEXT_16BIT (sval);
13925 else
13926 sval &= 0xffff;
13927 }
13928
13929 return (sval >= min_val
13930 && sval <= max_val
13931 && (sval & ((1 << operand->shift) - 1)) == 0);
13932}
13933
5c04167a
RS
13934/* Install immediate value VAL into MIPS16 instruction *INSN,
13935 extending it if necessary. The instruction in *INSN may
13936 already be extended.
13937
43c0598f
RS
13938 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13939 if none. In the former case, VAL is a 16-bit number with no
13940 defined signedness.
13941
13942 TYPE is the type of the immediate field. USER_INSN_LENGTH
13943 is the length that the user requested, or 0 if none. */
252b5132
RH
13944
13945static void
3b4dbbbf 13946mips16_immed (const char *file, unsigned int line, int type,
43c0598f 13947 bfd_reloc_code_real_type reloc, offsetT val,
5c04167a 13948 unsigned int user_insn_length, unsigned long *insn)
252b5132 13949{
3ccad066
RS
13950 const struct mips_int_operand *operand;
13951 unsigned int uval, length;
252b5132 13952
3ccad066
RS
13953 operand = mips16_immed_operand (type, FALSE);
13954 if (!mips16_immed_in_range_p (operand, reloc, val))
5c04167a
RS
13955 {
13956 /* We need an extended instruction. */
13957 if (user_insn_length == 2)
13958 as_bad_where (file, line, _("invalid unextended operand value"));
13959 else
13960 *insn |= MIPS16_EXTEND;
13961 }
13962 else if (user_insn_length == 4)
13963 {
13964 /* The operand doesn't force an unextended instruction to be extended.
13965 Warn if the user wanted an extended instruction anyway. */
13966 *insn |= MIPS16_EXTEND;
13967 as_warn_where (file, line,
13968 _("extended operand requested but not required"));
13969 }
252b5132 13970
3ccad066
RS
13971 length = mips16_opcode_length (*insn);
13972 if (length == 4)
252b5132 13973 {
3ccad066
RS
13974 operand = mips16_immed_operand (type, TRUE);
13975 if (!mips16_immed_in_range_p (operand, reloc, val))
13976 as_bad_where (file, line,
13977 _("operand value out of range for instruction"));
252b5132 13978 }
3ccad066
RS
13979 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13980 if (length == 2)
13981 *insn = mips_insert_operand (&operand->root, *insn, uval);
252b5132 13982 else
3ccad066 13983 *insn |= mips16_immed_extend (uval, operand->root.size);
252b5132
RH
13984}
13985\f
d6f16593 13986struct percent_op_match
ad8d3bb3 13987{
5e0116d5
RS
13988 const char *str;
13989 bfd_reloc_code_real_type reloc;
d6f16593
MR
13990};
13991
13992static const struct percent_op_match mips_percent_op[] =
ad8d3bb3 13993{
5e0116d5 13994 {"%lo", BFD_RELOC_LO16},
5e0116d5
RS
13995 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13996 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13997 {"%call16", BFD_RELOC_MIPS_CALL16},
13998 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13999 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14000 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14001 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14002 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14003 {"%got", BFD_RELOC_MIPS_GOT16},
14004 {"%gp_rel", BFD_RELOC_GPREL16},
14005 {"%half", BFD_RELOC_16},
14006 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14007 {"%higher", BFD_RELOC_MIPS_HIGHER},
14008 {"%neg", BFD_RELOC_MIPS_SUB},
3f98094e
DJ
14009 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14010 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14011 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14012 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14013 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14014 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14015 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
7361da2c
AB
14016 {"%hi", BFD_RELOC_HI16_S},
14017 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
14018 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
ad8d3bb3
TS
14019};
14020
d6f16593
MR
14021static const struct percent_op_match mips16_percent_op[] =
14022{
14023 {"%lo", BFD_RELOC_MIPS16_LO16},
14024 {"%gprel", BFD_RELOC_MIPS16_GPREL},
738e5348
RS
14025 {"%got", BFD_RELOC_MIPS16_GOT16},
14026 {"%call16", BFD_RELOC_MIPS16_CALL16},
d0f13682
CLT
14027 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14028 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14029 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14030 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14031 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14032 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14033 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14034 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
d6f16593
MR
14035};
14036
252b5132 14037
5e0116d5
RS
14038/* Return true if *STR points to a relocation operator. When returning true,
14039 move *STR over the operator and store its relocation code in *RELOC.
14040 Leave both *STR and *RELOC alone when returning false. */
14041
14042static bfd_boolean
17a2f251 14043parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
252b5132 14044{
d6f16593
MR
14045 const struct percent_op_match *percent_op;
14046 size_t limit, i;
14047
14048 if (mips_opts.mips16)
14049 {
14050 percent_op = mips16_percent_op;
14051 limit = ARRAY_SIZE (mips16_percent_op);
14052 }
14053 else
14054 {
14055 percent_op = mips_percent_op;
14056 limit = ARRAY_SIZE (mips_percent_op);
14057 }
76b3015f 14058
d6f16593 14059 for (i = 0; i < limit; i++)
5e0116d5 14060 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
394f9b3a 14061 {
3f98094e
DJ
14062 int len = strlen (percent_op[i].str);
14063
14064 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14065 continue;
14066
5e0116d5
RS
14067 *str += strlen (percent_op[i].str);
14068 *reloc = percent_op[i].reloc;
394f9b3a 14069
5e0116d5
RS
14070 /* Check whether the output BFD supports this relocation.
14071 If not, issue an error and fall back on something safe. */
14072 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
394f9b3a 14073 {
20203fb9 14074 as_bad (_("relocation %s isn't supported by the current ABI"),
5e0116d5 14075 percent_op[i].str);
01a3f561 14076 *reloc = BFD_RELOC_UNUSED;
394f9b3a 14077 }
5e0116d5 14078 return TRUE;
394f9b3a 14079 }
5e0116d5 14080 return FALSE;
394f9b3a 14081}
ad8d3bb3 14082
ad8d3bb3 14083
5e0116d5
RS
14084/* Parse string STR as a 16-bit relocatable operand. Store the
14085 expression in *EP and the relocations in the array starting
14086 at RELOC. Return the number of relocation operators used.
ad8d3bb3 14087
01a3f561 14088 On exit, EXPR_END points to the first character after the expression. */
ad8d3bb3 14089
5e0116d5 14090static size_t
17a2f251
TS
14091my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14092 char *str)
ad8d3bb3 14093{
5e0116d5
RS
14094 bfd_reloc_code_real_type reversed_reloc[3];
14095 size_t reloc_index, i;
09b8f35a
RS
14096 int crux_depth, str_depth;
14097 char *crux;
5e0116d5
RS
14098
14099 /* Search for the start of the main expression, recoding relocations
09b8f35a
RS
14100 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14101 of the main expression and with CRUX_DEPTH containing the number
14102 of open brackets at that point. */
14103 reloc_index = -1;
14104 str_depth = 0;
14105 do
fb1b3232 14106 {
09b8f35a
RS
14107 reloc_index++;
14108 crux = str;
14109 crux_depth = str_depth;
14110
14111 /* Skip over whitespace and brackets, keeping count of the number
14112 of brackets. */
14113 while (*str == ' ' || *str == '\t' || *str == '(')
14114 if (*str++ == '(')
14115 str_depth++;
5e0116d5 14116 }
09b8f35a
RS
14117 while (*str == '%'
14118 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14119 && parse_relocation (&str, &reversed_reloc[reloc_index]));
ad8d3bb3 14120
09b8f35a 14121 my_getExpression (ep, crux);
5e0116d5 14122 str = expr_end;
394f9b3a 14123
5e0116d5 14124 /* Match every open bracket. */
09b8f35a 14125 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
5e0116d5 14126 if (*str++ == ')')
09b8f35a 14127 crux_depth--;
394f9b3a 14128
09b8f35a 14129 if (crux_depth > 0)
20203fb9 14130 as_bad (_("unclosed '('"));
394f9b3a 14131
5e0116d5 14132 expr_end = str;
252b5132 14133
01a3f561 14134 if (reloc_index != 0)
64bdfcaf
RS
14135 {
14136 prev_reloc_op_frag = frag_now;
14137 for (i = 0; i < reloc_index; i++)
14138 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14139 }
fb1b3232 14140
5e0116d5 14141 return reloc_index;
252b5132
RH
14142}
14143
14144static void
17a2f251 14145my_getExpression (expressionS *ep, char *str)
252b5132
RH
14146{
14147 char *save_in;
14148
14149 save_in = input_line_pointer;
14150 input_line_pointer = str;
14151 expression (ep);
14152 expr_end = input_line_pointer;
14153 input_line_pointer = save_in;
252b5132
RH
14154}
14155
6d4af3c2 14156const char *
17a2f251 14157md_atof (int type, char *litP, int *sizeP)
252b5132 14158{
499ac353 14159 return ieee_md_atof (type, litP, sizeP, target_big_endian);
252b5132
RH
14160}
14161
14162void
17a2f251 14163md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH
14164{
14165 if (target_big_endian)
14166 number_to_chars_bigendian (buf, val, n);
14167 else
14168 number_to_chars_littleendian (buf, val, n);
14169}
14170\f
e013f690
TS
14171static int support_64bit_objects(void)
14172{
14173 const char **list, **l;
aa3d8fdf 14174 int yes;
e013f690
TS
14175
14176 list = bfd_target_list ();
14177 for (l = list; *l != NULL; l++)
aeffff67
RS
14178 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14179 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
e013f690 14180 break;
aa3d8fdf 14181 yes = (*l != NULL);
e013f690 14182 free (list);
aa3d8fdf 14183 return yes;
e013f690
TS
14184}
14185
316f5878
RS
14186/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14187 NEW_VALUE. Warn if another value was already specified. Note:
14188 we have to defer parsing the -march and -mtune arguments in order
14189 to handle 'from-abi' correctly, since the ABI might be specified
14190 in a later argument. */
14191
14192static void
17a2f251 14193mips_set_option_string (const char **string_ptr, const char *new_value)
316f5878
RS
14194{
14195 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
1661c76c 14196 as_warn (_("a different %s was already specified, is now %s"),
316f5878
RS
14197 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14198 new_value);
14199
14200 *string_ptr = new_value;
14201}
14202
252b5132 14203int
17b9d67d 14204md_parse_option (int c, const char *arg)
252b5132 14205{
c6278170
RS
14206 unsigned int i;
14207
14208 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14209 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14210 {
919731af 14211 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
c6278170
RS
14212 c == mips_ases[i].option_on);
14213 return 1;
14214 }
14215
252b5132
RH
14216 switch (c)
14217 {
119d663a
NC
14218 case OPTION_CONSTRUCT_FLOATS:
14219 mips_disable_float_construction = 0;
14220 break;
bdaaa2e1 14221
119d663a
NC
14222 case OPTION_NO_CONSTRUCT_FLOATS:
14223 mips_disable_float_construction = 1;
14224 break;
bdaaa2e1 14225
252b5132
RH
14226 case OPTION_TRAP:
14227 mips_trap = 1;
14228 break;
14229
14230 case OPTION_BREAK:
14231 mips_trap = 0;
14232 break;
14233
14234 case OPTION_EB:
14235 target_big_endian = 1;
14236 break;
14237
14238 case OPTION_EL:
14239 target_big_endian = 0;
14240 break;
14241
14242 case 'O':
4ffff32f
TS
14243 if (arg == NULL)
14244 mips_optimize = 1;
14245 else if (arg[0] == '0')
14246 mips_optimize = 0;
14247 else if (arg[0] == '1')
252b5132
RH
14248 mips_optimize = 1;
14249 else
14250 mips_optimize = 2;
14251 break;
14252
14253 case 'g':
14254 if (arg == NULL)
14255 mips_debug = 2;
14256 else
14257 mips_debug = atoi (arg);
252b5132
RH
14258 break;
14259
14260 case OPTION_MIPS1:
0b35dfee 14261 file_mips_opts.isa = ISA_MIPS1;
252b5132
RH
14262 break;
14263
14264 case OPTION_MIPS2:
0b35dfee 14265 file_mips_opts.isa = ISA_MIPS2;
252b5132
RH
14266 break;
14267
14268 case OPTION_MIPS3:
0b35dfee 14269 file_mips_opts.isa = ISA_MIPS3;
252b5132
RH
14270 break;
14271
14272 case OPTION_MIPS4:
0b35dfee 14273 file_mips_opts.isa = ISA_MIPS4;
e7af610e
NC
14274 break;
14275
84ea6cf2 14276 case OPTION_MIPS5:
0b35dfee 14277 file_mips_opts.isa = ISA_MIPS5;
84ea6cf2
NC
14278 break;
14279
e7af610e 14280 case OPTION_MIPS32:
0b35dfee 14281 file_mips_opts.isa = ISA_MIPS32;
252b5132
RH
14282 break;
14283
af7ee8bf 14284 case OPTION_MIPS32R2:
0b35dfee 14285 file_mips_opts.isa = ISA_MIPS32R2;
af7ee8bf
CD
14286 break;
14287
ae52f483 14288 case OPTION_MIPS32R3:
0ae19f05 14289 file_mips_opts.isa = ISA_MIPS32R3;
ae52f483
AB
14290 break;
14291
14292 case OPTION_MIPS32R5:
0ae19f05 14293 file_mips_opts.isa = ISA_MIPS32R5;
ae52f483
AB
14294 break;
14295
7361da2c
AB
14296 case OPTION_MIPS32R6:
14297 file_mips_opts.isa = ISA_MIPS32R6;
14298 break;
14299
5f74bc13 14300 case OPTION_MIPS64R2:
0b35dfee 14301 file_mips_opts.isa = ISA_MIPS64R2;
5f74bc13
CD
14302 break;
14303
ae52f483 14304 case OPTION_MIPS64R3:
0ae19f05 14305 file_mips_opts.isa = ISA_MIPS64R3;
ae52f483
AB
14306 break;
14307
14308 case OPTION_MIPS64R5:
0ae19f05 14309 file_mips_opts.isa = ISA_MIPS64R5;
ae52f483
AB
14310 break;
14311
7361da2c
AB
14312 case OPTION_MIPS64R6:
14313 file_mips_opts.isa = ISA_MIPS64R6;
14314 break;
14315
84ea6cf2 14316 case OPTION_MIPS64:
0b35dfee 14317 file_mips_opts.isa = ISA_MIPS64;
84ea6cf2
NC
14318 break;
14319
ec68c924 14320 case OPTION_MTUNE:
316f5878
RS
14321 mips_set_option_string (&mips_tune_string, arg);
14322 break;
ec68c924 14323
316f5878
RS
14324 case OPTION_MARCH:
14325 mips_set_option_string (&mips_arch_string, arg);
252b5132
RH
14326 break;
14327
14328 case OPTION_M4650:
316f5878
RS
14329 mips_set_option_string (&mips_arch_string, "4650");
14330 mips_set_option_string (&mips_tune_string, "4650");
252b5132
RH
14331 break;
14332
14333 case OPTION_NO_M4650:
14334 break;
14335
14336 case OPTION_M4010:
316f5878
RS
14337 mips_set_option_string (&mips_arch_string, "4010");
14338 mips_set_option_string (&mips_tune_string, "4010");
252b5132
RH
14339 break;
14340
14341 case OPTION_NO_M4010:
14342 break;
14343
14344 case OPTION_M4100:
316f5878
RS
14345 mips_set_option_string (&mips_arch_string, "4100");
14346 mips_set_option_string (&mips_tune_string, "4100");
252b5132
RH
14347 break;
14348
14349 case OPTION_NO_M4100:
14350 break;
14351
252b5132 14352 case OPTION_M3900:
316f5878
RS
14353 mips_set_option_string (&mips_arch_string, "3900");
14354 mips_set_option_string (&mips_tune_string, "3900");
252b5132 14355 break;
bdaaa2e1 14356
252b5132
RH
14357 case OPTION_NO_M3900:
14358 break;
14359
df58fc94 14360 case OPTION_MICROMIPS:
919731af 14361 if (file_mips_opts.mips16 == 1)
df58fc94
RS
14362 {
14363 as_bad (_("-mmicromips cannot be used with -mips16"));
14364 return 0;
14365 }
919731af 14366 file_mips_opts.micromips = 1;
df58fc94
RS
14367 mips_no_prev_insn ();
14368 break;
14369
14370 case OPTION_NO_MICROMIPS:
919731af 14371 file_mips_opts.micromips = 0;
df58fc94
RS
14372 mips_no_prev_insn ();
14373 break;
14374
252b5132 14375 case OPTION_MIPS16:
919731af 14376 if (file_mips_opts.micromips == 1)
df58fc94
RS
14377 {
14378 as_bad (_("-mips16 cannot be used with -micromips"));
14379 return 0;
14380 }
919731af 14381 file_mips_opts.mips16 = 1;
7d10b47d 14382 mips_no_prev_insn ();
252b5132
RH
14383 break;
14384
14385 case OPTION_NO_MIPS16:
919731af 14386 file_mips_opts.mips16 = 0;
7d10b47d 14387 mips_no_prev_insn ();
252b5132
RH
14388 break;
14389
6a32d874
CM
14390 case OPTION_FIX_24K:
14391 mips_fix_24k = 1;
14392 break;
14393
14394 case OPTION_NO_FIX_24K:
14395 mips_fix_24k = 0;
14396 break;
14397
a8d14a88
CM
14398 case OPTION_FIX_RM7000:
14399 mips_fix_rm7000 = 1;
14400 break;
14401
14402 case OPTION_NO_FIX_RM7000:
14403 mips_fix_rm7000 = 0;
14404 break;
14405
c67a084a
NC
14406 case OPTION_FIX_LOONGSON2F_JUMP:
14407 mips_fix_loongson2f_jump = TRUE;
14408 break;
14409
14410 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14411 mips_fix_loongson2f_jump = FALSE;
14412 break;
14413
14414 case OPTION_FIX_LOONGSON2F_NOP:
14415 mips_fix_loongson2f_nop = TRUE;
14416 break;
14417
14418 case OPTION_NO_FIX_LOONGSON2F_NOP:
14419 mips_fix_loongson2f_nop = FALSE;
14420 break;
14421
d766e8ec
RS
14422 case OPTION_FIX_VR4120:
14423 mips_fix_vr4120 = 1;
60b63b72
RS
14424 break;
14425
d766e8ec
RS
14426 case OPTION_NO_FIX_VR4120:
14427 mips_fix_vr4120 = 0;
60b63b72
RS
14428 break;
14429
7d8e00cf
RS
14430 case OPTION_FIX_VR4130:
14431 mips_fix_vr4130 = 1;
14432 break;
14433
14434 case OPTION_NO_FIX_VR4130:
14435 mips_fix_vr4130 = 0;
14436 break;
14437
d954098f
DD
14438 case OPTION_FIX_CN63XXP1:
14439 mips_fix_cn63xxp1 = TRUE;
14440 break;
14441
14442 case OPTION_NO_FIX_CN63XXP1:
14443 mips_fix_cn63xxp1 = FALSE;
14444 break;
14445
4a6a3df4
AO
14446 case OPTION_RELAX_BRANCH:
14447 mips_relax_branch = 1;
14448 break;
14449
14450 case OPTION_NO_RELAX_BRANCH:
14451 mips_relax_branch = 0;
14452 break;
14453
833794fc 14454 case OPTION_INSN32:
919731af 14455 file_mips_opts.insn32 = TRUE;
833794fc
MR
14456 break;
14457
14458 case OPTION_NO_INSN32:
919731af 14459 file_mips_opts.insn32 = FALSE;
833794fc
MR
14460 break;
14461
aa6975fb
ILT
14462 case OPTION_MSHARED:
14463 mips_in_shared = TRUE;
14464 break;
14465
14466 case OPTION_MNO_SHARED:
14467 mips_in_shared = FALSE;
14468 break;
14469
aed1a261 14470 case OPTION_MSYM32:
919731af 14471 file_mips_opts.sym32 = TRUE;
aed1a261
RS
14472 break;
14473
14474 case OPTION_MNO_SYM32:
919731af 14475 file_mips_opts.sym32 = FALSE;
aed1a261
RS
14476 break;
14477
252b5132
RH
14478 /* When generating ELF code, we permit -KPIC and -call_shared to
14479 select SVR4_PIC, and -non_shared to select no PIC. This is
14480 intended to be compatible with Irix 5. */
14481 case OPTION_CALL_SHARED:
252b5132 14482 mips_pic = SVR4_PIC;
143d77c5 14483 mips_abicalls = TRUE;
252b5132
RH
14484 break;
14485
861fb55a 14486 case OPTION_CALL_NONPIC:
861fb55a
DJ
14487 mips_pic = NO_PIC;
14488 mips_abicalls = TRUE;
14489 break;
14490
252b5132 14491 case OPTION_NON_SHARED:
252b5132 14492 mips_pic = NO_PIC;
143d77c5 14493 mips_abicalls = FALSE;
252b5132
RH
14494 break;
14495
44075ae2
TS
14496 /* The -xgot option tells the assembler to use 32 bit offsets
14497 when accessing the got in SVR4_PIC mode. It is for Irix
252b5132
RH
14498 compatibility. */
14499 case OPTION_XGOT:
14500 mips_big_got = 1;
14501 break;
14502
14503 case 'G':
6caf9ef4
TS
14504 g_switch_value = atoi (arg);
14505 g_switch_seen = 1;
252b5132
RH
14506 break;
14507
34ba82a8
TS
14508 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14509 and -mabi=64. */
252b5132 14510 case OPTION_32:
f3ded42a 14511 mips_abi = O32_ABI;
252b5132
RH
14512 break;
14513
e013f690 14514 case OPTION_N32:
316f5878 14515 mips_abi = N32_ABI;
e013f690 14516 break;
252b5132 14517
e013f690 14518 case OPTION_64:
316f5878 14519 mips_abi = N64_ABI;
f43abd2b 14520 if (!support_64bit_objects())
1661c76c 14521 as_fatal (_("no compiled in support for 64 bit object file format"));
252b5132
RH
14522 break;
14523
c97ef257 14524 case OPTION_GP32:
bad1aba3 14525 file_mips_opts.gp = 32;
c97ef257
AH
14526 break;
14527
14528 case OPTION_GP64:
bad1aba3 14529 file_mips_opts.gp = 64;
c97ef257 14530 break;
252b5132 14531
ca4e0257 14532 case OPTION_FP32:
0b35dfee 14533 file_mips_opts.fp = 32;
316f5878
RS
14534 break;
14535
351cdf24
MF
14536 case OPTION_FPXX:
14537 file_mips_opts.fp = 0;
14538 break;
14539
316f5878 14540 case OPTION_FP64:
0b35dfee 14541 file_mips_opts.fp = 64;
ca4e0257
RS
14542 break;
14543
351cdf24
MF
14544 case OPTION_ODD_SPREG:
14545 file_mips_opts.oddspreg = 1;
14546 break;
14547
14548 case OPTION_NO_ODD_SPREG:
14549 file_mips_opts.oddspreg = 0;
14550 break;
14551
037b32b9 14552 case OPTION_SINGLE_FLOAT:
0b35dfee 14553 file_mips_opts.single_float = 1;
037b32b9
AN
14554 break;
14555
14556 case OPTION_DOUBLE_FLOAT:
0b35dfee 14557 file_mips_opts.single_float = 0;
037b32b9
AN
14558 break;
14559
14560 case OPTION_SOFT_FLOAT:
0b35dfee 14561 file_mips_opts.soft_float = 1;
037b32b9
AN
14562 break;
14563
14564 case OPTION_HARD_FLOAT:
0b35dfee 14565 file_mips_opts.soft_float = 0;
037b32b9
AN
14566 break;
14567
252b5132 14568 case OPTION_MABI:
e013f690 14569 if (strcmp (arg, "32") == 0)
316f5878 14570 mips_abi = O32_ABI;
e013f690 14571 else if (strcmp (arg, "o64") == 0)
316f5878 14572 mips_abi = O64_ABI;
e013f690 14573 else if (strcmp (arg, "n32") == 0)
316f5878 14574 mips_abi = N32_ABI;
e013f690
TS
14575 else if (strcmp (arg, "64") == 0)
14576 {
316f5878 14577 mips_abi = N64_ABI;
e013f690 14578 if (! support_64bit_objects())
1661c76c 14579 as_fatal (_("no compiled in support for 64 bit object file "
e013f690
TS
14580 "format"));
14581 }
14582 else if (strcmp (arg, "eabi") == 0)
316f5878 14583 mips_abi = EABI_ABI;
e013f690 14584 else
da0e507f
TS
14585 {
14586 as_fatal (_("invalid abi -mabi=%s"), arg);
14587 return 0;
14588 }
252b5132
RH
14589 break;
14590
6b76fefe 14591 case OPTION_M7000_HILO_FIX:
b34976b6 14592 mips_7000_hilo_fix = TRUE;
6b76fefe
CM
14593 break;
14594
9ee72ff1 14595 case OPTION_MNO_7000_HILO_FIX:
b34976b6 14596 mips_7000_hilo_fix = FALSE;
6b76fefe
CM
14597 break;
14598
ecb4347a 14599 case OPTION_MDEBUG:
b34976b6 14600 mips_flag_mdebug = TRUE;
ecb4347a
DJ
14601 break;
14602
14603 case OPTION_NO_MDEBUG:
b34976b6 14604 mips_flag_mdebug = FALSE;
ecb4347a 14605 break;
dcd410fe
RO
14606
14607 case OPTION_PDR:
14608 mips_flag_pdr = TRUE;
14609 break;
14610
14611 case OPTION_NO_PDR:
14612 mips_flag_pdr = FALSE;
14613 break;
0a44bf69
RS
14614
14615 case OPTION_MVXWORKS_PIC:
14616 mips_pic = VXWORKS_PIC;
14617 break;
ecb4347a 14618
ba92f887
MR
14619 case OPTION_NAN:
14620 if (strcmp (arg, "2008") == 0)
7361da2c 14621 mips_nan2008 = 1;
ba92f887 14622 else if (strcmp (arg, "legacy") == 0)
7361da2c 14623 mips_nan2008 = 0;
ba92f887
MR
14624 else
14625 {
1661c76c 14626 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
ba92f887
MR
14627 return 0;
14628 }
14629 break;
14630
252b5132
RH
14631 default:
14632 return 0;
14633 }
14634
c67a084a
NC
14635 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14636
252b5132
RH
14637 return 1;
14638}
316f5878 14639\f
919731af 14640/* Set up globals to tune for the ISA or processor described by INFO. */
252b5132 14641
316f5878 14642static void
17a2f251 14643mips_set_tune (const struct mips_cpu_info *info)
316f5878
RS
14644{
14645 if (info != 0)
fef14a42 14646 mips_tune = info->cpu;
316f5878 14647}
80cc45a5 14648
34ba82a8 14649
252b5132 14650void
17a2f251 14651mips_after_parse_args (void)
e9670677 14652{
fef14a42
TS
14653 const struct mips_cpu_info *arch_info = 0;
14654 const struct mips_cpu_info *tune_info = 0;
14655
e9670677 14656 /* GP relative stuff not working for PE */
6caf9ef4 14657 if (strncmp (TARGET_OS, "pe", 2) == 0)
e9670677 14658 {
6caf9ef4 14659 if (g_switch_seen && g_switch_value != 0)
1661c76c 14660 as_bad (_("-G not supported in this configuration"));
e9670677
MR
14661 g_switch_value = 0;
14662 }
14663
cac012d6
AO
14664 if (mips_abi == NO_ABI)
14665 mips_abi = MIPS_DEFAULT_ABI;
14666
919731af 14667 /* The following code determines the architecture.
22923709
RS
14668 Similar code was added to GCC 3.3 (see override_options() in
14669 config/mips/mips.c). The GAS and GCC code should be kept in sync
14670 as much as possible. */
e9670677 14671
316f5878 14672 if (mips_arch_string != 0)
fef14a42 14673 arch_info = mips_parse_cpu ("-march", mips_arch_string);
e9670677 14674
0b35dfee 14675 if (file_mips_opts.isa != ISA_UNKNOWN)
e9670677 14676 {
0b35dfee 14677 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
fef14a42 14678 ISA level specified by -mipsN, while arch_info->isa contains
316f5878 14679 the -march selection (if any). */
fef14a42 14680 if (arch_info != 0)
e9670677 14681 {
316f5878
RS
14682 /* -march takes precedence over -mipsN, since it is more descriptive.
14683 There's no harm in specifying both as long as the ISA levels
14684 are the same. */
0b35dfee 14685 if (file_mips_opts.isa != arch_info->isa)
1661c76c
RS
14686 as_bad (_("-%s conflicts with the other architecture options,"
14687 " which imply -%s"),
0b35dfee 14688 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
fef14a42 14689 mips_cpu_info_from_isa (arch_info->isa)->name);
e9670677 14690 }
316f5878 14691 else
0b35dfee 14692 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
e9670677
MR
14693 }
14694
fef14a42 14695 if (arch_info == 0)
95bfe26e
MF
14696 {
14697 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14698 gas_assert (arch_info);
14699 }
e9670677 14700
fef14a42 14701 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
20203fb9 14702 as_bad (_("-march=%s is not compatible with the selected ABI"),
fef14a42
TS
14703 arch_info->name);
14704
919731af 14705 file_mips_opts.arch = arch_info->cpu;
14706 file_mips_opts.isa = arch_info->isa;
14707
14708 /* Set up initial mips_opts state. */
14709 mips_opts = file_mips_opts;
14710
14711 /* The register size inference code is now placed in
14712 file_mips_check_options. */
fef14a42 14713
0b35dfee 14714 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14715 processor. */
fef14a42
TS
14716 if (mips_tune_string != 0)
14717 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
e9670677 14718
fef14a42
TS
14719 if (tune_info == 0)
14720 mips_set_tune (arch_info);
14721 else
14722 mips_set_tune (tune_info);
e9670677 14723
ecb4347a 14724 if (mips_flag_mdebug < 0)
e8044f35 14725 mips_flag_mdebug = 0;
e9670677
MR
14726}
14727\f
14728void
17a2f251 14729mips_init_after_args (void)
252b5132
RH
14730{
14731 /* initialize opcodes */
14732 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
beae10d5 14733 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
252b5132
RH
14734}
14735
14736long
17a2f251 14737md_pcrel_from (fixS *fixP)
252b5132 14738{
a7ebbfdf
TS
14739 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14740 switch (fixP->fx_r_type)
14741 {
df58fc94
RS
14742 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14743 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14744 /* Return the address of the delay slot. */
14745 return addr + 2;
14746
14747 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14748 case BFD_RELOC_MICROMIPS_JMP:
c9775dde 14749 case BFD_RELOC_MIPS16_16_PCREL_S1:
a7ebbfdf 14750 case BFD_RELOC_16_PCREL_S2:
7361da2c
AB
14751 case BFD_RELOC_MIPS_21_PCREL_S2:
14752 case BFD_RELOC_MIPS_26_PCREL_S2:
a7ebbfdf
TS
14753 case BFD_RELOC_MIPS_JMP:
14754 /* Return the address of the delay slot. */
14755 return addr + 4;
df58fc94 14756
51f6035b
MR
14757 case BFD_RELOC_MIPS_18_PCREL_S3:
14758 /* Return the aligned address of the doubleword containing
14759 the instruction. */
14760 return addr & ~7;
14761
a7ebbfdf
TS
14762 default:
14763 return addr;
14764 }
252b5132
RH
14765}
14766
252b5132
RH
14767/* This is called before the symbol table is processed. In order to
14768 work with gcc when using mips-tfile, we must keep all local labels.
14769 However, in other cases, we want to discard them. If we were
14770 called with -g, but we didn't see any debugging information, it may
14771 mean that gcc is smuggling debugging information through to
14772 mips-tfile, in which case we must generate all local labels. */
14773
14774void
17a2f251 14775mips_frob_file_before_adjust (void)
252b5132
RH
14776{
14777#ifndef NO_ECOFF_DEBUGGING
14778 if (ECOFF_DEBUGGING
14779 && mips_debug != 0
14780 && ! ecoff_debugging_seen)
14781 flag_keep_locals = 1;
14782#endif
14783}
14784
3b91255e 14785/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
55cf6793 14786 the corresponding LO16 reloc. This is called before md_apply_fix and
3b91255e
RS
14787 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14788 relocation operators.
14789
14790 For our purposes, a %lo() expression matches a %got() or %hi()
14791 expression if:
14792
14793 (a) it refers to the same symbol; and
14794 (b) the offset applied in the %lo() expression is no lower than
14795 the offset applied in the %got() or %hi().
14796
14797 (b) allows us to cope with code like:
14798
14799 lui $4,%hi(foo)
14800 lh $4,%lo(foo+2)($4)
14801
14802 ...which is legal on RELA targets, and has a well-defined behaviour
14803 if the user knows that adding 2 to "foo" will not induce a carry to
14804 the high 16 bits.
14805
14806 When several %lo()s match a particular %got() or %hi(), we use the
14807 following rules to distinguish them:
14808
14809 (1) %lo()s with smaller offsets are a better match than %lo()s with
14810 higher offsets.
14811
14812 (2) %lo()s with no matching %got() or %hi() are better than those
14813 that already have a matching %got() or %hi().
14814
14815 (3) later %lo()s are better than earlier %lo()s.
14816
14817 These rules are applied in order.
14818
14819 (1) means, among other things, that %lo()s with identical offsets are
14820 chosen if they exist.
14821
14822 (2) means that we won't associate several high-part relocations with
14823 the same low-part relocation unless there's no alternative. Having
14824 several high parts for the same low part is a GNU extension; this rule
14825 allows careful users to avoid it.
14826
14827 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14828 with the last high-part relocation being at the front of the list.
14829 It therefore makes sense to choose the last matching low-part
14830 relocation, all other things being equal. It's also easier
14831 to code that way. */
252b5132
RH
14832
14833void
17a2f251 14834mips_frob_file (void)
252b5132
RH
14835{
14836 struct mips_hi_fixup *l;
35903be0 14837 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
252b5132
RH
14838
14839 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14840 {
14841 segment_info_type *seginfo;
3b91255e
RS
14842 bfd_boolean matched_lo_p;
14843 fixS **hi_pos, **lo_pos, **pos;
252b5132 14844
9c2799c2 14845 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
252b5132 14846
5919d012 14847 /* If a GOT16 relocation turns out to be against a global symbol,
b886a2ab
RS
14848 there isn't supposed to be a matching LO. Ignore %gots against
14849 constants; we'll report an error for those later. */
738e5348 14850 if (got16_reloc_p (l->fixp->fx_r_type)
b886a2ab
RS
14851 && !(l->fixp->fx_addsy
14852 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
5919d012
RS
14853 continue;
14854
14855 /* Check quickly whether the next fixup happens to be a matching %lo. */
14856 if (fixup_has_matching_lo_p (l->fixp))
252b5132
RH
14857 continue;
14858
252b5132 14859 seginfo = seg_info (l->seg);
252b5132 14860
3b91255e
RS
14861 /* Set HI_POS to the position of this relocation in the chain.
14862 Set LO_POS to the position of the chosen low-part relocation.
14863 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14864 relocation that matches an immediately-preceding high-part
14865 relocation. */
14866 hi_pos = NULL;
14867 lo_pos = NULL;
14868 matched_lo_p = FALSE;
738e5348 14869 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
35903be0 14870
3b91255e
RS
14871 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14872 {
14873 if (*pos == l->fixp)
14874 hi_pos = pos;
14875
35903be0 14876 if ((*pos)->fx_r_type == looking_for_rtype
30cfc97a 14877 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
3b91255e
RS
14878 && (*pos)->fx_offset >= l->fixp->fx_offset
14879 && (lo_pos == NULL
14880 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14881 || (!matched_lo_p
14882 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14883 lo_pos = pos;
14884
14885 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14886 && fixup_has_matching_lo_p (*pos));
14887 }
14888
14889 /* If we found a match, remove the high-part relocation from its
14890 current position and insert it before the low-part relocation.
14891 Make the offsets match so that fixup_has_matching_lo_p()
14892 will return true.
14893
14894 We don't warn about unmatched high-part relocations since some
14895 versions of gcc have been known to emit dead "lui ...%hi(...)"
14896 instructions. */
14897 if (lo_pos != NULL)
14898 {
14899 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14900 if (l->fixp->fx_next != *lo_pos)
252b5132 14901 {
3b91255e
RS
14902 *hi_pos = l->fixp->fx_next;
14903 l->fixp->fx_next = *lo_pos;
14904 *lo_pos = l->fixp;
252b5132 14905 }
252b5132
RH
14906 }
14907 }
14908}
14909
252b5132 14910int
17a2f251 14911mips_force_relocation (fixS *fixp)
252b5132 14912{
ae6063d4 14913 if (generic_force_reloc (fixp))
252b5132
RH
14914 return 1;
14915
df58fc94
RS
14916 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14917 so that the linker relaxation can update targets. */
14918 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14919 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14920 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14921 return 1;
14922
5caa2b07
MR
14923 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
14924 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
14925 microMIPS symbols so that we can do cross-mode branch diagnostics
14926 and BAL to JALX conversion by the linker. */
14927 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
9d862524
MR
14928 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14929 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2)
14930 && fixp->fx_addsy
14931 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy)))
14932 return 1;
14933
7361da2c 14934 /* We want all PC-relative relocations to be kept for R6 relaxation. */
912815f0 14935 if (ISA_IS_R6 (file_mips_opts.isa)
7361da2c
AB
14936 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14937 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14938 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
14939 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
14940 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
14941 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
14942 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
14943 return 1;
14944
3e722fb5 14945 return 0;
252b5132
RH
14946}
14947
b416ba9b
MR
14948/* Implement TC_FORCE_RELOCATION_ABS. */
14949
14950bfd_boolean
14951mips_force_relocation_abs (fixS *fixp)
14952{
14953 if (generic_force_reloc (fixp))
14954 return TRUE;
14955
14956 /* These relocations do not have enough bits in the in-place addend
14957 to hold an arbitrary absolute section's offset. */
14958 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type))
14959 return TRUE;
14960
14961 return FALSE;
14962}
14963
b886a2ab
RS
14964/* Read the instruction associated with RELOC from BUF. */
14965
14966static unsigned int
14967read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14968{
14969 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14970 return read_compressed_insn (buf, 4);
14971 else
14972 return read_insn (buf);
14973}
14974
14975/* Write instruction INSN to BUF, given that it has been relocated
14976 by RELOC. */
14977
14978static void
14979write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14980 unsigned long insn)
14981{
14982 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14983 write_compressed_insn (buf, insn, 4);
14984 else
14985 write_insn (buf, insn);
14986}
14987
9d862524
MR
14988/* Return TRUE if the instruction pointed to by FIXP is an invalid jump
14989 to a symbol in another ISA mode, which cannot be converted to JALX. */
14990
14991static bfd_boolean
14992fix_bad_cross_mode_jump_p (fixS *fixP)
14993{
14994 unsigned long opcode;
14995 int other;
14996 char *buf;
14997
14998 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
14999 return FALSE;
15000
15001 other = S_GET_OTHER (fixP->fx_addsy);
15002 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15003 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15004 switch (fixP->fx_r_type)
15005 {
15006 case BFD_RELOC_MIPS_JMP:
15007 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other);
15008 case BFD_RELOC_MICROMIPS_JMP:
15009 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other);
15010 default:
15011 return FALSE;
15012 }
15013}
15014
15015/* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15016 jump to a symbol in the same ISA mode. */
15017
15018static bfd_boolean
15019fix_bad_same_mode_jalx_p (fixS *fixP)
15020{
15021 unsigned long opcode;
15022 int other;
15023 char *buf;
15024
15025 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15026 return FALSE;
15027
15028 other = S_GET_OTHER (fixP->fx_addsy);
15029 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15030 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15031 switch (fixP->fx_r_type)
15032 {
15033 case BFD_RELOC_MIPS_JMP:
15034 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other);
15035 case BFD_RELOC_MIPS16_JMP:
15036 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other);
15037 case BFD_RELOC_MICROMIPS_JMP:
15038 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other);
15039 default:
15040 return FALSE;
15041 }
15042}
15043
15044/* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15045 to a symbol whose value plus addend is not aligned according to the
15046 ultimate (after linker relaxation) jump instruction's immediate field
15047 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15048 regular MIPS code, to (1 << 2). */
15049
15050static bfd_boolean
15051fix_bad_misaligned_jump_p (fixS *fixP, int shift)
15052{
15053 bfd_boolean micro_to_mips_p;
15054 valueT val;
15055 int other;
15056
15057 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15058 return FALSE;
15059
15060 other = S_GET_OTHER (fixP->fx_addsy);
15061 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other);
15062 val += fixP->fx_offset;
15063 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15064 && !ELF_ST_IS_MICROMIPS (other));
15065 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1))
15066 != ELF_ST_IS_COMPRESSED (other));
15067}
15068
15069/* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15070 to a symbol whose annotation indicates another ISA mode. For absolute
a6ebf616
MR
15071 symbols check the ISA bit instead.
15072
15073 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15074 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15075 MIPS symbols and associated with BAL instructions as these instructions
15076 may be be converted to JALX by the linker. */
9d862524
MR
15077
15078static bfd_boolean
15079fix_bad_cross_mode_branch_p (fixS *fixP)
15080{
15081 bfd_boolean absolute_p;
15082 unsigned long opcode;
15083 asection *symsec;
15084 valueT val;
15085 int other;
15086 char *buf;
15087
15088 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15089 return FALSE;
15090
15091 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15092 absolute_p = bfd_is_abs_section (symsec);
15093
15094 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
15095 other = S_GET_OTHER (fixP->fx_addsy);
15096
15097 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15098 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16;
15099 switch (fixP->fx_r_type)
15100 {
15101 case BFD_RELOC_16_PCREL_S2:
a6ebf616
MR
15102 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other))
15103 && opcode != 0x0411);
15104 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15105 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other))
15106 && opcode != 0x4060);
9d862524
MR
15107 case BFD_RELOC_MIPS_21_PCREL_S2:
15108 case BFD_RELOC_MIPS_26_PCREL_S2:
15109 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other);
15110 case BFD_RELOC_MIPS16_16_PCREL_S1:
15111 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other);
15112 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15113 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
9d862524
MR
15114 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other);
15115 default:
15116 abort ();
15117 }
15118}
15119
15120/* Return TRUE if the symbol plus addend associated with a regular MIPS
15121 branch instruction pointed to by FIXP is not aligned according to the
15122 branch instruction's immediate field requirement. We need the addend
15123 to preserve the ISA bit and also the sum must not have bit 2 set. We
15124 must explicitly OR in the ISA bit from symbol annotation as the bit
15125 won't be set in the symbol's value then. */
15126
15127static bfd_boolean
15128fix_bad_misaligned_branch_p (fixS *fixP)
15129{
15130 bfd_boolean absolute_p;
15131 asection *symsec;
15132 valueT isa_bit;
15133 valueT val;
15134 valueT off;
15135 int other;
15136
15137 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15138 return FALSE;
15139
15140 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15141 absolute_p = bfd_is_abs_section (symsec);
15142
15143 val = S_GET_VALUE (fixP->fx_addsy);
15144 other = S_GET_OTHER (fixP->fx_addsy);
15145 off = fixP->fx_offset;
15146
15147 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other);
15148 val |= ELF_ST_IS_COMPRESSED (other);
15149 val += off;
15150 return (val & 0x3) != isa_bit;
15151}
15152
15153/* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15154 and its calculated value VAL. */
15155
15156static void
15157fix_validate_branch (fixS *fixP, valueT val)
15158{
15159 if (fixP->fx_done && (val & 0x3) != 0)
15160 as_bad_where (fixP->fx_file, fixP->fx_line,
15161 _("branch to misaligned address (0x%lx)"),
15162 (long) (val + md_pcrel_from (fixP)));
15163 else if (fix_bad_cross_mode_branch_p (fixP))
15164 as_bad_where (fixP->fx_file, fixP->fx_line,
15165 _("branch to a symbol in another ISA mode"));
15166 else if (fix_bad_misaligned_branch_p (fixP))
15167 as_bad_where (fixP->fx_file, fixP->fx_line,
15168 _("branch to misaligned address (0x%lx)"),
15169 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15170 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0)
15171 as_bad_where (fixP->fx_file, fixP->fx_line,
15172 _("cannot encode misaligned addend "
15173 "in the relocatable field (0x%lx)"),
15174 (long) fixP->fx_offset);
15175}
15176
252b5132
RH
15177/* Apply a fixup to the object file. */
15178
94f592af 15179void
55cf6793 15180md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 15181{
4d68580a 15182 char *buf;
b886a2ab 15183 unsigned long insn;
a7ebbfdf 15184 reloc_howto_type *howto;
252b5132 15185
d56a8dda
RS
15186 if (fixP->fx_pcrel)
15187 switch (fixP->fx_r_type)
15188 {
15189 case BFD_RELOC_16_PCREL_S2:
c9775dde 15190 case BFD_RELOC_MIPS16_16_PCREL_S1:
d56a8dda
RS
15191 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15192 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15193 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15194 case BFD_RELOC_32_PCREL:
7361da2c
AB
15195 case BFD_RELOC_MIPS_21_PCREL_S2:
15196 case BFD_RELOC_MIPS_26_PCREL_S2:
15197 case BFD_RELOC_MIPS_18_PCREL_S3:
15198 case BFD_RELOC_MIPS_19_PCREL_S2:
15199 case BFD_RELOC_HI16_S_PCREL:
15200 case BFD_RELOC_LO16_PCREL:
d56a8dda
RS
15201 break;
15202
15203 case BFD_RELOC_32:
15204 fixP->fx_r_type = BFD_RELOC_32_PCREL;
15205 break;
15206
15207 default:
15208 as_bad_where (fixP->fx_file, fixP->fx_line,
15209 _("PC-relative reference to a different section"));
15210 break;
15211 }
15212
15213 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15214 that have no MIPS ELF equivalent. */
15215 if (fixP->fx_r_type != BFD_RELOC_8)
15216 {
15217 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15218 if (!howto)
15219 return;
15220 }
65551fa4 15221
df58fc94
RS
15222 gas_assert (fixP->fx_size == 2
15223 || fixP->fx_size == 4
d56a8dda 15224 || fixP->fx_r_type == BFD_RELOC_8
90ecf173
MR
15225 || fixP->fx_r_type == BFD_RELOC_16
15226 || fixP->fx_r_type == BFD_RELOC_64
15227 || fixP->fx_r_type == BFD_RELOC_CTOR
15228 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
df58fc94 15229 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
90ecf173
MR
15230 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15231 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
2f0c68f2
CM
15232 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
15233 || fixP->fx_r_type == BFD_RELOC_NONE);
252b5132 15234
4d68580a 15235 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
252b5132 15236
b1dca8ee
RS
15237 /* Don't treat parts of a composite relocation as done. There are two
15238 reasons for this:
15239
15240 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15241 should nevertheless be emitted if the first part is.
15242
15243 (2) In normal usage, composite relocations are never assembly-time
15244 constants. The easiest way of dealing with the pathological
15245 exceptions is to generate a relocation against STN_UNDEF and
15246 leave everything up to the linker. */
3994f87e 15247 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
252b5132
RH
15248 fixP->fx_done = 1;
15249
15250 switch (fixP->fx_r_type)
15251 {
3f98094e
DJ
15252 case BFD_RELOC_MIPS_TLS_GD:
15253 case BFD_RELOC_MIPS_TLS_LDM:
741d6ea8
JM
15254 case BFD_RELOC_MIPS_TLS_DTPREL32:
15255 case BFD_RELOC_MIPS_TLS_DTPREL64:
3f98094e
DJ
15256 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15257 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15258 case BFD_RELOC_MIPS_TLS_GOTTPREL:
d0f13682
CLT
15259 case BFD_RELOC_MIPS_TLS_TPREL32:
15260 case BFD_RELOC_MIPS_TLS_TPREL64:
3f98094e
DJ
15261 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15262 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
df58fc94
RS
15263 case BFD_RELOC_MICROMIPS_TLS_GD:
15264 case BFD_RELOC_MICROMIPS_TLS_LDM:
15265 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15266 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15267 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15268 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15269 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
d0f13682
CLT
15270 case BFD_RELOC_MIPS16_TLS_GD:
15271 case BFD_RELOC_MIPS16_TLS_LDM:
15272 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15273 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15274 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15275 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15276 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
4512dafa
MR
15277 if (fixP->fx_addsy)
15278 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15279 else
15280 as_bad_where (fixP->fx_file, fixP->fx_line,
15281 _("TLS relocation against a constant"));
15282 break;
3f98094e 15283
252b5132 15284 case BFD_RELOC_MIPS_JMP:
9d862524
MR
15285 case BFD_RELOC_MIPS16_JMP:
15286 case BFD_RELOC_MICROMIPS_JMP:
15287 {
15288 int shift;
15289
15290 gas_assert (!fixP->fx_done);
15291
15292 /* Shift is 2, unusually, for microMIPS JALX. */
15293 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15294 && (read_compressed_insn (buf, 4) >> 26) != 0x3c)
15295 shift = 1;
15296 else
15297 shift = 2;
15298
15299 if (fix_bad_cross_mode_jump_p (fixP))
15300 as_bad_where (fixP->fx_file, fixP->fx_line,
15301 _("jump to a symbol in another ISA mode"));
15302 else if (fix_bad_same_mode_jalx_p (fixP))
15303 as_bad_where (fixP->fx_file, fixP->fx_line,
15304 _("JALX to a symbol in the same ISA mode"));
15305 else if (fix_bad_misaligned_jump_p (fixP, shift))
15306 as_bad_where (fixP->fx_file, fixP->fx_line,
15307 _("jump to misaligned address (0x%lx)"),
15308 (long) (S_GET_VALUE (fixP->fx_addsy)
15309 + fixP->fx_offset));
15310 else if (HAVE_IN_PLACE_ADDENDS
15311 && (fixP->fx_offset & ((1 << shift) - 1)) != 0)
15312 as_bad_where (fixP->fx_file, fixP->fx_line,
15313 _("cannot encode misaligned addend "
15314 "in the relocatable field (0x%lx)"),
15315 (long) fixP->fx_offset);
15316 }
15317 /* Fall through. */
15318
e369bcce
TS
15319 case BFD_RELOC_MIPS_SHIFT5:
15320 case BFD_RELOC_MIPS_SHIFT6:
15321 case BFD_RELOC_MIPS_GOT_DISP:
15322 case BFD_RELOC_MIPS_GOT_PAGE:
15323 case BFD_RELOC_MIPS_GOT_OFST:
15324 case BFD_RELOC_MIPS_SUB:
15325 case BFD_RELOC_MIPS_INSERT_A:
15326 case BFD_RELOC_MIPS_INSERT_B:
15327 case BFD_RELOC_MIPS_DELETE:
15328 case BFD_RELOC_MIPS_HIGHEST:
15329 case BFD_RELOC_MIPS_HIGHER:
15330 case BFD_RELOC_MIPS_SCN_DISP:
15331 case BFD_RELOC_MIPS_REL16:
15332 case BFD_RELOC_MIPS_RELGOT:
15333 case BFD_RELOC_MIPS_JALR:
252b5132
RH
15334 case BFD_RELOC_HI16:
15335 case BFD_RELOC_HI16_S:
b886a2ab 15336 case BFD_RELOC_LO16:
cdf6fd85 15337 case BFD_RELOC_GPREL16:
252b5132
RH
15338 case BFD_RELOC_MIPS_LITERAL:
15339 case BFD_RELOC_MIPS_CALL16:
15340 case BFD_RELOC_MIPS_GOT16:
cdf6fd85 15341 case BFD_RELOC_GPREL32:
252b5132
RH
15342 case BFD_RELOC_MIPS_GOT_HI16:
15343 case BFD_RELOC_MIPS_GOT_LO16:
15344 case BFD_RELOC_MIPS_CALL_HI16:
15345 case BFD_RELOC_MIPS_CALL_LO16:
41947d9e
MR
15346 case BFD_RELOC_HI16_S_PCREL:
15347 case BFD_RELOC_LO16_PCREL:
252b5132 15348 case BFD_RELOC_MIPS16_GPREL:
738e5348
RS
15349 case BFD_RELOC_MIPS16_GOT16:
15350 case BFD_RELOC_MIPS16_CALL16:
d6f16593
MR
15351 case BFD_RELOC_MIPS16_HI16:
15352 case BFD_RELOC_MIPS16_HI16_S:
b886a2ab 15353 case BFD_RELOC_MIPS16_LO16:
df58fc94
RS
15354 case BFD_RELOC_MICROMIPS_GOT_DISP:
15355 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15356 case BFD_RELOC_MICROMIPS_GOT_OFST:
15357 case BFD_RELOC_MICROMIPS_SUB:
15358 case BFD_RELOC_MICROMIPS_HIGHEST:
15359 case BFD_RELOC_MICROMIPS_HIGHER:
15360 case BFD_RELOC_MICROMIPS_SCN_DISP:
15361 case BFD_RELOC_MICROMIPS_JALR:
15362 case BFD_RELOC_MICROMIPS_HI16:
15363 case BFD_RELOC_MICROMIPS_HI16_S:
b886a2ab 15364 case BFD_RELOC_MICROMIPS_LO16:
df58fc94
RS
15365 case BFD_RELOC_MICROMIPS_GPREL16:
15366 case BFD_RELOC_MICROMIPS_LITERAL:
15367 case BFD_RELOC_MICROMIPS_CALL16:
15368 case BFD_RELOC_MICROMIPS_GOT16:
15369 case BFD_RELOC_MICROMIPS_GOT_HI16:
15370 case BFD_RELOC_MICROMIPS_GOT_LO16:
15371 case BFD_RELOC_MICROMIPS_CALL_HI16:
15372 case BFD_RELOC_MICROMIPS_CALL_LO16:
067ec077 15373 case BFD_RELOC_MIPS_EH:
b886a2ab
RS
15374 if (fixP->fx_done)
15375 {
15376 offsetT value;
15377
15378 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15379 {
15380 insn = read_reloc_insn (buf, fixP->fx_r_type);
15381 if (mips16_reloc_p (fixP->fx_r_type))
15382 insn |= mips16_immed_extend (value, 16);
15383 else
15384 insn |= (value & 0xffff);
15385 write_reloc_insn (buf, fixP->fx_r_type, insn);
15386 }
15387 else
15388 as_bad_where (fixP->fx_file, fixP->fx_line,
1661c76c 15389 _("unsupported constant in relocation"));
b886a2ab 15390 }
252b5132
RH
15391 break;
15392
252b5132
RH
15393 case BFD_RELOC_64:
15394 /* This is handled like BFD_RELOC_32, but we output a sign
15395 extended value if we are only 32 bits. */
3e722fb5 15396 if (fixP->fx_done)
252b5132
RH
15397 {
15398 if (8 <= sizeof (valueT))
4d68580a 15399 md_number_to_chars (buf, *valP, 8);
252b5132
RH
15400 else
15401 {
a7ebbfdf 15402 valueT hiv;
252b5132 15403
a7ebbfdf 15404 if ((*valP & 0x80000000) != 0)
252b5132
RH
15405 hiv = 0xffffffff;
15406 else
15407 hiv = 0;
4d68580a
RS
15408 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15409 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
252b5132
RH
15410 }
15411 }
15412 break;
15413
056350c6 15414 case BFD_RELOC_RVA:
252b5132 15415 case BFD_RELOC_32:
b47468a6 15416 case BFD_RELOC_32_PCREL:
252b5132 15417 case BFD_RELOC_16:
d56a8dda 15418 case BFD_RELOC_8:
252b5132 15419 /* If we are deleting this reloc entry, we must fill in the
54f4ddb3
TS
15420 value now. This can happen if we have a .word which is not
15421 resolved when it appears but is later defined. */
252b5132 15422 if (fixP->fx_done)
4d68580a 15423 md_number_to_chars (buf, *valP, fixP->fx_size);
252b5132
RH
15424 break;
15425
7361da2c 15426 case BFD_RELOC_MIPS_21_PCREL_S2:
9d862524 15427 fix_validate_branch (fixP, *valP);
41947d9e
MR
15428 if (!fixP->fx_done)
15429 break;
15430
15431 if (*valP + 0x400000 <= 0x7fffff)
15432 {
15433 insn = read_insn (buf);
15434 insn |= (*valP >> 2) & 0x1fffff;
15435 write_insn (buf, insn);
15436 }
15437 else
15438 as_bad_where (fixP->fx_file, fixP->fx_line,
15439 _("branch out of range"));
15440 break;
15441
7361da2c 15442 case BFD_RELOC_MIPS_26_PCREL_S2:
9d862524 15443 fix_validate_branch (fixP, *valP);
41947d9e
MR
15444 if (!fixP->fx_done)
15445 break;
7361da2c 15446
41947d9e
MR
15447 if (*valP + 0x8000000 <= 0xfffffff)
15448 {
15449 insn = read_insn (buf);
15450 insn |= (*valP >> 2) & 0x3ffffff;
15451 write_insn (buf, insn);
15452 }
15453 else
15454 as_bad_where (fixP->fx_file, fixP->fx_line,
15455 _("branch out of range"));
7361da2c
AB
15456 break;
15457
15458 case BFD_RELOC_MIPS_18_PCREL_S3:
717ba204 15459 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
7361da2c 15460 as_bad_where (fixP->fx_file, fixP->fx_line,
0866e94c
MF
15461 _("PC-relative access using misaligned symbol (%lx)"),
15462 (long) S_GET_VALUE (fixP->fx_addsy));
15463 if ((fixP->fx_offset & 0x7) != 0)
15464 as_bad_where (fixP->fx_file, fixP->fx_line,
15465 _("PC-relative access using misaligned offset (%lx)"),
15466 (long) fixP->fx_offset);
41947d9e
MR
15467 if (!fixP->fx_done)
15468 break;
7361da2c 15469
41947d9e
MR
15470 if (*valP + 0x100000 <= 0x1fffff)
15471 {
15472 insn = read_insn (buf);
15473 insn |= (*valP >> 3) & 0x3ffff;
15474 write_insn (buf, insn);
15475 }
15476 else
15477 as_bad_where (fixP->fx_file, fixP->fx_line,
15478 _("PC-relative access out of range"));
7361da2c
AB
15479 break;
15480
15481 case BFD_RELOC_MIPS_19_PCREL_S2:
15482 if ((*valP & 0x3) != 0)
15483 as_bad_where (fixP->fx_file, fixP->fx_line,
15484 _("PC-relative access to misaligned address (%lx)"),
717ba204 15485 (long) *valP);
41947d9e
MR
15486 if (!fixP->fx_done)
15487 break;
7361da2c 15488
41947d9e
MR
15489 if (*valP + 0x100000 <= 0x1fffff)
15490 {
15491 insn = read_insn (buf);
15492 insn |= (*valP >> 2) & 0x7ffff;
15493 write_insn (buf, insn);
15494 }
15495 else
15496 as_bad_where (fixP->fx_file, fixP->fx_line,
15497 _("PC-relative access out of range"));
7361da2c
AB
15498 break;
15499
252b5132 15500 case BFD_RELOC_16_PCREL_S2:
9d862524 15501 fix_validate_branch (fixP, *valP);
cb56d3d3 15502
54f4ddb3
TS
15503 /* We need to save the bits in the instruction since fixup_segment()
15504 might be deleting the relocation entry (i.e., a branch within
15505 the current segment). */
a7ebbfdf 15506 if (! fixP->fx_done)
bb2d6cd7 15507 break;
252b5132 15508
54f4ddb3 15509 /* Update old instruction data. */
4d68580a 15510 insn = read_insn (buf);
252b5132 15511
a7ebbfdf
TS
15512 if (*valP + 0x20000 <= 0x3ffff)
15513 {
15514 insn |= (*valP >> 2) & 0xffff;
4d68580a 15515 write_insn (buf, insn);
a7ebbfdf
TS
15516 }
15517 else if (mips_pic == NO_PIC
15518 && fixP->fx_done
15519 && fixP->fx_frag->fr_address >= text_section->vma
15520 && (fixP->fx_frag->fr_address
587aac4e 15521 < text_section->vma + bfd_get_section_size (text_section))
a7ebbfdf
TS
15522 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15523 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15524 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
252b5132
RH
15525 {
15526 /* The branch offset is too large. If this is an
15527 unconditional branch, and we are not generating PIC code,
15528 we can convert it to an absolute jump instruction. */
a7ebbfdf
TS
15529 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15530 insn = 0x0c000000; /* jal */
252b5132 15531 else
a7ebbfdf
TS
15532 insn = 0x08000000; /* j */
15533 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15534 fixP->fx_done = 0;
15535 fixP->fx_addsy = section_symbol (text_section);
15536 *valP += md_pcrel_from (fixP);
4d68580a 15537 write_insn (buf, insn);
a7ebbfdf
TS
15538 }
15539 else
15540 {
15541 /* If we got here, we have branch-relaxation disabled,
15542 and there's nothing we can do to fix this instruction
15543 without turning it into a longer sequence. */
15544 as_bad_where (fixP->fx_file, fixP->fx_line,
1661c76c 15545 _("branch out of range"));
252b5132 15546 }
252b5132
RH
15547 break;
15548
c9775dde 15549 case BFD_RELOC_MIPS16_16_PCREL_S1:
df58fc94
RS
15550 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15551 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15552 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
96e9ba5f 15553 gas_assert (!fixP->fx_done);
9d862524
MR
15554 if (fix_bad_cross_mode_branch_p (fixP))
15555 as_bad_where (fixP->fx_file, fixP->fx_line,
15556 _("branch to a symbol in another ISA mode"));
15557 else if (fixP->fx_addsy
15558 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
15559 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy))
15560 && (fixP->fx_offset & 0x1) != 0)
15561 as_bad_where (fixP->fx_file, fixP->fx_line,
15562 _("branch to misaligned address (0x%lx)"),
15563 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15564 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0)
15565 as_bad_where (fixP->fx_file, fixP->fx_line,
15566 _("cannot encode misaligned addend "
15567 "in the relocatable field (0x%lx)"),
15568 (long) fixP->fx_offset);
df58fc94
RS
15569 break;
15570
252b5132
RH
15571 case BFD_RELOC_VTABLE_INHERIT:
15572 fixP->fx_done = 0;
15573 if (fixP->fx_addsy
15574 && !S_IS_DEFINED (fixP->fx_addsy)
15575 && !S_IS_WEAK (fixP->fx_addsy))
15576 S_SET_WEAK (fixP->fx_addsy);
15577 break;
15578
2f0c68f2 15579 case BFD_RELOC_NONE:
252b5132
RH
15580 case BFD_RELOC_VTABLE_ENTRY:
15581 fixP->fx_done = 0;
15582 break;
15583
15584 default:
b37df7c4 15585 abort ();
252b5132 15586 }
a7ebbfdf
TS
15587
15588 /* Remember value for tc_gen_reloc. */
15589 fixP->fx_addnumber = *valP;
252b5132
RH
15590}
15591
252b5132 15592static symbolS *
17a2f251 15593get_symbol (void)
252b5132
RH
15594{
15595 int c;
15596 char *name;
15597 symbolS *p;
15598
d02603dc 15599 c = get_symbol_name (&name);
252b5132 15600 p = (symbolS *) symbol_find_or_make (name);
d02603dc 15601 (void) restore_line_pointer (c);
252b5132
RH
15602 return p;
15603}
15604
742a56fe
RS
15605/* Align the current frag to a given power of two. If a particular
15606 fill byte should be used, FILL points to an integer that contains
15607 that byte, otherwise FILL is null.
15608
462427c4
RS
15609 This function used to have the comment:
15610
15611 The MIPS assembler also automatically adjusts any preceding label.
15612
15613 The implementation therefore applied the adjustment to a maximum of
15614 one label. However, other label adjustments are applied to batches
15615 of labels, and adjusting just one caused problems when new labels
15616 were added for the sake of debugging or unwind information.
15617 We therefore adjust all preceding labels (given as LABELS) instead. */
252b5132
RH
15618
15619static void
462427c4 15620mips_align (int to, int *fill, struct insn_label_list *labels)
252b5132 15621{
7d10b47d 15622 mips_emit_delays ();
df58fc94 15623 mips_record_compressed_mode ();
742a56fe
RS
15624 if (fill == NULL && subseg_text_p (now_seg))
15625 frag_align_code (to, 0);
15626 else
15627 frag_align (to, fill ? *fill : 0, 0);
252b5132 15628 record_alignment (now_seg, to);
462427c4 15629 mips_move_labels (labels, FALSE);
252b5132
RH
15630}
15631
15632/* Align to a given power of two. .align 0 turns off the automatic
15633 alignment used by the data creating pseudo-ops. */
15634
15635static void
17a2f251 15636s_align (int x ATTRIBUTE_UNUSED)
252b5132 15637{
742a56fe 15638 int temp, fill_value, *fill_ptr;
49954fb4 15639 long max_alignment = 28;
252b5132 15640
54f4ddb3 15641 /* o Note that the assembler pulls down any immediately preceding label
252b5132 15642 to the aligned address.
54f4ddb3 15643 o It's not documented but auto alignment is reinstated by
252b5132 15644 a .align pseudo instruction.
54f4ddb3 15645 o Note also that after auto alignment is turned off the mips assembler
252b5132 15646 issues an error on attempt to assemble an improperly aligned data item.
54f4ddb3 15647 We don't. */
252b5132
RH
15648
15649 temp = get_absolute_expression ();
15650 if (temp > max_alignment)
1661c76c 15651 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
252b5132
RH
15652 else if (temp < 0)
15653 {
1661c76c 15654 as_warn (_("alignment negative, 0 assumed"));
252b5132
RH
15655 temp = 0;
15656 }
15657 if (*input_line_pointer == ',')
15658 {
f9419b05 15659 ++input_line_pointer;
742a56fe
RS
15660 fill_value = get_absolute_expression ();
15661 fill_ptr = &fill_value;
252b5132
RH
15662 }
15663 else
742a56fe 15664 fill_ptr = 0;
252b5132
RH
15665 if (temp)
15666 {
a8dbcb85
TS
15667 segment_info_type *si = seg_info (now_seg);
15668 struct insn_label_list *l = si->label_list;
54f4ddb3 15669 /* Auto alignment should be switched on by next section change. */
252b5132 15670 auto_align = 1;
462427c4 15671 mips_align (temp, fill_ptr, l);
252b5132
RH
15672 }
15673 else
15674 {
15675 auto_align = 0;
15676 }
15677
15678 demand_empty_rest_of_line ();
15679}
15680
252b5132 15681static void
17a2f251 15682s_change_sec (int sec)
252b5132
RH
15683{
15684 segT seg;
15685
252b5132
RH
15686 /* The ELF backend needs to know that we are changing sections, so
15687 that .previous works correctly. We could do something like check
b6ff326e 15688 for an obj_section_change_hook macro, but that might be confusing
252b5132
RH
15689 as it would not be appropriate to use it in the section changing
15690 functions in read.c, since obj-elf.c intercepts those. FIXME:
15691 This should be cleaner, somehow. */
f3ded42a 15692 obj_elf_section_change_hook ();
252b5132 15693
7d10b47d 15694 mips_emit_delays ();
6a32d874 15695
252b5132
RH
15696 switch (sec)
15697 {
15698 case 't':
15699 s_text (0);
15700 break;
15701 case 'd':
15702 s_data (0);
15703 break;
15704 case 'b':
15705 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15706 demand_empty_rest_of_line ();
15707 break;
15708
15709 case 'r':
4d0d148d
TS
15710 seg = subseg_new (RDATA_SECTION_NAME,
15711 (subsegT) get_absolute_expression ());
f3ded42a
RS
15712 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15713 | SEC_READONLY | SEC_RELOC
15714 | SEC_DATA));
15715 if (strncmp (TARGET_OS, "elf", 3) != 0)
15716 record_alignment (seg, 4);
4d0d148d 15717 demand_empty_rest_of_line ();
252b5132
RH
15718 break;
15719
15720 case 's':
4d0d148d 15721 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
f3ded42a
RS
15722 bfd_set_section_flags (stdoutput, seg,
15723 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15724 if (strncmp (TARGET_OS, "elf", 3) != 0)
15725 record_alignment (seg, 4);
4d0d148d
TS
15726 demand_empty_rest_of_line ();
15727 break;
998b3c36
MR
15728
15729 case 'B':
15730 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
f3ded42a
RS
15731 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15732 if (strncmp (TARGET_OS, "elf", 3) != 0)
15733 record_alignment (seg, 4);
998b3c36
MR
15734 demand_empty_rest_of_line ();
15735 break;
252b5132
RH
15736 }
15737
15738 auto_align = 1;
15739}
b34976b6 15740
cca86cc8 15741void
17a2f251 15742s_change_section (int ignore ATTRIBUTE_UNUSED)
cca86cc8 15743{
d02603dc 15744 char *saved_ilp;
cca86cc8 15745 char *section_name;
d02603dc 15746 char c, endc;
684022ea 15747 char next_c = 0;
cca86cc8
SC
15748 int section_type;
15749 int section_flag;
15750 int section_entry_size;
15751 int section_alignment;
b34976b6 15752
d02603dc
NC
15753 saved_ilp = input_line_pointer;
15754 endc = get_symbol_name (&section_name);
15755 c = (endc == '"' ? input_line_pointer[1] : endc);
a816d1ed 15756 if (c)
d02603dc 15757 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
cca86cc8 15758
4cf0dd0d
TS
15759 /* Do we have .section Name<,"flags">? */
15760 if (c != ',' || (c == ',' && next_c == '"'))
cca86cc8 15761 {
d02603dc
NC
15762 /* Just after name is now '\0'. */
15763 (void) restore_line_pointer (endc);
15764 input_line_pointer = saved_ilp;
cca86cc8
SC
15765 obj_elf_section (ignore);
15766 return;
15767 }
d02603dc
NC
15768
15769 section_name = xstrdup (section_name);
15770 c = restore_line_pointer (endc);
15771
cca86cc8
SC
15772 input_line_pointer++;
15773
15774 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15775 if (c == ',')
15776 section_type = get_absolute_expression ();
15777 else
15778 section_type = 0;
d02603dc 15779
cca86cc8
SC
15780 if (*input_line_pointer++ == ',')
15781 section_flag = get_absolute_expression ();
15782 else
15783 section_flag = 0;
d02603dc 15784
cca86cc8
SC
15785 if (*input_line_pointer++ == ',')
15786 section_entry_size = get_absolute_expression ();
15787 else
15788 section_entry_size = 0;
d02603dc 15789
cca86cc8
SC
15790 if (*input_line_pointer++ == ',')
15791 section_alignment = get_absolute_expression ();
15792 else
15793 section_alignment = 0;
d02603dc 15794
87975d2a
AM
15795 /* FIXME: really ignore? */
15796 (void) section_alignment;
cca86cc8 15797
8ab8a5c8
RS
15798 /* When using the generic form of .section (as implemented by obj-elf.c),
15799 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15800 traditionally had to fall back on the more common @progbits instead.
15801
15802 There's nothing really harmful in this, since bfd will correct
15803 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
708587a4 15804 means that, for backwards compatibility, the special_section entries
8ab8a5c8
RS
15805 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15806
15807 Even so, we shouldn't force users of the MIPS .section syntax to
15808 incorrectly label the sections as SHT_PROGBITS. The best compromise
15809 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15810 generic type-checking code. */
15811 if (section_type == SHT_MIPS_DWARF)
15812 section_type = SHT_PROGBITS;
15813
cca86cc8
SC
15814 obj_elf_change_section (section_name, section_type, section_flag,
15815 section_entry_size, 0, 0, 0);
a816d1ed
AO
15816
15817 if (now_seg->name != section_name)
15818 free (section_name);
cca86cc8 15819}
252b5132
RH
15820
15821void
17a2f251 15822mips_enable_auto_align (void)
252b5132
RH
15823{
15824 auto_align = 1;
15825}
15826
15827static void
17a2f251 15828s_cons (int log_size)
252b5132 15829{
a8dbcb85
TS
15830 segment_info_type *si = seg_info (now_seg);
15831 struct insn_label_list *l = si->label_list;
252b5132 15832
7d10b47d 15833 mips_emit_delays ();
252b5132 15834 if (log_size > 0 && auto_align)
462427c4 15835 mips_align (log_size, 0, l);
252b5132 15836 cons (1 << log_size);
a1facbec 15837 mips_clear_insn_labels ();
252b5132
RH
15838}
15839
15840static void
17a2f251 15841s_float_cons (int type)
252b5132 15842{
a8dbcb85
TS
15843 segment_info_type *si = seg_info (now_seg);
15844 struct insn_label_list *l = si->label_list;
252b5132 15845
7d10b47d 15846 mips_emit_delays ();
252b5132
RH
15847
15848 if (auto_align)
49309057
ILT
15849 {
15850 if (type == 'd')
462427c4 15851 mips_align (3, 0, l);
49309057 15852 else
462427c4 15853 mips_align (2, 0, l);
49309057 15854 }
252b5132 15855
252b5132 15856 float_cons (type);
a1facbec 15857 mips_clear_insn_labels ();
252b5132
RH
15858}
15859
15860/* Handle .globl. We need to override it because on Irix 5 you are
15861 permitted to say
15862 .globl foo .text
15863 where foo is an undefined symbol, to mean that foo should be
15864 considered to be the address of a function. */
15865
15866static void
17a2f251 15867s_mips_globl (int x ATTRIBUTE_UNUSED)
252b5132
RH
15868{
15869 char *name;
15870 int c;
15871 symbolS *symbolP;
15872 flagword flag;
15873
8a06b769 15874 do
252b5132 15875 {
d02603dc 15876 c = get_symbol_name (&name);
8a06b769
TS
15877 symbolP = symbol_find_or_make (name);
15878 S_SET_EXTERNAL (symbolP);
15879
252b5132 15880 *input_line_pointer = c;
d02603dc 15881 SKIP_WHITESPACE_AFTER_NAME ();
252b5132 15882
8a06b769
TS
15883 /* On Irix 5, every global symbol that is not explicitly labelled as
15884 being a function is apparently labelled as being an object. */
15885 flag = BSF_OBJECT;
252b5132 15886
8a06b769
TS
15887 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15888 && (*input_line_pointer != ','))
15889 {
15890 char *secname;
15891 asection *sec;
15892
d02603dc 15893 c = get_symbol_name (&secname);
8a06b769
TS
15894 sec = bfd_get_section_by_name (stdoutput, secname);
15895 if (sec == NULL)
15896 as_bad (_("%s: no such section"), secname);
d02603dc 15897 (void) restore_line_pointer (c);
8a06b769
TS
15898
15899 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15900 flag = BSF_FUNCTION;
15901 }
15902
15903 symbol_get_bfdsym (symbolP)->flags |= flag;
15904
15905 c = *input_line_pointer;
15906 if (c == ',')
15907 {
15908 input_line_pointer++;
15909 SKIP_WHITESPACE ();
15910 if (is_end_of_line[(unsigned char) *input_line_pointer])
15911 c = '\n';
15912 }
15913 }
15914 while (c == ',');
252b5132 15915
252b5132
RH
15916 demand_empty_rest_of_line ();
15917}
15918
15919static void
17a2f251 15920s_option (int x ATTRIBUTE_UNUSED)
252b5132
RH
15921{
15922 char *opt;
15923 char c;
15924
d02603dc 15925 c = get_symbol_name (&opt);
252b5132
RH
15926
15927 if (*opt == 'O')
15928 {
15929 /* FIXME: What does this mean? */
15930 }
41a1578e 15931 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
252b5132
RH
15932 {
15933 int i;
15934
15935 i = atoi (opt + 3);
668c5ebc
MR
15936 if (i != 0 && i != 2)
15937 as_bad (_(".option pic%d not supported"), i);
15938 else if (mips_pic == VXWORKS_PIC)
15939 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
15940 else if (i == 0)
252b5132
RH
15941 mips_pic = NO_PIC;
15942 else if (i == 2)
143d77c5 15943 {
8b828383 15944 mips_pic = SVR4_PIC;
143d77c5
EC
15945 mips_abicalls = TRUE;
15946 }
252b5132 15947
4d0d148d 15948 if (mips_pic == SVR4_PIC)
252b5132
RH
15949 {
15950 if (g_switch_seen && g_switch_value != 0)
15951 as_warn (_("-G may not be used with SVR4 PIC code"));
15952 g_switch_value = 0;
15953 bfd_set_gp_size (stdoutput, 0);
15954 }
15955 }
15956 else
1661c76c 15957 as_warn (_("unrecognized option \"%s\""), opt);
252b5132 15958
d02603dc 15959 (void) restore_line_pointer (c);
252b5132
RH
15960 demand_empty_rest_of_line ();
15961}
15962
15963/* This structure is used to hold a stack of .set values. */
15964
e972090a
NC
15965struct mips_option_stack
15966{
252b5132
RH
15967 struct mips_option_stack *next;
15968 struct mips_set_options options;
15969};
15970
15971static struct mips_option_stack *mips_opts_stack;
15972
22522f88
MR
15973/* Return status for .set/.module option handling. */
15974
15975enum code_option_type
15976{
15977 /* Unrecognized option. */
15978 OPTION_TYPE_BAD = -1,
15979
15980 /* Ordinary option. */
15981 OPTION_TYPE_NORMAL,
15982
15983 /* ISA changing option. */
15984 OPTION_TYPE_ISA
15985};
15986
15987/* Handle common .set/.module options. Return status indicating option
15988 type. */
15989
15990static enum code_option_type
919731af 15991parse_code_option (char * name)
252b5132 15992{
22522f88 15993 bfd_boolean isa_set = FALSE;
c6278170 15994 const struct mips_ase *ase;
22522f88 15995
919731af 15996 if (strncmp (name, "at=", 3) == 0)
741fe287
MR
15997 {
15998 char *s = name + 3;
15999
16000 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
1661c76c 16001 as_bad (_("unrecognized register name `%s'"), s);
741fe287 16002 }
252b5132 16003 else if (strcmp (name, "at") == 0)
919731af 16004 mips_opts.at = ATREG;
252b5132 16005 else if (strcmp (name, "noat") == 0)
919731af 16006 mips_opts.at = ZERO;
252b5132 16007 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
919731af 16008 mips_opts.nomove = 0;
252b5132 16009 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
919731af 16010 mips_opts.nomove = 1;
252b5132 16011 else if (strcmp (name, "bopt") == 0)
919731af 16012 mips_opts.nobopt = 0;
252b5132 16013 else if (strcmp (name, "nobopt") == 0)
919731af 16014 mips_opts.nobopt = 1;
ad3fea08 16015 else if (strcmp (name, "gp=32") == 0)
bad1aba3 16016 mips_opts.gp = 32;
ad3fea08 16017 else if (strcmp (name, "gp=64") == 0)
919731af 16018 mips_opts.gp = 64;
ad3fea08 16019 else if (strcmp (name, "fp=32") == 0)
0b35dfee 16020 mips_opts.fp = 32;
351cdf24
MF
16021 else if (strcmp (name, "fp=xx") == 0)
16022 mips_opts.fp = 0;
ad3fea08 16023 else if (strcmp (name, "fp=64") == 0)
919731af 16024 mips_opts.fp = 64;
037b32b9
AN
16025 else if (strcmp (name, "softfloat") == 0)
16026 mips_opts.soft_float = 1;
16027 else if (strcmp (name, "hardfloat") == 0)
16028 mips_opts.soft_float = 0;
16029 else if (strcmp (name, "singlefloat") == 0)
16030 mips_opts.single_float = 1;
16031 else if (strcmp (name, "doublefloat") == 0)
16032 mips_opts.single_float = 0;
351cdf24
MF
16033 else if (strcmp (name, "nooddspreg") == 0)
16034 mips_opts.oddspreg = 0;
16035 else if (strcmp (name, "oddspreg") == 0)
16036 mips_opts.oddspreg = 1;
252b5132
RH
16037 else if (strcmp (name, "mips16") == 0
16038 || strcmp (name, "MIPS-16") == 0)
919731af 16039 mips_opts.mips16 = 1;
252b5132
RH
16040 else if (strcmp (name, "nomips16") == 0
16041 || strcmp (name, "noMIPS-16") == 0)
16042 mips_opts.mips16 = 0;
df58fc94 16043 else if (strcmp (name, "micromips") == 0)
919731af 16044 mips_opts.micromips = 1;
df58fc94
RS
16045 else if (strcmp (name, "nomicromips") == 0)
16046 mips_opts.micromips = 0;
c6278170
RS
16047 else if (name[0] == 'n'
16048 && name[1] == 'o'
16049 && (ase = mips_lookup_ase (name + 2)))
919731af 16050 mips_set_ase (ase, &mips_opts, FALSE);
c6278170 16051 else if ((ase = mips_lookup_ase (name)))
919731af 16052 mips_set_ase (ase, &mips_opts, TRUE);
1a2c1fad 16053 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
252b5132 16054 {
1a2c1fad
CD
16055 /* Permit the user to change the ISA and architecture on the fly.
16056 Needless to say, misuse can cause serious problems. */
919731af 16057 if (strncmp (name, "arch=", 5) == 0)
1a2c1fad
CD
16058 {
16059 const struct mips_cpu_info *p;
16060
919731af 16061 p = mips_parse_cpu ("internal use", name + 5);
1a2c1fad
CD
16062 if (!p)
16063 as_bad (_("unknown architecture %s"), name + 5);
16064 else
16065 {
16066 mips_opts.arch = p->cpu;
16067 mips_opts.isa = p->isa;
22522f88 16068 isa_set = TRUE;
1a2c1fad
CD
16069 }
16070 }
81a21e38
TS
16071 else if (strncmp (name, "mips", 4) == 0)
16072 {
16073 const struct mips_cpu_info *p;
16074
919731af 16075 p = mips_parse_cpu ("internal use", name);
81a21e38
TS
16076 if (!p)
16077 as_bad (_("unknown ISA level %s"), name + 4);
16078 else
16079 {
16080 mips_opts.arch = p->cpu;
16081 mips_opts.isa = p->isa;
22522f88 16082 isa_set = TRUE;
81a21e38
TS
16083 }
16084 }
af7ee8bf 16085 else
81a21e38 16086 as_bad (_("unknown ISA or architecture %s"), name);
252b5132
RH
16087 }
16088 else if (strcmp (name, "autoextend") == 0)
16089 mips_opts.noautoextend = 0;
16090 else if (strcmp (name, "noautoextend") == 0)
16091 mips_opts.noautoextend = 1;
833794fc
MR
16092 else if (strcmp (name, "insn32") == 0)
16093 mips_opts.insn32 = TRUE;
16094 else if (strcmp (name, "noinsn32") == 0)
16095 mips_opts.insn32 = FALSE;
919731af 16096 else if (strcmp (name, "sym32") == 0)
16097 mips_opts.sym32 = TRUE;
16098 else if (strcmp (name, "nosym32") == 0)
16099 mips_opts.sym32 = FALSE;
16100 else
22522f88
MR
16101 return OPTION_TYPE_BAD;
16102
16103 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
919731af 16104}
16105
16106/* Handle the .set pseudo-op. */
16107
16108static void
16109s_mipsset (int x ATTRIBUTE_UNUSED)
16110{
22522f88 16111 enum code_option_type type = OPTION_TYPE_NORMAL;
919731af 16112 char *name = input_line_pointer, ch;
919731af 16113
16114 file_mips_check_options ();
16115
16116 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16117 ++input_line_pointer;
16118 ch = *input_line_pointer;
16119 *input_line_pointer = '\0';
16120
16121 if (strchr (name, ','))
16122 {
16123 /* Generic ".set" directive; use the generic handler. */
16124 *input_line_pointer = ch;
16125 input_line_pointer = name;
16126 s_set (0);
16127 return;
16128 }
16129
16130 if (strcmp (name, "reorder") == 0)
16131 {
16132 if (mips_opts.noreorder)
16133 end_noreorder ();
16134 }
16135 else if (strcmp (name, "noreorder") == 0)
16136 {
16137 if (!mips_opts.noreorder)
16138 start_noreorder ();
16139 }
16140 else if (strcmp (name, "macro") == 0)
16141 mips_opts.warn_about_macros = 0;
16142 else if (strcmp (name, "nomacro") == 0)
16143 {
16144 if (mips_opts.noreorder == 0)
16145 as_bad (_("`noreorder' must be set before `nomacro'"));
16146 mips_opts.warn_about_macros = 1;
16147 }
16148 else if (strcmp (name, "gp=default") == 0)
16149 mips_opts.gp = file_mips_opts.gp;
16150 else if (strcmp (name, "fp=default") == 0)
16151 mips_opts.fp = file_mips_opts.fp;
16152 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16153 {
16154 mips_opts.isa = file_mips_opts.isa;
16155 mips_opts.arch = file_mips_opts.arch;
16156 mips_opts.gp = file_mips_opts.gp;
16157 mips_opts.fp = file_mips_opts.fp;
16158 }
252b5132
RH
16159 else if (strcmp (name, "push") == 0)
16160 {
16161 struct mips_option_stack *s;
16162
325801bd 16163 s = XNEW (struct mips_option_stack);
252b5132
RH
16164 s->next = mips_opts_stack;
16165 s->options = mips_opts;
16166 mips_opts_stack = s;
16167 }
16168 else if (strcmp (name, "pop") == 0)
16169 {
16170 struct mips_option_stack *s;
16171
16172 s = mips_opts_stack;
16173 if (s == NULL)
16174 as_bad (_(".set pop with no .set push"));
16175 else
16176 {
16177 /* If we're changing the reorder mode we need to handle
16178 delay slots correctly. */
16179 if (s->options.noreorder && ! mips_opts.noreorder)
7d10b47d 16180 start_noreorder ();
252b5132 16181 else if (! s->options.noreorder && mips_opts.noreorder)
7d10b47d 16182 end_noreorder ();
252b5132
RH
16183
16184 mips_opts = s->options;
16185 mips_opts_stack = s->next;
16186 free (s);
16187 }
16188 }
22522f88
MR
16189 else
16190 {
16191 type = parse_code_option (name);
16192 if (type == OPTION_TYPE_BAD)
16193 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
16194 }
919731af 16195
16196 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16197 registers based on what is supported by the arch/cpu. */
22522f88 16198 if (type == OPTION_TYPE_ISA)
e6559e01 16199 {
919731af 16200 switch (mips_opts.isa)
16201 {
16202 case 0:
16203 break;
16204 case ISA_MIPS1:
351cdf24
MF
16205 /* MIPS I cannot support FPXX. */
16206 mips_opts.fp = 32;
16207 /* fall-through. */
919731af 16208 case ISA_MIPS2:
16209 case ISA_MIPS32:
16210 case ISA_MIPS32R2:
16211 case ISA_MIPS32R3:
16212 case ISA_MIPS32R5:
16213 mips_opts.gp = 32;
351cdf24
MF
16214 if (mips_opts.fp != 0)
16215 mips_opts.fp = 32;
919731af 16216 break;
7361da2c
AB
16217 case ISA_MIPS32R6:
16218 mips_opts.gp = 32;
16219 mips_opts.fp = 64;
16220 break;
919731af 16221 case ISA_MIPS3:
16222 case ISA_MIPS4:
16223 case ISA_MIPS5:
16224 case ISA_MIPS64:
16225 case ISA_MIPS64R2:
16226 case ISA_MIPS64R3:
16227 case ISA_MIPS64R5:
7361da2c 16228 case ISA_MIPS64R6:
919731af 16229 mips_opts.gp = 64;
351cdf24
MF
16230 if (mips_opts.fp != 0)
16231 {
16232 if (mips_opts.arch == CPU_R5900)
16233 mips_opts.fp = 32;
16234 else
16235 mips_opts.fp = 64;
16236 }
919731af 16237 break;
16238 default:
16239 as_bad (_("unknown ISA level %s"), name + 4);
16240 break;
16241 }
e6559e01 16242 }
919731af 16243
16244 mips_check_options (&mips_opts, FALSE);
16245
16246 mips_check_isa_supports_ases ();
16247 *input_line_pointer = ch;
16248 demand_empty_rest_of_line ();
16249}
16250
16251/* Handle the .module pseudo-op. */
16252
16253static void
16254s_module (int ignore ATTRIBUTE_UNUSED)
16255{
16256 char *name = input_line_pointer, ch;
16257
16258 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16259 ++input_line_pointer;
16260 ch = *input_line_pointer;
16261 *input_line_pointer = '\0';
16262
16263 if (!file_mips_opts_checked)
252b5132 16264 {
22522f88 16265 if (parse_code_option (name) == OPTION_TYPE_BAD)
919731af 16266 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
16267
16268 /* Update module level settings from mips_opts. */
16269 file_mips_opts = mips_opts;
252b5132 16270 }
919731af 16271 else
16272 as_bad (_(".module is not permitted after generating code"));
16273
252b5132
RH
16274 *input_line_pointer = ch;
16275 demand_empty_rest_of_line ();
16276}
16277
16278/* Handle the .abicalls pseudo-op. I believe this is equivalent to
16279 .option pic2. It means to generate SVR4 PIC calls. */
16280
16281static void
17a2f251 16282s_abicalls (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16283{
16284 mips_pic = SVR4_PIC;
143d77c5 16285 mips_abicalls = TRUE;
4d0d148d
TS
16286
16287 if (g_switch_seen && g_switch_value != 0)
16288 as_warn (_("-G may not be used with SVR4 PIC code"));
16289 g_switch_value = 0;
16290
252b5132
RH
16291 bfd_set_gp_size (stdoutput, 0);
16292 demand_empty_rest_of_line ();
16293}
16294
16295/* Handle the .cpload pseudo-op. This is used when generating SVR4
16296 PIC code. It sets the $gp register for the function based on the
16297 function address, which is in the register named in the argument.
16298 This uses a relocation against _gp_disp, which is handled specially
16299 by the linker. The result is:
16300 lui $gp,%hi(_gp_disp)
16301 addiu $gp,$gp,%lo(_gp_disp)
16302 addu $gp,$gp,.cpload argument
aa6975fb
ILT
16303 The .cpload argument is normally $25 == $t9.
16304
16305 The -mno-shared option changes this to:
bbe506e8
TS
16306 lui $gp,%hi(__gnu_local_gp)
16307 addiu $gp,$gp,%lo(__gnu_local_gp)
aa6975fb
ILT
16308 and the argument is ignored. This saves an instruction, but the
16309 resulting code is not position independent; it uses an absolute
bbe506e8
TS
16310 address for __gnu_local_gp. Thus code assembled with -mno-shared
16311 can go into an ordinary executable, but not into a shared library. */
252b5132
RH
16312
16313static void
17a2f251 16314s_cpload (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16315{
16316 expressionS ex;
aa6975fb
ILT
16317 int reg;
16318 int in_shared;
252b5132 16319
919731af 16320 file_mips_check_options ();
16321
6478892d
TS
16322 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16323 .cpload is ignored. */
16324 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
16325 {
16326 s_ignore (0);
16327 return;
16328 }
16329
a276b80c
MR
16330 if (mips_opts.mips16)
16331 {
16332 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16333 ignore_rest_of_line ();
16334 return;
16335 }
16336
d3ecfc59 16337 /* .cpload should be in a .set noreorder section. */
252b5132
RH
16338 if (mips_opts.noreorder == 0)
16339 as_warn (_(".cpload not in noreorder section"));
16340
aa6975fb
ILT
16341 reg = tc_get_register (0);
16342
16343 /* If we need to produce a 64-bit address, we are better off using
16344 the default instruction sequence. */
aed1a261 16345 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
aa6975fb 16346
252b5132 16347 ex.X_op = O_symbol;
bbe506e8
TS
16348 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16349 "__gnu_local_gp");
252b5132
RH
16350 ex.X_op_symbol = NULL;
16351 ex.X_add_number = 0;
16352
16353 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
49309057 16354 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
252b5132 16355
8a75745d
MR
16356 mips_mark_labels ();
16357 mips_assembling_insn = TRUE;
16358
584892a6 16359 macro_start ();
67c0d1eb
RS
16360 macro_build_lui (&ex, mips_gp_register);
16361 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
17a2f251 16362 mips_gp_register, BFD_RELOC_LO16);
aa6975fb
ILT
16363 if (in_shared)
16364 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16365 mips_gp_register, reg);
584892a6 16366 macro_end ();
252b5132 16367
8a75745d 16368 mips_assembling_insn = FALSE;
252b5132
RH
16369 demand_empty_rest_of_line ();
16370}
16371
6478892d
TS
16372/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16373 .cpsetup $reg1, offset|$reg2, label
16374
16375 If offset is given, this results in:
16376 sd $gp, offset($sp)
956cd1d6 16377 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
16378 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16379 daddu $gp, $gp, $reg1
6478892d
TS
16380
16381 If $reg2 is given, this results in:
40fc1451 16382 or $reg2, $gp, $0
956cd1d6 16383 lui $gp, %hi(%neg(%gp_rel(label)))
698b7d9d
TS
16384 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16385 daddu $gp, $gp, $reg1
aa6975fb
ILT
16386 $reg1 is normally $25 == $t9.
16387
16388 The -mno-shared option replaces the last three instructions with
16389 lui $gp,%hi(_gp)
54f4ddb3 16390 addiu $gp,$gp,%lo(_gp) */
aa6975fb 16391
6478892d 16392static void
17a2f251 16393s_cpsetup (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
16394{
16395 expressionS ex_off;
16396 expressionS ex_sym;
16397 int reg1;
6478892d 16398
919731af 16399 file_mips_check_options ();
16400
8586fc66 16401 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
6478892d
TS
16402 We also need NewABI support. */
16403 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16404 {
16405 s_ignore (0);
16406 return;
16407 }
16408
a276b80c
MR
16409 if (mips_opts.mips16)
16410 {
16411 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16412 ignore_rest_of_line ();
16413 return;
16414 }
16415
6478892d
TS
16416 reg1 = tc_get_register (0);
16417 SKIP_WHITESPACE ();
16418 if (*input_line_pointer != ',')
16419 {
16420 as_bad (_("missing argument separator ',' for .cpsetup"));
16421 return;
16422 }
16423 else
80245285 16424 ++input_line_pointer;
6478892d
TS
16425 SKIP_WHITESPACE ();
16426 if (*input_line_pointer == '$')
80245285
TS
16427 {
16428 mips_cpreturn_register = tc_get_register (0);
16429 mips_cpreturn_offset = -1;
16430 }
6478892d 16431 else
80245285
TS
16432 {
16433 mips_cpreturn_offset = get_absolute_expression ();
16434 mips_cpreturn_register = -1;
16435 }
6478892d
TS
16436 SKIP_WHITESPACE ();
16437 if (*input_line_pointer != ',')
16438 {
16439 as_bad (_("missing argument separator ',' for .cpsetup"));
16440 return;
16441 }
16442 else
f9419b05 16443 ++input_line_pointer;
6478892d 16444 SKIP_WHITESPACE ();
f21f8242 16445 expression (&ex_sym);
6478892d 16446
8a75745d
MR
16447 mips_mark_labels ();
16448 mips_assembling_insn = TRUE;
16449
584892a6 16450 macro_start ();
6478892d
TS
16451 if (mips_cpreturn_register == -1)
16452 {
16453 ex_off.X_op = O_constant;
16454 ex_off.X_add_symbol = NULL;
16455 ex_off.X_op_symbol = NULL;
16456 ex_off.X_add_number = mips_cpreturn_offset;
16457
67c0d1eb 16458 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
17a2f251 16459 BFD_RELOC_LO16, SP);
6478892d
TS
16460 }
16461 else
40fc1451 16462 move_register (mips_cpreturn_register, mips_gp_register);
6478892d 16463
aed1a261 16464 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
aa6975fb 16465 {
df58fc94 16466 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
aa6975fb
ILT
16467 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16468 BFD_RELOC_HI16_S);
16469
16470 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16471 mips_gp_register, -1, BFD_RELOC_GPREL16,
16472 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16473
16474 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16475 mips_gp_register, reg1);
16476 }
16477 else
16478 {
16479 expressionS ex;
16480
16481 ex.X_op = O_symbol;
4184909a 16482 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
aa6975fb
ILT
16483 ex.X_op_symbol = NULL;
16484 ex.X_add_number = 0;
6e1304d8 16485
aa6975fb
ILT
16486 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16487 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16488
16489 macro_build_lui (&ex, mips_gp_register);
16490 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16491 mips_gp_register, BFD_RELOC_LO16);
16492 }
f21f8242 16493
584892a6 16494 macro_end ();
6478892d 16495
8a75745d 16496 mips_assembling_insn = FALSE;
6478892d
TS
16497 demand_empty_rest_of_line ();
16498}
16499
16500static void
17a2f251 16501s_cplocal (int ignore ATTRIBUTE_UNUSED)
6478892d 16502{
919731af 16503 file_mips_check_options ();
16504
6478892d 16505 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
54f4ddb3 16506 .cplocal is ignored. */
6478892d
TS
16507 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16508 {
16509 s_ignore (0);
16510 return;
16511 }
16512
a276b80c
MR
16513 if (mips_opts.mips16)
16514 {
16515 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16516 ignore_rest_of_line ();
16517 return;
16518 }
16519
6478892d 16520 mips_gp_register = tc_get_register (0);
85b51719 16521 demand_empty_rest_of_line ();
6478892d
TS
16522}
16523
252b5132
RH
16524/* Handle the .cprestore pseudo-op. This stores $gp into a given
16525 offset from $sp. The offset is remembered, and after making a PIC
16526 call $gp is restored from that location. */
16527
16528static void
17a2f251 16529s_cprestore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16530{
16531 expressionS ex;
252b5132 16532
919731af 16533 file_mips_check_options ();
16534
6478892d 16535 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
c9914766 16536 .cprestore is ignored. */
6478892d 16537 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
252b5132
RH
16538 {
16539 s_ignore (0);
16540 return;
16541 }
16542
a276b80c
MR
16543 if (mips_opts.mips16)
16544 {
16545 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16546 ignore_rest_of_line ();
16547 return;
16548 }
16549
252b5132 16550 mips_cprestore_offset = get_absolute_expression ();
7a621144 16551 mips_cprestore_valid = 1;
252b5132
RH
16552
16553 ex.X_op = O_constant;
16554 ex.X_add_symbol = NULL;
16555 ex.X_op_symbol = NULL;
16556 ex.X_add_number = mips_cprestore_offset;
16557
8a75745d
MR
16558 mips_mark_labels ();
16559 mips_assembling_insn = TRUE;
16560
584892a6 16561 macro_start ();
67c0d1eb
RS
16562 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16563 SP, HAVE_64BIT_ADDRESSES);
584892a6 16564 macro_end ();
252b5132 16565
8a75745d 16566 mips_assembling_insn = FALSE;
252b5132
RH
16567 demand_empty_rest_of_line ();
16568}
16569
6478892d 16570/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
67c1ffbe 16571 was given in the preceding .cpsetup, it results in:
6478892d 16572 ld $gp, offset($sp)
76b3015f 16573
6478892d 16574 If a register $reg2 was given there, it results in:
40fc1451 16575 or $gp, $reg2, $0 */
54f4ddb3 16576
6478892d 16577static void
17a2f251 16578s_cpreturn (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
16579{
16580 expressionS ex;
6478892d 16581
919731af 16582 file_mips_check_options ();
16583
6478892d
TS
16584 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16585 We also need NewABI support. */
16586 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16587 {
16588 s_ignore (0);
16589 return;
16590 }
16591
a276b80c
MR
16592 if (mips_opts.mips16)
16593 {
16594 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16595 ignore_rest_of_line ();
16596 return;
16597 }
16598
8a75745d
MR
16599 mips_mark_labels ();
16600 mips_assembling_insn = TRUE;
16601
584892a6 16602 macro_start ();
6478892d
TS
16603 if (mips_cpreturn_register == -1)
16604 {
16605 ex.X_op = O_constant;
16606 ex.X_add_symbol = NULL;
16607 ex.X_op_symbol = NULL;
16608 ex.X_add_number = mips_cpreturn_offset;
16609
67c0d1eb 16610 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
6478892d
TS
16611 }
16612 else
40fc1451
SD
16613 move_register (mips_gp_register, mips_cpreturn_register);
16614
584892a6 16615 macro_end ();
6478892d 16616
8a75745d 16617 mips_assembling_insn = FALSE;
6478892d
TS
16618 demand_empty_rest_of_line ();
16619}
16620
d0f13682
CLT
16621/* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16622 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16623 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16624 debug information or MIPS16 TLS. */
741d6ea8
JM
16625
16626static void
d0f13682
CLT
16627s_tls_rel_directive (const size_t bytes, const char *dirstr,
16628 bfd_reloc_code_real_type rtype)
741d6ea8
JM
16629{
16630 expressionS ex;
16631 char *p;
16632
16633 expression (&ex);
16634
16635 if (ex.X_op != O_symbol)
16636 {
1661c76c 16637 as_bad (_("unsupported use of %s"), dirstr);
741d6ea8
JM
16638 ignore_rest_of_line ();
16639 }
16640
16641 p = frag_more (bytes);
16642 md_number_to_chars (p, 0, bytes);
d0f13682 16643 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
741d6ea8 16644 demand_empty_rest_of_line ();
de64cffd 16645 mips_clear_insn_labels ();
741d6ea8
JM
16646}
16647
16648/* Handle .dtprelword. */
16649
16650static void
16651s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16652{
d0f13682 16653 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
741d6ea8
JM
16654}
16655
16656/* Handle .dtpreldword. */
16657
16658static void
16659s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16660{
d0f13682
CLT
16661 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16662}
16663
16664/* Handle .tprelword. */
16665
16666static void
16667s_tprelword (int ignore ATTRIBUTE_UNUSED)
16668{
16669 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16670}
16671
16672/* Handle .tpreldword. */
16673
16674static void
16675s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16676{
16677 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
741d6ea8
JM
16678}
16679
6478892d
TS
16680/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16681 code. It sets the offset to use in gp_rel relocations. */
16682
16683static void
17a2f251 16684s_gpvalue (int ignore ATTRIBUTE_UNUSED)
6478892d
TS
16685{
16686 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16687 We also need NewABI support. */
16688 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16689 {
16690 s_ignore (0);
16691 return;
16692 }
16693
def2e0dd 16694 mips_gprel_offset = get_absolute_expression ();
6478892d
TS
16695
16696 demand_empty_rest_of_line ();
16697}
16698
252b5132
RH
16699/* Handle the .gpword pseudo-op. This is used when generating PIC
16700 code. It generates a 32 bit GP relative reloc. */
16701
16702static void
17a2f251 16703s_gpword (int ignore ATTRIBUTE_UNUSED)
252b5132 16704{
a8dbcb85
TS
16705 segment_info_type *si;
16706 struct insn_label_list *l;
252b5132
RH
16707 expressionS ex;
16708 char *p;
16709
16710 /* When not generating PIC code, this is treated as .word. */
16711 if (mips_pic != SVR4_PIC)
16712 {
16713 s_cons (2);
16714 return;
16715 }
16716
a8dbcb85
TS
16717 si = seg_info (now_seg);
16718 l = si->label_list;
7d10b47d 16719 mips_emit_delays ();
252b5132 16720 if (auto_align)
462427c4 16721 mips_align (2, 0, l);
252b5132
RH
16722
16723 expression (&ex);
a1facbec 16724 mips_clear_insn_labels ();
252b5132
RH
16725
16726 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16727 {
1661c76c 16728 as_bad (_("unsupported use of .gpword"));
252b5132
RH
16729 ignore_rest_of_line ();
16730 }
16731
16732 p = frag_more (4);
17a2f251 16733 md_number_to_chars (p, 0, 4);
b34976b6 16734 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
cdf6fd85 16735 BFD_RELOC_GPREL32);
252b5132
RH
16736
16737 demand_empty_rest_of_line ();
16738}
16739
10181a0d 16740static void
17a2f251 16741s_gpdword (int ignore ATTRIBUTE_UNUSED)
10181a0d 16742{
a8dbcb85
TS
16743 segment_info_type *si;
16744 struct insn_label_list *l;
10181a0d
AO
16745 expressionS ex;
16746 char *p;
16747
16748 /* When not generating PIC code, this is treated as .dword. */
16749 if (mips_pic != SVR4_PIC)
16750 {
16751 s_cons (3);
16752 return;
16753 }
16754
a8dbcb85
TS
16755 si = seg_info (now_seg);
16756 l = si->label_list;
7d10b47d 16757 mips_emit_delays ();
10181a0d 16758 if (auto_align)
462427c4 16759 mips_align (3, 0, l);
10181a0d
AO
16760
16761 expression (&ex);
a1facbec 16762 mips_clear_insn_labels ();
10181a0d
AO
16763
16764 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16765 {
1661c76c 16766 as_bad (_("unsupported use of .gpdword"));
10181a0d
AO
16767 ignore_rest_of_line ();
16768 }
16769
16770 p = frag_more (8);
17a2f251 16771 md_number_to_chars (p, 0, 8);
a105a300 16772 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
6e1304d8 16773 BFD_RELOC_GPREL32)->fx_tcbit = 1;
10181a0d
AO
16774
16775 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
6e1304d8
RS
16776 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16777 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
10181a0d
AO
16778
16779 demand_empty_rest_of_line ();
16780}
16781
a3f278e2
CM
16782/* Handle the .ehword pseudo-op. This is used when generating unwinding
16783 tables. It generates a R_MIPS_EH reloc. */
16784
16785static void
16786s_ehword (int ignore ATTRIBUTE_UNUSED)
16787{
16788 expressionS ex;
16789 char *p;
16790
16791 mips_emit_delays ();
16792
16793 expression (&ex);
16794 mips_clear_insn_labels ();
16795
16796 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16797 {
1661c76c 16798 as_bad (_("unsupported use of .ehword"));
a3f278e2
CM
16799 ignore_rest_of_line ();
16800 }
16801
16802 p = frag_more (4);
16803 md_number_to_chars (p, 0, 4);
16804 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
2f0c68f2 16805 BFD_RELOC_32_PCREL);
a3f278e2
CM
16806
16807 demand_empty_rest_of_line ();
16808}
16809
252b5132
RH
16810/* Handle the .cpadd pseudo-op. This is used when dealing with switch
16811 tables in SVR4 PIC code. */
16812
16813static void
17a2f251 16814s_cpadd (int ignore ATTRIBUTE_UNUSED)
252b5132 16815{
252b5132
RH
16816 int reg;
16817
919731af 16818 file_mips_check_options ();
16819
10181a0d
AO
16820 /* This is ignored when not generating SVR4 PIC code. */
16821 if (mips_pic != SVR4_PIC)
252b5132
RH
16822 {
16823 s_ignore (0);
16824 return;
16825 }
16826
8a75745d
MR
16827 mips_mark_labels ();
16828 mips_assembling_insn = TRUE;
16829
252b5132 16830 /* Add $gp to the register named as an argument. */
584892a6 16831 macro_start ();
252b5132 16832 reg = tc_get_register (0);
67c0d1eb 16833 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
584892a6 16834 macro_end ();
252b5132 16835
8a75745d 16836 mips_assembling_insn = FALSE;
bdaaa2e1 16837 demand_empty_rest_of_line ();
252b5132
RH
16838}
16839
16840/* Handle the .insn pseudo-op. This marks instruction labels in
df58fc94 16841 mips16/micromips mode. This permits the linker to handle them specially,
252b5132
RH
16842 such as generating jalx instructions when needed. We also make
16843 them odd for the duration of the assembly, in order to generate the
16844 right sort of code. We will make them even in the adjust_symtab
16845 routine, while leaving them marked. This is convenient for the
16846 debugger and the disassembler. The linker knows to make them odd
16847 again. */
16848
16849static void
17a2f251 16850s_insn (int ignore ATTRIBUTE_UNUSED)
252b5132 16851{
7bb01e2d
MR
16852 file_mips_check_options ();
16853 file_ase_mips16 |= mips_opts.mips16;
16854 file_ase_micromips |= mips_opts.micromips;
16855
df58fc94 16856 mips_mark_labels ();
252b5132
RH
16857
16858 demand_empty_rest_of_line ();
16859}
16860
ba92f887
MR
16861/* Handle the .nan pseudo-op. */
16862
16863static void
16864s_nan (int ignore ATTRIBUTE_UNUSED)
16865{
16866 static const char str_legacy[] = "legacy";
16867 static const char str_2008[] = "2008";
16868 size_t i;
16869
16870 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
16871
16872 if (i == sizeof (str_2008) - 1
16873 && memcmp (input_line_pointer, str_2008, i) == 0)
7361da2c 16874 mips_nan2008 = 1;
ba92f887
MR
16875 else if (i == sizeof (str_legacy) - 1
16876 && memcmp (input_line_pointer, str_legacy, i) == 0)
7361da2c
AB
16877 {
16878 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16879 mips_nan2008 = 0;
16880 else
16881 as_bad (_("`%s' does not support legacy NaN"),
16882 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16883 }
ba92f887 16884 else
1661c76c 16885 as_bad (_("bad .nan directive"));
ba92f887
MR
16886
16887 input_line_pointer += i;
16888 demand_empty_rest_of_line ();
16889}
16890
754e2bb9
RS
16891/* Handle a .stab[snd] directive. Ideally these directives would be
16892 implemented in a transparent way, so that removing them would not
16893 have any effect on the generated instructions. However, s_stab
16894 internally changes the section, so in practice we need to decide
16895 now whether the preceding label marks compressed code. We do not
16896 support changing the compression mode of a label after a .stab*
16897 directive, such as in:
16898
16899 foo:
134c0c8b 16900 .stabs ...
754e2bb9
RS
16901 .set mips16
16902
16903 so the current mode wins. */
252b5132
RH
16904
16905static void
17a2f251 16906s_mips_stab (int type)
252b5132 16907{
754e2bb9 16908 mips_mark_labels ();
252b5132
RH
16909 s_stab (type);
16910}
16911
54f4ddb3 16912/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
252b5132
RH
16913
16914static void
17a2f251 16915s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
252b5132
RH
16916{
16917 char *name;
16918 int c;
16919 symbolS *symbolP;
16920 expressionS exp;
16921
d02603dc 16922 c = get_symbol_name (&name);
252b5132
RH
16923 symbolP = symbol_find_or_make (name);
16924 S_SET_WEAK (symbolP);
16925 *input_line_pointer = c;
16926
d02603dc 16927 SKIP_WHITESPACE_AFTER_NAME ();
252b5132
RH
16928
16929 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16930 {
16931 if (S_IS_DEFINED (symbolP))
16932 {
20203fb9 16933 as_bad (_("ignoring attempt to redefine symbol %s"),
252b5132
RH
16934 S_GET_NAME (symbolP));
16935 ignore_rest_of_line ();
16936 return;
16937 }
bdaaa2e1 16938
252b5132
RH
16939 if (*input_line_pointer == ',')
16940 {
16941 ++input_line_pointer;
16942 SKIP_WHITESPACE ();
16943 }
bdaaa2e1 16944
252b5132
RH
16945 expression (&exp);
16946 if (exp.X_op != O_symbol)
16947 {
20203fb9 16948 as_bad (_("bad .weakext directive"));
98d3f06f 16949 ignore_rest_of_line ();
252b5132
RH
16950 return;
16951 }
49309057 16952 symbol_set_value_expression (symbolP, &exp);
252b5132
RH
16953 }
16954
16955 demand_empty_rest_of_line ();
16956}
16957
16958/* Parse a register string into a number. Called from the ECOFF code
16959 to parse .frame. The argument is non-zero if this is the frame
16960 register, so that we can record it in mips_frame_reg. */
16961
16962int
17a2f251 16963tc_get_register (int frame)
252b5132 16964{
707bfff6 16965 unsigned int reg;
252b5132
RH
16966
16967 SKIP_WHITESPACE ();
707bfff6
TS
16968 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
16969 reg = 0;
252b5132 16970 if (frame)
7a621144
DJ
16971 {
16972 mips_frame_reg = reg != 0 ? reg : SP;
16973 mips_frame_reg_valid = 1;
16974 mips_cprestore_valid = 0;
16975 }
252b5132
RH
16976 return reg;
16977}
16978
16979valueT
17a2f251 16980md_section_align (asection *seg, valueT addr)
252b5132
RH
16981{
16982 int align = bfd_get_section_alignment (stdoutput, seg);
16983
f3ded42a
RS
16984 /* We don't need to align ELF sections to the full alignment.
16985 However, Irix 5 may prefer that we align them at least to a 16
16986 byte boundary. We don't bother to align the sections if we
16987 are targeted for an embedded system. */
16988 if (strncmp (TARGET_OS, "elf", 3) == 0)
16989 return addr;
16990 if (align > 4)
16991 align = 4;
252b5132 16992
8d3842cd 16993 return ((addr + (1 << align) - 1) & -(1 << align));
252b5132
RH
16994}
16995
16996/* Utility routine, called from above as well. If called while the
16997 input file is still being read, it's only an approximation. (For
16998 example, a symbol may later become defined which appeared to be
16999 undefined earlier.) */
17000
17001static int
17a2f251 17002nopic_need_relax (symbolS *sym, int before_relaxing)
252b5132
RH
17003{
17004 if (sym == 0)
17005 return 0;
17006
4d0d148d 17007 if (g_switch_value > 0)
252b5132
RH
17008 {
17009 const char *symname;
17010 int change;
17011
c9914766 17012 /* Find out whether this symbol can be referenced off the $gp
252b5132
RH
17013 register. It can be if it is smaller than the -G size or if
17014 it is in the .sdata or .sbss section. Certain symbols can
c9914766 17015 not be referenced off the $gp, although it appears as though
252b5132
RH
17016 they can. */
17017 symname = S_GET_NAME (sym);
17018 if (symname != (const char *) NULL
17019 && (strcmp (symname, "eprol") == 0
17020 || strcmp (symname, "etext") == 0
17021 || strcmp (symname, "_gp") == 0
17022 || strcmp (symname, "edata") == 0
17023 || strcmp (symname, "_fbss") == 0
17024 || strcmp (symname, "_fdata") == 0
17025 || strcmp (symname, "_ftext") == 0
17026 || strcmp (symname, "end") == 0
17027 || strcmp (symname, "_gp_disp") == 0))
17028 change = 1;
17029 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17030 && (0
17031#ifndef NO_ECOFF_DEBUGGING
49309057
ILT
17032 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17033 && (symbol_get_obj (sym)->ecoff_extern_size
17034 <= g_switch_value))
252b5132
RH
17035#endif
17036 /* We must defer this decision until after the whole
17037 file has been read, since there might be a .extern
17038 after the first use of this symbol. */
17039 || (before_relaxing
17040#ifndef NO_ECOFF_DEBUGGING
49309057 17041 && symbol_get_obj (sym)->ecoff_extern_size == 0
252b5132
RH
17042#endif
17043 && S_GET_VALUE (sym) == 0)
17044 || (S_GET_VALUE (sym) != 0
17045 && S_GET_VALUE (sym) <= g_switch_value)))
17046 change = 0;
17047 else
17048 {
17049 const char *segname;
17050
17051 segname = segment_name (S_GET_SEGMENT (sym));
9c2799c2 17052 gas_assert (strcmp (segname, ".lit8") != 0
252b5132
RH
17053 && strcmp (segname, ".lit4") != 0);
17054 change = (strcmp (segname, ".sdata") != 0
fba2b7f9
GK
17055 && strcmp (segname, ".sbss") != 0
17056 && strncmp (segname, ".sdata.", 7) != 0
d4dc2f22
TS
17057 && strncmp (segname, ".sbss.", 6) != 0
17058 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
fba2b7f9 17059 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
252b5132
RH
17060 }
17061 return change;
17062 }
17063 else
c9914766 17064 /* We are not optimizing for the $gp register. */
252b5132
RH
17065 return 1;
17066}
17067
5919d012
RS
17068
17069/* Return true if the given symbol should be considered local for SVR4 PIC. */
17070
17071static bfd_boolean
17a2f251 17072pic_need_relax (symbolS *sym, asection *segtype)
5919d012
RS
17073{
17074 asection *symsec;
5919d012
RS
17075
17076 /* Handle the case of a symbol equated to another symbol. */
17077 while (symbol_equated_reloc_p (sym))
17078 {
17079 symbolS *n;
17080
5f0fe04b 17081 /* It's possible to get a loop here in a badly written program. */
5919d012
RS
17082 n = symbol_get_value_expression (sym)->X_add_symbol;
17083 if (n == sym)
17084 break;
17085 sym = n;
17086 }
17087
df1f3cda
DD
17088 if (symbol_section_p (sym))
17089 return TRUE;
17090
5919d012
RS
17091 symsec = S_GET_SEGMENT (sym);
17092
5919d012 17093 /* This must duplicate the test in adjust_reloc_syms. */
45dfa85a
AM
17094 return (!bfd_is_und_section (symsec)
17095 && !bfd_is_abs_section (symsec)
5f0fe04b
TS
17096 && !bfd_is_com_section (symsec)
17097 && !s_is_linkonce (sym, segtype)
5919d012 17098 /* A global or weak symbol is treated as external. */
f3ded42a 17099 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
5919d012
RS
17100}
17101
17102
252b5132
RH
17103/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17104 extended opcode. SEC is the section the frag is in. */
17105
17106static int
17a2f251 17107mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
252b5132
RH
17108{
17109 int type;
3ccad066 17110 const struct mips_int_operand *operand;
252b5132 17111 offsetT val;
252b5132 17112 segT symsec;
98aa84af 17113 fragS *sym_frag;
252b5132
RH
17114
17115 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17116 return 0;
17117 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17118 return 1;
17119
88a7ef16 17120 symsec = S_GET_SEGMENT (fragp->fr_symbol);
252b5132 17121 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
3ccad066 17122 operand = mips16_immed_operand (type, FALSE);
88a7ef16
MR
17123 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
17124 || (operand->root.type == OP_PCREL
17125 ? sec != symsec
17126 : !bfd_is_abs_section (symsec)))
17127 return 1;
252b5132 17128
98aa84af 17129 sym_frag = symbol_get_frag (fragp->fr_symbol);
88a7ef16 17130 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
252b5132 17131
3ccad066 17132 if (operand->root.type == OP_PCREL)
252b5132 17133 {
3ccad066 17134 const struct mips_pcrel_operand *pcrel_op;
252b5132 17135 addressT addr;
3ccad066 17136 offsetT maxtiny;
252b5132 17137
88a7ef16
MR
17138 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17139 return 1;
252b5132 17140
88a7ef16 17141 pcrel_op = (const struct mips_pcrel_operand *) operand;
252b5132 17142
88a7ef16
MR
17143 /* If the relax_marker of the symbol fragment differs from the
17144 relax_marker of this fragment, we have not yet adjusted the
17145 symbol fragment fr_address. We want to add in STRETCH in
17146 order to get a better estimate of the address. This
17147 particularly matters because of the shift bits. */
252b5132 17148 if (stretch != 0
98aa84af 17149 && sym_frag->relax_marker != fragp->relax_marker)
252b5132
RH
17150 {
17151 fragS *f;
17152
17153 /* Adjust stretch for any alignment frag. Note that if have
17154 been expanding the earlier code, the symbol may be
17155 defined in what appears to be an earlier frag. FIXME:
17156 This doesn't handle the fr_subtype field, which specifies
17157 a maximum number of bytes to skip when doing an
17158 alignment. */
98aa84af 17159 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
252b5132
RH
17160 {
17161 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17162 {
17163 if (stretch < 0)
17164 stretch = - ((- stretch)
17165 & ~ ((1 << (int) f->fr_offset) - 1));
17166 else
17167 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17168 if (stretch == 0)
17169 break;
17170 }
17171 }
17172 if (f != NULL)
17173 val += stretch;
17174 }
17175
17176 addr = fragp->fr_address + fragp->fr_fix;
17177
17178 /* The base address rules are complicated. The base address of
17179 a branch is the following instruction. The base address of a
17180 PC relative load or add is the instruction itself, but if it
17181 is in a delay slot (in which case it can not be extended) use
17182 the address of the instruction whose delay slot it is in. */
3ccad066 17183 if (pcrel_op->include_isa_bit)
252b5132
RH
17184 {
17185 addr += 2;
17186
17187 /* If we are currently assuming that this frag should be
17188 extended, then, the current address is two bytes
bdaaa2e1 17189 higher. */
252b5132
RH
17190 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17191 addr += 2;
17192
17193 /* Ignore the low bit in the target, since it will be set
17194 for a text label. */
3ccad066 17195 val &= -2;
252b5132
RH
17196 }
17197 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17198 addr -= 4;
17199 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17200 addr -= 2;
17201
3ccad066 17202 val -= addr & -(1 << pcrel_op->align_log2);
252b5132
RH
17203
17204 /* If any of the shifted bits are set, we must use an extended
17205 opcode. If the address depends on the size of this
17206 instruction, this can lead to a loop, so we arrange to always
88a7ef16
MR
17207 use an extended opcode. */
17208 if ((val & ((1 << operand->shift) - 1)) != 0)
252b5132
RH
17209 {
17210 fragp->fr_subtype =
17211 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17212 return 1;
17213 }
17214
17215 /* If we are about to mark a frag as extended because the value
3ccad066
RS
17216 is precisely the next value above maxtiny, then there is a
17217 chance of an infinite loop as in the following code:
252b5132
RH
17218 la $4,foo
17219 .skip 1020
17220 .align 2
17221 foo:
17222 In this case when the la is extended, foo is 0x3fc bytes
17223 away, so the la can be shrunk, but then foo is 0x400 away, so
17224 the la must be extended. To avoid this loop, we mark the
17225 frag as extended if it was small, and is about to become
3ccad066
RS
17226 extended with the next value above maxtiny. */
17227 maxtiny = mips_int_operand_max (operand);
17228 if (val == maxtiny + (1 << operand->shift)
88a7ef16 17229 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
252b5132
RH
17230 {
17231 fragp->fr_subtype =
17232 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17233 return 1;
17234 }
17235 }
252b5132 17236
3ccad066 17237 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
252b5132
RH
17238}
17239
4a6a3df4
AO
17240/* Compute the length of a branch sequence, and adjust the
17241 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17242 worst-case length is computed, with UPDATE being used to indicate
17243 whether an unconditional (-1), branch-likely (+1) or regular (0)
17244 branch is to be computed. */
17245static int
17a2f251 17246relaxed_branch_length (fragS *fragp, asection *sec, int update)
4a6a3df4 17247{
b34976b6 17248 bfd_boolean toofar;
4a6a3df4
AO
17249 int length;
17250
17251 if (fragp
17252 && S_IS_DEFINED (fragp->fr_symbol)
991f40a9 17253 && !S_IS_WEAK (fragp->fr_symbol)
4a6a3df4
AO
17254 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17255 {
17256 addressT addr;
17257 offsetT val;
17258
17259 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17260
17261 addr = fragp->fr_address + fragp->fr_fix + 4;
17262
17263 val -= addr;
17264
17265 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17266 }
4a6a3df4 17267 else
c1f61bd2
MR
17268 /* If the symbol is not defined or it's in a different segment,
17269 we emit the long sequence. */
b34976b6 17270 toofar = TRUE;
4a6a3df4
AO
17271
17272 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17273 fragp->fr_subtype
66b3e8da
MR
17274 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17275 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
4a6a3df4
AO
17276 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17277 RELAX_BRANCH_LINK (fragp->fr_subtype),
17278 toofar);
17279
17280 length = 4;
17281 if (toofar)
17282 {
17283 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17284 length += 8;
17285
17286 if (mips_pic != NO_PIC)
17287 {
17288 /* Additional space for PIC loading of target address. */
17289 length += 8;
17290 if (mips_opts.isa == ISA_MIPS1)
17291 /* Additional space for $at-stabilizing nop. */
17292 length += 4;
17293 }
17294
17295 /* If branch is conditional. */
17296 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17297 length += 8;
17298 }
b34976b6 17299
4a6a3df4
AO
17300 return length;
17301}
17302
7bd374a4
MR
17303/* Get a FRAG's branch instruction delay slot size, either from the
17304 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17305 or SHORT_INSN_SIZE otherwise. */
17306
17307static int
17308frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size)
17309{
17310 char *buf = fragp->fr_literal + fragp->fr_fix;
17311
17312 if (al)
17313 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4;
17314 else
17315 return short_insn_size;
17316}
17317
df58fc94
RS
17318/* Compute the length of a branch sequence, and adjust the
17319 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17320 worst-case length is computed, with UPDATE being used to indicate
17321 whether an unconditional (-1), or regular (0) branch is to be
17322 computed. */
17323
17324static int
17325relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17326{
7bd374a4
MR
17327 bfd_boolean insn32 = TRUE;
17328 bfd_boolean nods = TRUE;
17329 bfd_boolean al = TRUE;
17330 int short_insn_size;
df58fc94
RS
17331 bfd_boolean toofar;
17332 int length;
17333
7bd374a4
MR
17334 if (fragp)
17335 {
17336 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
17337 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
17338 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17339 }
17340 short_insn_size = insn32 ? 4 : 2;
17341
df58fc94
RS
17342 if (fragp
17343 && S_IS_DEFINED (fragp->fr_symbol)
991f40a9 17344 && !S_IS_WEAK (fragp->fr_symbol)
df58fc94
RS
17345 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17346 {
17347 addressT addr;
17348 offsetT val;
17349
17350 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17351 /* Ignore the low bit in the target, since it will be set
17352 for a text label. */
17353 if ((val & 1) != 0)
17354 --val;
17355
17356 addr = fragp->fr_address + fragp->fr_fix + 4;
17357
17358 val -= addr;
17359
17360 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17361 }
df58fc94 17362 else
c1f61bd2
MR
17363 /* If the symbol is not defined or it's in a different segment,
17364 we emit the long sequence. */
df58fc94
RS
17365 toofar = TRUE;
17366
17367 if (fragp && update
17368 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17369 fragp->fr_subtype = (toofar
17370 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17371 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17372
17373 length = 4;
17374 if (toofar)
17375 {
17376 bfd_boolean compact_known = fragp != NULL;
17377 bfd_boolean compact = FALSE;
17378 bfd_boolean uncond;
17379
df58fc94 17380 if (fragp)
8484fb75
MR
17381 {
17382 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17383 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
8484fb75 17384 }
df58fc94
RS
17385 else
17386 uncond = update < 0;
17387
17388 /* If label is out of range, we turn branch <br>:
17389
17390 <br> label # 4 bytes
17391 0:
17392
17393 into:
17394
17395 j label # 4 bytes
8484fb75
MR
17396 nop # 2/4 bytes if
17397 # compact && (!PIC || insn32)
df58fc94
RS
17398 0:
17399 */
8484fb75
MR
17400 if ((mips_pic == NO_PIC || insn32) && (!compact_known || compact))
17401 length += short_insn_size;
df58fc94
RS
17402
17403 /* If assembling PIC code, we further turn:
17404
17405 j label # 4 bytes
17406
17407 into:
17408
17409 lw/ld at, %got(label)(gp) # 4 bytes
17410 d/addiu at, %lo(label) # 4 bytes
8484fb75 17411 jr/c at # 2/4 bytes
df58fc94
RS
17412 */
17413 if (mips_pic != NO_PIC)
8484fb75 17414 length += 4 + short_insn_size;
df58fc94 17415
7bd374a4
MR
17416 /* Add an extra nop if the jump has no compact form and we need
17417 to fill the delay slot. */
17418 if ((mips_pic == NO_PIC || al) && nods)
17419 length += (fragp
17420 ? frag_branch_delay_slot_size (fragp, al, short_insn_size)
17421 : short_insn_size);
17422
df58fc94
RS
17423 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17424
17425 <brneg> 0f # 4 bytes
8484fb75 17426 nop # 2/4 bytes if !compact
df58fc94
RS
17427 */
17428 if (!uncond)
8484fb75 17429 length += (compact_known && compact) ? 4 : 4 + short_insn_size;
df58fc94 17430 }
7bd374a4
MR
17431 else if (nods)
17432 {
17433 /* Add an extra nop to fill the delay slot. */
17434 gas_assert (fragp);
17435 length += frag_branch_delay_slot_size (fragp, al, short_insn_size);
17436 }
df58fc94
RS
17437
17438 return length;
17439}
17440
17441/* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17442 bit accordingly. */
17443
17444static int
17445relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17446{
17447 bfd_boolean toofar;
17448
df58fc94
RS
17449 if (fragp
17450 && S_IS_DEFINED (fragp->fr_symbol)
991f40a9 17451 && !S_IS_WEAK (fragp->fr_symbol)
df58fc94
RS
17452 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17453 {
17454 addressT addr;
17455 offsetT val;
17456 int type;
17457
17458 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17459 /* Ignore the low bit in the target, since it will be set
17460 for a text label. */
17461 if ((val & 1) != 0)
17462 --val;
17463
17464 /* Assume this is a 2-byte branch. */
17465 addr = fragp->fr_address + fragp->fr_fix + 2;
17466
17467 /* We try to avoid the infinite loop by not adding 2 more bytes for
17468 long branches. */
17469
17470 val -= addr;
17471
17472 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17473 if (type == 'D')
17474 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17475 else if (type == 'E')
17476 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17477 else
17478 abort ();
17479 }
17480 else
17481 /* If the symbol is not defined or it's in a different segment,
17482 we emit a normal 32-bit branch. */
17483 toofar = TRUE;
17484
17485 if (fragp && update
17486 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17487 fragp->fr_subtype
17488 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17489 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17490
17491 if (toofar)
17492 return 4;
17493
17494 return 2;
17495}
17496
252b5132
RH
17497/* Estimate the size of a frag before relaxing. Unless this is the
17498 mips16, we are not really relaxing here, and the final size is
17499 encoded in the subtype information. For the mips16, we have to
17500 decide whether we are using an extended opcode or not. */
17501
252b5132 17502int
17a2f251 17503md_estimate_size_before_relax (fragS *fragp, asection *segtype)
252b5132 17504{
5919d012 17505 int change;
252b5132 17506
4a6a3df4
AO
17507 if (RELAX_BRANCH_P (fragp->fr_subtype))
17508 {
17509
b34976b6
AM
17510 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17511
4a6a3df4
AO
17512 return fragp->fr_var;
17513 }
17514
252b5132 17515 if (RELAX_MIPS16_P (fragp->fr_subtype))
177b4a6a
AO
17516 /* We don't want to modify the EXTENDED bit here; it might get us
17517 into infinite loops. We change it only in mips_relax_frag(). */
17518 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
252b5132 17519
df58fc94
RS
17520 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17521 {
17522 int length = 4;
17523
17524 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17525 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17526 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17527 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17528 fragp->fr_var = length;
17529
17530 return length;
17531 }
17532
252b5132 17533 if (mips_pic == NO_PIC)
5919d012 17534 change = nopic_need_relax (fragp->fr_symbol, 0);
252b5132 17535 else if (mips_pic == SVR4_PIC)
5919d012 17536 change = pic_need_relax (fragp->fr_symbol, segtype);
0a44bf69
RS
17537 else if (mips_pic == VXWORKS_PIC)
17538 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17539 change = 0;
252b5132
RH
17540 else
17541 abort ();
17542
17543 if (change)
17544 {
4d7206a2 17545 fragp->fr_subtype |= RELAX_USE_SECOND;
4d7206a2 17546 return -RELAX_FIRST (fragp->fr_subtype);
252b5132 17547 }
4d7206a2
RS
17548 else
17549 return -RELAX_SECOND (fragp->fr_subtype);
252b5132
RH
17550}
17551
17552/* This is called to see whether a reloc against a defined symbol
de7e6852 17553 should be converted into a reloc against a section. */
252b5132
RH
17554
17555int
17a2f251 17556mips_fix_adjustable (fixS *fixp)
252b5132 17557{
252b5132
RH
17558 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17559 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17560 return 0;
a161fe53 17561
252b5132
RH
17562 if (fixp->fx_addsy == NULL)
17563 return 1;
a161fe53 17564
2f0c68f2
CM
17565 /* Allow relocs used for EH tables. */
17566 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17567 return 1;
17568
de7e6852
RS
17569 /* If symbol SYM is in a mergeable section, relocations of the form
17570 SYM + 0 can usually be made section-relative. The mergeable data
17571 is then identified by the section offset rather than by the symbol.
17572
17573 However, if we're generating REL LO16 relocations, the offset is split
17574 between the LO16 and parterning high part relocation. The linker will
17575 need to recalculate the complete offset in order to correctly identify
17576 the merge data.
17577
17578 The linker has traditionally not looked for the parterning high part
17579 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17580 placed anywhere. Rather than break backwards compatibility by changing
17581 this, it seems better not to force the issue, and instead keep the
17582 original symbol. This will work with either linker behavior. */
738e5348 17583 if ((lo16_reloc_p (fixp->fx_r_type)
704803a9 17584 || reloc_needs_lo_p (fixp->fx_r_type))
de7e6852
RS
17585 && HAVE_IN_PLACE_ADDENDS
17586 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17587 return 0;
17588
97f50151
MR
17589 /* There is no place to store an in-place offset for JALR relocations. */
17590 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
17591 return 0;
17592
17593 /* Likewise an in-range offset of limited PC-relative relocations may
2de39019 17594 overflow the in-place relocatable field if recalculated against the
7361da2c
AB
17595 start address of the symbol's containing section.
17596
17597 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17598 section relative to allow linker relaxations to be performed later on. */
97f50151 17599 if (limited_pcrel_reloc_p (fixp->fx_r_type)
912815f0 17600 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
1180b5a4
RS
17601 return 0;
17602
b314ec0e
RS
17603 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17604 to a floating-point stub. The same is true for non-R_MIPS16_26
17605 relocations against MIPS16 functions; in this case, the stub becomes
17606 the function's canonical address.
17607
17608 Floating-point stubs are stored in unique .mips16.call.* or
17609 .mips16.fn.* sections. If a stub T for function F is in section S,
17610 the first relocation in section S must be against F; this is how the
17611 linker determines the target function. All relocations that might
17612 resolve to T must also be against F. We therefore have the following
17613 restrictions, which are given in an intentionally-redundant way:
17614
17615 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17616 symbols.
17617
17618 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17619 if that stub might be used.
17620
17621 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17622 symbols.
17623
17624 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17625 that stub might be used.
17626
17627 There is a further restriction:
17628
df58fc94 17629 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
0e9c5a5c 17630 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
c9775dde
MR
17631 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17632 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17633 against MIPS16 or microMIPS symbols because we need to keep the
17634 MIPS16 or microMIPS symbol for the purpose of mode mismatch
a6ebf616
MR
17635 detection and JAL or BAL to JALX instruction conversion in the
17636 linker.
b314ec0e 17637
df58fc94 17638 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
507dcb32 17639 against a MIPS16 symbol. We deal with (5) by additionally leaving
0e9c5a5c 17640 alone any jump and branch relocations against a microMIPS symbol.
b314ec0e
RS
17641
17642 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17643 relocation against some symbol R, no relocation against R may be
17644 reduced. (Note that this deals with (2) as well as (1) because
17645 relocations against global symbols will never be reduced on ELF
17646 targets.) This approach is a little simpler than trying to detect
17647 stub sections, and gives the "all or nothing" per-symbol consistency
17648 that we have for MIPS16 symbols. */
f3ded42a 17649 if (fixp->fx_subsy == NULL
30c09090 17650 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
44d3da23 17651 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
0e9c5a5c
MR
17652 && (jmp_reloc_p (fixp->fx_r_type)
17653 || b_reloc_p (fixp->fx_r_type)))
44d3da23 17654 || *symbol_get_tc (fixp->fx_addsy)))
252b5132 17655 return 0;
a161fe53 17656
252b5132
RH
17657 return 1;
17658}
17659
17660/* Translate internal representation of relocation info to BFD target
17661 format. */
17662
17663arelent **
17a2f251 17664tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH
17665{
17666 static arelent *retval[4];
17667 arelent *reloc;
17668 bfd_reloc_code_real_type code;
17669
4b0cff4e 17670 memset (retval, 0, sizeof(retval));
325801bd
TS
17671 reloc = retval[0] = XCNEW (arelent);
17672 reloc->sym_ptr_ptr = XNEW (asymbol *);
49309057 17673 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH
17674 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17675
bad36eac
DJ
17676 if (fixp->fx_pcrel)
17677 {
df58fc94 17678 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
c9775dde 17679 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1
df58fc94
RS
17680 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17681 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
b47468a6 17682 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
7361da2c
AB
17683 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17684 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17685 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17686 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17687 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17688 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17689 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
bad36eac
DJ
17690
17691 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17692 Relocations want only the symbol offset. */
51f6035b
MR
17693 switch (fixp->fx_r_type)
17694 {
17695 case BFD_RELOC_MIPS_18_PCREL_S3:
17696 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
17697 break;
17698 default:
17699 reloc->addend = fixp->fx_addnumber + reloc->address;
17700 break;
17701 }
bad36eac 17702 }
17c6c9d9
MR
17703 else if (HAVE_IN_PLACE_ADDENDS
17704 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
17705 && (read_compressed_insn (fixp->fx_frag->fr_literal
17706 + fixp->fx_where, 4) >> 26) == 0x3c)
17707 {
17708 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17709 addend accordingly. */
17710 reloc->addend = fixp->fx_addnumber >> 1;
17711 }
bad36eac
DJ
17712 else
17713 reloc->addend = fixp->fx_addnumber;
252b5132 17714
438c16b8
TS
17715 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17716 entry to be used in the relocation's section offset. */
17717 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
252b5132
RH
17718 {
17719 reloc->address = reloc->addend;
17720 reloc->addend = 0;
17721 }
17722
252b5132 17723 code = fixp->fx_r_type;
252b5132 17724
bad36eac 17725 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH
17726 if (reloc->howto == NULL)
17727 {
17728 as_bad_where (fixp->fx_file, fixp->fx_line,
1661c76c
RS
17729 _("cannot represent %s relocation in this object file"
17730 " format"),
252b5132
RH
17731 bfd_get_reloc_code_name (code));
17732 retval[0] = NULL;
17733 }
17734
17735 return retval;
17736}
17737
17738/* Relax a machine dependent frag. This returns the amount by which
17739 the current size of the frag should change. */
17740
17741int
17a2f251 17742mips_relax_frag (asection *sec, fragS *fragp, long stretch)
252b5132 17743{
4a6a3df4
AO
17744 if (RELAX_BRANCH_P (fragp->fr_subtype))
17745 {
17746 offsetT old_var = fragp->fr_var;
b34976b6
AM
17747
17748 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
4a6a3df4
AO
17749
17750 return fragp->fr_var - old_var;
17751 }
17752
df58fc94
RS
17753 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17754 {
17755 offsetT old_var = fragp->fr_var;
17756 offsetT new_var = 4;
17757
17758 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17759 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17760 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17761 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17762 fragp->fr_var = new_var;
17763
17764 return new_var - old_var;
17765 }
17766
252b5132
RH
17767 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17768 return 0;
17769
88a7ef16 17770 if (mips16_extended_frag (fragp, sec, stretch))
252b5132
RH
17771 {
17772 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17773 return 0;
17774 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17775 return 2;
17776 }
17777 else
17778 {
17779 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17780 return 0;
17781 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17782 return -2;
17783 }
17784
17785 return 0;
17786}
17787
17788/* Convert a machine dependent frag. */
17789
17790void
17a2f251 17791md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
252b5132 17792{
4a6a3df4
AO
17793 if (RELAX_BRANCH_P (fragp->fr_subtype))
17794 {
4d68580a 17795 char *buf;
4a6a3df4
AO
17796 unsigned long insn;
17797 expressionS exp;
17798 fixS *fixp;
b34976b6 17799
4d68580a
RS
17800 buf = fragp->fr_literal + fragp->fr_fix;
17801 insn = read_insn (buf);
b34976b6 17802
4a6a3df4
AO
17803 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17804 {
17805 /* We generate a fixup instead of applying it right now
17806 because, if there are linker relaxations, we're going to
17807 need the relocations. */
17808 exp.X_op = O_symbol;
17809 exp.X_add_symbol = fragp->fr_symbol;
17810 exp.X_add_number = fragp->fr_offset;
17811
4d68580a
RS
17812 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17813 BFD_RELOC_16_PCREL_S2);
4a6a3df4
AO
17814 fixp->fx_file = fragp->fr_file;
17815 fixp->fx_line = fragp->fr_line;
b34976b6 17816
4d68580a 17817 buf = write_insn (buf, insn);
4a6a3df4
AO
17818 }
17819 else
17820 {
17821 int i;
17822
17823 as_warn_where (fragp->fr_file, fragp->fr_line,
1661c76c 17824 _("relaxed out-of-range branch into a jump"));
4a6a3df4
AO
17825
17826 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17827 goto uncond;
17828
17829 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17830 {
17831 /* Reverse the branch. */
17832 switch ((insn >> 28) & 0xf)
17833 {
17834 case 4:
56d438b1
CF
17835 if ((insn & 0xff000000) == 0x47000000
17836 || (insn & 0xff600000) == 0x45600000)
17837 {
17838 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17839 reversed by tweaking bit 23. */
17840 insn ^= 0x00800000;
17841 }
17842 else
17843 {
17844 /* bc[0-3][tf]l? instructions can have the condition
17845 reversed by tweaking a single TF bit, and their
17846 opcodes all have 0x4???????. */
17847 gas_assert ((insn & 0xf3e00000) == 0x41000000);
17848 insn ^= 0x00010000;
17849 }
4a6a3df4
AO
17850 break;
17851
17852 case 0:
17853 /* bltz 0x04000000 bgez 0x04010000
54f4ddb3 17854 bltzal 0x04100000 bgezal 0x04110000 */
9c2799c2 17855 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
4a6a3df4
AO
17856 insn ^= 0x00010000;
17857 break;
b34976b6 17858
4a6a3df4
AO
17859 case 1:
17860 /* beq 0x10000000 bne 0x14000000
54f4ddb3 17861 blez 0x18000000 bgtz 0x1c000000 */
4a6a3df4
AO
17862 insn ^= 0x04000000;
17863 break;
17864
17865 default:
17866 abort ();
17867 }
17868 }
17869
17870 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17871 {
17872 /* Clear the and-link bit. */
9c2799c2 17873 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
4a6a3df4 17874
54f4ddb3
TS
17875 /* bltzal 0x04100000 bgezal 0x04110000
17876 bltzall 0x04120000 bgezall 0x04130000 */
4a6a3df4
AO
17877 insn &= ~0x00100000;
17878 }
17879
17880 /* Branch over the branch (if the branch was likely) or the
17881 full jump (not likely case). Compute the offset from the
17882 current instruction to branch to. */
17883 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17884 i = 16;
17885 else
17886 {
17887 /* How many bytes in instructions we've already emitted? */
4d68580a 17888 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
17889 /* How many bytes in instructions from here to the end? */
17890 i = fragp->fr_var - i;
17891 }
17892 /* Convert to instruction count. */
17893 i >>= 2;
17894 /* Branch counts from the next instruction. */
b34976b6 17895 i--;
4a6a3df4
AO
17896 insn |= i;
17897 /* Branch over the jump. */
4d68580a 17898 buf = write_insn (buf, insn);
4a6a3df4 17899
54f4ddb3 17900 /* nop */
4d68580a 17901 buf = write_insn (buf, 0);
4a6a3df4
AO
17902
17903 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17904 {
17905 /* beql $0, $0, 2f */
17906 insn = 0x50000000;
17907 /* Compute the PC offset from the current instruction to
17908 the end of the variable frag. */
17909 /* How many bytes in instructions we've already emitted? */
4d68580a 17910 i = buf - fragp->fr_literal - fragp->fr_fix;
4a6a3df4
AO
17911 /* How many bytes in instructions from here to the end? */
17912 i = fragp->fr_var - i;
17913 /* Convert to instruction count. */
17914 i >>= 2;
17915 /* Don't decrement i, because we want to branch over the
17916 delay slot. */
4a6a3df4 17917 insn |= i;
4a6a3df4 17918
4d68580a
RS
17919 buf = write_insn (buf, insn);
17920 buf = write_insn (buf, 0);
4a6a3df4
AO
17921 }
17922
17923 uncond:
17924 if (mips_pic == NO_PIC)
17925 {
17926 /* j or jal. */
17927 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17928 ? 0x0c000000 : 0x08000000);
17929 exp.X_op = O_symbol;
17930 exp.X_add_symbol = fragp->fr_symbol;
17931 exp.X_add_number = fragp->fr_offset;
17932
4d68580a
RS
17933 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17934 FALSE, BFD_RELOC_MIPS_JMP);
4a6a3df4
AO
17935 fixp->fx_file = fragp->fr_file;
17936 fixp->fx_line = fragp->fr_line;
17937
4d68580a 17938 buf = write_insn (buf, insn);
4a6a3df4
AO
17939 }
17940 else
17941 {
66b3e8da
MR
17942 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17943
4a6a3df4 17944 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
66b3e8da
MR
17945 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17946 insn |= at << OP_SH_RT;
4a6a3df4
AO
17947 exp.X_op = O_symbol;
17948 exp.X_add_symbol = fragp->fr_symbol;
17949 exp.X_add_number = fragp->fr_offset;
17950
17951 if (fragp->fr_offset)
17952 {
17953 exp.X_add_symbol = make_expr_symbol (&exp);
17954 exp.X_add_number = 0;
17955 }
17956
4d68580a
RS
17957 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17958 FALSE, BFD_RELOC_MIPS_GOT16);
4a6a3df4
AO
17959 fixp->fx_file = fragp->fr_file;
17960 fixp->fx_line = fragp->fr_line;
17961
4d68580a 17962 buf = write_insn (buf, insn);
b34976b6 17963
4a6a3df4 17964 if (mips_opts.isa == ISA_MIPS1)
4d68580a
RS
17965 /* nop */
17966 buf = write_insn (buf, 0);
4a6a3df4
AO
17967
17968 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
66b3e8da
MR
17969 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17970 insn |= at << OP_SH_RS | at << OP_SH_RT;
4a6a3df4 17971
4d68580a
RS
17972 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17973 FALSE, BFD_RELOC_LO16);
4a6a3df4
AO
17974 fixp->fx_file = fragp->fr_file;
17975 fixp->fx_line = fragp->fr_line;
b34976b6 17976
4d68580a 17977 buf = write_insn (buf, insn);
4a6a3df4
AO
17978
17979 /* j(al)r $at. */
17980 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
66b3e8da 17981 insn = 0x0000f809;
4a6a3df4 17982 else
66b3e8da
MR
17983 insn = 0x00000008;
17984 insn |= at << OP_SH_RS;
4a6a3df4 17985
4d68580a 17986 buf = write_insn (buf, insn);
4a6a3df4
AO
17987 }
17988 }
17989
4a6a3df4 17990 fragp->fr_fix += fragp->fr_var;
4d68580a 17991 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
4a6a3df4
AO
17992 return;
17993 }
17994
df58fc94
RS
17995 /* Relax microMIPS branches. */
17996 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17997 {
4d68580a 17998 char *buf = fragp->fr_literal + fragp->fr_fix;
df58fc94 17999 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
8484fb75 18000 bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
7bd374a4 18001 bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
df58fc94
RS
18002 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18003 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
2309ddf2 18004 bfd_boolean short_ds;
df58fc94
RS
18005 unsigned long insn;
18006 expressionS exp;
18007 fixS *fixp;
18008
18009 exp.X_op = O_symbol;
18010 exp.X_add_symbol = fragp->fr_symbol;
18011 exp.X_add_number = fragp->fr_offset;
18012
18013 fragp->fr_fix += fragp->fr_var;
18014
18015 /* Handle 16-bit branches that fit or are forced to fit. */
18016 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18017 {
18018 /* We generate a fixup instead of applying it right now,
18019 because if there is linker relaxation, we're going to
18020 need the relocations. */
18021 if (type == 'D')
4d68580a 18022 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
18023 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18024 else if (type == 'E')
4d68580a 18025 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
df58fc94
RS
18026 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18027 else
18028 abort ();
18029
18030 fixp->fx_file = fragp->fr_file;
18031 fixp->fx_line = fragp->fr_line;
18032
18033 /* These relocations can have an addend that won't fit in
18034 2 octets. */
18035 fixp->fx_no_overflow = 1;
18036
18037 return;
18038 }
18039
2309ddf2 18040 /* Handle 32-bit branches that fit or are forced to fit. */
df58fc94
RS
18041 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18042 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18043 {
18044 /* We generate a fixup instead of applying it right now,
18045 because if there is linker relaxation, we're going to
18046 need the relocations. */
4d68580a
RS
18047 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18048 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
18049 fixp->fx_file = fragp->fr_file;
18050 fixp->fx_line = fragp->fr_line;
18051
18052 if (type == 0)
7bd374a4
MR
18053 {
18054 insn = read_compressed_insn (buf, 4);
18055 buf += 4;
18056
18057 if (nods)
18058 {
18059 /* Check the short-delay-slot bit. */
18060 if (!al || (insn & 0x02000000) != 0)
18061 buf = write_compressed_insn (buf, 0x0c00, 2);
18062 else
18063 buf = write_compressed_insn (buf, 0x00000000, 4);
18064 }
18065
18066 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18067 return;
18068 }
df58fc94
RS
18069 }
18070
18071 /* Relax 16-bit branches to 32-bit branches. */
18072 if (type != 0)
18073 {
4d68580a 18074 insn = read_compressed_insn (buf, 2);
df58fc94
RS
18075
18076 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18077 insn = 0x94000000; /* beq */
18078 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18079 {
18080 unsigned long regno;
18081
18082 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18083 regno = micromips_to_32_reg_d_map [regno];
18084 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18085 insn |= regno << MICROMIPSOP_SH_RS;
18086 }
18087 else
18088 abort ();
18089
18090 /* Nothing else to do, just write it out. */
18091 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18092 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18093 {
4d68580a 18094 buf = write_compressed_insn (buf, insn, 4);
7bd374a4
MR
18095 if (nods)
18096 buf = write_compressed_insn (buf, 0x0c00, 2);
4d68580a 18097 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
18098 return;
18099 }
18100 }
18101 else
4d68580a 18102 insn = read_compressed_insn (buf, 4);
df58fc94
RS
18103
18104 /* Relax 32-bit branches to a sequence of instructions. */
18105 as_warn_where (fragp->fr_file, fragp->fr_line,
1661c76c 18106 _("relaxed out-of-range branch into a jump"));
df58fc94 18107
2309ddf2 18108 /* Set the short-delay-slot bit. */
7bd374a4 18109 short_ds = !al || (insn & 0x02000000) != 0;
df58fc94
RS
18110
18111 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18112 {
18113 symbolS *l;
18114
18115 /* Reverse the branch. */
18116 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18117 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18118 insn ^= 0x20000000;
18119 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18120 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18121 || (insn & 0xffe00000) == 0x40800000 /* blez */
18122 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18123 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18124 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18125 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18126 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18127 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18128 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18129 insn ^= 0x00400000;
18130 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18131 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18132 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18133 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18134 insn ^= 0x00200000;
56d438b1
CF
18135 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
18136 BNZ.df */
18137 || (insn & 0xff600000) == 0x81600000) /* BZ.V
18138 BNZ.V */
18139 insn ^= 0x00800000;
df58fc94
RS
18140 else
18141 abort ();
18142
18143 if (al)
18144 {
18145 /* Clear the and-link and short-delay-slot bits. */
18146 gas_assert ((insn & 0xfda00000) == 0x40200000);
18147
18148 /* bltzal 0x40200000 bgezal 0x40600000 */
18149 /* bltzals 0x42200000 bgezals 0x42600000 */
18150 insn &= ~0x02200000;
18151 }
18152
18153 /* Make a label at the end for use with the branch. */
18154 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18155 micromips_label_inc ();
f3ded42a 18156 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
df58fc94
RS
18157
18158 /* Refer to it. */
4d68580a
RS
18159 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18160 BFD_RELOC_MICROMIPS_16_PCREL_S1);
df58fc94
RS
18161 fixp->fx_file = fragp->fr_file;
18162 fixp->fx_line = fragp->fr_line;
18163
18164 /* Branch over the jump. */
4d68580a 18165 buf = write_compressed_insn (buf, insn, 4);
8484fb75 18166
df58fc94 18167 if (!compact)
8484fb75
MR
18168 {
18169 /* nop */
18170 if (insn32)
18171 buf = write_compressed_insn (buf, 0x00000000, 4);
18172 else
18173 buf = write_compressed_insn (buf, 0x0c00, 2);
18174 }
df58fc94
RS
18175 }
18176
18177 if (mips_pic == NO_PIC)
18178 {
7bd374a4
MR
18179 unsigned long jal = (short_ds || nods
18180 ? 0x74000000 : 0xf4000000); /* jal/s */
2309ddf2 18181
df58fc94
RS
18182 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18183 insn = al ? jal : 0xd4000000;
18184
4d68580a
RS
18185 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18186 BFD_RELOC_MICROMIPS_JMP);
df58fc94
RS
18187 fixp->fx_file = fragp->fr_file;
18188 fixp->fx_line = fragp->fr_line;
18189
4d68580a 18190 buf = write_compressed_insn (buf, insn, 4);
8484fb75 18191
7bd374a4 18192 if (compact || nods)
8484fb75
MR
18193 {
18194 /* nop */
18195 if (insn32)
18196 buf = write_compressed_insn (buf, 0x00000000, 4);
18197 else
18198 buf = write_compressed_insn (buf, 0x0c00, 2);
18199 }
df58fc94
RS
18200 }
18201 else
18202 {
18203 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18204
18205 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18206 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18207 insn |= at << MICROMIPSOP_SH_RT;
18208
18209 if (exp.X_add_number)
18210 {
18211 exp.X_add_symbol = make_expr_symbol (&exp);
18212 exp.X_add_number = 0;
18213 }
18214
4d68580a
RS
18215 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18216 BFD_RELOC_MICROMIPS_GOT16);
df58fc94
RS
18217 fixp->fx_file = fragp->fr_file;
18218 fixp->fx_line = fragp->fr_line;
18219
4d68580a 18220 buf = write_compressed_insn (buf, insn, 4);
df58fc94
RS
18221
18222 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18223 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18224 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18225
4d68580a
RS
18226 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18227 BFD_RELOC_MICROMIPS_LO16);
df58fc94
RS
18228 fixp->fx_file = fragp->fr_file;
18229 fixp->fx_line = fragp->fr_line;
18230
4d68580a 18231 buf = write_compressed_insn (buf, insn, 4);
df58fc94 18232
8484fb75
MR
18233 if (insn32)
18234 {
18235 /* jr/jalr $at */
18236 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT;
18237 insn |= at << MICROMIPSOP_SH_RS;
18238
18239 buf = write_compressed_insn (buf, insn, 4);
df58fc94 18240
7bd374a4 18241 if (compact || nods)
8484fb75
MR
18242 /* nop */
18243 buf = write_compressed_insn (buf, 0x00000000, 4);
18244 }
18245 else
18246 {
18247 /* jr/jrc/jalr/jalrs $at */
18248 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
7bd374a4 18249 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */
8484fb75
MR
18250
18251 insn = al ? jalr : jr;
18252 insn |= at << MICROMIPSOP_SH_MJ;
18253
18254 buf = write_compressed_insn (buf, insn, 2);
7bd374a4
MR
18255 if (al && nods)
18256 {
18257 /* nop */
18258 if (short_ds)
18259 buf = write_compressed_insn (buf, 0x0c00, 2);
18260 else
18261 buf = write_compressed_insn (buf, 0x00000000, 4);
18262 }
8484fb75 18263 }
df58fc94
RS
18264 }
18265
4d68580a 18266 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
df58fc94
RS
18267 return;
18268 }
18269
252b5132
RH
18270 if (RELAX_MIPS16_P (fragp->fr_subtype))
18271 {
18272 int type;
3ccad066 18273 const struct mips_int_operand *operand;
252b5132 18274 offsetT val;
5c04167a
RS
18275 char *buf;
18276 unsigned int user_length, length;
9d862524 18277 bfd_boolean need_reloc;
252b5132 18278 unsigned long insn;
5c04167a 18279 bfd_boolean ext;
88a7ef16 18280 segT symsec;
252b5132
RH
18281
18282 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
3ccad066 18283 operand = mips16_immed_operand (type, FALSE);
252b5132 18284
5c04167a 18285 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
88a7ef16 18286 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
9d862524
MR
18287
18288 symsec = S_GET_SEGMENT (fragp->fr_symbol);
18289 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
18290 || (operand->root.type == OP_PCREL
18291 ? asec != symsec
18292 : !bfd_is_abs_section (symsec)));
18293
3ccad066 18294 if (operand->root.type == OP_PCREL)
252b5132 18295 {
3ccad066 18296 const struct mips_pcrel_operand *pcrel_op;
252b5132
RH
18297 addressT addr;
18298
3ccad066 18299 pcrel_op = (const struct mips_pcrel_operand *) operand;
252b5132
RH
18300 addr = fragp->fr_address + fragp->fr_fix;
18301
18302 /* The rules for the base address of a PC relative reloc are
18303 complicated; see mips16_extended_frag. */
3ccad066 18304 if (pcrel_op->include_isa_bit)
252b5132 18305 {
9d862524
MR
18306 if (!need_reloc)
18307 {
18308 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol)))
18309 as_bad_where (fragp->fr_file, fragp->fr_line,
18310 _("branch to a symbol in another ISA mode"));
18311 else if ((fragp->fr_offset & 0x1) != 0)
18312 as_bad_where (fragp->fr_file, fragp->fr_line,
18313 _("branch to misaligned address (0x%lx)"),
18314 (long) val);
18315 }
252b5132
RH
18316 addr += 2;
18317 if (ext)
18318 addr += 2;
18319 /* Ignore the low bit in the target, since it will be
18320 set for a text label. */
3ccad066 18321 val &= -2;
252b5132
RH
18322 }
18323 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18324 addr -= 4;
18325 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18326 addr -= 2;
18327
3ccad066 18328 addr &= -(1 << pcrel_op->align_log2);
252b5132
RH
18329 val -= addr;
18330
18331 /* Make sure the section winds up with the alignment we have
18332 assumed. */
3ccad066
RS
18333 if (operand->shift > 0)
18334 record_alignment (asec, operand->shift);
252b5132
RH
18335 }
18336
18337 if (ext
18338 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18339 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18340 as_warn_where (fragp->fr_file, fragp->fr_line,
18341 _("extended instruction in delay slot"));
18342
5c04167a 18343 buf = fragp->fr_literal + fragp->fr_fix;
252b5132 18344
4d68580a 18345 insn = read_compressed_insn (buf, 2);
5c04167a
RS
18346 if (ext)
18347 insn |= MIPS16_EXTEND;
252b5132 18348
5c04167a
RS
18349 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18350 user_length = 4;
18351 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18352 user_length = 2;
18353 else
18354 user_length = 0;
18355
9d862524 18356 if (need_reloc)
c9775dde
MR
18357 {
18358 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
18359 expressionS exp;
18360 fixS *fixp;
18361
18362 switch (type)
18363 {
18364 case 'p':
18365 case 'q':
18366 reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
18367 break;
18368 default:
18369 as_bad_where (fragp->fr_file, fragp->fr_line,
18370 _("unsupported relocation"));
18371 break;
18372 }
18373 if (reloc != BFD_RELOC_NONE)
18374 {
18375 gas_assert (ext);
18376
18377 exp.X_op = O_symbol;
18378 exp.X_add_symbol = fragp->fr_symbol;
18379 exp.X_add_number = fragp->fr_offset;
18380
18381 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp,
18382 TRUE, reloc);
18383
18384 fixp->fx_file = fragp->fr_file;
18385 fixp->fx_line = fragp->fr_line;
18386
18387 /* These relocations can have an addend that won't fit
18388 in 2 octets. */
18389 fixp->fx_no_overflow = 1;
18390 }
18391 }
88a7ef16
MR
18392 else
18393 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18394 BFD_RELOC_UNUSED, val, user_length, &insn);
252b5132 18395
5c04167a
RS
18396 length = (ext ? 4 : 2);
18397 gas_assert (mips16_opcode_length (insn) == length);
18398 write_compressed_insn (buf, insn, length);
18399 fragp->fr_fix += length;
252b5132
RH
18400 }
18401 else
18402 {
df58fc94
RS
18403 relax_substateT subtype = fragp->fr_subtype;
18404 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18405 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
4d7206a2
RS
18406 int first, second;
18407 fixS *fixp;
252b5132 18408
df58fc94
RS
18409 first = RELAX_FIRST (subtype);
18410 second = RELAX_SECOND (subtype);
4d7206a2 18411 fixp = (fixS *) fragp->fr_opcode;
252b5132 18412
df58fc94
RS
18413 /* If the delay slot chosen does not match the size of the instruction,
18414 then emit a warning. */
18415 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18416 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18417 {
18418 relax_substateT s;
18419 const char *msg;
18420
18421 s = subtype & (RELAX_DELAY_SLOT_16BIT
18422 | RELAX_DELAY_SLOT_SIZE_FIRST
18423 | RELAX_DELAY_SLOT_SIZE_SECOND);
18424 msg = macro_warning (s);
18425 if (msg != NULL)
db9b2be4 18426 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94
RS
18427 subtype &= ~s;
18428 }
18429
584892a6 18430 /* Possibly emit a warning if we've chosen the longer option. */
df58fc94 18431 if (use_second == second_longer)
584892a6 18432 {
df58fc94
RS
18433 relax_substateT s;
18434 const char *msg;
18435
18436 s = (subtype
18437 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18438 msg = macro_warning (s);
18439 if (msg != NULL)
db9b2be4 18440 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
df58fc94 18441 subtype &= ~s;
584892a6
RS
18442 }
18443
4d7206a2
RS
18444 /* Go through all the fixups for the first sequence. Disable them
18445 (by marking them as done) if we're going to use the second
18446 sequence instead. */
18447 while (fixp
18448 && fixp->fx_frag == fragp
18449 && fixp->fx_where < fragp->fr_fix - second)
18450 {
df58fc94 18451 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
18452 fixp->fx_done = 1;
18453 fixp = fixp->fx_next;
18454 }
252b5132 18455
4d7206a2
RS
18456 /* Go through the fixups for the second sequence. Disable them if
18457 we're going to use the first sequence, otherwise adjust their
18458 addresses to account for the relaxation. */
18459 while (fixp && fixp->fx_frag == fragp)
18460 {
df58fc94 18461 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
18462 fixp->fx_where -= first;
18463 else
18464 fixp->fx_done = 1;
18465 fixp = fixp->fx_next;
18466 }
18467
18468 /* Now modify the frag contents. */
df58fc94 18469 if (subtype & RELAX_USE_SECOND)
4d7206a2
RS
18470 {
18471 char *start;
18472
18473 start = fragp->fr_literal + fragp->fr_fix - first - second;
18474 memmove (start, start + first, second);
18475 fragp->fr_fix -= first;
18476 }
18477 else
18478 fragp->fr_fix -= second;
252b5132
RH
18479 }
18480}
18481
252b5132
RH
18482/* This function is called after the relocs have been generated.
18483 We've been storing mips16 text labels as odd. Here we convert them
18484 back to even for the convenience of the debugger. */
18485
18486void
17a2f251 18487mips_frob_file_after_relocs (void)
252b5132
RH
18488{
18489 asymbol **syms;
18490 unsigned int count, i;
18491
252b5132
RH
18492 syms = bfd_get_outsymbols (stdoutput);
18493 count = bfd_get_symcount (stdoutput);
18494 for (i = 0; i < count; i++, syms++)
df58fc94
RS
18495 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18496 && ((*syms)->value & 1) != 0)
18497 {
18498 (*syms)->value &= ~1;
18499 /* If the symbol has an odd size, it was probably computed
18500 incorrectly, so adjust that as well. */
18501 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18502 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18503 }
252b5132
RH
18504}
18505
a1facbec
MR
18506/* This function is called whenever a label is defined, including fake
18507 labels instantiated off the dot special symbol. It is used when
18508 handling branch delays; if a branch has a label, we assume we cannot
18509 move it. This also bumps the value of the symbol by 1 in compressed
18510 code. */
252b5132 18511
e1b47bd5 18512static void
a1facbec 18513mips_record_label (symbolS *sym)
252b5132 18514{
a8dbcb85 18515 segment_info_type *si = seg_info (now_seg);
252b5132
RH
18516 struct insn_label_list *l;
18517
18518 if (free_insn_labels == NULL)
325801bd 18519 l = XNEW (struct insn_label_list);
252b5132
RH
18520 else
18521 {
18522 l = free_insn_labels;
18523 free_insn_labels = l->next;
18524 }
18525
18526 l->label = sym;
a8dbcb85
TS
18527 l->next = si->label_list;
18528 si->label_list = l;
a1facbec 18529}
07a53e5c 18530
a1facbec
MR
18531/* This function is called as tc_frob_label() whenever a label is defined
18532 and adds a DWARF-2 record we only want for true labels. */
18533
18534void
18535mips_define_label (symbolS *sym)
18536{
18537 mips_record_label (sym);
07a53e5c 18538 dwarf2_emit_label (sym);
252b5132 18539}
e1b47bd5
RS
18540
18541/* This function is called by tc_new_dot_label whenever a new dot symbol
18542 is defined. */
18543
18544void
18545mips_add_dot_label (symbolS *sym)
18546{
18547 mips_record_label (sym);
18548 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18549 mips_compressed_mark_label (sym);
18550}
252b5132 18551\f
351cdf24
MF
18552/* Converting ASE flags from internal to .MIPS.abiflags values. */
18553static unsigned int
18554mips_convert_ase_flags (int ase)
18555{
18556 unsigned int ext_ases = 0;
18557
18558 if (ase & ASE_DSP)
18559 ext_ases |= AFL_ASE_DSP;
18560 if (ase & ASE_DSPR2)
18561 ext_ases |= AFL_ASE_DSPR2;
8f4f9071
MF
18562 if (ase & ASE_DSPR3)
18563 ext_ases |= AFL_ASE_DSPR3;
351cdf24
MF
18564 if (ase & ASE_EVA)
18565 ext_ases |= AFL_ASE_EVA;
18566 if (ase & ASE_MCU)
18567 ext_ases |= AFL_ASE_MCU;
18568 if (ase & ASE_MDMX)
18569 ext_ases |= AFL_ASE_MDMX;
18570 if (ase & ASE_MIPS3D)
18571 ext_ases |= AFL_ASE_MIPS3D;
18572 if (ase & ASE_MT)
18573 ext_ases |= AFL_ASE_MT;
18574 if (ase & ASE_SMARTMIPS)
18575 ext_ases |= AFL_ASE_SMARTMIPS;
18576 if (ase & ASE_VIRT)
18577 ext_ases |= AFL_ASE_VIRT;
18578 if (ase & ASE_MSA)
18579 ext_ases |= AFL_ASE_MSA;
18580 if (ase & ASE_XPA)
18581 ext_ases |= AFL_ASE_XPA;
18582
18583 return ext_ases;
18584}
252b5132
RH
18585/* Some special processing for a MIPS ELF file. */
18586
18587void
17a2f251 18588mips_elf_final_processing (void)
252b5132 18589{
351cdf24
MF
18590 int fpabi;
18591 Elf_Internal_ABIFlags_v0 flags;
18592
18593 flags.version = 0;
18594 flags.isa_rev = 0;
18595 switch (file_mips_opts.isa)
18596 {
18597 case INSN_ISA1:
18598 flags.isa_level = 1;
18599 break;
18600 case INSN_ISA2:
18601 flags.isa_level = 2;
18602 break;
18603 case INSN_ISA3:
18604 flags.isa_level = 3;
18605 break;
18606 case INSN_ISA4:
18607 flags.isa_level = 4;
18608 break;
18609 case INSN_ISA5:
18610 flags.isa_level = 5;
18611 break;
18612 case INSN_ISA32:
18613 flags.isa_level = 32;
18614 flags.isa_rev = 1;
18615 break;
18616 case INSN_ISA32R2:
18617 flags.isa_level = 32;
18618 flags.isa_rev = 2;
18619 break;
18620 case INSN_ISA32R3:
18621 flags.isa_level = 32;
18622 flags.isa_rev = 3;
18623 break;
18624 case INSN_ISA32R5:
18625 flags.isa_level = 32;
18626 flags.isa_rev = 5;
18627 break;
09c14161
MF
18628 case INSN_ISA32R6:
18629 flags.isa_level = 32;
18630 flags.isa_rev = 6;
18631 break;
351cdf24
MF
18632 case INSN_ISA64:
18633 flags.isa_level = 64;
18634 flags.isa_rev = 1;
18635 break;
18636 case INSN_ISA64R2:
18637 flags.isa_level = 64;
18638 flags.isa_rev = 2;
18639 break;
18640 case INSN_ISA64R3:
18641 flags.isa_level = 64;
18642 flags.isa_rev = 3;
18643 break;
18644 case INSN_ISA64R5:
18645 flags.isa_level = 64;
18646 flags.isa_rev = 5;
18647 break;
09c14161
MF
18648 case INSN_ISA64R6:
18649 flags.isa_level = 64;
18650 flags.isa_rev = 6;
18651 break;
351cdf24
MF
18652 }
18653
18654 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
18655 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
18656 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
18657 : (file_mips_opts.fp == 64) ? AFL_REG_64
18658 : AFL_REG_32;
18659 flags.cpr2_size = AFL_REG_NONE;
18660 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18661 Tag_GNU_MIPS_ABI_FP);
18662 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
18663 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
18664 if (file_ase_mips16)
18665 flags.ases |= AFL_ASE_MIPS16;
18666 if (file_ase_micromips)
18667 flags.ases |= AFL_ASE_MICROMIPS;
18668 flags.flags1 = 0;
18669 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18670 || file_mips_opts.fp == 64)
18671 && file_mips_opts.oddspreg)
18672 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
18673 flags.flags2 = 0;
18674
18675 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
18676 ((Elf_External_ABIFlags_v0 *)
18677 mips_flags_frag));
18678
252b5132 18679 /* Write out the register information. */
316f5878 18680 if (mips_abi != N64_ABI)
252b5132
RH
18681 {
18682 Elf32_RegInfo s;
18683
18684 s.ri_gprmask = mips_gprmask;
18685 s.ri_cprmask[0] = mips_cprmask[0];
18686 s.ri_cprmask[1] = mips_cprmask[1];
18687 s.ri_cprmask[2] = mips_cprmask[2];
18688 s.ri_cprmask[3] = mips_cprmask[3];
18689 /* The gp_value field is set by the MIPS ELF backend. */
18690
18691 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18692 ((Elf32_External_RegInfo *)
18693 mips_regmask_frag));
18694 }
18695 else
18696 {
18697 Elf64_Internal_RegInfo s;
18698
18699 s.ri_gprmask = mips_gprmask;
18700 s.ri_pad = 0;
18701 s.ri_cprmask[0] = mips_cprmask[0];
18702 s.ri_cprmask[1] = mips_cprmask[1];
18703 s.ri_cprmask[2] = mips_cprmask[2];
18704 s.ri_cprmask[3] = mips_cprmask[3];
18705 /* The gp_value field is set by the MIPS ELF backend. */
18706
18707 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18708 ((Elf64_External_RegInfo *)
18709 mips_regmask_frag));
18710 }
18711
18712 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18713 sort of BFD interface for this. */
18714 if (mips_any_noreorder)
18715 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18716 if (mips_pic != NO_PIC)
143d77c5 18717 {
8b828383 18718 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
143d77c5
EC
18719 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18720 }
18721 if (mips_abicalls)
18722 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
252b5132 18723
b015e599
AP
18724 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18725 defined at present; this might need to change in future. */
a4672219
TS
18726 if (file_ase_mips16)
18727 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
df58fc94
RS
18728 if (file_ase_micromips)
18729 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
919731af 18730 if (file_mips_opts.ase & ASE_MDMX)
deec1734 18731 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
1f25f5d3 18732
bdaaa2e1 18733 /* Set the MIPS ELF ABI flags. */
316f5878 18734 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
252b5132 18735 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
316f5878 18736 else if (mips_abi == O64_ABI)
252b5132 18737 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
316f5878 18738 else if (mips_abi == EABI_ABI)
252b5132 18739 {
bad1aba3 18740 if (file_mips_opts.gp == 64)
252b5132
RH
18741 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18742 else
18743 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18744 }
316f5878 18745 else if (mips_abi == N32_ABI)
be00bddd
TS
18746 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18747
c9914766 18748 /* Nothing to do for N64_ABI. */
252b5132
RH
18749
18750 if (mips_32bitmode)
18751 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
ad3fea08 18752
7361da2c 18753 if (mips_nan2008 == 1)
ba92f887
MR
18754 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18755
ad3fea08 18756 /* 32 bit code with 64 bit FP registers. */
351cdf24
MF
18757 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18758 Tag_GNU_MIPS_ABI_FP);
18759 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
f1c38003 18760 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
252b5132 18761}
252b5132 18762\f
beae10d5 18763typedef struct proc {
9b2f1d35
EC
18764 symbolS *func_sym;
18765 symbolS *func_end_sym;
beae10d5
KH
18766 unsigned long reg_mask;
18767 unsigned long reg_offset;
18768 unsigned long fpreg_mask;
18769 unsigned long fpreg_offset;
18770 unsigned long frame_offset;
18771 unsigned long frame_reg;
18772 unsigned long pc_reg;
18773} procS;
252b5132
RH
18774
18775static procS cur_proc;
18776static procS *cur_proc_ptr;
18777static int numprocs;
18778
df58fc94
RS
18779/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18780 as "2", and a normal nop as "0". */
18781
18782#define NOP_OPCODE_MIPS 0
18783#define NOP_OPCODE_MIPS16 1
18784#define NOP_OPCODE_MICROMIPS 2
742a56fe
RS
18785
18786char
18787mips_nop_opcode (void)
18788{
df58fc94
RS
18789 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18790 return NOP_OPCODE_MICROMIPS;
18791 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18792 return NOP_OPCODE_MIPS16;
18793 else
18794 return NOP_OPCODE_MIPS;
742a56fe
RS
18795}
18796
df58fc94
RS
18797/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18798 32-bit microMIPS NOPs here (if applicable). */
a19d8eb0 18799
0a9ef439 18800void
17a2f251 18801mips_handle_align (fragS *fragp)
a19d8eb0 18802{
df58fc94 18803 char nop_opcode;
742a56fe 18804 char *p;
c67a084a
NC
18805 int bytes, size, excess;
18806 valueT opcode;
742a56fe 18807
0a9ef439
RH
18808 if (fragp->fr_type != rs_align_code)
18809 return;
18810
742a56fe 18811 p = fragp->fr_literal + fragp->fr_fix;
df58fc94
RS
18812 nop_opcode = *p;
18813 switch (nop_opcode)
a19d8eb0 18814 {
df58fc94
RS
18815 case NOP_OPCODE_MICROMIPS:
18816 opcode = micromips_nop32_insn.insn_opcode;
18817 size = 4;
18818 break;
18819 case NOP_OPCODE_MIPS16:
c67a084a
NC
18820 opcode = mips16_nop_insn.insn_opcode;
18821 size = 2;
df58fc94
RS
18822 break;
18823 case NOP_OPCODE_MIPS:
18824 default:
c67a084a
NC
18825 opcode = nop_insn.insn_opcode;
18826 size = 4;
df58fc94 18827 break;
c67a084a 18828 }
a19d8eb0 18829
c67a084a
NC
18830 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18831 excess = bytes % size;
df58fc94
RS
18832
18833 /* Handle the leading part if we're not inserting a whole number of
18834 instructions, and make it the end of the fixed part of the frag.
18835 Try to fit in a short microMIPS NOP if applicable and possible,
18836 and use zeroes otherwise. */
18837 gas_assert (excess < 4);
18838 fragp->fr_fix += excess;
18839 switch (excess)
c67a084a 18840 {
df58fc94
RS
18841 case 3:
18842 *p++ = '\0';
18843 /* Fall through. */
18844 case 2:
833794fc 18845 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
df58fc94 18846 {
4d68580a 18847 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
df58fc94
RS
18848 break;
18849 }
18850 *p++ = '\0';
18851 /* Fall through. */
18852 case 1:
18853 *p++ = '\0';
18854 /* Fall through. */
18855 case 0:
18856 break;
a19d8eb0 18857 }
c67a084a
NC
18858
18859 md_number_to_chars (p, opcode, size);
18860 fragp->fr_var = size;
a19d8eb0
CP
18861}
18862
252b5132 18863static long
17a2f251 18864get_number (void)
252b5132
RH
18865{
18866 int negative = 0;
18867 long val = 0;
18868
18869 if (*input_line_pointer == '-')
18870 {
18871 ++input_line_pointer;
18872 negative = 1;
18873 }
3882b010 18874 if (!ISDIGIT (*input_line_pointer))
956cd1d6 18875 as_bad (_("expected simple number"));
252b5132
RH
18876 if (input_line_pointer[0] == '0')
18877 {
18878 if (input_line_pointer[1] == 'x')
18879 {
18880 input_line_pointer += 2;
3882b010 18881 while (ISXDIGIT (*input_line_pointer))
252b5132
RH
18882 {
18883 val <<= 4;
18884 val |= hex_value (*input_line_pointer++);
18885 }
18886 return negative ? -val : val;
18887 }
18888 else
18889 {
18890 ++input_line_pointer;
3882b010 18891 while (ISDIGIT (*input_line_pointer))
252b5132
RH
18892 {
18893 val <<= 3;
18894 val |= *input_line_pointer++ - '0';
18895 }
18896 return negative ? -val : val;
18897 }
18898 }
3882b010 18899 if (!ISDIGIT (*input_line_pointer))
252b5132
RH
18900 {
18901 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18902 *input_line_pointer, *input_line_pointer);
956cd1d6 18903 as_warn (_("invalid number"));
252b5132
RH
18904 return -1;
18905 }
3882b010 18906 while (ISDIGIT (*input_line_pointer))
252b5132
RH
18907 {
18908 val *= 10;
18909 val += *input_line_pointer++ - '0';
18910 }
18911 return negative ? -val : val;
18912}
18913
18914/* The .file directive; just like the usual .file directive, but there
c5dd6aab
DJ
18915 is an initial number which is the ECOFF file index. In the non-ECOFF
18916 case .file implies DWARF-2. */
18917
18918static void
17a2f251 18919s_mips_file (int x ATTRIBUTE_UNUSED)
c5dd6aab 18920{
ecb4347a
DJ
18921 static int first_file_directive = 0;
18922
c5dd6aab
DJ
18923 if (ECOFF_DEBUGGING)
18924 {
18925 get_number ();
18926 s_app_file (0);
18927 }
18928 else
ecb4347a
DJ
18929 {
18930 char *filename;
18931
18932 filename = dwarf2_directive_file (0);
18933
18934 /* Versions of GCC up to 3.1 start files with a ".file"
18935 directive even for stabs output. Make sure that this
18936 ".file" is handled. Note that you need a version of GCC
18937 after 3.1 in order to support DWARF-2 on MIPS. */
18938 if (filename != NULL && ! first_file_directive)
18939 {
18940 (void) new_logical_line (filename, -1);
c04f5787 18941 s_app_file_string (filename, 0);
ecb4347a
DJ
18942 }
18943 first_file_directive = 1;
18944 }
c5dd6aab
DJ
18945}
18946
18947/* The .loc directive, implying DWARF-2. */
252b5132
RH
18948
18949static void
17a2f251 18950s_mips_loc (int x ATTRIBUTE_UNUSED)
252b5132 18951{
c5dd6aab
DJ
18952 if (!ECOFF_DEBUGGING)
18953 dwarf2_directive_loc (0);
252b5132
RH
18954}
18955
252b5132
RH
18956/* The .end directive. */
18957
18958static void
17a2f251 18959s_mips_end (int x ATTRIBUTE_UNUSED)
252b5132
RH
18960{
18961 symbolS *p;
252b5132 18962
7a621144
DJ
18963 /* Following functions need their own .frame and .cprestore directives. */
18964 mips_frame_reg_valid = 0;
18965 mips_cprestore_valid = 0;
18966
252b5132
RH
18967 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18968 {
18969 p = get_symbol ();
18970 demand_empty_rest_of_line ();
18971 }
18972 else
18973 p = NULL;
18974
14949570 18975 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
252b5132
RH
18976 as_warn (_(".end not in text section"));
18977
18978 if (!cur_proc_ptr)
18979 {
1661c76c 18980 as_warn (_(".end directive without a preceding .ent directive"));
252b5132
RH
18981 demand_empty_rest_of_line ();
18982 return;
18983 }
18984
18985 if (p != NULL)
18986 {
9c2799c2 18987 gas_assert (S_GET_NAME (p));
9b2f1d35 18988 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
1661c76c 18989 as_warn (_(".end symbol does not match .ent symbol"));
ecb4347a
DJ
18990
18991 if (debug_type == DEBUG_STABS)
18992 stabs_generate_asm_endfunc (S_GET_NAME (p),
18993 S_GET_NAME (p));
252b5132
RH
18994 }
18995 else
18996 as_warn (_(".end directive missing or unknown symbol"));
18997
9b2f1d35
EC
18998 /* Create an expression to calculate the size of the function. */
18999 if (p && cur_proc_ptr)
19000 {
19001 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
325801bd 19002 expressionS *exp = XNEW (expressionS);
9b2f1d35
EC
19003
19004 obj->size = exp;
19005 exp->X_op = O_subtract;
19006 exp->X_add_symbol = symbol_temp_new_now ();
19007 exp->X_op_symbol = p;
19008 exp->X_add_number = 0;
19009
19010 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19011 }
19012
ecb4347a 19013 /* Generate a .pdr section. */
f3ded42a 19014 if (!ECOFF_DEBUGGING && mips_flag_pdr)
ecb4347a
DJ
19015 {
19016 segT saved_seg = now_seg;
19017 subsegT saved_subseg = now_subseg;
ecb4347a
DJ
19018 expressionS exp;
19019 char *fragp;
252b5132 19020
252b5132 19021#ifdef md_flush_pending_output
ecb4347a 19022 md_flush_pending_output ();
252b5132
RH
19023#endif
19024
9c2799c2 19025 gas_assert (pdr_seg);
ecb4347a 19026 subseg_set (pdr_seg, 0);
252b5132 19027
ecb4347a
DJ
19028 /* Write the symbol. */
19029 exp.X_op = O_symbol;
19030 exp.X_add_symbol = p;
19031 exp.X_add_number = 0;
19032 emit_expr (&exp, 4);
252b5132 19033
ecb4347a 19034 fragp = frag_more (7 * 4);
252b5132 19035
17a2f251
TS
19036 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19037 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19038 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19039 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19040 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19041 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19042 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
252b5132 19043
ecb4347a
DJ
19044 subseg_set (saved_seg, saved_subseg);
19045 }
252b5132
RH
19046
19047 cur_proc_ptr = NULL;
19048}
19049
19050/* The .aent and .ent directives. */
19051
19052static void
17a2f251 19053s_mips_ent (int aent)
252b5132 19054{
252b5132 19055 symbolS *symbolP;
252b5132
RH
19056
19057 symbolP = get_symbol ();
19058 if (*input_line_pointer == ',')
f9419b05 19059 ++input_line_pointer;
252b5132 19060 SKIP_WHITESPACE ();
3882b010 19061 if (ISDIGIT (*input_line_pointer)
d9a62219 19062 || *input_line_pointer == '-')
874e8986 19063 get_number ();
252b5132 19064
14949570 19065 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
1661c76c 19066 as_warn (_(".ent or .aent not in text section"));
252b5132
RH
19067
19068 if (!aent && cur_proc_ptr)
9a41af64 19069 as_warn (_("missing .end"));
252b5132
RH
19070
19071 if (!aent)
19072 {
7a621144
DJ
19073 /* This function needs its own .frame and .cprestore directives. */
19074 mips_frame_reg_valid = 0;
19075 mips_cprestore_valid = 0;
19076
252b5132
RH
19077 cur_proc_ptr = &cur_proc;
19078 memset (cur_proc_ptr, '\0', sizeof (procS));
19079
9b2f1d35 19080 cur_proc_ptr->func_sym = symbolP;
252b5132 19081
f9419b05 19082 ++numprocs;
ecb4347a
DJ
19083
19084 if (debug_type == DEBUG_STABS)
19085 stabs_generate_asm_func (S_GET_NAME (symbolP),
19086 S_GET_NAME (symbolP));
252b5132
RH
19087 }
19088
7c0fc524
MR
19089 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19090
252b5132
RH
19091 demand_empty_rest_of_line ();
19092}
19093
19094/* The .frame directive. If the mdebug section is present (IRIX 5 native)
bdaaa2e1 19095 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
252b5132 19096 s_mips_frame is used so that we can set the PDR information correctly.
bdaaa2e1 19097 We can't use the ecoff routines because they make reference to the ecoff
252b5132
RH
19098 symbol table (in the mdebug section). */
19099
19100static void
17a2f251 19101s_mips_frame (int ignore ATTRIBUTE_UNUSED)
252b5132 19102{
f3ded42a
RS
19103 if (ECOFF_DEBUGGING)
19104 s_ignore (ignore);
19105 else
ecb4347a
DJ
19106 {
19107 long val;
252b5132 19108
ecb4347a
DJ
19109 if (cur_proc_ptr == (procS *) NULL)
19110 {
19111 as_warn (_(".frame outside of .ent"));
19112 demand_empty_rest_of_line ();
19113 return;
19114 }
252b5132 19115
ecb4347a
DJ
19116 cur_proc_ptr->frame_reg = tc_get_register (1);
19117
19118 SKIP_WHITESPACE ();
19119 if (*input_line_pointer++ != ','
19120 || get_absolute_expression_and_terminator (&val) != ',')
19121 {
1661c76c 19122 as_warn (_("bad .frame directive"));
ecb4347a
DJ
19123 --input_line_pointer;
19124 demand_empty_rest_of_line ();
19125 return;
19126 }
252b5132 19127
ecb4347a
DJ
19128 cur_proc_ptr->frame_offset = val;
19129 cur_proc_ptr->pc_reg = tc_get_register (0);
252b5132 19130
252b5132 19131 demand_empty_rest_of_line ();
252b5132 19132 }
252b5132
RH
19133}
19134
bdaaa2e1
KH
19135/* The .fmask and .mask directives. If the mdebug section is present
19136 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
252b5132 19137 embedded targets, s_mips_mask is used so that we can set the PDR
bdaaa2e1 19138 information correctly. We can't use the ecoff routines because they
252b5132
RH
19139 make reference to the ecoff symbol table (in the mdebug section). */
19140
19141static void
17a2f251 19142s_mips_mask (int reg_type)
252b5132 19143{
f3ded42a
RS
19144 if (ECOFF_DEBUGGING)
19145 s_ignore (reg_type);
19146 else
252b5132 19147 {
ecb4347a 19148 long mask, off;
252b5132 19149
ecb4347a
DJ
19150 if (cur_proc_ptr == (procS *) NULL)
19151 {
19152 as_warn (_(".mask/.fmask outside of .ent"));
19153 demand_empty_rest_of_line ();
19154 return;
19155 }
252b5132 19156
ecb4347a
DJ
19157 if (get_absolute_expression_and_terminator (&mask) != ',')
19158 {
1661c76c 19159 as_warn (_("bad .mask/.fmask directive"));
ecb4347a
DJ
19160 --input_line_pointer;
19161 demand_empty_rest_of_line ();
19162 return;
19163 }
252b5132 19164
ecb4347a
DJ
19165 off = get_absolute_expression ();
19166
19167 if (reg_type == 'F')
19168 {
19169 cur_proc_ptr->fpreg_mask = mask;
19170 cur_proc_ptr->fpreg_offset = off;
19171 }
19172 else
19173 {
19174 cur_proc_ptr->reg_mask = mask;
19175 cur_proc_ptr->reg_offset = off;
19176 }
19177
19178 demand_empty_rest_of_line ();
252b5132 19179 }
252b5132
RH
19180}
19181
316f5878
RS
19182/* A table describing all the processors gas knows about. Names are
19183 matched in the order listed.
e7af610e 19184
316f5878
RS
19185 To ease comparison, please keep this table in the same order as
19186 gcc's mips_cpu_info_table[]. */
e972090a
NC
19187static const struct mips_cpu_info mips_cpu_info_table[] =
19188{
316f5878 19189 /* Entries for generic ISAs */
d16afab6
RS
19190 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19191 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19192 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19193 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19194 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19195 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19196 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
ae52f483
AB
19197 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
19198 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
7361da2c 19199 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
d16afab6
RS
19200 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19201 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
ae52f483
AB
19202 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
19203 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
7361da2c 19204 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
316f5878
RS
19205
19206 /* MIPS I */
d16afab6
RS
19207 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19208 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19209 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
316f5878
RS
19210
19211 /* MIPS II */
d16afab6 19212 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
316f5878
RS
19213
19214 /* MIPS III */
d16afab6
RS
19215 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19216 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19217 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19218 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19219 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19220 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19221 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19222 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19223 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19224 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19225 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19226 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19227 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
b15591bb 19228 /* ST Microelectronics Loongson 2E and 2F cores */
d16afab6
RS
19229 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19230 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
316f5878
RS
19231
19232 /* MIPS IV */
d16afab6
RS
19233 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19234 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19235 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19236 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19237 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19238 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19239 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19240 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19241 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19242 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19243 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19244 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19245 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19246 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19247 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
316f5878
RS
19248
19249 /* MIPS 32 */
d16afab6
RS
19250 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19251 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19252 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19253 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
ad3fea08
TS
19254
19255 /* MIPS 32 Release 2 */
d16afab6
RS
19256 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19257 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19258 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19259 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19260 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19261 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19262 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19263 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19264 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19265 ISA_MIPS32R2, CPU_MIPS32R2 },
19266 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19267 ISA_MIPS32R2, CPU_MIPS32R2 },
19268 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19269 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19270 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19271 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 19272 /* Deprecated forms of the above. */
d16afab6
RS
19273 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19274 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 19275 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
d16afab6
RS
19276 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19277 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19278 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19279 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 19280 /* Deprecated forms of the above. */
d16afab6
RS
19281 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19282 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 19283 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
d16afab6
RS
19284 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19285 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19286 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19287 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 19288 /* Deprecated forms of the above. */
d16afab6
RS
19289 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19290 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
711eefe4 19291 /* 34Kn is a 34kc without DSP. */
d16afab6 19292 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
01fd108f 19293 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
d16afab6
RS
19294 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19295 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19296 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19297 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19298 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
0fdf1951 19299 /* Deprecated forms of the above. */
d16afab6
RS
19300 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19301 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
30f8113a 19302 /* 1004K cores are multiprocessor versions of the 34K. */
d16afab6
RS
19303 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19304 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19305 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19306 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
77403ce9
RS
19307 /* interaptiv is the new name for 1004kf */
19308 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
c6e5c03a
RS
19309 /* M5100 family */
19310 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19311 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
bbaa46c0 19312 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
134c0c8b 19313 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
32b26a03 19314
316f5878 19315 /* MIPS 64 */
d16afab6
RS
19316 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19317 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19318 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19319 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
ad3fea08 19320
c7a23324 19321 /* Broadcom SB-1 CPU core */
d16afab6 19322 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
1e85aad8 19323 /* Broadcom SB-1A CPU core */
d16afab6 19324 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
3739860c 19325
4ba154f5 19326 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
e7af610e 19327
ed163775
MR
19328 /* MIPS 64 Release 2 */
19329
967344c6 19330 /* Cavium Networks Octeon CPU core */
d16afab6
RS
19331 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19332 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19333 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
2c629856 19334 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
967344c6 19335
52b6b6b9 19336 /* RMI Xlr */
d16afab6 19337 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
52b6b6b9 19338
55a36193
MK
19339 /* Broadcom XLP.
19340 XLP is mostly like XLR, with the prominent exception that it is
19341 MIPS64R2 rather than MIPS64. */
d16afab6 19342 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
55a36193 19343
a4968f42 19344 /* MIPS 64 Release 6 */
7ef0d297 19345 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
a4968f42 19346 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
7ef0d297 19347
316f5878 19348 /* End marker */
d16afab6 19349 { NULL, 0, 0, 0, 0 }
316f5878 19350};
e7af610e 19351
84ea6cf2 19352
316f5878
RS
19353/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19354 with a final "000" replaced by "k". Ignore case.
e7af610e 19355
316f5878 19356 Note: this function is shared between GCC and GAS. */
c6c98b38 19357
b34976b6 19358static bfd_boolean
17a2f251 19359mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
19360{
19361 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19362 given++, canonical++;
19363
19364 return ((*given == 0 && *canonical == 0)
19365 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19366}
19367
19368
19369/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19370 CPU name. We've traditionally allowed a lot of variation here.
19371
19372 Note: this function is shared between GCC and GAS. */
19373
b34976b6 19374static bfd_boolean
17a2f251 19375mips_matching_cpu_name_p (const char *canonical, const char *given)
316f5878
RS
19376{
19377 /* First see if the name matches exactly, or with a final "000"
19378 turned into "k". */
19379 if (mips_strict_matching_cpu_name_p (canonical, given))
b34976b6 19380 return TRUE;
316f5878
RS
19381
19382 /* If not, try comparing based on numerical designation alone.
19383 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19384 if (TOLOWER (*given) == 'r')
19385 given++;
19386 if (!ISDIGIT (*given))
b34976b6 19387 return FALSE;
316f5878
RS
19388
19389 /* Skip over some well-known prefixes in the canonical name,
19390 hoping to find a number there too. */
19391 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19392 canonical += 2;
19393 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19394 canonical += 2;
19395 else if (TOLOWER (canonical[0]) == 'r')
19396 canonical += 1;
19397
19398 return mips_strict_matching_cpu_name_p (canonical, given);
19399}
19400
19401
19402/* Parse an option that takes the name of a processor as its argument.
19403 OPTION is the name of the option and CPU_STRING is the argument.
19404 Return the corresponding processor enumeration if the CPU_STRING is
19405 recognized, otherwise report an error and return null.
19406
19407 A similar function exists in GCC. */
e7af610e
NC
19408
19409static const struct mips_cpu_info *
17a2f251 19410mips_parse_cpu (const char *option, const char *cpu_string)
e7af610e 19411{
316f5878 19412 const struct mips_cpu_info *p;
e7af610e 19413
316f5878
RS
19414 /* 'from-abi' selects the most compatible architecture for the given
19415 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19416 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19417 version. Look first at the -mgp options, if given, otherwise base
19418 the choice on MIPS_DEFAULT_64BIT.
e7af610e 19419
316f5878
RS
19420 Treat NO_ABI like the EABIs. One reason to do this is that the
19421 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19422 architecture. This code picks MIPS I for 'mips' and MIPS III for
19423 'mips64', just as we did in the days before 'from-abi'. */
19424 if (strcasecmp (cpu_string, "from-abi") == 0)
19425 {
19426 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19427 return mips_cpu_info_from_isa (ISA_MIPS1);
19428
19429 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19430 return mips_cpu_info_from_isa (ISA_MIPS3);
19431
bad1aba3 19432 if (file_mips_opts.gp >= 0)
19433 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
0b35dfee 19434 ? ISA_MIPS1 : ISA_MIPS3);
316f5878
RS
19435
19436 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19437 ? ISA_MIPS3
19438 : ISA_MIPS1);
19439 }
19440
19441 /* 'default' has traditionally been a no-op. Probably not very useful. */
19442 if (strcasecmp (cpu_string, "default") == 0)
19443 return 0;
19444
19445 for (p = mips_cpu_info_table; p->name != 0; p++)
19446 if (mips_matching_cpu_name_p (p->name, cpu_string))
19447 return p;
19448
1661c76c 19449 as_bad (_("bad value (%s) for %s"), cpu_string, option);
316f5878 19450 return 0;
e7af610e
NC
19451}
19452
316f5878
RS
19453/* Return the canonical processor information for ISA (a member of the
19454 ISA_MIPS* enumeration). */
19455
e7af610e 19456static const struct mips_cpu_info *
17a2f251 19457mips_cpu_info_from_isa (int isa)
e7af610e
NC
19458{
19459 int i;
19460
19461 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
ad3fea08 19462 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
316f5878 19463 && isa == mips_cpu_info_table[i].isa)
e7af610e
NC
19464 return (&mips_cpu_info_table[i]);
19465
e972090a 19466 return NULL;
e7af610e 19467}
fef14a42
TS
19468
19469static const struct mips_cpu_info *
17a2f251 19470mips_cpu_info_from_arch (int arch)
fef14a42
TS
19471{
19472 int i;
19473
19474 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19475 if (arch == mips_cpu_info_table[i].cpu)
19476 return (&mips_cpu_info_table[i]);
19477
19478 return NULL;
19479}
316f5878
RS
19480\f
19481static void
17a2f251 19482show (FILE *stream, const char *string, int *col_p, int *first_p)
316f5878
RS
19483{
19484 if (*first_p)
19485 {
19486 fprintf (stream, "%24s", "");
19487 *col_p = 24;
19488 }
19489 else
19490 {
19491 fprintf (stream, ", ");
19492 *col_p += 2;
19493 }
e7af610e 19494
316f5878
RS
19495 if (*col_p + strlen (string) > 72)
19496 {
19497 fprintf (stream, "\n%24s", "");
19498 *col_p = 24;
19499 }
19500
19501 fprintf (stream, "%s", string);
19502 *col_p += strlen (string);
19503
19504 *first_p = 0;
19505}
19506
19507void
17a2f251 19508md_show_usage (FILE *stream)
e7af610e 19509{
316f5878
RS
19510 int column, first;
19511 size_t i;
19512
19513 fprintf (stream, _("\
19514MIPS options:\n\
316f5878
RS
19515-EB generate big endian output\n\
19516-EL generate little endian output\n\
19517-g, -g2 do not remove unneeded NOPs or swap branches\n\
19518-G NUM allow referencing objects up to NUM bytes\n\
19519 implicitly with the gp register [default 8]\n"));
19520 fprintf (stream, _("\
19521-mips1 generate MIPS ISA I instructions\n\
19522-mips2 generate MIPS ISA II instructions\n\
19523-mips3 generate MIPS ISA III instructions\n\
19524-mips4 generate MIPS ISA IV instructions\n\
19525-mips5 generate MIPS ISA V instructions\n\
19526-mips32 generate MIPS32 ISA instructions\n\
af7ee8bf 19527-mips32r2 generate MIPS32 release 2 ISA instructions\n\
ae52f483
AB
19528-mips32r3 generate MIPS32 release 3 ISA instructions\n\
19529-mips32r5 generate MIPS32 release 5 ISA instructions\n\
7361da2c 19530-mips32r6 generate MIPS32 release 6 ISA instructions\n\
316f5878 19531-mips64 generate MIPS64 ISA instructions\n\
5f74bc13 19532-mips64r2 generate MIPS64 release 2 ISA instructions\n\
ae52f483
AB
19533-mips64r3 generate MIPS64 release 3 ISA instructions\n\
19534-mips64r5 generate MIPS64 release 5 ISA instructions\n\
7361da2c 19535-mips64r6 generate MIPS64 release 6 ISA instructions\n\
316f5878
RS
19536-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19537
19538 first = 1;
e7af610e
NC
19539
19540 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
316f5878
RS
19541 show (stream, mips_cpu_info_table[i].name, &column, &first);
19542 show (stream, "from-abi", &column, &first);
19543 fputc ('\n', stream);
e7af610e 19544
316f5878
RS
19545 fprintf (stream, _("\
19546-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19547-no-mCPU don't generate code specific to CPU.\n\
19548 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19549
19550 first = 1;
19551
19552 show (stream, "3900", &column, &first);
19553 show (stream, "4010", &column, &first);
19554 show (stream, "4100", &column, &first);
19555 show (stream, "4650", &column, &first);
19556 fputc ('\n', stream);
19557
19558 fprintf (stream, _("\
19559-mips16 generate mips16 instructions\n\
19560-no-mips16 do not generate mips16 instructions\n"));
19561 fprintf (stream, _("\
df58fc94
RS
19562-mmicromips generate microMIPS instructions\n\
19563-mno-micromips do not generate microMIPS instructions\n"));
19564 fprintf (stream, _("\
e16bfa71 19565-msmartmips generate smartmips instructions\n\
3739860c 19566-mno-smartmips do not generate smartmips instructions\n"));
e16bfa71 19567 fprintf (stream, _("\
74cd071d
CF
19568-mdsp generate DSP instructions\n\
19569-mno-dsp do not generate DSP instructions\n"));
19570 fprintf (stream, _("\
8b082fb1
TS
19571-mdspr2 generate DSP R2 instructions\n\
19572-mno-dspr2 do not generate DSP R2 instructions\n"));
19573 fprintf (stream, _("\
8f4f9071
MF
19574-mdspr3 generate DSP R3 instructions\n\
19575-mno-dspr3 do not generate DSP R3 instructions\n"));
19576 fprintf (stream, _("\
ef2e4d86
CF
19577-mmt generate MT instructions\n\
19578-mno-mt do not generate MT instructions\n"));
19579 fprintf (stream, _("\
dec0624d
MR
19580-mmcu generate MCU instructions\n\
19581-mno-mcu do not generate MCU instructions\n"));
19582 fprintf (stream, _("\
56d438b1
CF
19583-mmsa generate MSA instructions\n\
19584-mno-msa do not generate MSA instructions\n"));
19585 fprintf (stream, _("\
7d64c587
AB
19586-mxpa generate eXtended Physical Address (XPA) instructions\n\
19587-mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19588 fprintf (stream, _("\
b015e599
AP
19589-mvirt generate Virtualization instructions\n\
19590-mno-virt do not generate Virtualization instructions\n"));
19591 fprintf (stream, _("\
833794fc
MR
19592-minsn32 only generate 32-bit microMIPS instructions\n\
19593-mno-insn32 generate all microMIPS instructions\n"));
19594 fprintf (stream, _("\
c67a084a
NC
19595-mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19596-mfix-loongson2f-nop work around Loongson2F NOP errata\n\
d766e8ec 19597-mfix-vr4120 work around certain VR4120 errata\n\
7d8e00cf 19598-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
6a32d874 19599-mfix-24k insert a nop after ERET and DERET instructions\n\
d954098f 19600-mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
316f5878
RS
19601-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19602-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
aed1a261 19603-msym32 assume all symbols have 32-bit values\n\
316f5878
RS
19604-O0 remove unneeded NOPs, do not swap branches\n\
19605-O remove unneeded NOPs and swap branches\n\
316f5878
RS
19606--trap, --no-break trap exception on div by 0 and mult overflow\n\
19607--break, --no-trap break exception on div by 0 and mult overflow\n"));
037b32b9
AN
19608 fprintf (stream, _("\
19609-mhard-float allow floating-point instructions\n\
19610-msoft-float do not allow floating-point instructions\n\
19611-msingle-float only allow 32-bit floating-point operations\n\
19612-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
3bf0dbfb 19613--[no-]construct-floats [dis]allow floating point values to be constructed\n\
ba92f887
MR
19614--[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19615-mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19616
19617 first = 1;
19618
19619 show (stream, "legacy", &column, &first);
19620 show (stream, "2008", &column, &first);
19621
19622 fputc ('\n', stream);
19623
316f5878
RS
19624 fprintf (stream, _("\
19625-KPIC, -call_shared generate SVR4 position independent code\n\
861fb55a 19626-call_nonpic generate non-PIC code that can operate with DSOs\n\
0c000745 19627-mvxworks-pic generate VxWorks position independent code\n\
861fb55a 19628-non_shared do not generate code that can operate with DSOs\n\
316f5878 19629-xgot assume a 32 bit GOT\n\
dcd410fe 19630-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
bbe506e8 19631-mshared, -mno-shared disable/enable .cpload optimization for\n\
d821e36b 19632 position dependent (non shared) code\n\
316f5878
RS
19633-mabi=ABI create ABI conformant object file for:\n"));
19634
19635 first = 1;
19636
19637 show (stream, "32", &column, &first);
19638 show (stream, "o64", &column, &first);
19639 show (stream, "n32", &column, &first);
19640 show (stream, "64", &column, &first);
19641 show (stream, "eabi", &column, &first);
19642
19643 fputc ('\n', stream);
19644
19645 fprintf (stream, _("\
19646-32 create o32 ABI object file (default)\n\
19647-n32 create n32 ABI object file\n\
19648-64 create 64 ABI object file\n"));
e7af610e 19649}
14e777e0 19650
1575952e 19651#ifdef TE_IRIX
14e777e0 19652enum dwarf2_format
413a266c 19653mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
14e777e0 19654{
369943fe 19655 if (HAVE_64BIT_SYMBOLS)
1575952e 19656 return dwarf2_format_64bit_irix;
14e777e0
KB
19657 else
19658 return dwarf2_format_32bit;
19659}
1575952e 19660#endif
73369e65
EC
19661
19662int
19663mips_dwarf2_addr_size (void)
19664{
6b6b3450 19665 if (HAVE_64BIT_OBJECTS)
73369e65 19666 return 8;
73369e65
EC
19667 else
19668 return 4;
19669}
5862107c
EC
19670
19671/* Standard calling conventions leave the CFA at SP on entry. */
19672void
19673mips_cfi_frame_initial_instructions (void)
19674{
19675 cfi_add_CFA_def_cfa_register (SP);
19676}
19677
707bfff6
TS
19678int
19679tc_mips_regname_to_dw2regnum (char *regname)
19680{
19681 unsigned int regnum = -1;
19682 unsigned int reg;
19683
19684 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
19685 regnum = reg;
19686
19687 return regnum;
19688}
263b2574 19689
19690/* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19691 Given a symbolic attribute NAME, return the proper integer value.
19692 Returns -1 if the attribute is not known. */
19693
19694int
19695mips_convert_symbolic_attribute (const char *name)
19696{
19697 static const struct
19698 {
19699 const char * name;
19700 const int tag;
19701 }
19702 attribute_table[] =
19703 {
19704#define T(tag) {#tag, tag}
19705 T (Tag_GNU_MIPS_ABI_FP),
19706 T (Tag_GNU_MIPS_ABI_MSA),
19707#undef T
19708 };
19709 unsigned int i;
19710
19711 if (name == NULL)
19712 return -1;
19713
19714 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
19715 if (streq (name, attribute_table[i].name))
19716 return attribute_table[i].tag;
19717
19718 return -1;
19719}
fd5c94ab
RS
19720
19721void
19722md_mips_end (void)
19723{
351cdf24
MF
19724 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
19725
fd5c94ab
RS
19726 mips_emit_delays ();
19727 if (cur_proc_ptr)
19728 as_warn (_("missing .end at end of assembly"));
919731af 19729
19730 /* Just in case no code was emitted, do the consistency check. */
19731 file_mips_check_options ();
351cdf24
MF
19732
19733 /* Set a floating-point ABI if the user did not. */
19734 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
19735 {
19736 /* Perform consistency checks on the floating-point ABI. */
19737 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19738 Tag_GNU_MIPS_ABI_FP);
19739 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
19740 check_fpabi (fpabi);
19741 }
19742 else
19743 {
19744 /* Soft-float gets precedence over single-float, the two options should
19745 not be used together so this should not matter. */
19746 if (file_mips_opts.soft_float == 1)
19747 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
19748 /* Single-float gets precedence over all double_float cases. */
19749 else if (file_mips_opts.single_float == 1)
19750 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
19751 else
19752 {
19753 switch (file_mips_opts.fp)
19754 {
19755 case 32:
19756 if (file_mips_opts.gp == 32)
19757 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19758 break;
19759 case 0:
19760 fpabi = Val_GNU_MIPS_ABI_FP_XX;
19761 break;
19762 case 64:
19763 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
19764 fpabi = Val_GNU_MIPS_ABI_FP_64A;
19765 else if (file_mips_opts.gp == 32)
19766 fpabi = Val_GNU_MIPS_ABI_FP_64;
19767 else
19768 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19769 break;
19770 }
19771 }
19772
19773 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19774 Tag_GNU_MIPS_ABI_FP, fpabi);
19775 }
fd5c94ab 19776}
2f0c68f2
CM
19777
19778/* Returns the relocation type required for a particular CFI encoding. */
19779
19780bfd_reloc_code_real_type
19781mips_cfi_reloc_for_encoding (int encoding)
19782{
19783 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
19784 return BFD_RELOC_32_PCREL;
19785 else return BFD_RELOC_NONE;
19786}
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