Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
98d3f06f | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
47 | #ifdef OBJ_MAYBE_ELF | |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
49 | static int mips_output_flavor PARAMS ((void)); | |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
252b5132 RH |
57 | #undef obj_frob_file |
58 | #undef obj_frob_file_after_relocs | |
59 | #undef obj_frob_symbol | |
60 | #undef obj_pop_insert | |
61 | #undef obj_sec_sym_ok_for_reloc | |
62 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
71 | #include "elf/mips.h" | |
72 | #endif | |
73 | ||
74 | #ifndef ECOFF_DEBUGGING | |
75 | #define NO_ECOFF_DEBUGGING | |
76 | #define ECOFF_DEBUGGING 0 | |
77 | #endif | |
78 | ||
79 | #include "ecoff.h" | |
80 | ||
81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
82 | static char *mips_regmask_frag; | |
83 | #endif | |
84 | ||
85 | #define AT 1 | |
86 | #define TREG 24 | |
87 | #define PIC_CALL_REG 25 | |
88 | #define KT0 26 | |
89 | #define KT1 27 | |
90 | #define GP 28 | |
91 | #define SP 29 | |
92 | #define FP 30 | |
93 | #define RA 31 | |
94 | ||
95 | #define ILLEGAL_REG (32) | |
96 | ||
97 | /* Allow override of standard little-endian ECOFF format. */ | |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
103 | extern int target_big_endian; | |
104 | ||
252b5132 RH |
105 | /* The name of the readonly data section. */ |
106 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
107 | ? ".data" \ | |
108 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
109 | ? ".rdata" \ | |
056350c6 NC |
110 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
111 | ? ".rdata" \ | |
252b5132 RH |
112 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
113 | ? ".rodata" \ | |
114 | : (abort (), "")) | |
115 | ||
a325df1d TS |
116 | /* The ABI to use. */ |
117 | enum mips_abi_level | |
118 | { | |
119 | NO_ABI = 0, | |
120 | O32_ABI, | |
121 | O64_ABI, | |
122 | N32_ABI, | |
123 | N64_ABI, | |
124 | EABI_ABI | |
125 | }; | |
126 | ||
127 | /* MIPS ABI we are using for this output file. */ | |
128 | static enum mips_abi_level file_mips_abi = NO_ABI; | |
129 | ||
252b5132 RH |
130 | /* This is the set of options which may be modified by the .set |
131 | pseudo-op. We use a struct so that .set push and .set pop are more | |
132 | reliable. */ | |
133 | ||
e972090a NC |
134 | struct mips_set_options |
135 | { | |
252b5132 RH |
136 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
137 | if it has not been initialized. Changed by `.set mipsN', and the | |
138 | -mipsN command line option, and the default CPU. */ | |
139 | int isa; | |
1f25f5d3 CD |
140 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
141 | if they have not been initialized. Changed by `.set <asename>', by | |
142 | command line options, and based on the default architecture. */ | |
143 | int ase_mips3d; | |
252b5132 RH |
144 | /* Whether we are assembling for the mips16 processor. 0 if we are |
145 | not, 1 if we are, and -1 if the value has not been initialized. | |
146 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
147 | -nomips16 command line options, and the default CPU. */ | |
148 | int mips16; | |
149 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
150 | reorder' and `.set noreorder'. */ | |
151 | int noreorder; | |
152 | /* Non-zero if we should not permit the $at ($1) register to be used | |
153 | in instructions. Changed by `.set at' and `.set noat'. */ | |
154 | int noat; | |
155 | /* Non-zero if we should warn when a macro instruction expands into | |
156 | more than one machine instruction. Changed by `.set nomacro' and | |
157 | `.set macro'. */ | |
158 | int warn_about_macros; | |
159 | /* Non-zero if we should not move instructions. Changed by `.set | |
160 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
161 | int nomove; | |
162 | /* Non-zero if we should not optimize branches by moving the target | |
163 | of the branch into the delay slot. Actually, we don't perform | |
164 | this optimization anyhow. Changed by `.set bopt' and `.set | |
165 | nobopt'. */ | |
166 | int nobopt; | |
167 | /* Non-zero if we should not autoextend mips16 instructions. | |
168 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
169 | int noautoextend; | |
a325df1d TS |
170 | /* Restrict general purpose registers and floating point registers |
171 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
172 | is passed but can changed if the assembler code uses .set mipsN. */ | |
173 | int gp32; | |
174 | int fp32; | |
175 | /* The ABI currently in use. This is changed by .set mipsN to loosen | |
176 | restrictions and doesn't affect the whole file. */ | |
177 | enum mips_abi_level abi; | |
252b5132 RH |
178 | }; |
179 | ||
a325df1d | 180 | /* True if -mgp32 was passed. */ |
a8e8e863 | 181 | static int file_mips_gp32 = -1; |
a325df1d TS |
182 | |
183 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 184 | static int file_mips_fp32 = -1; |
a325df1d | 185 | |
252b5132 | 186 | /* This is the struct we use to hold the current set of options. Note |
e7af610e NC |
187 | that we must set the isa field to ISA_UNKNOWN and the mips16 field to |
188 | -1 to indicate that they have not been initialized. */ | |
252b5132 | 189 | |
e972090a NC |
190 | static struct mips_set_options mips_opts = |
191 | { | |
1f25f5d3 | 192 | ISA_UNKNOWN, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI |
e7af610e | 193 | }; |
252b5132 RH |
194 | |
195 | /* These variables are filled in with the masks of registers used. | |
196 | The object format code reads them and puts them in the appropriate | |
197 | place. */ | |
198 | unsigned long mips_gprmask; | |
199 | unsigned long mips_cprmask[4]; | |
200 | ||
201 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 202 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 203 | |
1f25f5d3 CD |
204 | /* True if -mips3d was passed or implied by arguments passed on the |
205 | command line (e.g., by -march). */ | |
206 | static int file_ase_mips3d; | |
207 | ||
ec68c924 | 208 | /* The argument of the -mcpu= flag. Historical for code generation. */ |
e7af610e | 209 | static int mips_cpu = CPU_UNKNOWN; |
252b5132 | 210 | |
ec68c924 EC |
211 | /* The argument of the -march= flag. The architecture we are assembling. */ |
212 | static int mips_arch = CPU_UNKNOWN; | |
213 | ||
214 | /* The argument of the -mtune= flag. The architecture for which we | |
215 | are optimizing. */ | |
216 | static int mips_tune = CPU_UNKNOWN; | |
217 | ||
2f4dcb11 | 218 | /* Whether we should mark the file EABI64 or EABI32. */ |
252b5132 RH |
219 | static int mips_eabi64 = 0; |
220 | ||
221 | /* If they asked for mips1 or mips2 and a cpu that is | |
bdaaa2e1 | 222 | mips3 or greater, then mark the object file 32BITMODE. */ |
252b5132 RH |
223 | static int mips_32bitmode = 0; |
224 | ||
9ce8a5dd GRK |
225 | /* Some ISA's have delay slots for instructions which read or write |
226 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 227 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
228 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
229 | delay slot in this ISA. The uses of this macro assume that any | |
230 | ISA that has delay slots for one of these, has them for all. They | |
231 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 232 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 233 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
234 | (ISA) == ISA_MIPS1 \ |
235 | || (ISA) == ISA_MIPS2 \ | |
236 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
237 | ) |
238 | ||
bdaaa2e1 | 239 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 240 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
241 | (ISA) == ISA_MIPS3 \ |
242 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 243 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 244 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
245 | ) |
246 | ||
e013f690 | 247 | #define HAVE_32BIT_GPRS \ |
a325df1d TS |
248 | (mips_opts.gp32 \ |
249 | || mips_opts.abi == O32_ABI \ | |
e013f690 | 250 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 251 | |
e013f690 | 252 | #define HAVE_32BIT_FPRS \ |
a325df1d TS |
253 | (mips_opts.fp32 \ |
254 | || mips_opts.abi == O32_ABI \ | |
e013f690 | 255 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
256 | |
257 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
258 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
259 | ||
a325df1d | 260 | #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI) |
e013f690 | 261 | |
a325df1d | 262 | #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI) |
e013f690 TS |
263 | |
264 | /* We can only have 64bit addresses if the object file format | |
265 | supports it. */ | |
afdbd6d0 CD |
266 | #define HAVE_32BIT_ADDRESSES \ |
267 | (HAVE_32BIT_GPRS \ | |
268 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
269 | || ! HAVE_64BIT_OBJECTS) \ | |
270 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
271 | |
272 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 273 | |
1f25f5d3 CD |
274 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
275 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
276 | ) | |
277 | ||
bdaaa2e1 | 278 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 279 | reads from the HI and LO registers, and thus does not |
ec68c924 | 280 | require nops to be inserted. */ |
252b5132 | 281 | |
ec68c924 | 282 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
0a758a12 | 283 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
284 | ) |
285 | ||
286 | /* Whether the processor uses hardware interlocks to protect reads | |
287 | from the GPRs, and thus does not require nops to be inserted. */ | |
288 | #define gpr_interlocks \ | |
e7af610e | 289 | (mips_opts.isa != ISA_MIPS1 \ |
ec68c924 | 290 | || mips_arch == CPU_R3900) |
252b5132 RH |
291 | |
292 | /* As with other "interlocks" this is used by hardware that has FP | |
293 | (co-processor) interlocks. */ | |
bdaaa2e1 | 294 | /* Itbl support may require additional care here. */ |
ec68c924 | 295 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
0a758a12 | 296 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
297 | ) |
298 | ||
6b76fefe CM |
299 | /* Is this a mfhi or mflo instruction? */ |
300 | #define MF_HILO_INSN(PINFO) \ | |
301 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
302 | ||
252b5132 RH |
303 | /* MIPS PIC level. */ |
304 | ||
e972090a NC |
305 | enum mips_pic_level |
306 | { | |
252b5132 RH |
307 | /* Do not generate PIC code. */ |
308 | NO_PIC, | |
309 | ||
310 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
311 | not sure what it is supposed to do. */ | |
312 | IRIX4_PIC, | |
313 | ||
314 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
315 | SVR4_PIC, | |
316 | ||
317 | /* Generate PIC code without using a global offset table: the data | |
318 | segment has a maximum size of 64K, all data references are off | |
319 | the $gp register, and all text references are PC relative. This | |
320 | is used on some embedded systems. */ | |
321 | EMBEDDED_PIC | |
322 | }; | |
323 | ||
324 | static enum mips_pic_level mips_pic; | |
325 | ||
39c0a331 L |
326 | /* Warn about all NOPS that the assembler generates. */ |
327 | static int warn_nops = 0; | |
328 | ||
c9914766 | 329 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 330 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 331 | static int mips_big_got = 0; |
252b5132 RH |
332 | |
333 | /* 1 if trap instructions should used for overflow rather than break | |
334 | instructions. */ | |
c9914766 | 335 | static int mips_trap = 0; |
252b5132 | 336 | |
119d663a | 337 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 338 | by assembling two single width halves into two single width floating |
119d663a NC |
339 | point registers which just happen to alias the double width destination |
340 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 341 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
342 | automatically at assemble time. */ |
343 | static int mips_disable_float_construction; | |
344 | ||
252b5132 RH |
345 | /* Non-zero if any .set noreorder directives were used. */ |
346 | ||
347 | static int mips_any_noreorder; | |
348 | ||
6b76fefe CM |
349 | /* Non-zero if nops should be inserted when the register referenced in |
350 | an mfhi/mflo instruction is read in the next two instructions. */ | |
351 | static int mips_7000_hilo_fix; | |
352 | ||
252b5132 | 353 | /* The size of the small data section. */ |
156c2f8b | 354 | static unsigned int g_switch_value = 8; |
252b5132 RH |
355 | /* Whether the -G option was used. */ |
356 | static int g_switch_seen = 0; | |
357 | ||
358 | #define N_RMASK 0xc4 | |
359 | #define N_VFP 0xd4 | |
360 | ||
361 | /* If we can determine in advance that GP optimization won't be | |
362 | possible, we can skip the relaxation stuff that tries to produce | |
363 | GP-relative references. This makes delay slot optimization work | |
364 | better. | |
365 | ||
366 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
367 | gcc output. It needs to guess right for gcc, otherwise gcc |
368 | will put what it thinks is a GP-relative instruction in a branch | |
369 | delay slot. | |
252b5132 RH |
370 | |
371 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
372 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
373 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
374 | ||
375 | /* handle of the OPCODE hash table */ | |
376 | static struct hash_control *op_hash = NULL; | |
377 | ||
378 | /* The opcode hash table we use for the mips16. */ | |
379 | static struct hash_control *mips16_op_hash = NULL; | |
380 | ||
381 | /* This array holds the chars that always start a comment. If the | |
382 | pre-processor is disabled, these aren't very useful */ | |
383 | const char comment_chars[] = "#"; | |
384 | ||
385 | /* This array holds the chars that only start a comment at the beginning of | |
386 | a line. If the line seems to have the form '# 123 filename' | |
387 | .line and .file directives will appear in the pre-processed output */ | |
388 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
389 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 390 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
391 | /* Also note that C style comments are always supported. */ |
392 | const char line_comment_chars[] = "#"; | |
393 | ||
bdaaa2e1 | 394 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 395 | const char line_separator_chars[] = ";"; |
252b5132 RH |
396 | |
397 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
398 | const char EXP_CHARS[] = "eE"; | |
399 | ||
400 | /* Chars that mean this number is a floating point constant */ | |
401 | /* As in 0f12.456 */ | |
402 | /* or 0d1.2345e12 */ | |
403 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
404 | ||
405 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
406 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
407 | but nothing is ideal around here. | |
408 | */ | |
409 | ||
410 | static char *insn_error; | |
411 | ||
412 | static int auto_align = 1; | |
413 | ||
414 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
415 | offset in the stack frame from which to restore the $gp register. | |
416 | This is set by the .cprestore pseudo-op, and saved in this | |
417 | variable. */ | |
418 | static offsetT mips_cprestore_offset = -1; | |
419 | ||
6478892d TS |
420 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
421 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 422 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
423 | static offsetT mips_cpreturn_offset = -1; |
424 | static int mips_cpreturn_register = -1; | |
425 | static int mips_gp_register = GP; | |
def2e0dd | 426 | static int mips_gprel_offset = 0; |
6478892d | 427 | |
7a621144 DJ |
428 | /* Whether mips_cprestore_offset has been set in the current function |
429 | (or whether it has already been warned about, if not). */ | |
430 | static int mips_cprestore_valid = 0; | |
431 | ||
252b5132 RH |
432 | /* This is the register which holds the stack frame, as set by the |
433 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
434 | static int mips_frame_reg = SP; | |
435 | ||
7a621144 DJ |
436 | /* Whether mips_frame_reg has been set in the current function |
437 | (or whether it has already been warned about, if not). */ | |
438 | static int mips_frame_reg_valid = 0; | |
439 | ||
252b5132 RH |
440 | /* To output NOP instructions correctly, we need to keep information |
441 | about the previous two instructions. */ | |
442 | ||
443 | /* Whether we are optimizing. The default value of 2 means to remove | |
444 | unneeded NOPs and swap branch instructions when possible. A value | |
445 | of 1 means to not swap branches. A value of 0 means to always | |
446 | insert NOPs. */ | |
447 | static int mips_optimize = 2; | |
448 | ||
449 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
450 | equivalent to seeing no -g option at all. */ | |
451 | static int mips_debug = 0; | |
452 | ||
453 | /* The previous instruction. */ | |
454 | static struct mips_cl_insn prev_insn; | |
455 | ||
456 | /* The instruction before prev_insn. */ | |
457 | static struct mips_cl_insn prev_prev_insn; | |
458 | ||
459 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
460 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 461 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
462 | |
463 | /* Non-zero if prev_insn is valid. */ | |
464 | static int prev_insn_valid; | |
465 | ||
466 | /* The frag for the previous instruction. */ | |
467 | static struct frag *prev_insn_frag; | |
468 | ||
469 | /* The offset into prev_insn_frag for the previous instruction. */ | |
470 | static long prev_insn_where; | |
471 | ||
472 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 473 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
474 | |
475 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 476 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
477 | |
478 | /* Non-zero if the previous instruction was in a delay slot. */ | |
479 | static int prev_insn_is_delay_slot; | |
480 | ||
481 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
482 | static int prev_insn_unreordered; | |
483 | ||
484 | /* Non-zero if the previous instruction uses an extend opcode (if | |
485 | mips16). */ | |
486 | static int prev_insn_extended; | |
487 | ||
488 | /* Non-zero if the previous previous instruction was in a .set | |
489 | noreorder. */ | |
490 | static int prev_prev_insn_unreordered; | |
491 | ||
492 | /* If this is set, it points to a frag holding nop instructions which | |
493 | were inserted before the start of a noreorder section. If those | |
494 | nops turn out to be unnecessary, the size of the frag can be | |
495 | decreased. */ | |
496 | static fragS *prev_nop_frag; | |
497 | ||
498 | /* The number of nop instructions we created in prev_nop_frag. */ | |
499 | static int prev_nop_frag_holds; | |
500 | ||
501 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 502 | prev_nop_frag. */ |
252b5132 RH |
503 | static int prev_nop_frag_required; |
504 | ||
505 | /* The number of instructions we've seen since prev_nop_frag. */ | |
506 | static int prev_nop_frag_since; | |
507 | ||
508 | /* For ECOFF and ELF, relocations against symbols are done in two | |
509 | parts, with a HI relocation and a LO relocation. Each relocation | |
510 | has only 16 bits of space to store an addend. This means that in | |
511 | order for the linker to handle carries correctly, it must be able | |
512 | to locate both the HI and the LO relocation. This means that the | |
513 | relocations must appear in order in the relocation table. | |
514 | ||
515 | In order to implement this, we keep track of each unmatched HI | |
516 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 517 | corresponding LO relocation. */ |
252b5132 | 518 | |
e972090a NC |
519 | struct mips_hi_fixup |
520 | { | |
252b5132 RH |
521 | /* Next HI fixup. */ |
522 | struct mips_hi_fixup *next; | |
523 | /* This fixup. */ | |
524 | fixS *fixp; | |
525 | /* The section this fixup is in. */ | |
526 | segT seg; | |
527 | }; | |
528 | ||
529 | /* The list of unmatched HI relocs. */ | |
530 | ||
531 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
532 | ||
533 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
534 | ||
535 | #define X ILLEGAL_REG | |
e972090a NC |
536 | static const int mips32_to_16_reg_map[] = |
537 | { | |
252b5132 RH |
538 | X, X, 2, 3, 4, 5, 6, 7, |
539 | X, X, X, X, X, X, X, X, | |
540 | 0, 1, X, X, X, X, X, X, | |
541 | X, X, X, X, X, X, X, X | |
542 | }; | |
543 | #undef X | |
544 | ||
545 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
546 | ||
e972090a NC |
547 | static const unsigned int mips16_to_32_reg_map[] = |
548 | { | |
252b5132 RH |
549 | 16, 17, 2, 3, 4, 5, 6, 7 |
550 | }; | |
551 | \f | |
552 | /* Since the MIPS does not have multiple forms of PC relative | |
553 | instructions, we do not have to do relaxing as is done on other | |
554 | platforms. However, we do have to handle GP relative addressing | |
555 | correctly, which turns out to be a similar problem. | |
556 | ||
557 | Every macro that refers to a symbol can occur in (at least) two | |
558 | forms, one with GP relative addressing and one without. For | |
559 | example, loading a global variable into a register generally uses | |
560 | a macro instruction like this: | |
561 | lw $4,i | |
562 | If i can be addressed off the GP register (this is true if it is in | |
563 | the .sbss or .sdata section, or if it is known to be smaller than | |
564 | the -G argument) this will generate the following instruction: | |
565 | lw $4,i($gp) | |
566 | This instruction will use a GPREL reloc. If i can not be addressed | |
567 | off the GP register, the following instruction sequence will be used: | |
568 | lui $at,i | |
569 | lw $4,i($at) | |
570 | In this case the first instruction will have a HI16 reloc, and the | |
571 | second reloc will have a LO16 reloc. Both relocs will be against | |
572 | the symbol i. | |
573 | ||
574 | The issue here is that we may not know whether i is GP addressable | |
575 | until after we see the instruction that uses it. Therefore, we | |
576 | want to be able to choose the final instruction sequence only at | |
577 | the end of the assembly. This is similar to the way other | |
578 | platforms choose the size of a PC relative instruction only at the | |
579 | end of assembly. | |
580 | ||
581 | When generating position independent code we do not use GP | |
582 | addressing in quite the same way, but the issue still arises as | |
583 | external symbols and local symbols must be handled differently. | |
584 | ||
585 | We handle these issues by actually generating both possible | |
586 | instruction sequences. The longer one is put in a frag_var with | |
587 | type rs_machine_dependent. We encode what to do with the frag in | |
588 | the subtype field. We encode (1) the number of existing bytes to | |
589 | replace, (2) the number of new bytes to use, (3) the offset from | |
590 | the start of the existing bytes to the first reloc we must generate | |
591 | (that is, the offset is applied from the start of the existing | |
592 | bytes after they are replaced by the new bytes, if any), (4) the | |
593 | offset from the start of the existing bytes to the second reloc, | |
594 | (5) whether a third reloc is needed (the third reloc is always four | |
595 | bytes after the second reloc), and (6) whether to warn if this | |
596 | variant is used (this is sometimes needed if .set nomacro or .set | |
597 | noat is in effect). All these numbers are reasonably small. | |
598 | ||
599 | Generating two instruction sequences must be handled carefully to | |
600 | ensure that delay slots are handled correctly. Fortunately, there | |
601 | are a limited number of cases. When the second instruction | |
602 | sequence is generated, append_insn is directed to maintain the | |
603 | existing delay slot information, so it continues to apply to any | |
604 | code after the second instruction sequence. This means that the | |
605 | second instruction sequence must not impose any requirements not | |
606 | required by the first instruction sequence. | |
607 | ||
608 | These variant frags are then handled in functions called by the | |
609 | machine independent code. md_estimate_size_before_relax returns | |
610 | the final size of the frag. md_convert_frag sets up the final form | |
611 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
612 | one if needed. */ | |
613 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
614 | ((relax_substateT) \ | |
615 | (((old) << 23) \ | |
616 | | ((new) << 16) \ | |
617 | | (((reloc1) + 64) << 9) \ | |
618 | | (((reloc2) + 64) << 2) \ | |
619 | | ((reloc3) ? (1 << 1) : 0) \ | |
620 | | ((warn) ? 1 : 0))) | |
621 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
622 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
623 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
624 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
625 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
626 | #define RELAX_WARN(i) ((i) & 1) | |
627 | ||
628 | /* For mips16 code, we use an entirely different form of relaxation. | |
629 | mips16 supports two versions of most instructions which take | |
630 | immediate values: a small one which takes some small value, and a | |
631 | larger one which takes a 16 bit value. Since branches also follow | |
632 | this pattern, relaxing these values is required. | |
633 | ||
634 | We can assemble both mips16 and normal MIPS code in a single | |
635 | object. Therefore, we need to support this type of relaxation at | |
636 | the same time that we support the relaxation described above. We | |
637 | use the high bit of the subtype field to distinguish these cases. | |
638 | ||
639 | The information we store for this type of relaxation is the | |
640 | argument code found in the opcode file for this relocation, whether | |
641 | the user explicitly requested a small or extended form, and whether | |
642 | the relocation is in a jump or jal delay slot. That tells us the | |
643 | size of the value, and how it should be stored. We also store | |
644 | whether the fragment is considered to be extended or not. We also | |
645 | store whether this is known to be a branch to a different section, | |
646 | whether we have tried to relax this frag yet, and whether we have | |
647 | ever extended a PC relative fragment because of a shift count. */ | |
648 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
649 | (0x80000000 \ | |
650 | | ((type) & 0xff) \ | |
651 | | ((small) ? 0x100 : 0) \ | |
652 | | ((ext) ? 0x200 : 0) \ | |
653 | | ((dslot) ? 0x400 : 0) \ | |
654 | | ((jal_dslot) ? 0x800 : 0)) | |
655 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
656 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
657 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
658 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
659 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
660 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
661 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
662 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
663 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
664 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
665 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
666 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
667 | \f | |
668 | /* Prototypes for static functions. */ | |
669 | ||
670 | #ifdef __STDC__ | |
671 | #define internalError() \ | |
672 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
673 | #else | |
674 | #define internalError() as_fatal (_("MIPS internal Error")); | |
675 | #endif | |
676 | ||
677 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
678 | ||
679 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
680 | unsigned int reg, enum mips_regclass class)); | |
156c2f8b | 681 | static int reg_needs_delay PARAMS ((unsigned int)); |
252b5132 RH |
682 | static void mips16_mark_labels PARAMS ((void)); |
683 | static void append_insn PARAMS ((char *place, | |
684 | struct mips_cl_insn * ip, | |
685 | expressionS * p, | |
f6688943 | 686 | bfd_reloc_code_real_type *r, |
252b5132 RH |
687 | boolean)); |
688 | static void mips_no_prev_insn PARAMS ((int)); | |
689 | static void mips_emit_delays PARAMS ((boolean)); | |
690 | #ifdef USE_STDARG | |
691 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
692 | const char *name, const char *fmt, | |
693 | ...)); | |
694 | #else | |
695 | static void macro_build (); | |
696 | #endif | |
697 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
698 | const char *, const char *, | |
699 | va_list)); | |
438c16b8 | 700 | static void macro_build_jalr PARAMS ((int, expressionS *)); |
252b5132 RH |
701 | static void macro_build_lui PARAMS ((char *place, int *counter, |
702 | expressionS * ep, int regnum)); | |
703 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
704 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
705 | expressionS *)); | |
706 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
c9914766 | 707 | static void load_address PARAMS ((int *, int, expressionS *, int *)); |
ea1fb5dc | 708 | static void move_register PARAMS ((int *, int, int)); |
252b5132 RH |
709 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
710 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
711 | #ifdef LOSING_COMPILER | |
712 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
713 | #endif | |
714 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
715 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
716 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
717 | boolean, boolean, unsigned long *, | |
718 | boolean *, unsigned short *)); | |
394f9b3a | 719 | static int my_getPercentOp PARAMS ((char **, unsigned int *, int *)); |
ad8d3bb3 TS |
720 | static int my_getSmallParser PARAMS ((char **, unsigned int *, int *)); |
721 | static int my_getSmallExpression PARAMS ((expressionS *, char *)); | |
722 | static void my_getExpression PARAMS ((expressionS *, char *)); | |
ae948b86 | 723 | #ifdef OBJ_ELF |
e013f690 | 724 | static int support_64bit_objects PARAMS((void)); |
ae948b86 | 725 | #endif |
252b5132 RH |
726 | static symbolS *get_symbol PARAMS ((void)); |
727 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
728 | static void s_align PARAMS ((int)); | |
729 | static void s_change_sec PARAMS ((int)); | |
730 | static void s_cons PARAMS ((int)); | |
731 | static void s_float_cons PARAMS ((int)); | |
732 | static void s_mips_globl PARAMS ((int)); | |
733 | static void s_option PARAMS ((int)); | |
734 | static void s_mipsset PARAMS ((int)); | |
735 | static void s_abicalls PARAMS ((int)); | |
736 | static void s_cpload PARAMS ((int)); | |
6478892d TS |
737 | static void s_cpsetup PARAMS ((int)); |
738 | static void s_cplocal PARAMS ((int)); | |
252b5132 | 739 | static void s_cprestore PARAMS ((int)); |
6478892d TS |
740 | static void s_cpreturn PARAMS ((int)); |
741 | static void s_gpvalue PARAMS ((int)); | |
252b5132 RH |
742 | static void s_gpword PARAMS ((int)); |
743 | static void s_cpadd PARAMS ((int)); | |
744 | static void s_insn PARAMS ((int)); | |
745 | static void md_obj_begin PARAMS ((void)); | |
746 | static void md_obj_end PARAMS ((void)); | |
747 | static long get_number PARAMS ((void)); | |
748 | static void s_mips_ent PARAMS ((int)); | |
749 | static void s_mips_end PARAMS ((int)); | |
750 | static void s_mips_frame PARAMS ((int)); | |
751 | static void s_mips_mask PARAMS ((int)); | |
752 | static void s_mips_stab PARAMS ((int)); | |
753 | static void s_mips_weakext PARAMS ((int)); | |
754 | static void s_file PARAMS ((int)); | |
755 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
e7af610e NC |
756 | static const char *mips_isa_to_str PARAMS ((int)); |
757 | static const char *mips_cpu_to_str PARAMS ((int)); | |
252b5132 | 758 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
e87a0284 | 759 | static void show PARAMS ((FILE *, char *, int *, int *)); |
add55e1f RS |
760 | #ifdef OBJ_ELF |
761 | static int mips_need_elf_addend_fixup PARAMS ((fixS *)); | |
762 | #endif | |
e7af610e | 763 | |
ad8d3bb3 | 764 | /* Return values of my_getSmallExpression(). */ |
fb1b3232 | 765 | |
ad8d3bb3 | 766 | enum small_ex_type |
fb1b3232 TS |
767 | { |
768 | S_EX_NONE = 0, | |
ad8d3bb3 TS |
769 | S_EX_REGISTER, |
770 | ||
771 | /* Direct relocation creation by %percent_op(). */ | |
772 | S_EX_HALF, | |
fb1b3232 | 773 | S_EX_HI, |
ad8d3bb3 TS |
774 | S_EX_LO, |
775 | S_EX_GP_REL, | |
776 | S_EX_GOT, | |
777 | S_EX_CALL16, | |
778 | S_EX_GOT_DISP, | |
779 | S_EX_GOT_PAGE, | |
780 | S_EX_GOT_OFST, | |
781 | S_EX_GOT_HI, | |
782 | S_EX_GOT_LO, | |
783 | S_EX_NEG, | |
fb1b3232 TS |
784 | S_EX_HIGHER, |
785 | S_EX_HIGHEST, | |
ad8d3bb3 TS |
786 | S_EX_CALL_HI, |
787 | S_EX_CALL_LO | |
fb1b3232 TS |
788 | }; |
789 | ||
e7af610e NC |
790 | /* Table and functions used to map between CPU/ISA names, and |
791 | ISA levels, and CPU numbers. */ | |
792 | ||
e972090a NC |
793 | struct mips_cpu_info |
794 | { | |
e7af610e NC |
795 | const char *name; /* CPU or ISA name. */ |
796 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
797 | int isa; /* ISA level. */ | |
798 | int cpu; /* CPU number (default CPU if ISA). */ | |
799 | }; | |
800 | ||
801 | static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); | |
802 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); | |
803 | static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); | |
252b5132 RH |
804 | \f |
805 | /* Pseudo-op table. | |
806 | ||
807 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
808 | should be defined here, but are currently unsupported: .alias, | |
809 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
810 | ||
811 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
812 | specific to the type of debugging information being generated, and | |
813 | should be defined by the object format: .aent, .begin, .bend, | |
814 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
815 | .vreg. | |
816 | ||
817 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
818 | not MIPS CPU specific, but are also not specific to the object file | |
819 | format. This file is probably the best place to define them, but | |
820 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
821 | .struct. */ | |
822 | ||
e972090a NC |
823 | static const pseudo_typeS mips_pseudo_table[] = |
824 | { | |
beae10d5 | 825 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
826 | {"option", s_option, 0}, |
827 | {"set", s_mipsset, 0}, | |
828 | {"rdata", s_change_sec, 'r'}, | |
829 | {"sdata", s_change_sec, 's'}, | |
830 | {"livereg", s_ignore, 0}, | |
831 | {"abicalls", s_abicalls, 0}, | |
832 | {"cpload", s_cpload, 0}, | |
6478892d TS |
833 | {"cpsetup", s_cpsetup, 0}, |
834 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 835 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
836 | {"cpreturn", s_cpreturn, 0}, |
837 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 RH |
838 | {"gpword", s_gpword, 0}, |
839 | {"cpadd", s_cpadd, 0}, | |
840 | {"insn", s_insn, 0}, | |
841 | ||
beae10d5 | 842 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
843 | chips. */ |
844 | {"asciiz", stringer, 1}, | |
845 | {"bss", s_change_sec, 'b'}, | |
846 | {"err", s_err, 0}, | |
847 | {"half", s_cons, 1}, | |
848 | {"dword", s_cons, 3}, | |
849 | {"weakext", s_mips_weakext, 0}, | |
850 | ||
beae10d5 | 851 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
852 | here for one reason or another. */ |
853 | {"align", s_align, 0}, | |
854 | {"byte", s_cons, 0}, | |
855 | {"data", s_change_sec, 'd'}, | |
856 | {"double", s_float_cons, 'd'}, | |
857 | {"float", s_float_cons, 'f'}, | |
858 | {"globl", s_mips_globl, 0}, | |
859 | {"global", s_mips_globl, 0}, | |
860 | {"hword", s_cons, 1}, | |
861 | {"int", s_cons, 2}, | |
862 | {"long", s_cons, 2}, | |
863 | {"octa", s_cons, 4}, | |
864 | {"quad", s_cons, 3}, | |
865 | {"short", s_cons, 1}, | |
866 | {"single", s_float_cons, 'f'}, | |
867 | {"stabn", s_mips_stab, 'n'}, | |
868 | {"text", s_change_sec, 't'}, | |
869 | {"word", s_cons, 2}, | |
add56521 L |
870 | |
871 | #ifdef MIPS_STABS_ELF | |
872 | { "extern", ecoff_directive_extern, 0}, | |
873 | #endif | |
874 | ||
43841e91 | 875 | { NULL, NULL, 0 }, |
252b5132 RH |
876 | }; |
877 | ||
e972090a NC |
878 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
879 | { | |
beae10d5 KH |
880 | /* These pseudo-ops should be defined by the object file format. |
881 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
882 | {"aent", s_mips_ent, 1}, |
883 | {"bgnb", s_ignore, 0}, | |
884 | {"end", s_mips_end, 0}, | |
885 | {"endb", s_ignore, 0}, | |
886 | {"ent", s_mips_ent, 0}, | |
887 | {"file", s_file, 0}, | |
888 | {"fmask", s_mips_mask, 'F'}, | |
889 | {"frame", s_mips_frame, 0}, | |
890 | {"loc", s_ignore, 0}, | |
891 | {"mask", s_mips_mask, 'R'}, | |
892 | {"verstamp", s_ignore, 0}, | |
43841e91 | 893 | { NULL, NULL, 0 }, |
252b5132 RH |
894 | }; |
895 | ||
896 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
897 | ||
898 | void | |
899 | mips_pop_insert () | |
900 | { | |
901 | pop_insert (mips_pseudo_table); | |
902 | if (! ECOFF_DEBUGGING) | |
903 | pop_insert (mips_nonecoff_pseudo_table); | |
904 | } | |
905 | \f | |
906 | /* Symbols labelling the current insn. */ | |
907 | ||
e972090a NC |
908 | struct insn_label_list |
909 | { | |
252b5132 RH |
910 | struct insn_label_list *next; |
911 | symbolS *label; | |
912 | }; | |
913 | ||
914 | static struct insn_label_list *insn_labels; | |
915 | static struct insn_label_list *free_insn_labels; | |
916 | ||
917 | static void mips_clear_insn_labels PARAMS ((void)); | |
918 | ||
919 | static inline void | |
920 | mips_clear_insn_labels () | |
921 | { | |
922 | register struct insn_label_list **pl; | |
923 | ||
924 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
925 | ; | |
926 | *pl = insn_labels; | |
927 | insn_labels = NULL; | |
928 | } | |
929 | \f | |
930 | static char *expr_end; | |
931 | ||
932 | /* Expressions which appear in instructions. These are set by | |
933 | mips_ip. */ | |
934 | ||
935 | static expressionS imm_expr; | |
936 | static expressionS offset_expr; | |
937 | ||
938 | /* Relocs associated with imm_expr and offset_expr. */ | |
939 | ||
f6688943 TS |
940 | static bfd_reloc_code_real_type imm_reloc[3] |
941 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
942 | static bfd_reloc_code_real_type offset_reloc[3] | |
943 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
944 | |
945 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
946 | ||
947 | static boolean imm_unmatched_hi; | |
948 | ||
949 | /* These are set by mips16_ip if an explicit extension is used. */ | |
950 | ||
951 | static boolean mips16_small, mips16_ext; | |
952 | ||
953 | #ifdef MIPS_STABS_ELF | |
954 | /* The pdr segment for per procedure frame/regmask info */ | |
955 | ||
956 | static segT pdr_seg; | |
957 | #endif | |
958 | ||
e7af610e NC |
959 | static const char * |
960 | mips_isa_to_str (isa) | |
961 | int isa; | |
962 | { | |
963 | const struct mips_cpu_info *ci; | |
964 | static char s[20]; | |
965 | ||
966 | ci = mips_cpu_info_from_isa (isa); | |
967 | if (ci != NULL) | |
968 | return (ci->name); | |
969 | ||
970 | sprintf (s, "ISA#%d", isa); | |
971 | return s; | |
972 | } | |
973 | ||
974 | static const char * | |
156c2f8b NC |
975 | mips_cpu_to_str (cpu) |
976 | int cpu; | |
977 | { | |
e7af610e | 978 | const struct mips_cpu_info *ci; |
156c2f8b | 979 | static char s[16]; |
e7af610e NC |
980 | |
981 | ci = mips_cpu_info_from_cpu (cpu); | |
982 | if (ci != NULL) | |
983 | return (ci->name); | |
984 | ||
985 | sprintf (s, "CPU#%d", cpu); | |
986 | return s; | |
156c2f8b NC |
987 | } |
988 | ||
e013f690 TS |
989 | /* The default target format to use. */ |
990 | ||
991 | const char * | |
992 | mips_target_format () | |
993 | { | |
994 | switch (OUTPUT_FLAVOR) | |
995 | { | |
996 | case bfd_target_aout_flavour: | |
997 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
998 | case bfd_target_ecoff_flavour: | |
999 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1000 | case bfd_target_coff_flavour: | |
1001 | return "pe-mips"; | |
1002 | case bfd_target_elf_flavour: | |
1003 | #ifdef TE_TMIPS | |
1004 | /* This is traditional mips */ | |
1005 | return (target_big_endian | |
1006 | ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips" | |
1007 | : "elf32-tradbigmips") | |
1008 | : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips" | |
1009 | : "elf32-tradlittlemips")); | |
1010 | #else | |
1011 | return (target_big_endian | |
1012 | ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips") | |
1013 | : (HAVE_64BIT_OBJECTS ? "elf64-littlemips" | |
1014 | : "elf32-littlemips")); | |
1015 | #endif | |
1016 | default: | |
1017 | abort (); | |
1018 | return NULL; | |
1019 | } | |
1020 | } | |
1021 | ||
156c2f8b NC |
1022 | /* This function is called once, at assembler startup time. It should |
1023 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1024 | ||
252b5132 RH |
1025 | void |
1026 | md_begin () | |
1027 | { | |
252b5132 | 1028 | register const char *retval = NULL; |
156c2f8b | 1029 | int i = 0; |
252b5132 RH |
1030 | const char *cpu; |
1031 | char *a = NULL; | |
1032 | int broken = 0; | |
1033 | int mips_isa_from_cpu; | |
e7af610e NC |
1034 | int target_cpu_had_mips16 = 0; |
1035 | const struct mips_cpu_info *ci; | |
252b5132 | 1036 | |
056350c6 NC |
1037 | /* GP relative stuff not working for PE */ |
1038 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
1039 | && g_switch_value != 0) | |
1040 | { | |
1041 | if (g_switch_seen) | |
1042 | as_bad (_("-G not supported in this configuration.")); | |
1043 | g_switch_value = 0; | |
1044 | } | |
1045 | ||
252b5132 RH |
1046 | cpu = TARGET_CPU; |
1047 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
1048 | { | |
1049 | a = xmalloc (sizeof TARGET_CPU); | |
1050 | strcpy (a, TARGET_CPU); | |
1051 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
1052 | cpu = a; | |
1053 | } | |
1054 | ||
e7af610e | 1055 | if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) |
252b5132 | 1056 | { |
e7af610e NC |
1057 | target_cpu_had_mips16 = 1; |
1058 | cpu += sizeof "mips16" - 1; | |
252b5132 RH |
1059 | } |
1060 | ||
e7af610e NC |
1061 | if (mips_opts.mips16 < 0) |
1062 | mips_opts.mips16 = target_cpu_had_mips16; | |
252b5132 | 1063 | |
6dce9e24 TS |
1064 | /* Backward compatibility for historic -mcpu= option. Check for |
1065 | incompatible options, warn if -mcpu is used. */ | |
1066 | if (mips_cpu != CPU_UNKNOWN | |
1067 | && mips_arch != CPU_UNKNOWN | |
1068 | && mips_cpu != mips_arch) | |
1069 | { | |
1070 | as_fatal (_("The -mcpu option can't be used together with -march. " | |
1071 | "Use -mtune instead of -mcpu.")); | |
1072 | } | |
1073 | ||
1074 | if (mips_cpu != CPU_UNKNOWN | |
1075 | && mips_tune != CPU_UNKNOWN | |
1076 | && mips_cpu != mips_tune) | |
1077 | { | |
1078 | as_fatal (_("The -mcpu option can't be used together with -mtune. " | |
1079 | "Use -march instead of -mcpu.")); | |
1080 | } | |
1081 | ||
a8e8e863 DJ |
1082 | #if 1 |
1083 | /* For backward compatibility, let -mipsN set various defaults. */ | |
1084 | /* This code should go away, to be replaced with something rather more | |
1085 | draconian. Until GCC 3.1 has been released for some reasonable | |
1086 | amount of time, however, we need to support this. */ | |
1087 | if (mips_opts.isa != ISA_UNKNOWN) | |
1088 | { | |
1089 | /* Translate -mipsN to the appropriate settings of file_mips_gp32 | |
1090 | and file_mips_fp32. Tag binaries as using the mipsN ISA. */ | |
1091 | if (file_mips_gp32 < 0) | |
1092 | { | |
1093 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1094 | file_mips_gp32 = 0; | |
1095 | else | |
1096 | file_mips_gp32 = 1; | |
1097 | } | |
1098 | if (file_mips_fp32 < 0) | |
1099 | { | |
1100 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1101 | file_mips_fp32 = 0; | |
1102 | else | |
1103 | file_mips_fp32 = 1; | |
1104 | } | |
1105 | ||
1106 | ci = mips_cpu_info_from_isa (mips_opts.isa); | |
1107 | assert (ci != NULL); | |
1108 | /* -mipsN has higher priority than -mcpu but lower than -march. */ | |
1109 | if (mips_arch == CPU_UNKNOWN) | |
1110 | mips_arch = ci->cpu; | |
1111 | ||
1112 | /* Default mips_abi. */ | |
1113 | if (mips_opts.abi == NO_ABI) | |
1114 | { | |
1115 | if (mips_opts.isa == ISA_MIPS1 || mips_opts.isa == ISA_MIPS2) | |
1116 | mips_opts.abi = O32_ABI; | |
1117 | else if (mips_opts.isa == ISA_MIPS3 || mips_opts.isa == ISA_MIPS4) | |
1118 | mips_opts.abi = O64_ABI; | |
1119 | } | |
1120 | } | |
1121 | ||
6dce9e24 TS |
1122 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) |
1123 | { | |
1124 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1125 | assert (ci != NULL); | |
1126 | mips_arch = ci->cpu; | |
1127 | as_warn (_("The -mcpu option is deprecated. Please use -march and " | |
1128 | "-mtune instead.")); | |
1129 | } | |
1130 | ||
a8e8e863 DJ |
1131 | /* Set tune from -mcpu, not from -mipsN. */ |
1132 | if (mips_tune == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) | |
1133 | { | |
1134 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1135 | assert (ci != NULL); | |
1136 | mips_tune = ci->cpu; | |
1137 | } | |
1138 | ||
ec68c924 | 1139 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was |
e7af610e NC |
1140 | specified on the command line, or some other value if one was. |
1141 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
1142 | the command line, or will be set otherwise if one was. */ | |
a8e8e863 DJ |
1143 | |
1144 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) | |
1145 | /* Handled above. */; | |
1146 | #else | |
1147 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) | |
1148 | { | |
1149 | ci = mips_cpu_info_from_cpu (mips_cpu); | |
1150 | assert (ci != NULL); | |
1151 | mips_arch = ci->cpu; | |
1152 | as_warn (_("The -mcpu option is deprecated. Please use -march and " | |
1153 | "-mtune instead.")); | |
1154 | } | |
1155 | ||
1156 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was | |
1157 | specified on the command line, or some other value if one was. | |
1158 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on | |
1159 | the command line, or will be set otherwise if one was. */ | |
1160 | ||
ec68c924 | 1161 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
252b5132 | 1162 | { |
1ff54a84 TS |
1163 | /* We have to check if the isa is the default isa of arch. Otherwise |
1164 | we'll get invalid object file headers. */ | |
1165 | ci = mips_cpu_info_from_cpu (mips_arch); | |
1166 | assert (ci != NULL); | |
1167 | if (mips_opts.isa != ci->isa) | |
1168 | { | |
1169 | /* This really should be an error instead of a warning, but old | |
1170 | compilers only have -mcpu which sets both arch and tune. For | |
1171 | now, we discard arch and preserve tune. */ | |
1172 | as_warn (_("The -march option is incompatible to -mipsN and " | |
1173 | "therefore ignored.")); | |
1174 | if (mips_tune == CPU_UNKNOWN) | |
1175 | mips_tune = mips_arch; | |
1176 | ci = mips_cpu_info_from_isa (mips_opts.isa); | |
1177 | assert (ci != NULL); | |
1178 | mips_arch = ci->cpu; | |
1179 | } | |
252b5132 | 1180 | } |
a8e8e863 | 1181 | #endif |
ec68c924 | 1182 | else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) |
252b5132 | 1183 | { |
ec68c924 EC |
1184 | /* We have ARCH, we need ISA. */ |
1185 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1186 | assert (ci != NULL); |
1187 | mips_opts.isa = ci->isa; | |
1188 | } | |
ec68c924 | 1189 | else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
e7af610e | 1190 | { |
ec68c924 | 1191 | /* We have ISA, we need default ARCH. */ |
e7af610e NC |
1192 | ci = mips_cpu_info_from_isa (mips_opts.isa); |
1193 | assert (ci != NULL); | |
ec68c924 EC |
1194 | mips_arch = ci->cpu; |
1195 | } | |
e7af610e NC |
1196 | else |
1197 | { | |
ec68c924 | 1198 | /* We need to set both ISA and ARCH from target cpu. */ |
e7af610e NC |
1199 | ci = mips_cpu_info_from_name (cpu); |
1200 | if (ci == NULL) | |
beae10d5 | 1201 | ci = mips_cpu_info_from_cpu (CPU_R3000); |
e7af610e NC |
1202 | assert (ci != NULL); |
1203 | mips_opts.isa = ci->isa; | |
ec68c924 | 1204 | mips_arch = ci->cpu; |
252b5132 RH |
1205 | } |
1206 | ||
ec68c924 EC |
1207 | if (mips_tune == CPU_UNKNOWN) |
1208 | mips_tune = mips_arch; | |
1209 | ||
1210 | ci = mips_cpu_info_from_cpu (mips_arch); | |
e7af610e NC |
1211 | assert (ci != NULL); |
1212 | mips_isa_from_cpu = ci->isa; | |
1213 | ||
252b5132 | 1214 | /* End of TARGET_CPU processing, get rid of malloced memory |
bdaaa2e1 | 1215 | if necessary. */ |
252b5132 RH |
1216 | cpu = NULL; |
1217 | if (a != NULL) | |
1218 | { | |
156c2f8b NC |
1219 | free (a); |
1220 | a = NULL; | |
252b5132 RH |
1221 | } |
1222 | ||
e7af610e | 1223 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
252b5132 RH |
1224 | as_bad (_("trap exception not supported at ISA 1")); |
1225 | ||
1226 | /* Set the EABI kind based on the ISA before the user gets | |
1227 | to change the ISA with directives. This isn't really | |
bdaaa2e1 | 1228 | the best, but then neither is basing the abi on the isa. */ |
9ce8a5dd | 1229 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
a325df1d | 1230 | && mips_opts.abi == EABI_ABI) |
252b5132 RH |
1231 | mips_eabi64 = 1; |
1232 | ||
e7af610e NC |
1233 | /* If they asked for mips1 or mips2 and a cpu that is |
1234 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1235 | if (mips_isa_from_cpu != ISA_UNKNOWN | |
1236 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) | |
1237 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
1238 | mips_32bitmode = 1; | |
252b5132 | 1239 | |
1f25f5d3 CD |
1240 | /* If the selected architecture includes support for ASEs, enable |
1241 | generation of code for them. */ | |
1242 | if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch)) | |
1243 | mips_opts.ase_mips3d = 1; | |
1244 | ||
ec68c924 | 1245 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1246 | as_warn (_("Could not set architecture and machine")); |
1247 | ||
a8e8e863 DJ |
1248 | if (file_mips_gp32 < 0) |
1249 | file_mips_gp32 = 0; | |
1250 | if (file_mips_fp32 < 0) | |
1251 | file_mips_fp32 = 0; | |
1252 | ||
252b5132 | 1253 | file_mips_isa = mips_opts.isa; |
a325df1d | 1254 | file_mips_abi = mips_opts.abi; |
1f25f5d3 | 1255 | file_ase_mips3d = mips_opts.ase_mips3d; |
a325df1d TS |
1256 | mips_opts.gp32 = file_mips_gp32; |
1257 | mips_opts.fp32 = file_mips_fp32; | |
252b5132 | 1258 | |
438c16b8 TS |
1259 | if (HAVE_NEWABI) |
1260 | mips_big_got = 1; | |
1261 | ||
252b5132 RH |
1262 | op_hash = hash_new (); |
1263 | ||
1264 | for (i = 0; i < NUMOPCODES;) | |
1265 | { | |
1266 | const char *name = mips_opcodes[i].name; | |
1267 | ||
1268 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1269 | if (retval != NULL) | |
1270 | { | |
1271 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1272 | mips_opcodes[i].name, retval); | |
1273 | /* Probably a memory allocation problem? Give up now. */ | |
1274 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1275 | } | |
1276 | do | |
1277 | { | |
1278 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1279 | { | |
1280 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1281 | broken = 1; | |
1282 | } | |
1283 | ++i; | |
1284 | } | |
1285 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1286 | } | |
1287 | ||
1288 | mips16_op_hash = hash_new (); | |
1289 | ||
1290 | i = 0; | |
1291 | while (i < bfd_mips16_num_opcodes) | |
1292 | { | |
1293 | const char *name = mips16_opcodes[i].name; | |
1294 | ||
1295 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1296 | if (retval != NULL) | |
1297 | as_fatal (_("internal: can't hash `%s': %s"), | |
1298 | mips16_opcodes[i].name, retval); | |
1299 | do | |
1300 | { | |
1301 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1302 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1303 | != mips16_opcodes[i].match)) | |
1304 | { | |
1305 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1306 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1307 | broken = 1; | |
1308 | } | |
1309 | ++i; | |
1310 | } | |
1311 | while (i < bfd_mips16_num_opcodes | |
1312 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1313 | } | |
1314 | ||
1315 | if (broken) | |
1316 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1317 | ||
1318 | /* We add all the general register names to the symbol table. This | |
1319 | helps us detect invalid uses of them. */ | |
1320 | for (i = 0; i < 32; i++) | |
1321 | { | |
1322 | char buf[5]; | |
1323 | ||
1324 | sprintf (buf, "$%d", i); | |
1325 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1326 | &zero_address_frag)); | |
1327 | } | |
1328 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1329 | &zero_address_frag)); | |
1330 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1331 | &zero_address_frag)); | |
1332 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1333 | &zero_address_frag)); | |
1334 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1335 | &zero_address_frag)); | |
1336 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1337 | &zero_address_frag)); | |
1338 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1339 | &zero_address_frag)); | |
1340 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1341 | &zero_address_frag)); | |
1342 | ||
1343 | mips_no_prev_insn (false); | |
1344 | ||
1345 | mips_gprmask = 0; | |
1346 | mips_cprmask[0] = 0; | |
1347 | mips_cprmask[1] = 0; | |
1348 | mips_cprmask[2] = 0; | |
1349 | mips_cprmask[3] = 0; | |
1350 | ||
1351 | /* set the default alignment for the text section (2**2) */ | |
1352 | record_alignment (text_section, 2); | |
1353 | ||
1354 | if (USE_GLOBAL_POINTER_OPT) | |
1355 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1356 | ||
1357 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1358 | { | |
1359 | /* On a native system, sections must be aligned to 16 byte | |
1360 | boundaries. When configured for an embedded ELF target, we | |
1361 | don't bother. */ | |
1362 | if (strcmp (TARGET_OS, "elf") != 0) | |
1363 | { | |
1364 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1365 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1366 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1367 | } | |
1368 | ||
1369 | /* Create a .reginfo section for register masks and a .mdebug | |
1370 | section for debugging information. */ | |
1371 | { | |
1372 | segT seg; | |
1373 | subsegT subseg; | |
1374 | flagword flags; | |
1375 | segT sec; | |
1376 | ||
1377 | seg = now_seg; | |
1378 | subseg = now_subseg; | |
1379 | ||
1380 | /* The ABI says this section should be loaded so that the | |
1381 | running program can access it. However, we don't load it | |
1382 | if we are configured for an embedded target */ | |
1383 | flags = SEC_READONLY | SEC_DATA; | |
1384 | if (strcmp (TARGET_OS, "elf") != 0) | |
1385 | flags |= SEC_ALLOC | SEC_LOAD; | |
1386 | ||
195325d2 | 1387 | if (file_mips_abi != N64_ABI) |
252b5132 RH |
1388 | { |
1389 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1390 | ||
195325d2 TS |
1391 | bfd_set_section_flags (stdoutput, sec, flags); |
1392 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1393 | |
252b5132 RH |
1394 | #ifdef OBJ_ELF |
1395 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1396 | #endif | |
1397 | } | |
1398 | else | |
1399 | { | |
1400 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1401 | .reginfo section. */ | |
1402 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1403 | bfd_set_section_flags (stdoutput, sec, flags); |
1404 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1405 | |
1406 | #ifdef OBJ_ELF | |
1407 | /* Set up the option header. */ | |
1408 | { | |
1409 | Elf_Internal_Options opthdr; | |
1410 | char *f; | |
1411 | ||
1412 | opthdr.kind = ODK_REGINFO; | |
1413 | opthdr.size = (sizeof (Elf_External_Options) | |
1414 | + sizeof (Elf64_External_RegInfo)); | |
1415 | opthdr.section = 0; | |
1416 | opthdr.info = 0; | |
1417 | f = frag_more (sizeof (Elf_External_Options)); | |
1418 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1419 | (Elf_External_Options *) f); | |
1420 | ||
1421 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1422 | } | |
1423 | #endif | |
1424 | } | |
1425 | ||
1426 | if (ECOFF_DEBUGGING) | |
1427 | { | |
1428 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1429 | (void) bfd_set_section_flags (stdoutput, sec, | |
1430 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1431 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1432 | } | |
1433 | ||
1434 | #ifdef MIPS_STABS_ELF | |
1435 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1436 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1437 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1438 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1439 | #endif | |
1440 | ||
1441 | subseg_set (seg, subseg); | |
1442 | } | |
1443 | } | |
1444 | ||
1445 | if (! ECOFF_DEBUGGING) | |
1446 | md_obj_begin (); | |
1447 | } | |
1448 | ||
1449 | void | |
1450 | md_mips_end () | |
1451 | { | |
1452 | if (! ECOFF_DEBUGGING) | |
1453 | md_obj_end (); | |
1454 | } | |
1455 | ||
1456 | void | |
1457 | md_assemble (str) | |
1458 | char *str; | |
1459 | { | |
1460 | struct mips_cl_insn insn; | |
f6688943 TS |
1461 | bfd_reloc_code_real_type unused_reloc[3] |
1462 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1463 | |
1464 | imm_expr.X_op = O_absent; | |
252b5132 RH |
1465 | imm_unmatched_hi = false; |
1466 | offset_expr.X_op = O_absent; | |
f6688943 TS |
1467 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1468 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1469 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1470 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1471 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1472 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1473 | |
1474 | if (mips_opts.mips16) | |
1475 | mips16_ip (str, &insn); | |
1476 | else | |
1477 | { | |
1478 | mips_ip (str, &insn); | |
beae10d5 KH |
1479 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1480 | str, insn.insn_opcode)); | |
252b5132 RH |
1481 | } |
1482 | ||
1483 | if (insn_error) | |
1484 | { | |
1485 | as_bad ("%s `%s'", insn_error, str); | |
1486 | return; | |
1487 | } | |
1488 | ||
1489 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1490 | { | |
1491 | if (mips_opts.mips16) | |
1492 | mips16_macro (&insn); | |
1493 | else | |
1494 | macro (&insn); | |
1495 | } | |
1496 | else | |
1497 | { | |
1498 | if (imm_expr.X_op != O_absent) | |
c4e7957c | 1499 | append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi); |
252b5132 | 1500 | else if (offset_expr.X_op != O_absent) |
c4e7957c | 1501 | append_insn (NULL, &insn, &offset_expr, offset_reloc, false); |
252b5132 | 1502 | else |
c4e7957c | 1503 | append_insn (NULL, &insn, NULL, unused_reloc, false); |
252b5132 RH |
1504 | } |
1505 | } | |
1506 | ||
1507 | /* See whether instruction IP reads register REG. CLASS is the type | |
1508 | of register. */ | |
1509 | ||
1510 | static int | |
1511 | insn_uses_reg (ip, reg, class) | |
1512 | struct mips_cl_insn *ip; | |
1513 | unsigned int reg; | |
1514 | enum mips_regclass class; | |
1515 | { | |
1516 | if (class == MIPS16_REG) | |
1517 | { | |
1518 | assert (mips_opts.mips16); | |
1519 | reg = mips16_to_32_reg_map[reg]; | |
1520 | class = MIPS_GR_REG; | |
1521 | } | |
1522 | ||
1523 | /* Don't report on general register 0, since it never changes. */ | |
1524 | if (class == MIPS_GR_REG && reg == 0) | |
1525 | return 0; | |
1526 | ||
1527 | if (class == MIPS_FP_REG) | |
1528 | { | |
1529 | assert (! mips_opts.mips16); | |
1530 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1531 | This is not optimal, because it will introduce an unnecessary | |
1532 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1533 | need to distinguish reading both $f0 and $f1 or just one of | |
1534 | them. Note that we don't have to check the other way, | |
1535 | because there is no instruction that sets both $f0 and $f1 | |
1536 | and requires a delay. */ | |
1537 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1538 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1539 | == (reg &~ (unsigned) 1))) | |
1540 | return 1; | |
1541 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1542 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1543 | == (reg &~ (unsigned) 1))) | |
1544 | return 1; | |
1545 | } | |
1546 | else if (! mips_opts.mips16) | |
1547 | { | |
1548 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1549 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1550 | return 1; | |
1551 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1552 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1553 | return 1; | |
1554 | } | |
1555 | else | |
1556 | { | |
1557 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1558 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1559 | & MIPS16OP_MASK_RX)] | |
1560 | == reg)) | |
1561 | return 1; | |
1562 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1563 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1564 | & MIPS16OP_MASK_RY)] | |
1565 | == reg)) | |
1566 | return 1; | |
1567 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1568 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1569 | & MIPS16OP_MASK_MOVE32Z)] | |
1570 | == reg)) | |
1571 | return 1; | |
1572 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1573 | return 1; | |
1574 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1575 | return 1; | |
1576 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1577 | return 1; | |
1578 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1579 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1580 | & MIPS16OP_MASK_REGR32) == reg) | |
1581 | return 1; | |
1582 | } | |
1583 | ||
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | /* This function returns true if modifying a register requires a | |
1588 | delay. */ | |
1589 | ||
1590 | static int | |
1591 | reg_needs_delay (reg) | |
156c2f8b | 1592 | unsigned int reg; |
252b5132 RH |
1593 | { |
1594 | unsigned long prev_pinfo; | |
1595 | ||
1596 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1597 | if (! mips_opts.noreorder | |
9ce8a5dd | 1598 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1599 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1600 | || (! gpr_interlocks | |
1601 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1602 | { | |
1603 | /* A load from a coprocessor or from memory. All load | |
1604 | delays delay the use of general register rt for one | |
1605 | instruction on the r3000. The r6000 and r4000 use | |
1606 | interlocks. */ | |
bdaaa2e1 | 1607 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1608 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1609 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1610 | return 1; | |
1611 | } | |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1617 | handle them specially, such as generating jalx instructions when | |
1618 | needed. We also make them odd for the duration of the assembly, in | |
1619 | order to generate the right sort of code. We will make them even | |
1620 | in the adjust_symtab routine, while leaving them marked. This is | |
1621 | convenient for the debugger and the disassembler. The linker knows | |
1622 | to make them odd again. */ | |
1623 | ||
1624 | static void | |
1625 | mips16_mark_labels () | |
1626 | { | |
1627 | if (mips_opts.mips16) | |
1628 | { | |
1629 | struct insn_label_list *l; | |
98aa84af | 1630 | valueT val; |
252b5132 RH |
1631 | |
1632 | for (l = insn_labels; l != NULL; l = l->next) | |
1633 | { | |
1634 | #ifdef OBJ_ELF | |
1635 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1636 | S_SET_OTHER (l->label, STO_MIPS16); | |
1637 | #endif | |
98aa84af AM |
1638 | val = S_GET_VALUE (l->label); |
1639 | if ((val & 1) == 0) | |
1640 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1641 | } |
1642 | } | |
1643 | } | |
1644 | ||
1645 | /* Output an instruction. PLACE is where to put the instruction; if | |
1646 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1647 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1648 | used with RELOC_TYPE. */ | |
1649 | ||
1650 | static void | |
1651 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1652 | char *place; | |
1653 | struct mips_cl_insn *ip; | |
1654 | expressionS *address_expr; | |
f6688943 | 1655 | bfd_reloc_code_real_type *reloc_type; |
252b5132 RH |
1656 | boolean unmatched_hi; |
1657 | { | |
1658 | register unsigned long prev_pinfo, pinfo; | |
1659 | char *f; | |
f6688943 | 1660 | fixS *fixp[3]; |
252b5132 RH |
1661 | int nops = 0; |
1662 | ||
1663 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1664 | mips16_mark_labels (); |
252b5132 RH |
1665 | |
1666 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1667 | pinfo = ip->insn_mo->pinfo; | |
1668 | ||
1669 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1670 | { | |
1671 | int prev_prev_nop; | |
1672 | ||
1673 | /* If the previous insn required any delay slots, see if we need | |
1674 | to insert a NOP or two. There are eight kinds of possible | |
1675 | hazards, of which an instruction can have at most one type. | |
1676 | (1) a load from memory delay | |
1677 | (2) a load from a coprocessor delay | |
1678 | (3) an unconditional branch delay | |
1679 | (4) a conditional branch delay | |
1680 | (5) a move to coprocessor register delay | |
1681 | (6) a load coprocessor register from memory delay | |
1682 | (7) a coprocessor condition code delay | |
1683 | (8) a HI/LO special register delay | |
1684 | ||
1685 | There are a lot of optimizations we could do that we don't. | |
1686 | In particular, we do not, in general, reorder instructions. | |
1687 | If you use gcc with optimization, it will reorder | |
1688 | instructions and generally do much more optimization then we | |
1689 | do here; repeating all that work in the assembler would only | |
1690 | benefit hand written assembly code, and does not seem worth | |
1691 | it. */ | |
1692 | ||
1693 | /* This is how a NOP is emitted. */ | |
1694 | #define emit_nop() \ | |
1695 | (mips_opts.mips16 \ | |
1696 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1697 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1698 | ||
1699 | /* The previous insn might require a delay slot, depending upon | |
1700 | the contents of the current insn. */ | |
1701 | if (! mips_opts.mips16 | |
9ce8a5dd | 1702 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1703 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1704 | && ! cop_interlocks) | |
1705 | || (! gpr_interlocks | |
1706 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1707 | { | |
1708 | /* A load from a coprocessor or from memory. All load | |
1709 | delays delay the use of general register rt for one | |
1710 | instruction on the r3000. The r6000 and r4000 use | |
1711 | interlocks. */ | |
beae10d5 | 1712 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1713 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1714 | if (mips_optimize == 0 | |
1715 | || insn_uses_reg (ip, | |
1716 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1717 | & OP_MASK_RT), | |
1718 | MIPS_GR_REG)) | |
1719 | ++nops; | |
1720 | } | |
1721 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1722 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1723 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1724 | && ! cop_interlocks) |
e7af610e | 1725 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1726 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1727 | { | |
1728 | /* A generic coprocessor delay. The previous instruction | |
1729 | modified a coprocessor general or control register. If | |
1730 | it modified a control register, we need to avoid any | |
1731 | coprocessor instruction (this is probably not always | |
1732 | required, but it sometimes is). If it modified a general | |
1733 | register, we avoid using that register. | |
1734 | ||
1735 | On the r6000 and r4000 loading a coprocessor register | |
1736 | from memory is interlocked, and does not require a delay. | |
1737 | ||
1738 | This case is not handled very well. There is no special | |
1739 | knowledge of CP0 handling, and the coprocessors other | |
1740 | than the floating point unit are not distinguished at | |
1741 | all. */ | |
1742 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1743 | Need to modify this to include knowledge about |
252b5132 RH |
1744 | user specified delays! */ |
1745 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1746 | { | |
1747 | if (mips_optimize == 0 | |
1748 | || insn_uses_reg (ip, | |
1749 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1750 | & OP_MASK_FT), | |
1751 | MIPS_FP_REG)) | |
1752 | ++nops; | |
1753 | } | |
1754 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1755 | { | |
1756 | if (mips_optimize == 0 | |
1757 | || insn_uses_reg (ip, | |
1758 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1759 | & OP_MASK_FS), | |
1760 | MIPS_FP_REG)) | |
1761 | ++nops; | |
1762 | } | |
1763 | else | |
1764 | { | |
1765 | /* We don't know exactly what the previous instruction | |
1766 | does. If the current instruction uses a coprocessor | |
1767 | register, we must insert a NOP. If previous | |
1768 | instruction may set the condition codes, and the | |
1769 | current instruction uses them, we must insert two | |
1770 | NOPS. */ | |
bdaaa2e1 | 1771 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1772 | if (mips_optimize == 0 |
1773 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1774 | && (pinfo & INSN_READ_COND_CODE))) | |
1775 | nops += 2; | |
1776 | else if (pinfo & INSN_COP) | |
1777 | ++nops; | |
1778 | } | |
1779 | } | |
1780 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1781 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1782 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1783 | && ! cop_interlocks) | |
1784 | { | |
1785 | /* The previous instruction sets the coprocessor condition | |
1786 | codes, but does not require a general coprocessor delay | |
1787 | (this means it is a floating point comparison | |
1788 | instruction). If this instruction uses the condition | |
1789 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1790 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1791 | if (mips_optimize == 0 |
1792 | || (pinfo & INSN_READ_COND_CODE)) | |
1793 | ++nops; | |
1794 | } | |
6b76fefe CM |
1795 | |
1796 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1797 | previous insn was an mfhi/mflo and the current insn | |
1798 | reads the register that the mfhi/mflo wrote to, then | |
1799 | insert two nops. */ | |
1800 | ||
1801 | else if (mips_7000_hilo_fix | |
1802 | && MF_HILO_INSN (prev_pinfo) | |
1803 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1804 | & OP_MASK_RD), |
1805 | MIPS_GR_REG)) | |
6b76fefe CM |
1806 | { |
1807 | nops += 2; | |
1808 | } | |
1809 | ||
1810 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1811 | 2nd previous insn was an mfhi/mflo and the current insn | |
1812 | reads the register that the mfhi/mflo wrote to, then | |
1813 | insert one nop. */ | |
1814 | ||
1815 | else if (mips_7000_hilo_fix | |
1816 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1817 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1818 | & OP_MASK_RD), | |
1819 | MIPS_GR_REG)) | |
bdaaa2e1 | 1820 | |
6b76fefe | 1821 | { |
f9419b05 | 1822 | ++nops; |
6b76fefe | 1823 | } |
bdaaa2e1 | 1824 | |
252b5132 RH |
1825 | else if (prev_pinfo & INSN_READ_LO) |
1826 | { | |
1827 | /* The previous instruction reads the LO register; if the | |
1828 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1829 | insert two NOPS. Some newer processors have interlocks. |
1830 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1831 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1832 | though the tx39's divide insns still do require the |
1833 | delay. */ | |
252b5132 | 1834 | if (! (hilo_interlocks |
ec68c924 | 1835 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1836 | && (mips_optimize == 0 |
1837 | || (pinfo & INSN_WRITE_LO))) | |
1838 | nops += 2; | |
1839 | /* Most mips16 branch insns don't have a delay slot. | |
1840 | If a read from LO is immediately followed by a branch | |
1841 | to a write to LO we have a read followed by a write | |
1842 | less than 2 insns away. We assume the target of | |
1843 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1844 | between a read and an immediately following branch. */ |
252b5132 RH |
1845 | else if (mips_opts.mips16 |
1846 | && (mips_optimize == 0 | |
1847 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1848 | ++nops; |
252b5132 RH |
1849 | } |
1850 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1851 | { | |
1852 | /* The previous instruction reads the HI register; if the | |
1853 | current instruction writes to the HI register, we must | |
1854 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1855 | Also the note tx39's multiply above. */ |
252b5132 | 1856 | if (! (hilo_interlocks |
ec68c924 | 1857 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1858 | && (mips_optimize == 0 |
1859 | || (pinfo & INSN_WRITE_HI))) | |
1860 | nops += 2; | |
1861 | /* Most mips16 branch insns don't have a delay slot. | |
1862 | If a read from HI is immediately followed by a branch | |
1863 | to a write to HI we have a read followed by a write | |
1864 | less than 2 insns away. We assume the target of | |
1865 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1866 | between a read and an immediately following branch. */ |
252b5132 RH |
1867 | else if (mips_opts.mips16 |
1868 | && (mips_optimize == 0 | |
1869 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1870 | ++nops; |
252b5132 RH |
1871 | } |
1872 | ||
1873 | /* If the previous instruction was in a noreorder section, then | |
1874 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1875 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1876 | if (prev_insn_unreordered) |
1877 | nops = 0; | |
1878 | ||
1879 | /* There are two cases which require two intervening | |
1880 | instructions: 1) setting the condition codes using a move to | |
1881 | coprocessor instruction which requires a general coprocessor | |
1882 | delay and then reading the condition codes 2) reading the HI | |
1883 | or LO register and then writing to it (except on processors | |
1884 | which have interlocks). If we are not already emitting a NOP | |
1885 | instruction, we must check for these cases compared to the | |
1886 | instruction previous to the previous instruction. */ | |
1887 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1888 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1889 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1890 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1891 | && (pinfo & INSN_READ_COND_CODE) | |
1892 | && ! cop_interlocks) | |
1893 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1894 | && (pinfo & INSN_WRITE_LO) | |
1895 | && ! (hilo_interlocks | |
ec68c924 | 1896 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1897 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1898 | && (pinfo & INSN_WRITE_HI) | |
1899 | && ! (hilo_interlocks | |
ec68c924 | 1900 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1901 | prev_prev_nop = 1; |
1902 | else | |
1903 | prev_prev_nop = 0; | |
1904 | ||
1905 | if (prev_prev_insn_unreordered) | |
1906 | prev_prev_nop = 0; | |
1907 | ||
1908 | if (prev_prev_nop && nops == 0) | |
1909 | ++nops; | |
1910 | ||
1911 | /* If we are being given a nop instruction, don't bother with | |
1912 | one of the nops we would otherwise output. This will only | |
1913 | happen when a nop instruction is used with mips_optimize set | |
1914 | to 0. */ | |
1915 | if (nops > 0 | |
1916 | && ! mips_opts.noreorder | |
156c2f8b | 1917 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1918 | --nops; |
1919 | ||
1920 | /* Now emit the right number of NOP instructions. */ | |
1921 | if (nops > 0 && ! mips_opts.noreorder) | |
1922 | { | |
1923 | fragS *old_frag; | |
1924 | unsigned long old_frag_offset; | |
1925 | int i; | |
1926 | struct insn_label_list *l; | |
1927 | ||
1928 | old_frag = frag_now; | |
1929 | old_frag_offset = frag_now_fix (); | |
1930 | ||
1931 | for (i = 0; i < nops; i++) | |
1932 | emit_nop (); | |
1933 | ||
1934 | if (listing) | |
1935 | { | |
1936 | listing_prev_line (); | |
1937 | /* We may be at the start of a variant frag. In case we | |
1938 | are, make sure there is enough space for the frag | |
1939 | after the frags created by listing_prev_line. The | |
1940 | argument to frag_grow here must be at least as large | |
1941 | as the argument to all other calls to frag_grow in | |
1942 | this file. We don't have to worry about being in the | |
1943 | middle of a variant frag, because the variants insert | |
1944 | all needed nop instructions themselves. */ | |
1945 | frag_grow (40); | |
1946 | } | |
1947 | ||
1948 | for (l = insn_labels; l != NULL; l = l->next) | |
1949 | { | |
98aa84af AM |
1950 | valueT val; |
1951 | ||
252b5132 | 1952 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1953 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1954 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1955 | /* mips16 text labels are stored as odd. */ |
1956 | if (mips_opts.mips16) | |
f9419b05 | 1957 | ++val; |
98aa84af | 1958 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1959 | } |
1960 | ||
1961 | #ifndef NO_ECOFF_DEBUGGING | |
1962 | if (ECOFF_DEBUGGING) | |
1963 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1964 | #endif | |
1965 | } | |
1966 | else if (prev_nop_frag != NULL) | |
1967 | { | |
1968 | /* We have a frag holding nops we may be able to remove. If | |
1969 | we don't need any nops, we can decrease the size of | |
1970 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1971 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1972 | if (prev_nop_frag_since == 0) |
1973 | { | |
1974 | if (nops == 0) | |
1975 | { | |
1976 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1977 | --prev_nop_frag_holds; | |
1978 | } | |
1979 | else | |
1980 | prev_nop_frag_required += nops; | |
1981 | } | |
1982 | else | |
1983 | { | |
1984 | if (prev_prev_nop == 0) | |
1985 | { | |
1986 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1987 | --prev_nop_frag_holds; | |
1988 | } | |
1989 | else | |
1990 | ++prev_nop_frag_required; | |
1991 | } | |
1992 | ||
1993 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1994 | prev_nop_frag = NULL; | |
1995 | ||
1996 | ++prev_nop_frag_since; | |
1997 | ||
1998 | /* Sanity check: by the time we reach the second instruction | |
1999 | after prev_nop_frag, we should have used up all the nops | |
2000 | one way or another. */ | |
2001 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
2002 | } | |
2003 | } | |
2004 | ||
f6688943 | 2005 | if (*reloc_type > BFD_RELOC_UNUSED) |
252b5132 RH |
2006 | { |
2007 | /* We need to set up a variant frag. */ | |
2008 | assert (mips_opts.mips16 && address_expr != NULL); | |
2009 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2010 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2011 | mips16_small, mips16_ext, |
2012 | (prev_pinfo | |
2013 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2014 | (*prev_insn_reloc_type |
252b5132 | 2015 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2016 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
2017 | } |
2018 | else if (place != NULL) | |
2019 | f = place; | |
2020 | else if (mips_opts.mips16 | |
2021 | && ! ip->use_extend | |
f6688943 | 2022 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2023 | { |
2024 | /* Make sure there is enough room to swap this instruction with | |
2025 | a following jump instruction. */ | |
2026 | frag_grow (6); | |
2027 | f = frag_more (2); | |
2028 | } | |
2029 | else | |
2030 | { | |
2031 | if (mips_opts.mips16 | |
2032 | && mips_opts.noreorder | |
2033 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2034 | as_warn (_("extended instruction in delay slot")); | |
2035 | ||
2036 | f = frag_more (4); | |
2037 | } | |
2038 | ||
f6688943 TS |
2039 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2040 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2041 | { |
2042 | if (address_expr->X_op == O_constant) | |
2043 | { | |
4db1a35d | 2044 | valueT tmp; |
f6688943 TS |
2045 | |
2046 | switch (*reloc_type) | |
252b5132 RH |
2047 | { |
2048 | case BFD_RELOC_32: | |
2049 | ip->insn_opcode |= address_expr->X_add_number; | |
2050 | break; | |
2051 | ||
f6688943 TS |
2052 | case BFD_RELOC_MIPS_HIGHEST: |
2053 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
2054 | tmp >>= 16; | |
2055 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2056 | break; | |
2057 | ||
2058 | case BFD_RELOC_MIPS_HIGHER: | |
2059 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2060 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2061 | break; | |
2062 | ||
2063 | case BFD_RELOC_HI16_S: | |
2064 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2065 | >> 16) & 0xffff; | |
2066 | break; | |
2067 | ||
2068 | case BFD_RELOC_HI16: | |
2069 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2070 | break; | |
2071 | ||
252b5132 RH |
2072 | case BFD_RELOC_LO16: |
2073 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
2074 | break; | |
2075 | ||
2076 | case BFD_RELOC_MIPS_JMP: | |
2077 | if ((address_expr->X_add_number & 3) != 0) | |
2078 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2079 | (unsigned long) address_expr->X_add_number); | |
7496292d TS |
2080 | if (address_expr->X_add_number & ~0xfffffff |
2081 | || address_expr->X_add_number > 0x7fffffc) | |
2082 | as_bad (_("jump address range overflow (0x%lx)"), | |
2083 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2084 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2085 | break; | |
2086 | ||
2087 | case BFD_RELOC_MIPS16_JMP: | |
2088 | if ((address_expr->X_add_number & 3) != 0) | |
2089 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2090 | (unsigned long) address_expr->X_add_number); | |
7496292d TS |
2091 | if (address_expr->X_add_number & ~0xfffffff |
2092 | || address_expr->X_add_number > 0x7fffffc) | |
2093 | as_bad (_("jump address range overflow (0x%lx)"), | |
2094 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2095 | ip->insn_opcode |= |
2096 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2097 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2098 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2099 | break; | |
2100 | ||
cb56d3d3 | 2101 | case BFD_RELOC_16_PCREL: |
233b8738 | 2102 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
cb56d3d3 TS |
2103 | break; |
2104 | ||
252b5132 RH |
2105 | case BFD_RELOC_16_PCREL_S2: |
2106 | goto need_reloc; | |
2107 | ||
2108 | default: | |
2109 | internalError (); | |
2110 | } | |
2111 | } | |
2112 | else | |
2113 | { | |
2114 | need_reloc: | |
f6688943 | 2115 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
2116 | if (place == NULL) |
2117 | { | |
f6688943 TS |
2118 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
2119 | address_expr, | |
2120 | (*reloc_type == BFD_RELOC_16_PCREL | |
2121 | || *reloc_type == BFD_RELOC_16_PCREL_S2), | |
2122 | reloc_type[0]); | |
2123 | ||
b6ff326e | 2124 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2125 | 4 octets for 64bit assembly. */ |
2126 | if (HAVE_64BIT_GPRS && | |
2127 | (*reloc_type == BFD_RELOC_16 | |
98d3f06f KH |
2128 | || *reloc_type == BFD_RELOC_32 |
2129 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2130 | || *reloc_type == BFD_RELOC_HI16_S | |
2131 | || *reloc_type == BFD_RELOC_LO16 | |
2132 | || *reloc_type == BFD_RELOC_GPREL16 | |
2133 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2134 | || *reloc_type == BFD_RELOC_GPREL32 | |
2135 | || *reloc_type == BFD_RELOC_64 | |
2136 | || *reloc_type == BFD_RELOC_CTOR | |
2137 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2138 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2139 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2140 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2141 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2142 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
2143 | fixp[0]->fx_no_overflow = 1; |
2144 | ||
252b5132 RH |
2145 | if (unmatched_hi) |
2146 | { | |
2147 | struct mips_hi_fixup *hi_fixup; | |
2148 | ||
f6688943 | 2149 | assert (*reloc_type == BFD_RELOC_HI16_S); |
252b5132 RH |
2150 | hi_fixup = ((struct mips_hi_fixup *) |
2151 | xmalloc (sizeof (struct mips_hi_fixup))); | |
f6688943 | 2152 | hi_fixup->fixp = fixp[0]; |
252b5132 RH |
2153 | hi_fixup->seg = now_seg; |
2154 | hi_fixup->next = mips_hi_fixup_list; | |
2155 | mips_hi_fixup_list = hi_fixup; | |
2156 | } | |
f6688943 TS |
2157 | |
2158 | if (reloc_type[1] != BFD_RELOC_UNUSED) | |
2159 | { | |
2160 | /* FIXME: This symbol can be one of | |
2161 | RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */ | |
2162 | address_expr->X_op = O_absent; | |
2163 | address_expr->X_add_symbol = 0; | |
2164 | address_expr->X_add_number = 0; | |
2165 | ||
2166 | fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2167 | 4, address_expr, false, | |
2168 | reloc_type[1]); | |
2169 | ||
b6ff326e | 2170 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2171 | 4 octets for 64bit assembly. */ |
2172 | if (HAVE_64BIT_GPRS && | |
2173 | (*reloc_type == BFD_RELOC_16 | |
2174 | || *reloc_type == BFD_RELOC_32 | |
2175 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2176 | || *reloc_type == BFD_RELOC_HI16_S | |
2177 | || *reloc_type == BFD_RELOC_LO16 | |
2178 | || *reloc_type == BFD_RELOC_GPREL16 | |
2179 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2180 | || *reloc_type == BFD_RELOC_GPREL32 | |
2181 | || *reloc_type == BFD_RELOC_64 | |
2182 | || *reloc_type == BFD_RELOC_CTOR | |
2183 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2184 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2185 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2186 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2187 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2188 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2189 | fixp[1]->fx_no_overflow = 1; |
f6688943 TS |
2190 | |
2191 | if (reloc_type[2] != BFD_RELOC_UNUSED) | |
2192 | { | |
2193 | address_expr->X_op = O_absent; | |
2194 | address_expr->X_add_symbol = 0; | |
2195 | address_expr->X_add_number = 0; | |
2196 | ||
2197 | fixp[2] = fix_new_exp (frag_now, | |
2198 | f - frag_now->fr_literal, 4, | |
2199 | address_expr, false, | |
2200 | reloc_type[2]); | |
2201 | ||
b6ff326e | 2202 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
2203 | 4 octets for 64bit assembly. */ |
2204 | if (HAVE_64BIT_GPRS && | |
2205 | (*reloc_type == BFD_RELOC_16 | |
2206 | || *reloc_type == BFD_RELOC_32 | |
2207 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
2208 | || *reloc_type == BFD_RELOC_HI16_S | |
2209 | || *reloc_type == BFD_RELOC_LO16 | |
2210 | || *reloc_type == BFD_RELOC_GPREL16 | |
2211 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
2212 | || *reloc_type == BFD_RELOC_GPREL32 | |
2213 | || *reloc_type == BFD_RELOC_64 | |
2214 | || *reloc_type == BFD_RELOC_CTOR | |
2215 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
2216 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
2217 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
2218 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
2219 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2220 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2221 | fixp[2]->fx_no_overflow = 1; |
f6688943 TS |
2222 | } |
2223 | } | |
252b5132 RH |
2224 | } |
2225 | } | |
2226 | } | |
2227 | ||
2228 | if (! mips_opts.mips16) | |
2229 | md_number_to_chars (f, ip->insn_opcode, 4); | |
f6688943 | 2230 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2231 | { |
2232 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2233 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
2234 | } | |
2235 | else | |
2236 | { | |
2237 | if (ip->use_extend) | |
2238 | { | |
2239 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2240 | f += 2; | |
2241 | } | |
2242 | md_number_to_chars (f, ip->insn_opcode, 2); | |
2243 | } | |
2244 | ||
2245 | /* Update the register mask information. */ | |
2246 | if (! mips_opts.mips16) | |
2247 | { | |
2248 | if (pinfo & INSN_WRITE_GPR_D) | |
2249 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2250 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2251 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2252 | if (pinfo & INSN_READ_GPR_S) | |
2253 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2254 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2255 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2256 | if (pinfo & INSN_WRITE_FPR_D) |
2257 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2258 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2259 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2260 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2261 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2262 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2263 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2264 | if (pinfo & INSN_COP) | |
2265 | { | |
bdaaa2e1 KH |
2266 | /* We don't keep enough information to sort these cases out. |
2267 | The itbl support does keep this information however, although | |
2268 | we currently don't support itbl fprmats as part of the cop | |
2269 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2270 | } |
2271 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2272 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2273 | } |
2274 | else | |
2275 | { | |
2276 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2277 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2278 | & MIPS16OP_MASK_RX); | |
2279 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2280 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2281 | & MIPS16OP_MASK_RY); | |
2282 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2283 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2284 | & MIPS16OP_MASK_RZ); | |
2285 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2286 | mips_gprmask |= 1 << TREG; | |
2287 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2288 | mips_gprmask |= 1 << SP; | |
2289 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2290 | mips_gprmask |= 1 << RA; | |
2291 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2292 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2293 | if (pinfo & MIPS16_INSN_READ_Z) | |
2294 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2295 | & MIPS16OP_MASK_MOVE32Z); | |
2296 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2297 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2298 | & MIPS16OP_MASK_REGR32); | |
2299 | } | |
2300 | ||
2301 | if (place == NULL && ! mips_opts.noreorder) | |
2302 | { | |
2303 | /* Filling the branch delay slot is more complex. We try to | |
2304 | switch the branch with the previous instruction, which we can | |
2305 | do if the previous instruction does not set up a condition | |
2306 | that the branch tests and if the branch is not itself the | |
2307 | target of any branch. */ | |
2308 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2309 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2310 | { | |
2311 | if (mips_optimize < 2 | |
2312 | /* If we have seen .set volatile or .set nomove, don't | |
2313 | optimize. */ | |
2314 | || mips_opts.nomove != 0 | |
2315 | /* If we had to emit any NOP instructions, then we | |
2316 | already know we can not swap. */ | |
2317 | || nops != 0 | |
2318 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2319 | swap. */ |
252b5132 RH |
2320 | || ! prev_insn_valid |
2321 | /* If the previous insn is already in a branch delay | |
2322 | slot, then we can not swap. */ | |
2323 | || prev_insn_is_delay_slot | |
2324 | /* If the previous previous insn was in a .set | |
2325 | noreorder, we can't swap. Actually, the MIPS | |
2326 | assembler will swap in this situation. However, gcc | |
2327 | configured -with-gnu-as will generate code like | |
2328 | .set noreorder | |
2329 | lw $4,XXX | |
2330 | .set reorder | |
2331 | INSN | |
2332 | bne $4,$0,foo | |
2333 | in which we can not swap the bne and INSN. If gcc is | |
2334 | not configured -with-gnu-as, it does not output the | |
2335 | .set pseudo-ops. We don't have to check | |
2336 | prev_insn_unreordered, because prev_insn_valid will | |
2337 | be 0 in that case. We don't want to use | |
2338 | prev_prev_insn_valid, because we do want to be able | |
2339 | to swap at the start of a function. */ | |
2340 | || prev_prev_insn_unreordered | |
2341 | /* If the branch is itself the target of a branch, we | |
2342 | can not swap. We cheat on this; all we check for is | |
2343 | whether there is a label on this instruction. If | |
2344 | there are any branches to anything other than a | |
2345 | label, users must use .set noreorder. */ | |
2346 | || insn_labels != NULL | |
2347 | /* If the previous instruction is in a variant frag, we | |
2348 | can not do the swap. This does not apply to the | |
2349 | mips16, which uses variant frags for different | |
2350 | purposes. */ | |
2351 | || (! mips_opts.mips16 | |
2352 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2353 | /* If the branch reads the condition codes, we don't | |
2354 | even try to swap, because in the sequence | |
2355 | ctc1 $X,$31 | |
2356 | INSN | |
2357 | INSN | |
2358 | bc1t LABEL | |
2359 | we can not swap, and I don't feel like handling that | |
2360 | case. */ | |
2361 | || (! mips_opts.mips16 | |
9ce8a5dd | 2362 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2363 | && (pinfo & INSN_READ_COND_CODE)) |
2364 | /* We can not swap with an instruction that requires a | |
2365 | delay slot, becase the target of the branch might | |
2366 | interfere with that instruction. */ | |
2367 | || (! mips_opts.mips16 | |
9ce8a5dd | 2368 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2369 | && (prev_pinfo |
bdaaa2e1 | 2370 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2371 | & (INSN_LOAD_COPROC_DELAY |
2372 | | INSN_COPROC_MOVE_DELAY | |
2373 | | INSN_WRITE_COND_CODE))) | |
2374 | || (! (hilo_interlocks | |
ec68c924 | 2375 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2376 | && (prev_pinfo |
2377 | & (INSN_READ_LO | |
2378 | | INSN_READ_HI))) | |
2379 | || (! mips_opts.mips16 | |
2380 | && ! gpr_interlocks | |
2381 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2382 | || (! mips_opts.mips16 | |
e7af610e | 2383 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2384 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2385 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2386 | /* We can not swap with a branch instruction. */ | |
2387 | || (prev_pinfo | |
2388 | & (INSN_UNCOND_BRANCH_DELAY | |
2389 | | INSN_COND_BRANCH_DELAY | |
2390 | | INSN_COND_BRANCH_LIKELY)) | |
2391 | /* We do not swap with a trap instruction, since it | |
2392 | complicates trap handlers to have the trap | |
2393 | instruction be in a delay slot. */ | |
2394 | || (prev_pinfo & INSN_TRAP) | |
2395 | /* If the branch reads a register that the previous | |
2396 | instruction sets, we can not swap. */ | |
2397 | || (! mips_opts.mips16 | |
2398 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2399 | && insn_uses_reg (ip, | |
2400 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2401 | & OP_MASK_RT), | |
2402 | MIPS_GR_REG)) | |
2403 | || (! mips_opts.mips16 | |
2404 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2405 | && insn_uses_reg (ip, | |
2406 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2407 | & OP_MASK_RD), | |
2408 | MIPS_GR_REG)) | |
2409 | || (mips_opts.mips16 | |
2410 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2411 | && insn_uses_reg (ip, | |
2412 | ((prev_insn.insn_opcode | |
2413 | >> MIPS16OP_SH_RX) | |
2414 | & MIPS16OP_MASK_RX), | |
2415 | MIPS16_REG)) | |
2416 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2417 | && insn_uses_reg (ip, | |
2418 | ((prev_insn.insn_opcode | |
2419 | >> MIPS16OP_SH_RY) | |
2420 | & MIPS16OP_MASK_RY), | |
2421 | MIPS16_REG)) | |
2422 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2423 | && insn_uses_reg (ip, | |
2424 | ((prev_insn.insn_opcode | |
2425 | >> MIPS16OP_SH_RZ) | |
2426 | & MIPS16OP_MASK_RZ), | |
2427 | MIPS16_REG)) | |
2428 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2429 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2430 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2431 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2432 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2433 | && insn_uses_reg (ip, | |
2434 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2435 | insn_opcode), | |
2436 | MIPS_GR_REG)))) | |
2437 | /* If the branch writes a register that the previous | |
2438 | instruction sets, we can not swap (we know that | |
2439 | branches write only to RD or to $31). */ | |
2440 | || (! mips_opts.mips16 | |
2441 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2442 | && (((pinfo & INSN_WRITE_GPR_D) | |
2443 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2444 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2445 | || ((pinfo & INSN_WRITE_GPR_31) | |
2446 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2447 | & OP_MASK_RT) | |
f9419b05 | 2448 | == RA)))) |
252b5132 RH |
2449 | || (! mips_opts.mips16 |
2450 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2451 | && (((pinfo & INSN_WRITE_GPR_D) | |
2452 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2453 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2454 | || ((pinfo & INSN_WRITE_GPR_31) | |
2455 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2456 | & OP_MASK_RD) | |
f9419b05 | 2457 | == RA)))) |
252b5132 RH |
2458 | || (mips_opts.mips16 |
2459 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2460 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2461 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2462 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2463 | == RA)))) | |
2464 | /* If the branch writes a register that the previous | |
2465 | instruction reads, we can not swap (we know that | |
2466 | branches only write to RD or to $31). */ | |
2467 | || (! mips_opts.mips16 | |
2468 | && (pinfo & INSN_WRITE_GPR_D) | |
2469 | && insn_uses_reg (&prev_insn, | |
2470 | ((ip->insn_opcode >> OP_SH_RD) | |
2471 | & OP_MASK_RD), | |
2472 | MIPS_GR_REG)) | |
2473 | || (! mips_opts.mips16 | |
2474 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2475 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2476 | || (mips_opts.mips16 |
2477 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2478 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2479 | /* If we are generating embedded PIC code, the branch | |
2480 | might be expanded into a sequence which uses $at, so | |
2481 | we can't swap with an instruction which reads it. */ | |
2482 | || (mips_pic == EMBEDDED_PIC | |
2483 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2484 | /* If the previous previous instruction has a load | |
2485 | delay, and sets a register that the branch reads, we | |
2486 | can not swap. */ | |
2487 | || (! mips_opts.mips16 | |
9ce8a5dd | 2488 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2489 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2490 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2491 | || (! gpr_interlocks | |
2492 | && (prev_prev_insn.insn_mo->pinfo | |
2493 | & INSN_LOAD_MEMORY_DELAY))) | |
2494 | && insn_uses_reg (ip, | |
2495 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2496 | & OP_MASK_RT), | |
2497 | MIPS_GR_REG)) | |
2498 | /* If one instruction sets a condition code and the | |
2499 | other one uses a condition code, we can not swap. */ | |
2500 | || ((pinfo & INSN_READ_COND_CODE) | |
2501 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2502 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2503 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2504 | /* If the previous instruction uses the PC, we can not | |
2505 | swap. */ | |
2506 | || (mips_opts.mips16 | |
2507 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2508 | /* If the previous instruction was extended, we can not | |
2509 | swap. */ | |
2510 | || (mips_opts.mips16 && prev_insn_extended) | |
2511 | /* If the previous instruction had a fixup in mips16 | |
2512 | mode, we can not swap. This normally means that the | |
2513 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2514 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2515 | /* If the previous instruction is a sync, sync.l, or |
2516 | sync.p, we can not swap. */ | |
f173e82e | 2517 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2518 | { |
2519 | /* We could do even better for unconditional branches to | |
2520 | portions of this object file; we could pick up the | |
2521 | instruction at the destination, put it in the delay | |
2522 | slot, and bump the destination address. */ | |
2523 | emit_nop (); | |
2524 | /* Update the previous insn information. */ | |
2525 | prev_prev_insn = *ip; | |
2526 | prev_insn.insn_mo = &dummy_opcode; | |
2527 | } | |
2528 | else | |
2529 | { | |
2530 | /* It looks like we can actually do the swap. */ | |
2531 | if (! mips_opts.mips16) | |
2532 | { | |
2533 | char *prev_f; | |
2534 | char temp[4]; | |
2535 | ||
2536 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2537 | memcpy (temp, prev_f, 4); | |
2538 | memcpy (prev_f, f, 4); | |
2539 | memcpy (f, temp, 4); | |
f6688943 TS |
2540 | if (prev_insn_fixp[0]) |
2541 | { | |
2542 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2543 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2544 | } | |
2545 | if (prev_insn_fixp[1]) | |
2546 | { | |
2547 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2548 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2549 | } | |
2550 | if (prev_insn_fixp[2]) | |
252b5132 | 2551 | { |
f6688943 TS |
2552 | prev_insn_fixp[2]->fx_frag = frag_now; |
2553 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2554 | } |
f6688943 | 2555 | if (fixp[0]) |
252b5132 | 2556 | { |
f6688943 TS |
2557 | fixp[0]->fx_frag = prev_insn_frag; |
2558 | fixp[0]->fx_where = prev_insn_where; | |
2559 | } | |
2560 | if (fixp[1]) | |
2561 | { | |
2562 | fixp[1]->fx_frag = prev_insn_frag; | |
2563 | fixp[1]->fx_where = prev_insn_where; | |
2564 | } | |
2565 | if (fixp[2]) | |
2566 | { | |
2567 | fixp[2]->fx_frag = prev_insn_frag; | |
2568 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2569 | } |
2570 | } | |
2571 | else | |
2572 | { | |
2573 | char *prev_f; | |
2574 | char temp[2]; | |
2575 | ||
f6688943 TS |
2576 | assert (prev_insn_fixp[0] == NULL); |
2577 | assert (prev_insn_fixp[1] == NULL); | |
2578 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2579 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2580 | memcpy (temp, prev_f, 2); | |
2581 | memcpy (prev_f, f, 2); | |
f6688943 | 2582 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2583 | { |
f6688943 | 2584 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2585 | memcpy (f, temp, 2); |
2586 | } | |
2587 | else | |
2588 | { | |
2589 | memcpy (f, f + 2, 2); | |
2590 | memcpy (f + 2, temp, 2); | |
2591 | } | |
f6688943 TS |
2592 | if (fixp[0]) |
2593 | { | |
2594 | fixp[0]->fx_frag = prev_insn_frag; | |
2595 | fixp[0]->fx_where = prev_insn_where; | |
2596 | } | |
2597 | if (fixp[1]) | |
2598 | { | |
2599 | fixp[1]->fx_frag = prev_insn_frag; | |
2600 | fixp[1]->fx_where = prev_insn_where; | |
2601 | } | |
2602 | if (fixp[2]) | |
252b5132 | 2603 | { |
f6688943 TS |
2604 | fixp[2]->fx_frag = prev_insn_frag; |
2605 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2606 | } |
2607 | } | |
2608 | ||
2609 | /* Update the previous insn information; leave prev_insn | |
2610 | unchanged. */ | |
2611 | prev_prev_insn = *ip; | |
2612 | } | |
2613 | prev_insn_is_delay_slot = 1; | |
2614 | ||
2615 | /* If that was an unconditional branch, forget the previous | |
2616 | insn information. */ | |
2617 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2618 | { | |
2619 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2620 | prev_insn.insn_mo = &dummy_opcode; | |
2621 | } | |
2622 | ||
f6688943 TS |
2623 | prev_insn_fixp[0] = NULL; |
2624 | prev_insn_fixp[1] = NULL; | |
2625 | prev_insn_fixp[2] = NULL; | |
2626 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2627 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2628 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2629 | prev_insn_extended = 0; |
2630 | } | |
2631 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2632 | { | |
2633 | /* We don't yet optimize a branch likely. What we should do | |
2634 | is look at the target, copy the instruction found there | |
2635 | into the delay slot, and increment the branch to jump to | |
2636 | the next instruction. */ | |
2637 | emit_nop (); | |
2638 | /* Update the previous insn information. */ | |
2639 | prev_prev_insn = *ip; | |
2640 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2641 | prev_insn_fixp[0] = NULL; |
2642 | prev_insn_fixp[1] = NULL; | |
2643 | prev_insn_fixp[2] = NULL; | |
2644 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2645 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2646 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2647 | prev_insn_extended = 0; |
2648 | } | |
2649 | else | |
2650 | { | |
2651 | /* Update the previous insn information. */ | |
2652 | if (nops > 0) | |
2653 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2654 | else | |
2655 | prev_prev_insn = prev_insn; | |
2656 | prev_insn = *ip; | |
2657 | ||
2658 | /* Any time we see a branch, we always fill the delay slot | |
2659 | immediately; since this insn is not a branch, we know it | |
2660 | is not in a delay slot. */ | |
2661 | prev_insn_is_delay_slot = 0; | |
2662 | ||
f6688943 TS |
2663 | prev_insn_fixp[0] = fixp[0]; |
2664 | prev_insn_fixp[1] = fixp[1]; | |
2665 | prev_insn_fixp[2] = fixp[2]; | |
2666 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2667 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2668 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2669 | if (mips_opts.mips16) |
2670 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2671 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2672 | } |
2673 | ||
2674 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2675 | prev_insn_unreordered = 0; | |
2676 | prev_insn_frag = frag_now; | |
2677 | prev_insn_where = f - frag_now->fr_literal; | |
2678 | prev_insn_valid = 1; | |
2679 | } | |
2680 | else if (place == NULL) | |
2681 | { | |
2682 | /* We need to record a bit of information even when we are not | |
2683 | reordering, in order to determine the base address for mips16 | |
2684 | PC relative relocs. */ | |
2685 | prev_prev_insn = prev_insn; | |
2686 | prev_insn = *ip; | |
f6688943 TS |
2687 | prev_insn_reloc_type[0] = reloc_type[0]; |
2688 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2689 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2690 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2691 | prev_insn_unreordered = 1; | |
2692 | } | |
2693 | ||
2694 | /* We just output an insn, so the next one doesn't have a label. */ | |
2695 | mips_clear_insn_labels (); | |
2696 | ||
2697 | /* We must ensure that a fixup associated with an unmatched %hi | |
2698 | reloc does not become a variant frag. Otherwise, the | |
2699 | rearrangement of %hi relocs in frob_file may confuse | |
2700 | tc_gen_reloc. */ | |
2701 | if (unmatched_hi) | |
2702 | { | |
2703 | frag_wane (frag_now); | |
2704 | frag_new (0); | |
2705 | } | |
2706 | } | |
2707 | ||
2708 | /* This function forgets that there was any previous instruction or | |
2709 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2710 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2711 | |
2712 | static void | |
2713 | mips_no_prev_insn (preserve) | |
2714 | int preserve; | |
2715 | { | |
2716 | if (! preserve) | |
2717 | { | |
2718 | prev_insn.insn_mo = &dummy_opcode; | |
2719 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2720 | prev_nop_frag = NULL; | |
2721 | prev_nop_frag_holds = 0; | |
2722 | prev_nop_frag_required = 0; | |
2723 | prev_nop_frag_since = 0; | |
2724 | } | |
2725 | prev_insn_valid = 0; | |
2726 | prev_insn_is_delay_slot = 0; | |
2727 | prev_insn_unreordered = 0; | |
2728 | prev_insn_extended = 0; | |
f6688943 TS |
2729 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2730 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2731 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2732 | prev_prev_insn_unreordered = 0; |
2733 | mips_clear_insn_labels (); | |
2734 | } | |
2735 | ||
2736 | /* This function must be called whenever we turn on noreorder or emit | |
2737 | something other than instructions. It inserts any NOPS which might | |
2738 | be needed by the previous instruction, and clears the information | |
2739 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2740 | instructions are to follow. */ |
252b5132 RH |
2741 | |
2742 | static void | |
2743 | mips_emit_delays (insns) | |
2744 | boolean insns; | |
2745 | { | |
2746 | if (! mips_opts.noreorder) | |
2747 | { | |
2748 | int nops; | |
2749 | ||
2750 | nops = 0; | |
2751 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2752 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2753 | && (! cop_interlocks |
2754 | && (prev_insn.insn_mo->pinfo | |
2755 | & (INSN_LOAD_COPROC_DELAY | |
2756 | | INSN_COPROC_MOVE_DELAY | |
2757 | | INSN_WRITE_COND_CODE)))) | |
2758 | || (! hilo_interlocks | |
2759 | && (prev_insn.insn_mo->pinfo | |
2760 | & (INSN_READ_LO | |
2761 | | INSN_READ_HI))) | |
2762 | || (! mips_opts.mips16 | |
2763 | && ! gpr_interlocks | |
bdaaa2e1 | 2764 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2765 | & INSN_LOAD_MEMORY_DELAY)) |
2766 | || (! mips_opts.mips16 | |
e7af610e | 2767 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2768 | && (prev_insn.insn_mo->pinfo |
2769 | & INSN_COPROC_MEMORY_DELAY))) | |
2770 | { | |
beae10d5 | 2771 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2772 | ++nops; |
2773 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2774 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2775 | && (! cop_interlocks |
2776 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2777 | || (! hilo_interlocks | |
2778 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2779 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2780 | ++nops; | |
2781 | ||
2782 | if (prev_insn_unreordered) | |
2783 | nops = 0; | |
2784 | } | |
2785 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2786 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2787 | && (! cop_interlocks |
2788 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2789 | || (! hilo_interlocks | |
2790 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2791 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2792 | { | |
beae10d5 | 2793 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2794 | if (! prev_prev_insn_unreordered) |
2795 | ++nops; | |
2796 | } | |
2797 | ||
2798 | if (nops > 0) | |
2799 | { | |
2800 | struct insn_label_list *l; | |
2801 | ||
2802 | if (insns) | |
2803 | { | |
2804 | /* Record the frag which holds the nop instructions, so | |
2805 | that we can remove them if we don't need them. */ | |
2806 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2807 | prev_nop_frag = frag_now; | |
2808 | prev_nop_frag_holds = nops; | |
2809 | prev_nop_frag_required = 0; | |
2810 | prev_nop_frag_since = 0; | |
2811 | } | |
2812 | ||
2813 | for (; nops > 0; --nops) | |
2814 | emit_nop (); | |
2815 | ||
2816 | if (insns) | |
2817 | { | |
2818 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2819 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2820 | frag_wane (frag_now); |
2821 | frag_new (0); | |
2822 | } | |
2823 | ||
2824 | for (l = insn_labels; l != NULL; l = l->next) | |
2825 | { | |
98aa84af AM |
2826 | valueT val; |
2827 | ||
252b5132 | 2828 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2829 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2830 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2831 | /* mips16 text labels are stored as odd. */ |
2832 | if (mips_opts.mips16) | |
f9419b05 | 2833 | ++val; |
98aa84af | 2834 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2835 | } |
2836 | } | |
2837 | } | |
2838 | ||
2839 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2840 | if (insns) |
252b5132 RH |
2841 | mips16_mark_labels (); |
2842 | ||
2843 | mips_no_prev_insn (insns); | |
2844 | } | |
2845 | ||
2846 | /* Build an instruction created by a macro expansion. This is passed | |
2847 | a pointer to the count of instructions created so far, an | |
2848 | expression, the name of the instruction to build, an operand format | |
2849 | string, and corresponding arguments. */ | |
2850 | ||
2851 | #ifdef USE_STDARG | |
2852 | static void | |
2853 | macro_build (char *place, | |
2854 | int *counter, | |
2855 | expressionS * ep, | |
2856 | const char *name, | |
2857 | const char *fmt, | |
2858 | ...) | |
2859 | #else | |
2860 | static void | |
2861 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2862 | char *place; | |
2863 | int *counter; | |
2864 | expressionS *ep; | |
2865 | const char *name; | |
2866 | const char *fmt; | |
2867 | va_dcl | |
2868 | #endif | |
2869 | { | |
2870 | struct mips_cl_insn insn; | |
f6688943 | 2871 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2872 | va_list args; |
252b5132 RH |
2873 | |
2874 | #ifdef USE_STDARG | |
2875 | va_start (args, fmt); | |
2876 | #else | |
2877 | va_start (args); | |
2878 | #endif | |
2879 | ||
2880 | /* | |
2881 | * If the macro is about to expand into a second instruction, | |
2882 | * print a warning if needed. We need to pass ip as a parameter | |
2883 | * to generate a better warning message here... | |
2884 | */ | |
2885 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2886 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2887 | ||
80cc45a5 EC |
2888 | /* |
2889 | * If the macro is about to expand into a second instruction, | |
2890 | * and it is in a delay slot, print a warning. | |
2891 | */ | |
2892 | if (place == NULL | |
2893 | && *counter == 1 | |
2894 | && mips_opts.noreorder | |
2895 | && (prev_prev_insn.insn_mo->pinfo | |
2896 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2897 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2898 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2899 | ||
252b5132 | 2900 | if (place == NULL) |
f9419b05 | 2901 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2902 | |
2903 | if (mips_opts.mips16) | |
2904 | { | |
2905 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2906 | va_end (args); | |
2907 | return; | |
2908 | } | |
2909 | ||
f6688943 TS |
2910 | r[0] = BFD_RELOC_UNUSED; |
2911 | r[1] = BFD_RELOC_UNUSED; | |
2912 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2913 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2914 | assert (insn.insn_mo); | |
2915 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2916 | ||
2917 | /* Search until we get a match for NAME. */ | |
2918 | while (1) | |
2919 | { | |
98d3f06f | 2920 | /* It is assumed here that macros will never generate |
af55c2e6 | 2921 | MIPS-3D instructions. */ |
252b5132 RH |
2922 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2923 | && insn.insn_mo->pinfo != INSN_MACRO | |
af55c2e6 | 2924 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch) |
ec68c924 | 2925 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2926 | break; |
2927 | ||
2928 | ++insn.insn_mo; | |
2929 | assert (insn.insn_mo->name); | |
2930 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2931 | } | |
2932 | ||
2933 | insn.insn_opcode = insn.insn_mo->match; | |
2934 | for (;;) | |
2935 | { | |
2936 | switch (*fmt++) | |
2937 | { | |
2938 | case '\0': | |
2939 | break; | |
2940 | ||
2941 | case ',': | |
2942 | case '(': | |
2943 | case ')': | |
2944 | continue; | |
2945 | ||
2946 | case 't': | |
2947 | case 'w': | |
2948 | case 'E': | |
38487616 | 2949 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2950 | continue; |
2951 | ||
2952 | case 'c': | |
38487616 TS |
2953 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2954 | continue; | |
2955 | ||
252b5132 RH |
2956 | case 'T': |
2957 | case 'W': | |
38487616 | 2958 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2959 | continue; |
2960 | ||
2961 | case 'd': | |
2962 | case 'G': | |
38487616 | 2963 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2964 | continue; |
2965 | ||
4372b673 NC |
2966 | case 'U': |
2967 | { | |
2968 | int tmp = va_arg (args, int); | |
2969 | ||
38487616 TS |
2970 | insn.insn_opcode |= tmp << OP_SH_RT; |
2971 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2972 | continue; |
4372b673 NC |
2973 | } |
2974 | ||
252b5132 RH |
2975 | case 'V': |
2976 | case 'S': | |
38487616 | 2977 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2978 | continue; |
2979 | ||
2980 | case 'z': | |
2981 | continue; | |
2982 | ||
2983 | case '<': | |
38487616 | 2984 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2985 | continue; |
2986 | ||
2987 | case 'D': | |
38487616 | 2988 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
2989 | continue; |
2990 | ||
2991 | case 'B': | |
38487616 | 2992 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
2993 | continue; |
2994 | ||
4372b673 | 2995 | case 'J': |
38487616 | 2996 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
2997 | continue; |
2998 | ||
252b5132 | 2999 | case 'q': |
38487616 | 3000 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3001 | continue; |
3002 | ||
3003 | case 'b': | |
3004 | case 's': | |
3005 | case 'r': | |
3006 | case 'v': | |
38487616 | 3007 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3008 | continue; |
3009 | ||
3010 | case 'i': | |
3011 | case 'j': | |
3012 | case 'o': | |
f6688943 | 3013 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3014 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3015 | || *r == BFD_RELOC_MIPS_LITERAL |
3016 | || *r == BFD_RELOC_MIPS_HIGHER | |
3017 | || *r == BFD_RELOC_HI16_S | |
3018 | || *r == BFD_RELOC_LO16 | |
3019 | || *r == BFD_RELOC_MIPS_GOT16 | |
3020 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3021 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3022 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3023 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
3024 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3025 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 3026 | || (ep->X_op == O_subtract |
f6688943 | 3027 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
3028 | continue; |
3029 | ||
3030 | case 'u': | |
f6688943 | 3031 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3032 | assert (ep != NULL |
3033 | && (ep->X_op == O_constant | |
3034 | || (ep->X_op == O_symbol | |
f6688943 TS |
3035 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3036 | || *r == BFD_RELOC_HI16_S | |
3037 | || *r == BFD_RELOC_HI16 | |
3038 | || *r == BFD_RELOC_GPREL16 | |
3039 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3040 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 3041 | || (ep->X_op == O_subtract |
f6688943 | 3042 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
3043 | continue; |
3044 | ||
3045 | case 'p': | |
3046 | assert (ep != NULL); | |
3047 | /* | |
3048 | * This allows macro() to pass an immediate expression for | |
3049 | * creating short branches without creating a symbol. | |
3050 | * Note that the expression still might come from the assembly | |
3051 | * input, in which case the value is not checked for range nor | |
3052 | * is a relocation entry generated (yuck). | |
3053 | */ | |
3054 | if (ep->X_op == O_constant) | |
3055 | { | |
3056 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3057 | ep = NULL; | |
3058 | } | |
3059 | else | |
cb56d3d3 | 3060 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 3061 | *r = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 3062 | else |
f6688943 | 3063 | *r = BFD_RELOC_16_PCREL; |
252b5132 RH |
3064 | continue; |
3065 | ||
3066 | case 'a': | |
3067 | assert (ep != NULL); | |
f6688943 | 3068 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3069 | continue; |
3070 | ||
3071 | case 'C': | |
3072 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3073 | continue; | |
3074 | ||
3075 | default: | |
3076 | internalError (); | |
3077 | } | |
3078 | break; | |
3079 | } | |
3080 | va_end (args); | |
f6688943 | 3081 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
3082 | |
3083 | append_insn (place, &insn, ep, r, false); | |
3084 | } | |
3085 | ||
3086 | static void | |
3087 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
3088 | char *place; | |
43841e91 | 3089 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
3090 | expressionS *ep; |
3091 | const char *name; | |
3092 | const char *fmt; | |
3093 | va_list args; | |
3094 | { | |
3095 | struct mips_cl_insn insn; | |
f6688943 TS |
3096 | bfd_reloc_code_real_type r[3] |
3097 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3098 | |
252b5132 RH |
3099 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3100 | assert (insn.insn_mo); | |
3101 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3102 | ||
3103 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3104 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3105 | { | |
3106 | ++insn.insn_mo; | |
3107 | assert (insn.insn_mo->name); | |
3108 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3109 | } | |
3110 | ||
3111 | insn.insn_opcode = insn.insn_mo->match; | |
3112 | insn.use_extend = false; | |
3113 | ||
3114 | for (;;) | |
3115 | { | |
3116 | int c; | |
3117 | ||
3118 | c = *fmt++; | |
3119 | switch (c) | |
3120 | { | |
3121 | case '\0': | |
3122 | break; | |
3123 | ||
3124 | case ',': | |
3125 | case '(': | |
3126 | case ')': | |
3127 | continue; | |
3128 | ||
3129 | case 'y': | |
3130 | case 'w': | |
3131 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3132 | continue; | |
3133 | ||
3134 | case 'x': | |
3135 | case 'v': | |
3136 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3137 | continue; | |
3138 | ||
3139 | case 'z': | |
3140 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3141 | continue; | |
3142 | ||
3143 | case 'Z': | |
3144 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3145 | continue; | |
3146 | ||
3147 | case '0': | |
3148 | case 'S': | |
3149 | case 'P': | |
3150 | case 'R': | |
3151 | continue; | |
3152 | ||
3153 | case 'X': | |
3154 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3155 | continue; | |
3156 | ||
3157 | case 'Y': | |
3158 | { | |
3159 | int regno; | |
3160 | ||
3161 | regno = va_arg (args, int); | |
3162 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3163 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3164 | } | |
3165 | continue; | |
3166 | ||
3167 | case '<': | |
3168 | case '>': | |
3169 | case '4': | |
3170 | case '5': | |
3171 | case 'H': | |
3172 | case 'W': | |
3173 | case 'D': | |
3174 | case 'j': | |
3175 | case '8': | |
3176 | case 'V': | |
3177 | case 'C': | |
3178 | case 'U': | |
3179 | case 'k': | |
3180 | case 'K': | |
3181 | case 'p': | |
3182 | case 'q': | |
3183 | { | |
3184 | assert (ep != NULL); | |
3185 | ||
3186 | if (ep->X_op != O_constant) | |
874e8986 | 3187 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3188 | else |
3189 | { | |
c4e7957c TS |
3190 | mips16_immed (NULL, 0, c, ep->X_add_number, false, false, |
3191 | false, &insn.insn_opcode, &insn.use_extend, | |
3192 | &insn.extend); | |
252b5132 | 3193 | ep = NULL; |
f6688943 | 3194 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3195 | } |
3196 | } | |
3197 | continue; | |
3198 | ||
3199 | case '6': | |
3200 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3201 | continue; | |
3202 | } | |
3203 | ||
3204 | break; | |
3205 | } | |
3206 | ||
f6688943 | 3207 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
3208 | |
3209 | append_insn (place, &insn, ep, r, false); | |
3210 | } | |
3211 | ||
438c16b8 TS |
3212 | /* |
3213 | * Generate a "jalr" instruction with a relocation hint to the called | |
3214 | * function. This occurs in NewABI PIC code. | |
3215 | */ | |
3216 | static void | |
3217 | macro_build_jalr (icnt, ep) | |
3218 | int icnt; | |
3219 | expressionS *ep; | |
3220 | { | |
3221 | if (HAVE_NEWABI) | |
3222 | frag_more (0); | |
3223 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s", | |
3224 | RA, PIC_CALL_REG); | |
3225 | if (HAVE_NEWABI) | |
3226 | fix_new_exp (frag_now, 0, 0, ep, false, BFD_RELOC_MIPS_JALR); | |
3227 | } | |
3228 | ||
252b5132 RH |
3229 | /* |
3230 | * Generate a "lui" instruction. | |
3231 | */ | |
3232 | static void | |
3233 | macro_build_lui (place, counter, ep, regnum) | |
3234 | char *place; | |
3235 | int *counter; | |
3236 | expressionS *ep; | |
3237 | int regnum; | |
3238 | { | |
3239 | expressionS high_expr; | |
3240 | struct mips_cl_insn insn; | |
f6688943 TS |
3241 | bfd_reloc_code_real_type r[3] |
3242 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
3243 | CONST char *name = "lui"; |
3244 | CONST char *fmt = "t,u"; | |
3245 | ||
3246 | assert (! mips_opts.mips16); | |
3247 | ||
3248 | if (place == NULL) | |
3249 | high_expr = *ep; | |
3250 | else | |
3251 | { | |
3252 | high_expr.X_op = O_constant; | |
3253 | high_expr.X_add_number = ep->X_add_number; | |
3254 | } | |
3255 | ||
3256 | if (high_expr.X_op == O_constant) | |
3257 | { | |
3258 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3259 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3260 | >> 16) & 0xffff; | |
f6688943 | 3261 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3262 | } |
f6688943 | 3263 | else if (! HAVE_NEWABI) |
252b5132 RH |
3264 | { |
3265 | assert (ep->X_op == O_symbol); | |
3266 | /* _gp_disp is a special case, used from s_cpload. */ | |
3267 | assert (mips_pic == NO_PIC | |
3268 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
f6688943 | 3269 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3270 | } |
3271 | ||
3272 | /* | |
3273 | * If the macro is about to expand into a second instruction, | |
3274 | * print a warning if needed. We need to pass ip as a parameter | |
3275 | * to generate a better warning message here... | |
3276 | */ | |
3277 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3278 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3279 | ||
3280 | if (place == NULL) | |
f9419b05 | 3281 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3282 | |
3283 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3284 | assert (insn.insn_mo); | |
3285 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3286 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3287 | ||
3288 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3289 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3290 | { |
3291 | insn.insn_opcode |= high_expr.X_add_number; | |
3292 | append_insn (place, &insn, NULL, r, false); | |
3293 | } | |
3294 | else | |
3295 | append_insn (place, &insn, &high_expr, r, false); | |
3296 | } | |
3297 | ||
3298 | /* set_at() | |
3299 | * Generates code to set the $at register to true (one) | |
3300 | * if reg is less than the immediate expression. | |
3301 | */ | |
3302 | static void | |
3303 | set_at (counter, reg, unsignedp) | |
3304 | int *counter; | |
3305 | int reg; | |
3306 | int unsignedp; | |
3307 | { | |
3308 | if (imm_expr.X_op == O_constant | |
3309 | && imm_expr.X_add_number >= -0x8000 | |
3310 | && imm_expr.X_add_number < 0x8000) | |
3311 | macro_build ((char *) NULL, counter, &imm_expr, | |
3312 | unsignedp ? "sltiu" : "slti", | |
3313 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3314 | else | |
3315 | { | |
4d34fb5f | 3316 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 | 3317 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 RH |
3318 | unsignedp ? "sltu" : "slt", |
3319 | "d,v,t", AT, reg, AT); | |
3320 | } | |
3321 | } | |
3322 | ||
3323 | /* Warn if an expression is not a constant. */ | |
3324 | ||
3325 | static void | |
3326 | check_absolute_expr (ip, ex) | |
3327 | struct mips_cl_insn *ip; | |
3328 | expressionS *ex; | |
3329 | { | |
3330 | if (ex->X_op == O_big) | |
3331 | as_bad (_("unsupported large constant")); | |
3332 | else if (ex->X_op != O_constant) | |
3333 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3334 | } | |
3335 | ||
3336 | /* Count the leading zeroes by performing a binary chop. This is a | |
3337 | bulky bit of source, but performance is a LOT better for the | |
3338 | majority of values than a simple loop to count the bits: | |
3339 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3340 | if ((v) & (1 << (31 - lcnt))) | |
3341 | break; | |
3342 | However it is not code size friendly, and the gain will drop a bit | |
3343 | on certain cached systems. | |
3344 | */ | |
3345 | #define COUNT_TOP_ZEROES(v) \ | |
3346 | (((v) & ~0xffff) == 0 \ | |
3347 | ? ((v) & ~0xff) == 0 \ | |
3348 | ? ((v) & ~0xf) == 0 \ | |
3349 | ? ((v) & ~0x3) == 0 \ | |
3350 | ? ((v) & ~0x1) == 0 \ | |
3351 | ? !(v) \ | |
3352 | ? 32 \ | |
3353 | : 31 \ | |
3354 | : 30 \ | |
3355 | : ((v) & ~0x7) == 0 \ | |
3356 | ? 29 \ | |
3357 | : 28 \ | |
3358 | : ((v) & ~0x3f) == 0 \ | |
3359 | ? ((v) & ~0x1f) == 0 \ | |
3360 | ? 27 \ | |
3361 | : 26 \ | |
3362 | : ((v) & ~0x7f) == 0 \ | |
3363 | ? 25 \ | |
3364 | : 24 \ | |
3365 | : ((v) & ~0xfff) == 0 \ | |
3366 | ? ((v) & ~0x3ff) == 0 \ | |
3367 | ? ((v) & ~0x1ff) == 0 \ | |
3368 | ? 23 \ | |
3369 | : 22 \ | |
3370 | : ((v) & ~0x7ff) == 0 \ | |
3371 | ? 21 \ | |
3372 | : 20 \ | |
3373 | : ((v) & ~0x3fff) == 0 \ | |
3374 | ? ((v) & ~0x1fff) == 0 \ | |
3375 | ? 19 \ | |
3376 | : 18 \ | |
3377 | : ((v) & ~0x7fff) == 0 \ | |
3378 | ? 17 \ | |
3379 | : 16 \ | |
3380 | : ((v) & ~0xffffff) == 0 \ | |
3381 | ? ((v) & ~0xfffff) == 0 \ | |
3382 | ? ((v) & ~0x3ffff) == 0 \ | |
3383 | ? ((v) & ~0x1ffff) == 0 \ | |
3384 | ? 15 \ | |
3385 | : 14 \ | |
3386 | : ((v) & ~0x7ffff) == 0 \ | |
3387 | ? 13 \ | |
3388 | : 12 \ | |
3389 | : ((v) & ~0x3fffff) == 0 \ | |
3390 | ? ((v) & ~0x1fffff) == 0 \ | |
3391 | ? 11 \ | |
3392 | : 10 \ | |
3393 | : ((v) & ~0x7fffff) == 0 \ | |
3394 | ? 9 \ | |
3395 | : 8 \ | |
3396 | : ((v) & ~0xfffffff) == 0 \ | |
3397 | ? ((v) & ~0x3ffffff) == 0 \ | |
3398 | ? ((v) & ~0x1ffffff) == 0 \ | |
3399 | ? 7 \ | |
3400 | : 6 \ | |
3401 | : ((v) & ~0x7ffffff) == 0 \ | |
3402 | ? 5 \ | |
3403 | : 4 \ | |
3404 | : ((v) & ~0x3fffffff) == 0 \ | |
3405 | ? ((v) & ~0x1fffffff) == 0 \ | |
3406 | ? 3 \ | |
3407 | : 2 \ | |
3408 | : ((v) & ~0x7fffffff) == 0 \ | |
3409 | ? 1 \ | |
3410 | : 0) | |
3411 | ||
6373ee54 CD |
3412 | /* Is the given value a sign-extended 32-bit value? */ |
3413 | #define IS_SEXT_32BIT_NUM(x) \ | |
3414 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
3415 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
3416 | ||
252b5132 RH |
3417 | /* load_register() |
3418 | * This routine generates the least number of instructions neccessary to load | |
3419 | * an absolute expression value into a register. | |
3420 | */ | |
3421 | static void | |
3422 | load_register (counter, reg, ep, dbl) | |
3423 | int *counter; | |
3424 | int reg; | |
3425 | expressionS *ep; | |
3426 | int dbl; | |
3427 | { | |
3428 | int freg; | |
3429 | expressionS hi32, lo32; | |
3430 | ||
3431 | if (ep->X_op != O_big) | |
3432 | { | |
3433 | assert (ep->X_op == O_constant); | |
3434 | if (ep->X_add_number < 0x8000 | |
3435 | && (ep->X_add_number >= 0 | |
3436 | || (ep->X_add_number >= -0x8000 | |
3437 | && (! dbl | |
3438 | || ! ep->X_unsigned | |
3439 | || sizeof (ep->X_add_number) > 4)))) | |
3440 | { | |
3441 | /* We can handle 16 bit signed values with an addiu to | |
3442 | $zero. No need to ever use daddiu here, since $zero and | |
3443 | the result are always correct in 32 bit mode. */ | |
3444 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3445 | (int) BFD_RELOC_LO16); | |
3446 | return; | |
3447 | } | |
3448 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3449 | { | |
3450 | /* We can handle 16 bit unsigned values with an ori to | |
3451 | $zero. */ | |
3452 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3453 | (int) BFD_RELOC_LO16); | |
3454 | return; | |
3455 | } | |
6373ee54 | 3456 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
252b5132 RH |
3457 | && (! dbl |
3458 | || ! ep->X_unsigned | |
3459 | || sizeof (ep->X_add_number) > 4 | |
3460 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3461 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3462 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3463 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3464 | && ! dbl |
3465 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3466 | == ~ (offsetT) 0xffffffff))) | |
3467 | { | |
3468 | /* 32 bit values require an lui. */ | |
3469 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3470 | (int) BFD_RELOC_HI16); | |
3471 | if ((ep->X_add_number & 0xffff) != 0) | |
3472 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3473 | (int) BFD_RELOC_LO16); | |
3474 | return; | |
3475 | } | |
3476 | } | |
3477 | ||
3478 | /* The value is larger than 32 bits. */ | |
3479 | ||
ca4e0257 | 3480 | if (HAVE_32BIT_GPRS) |
252b5132 | 3481 | { |
956cd1d6 TS |
3482 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3483 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3484 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3485 | (int) BFD_RELOC_LO16); | |
3486 | return; | |
3487 | } | |
3488 | ||
3489 | if (ep->X_op != O_big) | |
3490 | { | |
3491 | hi32 = *ep; | |
3492 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3493 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3494 | hi32.X_add_number &= 0xffffffff; | |
3495 | lo32 = *ep; | |
3496 | lo32.X_add_number &= 0xffffffff; | |
3497 | } | |
3498 | else | |
3499 | { | |
3500 | assert (ep->X_add_number > 2); | |
3501 | if (ep->X_add_number == 3) | |
3502 | generic_bignum[3] = 0; | |
3503 | else if (ep->X_add_number > 4) | |
3504 | as_bad (_("Number larger than 64 bits")); | |
3505 | lo32.X_op = O_constant; | |
3506 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3507 | hi32.X_op = O_constant; | |
3508 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3509 | } | |
3510 | ||
3511 | if (hi32.X_add_number == 0) | |
3512 | freg = 0; | |
3513 | else | |
3514 | { | |
3515 | int shift, bit; | |
3516 | unsigned long hi, lo; | |
3517 | ||
956cd1d6 | 3518 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3519 | { |
3520 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3521 | { | |
3522 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3523 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3524 | return; |
3525 | } | |
3526 | if (lo32.X_add_number & 0x80000000) | |
3527 | { | |
3528 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3529 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3530 | if (lo32.X_add_number & 0xffff) |
3531 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3532 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3533 | return; |
3534 | } | |
3535 | } | |
252b5132 RH |
3536 | |
3537 | /* Check for 16bit shifted constant. We know that hi32 is | |
3538 | non-zero, so start the mask on the first bit of the hi32 | |
3539 | value. */ | |
3540 | shift = 17; | |
3541 | do | |
beae10d5 KH |
3542 | { |
3543 | unsigned long himask, lomask; | |
3544 | ||
3545 | if (shift < 32) | |
3546 | { | |
3547 | himask = 0xffff >> (32 - shift); | |
3548 | lomask = (0xffff << shift) & 0xffffffff; | |
3549 | } | |
3550 | else | |
3551 | { | |
3552 | himask = 0xffff << (shift - 32); | |
3553 | lomask = 0; | |
3554 | } | |
3555 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3556 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3557 | { | |
3558 | expressionS tmp; | |
3559 | ||
3560 | tmp.X_op = O_constant; | |
3561 | if (shift < 32) | |
3562 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3563 | | (lo32.X_add_number >> shift)); | |
3564 | else | |
3565 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3566 | macro_build ((char *) NULL, counter, &tmp, | |
3567 | "ori", "t,r,i", reg, 0, | |
3568 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 3569 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3570 | (shift >= 32) ? "dsll32" : "dsll", |
3571 | "d,w,<", reg, reg, | |
3572 | (shift >= 32) ? shift - 32 : shift); | |
3573 | return; | |
3574 | } | |
f9419b05 | 3575 | ++shift; |
beae10d5 KH |
3576 | } |
3577 | while (shift <= (64 - 16)); | |
252b5132 RH |
3578 | |
3579 | /* Find the bit number of the lowest one bit, and store the | |
3580 | shifted value in hi/lo. */ | |
3581 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3582 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3583 | if (lo != 0) | |
3584 | { | |
3585 | bit = 0; | |
3586 | while ((lo & 1) == 0) | |
3587 | { | |
3588 | lo >>= 1; | |
3589 | ++bit; | |
3590 | } | |
3591 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3592 | hi >>= bit; | |
3593 | } | |
3594 | else | |
3595 | { | |
3596 | bit = 32; | |
3597 | while ((hi & 1) == 0) | |
3598 | { | |
3599 | hi >>= 1; | |
3600 | ++bit; | |
3601 | } | |
3602 | lo = hi; | |
3603 | hi = 0; | |
3604 | } | |
3605 | ||
3606 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3607 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3608 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3609 | { |
3610 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3611 | if (shift != 0) |
beae10d5 | 3612 | { |
252b5132 RH |
3613 | expressionS tmp; |
3614 | ||
3615 | /* This instruction will set the register to be all | |
3616 | ones. */ | |
beae10d5 KH |
3617 | tmp.X_op = O_constant; |
3618 | tmp.X_add_number = (offsetT) -1; | |
3619 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3620 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3621 | if (bit != 0) |
3622 | { | |
3623 | bit += shift; | |
2396cfb9 | 3624 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3625 | (bit >= 32) ? "dsll32" : "dsll", |
3626 | "d,w,<", reg, reg, | |
3627 | (bit >= 32) ? bit - 32 : bit); | |
3628 | } | |
2396cfb9 | 3629 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 | 3630 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3631 | "d,w,<", reg, reg, |
252b5132 | 3632 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3633 | return; |
3634 | } | |
3635 | } | |
252b5132 RH |
3636 | |
3637 | /* Sign extend hi32 before calling load_register, because we can | |
3638 | generally get better code when we load a sign extended value. */ | |
3639 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3640 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3641 | load_register (counter, reg, &hi32, 0); |
3642 | freg = reg; | |
3643 | } | |
3644 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3645 | { | |
3646 | if (freg != 0) | |
3647 | { | |
2396cfb9 TS |
3648 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3649 | "dsll32", "d,w,<", reg, freg, 0); | |
252b5132 RH |
3650 | freg = reg; |
3651 | } | |
3652 | } | |
3653 | else | |
3654 | { | |
3655 | expressionS mid16; | |
3656 | ||
956cd1d6 | 3657 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3658 | { |
252b5132 RH |
3659 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3660 | (int) BFD_RELOC_HI16); | |
956cd1d6 TS |
3661 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3662 | "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3663 | return; |
3664 | } | |
252b5132 RH |
3665 | |
3666 | if (freg != 0) | |
3667 | { | |
956cd1d6 TS |
3668 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3669 | "d,w,<", reg, freg, 16); | |
252b5132 RH |
3670 | freg = reg; |
3671 | } | |
3672 | mid16 = lo32; | |
3673 | mid16.X_add_number >>= 16; | |
3674 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3675 | freg, (int) BFD_RELOC_LO16); | |
956cd1d6 TS |
3676 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3677 | "d,w,<", reg, reg, 16); | |
252b5132 RH |
3678 | freg = reg; |
3679 | } | |
3680 | if ((lo32.X_add_number & 0xffff) != 0) | |
3681 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3682 | (int) BFD_RELOC_LO16); | |
3683 | } | |
3684 | ||
3685 | /* Load an address into a register. */ | |
3686 | ||
3687 | static void | |
c9914766 | 3688 | load_address (counter, reg, ep, used_at) |
252b5132 RH |
3689 | int *counter; |
3690 | int reg; | |
3691 | expressionS *ep; | |
d6bc6245 | 3692 | int *used_at; |
252b5132 | 3693 | { |
f9419b05 | 3694 | char *p = NULL; |
252b5132 RH |
3695 | |
3696 | if (ep->X_op != O_constant | |
3697 | && ep->X_op != O_symbol) | |
3698 | { | |
3699 | as_bad (_("expression too complex")); | |
3700 | ep->X_op = O_constant; | |
3701 | } | |
3702 | ||
3703 | if (ep->X_op == O_constant) | |
3704 | { | |
c9914766 | 3705 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3706 | return; |
3707 | } | |
3708 | ||
3709 | if (mips_pic == NO_PIC) | |
3710 | { | |
3711 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3712 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3713 | Otherwise we want |
3714 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3715 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3716 | If we have an addend, we always use the latter form. |
76b3015f | 3717 | |
d6bc6245 TS |
3718 | With 64bit address space and a usable $at we want |
3719 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3720 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3721 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3722 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3723 | dsll32 $reg,0 | |
3724 | dadd $reg,$reg,$at | |
76b3015f | 3725 | |
d6bc6245 TS |
3726 | If $at is already in use, we use an path which is suboptimal |
3727 | on superscalar processors. | |
3728 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3729 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3730 | dsll $reg,16 | |
3731 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3732 | dsll $reg,16 | |
3733 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3734 | */ | |
c9914766 | 3735 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3736 | { |
d6bc6245 TS |
3737 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3738 | hold the data for such large chunks. */ | |
3739 | ||
3740 | if (*used_at == 0) | |
3741 | { | |
3742 | macro_build (p, counter, ep, "lui", "t,u", | |
3743 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3744 | macro_build (p, counter, ep, "lui", "t,u", | |
3745 | AT, (int) BFD_RELOC_HI16_S); | |
3746 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3747 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3748 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3749 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3750 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
3751 | "d,w,<", reg, reg, 0); | |
3752 | macro_build (p, counter, (expressionS *) NULL, "dadd", | |
3753 | "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3754 | *used_at = 1; |
3755 | } | |
3756 | else | |
3757 | { | |
3758 | macro_build (p, counter, ep, "lui", "t,u", | |
3759 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3760 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3761 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
3762 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3763 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3764 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3765 | reg, reg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
3766 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3767 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3768 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3769 | reg, reg, (int) BFD_RELOC_LO16); | |
3770 | } | |
3771 | } | |
252b5132 RH |
3772 | else |
3773 | { | |
d6bc6245 TS |
3774 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3775 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3776 | { | |
3777 | frag_grow (20); | |
3778 | macro_build ((char *) NULL, counter, ep, | |
c9914766 TS |
3779 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
3780 | reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3781 | p = frag_var (rs_machine_dependent, 8, 0, |
3782 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3783 | mips_opts.warn_about_macros), | |
956cd1d6 | 3784 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3785 | } |
3786 | macro_build_lui (p, counter, ep, reg); | |
3787 | if (p != NULL) | |
3788 | p += 4; | |
c9914766 TS |
3789 | macro_build (p, counter, ep, |
3790 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
d6bc6245 TS |
3791 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3792 | } | |
252b5132 RH |
3793 | } |
3794 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3795 | { | |
3796 | expressionS ex; | |
3797 | ||
3798 | /* If this is a reference to an external symbol, we want | |
3799 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3800 | Otherwise we want | |
3801 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3802 | nop | |
3803 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3804 | If there is a constant, it must be added in after. */ | |
3805 | ex.X_add_number = ep->X_add_number; | |
3806 | ep->X_add_number = 0; | |
3807 | frag_grow (20); | |
3808 | macro_build ((char *) NULL, counter, ep, | |
c9914766 TS |
3809 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", |
3810 | reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
3811 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); |
3812 | p = frag_var (rs_machine_dependent, 4, 0, | |
3813 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3814 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3815 | macro_build (p, counter, ep, | |
ca4e0257 | 3816 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3817 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3818 | if (ex.X_add_number != 0) | |
3819 | { | |
3820 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3821 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3822 | ex.X_op = O_constant; | |
3823 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3824 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3825 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3826 | } | |
3827 | } | |
3828 | else if (mips_pic == SVR4_PIC) | |
3829 | { | |
3830 | expressionS ex; | |
3831 | int off; | |
3832 | ||
3833 | /* This is the large GOT case. If this is a reference to an | |
3834 | external symbol, we want | |
3835 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3836 | addu $reg,$reg,$gp | |
3837 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3838 | Otherwise, for a reference to a local symbol, we want | |
3839 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3840 | nop | |
3841 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
438c16b8 TS |
3842 | If we have NewABI, we want |
3843 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
3844 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
252b5132 RH |
3845 | If there is a constant, it must be added in after. */ |
3846 | ex.X_add_number = ep->X_add_number; | |
3847 | ep->X_add_number = 0; | |
438c16b8 TS |
3848 | if (HAVE_NEWABI) |
3849 | { | |
3850 | macro_build ((char *) NULL, counter, ep, | |
3851 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3852 | (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
3853 | macro_build (p, counter, ep, | |
3854 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", | |
3855 | reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST); | |
3856 | } | |
252b5132 | 3857 | else |
438c16b8 TS |
3858 | { |
3859 | if (reg_needs_delay (mips_gp_register)) | |
3860 | off = 4; | |
3861 | else | |
3862 | off = 0; | |
3863 | frag_grow (32); | |
3864 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3865 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3866 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3867 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg, | |
3868 | reg, mips_gp_register); | |
3869 | macro_build ((char *) NULL, counter, ep, | |
3870 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
3871 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3872 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3873 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3874 | mips_opts.warn_about_macros), | |
3875 | ep->X_add_symbol, 0, NULL); | |
3876 | if (off > 0) | |
3877 | { | |
3878 | /* We need a nop before loading from $gp. This special | |
3879 | check is required because the lui which starts the main | |
3880 | instruction stream does not refer to $gp, and so will not | |
3881 | insert the nop which may be required. */ | |
3882 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3883 | p += 4; | |
3884 | } | |
3885 | macro_build (p, counter, ep, | |
3886 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3887 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
3888 | p += 4; | |
252b5132 RH |
3889 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
3890 | p += 4; | |
438c16b8 TS |
3891 | macro_build (p, counter, ep, |
3892 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3893 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
252b5132 | 3894 | } |
438c16b8 | 3895 | |
252b5132 RH |
3896 | if (ex.X_add_number != 0) |
3897 | { | |
3898 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3899 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3900 | ex.X_op = O_constant; | |
f7ea7ef2 TS |
3901 | macro_build ((char *) NULL, counter, &ex, |
3902 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
252b5132 RH |
3903 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3904 | } | |
3905 | } | |
3906 | else if (mips_pic == EMBEDDED_PIC) | |
3907 | { | |
3908 | /* We always do | |
cdf6fd85 | 3909 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 TS |
3910 | */ |
3911 | macro_build ((char *) NULL, counter, ep, | |
3912 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3913 | "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
3914 | } |
3915 | else | |
3916 | abort (); | |
3917 | } | |
3918 | ||
ea1fb5dc RS |
3919 | /* Move the contents of register SOURCE into register DEST. */ |
3920 | ||
3921 | static void | |
3922 | move_register (counter, dest, source) | |
3923 | int *counter; | |
3924 | int dest; | |
3925 | int source; | |
3926 | { | |
3927 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3928 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
3929 | "d,v,t", dest, source, 0); | |
3930 | } | |
3931 | ||
252b5132 RH |
3932 | /* |
3933 | * Build macros | |
3934 | * This routine implements the seemingly endless macro or synthesized | |
3935 | * instructions and addressing modes in the mips assembly language. Many | |
3936 | * of these macros are simple and are similar to each other. These could | |
3937 | * probably be handled by some kind of table or grammer aproach instead of | |
3938 | * this verbose method. Others are not simple macros but are more like | |
3939 | * optimizing code generation. | |
3940 | * One interesting optimization is when several store macros appear | |
3941 | * consecutivly that would load AT with the upper half of the same address. | |
3942 | * The ensuing load upper instructions are ommited. This implies some kind | |
3943 | * of global optimization. We currently only optimize within a single macro. | |
3944 | * For many of the load and store macros if the address is specified as a | |
3945 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3946 | * first load register 'at' with zero and use it as the base register. The | |
3947 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3948 | * we're missing. | |
3949 | */ | |
3950 | static void | |
3951 | macro (ip) | |
3952 | struct mips_cl_insn *ip; | |
3953 | { | |
3954 | register int treg, sreg, dreg, breg; | |
3955 | int tempreg; | |
3956 | int mask; | |
3957 | int icnt = 0; | |
43841e91 | 3958 | int used_at = 0; |
252b5132 RH |
3959 | expressionS expr1; |
3960 | const char *s; | |
3961 | const char *s2; | |
3962 | const char *fmt; | |
3963 | int likely = 0; | |
3964 | int dbl = 0; | |
3965 | int coproc = 0; | |
3966 | int lr = 0; | |
3967 | int imm = 0; | |
3968 | offsetT maxnum; | |
3969 | int off; | |
3970 | bfd_reloc_code_real_type r; | |
252b5132 RH |
3971 | int hold_mips_optimize; |
3972 | ||
3973 | assert (! mips_opts.mips16); | |
3974 | ||
3975 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3976 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3977 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3978 | mask = ip->insn_mo->mask; | |
3979 | ||
3980 | expr1.X_op = O_constant; | |
3981 | expr1.X_op_symbol = NULL; | |
3982 | expr1.X_add_symbol = NULL; | |
3983 | expr1.X_add_number = 1; | |
3984 | ||
3985 | switch (mask) | |
3986 | { | |
3987 | case M_DABS: | |
3988 | dbl = 1; | |
3989 | case M_ABS: | |
3990 | /* bgez $a0,.+12 | |
3991 | move v0,$a0 | |
3992 | sub v0,$zero,$a0 | |
3993 | */ | |
3994 | ||
3995 | mips_emit_delays (true); | |
3996 | ++mips_opts.noreorder; | |
3997 | mips_any_noreorder = 1; | |
3998 | ||
3999 | expr1.X_add_number = 8; | |
4000 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
4001 | if (dreg == sreg) | |
2396cfb9 TS |
4002 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4003 | 0); | |
252b5132 | 4004 | else |
ea1fb5dc | 4005 | move_register (&icnt, dreg, sreg); |
2396cfb9 | 4006 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4007 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
4008 | |
4009 | --mips_opts.noreorder; | |
4010 | return; | |
4011 | ||
4012 | case M_ADD_I: | |
4013 | s = "addi"; | |
4014 | s2 = "add"; | |
4015 | goto do_addi; | |
4016 | case M_ADDU_I: | |
4017 | s = "addiu"; | |
4018 | s2 = "addu"; | |
4019 | goto do_addi; | |
4020 | case M_DADD_I: | |
4021 | dbl = 1; | |
4022 | s = "daddi"; | |
4023 | s2 = "dadd"; | |
4024 | goto do_addi; | |
4025 | case M_DADDU_I: | |
4026 | dbl = 1; | |
4027 | s = "daddiu"; | |
4028 | s2 = "daddu"; | |
4029 | do_addi: | |
4030 | if (imm_expr.X_op == O_constant | |
4031 | && imm_expr.X_add_number >= -0x8000 | |
4032 | && imm_expr.X_add_number < 0x8000) | |
4033 | { | |
4034 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
4035 | (int) BFD_RELOC_LO16); | |
4036 | return; | |
4037 | } | |
4038 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4039 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4040 | treg, sreg, AT); | |
252b5132 RH |
4041 | break; |
4042 | ||
4043 | case M_AND_I: | |
4044 | s = "andi"; | |
4045 | s2 = "and"; | |
4046 | goto do_bit; | |
4047 | case M_OR_I: | |
4048 | s = "ori"; | |
4049 | s2 = "or"; | |
4050 | goto do_bit; | |
4051 | case M_NOR_I: | |
4052 | s = ""; | |
4053 | s2 = "nor"; | |
4054 | goto do_bit; | |
4055 | case M_XOR_I: | |
4056 | s = "xori"; | |
4057 | s2 = "xor"; | |
4058 | do_bit: | |
4059 | if (imm_expr.X_op == O_constant | |
4060 | && imm_expr.X_add_number >= 0 | |
4061 | && imm_expr.X_add_number < 0x10000) | |
4062 | { | |
4063 | if (mask != M_NOR_I) | |
4064 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
4065 | sreg, (int) BFD_RELOC_LO16); | |
4066 | else | |
4067 | { | |
4068 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
4069 | treg, sreg, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4070 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
4071 | "d,v,t", treg, treg, 0); | |
252b5132 RH |
4072 | } |
4073 | return; | |
4074 | } | |
4075 | ||
d6bc6245 | 4076 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
4077 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
4078 | treg, sreg, AT); | |
252b5132 RH |
4079 | break; |
4080 | ||
4081 | case M_BEQ_I: | |
4082 | s = "beq"; | |
4083 | goto beq_i; | |
4084 | case M_BEQL_I: | |
4085 | s = "beql"; | |
4086 | likely = 1; | |
4087 | goto beq_i; | |
4088 | case M_BNE_I: | |
4089 | s = "bne"; | |
4090 | goto beq_i; | |
4091 | case M_BNEL_I: | |
4092 | s = "bnel"; | |
4093 | likely = 1; | |
4094 | beq_i: | |
4095 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4096 | { | |
4097 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
4098 | 0); | |
4099 | return; | |
4100 | } | |
4d34fb5f | 4101 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
252b5132 RH |
4102 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
4103 | break; | |
4104 | ||
4105 | case M_BGEL: | |
4106 | likely = 1; | |
4107 | case M_BGE: | |
4108 | if (treg == 0) | |
4109 | { | |
4110 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4111 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4112 | return; |
4113 | } | |
4114 | if (sreg == 0) | |
4115 | { | |
4116 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 4117 | likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4118 | return; |
4119 | } | |
2396cfb9 TS |
4120 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4121 | AT, sreg, treg); | |
252b5132 | 4122 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4123 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4124 | break; |
4125 | ||
4126 | case M_BGTL_I: | |
4127 | likely = 1; | |
4128 | case M_BGT_I: | |
4129 | /* check for > max integer */ | |
4130 | maxnum = 0x7fffffff; | |
ca4e0257 | 4131 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4132 | { |
4133 | maxnum <<= 16; | |
4134 | maxnum |= 0xffff; | |
4135 | maxnum <<= 16; | |
4136 | maxnum |= 0xffff; | |
4137 | } | |
4138 | if (imm_expr.X_op == O_constant | |
4139 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4140 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4141 | { |
4142 | do_false: | |
4143 | /* result is always false */ | |
4144 | if (! likely) | |
4145 | { | |
39c0a331 L |
4146 | if (warn_nops) |
4147 | as_warn (_("Branch %s is always false (nop)"), | |
4148 | ip->insn_mo->name); | |
2396cfb9 TS |
4149 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
4150 | "", 0); | |
252b5132 RH |
4151 | } |
4152 | else | |
4153 | { | |
39c0a331 L |
4154 | if (warn_nops) |
4155 | as_warn (_("Branch likely %s is always false"), | |
4156 | ip->insn_mo->name); | |
252b5132 RH |
4157 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
4158 | "s,t,p", 0, 0); | |
4159 | } | |
4160 | return; | |
4161 | } | |
4162 | if (imm_expr.X_op != O_constant) | |
4163 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4164 | ++imm_expr.X_add_number; |
252b5132 RH |
4165 | /* FALLTHROUGH */ |
4166 | case M_BGE_I: | |
4167 | case M_BGEL_I: | |
4168 | if (mask == M_BGEL_I) | |
4169 | likely = 1; | |
4170 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4171 | { | |
4172 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4173 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4174 | return; |
4175 | } | |
4176 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4177 | { | |
4178 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4179 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4180 | return; |
4181 | } | |
4182 | maxnum = 0x7fffffff; | |
ca4e0257 | 4183 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4184 | { |
4185 | maxnum <<= 16; | |
4186 | maxnum |= 0xffff; | |
4187 | maxnum <<= 16; | |
4188 | maxnum |= 0xffff; | |
4189 | } | |
4190 | maxnum = - maxnum - 1; | |
4191 | if (imm_expr.X_op == O_constant | |
4192 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4193 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4194 | { |
4195 | do_true: | |
4196 | /* result is always true */ | |
4197 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4198 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4199 | return; | |
4200 | } | |
4201 | set_at (&icnt, sreg, 0); | |
4202 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4203 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4204 | break; |
4205 | ||
4206 | case M_BGEUL: | |
4207 | likely = 1; | |
4208 | case M_BGEU: | |
4209 | if (treg == 0) | |
4210 | goto do_true; | |
4211 | if (sreg == 0) | |
4212 | { | |
4213 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4214 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4215 | return; |
4216 | } | |
2396cfb9 TS |
4217 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4218 | "d,v,t", AT, sreg, treg); | |
252b5132 | 4219 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4220 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4221 | break; |
4222 | ||
4223 | case M_BGTUL_I: | |
4224 | likely = 1; | |
4225 | case M_BGTU_I: | |
4226 | if (sreg == 0 | |
ca4e0257 | 4227 | || (HAVE_32BIT_GPRS |
252b5132 | 4228 | && imm_expr.X_op == O_constant |
956cd1d6 | 4229 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4230 | goto do_false; |
4231 | if (imm_expr.X_op != O_constant) | |
4232 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4233 | ++imm_expr.X_add_number; |
252b5132 RH |
4234 | /* FALLTHROUGH */ |
4235 | case M_BGEU_I: | |
4236 | case M_BGEUL_I: | |
4237 | if (mask == M_BGEUL_I) | |
4238 | likely = 1; | |
4239 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4240 | goto do_true; | |
4241 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4242 | { | |
4243 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4244 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4245 | return; |
4246 | } | |
4247 | set_at (&icnt, sreg, 1); | |
4248 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4249 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4250 | break; |
4251 | ||
4252 | case M_BGTL: | |
4253 | likely = 1; | |
4254 | case M_BGT: | |
4255 | if (treg == 0) | |
4256 | { | |
4257 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4258 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4259 | return; |
4260 | } | |
4261 | if (sreg == 0) | |
4262 | { | |
4263 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4264 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4265 | return; |
4266 | } | |
2396cfb9 TS |
4267 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4268 | AT, treg, sreg); | |
252b5132 | 4269 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4270 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4271 | break; |
4272 | ||
4273 | case M_BGTUL: | |
4274 | likely = 1; | |
4275 | case M_BGTU: | |
4276 | if (treg == 0) | |
4277 | { | |
4278 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4279 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4280 | return; |
4281 | } | |
4282 | if (sreg == 0) | |
4283 | goto do_false; | |
2396cfb9 TS |
4284 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4285 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4286 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4287 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4288 | break; |
4289 | ||
4290 | case M_BLEL: | |
4291 | likely = 1; | |
4292 | case M_BLE: | |
4293 | if (treg == 0) | |
4294 | { | |
4295 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4296 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4297 | return; |
4298 | } | |
4299 | if (sreg == 0) | |
4300 | { | |
4301 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4302 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4303 | return; |
4304 | } | |
2396cfb9 TS |
4305 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4306 | AT, treg, sreg); | |
252b5132 | 4307 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4308 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4309 | break; |
4310 | ||
4311 | case M_BLEL_I: | |
4312 | likely = 1; | |
4313 | case M_BLE_I: | |
4314 | maxnum = 0x7fffffff; | |
ca4e0257 | 4315 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4316 | { |
4317 | maxnum <<= 16; | |
4318 | maxnum |= 0xffff; | |
4319 | maxnum <<= 16; | |
4320 | maxnum |= 0xffff; | |
4321 | } | |
4322 | if (imm_expr.X_op == O_constant | |
4323 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4324 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4325 | goto do_true; |
4326 | if (imm_expr.X_op != O_constant) | |
4327 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4328 | ++imm_expr.X_add_number; |
252b5132 RH |
4329 | /* FALLTHROUGH */ |
4330 | case M_BLT_I: | |
4331 | case M_BLTL_I: | |
4332 | if (mask == M_BLTL_I) | |
4333 | likely = 1; | |
4334 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4335 | { | |
4336 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4337 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4338 | return; |
4339 | } | |
4340 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4341 | { | |
4342 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4343 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4344 | return; |
4345 | } | |
4346 | set_at (&icnt, sreg, 0); | |
4347 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4348 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4349 | break; |
4350 | ||
4351 | case M_BLEUL: | |
4352 | likely = 1; | |
4353 | case M_BLEU: | |
4354 | if (treg == 0) | |
4355 | { | |
4356 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4357 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4358 | return; |
4359 | } | |
4360 | if (sreg == 0) | |
4361 | goto do_true; | |
2396cfb9 TS |
4362 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4363 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4364 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4365 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4366 | break; |
4367 | ||
4368 | case M_BLEUL_I: | |
4369 | likely = 1; | |
4370 | case M_BLEU_I: | |
4371 | if (sreg == 0 | |
ca4e0257 | 4372 | || (HAVE_32BIT_GPRS |
252b5132 | 4373 | && imm_expr.X_op == O_constant |
956cd1d6 | 4374 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4375 | goto do_true; |
4376 | if (imm_expr.X_op != O_constant) | |
4377 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4378 | ++imm_expr.X_add_number; |
252b5132 RH |
4379 | /* FALLTHROUGH */ |
4380 | case M_BLTU_I: | |
4381 | case M_BLTUL_I: | |
4382 | if (mask == M_BLTUL_I) | |
4383 | likely = 1; | |
4384 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4385 | goto do_false; | |
4386 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4387 | { | |
4388 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4389 | likely ? "beql" : "beq", | |
4390 | "s,t,p", sreg, 0); | |
4391 | return; | |
4392 | } | |
4393 | set_at (&icnt, sreg, 1); | |
4394 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4395 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4396 | break; |
4397 | ||
4398 | case M_BLTL: | |
4399 | likely = 1; | |
4400 | case M_BLT: | |
4401 | if (treg == 0) | |
4402 | { | |
4403 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4404 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4405 | return; |
4406 | } | |
4407 | if (sreg == 0) | |
4408 | { | |
4409 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4410 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4411 | return; |
4412 | } | |
2396cfb9 TS |
4413 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4414 | AT, sreg, treg); | |
252b5132 | 4415 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4416 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4417 | break; |
4418 | ||
4419 | case M_BLTUL: | |
4420 | likely = 1; | |
4421 | case M_BLTU: | |
4422 | if (treg == 0) | |
4423 | goto do_false; | |
4424 | if (sreg == 0) | |
4425 | { | |
4426 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4427 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4428 | return; |
4429 | } | |
2396cfb9 TS |
4430 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4431 | "d,v,t", AT, sreg, | |
252b5132 RH |
4432 | treg); |
4433 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4434 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4435 | break; |
4436 | ||
4437 | case M_DDIV_3: | |
4438 | dbl = 1; | |
4439 | case M_DIV_3: | |
4440 | s = "mflo"; | |
4441 | goto do_div3; | |
4442 | case M_DREM_3: | |
4443 | dbl = 1; | |
4444 | case M_REM_3: | |
4445 | s = "mfhi"; | |
4446 | do_div3: | |
4447 | if (treg == 0) | |
4448 | { | |
4449 | as_warn (_("Divide by zero.")); | |
4450 | if (mips_trap) | |
2396cfb9 TS |
4451 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4452 | "s,t", 0, 0); | |
252b5132 | 4453 | else |
2396cfb9 TS |
4454 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4455 | "c", 7); | |
252b5132 RH |
4456 | return; |
4457 | } | |
4458 | ||
4459 | mips_emit_delays (true); | |
4460 | ++mips_opts.noreorder; | |
4461 | mips_any_noreorder = 1; | |
4462 | if (mips_trap) | |
4463 | { | |
2396cfb9 TS |
4464 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4465 | "s,t", treg, 0); | |
4466 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a41af64 | 4467 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4468 | } |
4469 | else | |
4470 | { | |
4471 | expr1.X_add_number = 8; | |
4472 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 | 4473 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4474 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
2396cfb9 TS |
4475 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4476 | "c", 7); | |
252b5132 RH |
4477 | } |
4478 | expr1.X_add_number = -1; | |
4479 | macro_build ((char *) NULL, &icnt, &expr1, | |
4480 | dbl ? "daddiu" : "addiu", | |
4481 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4482 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4483 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4484 | if (dbl) | |
4485 | { | |
4486 | expr1.X_add_number = 1; | |
4487 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4488 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4489 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
4490 | "d,w,<", AT, AT, 31); | |
252b5132 RH |
4491 | } |
4492 | else | |
4493 | { | |
4494 | expr1.X_add_number = 0x80000000; | |
4495 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4496 | (int) BFD_RELOC_HI16); | |
4497 | } | |
4498 | if (mips_trap) | |
4499 | { | |
2396cfb9 TS |
4500 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4501 | "s,t", sreg, AT); | |
252b5132 RH |
4502 | /* We want to close the noreorder block as soon as possible, so |
4503 | that later insns are available for delay slot filling. */ | |
4504 | --mips_opts.noreorder; | |
4505 | } | |
4506 | else | |
4507 | { | |
4508 | expr1.X_add_number = 8; | |
4509 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2396cfb9 TS |
4510 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4511 | 0); | |
252b5132 RH |
4512 | |
4513 | /* We want to close the noreorder block as soon as possible, so | |
4514 | that later insns are available for delay slot filling. */ | |
4515 | --mips_opts.noreorder; | |
4516 | ||
2396cfb9 TS |
4517 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4518 | "c", 6); | |
252b5132 | 4519 | } |
2396cfb9 | 4520 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
252b5132 RH |
4521 | break; |
4522 | ||
4523 | case M_DIV_3I: | |
4524 | s = "div"; | |
4525 | s2 = "mflo"; | |
4526 | goto do_divi; | |
4527 | case M_DIVU_3I: | |
4528 | s = "divu"; | |
4529 | s2 = "mflo"; | |
4530 | goto do_divi; | |
4531 | case M_REM_3I: | |
4532 | s = "div"; | |
4533 | s2 = "mfhi"; | |
4534 | goto do_divi; | |
4535 | case M_REMU_3I: | |
4536 | s = "divu"; | |
4537 | s2 = "mfhi"; | |
4538 | goto do_divi; | |
4539 | case M_DDIV_3I: | |
4540 | dbl = 1; | |
4541 | s = "ddiv"; | |
4542 | s2 = "mflo"; | |
4543 | goto do_divi; | |
4544 | case M_DDIVU_3I: | |
4545 | dbl = 1; | |
4546 | s = "ddivu"; | |
4547 | s2 = "mflo"; | |
4548 | goto do_divi; | |
4549 | case M_DREM_3I: | |
4550 | dbl = 1; | |
4551 | s = "ddiv"; | |
4552 | s2 = "mfhi"; | |
4553 | goto do_divi; | |
4554 | case M_DREMU_3I: | |
4555 | dbl = 1; | |
4556 | s = "ddivu"; | |
4557 | s2 = "mfhi"; | |
4558 | do_divi: | |
4559 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4560 | { | |
4561 | as_warn (_("Divide by zero.")); | |
4562 | if (mips_trap) | |
2396cfb9 TS |
4563 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4564 | "s,t", 0, 0); | |
252b5132 | 4565 | else |
2396cfb9 TS |
4566 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4567 | "c", 7); | |
252b5132 RH |
4568 | return; |
4569 | } | |
4570 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4571 | { | |
4572 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4573 | move_register (&icnt, dreg, sreg); |
252b5132 | 4574 | else |
ea1fb5dc | 4575 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4576 | return; |
4577 | } | |
4578 | if (imm_expr.X_op == O_constant | |
4579 | && imm_expr.X_add_number == -1 | |
4580 | && s[strlen (s) - 1] != 'u') | |
4581 | { | |
4582 | if (strcmp (s2, "mflo") == 0) | |
4583 | { | |
2396cfb9 TS |
4584 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4585 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); | |
252b5132 RH |
4586 | } |
4587 | else | |
ea1fb5dc | 4588 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4589 | return; |
4590 | } | |
4591 | ||
4592 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4593 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4594 | sreg, AT); | |
4595 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); | |
252b5132 RH |
4596 | break; |
4597 | ||
4598 | case M_DIVU_3: | |
4599 | s = "divu"; | |
4600 | s2 = "mflo"; | |
4601 | goto do_divu3; | |
4602 | case M_REMU_3: | |
4603 | s = "divu"; | |
4604 | s2 = "mfhi"; | |
4605 | goto do_divu3; | |
4606 | case M_DDIVU_3: | |
4607 | s = "ddivu"; | |
4608 | s2 = "mflo"; | |
4609 | goto do_divu3; | |
4610 | case M_DREMU_3: | |
4611 | s = "ddivu"; | |
4612 | s2 = "mfhi"; | |
4613 | do_divu3: | |
4614 | mips_emit_delays (true); | |
4615 | ++mips_opts.noreorder; | |
4616 | mips_any_noreorder = 1; | |
4617 | if (mips_trap) | |
4618 | { | |
2396cfb9 TS |
4619 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
4620 | "s,t", treg, 0); | |
4621 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", | |
4622 | sreg, treg); | |
252b5132 RH |
4623 | /* We want to close the noreorder block as soon as possible, so |
4624 | that later insns are available for delay slot filling. */ | |
4625 | --mips_opts.noreorder; | |
4626 | } | |
4627 | else | |
4628 | { | |
4629 | expr1.X_add_number = 8; | |
4630 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 TS |
4631 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4632 | sreg, treg); | |
252b5132 RH |
4633 | |
4634 | /* We want to close the noreorder block as soon as possible, so | |
4635 | that later insns are available for delay slot filling. */ | |
4636 | --mips_opts.noreorder; | |
2396cfb9 TS |
4637 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4638 | "c", 7); | |
252b5132 | 4639 | } |
2396cfb9 | 4640 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
252b5132 RH |
4641 | return; |
4642 | ||
4643 | case M_DLA_AB: | |
4644 | dbl = 1; | |
4645 | case M_LA_AB: | |
4646 | /* Load the address of a symbol into a register. If breg is not | |
4647 | zero, we then add a base register to it. */ | |
4648 | ||
3bec30a8 TS |
4649 | if (dbl && HAVE_32BIT_GPRS) |
4650 | as_warn (_("dla used to load 32-bit register")); | |
4651 | ||
c90bbe5b | 4652 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4653 | as_warn (_("la used to load 64-bit address")); |
4654 | ||
afdbd6d0 CD |
4655 | if (treg == breg) |
4656 | { | |
4657 | tempreg = AT; | |
4658 | used_at = 1; | |
4659 | } | |
4660 | else | |
4661 | { | |
4662 | tempreg = treg; | |
4663 | used_at = 0; | |
4664 | } | |
4665 | ||
252b5132 RH |
4666 | /* When generating embedded PIC code, we permit expressions of |
4667 | the form | |
afdbd6d0 CD |
4668 | la $treg,foo-bar |
4669 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4670 | where bar is an address in the current section. These are used |
252b5132 RH |
4671 | when getting the addresses of functions. We don't permit |
4672 | X_add_number to be non-zero, because if the symbol is | |
4673 | external the relaxing code needs to know that any addend is | |
4674 | purely the offset to X_op_symbol. */ | |
4675 | if (mips_pic == EMBEDDED_PIC | |
4676 | && offset_expr.X_op == O_subtract | |
49309057 | 4677 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4678 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4679 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4680 | && (S_GET_SEGMENT | |
4681 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4682 | ->X_add_symbol) | |
bb2d6cd7 | 4683 | == now_seg))) |
bb2d6cd7 GK |
4684 | && (offset_expr.X_add_number == 0 |
4685 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4686 | { |
afdbd6d0 CD |
4687 | if (breg == 0) |
4688 | { | |
4689 | tempreg = treg; | |
4690 | used_at = 0; | |
4691 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4692 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4693 | } | |
4694 | else | |
4695 | { | |
4696 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4697 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4698 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4d34fb5f | 4699 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4700 | "d,v,t", tempreg, tempreg, breg); |
4701 | } | |
252b5132 | 4702 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 4703 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
afdbd6d0 CD |
4704 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
4705 | if (! used_at) | |
4706 | return; | |
4707 | break; | |
252b5132 RH |
4708 | } |
4709 | ||
4710 | if (offset_expr.X_op != O_symbol | |
4711 | && offset_expr.X_op != O_constant) | |
4712 | { | |
4713 | as_bad (_("expression too complex")); | |
4714 | offset_expr.X_op = O_constant; | |
4715 | } | |
4716 | ||
252b5132 | 4717 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4718 | load_register (&icnt, tempreg, &offset_expr, |
4719 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4720 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4721 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4722 | else if (mips_pic == NO_PIC) |
4723 | { | |
d6bc6245 | 4724 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4725 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4726 | Otherwise we want |
4727 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4728 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4729 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4730 | so we may as well always use the latter form. |
76b3015f | 4731 | |
d6bc6245 TS |
4732 | With 64bit address space and a usable $at we want |
4733 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4734 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4735 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4736 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4737 | dsll32 $tempreg,0 | |
4738 | dadd $tempreg,$tempreg,$at | |
76b3015f | 4739 | |
d6bc6245 TS |
4740 | If $at is already in use, we use an path which is suboptimal |
4741 | on superscalar processors. | |
4742 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4743 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4744 | dsll $tempreg,16 | |
4745 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4746 | dsll $tempreg,16 | |
4747 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4748 | */ | |
f9419b05 | 4749 | char *p = NULL; |
d6bc6245 | 4750 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4751 | { |
d6bc6245 TS |
4752 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4753 | hold the data for such large chunks. */ | |
4754 | ||
98d3f06f KH |
4755 | if (used_at == 0) |
4756 | { | |
4757 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4758 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4759 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4760 | AT, (int) BFD_RELOC_HI16_S); | |
4761 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4762 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4763 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4764 | AT, AT, (int) BFD_RELOC_LO16); | |
4765 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
4766 | "d,w,<", tempreg, tempreg, 0); | |
4767 | macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t", | |
4768 | tempreg, tempreg, AT); | |
4769 | used_at = 1; | |
4770 | } | |
4771 | else | |
4772 | { | |
4773 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4774 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4775 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4776 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4777 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4778 | tempreg, tempreg, 16); | |
4779 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4780 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
4781 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4782 | tempreg, tempreg, 16); | |
4783 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4784 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4785 | } | |
4786 | } | |
4787 | else | |
4788 | { | |
4789 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4790 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4791 | { | |
4792 | frag_grow (20); | |
4793 | macro_build ((char *) NULL, &icnt, &offset_expr, "addiu", | |
c9914766 TS |
4794 | "t,r,j", tempreg, mips_gp_register, |
4795 | (int) BFD_RELOC_GPREL16); | |
98d3f06f KH |
4796 | p = frag_var (rs_machine_dependent, 8, 0, |
4797 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4798 | mips_opts.warn_about_macros), | |
4799 | offset_expr.X_add_symbol, 0, NULL); | |
4800 | } | |
4801 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4802 | if (p != NULL) | |
4803 | p += 4; | |
4804 | macro_build (p, &icnt, &offset_expr, "addiu", | |
4805 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4806 | } | |
252b5132 RH |
4807 | } |
4808 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4809 | { | |
9117d219 NC |
4810 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4811 | ||
252b5132 RH |
4812 | /* If this is a reference to an external symbol, and there |
4813 | is no constant, we want | |
4814 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4815 | or if tempreg is PIC_CALL_REG |
4816 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4817 | For a local symbol, we want |
4818 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4819 | nop | |
4820 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4821 | ||
4822 | If we have a small constant, and this is a reference to | |
4823 | an external symbol, we want | |
4824 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4825 | nop | |
4826 | addiu $tempreg,$tempreg,<constant> | |
4827 | For a local symbol, we want the same instruction | |
4828 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4829 | addiu instruction. | |
4830 | ||
4831 | If we have a large constant, and this is a reference to | |
4832 | an external symbol, we want | |
4833 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4834 | lui $at,<hiconstant> | |
4835 | addiu $at,$at,<loconstant> | |
4836 | addu $tempreg,$tempreg,$at | |
4837 | For a local symbol, we want the same instruction | |
4838 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4839 | addiu instruction. */ | |
4840 | expr1.X_add_number = offset_expr.X_add_number; | |
4841 | offset_expr.X_add_number = 0; | |
4842 | frag_grow (32); | |
9117d219 NC |
4843 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4844 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
4d34fb5f TS |
4845 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4846 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
c9914766 | 4847 | "t,o(b)", tempreg, lw_reloc_type, mips_gp_register); |
252b5132 RH |
4848 | if (expr1.X_add_number == 0) |
4849 | { | |
4850 | int off; | |
f9419b05 | 4851 | char *p; |
252b5132 RH |
4852 | |
4853 | if (breg == 0) | |
4854 | off = 0; | |
4855 | else | |
4856 | { | |
4857 | /* We're going to put in an addu instruction using | |
4858 | tempreg, so we may as well insert the nop right | |
4859 | now. */ | |
4860 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4861 | "nop", ""); | |
4862 | off = 4; | |
4863 | } | |
4864 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4865 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4866 | (breg == 0 | |
4867 | ? mips_opts.warn_about_macros | |
4868 | : 0)), | |
c4e7957c | 4869 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4870 | if (breg == 0) |
4871 | { | |
4872 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4873 | p += 4; | |
4874 | } | |
4875 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4876 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4877 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4878 | /* FIXME: If breg == 0, and the next instruction uses | |
4879 | $tempreg, then if this variant case is used an extra | |
4880 | nop will be generated. */ | |
4881 | } | |
4882 | else if (expr1.X_add_number >= -0x8000 | |
4883 | && expr1.X_add_number < 0x8000) | |
4884 | { | |
4885 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4886 | "nop", ""); | |
4887 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4888 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 | 4889 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
c4e7957c TS |
4890 | frag_var (rs_machine_dependent, 0, 0, |
4891 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4892 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4893 | } |
4894 | else | |
4895 | { | |
4896 | int off1; | |
4897 | ||
4898 | /* If we are going to add in a base register, and the | |
4899 | target register and the base register are the same, | |
4900 | then we are using AT as a temporary register. Since | |
4901 | we want to load the constant into AT, we add our | |
4902 | current AT (from the global offset table) and the | |
4903 | register into the register now, and pretend we were | |
4904 | not using a base register. */ | |
4905 | if (breg != treg) | |
4906 | off1 = 0; | |
4907 | else | |
4908 | { | |
4909 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4910 | "nop", ""); | |
4911 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4912 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4913 | "d,v,t", treg, AT, breg); |
4914 | breg = 0; | |
4915 | tempreg = treg; | |
4916 | off1 = -8; | |
4917 | } | |
4918 | ||
4919 | /* Set mips_optimize around the lui instruction to avoid | |
4920 | inserting an unnecessary nop after the lw. */ | |
4921 | hold_mips_optimize = mips_optimize; | |
4922 | mips_optimize = 2; | |
c4e7957c | 4923 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
4924 | mips_optimize = hold_mips_optimize; |
4925 | ||
4926 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4927 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4928 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4929 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4930 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 4931 | "d,v,t", tempreg, tempreg, AT); |
c4e7957c TS |
4932 | frag_var (rs_machine_dependent, 0, 0, |
4933 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4934 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4935 | used_at = 1; |
4936 | } | |
4937 | } | |
4938 | else if (mips_pic == SVR4_PIC) | |
4939 | { | |
4940 | int gpdel; | |
f9419b05 | 4941 | char *p; |
9117d219 NC |
4942 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
4943 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
252b5132 RH |
4944 | |
4945 | /* This is the large GOT case. If this is a reference to an | |
4946 | external symbol, and there is no constant, we want | |
4947 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4948 | addu $tempreg,$tempreg,$gp | |
4949 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
4950 | or if tempreg is PIC_CALL_REG |
4951 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4952 | addu $tempreg,$tempreg,$gp | |
4953 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
4954 | For a local symbol, we want |
4955 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4956 | nop | |
4957 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4958 | ||
4959 | If we have a small constant, and this is a reference to | |
4960 | an external symbol, we want | |
4961 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4962 | addu $tempreg,$tempreg,$gp | |
4963 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4964 | nop | |
4965 | addiu $tempreg,$tempreg,<constant> | |
4966 | For a local symbol, we want | |
4967 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4968 | nop | |
4969 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4970 | ||
4971 | If we have a large constant, and this is a reference to | |
4972 | an external symbol, we want | |
4973 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4974 | addu $tempreg,$tempreg,$gp | |
4975 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4976 | lui $at,<hiconstant> | |
4977 | addiu $at,$at,<loconstant> | |
4978 | addu $tempreg,$tempreg,$at | |
4979 | For a local symbol, we want | |
4980 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4981 | lui $at,<hiconstant> | |
4982 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4983 | addu $tempreg,$tempreg,$at | |
438c16b8 TS |
4984 | |
4985 | For NewABI, we want for data addresses | |
4986 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4987 | If tempreg is PIC_CALL_REG pointing to a external symbol, we want | |
4988 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
4989 | */ | |
4990 | if (HAVE_NEWABI) | |
4991 | { | |
4992 | int reloc_type = (tempreg == PIC_CALL_REG | |
4993 | ? BFD_RELOC_MIPS_CALL16 | |
4994 | : BFD_RELOC_MIPS_GOT_DISP); | |
4995 | ||
4996 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4997 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
4998 | "t,o(b)", tempreg, reloc_type, mips_gp_register); | |
4999 | ||
5000 | if (breg != 0) | |
5001 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5002 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5003 | "d,v,t", treg, tempreg, breg); | |
5004 | ||
5005 | if (! used_at) | |
5006 | return; | |
5007 | ||
5008 | break; | |
5009 | } | |
252b5132 RH |
5010 | expr1.X_add_number = offset_expr.X_add_number; |
5011 | offset_expr.X_add_number = 0; | |
5012 | frag_grow (52); | |
f7ea7ef2 | 5013 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5014 | gpdel = 4; |
5015 | else | |
5016 | gpdel = 0; | |
9117d219 NC |
5017 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
5018 | { | |
5019 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5020 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5021 | } | |
252b5132 | 5022 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 5023 | tempreg, lui_reloc_type); |
252b5132 | 5024 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
ca4e0257 | 5025 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5026 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 5027 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 5028 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
9117d219 | 5029 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5030 | if (expr1.X_add_number == 0) |
5031 | { | |
5032 | int off; | |
5033 | ||
5034 | if (breg == 0) | |
5035 | off = 0; | |
5036 | else | |
5037 | { | |
5038 | /* We're going to put in an addu instruction using | |
5039 | tempreg, so we may as well insert the nop right | |
5040 | now. */ | |
5041 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5042 | "nop", ""); | |
5043 | off = 4; | |
5044 | } | |
5045 | ||
5046 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5047 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
5048 | 8 + gpdel, 0, | |
5049 | (breg == 0 | |
5050 | ? mips_opts.warn_about_macros | |
5051 | : 0)), | |
c4e7957c | 5052 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5053 | } |
5054 | else if (expr1.X_add_number >= -0x8000 | |
5055 | && expr1.X_add_number < 0x8000) | |
5056 | { | |
5057 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5058 | "nop", ""); | |
5059 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5060 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5061 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5062 | ||
5063 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5064 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
5065 | (breg == 0 | |
5066 | ? mips_opts.warn_about_macros | |
5067 | : 0)), | |
c4e7957c | 5068 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5069 | } |
5070 | else | |
5071 | { | |
5072 | int adj, dreg; | |
5073 | ||
5074 | /* If we are going to add in a base register, and the | |
5075 | target register and the base register are the same, | |
5076 | then we are using AT as a temporary register. Since | |
5077 | we want to load the constant into AT, we add our | |
5078 | current AT (from the global offset table) and the | |
5079 | register into the register now, and pretend we were | |
5080 | not using a base register. */ | |
5081 | if (breg != treg) | |
5082 | { | |
5083 | adj = 0; | |
5084 | dreg = tempreg; | |
5085 | } | |
5086 | else | |
5087 | { | |
5088 | assert (tempreg == AT); | |
5089 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5090 | "nop", ""); | |
5091 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5092 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5093 | "d,v,t", treg, AT, breg); |
5094 | dreg = treg; | |
5095 | adj = 8; | |
5096 | } | |
5097 | ||
5098 | /* Set mips_optimize around the lui instruction to avoid | |
5099 | inserting an unnecessary nop after the lw. */ | |
5100 | hold_mips_optimize = mips_optimize; | |
5101 | mips_optimize = 2; | |
c4e7957c | 5102 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
5103 | mips_optimize = hold_mips_optimize; |
5104 | ||
5105 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 5106 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5107 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5108 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5109 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5110 | "d,v,t", dreg, dreg, AT); |
5111 | ||
5112 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
5113 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
5114 | 8 + gpdel, 0, | |
5115 | (breg == 0 | |
5116 | ? mips_opts.warn_about_macros | |
5117 | : 0)), | |
c4e7957c | 5118 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5119 | |
5120 | used_at = 1; | |
5121 | } | |
5122 | ||
5123 | if (gpdel > 0) | |
5124 | { | |
5125 | /* This is needed because this instruction uses $gp, but | |
5126 | the first instruction on the main stream does not. */ | |
5127 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5128 | p += 4; | |
5129 | } | |
5130 | macro_build (p, &icnt, &offset_expr, | |
4d34fb5f | 5131 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
5132 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
5133 | mips_gp_register); | |
252b5132 RH |
5134 | p += 4; |
5135 | if (expr1.X_add_number >= -0x8000 | |
5136 | && expr1.X_add_number < 0x8000) | |
5137 | { | |
5138 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5139 | p += 4; | |
5140 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5141 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5142 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5143 | /* FIXME: If add_number is 0, and there was no base | |
5144 | register, the external symbol case ended with a load, | |
5145 | so if the symbol turns out to not be external, and | |
5146 | the next instruction uses tempreg, an unnecessary nop | |
5147 | will be inserted. */ | |
5148 | } | |
5149 | else | |
5150 | { | |
5151 | if (breg == treg) | |
5152 | { | |
5153 | /* We must add in the base register now, as in the | |
5154 | external symbol case. */ | |
5155 | assert (tempreg == AT); | |
5156 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5157 | p += 4; | |
5158 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5159 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5160 | "d,v,t", treg, AT, breg); |
5161 | p += 4; | |
5162 | tempreg = treg; | |
5163 | /* We set breg to 0 because we have arranged to add | |
5164 | it in in both cases. */ | |
5165 | breg = 0; | |
5166 | } | |
5167 | ||
5168 | macro_build_lui (p, &icnt, &expr1, AT); | |
5169 | p += 4; | |
5170 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5171 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5172 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5173 | p += 4; | |
5174 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5175 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5176 | "d,v,t", tempreg, tempreg, AT); |
5177 | p += 4; | |
5178 | } | |
5179 | } | |
5180 | else if (mips_pic == EMBEDDED_PIC) | |
5181 | { | |
5182 | /* We use | |
cdf6fd85 | 5183 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5184 | */ |
5185 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
5186 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
5187 | tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
5188 | } |
5189 | else | |
5190 | abort (); | |
5191 | ||
5192 | if (breg != 0) | |
4d34fb5f TS |
5193 | { |
5194 | char *s; | |
5195 | ||
5196 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
5197 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; | |
5198 | else | |
5199 | s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu"; | |
5200 | ||
5201 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
5202 | "d,v,t", treg, tempreg, breg); | |
5203 | } | |
252b5132 RH |
5204 | |
5205 | if (! used_at) | |
5206 | return; | |
5207 | ||
5208 | break; | |
5209 | ||
5210 | case M_J_A: | |
5211 | /* The j instruction may not be used in PIC code, since it | |
5212 | requires an absolute address. We convert it to a b | |
5213 | instruction. */ | |
5214 | if (mips_pic == NO_PIC) | |
5215 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
5216 | else | |
5217 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
5218 | return; | |
5219 | ||
5220 | /* The jal instructions must be handled as macros because when | |
5221 | generating PIC code they expand to multi-instruction | |
5222 | sequences. Normally they are simple instructions. */ | |
5223 | case M_JAL_1: | |
5224 | dreg = RA; | |
5225 | /* Fall through. */ | |
5226 | case M_JAL_2: | |
5227 | if (mips_pic == NO_PIC | |
5228 | || mips_pic == EMBEDDED_PIC) | |
5229 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
5230 | "d,s", dreg, sreg); | |
5231 | else if (mips_pic == SVR4_PIC) | |
5232 | { | |
5233 | if (sreg != PIC_CALL_REG) | |
5234 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5235 | |
252b5132 RH |
5236 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
5237 | "d,s", dreg, sreg); | |
6478892d | 5238 | if (! HAVE_NEWABI) |
252b5132 | 5239 | { |
6478892d TS |
5240 | if (mips_cprestore_offset < 0) |
5241 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5242 | else | |
5243 | { | |
7a621144 DJ |
5244 | if (! mips_frame_reg_valid) |
5245 | { | |
5246 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5247 | /* Quiet this warning. */ | |
5248 | mips_frame_reg_valid = 1; | |
5249 | } | |
5250 | if (! mips_cprestore_valid) | |
5251 | { | |
5252 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5253 | /* Quiet this warning. */ | |
5254 | mips_cprestore_valid = 1; | |
5255 | } | |
6478892d TS |
5256 | expr1.X_add_number = mips_cprestore_offset; |
5257 | macro_build ((char *) NULL, &icnt, &expr1, | |
5258 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
c9914766 TS |
5259 | mips_gp_register, (int) BFD_RELOC_LO16, |
5260 | mips_frame_reg); | |
6478892d | 5261 | } |
252b5132 RH |
5262 | } |
5263 | } | |
5264 | else | |
5265 | abort (); | |
5266 | ||
5267 | return; | |
5268 | ||
5269 | case M_JAL_A: | |
5270 | if (mips_pic == NO_PIC) | |
5271 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5272 | else if (mips_pic == SVR4_PIC) | |
5273 | { | |
f9419b05 TS |
5274 | char *p; |
5275 | ||
252b5132 RH |
5276 | /* If this is a reference to an external symbol, and we are |
5277 | using a small GOT, we want | |
5278 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5279 | nop | |
f9419b05 | 5280 | jalr $ra,$25 |
252b5132 RH |
5281 | nop |
5282 | lw $gp,cprestore($sp) | |
5283 | The cprestore value is set using the .cprestore | |
5284 | pseudo-op. If we are using a big GOT, we want | |
5285 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5286 | addu $25,$25,$gp | |
5287 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5288 | nop | |
f9419b05 | 5289 | jalr $ra,$25 |
252b5132 RH |
5290 | nop |
5291 | lw $gp,cprestore($sp) | |
5292 | If the symbol is not external, we want | |
5293 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5294 | nop | |
5295 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5296 | jalr $ra,$25 |
252b5132 | 5297 | nop |
438c16b8 TS |
5298 | lw $gp,cprestore($sp) |
5299 | For NewABI, we want | |
5300 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5301 | jalr $ra,$25 (BFD_RELOC_MIPS_JALR) | |
5302 | */ | |
5303 | if (HAVE_NEWABI) | |
252b5132 RH |
5304 | { |
5305 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5306 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 | 5307 | "t,o(b)", PIC_CALL_REG, |
438c16b8 TS |
5308 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
5309 | macro_build_jalr (icnt, &offset_expr); | |
252b5132 RH |
5310 | } |
5311 | else | |
5312 | { | |
438c16b8 TS |
5313 | frag_grow (40); |
5314 | if (! mips_big_got) | |
5315 | { | |
5316 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5317 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5318 | "t,o(b)", PIC_CALL_REG, | |
5319 | (int) BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
5320 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5321 | "nop", ""); | |
5322 | p = frag_var (rs_machine_dependent, 4, 0, | |
5323 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5324 | offset_expr.X_add_symbol, 0, NULL); | |
5325 | } | |
252b5132 | 5326 | else |
252b5132 | 5327 | { |
438c16b8 TS |
5328 | int gpdel; |
5329 | ||
5330 | if (reg_needs_delay (mips_gp_register)) | |
5331 | gpdel = 4; | |
5332 | else | |
5333 | gpdel = 0; | |
5334 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", | |
5335 | "t,u", PIC_CALL_REG, | |
5336 | (int) BFD_RELOC_MIPS_CALL_HI16); | |
5337 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5338 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5339 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, | |
5340 | mips_gp_register); | |
5341 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5342 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5343 | "t,o(b)", PIC_CALL_REG, | |
5344 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5345 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5346 | "nop", ""); | |
5347 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5348 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5349 | 8 + gpdel, 0, 0), | |
5350 | offset_expr.X_add_symbol, 0, NULL); | |
5351 | if (gpdel > 0) | |
5352 | { | |
5353 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5354 | p += 4; | |
5355 | } | |
5356 | macro_build (p, &icnt, &offset_expr, | |
5357 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5358 | "t,o(b)", PIC_CALL_REG, | |
5359 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
5360 | p += 4; | |
252b5132 RH |
5361 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
5362 | p += 4; | |
5363 | } | |
5364 | macro_build (p, &icnt, &offset_expr, | |
438c16b8 TS |
5365 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
5366 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
5367 | (int) BFD_RELOC_LO16); | |
5368 | macro_build_jalr (icnt, &offset_expr); | |
5369 | ||
6478892d TS |
5370 | if (mips_cprestore_offset < 0) |
5371 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5372 | else | |
5373 | { | |
7a621144 DJ |
5374 | if (! mips_frame_reg_valid) |
5375 | { | |
5376 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5377 | /* Quiet this warning. */ | |
5378 | mips_frame_reg_valid = 1; | |
5379 | } | |
5380 | if (! mips_cprestore_valid) | |
5381 | { | |
5382 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5383 | /* Quiet this warning. */ | |
5384 | mips_cprestore_valid = 1; | |
5385 | } | |
6478892d TS |
5386 | if (mips_opts.noreorder) |
5387 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
98d3f06f | 5388 | "nop", ""); |
6478892d TS |
5389 | expr1.X_add_number = mips_cprestore_offset; |
5390 | macro_build ((char *) NULL, &icnt, &expr1, | |
5391 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
c9914766 TS |
5392 | mips_gp_register, (int) BFD_RELOC_LO16, |
5393 | mips_frame_reg); | |
6478892d | 5394 | } |
252b5132 RH |
5395 | } |
5396 | } | |
5397 | else if (mips_pic == EMBEDDED_PIC) | |
5398 | { | |
5399 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5400 | /* The linker may expand the call to a longer sequence which | |
5401 | uses $at, so we must break rather than return. */ | |
5402 | break; | |
5403 | } | |
5404 | else | |
5405 | abort (); | |
5406 | ||
5407 | return; | |
5408 | ||
5409 | case M_LB_AB: | |
5410 | s = "lb"; | |
5411 | goto ld; | |
5412 | case M_LBU_AB: | |
5413 | s = "lbu"; | |
5414 | goto ld; | |
5415 | case M_LH_AB: | |
5416 | s = "lh"; | |
5417 | goto ld; | |
5418 | case M_LHU_AB: | |
5419 | s = "lhu"; | |
5420 | goto ld; | |
5421 | case M_LW_AB: | |
5422 | s = "lw"; | |
5423 | goto ld; | |
5424 | case M_LWC0_AB: | |
5425 | s = "lwc0"; | |
bdaaa2e1 | 5426 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5427 | coproc = 1; |
5428 | goto ld; | |
5429 | case M_LWC1_AB: | |
5430 | s = "lwc1"; | |
bdaaa2e1 | 5431 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5432 | coproc = 1; |
5433 | goto ld; | |
5434 | case M_LWC2_AB: | |
5435 | s = "lwc2"; | |
bdaaa2e1 | 5436 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5437 | coproc = 1; |
5438 | goto ld; | |
5439 | case M_LWC3_AB: | |
5440 | s = "lwc3"; | |
bdaaa2e1 | 5441 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5442 | coproc = 1; |
5443 | goto ld; | |
5444 | case M_LWL_AB: | |
5445 | s = "lwl"; | |
5446 | lr = 1; | |
5447 | goto ld; | |
5448 | case M_LWR_AB: | |
5449 | s = "lwr"; | |
5450 | lr = 1; | |
5451 | goto ld; | |
5452 | case M_LDC1_AB: | |
ec68c924 | 5453 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5454 | { |
5455 | as_bad (_("opcode not supported on this processor")); | |
5456 | return; | |
5457 | } | |
5458 | s = "ldc1"; | |
bdaaa2e1 | 5459 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5460 | coproc = 1; |
5461 | goto ld; | |
5462 | case M_LDC2_AB: | |
5463 | s = "ldc2"; | |
bdaaa2e1 | 5464 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5465 | coproc = 1; |
5466 | goto ld; | |
5467 | case M_LDC3_AB: | |
5468 | s = "ldc3"; | |
bdaaa2e1 | 5469 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5470 | coproc = 1; |
5471 | goto ld; | |
5472 | case M_LDL_AB: | |
5473 | s = "ldl"; | |
5474 | lr = 1; | |
5475 | goto ld; | |
5476 | case M_LDR_AB: | |
5477 | s = "ldr"; | |
5478 | lr = 1; | |
5479 | goto ld; | |
5480 | case M_LL_AB: | |
5481 | s = "ll"; | |
5482 | goto ld; | |
5483 | case M_LLD_AB: | |
5484 | s = "lld"; | |
5485 | goto ld; | |
5486 | case M_LWU_AB: | |
5487 | s = "lwu"; | |
5488 | ld: | |
5489 | if (breg == treg || coproc || lr) | |
5490 | { | |
5491 | tempreg = AT; | |
5492 | used_at = 1; | |
5493 | } | |
5494 | else | |
5495 | { | |
5496 | tempreg = treg; | |
5497 | used_at = 0; | |
5498 | } | |
5499 | goto ld_st; | |
5500 | case M_SB_AB: | |
5501 | s = "sb"; | |
5502 | goto st; | |
5503 | case M_SH_AB: | |
5504 | s = "sh"; | |
5505 | goto st; | |
5506 | case M_SW_AB: | |
5507 | s = "sw"; | |
5508 | goto st; | |
5509 | case M_SWC0_AB: | |
5510 | s = "swc0"; | |
bdaaa2e1 | 5511 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5512 | coproc = 1; |
5513 | goto st; | |
5514 | case M_SWC1_AB: | |
5515 | s = "swc1"; | |
bdaaa2e1 | 5516 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5517 | coproc = 1; |
5518 | goto st; | |
5519 | case M_SWC2_AB: | |
5520 | s = "swc2"; | |
bdaaa2e1 | 5521 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5522 | coproc = 1; |
5523 | goto st; | |
5524 | case M_SWC3_AB: | |
5525 | s = "swc3"; | |
bdaaa2e1 | 5526 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5527 | coproc = 1; |
5528 | goto st; | |
5529 | case M_SWL_AB: | |
5530 | s = "swl"; | |
5531 | goto st; | |
5532 | case M_SWR_AB: | |
5533 | s = "swr"; | |
5534 | goto st; | |
5535 | case M_SC_AB: | |
5536 | s = "sc"; | |
5537 | goto st; | |
5538 | case M_SCD_AB: | |
5539 | s = "scd"; | |
5540 | goto st; | |
5541 | case M_SDC1_AB: | |
ec68c924 | 5542 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5543 | { |
5544 | as_bad (_("opcode not supported on this processor")); | |
5545 | return; | |
5546 | } | |
5547 | s = "sdc1"; | |
5548 | coproc = 1; | |
bdaaa2e1 | 5549 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5550 | goto st; |
5551 | case M_SDC2_AB: | |
5552 | s = "sdc2"; | |
bdaaa2e1 | 5553 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5554 | coproc = 1; |
5555 | goto st; | |
5556 | case M_SDC3_AB: | |
5557 | s = "sdc3"; | |
bdaaa2e1 | 5558 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5559 | coproc = 1; |
5560 | goto st; | |
5561 | case M_SDL_AB: | |
5562 | s = "sdl"; | |
5563 | goto st; | |
5564 | case M_SDR_AB: | |
5565 | s = "sdr"; | |
5566 | st: | |
5567 | tempreg = AT; | |
5568 | used_at = 1; | |
5569 | ld_st: | |
bdaaa2e1 | 5570 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5571 | if (mask == M_LWC1_AB |
5572 | || mask == M_SWC1_AB | |
5573 | || mask == M_LDC1_AB | |
5574 | || mask == M_SDC1_AB | |
5575 | || mask == M_L_DAB | |
5576 | || mask == M_S_DAB) | |
5577 | fmt = "T,o(b)"; | |
5578 | else if (coproc) | |
5579 | fmt = "E,o(b)"; | |
5580 | else | |
5581 | fmt = "t,o(b)"; | |
5582 | ||
afdbd6d0 CD |
5583 | /* For embedded PIC, we allow loads where the offset is calculated |
5584 | by subtracting a symbol in the current segment from an unknown | |
5585 | symbol, relative to a base register, e.g.: | |
5586 | <op> $treg, <sym>-<localsym>($breg) | |
5587 | This is used by the compiler for switch statements. */ | |
76b3015f | 5588 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5589 | && offset_expr.X_op == O_subtract |
5590 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5591 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5592 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5593 | && (S_GET_SEGMENT | |
5594 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5595 | ->X_add_symbol) | |
5596 | == now_seg))) | |
5597 | && breg != 0 | |
5598 | && (offset_expr.X_add_number == 0 | |
5599 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5600 | { | |
5601 | /* For this case, we output the instructions: | |
5602 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5603 | addiu $tempreg,$tempreg,$breg | |
5604 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5605 | If the relocation would fit entirely in 16 bits, it would be | |
5606 | nice to emit: | |
5607 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5608 | instead, but that seems quite difficult. */ | |
5609 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5610 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
5611 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5612 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
5613 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
5614 | ? "addu" : "daddu"), | |
5615 | "d,v,t", tempreg, tempreg, breg); | |
5616 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, | |
5617 | (int) BFD_RELOC_PCREL_LO16, tempreg); | |
5618 | if (! used_at) | |
5619 | return; | |
5620 | break; | |
5621 | } | |
5622 | ||
252b5132 RH |
5623 | if (offset_expr.X_op != O_constant |
5624 | && offset_expr.X_op != O_symbol) | |
5625 | { | |
5626 | as_bad (_("expression too complex")); | |
5627 | offset_expr.X_op = O_constant; | |
5628 | } | |
5629 | ||
5630 | /* A constant expression in PIC code can be handled just as it | |
5631 | is in non PIC code. */ | |
5632 | if (mips_pic == NO_PIC | |
5633 | || offset_expr.X_op == O_constant) | |
5634 | { | |
f9419b05 TS |
5635 | char *p; |
5636 | ||
252b5132 RH |
5637 | /* If this is a reference to a GP relative symbol, and there |
5638 | is no base register, we want | |
cdf6fd85 | 5639 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5640 | Otherwise, if there is no base register, we want |
5641 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5642 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5643 | If we have a constant, we need two instructions anyhow, | |
5644 | so we always use the latter form. | |
5645 | ||
5646 | If we have a base register, and this is a reference to a | |
5647 | GP relative symbol, we want | |
5648 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5649 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5650 | Otherwise we want |
5651 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5652 | addu $tempreg,$tempreg,$breg | |
5653 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5654 | With a constant we always use the latter case. |
76b3015f | 5655 | |
d6bc6245 TS |
5656 | With 64bit address space and no base register and $at usable, |
5657 | we want | |
5658 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5659 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5660 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5661 | dsll32 $tempreg,0 | |
5662 | daddu $tempreg,$at | |
5663 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5664 | If we have a base register, we want | |
5665 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5666 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5667 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5668 | daddu $at,$breg | |
5669 | dsll32 $tempreg,0 | |
5670 | daddu $tempreg,$at | |
5671 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5672 | ||
5673 | Without $at we can't generate the optimal path for superscalar | |
5674 | processors here since this would require two temporary registers. | |
5675 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5676 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5677 | dsll $tempreg,16 | |
5678 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5679 | dsll $tempreg,16 | |
5680 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5681 | If we have a base register, we want | |
5682 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5683 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5684 | dsll $tempreg,16 | |
5685 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5686 | dsll $tempreg,16 | |
5687 | daddu $tempreg,$tempreg,$breg | |
5688 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5689 | |
5690 | If we have 64-bit addresses, as an optimization, for | |
5691 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5692 | addresses) we fall back to the 32-bit address generation | |
5693 | mechanism since it is more efficient. This code should | |
5694 | probably attempt to generate 64-bit constants more | |
5695 | efficiently in general. | |
d6bc6245 | 5696 | */ |
6373ee54 CD |
5697 | if (HAVE_64BIT_ADDRESSES |
5698 | && !(offset_expr.X_op == O_constant | |
5699 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number))) | |
d6bc6245 TS |
5700 | { |
5701 | p = NULL; | |
5702 | ||
5703 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5704 | hold the data for such large chunks. */ | |
5705 | ||
5706 | if (used_at == 0) | |
5707 | { | |
5708 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5709 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5710 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5711 | AT, (int) BFD_RELOC_HI16_S); | |
5712 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5713 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
5714 | if (breg != 0) | |
2396cfb9 TS |
5715 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5716 | "d,v,t", AT, AT, breg); | |
5717 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
5718 | "d,w,<", tempreg, tempreg, 0); | |
5719 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", | |
5720 | "d,v,t", tempreg, tempreg, AT); | |
d6bc6245 TS |
5721 | macro_build (p, &icnt, &offset_expr, s, |
5722 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5723 | used_at = 1; | |
5724 | } | |
5725 | else | |
5726 | { | |
5727 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5728 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5729 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5730 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
5731 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5732 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 TS |
5733 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
5734 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
5735 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5736 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5737 | if (breg != 0) |
2396cfb9 TS |
5738 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5739 | "d,v,t", tempreg, tempreg, breg); | |
d6bc6245 TS |
5740 | macro_build (p, &icnt, &offset_expr, s, |
5741 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5742 | } | |
5743 | ||
5744 | return; | |
5745 | } | |
76b3015f | 5746 | |
252b5132 RH |
5747 | if (breg == 0) |
5748 | { | |
e7d556df | 5749 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5750 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5751 | p = NULL; | |
5752 | else | |
5753 | { | |
5754 | frag_grow (20); | |
5755 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 TS |
5756 | treg, (int) BFD_RELOC_GPREL16, |
5757 | mips_gp_register); | |
252b5132 RH |
5758 | p = frag_var (rs_machine_dependent, 8, 0, |
5759 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5760 | (mips_opts.warn_about_macros | |
5761 | || (used_at | |
5762 | && mips_opts.noat))), | |
956cd1d6 | 5763 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5764 | used_at = 0; |
5765 | } | |
5766 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5767 | if (p != NULL) | |
5768 | p += 4; | |
5769 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5770 | (int) BFD_RELOC_LO16, tempreg); | |
5771 | } | |
5772 | else | |
5773 | { | |
e7d556df | 5774 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5775 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5776 | p = NULL; | |
5777 | else | |
5778 | { | |
5779 | frag_grow (28); | |
5780 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5781 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5782 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 5783 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 5784 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5785 | p = frag_var (rs_machine_dependent, 12, 0, |
5786 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 5787 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5788 | } |
5789 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5790 | if (p != NULL) | |
5791 | p += 4; | |
5792 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5793 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5794 | "d,v,t", tempreg, tempreg, breg); |
5795 | if (p != NULL) | |
5796 | p += 4; | |
5797 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5798 | (int) BFD_RELOC_LO16, tempreg); | |
5799 | } | |
5800 | } | |
5801 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5802 | { | |
f9419b05 TS |
5803 | char *p; |
5804 | ||
252b5132 RH |
5805 | /* If this is a reference to an external symbol, we want |
5806 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5807 | nop | |
5808 | <op> $treg,0($tempreg) | |
5809 | Otherwise we want | |
5810 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5811 | nop | |
5812 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5813 | <op> $treg,0($tempreg) | |
5814 | If there is a base register, we add it to $tempreg before | |
5815 | the <op>. If there is a constant, we stick it in the | |
5816 | <op> instruction. We don't handle constants larger than | |
5817 | 16 bits, because we have no way to load the upper 16 bits | |
5818 | (actually, we could handle them for the subset of cases | |
5819 | in which we are not using $at). */ | |
5820 | assert (offset_expr.X_op == O_symbol); | |
5821 | expr1.X_add_number = offset_expr.X_add_number; | |
5822 | offset_expr.X_add_number = 0; | |
5823 | if (expr1.X_add_number < -0x8000 | |
5824 | || expr1.X_add_number >= 0x8000) | |
5825 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5826 | frag_grow (20); | |
5827 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
5828 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg, |
5829 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 | 5830 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
bdaaa2e1 | 5831 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 5832 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 5833 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 | 5834 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5835 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5836 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5837 | if (breg != 0) | |
5838 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5839 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5840 | "d,v,t", tempreg, tempreg, breg); |
5841 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5842 | (int) BFD_RELOC_LO16, tempreg); | |
5843 | } | |
5844 | else if (mips_pic == SVR4_PIC) | |
5845 | { | |
5846 | int gpdel; | |
f9419b05 | 5847 | char *p; |
252b5132 RH |
5848 | |
5849 | /* If this is a reference to an external symbol, we want | |
5850 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5851 | addu $tempreg,$tempreg,$gp | |
5852 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5853 | <op> $treg,0($tempreg) | |
5854 | Otherwise we want | |
5855 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5856 | nop | |
5857 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5858 | <op> $treg,0($tempreg) | |
5859 | If there is a base register, we add it to $tempreg before | |
5860 | the <op>. If there is a constant, we stick it in the | |
5861 | <op> instruction. We don't handle constants larger than | |
5862 | 16 bits, because we have no way to load the upper 16 bits | |
5863 | (actually, we could handle them for the subset of cases | |
438c16b8 TS |
5864 | in which we are not using $at). |
5865 | ||
5866 | For NewABI, we want | |
5867 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5868 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5869 | <op> $treg,0($tempreg) | |
5870 | */ | |
252b5132 RH |
5871 | assert (offset_expr.X_op == O_symbol); |
5872 | expr1.X_add_number = offset_expr.X_add_number; | |
5873 | offset_expr.X_add_number = 0; | |
5874 | if (expr1.X_add_number < -0x8000 | |
5875 | || expr1.X_add_number >= 0x8000) | |
5876 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
438c16b8 TS |
5877 | if (HAVE_NEWABI) |
5878 | { | |
5879 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5880 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5881 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE, | |
5882 | mips_gp_register); | |
5883 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5884 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
5885 | "t,r,j", tempreg, tempreg, | |
5886 | BFD_RELOC_MIPS_GOT_OFST); | |
5887 | if (breg != 0) | |
5888 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5889 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5890 | "d,v,t", tempreg, tempreg, breg); | |
5891 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5892 | (int) BFD_RELOC_LO16, tempreg); | |
5893 | ||
5894 | if (! used_at) | |
5895 | return; | |
5896 | ||
5897 | break; | |
5898 | } | |
f7ea7ef2 | 5899 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5900 | gpdel = 4; |
5901 | else | |
5902 | gpdel = 0; | |
5903 | frag_grow (36); | |
5904 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5905 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5906 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5907 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5908 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 5909 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 5910 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5911 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5912 | tempreg); | |
5913 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5914 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 5915 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5916 | if (gpdel > 0) |
5917 | { | |
5918 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5919 | p += 4; | |
5920 | } | |
5921 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5922 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
5923 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
5924 | mips_gp_register); | |
252b5132 RH |
5925 | p += 4; |
5926 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5927 | p += 4; | |
5928 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5929 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5930 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5931 | if (breg != 0) | |
5932 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5933 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5934 | "d,v,t", tempreg, tempreg, breg); |
5935 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5936 | (int) BFD_RELOC_LO16, tempreg); | |
5937 | } | |
5938 | else if (mips_pic == EMBEDDED_PIC) | |
5939 | { | |
5940 | /* If there is no base register, we want | |
cdf6fd85 | 5941 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5942 | If there is a base register, we want |
5943 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5944 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5945 | */ |
5946 | assert (offset_expr.X_op == O_symbol); | |
5947 | if (breg == 0) | |
5948 | { | |
5949 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 | 5950 | treg, (int) BFD_RELOC_GPREL16, mips_gp_register); |
252b5132 RH |
5951 | used_at = 0; |
5952 | } | |
5953 | else | |
5954 | { | |
5955 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5956 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5957 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 5958 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 5959 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5960 | } |
5961 | } | |
5962 | else | |
5963 | abort (); | |
5964 | ||
5965 | if (! used_at) | |
5966 | return; | |
5967 | ||
5968 | break; | |
5969 | ||
5970 | case M_LI: | |
5971 | case M_LI_S: | |
5972 | load_register (&icnt, treg, &imm_expr, 0); | |
5973 | return; | |
5974 | ||
5975 | case M_DLI: | |
5976 | load_register (&icnt, treg, &imm_expr, 1); | |
5977 | return; | |
5978 | ||
5979 | case M_LI_SS: | |
5980 | if (imm_expr.X_op == O_constant) | |
5981 | { | |
5982 | load_register (&icnt, AT, &imm_expr, 0); | |
5983 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5984 | "mtc1", "t,G", AT, treg); | |
5985 | break; | |
5986 | } | |
5987 | else | |
5988 | { | |
5989 | assert (offset_expr.X_op == O_symbol | |
5990 | && strcmp (segment_name (S_GET_SEGMENT | |
5991 | (offset_expr.X_add_symbol)), | |
5992 | ".lit4") == 0 | |
5993 | && offset_expr.X_add_number == 0); | |
5994 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
c9914766 | 5995 | treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
5996 | return; |
5997 | } | |
5998 | ||
5999 | case M_LI_D: | |
ca4e0257 RS |
6000 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6001 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6002 | order 32 bits of the value and the low order 32 bits are either | |
6003 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6004 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6005 | { | |
ca4e0257 | 6006 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6007 | load_register (&icnt, treg, &imm_expr, 1); |
6008 | else | |
6009 | { | |
6010 | int hreg, lreg; | |
6011 | ||
6012 | if (target_big_endian) | |
6013 | { | |
6014 | hreg = treg; | |
6015 | lreg = treg + 1; | |
6016 | } | |
6017 | else | |
6018 | { | |
6019 | hreg = treg + 1; | |
6020 | lreg = treg; | |
6021 | } | |
6022 | ||
6023 | if (hreg <= 31) | |
6024 | load_register (&icnt, hreg, &imm_expr, 0); | |
6025 | if (lreg <= 31) | |
6026 | { | |
6027 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 6028 | move_register (&icnt, lreg, 0); |
252b5132 RH |
6029 | else |
6030 | { | |
6031 | assert (offset_expr.X_op == O_constant); | |
6032 | load_register (&icnt, lreg, &offset_expr, 0); | |
6033 | } | |
6034 | } | |
6035 | } | |
6036 | return; | |
6037 | } | |
6038 | ||
6039 | /* We know that sym is in the .rdata section. First we get the | |
6040 | upper 16 bits of the address. */ | |
6041 | if (mips_pic == NO_PIC) | |
6042 | { | |
956cd1d6 | 6043 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
6044 | } |
6045 | else if (mips_pic == SVR4_PIC) | |
6046 | { | |
6047 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6048 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6049 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6050 | mips_gp_register); | |
252b5132 RH |
6051 | } |
6052 | else if (mips_pic == EMBEDDED_PIC) | |
6053 | { | |
6054 | /* For embedded PIC we pick up the entire address off $gp in | |
6055 | a single instruction. */ | |
6056 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
6057 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT, |
6058 | mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
6059 | offset_expr.X_op = O_constant; |
6060 | offset_expr.X_add_number = 0; | |
6061 | } | |
6062 | else | |
6063 | abort (); | |
bdaaa2e1 | 6064 | |
252b5132 | 6065 | /* Now we load the register(s). */ |
ca4e0257 | 6066 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6067 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
6068 | treg, (int) BFD_RELOC_LO16, AT); | |
6069 | else | |
6070 | { | |
6071 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6072 | treg, (int) BFD_RELOC_LO16, AT); | |
f9419b05 | 6073 | if (treg != RA) |
252b5132 RH |
6074 | { |
6075 | /* FIXME: How in the world do we deal with the possible | |
6076 | overflow here? */ | |
6077 | offset_expr.X_add_number += 4; | |
6078 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
6079 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
6080 | } | |
6081 | } | |
6082 | ||
6083 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6084 | does not become a variant frag. */ | |
6085 | frag_wane (frag_now); | |
6086 | frag_new (0); | |
6087 | ||
6088 | break; | |
6089 | ||
6090 | case M_LI_DD: | |
ca4e0257 RS |
6091 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6092 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6093 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6094 | the value and the low order 32 bits are either zero or in | |
6095 | OFFSET_EXPR. */ | |
252b5132 RH |
6096 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6097 | { | |
ca4e0257 RS |
6098 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
6099 | if (HAVE_64BIT_FPRS) | |
6100 | { | |
6101 | assert (HAVE_64BIT_GPRS); | |
6102 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6103 | "dmtc1", "t,S", AT, treg); | |
6104 | } | |
252b5132 RH |
6105 | else |
6106 | { | |
6107 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6108 | "mtc1", "t,G", AT, treg + 1); | |
6109 | if (offset_expr.X_op == O_absent) | |
6110 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6111 | "mtc1", "t,G", 0, treg); | |
6112 | else | |
6113 | { | |
6114 | assert (offset_expr.X_op == O_constant); | |
6115 | load_register (&icnt, AT, &offset_expr, 0); | |
6116 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6117 | "mtc1", "t,G", AT, treg); | |
6118 | } | |
6119 | } | |
6120 | break; | |
6121 | } | |
6122 | ||
6123 | assert (offset_expr.X_op == O_symbol | |
6124 | && offset_expr.X_add_number == 0); | |
6125 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6126 | if (strcmp (s, ".lit8") == 0) | |
6127 | { | |
e7af610e | 6128 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6129 | { |
6130 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
c9914766 TS |
6131 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, |
6132 | mips_gp_register); | |
252b5132 RH |
6133 | return; |
6134 | } | |
c9914766 | 6135 | breg = mips_gp_register; |
252b5132 RH |
6136 | r = BFD_RELOC_MIPS_LITERAL; |
6137 | goto dob; | |
6138 | } | |
6139 | else | |
6140 | { | |
6141 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6142 | if (mips_pic == SVR4_PIC) | |
6143 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6144 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6145 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6146 | mips_gp_register); | |
252b5132 RH |
6147 | else |
6148 | { | |
6149 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6150 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6151 | } |
bdaaa2e1 | 6152 | |
e7af610e | 6153 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6154 | { |
6155 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
6156 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
6157 | ||
6158 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6159 | that this does not become a variant frag. */ | |
6160 | frag_wane (frag_now); | |
6161 | frag_new (0); | |
6162 | ||
6163 | break; | |
6164 | } | |
6165 | breg = AT; | |
6166 | r = BFD_RELOC_LO16; | |
6167 | goto dob; | |
6168 | } | |
6169 | ||
6170 | case M_L_DOB: | |
ec68c924 | 6171 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6172 | { |
6173 | as_bad (_("opcode not supported on this processor")); | |
6174 | return; | |
6175 | } | |
6176 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6177 | to adjust when loading from memory. */ | |
6178 | r = BFD_RELOC_LO16; | |
6179 | dob: | |
e7af610e | 6180 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6181 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6182 | target_big_endian ? treg + 1 : treg, | |
6183 | (int) r, breg); | |
6184 | /* FIXME: A possible overflow which I don't know how to deal | |
6185 | with. */ | |
6186 | offset_expr.X_add_number += 4; | |
6187 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
6188 | target_big_endian ? treg : treg + 1, | |
6189 | (int) r, breg); | |
6190 | ||
6191 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6192 | does not become a variant frag. */ | |
6193 | frag_wane (frag_now); | |
6194 | frag_new (0); | |
6195 | ||
6196 | if (breg != AT) | |
6197 | return; | |
6198 | break; | |
6199 | ||
6200 | case M_L_DAB: | |
6201 | /* | |
6202 | * The MIPS assembler seems to check for X_add_number not | |
6203 | * being double aligned and generating: | |
6204 | * lui at,%hi(foo+1) | |
6205 | * addu at,at,v1 | |
6206 | * addiu at,at,%lo(foo+1) | |
6207 | * lwc1 f2,0(at) | |
6208 | * lwc1 f3,4(at) | |
6209 | * But, the resulting address is the same after relocation so why | |
6210 | * generate the extra instruction? | |
6211 | */ | |
ec68c924 | 6212 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6213 | { |
6214 | as_bad (_("opcode not supported on this processor")); | |
6215 | return; | |
6216 | } | |
bdaaa2e1 | 6217 | /* Itbl support may require additional care here. */ |
252b5132 | 6218 | coproc = 1; |
e7af610e | 6219 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6220 | { |
6221 | s = "ldc1"; | |
6222 | goto ld; | |
6223 | } | |
6224 | ||
6225 | s = "lwc1"; | |
6226 | fmt = "T,o(b)"; | |
6227 | goto ldd_std; | |
6228 | ||
6229 | case M_S_DAB: | |
ec68c924 | 6230 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6231 | { |
6232 | as_bad (_("opcode not supported on this processor")); | |
6233 | return; | |
6234 | } | |
6235 | ||
e7af610e | 6236 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6237 | { |
6238 | s = "sdc1"; | |
6239 | goto st; | |
6240 | } | |
6241 | ||
6242 | s = "swc1"; | |
6243 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6244 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6245 | coproc = 1; |
6246 | goto ldd_std; | |
6247 | ||
6248 | case M_LD_AB: | |
ca4e0257 | 6249 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6250 | { |
6251 | s = "ld"; | |
6252 | goto ld; | |
6253 | } | |
6254 | ||
6255 | s = "lw"; | |
6256 | fmt = "t,o(b)"; | |
6257 | goto ldd_std; | |
6258 | ||
6259 | case M_SD_AB: | |
ca4e0257 | 6260 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6261 | { |
6262 | s = "sd"; | |
6263 | goto st; | |
6264 | } | |
6265 | ||
6266 | s = "sw"; | |
6267 | fmt = "t,o(b)"; | |
6268 | ||
6269 | ldd_std: | |
afdbd6d0 CD |
6270 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6271 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6272 | This is not currently done by the compiler, and assembly coders | |
6273 | writing embedded-pic code can cope. */ | |
6274 | ||
252b5132 RH |
6275 | if (offset_expr.X_op != O_symbol |
6276 | && offset_expr.X_op != O_constant) | |
6277 | { | |
6278 | as_bad (_("expression too complex")); | |
6279 | offset_expr.X_op = O_constant; | |
6280 | } | |
6281 | ||
6282 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6283 | to adjust when loading from memory. We set coproc if we must | |
6284 | load $fn+1 first. */ | |
bdaaa2e1 | 6285 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6286 | if (! target_big_endian) |
6287 | coproc = 0; | |
6288 | ||
6289 | if (mips_pic == NO_PIC | |
6290 | || offset_expr.X_op == O_constant) | |
6291 | { | |
f9419b05 TS |
6292 | char *p; |
6293 | ||
252b5132 | 6294 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6295 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6296 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6297 | If we have a base register, we use this |
6298 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6299 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6300 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6301 | If this is not a GP relative symbol, we want |
6302 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6303 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6304 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6305 | If there is a base register, we add it to $at after the | |
6306 | lui instruction. If there is a constant, we always use | |
6307 | the last case. */ | |
e7d556df | 6308 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6309 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6310 | { | |
6311 | p = NULL; | |
6312 | used_at = 1; | |
6313 | } | |
6314 | else | |
6315 | { | |
6316 | int off; | |
6317 | ||
6318 | if (breg == 0) | |
6319 | { | |
6320 | frag_grow (28); | |
c9914766 | 6321 | tempreg = mips_gp_register; |
252b5132 RH |
6322 | off = 0; |
6323 | used_at = 0; | |
6324 | } | |
6325 | else | |
6326 | { | |
6327 | frag_grow (36); | |
6328 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6329 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6330 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6331 | tempreg = AT; |
6332 | off = 4; | |
6333 | used_at = 1; | |
6334 | } | |
6335 | ||
beae10d5 | 6336 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6337 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6338 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6339 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6340 | offset_expr.X_add_number += 4; |
6341 | ||
6342 | /* Set mips_optimize to 2 to avoid inserting an | |
6343 | undesired nop. */ | |
6344 | hold_mips_optimize = mips_optimize; | |
6345 | mips_optimize = 2; | |
beae10d5 | 6346 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6347 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6348 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6349 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6350 | mips_optimize = hold_mips_optimize; |
6351 | ||
6352 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6353 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6354 | used_at && mips_opts.noat), | |
956cd1d6 | 6355 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6356 | |
6357 | /* We just generated two relocs. When tc_gen_reloc | |
6358 | handles this case, it will skip the first reloc and | |
6359 | handle the second. The second reloc already has an | |
6360 | extra addend of 4, which we added above. We must | |
6361 | subtract it out, and then subtract another 4 to make | |
6362 | the first reloc come out right. The second reloc | |
6363 | will come out right because we are going to add 4 to | |
6364 | offset_expr when we build its instruction below. | |
6365 | ||
6366 | If we have a symbol, then we don't want to include | |
6367 | the offset, because it will wind up being included | |
6368 | when we generate the reloc. */ | |
6369 | ||
6370 | if (offset_expr.X_op == O_constant) | |
6371 | offset_expr.X_add_number -= 8; | |
6372 | else | |
6373 | { | |
6374 | offset_expr.X_add_number = -4; | |
6375 | offset_expr.X_op = O_constant; | |
6376 | } | |
6377 | } | |
6378 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6379 | if (p != NULL) | |
6380 | p += 4; | |
6381 | if (breg != 0) | |
6382 | { | |
6383 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6384 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6385 | "d,v,t", AT, breg, AT); |
6386 | if (p != NULL) | |
6387 | p += 4; | |
6388 | } | |
beae10d5 | 6389 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6390 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6391 | coproc ? treg + 1 : treg, | |
6392 | (int) BFD_RELOC_LO16, AT); | |
6393 | if (p != NULL) | |
6394 | p += 4; | |
6395 | /* FIXME: How do we handle overflow here? */ | |
6396 | offset_expr.X_add_number += 4; | |
beae10d5 | 6397 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6398 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6399 | coproc ? treg : treg + 1, | |
6400 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6401 | } |
252b5132 RH |
6402 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6403 | { | |
6404 | int off; | |
6405 | ||
6406 | /* If this is a reference to an external symbol, we want | |
6407 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6408 | nop | |
6409 | <op> $treg,0($at) | |
6410 | <op> $treg+1,4($at) | |
6411 | Otherwise we want | |
6412 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6413 | nop | |
6414 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6415 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6416 | If there is a base register we add it to $at before the | |
6417 | lwc1 instructions. If there is a constant we include it | |
6418 | in the lwc1 instructions. */ | |
6419 | used_at = 1; | |
6420 | expr1.X_add_number = offset_expr.X_add_number; | |
6421 | offset_expr.X_add_number = 0; | |
6422 | if (expr1.X_add_number < -0x8000 | |
6423 | || expr1.X_add_number >= 0x8000 - 4) | |
6424 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6425 | if (breg == 0) | |
6426 | off = 0; | |
6427 | else | |
6428 | off = 4; | |
6429 | frag_grow (24 + off); | |
6430 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
6431 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT, |
6432 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6433 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
6434 | if (breg != 0) | |
6435 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6436 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6437 | "d,v,t", AT, breg, AT); |
beae10d5 | 6438 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6439 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6440 | coproc ? treg + 1 : treg, | |
6441 | (int) BFD_RELOC_LO16, AT); | |
6442 | expr1.X_add_number += 4; | |
6443 | ||
6444 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6445 | nop. */ | |
6446 | hold_mips_optimize = mips_optimize; | |
6447 | mips_optimize = 2; | |
beae10d5 | 6448 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6449 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6450 | coproc ? treg : treg + 1, | |
6451 | (int) BFD_RELOC_LO16, AT); | |
6452 | mips_optimize = hold_mips_optimize; | |
6453 | ||
6454 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6455 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6456 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6457 | } |
6458 | else if (mips_pic == SVR4_PIC) | |
6459 | { | |
6460 | int gpdel, off; | |
f9419b05 | 6461 | char *p; |
252b5132 RH |
6462 | |
6463 | /* If this is a reference to an external symbol, we want | |
6464 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6465 | addu $at,$at,$gp | |
6466 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6467 | nop | |
6468 | <op> $treg,0($at) | |
6469 | <op> $treg+1,4($at) | |
6470 | Otherwise we want | |
6471 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6472 | nop | |
6473 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6474 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6475 | If there is a base register we add it to $at before the | |
6476 | lwc1 instructions. If there is a constant we include it | |
6477 | in the lwc1 instructions. */ | |
6478 | used_at = 1; | |
6479 | expr1.X_add_number = offset_expr.X_add_number; | |
6480 | offset_expr.X_add_number = 0; | |
6481 | if (expr1.X_add_number < -0x8000 | |
6482 | || expr1.X_add_number >= 0x8000 - 4) | |
6483 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6484 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6485 | gpdel = 4; |
6486 | else | |
6487 | gpdel = 0; | |
6488 | if (breg == 0) | |
6489 | off = 0; | |
6490 | else | |
6491 | off = 4; | |
6492 | frag_grow (56); | |
6493 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6494 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6495 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6496 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6497 | "d,v,t", AT, AT, mips_gp_register); |
252b5132 | 6498 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 6499 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6500 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
6501 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6502 | if (breg != 0) | |
6503 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6504 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6505 | "d,v,t", AT, breg, AT); |
beae10d5 | 6506 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6507 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6508 | coproc ? treg + 1 : treg, | |
6509 | (int) BFD_RELOC_LO16, AT); | |
6510 | expr1.X_add_number += 4; | |
6511 | ||
6512 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6513 | nop. */ | |
6514 | hold_mips_optimize = mips_optimize; | |
6515 | mips_optimize = 2; | |
beae10d5 | 6516 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6517 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6518 | coproc ? treg : treg + 1, | |
6519 | (int) BFD_RELOC_LO16, AT); | |
6520 | mips_optimize = hold_mips_optimize; | |
6521 | expr1.X_add_number -= 4; | |
6522 | ||
6523 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6524 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6525 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6526 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6527 | if (gpdel > 0) |
6528 | { | |
6529 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6530 | p += 4; | |
6531 | } | |
6532 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6533 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6534 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6535 | mips_gp_register); | |
252b5132 RH |
6536 | p += 4; |
6537 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6538 | p += 4; | |
6539 | if (breg != 0) | |
6540 | { | |
6541 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6542 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6543 | "d,v,t", AT, breg, AT); |
6544 | p += 4; | |
6545 | } | |
beae10d5 | 6546 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6547 | macro_build (p, &icnt, &expr1, s, fmt, |
6548 | coproc ? treg + 1 : treg, | |
6549 | (int) BFD_RELOC_LO16, AT); | |
6550 | p += 4; | |
6551 | expr1.X_add_number += 4; | |
6552 | ||
6553 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6554 | nop. */ | |
6555 | hold_mips_optimize = mips_optimize; | |
6556 | mips_optimize = 2; | |
beae10d5 | 6557 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6558 | macro_build (p, &icnt, &expr1, s, fmt, |
6559 | coproc ? treg : treg + 1, | |
6560 | (int) BFD_RELOC_LO16, AT); | |
6561 | mips_optimize = hold_mips_optimize; | |
6562 | } | |
6563 | else if (mips_pic == EMBEDDED_PIC) | |
6564 | { | |
6565 | /* If there is no base register, we use | |
cdf6fd85 TS |
6566 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6567 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6568 | If we have a base register, we use |
6569 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6570 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6571 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6572 | */ |
6573 | if (breg == 0) | |
6574 | { | |
c9914766 | 6575 | tempreg = mips_gp_register; |
252b5132 RH |
6576 | used_at = 0; |
6577 | } | |
6578 | else | |
6579 | { | |
6580 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6581 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6582 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6583 | tempreg = AT; |
6584 | used_at = 1; | |
6585 | } | |
6586 | ||
beae10d5 | 6587 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6588 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6589 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6590 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6591 | offset_expr.X_add_number += 4; |
beae10d5 | 6592 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6593 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6594 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6595 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6596 | } |
6597 | else | |
6598 | abort (); | |
6599 | ||
6600 | if (! used_at) | |
6601 | return; | |
6602 | ||
6603 | break; | |
6604 | ||
6605 | case M_LD_OB: | |
6606 | s = "lw"; | |
6607 | goto sd_ob; | |
6608 | case M_SD_OB: | |
6609 | s = "sw"; | |
6610 | sd_ob: | |
ca4e0257 | 6611 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
6612 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6613 | (int) BFD_RELOC_LO16, breg); | |
6614 | offset_expr.X_add_number += 4; | |
6615 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
6616 | (int) BFD_RELOC_LO16, breg); | |
6617 | return; | |
6618 | ||
6619 | /* New code added to support COPZ instructions. | |
6620 | This code builds table entries out of the macros in mip_opcodes. | |
6621 | R4000 uses interlocks to handle coproc delays. | |
6622 | Other chips (like the R3000) require nops to be inserted for delays. | |
6623 | ||
f72c8c98 | 6624 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6625 | In order to fill delay slots for non-interlocked chips, |
6626 | we must have a way to specify delays based on the coprocessor. | |
6627 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6628 | What are the side-effects of the cop instruction? | |
6629 | What cache support might we have and what are its effects? | |
6630 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6631 | What registers are read/set/modified? |
252b5132 RH |
6632 | |
6633 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6634 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6635 | |
6636 | case M_COP0: | |
6637 | s = "c0"; | |
6638 | goto copz; | |
6639 | case M_COP1: | |
6640 | s = "c1"; | |
6641 | goto copz; | |
6642 | case M_COP2: | |
6643 | s = "c2"; | |
6644 | goto copz; | |
6645 | case M_COP3: | |
6646 | s = "c3"; | |
6647 | copz: | |
6648 | /* For now we just do C (same as Cz). The parameter will be | |
6649 | stored in insn_opcode by mips_ip. */ | |
6650 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6651 | ip->insn_opcode); | |
6652 | return; | |
6653 | ||
ea1fb5dc RS |
6654 | case M_MOVE: |
6655 | move_register (&icnt, dreg, sreg); | |
6656 | return; | |
6657 | ||
252b5132 RH |
6658 | #ifdef LOSING_COMPILER |
6659 | default: | |
6660 | /* Try and see if this is a new itbl instruction. | |
6661 | This code builds table entries out of the macros in mip_opcodes. | |
6662 | FIXME: For now we just assemble the expression and pass it's | |
6663 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6664 | We may want to have the assembler assemble this value, |
252b5132 RH |
6665 | so that we gain the assembler's knowledge of delay slots, |
6666 | symbols, etc. | |
6667 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6668 | if (itbl_have_entries |
252b5132 | 6669 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6670 | { |
252b5132 RH |
6671 | s = ip->insn_mo->name; |
6672 | s2 = "cop3"; | |
6673 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
6674 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
6675 | return; | |
beae10d5 | 6676 | } |
252b5132 RH |
6677 | macro2 (ip); |
6678 | return; | |
6679 | } | |
6680 | if (mips_opts.noat) | |
6681 | as_warn (_("Macro used $at after \".set noat\"")); | |
6682 | } | |
bdaaa2e1 | 6683 | |
252b5132 RH |
6684 | static void |
6685 | macro2 (ip) | |
6686 | struct mips_cl_insn *ip; | |
6687 | { | |
6688 | register int treg, sreg, dreg, breg; | |
6689 | int tempreg; | |
6690 | int mask; | |
6691 | int icnt = 0; | |
6692 | int used_at; | |
6693 | expressionS expr1; | |
6694 | const char *s; | |
6695 | const char *s2; | |
6696 | const char *fmt; | |
6697 | int likely = 0; | |
6698 | int dbl = 0; | |
6699 | int coproc = 0; | |
6700 | int lr = 0; | |
6701 | int imm = 0; | |
6702 | int off; | |
6703 | offsetT maxnum; | |
6704 | bfd_reloc_code_real_type r; | |
6705 | char *p; | |
bdaaa2e1 | 6706 | |
252b5132 RH |
6707 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6708 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6709 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6710 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6711 | |
252b5132 RH |
6712 | expr1.X_op = O_constant; |
6713 | expr1.X_op_symbol = NULL; | |
6714 | expr1.X_add_symbol = NULL; | |
6715 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6716 | |
252b5132 RH |
6717 | switch (mask) |
6718 | { | |
6719 | #endif /* LOSING_COMPILER */ | |
6720 | ||
6721 | case M_DMUL: | |
6722 | dbl = 1; | |
6723 | case M_MUL: | |
2396cfb9 TS |
6724 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6725 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); | |
6726 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6727 | dreg); | |
252b5132 RH |
6728 | return; |
6729 | ||
6730 | case M_DMUL_I: | |
6731 | dbl = 1; | |
6732 | case M_MUL_I: | |
6733 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6734 | not trying to be that fancy. GCC should do this for us | |
6735 | anyway. */ | |
6736 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6737 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6738 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
2396cfb9 TS |
6739 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6740 | dreg); | |
252b5132 RH |
6741 | break; |
6742 | ||
6743 | case M_DMULO_I: | |
6744 | dbl = 1; | |
6745 | case M_MULO_I: | |
6746 | imm = 1; | |
6747 | goto do_mulo; | |
6748 | ||
6749 | case M_DMULO: | |
6750 | dbl = 1; | |
6751 | case M_MULO: | |
6752 | do_mulo: | |
6753 | mips_emit_delays (true); | |
6754 | ++mips_opts.noreorder; | |
6755 | mips_any_noreorder = 1; | |
6756 | if (imm) | |
6757 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6758 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6759 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
2396cfb9 TS |
6760 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6761 | dreg); | |
6762 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f9419b05 | 6763 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); |
2396cfb9 TS |
6764 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6765 | AT); | |
252b5132 | 6766 | if (mips_trap) |
2396cfb9 TS |
6767 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t", |
6768 | dreg, AT); | |
252b5132 RH |
6769 | else |
6770 | { | |
6771 | expr1.X_add_number = 8; | |
2396cfb9 TS |
6772 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
6773 | AT); | |
6774 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", | |
6775 | 0); | |
6776 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6777 | "c", 6); | |
252b5132 RH |
6778 | } |
6779 | --mips_opts.noreorder; | |
2396cfb9 | 6780 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
252b5132 RH |
6781 | break; |
6782 | ||
6783 | case M_DMULOU_I: | |
6784 | dbl = 1; | |
6785 | case M_MULOU_I: | |
6786 | imm = 1; | |
6787 | goto do_mulou; | |
6788 | ||
6789 | case M_DMULOU: | |
6790 | dbl = 1; | |
6791 | case M_MULOU: | |
6792 | do_mulou: | |
6793 | mips_emit_delays (true); | |
6794 | ++mips_opts.noreorder; | |
6795 | mips_any_noreorder = 1; | |
6796 | if (imm) | |
6797 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6798 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
6799 | dbl ? "dmultu" : "multu", |
6800 | "s,t", sreg, imm ? AT : treg); | |
2396cfb9 TS |
6801 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6802 | AT); | |
6803 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6804 | dreg); | |
252b5132 | 6805 | if (mips_trap) |
2396cfb9 TS |
6806 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t", |
6807 | AT, 0); | |
252b5132 RH |
6808 | else |
6809 | { | |
6810 | expr1.X_add_number = 8; | |
6811 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
2396cfb9 TS |
6812 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
6813 | 0); | |
6814 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6815 | "c", 6); | |
252b5132 RH |
6816 | } |
6817 | --mips_opts.noreorder; | |
6818 | break; | |
6819 | ||
771c7ce4 TS |
6820 | case M_DROL: |
6821 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", | |
6822 | "d,v,t", AT, 0, treg); | |
6823 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
6824 | "d,t,s", AT, sreg, AT); | |
6825 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
6826 | "d,t,s", dreg, sreg, treg); | |
6827 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6828 | "d,v,t", dreg, dreg, AT); | |
6829 | break; | |
6830 | ||
252b5132 | 6831 | case M_ROL: |
2396cfb9 TS |
6832 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6833 | "d,v,t", AT, 0, treg); | |
6834 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6835 | "d,t,s", AT, sreg, AT); | |
6836 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6837 | "d,t,s", dreg, sreg, treg); | |
6838 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6839 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6840 | break; |
6841 | ||
771c7ce4 TS |
6842 | case M_DROL_I: |
6843 | { | |
6844 | unsigned int rot; | |
6845 | char *l, *r; | |
6846 | ||
6847 | if (imm_expr.X_op != O_constant) | |
6848 | as_bad (_("rotate count too large")); | |
6849 | rot = imm_expr.X_add_number & 0x3f; | |
6850 | if (! rot) | |
6851 | break; | |
6852 | l = (rot < 0x20) ? "dsll" : "dsll32"; | |
6853 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6854 | rot &= 0x1f; | |
6855 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
6856 | "d,w,<", AT, sreg, rot); | |
6857 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
6858 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6859 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6860 | "d,v,t", dreg, dreg, AT); | |
6861 | } | |
6862 | break; | |
6863 | ||
252b5132 | 6864 | case M_ROL_I: |
771c7ce4 TS |
6865 | { |
6866 | unsigned int rot; | |
6867 | ||
6868 | if (imm_expr.X_op != O_constant) | |
6869 | as_bad (_("rotate count too large")); | |
6870 | rot = imm_expr.X_add_number & 0x1f; | |
6871 | if (! rot) | |
6872 | break; | |
6873 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
6874 | "d,w,<", AT, sreg, rot); | |
6875 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6876 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6877 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6878 | "d,v,t", dreg, dreg, AT); | |
6879 | } | |
6880 | break; | |
6881 | ||
6882 | case M_DROR: | |
6883 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", | |
6884 | "d,v,t", AT, 0, treg); | |
6885 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
6886 | "d,t,s", AT, sreg, AT); | |
6887 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
6888 | "d,t,s", dreg, sreg, treg); | |
6889 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6890 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6891 | break; |
6892 | ||
6893 | case M_ROR: | |
2396cfb9 TS |
6894 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6895 | "d,v,t", AT, 0, treg); | |
6896 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6897 | "d,t,s", AT, sreg, AT); | |
6898 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6899 | "d,t,s", dreg, sreg, treg); | |
6900 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6901 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6902 | break; |
6903 | ||
771c7ce4 TS |
6904 | case M_DROR_I: |
6905 | { | |
6906 | unsigned int rot; | |
6907 | char *l, *r; | |
6908 | ||
6909 | if (imm_expr.X_op != O_constant) | |
6910 | as_bad (_("rotate count too large")); | |
6911 | rot = imm_expr.X_add_number & 0x3f; | |
6912 | if (! rot) | |
6913 | break; | |
6914 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; | |
6915 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6916 | rot &= 0x1f; | |
6917 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
6918 | "d,w,<", AT, sreg, rot); | |
6919 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
6920 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6921 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6922 | "d,v,t", dreg, dreg, AT); | |
6923 | } | |
6924 | break; | |
6925 | ||
252b5132 | 6926 | case M_ROR_I: |
771c7ce4 TS |
6927 | { |
6928 | unsigned int rot; | |
6929 | ||
6930 | if (imm_expr.X_op != O_constant) | |
6931 | as_bad (_("rotate count too large")); | |
6932 | rot = imm_expr.X_add_number & 0x1f; | |
6933 | if (! rot) | |
6934 | break; | |
6935 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6936 | "d,w,<", AT, sreg, rot); | |
6937 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
6938 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6939 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6940 | "d,v,t", dreg, dreg, AT); | |
6941 | } | |
252b5132 RH |
6942 | break; |
6943 | ||
6944 | case M_S_DOB: | |
ec68c924 | 6945 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6946 | { |
6947 | as_bad (_("opcode not supported on this processor")); | |
6948 | return; | |
6949 | } | |
e7af610e | 6950 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6951 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6952 | to adjust when storing to memory. */ | |
6953 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6954 | target_big_endian ? treg + 1 : treg, | |
6955 | (int) BFD_RELOC_LO16, breg); | |
6956 | offset_expr.X_add_number += 4; | |
6957 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6958 | target_big_endian ? treg : treg + 1, | |
6959 | (int) BFD_RELOC_LO16, breg); | |
6960 | return; | |
6961 | ||
6962 | case M_SEQ: | |
6963 | if (sreg == 0) | |
6964 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6965 | treg, (int) BFD_RELOC_LO16); | |
6966 | else if (treg == 0) | |
6967 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6968 | sreg, (int) BFD_RELOC_LO16); | |
6969 | else | |
6970 | { | |
2396cfb9 TS |
6971 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6972 | "d,v,t", dreg, sreg, treg); | |
252b5132 RH |
6973 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6974 | dreg, (int) BFD_RELOC_LO16); | |
6975 | } | |
6976 | return; | |
6977 | ||
6978 | case M_SEQ_I: | |
6979 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6980 | { | |
6981 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6982 | sreg, (int) BFD_RELOC_LO16); | |
6983 | return; | |
6984 | } | |
6985 | if (sreg == 0) | |
6986 | { | |
6987 | as_warn (_("Instruction %s: result is always false"), | |
6988 | ip->insn_mo->name); | |
ea1fb5dc | 6989 | move_register (&icnt, dreg, 0); |
252b5132 RH |
6990 | return; |
6991 | } | |
6992 | if (imm_expr.X_op == O_constant | |
6993 | && imm_expr.X_add_number >= 0 | |
6994 | && imm_expr.X_add_number < 0x10000) | |
6995 | { | |
6996 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6997 | sreg, (int) BFD_RELOC_LO16); | |
6998 | used_at = 0; | |
6999 | } | |
7000 | else if (imm_expr.X_op == O_constant | |
7001 | && imm_expr.X_add_number > -0x8000 | |
7002 | && imm_expr.X_add_number < 0) | |
7003 | { | |
7004 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7005 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7006 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7007 | "t,r,j", dreg, sreg, |
7008 | (int) BFD_RELOC_LO16); | |
7009 | used_at = 0; | |
7010 | } | |
7011 | else | |
7012 | { | |
4d34fb5f | 7013 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7014 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7015 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7016 | used_at = 1; |
7017 | } | |
7018 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
7019 | (int) BFD_RELOC_LO16); | |
7020 | if (used_at) | |
7021 | break; | |
7022 | return; | |
7023 | ||
7024 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7025 | s = "slt"; | |
7026 | goto sge; | |
7027 | case M_SGEU: | |
7028 | s = "sltu"; | |
7029 | sge: | |
2396cfb9 TS |
7030 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7031 | dreg, sreg, treg); | |
252b5132 RH |
7032 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7033 | (int) BFD_RELOC_LO16); | |
7034 | return; | |
7035 | ||
7036 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7037 | case M_SGEU_I: | |
7038 | if (imm_expr.X_op == O_constant | |
7039 | && imm_expr.X_add_number >= -0x8000 | |
7040 | && imm_expr.X_add_number < 0x8000) | |
7041 | { | |
7042 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7043 | mask == M_SGE_I ? "slti" : "sltiu", | |
7044 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7045 | used_at = 0; | |
7046 | } | |
7047 | else | |
7048 | { | |
4d34fb5f | 7049 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7050 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
7051 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, | |
7052 | AT); | |
252b5132 RH |
7053 | used_at = 1; |
7054 | } | |
7055 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
7056 | (int) BFD_RELOC_LO16); | |
7057 | if (used_at) | |
7058 | break; | |
7059 | return; | |
7060 | ||
7061 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7062 | s = "slt"; | |
7063 | goto sgt; | |
7064 | case M_SGTU: | |
7065 | s = "sltu"; | |
7066 | sgt: | |
2396cfb9 TS |
7067 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7068 | dreg, treg, sreg); | |
252b5132 RH |
7069 | return; |
7070 | ||
7071 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7072 | s = "slt"; | |
7073 | goto sgti; | |
7074 | case M_SGTU_I: | |
7075 | s = "sltu"; | |
7076 | sgti: | |
4d34fb5f | 7077 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7078 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7079 | dreg, AT, sreg); | |
252b5132 RH |
7080 | break; |
7081 | ||
2396cfb9 | 7082 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7083 | s = "slt"; |
7084 | goto sle; | |
7085 | case M_SLEU: | |
7086 | s = "sltu"; | |
7087 | sle: | |
2396cfb9 TS |
7088 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7089 | dreg, treg, sreg); | |
252b5132 RH |
7090 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7091 | (int) BFD_RELOC_LO16); | |
7092 | return; | |
7093 | ||
2396cfb9 | 7094 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7095 | s = "slt"; |
7096 | goto slei; | |
7097 | case M_SLEU_I: | |
7098 | s = "sltu"; | |
7099 | slei: | |
4d34fb5f | 7100 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7101 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
7102 | dreg, AT, sreg); | |
252b5132 RH |
7103 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
7104 | (int) BFD_RELOC_LO16); | |
7105 | break; | |
7106 | ||
7107 | case M_SLT_I: | |
7108 | if (imm_expr.X_op == O_constant | |
7109 | && imm_expr.X_add_number >= -0x8000 | |
7110 | && imm_expr.X_add_number < 0x8000) | |
7111 | { | |
7112 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
7113 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7114 | return; | |
7115 | } | |
4d34fb5f | 7116 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7117 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
7118 | dreg, sreg, AT); | |
252b5132 RH |
7119 | break; |
7120 | ||
7121 | case M_SLTU_I: | |
7122 | if (imm_expr.X_op == O_constant | |
7123 | && imm_expr.X_add_number >= -0x8000 | |
7124 | && imm_expr.X_add_number < 0x8000) | |
7125 | { | |
7126 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
7127 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7128 | return; | |
7129 | } | |
4d34fb5f | 7130 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7131 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7132 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7133 | break; |
7134 | ||
7135 | case M_SNE: | |
7136 | if (sreg == 0) | |
2396cfb9 TS |
7137 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7138 | "d,v,t", dreg, 0, treg); | |
252b5132 | 7139 | else if (treg == 0) |
2396cfb9 TS |
7140 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7141 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7142 | else |
7143 | { | |
2396cfb9 TS |
7144 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7145 | "d,v,t", dreg, sreg, treg); | |
7146 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", | |
7147 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7148 | } |
7149 | return; | |
7150 | ||
7151 | case M_SNE_I: | |
7152 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7153 | { | |
2396cfb9 TS |
7154 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7155 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7156 | return; |
7157 | } | |
7158 | if (sreg == 0) | |
7159 | { | |
7160 | as_warn (_("Instruction %s: result is always true"), | |
7161 | ip->insn_mo->name); | |
7162 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 7163 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7164 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
7165 | return; | |
7166 | } | |
7167 | if (imm_expr.X_op == O_constant | |
7168 | && imm_expr.X_add_number >= 0 | |
7169 | && imm_expr.X_add_number < 0x10000) | |
7170 | { | |
7171 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
7172 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7173 | used_at = 0; | |
7174 | } | |
7175 | else if (imm_expr.X_op == O_constant | |
7176 | && imm_expr.X_add_number > -0x8000 | |
7177 | && imm_expr.X_add_number < 0) | |
7178 | { | |
7179 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7180 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7181 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7182 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
7183 | used_at = 0; | |
7184 | } | |
7185 | else | |
7186 | { | |
4d34fb5f | 7187 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7188 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7189 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7190 | used_at = 1; |
7191 | } | |
2396cfb9 TS |
7192 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7193 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7194 | if (used_at) |
7195 | break; | |
7196 | return; | |
7197 | ||
7198 | case M_DSUB_I: | |
7199 | dbl = 1; | |
7200 | case M_SUB_I: | |
7201 | if (imm_expr.X_op == O_constant | |
7202 | && imm_expr.X_add_number > -0x8000 | |
7203 | && imm_expr.X_add_number <= 0x8000) | |
7204 | { | |
7205 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7206 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7207 | dbl ? "daddi" : "addi", | |
7208 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7209 | return; | |
7210 | } | |
7211 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7212 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7213 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7214 | break; |
7215 | ||
7216 | case M_DSUBU_I: | |
7217 | dbl = 1; | |
7218 | case M_SUBU_I: | |
7219 | if (imm_expr.X_op == O_constant | |
7220 | && imm_expr.X_add_number > -0x8000 | |
7221 | && imm_expr.X_add_number <= 0x8000) | |
7222 | { | |
7223 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7224 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7225 | dbl ? "daddiu" : "addiu", | |
7226 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7227 | return; | |
7228 | } | |
7229 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7230 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7231 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7232 | break; |
7233 | ||
7234 | case M_TEQ_I: | |
7235 | s = "teq"; | |
7236 | goto trap; | |
7237 | case M_TGE_I: | |
7238 | s = "tge"; | |
7239 | goto trap; | |
7240 | case M_TGEU_I: | |
7241 | s = "tgeu"; | |
7242 | goto trap; | |
7243 | case M_TLT_I: | |
7244 | s = "tlt"; | |
7245 | goto trap; | |
7246 | case M_TLTU_I: | |
7247 | s = "tltu"; | |
7248 | goto trap; | |
7249 | case M_TNE_I: | |
7250 | s = "tne"; | |
7251 | trap: | |
4d34fb5f | 7252 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7253 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
7254 | AT); | |
252b5132 RH |
7255 | break; |
7256 | ||
252b5132 | 7257 | case M_TRUNCWS: |
43841e91 | 7258 | case M_TRUNCWD: |
e7af610e | 7259 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7260 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7261 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7262 | ||
7263 | /* | |
7264 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7265 | * or is there a reason for it? | |
7266 | */ | |
7267 | mips_emit_delays (true); | |
7268 | ++mips_opts.noreorder; | |
7269 | mips_any_noreorder = 1; | |
2396cfb9 | 7270 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7271 | treg, RA); |
2396cfb9 | 7272 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7273 | treg, RA); |
2396cfb9 | 7274 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7275 | expr1.X_add_number = 3; |
7276 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
7277 | (int) BFD_RELOC_LO16); | |
7278 | expr1.X_add_number = 2; | |
7279 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
7280 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 7281 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7282 | AT, RA); |
2396cfb9 TS |
7283 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
7284 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 7285 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
2396cfb9 | 7286 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7287 | treg, RA); |
2396cfb9 | 7288 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7289 | --mips_opts.noreorder; |
7290 | break; | |
7291 | ||
7292 | case M_ULH: | |
7293 | s = "lb"; | |
7294 | goto ulh; | |
7295 | case M_ULHU: | |
7296 | s = "lbu"; | |
7297 | ulh: | |
7298 | if (offset_expr.X_add_number >= 0x7fff) | |
7299 | as_bad (_("operand overflow")); | |
7300 | /* avoid load delay */ | |
7301 | if (! target_big_endian) | |
f9419b05 | 7302 | ++offset_expr.X_add_number; |
252b5132 RH |
7303 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7304 | (int) BFD_RELOC_LO16, breg); | |
7305 | if (! target_big_endian) | |
f9419b05 | 7306 | --offset_expr.X_add_number; |
252b5132 | 7307 | else |
f9419b05 | 7308 | ++offset_expr.X_add_number; |
252b5132 RH |
7309 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
7310 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7311 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7312 | treg, treg, 8); | |
7313 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7314 | treg, treg, AT); | |
252b5132 RH |
7315 | break; |
7316 | ||
7317 | case M_ULD: | |
7318 | s = "ldl"; | |
7319 | s2 = "ldr"; | |
7320 | off = 7; | |
7321 | goto ulw; | |
7322 | case M_ULW: | |
7323 | s = "lwl"; | |
7324 | s2 = "lwr"; | |
7325 | off = 3; | |
7326 | ulw: | |
7327 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7328 | as_bad (_("operand overflow")); | |
7329 | if (! target_big_endian) | |
7330 | offset_expr.X_add_number += off; | |
7331 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7332 | (int) BFD_RELOC_LO16, breg); | |
7333 | if (! target_big_endian) | |
7334 | offset_expr.X_add_number -= off; | |
7335 | else | |
7336 | offset_expr.X_add_number += off; | |
7337 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7338 | (int) BFD_RELOC_LO16, breg); | |
7339 | return; | |
7340 | ||
7341 | case M_ULD_A: | |
7342 | s = "ldl"; | |
7343 | s2 = "ldr"; | |
7344 | off = 7; | |
7345 | goto ulwa; | |
7346 | case M_ULW_A: | |
7347 | s = "lwl"; | |
7348 | s2 = "lwr"; | |
7349 | off = 3; | |
7350 | ulwa: | |
d6bc6245 | 7351 | used_at = 1; |
c9914766 | 7352 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7353 | if (breg != 0) |
7354 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7355 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7356 | "d,v,t", AT, AT, breg); |
7357 | if (! target_big_endian) | |
7358 | expr1.X_add_number = off; | |
7359 | else | |
7360 | expr1.X_add_number = 0; | |
7361 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7362 | (int) BFD_RELOC_LO16, AT); | |
7363 | if (! target_big_endian) | |
7364 | expr1.X_add_number = 0; | |
7365 | else | |
7366 | expr1.X_add_number = off; | |
7367 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7368 | (int) BFD_RELOC_LO16, AT); | |
7369 | break; | |
7370 | ||
7371 | case M_ULH_A: | |
7372 | case M_ULHU_A: | |
d6bc6245 | 7373 | used_at = 1; |
c9914766 | 7374 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7375 | if (breg != 0) |
7376 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7377 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7378 | "d,v,t", AT, AT, breg); |
7379 | if (target_big_endian) | |
7380 | expr1.X_add_number = 0; | |
7381 | macro_build ((char *) NULL, &icnt, &expr1, | |
7382 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
7383 | (int) BFD_RELOC_LO16, AT); | |
7384 | if (target_big_endian) | |
7385 | expr1.X_add_number = 1; | |
7386 | else | |
7387 | expr1.X_add_number = 0; | |
7388 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7389 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7390 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7391 | treg, treg, 8); | |
7392 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7393 | treg, treg, AT); | |
252b5132 RH |
7394 | break; |
7395 | ||
7396 | case M_USH: | |
7397 | if (offset_expr.X_add_number >= 0x7fff) | |
7398 | as_bad (_("operand overflow")); | |
7399 | if (target_big_endian) | |
f9419b05 | 7400 | ++offset_expr.X_add_number; |
252b5132 RH |
7401 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
7402 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7403 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7404 | AT, treg, 8); | |
252b5132 | 7405 | if (target_big_endian) |
f9419b05 | 7406 | --offset_expr.X_add_number; |
252b5132 | 7407 | else |
f9419b05 | 7408 | ++offset_expr.X_add_number; |
252b5132 RH |
7409 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
7410 | (int) BFD_RELOC_LO16, breg); | |
7411 | break; | |
7412 | ||
7413 | case M_USD: | |
7414 | s = "sdl"; | |
7415 | s2 = "sdr"; | |
7416 | off = 7; | |
7417 | goto usw; | |
7418 | case M_USW: | |
7419 | s = "swl"; | |
7420 | s2 = "swr"; | |
7421 | off = 3; | |
7422 | usw: | |
7423 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7424 | as_bad (_("operand overflow")); | |
7425 | if (! target_big_endian) | |
7426 | offset_expr.X_add_number += off; | |
7427 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7428 | (int) BFD_RELOC_LO16, breg); | |
7429 | if (! target_big_endian) | |
7430 | offset_expr.X_add_number -= off; | |
7431 | else | |
7432 | offset_expr.X_add_number += off; | |
7433 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7434 | (int) BFD_RELOC_LO16, breg); | |
7435 | return; | |
7436 | ||
7437 | case M_USD_A: | |
7438 | s = "sdl"; | |
7439 | s2 = "sdr"; | |
7440 | off = 7; | |
7441 | goto uswa; | |
7442 | case M_USW_A: | |
7443 | s = "swl"; | |
7444 | s2 = "swr"; | |
7445 | off = 3; | |
7446 | uswa: | |
d6bc6245 | 7447 | used_at = 1; |
c9914766 | 7448 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7449 | if (breg != 0) |
7450 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7451 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7452 | "d,v,t", AT, AT, breg); |
7453 | if (! target_big_endian) | |
7454 | expr1.X_add_number = off; | |
7455 | else | |
7456 | expr1.X_add_number = 0; | |
7457 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7458 | (int) BFD_RELOC_LO16, AT); | |
7459 | if (! target_big_endian) | |
7460 | expr1.X_add_number = 0; | |
7461 | else | |
7462 | expr1.X_add_number = off; | |
7463 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7464 | (int) BFD_RELOC_LO16, AT); | |
7465 | break; | |
7466 | ||
7467 | case M_USH_A: | |
d6bc6245 | 7468 | used_at = 1; |
c9914766 | 7469 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7470 | if (breg != 0) |
7471 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7472 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7473 | "d,v,t", AT, AT, breg); |
7474 | if (! target_big_endian) | |
7475 | expr1.X_add_number = 0; | |
7476 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7477 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7478 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7479 | treg, treg, 8); | |
252b5132 RH |
7480 | if (! target_big_endian) |
7481 | expr1.X_add_number = 1; | |
7482 | else | |
7483 | expr1.X_add_number = 0; | |
7484 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7485 | (int) BFD_RELOC_LO16, AT); | |
7486 | if (! target_big_endian) | |
7487 | expr1.X_add_number = 0; | |
7488 | else | |
7489 | expr1.X_add_number = 1; | |
7490 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7491 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7492 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7493 | treg, treg, 8); | |
7494 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7495 | treg, treg, AT); | |
252b5132 RH |
7496 | break; |
7497 | ||
7498 | default: | |
7499 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7500 | are added dynamically. */ |
252b5132 RH |
7501 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7502 | break; | |
7503 | } | |
7504 | if (mips_opts.noat) | |
7505 | as_warn (_("Macro used $at after \".set noat\"")); | |
7506 | } | |
7507 | ||
7508 | /* Implement macros in mips16 mode. */ | |
7509 | ||
7510 | static void | |
7511 | mips16_macro (ip) | |
7512 | struct mips_cl_insn *ip; | |
7513 | { | |
7514 | int mask; | |
7515 | int xreg, yreg, zreg, tmp; | |
7516 | int icnt; | |
7517 | expressionS expr1; | |
7518 | int dbl; | |
7519 | const char *s, *s2, *s3; | |
7520 | ||
7521 | mask = ip->insn_mo->mask; | |
7522 | ||
7523 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7524 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7525 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7526 | ||
7527 | icnt = 0; | |
7528 | ||
7529 | expr1.X_op = O_constant; | |
7530 | expr1.X_op_symbol = NULL; | |
7531 | expr1.X_add_symbol = NULL; | |
7532 | expr1.X_add_number = 1; | |
7533 | ||
7534 | dbl = 0; | |
7535 | ||
7536 | switch (mask) | |
7537 | { | |
7538 | default: | |
7539 | internalError (); | |
7540 | ||
7541 | case M_DDIV_3: | |
7542 | dbl = 1; | |
7543 | case M_DIV_3: | |
7544 | s = "mflo"; | |
7545 | goto do_div3; | |
7546 | case M_DREM_3: | |
7547 | dbl = 1; | |
7548 | case M_REM_3: | |
7549 | s = "mfhi"; | |
7550 | do_div3: | |
7551 | mips_emit_delays (true); | |
7552 | ++mips_opts.noreorder; | |
7553 | mips_any_noreorder = 1; | |
2396cfb9 | 7554 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
7555 | dbl ? "ddiv" : "div", |
7556 | "0,x,y", xreg, yreg); | |
7557 | expr1.X_add_number = 2; | |
7558 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
7559 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
7560 | 7); | |
bdaaa2e1 | 7561 | |
252b5132 RH |
7562 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7563 | since that causes an overflow. We should do that as well, | |
7564 | but I don't see how to do the comparisons without a temporary | |
7565 | register. */ | |
7566 | --mips_opts.noreorder; | |
2396cfb9 | 7567 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
252b5132 RH |
7568 | break; |
7569 | ||
7570 | case M_DIVU_3: | |
7571 | s = "divu"; | |
7572 | s2 = "mflo"; | |
7573 | goto do_divu3; | |
7574 | case M_REMU_3: | |
7575 | s = "divu"; | |
7576 | s2 = "mfhi"; | |
7577 | goto do_divu3; | |
7578 | case M_DDIVU_3: | |
7579 | s = "ddivu"; | |
7580 | s2 = "mflo"; | |
7581 | goto do_divu3; | |
7582 | case M_DREMU_3: | |
7583 | s = "ddivu"; | |
7584 | s2 = "mfhi"; | |
7585 | do_divu3: | |
7586 | mips_emit_delays (true); | |
7587 | ++mips_opts.noreorder; | |
7588 | mips_any_noreorder = 1; | |
2396cfb9 TS |
7589 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
7590 | xreg, yreg); | |
252b5132 RH |
7591 | expr1.X_add_number = 2; |
7592 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
98d3f06f KH |
7593 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
7594 | "6", 7); | |
252b5132 | 7595 | --mips_opts.noreorder; |
2396cfb9 | 7596 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
252b5132 RH |
7597 | break; |
7598 | ||
7599 | case M_DMUL: | |
7600 | dbl = 1; | |
7601 | case M_MUL: | |
2396cfb9 | 7602 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7603 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
2396cfb9 TS |
7604 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
7605 | zreg); | |
252b5132 RH |
7606 | return; |
7607 | ||
7608 | case M_DSUBU_I: | |
7609 | dbl = 1; | |
7610 | goto do_subu; | |
7611 | case M_SUBU_I: | |
7612 | do_subu: | |
7613 | if (imm_expr.X_op != O_constant) | |
7614 | as_bad (_("Unsupported large constant")); | |
7615 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7616 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 7617 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7618 | break; |
7619 | ||
7620 | case M_SUBU_I_2: | |
7621 | if (imm_expr.X_op != O_constant) | |
7622 | as_bad (_("Unsupported large constant")); | |
7623 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7624 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
7625 | "x,k", xreg); | |
7626 | break; | |
7627 | ||
7628 | case M_DSUBU_I_2: | |
7629 | if (imm_expr.X_op != O_constant) | |
7630 | as_bad (_("Unsupported large constant")); | |
7631 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7632 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
7633 | "y,j", yreg); | |
7634 | break; | |
7635 | ||
7636 | case M_BEQ: | |
7637 | s = "cmp"; | |
7638 | s2 = "bteqz"; | |
7639 | goto do_branch; | |
7640 | case M_BNE: | |
7641 | s = "cmp"; | |
7642 | s2 = "btnez"; | |
7643 | goto do_branch; | |
7644 | case M_BLT: | |
7645 | s = "slt"; | |
7646 | s2 = "btnez"; | |
7647 | goto do_branch; | |
7648 | case M_BLTU: | |
7649 | s = "sltu"; | |
7650 | s2 = "btnez"; | |
7651 | goto do_branch; | |
7652 | case M_BLE: | |
7653 | s = "slt"; | |
7654 | s2 = "bteqz"; | |
7655 | goto do_reverse_branch; | |
7656 | case M_BLEU: | |
7657 | s = "sltu"; | |
7658 | s2 = "bteqz"; | |
7659 | goto do_reverse_branch; | |
7660 | case M_BGE: | |
7661 | s = "slt"; | |
7662 | s2 = "bteqz"; | |
7663 | goto do_branch; | |
7664 | case M_BGEU: | |
7665 | s = "sltu"; | |
7666 | s2 = "bteqz"; | |
7667 | goto do_branch; | |
7668 | case M_BGT: | |
7669 | s = "slt"; | |
7670 | s2 = "btnez"; | |
7671 | goto do_reverse_branch; | |
7672 | case M_BGTU: | |
7673 | s = "sltu"; | |
7674 | s2 = "btnez"; | |
7675 | ||
7676 | do_reverse_branch: | |
7677 | tmp = xreg; | |
7678 | xreg = yreg; | |
7679 | yreg = tmp; | |
7680 | ||
7681 | do_branch: | |
7682 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
7683 | xreg, yreg); | |
7684 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7685 | break; | |
7686 | ||
7687 | case M_BEQ_I: | |
7688 | s = "cmpi"; | |
7689 | s2 = "bteqz"; | |
7690 | s3 = "x,U"; | |
7691 | goto do_branch_i; | |
7692 | case M_BNE_I: | |
7693 | s = "cmpi"; | |
7694 | s2 = "btnez"; | |
7695 | s3 = "x,U"; | |
7696 | goto do_branch_i; | |
7697 | case M_BLT_I: | |
7698 | s = "slti"; | |
7699 | s2 = "btnez"; | |
7700 | s3 = "x,8"; | |
7701 | goto do_branch_i; | |
7702 | case M_BLTU_I: | |
7703 | s = "sltiu"; | |
7704 | s2 = "btnez"; | |
7705 | s3 = "x,8"; | |
7706 | goto do_branch_i; | |
7707 | case M_BLE_I: | |
7708 | s = "slti"; | |
7709 | s2 = "btnez"; | |
7710 | s3 = "x,8"; | |
7711 | goto do_addone_branch_i; | |
7712 | case M_BLEU_I: | |
7713 | s = "sltiu"; | |
7714 | s2 = "btnez"; | |
7715 | s3 = "x,8"; | |
7716 | goto do_addone_branch_i; | |
7717 | case M_BGE_I: | |
7718 | s = "slti"; | |
7719 | s2 = "bteqz"; | |
7720 | s3 = "x,8"; | |
7721 | goto do_branch_i; | |
7722 | case M_BGEU_I: | |
7723 | s = "sltiu"; | |
7724 | s2 = "bteqz"; | |
7725 | s3 = "x,8"; | |
7726 | goto do_branch_i; | |
7727 | case M_BGT_I: | |
7728 | s = "slti"; | |
7729 | s2 = "bteqz"; | |
7730 | s3 = "x,8"; | |
7731 | goto do_addone_branch_i; | |
7732 | case M_BGTU_I: | |
7733 | s = "sltiu"; | |
7734 | s2 = "bteqz"; | |
7735 | s3 = "x,8"; | |
7736 | ||
7737 | do_addone_branch_i: | |
7738 | if (imm_expr.X_op != O_constant) | |
7739 | as_bad (_("Unsupported large constant")); | |
7740 | ++imm_expr.X_add_number; | |
7741 | ||
7742 | do_branch_i: | |
7743 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7744 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7745 | break; | |
7746 | ||
7747 | case M_ABS: | |
7748 | expr1.X_add_number = 0; | |
98d3f06f | 7749 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 7750 | if (xreg != yreg) |
ea1fb5dc | 7751 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
7752 | expr1.X_add_number = 2; |
7753 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7754 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7755 | "neg", "x,w", xreg, xreg); | |
7756 | } | |
7757 | } | |
7758 | ||
7759 | /* For consistency checking, verify that all bits are specified either | |
7760 | by the match/mask part of the instruction definition, or by the | |
7761 | operand list. */ | |
7762 | static int | |
7763 | validate_mips_insn (opc) | |
7764 | const struct mips_opcode *opc; | |
7765 | { | |
7766 | const char *p = opc->args; | |
7767 | char c; | |
7768 | unsigned long used_bits = opc->mask; | |
7769 | ||
7770 | if ((used_bits & opc->match) != opc->match) | |
7771 | { | |
7772 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7773 | opc->name, opc->args); | |
7774 | return 0; | |
7775 | } | |
7776 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7777 | while (*p) | |
7778 | switch (c = *p++) | |
7779 | { | |
7780 | case ',': break; | |
7781 | case '(': break; | |
7782 | case ')': break; | |
7783 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7784 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7785 | case 'A': break; | |
4372b673 | 7786 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7787 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7788 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7789 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7790 | case 'F': break; | |
7791 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7792 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7793 | case 'I': break; |
e972090a | 7794 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
7795 | case 'L': break; |
7796 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7797 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
7798 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
7799 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7800 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7801 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7802 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7803 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
7804 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7805 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7806 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7807 | case 'f': break; | |
7808 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7809 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7810 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7811 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7812 | case 'l': break; | |
7813 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7814 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7815 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7816 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7817 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7818 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7819 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7820 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7821 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7822 | case 'x': break; | |
7823 | case 'z': break; | |
7824 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7825 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7826 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
252b5132 RH |
7827 | default: |
7828 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7829 | c, opc->name, opc->args); | |
7830 | return 0; | |
7831 | } | |
7832 | #undef USE_BITS | |
7833 | if (used_bits != 0xffffffff) | |
7834 | { | |
7835 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7836 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7837 | return 0; | |
7838 | } | |
7839 | return 1; | |
7840 | } | |
7841 | ||
7842 | /* This routine assembles an instruction into its binary format. As a | |
7843 | side effect, it sets one of the global variables imm_reloc or | |
7844 | offset_reloc to the type of relocation to do if one of the operands | |
7845 | is an address expression. */ | |
7846 | ||
7847 | static void | |
7848 | mips_ip (str, ip) | |
7849 | char *str; | |
7850 | struct mips_cl_insn *ip; | |
7851 | { | |
7852 | char *s; | |
7853 | const char *args; | |
43841e91 | 7854 | char c = 0; |
252b5132 RH |
7855 | struct mips_opcode *insn; |
7856 | char *argsStart; | |
7857 | unsigned int regno; | |
7858 | unsigned int lastregno = 0; | |
7859 | char *s_reset; | |
7860 | char save_c = 0; | |
252b5132 RH |
7861 | |
7862 | insn_error = NULL; | |
7863 | ||
7864 | /* If the instruction contains a '.', we first try to match an instruction | |
7865 | including the '.'. Then we try again without the '.'. */ | |
7866 | insn = NULL; | |
3882b010 | 7867 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7868 | continue; |
7869 | ||
7870 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7871 | the call to hash_find. Save the character we replaced just in case we | |
7872 | have to re-parse the instruction. */ | |
3882b010 | 7873 | if (ISSPACE (*s)) |
252b5132 RH |
7874 | { |
7875 | save_c = *s; | |
7876 | *s++ = '\0'; | |
7877 | } | |
bdaaa2e1 | 7878 | |
252b5132 RH |
7879 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7880 | ||
7881 | /* If we didn't find the instruction in the opcode table, try again, but | |
7882 | this time with just the instruction up to, but not including the | |
7883 | first '.'. */ | |
7884 | if (insn == NULL) | |
7885 | { | |
bdaaa2e1 | 7886 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7887 | if (save_c) |
7888 | *(--s) = save_c; | |
7889 | ||
7890 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7891 | for (s = str; |
7892 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7893 | ++s) | |
252b5132 RH |
7894 | continue; |
7895 | ||
7896 | /* If we did not find a '.', then we can quit now. */ | |
7897 | if (*s != '.') | |
7898 | { | |
7899 | insn_error = "unrecognized opcode"; | |
7900 | return; | |
7901 | } | |
7902 | ||
7903 | /* Lookup the instruction in the hash table. */ | |
7904 | *s++ = '\0'; | |
7905 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7906 | { | |
7907 | insn_error = "unrecognized opcode"; | |
7908 | return; | |
7909 | } | |
252b5132 RH |
7910 | } |
7911 | ||
7912 | argsStart = s; | |
7913 | for (;;) | |
7914 | { | |
252b5132 RH |
7915 | boolean ok; |
7916 | ||
7917 | assert (strcmp (insn->name, str) == 0); | |
7918 | ||
1f25f5d3 CD |
7919 | if (OPCODE_IS_MEMBER (insn, |
7920 | (mips_opts.isa | |
98d3f06f | 7921 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
1f25f5d3 | 7922 | mips_arch)) |
252b5132 | 7923 | ok = true; |
bdaaa2e1 | 7924 | else |
252b5132 | 7925 | ok = false; |
bdaaa2e1 | 7926 | |
252b5132 RH |
7927 | if (insn->pinfo != INSN_MACRO) |
7928 | { | |
ec68c924 | 7929 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
252b5132 RH |
7930 | ok = false; |
7931 | } | |
7932 | ||
7933 | if (! ok) | |
7934 | { | |
7935 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7936 | && strcmp (insn->name, insn[1].name) == 0) | |
7937 | { | |
7938 | ++insn; | |
7939 | continue; | |
7940 | } | |
252b5132 | 7941 | else |
beae10d5 | 7942 | { |
268f6bed L |
7943 | if (!insn_error) |
7944 | { | |
7945 | static char buf[100]; | |
7946 | sprintf (buf, | |
7947 | _("opcode not supported on this processor: %s (%s)"), | |
ec68c924 | 7948 | mips_cpu_to_str (mips_arch), |
268f6bed | 7949 | mips_isa_to_str (mips_opts.isa)); |
bdaaa2e1 | 7950 | |
268f6bed L |
7951 | insn_error = buf; |
7952 | } | |
7953 | if (save_c) | |
7954 | *(--s) = save_c; | |
2bd7f1f3 | 7955 | return; |
252b5132 | 7956 | } |
252b5132 RH |
7957 | } |
7958 | ||
7959 | ip->insn_mo = insn; | |
7960 | ip->insn_opcode = insn->match; | |
268f6bed | 7961 | insn_error = NULL; |
252b5132 RH |
7962 | for (args = insn->args;; ++args) |
7963 | { | |
ad8d3bb3 | 7964 | s += strspn (s, " \t"); |
252b5132 RH |
7965 | switch (*args) |
7966 | { | |
7967 | case '\0': /* end of args */ | |
7968 | if (*s == '\0') | |
7969 | return; | |
7970 | break; | |
7971 | ||
7972 | case ',': | |
7973 | if (*s++ == *args) | |
7974 | continue; | |
7975 | s--; | |
7976 | switch (*++args) | |
7977 | { | |
7978 | case 'r': | |
7979 | case 'v': | |
38487616 | 7980 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
7981 | continue; |
7982 | ||
7983 | case 'w': | |
38487616 TS |
7984 | ip->insn_opcode |= lastregno << OP_SH_RT; |
7985 | continue; | |
7986 | ||
252b5132 | 7987 | case 'W': |
38487616 | 7988 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
7989 | continue; |
7990 | ||
7991 | case 'V': | |
38487616 | 7992 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
7993 | continue; |
7994 | } | |
7995 | break; | |
7996 | ||
7997 | case '(': | |
7998 | /* Handle optional base register. | |
7999 | Either the base register is omitted or | |
bdaaa2e1 | 8000 | we must have a left paren. */ |
252b5132 RH |
8001 | /* This is dependent on the next operand specifier |
8002 | is a base register specification. */ | |
8003 | assert (args[1] == 'b' || args[1] == '5' | |
8004 | || args[1] == '-' || args[1] == '4'); | |
8005 | if (*s == '\0') | |
8006 | return; | |
8007 | ||
8008 | case ')': /* these must match exactly */ | |
8009 | if (*s++ == *args) | |
8010 | continue; | |
8011 | break; | |
8012 | ||
8013 | case '<': /* must be at least one digit */ | |
8014 | /* | |
8015 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8016 | * than 31 or less than 0, then the shift amount should be |
8017 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8018 | * We issue a warning and mask out all but the low 5 bits. |
8019 | */ | |
8020 | my_getExpression (&imm_expr, s); | |
8021 | check_absolute_expr (ip, &imm_expr); | |
8022 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8023 | { | |
8024 | as_warn (_("Improper shift amount (%ld)"), | |
8025 | (long) imm_expr.X_add_number); | |
38487616 | 8026 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8027 | } |
38487616 | 8028 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8029 | imm_expr.X_op = O_absent; |
8030 | s = expr_end; | |
8031 | continue; | |
8032 | ||
8033 | case '>': /* shift amount minus 32 */ | |
8034 | my_getExpression (&imm_expr, s); | |
8035 | check_absolute_expr (ip, &imm_expr); | |
8036 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8037 | || (unsigned long) imm_expr.X_add_number > 63) | |
8038 | break; | |
38487616 | 8039 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8040 | imm_expr.X_op = O_absent; |
8041 | s = expr_end; | |
8042 | continue; | |
8043 | ||
252b5132 RH |
8044 | case 'k': /* cache code */ |
8045 | case 'h': /* prefx code */ | |
8046 | my_getExpression (&imm_expr, s); | |
8047 | check_absolute_expr (ip, &imm_expr); | |
8048 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8049 | { | |
8050 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8051 | ip->insn_mo->name, | |
8052 | (unsigned long) imm_expr.X_add_number); | |
8053 | imm_expr.X_add_number &= 0x1f; | |
8054 | } | |
8055 | if (*args == 'k') | |
8056 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8057 | else | |
8058 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8059 | imm_expr.X_op = O_absent; | |
8060 | s = expr_end; | |
8061 | continue; | |
8062 | ||
8063 | case 'c': /* break code */ | |
8064 | my_getExpression (&imm_expr, s); | |
8065 | check_absolute_expr (ip, &imm_expr); | |
8066 | if ((unsigned) imm_expr.X_add_number > 1023) | |
8067 | { | |
8068 | as_warn (_("Illegal break code (%ld)"), | |
8069 | (long) imm_expr.X_add_number); | |
38487616 | 8070 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8071 | } |
38487616 | 8072 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8073 | imm_expr.X_op = O_absent; |
8074 | s = expr_end; | |
8075 | continue; | |
8076 | ||
8077 | case 'q': /* lower break code */ | |
8078 | my_getExpression (&imm_expr, s); | |
8079 | check_absolute_expr (ip, &imm_expr); | |
8080 | if ((unsigned) imm_expr.X_add_number > 1023) | |
8081 | { | |
8082 | as_warn (_("Illegal lower break code (%ld)"), | |
8083 | (long) imm_expr.X_add_number); | |
38487616 | 8084 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8085 | } |
38487616 | 8086 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8087 | imm_expr.X_op = O_absent; |
8088 | s = expr_end; | |
8089 | continue; | |
8090 | ||
4372b673 | 8091 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8092 | my_getExpression (&imm_expr, s); |
156c2f8b | 8093 | check_absolute_expr (ip, &imm_expr); |
38487616 | 8094 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20) |
4372b673 | 8095 | as_warn (_("Illegal 20-bit code (%ld)"), |
252b5132 | 8096 | (long) imm_expr.X_add_number); |
38487616 | 8097 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8098 | imm_expr.X_op = O_absent; |
8099 | s = expr_end; | |
8100 | continue; | |
8101 | ||
98d3f06f | 8102 | case 'C': /* Coprocessor code */ |
beae10d5 | 8103 | my_getExpression (&imm_expr, s); |
252b5132 | 8104 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8105 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8106 | { |
beae10d5 | 8107 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
252b5132 | 8108 | (long) imm_expr.X_add_number); |
98d3f06f | 8109 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8110 | } |
beae10d5 KH |
8111 | ip->insn_opcode |= imm_expr.X_add_number; |
8112 | imm_expr.X_op = O_absent; | |
8113 | s = expr_end; | |
8114 | continue; | |
252b5132 | 8115 | |
4372b673 NC |
8116 | case 'J': /* 19-bit wait code. */ |
8117 | my_getExpression (&imm_expr, s); | |
8118 | check_absolute_expr (ip, &imm_expr); | |
38487616 | 8119 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19) |
4372b673 NC |
8120 | as_warn (_("Illegal 19-bit code (%ld)"), |
8121 | (long) imm_expr.X_add_number); | |
38487616 | 8122 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8123 | imm_expr.X_op = O_absent; |
8124 | s = expr_end; | |
8125 | continue; | |
8126 | ||
252b5132 | 8127 | case 'P': /* Performance register */ |
beae10d5 | 8128 | my_getExpression (&imm_expr, s); |
252b5132 | 8129 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8130 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8131 | { |
38487616 | 8132 | as_warn (_("Invalid performance register (%ld)"), |
252b5132 | 8133 | (long) imm_expr.X_add_number); |
38487616 | 8134 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8135 | } |
38487616 | 8136 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8137 | imm_expr.X_op = O_absent; |
8138 | s = expr_end; | |
8139 | continue; | |
252b5132 RH |
8140 | |
8141 | case 'b': /* base register */ | |
8142 | case 'd': /* destination register */ | |
8143 | case 's': /* source register */ | |
8144 | case 't': /* target register */ | |
8145 | case 'r': /* both target and source */ | |
8146 | case 'v': /* both dest and source */ | |
8147 | case 'w': /* both dest and target */ | |
8148 | case 'E': /* coprocessor target register */ | |
8149 | case 'G': /* coprocessor destination register */ | |
8150 | case 'x': /* ignore register name */ | |
8151 | case 'z': /* must be zero register */ | |
4372b673 | 8152 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8153 | s_reset = s; |
8154 | if (s[0] == '$') | |
8155 | { | |
8156 | ||
3882b010 | 8157 | if (ISDIGIT (s[1])) |
252b5132 RH |
8158 | { |
8159 | ++s; | |
8160 | regno = 0; | |
8161 | do | |
8162 | { | |
8163 | regno *= 10; | |
8164 | regno += *s - '0'; | |
8165 | ++s; | |
8166 | } | |
3882b010 | 8167 | while (ISDIGIT (*s)); |
252b5132 RH |
8168 | if (regno > 31) |
8169 | as_bad (_("Invalid register number (%d)"), regno); | |
8170 | } | |
8171 | else if (*args == 'E' || *args == 'G') | |
8172 | goto notreg; | |
8173 | else | |
8174 | { | |
8175 | if (s[1] == 'f' && s[2] == 'p') | |
8176 | { | |
8177 | s += 3; | |
8178 | regno = FP; | |
8179 | } | |
8180 | else if (s[1] == 's' && s[2] == 'p') | |
8181 | { | |
8182 | s += 3; | |
8183 | regno = SP; | |
8184 | } | |
8185 | else if (s[1] == 'g' && s[2] == 'p') | |
8186 | { | |
8187 | s += 3; | |
8188 | regno = GP; | |
8189 | } | |
8190 | else if (s[1] == 'a' && s[2] == 't') | |
8191 | { | |
8192 | s += 3; | |
8193 | regno = AT; | |
8194 | } | |
8195 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8196 | { | |
8197 | s += 4; | |
8198 | regno = KT0; | |
8199 | } | |
8200 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8201 | { | |
8202 | s += 4; | |
8203 | regno = KT1; | |
8204 | } | |
8205 | else if (itbl_have_entries) | |
8206 | { | |
8207 | char *p, *n; | |
d7ba4a77 | 8208 | unsigned long r; |
252b5132 | 8209 | |
d7ba4a77 | 8210 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8211 | n = itbl_get_field (&p); /* n is name */ |
8212 | ||
d7ba4a77 ILT |
8213 | /* See if this is a register defined in an |
8214 | itbl entry. */ | |
8215 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8216 | { |
8217 | /* Get_field advances to the start of | |
8218 | the next field, so we need to back | |
d7ba4a77 | 8219 | rack to the end of the last field. */ |
bdaaa2e1 | 8220 | if (p) |
252b5132 | 8221 | s = p - 1; |
bdaaa2e1 | 8222 | else |
d7ba4a77 | 8223 | s = strchr (s, '\0'); |
252b5132 RH |
8224 | regno = r; |
8225 | } | |
8226 | else | |
8227 | goto notreg; | |
beae10d5 | 8228 | } |
252b5132 RH |
8229 | else |
8230 | goto notreg; | |
8231 | } | |
8232 | if (regno == AT | |
8233 | && ! mips_opts.noat | |
8234 | && *args != 'E' | |
8235 | && *args != 'G') | |
8236 | as_warn (_("Used $at without \".set noat\"")); | |
8237 | c = *args; | |
8238 | if (*s == ' ') | |
f9419b05 | 8239 | ++s; |
252b5132 RH |
8240 | if (args[1] != *s) |
8241 | { | |
8242 | if (c == 'r' || c == 'v' || c == 'w') | |
8243 | { | |
8244 | regno = lastregno; | |
8245 | s = s_reset; | |
f9419b05 | 8246 | ++args; |
252b5132 RH |
8247 | } |
8248 | } | |
8249 | /* 'z' only matches $0. */ | |
8250 | if (c == 'z' && regno != 0) | |
8251 | break; | |
8252 | ||
bdaaa2e1 KH |
8253 | /* Now that we have assembled one operand, we use the args string |
8254 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8255 | switch (c) |
8256 | { | |
8257 | case 'r': | |
8258 | case 's': | |
8259 | case 'v': | |
8260 | case 'b': | |
38487616 | 8261 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8262 | break; |
8263 | case 'd': | |
8264 | case 'G': | |
38487616 | 8265 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8266 | break; |
4372b673 | 8267 | case 'U': |
38487616 TS |
8268 | ip->insn_opcode |= regno << OP_SH_RD; |
8269 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8270 | break; |
252b5132 RH |
8271 | case 'w': |
8272 | case 't': | |
8273 | case 'E': | |
38487616 | 8274 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8275 | break; |
8276 | case 'x': | |
8277 | /* This case exists because on the r3000 trunc | |
8278 | expands into a macro which requires a gp | |
8279 | register. On the r6000 or r4000 it is | |
8280 | assembled into a single instruction which | |
8281 | ignores the register. Thus the insn version | |
8282 | is MIPS_ISA2 and uses 'x', and the macro | |
8283 | version is MIPS_ISA1 and uses 't'. */ | |
8284 | break; | |
8285 | case 'z': | |
8286 | /* This case is for the div instruction, which | |
8287 | acts differently if the destination argument | |
8288 | is $0. This only matches $0, and is checked | |
8289 | outside the switch. */ | |
8290 | break; | |
8291 | case 'D': | |
8292 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8293 | break; | |
8294 | /* What about all other operands like 'i', which | |
8295 | can be specified in the opcode table? */ | |
8296 | } | |
8297 | lastregno = regno; | |
8298 | continue; | |
8299 | } | |
8300 | notreg: | |
8301 | switch (*args++) | |
8302 | { | |
8303 | case 'r': | |
8304 | case 'v': | |
38487616 | 8305 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8306 | continue; |
8307 | case 'w': | |
38487616 | 8308 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8309 | continue; |
8310 | } | |
8311 | break; | |
8312 | ||
8313 | case 'D': /* floating point destination register */ | |
8314 | case 'S': /* floating point source register */ | |
8315 | case 'T': /* floating point target register */ | |
8316 | case 'R': /* floating point source register */ | |
8317 | case 'V': | |
8318 | case 'W': | |
8319 | s_reset = s; | |
3882b010 L |
8320 | if (s[0] == '$' && s[1] == 'f' |
8321 | && ISDIGIT (s[2])) | |
252b5132 RH |
8322 | { |
8323 | s += 2; | |
8324 | regno = 0; | |
8325 | do | |
8326 | { | |
8327 | regno *= 10; | |
8328 | regno += *s - '0'; | |
8329 | ++s; | |
8330 | } | |
3882b010 | 8331 | while (ISDIGIT (*s)); |
252b5132 RH |
8332 | |
8333 | if (regno > 31) | |
8334 | as_bad (_("Invalid float register number (%d)"), regno); | |
8335 | ||
8336 | if ((regno & 1) != 0 | |
ca4e0257 | 8337 | && HAVE_32BIT_FPRS |
252b5132 RH |
8338 | && ! (strcmp (str, "mtc1") == 0 |
8339 | || strcmp (str, "mfc1") == 0 | |
8340 | || strcmp (str, "lwc1") == 0 | |
8341 | || strcmp (str, "swc1") == 0 | |
8342 | || strcmp (str, "l.s") == 0 | |
8343 | || strcmp (str, "s.s") == 0)) | |
8344 | as_warn (_("Float register should be even, was %d"), | |
8345 | regno); | |
8346 | ||
8347 | c = *args; | |
8348 | if (*s == ' ') | |
f9419b05 | 8349 | ++s; |
252b5132 RH |
8350 | if (args[1] != *s) |
8351 | { | |
8352 | if (c == 'V' || c == 'W') | |
8353 | { | |
8354 | regno = lastregno; | |
8355 | s = s_reset; | |
f9419b05 | 8356 | ++args; |
252b5132 RH |
8357 | } |
8358 | } | |
8359 | switch (c) | |
8360 | { | |
8361 | case 'D': | |
38487616 | 8362 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8363 | break; |
8364 | case 'V': | |
8365 | case 'S': | |
38487616 | 8366 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 RH |
8367 | break; |
8368 | case 'W': | |
8369 | case 'T': | |
38487616 | 8370 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8371 | break; |
8372 | case 'R': | |
38487616 | 8373 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8374 | break; |
8375 | } | |
8376 | lastregno = regno; | |
8377 | continue; | |
8378 | } | |
8379 | ||
252b5132 RH |
8380 | switch (*args++) |
8381 | { | |
8382 | case 'V': | |
38487616 | 8383 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8384 | continue; |
8385 | case 'W': | |
38487616 | 8386 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8387 | continue; |
8388 | } | |
8389 | break; | |
8390 | ||
8391 | case 'I': | |
8392 | my_getExpression (&imm_expr, s); | |
8393 | if (imm_expr.X_op != O_big | |
8394 | && imm_expr.X_op != O_constant) | |
8395 | insn_error = _("absolute expression required"); | |
8396 | s = expr_end; | |
8397 | continue; | |
8398 | ||
8399 | case 'A': | |
8400 | my_getExpression (&offset_expr, s); | |
f6688943 | 8401 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8402 | s = expr_end; |
8403 | continue; | |
8404 | ||
8405 | case 'F': | |
8406 | case 'L': | |
8407 | case 'f': | |
8408 | case 'l': | |
8409 | { | |
8410 | int f64; | |
ca4e0257 | 8411 | int using_gprs; |
252b5132 RH |
8412 | char *save_in; |
8413 | char *err; | |
8414 | unsigned char temp[8]; | |
8415 | int len; | |
8416 | unsigned int length; | |
8417 | segT seg; | |
8418 | subsegT subseg; | |
8419 | char *p; | |
8420 | ||
8421 | /* These only appear as the last operand in an | |
8422 | instruction, and every instruction that accepts | |
8423 | them in any variant accepts them in all variants. | |
8424 | This means we don't have to worry about backing out | |
8425 | any changes if the instruction does not match. | |
8426 | ||
8427 | The difference between them is the size of the | |
8428 | floating point constant and where it goes. For 'F' | |
8429 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8430 | is 32 bits. Where the constant is placed is based | |
8431 | on how the MIPS assembler does things: | |
8432 | F -- .rdata | |
8433 | L -- .lit8 | |
8434 | f -- immediate value | |
8435 | l -- .lit4 | |
8436 | ||
8437 | The .lit4 and .lit8 sections are only used if | |
8438 | permitted by the -G argument. | |
8439 | ||
8440 | When generating embedded PIC code, we use the | |
8441 | .lit8 section but not the .lit4 section (we can do | |
8442 | .lit4 inline easily; we need to put .lit8 | |
8443 | somewhere in the data segment, and using .lit8 | |
8444 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8445 | .lit8 entries). |
8446 | ||
8447 | The code below needs to know whether the target register | |
8448 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8449 | 'F' are used with GPR-based instructions and 'l' and | |
8450 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8451 | |
8452 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8453 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8454 | |
8455 | save_in = input_line_pointer; | |
8456 | input_line_pointer = s; | |
8457 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8458 | length = len; | |
8459 | s = input_line_pointer; | |
8460 | input_line_pointer = save_in; | |
8461 | if (err != NULL && *err != '\0') | |
8462 | { | |
8463 | as_bad (_("Bad floating point constant: %s"), err); | |
8464 | memset (temp, '\0', sizeof temp); | |
8465 | length = f64 ? 8 : 4; | |
8466 | } | |
8467 | ||
156c2f8b | 8468 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8469 | |
8470 | if (*args == 'f' | |
8471 | || (*args == 'l' | |
8472 | && (! USE_GLOBAL_POINTER_OPT | |
8473 | || mips_pic == EMBEDDED_PIC | |
8474 | || g_switch_value < 4 | |
8475 | || (temp[0] == 0 && temp[1] == 0) | |
8476 | || (temp[2] == 0 && temp[3] == 0)))) | |
8477 | { | |
8478 | imm_expr.X_op = O_constant; | |
8479 | if (! target_big_endian) | |
8480 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8481 | else | |
8482 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8483 | } | |
8484 | else if (length > 4 | |
119d663a | 8485 | && ! mips_disable_float_construction |
ca4e0257 RS |
8486 | /* Constants can only be constructed in GPRs and |
8487 | copied to FPRs if the GPRs are at least as wide | |
8488 | as the FPRs. Force the constant into memory if | |
8489 | we are using 64-bit FPRs but the GPRs are only | |
8490 | 32 bits wide. */ | |
8491 | && (using_gprs | |
8492 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8493 | && ((temp[0] == 0 && temp[1] == 0) |
8494 | || (temp[2] == 0 && temp[3] == 0)) | |
8495 | && ((temp[4] == 0 && temp[5] == 0) | |
8496 | || (temp[6] == 0 && temp[7] == 0))) | |
8497 | { | |
ca4e0257 RS |
8498 | /* The value is simple enough to load with a couple of |
8499 | instructions. If using 32-bit registers, set | |
8500 | imm_expr to the high order 32 bits and offset_expr to | |
8501 | the low order 32 bits. Otherwise, set imm_expr to | |
8502 | the entire 64 bit constant. */ | |
8503 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8504 | { |
8505 | imm_expr.X_op = O_constant; | |
8506 | offset_expr.X_op = O_constant; | |
8507 | if (! target_big_endian) | |
8508 | { | |
8509 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8510 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8511 | } | |
8512 | else | |
8513 | { | |
8514 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8515 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8516 | } | |
8517 | if (offset_expr.X_add_number == 0) | |
8518 | offset_expr.X_op = O_absent; | |
8519 | } | |
8520 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8521 | { | |
8522 | imm_expr.X_op = O_constant; | |
8523 | if (! target_big_endian) | |
8524 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8525 | else | |
8526 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8527 | } | |
8528 | else | |
8529 | { | |
8530 | imm_expr.X_op = O_big; | |
8531 | imm_expr.X_add_number = 4; | |
8532 | if (! target_big_endian) | |
8533 | { | |
8534 | generic_bignum[0] = bfd_getl16 (temp); | |
8535 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8536 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8537 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8538 | } | |
8539 | else | |
8540 | { | |
8541 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8542 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8543 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8544 | generic_bignum[3] = bfd_getb16 (temp); | |
8545 | } | |
8546 | } | |
8547 | } | |
8548 | else | |
8549 | { | |
8550 | const char *newname; | |
8551 | segT new_seg; | |
8552 | ||
8553 | /* Switch to the right section. */ | |
8554 | seg = now_seg; | |
8555 | subseg = now_subseg; | |
8556 | switch (*args) | |
8557 | { | |
8558 | default: /* unused default case avoids warnings. */ | |
8559 | case 'L': | |
8560 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
8561 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
8562 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
8563 | newname = ".lit8"; |
8564 | break; | |
8565 | case 'F': | |
bb2d6cd7 GK |
8566 | if (mips_pic == EMBEDDED_PIC) |
8567 | newname = ".lit8"; | |
8568 | else | |
8569 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
8570 | break; |
8571 | case 'l': | |
8572 | assert (!USE_GLOBAL_POINTER_OPT | |
8573 | || g_switch_value >= 4); | |
8574 | newname = ".lit4"; | |
8575 | break; | |
8576 | } | |
8577 | new_seg = subseg_new (newname, (subsegT) 0); | |
8578 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8579 | bfd_set_section_flags (stdoutput, new_seg, | |
8580 | (SEC_ALLOC | |
8581 | | SEC_LOAD | |
8582 | | SEC_READONLY | |
8583 | | SEC_DATA)); | |
8584 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8585 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8586 | && strcmp (TARGET_OS, "elf") != 0) | |
8587 | record_alignment (new_seg, 4); | |
8588 | else | |
8589 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8590 | if (seg == now_seg) | |
8591 | as_bad (_("Can't use floating point insn in this section")); | |
8592 | ||
8593 | /* Set the argument to the current address in the | |
8594 | section. */ | |
8595 | offset_expr.X_op = O_symbol; | |
8596 | offset_expr.X_add_symbol = | |
8597 | symbol_new ("L0\001", now_seg, | |
8598 | (valueT) frag_now_fix (), frag_now); | |
8599 | offset_expr.X_add_number = 0; | |
8600 | ||
8601 | /* Put the floating point number into the section. */ | |
8602 | p = frag_more ((int) length); | |
8603 | memcpy (p, temp, length); | |
8604 | ||
8605 | /* Switch back to the original section. */ | |
8606 | subseg_set (seg, subseg); | |
8607 | } | |
8608 | } | |
8609 | continue; | |
8610 | ||
8611 | case 'i': /* 16 bit unsigned immediate */ | |
8612 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8613 | *imm_reloc = BFD_RELOC_LO16; |
252b5132 | 8614 | c = my_getSmallExpression (&imm_expr, s); |
fb1b3232 | 8615 | if (c != S_EX_NONE) |
252b5132 | 8616 | { |
fb1b3232 | 8617 | if (c != S_EX_LO) |
252b5132 RH |
8618 | { |
8619 | if (imm_expr.X_op == O_constant) | |
8620 | imm_expr.X_add_number = | |
8621 | (imm_expr.X_add_number >> 16) & 0xffff; | |
ad8d3bb3 | 8622 | #ifdef OBJ_ELF |
fb1b3232 | 8623 | else if (c == S_EX_HIGHEST) |
98d3f06f | 8624 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
fb1b3232 | 8625 | else if (c == S_EX_HIGHER) |
98d3f06f | 8626 | *imm_reloc = BFD_RELOC_MIPS_HIGHER; |
ad8d3bb3 TS |
8627 | else if (c == S_EX_GP_REL) |
8628 | { | |
8629 | /* This occurs in NewABI only. */ | |
8630 | c = my_getSmallExpression (&imm_expr, s); | |
8631 | if (c != S_EX_NEG) | |
8632 | as_bad (_("bad composition of relocations")); | |
8633 | else | |
8634 | { | |
8635 | c = my_getSmallExpression (&imm_expr, s); | |
8636 | if (c != S_EX_LO) | |
8637 | as_bad (_("bad composition of relocations")); | |
8638 | else | |
8639 | { | |
8640 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8641 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8642 | imm_reloc[2] = BFD_RELOC_LO16; | |
8643 | } | |
8644 | } | |
8645 | } | |
8646 | #endif | |
fb1b3232 | 8647 | else if (c == S_EX_HI) |
252b5132 | 8648 | { |
f6688943 | 8649 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8650 | imm_unmatched_hi = true; |
8651 | } | |
8652 | else | |
f6688943 | 8653 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8654 | } |
8655 | else if (imm_expr.X_op == O_constant) | |
8656 | imm_expr.X_add_number &= 0xffff; | |
8657 | } | |
8658 | if (*args == 'i') | |
8659 | { | |
fb1b3232 | 8660 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8661 | || ((imm_expr.X_add_number < 0 |
beae10d5 KH |
8662 | || imm_expr.X_add_number >= 0x10000) |
8663 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
8664 | { |
8665 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8666 | !strcmp (insn->name, insn[1].name)) | |
8667 | break; | |
2ae7e77b AH |
8668 | if (imm_expr.X_op == O_constant |
8669 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8670 | as_bad (_("16 bit expression not in range 0..65535")); |
8671 | } | |
8672 | } | |
8673 | else | |
8674 | { | |
8675 | int more; | |
8676 | offsetT max; | |
8677 | ||
8678 | /* The upper bound should be 0x8000, but | |
8679 | unfortunately the MIPS assembler accepts numbers | |
8680 | from 0x8000 to 0xffff and sign extends them, and | |
8681 | we want to be compatible. We only permit this | |
8682 | extended range for an instruction which does not | |
8683 | provide any further alternates, since those | |
8684 | alternates may handle other cases. People should | |
8685 | use the numbers they mean, rather than relying on | |
8686 | a mysterious sign extension. */ | |
8687 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8688 | strcmp (insn->name, insn[1].name) == 0); | |
8689 | if (more) | |
8690 | max = 0x8000; | |
8691 | else | |
8692 | max = 0x10000; | |
fb1b3232 | 8693 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8694 | || ((imm_expr.X_add_number < -0x8000 |
beae10d5 KH |
8695 | || imm_expr.X_add_number >= max) |
8696 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
8697 | || (more |
8698 | && imm_expr.X_add_number < 0 | |
ca4e0257 | 8699 | && HAVE_64BIT_GPRS |
252b5132 RH |
8700 | && imm_expr.X_unsigned |
8701 | && sizeof (imm_expr.X_add_number) <= 4)) | |
8702 | { | |
8703 | if (more) | |
8704 | break; | |
2ae7e77b AH |
8705 | if (imm_expr.X_op == O_constant |
8706 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8707 | as_bad (_("16 bit expression not in range -32768..32767")); |
8708 | } | |
8709 | } | |
8710 | s = expr_end; | |
8711 | continue; | |
8712 | ||
8713 | case 'o': /* 16 bit offset */ | |
8714 | c = my_getSmallExpression (&offset_expr, s); | |
8715 | ||
8716 | /* If this value won't fit into a 16 bit offset, then go | |
8717 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8718 | code pattern. */ |
fb1b3232 | 8719 | if (c == S_EX_NONE |
252b5132 RH |
8720 | && (offset_expr.X_op != O_constant |
8721 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8722 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8723 | break; |
8724 | ||
fb1b3232 | 8725 | if (c == S_EX_HI) |
252b5132 RH |
8726 | { |
8727 | if (offset_expr.X_op != O_constant) | |
8728 | break; | |
8729 | offset_expr.X_add_number = | |
8730 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8731 | } | |
f6688943 | 8732 | *offset_reloc = BFD_RELOC_LO16; |
252b5132 RH |
8733 | s = expr_end; |
8734 | continue; | |
8735 | ||
8736 | case 'p': /* pc relative offset */ | |
cb56d3d3 | 8737 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 8738 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 8739 | else |
f6688943 | 8740 | *offset_reloc = BFD_RELOC_16_PCREL; |
252b5132 RH |
8741 | my_getExpression (&offset_expr, s); |
8742 | s = expr_end; | |
8743 | continue; | |
8744 | ||
8745 | case 'u': /* upper 16 bits */ | |
8746 | c = my_getSmallExpression (&imm_expr, s); | |
f6688943 | 8747 | *imm_reloc = BFD_RELOC_LO16; |
e7d556df | 8748 | if (c != S_EX_NONE) |
252b5132 | 8749 | { |
fb1b3232 | 8750 | if (c != S_EX_LO) |
252b5132 RH |
8751 | { |
8752 | if (imm_expr.X_op == O_constant) | |
8753 | imm_expr.X_add_number = | |
8754 | (imm_expr.X_add_number >> 16) & 0xffff; | |
fb1b3232 | 8755 | else if (c == S_EX_HI) |
252b5132 | 8756 | { |
f6688943 | 8757 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8758 | imm_unmatched_hi = true; |
8759 | } | |
645dc66c TS |
8760 | #ifdef OBJ_ELF |
8761 | else if (c == S_EX_HIGHEST) | |
98d3f06f | 8762 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
ad8d3bb3 TS |
8763 | else if (c == S_EX_GP_REL) |
8764 | { | |
8765 | /* This occurs in NewABI only. */ | |
8766 | c = my_getSmallExpression (&imm_expr, s); | |
8767 | if (c != S_EX_NEG) | |
8768 | as_bad (_("bad composition of relocations")); | |
8769 | else | |
8770 | { | |
8771 | c = my_getSmallExpression (&imm_expr, s); | |
8772 | if (c != S_EX_HI) | |
8773 | as_bad (_("bad composition of relocations")); | |
8774 | else | |
8775 | { | |
8776 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8777 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8778 | imm_reloc[2] = BFD_RELOC_HI16_S; | |
8779 | } | |
8780 | } | |
8781 | } | |
8782 | #endif | |
252b5132 | 8783 | else |
f6688943 | 8784 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8785 | } |
8786 | else if (imm_expr.X_op == O_constant) | |
8787 | imm_expr.X_add_number &= 0xffff; | |
8788 | } | |
8789 | if (imm_expr.X_op == O_constant | |
8790 | && (imm_expr.X_add_number < 0 | |
8791 | || imm_expr.X_add_number >= 0x10000)) | |
8792 | as_bad (_("lui expression not in range 0..65535")); | |
8793 | s = expr_end; | |
8794 | continue; | |
8795 | ||
8796 | case 'a': /* 26 bit address */ | |
8797 | my_getExpression (&offset_expr, s); | |
8798 | s = expr_end; | |
f6688943 | 8799 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8800 | continue; |
8801 | ||
8802 | case 'N': /* 3 bit branch condition code */ | |
8803 | case 'M': /* 3 bit compare condition code */ | |
8804 | if (strncmp (s, "$fcc", 4) != 0) | |
8805 | break; | |
8806 | s += 4; | |
8807 | regno = 0; | |
8808 | do | |
8809 | { | |
8810 | regno *= 10; | |
8811 | regno += *s - '0'; | |
8812 | ++s; | |
8813 | } | |
3882b010 | 8814 | while (ISDIGIT (*s)); |
252b5132 RH |
8815 | if (regno > 7) |
8816 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
8817 | if (*args == 'N') | |
8818 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8819 | else | |
8820 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 8821 | continue; |
252b5132 | 8822 | |
156c2f8b NC |
8823 | case 'H': |
8824 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8825 | s += 2; | |
3882b010 | 8826 | if (ISDIGIT (*s)) |
156c2f8b NC |
8827 | { |
8828 | c = 0; | |
8829 | do | |
8830 | { | |
8831 | c *= 10; | |
8832 | c += *s - '0'; | |
8833 | ++s; | |
8834 | } | |
3882b010 | 8835 | while (ISDIGIT (*s)); |
156c2f8b NC |
8836 | } |
8837 | else | |
8838 | c = 8; /* Invalid sel value. */ | |
8839 | ||
8840 | if (c > 7) | |
8841 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8842 | ip->insn_opcode |= c; | |
8843 | continue; | |
8844 | ||
252b5132 RH |
8845 | default: |
8846 | as_bad (_("bad char = '%c'\n"), *args); | |
8847 | internalError (); | |
8848 | } | |
8849 | break; | |
8850 | } | |
8851 | /* Args don't match. */ | |
8852 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8853 | !strcmp (insn->name, insn[1].name)) | |
8854 | { | |
8855 | ++insn; | |
8856 | s = argsStart; | |
268f6bed | 8857 | insn_error = _("illegal operands"); |
252b5132 RH |
8858 | continue; |
8859 | } | |
268f6bed L |
8860 | if (save_c) |
8861 | *(--s) = save_c; | |
252b5132 RH |
8862 | insn_error = _("illegal operands"); |
8863 | return; | |
8864 | } | |
8865 | } | |
8866 | ||
8867 | /* This routine assembles an instruction into its binary format when | |
8868 | assembling for the mips16. As a side effect, it sets one of the | |
8869 | global variables imm_reloc or offset_reloc to the type of | |
8870 | relocation to do if one of the operands is an address expression. | |
8871 | It also sets mips16_small and mips16_ext if the user explicitly | |
8872 | requested a small or extended instruction. */ | |
8873 | ||
8874 | static void | |
8875 | mips16_ip (str, ip) | |
8876 | char *str; | |
8877 | struct mips_cl_insn *ip; | |
8878 | { | |
8879 | char *s; | |
8880 | const char *args; | |
8881 | struct mips_opcode *insn; | |
8882 | char *argsstart; | |
8883 | unsigned int regno; | |
8884 | unsigned int lastregno = 0; | |
8885 | char *s_reset; | |
8886 | ||
8887 | insn_error = NULL; | |
8888 | ||
8889 | mips16_small = false; | |
8890 | mips16_ext = false; | |
8891 | ||
3882b010 | 8892 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
8893 | ; |
8894 | switch (*s) | |
8895 | { | |
8896 | case '\0': | |
8897 | break; | |
8898 | ||
8899 | case ' ': | |
8900 | *s++ = '\0'; | |
8901 | break; | |
8902 | ||
8903 | case '.': | |
8904 | if (s[1] == 't' && s[2] == ' ') | |
8905 | { | |
8906 | *s = '\0'; | |
8907 | mips16_small = true; | |
8908 | s += 3; | |
8909 | break; | |
8910 | } | |
8911 | else if (s[1] == 'e' && s[2] == ' ') | |
8912 | { | |
8913 | *s = '\0'; | |
8914 | mips16_ext = true; | |
8915 | s += 3; | |
8916 | break; | |
8917 | } | |
8918 | /* Fall through. */ | |
8919 | default: | |
8920 | insn_error = _("unknown opcode"); | |
8921 | return; | |
8922 | } | |
8923 | ||
8924 | if (mips_opts.noautoextend && ! mips16_ext) | |
8925 | mips16_small = true; | |
8926 | ||
8927 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
8928 | { | |
8929 | insn_error = _("unrecognized opcode"); | |
8930 | return; | |
8931 | } | |
8932 | ||
8933 | argsstart = s; | |
8934 | for (;;) | |
8935 | { | |
8936 | assert (strcmp (insn->name, str) == 0); | |
8937 | ||
8938 | ip->insn_mo = insn; | |
8939 | ip->insn_opcode = insn->match; | |
8940 | ip->use_extend = false; | |
8941 | imm_expr.X_op = O_absent; | |
f6688943 TS |
8942 | imm_reloc[0] = BFD_RELOC_UNUSED; |
8943 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
8944 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 8945 | offset_expr.X_op = O_absent; |
f6688943 TS |
8946 | offset_reloc[0] = BFD_RELOC_UNUSED; |
8947 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8948 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
8949 | for (args = insn->args; 1; ++args) |
8950 | { | |
8951 | int c; | |
8952 | ||
8953 | if (*s == ' ') | |
8954 | ++s; | |
8955 | ||
8956 | /* In this switch statement we call break if we did not find | |
8957 | a match, continue if we did find a match, or return if we | |
8958 | are done. */ | |
8959 | ||
8960 | c = *args; | |
8961 | switch (c) | |
8962 | { | |
8963 | case '\0': | |
8964 | if (*s == '\0') | |
8965 | { | |
8966 | /* Stuff the immediate value in now, if we can. */ | |
8967 | if (imm_expr.X_op == O_constant | |
f6688943 | 8968 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
8969 | && insn->pinfo != INSN_MACRO) |
8970 | { | |
c4e7957c | 8971 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
252b5132 RH |
8972 | imm_expr.X_add_number, true, mips16_small, |
8973 | mips16_ext, &ip->insn_opcode, | |
8974 | &ip->use_extend, &ip->extend); | |
8975 | imm_expr.X_op = O_absent; | |
f6688943 | 8976 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
8977 | } |
8978 | ||
8979 | return; | |
8980 | } | |
8981 | break; | |
8982 | ||
8983 | case ',': | |
8984 | if (*s++ == c) | |
8985 | continue; | |
8986 | s--; | |
8987 | switch (*++args) | |
8988 | { | |
8989 | case 'v': | |
8990 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8991 | continue; | |
8992 | case 'w': | |
8993 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8994 | continue; | |
8995 | } | |
8996 | break; | |
8997 | ||
8998 | case '(': | |
8999 | case ')': | |
9000 | if (*s++ == c) | |
9001 | continue; | |
9002 | break; | |
9003 | ||
9004 | case 'v': | |
9005 | case 'w': | |
9006 | if (s[0] != '$') | |
9007 | { | |
9008 | if (c == 'v') | |
9009 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9010 | else | |
9011 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9012 | ++args; | |
9013 | continue; | |
9014 | } | |
9015 | /* Fall through. */ | |
9016 | case 'x': | |
9017 | case 'y': | |
9018 | case 'z': | |
9019 | case 'Z': | |
9020 | case '0': | |
9021 | case 'S': | |
9022 | case 'R': | |
9023 | case 'X': | |
9024 | case 'Y': | |
9025 | if (s[0] != '$') | |
9026 | break; | |
9027 | s_reset = s; | |
3882b010 | 9028 | if (ISDIGIT (s[1])) |
252b5132 RH |
9029 | { |
9030 | ++s; | |
9031 | regno = 0; | |
9032 | do | |
9033 | { | |
9034 | regno *= 10; | |
9035 | regno += *s - '0'; | |
9036 | ++s; | |
9037 | } | |
3882b010 | 9038 | while (ISDIGIT (*s)); |
252b5132 RH |
9039 | if (regno > 31) |
9040 | { | |
9041 | as_bad (_("invalid register number (%d)"), regno); | |
9042 | regno = 2; | |
9043 | } | |
9044 | } | |
9045 | else | |
9046 | { | |
9047 | if (s[1] == 'f' && s[2] == 'p') | |
9048 | { | |
9049 | s += 3; | |
9050 | regno = FP; | |
9051 | } | |
9052 | else if (s[1] == 's' && s[2] == 'p') | |
9053 | { | |
9054 | s += 3; | |
9055 | regno = SP; | |
9056 | } | |
9057 | else if (s[1] == 'g' && s[2] == 'p') | |
9058 | { | |
9059 | s += 3; | |
9060 | regno = GP; | |
9061 | } | |
9062 | else if (s[1] == 'a' && s[2] == 't') | |
9063 | { | |
9064 | s += 3; | |
9065 | regno = AT; | |
9066 | } | |
9067 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9068 | { | |
9069 | s += 4; | |
9070 | regno = KT0; | |
9071 | } | |
9072 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9073 | { | |
9074 | s += 4; | |
9075 | regno = KT1; | |
9076 | } | |
9077 | else | |
9078 | break; | |
9079 | } | |
9080 | ||
9081 | if (*s == ' ') | |
9082 | ++s; | |
9083 | if (args[1] != *s) | |
9084 | { | |
9085 | if (c == 'v' || c == 'w') | |
9086 | { | |
9087 | regno = mips16_to_32_reg_map[lastregno]; | |
9088 | s = s_reset; | |
f9419b05 | 9089 | ++args; |
252b5132 RH |
9090 | } |
9091 | } | |
9092 | ||
9093 | switch (c) | |
9094 | { | |
9095 | case 'x': | |
9096 | case 'y': | |
9097 | case 'z': | |
9098 | case 'v': | |
9099 | case 'w': | |
9100 | case 'Z': | |
9101 | regno = mips32_to_16_reg_map[regno]; | |
9102 | break; | |
9103 | ||
9104 | case '0': | |
9105 | if (regno != 0) | |
9106 | regno = ILLEGAL_REG; | |
9107 | break; | |
9108 | ||
9109 | case 'S': | |
9110 | if (regno != SP) | |
9111 | regno = ILLEGAL_REG; | |
9112 | break; | |
9113 | ||
9114 | case 'R': | |
9115 | if (regno != RA) | |
9116 | regno = ILLEGAL_REG; | |
9117 | break; | |
9118 | ||
9119 | case 'X': | |
9120 | case 'Y': | |
9121 | if (regno == AT && ! mips_opts.noat) | |
9122 | as_warn (_("used $at without \".set noat\"")); | |
9123 | break; | |
9124 | ||
9125 | default: | |
9126 | internalError (); | |
9127 | } | |
9128 | ||
9129 | if (regno == ILLEGAL_REG) | |
9130 | break; | |
9131 | ||
9132 | switch (c) | |
9133 | { | |
9134 | case 'x': | |
9135 | case 'v': | |
9136 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9137 | break; | |
9138 | case 'y': | |
9139 | case 'w': | |
9140 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9141 | break; | |
9142 | case 'z': | |
9143 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9144 | break; | |
9145 | case 'Z': | |
9146 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9147 | case '0': | |
9148 | case 'S': | |
9149 | case 'R': | |
9150 | break; | |
9151 | case 'X': | |
9152 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9153 | break; | |
9154 | case 'Y': | |
9155 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9156 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9157 | break; | |
9158 | default: | |
9159 | internalError (); | |
9160 | } | |
9161 | ||
9162 | lastregno = regno; | |
9163 | continue; | |
9164 | ||
9165 | case 'P': | |
9166 | if (strncmp (s, "$pc", 3) == 0) | |
9167 | { | |
9168 | s += 3; | |
9169 | continue; | |
9170 | } | |
9171 | break; | |
9172 | ||
9173 | case '<': | |
9174 | case '>': | |
9175 | case '[': | |
9176 | case ']': | |
9177 | case '4': | |
9178 | case '5': | |
9179 | case 'H': | |
9180 | case 'W': | |
9181 | case 'D': | |
9182 | case 'j': | |
9183 | case '8': | |
9184 | case 'V': | |
9185 | case 'C': | |
9186 | case 'U': | |
9187 | case 'k': | |
9188 | case 'K': | |
9189 | if (s[0] == '%' | |
9190 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9191 | { | |
9192 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9193 | and generate the appropriate reloc. If the text | |
9194 | inside %gprel is not a symbol name with an | |
9195 | optional offset, then we generate a normal reloc | |
9196 | and will probably fail later. */ | |
9197 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9198 | if (imm_expr.X_op == O_symbol) | |
9199 | { | |
9200 | mips16_ext = true; | |
f6688943 | 9201 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 RH |
9202 | s = expr_end; |
9203 | ip->use_extend = true; | |
9204 | ip->extend = 0; | |
9205 | continue; | |
9206 | } | |
9207 | } | |
9208 | else | |
9209 | { | |
9210 | /* Just pick up a normal expression. */ | |
9211 | my_getExpression (&imm_expr, s); | |
9212 | } | |
9213 | ||
9214 | if (imm_expr.X_op == O_register) | |
9215 | { | |
9216 | /* What we thought was an expression turned out to | |
9217 | be a register. */ | |
9218 | ||
9219 | if (s[0] == '(' && args[1] == '(') | |
9220 | { | |
9221 | /* It looks like the expression was omitted | |
9222 | before a register indirection, which means | |
9223 | that the expression is implicitly zero. We | |
9224 | still set up imm_expr, so that we handle | |
9225 | explicit extensions correctly. */ | |
9226 | imm_expr.X_op = O_constant; | |
9227 | imm_expr.X_add_number = 0; | |
f6688943 | 9228 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9229 | continue; |
9230 | } | |
9231 | ||
9232 | break; | |
9233 | } | |
9234 | ||
9235 | /* We need to relax this instruction. */ | |
f6688943 | 9236 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9237 | s = expr_end; |
9238 | continue; | |
9239 | ||
9240 | case 'p': | |
9241 | case 'q': | |
9242 | case 'A': | |
9243 | case 'B': | |
9244 | case 'E': | |
9245 | /* We use offset_reloc rather than imm_reloc for the PC | |
9246 | relative operands. This lets macros with both | |
9247 | immediate and address operands work correctly. */ | |
9248 | my_getExpression (&offset_expr, s); | |
9249 | ||
9250 | if (offset_expr.X_op == O_register) | |
9251 | break; | |
9252 | ||
9253 | /* We need to relax this instruction. */ | |
f6688943 | 9254 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9255 | s = expr_end; |
9256 | continue; | |
9257 | ||
9258 | case '6': /* break code */ | |
9259 | my_getExpression (&imm_expr, s); | |
9260 | check_absolute_expr (ip, &imm_expr); | |
9261 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9262 | { | |
9263 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9264 | ip->insn_mo->name, | |
9265 | (unsigned long) imm_expr.X_add_number); | |
9266 | imm_expr.X_add_number &= 0x3f; | |
9267 | } | |
9268 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9269 | imm_expr.X_op = O_absent; | |
9270 | s = expr_end; | |
9271 | continue; | |
9272 | ||
9273 | case 'a': /* 26 bit address */ | |
9274 | my_getExpression (&offset_expr, s); | |
9275 | s = expr_end; | |
f6688943 | 9276 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9277 | ip->insn_opcode <<= 16; |
9278 | continue; | |
9279 | ||
9280 | case 'l': /* register list for entry macro */ | |
9281 | case 'L': /* register list for exit macro */ | |
9282 | { | |
9283 | int mask; | |
9284 | ||
9285 | if (c == 'l') | |
9286 | mask = 0; | |
9287 | else | |
9288 | mask = 7 << 3; | |
9289 | while (*s != '\0') | |
9290 | { | |
9291 | int freg, reg1, reg2; | |
9292 | ||
9293 | while (*s == ' ' || *s == ',') | |
9294 | ++s; | |
9295 | if (*s != '$') | |
9296 | { | |
9297 | as_bad (_("can't parse register list")); | |
9298 | break; | |
9299 | } | |
9300 | ++s; | |
9301 | if (*s != 'f') | |
9302 | freg = 0; | |
9303 | else | |
9304 | { | |
9305 | freg = 1; | |
9306 | ++s; | |
9307 | } | |
9308 | reg1 = 0; | |
3882b010 | 9309 | while (ISDIGIT (*s)) |
252b5132 RH |
9310 | { |
9311 | reg1 *= 10; | |
9312 | reg1 += *s - '0'; | |
9313 | ++s; | |
9314 | } | |
9315 | if (*s == ' ') | |
9316 | ++s; | |
9317 | if (*s != '-') | |
9318 | reg2 = reg1; | |
9319 | else | |
9320 | { | |
9321 | ++s; | |
9322 | if (*s != '$') | |
9323 | break; | |
9324 | ++s; | |
9325 | if (freg) | |
9326 | { | |
9327 | if (*s == 'f') | |
9328 | ++s; | |
9329 | else | |
9330 | { | |
9331 | as_bad (_("invalid register list")); | |
9332 | break; | |
9333 | } | |
9334 | } | |
9335 | reg2 = 0; | |
3882b010 | 9336 | while (ISDIGIT (*s)) |
252b5132 RH |
9337 | { |
9338 | reg2 *= 10; | |
9339 | reg2 += *s - '0'; | |
9340 | ++s; | |
9341 | } | |
9342 | } | |
9343 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9344 | { | |
9345 | mask &= ~ (7 << 3); | |
9346 | mask |= 5 << 3; | |
9347 | } | |
9348 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9349 | { | |
9350 | mask &= ~ (7 << 3); | |
9351 | mask |= 6 << 3; | |
9352 | } | |
9353 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9354 | mask |= (reg2 - 3) << 3; | |
9355 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9356 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9357 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9358 | mask |= 1; |
9359 | else | |
9360 | { | |
9361 | as_bad (_("invalid register list")); | |
9362 | break; | |
9363 | } | |
9364 | } | |
9365 | /* The mask is filled in in the opcode table for the | |
9366 | benefit of the disassembler. We remove it before | |
9367 | applying the actual mask. */ | |
9368 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9369 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9370 | } | |
9371 | continue; | |
9372 | ||
9373 | case 'e': /* extend code */ | |
9374 | my_getExpression (&imm_expr, s); | |
9375 | check_absolute_expr (ip, &imm_expr); | |
9376 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9377 | { | |
9378 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9379 | ip->insn_mo->name, | |
9380 | (unsigned long) imm_expr.X_add_number); | |
9381 | imm_expr.X_add_number &= 0x7ff; | |
9382 | } | |
9383 | ip->insn_opcode |= imm_expr.X_add_number; | |
9384 | imm_expr.X_op = O_absent; | |
9385 | s = expr_end; | |
9386 | continue; | |
9387 | ||
9388 | default: | |
9389 | internalError (); | |
9390 | } | |
9391 | break; | |
9392 | } | |
9393 | ||
9394 | /* Args don't match. */ | |
9395 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9396 | strcmp (insn->name, insn[1].name) == 0) | |
9397 | { | |
9398 | ++insn; | |
9399 | s = argsstart; | |
9400 | continue; | |
9401 | } | |
9402 | ||
9403 | insn_error = _("illegal operands"); | |
9404 | ||
9405 | return; | |
9406 | } | |
9407 | } | |
9408 | ||
9409 | /* This structure holds information we know about a mips16 immediate | |
9410 | argument type. */ | |
9411 | ||
e972090a NC |
9412 | struct mips16_immed_operand |
9413 | { | |
252b5132 RH |
9414 | /* The type code used in the argument string in the opcode table. */ |
9415 | int type; | |
9416 | /* The number of bits in the short form of the opcode. */ | |
9417 | int nbits; | |
9418 | /* The number of bits in the extended form of the opcode. */ | |
9419 | int extbits; | |
9420 | /* The amount by which the short form is shifted when it is used; | |
9421 | for example, the sw instruction has a shift count of 2. */ | |
9422 | int shift; | |
9423 | /* The amount by which the short form is shifted when it is stored | |
9424 | into the instruction code. */ | |
9425 | int op_shift; | |
9426 | /* Non-zero if the short form is unsigned. */ | |
9427 | int unsp; | |
9428 | /* Non-zero if the extended form is unsigned. */ | |
9429 | int extu; | |
9430 | /* Non-zero if the value is PC relative. */ | |
9431 | int pcrel; | |
9432 | }; | |
9433 | ||
9434 | /* The mips16 immediate operand types. */ | |
9435 | ||
9436 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9437 | { | |
9438 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9439 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9440 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9441 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9442 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9443 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9444 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9445 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9446 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9447 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9448 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9449 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9450 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9451 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9452 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9453 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9454 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9455 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9456 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9457 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9458 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9459 | }; | |
9460 | ||
9461 | #define MIPS16_NUM_IMMED \ | |
9462 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9463 | ||
9464 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9465 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9466 | whether an extended value is needed; if one is needed, it sets | |
9467 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9468 | If SMALL is true, an unextended opcode was explicitly requested. | |
9469 | If EXT is true, an extended opcode was explicitly requested. If | |
9470 | WARN is true, warn if EXT does not match reality. */ | |
9471 | ||
9472 | static void | |
9473 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
9474 | extend) | |
9475 | char *file; | |
9476 | unsigned int line; | |
9477 | int type; | |
9478 | offsetT val; | |
9479 | boolean warn; | |
9480 | boolean small; | |
9481 | boolean ext; | |
9482 | unsigned long *insn; | |
9483 | boolean *use_extend; | |
9484 | unsigned short *extend; | |
9485 | { | |
9486 | register const struct mips16_immed_operand *op; | |
9487 | int mintiny, maxtiny; | |
9488 | boolean needext; | |
9489 | ||
9490 | op = mips16_immed_operands; | |
9491 | while (op->type != type) | |
9492 | { | |
9493 | ++op; | |
9494 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9495 | } | |
9496 | ||
9497 | if (op->unsp) | |
9498 | { | |
9499 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9500 | { | |
9501 | mintiny = 1; | |
9502 | maxtiny = 1 << op->nbits; | |
9503 | } | |
9504 | else | |
9505 | { | |
9506 | mintiny = 0; | |
9507 | maxtiny = (1 << op->nbits) - 1; | |
9508 | } | |
9509 | } | |
9510 | else | |
9511 | { | |
9512 | mintiny = - (1 << (op->nbits - 1)); | |
9513 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9514 | } | |
9515 | ||
9516 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9517 | if (type == 'p' || type == 'q') | |
9518 | val /= 2; | |
9519 | ||
9520 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9521 | || val < (mintiny << op->shift) | |
9522 | || val > (maxtiny << op->shift)) | |
9523 | needext = true; | |
9524 | else | |
9525 | needext = false; | |
9526 | ||
9527 | if (warn && ext && ! needext) | |
beae10d5 KH |
9528 | as_warn_where (file, line, |
9529 | _("extended operand requested but not required")); | |
252b5132 RH |
9530 | if (small && needext) |
9531 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9532 | ||
9533 | if (small || (! ext && ! needext)) | |
9534 | { | |
9535 | int insnval; | |
9536 | ||
9537 | *use_extend = false; | |
9538 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
9539 | insnval <<= op->op_shift; | |
9540 | *insn |= insnval; | |
9541 | } | |
9542 | else | |
9543 | { | |
9544 | long minext, maxext; | |
9545 | int extval; | |
9546 | ||
9547 | if (op->extu) | |
9548 | { | |
9549 | minext = 0; | |
9550 | maxext = (1 << op->extbits) - 1; | |
9551 | } | |
9552 | else | |
9553 | { | |
9554 | minext = - (1 << (op->extbits - 1)); | |
9555 | maxext = (1 << (op->extbits - 1)) - 1; | |
9556 | } | |
9557 | if (val < minext || val > maxext) | |
9558 | as_bad_where (file, line, | |
9559 | _("operand value out of range for instruction")); | |
9560 | ||
9561 | *use_extend = true; | |
9562 | if (op->extbits == 16) | |
9563 | { | |
9564 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9565 | val &= 0x1f; | |
9566 | } | |
9567 | else if (op->extbits == 15) | |
9568 | { | |
9569 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9570 | val &= 0xf; | |
9571 | } | |
9572 | else | |
9573 | { | |
9574 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9575 | val = 0; | |
9576 | } | |
9577 | ||
9578 | *extend = (unsigned short) extval; | |
9579 | *insn |= val; | |
9580 | } | |
9581 | } | |
9582 | \f | |
ad8d3bb3 TS |
9583 | static struct percent_op_match |
9584 | { | |
9585 | const char *str; | |
9586 | const enum small_ex_type type; | |
9587 | } percent_op[] = | |
9588 | { | |
ad8d3bb3 TS |
9589 | {"%lo", S_EX_LO}, |
9590 | #ifdef OBJ_ELF | |
394f9b3a TS |
9591 | {"%call_hi", S_EX_CALL_HI}, |
9592 | {"%call_lo", S_EX_CALL_LO}, | |
ad8d3bb3 TS |
9593 | {"%call16", S_EX_CALL16}, |
9594 | {"%got_disp", S_EX_GOT_DISP}, | |
9595 | {"%got_page", S_EX_GOT_PAGE}, | |
9596 | {"%got_ofst", S_EX_GOT_OFST}, | |
9597 | {"%got_hi", S_EX_GOT_HI}, | |
9598 | {"%got_lo", S_EX_GOT_LO}, | |
394f9b3a TS |
9599 | {"%got", S_EX_GOT}, |
9600 | {"%gp_rel", S_EX_GP_REL}, | |
9601 | {"%half", S_EX_HALF}, | |
ad8d3bb3 | 9602 | {"%highest", S_EX_HIGHEST}, |
394f9b3a TS |
9603 | {"%higher", S_EX_HIGHER}, |
9604 | {"%neg", S_EX_NEG}, | |
ad8d3bb3 | 9605 | #endif |
394f9b3a | 9606 | {"%hi", S_EX_HI} |
ad8d3bb3 TS |
9607 | }; |
9608 | ||
9609 | /* Parse small expression input. STR gets adjusted to eat up whitespace. | |
9610 | It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's | |
9611 | can be nested, this is handled by blanking the innermost, parsing the | |
9612 | rest by subsequent calls. */ | |
252b5132 RH |
9613 | |
9614 | static int | |
ad8d3bb3 TS |
9615 | my_getSmallParser (str, len, nestlevel) |
9616 | char **str; | |
9617 | unsigned int *len; | |
9618 | int *nestlevel; | |
252b5132 | 9619 | { |
ad8d3bb3 TS |
9620 | *len = 0; |
9621 | *str += strspn (*str, " \t"); | |
394f9b3a | 9622 | /* Check for expression in parentheses. */ |
ad8d3bb3 | 9623 | if (**str == '(') |
252b5132 | 9624 | { |
ad8d3bb3 TS |
9625 | char *b = *str + 1 + strspn (*str + 1, " \t"); |
9626 | char *e; | |
9627 | ||
9628 | /* Check for base register. */ | |
9629 | if (b[0] == '$') | |
9630 | { | |
9631 | if (strchr (b, ')') | |
9632 | && (e = b + strcspn (b, ") \t")) | |
9633 | && e - b > 1 && e - b < 4) | |
9634 | { | |
98d3f06f KH |
9635 | if ((e - b == 3 |
9636 | && ((b[1] == 'f' && b[2] == 'p') | |
9637 | || (b[1] == 's' && b[2] == 'p') | |
9638 | || (b[1] == 'g' && b[2] == 'p') | |
9639 | || (b[1] == 'a' && b[2] == 't') | |
9640 | || (ISDIGIT (b[1]) | |
9641 | && ISDIGIT (b[2])))) | |
9642 | || (ISDIGIT (b[1]))) | |
9643 | { | |
9644 | *len = strcspn (*str, ")") + 1; | |
9645 | return S_EX_REGISTER; | |
9646 | } | |
ad8d3bb3 TS |
9647 | } |
9648 | } | |
394f9b3a | 9649 | /* Check for percent_op (in parentheses). */ |
ad8d3bb3 TS |
9650 | else if (b[0] == '%') |
9651 | { | |
9652 | *str = b; | |
394f9b3a | 9653 | return my_getPercentOp (str, len, nestlevel); |
ad8d3bb3 | 9654 | } |
76b3015f | 9655 | |
394f9b3a TS |
9656 | /* Some other expression in the parentheses, which can contain |
9657 | parentheses itself. Attempt to find the matching one. */ | |
9658 | { | |
9659 | int pcnt = 1; | |
9660 | char *s; | |
9661 | ||
9662 | *len = 1; | |
9663 | for (s = *str + 1; *s && pcnt; s++, (*len)++) | |
9664 | { | |
9665 | if (*s == '(') | |
f9419b05 | 9666 | ++pcnt; |
394f9b3a | 9667 | else if (*s == ')') |
f9419b05 | 9668 | --pcnt; |
394f9b3a TS |
9669 | } |
9670 | } | |
fb1b3232 | 9671 | } |
394f9b3a | 9672 | /* Check for percent_op (outside of parentheses). */ |
ad8d3bb3 | 9673 | else if (*str[0] == '%') |
394f9b3a TS |
9674 | return my_getPercentOp (str, len, nestlevel); |
9675 | ||
9676 | /* Any other expression. */ | |
9677 | return S_EX_NONE; | |
9678 | } | |
ad8d3bb3 | 9679 | |
394f9b3a TS |
9680 | static int |
9681 | my_getPercentOp (str, len, nestlevel) | |
9682 | char **str; | |
9683 | unsigned int *len; | |
9684 | int *nestlevel; | |
9685 | { | |
9686 | char *tmp = *str + 1; | |
9687 | unsigned int i = 0; | |
ad8d3bb3 | 9688 | |
394f9b3a TS |
9689 | while (ISALPHA (*tmp) || *tmp == '_') |
9690 | { | |
9691 | *tmp = TOLOWER (*tmp); | |
9692 | tmp++; | |
9693 | } | |
9694 | while (i < (sizeof (percent_op) / sizeof (struct percent_op_match))) | |
9695 | { | |
9696 | if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str))) | |
98d3f06f | 9697 | i++; |
394f9b3a | 9698 | else |
ad8d3bb3 | 9699 | { |
394f9b3a | 9700 | int type = percent_op[i].type; |
ad8d3bb3 | 9701 | |
394f9b3a TS |
9702 | /* Only %hi and %lo are allowed for OldABI. */ |
9703 | if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO) | |
9704 | return S_EX_NONE; | |
ad8d3bb3 | 9705 | |
394f9b3a | 9706 | *len = strlen (percent_op[i].str); |
f9419b05 | 9707 | ++(*nestlevel); |
394f9b3a | 9708 | return type; |
ad8d3bb3 | 9709 | } |
fb1b3232 | 9710 | } |
ad8d3bb3 TS |
9711 | return S_EX_NONE; |
9712 | } | |
9713 | ||
9714 | static int | |
9715 | my_getSmallExpression (ep, str) | |
9716 | expressionS *ep; | |
9717 | char *str; | |
9718 | { | |
9719 | static char *oldstr = NULL; | |
9720 | int c = S_EX_NONE; | |
9721 | int oldc; | |
394f9b3a | 9722 | int nestlevel = -1; |
ad8d3bb3 TS |
9723 | unsigned int len; |
9724 | ||
394f9b3a TS |
9725 | /* Don't update oldstr if the last call had nested percent_op's. We need |
9726 | it to parse the outer ones later. */ | |
ad8d3bb3 TS |
9727 | if (! oldstr) |
9728 | oldstr = str; | |
76b3015f | 9729 | |
ad8d3bb3 | 9730 | do |
fb1b3232 | 9731 | { |
ad8d3bb3 | 9732 | oldc = c; |
394f9b3a | 9733 | c = my_getSmallParser (&str, &len, &nestlevel); |
ad8d3bb3 TS |
9734 | if (c != S_EX_NONE && c != S_EX_REGISTER) |
9735 | str += len; | |
fb1b3232 | 9736 | } |
ad8d3bb3 TS |
9737 | while (c != S_EX_NONE && c != S_EX_REGISTER); |
9738 | ||
394f9b3a | 9739 | if (nestlevel >= 0) |
fb1b3232 | 9740 | { |
394f9b3a TS |
9741 | /* A percent_op was encountered. Don't try to get an expression if |
9742 | it is already blanked out. */ | |
ad8d3bb3 TS |
9743 | if (*(str + strspn (str + 1, " )")) != ')') |
9744 | { | |
9745 | char save; | |
9746 | ||
394f9b3a | 9747 | /* Let my_getExpression() stop at the closing parenthesis. */ |
ad8d3bb3 TS |
9748 | save = *(str + len); |
9749 | *(str + len) = '\0'; | |
9750 | my_getExpression (ep, str); | |
9751 | *(str + len) = save; | |
9752 | } | |
394f9b3a | 9753 | if (nestlevel > 0) |
ad8d3bb3 | 9754 | { |
394f9b3a TS |
9755 | /* Blank out including the % sign and the proper matching |
9756 | parenthesis. */ | |
9757 | int pcnt = 1; | |
9758 | char *s = strrchr (oldstr, '%'); | |
9759 | char *end; | |
9760 | ||
9761 | for (end = strchr (s, '(') + 1; *end && pcnt; end++) | |
9762 | { | |
9763 | if (*end == '(') | |
f9419b05 | 9764 | ++pcnt; |
394f9b3a | 9765 | else if (*end == ')') |
f9419b05 | 9766 | --pcnt; |
394f9b3a TS |
9767 | } |
9768 | ||
9769 | memset (s, ' ', end - s); | |
ad8d3bb3 TS |
9770 | str = oldstr; |
9771 | } | |
9772 | else | |
394f9b3a TS |
9773 | expr_end = str + len; |
9774 | ||
ad8d3bb3 | 9775 | c = oldc; |
fb1b3232 | 9776 | } |
ad8d3bb3 | 9777 | else if (c == S_EX_NONE) |
fb1b3232 | 9778 | { |
ad8d3bb3 | 9779 | my_getExpression (ep, str); |
fb1b3232 | 9780 | } |
ad8d3bb3 | 9781 | else if (c == S_EX_REGISTER) |
fb1b3232 | 9782 | { |
ad8d3bb3 TS |
9783 | ep->X_op = O_constant; |
9784 | expr_end = str; | |
9785 | ep->X_add_symbol = NULL; | |
9786 | ep->X_op_symbol = NULL; | |
9787 | ep->X_add_number = 0; | |
fb1b3232 | 9788 | } |
fb1b3232 TS |
9789 | else |
9790 | { | |
98d3f06f | 9791 | as_fatal (_("internal error")); |
fb1b3232 | 9792 | } |
252b5132 | 9793 | |
394f9b3a TS |
9794 | if (nestlevel <= 0) |
9795 | /* All percent_op's have been handled. */ | |
ad8d3bb3 | 9796 | oldstr = NULL; |
fb1b3232 | 9797 | |
fb1b3232 | 9798 | return c; |
252b5132 RH |
9799 | } |
9800 | ||
9801 | static void | |
9802 | my_getExpression (ep, str) | |
9803 | expressionS *ep; | |
9804 | char *str; | |
9805 | { | |
9806 | char *save_in; | |
98aa84af | 9807 | valueT val; |
252b5132 RH |
9808 | |
9809 | save_in = input_line_pointer; | |
9810 | input_line_pointer = str; | |
9811 | expression (ep); | |
9812 | expr_end = input_line_pointer; | |
9813 | input_line_pointer = save_in; | |
9814 | ||
9815 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9816 | then we bump the value of the symbol by 1 since that is how other | |
9817 | text symbols are handled. We don't bother to handle complex | |
9818 | expressions, just `.' plus or minus a constant. */ | |
9819 | if (mips_opts.mips16 | |
9820 | && ep->X_op == O_symbol | |
9821 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9822 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9823 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9824 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9825 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9826 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9827 | } |
9828 | ||
9829 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9830 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9831 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9832 | returned, or NULL on OK. */ |
9833 | ||
9834 | char * | |
9835 | md_atof (type, litP, sizeP) | |
9836 | int type; | |
9837 | char *litP; | |
9838 | int *sizeP; | |
9839 | { | |
9840 | int prec; | |
9841 | LITTLENUM_TYPE words[4]; | |
9842 | char *t; | |
9843 | int i; | |
9844 | ||
9845 | switch (type) | |
9846 | { | |
9847 | case 'f': | |
9848 | prec = 2; | |
9849 | break; | |
9850 | ||
9851 | case 'd': | |
9852 | prec = 4; | |
9853 | break; | |
9854 | ||
9855 | default: | |
9856 | *sizeP = 0; | |
9857 | return _("bad call to md_atof"); | |
9858 | } | |
9859 | ||
9860 | t = atof_ieee (input_line_pointer, type, words); | |
9861 | if (t) | |
9862 | input_line_pointer = t; | |
9863 | ||
9864 | *sizeP = prec * 2; | |
9865 | ||
9866 | if (! target_big_endian) | |
9867 | { | |
9868 | for (i = prec - 1; i >= 0; i--) | |
9869 | { | |
9870 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9871 | litP += 2; | |
9872 | } | |
9873 | } | |
9874 | else | |
9875 | { | |
9876 | for (i = 0; i < prec; i++) | |
9877 | { | |
9878 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9879 | litP += 2; | |
9880 | } | |
9881 | } | |
bdaaa2e1 | 9882 | |
252b5132 RH |
9883 | return NULL; |
9884 | } | |
9885 | ||
9886 | void | |
9887 | md_number_to_chars (buf, val, n) | |
9888 | char *buf; | |
9889 | valueT val; | |
9890 | int n; | |
9891 | { | |
9892 | if (target_big_endian) | |
9893 | number_to_chars_bigendian (buf, val, n); | |
9894 | else | |
9895 | number_to_chars_littleendian (buf, val, n); | |
9896 | } | |
9897 | \f | |
ae948b86 | 9898 | #ifdef OBJ_ELF |
e013f690 TS |
9899 | static int support_64bit_objects(void) |
9900 | { | |
9901 | const char **list, **l; | |
9902 | ||
9903 | list = bfd_target_list (); | |
9904 | for (l = list; *l != NULL; l++) | |
9905 | #ifdef TE_TMIPS | |
9906 | /* This is traditional mips */ | |
9907 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9908 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9909 | #else | |
9910 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9911 | || strcmp (*l, "elf64-littlemips") == 0) | |
9912 | #endif | |
9913 | break; | |
9914 | free (list); | |
9915 | return (*l != NULL); | |
9916 | } | |
ae948b86 | 9917 | #endif /* OBJ_ELF */ |
e013f690 | 9918 | |
39c0a331 | 9919 | CONST char *md_shortopts = "nO::g::G:"; |
252b5132 | 9920 | |
e972090a NC |
9921 | struct option md_longopts[] = |
9922 | { | |
252b5132 RH |
9923 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
9924 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
9925 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
9926 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
9927 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
9928 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
9929 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
9930 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
9931 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
ae948b86 TS |
9932 | #define OPTION_MIPS5 (OPTION_MD_BASE + 5) |
9933 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
9934 | #define OPTION_MIPS32 (OPTION_MD_BASE + 6) | |
9935 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
9936 | #define OPTION_MIPS64 (OPTION_MD_BASE + 7) | |
9937 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
9938 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8) | |
252b5132 | 9939 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
ae948b86 | 9940 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
252b5132 RH |
9941 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9942 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
ae948b86 | 9943 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
252b5132 RH |
9944 | {"break", no_argument, NULL, OPTION_BREAK}, |
9945 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
ae948b86 | 9946 | #define OPTION_EB (OPTION_MD_BASE + 11) |
252b5132 | 9947 | {"EB", no_argument, NULL, OPTION_EB}, |
ae948b86 | 9948 | #define OPTION_EL (OPTION_MD_BASE + 12) |
252b5132 | 9949 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 9950 | #define OPTION_MIPS16 (OPTION_MD_BASE + 13) |
252b5132 | 9951 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
ae948b86 | 9952 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14) |
252b5132 | 9953 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
ae948b86 | 9954 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15) |
6b76fefe | 9955 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
9ee72ff1 TS |
9956 | #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16) |
9957 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
9958 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
ae948b86 TS |
9959 | #define OPTION_FP32 (OPTION_MD_BASE + 17) |
9960 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
9961 | #define OPTION_GP32 (OPTION_MD_BASE + 18) | |
c97ef257 | 9962 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
ae948b86 | 9963 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19) |
119d663a | 9964 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
ae948b86 | 9965 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20) |
119d663a | 9966 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
ae948b86 | 9967 | #define OPTION_MARCH (OPTION_MD_BASE + 21) |
ec68c924 | 9968 | {"march", required_argument, NULL, OPTION_MARCH}, |
ae948b86 | 9969 | #define OPTION_MTUNE (OPTION_MD_BASE + 22) |
ec68c924 | 9970 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
ae948b86 TS |
9971 | #define OPTION_MCPU (OPTION_MD_BASE + 23) |
9972 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
9973 | #define OPTION_M4650 (OPTION_MD_BASE + 24) | |
9974 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
9975 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 25) | |
9976 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
9977 | #define OPTION_M4010 (OPTION_MD_BASE + 26) | |
9978 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
9979 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 27) | |
9980 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
9981 | #define OPTION_M4100 (OPTION_MD_BASE + 28) | |
9982 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
9983 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 29) | |
9984 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
9985 | #define OPTION_M3900 (OPTION_MD_BASE + 30) | |
9986 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
9987 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 31) | |
9988 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
9989 | #define OPTION_GP64 (OPTION_MD_BASE + 32) | |
9990 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1f25f5d3 CD |
9991 | #define OPTION_MIPS3D (OPTION_MD_BASE + 33) |
9992 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
9993 | #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34) | |
9994 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
156c2f8b | 9995 | #ifdef OBJ_ELF |
1f25f5d3 | 9996 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 35) |
156c2f8b | 9997 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
9998 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
9999 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10000 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10001 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10002 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10003 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10004 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10005 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10006 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10007 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10008 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10009 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10010 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10011 | {"64", no_argument, NULL, OPTION_64}, |
ae948b86 | 10012 | #endif /* OBJ_ELF */ |
252b5132 RH |
10013 | {NULL, no_argument, NULL, 0} |
10014 | }; | |
156c2f8b | 10015 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
10016 | |
10017 | int | |
10018 | md_parse_option (c, arg) | |
10019 | int c; | |
10020 | char *arg; | |
10021 | { | |
10022 | switch (c) | |
10023 | { | |
119d663a NC |
10024 | case OPTION_CONSTRUCT_FLOATS: |
10025 | mips_disable_float_construction = 0; | |
10026 | break; | |
bdaaa2e1 | 10027 | |
119d663a NC |
10028 | case OPTION_NO_CONSTRUCT_FLOATS: |
10029 | mips_disable_float_construction = 1; | |
10030 | break; | |
bdaaa2e1 | 10031 | |
252b5132 RH |
10032 | case OPTION_TRAP: |
10033 | mips_trap = 1; | |
10034 | break; | |
10035 | ||
10036 | case OPTION_BREAK: | |
10037 | mips_trap = 0; | |
10038 | break; | |
10039 | ||
10040 | case OPTION_EB: | |
10041 | target_big_endian = 1; | |
10042 | break; | |
10043 | ||
10044 | case OPTION_EL: | |
10045 | target_big_endian = 0; | |
10046 | break; | |
10047 | ||
39c0a331 L |
10048 | case 'n': |
10049 | warn_nops = 1; | |
10050 | break; | |
10051 | ||
252b5132 RH |
10052 | case 'O': |
10053 | if (arg && arg[1] == '0') | |
10054 | mips_optimize = 1; | |
10055 | else | |
10056 | mips_optimize = 2; | |
10057 | break; | |
10058 | ||
10059 | case 'g': | |
10060 | if (arg == NULL) | |
10061 | mips_debug = 2; | |
10062 | else | |
10063 | mips_debug = atoi (arg); | |
10064 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10065 | optimizations which limit full symbolic debugging. We take | |
10066 | that to be equivalent to -O0. */ | |
10067 | if (mips_debug == 2) | |
10068 | mips_optimize = 1; | |
10069 | break; | |
10070 | ||
10071 | case OPTION_MIPS1: | |
e7af610e | 10072 | mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
10073 | break; |
10074 | ||
10075 | case OPTION_MIPS2: | |
e7af610e | 10076 | mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
10077 | break; |
10078 | ||
10079 | case OPTION_MIPS3: | |
e7af610e | 10080 | mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
10081 | break; |
10082 | ||
10083 | case OPTION_MIPS4: | |
e7af610e NC |
10084 | mips_opts.isa = ISA_MIPS4; |
10085 | break; | |
10086 | ||
84ea6cf2 NC |
10087 | case OPTION_MIPS5: |
10088 | mips_opts.isa = ISA_MIPS5; | |
10089 | break; | |
10090 | ||
e7af610e NC |
10091 | case OPTION_MIPS32: |
10092 | mips_opts.isa = ISA_MIPS32; | |
252b5132 RH |
10093 | break; |
10094 | ||
84ea6cf2 NC |
10095 | case OPTION_MIPS64: |
10096 | mips_opts.isa = ISA_MIPS64; | |
10097 | break; | |
10098 | ||
ec68c924 EC |
10099 | case OPTION_MTUNE: |
10100 | case OPTION_MARCH: | |
252b5132 RH |
10101 | case OPTION_MCPU: |
10102 | { | |
ec68c924 EC |
10103 | int cpu = CPU_UNKNOWN; |
10104 | ||
e7af610e | 10105 | /* Identify the processor type. */ |
ec68c924 | 10106 | if (strcasecmp (arg, "default") != 0) |
252b5132 | 10107 | { |
e7af610e | 10108 | const struct mips_cpu_info *ci; |
252b5132 | 10109 | |
e7af610e NC |
10110 | ci = mips_cpu_info_from_name (arg); |
10111 | if (ci == NULL || ci->is_isa) | |
ec68c924 EC |
10112 | { |
10113 | switch (c) | |
10114 | { | |
10115 | case OPTION_MTUNE: | |
10116 | as_fatal (_("invalid architecture -mtune=%s"), arg); | |
10117 | break; | |
10118 | case OPTION_MARCH: | |
10119 | as_fatal (_("invalid architecture -march=%s"), arg); | |
10120 | break; | |
10121 | case OPTION_MCPU: | |
10122 | as_fatal (_("invalid architecture -mcpu=%s"), arg); | |
10123 | break; | |
10124 | } | |
10125 | } | |
e7af610e | 10126 | else |
98d3f06f | 10127 | cpu = ci->cpu; |
ec68c924 EC |
10128 | } |
10129 | ||
10130 | switch (c) | |
10131 | { | |
10132 | case OPTION_MTUNE: | |
6dce9e24 | 10133 | if (mips_tune != CPU_UNKNOWN && mips_tune != cpu) |
98d3f06f KH |
10134 | as_warn (_("A different -mtune= was already specified, is now " |
10135 | "-mtune=%s"), arg); | |
ec68c924 EC |
10136 | mips_tune = cpu; |
10137 | break; | |
10138 | case OPTION_MARCH: | |
6dce9e24 | 10139 | if (mips_arch != CPU_UNKNOWN && mips_arch != cpu) |
98d3f06f KH |
10140 | as_warn (_("A different -march= was already specified, is now " |
10141 | "-march=%s"), arg); | |
ec68c924 EC |
10142 | mips_arch = cpu; |
10143 | break; | |
10144 | case OPTION_MCPU: | |
6dce9e24 | 10145 | if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu) |
98d3f06f KH |
10146 | as_warn (_("A different -mcpu= was already specified, is now " |
10147 | "-mcpu=%s"), arg); | |
ec68c924 | 10148 | mips_cpu = cpu; |
252b5132 RH |
10149 | } |
10150 | } | |
10151 | break; | |
10152 | ||
10153 | case OPTION_M4650: | |
6dce9e24 TS |
10154 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650) |
10155 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650)) | |
98d3f06f KH |
10156 | as_warn (_("A different -march= or -mtune= was already specified, " |
10157 | "is now -m4650")); | |
ec68c924 EC |
10158 | mips_arch = CPU_R4650; |
10159 | mips_tune = CPU_R4650; | |
252b5132 RH |
10160 | break; |
10161 | ||
10162 | case OPTION_NO_M4650: | |
10163 | break; | |
10164 | ||
10165 | case OPTION_M4010: | |
6dce9e24 TS |
10166 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010) |
10167 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010)) | |
98d3f06f KH |
10168 | as_warn (_("A different -march= or -mtune= was already specified, " |
10169 | "is now -m4010")); | |
ec68c924 EC |
10170 | mips_arch = CPU_R4010; |
10171 | mips_tune = CPU_R4010; | |
252b5132 RH |
10172 | break; |
10173 | ||
10174 | case OPTION_NO_M4010: | |
10175 | break; | |
10176 | ||
10177 | case OPTION_M4100: | |
6dce9e24 TS |
10178 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100) |
10179 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100)) | |
98d3f06f KH |
10180 | as_warn (_("A different -march= or -mtune= was already specified, " |
10181 | "is now -m4100")); | |
ec68c924 EC |
10182 | mips_arch = CPU_VR4100; |
10183 | mips_tune = CPU_VR4100; | |
252b5132 RH |
10184 | break; |
10185 | ||
10186 | case OPTION_NO_M4100: | |
10187 | break; | |
10188 | ||
252b5132 | 10189 | case OPTION_M3900: |
6dce9e24 TS |
10190 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900) |
10191 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900)) | |
98d3f06f KH |
10192 | as_warn (_("A different -march= or -mtune= was already specified, " |
10193 | "is now -m3900")); | |
ec68c924 EC |
10194 | mips_arch = CPU_R3900; |
10195 | mips_tune = CPU_R3900; | |
252b5132 | 10196 | break; |
bdaaa2e1 | 10197 | |
252b5132 RH |
10198 | case OPTION_NO_M3900: |
10199 | break; | |
10200 | ||
10201 | case OPTION_MIPS16: | |
10202 | mips_opts.mips16 = 1; | |
10203 | mips_no_prev_insn (false); | |
10204 | break; | |
10205 | ||
10206 | case OPTION_NO_MIPS16: | |
10207 | mips_opts.mips16 = 0; | |
10208 | mips_no_prev_insn (false); | |
10209 | break; | |
10210 | ||
1f25f5d3 CD |
10211 | case OPTION_MIPS3D: |
10212 | mips_opts.ase_mips3d = 1; | |
10213 | break; | |
10214 | ||
10215 | case OPTION_NO_MIPS3D: | |
10216 | mips_opts.ase_mips3d = 0; | |
10217 | break; | |
10218 | ||
252b5132 RH |
10219 | case OPTION_MEMBEDDED_PIC: |
10220 | mips_pic = EMBEDDED_PIC; | |
10221 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10222 | { | |
10223 | as_bad (_("-G may not be used with embedded PIC code")); | |
10224 | return 0; | |
10225 | } | |
10226 | g_switch_value = 0x7fffffff; | |
10227 | break; | |
10228 | ||
0f074f60 | 10229 | #ifdef OBJ_ELF |
252b5132 RH |
10230 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10231 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10232 | intended to be compatible with Irix 5. */ | |
10233 | case OPTION_CALL_SHARED: | |
10234 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10235 | { | |
10236 | as_bad (_("-call_shared is supported only for ELF format")); | |
10237 | return 0; | |
10238 | } | |
10239 | mips_pic = SVR4_PIC; | |
10240 | if (g_switch_seen && g_switch_value != 0) | |
10241 | { | |
10242 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10243 | return 0; | |
10244 | } | |
10245 | g_switch_value = 0; | |
10246 | break; | |
10247 | ||
10248 | case OPTION_NON_SHARED: | |
10249 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10250 | { | |
10251 | as_bad (_("-non_shared is supported only for ELF format")); | |
10252 | return 0; | |
10253 | } | |
10254 | mips_pic = NO_PIC; | |
10255 | break; | |
10256 | ||
10257 | /* The -xgot option tells the assembler to use 32 offsets when | |
10258 | accessing the got in SVR4_PIC mode. It is for Irix | |
10259 | compatibility. */ | |
10260 | case OPTION_XGOT: | |
10261 | mips_big_got = 1; | |
10262 | break; | |
0f074f60 | 10263 | #endif /* OBJ_ELF */ |
252b5132 RH |
10264 | |
10265 | case 'G': | |
10266 | if (! USE_GLOBAL_POINTER_OPT) | |
10267 | { | |
10268 | as_bad (_("-G is not supported for this configuration")); | |
10269 | return 0; | |
10270 | } | |
10271 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10272 | { | |
10273 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10274 | return 0; | |
10275 | } | |
10276 | else | |
10277 | g_switch_value = atoi (arg); | |
10278 | g_switch_seen = 1; | |
10279 | break; | |
10280 | ||
0f074f60 | 10281 | #ifdef OBJ_ELF |
34ba82a8 TS |
10282 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10283 | and -mabi=64. */ | |
252b5132 | 10284 | case OPTION_32: |
34ba82a8 TS |
10285 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10286 | { | |
10287 | as_bad (_("-32 is supported for ELF format only")); | |
10288 | return 0; | |
10289 | } | |
a325df1d | 10290 | mips_opts.abi = O32_ABI; |
252b5132 RH |
10291 | break; |
10292 | ||
e013f690 | 10293 | case OPTION_N32: |
34ba82a8 TS |
10294 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10295 | { | |
10296 | as_bad (_("-n32 is supported for ELF format only")); | |
10297 | return 0; | |
10298 | } | |
a325df1d | 10299 | mips_opts.abi = N32_ABI; |
e013f690 | 10300 | break; |
252b5132 | 10301 | |
e013f690 | 10302 | case OPTION_64: |
34ba82a8 TS |
10303 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10304 | { | |
10305 | as_bad (_("-64 is supported for ELF format only")); | |
10306 | return 0; | |
10307 | } | |
a325df1d | 10308 | mips_opts.abi = N64_ABI; |
e013f690 TS |
10309 | if (! support_64bit_objects()) |
10310 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10311 | break; |
ae948b86 | 10312 | #endif /* OBJ_ELF */ |
252b5132 | 10313 | |
c97ef257 | 10314 | case OPTION_GP32: |
a325df1d TS |
10315 | file_mips_gp32 = 1; |
10316 | if (mips_opts.abi != O32_ABI) | |
10317 | mips_opts.abi = NO_ABI; | |
c97ef257 AH |
10318 | break; |
10319 | ||
10320 | case OPTION_GP64: | |
a325df1d TS |
10321 | file_mips_gp32 = 0; |
10322 | if (mips_opts.abi == O32_ABI) | |
10323 | mips_opts.abi = NO_ABI; | |
c97ef257 | 10324 | break; |
252b5132 | 10325 | |
ca4e0257 | 10326 | case OPTION_FP32: |
a325df1d TS |
10327 | file_mips_fp32 = 1; |
10328 | if (mips_opts.abi != O32_ABI) | |
10329 | mips_opts.abi = NO_ABI; | |
ca4e0257 RS |
10330 | break; |
10331 | ||
ae948b86 | 10332 | #ifdef OBJ_ELF |
252b5132 | 10333 | case OPTION_MABI: |
34ba82a8 TS |
10334 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10335 | { | |
10336 | as_bad (_("-mabi is supported for ELF format only")); | |
10337 | return 0; | |
10338 | } | |
e013f690 | 10339 | if (strcmp (arg, "32") == 0) |
a325df1d | 10340 | mips_opts.abi = O32_ABI; |
e013f690 | 10341 | else if (strcmp (arg, "o64") == 0) |
a325df1d | 10342 | mips_opts.abi = O64_ABI; |
e013f690 | 10343 | else if (strcmp (arg, "n32") == 0) |
a325df1d | 10344 | mips_opts.abi = N32_ABI; |
e013f690 TS |
10345 | else if (strcmp (arg, "64") == 0) |
10346 | { | |
a325df1d | 10347 | mips_opts.abi = N64_ABI; |
e013f690 TS |
10348 | if (! support_64bit_objects()) |
10349 | as_fatal (_("No compiled in support for 64 bit object file " | |
10350 | "format")); | |
10351 | } | |
10352 | else if (strcmp (arg, "eabi") == 0) | |
a325df1d | 10353 | mips_opts.abi = EABI_ABI; |
e013f690 | 10354 | else |
da0e507f TS |
10355 | { |
10356 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10357 | return 0; | |
10358 | } | |
252b5132 | 10359 | break; |
e013f690 | 10360 | #endif /* OBJ_ELF */ |
252b5132 | 10361 | |
6b76fefe CM |
10362 | case OPTION_M7000_HILO_FIX: |
10363 | mips_7000_hilo_fix = true; | |
10364 | break; | |
10365 | ||
9ee72ff1 | 10366 | case OPTION_MNO_7000_HILO_FIX: |
6b76fefe CM |
10367 | mips_7000_hilo_fix = false; |
10368 | break; | |
10369 | ||
252b5132 RH |
10370 | default: |
10371 | return 0; | |
10372 | } | |
10373 | ||
10374 | return 1; | |
10375 | } | |
10376 | ||
252b5132 RH |
10377 | static void |
10378 | show (stream, string, col_p, first_p) | |
10379 | FILE *stream; | |
10380 | char *string; | |
10381 | int *col_p; | |
10382 | int *first_p; | |
10383 | { | |
10384 | if (*first_p) | |
10385 | { | |
10386 | fprintf (stream, "%24s", ""); | |
10387 | *col_p = 24; | |
10388 | } | |
10389 | else | |
10390 | { | |
10391 | fprintf (stream, ", "); | |
10392 | *col_p += 2; | |
10393 | } | |
10394 | ||
10395 | if (*col_p + strlen (string) > 72) | |
10396 | { | |
10397 | fprintf (stream, "\n%24s", ""); | |
10398 | *col_p = 24; | |
10399 | } | |
10400 | ||
10401 | fprintf (stream, "%s", string); | |
10402 | *col_p += strlen (string); | |
10403 | ||
10404 | *first_p = 0; | |
10405 | } | |
10406 | ||
252b5132 RH |
10407 | void |
10408 | md_show_usage (stream) | |
10409 | FILE *stream; | |
10410 | { | |
10411 | int column, first; | |
10412 | ||
beae10d5 | 10413 | fprintf (stream, _("\ |
252b5132 RH |
10414 | MIPS options:\n\ |
10415 | -membedded-pic generate embedded position independent code\n\ | |
10416 | -EB generate big endian output\n\ | |
10417 | -EL generate little endian output\n\ | |
9a41af64 | 10418 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ |
252b5132 RH |
10419 | -G NUM allow referencing objects up to NUM bytes\n\ |
10420 | implicitly with the gp register [default 8]\n")); | |
beae10d5 | 10421 | fprintf (stream, _("\ |
252b5132 RH |
10422 | -mips1 generate MIPS ISA I instructions\n\ |
10423 | -mips2 generate MIPS ISA II instructions\n\ | |
10424 | -mips3 generate MIPS ISA III instructions\n\ | |
10425 | -mips4 generate MIPS ISA IV instructions\n\ | |
84ea6cf2 | 10426 | -mips5 generate MIPS ISA V instructions\n\ |
e7af610e | 10427 | -mips32 generate MIPS32 ISA instructions\n\ |
84ea6cf2 | 10428 | -mips64 generate MIPS64 ISA instructions\n\ |
ec68c924 | 10429 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
252b5132 RH |
10430 | |
10431 | first = 1; | |
10432 | ||
10433 | show (stream, "2000", &column, &first); | |
10434 | show (stream, "3000", &column, &first); | |
10435 | show (stream, "3900", &column, &first); | |
10436 | show (stream, "4000", &column, &first); | |
10437 | show (stream, "4010", &column, &first); | |
10438 | show (stream, "4100", &column, &first); | |
10439 | show (stream, "4111", &column, &first); | |
10440 | show (stream, "4300", &column, &first); | |
10441 | show (stream, "4400", &column, &first); | |
10442 | show (stream, "4600", &column, &first); | |
10443 | show (stream, "4650", &column, &first); | |
10444 | show (stream, "5000", &column, &first); | |
18ae5d72 EC |
10445 | show (stream, "5200", &column, &first); |
10446 | show (stream, "5230", &column, &first); | |
10447 | show (stream, "5231", &column, &first); | |
10448 | show (stream, "5261", &column, &first); | |
10449 | show (stream, "5721", &column, &first); | |
252b5132 RH |
10450 | show (stream, "6000", &column, &first); |
10451 | show (stream, "8000", &column, &first); | |
10452 | show (stream, "10000", &column, &first); | |
d1cf510e | 10453 | show (stream, "12000", &column, &first); |
2e4acd24 | 10454 | show (stream, "sb1", &column, &first); |
252b5132 RH |
10455 | fputc ('\n', stream); |
10456 | ||
10457 | fprintf (stream, _("\ | |
ec68c924 | 10458 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
252b5132 RH |
10459 | -no-mCPU don't generate code specific to CPU.\n\ |
10460 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
10461 | ||
10462 | first = 1; | |
10463 | ||
10464 | show (stream, "3900", &column, &first); | |
10465 | show (stream, "4010", &column, &first); | |
10466 | show (stream, "4100", &column, &first); | |
10467 | show (stream, "4650", &column, &first); | |
10468 | fputc ('\n', stream); | |
10469 | ||
beae10d5 | 10470 | fprintf (stream, _("\ |
252b5132 RH |
10471 | -mips16 generate mips16 instructions\n\ |
10472 | -no-mips16 do not generate mips16 instructions\n")); | |
beae10d5 | 10473 | fprintf (stream, _("\ |
ca4e0257 RS |
10474 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
10475 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
252b5132 RH |
10476 | -O0 remove unneeded NOPs, do not swap branches\n\ |
10477 | -O remove unneeded NOPs and swap branches\n\ | |
63486801 | 10478 | -n warn about NOPs generated from macros\n\ |
119d663a | 10479 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
252b5132 RH |
10480 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
10481 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
10482 | #ifdef OBJ_ELF | |
beae10d5 | 10483 | fprintf (stream, _("\ |
252b5132 RH |
10484 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
10485 | -non_shared do not generate position independent code\n\ | |
10486 | -xgot assume a 32 bit GOT\n\ | |
34ba82a8 TS |
10487 | -mabi=ABI create ABI conformant object file for:\n")); |
10488 | ||
10489 | first = 1; | |
10490 | ||
10491 | show (stream, "32", &column, &first); | |
10492 | show (stream, "o64", &column, &first); | |
10493 | show (stream, "n32", &column, &first); | |
10494 | show (stream, "64", &column, &first); | |
10495 | show (stream, "eabi", &column, &first); | |
80cc45a5 | 10496 | |
34ba82a8 TS |
10497 | fputc ('\n', stream); |
10498 | ||
10499 | fprintf (stream, _("\ | |
e013f690 TS |
10500 | -32 create o32 ABI object file (default)\n\ |
10501 | -n32 create n32 ABI object file\n\ | |
10502 | -64 create 64 ABI object file\n")); | |
252b5132 RH |
10503 | #endif |
10504 | } | |
10505 | \f | |
10506 | void | |
10507 | mips_init_after_args () | |
10508 | { | |
10509 | /* initialize opcodes */ | |
10510 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10511 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10512 | } |
10513 | ||
10514 | long | |
10515 | md_pcrel_from (fixP) | |
10516 | fixS *fixP; | |
10517 | { | |
10518 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
10519 | && fixP->fx_addsy != (symbolS *) NULL | |
10520 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
10521 | { | |
6478892d TS |
10522 | /* This makes a branch to an undefined symbol be a branch to the |
10523 | current location. */ | |
cb56d3d3 | 10524 | if (mips_pic == EMBEDDED_PIC) |
6478892d | 10525 | return 4; |
cb56d3d3 | 10526 | else |
6478892d | 10527 | return 1; |
252b5132 RH |
10528 | } |
10529 | ||
c9914766 | 10530 | /* Return the address of the delay slot. */ |
252b5132 RH |
10531 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
10532 | } | |
10533 | ||
252b5132 RH |
10534 | /* This is called before the symbol table is processed. In order to |
10535 | work with gcc when using mips-tfile, we must keep all local labels. | |
10536 | However, in other cases, we want to discard them. If we were | |
10537 | called with -g, but we didn't see any debugging information, it may | |
10538 | mean that gcc is smuggling debugging information through to | |
10539 | mips-tfile, in which case we must generate all local labels. */ | |
10540 | ||
10541 | void | |
10542 | mips_frob_file_before_adjust () | |
10543 | { | |
10544 | #ifndef NO_ECOFF_DEBUGGING | |
10545 | if (ECOFF_DEBUGGING | |
10546 | && mips_debug != 0 | |
10547 | && ! ecoff_debugging_seen) | |
10548 | flag_keep_locals = 1; | |
10549 | #endif | |
10550 | } | |
10551 | ||
10552 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10553 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10554 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10555 | explicit use of the %hi modifier. */ | |
10556 | ||
10557 | void | |
10558 | mips_frob_file () | |
10559 | { | |
10560 | struct mips_hi_fixup *l; | |
10561 | ||
10562 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10563 | { | |
10564 | segment_info_type *seginfo; | |
10565 | int pass; | |
10566 | ||
10567 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
10568 | ||
10569 | /* Check quickly whether the next fixup happens to be a matching | |
10570 | %lo. */ | |
10571 | if (l->fixp->fx_next != NULL | |
10572 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
10573 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
10574 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
10575 | continue; | |
10576 | ||
10577 | /* Look through the fixups for this segment for a matching %lo. | |
10578 | When we find one, move the %hi just in front of it. We do | |
10579 | this in two passes. In the first pass, we try to find a | |
10580 | unique %lo. In the second pass, we permit multiple %hi | |
10581 | relocs for a single %lo (this is a GNU extension). */ | |
10582 | seginfo = seg_info (l->seg); | |
10583 | for (pass = 0; pass < 2; pass++) | |
10584 | { | |
10585 | fixS *f, *prev; | |
10586 | ||
10587 | prev = NULL; | |
10588 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10589 | { | |
10590 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10591 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10592 | && f->fx_addsy == l->fixp->fx_addsy | |
10593 | && f->fx_offset == l->fixp->fx_offset | |
10594 | && (pass == 1 | |
10595 | || prev == NULL | |
10596 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
10597 | || prev->fx_addsy != f->fx_addsy | |
10598 | || prev->fx_offset != f->fx_offset)) | |
10599 | { | |
10600 | fixS **pf; | |
10601 | ||
10602 | /* Move l->fixp before f. */ | |
10603 | for (pf = &seginfo->fix_root; | |
10604 | *pf != l->fixp; | |
10605 | pf = &(*pf)->fx_next) | |
10606 | assert (*pf != NULL); | |
10607 | ||
10608 | *pf = l->fixp->fx_next; | |
10609 | ||
10610 | l->fixp->fx_next = f; | |
10611 | if (prev == NULL) | |
10612 | seginfo->fix_root = l->fixp; | |
10613 | else | |
10614 | prev->fx_next = l->fixp; | |
10615 | ||
10616 | break; | |
10617 | } | |
10618 | ||
10619 | prev = f; | |
10620 | } | |
10621 | ||
10622 | if (f != NULL) | |
10623 | break; | |
10624 | ||
10625 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10626 | can leave a %hi without a %lo. */ | |
10627 | if (pass == 1) | |
10628 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10629 | _("Unmatched %%hi reloc")); | |
10630 | #endif | |
10631 | } | |
10632 | } | |
10633 | } | |
10634 | ||
10635 | /* When generating embedded PIC code we need to use a special | |
10636 | relocation to represent the difference of two symbols in the .text | |
10637 | section (switch tables use a difference of this sort). See | |
10638 | include/coff/mips.h for details. This macro checks whether this | |
10639 | fixup requires the special reloc. */ | |
10640 | #define SWITCH_TABLE(fixp) \ | |
10641 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10642 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10643 | && (fixp)->fx_addsy != NULL \ |
10644 | && (fixp)->fx_subsy != NULL \ | |
10645 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10646 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10647 | ||
10648 | /* When generating embedded PIC code we must keep all PC relative | |
10649 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
10650 | to keep relocations for switch table entries. |
10651 | ||
10652 | We may have combined relocations without symbols in the N32/N64 ABI. | |
10653 | We have to prevent gas from dropping them. */ | |
252b5132 | 10654 | |
252b5132 RH |
10655 | int |
10656 | mips_force_relocation (fixp) | |
10657 | fixS *fixp; | |
10658 | { | |
10659 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
10660 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10661 | return 1; | |
10662 | ||
f6688943 TS |
10663 | if (HAVE_NEWABI |
10664 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10665 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10666 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10667 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10668 | return 1; | |
10669 | ||
252b5132 RH |
10670 | return (mips_pic == EMBEDDED_PIC |
10671 | && (fixp->fx_pcrel | |
10672 | || SWITCH_TABLE (fixp) | |
10673 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10674 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
10675 | } | |
10676 | ||
add55e1f RS |
10677 | #ifdef OBJ_ELF |
10678 | static int | |
10679 | mips_need_elf_addend_fixup (fixP) | |
10680 | fixS *fixP; | |
10681 | { | |
2d2bf3e0 CD |
10682 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
10683 | return 1; | |
b25a253c CD |
10684 | if (mips_pic == EMBEDDED_PIC |
10685 | && S_IS_WEAK (fixP->fx_addsy)) | |
10686 | return 1; | |
10687 | if (mips_pic != EMBEDDED_PIC | |
10688 | && (S_IS_WEAK (fixP->fx_addsy) | |
10689 | || S_IS_EXTERN (fixP->fx_addsy)) | |
2d2bf3e0 CD |
10690 | && !S_IS_COMMON (fixP->fx_addsy)) |
10691 | return 1; | |
10692 | if (symbol_used_in_reloc_p (fixP->fx_addsy) | |
10693 | && (((bfd_get_section_flags (stdoutput, | |
10694 | S_GET_SEGMENT (fixP->fx_addsy)) | |
10695 | & SEC_LINK_ONCE) != 0) | |
10696 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
10697 | ".gnu.linkonce", | |
10698 | sizeof (".gnu.linkonce") - 1))) | |
10699 | return 1; | |
10700 | return 0; | |
add55e1f RS |
10701 | } |
10702 | #endif | |
10703 | ||
252b5132 RH |
10704 | /* Apply a fixup to the object file. */ |
10705 | ||
94f592af NC |
10706 | void |
10707 | md_apply_fix3 (fixP, valP, seg) | |
252b5132 | 10708 | fixS *fixP; |
98d3f06f | 10709 | valueT *valP; |
94f592af | 10710 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 10711 | { |
874e8986 | 10712 | bfd_byte *buf; |
98aa84af AM |
10713 | long insn; |
10714 | valueT value; | |
252b5132 RH |
10715 | |
10716 | assert (fixP->fx_size == 4 | |
10717 | || fixP->fx_r_type == BFD_RELOC_16 | |
f6688943 TS |
10718 | || fixP->fx_r_type == BFD_RELOC_32 |
10719 | || fixP->fx_r_type == BFD_RELOC_MIPS_JMP | |
10720 | || fixP->fx_r_type == BFD_RELOC_HI16_S | |
10721 | || fixP->fx_r_type == BFD_RELOC_LO16 | |
10722 | || fixP->fx_r_type == BFD_RELOC_GPREL16 | |
76b3015f | 10723 | || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL |
f6688943 | 10724 | || fixP->fx_r_type == BFD_RELOC_GPREL32 |
252b5132 | 10725 | || fixP->fx_r_type == BFD_RELOC_64 |
f6688943 TS |
10726 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10727 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10728 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST | |
10729 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER | |
10730 | || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP | |
10731 | || fixP->fx_r_type == BFD_RELOC_MIPS_REL16 | |
10732 | || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT | |
252b5132 | 10733 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
438c16b8 TS |
10734 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
10735 | || fixP->fx_r_type == BFD_RELOC_MIPS_JALR); | |
252b5132 | 10736 | |
98d3f06f | 10737 | value = *valP; |
252b5132 RH |
10738 | |
10739 | /* If we aren't adjusting this fixup to be against the section | |
10740 | symbol, we need to adjust the value. */ | |
10741 | #ifdef OBJ_ELF | |
10742 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 10743 | { |
add55e1f | 10744 | if (mips_need_elf_addend_fixup (fixP)) |
98aa84af AM |
10745 | { |
10746 | valueT symval = S_GET_VALUE (fixP->fx_addsy); | |
94f592af | 10747 | |
98aa84af | 10748 | value -= symval; |
add55e1f | 10749 | if (value != 0 && ! fixP->fx_pcrel) |
98aa84af AM |
10750 | { |
10751 | /* In this case, the bfd_install_relocation routine will | |
10752 | incorrectly add the symbol value back in. We just want | |
7461da6e | 10753 | the addend to appear in the object file. */ |
98aa84af | 10754 | value -= symval; |
7461da6e RS |
10755 | |
10756 | /* Make sure the addend is still non-zero. If it became zero | |
10757 | after the last operation, set it to a spurious value and | |
10758 | subtract the same value from the object file's contents. */ | |
10759 | if (value == 0) | |
10760 | { | |
10761 | value = 8; | |
10762 | ||
10763 | /* The in-place addends for LO16 relocations are signed; | |
10764 | leave the matching HI16 in-place addends as zero. */ | |
10765 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
10766 | { | |
10767 | reloc_howto_type *howto; | |
10768 | bfd_vma contents, mask, field; | |
10769 | ||
10770 | howto = bfd_reloc_type_lookup (stdoutput, | |
10771 | fixP->fx_r_type); | |
10772 | ||
10773 | contents = bfd_get_bits (fixP->fx_frag->fr_literal | |
10774 | + fixP->fx_where, | |
10775 | fixP->fx_size * 8, | |
10776 | target_big_endian); | |
10777 | ||
10778 | /* MASK has bits set where the relocation should go. | |
10779 | FIELD is -value, shifted into the appropriate place | |
10780 | for this relocation. */ | |
10781 | mask = 1 << (howto->bitsize - 1); | |
10782 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
10783 | field = (-value >> howto->rightshift) << howto->bitpos; | |
10784 | ||
10785 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
10786 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
10787 | fixP->fx_size * 8, | |
10788 | target_big_endian); | |
10789 | } | |
10790 | } | |
98aa84af AM |
10791 | } |
10792 | } | |
252b5132 | 10793 | |
bb2d6cd7 GK |
10794 | /* This code was generated using trial and error and so is |
10795 | fragile and not trustworthy. If you change it, you should | |
10796 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
10797 | they still pass. */ | |
10798 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
10799 | { | |
10800 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10801 | ||
10802 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
10803 | This gives the right results, but it can't possibly | |
10804 | be the way things are supposed to work. */ | |
cb56d3d3 TS |
10805 | if ((fixP->fx_r_type != BFD_RELOC_16_PCREL |
10806 | && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2) | |
bb2d6cd7 GK |
10807 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
10808 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10809 | } | |
10810 | } | |
10811 | #endif | |
252b5132 | 10812 | |
94f592af | 10813 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */ |
252b5132 RH |
10814 | |
10815 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
10816 | fixP->fx_done = 1; | |
10817 | ||
10818 | switch (fixP->fx_r_type) | |
10819 | { | |
10820 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
10821 | case BFD_RELOC_MIPS_SHIFT5: |
10822 | case BFD_RELOC_MIPS_SHIFT6: | |
10823 | case BFD_RELOC_MIPS_GOT_DISP: | |
10824 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10825 | case BFD_RELOC_MIPS_GOT_OFST: | |
10826 | case BFD_RELOC_MIPS_SUB: | |
10827 | case BFD_RELOC_MIPS_INSERT_A: | |
10828 | case BFD_RELOC_MIPS_INSERT_B: | |
10829 | case BFD_RELOC_MIPS_DELETE: | |
10830 | case BFD_RELOC_MIPS_HIGHEST: | |
10831 | case BFD_RELOC_MIPS_HIGHER: | |
10832 | case BFD_RELOC_MIPS_SCN_DISP: | |
10833 | case BFD_RELOC_MIPS_REL16: | |
10834 | case BFD_RELOC_MIPS_RELGOT: | |
10835 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10836 | case BFD_RELOC_HI16: |
10837 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10838 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10839 | case BFD_RELOC_MIPS_LITERAL: |
10840 | case BFD_RELOC_MIPS_CALL16: | |
10841 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10842 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10843 | case BFD_RELOC_MIPS_GOT_HI16: |
10844 | case BFD_RELOC_MIPS_GOT_LO16: | |
10845 | case BFD_RELOC_MIPS_CALL_HI16: | |
10846 | case BFD_RELOC_MIPS_CALL_LO16: | |
10847 | case BFD_RELOC_MIPS16_GPREL: | |
10848 | if (fixP->fx_pcrel) | |
10849 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10850 | _("Invalid PC relative reloc")); | |
10851 | /* Nothing needed to do. The value comes from the reloc entry */ | |
10852 | break; | |
10853 | ||
10854 | case BFD_RELOC_MIPS16_JMP: | |
10855 | /* We currently always generate a reloc against a symbol, which | |
10856 | means that we don't want an addend even if the symbol is | |
10857 | defined. */ | |
10858 | fixP->fx_addnumber = 0; | |
10859 | break; | |
10860 | ||
10861 | case BFD_RELOC_PCREL_HI16_S: | |
10862 | /* The addend for this is tricky if it is internal, so we just | |
10863 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10864 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10865 | && !fixP->fx_done |
10866 | && value != 0) | |
10867 | break; | |
10868 | if (fixP->fx_addsy | |
10869 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
10870 | { |
10871 | /* For an external symbol adjust by the address to make it | |
10872 | pcrel_offset. We use the address of the RELLO reloc | |
10873 | which follows this one. */ | |
10874 | value += (fixP->fx_next->fx_frag->fr_address | |
10875 | + fixP->fx_next->fx_where); | |
10876 | } | |
e7d556df | 10877 | value = ((value + 0x8000) >> 16) & 0xffff; |
874e8986 | 10878 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10879 | if (target_big_endian) |
10880 | buf += 2; | |
874e8986 | 10881 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10882 | break; |
10883 | ||
10884 | case BFD_RELOC_PCREL_LO16: | |
10885 | /* The addend for this is tricky if it is internal, so we just | |
10886 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10887 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10888 | && !fixP->fx_done |
10889 | && value != 0) | |
10890 | break; | |
10891 | if (fixP->fx_addsy | |
10892 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 | 10893 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
874e8986 | 10894 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10895 | if (target_big_endian) |
10896 | buf += 2; | |
874e8986 | 10897 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10898 | break; |
10899 | ||
10900 | case BFD_RELOC_64: | |
10901 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10902 | extended value if we are only 32 bits. */ | |
10903 | if (fixP->fx_done | |
10904 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10905 | { | |
10906 | if (8 <= sizeof (valueT)) | |
10907 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10908 | value, 8); | |
10909 | else | |
10910 | { | |
10911 | long w1, w2; | |
10912 | long hiv; | |
10913 | ||
10914 | w1 = w2 = fixP->fx_where; | |
10915 | if (target_big_endian) | |
10916 | w1 += 4; | |
10917 | else | |
10918 | w2 += 4; | |
10919 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
10920 | if ((value & 0x80000000) != 0) | |
10921 | hiv = 0xffffffff; | |
10922 | else | |
10923 | hiv = 0; | |
10924 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
10925 | } | |
10926 | } | |
10927 | break; | |
10928 | ||
056350c6 | 10929 | case BFD_RELOC_RVA: |
252b5132 RH |
10930 | case BFD_RELOC_32: |
10931 | /* If we are deleting this reloc entry, we must fill in the | |
10932 | value now. This can happen if we have a .word which is not | |
10933 | resolved when it appears but is later defined. We also need | |
10934 | to fill in the value if this is an embedded PIC switch table | |
10935 | entry. */ | |
10936 | if (fixP->fx_done | |
10937 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10938 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10939 | value, 4); | |
10940 | break; | |
10941 | ||
10942 | case BFD_RELOC_16: | |
10943 | /* If we are deleting this reloc entry, we must fill in the | |
10944 | value now. */ | |
10945 | assert (fixP->fx_size == 2); | |
10946 | if (fixP->fx_done) | |
10947 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10948 | value, 2); | |
10949 | break; | |
10950 | ||
10951 | case BFD_RELOC_LO16: | |
10952 | /* When handling an embedded PIC switch statement, we can wind | |
10953 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10954 | if (fixP->fx_done) | |
10955 | { | |
98aa84af | 10956 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
10957 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10958 | _("relocation overflow")); | |
874e8986 | 10959 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10960 | if (target_big_endian) |
10961 | buf += 2; | |
874e8986 | 10962 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10963 | } |
10964 | break; | |
10965 | ||
10966 | case BFD_RELOC_16_PCREL_S2: | |
cb56d3d3 TS |
10967 | if ((value & 0x3) != 0) |
10968 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10969 | _("Branch to odd address (%lx)"), (long) value); | |
10970 | ||
10971 | /* Fall through. */ | |
10972 | ||
10973 | case BFD_RELOC_16_PCREL: | |
252b5132 RH |
10974 | /* |
10975 | * We need to save the bits in the instruction since fixup_segment() | |
10976 | * might be deleting the relocation entry (i.e., a branch within | |
10977 | * the current segment). | |
10978 | */ | |
bb2d6cd7 GK |
10979 | if (!fixP->fx_done && value != 0) |
10980 | break; | |
10981 | /* If 'value' is zero, the remaining reloc code won't actually | |
10982 | do the store, so it must be done here. This is probably | |
10983 | a bug somewhere. */ | |
b25a253c CD |
10984 | if (!fixP->fx_done |
10985 | && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 | |
10986 | || fixP->fx_addsy == NULL /* ??? */ | |
10987 | || ! S_IS_DEFINED (fixP->fx_addsy))) | |
bb2d6cd7 | 10988 | value -= fixP->fx_frag->fr_address + fixP->fx_where; |
bdaaa2e1 | 10989 | |
98aa84af | 10990 | value = (offsetT) value >> 2; |
252b5132 RH |
10991 | |
10992 | /* update old instruction data */ | |
874e8986 | 10993 | buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal); |
252b5132 RH |
10994 | if (target_big_endian) |
10995 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
10996 | else | |
10997 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
10998 | ||
98aa84af | 10999 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
11000 | insn |= value & 0xffff; |
11001 | else | |
11002 | { | |
11003 | /* The branch offset is too large. If this is an | |
11004 | unconditional branch, and we are not generating PIC code, | |
11005 | we can convert it to an absolute jump instruction. */ | |
11006 | if (mips_pic == NO_PIC | |
11007 | && fixP->fx_done | |
11008 | && fixP->fx_frag->fr_address >= text_section->vma | |
11009 | && (fixP->fx_frag->fr_address | |
11010 | < text_section->vma + text_section->_raw_size) | |
11011 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11012 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11013 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
11014 | { | |
11015 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
11016 | insn = 0x0c000000; /* jal */ | |
11017 | else | |
11018 | insn = 0x08000000; /* j */ | |
11019 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11020 | fixP->fx_done = 0; | |
11021 | fixP->fx_addsy = section_symbol (text_section); | |
11022 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
11023 | } | |
11024 | else | |
11025 | { | |
11026 | /* FIXME. It would be possible in principle to handle | |
11027 | conditional branches which overflow. They could be | |
11028 | transformed into a branch around a jump. This would | |
11029 | require setting up variant frags for each different | |
11030 | branch type. The native MIPS assembler attempts to | |
11031 | handle these cases, but it appears to do it | |
11032 | incorrectly. */ | |
11033 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11034 | _("Branch out of range")); | |
11035 | } | |
11036 | } | |
11037 | ||
11038 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
11039 | break; | |
11040 | ||
11041 | case BFD_RELOC_VTABLE_INHERIT: | |
11042 | fixP->fx_done = 0; | |
11043 | if (fixP->fx_addsy | |
11044 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11045 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11046 | S_SET_WEAK (fixP->fx_addsy); | |
11047 | break; | |
11048 | ||
11049 | case BFD_RELOC_VTABLE_ENTRY: | |
11050 | fixP->fx_done = 0; | |
11051 | break; | |
11052 | ||
11053 | default: | |
11054 | internalError (); | |
11055 | } | |
252b5132 RH |
11056 | } |
11057 | ||
11058 | #if 0 | |
11059 | void | |
11060 | printInsn (oc) | |
11061 | unsigned long oc; | |
11062 | { | |
11063 | const struct mips_opcode *p; | |
11064 | int treg, sreg, dreg, shamt; | |
11065 | short imm; | |
11066 | const char *args; | |
11067 | int i; | |
11068 | ||
11069 | for (i = 0; i < NUMOPCODES; ++i) | |
11070 | { | |
11071 | p = &mips_opcodes[i]; | |
11072 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11073 | { | |
11074 | printf ("%08lx %s\t", oc, p->name); | |
11075 | treg = (oc >> 16) & 0x1f; | |
11076 | sreg = (oc >> 21) & 0x1f; | |
11077 | dreg = (oc >> 11) & 0x1f; | |
11078 | shamt = (oc >> 6) & 0x1f; | |
11079 | imm = oc; | |
11080 | for (args = p->args;; ++args) | |
11081 | { | |
11082 | switch (*args) | |
11083 | { | |
11084 | case '\0': | |
11085 | printf ("\n"); | |
11086 | break; | |
11087 | ||
11088 | case ',': | |
11089 | case '(': | |
11090 | case ')': | |
11091 | printf ("%c", *args); | |
11092 | continue; | |
11093 | ||
11094 | case 'r': | |
11095 | assert (treg == sreg); | |
11096 | printf ("$%d,$%d", treg, sreg); | |
11097 | continue; | |
11098 | ||
11099 | case 'd': | |
11100 | case 'G': | |
11101 | printf ("$%d", dreg); | |
11102 | continue; | |
11103 | ||
11104 | case 't': | |
11105 | case 'E': | |
11106 | printf ("$%d", treg); | |
11107 | continue; | |
11108 | ||
11109 | case 'k': | |
11110 | printf ("0x%x", treg); | |
11111 | continue; | |
11112 | ||
11113 | case 'b': | |
11114 | case 's': | |
11115 | printf ("$%d", sreg); | |
11116 | continue; | |
11117 | ||
11118 | case 'a': | |
11119 | printf ("0x%08lx", oc & 0x1ffffff); | |
11120 | continue; | |
11121 | ||
11122 | case 'i': | |
11123 | case 'j': | |
11124 | case 'o': | |
11125 | case 'u': | |
11126 | printf ("%d", imm); | |
11127 | continue; | |
11128 | ||
11129 | case '<': | |
11130 | case '>': | |
11131 | printf ("$%d", shamt); | |
11132 | continue; | |
11133 | ||
11134 | default: | |
11135 | internalError (); | |
11136 | } | |
11137 | break; | |
11138 | } | |
11139 | return; | |
11140 | } | |
11141 | } | |
11142 | printf (_("%08lx UNDEFINED\n"), oc); | |
11143 | } | |
11144 | #endif | |
11145 | ||
11146 | static symbolS * | |
11147 | get_symbol () | |
11148 | { | |
11149 | int c; | |
11150 | char *name; | |
11151 | symbolS *p; | |
11152 | ||
11153 | name = input_line_pointer; | |
11154 | c = get_symbol_end (); | |
11155 | p = (symbolS *) symbol_find_or_make (name); | |
11156 | *input_line_pointer = c; | |
11157 | return p; | |
11158 | } | |
11159 | ||
11160 | /* Align the current frag to a given power of two. The MIPS assembler | |
11161 | also automatically adjusts any preceding label. */ | |
11162 | ||
11163 | static void | |
11164 | mips_align (to, fill, label) | |
11165 | int to; | |
11166 | int fill; | |
11167 | symbolS *label; | |
11168 | { | |
11169 | mips_emit_delays (false); | |
11170 | frag_align (to, fill, 0); | |
11171 | record_alignment (now_seg, to); | |
11172 | if (label != NULL) | |
11173 | { | |
11174 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11175 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11176 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11177 | } | |
11178 | } | |
11179 | ||
11180 | /* Align to a given power of two. .align 0 turns off the automatic | |
11181 | alignment used by the data creating pseudo-ops. */ | |
11182 | ||
11183 | static void | |
11184 | s_align (x) | |
43841e91 | 11185 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11186 | { |
11187 | register int temp; | |
11188 | register long temp_fill; | |
11189 | long max_alignment = 15; | |
11190 | ||
11191 | /* | |
11192 | ||
11193 | o Note that the assembler pulls down any immediately preceeding label | |
11194 | to the aligned address. | |
11195 | o It's not documented but auto alignment is reinstated by | |
11196 | a .align pseudo instruction. | |
11197 | o Note also that after auto alignment is turned off the mips assembler | |
11198 | issues an error on attempt to assemble an improperly aligned data item. | |
11199 | We don't. | |
11200 | ||
11201 | */ | |
11202 | ||
11203 | temp = get_absolute_expression (); | |
11204 | if (temp > max_alignment) | |
11205 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11206 | else if (temp < 0) | |
11207 | { | |
11208 | as_warn (_("Alignment negative: 0 assumed.")); | |
11209 | temp = 0; | |
11210 | } | |
11211 | if (*input_line_pointer == ',') | |
11212 | { | |
f9419b05 | 11213 | ++input_line_pointer; |
252b5132 RH |
11214 | temp_fill = get_absolute_expression (); |
11215 | } | |
11216 | else | |
11217 | temp_fill = 0; | |
11218 | if (temp) | |
11219 | { | |
11220 | auto_align = 1; | |
11221 | mips_align (temp, (int) temp_fill, | |
11222 | insn_labels != NULL ? insn_labels->label : NULL); | |
11223 | } | |
11224 | else | |
11225 | { | |
11226 | auto_align = 0; | |
11227 | } | |
11228 | ||
11229 | demand_empty_rest_of_line (); | |
11230 | } | |
11231 | ||
11232 | void | |
11233 | mips_flush_pending_output () | |
11234 | { | |
11235 | mips_emit_delays (false); | |
11236 | mips_clear_insn_labels (); | |
11237 | } | |
11238 | ||
11239 | static void | |
11240 | s_change_sec (sec) | |
11241 | int sec; | |
11242 | { | |
11243 | segT seg; | |
11244 | ||
11245 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11246 | .sdata and .sbss sections. We change the .data and .rdata | |
11247 | pseudo-ops to use .sdata. */ | |
11248 | if (mips_pic == EMBEDDED_PIC | |
11249 | && (sec == 'd' || sec == 'r')) | |
11250 | sec = 's'; | |
11251 | ||
11252 | #ifdef OBJ_ELF | |
11253 | /* The ELF backend needs to know that we are changing sections, so | |
11254 | that .previous works correctly. We could do something like check | |
b6ff326e | 11255 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11256 | as it would not be appropriate to use it in the section changing |
11257 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11258 | This should be cleaner, somehow. */ | |
11259 | obj_elf_section_change_hook (); | |
11260 | #endif | |
11261 | ||
11262 | mips_emit_delays (false); | |
11263 | switch (sec) | |
11264 | { | |
11265 | case 't': | |
11266 | s_text (0); | |
11267 | break; | |
11268 | case 'd': | |
11269 | s_data (0); | |
11270 | break; | |
11271 | case 'b': | |
11272 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11273 | demand_empty_rest_of_line (); | |
11274 | break; | |
11275 | ||
11276 | case 'r': | |
11277 | if (USE_GLOBAL_POINTER_OPT) | |
11278 | { | |
11279 | seg = subseg_new (RDATA_SECTION_NAME, | |
11280 | (subsegT) get_absolute_expression ()); | |
11281 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11282 | { | |
11283 | bfd_set_section_flags (stdoutput, seg, | |
11284 | (SEC_ALLOC | |
11285 | | SEC_LOAD | |
11286 | | SEC_READONLY | |
11287 | | SEC_RELOC | |
11288 | | SEC_DATA)); | |
11289 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11290 | record_alignment (seg, 4); |
252b5132 RH |
11291 | } |
11292 | demand_empty_rest_of_line (); | |
11293 | } | |
11294 | else | |
11295 | { | |
11296 | as_bad (_("No read only data section in this object file format")); | |
11297 | demand_empty_rest_of_line (); | |
11298 | return; | |
11299 | } | |
11300 | break; | |
11301 | ||
11302 | case 's': | |
11303 | if (USE_GLOBAL_POINTER_OPT) | |
11304 | { | |
11305 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11306 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11307 | { | |
11308 | bfd_set_section_flags (stdoutput, seg, | |
11309 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11310 | | SEC_DATA); | |
11311 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11312 | record_alignment (seg, 4); |
252b5132 RH |
11313 | } |
11314 | demand_empty_rest_of_line (); | |
11315 | break; | |
11316 | } | |
11317 | else | |
11318 | { | |
11319 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11320 | demand_empty_rest_of_line (); | |
11321 | return; | |
11322 | } | |
11323 | } | |
11324 | ||
11325 | auto_align = 1; | |
11326 | } | |
11327 | ||
11328 | void | |
11329 | mips_enable_auto_align () | |
11330 | { | |
11331 | auto_align = 1; | |
11332 | } | |
11333 | ||
11334 | static void | |
11335 | s_cons (log_size) | |
11336 | int log_size; | |
11337 | { | |
11338 | symbolS *label; | |
11339 | ||
11340 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11341 | mips_emit_delays (false); | |
11342 | if (log_size > 0 && auto_align) | |
11343 | mips_align (log_size, 0, label); | |
11344 | mips_clear_insn_labels (); | |
11345 | cons (1 << log_size); | |
11346 | } | |
11347 | ||
11348 | static void | |
11349 | s_float_cons (type) | |
11350 | int type; | |
11351 | { | |
11352 | symbolS *label; | |
11353 | ||
11354 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11355 | ||
11356 | mips_emit_delays (false); | |
11357 | ||
11358 | if (auto_align) | |
49309057 ILT |
11359 | { |
11360 | if (type == 'd') | |
11361 | mips_align (3, 0, label); | |
11362 | else | |
11363 | mips_align (2, 0, label); | |
11364 | } | |
252b5132 RH |
11365 | |
11366 | mips_clear_insn_labels (); | |
11367 | ||
11368 | float_cons (type); | |
11369 | } | |
11370 | ||
11371 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11372 | permitted to say | |
11373 | .globl foo .text | |
11374 | where foo is an undefined symbol, to mean that foo should be | |
11375 | considered to be the address of a function. */ | |
11376 | ||
11377 | static void | |
11378 | s_mips_globl (x) | |
43841e91 | 11379 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11380 | { |
11381 | char *name; | |
11382 | int c; | |
11383 | symbolS *symbolP; | |
11384 | flagword flag; | |
11385 | ||
11386 | name = input_line_pointer; | |
11387 | c = get_symbol_end (); | |
11388 | symbolP = symbol_find_or_make (name); | |
11389 | *input_line_pointer = c; | |
11390 | SKIP_WHITESPACE (); | |
11391 | ||
11392 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11393 | being a function is apparently labelled as being an object. */ | |
11394 | flag = BSF_OBJECT; | |
11395 | ||
11396 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11397 | { | |
11398 | char *secname; | |
11399 | asection *sec; | |
11400 | ||
11401 | secname = input_line_pointer; | |
11402 | c = get_symbol_end (); | |
11403 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11404 | if (sec == NULL) | |
11405 | as_bad (_("%s: no such section"), secname); | |
11406 | *input_line_pointer = c; | |
11407 | ||
11408 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11409 | flag = BSF_FUNCTION; | |
11410 | } | |
11411 | ||
49309057 | 11412 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11413 | |
11414 | S_SET_EXTERNAL (symbolP); | |
11415 | demand_empty_rest_of_line (); | |
11416 | } | |
11417 | ||
11418 | static void | |
11419 | s_option (x) | |
43841e91 | 11420 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11421 | { |
11422 | char *opt; | |
11423 | char c; | |
11424 | ||
11425 | opt = input_line_pointer; | |
11426 | c = get_symbol_end (); | |
11427 | ||
11428 | if (*opt == 'O') | |
11429 | { | |
11430 | /* FIXME: What does this mean? */ | |
11431 | } | |
11432 | else if (strncmp (opt, "pic", 3) == 0) | |
11433 | { | |
11434 | int i; | |
11435 | ||
11436 | i = atoi (opt + 3); | |
11437 | if (i == 0) | |
11438 | mips_pic = NO_PIC; | |
11439 | else if (i == 2) | |
11440 | mips_pic = SVR4_PIC; | |
11441 | else | |
11442 | as_bad (_(".option pic%d not supported"), i); | |
11443 | ||
11444 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11445 | { | |
11446 | if (g_switch_seen && g_switch_value != 0) | |
11447 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11448 | g_switch_value = 0; | |
11449 | bfd_set_gp_size (stdoutput, 0); | |
11450 | } | |
11451 | } | |
11452 | else | |
11453 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11454 | ||
11455 | *input_line_pointer = c; | |
11456 | demand_empty_rest_of_line (); | |
11457 | } | |
11458 | ||
11459 | /* This structure is used to hold a stack of .set values. */ | |
11460 | ||
e972090a NC |
11461 | struct mips_option_stack |
11462 | { | |
252b5132 RH |
11463 | struct mips_option_stack *next; |
11464 | struct mips_set_options options; | |
11465 | }; | |
11466 | ||
11467 | static struct mips_option_stack *mips_opts_stack; | |
11468 | ||
11469 | /* Handle the .set pseudo-op. */ | |
11470 | ||
11471 | static void | |
11472 | s_mipsset (x) | |
43841e91 | 11473 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11474 | { |
11475 | char *name = input_line_pointer, ch; | |
11476 | ||
11477 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11478 | ++input_line_pointer; |
252b5132 RH |
11479 | ch = *input_line_pointer; |
11480 | *input_line_pointer = '\0'; | |
11481 | ||
11482 | if (strcmp (name, "reorder") == 0) | |
11483 | { | |
11484 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11485 | { | |
11486 | /* If we still have pending nops, we can discard them. The | |
11487 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11488 | needed. */ |
252b5132 RH |
11489 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11490 | * (mips_opts.mips16 ? 2 : 4)); | |
11491 | prev_nop_frag = NULL; | |
11492 | } | |
11493 | mips_opts.noreorder = 0; | |
11494 | } | |
11495 | else if (strcmp (name, "noreorder") == 0) | |
11496 | { | |
11497 | mips_emit_delays (true); | |
11498 | mips_opts.noreorder = 1; | |
11499 | mips_any_noreorder = 1; | |
11500 | } | |
11501 | else if (strcmp (name, "at") == 0) | |
11502 | { | |
11503 | mips_opts.noat = 0; | |
11504 | } | |
11505 | else if (strcmp (name, "noat") == 0) | |
11506 | { | |
11507 | mips_opts.noat = 1; | |
11508 | } | |
11509 | else if (strcmp (name, "macro") == 0) | |
11510 | { | |
11511 | mips_opts.warn_about_macros = 0; | |
11512 | } | |
11513 | else if (strcmp (name, "nomacro") == 0) | |
11514 | { | |
11515 | if (mips_opts.noreorder == 0) | |
11516 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11517 | mips_opts.warn_about_macros = 1; | |
11518 | } | |
11519 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11520 | { | |
11521 | mips_opts.nomove = 0; | |
11522 | } | |
11523 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11524 | { | |
11525 | mips_opts.nomove = 1; | |
11526 | } | |
11527 | else if (strcmp (name, "bopt") == 0) | |
11528 | { | |
11529 | mips_opts.nobopt = 0; | |
11530 | } | |
11531 | else if (strcmp (name, "nobopt") == 0) | |
11532 | { | |
11533 | mips_opts.nobopt = 1; | |
11534 | } | |
11535 | else if (strcmp (name, "mips16") == 0 | |
11536 | || strcmp (name, "MIPS-16") == 0) | |
11537 | mips_opts.mips16 = 1; | |
11538 | else if (strcmp (name, "nomips16") == 0 | |
11539 | || strcmp (name, "noMIPS-16") == 0) | |
11540 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11541 | else if (strcmp (name, "mips3d") == 0) |
11542 | mips_opts.ase_mips3d = 1; | |
11543 | else if (strcmp (name, "nomips3d") == 0) | |
11544 | mips_opts.ase_mips3d = 0; | |
252b5132 RH |
11545 | else if (strncmp (name, "mips", 4) == 0) |
11546 | { | |
11547 | int isa; | |
11548 | ||
11549 | /* Permit the user to change the ISA on the fly. Needless to | |
11550 | say, misuse can cause serious problems. */ | |
11551 | isa = atoi (name + 4); | |
553178e4 | 11552 | switch (isa) |
98d3f06f KH |
11553 | { |
11554 | case 0: | |
11555 | mips_opts.gp32 = file_mips_gp32; | |
11556 | mips_opts.fp32 = file_mips_fp32; | |
11557 | mips_opts.abi = file_mips_abi; | |
11558 | break; | |
11559 | case 1: | |
11560 | case 2: | |
11561 | case 32: | |
11562 | mips_opts.gp32 = 1; | |
11563 | mips_opts.fp32 = 1; | |
11564 | break; | |
11565 | case 3: | |
11566 | case 4: | |
11567 | case 5: | |
11568 | case 64: | |
11569 | /* Loosen ABI register width restriction. */ | |
11570 | if (mips_opts.abi == O32_ABI) | |
11571 | mips_opts.abi = NO_ABI; | |
11572 | mips_opts.gp32 = 0; | |
11573 | mips_opts.fp32 = 0; | |
11574 | break; | |
11575 | default: | |
11576 | as_bad (_("unknown ISA level %s"), name + 4); | |
11577 | break; | |
11578 | } | |
553178e4 | 11579 | |
e7af610e | 11580 | switch (isa) |
98d3f06f KH |
11581 | { |
11582 | case 0: mips_opts.isa = file_mips_isa; break; | |
11583 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
11584 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
11585 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
11586 | case 4: mips_opts.isa = ISA_MIPS4; break; | |
11587 | case 5: mips_opts.isa = ISA_MIPS5; break; | |
11588 | case 32: mips_opts.isa = ISA_MIPS32; break; | |
11589 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
11590 | default: as_bad (_("unknown ISA level %s"), name + 4); break; | |
11591 | } | |
252b5132 RH |
11592 | } |
11593 | else if (strcmp (name, "autoextend") == 0) | |
11594 | mips_opts.noautoextend = 0; | |
11595 | else if (strcmp (name, "noautoextend") == 0) | |
11596 | mips_opts.noautoextend = 1; | |
11597 | else if (strcmp (name, "push") == 0) | |
11598 | { | |
11599 | struct mips_option_stack *s; | |
11600 | ||
11601 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11602 | s->next = mips_opts_stack; | |
11603 | s->options = mips_opts; | |
11604 | mips_opts_stack = s; | |
11605 | } | |
11606 | else if (strcmp (name, "pop") == 0) | |
11607 | { | |
11608 | struct mips_option_stack *s; | |
11609 | ||
11610 | s = mips_opts_stack; | |
11611 | if (s == NULL) | |
11612 | as_bad (_(".set pop with no .set push")); | |
11613 | else | |
11614 | { | |
11615 | /* If we're changing the reorder mode we need to handle | |
11616 | delay slots correctly. */ | |
11617 | if (s->options.noreorder && ! mips_opts.noreorder) | |
11618 | mips_emit_delays (true); | |
11619 | else if (! s->options.noreorder && mips_opts.noreorder) | |
11620 | { | |
11621 | if (prev_nop_frag != NULL) | |
11622 | { | |
11623 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11624 | * (mips_opts.mips16 ? 2 : 4)); | |
11625 | prev_nop_frag = NULL; | |
11626 | } | |
11627 | } | |
11628 | ||
11629 | mips_opts = s->options; | |
11630 | mips_opts_stack = s->next; | |
11631 | free (s); | |
11632 | } | |
11633 | } | |
11634 | else | |
11635 | { | |
11636 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11637 | } | |
11638 | *input_line_pointer = ch; | |
11639 | demand_empty_rest_of_line (); | |
11640 | } | |
11641 | ||
11642 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11643 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11644 | ||
11645 | static void | |
11646 | s_abicalls (ignore) | |
43841e91 | 11647 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11648 | { |
11649 | mips_pic = SVR4_PIC; | |
11650 | if (USE_GLOBAL_POINTER_OPT) | |
11651 | { | |
11652 | if (g_switch_seen && g_switch_value != 0) | |
11653 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11654 | g_switch_value = 0; | |
11655 | } | |
11656 | bfd_set_gp_size (stdoutput, 0); | |
11657 | demand_empty_rest_of_line (); | |
11658 | } | |
11659 | ||
11660 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11661 | PIC code. It sets the $gp register for the function based on the | |
11662 | function address, which is in the register named in the argument. | |
11663 | This uses a relocation against _gp_disp, which is handled specially | |
11664 | by the linker. The result is: | |
11665 | lui $gp,%hi(_gp_disp) | |
11666 | addiu $gp,$gp,%lo(_gp_disp) | |
11667 | addu $gp,$gp,.cpload argument | |
11668 | The .cpload argument is normally $25 == $t9. */ | |
11669 | ||
11670 | static void | |
11671 | s_cpload (ignore) | |
43841e91 | 11672 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11673 | { |
11674 | expressionS ex; | |
11675 | int icnt = 0; | |
11676 | ||
6478892d TS |
11677 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11678 | .cpload is ignored. */ | |
11679 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11680 | { |
11681 | s_ignore (0); | |
11682 | return; | |
11683 | } | |
11684 | ||
d3ecfc59 | 11685 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11686 | if (mips_opts.noreorder == 0) |
11687 | as_warn (_(".cpload not in noreorder section")); | |
11688 | ||
11689 | ex.X_op = O_symbol; | |
11690 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11691 | ex.X_op_symbol = NULL; | |
11692 | ex.X_add_number = 0; | |
11693 | ||
11694 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11695 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11696 | |
c9914766 TS |
11697 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
11698 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", | |
11699 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16); | |
252b5132 RH |
11700 | |
11701 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
c9914766 | 11702 | mips_gp_register, mips_gp_register, tc_get_register (0)); |
252b5132 RH |
11703 | |
11704 | demand_empty_rest_of_line (); | |
11705 | } | |
11706 | ||
6478892d TS |
11707 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11708 | .cpsetup $reg1, offset|$reg2, label | |
11709 | ||
11710 | If offset is given, this results in: | |
11711 | sd $gp, offset($sp) | |
956cd1d6 TS |
11712 | lui $gp, %hi(%neg(%gp_rel(label))) |
11713 | daddiu $gp, $gp, %lo(%neg(%gp_rel(label))) | |
6478892d TS |
11714 | addu $gp, $gp, $reg1 |
11715 | ||
11716 | If $reg2 is given, this results in: | |
11717 | daddu $reg2, $gp, $0 | |
956cd1d6 TS |
11718 | lui $gp, %hi(%neg(%gp_rel(label))) |
11719 | daddiu $gp, $gp, %lo(%neg(%gp_rel(label))) | |
6478892d TS |
11720 | addu $gp, $gp, $reg1 |
11721 | */ | |
11722 | static void | |
11723 | s_cpsetup (ignore) | |
11724 | int ignore ATTRIBUTE_UNUSED; | |
11725 | { | |
11726 | expressionS ex_off; | |
11727 | expressionS ex_sym; | |
11728 | int reg1; | |
11729 | int icnt = 0; | |
11730 | char *sym; | |
11731 | ||
8586fc66 | 11732 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11733 | We also need NewABI support. */ |
11734 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11735 | { | |
11736 | s_ignore (0); | |
11737 | return; | |
11738 | } | |
11739 | ||
11740 | reg1 = tc_get_register (0); | |
11741 | SKIP_WHITESPACE (); | |
11742 | if (*input_line_pointer != ',') | |
11743 | { | |
11744 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11745 | return; | |
11746 | } | |
11747 | else | |
11748 | input_line_pointer++; | |
11749 | SKIP_WHITESPACE (); | |
11750 | if (*input_line_pointer == '$') | |
11751 | mips_cpreturn_register = tc_get_register (0); | |
11752 | else | |
11753 | mips_cpreturn_offset = get_absolute_expression (); | |
11754 | SKIP_WHITESPACE (); | |
11755 | if (*input_line_pointer != ',') | |
11756 | { | |
11757 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11758 | return; | |
11759 | } | |
11760 | else | |
f9419b05 | 11761 | ++input_line_pointer; |
6478892d TS |
11762 | SKIP_WHITESPACE (); |
11763 | sym = input_line_pointer; | |
11764 | while (ISALNUM (*input_line_pointer)) | |
f9419b05 | 11765 | ++input_line_pointer; |
6478892d TS |
11766 | *input_line_pointer = 0; |
11767 | ||
11768 | ex_sym.X_op = O_symbol; | |
11769 | ex_sym.X_add_symbol = symbol_find_or_make (sym); | |
11770 | ex_sym.X_op_symbol = NULL; | |
11771 | ex_sym.X_add_number = 0; | |
11772 | ||
11773 | if (mips_cpreturn_register == -1) | |
11774 | { | |
11775 | ex_off.X_op = O_constant; | |
11776 | ex_off.X_add_symbol = NULL; | |
11777 | ex_off.X_op_symbol = NULL; | |
11778 | ex_off.X_add_number = mips_cpreturn_offset; | |
11779 | ||
11780 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
11781 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11782 | } | |
11783 | else | |
11784 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11785 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
11786 | ||
11787 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, | |
11788 | (int) BFD_RELOC_GPREL16); | |
8586fc66 TS |
11789 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
11790 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_HI16_S); | |
6478892d TS |
11791 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", |
11792 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
8586fc66 TS |
11793 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
11794 | fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_LO16); | |
11795 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
11796 | HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t", | |
11797 | mips_gp_register, mips_gp_register, reg1); | |
6478892d TS |
11798 | |
11799 | demand_empty_rest_of_line (); | |
11800 | } | |
11801 | ||
11802 | static void | |
11803 | s_cplocal (ignore) | |
11804 | int ignore ATTRIBUTE_UNUSED; | |
11805 | { | |
11806 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11807 | .cplocal is ignored. */ | |
11808 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11809 | { | |
11810 | s_ignore (0); | |
11811 | return; | |
11812 | } | |
11813 | ||
11814 | mips_gp_register = tc_get_register (0); | |
11815 | } | |
11816 | ||
252b5132 RH |
11817 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11818 | offset from $sp. The offset is remembered, and after making a PIC | |
11819 | call $gp is restored from that location. */ | |
11820 | ||
11821 | static void | |
11822 | s_cprestore (ignore) | |
43841e91 | 11823 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11824 | { |
11825 | expressionS ex; | |
11826 | int icnt = 0; | |
11827 | ||
6478892d | 11828 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11829 | .cprestore is ignored. */ |
6478892d | 11830 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11831 | { |
11832 | s_ignore (0); | |
11833 | return; | |
11834 | } | |
11835 | ||
11836 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11837 | mips_cprestore_valid = 1; |
252b5132 RH |
11838 | |
11839 | ex.X_op = O_constant; | |
11840 | ex.X_add_symbol = NULL; | |
11841 | ex.X_op_symbol = NULL; | |
11842 | ex.X_add_number = mips_cprestore_offset; | |
11843 | ||
c9914766 TS |
11844 | macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd", |
11845 | "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
252b5132 RH |
11846 | |
11847 | demand_empty_rest_of_line (); | |
11848 | } | |
11849 | ||
6478892d TS |
11850 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
11851 | was given in the preceeding .gpsetup, it results in: | |
11852 | ld $gp, offset($sp) | |
76b3015f | 11853 | |
6478892d TS |
11854 | If a register $reg2 was given there, it results in: |
11855 | daddiu $gp, $gp, $reg2 | |
11856 | */ | |
11857 | static void | |
11858 | s_cpreturn (ignore) | |
11859 | int ignore ATTRIBUTE_UNUSED; | |
11860 | { | |
11861 | expressionS ex; | |
11862 | int icnt = 0; | |
11863 | ||
11864 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11865 | We also need NewABI support. */ | |
11866 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11867 | { | |
11868 | s_ignore (0); | |
11869 | return; | |
11870 | } | |
11871 | ||
11872 | if (mips_cpreturn_register == -1) | |
11873 | { | |
11874 | ex.X_op = O_constant; | |
11875 | ex.X_add_symbol = NULL; | |
11876 | ex.X_op_symbol = NULL; | |
11877 | ex.X_add_number = mips_cpreturn_offset; | |
11878 | ||
11879 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
11880 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11881 | } | |
11882 | else | |
11883 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11884 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
11885 | ||
11886 | demand_empty_rest_of_line (); | |
11887 | } | |
11888 | ||
11889 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11890 | code. It sets the offset to use in gp_rel relocations. */ | |
11891 | ||
11892 | static void | |
11893 | s_gpvalue (ignore) | |
11894 | int ignore ATTRIBUTE_UNUSED; | |
11895 | { | |
11896 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11897 | We also need NewABI support. */ | |
11898 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11899 | { | |
11900 | s_ignore (0); | |
11901 | return; | |
11902 | } | |
11903 | ||
def2e0dd | 11904 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
11905 | |
11906 | demand_empty_rest_of_line (); | |
11907 | } | |
11908 | ||
252b5132 RH |
11909 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11910 | code. It generates a 32 bit GP relative reloc. */ | |
11911 | ||
11912 | static void | |
11913 | s_gpword (ignore) | |
43841e91 | 11914 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11915 | { |
11916 | symbolS *label; | |
11917 | expressionS ex; | |
11918 | char *p; | |
11919 | ||
11920 | /* When not generating PIC code, this is treated as .word. */ | |
11921 | if (mips_pic != SVR4_PIC) | |
11922 | { | |
11923 | s_cons (2); | |
11924 | return; | |
11925 | } | |
11926 | ||
11927 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11928 | mips_emit_delays (true); | |
11929 | if (auto_align) | |
11930 | mips_align (2, 0, label); | |
11931 | mips_clear_insn_labels (); | |
11932 | ||
11933 | expression (&ex); | |
11934 | ||
11935 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
11936 | { | |
11937 | as_bad (_("Unsupported use of .gpword")); | |
11938 | ignore_rest_of_line (); | |
11939 | } | |
11940 | ||
11941 | p = frag_more (4); | |
11942 | md_number_to_chars (p, (valueT) 0, 4); | |
c9914766 | 11943 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false, |
cdf6fd85 | 11944 | BFD_RELOC_GPREL32); |
252b5132 RH |
11945 | |
11946 | demand_empty_rest_of_line (); | |
11947 | } | |
11948 | ||
11949 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
11950 | tables in SVR4 PIC code. */ | |
11951 | ||
11952 | static void | |
11953 | s_cpadd (ignore) | |
43841e91 | 11954 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11955 | { |
11956 | int icnt = 0; | |
11957 | int reg; | |
11958 | ||
6478892d TS |
11959 | /* This is ignored when not generating SVR4 PIC code or if this is NewABI |
11960 | code. */ | |
11961 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11962 | { |
11963 | s_ignore (0); | |
11964 | return; | |
11965 | } | |
11966 | ||
11967 | /* Add $gp to the register named as an argument. */ | |
11968 | reg = tc_get_register (0); | |
11969 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 11970 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 11971 | "d,v,t", reg, reg, mips_gp_register); |
252b5132 | 11972 | |
bdaaa2e1 | 11973 | demand_empty_rest_of_line (); |
252b5132 RH |
11974 | } |
11975 | ||
11976 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
11977 | mips16 mode. This permits the linker to handle them specially, | |
11978 | such as generating jalx instructions when needed. We also make | |
11979 | them odd for the duration of the assembly, in order to generate the | |
11980 | right sort of code. We will make them even in the adjust_symtab | |
11981 | routine, while leaving them marked. This is convenient for the | |
11982 | debugger and the disassembler. The linker knows to make them odd | |
11983 | again. */ | |
11984 | ||
11985 | static void | |
11986 | s_insn (ignore) | |
43841e91 | 11987 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 11988 | { |
f9419b05 | 11989 | mips16_mark_labels (); |
252b5132 RH |
11990 | |
11991 | demand_empty_rest_of_line (); | |
11992 | } | |
11993 | ||
11994 | /* Handle a .stabn directive. We need these in order to mark a label | |
11995 | as being a mips16 text label correctly. Sometimes the compiler | |
11996 | will emit a label, followed by a .stabn, and then switch sections. | |
11997 | If the label and .stabn are in mips16 mode, then the label is | |
11998 | really a mips16 text label. */ | |
11999 | ||
12000 | static void | |
12001 | s_mips_stab (type) | |
12002 | int type; | |
12003 | { | |
f9419b05 | 12004 | if (type == 'n') |
252b5132 RH |
12005 | mips16_mark_labels (); |
12006 | ||
12007 | s_stab (type); | |
12008 | } | |
12009 | ||
12010 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12011 | */ | |
12012 | ||
12013 | static void | |
12014 | s_mips_weakext (ignore) | |
43841e91 | 12015 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12016 | { |
12017 | char *name; | |
12018 | int c; | |
12019 | symbolS *symbolP; | |
12020 | expressionS exp; | |
12021 | ||
12022 | name = input_line_pointer; | |
12023 | c = get_symbol_end (); | |
12024 | symbolP = symbol_find_or_make (name); | |
12025 | S_SET_WEAK (symbolP); | |
12026 | *input_line_pointer = c; | |
12027 | ||
12028 | SKIP_WHITESPACE (); | |
12029 | ||
12030 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12031 | { | |
12032 | if (S_IS_DEFINED (symbolP)) | |
12033 | { | |
956cd1d6 | 12034 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12035 | S_GET_NAME (symbolP)); |
12036 | ignore_rest_of_line (); | |
12037 | return; | |
12038 | } | |
bdaaa2e1 | 12039 | |
252b5132 RH |
12040 | if (*input_line_pointer == ',') |
12041 | { | |
12042 | ++input_line_pointer; | |
12043 | SKIP_WHITESPACE (); | |
12044 | } | |
bdaaa2e1 | 12045 | |
252b5132 RH |
12046 | expression (&exp); |
12047 | if (exp.X_op != O_symbol) | |
12048 | { | |
12049 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12050 | ignore_rest_of_line (); |
252b5132 RH |
12051 | return; |
12052 | } | |
49309057 | 12053 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12054 | } |
12055 | ||
12056 | demand_empty_rest_of_line (); | |
12057 | } | |
12058 | ||
12059 | /* Parse a register string into a number. Called from the ECOFF code | |
12060 | to parse .frame. The argument is non-zero if this is the frame | |
12061 | register, so that we can record it in mips_frame_reg. */ | |
12062 | ||
12063 | int | |
12064 | tc_get_register (frame) | |
12065 | int frame; | |
12066 | { | |
12067 | int reg; | |
12068 | ||
12069 | SKIP_WHITESPACE (); | |
12070 | if (*input_line_pointer++ != '$') | |
12071 | { | |
12072 | as_warn (_("expected `$'")); | |
12073 | reg = 0; | |
12074 | } | |
3882b010 | 12075 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12076 | { |
12077 | reg = get_absolute_expression (); | |
12078 | if (reg < 0 || reg >= 32) | |
12079 | { | |
12080 | as_warn (_("Bad register number")); | |
12081 | reg = 0; | |
12082 | } | |
12083 | } | |
12084 | else | |
12085 | { | |
12086 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
12087 | reg = FP; | |
12088 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
12089 | reg = SP; | |
12090 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
12091 | reg = GP; | |
12092 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
12093 | reg = AT; | |
12094 | else | |
12095 | { | |
12096 | as_warn (_("Unrecognized register name")); | |
12097 | reg = 0; | |
12098 | } | |
12099 | input_line_pointer += 2; | |
12100 | } | |
12101 | if (frame) | |
7a621144 DJ |
12102 | { |
12103 | mips_frame_reg = reg != 0 ? reg : SP; | |
12104 | mips_frame_reg_valid = 1; | |
12105 | mips_cprestore_valid = 0; | |
12106 | } | |
252b5132 RH |
12107 | return reg; |
12108 | } | |
12109 | ||
12110 | valueT | |
12111 | md_section_align (seg, addr) | |
12112 | asection *seg; | |
12113 | valueT addr; | |
12114 | { | |
12115 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12116 | ||
12117 | #ifdef OBJ_ELF | |
12118 | /* We don't need to align ELF sections to the full alignment. | |
12119 | However, Irix 5 may prefer that we align them at least to a 16 | |
12120 | byte boundary. We don't bother to align the sections if we are | |
12121 | targeted for an embedded system. */ | |
12122 | if (strcmp (TARGET_OS, "elf") == 0) | |
12123 | return addr; | |
12124 | if (align > 4) | |
12125 | align = 4; | |
12126 | #endif | |
12127 | ||
12128 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12129 | } | |
12130 | ||
12131 | /* Utility routine, called from above as well. If called while the | |
12132 | input file is still being read, it's only an approximation. (For | |
12133 | example, a symbol may later become defined which appeared to be | |
12134 | undefined earlier.) */ | |
12135 | ||
12136 | static int | |
12137 | nopic_need_relax (sym, before_relaxing) | |
12138 | symbolS *sym; | |
12139 | int before_relaxing; | |
12140 | { | |
12141 | if (sym == 0) | |
12142 | return 0; | |
12143 | ||
6478892d | 12144 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12145 | { |
12146 | const char *symname; | |
12147 | int change; | |
12148 | ||
c9914766 | 12149 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12150 | register. It can be if it is smaller than the -G size or if |
12151 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12152 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12153 | they can. */ |
12154 | symname = S_GET_NAME (sym); | |
12155 | if (symname != (const char *) NULL | |
12156 | && (strcmp (symname, "eprol") == 0 | |
12157 | || strcmp (symname, "etext") == 0 | |
12158 | || strcmp (symname, "_gp") == 0 | |
12159 | || strcmp (symname, "edata") == 0 | |
12160 | || strcmp (symname, "_fbss") == 0 | |
12161 | || strcmp (symname, "_fdata") == 0 | |
12162 | || strcmp (symname, "_ftext") == 0 | |
12163 | || strcmp (symname, "end") == 0 | |
12164 | || strcmp (symname, "_gp_disp") == 0)) | |
12165 | change = 1; | |
12166 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12167 | && (0 | |
12168 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12169 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12170 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12171 | <= g_switch_value)) | |
252b5132 RH |
12172 | #endif |
12173 | /* We must defer this decision until after the whole | |
12174 | file has been read, since there might be a .extern | |
12175 | after the first use of this symbol. */ | |
12176 | || (before_relaxing | |
12177 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12178 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12179 | #endif |
12180 | && S_GET_VALUE (sym) == 0) | |
12181 | || (S_GET_VALUE (sym) != 0 | |
12182 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12183 | change = 0; | |
12184 | else | |
12185 | { | |
12186 | const char *segname; | |
12187 | ||
12188 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12189 | assert (strcmp (segname, ".lit8") != 0 | |
12190 | && strcmp (segname, ".lit4") != 0); | |
12191 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12192 | && strcmp (segname, ".sbss") != 0 |
12193 | && strncmp (segname, ".sdata.", 7) != 0 | |
12194 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12195 | } |
12196 | return change; | |
12197 | } | |
12198 | else | |
c9914766 | 12199 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12200 | return 1; |
12201 | } | |
12202 | ||
12203 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
12204 | extended opcode. SEC is the section the frag is in. */ | |
12205 | ||
12206 | static int | |
12207 | mips16_extended_frag (fragp, sec, stretch) | |
12208 | fragS *fragp; | |
12209 | asection *sec; | |
12210 | long stretch; | |
12211 | { | |
12212 | int type; | |
12213 | register const struct mips16_immed_operand *op; | |
12214 | offsetT val; | |
12215 | int mintiny, maxtiny; | |
12216 | segT symsec; | |
98aa84af | 12217 | fragS *sym_frag; |
252b5132 RH |
12218 | |
12219 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12220 | return 0; | |
12221 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12222 | return 1; | |
12223 | ||
12224 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12225 | op = mips16_immed_operands; | |
12226 | while (op->type != type) | |
12227 | { | |
12228 | ++op; | |
12229 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12230 | } | |
12231 | ||
12232 | if (op->unsp) | |
12233 | { | |
12234 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12235 | { | |
12236 | mintiny = 1; | |
12237 | maxtiny = 1 << op->nbits; | |
12238 | } | |
12239 | else | |
12240 | { | |
12241 | mintiny = 0; | |
12242 | maxtiny = (1 << op->nbits) - 1; | |
12243 | } | |
12244 | } | |
12245 | else | |
12246 | { | |
12247 | mintiny = - (1 << (op->nbits - 1)); | |
12248 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12249 | } | |
12250 | ||
98aa84af | 12251 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12252 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12253 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12254 | |
12255 | if (op->pcrel) | |
12256 | { | |
12257 | addressT addr; | |
12258 | ||
12259 | /* We won't have the section when we are called from | |
12260 | mips_relax_frag. However, we will always have been called | |
12261 | from md_estimate_size_before_relax first. If this is a | |
12262 | branch to a different section, we mark it as such. If SEC is | |
12263 | NULL, and the frag is not marked, then it must be a branch to | |
12264 | the same section. */ | |
12265 | if (sec == NULL) | |
12266 | { | |
12267 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12268 | return 1; | |
12269 | } | |
12270 | else | |
12271 | { | |
98aa84af | 12272 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12273 | if (symsec != sec) |
12274 | { | |
12275 | fragp->fr_subtype = | |
12276 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12277 | ||
12278 | /* FIXME: We should support this, and let the linker | |
12279 | catch branches and loads that are out of range. */ | |
12280 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12281 | _("unsupported PC relative reference to different section")); | |
12282 | ||
12283 | return 1; | |
12284 | } | |
98aa84af AM |
12285 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12286 | /* Assume non-extended on the first relaxation pass. | |
12287 | The address we have calculated will be bogus if this is | |
12288 | a forward branch to another frag, as the forward frag | |
12289 | will have fr_address == 0. */ | |
12290 | return 0; | |
252b5132 RH |
12291 | } |
12292 | ||
12293 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12294 | the same section. If the relax_marker of the symbol fragment |
12295 | differs from the relax_marker of this fragment, we have not | |
12296 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12297 | in STRETCH in order to get a better estimate of the address. |
12298 | This particularly matters because of the shift bits. */ | |
12299 | if (stretch != 0 | |
98aa84af | 12300 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12301 | { |
12302 | fragS *f; | |
12303 | ||
12304 | /* Adjust stretch for any alignment frag. Note that if have | |
12305 | been expanding the earlier code, the symbol may be | |
12306 | defined in what appears to be an earlier frag. FIXME: | |
12307 | This doesn't handle the fr_subtype field, which specifies | |
12308 | a maximum number of bytes to skip when doing an | |
12309 | alignment. */ | |
98aa84af | 12310 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12311 | { |
12312 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12313 | { | |
12314 | if (stretch < 0) | |
12315 | stretch = - ((- stretch) | |
12316 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12317 | else | |
12318 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12319 | if (stretch == 0) | |
12320 | break; | |
12321 | } | |
12322 | } | |
12323 | if (f != NULL) | |
12324 | val += stretch; | |
12325 | } | |
12326 | ||
12327 | addr = fragp->fr_address + fragp->fr_fix; | |
12328 | ||
12329 | /* The base address rules are complicated. The base address of | |
12330 | a branch is the following instruction. The base address of a | |
12331 | PC relative load or add is the instruction itself, but if it | |
12332 | is in a delay slot (in which case it can not be extended) use | |
12333 | the address of the instruction whose delay slot it is in. */ | |
12334 | if (type == 'p' || type == 'q') | |
12335 | { | |
12336 | addr += 2; | |
12337 | ||
12338 | /* If we are currently assuming that this frag should be | |
12339 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12340 | higher. */ |
252b5132 RH |
12341 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12342 | addr += 2; | |
12343 | ||
12344 | /* Ignore the low bit in the target, since it will be set | |
12345 | for a text label. */ | |
12346 | if ((val & 1) != 0) | |
12347 | --val; | |
12348 | } | |
12349 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12350 | addr -= 4; | |
12351 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12352 | addr -= 2; | |
12353 | ||
12354 | val -= addr & ~ ((1 << op->shift) - 1); | |
12355 | ||
12356 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12357 | if (type == 'p' || type == 'q') | |
12358 | val /= 2; | |
12359 | ||
12360 | /* If any of the shifted bits are set, we must use an extended | |
12361 | opcode. If the address depends on the size of this | |
12362 | instruction, this can lead to a loop, so we arrange to always | |
12363 | use an extended opcode. We only check this when we are in | |
12364 | the main relaxation loop, when SEC is NULL. */ | |
12365 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12366 | { | |
12367 | fragp->fr_subtype = | |
12368 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12369 | return 1; | |
12370 | } | |
12371 | ||
12372 | /* If we are about to mark a frag as extended because the value | |
12373 | is precisely maxtiny + 1, then there is a chance of an | |
12374 | infinite loop as in the following code: | |
12375 | la $4,foo | |
12376 | .skip 1020 | |
12377 | .align 2 | |
12378 | foo: | |
12379 | In this case when the la is extended, foo is 0x3fc bytes | |
12380 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12381 | the la must be extended. To avoid this loop, we mark the | |
12382 | frag as extended if it was small, and is about to become | |
12383 | extended with a value of maxtiny + 1. */ | |
12384 | if (val == ((maxtiny + 1) << op->shift) | |
12385 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12386 | && sec == NULL) | |
12387 | { | |
12388 | fragp->fr_subtype = | |
12389 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12390 | return 1; | |
12391 | } | |
12392 | } | |
12393 | else if (symsec != absolute_section && sec != NULL) | |
12394 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12395 | ||
12396 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12397 | || val < (mintiny << op->shift) | |
12398 | || val > (maxtiny << op->shift)) | |
12399 | return 1; | |
12400 | else | |
12401 | return 0; | |
12402 | } | |
12403 | ||
12404 | /* Estimate the size of a frag before relaxing. Unless this is the | |
12405 | mips16, we are not really relaxing here, and the final size is | |
12406 | encoded in the subtype information. For the mips16, we have to | |
12407 | decide whether we are using an extended opcode or not. */ | |
12408 | ||
252b5132 RH |
12409 | int |
12410 | md_estimate_size_before_relax (fragp, segtype) | |
12411 | fragS *fragp; | |
12412 | asection *segtype; | |
12413 | { | |
43841e91 | 12414 | int change = 0; |
8614eeee | 12415 | boolean linkonce = false; |
252b5132 RH |
12416 | |
12417 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
177b4a6a AO |
12418 | /* We don't want to modify the EXTENDED bit here; it might get us |
12419 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12420 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12421 | |
12422 | if (mips_pic == NO_PIC) | |
12423 | { | |
12424 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
12425 | } | |
12426 | else if (mips_pic == SVR4_PIC) | |
12427 | { | |
12428 | symbolS *sym; | |
12429 | asection *symsec; | |
12430 | ||
12431 | sym = fragp->fr_symbol; | |
12432 | ||
12433 | /* Handle the case of a symbol equated to another symbol. */ | |
e0890092 | 12434 | while (symbol_equated_reloc_p (sym)) |
252b5132 RH |
12435 | { |
12436 | symbolS *n; | |
12437 | ||
12438 | /* It's possible to get a loop here in a badly written | |
12439 | program. */ | |
49309057 | 12440 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
12441 | if (n == sym) |
12442 | break; | |
12443 | sym = n; | |
12444 | } | |
12445 | ||
12446 | symsec = S_GET_SEGMENT (sym); | |
12447 | ||
8614eeee UC |
12448 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
12449 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
12450 | { |
12451 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12452 | != 0) | |
12453 | linkonce = true; | |
12454 | ||
12455 | /* The GNU toolchain uses an extension for ELF: a section | |
12456 | beginning with the magic string .gnu.linkonce is a linkonce | |
12457 | section. */ | |
12458 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12459 | sizeof ".gnu.linkonce" - 1) == 0) | |
12460 | linkonce = true; | |
12461 | } | |
8614eeee | 12462 | |
252b5132 RH |
12463 | /* This must duplicate the test in adjust_reloc_syms. */ |
12464 | change = (symsec != &bfd_und_section | |
12465 | && symsec != &bfd_abs_section | |
426b0403 | 12466 | && ! bfd_is_com_section (symsec) |
8614eeee | 12467 | && !linkonce |
426b0403 | 12468 | #ifdef OBJ_ELF |
ea4ff978 | 12469 | /* A global or weak symbol is treated as external. */ |
9151e8bf | 12470 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour |
b25a253c CD |
12471 | || (! S_IS_WEAK (sym) |
12472 | && (! S_IS_EXTERN (sym) || mips_pic == EMBEDDED_PIC))) | |
426b0403 AM |
12473 | #endif |
12474 | ); | |
252b5132 RH |
12475 | } |
12476 | else | |
12477 | abort (); | |
12478 | ||
12479 | if (change) | |
12480 | { | |
12481 | /* Record the offset to the first reloc in the fr_opcode field. | |
12482 | This lets md_convert_frag and tc_gen_reloc know that the code | |
12483 | must be expanded. */ | |
12484 | fragp->fr_opcode = (fragp->fr_literal | |
12485 | + fragp->fr_fix | |
12486 | - RELAX_OLD (fragp->fr_subtype) | |
12487 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
12488 | /* FIXME: This really needs as_warn_where. */ | |
12489 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
12490 | as_warn (_("AT used after \".set noat\" or macro used after " |
12491 | "\".set nomacro\"")); | |
12492 | ||
12493 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
12494 | } |
12495 | ||
9a41af64 | 12496 | return 0; |
252b5132 RH |
12497 | } |
12498 | ||
12499 | /* This is called to see whether a reloc against a defined symbol | |
12500 | should be converted into a reloc against a section. Don't adjust | |
12501 | MIPS16 jump relocations, so we don't have to worry about the format | |
12502 | of the offset in the .o file. Don't adjust relocations against | |
12503 | mips16 symbols, so that the linker can find them if it needs to set | |
12504 | up a stub. */ | |
12505 | ||
12506 | int | |
12507 | mips_fix_adjustable (fixp) | |
12508 | fixS *fixp; | |
12509 | { | |
ea4ff978 L |
12510 | #ifdef OBJ_ELF |
12511 | /* Prevent all adjustments to global symbols. */ | |
46bac6de | 12512 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
b25a253c | 12513 | && mips_pic != EMBEDDED_PIC |
46bac6de | 12514 | && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))) |
ea4ff978 L |
12515 | return 0; |
12516 | #endif | |
252b5132 RH |
12517 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12518 | return 0; | |
12519 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
12520 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12521 | return 0; | |
12522 | if (fixp->fx_addsy == NULL) | |
12523 | return 1; | |
12524 | #ifdef OBJ_ELF | |
12525 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
12526 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12527 | && fixp->fx_subsy == NULL) | |
12528 | return 0; | |
12529 | #endif | |
12530 | return 1; | |
12531 | } | |
12532 | ||
12533 | /* Translate internal representation of relocation info to BFD target | |
12534 | format. */ | |
12535 | ||
12536 | arelent ** | |
12537 | tc_gen_reloc (section, fixp) | |
43841e91 | 12538 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
12539 | fixS *fixp; |
12540 | { | |
12541 | static arelent *retval[4]; | |
12542 | arelent *reloc; | |
12543 | bfd_reloc_code_real_type code; | |
12544 | ||
12545 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
12546 | retval[1] = NULL; | |
12547 | ||
49309057 ILT |
12548 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12549 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12550 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12551 | ||
12552 | if (mips_pic == EMBEDDED_PIC | |
12553 | && SWITCH_TABLE (fixp)) | |
12554 | { | |
12555 | /* For a switch table entry we use a special reloc. The addend | |
12556 | is actually the difference between the reloc address and the | |
12557 | subtrahend. */ | |
12558 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
12559 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
12560 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
12561 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
12562 | } | |
12563 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
12564 | { | |
4514d474 CD |
12565 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12566 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12567 | else |
4514d474 CD |
12568 | { |
12569 | /* We use a special addend for an internal RELLO reloc. */ | |
12570 | if (symbol_section_p (fixp->fx_addsy)) | |
12571 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
12572 | else | |
12573 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
12574 | } | |
252b5132 RH |
12575 | } |
12576 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
12577 | { | |
12578 | assert (fixp->fx_next != NULL | |
12579 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
12580 | |
12581 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 12582 | accordingly. */ |
4514d474 CD |
12583 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12584 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 12585 | else |
4514d474 CD |
12586 | { |
12587 | /* We use a special addend for an internal RELHI reloc. */ | |
12588 | if (symbol_section_p (fixp->fx_addsy)) | |
12589 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
12590 | + fixp->fx_next->fx_where | |
12591 | - S_GET_VALUE (fixp->fx_subsy)); | |
12592 | else | |
12593 | reloc->addend = (fixp->fx_addnumber | |
12594 | + fixp->fx_next->fx_frag->fr_address | |
12595 | + fixp->fx_next->fx_where); | |
12596 | } | |
252b5132 | 12597 | } |
4514d474 CD |
12598 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12599 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
12600 | else |
12601 | { | |
12602 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
12603 | /* A gruesome hack which is a result of the gruesome gas reloc | |
12604 | handling. */ | |
12605 | reloc->addend = reloc->address; | |
12606 | else | |
12607 | reloc->addend = -reloc->address; | |
12608 | } | |
12609 | ||
12610 | /* If this is a variant frag, we may need to adjust the existing | |
12611 | reloc and generate a new one. */ | |
12612 | if (fixp->fx_frag->fr_opcode != NULL | |
cdf6fd85 | 12613 | && (fixp->fx_r_type == BFD_RELOC_GPREL16 |
252b5132 RH |
12614 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
12615 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
12616 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
12617 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
12618 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d TS |
12619 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
12620 | && ! HAVE_NEWABI) | |
252b5132 RH |
12621 | { |
12622 | arelent *reloc2; | |
12623 | ||
12624 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
12625 | ||
12626 | /* If this is not the last reloc in this frag, then we have two | |
12627 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
12628 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
12629 | the second one handle all of them. */ | |
12630 | if (fixp->fx_next != NULL | |
12631 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
12632 | { | |
cdf6fd85 TS |
12633 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
12634 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
12635 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
12636 | && (fixp->fx_next->fx_r_type | |
12637 | == BFD_RELOC_MIPS_GOT_LO16)) | |
12638 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
12639 | && (fixp->fx_next->fx_r_type | |
12640 | == BFD_RELOC_MIPS_CALL_LO16))); | |
12641 | retval[0] = NULL; | |
12642 | return retval; | |
12643 | } | |
12644 | ||
12645 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
12646 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
12647 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
12648 | retval[2] = NULL; | |
49309057 ILT |
12649 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12650 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12651 | reloc2->address = (reloc->address |
12652 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
12653 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
12654 | reloc2->addend = fixp->fx_addnumber; | |
12655 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
12656 | assert (reloc2->howto != NULL); | |
12657 | ||
12658 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
12659 | { | |
12660 | arelent *reloc3; | |
12661 | ||
12662 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
12663 | retval[3] = NULL; | |
12664 | *reloc3 = *reloc2; | |
12665 | reloc3->address += 4; | |
12666 | } | |
12667 | ||
12668 | if (mips_pic == NO_PIC) | |
12669 | { | |
cdf6fd85 | 12670 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
12671 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
12672 | } | |
12673 | else if (mips_pic == SVR4_PIC) | |
12674 | { | |
12675 | switch (fixp->fx_r_type) | |
12676 | { | |
12677 | default: | |
12678 | abort (); | |
12679 | case BFD_RELOC_MIPS_GOT16: | |
12680 | break; | |
12681 | case BFD_RELOC_MIPS_CALL16: | |
12682 | case BFD_RELOC_MIPS_GOT_LO16: | |
12683 | case BFD_RELOC_MIPS_CALL_LO16: | |
12684 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
12685 | break; | |
12686 | } | |
12687 | } | |
12688 | else | |
12689 | abort (); | |
12690 | } | |
12691 | ||
438c16b8 TS |
12692 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12693 | entry to be used in the relocation's section offset. */ | |
12694 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12695 | { |
12696 | reloc->address = reloc->addend; | |
12697 | reloc->addend = 0; | |
12698 | } | |
12699 | ||
12700 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
12701 | fixup_segment converted a non-PC relative reloc into a PC | |
12702 | relative reloc. In such a case, we need to convert the reloc | |
12703 | code. */ | |
12704 | code = fixp->fx_r_type; | |
12705 | if (fixp->fx_pcrel) | |
12706 | { | |
12707 | switch (code) | |
12708 | { | |
12709 | case BFD_RELOC_8: | |
12710 | code = BFD_RELOC_8_PCREL; | |
12711 | break; | |
12712 | case BFD_RELOC_16: | |
12713 | code = BFD_RELOC_16_PCREL; | |
12714 | break; | |
12715 | case BFD_RELOC_32: | |
12716 | code = BFD_RELOC_32_PCREL; | |
12717 | break; | |
12718 | case BFD_RELOC_64: | |
12719 | code = BFD_RELOC_64_PCREL; | |
12720 | break; | |
12721 | case BFD_RELOC_8_PCREL: | |
12722 | case BFD_RELOC_16_PCREL: | |
12723 | case BFD_RELOC_32_PCREL: | |
12724 | case BFD_RELOC_64_PCREL: | |
12725 | case BFD_RELOC_16_PCREL_S2: | |
12726 | case BFD_RELOC_PCREL_HI16_S: | |
12727 | case BFD_RELOC_PCREL_LO16: | |
12728 | break; | |
12729 | default: | |
12730 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12731 | _("Cannot make %s relocation PC relative"), | |
12732 | bfd_get_reloc_code_name (code)); | |
12733 | } | |
12734 | } | |
12735 | ||
add55e1f RS |
12736 | #ifdef OBJ_ELF |
12737 | /* md_apply_fix3 has a double-subtraction hack to get | |
12738 | bfd_install_relocation to behave nicely. GPREL relocations are | |
12739 | handled correctly without this hack, so undo it here. We can't | |
12740 | stop md_apply_fix3 from subtracting twice in the first place since | |
12741 | the fake addend is required for variant frags above. */ | |
12742 | if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour | |
d11008e1 | 12743 | && code == BFD_RELOC_GPREL16 |
add55e1f RS |
12744 | && reloc->addend != 0 |
12745 | && mips_need_elf_addend_fixup (fixp)) | |
12746 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); | |
12747 | #endif | |
12748 | ||
252b5132 RH |
12749 | /* To support a PC relative reloc when generating embedded PIC code |
12750 | for ECOFF, we use a Cygnus extension. We check for that here to | |
12751 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
12752 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12753 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
12754 | && code == BFD_RELOC_16_PCREL_S2 |
12755 | && mips_pic != EMBEDDED_PIC) | |
12756 | reloc->howto = NULL; | |
12757 | else | |
12758 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12759 | ||
12760 | if (reloc->howto == NULL) | |
12761 | { | |
12762 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12763 | _("Can not represent %s relocation in this object file format"), | |
12764 | bfd_get_reloc_code_name (code)); | |
12765 | retval[0] = NULL; | |
12766 | } | |
12767 | ||
12768 | return retval; | |
12769 | } | |
12770 | ||
12771 | /* Relax a machine dependent frag. This returns the amount by which | |
12772 | the current size of the frag should change. */ | |
12773 | ||
12774 | int | |
12775 | mips_relax_frag (fragp, stretch) | |
12776 | fragS *fragp; | |
12777 | long stretch; | |
12778 | { | |
12779 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
12780 | return 0; | |
12781 | ||
c4e7957c | 12782 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12783 | { |
12784 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12785 | return 0; | |
12786 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12787 | return 2; | |
12788 | } | |
12789 | else | |
12790 | { | |
12791 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12792 | return 0; | |
12793 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12794 | return -2; | |
12795 | } | |
12796 | ||
12797 | return 0; | |
12798 | } | |
12799 | ||
12800 | /* Convert a machine dependent frag. */ | |
12801 | ||
12802 | void | |
12803 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 12804 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
12805 | segT asec; |
12806 | fragS *fragp; | |
12807 | { | |
12808 | int old, new; | |
12809 | char *fixptr; | |
12810 | ||
12811 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
12812 | { | |
12813 | int type; | |
12814 | register const struct mips16_immed_operand *op; | |
12815 | boolean small, ext; | |
12816 | offsetT val; | |
12817 | bfd_byte *buf; | |
12818 | unsigned long insn; | |
12819 | boolean use_extend; | |
12820 | unsigned short extend; | |
12821 | ||
12822 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12823 | op = mips16_immed_operands; | |
12824 | while (op->type != type) | |
12825 | ++op; | |
12826 | ||
12827 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12828 | { | |
12829 | small = false; | |
12830 | ext = true; | |
12831 | } | |
12832 | else | |
12833 | { | |
12834 | small = true; | |
12835 | ext = false; | |
12836 | } | |
12837 | ||
6386f3a7 | 12838 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
12839 | val = S_GET_VALUE (fragp->fr_symbol); |
12840 | if (op->pcrel) | |
12841 | { | |
12842 | addressT addr; | |
12843 | ||
12844 | addr = fragp->fr_address + fragp->fr_fix; | |
12845 | ||
12846 | /* The rules for the base address of a PC relative reloc are | |
12847 | complicated; see mips16_extended_frag. */ | |
12848 | if (type == 'p' || type == 'q') | |
12849 | { | |
12850 | addr += 2; | |
12851 | if (ext) | |
12852 | addr += 2; | |
12853 | /* Ignore the low bit in the target, since it will be | |
12854 | set for a text label. */ | |
12855 | if ((val & 1) != 0) | |
12856 | --val; | |
12857 | } | |
12858 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12859 | addr -= 4; | |
12860 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12861 | addr -= 2; | |
12862 | ||
12863 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
12864 | val -= addr; | |
12865 | ||
12866 | /* Make sure the section winds up with the alignment we have | |
12867 | assumed. */ | |
12868 | if (op->shift > 0) | |
12869 | record_alignment (asec, op->shift); | |
12870 | } | |
12871 | ||
12872 | if (ext | |
12873 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
12874 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
12875 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12876 | _("extended instruction in delay slot")); | |
12877 | ||
12878 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
12879 | ||
12880 | if (target_big_endian) | |
12881 | insn = bfd_getb16 (buf); | |
12882 | else | |
12883 | insn = bfd_getl16 (buf); | |
12884 | ||
12885 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
12886 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
12887 | small, ext, &insn, &use_extend, &extend); | |
12888 | ||
12889 | if (use_extend) | |
12890 | { | |
874e8986 | 12891 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
12892 | fragp->fr_fix += 2; |
12893 | buf += 2; | |
12894 | } | |
12895 | ||
874e8986 | 12896 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
12897 | fragp->fr_fix += 2; |
12898 | buf += 2; | |
12899 | } | |
12900 | else | |
12901 | { | |
12902 | if (fragp->fr_opcode == NULL) | |
12903 | return; | |
12904 | ||
12905 | old = RELAX_OLD (fragp->fr_subtype); | |
12906 | new = RELAX_NEW (fragp->fr_subtype); | |
12907 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
12908 | ||
12909 | if (new > 0) | |
12910 | memcpy (fixptr - old, fixptr, new); | |
12911 | ||
12912 | fragp->fr_fix += new - old; | |
12913 | } | |
12914 | } | |
12915 | ||
12916 | #ifdef OBJ_ELF | |
12917 | ||
12918 | /* This function is called after the relocs have been generated. | |
12919 | We've been storing mips16 text labels as odd. Here we convert them | |
12920 | back to even for the convenience of the debugger. */ | |
12921 | ||
12922 | void | |
12923 | mips_frob_file_after_relocs () | |
12924 | { | |
12925 | asymbol **syms; | |
12926 | unsigned int count, i; | |
12927 | ||
12928 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
12929 | return; | |
12930 | ||
12931 | syms = bfd_get_outsymbols (stdoutput); | |
12932 | count = bfd_get_symcount (stdoutput); | |
12933 | for (i = 0; i < count; i++, syms++) | |
12934 | { | |
12935 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
12936 | && ((*syms)->value & 1) != 0) | |
12937 | { | |
12938 | (*syms)->value &= ~1; | |
12939 | /* If the symbol has an odd size, it was probably computed | |
12940 | incorrectly, so adjust that as well. */ | |
12941 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
12942 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
12943 | } | |
12944 | } | |
12945 | } | |
12946 | ||
12947 | #endif | |
12948 | ||
12949 | /* This function is called whenever a label is defined. It is used | |
12950 | when handling branch delays; if a branch has a label, we assume we | |
12951 | can not move it. */ | |
12952 | ||
12953 | void | |
12954 | mips_define_label (sym) | |
12955 | symbolS *sym; | |
12956 | { | |
12957 | struct insn_label_list *l; | |
12958 | ||
12959 | if (free_insn_labels == NULL) | |
12960 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
12961 | else | |
12962 | { | |
12963 | l = free_insn_labels; | |
12964 | free_insn_labels = l->next; | |
12965 | } | |
12966 | ||
12967 | l->label = sym; | |
12968 | l->next = insn_labels; | |
12969 | insn_labels = l; | |
12970 | } | |
12971 | \f | |
12972 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12973 | ||
12974 | /* Some special processing for a MIPS ELF file. */ | |
12975 | ||
12976 | void | |
12977 | mips_elf_final_processing () | |
12978 | { | |
12979 | /* Write out the register information. */ | |
195325d2 | 12980 | if (file_mips_abi != N64_ABI) |
252b5132 RH |
12981 | { |
12982 | Elf32_RegInfo s; | |
12983 | ||
12984 | s.ri_gprmask = mips_gprmask; | |
12985 | s.ri_cprmask[0] = mips_cprmask[0]; | |
12986 | s.ri_cprmask[1] = mips_cprmask[1]; | |
12987 | s.ri_cprmask[2] = mips_cprmask[2]; | |
12988 | s.ri_cprmask[3] = mips_cprmask[3]; | |
12989 | /* The gp_value field is set by the MIPS ELF backend. */ | |
12990 | ||
12991 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
12992 | ((Elf32_External_RegInfo *) | |
12993 | mips_regmask_frag)); | |
12994 | } | |
12995 | else | |
12996 | { | |
12997 | Elf64_Internal_RegInfo s; | |
12998 | ||
12999 | s.ri_gprmask = mips_gprmask; | |
13000 | s.ri_pad = 0; | |
13001 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13002 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13003 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13004 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13005 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13006 | ||
13007 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13008 | ((Elf64_External_RegInfo *) | |
13009 | mips_regmask_frag)); | |
13010 | } | |
13011 | ||
13012 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13013 | sort of BFD interface for this. */ | |
13014 | if (mips_any_noreorder) | |
13015 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13016 | if (mips_pic != NO_PIC) | |
13017 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
13018 | ||
98d3f06f | 13019 | /* Set MIPS ELF flags for ASEs. */ |
1f25f5d3 CD |
13020 | #if 0 /* XXX FIXME */ |
13021 | if (file_ase_mips3d) | |
13022 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13023 | #endif | |
13024 | ||
bdaaa2e1 | 13025 | /* Set the MIPS ELF ABI flags. */ |
a325df1d | 13026 | if (file_mips_abi == NO_ABI) |
252b5132 | 13027 | ; |
a325df1d | 13028 | else if (file_mips_abi == O32_ABI) |
252b5132 | 13029 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
a325df1d | 13030 | else if (file_mips_abi == O64_ABI) |
252b5132 | 13031 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
a325df1d | 13032 | else if (file_mips_abi == EABI_ABI) |
252b5132 RH |
13033 | { |
13034 | if (mips_eabi64) | |
13035 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
13036 | else | |
13037 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13038 | } | |
a325df1d | 13039 | else if (file_mips_abi == N32_ABI) |
be00bddd TS |
13040 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13041 | ||
c9914766 | 13042 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13043 | |
13044 | if (mips_32bitmode) | |
13045 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13046 | } | |
13047 | ||
13048 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13049 | \f | |
beae10d5 KH |
13050 | typedef struct proc { |
13051 | symbolS *isym; | |
13052 | unsigned long reg_mask; | |
13053 | unsigned long reg_offset; | |
13054 | unsigned long fpreg_mask; | |
13055 | unsigned long fpreg_offset; | |
13056 | unsigned long frame_offset; | |
13057 | unsigned long frame_reg; | |
13058 | unsigned long pc_reg; | |
13059 | } procS; | |
252b5132 RH |
13060 | |
13061 | static procS cur_proc; | |
13062 | static procS *cur_proc_ptr; | |
13063 | static int numprocs; | |
13064 | ||
0a9ef439 | 13065 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13066 | |
0a9ef439 RH |
13067 | void |
13068 | mips_handle_align (fragp) | |
13069 | fragS *fragp; | |
a19d8eb0 | 13070 | { |
0a9ef439 RH |
13071 | if (fragp->fr_type != rs_align_code) |
13072 | return; | |
13073 | ||
13074 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13075 | { |
13076 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13077 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13078 | ||
0a9ef439 RH |
13079 | int bytes; |
13080 | char *p; | |
a19d8eb0 | 13081 | |
0a9ef439 RH |
13082 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13083 | p = fragp->fr_literal + fragp->fr_fix; | |
13084 | ||
13085 | if (bytes & 1) | |
13086 | { | |
13087 | *p++ = 0; | |
f9419b05 | 13088 | fragp->fr_fix++; |
0a9ef439 RH |
13089 | } |
13090 | ||
13091 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13092 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13093 | } |
13094 | ||
0a9ef439 | 13095 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13096 | } |
13097 | ||
252b5132 RH |
13098 | static void |
13099 | md_obj_begin () | |
13100 | { | |
13101 | } | |
13102 | ||
13103 | static void | |
13104 | md_obj_end () | |
13105 | { | |
13106 | /* check for premature end, nesting errors, etc */ | |
13107 | if (cur_proc_ptr) | |
9a41af64 | 13108 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13109 | } |
13110 | ||
13111 | static long | |
13112 | get_number () | |
13113 | { | |
13114 | int negative = 0; | |
13115 | long val = 0; | |
13116 | ||
13117 | if (*input_line_pointer == '-') | |
13118 | { | |
13119 | ++input_line_pointer; | |
13120 | negative = 1; | |
13121 | } | |
3882b010 | 13122 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13123 | as_bad (_("expected simple number")); |
252b5132 RH |
13124 | if (input_line_pointer[0] == '0') |
13125 | { | |
13126 | if (input_line_pointer[1] == 'x') | |
13127 | { | |
13128 | input_line_pointer += 2; | |
3882b010 | 13129 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13130 | { |
13131 | val <<= 4; | |
13132 | val |= hex_value (*input_line_pointer++); | |
13133 | } | |
13134 | return negative ? -val : val; | |
13135 | } | |
13136 | else | |
13137 | { | |
13138 | ++input_line_pointer; | |
3882b010 | 13139 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13140 | { |
13141 | val <<= 3; | |
13142 | val |= *input_line_pointer++ - '0'; | |
13143 | } | |
13144 | return negative ? -val : val; | |
13145 | } | |
13146 | } | |
3882b010 | 13147 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13148 | { |
13149 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13150 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13151 | as_warn (_("invalid number")); |
252b5132 RH |
13152 | return -1; |
13153 | } | |
3882b010 | 13154 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13155 | { |
13156 | val *= 10; | |
13157 | val += *input_line_pointer++ - '0'; | |
13158 | } | |
13159 | return negative ? -val : val; | |
13160 | } | |
13161 | ||
13162 | /* The .file directive; just like the usual .file directive, but there | |
13163 | is an initial number which is the ECOFF file index. */ | |
13164 | ||
13165 | static void | |
13166 | s_file (x) | |
43841e91 | 13167 | int x ATTRIBUTE_UNUSED; |
252b5132 | 13168 | { |
874e8986 | 13169 | get_number (); |
252b5132 RH |
13170 | s_app_file (0); |
13171 | } | |
13172 | ||
252b5132 RH |
13173 | /* The .end directive. */ |
13174 | ||
13175 | static void | |
13176 | s_mips_end (x) | |
43841e91 | 13177 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
13178 | { |
13179 | symbolS *p; | |
13180 | int maybe_text; | |
13181 | ||
7a621144 DJ |
13182 | /* Following functions need their own .frame and .cprestore directives. */ |
13183 | mips_frame_reg_valid = 0; | |
13184 | mips_cprestore_valid = 0; | |
13185 | ||
252b5132 RH |
13186 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13187 | { | |
13188 | p = get_symbol (); | |
13189 | demand_empty_rest_of_line (); | |
13190 | } | |
13191 | else | |
13192 | p = NULL; | |
13193 | ||
13194 | #ifdef BFD_ASSEMBLER | |
13195 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
13196 | maybe_text = 1; | |
13197 | else | |
13198 | maybe_text = 0; | |
13199 | #else | |
13200 | if (now_seg != data_section && now_seg != bss_section) | |
13201 | maybe_text = 1; | |
13202 | else | |
13203 | maybe_text = 0; | |
13204 | #endif | |
13205 | ||
13206 | if (!maybe_text) | |
13207 | as_warn (_(".end not in text section")); | |
13208 | ||
13209 | if (!cur_proc_ptr) | |
13210 | { | |
13211 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13212 | demand_empty_rest_of_line (); | |
13213 | return; | |
13214 | } | |
13215 | ||
13216 | if (p != NULL) | |
13217 | { | |
13218 | assert (S_GET_NAME (p)); | |
13219 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13220 | as_warn (_(".end symbol does not match .ent symbol.")); | |
13221 | } | |
13222 | else | |
13223 | as_warn (_(".end directive missing or unknown symbol")); | |
13224 | ||
13225 | #ifdef MIPS_STABS_ELF | |
13226 | { | |
13227 | segT saved_seg = now_seg; | |
13228 | subsegT saved_subseg = now_subseg; | |
252b5132 | 13229 | valueT dot; |
252b5132 RH |
13230 | expressionS exp; |
13231 | char *fragp; | |
13232 | ||
13233 | dot = frag_now_fix (); | |
13234 | ||
13235 | #ifdef md_flush_pending_output | |
13236 | md_flush_pending_output (); | |
13237 | #endif | |
13238 | ||
13239 | assert (pdr_seg); | |
13240 | subseg_set (pdr_seg, 0); | |
13241 | ||
beae10d5 | 13242 | /* Write the symbol. */ |
252b5132 RH |
13243 | exp.X_op = O_symbol; |
13244 | exp.X_add_symbol = p; | |
13245 | exp.X_add_number = 0; | |
13246 | emit_expr (&exp, 4); | |
13247 | ||
beae10d5 | 13248 | fragp = frag_more (7 * 4); |
252b5132 | 13249 | |
beae10d5 KH |
13250 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
13251 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
13252 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
13253 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
13254 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
13255 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
13256 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 RH |
13257 | |
13258 | subseg_set (saved_seg, saved_subseg); | |
13259 | } | |
f9419b05 | 13260 | #endif /* MIPS_STABS_ELF */ |
252b5132 RH |
13261 | |
13262 | cur_proc_ptr = NULL; | |
13263 | } | |
13264 | ||
13265 | /* The .aent and .ent directives. */ | |
13266 | ||
13267 | static void | |
13268 | s_mips_ent (aent) | |
13269 | int aent; | |
13270 | { | |
252b5132 RH |
13271 | symbolS *symbolP; |
13272 | int maybe_text; | |
13273 | ||
13274 | symbolP = get_symbol (); | |
13275 | if (*input_line_pointer == ',') | |
f9419b05 | 13276 | ++input_line_pointer; |
252b5132 | 13277 | SKIP_WHITESPACE (); |
3882b010 | 13278 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13279 | || *input_line_pointer == '-') |
874e8986 | 13280 | get_number (); |
252b5132 RH |
13281 | |
13282 | #ifdef BFD_ASSEMBLER | |
13283 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
13284 | maybe_text = 1; | |
13285 | else | |
13286 | maybe_text = 0; | |
13287 | #else | |
13288 | if (now_seg != data_section && now_seg != bss_section) | |
13289 | maybe_text = 1; | |
13290 | else | |
13291 | maybe_text = 0; | |
13292 | #endif | |
13293 | ||
13294 | if (!maybe_text) | |
13295 | as_warn (_(".ent or .aent not in text section.")); | |
13296 | ||
13297 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13298 | as_warn (_("missing .end")); |
252b5132 RH |
13299 | |
13300 | if (!aent) | |
13301 | { | |
7a621144 DJ |
13302 | /* This function needs its own .frame and .cprestore directives. */ |
13303 | mips_frame_reg_valid = 0; | |
13304 | mips_cprestore_valid = 0; | |
13305 | ||
252b5132 RH |
13306 | cur_proc_ptr = &cur_proc; |
13307 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13308 | ||
13309 | cur_proc_ptr->isym = symbolP; | |
13310 | ||
49309057 | 13311 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13312 | |
f9419b05 | 13313 | ++numprocs; |
252b5132 RH |
13314 | } |
13315 | ||
13316 | demand_empty_rest_of_line (); | |
13317 | } | |
13318 | ||
13319 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13320 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13321 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13322 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13323 | symbol table (in the mdebug section). */ |
13324 | ||
13325 | static void | |
13326 | s_mips_frame (ignore) | |
2b3c5a5d | 13327 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
13328 | { |
13329 | #ifdef MIPS_STABS_ELF | |
13330 | ||
13331 | long val; | |
13332 | ||
beae10d5 | 13333 | if (cur_proc_ptr == (procS *) NULL) |
252b5132 RH |
13334 | { |
13335 | as_warn (_(".frame outside of .ent")); | |
13336 | demand_empty_rest_of_line (); | |
13337 | return; | |
13338 | } | |
13339 | ||
13340 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
13341 | ||
13342 | SKIP_WHITESPACE (); | |
13343 | if (*input_line_pointer++ != ',' | |
13344 | || get_absolute_expression_and_terminator (&val) != ',') | |
13345 | { | |
13346 | as_warn (_("Bad .frame directive")); | |
13347 | --input_line_pointer; | |
13348 | demand_empty_rest_of_line (); | |
13349 | return; | |
13350 | } | |
13351 | ||
13352 | cur_proc_ptr->frame_offset = val; | |
13353 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
13354 | ||
13355 | demand_empty_rest_of_line (); | |
13356 | #else | |
13357 | s_ignore (ignore); | |
13358 | #endif /* MIPS_STABS_ELF */ | |
13359 | } | |
13360 | ||
bdaaa2e1 KH |
13361 | /* The .fmask and .mask directives. If the mdebug section is present |
13362 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13363 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13364 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13365 | make reference to the ecoff symbol table (in the mdebug section). */ |
13366 | ||
13367 | static void | |
13368 | s_mips_mask (reg_type) | |
13369 | char reg_type; | |
13370 | { | |
13371 | #ifdef MIPS_STABS_ELF | |
13372 | long mask, off; | |
bdaaa2e1 | 13373 | |
252b5132 RH |
13374 | if (cur_proc_ptr == (procS *) NULL) |
13375 | { | |
13376 | as_warn (_(".mask/.fmask outside of .ent")); | |
13377 | demand_empty_rest_of_line (); | |
13378 | return; | |
13379 | } | |
13380 | ||
13381 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
13382 | { | |
13383 | as_warn (_("Bad .mask/.fmask directive")); | |
13384 | --input_line_pointer; | |
13385 | demand_empty_rest_of_line (); | |
13386 | return; | |
13387 | } | |
13388 | ||
13389 | off = get_absolute_expression (); | |
13390 | ||
13391 | if (reg_type == 'F') | |
13392 | { | |
13393 | cur_proc_ptr->fpreg_mask = mask; | |
13394 | cur_proc_ptr->fpreg_offset = off; | |
13395 | } | |
13396 | else | |
13397 | { | |
13398 | cur_proc_ptr->reg_mask = mask; | |
13399 | cur_proc_ptr->reg_offset = off; | |
13400 | } | |
13401 | ||
13402 | demand_empty_rest_of_line (); | |
13403 | #else | |
13404 | s_ignore (reg_type); | |
13405 | #endif /* MIPS_STABS_ELF */ | |
13406 | } | |
13407 | ||
13408 | /* The .loc directive. */ | |
13409 | ||
13410 | #if 0 | |
13411 | static void | |
13412 | s_loc (x) | |
13413 | int x; | |
13414 | { | |
13415 | symbolS *symbolP; | |
13416 | int lineno; | |
13417 | int addroff; | |
13418 | ||
13419 | assert (now_seg == text_section); | |
13420 | ||
13421 | lineno = get_number (); | |
13422 | addroff = frag_now_fix (); | |
13423 | ||
13424 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
13425 | S_SET_TYPE (symbolP, N_SLINE); | |
13426 | S_SET_OTHER (symbolP, 0); | |
13427 | S_SET_DESC (symbolP, lineno); | |
13428 | symbolP->sy_segment = now_seg; | |
13429 | } | |
13430 | #endif | |
e7af610e NC |
13431 | |
13432 | /* CPU name/ISA/number mapping table. | |
13433 | ||
13434 | Entries are grouped by type. The first matching CPU or ISA entry | |
13435 | gets chosen by CPU or ISA, so it should be the 'canonical' name | |
13436 | for that type. Entries after that within the type are sorted | |
13437 | alphabetically. | |
13438 | ||
13439 | Case is ignored in comparison, so put the canonical entry in the | |
13440 | appropriate case but everything else in lower case to ease eye pain. */ | |
e972090a NC |
13441 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13442 | { | |
e7af610e NC |
13443 | /* MIPS1 ISA */ |
13444 | { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, | |
13445 | { "mips", 1, ISA_MIPS1, CPU_R3000, }, | |
13446 | ||
13447 | /* MIPS2 ISA */ | |
13448 | { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, | |
13449 | ||
13450 | /* MIPS3 ISA */ | |
13451 | { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, | |
13452 | ||
13453 | /* MIPS4 ISA */ | |
13454 | { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, | |
13455 | ||
84ea6cf2 NC |
13456 | /* MIPS5 ISA */ |
13457 | { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, }, | |
13458 | { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, }, | |
13459 | ||
e7af610e NC |
13460 | /* MIPS32 ISA */ |
13461 | { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, | |
3c02b2ab | 13462 | { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, }, |
e7af610e | 13463 | { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, |
3c02b2ab EC |
13464 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, |
13465 | { "4km", 0, ISA_MIPS32, CPU_MIPS32, }, | |
13466 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32, }, | |
13467 | ||
13468 | /* For historical reasons. */ | |
13469 | { "MIPS64", 1, ISA_MIPS3, CPU_R4000, }, | |
e7af610e | 13470 | |
84ea6cf2 | 13471 | /* MIPS64 ISA */ |
3c02b2ab | 13472 | { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, }, |
84ea6cf2 | 13473 | { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, }, |
3c02b2ab EC |
13474 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64, }, |
13475 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64, }, | |
e7af610e NC |
13476 | |
13477 | /* R2000 CPU */ | |
13478 | { "R2000", 0, ISA_MIPS1, CPU_R2000, }, | |
13479 | { "2000", 0, ISA_MIPS1, CPU_R2000, }, | |
13480 | { "2k", 0, ISA_MIPS1, CPU_R2000, }, | |
13481 | { "r2k", 0, ISA_MIPS1, CPU_R2000, }, | |
13482 | ||
13483 | /* R3000 CPU */ | |
13484 | { "R3000", 0, ISA_MIPS1, CPU_R3000, }, | |
13485 | { "3000", 0, ISA_MIPS1, CPU_R3000, }, | |
13486 | { "3k", 0, ISA_MIPS1, CPU_R3000, }, | |
13487 | { "r3k", 0, ISA_MIPS1, CPU_R3000, }, | |
13488 | ||
13489 | /* TX3900 CPU */ | |
13490 | { "R3900", 0, ISA_MIPS1, CPU_R3900, }, | |
13491 | { "3900", 0, ISA_MIPS1, CPU_R3900, }, | |
e972090a | 13492 | { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, |
e7af610e NC |
13493 | |
13494 | /* R4000 CPU */ | |
13495 | { "R4000", 0, ISA_MIPS3, CPU_R4000, }, | |
13496 | { "4000", 0, ISA_MIPS3, CPU_R4000, }, | |
13497 | { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ | |
13498 | { "r4k", 0, ISA_MIPS3, CPU_R4000, }, | |
13499 | ||
13500 | /* R4010 CPU */ | |
13501 | { "R4010", 0, ISA_MIPS2, CPU_R4010, }, | |
13502 | { "4010", 0, ISA_MIPS2, CPU_R4010, }, | |
13503 | ||
13504 | /* R4400 CPU */ | |
13505 | { "R4400", 0, ISA_MIPS3, CPU_R4400, }, | |
13506 | { "4400", 0, ISA_MIPS3, CPU_R4400, }, | |
13507 | ||
13508 | /* R4600 CPU */ | |
13509 | { "R4600", 0, ISA_MIPS3, CPU_R4600, }, | |
13510 | { "4600", 0, ISA_MIPS3, CPU_R4600, }, | |
13511 | { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, | |
13512 | { "orion", 0, ISA_MIPS3, CPU_R4600, }, | |
13513 | ||
13514 | /* R4650 CPU */ | |
13515 | { "R4650", 0, ISA_MIPS3, CPU_R4650, }, | |
13516 | { "4650", 0, ISA_MIPS3, CPU_R4650, }, | |
13517 | ||
13518 | /* R6000 CPU */ | |
13519 | { "R6000", 0, ISA_MIPS2, CPU_R6000, }, | |
13520 | { "6000", 0, ISA_MIPS2, CPU_R6000, }, | |
13521 | { "6k", 0, ISA_MIPS2, CPU_R6000, }, | |
13522 | { "r6k", 0, ISA_MIPS2, CPU_R6000, }, | |
13523 | ||
13524 | /* R8000 CPU */ | |
13525 | { "R8000", 0, ISA_MIPS4, CPU_R8000, }, | |
13526 | { "8000", 0, ISA_MIPS4, CPU_R8000, }, | |
13527 | { "8k", 0, ISA_MIPS4, CPU_R8000, }, | |
13528 | { "r8k", 0, ISA_MIPS4, CPU_R8000, }, | |
13529 | ||
13530 | /* R10000 CPU */ | |
13531 | { "R10000", 0, ISA_MIPS4, CPU_R10000, }, | |
13532 | { "10000", 0, ISA_MIPS4, CPU_R10000, }, | |
13533 | { "10k", 0, ISA_MIPS4, CPU_R10000, }, | |
13534 | { "r10k", 0, ISA_MIPS4, CPU_R10000, }, | |
13535 | ||
d1cf510e NC |
13536 | /* R12000 CPU */ |
13537 | { "R12000", 0, ISA_MIPS4, CPU_R12000, }, | |
13538 | { "12000", 0, ISA_MIPS4, CPU_R12000, }, | |
13539 | { "12k", 0, ISA_MIPS4, CPU_R12000, }, | |
13540 | { "r12k", 0, ISA_MIPS4, CPU_R12000, }, | |
13541 | ||
e7af610e NC |
13542 | /* VR4100 CPU */ |
13543 | { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13544 | { "4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13545 | { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13546 | { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, | |
13547 | ||
13548 | /* VR4111 CPU */ | |
13549 | { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13550 | { "4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13551 | { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13552 | { "r4111", 0, ISA_MIPS3, CPU_R4111, }, | |
13553 | ||
13554 | /* VR4300 CPU */ | |
13555 | { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13556 | { "4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13557 | { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13558 | { "r4300", 0, ISA_MIPS3, CPU_R4300, }, | |
13559 | ||
13560 | /* VR5000 CPU */ | |
13561 | { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13562 | { "5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13563 | { "5k", 0, ISA_MIPS4, CPU_R5000, }, | |
13564 | { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13565 | { "r5000", 0, ISA_MIPS4, CPU_R5000, }, | |
13566 | { "r5200", 0, ISA_MIPS4, CPU_R5000, }, | |
18ae5d72 | 13567 | { "rm5200", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13568 | { "r5230", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13569 | { "rm5230", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13570 | { "r5231", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13571 | { "rm5231", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13572 | { "r5261", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13573 | { "rm5261", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e | 13574 | { "r5721", 0, ISA_MIPS4, CPU_R5000, }, |
18ae5d72 | 13575 | { "rm5721", 0, ISA_MIPS4, CPU_R5000, }, |
e7af610e NC |
13576 | { "r5k", 0, ISA_MIPS4, CPU_R5000, }, |
13577 | { "r7000", 0, ISA_MIPS4, CPU_R5000, }, | |
13578 | ||
2e4acd24 | 13579 | /* Broadcom SB-1 CPU */ |
c6c98b38 | 13580 | { "SB-1", 0, ISA_MIPS64, CPU_SB1, }, |
e972090a | 13581 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1, }, |
c6c98b38 NC |
13582 | { "sb1", 0, ISA_MIPS64, CPU_SB1, }, |
13583 | { "sb1250", 0, ISA_MIPS64, CPU_SB1, }, | |
13584 | ||
beae10d5 | 13585 | /* End marker. */ |
e7af610e NC |
13586 | { NULL, 0, 0, 0, }, |
13587 | }; | |
13588 | ||
13589 | static const struct mips_cpu_info * | |
13590 | mips_cpu_info_from_name (name) | |
13591 | const char *name; | |
13592 | { | |
13593 | int i; | |
13594 | ||
13595 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
beae10d5 | 13596 | if (strcasecmp (name, mips_cpu_info_table[i].name) == 0) |
e7af610e NC |
13597 | return (&mips_cpu_info_table[i]); |
13598 | ||
e972090a | 13599 | return NULL; |
e7af610e NC |
13600 | } |
13601 | ||
13602 | static const struct mips_cpu_info * | |
13603 | mips_cpu_info_from_isa (isa) | |
13604 | int isa; | |
13605 | { | |
13606 | int i; | |
13607 | ||
13608 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13609 | if (mips_cpu_info_table[i].is_isa | |
13610 | && isa == mips_cpu_info_table[i].isa) | |
13611 | return (&mips_cpu_info_table[i]); | |
13612 | ||
e972090a | 13613 | return NULL; |
e7af610e NC |
13614 | } |
13615 | ||
13616 | static const struct mips_cpu_info * | |
13617 | mips_cpu_info_from_cpu (cpu) | |
13618 | int cpu; | |
13619 | { | |
13620 | int i; | |
13621 | ||
13622 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13623 | if (!mips_cpu_info_table[i].is_isa | |
13624 | && cpu == mips_cpu_info_table[i].cpu) | |
13625 | return (&mips_cpu_info_table[i]); | |
13626 | ||
e972090a | 13627 | return NULL; |
e7af610e | 13628 | } |