Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 | 36 | |
42429eac RS |
37 | /* Check assumptions made in this file. */ |
38 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
39 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
40 | ||
252b5132 RH |
41 | #ifdef DEBUG |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
252b5132 | 47 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
48 | static int mips_output_flavor (void); |
49 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
50 | #undef OBJ_PROCESS_STAB |
51 | #undef OUTPUT_FLAVOR | |
52 | #undef S_GET_ALIGN | |
53 | #undef S_GET_SIZE | |
54 | #undef S_SET_ALIGN | |
55 | #undef S_SET_SIZE | |
252b5132 RH |
56 | #undef obj_frob_file |
57 | #undef obj_frob_file_after_relocs | |
58 | #undef obj_frob_symbol | |
59 | #undef obj_pop_insert | |
60 | #undef obj_sec_sym_ok_for_reloc | |
61 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
62 | ||
63 | #include "obj-elf.h" | |
64 | /* Fix any of them that we actually care about. */ | |
65 | #undef OUTPUT_FLAVOR | |
66 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 67 | |
252b5132 | 68 | #include "elf/mips.h" |
252b5132 RH |
69 | |
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
252b5132 | 88 | static char *mips_regmask_frag; |
252b5132 | 89 | |
85b51719 | 90 | #define ZERO 0 |
741fe287 | 91 | #define ATREG 1 |
df58fc94 RS |
92 | #define S0 16 |
93 | #define S7 23 | |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | extern int target_big_endian; |
108 | ||
252b5132 | 109 | /* The name of the readonly data section. */ |
e8044f35 | 110 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 111 | |
a4e06468 RS |
112 | /* Ways in which an instruction can be "appended" to the output. */ |
113 | enum append_method { | |
114 | /* Just add it normally. */ | |
115 | APPEND_ADD, | |
116 | ||
117 | /* Add it normally and then add a nop. */ | |
118 | APPEND_ADD_WITH_NOP, | |
119 | ||
120 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
121 | APPEND_ADD_COMPACT, | |
122 | ||
123 | /* Insert the instruction before the last one. */ | |
124 | APPEND_SWAP | |
125 | }; | |
126 | ||
47e39b9d RS |
127 | /* Information about an instruction, including its format, operands |
128 | and fixups. */ | |
129 | struct mips_cl_insn | |
130 | { | |
131 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
132 | const struct mips_opcode *insn_mo; | |
133 | ||
47e39b9d | 134 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
135 | a copy of INSN_MO->match with the operands filled in. If we have |
136 | decided to use an extended MIPS16 instruction, this includes the | |
137 | extension. */ | |
47e39b9d RS |
138 | unsigned long insn_opcode; |
139 | ||
140 | /* The frag that contains the instruction. */ | |
141 | struct frag *frag; | |
142 | ||
143 | /* The offset into FRAG of the first instruction byte. */ | |
144 | long where; | |
145 | ||
146 | /* The relocs associated with the instruction, if any. */ | |
147 | fixS *fixp[3]; | |
148 | ||
a38419a5 RS |
149 | /* True if this entry cannot be moved from its current position. */ |
150 | unsigned int fixed_p : 1; | |
47e39b9d | 151 | |
708587a4 | 152 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
153 | unsigned int noreorder_p : 1; |
154 | ||
2fa15973 RS |
155 | /* True for mips16 instructions that jump to an absolute address. */ |
156 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
157 | |
158 | /* True if this instruction is complete. */ | |
159 | unsigned int complete_p : 1; | |
e407c74b NC |
160 | |
161 | /* True if this instruction is cleared from history by unconditional | |
162 | branch. */ | |
163 | unsigned int cleared_p : 1; | |
47e39b9d RS |
164 | }; |
165 | ||
a325df1d TS |
166 | /* The ABI to use. */ |
167 | enum mips_abi_level | |
168 | { | |
169 | NO_ABI = 0, | |
170 | O32_ABI, | |
171 | O64_ABI, | |
172 | N32_ABI, | |
173 | N64_ABI, | |
174 | EABI_ABI | |
175 | }; | |
176 | ||
177 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 178 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 179 | |
143d77c5 EC |
180 | /* Whether or not we have code that can call pic code. */ |
181 | int mips_abicalls = FALSE; | |
182 | ||
aa6975fb ILT |
183 | /* Whether or not we have code which can be put into a shared |
184 | library. */ | |
185 | static bfd_boolean mips_in_shared = TRUE; | |
186 | ||
252b5132 RH |
187 | /* This is the set of options which may be modified by the .set |
188 | pseudo-op. We use a struct so that .set push and .set pop are more | |
189 | reliable. */ | |
190 | ||
e972090a NC |
191 | struct mips_set_options |
192 | { | |
252b5132 RH |
193 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
194 | if it has not been initialized. Changed by `.set mipsN', and the | |
195 | -mipsN command line option, and the default CPU. */ | |
196 | int isa; | |
846ef2d0 RS |
197 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
198 | <asename>', by command line options, and based on the default | |
199 | architecture. */ | |
200 | int ase; | |
252b5132 RH |
201 | /* Whether we are assembling for the mips16 processor. 0 if we are |
202 | not, 1 if we are, and -1 if the value has not been initialized. | |
203 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
204 | -nomips16 command line options, and the default CPU. */ | |
205 | int mips16; | |
df58fc94 RS |
206 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
207 | 1 if we are, and -1 if the value has not been initialized. Changed | |
208 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
209 | and -mno-micromips command line options, and the default CPU. */ | |
210 | int micromips; | |
252b5132 RH |
211 | /* Non-zero if we should not reorder instructions. Changed by `.set |
212 | reorder' and `.set noreorder'. */ | |
213 | int noreorder; | |
741fe287 MR |
214 | /* Non-zero if we should not permit the register designated "assembler |
215 | temporary" to be used in instructions. The value is the register | |
216 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
217 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
218 | unsigned int at; | |
252b5132 RH |
219 | /* Non-zero if we should warn when a macro instruction expands into |
220 | more than one machine instruction. Changed by `.set nomacro' and | |
221 | `.set macro'. */ | |
222 | int warn_about_macros; | |
223 | /* Non-zero if we should not move instructions. Changed by `.set | |
224 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
225 | int nomove; | |
226 | /* Non-zero if we should not optimize branches by moving the target | |
227 | of the branch into the delay slot. Actually, we don't perform | |
228 | this optimization anyhow. Changed by `.set bopt' and `.set | |
229 | nobopt'. */ | |
230 | int nobopt; | |
231 | /* Non-zero if we should not autoextend mips16 instructions. | |
232 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
233 | int noautoextend; | |
833794fc MR |
234 | /* True if we should only emit 32-bit microMIPS instructions. |
235 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
236 | and -mno-insn32 command line options. */ | |
237 | bfd_boolean insn32; | |
a325df1d TS |
238 | /* Restrict general purpose registers and floating point registers |
239 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
240 | is passed but can changed if the assembler code uses .set mipsN. */ | |
241 | int gp32; | |
242 | int fp32; | |
fef14a42 TS |
243 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
244 | command line option, and the default CPU. */ | |
245 | int arch; | |
aed1a261 RS |
246 | /* True if ".set sym32" is in effect. */ |
247 | bfd_boolean sym32; | |
037b32b9 AN |
248 | /* True if floating-point operations are not allowed. Changed by .set |
249 | softfloat or .set hardfloat, by command line options -msoft-float or | |
250 | -mhard-float. The default is false. */ | |
251 | bfd_boolean soft_float; | |
252 | ||
253 | /* True if only single-precision floating-point operations are allowed. | |
254 | Changed by .set singlefloat or .set doublefloat, command-line options | |
255 | -msingle-float or -mdouble-float. The default is false. */ | |
256 | bfd_boolean single_float; | |
252b5132 RH |
257 | }; |
258 | ||
037b32b9 AN |
259 | /* This is the struct we use to hold the current set of options. Note |
260 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
261 | -1 to indicate that they have not been initialized. */ | |
262 | ||
a325df1d | 263 | /* True if -mgp32 was passed. */ |
a8e8e863 | 264 | static int file_mips_gp32 = -1; |
a325df1d TS |
265 | |
266 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 267 | static int file_mips_fp32 = -1; |
a325df1d | 268 | |
037b32b9 AN |
269 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
270 | static int file_mips_soft_float = 0; | |
271 | ||
272 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
273 | static int file_mips_single_float = 0; | |
252b5132 | 274 | |
ba92f887 MR |
275 | /* True if -mnan=2008, false if -mnan=legacy. */ |
276 | static bfd_boolean mips_flag_nan2008 = FALSE; | |
277 | ||
e972090a NC |
278 | static struct mips_set_options mips_opts = |
279 | { | |
846ef2d0 | 280 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 281 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc MR |
282 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
283 | /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, | |
b015e599 | 284 | /* soft_float */ FALSE, /* single_float */ FALSE |
e7af610e | 285 | }; |
252b5132 | 286 | |
846ef2d0 RS |
287 | /* The set of ASEs that were selected on the command line, either |
288 | explicitly via ASE options or implicitly through things like -march. */ | |
289 | static unsigned int file_ase; | |
290 | ||
291 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ | |
292 | static unsigned int file_ase_explicit; | |
293 | ||
252b5132 RH |
294 | /* These variables are filled in with the masks of registers used. |
295 | The object format code reads them and puts them in the appropriate | |
296 | place. */ | |
297 | unsigned long mips_gprmask; | |
298 | unsigned long mips_cprmask[4]; | |
299 | ||
300 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 301 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 302 | |
738f4d98 | 303 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
304 | static int file_ase_mips16; |
305 | ||
3994f87e TS |
306 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
307 | || mips_opts.isa == ISA_MIPS32R2 \ | |
308 | || mips_opts.isa == ISA_MIPS64 \ | |
309 | || mips_opts.isa == ISA_MIPS64R2) | |
310 | ||
df58fc94 RS |
311 | /* True if any microMIPS code was produced. */ |
312 | static int file_ase_micromips; | |
313 | ||
b12dd2e4 CF |
314 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
315 | #ifdef TE_IRIX | |
1180b5a4 | 316 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 317 | #else |
1180b5a4 RS |
318 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
319 | because there's no place for any addend, the only acceptable | |
320 | expression is a bare symbol. */ | |
321 | #define MIPS_JALR_HINT_P(EXPR) \ | |
322 | (!HAVE_IN_PLACE_ADDENDS \ | |
323 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
324 | #endif |
325 | ||
ec68c924 | 326 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 327 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 328 | static const char *mips_arch_string; |
ec68c924 EC |
329 | |
330 | /* The argument of the -mtune= flag. The architecture for which we | |
331 | are optimizing. */ | |
332 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 333 | static const char *mips_tune_string; |
ec68c924 | 334 | |
316f5878 | 335 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
336 | static int mips_32bitmode = 0; |
337 | ||
316f5878 RS |
338 | /* True if the given ABI requires 32-bit registers. */ |
339 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
340 | ||
341 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
342 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
343 | ((ABI) == N32_ABI \ | |
344 | || (ABI) == N64_ABI \ | |
316f5878 RS |
345 | || (ABI) == O64_ABI) |
346 | ||
ad3fea08 | 347 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
348 | #define ISA_HAS_64BIT_REGS(ISA) \ |
349 | ((ISA) == ISA_MIPS3 \ | |
350 | || (ISA) == ISA_MIPS4 \ | |
351 | || (ISA) == ISA_MIPS5 \ | |
352 | || (ISA) == ISA_MIPS64 \ | |
353 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 354 | |
ad3fea08 TS |
355 | /* Return true if ISA supports 64 bit wide float registers. */ |
356 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
357 | ((ISA) == ISA_MIPS3 \ | |
358 | || (ISA) == ISA_MIPS4 \ | |
359 | || (ISA) == ISA_MIPS5 \ | |
360 | || (ISA) == ISA_MIPS32R2 \ | |
361 | || (ISA) == ISA_MIPS64 \ | |
362 | || (ISA) == ISA_MIPS64R2) | |
363 | ||
af7ee8bf CD |
364 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
365 | instructions. */ | |
707bfff6 | 366 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
367 | ((ISA) == ISA_MIPS64R2 \ |
368 | || (mips_opts.micromips \ | |
369 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
370 | ) | |
af7ee8bf CD |
371 | |
372 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
373 | instructions. */ | |
707bfff6 TS |
374 | #define ISA_HAS_ROR(ISA) \ |
375 | ((ISA) == ISA_MIPS32R2 \ | |
376 | || (ISA) == ISA_MIPS64R2 \ | |
846ef2d0 | 377 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
378 | || mips_opts.micromips \ |
379 | ) | |
707bfff6 | 380 | |
7455baf8 TS |
381 | /* Return true if ISA supports single-precision floats in odd registers. */ |
382 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
383 | ((ISA) == ISA_MIPS32 \ | |
384 | || (ISA) == ISA_MIPS32R2 \ | |
385 | || (ISA) == ISA_MIPS64 \ | |
386 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 387 | |
ad3fea08 TS |
388 | /* Return true if ISA supports move to/from high part of a 64-bit |
389 | floating-point register. */ | |
390 | #define ISA_HAS_MXHC1(ISA) \ | |
391 | ((ISA) == ISA_MIPS32R2 \ | |
392 | || (ISA) == ISA_MIPS64R2) | |
393 | ||
e013f690 | 394 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 395 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 396 | |
e013f690 | 397 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 398 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 399 | |
ad3fea08 TS |
400 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
401 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 402 | |
316f5878 | 403 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 404 | |
316f5878 | 405 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 406 | |
3b91255e RS |
407 | /* True if relocations are stored in-place. */ |
408 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
409 | ||
aed1a261 RS |
410 | /* The ABI-derived address size. */ |
411 | #define HAVE_64BIT_ADDRESSES \ | |
412 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
413 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 414 | |
aed1a261 RS |
415 | /* The size of symbolic constants (i.e., expressions of the form |
416 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
417 | #define HAVE_32BIT_SYMBOLS \ | |
418 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
419 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 420 | |
b7c7d6c1 TS |
421 | /* Addresses are loaded in different ways, depending on the address size |
422 | in use. The n32 ABI Documentation also mandates the use of additions | |
423 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 424 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 425 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
426 | |
427 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 428 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
429 | |
430 | #define ADDRESS_LOAD_INSN \ | |
431 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
432 | ||
433 | #define ADDRESS_STORE_INSN \ | |
434 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
435 | ||
a4672219 | 436 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
437 | #define CPU_HAS_MIPS16(cpu) \ |
438 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
439 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 440 | |
2309ddf2 | 441 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
442 | #define CPU_HAS_MICROMIPS(cpu) 0 |
443 | ||
60b63b72 RS |
444 | /* True if CPU has a dror instruction. */ |
445 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
446 | ||
447 | /* True if CPU has a ror instruction. */ | |
448 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
449 | ||
dd6a37e7 | 450 | /* True if CPU is in the Octeon family */ |
432233b3 | 451 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 452 | |
dd3cbb7e | 453 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 454 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 455 | |
0aa27725 RS |
456 | /* True, if CPU has support for ldc1 and sdc1. */ |
457 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
458 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
459 | ||
c8978940 CD |
460 | /* True if mflo and mfhi can be immediately followed by instructions |
461 | which write to the HI and LO registers. | |
462 | ||
463 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
464 | (at least) two instructions between the reads of HI/LO and | |
465 | instructions which write them, and later ISAs do not. Contradicting | |
466 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
467 | the UM for the NEC Vr5000) document needing the instructions between | |
468 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
469 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
470 | earlier-ISA CPUs for which CPU documentation declares that the | |
471 | instructions are really interlocked. */ | |
472 | #define hilo_interlocks \ | |
473 | (mips_opts.isa == ISA_MIPS32 \ | |
474 | || mips_opts.isa == ISA_MIPS32R2 \ | |
475 | || mips_opts.isa == ISA_MIPS64 \ | |
476 | || mips_opts.isa == ISA_MIPS64R2 \ | |
477 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 478 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
479 | || mips_opts.arch == CPU_R10000 \ |
480 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
481 | || mips_opts.arch == CPU_R14000 \ |
482 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 483 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 484 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 485 | || mips_opts.micromips \ |
c8978940 | 486 | ) |
252b5132 RH |
487 | |
488 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
489 | from the GPRs after they are loaded from memory, and thus does not |
490 | require nops to be inserted. This applies to instructions marked | |
491 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
492 | level I and microMIPS mode instructions are always interlocked. */ |
493 | #define gpr_interlocks \ | |
494 | (mips_opts.isa != ISA_MIPS1 \ | |
495 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 496 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
497 | || mips_opts.micromips \ |
498 | ) | |
252b5132 | 499 | |
81912461 ILT |
500 | /* Whether the processor uses hardware interlocks to avoid delays |
501 | required by coprocessor instructions, and thus does not require | |
502 | nops to be inserted. This applies to instructions marked | |
503 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
504 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
505 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
506 | levels I, II, and III and microMIPS mode instructions are always |
507 | interlocked. */ | |
bdaaa2e1 | 508 | /* Itbl support may require additional care here. */ |
81912461 ILT |
509 | #define cop_interlocks \ |
510 | ((mips_opts.isa != ISA_MIPS1 \ | |
511 | && mips_opts.isa != ISA_MIPS2 \ | |
512 | && mips_opts.isa != ISA_MIPS3) \ | |
513 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 514 | || mips_opts.micromips \ |
81912461 ILT |
515 | ) |
516 | ||
517 | /* Whether the processor uses hardware interlocks to protect reads | |
518 | from coprocessor registers after they are loaded from memory, and | |
519 | thus does not require nops to be inserted. This applies to | |
520 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
521 | requires at MIPS ISA level I and microMIPS mode instructions are |
522 | always interlocked. */ | |
523 | #define cop_mem_interlocks \ | |
524 | (mips_opts.isa != ISA_MIPS1 \ | |
525 | || mips_opts.micromips \ | |
526 | ) | |
252b5132 | 527 | |
6b76fefe CM |
528 | /* Is this a mfhi or mflo instruction? */ |
529 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
530 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
531 | ||
df58fc94 RS |
532 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
533 | has been selected. This implies, in particular, that addresses of text | |
534 | labels have their LSB set. */ | |
535 | #define HAVE_CODE_COMPRESSION \ | |
536 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
537 | ||
42429eac RS |
538 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
539 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1)) | |
540 | #define GPR_SMIN (-GPR_SMAX - 1) | |
541 | ||
252b5132 RH |
542 | /* MIPS PIC level. */ |
543 | ||
a161fe53 | 544 | enum mips_pic_level mips_pic; |
252b5132 | 545 | |
c9914766 | 546 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 547 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 548 | static int mips_big_got = 0; |
252b5132 RH |
549 | |
550 | /* 1 if trap instructions should used for overflow rather than break | |
551 | instructions. */ | |
c9914766 | 552 | static int mips_trap = 0; |
252b5132 | 553 | |
119d663a | 554 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 555 | by assembling two single width halves into two single width floating |
119d663a NC |
556 | point registers which just happen to alias the double width destination |
557 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 558 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
559 | automatically at assemble time. */ |
560 | static int mips_disable_float_construction; | |
561 | ||
252b5132 RH |
562 | /* Non-zero if any .set noreorder directives were used. */ |
563 | ||
564 | static int mips_any_noreorder; | |
565 | ||
6b76fefe CM |
566 | /* Non-zero if nops should be inserted when the register referenced in |
567 | an mfhi/mflo instruction is read in the next two instructions. */ | |
568 | static int mips_7000_hilo_fix; | |
569 | ||
02ffd3e4 | 570 | /* The size of objects in the small data section. */ |
156c2f8b | 571 | static unsigned int g_switch_value = 8; |
252b5132 RH |
572 | /* Whether the -G option was used. */ |
573 | static int g_switch_seen = 0; | |
574 | ||
575 | #define N_RMASK 0xc4 | |
576 | #define N_VFP 0xd4 | |
577 | ||
578 | /* If we can determine in advance that GP optimization won't be | |
579 | possible, we can skip the relaxation stuff that tries to produce | |
580 | GP-relative references. This makes delay slot optimization work | |
581 | better. | |
582 | ||
583 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
584 | gcc output. It needs to guess right for gcc, otherwise gcc |
585 | will put what it thinks is a GP-relative instruction in a branch | |
586 | delay slot. | |
252b5132 RH |
587 | |
588 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
589 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 590 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
591 | |
592 | /* handle of the OPCODE hash table */ | |
593 | static struct hash_control *op_hash = NULL; | |
594 | ||
595 | /* The opcode hash table we use for the mips16. */ | |
596 | static struct hash_control *mips16_op_hash = NULL; | |
597 | ||
df58fc94 RS |
598 | /* The opcode hash table we use for the microMIPS ASE. */ |
599 | static struct hash_control *micromips_op_hash = NULL; | |
600 | ||
252b5132 RH |
601 | /* This array holds the chars that always start a comment. If the |
602 | pre-processor is disabled, these aren't very useful */ | |
603 | const char comment_chars[] = "#"; | |
604 | ||
605 | /* This array holds the chars that only start a comment at the beginning of | |
606 | a line. If the line seems to have the form '# 123 filename' | |
607 | .line and .file directives will appear in the pre-processed output */ | |
608 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
609 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 610 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
611 | /* Also note that C style comments are always supported. */ |
612 | const char line_comment_chars[] = "#"; | |
613 | ||
bdaaa2e1 | 614 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 615 | const char line_separator_chars[] = ";"; |
252b5132 RH |
616 | |
617 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
618 | const char EXP_CHARS[] = "eE"; | |
619 | ||
620 | /* Chars that mean this number is a floating point constant */ | |
621 | /* As in 0f12.456 */ | |
622 | /* or 0d1.2345e12 */ | |
623 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
624 | ||
625 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
626 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
627 | but nothing is ideal around here. | |
628 | */ | |
629 | ||
630 | static char *insn_error; | |
631 | ||
632 | static int auto_align = 1; | |
633 | ||
634 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
635 | offset in the stack frame from which to restore the $gp register. | |
636 | This is set by the .cprestore pseudo-op, and saved in this | |
637 | variable. */ | |
638 | static offsetT mips_cprestore_offset = -1; | |
639 | ||
67c1ffbe | 640 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 641 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 642 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
643 | static offsetT mips_cpreturn_offset = -1; |
644 | static int mips_cpreturn_register = -1; | |
645 | static int mips_gp_register = GP; | |
def2e0dd | 646 | static int mips_gprel_offset = 0; |
6478892d | 647 | |
7a621144 DJ |
648 | /* Whether mips_cprestore_offset has been set in the current function |
649 | (or whether it has already been warned about, if not). */ | |
650 | static int mips_cprestore_valid = 0; | |
651 | ||
252b5132 RH |
652 | /* This is the register which holds the stack frame, as set by the |
653 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
654 | static int mips_frame_reg = SP; | |
655 | ||
7a621144 DJ |
656 | /* Whether mips_frame_reg has been set in the current function |
657 | (or whether it has already been warned about, if not). */ | |
658 | static int mips_frame_reg_valid = 0; | |
659 | ||
252b5132 RH |
660 | /* To output NOP instructions correctly, we need to keep information |
661 | about the previous two instructions. */ | |
662 | ||
663 | /* Whether we are optimizing. The default value of 2 means to remove | |
664 | unneeded NOPs and swap branch instructions when possible. A value | |
665 | of 1 means to not swap branches. A value of 0 means to always | |
666 | insert NOPs. */ | |
667 | static int mips_optimize = 2; | |
668 | ||
669 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
670 | equivalent to seeing no -g option at all. */ | |
671 | static int mips_debug = 0; | |
672 | ||
7d8e00cf RS |
673 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
674 | #define MAX_VR4130_NOPS 4 | |
675 | ||
676 | /* The maximum number of NOPs needed to fill delay slots. */ | |
677 | #define MAX_DELAY_NOPS 2 | |
678 | ||
679 | /* The maximum number of NOPs needed for any purpose. */ | |
680 | #define MAX_NOPS 4 | |
71400594 RS |
681 | |
682 | /* A list of previous instructions, with index 0 being the most recent. | |
683 | We need to look back MAX_NOPS instructions when filling delay slots | |
684 | or working around processor errata. We need to look back one | |
685 | instruction further if we're thinking about using history[0] to | |
686 | fill a branch delay slot. */ | |
687 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 688 | |
1e915849 | 689 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
690 | static struct mips_cl_insn nop_insn; |
691 | static struct mips_cl_insn mips16_nop_insn; | |
692 | static struct mips_cl_insn micromips_nop16_insn; | |
693 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
694 | |
695 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
696 | #define NOP_INSN (mips_opts.mips16 \ |
697 | ? &mips16_nop_insn \ | |
698 | : (mips_opts.micromips \ | |
699 | ? (mips_opts.insn32 \ | |
700 | ? µmips_nop32_insn \ | |
701 | : µmips_nop16_insn) \ | |
702 | : &nop_insn)) | |
df58fc94 RS |
703 | |
704 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
705 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
706 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
707 | ? 2 : 4) | |
252b5132 | 708 | |
252b5132 RH |
709 | /* If this is set, it points to a frag holding nop instructions which |
710 | were inserted before the start of a noreorder section. If those | |
711 | nops turn out to be unnecessary, the size of the frag can be | |
712 | decreased. */ | |
713 | static fragS *prev_nop_frag; | |
714 | ||
715 | /* The number of nop instructions we created in prev_nop_frag. */ | |
716 | static int prev_nop_frag_holds; | |
717 | ||
718 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 719 | prev_nop_frag. */ |
252b5132 RH |
720 | static int prev_nop_frag_required; |
721 | ||
722 | /* The number of instructions we've seen since prev_nop_frag. */ | |
723 | static int prev_nop_frag_since; | |
724 | ||
e8044f35 RS |
725 | /* Relocations against symbols are sometimes done in two parts, with a HI |
726 | relocation and a LO relocation. Each relocation has only 16 bits of | |
727 | space to store an addend. This means that in order for the linker to | |
728 | handle carries correctly, it must be able to locate both the HI and | |
729 | the LO relocation. This means that the relocations must appear in | |
730 | order in the relocation table. | |
252b5132 RH |
731 | |
732 | In order to implement this, we keep track of each unmatched HI | |
733 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 734 | corresponding LO relocation. */ |
252b5132 | 735 | |
e972090a NC |
736 | struct mips_hi_fixup |
737 | { | |
252b5132 RH |
738 | /* Next HI fixup. */ |
739 | struct mips_hi_fixup *next; | |
740 | /* This fixup. */ | |
741 | fixS *fixp; | |
742 | /* The section this fixup is in. */ | |
743 | segT seg; | |
744 | }; | |
745 | ||
746 | /* The list of unmatched HI relocs. */ | |
747 | ||
748 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
749 | ||
64bdfcaf RS |
750 | /* The frag containing the last explicit relocation operator. |
751 | Null if explicit relocations have not been used. */ | |
752 | ||
753 | static fragS *prev_reloc_op_frag; | |
754 | ||
252b5132 RH |
755 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
756 | ||
757 | #define X ILLEGAL_REG | |
e972090a NC |
758 | static const int mips32_to_16_reg_map[] = |
759 | { | |
252b5132 RH |
760 | X, X, 2, 3, 4, 5, 6, 7, |
761 | X, X, X, X, X, X, X, X, | |
762 | 0, 1, X, X, X, X, X, X, | |
763 | X, X, X, X, X, X, X, X | |
764 | }; | |
765 | #undef X | |
766 | ||
767 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
768 | ||
e972090a NC |
769 | static const unsigned int mips16_to_32_reg_map[] = |
770 | { | |
252b5132 RH |
771 | 16, 17, 2, 3, 4, 5, 6, 7 |
772 | }; | |
60b63b72 | 773 | |
df58fc94 RS |
774 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
775 | ||
776 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
777 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
778 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
779 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
780 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
781 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
782 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
783 | ||
784 | #define X ILLEGAL_REG | |
df58fc94 RS |
785 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ |
786 | static const int mips32_to_micromips_reg_m_map[] = | |
787 | { | |
788 | 0, X, 2, 3, X, X, X, X, | |
789 | X, X, X, X, X, X, X, X, | |
790 | 4, 1, 5, 6, 7, X, X, X, | |
791 | X, X, X, X, X, X, X, X | |
792 | }; | |
793 | ||
794 | /* reg type q: 0, 2-7. 17. */ | |
795 | static const int mips32_to_micromips_reg_q_map[] = | |
796 | { | |
797 | 0, X, 2, 3, 4, 5, 6, 7, | |
798 | X, X, X, X, X, X, X, X, | |
799 | X, 1, X, X, X, X, X, X, | |
800 | X, X, X, X, X, X, X, X | |
801 | }; | |
802 | ||
803 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
804 | #undef X | |
805 | ||
806 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
807 | ||
808 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
809 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
810 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
811 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
812 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
813 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
814 | ||
815 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 816 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
817 | { |
818 | 5, 5, 6, 4, 4, 4, 4, 4 | |
819 | }; | |
e76ff5ab | 820 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
821 | { |
822 | 6, 7, 7, 21, 22, 5, 6, 7 | |
823 | }; | |
824 | ||
825 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
826 | ||
827 | /* The microMIPS registers with type m. */ | |
828 | static const unsigned int micromips_to_32_reg_m_map[] = | |
829 | { | |
830 | 0, 17, 2, 3, 16, 18, 19, 20 | |
831 | }; | |
832 | ||
833 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
834 | ||
835 | /* The microMIPS registers with type q. */ | |
836 | static const unsigned int micromips_to_32_reg_q_map[] = | |
837 | { | |
838 | 0, 17, 2, 3, 4, 5, 6, 7 | |
839 | }; | |
840 | ||
841 | /* microMIPS imm type B. */ | |
842 | static const int micromips_imm_b_map[] = | |
843 | { | |
844 | 1, 4, 8, 12, 16, 20, 24, -1 | |
845 | }; | |
846 | ||
847 | /* microMIPS imm type C. */ | |
848 | static const int micromips_imm_c_map[] = | |
849 | { | |
850 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
851 | }; | |
852 | ||
71400594 RS |
853 | /* Classifies the kind of instructions we're interested in when |
854 | implementing -mfix-vr4120. */ | |
c67a084a NC |
855 | enum fix_vr4120_class |
856 | { | |
71400594 RS |
857 | FIX_VR4120_MACC, |
858 | FIX_VR4120_DMACC, | |
859 | FIX_VR4120_MULT, | |
860 | FIX_VR4120_DMULT, | |
861 | FIX_VR4120_DIV, | |
862 | FIX_VR4120_MTHILO, | |
863 | NUM_FIX_VR4120_CLASSES | |
864 | }; | |
865 | ||
c67a084a NC |
866 | /* ...likewise -mfix-loongson2f-jump. */ |
867 | static bfd_boolean mips_fix_loongson2f_jump; | |
868 | ||
869 | /* ...likewise -mfix-loongson2f-nop. */ | |
870 | static bfd_boolean mips_fix_loongson2f_nop; | |
871 | ||
872 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
873 | static bfd_boolean mips_fix_loongson2f; | |
874 | ||
71400594 RS |
875 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
876 | there must be at least one other instruction between an instruction | |
877 | of type X and an instruction of type Y. */ | |
878 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
879 | ||
880 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 881 | static int mips_fix_vr4120; |
4a6a3df4 | 882 | |
7d8e00cf RS |
883 | /* ...likewise -mfix-vr4130. */ |
884 | static int mips_fix_vr4130; | |
885 | ||
6a32d874 CM |
886 | /* ...likewise -mfix-24k. */ |
887 | static int mips_fix_24k; | |
888 | ||
d954098f DD |
889 | /* ...likewise -mfix-cn63xxp1 */ |
890 | static bfd_boolean mips_fix_cn63xxp1; | |
891 | ||
4a6a3df4 AO |
892 | /* We don't relax branches by default, since this causes us to expand |
893 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
894 | fail to compute the offset before expanding the macro to the most | |
895 | efficient expansion. */ | |
896 | ||
897 | static int mips_relax_branch; | |
252b5132 | 898 | \f |
4d7206a2 RS |
899 | /* The expansion of many macros depends on the type of symbol that |
900 | they refer to. For example, when generating position-dependent code, | |
901 | a macro that refers to a symbol may have two different expansions, | |
902 | one which uses GP-relative addresses and one which uses absolute | |
903 | addresses. When generating SVR4-style PIC, a macro may have | |
904 | different expansions for local and global symbols. | |
905 | ||
906 | We handle these situations by generating both sequences and putting | |
907 | them in variant frags. In position-dependent code, the first sequence | |
908 | will be the GP-relative one and the second sequence will be the | |
909 | absolute one. In SVR4 PIC, the first sequence will be for global | |
910 | symbols and the second will be for local symbols. | |
911 | ||
584892a6 RS |
912 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
913 | SECOND are the lengths of the two sequences in bytes. These fields | |
914 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
915 | the subtype has the following flags: | |
4d7206a2 | 916 | |
584892a6 RS |
917 | RELAX_USE_SECOND |
918 | Set if it has been decided that we should use the second | |
919 | sequence instead of the first. | |
920 | ||
921 | RELAX_SECOND_LONGER | |
922 | Set in the first variant frag if the macro's second implementation | |
923 | is longer than its first. This refers to the macro as a whole, | |
924 | not an individual relaxation. | |
925 | ||
926 | RELAX_NOMACRO | |
927 | Set in the first variant frag if the macro appeared in a .set nomacro | |
928 | block and if one alternative requires a warning but the other does not. | |
929 | ||
930 | RELAX_DELAY_SLOT | |
931 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
932 | delay slot. | |
4d7206a2 | 933 | |
df58fc94 RS |
934 | RELAX_DELAY_SLOT_16BIT |
935 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
936 | 16-bit instruction. | |
937 | ||
938 | RELAX_DELAY_SLOT_SIZE_FIRST | |
939 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
940 | the macro is of the wrong size for the branch delay slot. | |
941 | ||
942 | RELAX_DELAY_SLOT_SIZE_SECOND | |
943 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
944 | the macro is of the wrong size for the branch delay slot. | |
945 | ||
4d7206a2 RS |
946 | The frag's "opcode" points to the first fixup for relaxable code. |
947 | ||
948 | Relaxable macros are generated using a sequence such as: | |
949 | ||
950 | relax_start (SYMBOL); | |
951 | ... generate first expansion ... | |
952 | relax_switch (); | |
953 | ... generate second expansion ... | |
954 | relax_end (); | |
955 | ||
956 | The code and fixups for the unwanted alternative are discarded | |
957 | by md_convert_frag. */ | |
584892a6 | 958 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 959 | |
584892a6 RS |
960 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
961 | #define RELAX_SECOND(X) ((X) & 0xff) | |
962 | #define RELAX_USE_SECOND 0x10000 | |
963 | #define RELAX_SECOND_LONGER 0x20000 | |
964 | #define RELAX_NOMACRO 0x40000 | |
965 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
966 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
967 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
968 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 969 | |
4a6a3df4 AO |
970 | /* Branch without likely bit. If label is out of range, we turn: |
971 | ||
972 | beq reg1, reg2, label | |
973 | delay slot | |
974 | ||
975 | into | |
976 | ||
977 | bne reg1, reg2, 0f | |
978 | nop | |
979 | j label | |
980 | 0: delay slot | |
981 | ||
982 | with the following opcode replacements: | |
983 | ||
984 | beq <-> bne | |
985 | blez <-> bgtz | |
986 | bltz <-> bgez | |
987 | bc1f <-> bc1t | |
988 | ||
989 | bltzal <-> bgezal (with jal label instead of j label) | |
990 | ||
991 | Even though keeping the delay slot instruction in the delay slot of | |
992 | the branch would be more efficient, it would be very tricky to do | |
993 | correctly, because we'd have to introduce a variable frag *after* | |
994 | the delay slot instruction, and expand that instead. Let's do it | |
995 | the easy way for now, even if the branch-not-taken case now costs | |
996 | one additional instruction. Out-of-range branches are not supposed | |
997 | to be common, anyway. | |
998 | ||
999 | Branch likely. If label is out of range, we turn: | |
1000 | ||
1001 | beql reg1, reg2, label | |
1002 | delay slot (annulled if branch not taken) | |
1003 | ||
1004 | into | |
1005 | ||
1006 | beql reg1, reg2, 1f | |
1007 | nop | |
1008 | beql $0, $0, 2f | |
1009 | nop | |
1010 | 1: j[al] label | |
1011 | delay slot (executed only if branch taken) | |
1012 | 2: | |
1013 | ||
1014 | It would be possible to generate a shorter sequence by losing the | |
1015 | likely bit, generating something like: | |
b34976b6 | 1016 | |
4a6a3df4 AO |
1017 | bne reg1, reg2, 0f |
1018 | nop | |
1019 | j[al] label | |
1020 | delay slot (executed only if branch taken) | |
1021 | 0: | |
1022 | ||
1023 | beql -> bne | |
1024 | bnel -> beq | |
1025 | blezl -> bgtz | |
1026 | bgtzl -> blez | |
1027 | bltzl -> bgez | |
1028 | bgezl -> bltz | |
1029 | bc1fl -> bc1t | |
1030 | bc1tl -> bc1f | |
1031 | ||
1032 | bltzall -> bgezal (with jal label instead of j label) | |
1033 | bgezall -> bltzal (ditto) | |
1034 | ||
1035 | ||
1036 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1037 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1038 | ((relax_substateT) \ | |
1039 | (0xc0000000 \ | |
1040 | | ((at) & 0x1f) \ | |
1041 | | ((toofar) ? 0x20 : 0) \ | |
1042 | | ((link) ? 0x40 : 0) \ | |
1043 | | ((likely) ? 0x80 : 0) \ | |
1044 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1045 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1046 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1047 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1048 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1049 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1050 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1051 | |
252b5132 RH |
1052 | /* For mips16 code, we use an entirely different form of relaxation. |
1053 | mips16 supports two versions of most instructions which take | |
1054 | immediate values: a small one which takes some small value, and a | |
1055 | larger one which takes a 16 bit value. Since branches also follow | |
1056 | this pattern, relaxing these values is required. | |
1057 | ||
1058 | We can assemble both mips16 and normal MIPS code in a single | |
1059 | object. Therefore, we need to support this type of relaxation at | |
1060 | the same time that we support the relaxation described above. We | |
1061 | use the high bit of the subtype field to distinguish these cases. | |
1062 | ||
1063 | The information we store for this type of relaxation is the | |
1064 | argument code found in the opcode file for this relocation, whether | |
1065 | the user explicitly requested a small or extended form, and whether | |
1066 | the relocation is in a jump or jal delay slot. That tells us the | |
1067 | size of the value, and how it should be stored. We also store | |
1068 | whether the fragment is considered to be extended or not. We also | |
1069 | store whether this is known to be a branch to a different section, | |
1070 | whether we have tried to relax this frag yet, and whether we have | |
1071 | ever extended a PC relative fragment because of a shift count. */ | |
1072 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1073 | (0x80000000 \ | |
1074 | | ((type) & 0xff) \ | |
1075 | | ((small) ? 0x100 : 0) \ | |
1076 | | ((ext) ? 0x200 : 0) \ | |
1077 | | ((dslot) ? 0x400 : 0) \ | |
1078 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1079 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1080 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1081 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1082 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1083 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1084 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1085 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1086 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1087 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1088 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1089 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1090 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1091 | |
df58fc94 RS |
1092 | /* For microMIPS code, we use relaxation similar to one we use for |
1093 | MIPS16 code. Some instructions that take immediate values support | |
1094 | two encodings: a small one which takes some small value, and a | |
1095 | larger one which takes a 16 bit value. As some branches also follow | |
1096 | this pattern, relaxing these values is required. | |
1097 | ||
1098 | We can assemble both microMIPS and normal MIPS code in a single | |
1099 | object. Therefore, we need to support this type of relaxation at | |
1100 | the same time that we support the relaxation described above. We | |
1101 | use one of the high bits of the subtype field to distinguish these | |
1102 | cases. | |
1103 | ||
1104 | The information we store for this type of relaxation is the argument | |
1105 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1106 | selected as the assembler temporary, whether the branch is |
1107 | unconditional, whether it is compact, whether it stores the link | |
1108 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1109 | branches to a sequence of instructions is enabled, and whether the | |
1110 | displacement of a branch is too large to fit as an immediate argument | |
1111 | of a 16-bit and a 32-bit branch, respectively. */ | |
1112 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1113 | relax32, toofar16, toofar32) \ | |
1114 | (0x40000000 \ | |
1115 | | ((type) & 0xff) \ | |
1116 | | (((at) & 0x1f) << 8) \ | |
1117 | | ((uncond) ? 0x2000 : 0) \ | |
1118 | | ((compact) ? 0x4000 : 0) \ | |
1119 | | ((link) ? 0x8000 : 0) \ | |
1120 | | ((relax32) ? 0x10000 : 0) \ | |
1121 | | ((toofar16) ? 0x20000 : 0) \ | |
1122 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1123 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1124 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1125 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1126 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1127 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1128 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1129 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1130 | ||
1131 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1132 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1133 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1134 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1135 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1136 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1137 | |
43c0598f RS |
1138 | /* Sign-extend 16-bit value X. */ |
1139 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1140 | ||
885add95 CD |
1141 | /* Is the given value a sign-extended 32-bit value? */ |
1142 | #define IS_SEXT_32BIT_NUM(x) \ | |
1143 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1144 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1145 | ||
1146 | /* Is the given value a sign-extended 16-bit value? */ | |
1147 | #define IS_SEXT_16BIT_NUM(x) \ | |
1148 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1149 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1150 | ||
df58fc94 RS |
1151 | /* Is the given value a sign-extended 12-bit value? */ |
1152 | #define IS_SEXT_12BIT_NUM(x) \ | |
1153 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1154 | ||
7f3c4072 CM |
1155 | /* Is the given value a sign-extended 9-bit value? */ |
1156 | #define IS_SEXT_9BIT_NUM(x) \ | |
1157 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1158 | ||
2051e8c4 MR |
1159 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1160 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1161 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1162 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1163 | ||
bf12938e RS |
1164 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1165 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1166 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1167 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1168 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1169 | ||
1170 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1171 | SHIFT places. */ | |
1172 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1173 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1174 | ||
1175 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1176 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1177 | ||
1178 | include/opcode/mips.h specifies operand fields using the macros | |
1179 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1180 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1181 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1182 | do \ | |
1183 | if (!(MICROMIPS)) \ | |
1184 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1185 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1186 | else \ | |
1187 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1188 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1189 | while (0) | |
bf12938e RS |
1190 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1191 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1192 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1193 | ||
1194 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1195 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1196 | (!(MICROMIPS) \ | |
1197 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1198 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1199 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1200 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1201 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1202 | MIPS16OP_MASK_##FIELD, \ | |
1203 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1204 | |
1205 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1206 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1207 | \f |
df58fc94 RS |
1208 | /* Whether or not we are emitting a branch-likely macro. */ |
1209 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1210 | ||
4d7206a2 RS |
1211 | /* Global variables used when generating relaxable macros. See the |
1212 | comment above RELAX_ENCODE for more details about how relaxation | |
1213 | is used. */ | |
1214 | static struct { | |
1215 | /* 0 if we're not emitting a relaxable macro. | |
1216 | 1 if we're emitting the first of the two relaxation alternatives. | |
1217 | 2 if we're emitting the second alternative. */ | |
1218 | int sequence; | |
1219 | ||
1220 | /* The first relaxable fixup in the current frag. (In other words, | |
1221 | the first fixup that refers to relaxable code.) */ | |
1222 | fixS *first_fixup; | |
1223 | ||
1224 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1225 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1226 | unsigned int sizes[2]; | |
1227 | ||
1228 | /* The symbol on which the choice of sequence depends. */ | |
1229 | symbolS *symbol; | |
1230 | } mips_relax; | |
252b5132 | 1231 | \f |
584892a6 RS |
1232 | /* Global variables used to decide whether a macro needs a warning. */ |
1233 | static struct { | |
1234 | /* True if the macro is in a branch delay slot. */ | |
1235 | bfd_boolean delay_slot_p; | |
1236 | ||
df58fc94 RS |
1237 | /* Set to the length in bytes required if the macro is in a delay slot |
1238 | that requires a specific length of instruction, otherwise zero. */ | |
1239 | unsigned int delay_slot_length; | |
1240 | ||
584892a6 RS |
1241 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1242 | in bytes and sizes[1] is the length of the second alternative. | |
1243 | For non-relaxable macros, both elements give the length of the | |
1244 | macro in bytes. */ | |
1245 | unsigned int sizes[2]; | |
1246 | ||
df58fc94 RS |
1247 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1248 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1249 | is the length of the first instruction of the second alternative. | |
1250 | For non-relaxable macros, both elements give the length of the first | |
1251 | instruction in bytes. | |
1252 | ||
1253 | Set to zero if we haven't yet seen the first instruction. */ | |
1254 | unsigned int first_insn_sizes[2]; | |
1255 | ||
1256 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1257 | first alternative and insns[1] is the number of instructions for the | |
1258 | second alternative. | |
1259 | ||
1260 | For non-relaxable macros, both elements give the number of | |
1261 | instructions for the macro. */ | |
1262 | unsigned int insns[2]; | |
1263 | ||
584892a6 RS |
1264 | /* The first variant frag for this macro. */ |
1265 | fragS *first_frag; | |
1266 | } mips_macro_warning; | |
1267 | \f | |
252b5132 RH |
1268 | /* Prototypes for static functions. */ |
1269 | ||
252b5132 RH |
1270 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1271 | ||
b34976b6 | 1272 | static void append_insn |
df58fc94 RS |
1273 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1274 | bfd_boolean expansionp); | |
7d10b47d | 1275 | static void mips_no_prev_insn (void); |
c67a084a | 1276 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1277 | static void mips16_macro_build |
03ea81db | 1278 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1279 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1280 | static void macro_start (void); |
1281 | static void macro_end (void); | |
833794fc | 1282 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1283 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1284 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1285 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1286 | static void mips16_immed |
43c0598f RS |
1287 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1288 | unsigned int, unsigned long *); | |
5e0116d5 | 1289 | static size_t my_getSmallExpression |
17a2f251 TS |
1290 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1291 | static void my_getExpression (expressionS *, char *); | |
1292 | static void s_align (int); | |
1293 | static void s_change_sec (int); | |
1294 | static void s_change_section (int); | |
1295 | static void s_cons (int); | |
1296 | static void s_float_cons (int); | |
1297 | static void s_mips_globl (int); | |
1298 | static void s_option (int); | |
1299 | static void s_mipsset (int); | |
1300 | static void s_abicalls (int); | |
1301 | static void s_cpload (int); | |
1302 | static void s_cpsetup (int); | |
1303 | static void s_cplocal (int); | |
1304 | static void s_cprestore (int); | |
1305 | static void s_cpreturn (int); | |
741d6ea8 JM |
1306 | static void s_dtprelword (int); |
1307 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1308 | static void s_tprelword (int); |
1309 | static void s_tpreldword (int); | |
17a2f251 TS |
1310 | static void s_gpvalue (int); |
1311 | static void s_gpword (int); | |
1312 | static void s_gpdword (int); | |
a3f278e2 | 1313 | static void s_ehword (int); |
17a2f251 TS |
1314 | static void s_cpadd (int); |
1315 | static void s_insn (int); | |
ba92f887 | 1316 | static void s_nan (int); |
17a2f251 TS |
1317 | static void md_obj_begin (void); |
1318 | static void md_obj_end (void); | |
1319 | static void s_mips_ent (int); | |
1320 | static void s_mips_end (int); | |
1321 | static void s_mips_frame (int); | |
1322 | static void s_mips_mask (int reg_type); | |
1323 | static void s_mips_stab (int); | |
1324 | static void s_mips_weakext (int); | |
1325 | static void s_mips_file (int); | |
1326 | static void s_mips_loc (int); | |
1327 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1328 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1329 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1330 | static int validate_micromips_insn (const struct mips_opcode *); |
1331 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1332 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1333 | |
1334 | /* Table and functions used to map between CPU/ISA names, and | |
1335 | ISA levels, and CPU numbers. */ | |
1336 | ||
e972090a NC |
1337 | struct mips_cpu_info |
1338 | { | |
e7af610e | 1339 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1340 | int flags; /* MIPS_CPU_* flags. */ |
1341 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1342 | int isa; /* ISA level. */ |
1343 | int cpu; /* CPU number (default CPU if ISA). */ | |
1344 | }; | |
1345 | ||
ad3fea08 | 1346 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1347 | |
17a2f251 TS |
1348 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1349 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1350 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1351 | \f |
c31f3936 RS |
1352 | /* Command-line options. */ |
1353 | const char *md_shortopts = "O::g::G:"; | |
1354 | ||
1355 | enum options | |
1356 | { | |
1357 | OPTION_MARCH = OPTION_MD_BASE, | |
1358 | OPTION_MTUNE, | |
1359 | OPTION_MIPS1, | |
1360 | OPTION_MIPS2, | |
1361 | OPTION_MIPS3, | |
1362 | OPTION_MIPS4, | |
1363 | OPTION_MIPS5, | |
1364 | OPTION_MIPS32, | |
1365 | OPTION_MIPS64, | |
1366 | OPTION_MIPS32R2, | |
1367 | OPTION_MIPS64R2, | |
1368 | OPTION_MIPS16, | |
1369 | OPTION_NO_MIPS16, | |
1370 | OPTION_MIPS3D, | |
1371 | OPTION_NO_MIPS3D, | |
1372 | OPTION_MDMX, | |
1373 | OPTION_NO_MDMX, | |
1374 | OPTION_DSP, | |
1375 | OPTION_NO_DSP, | |
1376 | OPTION_MT, | |
1377 | OPTION_NO_MT, | |
1378 | OPTION_VIRT, | |
1379 | OPTION_NO_VIRT, | |
1380 | OPTION_SMARTMIPS, | |
1381 | OPTION_NO_SMARTMIPS, | |
1382 | OPTION_DSPR2, | |
1383 | OPTION_NO_DSPR2, | |
1384 | OPTION_EVA, | |
1385 | OPTION_NO_EVA, | |
1386 | OPTION_MICROMIPS, | |
1387 | OPTION_NO_MICROMIPS, | |
1388 | OPTION_MCU, | |
1389 | OPTION_NO_MCU, | |
1390 | OPTION_COMPAT_ARCH_BASE, | |
1391 | OPTION_M4650, | |
1392 | OPTION_NO_M4650, | |
1393 | OPTION_M4010, | |
1394 | OPTION_NO_M4010, | |
1395 | OPTION_M4100, | |
1396 | OPTION_NO_M4100, | |
1397 | OPTION_M3900, | |
1398 | OPTION_NO_M3900, | |
1399 | OPTION_M7000_HILO_FIX, | |
1400 | OPTION_MNO_7000_HILO_FIX, | |
1401 | OPTION_FIX_24K, | |
1402 | OPTION_NO_FIX_24K, | |
1403 | OPTION_FIX_LOONGSON2F_JUMP, | |
1404 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1405 | OPTION_FIX_LOONGSON2F_NOP, | |
1406 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1407 | OPTION_FIX_VR4120, | |
1408 | OPTION_NO_FIX_VR4120, | |
1409 | OPTION_FIX_VR4130, | |
1410 | OPTION_NO_FIX_VR4130, | |
1411 | OPTION_FIX_CN63XXP1, | |
1412 | OPTION_NO_FIX_CN63XXP1, | |
1413 | OPTION_TRAP, | |
1414 | OPTION_BREAK, | |
1415 | OPTION_EB, | |
1416 | OPTION_EL, | |
1417 | OPTION_FP32, | |
1418 | OPTION_GP32, | |
1419 | OPTION_CONSTRUCT_FLOATS, | |
1420 | OPTION_NO_CONSTRUCT_FLOATS, | |
1421 | OPTION_FP64, | |
1422 | OPTION_GP64, | |
1423 | OPTION_RELAX_BRANCH, | |
1424 | OPTION_NO_RELAX_BRANCH, | |
833794fc MR |
1425 | OPTION_INSN32, |
1426 | OPTION_NO_INSN32, | |
c31f3936 RS |
1427 | OPTION_MSHARED, |
1428 | OPTION_MNO_SHARED, | |
1429 | OPTION_MSYM32, | |
1430 | OPTION_MNO_SYM32, | |
1431 | OPTION_SOFT_FLOAT, | |
1432 | OPTION_HARD_FLOAT, | |
1433 | OPTION_SINGLE_FLOAT, | |
1434 | OPTION_DOUBLE_FLOAT, | |
1435 | OPTION_32, | |
c31f3936 RS |
1436 | OPTION_CALL_SHARED, |
1437 | OPTION_CALL_NONPIC, | |
1438 | OPTION_NON_SHARED, | |
1439 | OPTION_XGOT, | |
1440 | OPTION_MABI, | |
1441 | OPTION_N32, | |
1442 | OPTION_64, | |
1443 | OPTION_MDEBUG, | |
1444 | OPTION_NO_MDEBUG, | |
1445 | OPTION_PDR, | |
1446 | OPTION_NO_PDR, | |
1447 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1448 | OPTION_NAN, |
c31f3936 RS |
1449 | OPTION_END_OF_ENUM |
1450 | }; | |
1451 | ||
1452 | struct option md_longopts[] = | |
1453 | { | |
1454 | /* Options which specify architecture. */ | |
1455 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1456 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1457 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1458 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1459 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1460 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1461 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1462 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1463 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1464 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1465 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
1466 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
1467 | ||
1468 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1469 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1470 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1471 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1472 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1473 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1474 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1475 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1476 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1477 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1478 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1479 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1480 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1481 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1482 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
1483 | {"meva", no_argument, NULL, OPTION_EVA}, | |
1484 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1485 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1486 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1487 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1488 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1489 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1490 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
1491 | ||
1492 | /* Old-style architecture options. Don't add more of these. */ | |
1493 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1494 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1495 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1496 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1497 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1498 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1499 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1500 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1501 | ||
1502 | /* Options which enable bug fixes. */ | |
1503 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1504 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1505 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1506 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1507 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1508 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1509 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1510 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1511 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1512 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1513 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1514 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1515 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
1516 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, | |
1517 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1518 | ||
1519 | /* Miscellaneous options. */ | |
1520 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1521 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1522 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1523 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1524 | {"EB", no_argument, NULL, OPTION_EB}, | |
1525 | {"EL", no_argument, NULL, OPTION_EL}, | |
1526 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1527 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1528 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1529 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1530 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
1531 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1532 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1533 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
833794fc MR |
1534 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1535 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1536 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1537 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1538 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1539 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1540 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1541 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1542 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1543 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
1544 | ||
1545 | /* Strictly speaking this next option is ELF specific, | |
1546 | but we allow it for other ports as well in order to | |
1547 | make testing easier. */ | |
1548 | {"32", no_argument, NULL, OPTION_32}, | |
1549 | ||
1550 | /* ELF-specific options. */ | |
c31f3936 RS |
1551 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1552 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1553 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1554 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1555 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1556 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1557 | {"n32", no_argument, NULL, OPTION_N32}, | |
1558 | {"64", no_argument, NULL, OPTION_64}, | |
1559 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1560 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1561 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1562 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1563 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1564 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1565 | |
1566 | {NULL, no_argument, NULL, 0} | |
1567 | }; | |
1568 | size_t md_longopts_size = sizeof (md_longopts); | |
1569 | \f | |
c6278170 RS |
1570 | /* Information about either an Application Specific Extension or an |
1571 | optional architecture feature that, for simplicity, we treat in the | |
1572 | same way as an ASE. */ | |
1573 | struct mips_ase | |
1574 | { | |
1575 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1576 | const char *name; | |
1577 | ||
1578 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1579 | and 64-bit architectures, the flags here refer to the subset that | |
1580 | is available on both. */ | |
1581 | unsigned int flags; | |
1582 | ||
1583 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1584 | architectures but that are not included in FLAGS. */ | |
1585 | unsigned int flags64; | |
1586 | ||
1587 | /* The command-line options that turn the ASE on and off. */ | |
1588 | int option_on; | |
1589 | int option_off; | |
1590 | ||
1591 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1592 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1593 | int mips32_rev; | |
1594 | int mips64_rev; | |
1595 | int micromips32_rev; | |
1596 | int micromips64_rev; | |
1597 | }; | |
1598 | ||
1599 | /* A table of all supported ASEs. */ | |
1600 | static const struct mips_ase mips_ases[] = { | |
1601 | { "dsp", ASE_DSP, ASE_DSP64, | |
1602 | OPTION_DSP, OPTION_NO_DSP, | |
1603 | 2, 2, 2, 2 }, | |
1604 | ||
1605 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1606 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
1607 | 2, 2, 2, 2 }, | |
1608 | ||
1609 | { "eva", ASE_EVA, 0, | |
1610 | OPTION_EVA, OPTION_NO_EVA, | |
1611 | 2, 2, 2, 2 }, | |
1612 | ||
1613 | { "mcu", ASE_MCU, 0, | |
1614 | OPTION_MCU, OPTION_NO_MCU, | |
1615 | 2, 2, 2, 2 }, | |
1616 | ||
1617 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1618 | { "mdmx", ASE_MDMX, 0, | |
1619 | OPTION_MDMX, OPTION_NO_MDMX, | |
1620 | -1, 1, -1, -1 }, | |
1621 | ||
1622 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1623 | { "mips3d", ASE_MIPS3D, 0, | |
1624 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
1625 | 2, 1, -1, -1 }, | |
1626 | ||
1627 | { "mt", ASE_MT, 0, | |
1628 | OPTION_MT, OPTION_NO_MT, | |
1629 | 2, 2, -1, -1 }, | |
1630 | ||
1631 | { "smartmips", ASE_SMARTMIPS, 0, | |
1632 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
1633 | 1, -1, -1, -1 }, | |
1634 | ||
1635 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1636 | OPTION_VIRT, OPTION_NO_VIRT, | |
1637 | 2, 2, 2, 2 } | |
1638 | }; | |
1639 | ||
1640 | /* The set of ASEs that require -mfp64. */ | |
1641 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX) | |
1642 | ||
1643 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1644 | static const unsigned int mips_ase_groups[] = { | |
1645 | ASE_DSP | ASE_DSPR2 | |
1646 | }; | |
1647 | \f | |
252b5132 RH |
1648 | /* Pseudo-op table. |
1649 | ||
1650 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1651 | should be defined here, but are currently unsupported: .alias, | |
1652 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1653 | ||
1654 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1655 | specific to the type of debugging information being generated, and | |
1656 | should be defined by the object format: .aent, .begin, .bend, | |
1657 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1658 | .vreg. | |
1659 | ||
1660 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1661 | not MIPS CPU specific, but are also not specific to the object file | |
1662 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1663 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1664 | |
e972090a NC |
1665 | static const pseudo_typeS mips_pseudo_table[] = |
1666 | { | |
beae10d5 | 1667 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1668 | {"option", s_option, 0}, |
1669 | {"set", s_mipsset, 0}, | |
1670 | {"rdata", s_change_sec, 'r'}, | |
1671 | {"sdata", s_change_sec, 's'}, | |
1672 | {"livereg", s_ignore, 0}, | |
1673 | {"abicalls", s_abicalls, 0}, | |
1674 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1675 | {"cpsetup", s_cpsetup, 0}, |
1676 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1677 | {"cprestore", s_cprestore, 0}, |
6478892d | 1678 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1679 | {"dtprelword", s_dtprelword, 0}, |
1680 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1681 | {"tprelword", s_tprelword, 0}, |
1682 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1683 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1684 | {"gpword", s_gpword, 0}, |
10181a0d | 1685 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1686 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1687 | {"cpadd", s_cpadd, 0}, |
1688 | {"insn", s_insn, 0}, | |
ba92f887 | 1689 | {"nan", s_nan, 0}, |
252b5132 | 1690 | |
beae10d5 | 1691 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1692 | chips. */ |
38a57ae7 | 1693 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1694 | {"bss", s_change_sec, 'b'}, |
1695 | {"err", s_err, 0}, | |
1696 | {"half", s_cons, 1}, | |
1697 | {"dword", s_cons, 3}, | |
1698 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1699 | {"origin", s_org, 0}, |
1700 | {"repeat", s_rept, 0}, | |
252b5132 | 1701 | |
998b3c36 MR |
1702 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1703 | {"sbss", s_change_sec, 'B'}, | |
1704 | ||
beae10d5 | 1705 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1706 | here for one reason or another. */ |
1707 | {"align", s_align, 0}, | |
1708 | {"byte", s_cons, 0}, | |
1709 | {"data", s_change_sec, 'd'}, | |
1710 | {"double", s_float_cons, 'd'}, | |
1711 | {"float", s_float_cons, 'f'}, | |
1712 | {"globl", s_mips_globl, 0}, | |
1713 | {"global", s_mips_globl, 0}, | |
1714 | {"hword", s_cons, 1}, | |
1715 | {"int", s_cons, 2}, | |
1716 | {"long", s_cons, 2}, | |
1717 | {"octa", s_cons, 4}, | |
1718 | {"quad", s_cons, 3}, | |
cca86cc8 | 1719 | {"section", s_change_section, 0}, |
252b5132 RH |
1720 | {"short", s_cons, 1}, |
1721 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1722 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1723 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1724 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1725 | {"text", s_change_sec, 't'}, |
1726 | {"word", s_cons, 2}, | |
add56521 | 1727 | |
add56521 | 1728 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1729 | |
43841e91 | 1730 | { NULL, NULL, 0 }, |
252b5132 RH |
1731 | }; |
1732 | ||
e972090a NC |
1733 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1734 | { | |
beae10d5 KH |
1735 | /* These pseudo-ops should be defined by the object file format. |
1736 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1737 | {"aent", s_mips_ent, 1}, |
1738 | {"bgnb", s_ignore, 0}, | |
1739 | {"end", s_mips_end, 0}, | |
1740 | {"endb", s_ignore, 0}, | |
1741 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1742 | {"file", s_mips_file, 0}, |
252b5132 RH |
1743 | {"fmask", s_mips_mask, 'F'}, |
1744 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1745 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1746 | {"mask", s_mips_mask, 'R'}, |
1747 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1748 | { NULL, NULL, 0 }, |
252b5132 RH |
1749 | }; |
1750 | ||
3ae8dd8d MR |
1751 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1752 | purpose of the `.dc.a' internal pseudo-op. */ | |
1753 | ||
1754 | int | |
1755 | mips_address_bytes (void) | |
1756 | { | |
1757 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1758 | } | |
1759 | ||
17a2f251 | 1760 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1761 | |
1762 | void | |
17a2f251 | 1763 | mips_pop_insert (void) |
252b5132 RH |
1764 | { |
1765 | pop_insert (mips_pseudo_table); | |
1766 | if (! ECOFF_DEBUGGING) | |
1767 | pop_insert (mips_nonecoff_pseudo_table); | |
1768 | } | |
1769 | \f | |
1770 | /* Symbols labelling the current insn. */ | |
1771 | ||
e972090a NC |
1772 | struct insn_label_list |
1773 | { | |
252b5132 RH |
1774 | struct insn_label_list *next; |
1775 | symbolS *label; | |
1776 | }; | |
1777 | ||
252b5132 | 1778 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1779 | #define label_list tc_segment_info_data.labels |
252b5132 | 1780 | |
17a2f251 | 1781 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1782 | static void mips_mark_labels (void); |
1783 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1784 | |
1785 | static inline void | |
17a2f251 | 1786 | mips_clear_insn_labels (void) |
252b5132 RH |
1787 | { |
1788 | register struct insn_label_list **pl; | |
a8dbcb85 | 1789 | segment_info_type *si; |
252b5132 | 1790 | |
a8dbcb85 TS |
1791 | if (now_seg) |
1792 | { | |
1793 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1794 | ; | |
1795 | ||
1796 | si = seg_info (now_seg); | |
1797 | *pl = si->label_list; | |
1798 | si->label_list = NULL; | |
1799 | } | |
252b5132 | 1800 | } |
a8dbcb85 | 1801 | |
df58fc94 RS |
1802 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1803 | ||
1804 | static inline void | |
1805 | mips_mark_labels (void) | |
1806 | { | |
1807 | if (HAVE_CODE_COMPRESSION) | |
1808 | mips_compressed_mark_labels (); | |
1809 | } | |
252b5132 RH |
1810 | \f |
1811 | static char *expr_end; | |
1812 | ||
77bd4346 RS |
1813 | /* Expressions which appear in macro instructions. These are set by |
1814 | mips_ip and read by macro. */ | |
252b5132 RH |
1815 | |
1816 | static expressionS imm_expr; | |
5f74bc13 | 1817 | static expressionS imm2_expr; |
252b5132 | 1818 | |
77bd4346 RS |
1819 | /* The relocatable field in an instruction and the relocs associated |
1820 | with it. These variables are used for instructions like LUI and | |
1821 | JAL as well as true offsets. They are also used for address | |
1822 | operands in macros. */ | |
252b5132 | 1823 | |
77bd4346 | 1824 | static expressionS offset_expr; |
f6688943 TS |
1825 | static bfd_reloc_code_real_type offset_reloc[3] |
1826 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1827 | |
df58fc94 RS |
1828 | /* This is set to the resulting size of the instruction to be produced |
1829 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1830 | explicit size is supplied. */ | |
252b5132 | 1831 | |
df58fc94 | 1832 | static unsigned int forced_insn_length; |
252b5132 | 1833 | |
e1b47bd5 RS |
1834 | /* True if we are assembling an instruction. All dot symbols defined during |
1835 | this time should be treated as code labels. */ | |
1836 | ||
1837 | static bfd_boolean mips_assembling_insn; | |
1838 | ||
ecb4347a DJ |
1839 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1840 | ECOFF debugging. */ | |
252b5132 RH |
1841 | |
1842 | static segT pdr_seg; | |
252b5132 | 1843 | |
e013f690 TS |
1844 | /* The default target format to use. */ |
1845 | ||
aeffff67 RS |
1846 | #if defined (TE_FreeBSD) |
1847 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1848 | #elif defined (TE_TMIPS) | |
1849 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1850 | #else | |
1851 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1852 | #endif | |
1853 | ||
e013f690 | 1854 | const char * |
17a2f251 | 1855 | mips_target_format (void) |
e013f690 TS |
1856 | { |
1857 | switch (OUTPUT_FLAVOR) | |
1858 | { | |
e013f690 | 1859 | case bfd_target_elf_flavour: |
0a44bf69 RS |
1860 | #ifdef TE_VXWORKS |
1861 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1862 | return (target_big_endian | |
1863 | ? "elf32-bigmips-vxworks" | |
1864 | : "elf32-littlemips-vxworks"); | |
1865 | #endif | |
e013f690 | 1866 | return (target_big_endian |
cfe86eaa | 1867 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1868 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1869 | : (HAVE_NEWABI |
aeffff67 RS |
1870 | ? ELF_TARGET ("elf32-n", "big") |
1871 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1872 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1873 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1874 | : (HAVE_NEWABI |
aeffff67 RS |
1875 | ? ELF_TARGET ("elf32-n", "little") |
1876 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1877 | default: |
1878 | abort (); | |
1879 | return NULL; | |
1880 | } | |
1881 | } | |
1882 | ||
c6278170 RS |
1883 | /* Return the ISA revision that is currently in use, or 0 if we are |
1884 | generating code for MIPS V or below. */ | |
1885 | ||
1886 | static int | |
1887 | mips_isa_rev (void) | |
1888 | { | |
1889 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
1890 | return 2; | |
1891 | ||
1892 | /* microMIPS implies revision 2 or above. */ | |
1893 | if (mips_opts.micromips) | |
1894 | return 2; | |
1895 | ||
1896 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
1897 | return 1; | |
1898 | ||
1899 | return 0; | |
1900 | } | |
1901 | ||
1902 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
1903 | ||
1904 | static unsigned int | |
1905 | mips_ase_mask (unsigned int flags) | |
1906 | { | |
1907 | unsigned int i; | |
1908 | ||
1909 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
1910 | if (flags & mips_ase_groups[i]) | |
1911 | flags |= mips_ase_groups[i]; | |
1912 | return flags; | |
1913 | } | |
1914 | ||
1915 | /* Check whether the current ISA supports ASE. Issue a warning if | |
1916 | appropriate. */ | |
1917 | ||
1918 | static void | |
1919 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
1920 | { | |
1921 | const char *base; | |
1922 | int min_rev, size; | |
1923 | static unsigned int warned_isa; | |
1924 | static unsigned int warned_fp32; | |
1925 | ||
1926 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1927 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
1928 | else | |
1929 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
1930 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
1931 | && (warned_isa & ase->flags) != ase->flags) | |
1932 | { | |
1933 | warned_isa |= ase->flags; | |
1934 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
1935 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
1936 | if (min_rev < 0) | |
1937 | as_warn (_("The %d-bit %s architecture does not support the" | |
1938 | " `%s' extension"), size, base, ase->name); | |
1939 | else | |
1940 | as_warn (_("The `%s' extension requires %s%d revision %d or greater"), | |
1941 | ase->name, base, size, min_rev); | |
1942 | } | |
1943 | if ((ase->flags & FP64_ASES) | |
1944 | && mips_opts.fp32 | |
1945 | && (warned_fp32 & ase->flags) != ase->flags) | |
1946 | { | |
1947 | warned_fp32 |= ase->flags; | |
1948 | as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name); | |
1949 | } | |
1950 | } | |
1951 | ||
1952 | /* Check all enabled ASEs to see whether they are supported by the | |
1953 | chosen architecture. */ | |
1954 | ||
1955 | static void | |
1956 | mips_check_isa_supports_ases (void) | |
1957 | { | |
1958 | unsigned int i, mask; | |
1959 | ||
1960 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
1961 | { | |
1962 | mask = mips_ase_mask (mips_ases[i].flags); | |
1963 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
1964 | mips_check_isa_supports_ase (&mips_ases[i]); | |
1965 | } | |
1966 | } | |
1967 | ||
1968 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
1969 | that were affected. */ | |
1970 | ||
1971 | static unsigned int | |
1972 | mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p) | |
1973 | { | |
1974 | unsigned int mask; | |
1975 | ||
1976 | mask = mips_ase_mask (ase->flags); | |
1977 | mips_opts.ase &= ~mask; | |
1978 | if (enabled_p) | |
1979 | mips_opts.ase |= ase->flags; | |
1980 | return mask; | |
1981 | } | |
1982 | ||
1983 | /* Return the ASE called NAME, or null if none. */ | |
1984 | ||
1985 | static const struct mips_ase * | |
1986 | mips_lookup_ase (const char *name) | |
1987 | { | |
1988 | unsigned int i; | |
1989 | ||
1990 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
1991 | if (strcmp (name, mips_ases[i].name) == 0) | |
1992 | return &mips_ases[i]; | |
1993 | return NULL; | |
1994 | } | |
1995 | ||
df58fc94 RS |
1996 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1997 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1998 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1999 | major opcode) will require further modifications to the opcode | |
2000 | table. */ | |
2001 | ||
2002 | static inline unsigned int | |
2003 | micromips_insn_length (const struct mips_opcode *mo) | |
2004 | { | |
2005 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
2006 | } | |
2007 | ||
5c04167a RS |
2008 | /* Return the length of MIPS16 instruction OPCODE. */ |
2009 | ||
2010 | static inline unsigned int | |
2011 | mips16_opcode_length (unsigned long opcode) | |
2012 | { | |
2013 | return (opcode >> 16) == 0 ? 2 : 4; | |
2014 | } | |
2015 | ||
1e915849 RS |
2016 | /* Return the length of instruction INSN. */ |
2017 | ||
2018 | static inline unsigned int | |
2019 | insn_length (const struct mips_cl_insn *insn) | |
2020 | { | |
df58fc94 RS |
2021 | if (mips_opts.micromips) |
2022 | return micromips_insn_length (insn->insn_mo); | |
2023 | else if (mips_opts.mips16) | |
5c04167a | 2024 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2025 | else |
1e915849 | 2026 | return 4; |
1e915849 RS |
2027 | } |
2028 | ||
2029 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2030 | ||
2031 | static void | |
2032 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2033 | { | |
2034 | size_t i; | |
2035 | ||
2036 | insn->insn_mo = mo; | |
1e915849 RS |
2037 | insn->insn_opcode = mo->match; |
2038 | insn->frag = NULL; | |
2039 | insn->where = 0; | |
2040 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2041 | insn->fixp[i] = NULL; | |
2042 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2043 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2044 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2045 | insn->complete_p = 0; |
e407c74b | 2046 | insn->cleared_p = 0; |
1e915849 RS |
2047 | } |
2048 | ||
df58fc94 | 2049 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2050 | |
2051 | static void | |
df58fc94 | 2052 | mips_record_compressed_mode (void) |
742a56fe RS |
2053 | { |
2054 | segment_info_type *si; | |
2055 | ||
2056 | si = seg_info (now_seg); | |
2057 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2058 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2059 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2060 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2061 | } |
2062 | ||
4d68580a RS |
2063 | /* Read a standard MIPS instruction from BUF. */ |
2064 | ||
2065 | static unsigned long | |
2066 | read_insn (char *buf) | |
2067 | { | |
2068 | if (target_big_endian) | |
2069 | return bfd_getb32 ((bfd_byte *) buf); | |
2070 | else | |
2071 | return bfd_getl32 ((bfd_byte *) buf); | |
2072 | } | |
2073 | ||
2074 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2075 | the next byte. */ | |
2076 | ||
2077 | static char * | |
2078 | write_insn (char *buf, unsigned int insn) | |
2079 | { | |
2080 | md_number_to_chars (buf, insn, 4); | |
2081 | return buf + 4; | |
2082 | } | |
2083 | ||
2084 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2085 | has length LENGTH. */ | |
2086 | ||
2087 | static unsigned long | |
2088 | read_compressed_insn (char *buf, unsigned int length) | |
2089 | { | |
2090 | unsigned long insn; | |
2091 | unsigned int i; | |
2092 | ||
2093 | insn = 0; | |
2094 | for (i = 0; i < length; i += 2) | |
2095 | { | |
2096 | insn <<= 16; | |
2097 | if (target_big_endian) | |
2098 | insn |= bfd_getb16 ((char *) buf); | |
2099 | else | |
2100 | insn |= bfd_getl16 ((char *) buf); | |
2101 | buf += 2; | |
2102 | } | |
2103 | return insn; | |
2104 | } | |
2105 | ||
5c04167a RS |
2106 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2107 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2108 | ||
2109 | static char * | |
2110 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2111 | { | |
2112 | unsigned int i; | |
2113 | ||
2114 | for (i = 0; i < length; i += 2) | |
2115 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2116 | return buf + length; | |
2117 | } | |
2118 | ||
1e915849 RS |
2119 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2120 | ||
2121 | static void | |
2122 | install_insn (const struct mips_cl_insn *insn) | |
2123 | { | |
2124 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2125 | if (HAVE_CODE_COMPRESSION) |
2126 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2127 | else |
4d68580a | 2128 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2129 | mips_record_compressed_mode (); |
1e915849 RS |
2130 | } |
2131 | ||
2132 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2133 | and install the opcode in the new location. */ | |
2134 | ||
2135 | static void | |
2136 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2137 | { | |
2138 | size_t i; | |
2139 | ||
2140 | insn->frag = frag; | |
2141 | insn->where = where; | |
2142 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2143 | if (insn->fixp[i] != NULL) | |
2144 | { | |
2145 | insn->fixp[i]->fx_frag = frag; | |
2146 | insn->fixp[i]->fx_where = where; | |
2147 | } | |
2148 | install_insn (insn); | |
2149 | } | |
2150 | ||
2151 | /* Add INSN to the end of the output. */ | |
2152 | ||
2153 | static void | |
2154 | add_fixed_insn (struct mips_cl_insn *insn) | |
2155 | { | |
2156 | char *f = frag_more (insn_length (insn)); | |
2157 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2158 | } | |
2159 | ||
2160 | /* Start a variant frag and move INSN to the start of the variant part, | |
2161 | marking it as fixed. The other arguments are as for frag_var. */ | |
2162 | ||
2163 | static void | |
2164 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2165 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2166 | { | |
2167 | frag_grow (max_chars); | |
2168 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2169 | insn->fixed_p = 1; | |
2170 | frag_var (rs_machine_dependent, max_chars, var, | |
2171 | subtype, symbol, offset, NULL); | |
2172 | } | |
2173 | ||
2174 | /* Insert N copies of INSN into the history buffer, starting at | |
2175 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2176 | ||
2177 | static void | |
2178 | insert_into_history (unsigned int first, unsigned int n, | |
2179 | const struct mips_cl_insn *insn) | |
2180 | { | |
2181 | if (mips_relax.sequence != 2) | |
2182 | { | |
2183 | unsigned int i; | |
2184 | ||
2185 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2186 | if (i >= first + n) | |
2187 | history[i] = history[i - n]; | |
2188 | else | |
2189 | history[i] = *insn; | |
2190 | } | |
2191 | } | |
2192 | ||
71400594 RS |
2193 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2194 | the idea is to make it obvious at a glance that each errata is | |
2195 | included. */ | |
2196 | ||
2197 | static void | |
2198 | init_vr4120_conflicts (void) | |
2199 | { | |
2200 | #define CONFLICT(FIRST, SECOND) \ | |
2201 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2202 | ||
2203 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2204 | CONFLICT (MACC, DIV); | |
2205 | CONFLICT (DMACC, DIV); | |
2206 | ||
2207 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2208 | CONFLICT (DMULT, DMULT); | |
2209 | CONFLICT (DMULT, DMACC); | |
2210 | CONFLICT (DMACC, DMULT); | |
2211 | CONFLICT (DMACC, DMACC); | |
2212 | ||
2213 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2214 | CONFLICT (MACC, MTHILO); | |
2215 | CONFLICT (DMACC, MTHILO); | |
2216 | ||
2217 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2218 | instruction is executed immediately after a MACC or DMACC | |
2219 | instruction, the result of [either instruction] is incorrect." */ | |
2220 | CONFLICT (MACC, MULT); | |
2221 | CONFLICT (MACC, DMULT); | |
2222 | CONFLICT (DMACC, MULT); | |
2223 | CONFLICT (DMACC, DMULT); | |
2224 | ||
2225 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2226 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2227 | DDIV or DDIVU instruction, the result of the MACC or | |
2228 | DMACC instruction is incorrect.". */ | |
2229 | CONFLICT (DMULT, MACC); | |
2230 | CONFLICT (DMULT, DMACC); | |
2231 | CONFLICT (DIV, MACC); | |
2232 | CONFLICT (DIV, DMACC); | |
2233 | ||
2234 | #undef CONFLICT | |
2235 | } | |
2236 | ||
707bfff6 TS |
2237 | struct regname { |
2238 | const char *name; | |
2239 | unsigned int num; | |
2240 | }; | |
2241 | ||
2242 | #define RTYPE_MASK 0x1ff00 | |
2243 | #define RTYPE_NUM 0x00100 | |
2244 | #define RTYPE_FPU 0x00200 | |
2245 | #define RTYPE_FCC 0x00400 | |
2246 | #define RTYPE_VEC 0x00800 | |
2247 | #define RTYPE_GP 0x01000 | |
2248 | #define RTYPE_CP0 0x02000 | |
2249 | #define RTYPE_PC 0x04000 | |
2250 | #define RTYPE_ACC 0x08000 | |
2251 | #define RTYPE_CCC 0x10000 | |
2252 | #define RNUM_MASK 0x000ff | |
2253 | #define RWARN 0x80000 | |
2254 | ||
2255 | #define GENERIC_REGISTER_NUMBERS \ | |
2256 | {"$0", RTYPE_NUM | 0}, \ | |
2257 | {"$1", RTYPE_NUM | 1}, \ | |
2258 | {"$2", RTYPE_NUM | 2}, \ | |
2259 | {"$3", RTYPE_NUM | 3}, \ | |
2260 | {"$4", RTYPE_NUM | 4}, \ | |
2261 | {"$5", RTYPE_NUM | 5}, \ | |
2262 | {"$6", RTYPE_NUM | 6}, \ | |
2263 | {"$7", RTYPE_NUM | 7}, \ | |
2264 | {"$8", RTYPE_NUM | 8}, \ | |
2265 | {"$9", RTYPE_NUM | 9}, \ | |
2266 | {"$10", RTYPE_NUM | 10}, \ | |
2267 | {"$11", RTYPE_NUM | 11}, \ | |
2268 | {"$12", RTYPE_NUM | 12}, \ | |
2269 | {"$13", RTYPE_NUM | 13}, \ | |
2270 | {"$14", RTYPE_NUM | 14}, \ | |
2271 | {"$15", RTYPE_NUM | 15}, \ | |
2272 | {"$16", RTYPE_NUM | 16}, \ | |
2273 | {"$17", RTYPE_NUM | 17}, \ | |
2274 | {"$18", RTYPE_NUM | 18}, \ | |
2275 | {"$19", RTYPE_NUM | 19}, \ | |
2276 | {"$20", RTYPE_NUM | 20}, \ | |
2277 | {"$21", RTYPE_NUM | 21}, \ | |
2278 | {"$22", RTYPE_NUM | 22}, \ | |
2279 | {"$23", RTYPE_NUM | 23}, \ | |
2280 | {"$24", RTYPE_NUM | 24}, \ | |
2281 | {"$25", RTYPE_NUM | 25}, \ | |
2282 | {"$26", RTYPE_NUM | 26}, \ | |
2283 | {"$27", RTYPE_NUM | 27}, \ | |
2284 | {"$28", RTYPE_NUM | 28}, \ | |
2285 | {"$29", RTYPE_NUM | 29}, \ | |
2286 | {"$30", RTYPE_NUM | 30}, \ | |
2287 | {"$31", RTYPE_NUM | 31} | |
2288 | ||
2289 | #define FPU_REGISTER_NAMES \ | |
2290 | {"$f0", RTYPE_FPU | 0}, \ | |
2291 | {"$f1", RTYPE_FPU | 1}, \ | |
2292 | {"$f2", RTYPE_FPU | 2}, \ | |
2293 | {"$f3", RTYPE_FPU | 3}, \ | |
2294 | {"$f4", RTYPE_FPU | 4}, \ | |
2295 | {"$f5", RTYPE_FPU | 5}, \ | |
2296 | {"$f6", RTYPE_FPU | 6}, \ | |
2297 | {"$f7", RTYPE_FPU | 7}, \ | |
2298 | {"$f8", RTYPE_FPU | 8}, \ | |
2299 | {"$f9", RTYPE_FPU | 9}, \ | |
2300 | {"$f10", RTYPE_FPU | 10}, \ | |
2301 | {"$f11", RTYPE_FPU | 11}, \ | |
2302 | {"$f12", RTYPE_FPU | 12}, \ | |
2303 | {"$f13", RTYPE_FPU | 13}, \ | |
2304 | {"$f14", RTYPE_FPU | 14}, \ | |
2305 | {"$f15", RTYPE_FPU | 15}, \ | |
2306 | {"$f16", RTYPE_FPU | 16}, \ | |
2307 | {"$f17", RTYPE_FPU | 17}, \ | |
2308 | {"$f18", RTYPE_FPU | 18}, \ | |
2309 | {"$f19", RTYPE_FPU | 19}, \ | |
2310 | {"$f20", RTYPE_FPU | 20}, \ | |
2311 | {"$f21", RTYPE_FPU | 21}, \ | |
2312 | {"$f22", RTYPE_FPU | 22}, \ | |
2313 | {"$f23", RTYPE_FPU | 23}, \ | |
2314 | {"$f24", RTYPE_FPU | 24}, \ | |
2315 | {"$f25", RTYPE_FPU | 25}, \ | |
2316 | {"$f26", RTYPE_FPU | 26}, \ | |
2317 | {"$f27", RTYPE_FPU | 27}, \ | |
2318 | {"$f28", RTYPE_FPU | 28}, \ | |
2319 | {"$f29", RTYPE_FPU | 29}, \ | |
2320 | {"$f30", RTYPE_FPU | 30}, \ | |
2321 | {"$f31", RTYPE_FPU | 31} | |
2322 | ||
2323 | #define FPU_CONDITION_CODE_NAMES \ | |
2324 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2325 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2326 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2327 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2328 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2329 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2330 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2331 | {"$fcc7", RTYPE_FCC | 7} | |
2332 | ||
2333 | #define COPROC_CONDITION_CODE_NAMES \ | |
2334 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2335 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2336 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2337 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2338 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2339 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2340 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2341 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2342 | ||
2343 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2344 | {"$a4", RTYPE_GP | 8}, \ | |
2345 | {"$a5", RTYPE_GP | 9}, \ | |
2346 | {"$a6", RTYPE_GP | 10}, \ | |
2347 | {"$a7", RTYPE_GP | 11}, \ | |
2348 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2349 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2350 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2351 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2352 | {"$t0", RTYPE_GP | 12}, \ | |
2353 | {"$t1", RTYPE_GP | 13}, \ | |
2354 | {"$t2", RTYPE_GP | 14}, \ | |
2355 | {"$t3", RTYPE_GP | 15} | |
2356 | ||
2357 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2358 | {"$t0", RTYPE_GP | 8}, \ | |
2359 | {"$t1", RTYPE_GP | 9}, \ | |
2360 | {"$t2", RTYPE_GP | 10}, \ | |
2361 | {"$t3", RTYPE_GP | 11}, \ | |
2362 | {"$t4", RTYPE_GP | 12}, \ | |
2363 | {"$t5", RTYPE_GP | 13}, \ | |
2364 | {"$t6", RTYPE_GP | 14}, \ | |
2365 | {"$t7", RTYPE_GP | 15}, \ | |
2366 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2367 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2368 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2369 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2370 | ||
2371 | /* Remaining symbolic register names */ | |
2372 | #define SYMBOLIC_REGISTER_NAMES \ | |
2373 | {"$zero", RTYPE_GP | 0}, \ | |
2374 | {"$at", RTYPE_GP | 1}, \ | |
2375 | {"$AT", RTYPE_GP | 1}, \ | |
2376 | {"$v0", RTYPE_GP | 2}, \ | |
2377 | {"$v1", RTYPE_GP | 3}, \ | |
2378 | {"$a0", RTYPE_GP | 4}, \ | |
2379 | {"$a1", RTYPE_GP | 5}, \ | |
2380 | {"$a2", RTYPE_GP | 6}, \ | |
2381 | {"$a3", RTYPE_GP | 7}, \ | |
2382 | {"$s0", RTYPE_GP | 16}, \ | |
2383 | {"$s1", RTYPE_GP | 17}, \ | |
2384 | {"$s2", RTYPE_GP | 18}, \ | |
2385 | {"$s3", RTYPE_GP | 19}, \ | |
2386 | {"$s4", RTYPE_GP | 20}, \ | |
2387 | {"$s5", RTYPE_GP | 21}, \ | |
2388 | {"$s6", RTYPE_GP | 22}, \ | |
2389 | {"$s7", RTYPE_GP | 23}, \ | |
2390 | {"$t8", RTYPE_GP | 24}, \ | |
2391 | {"$t9", RTYPE_GP | 25}, \ | |
2392 | {"$k0", RTYPE_GP | 26}, \ | |
2393 | {"$kt0", RTYPE_GP | 26}, \ | |
2394 | {"$k1", RTYPE_GP | 27}, \ | |
2395 | {"$kt1", RTYPE_GP | 27}, \ | |
2396 | {"$gp", RTYPE_GP | 28}, \ | |
2397 | {"$sp", RTYPE_GP | 29}, \ | |
2398 | {"$s8", RTYPE_GP | 30}, \ | |
2399 | {"$fp", RTYPE_GP | 30}, \ | |
2400 | {"$ra", RTYPE_GP | 31} | |
2401 | ||
2402 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2403 | {"$pc", RTYPE_PC | 0} | |
2404 | ||
2405 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2406 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2407 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2408 | {"$v2", RTYPE_VEC | 2}, \ | |
2409 | {"$v3", RTYPE_VEC | 3}, \ | |
2410 | {"$v4", RTYPE_VEC | 4}, \ | |
2411 | {"$v5", RTYPE_VEC | 5}, \ | |
2412 | {"$v6", RTYPE_VEC | 6}, \ | |
2413 | {"$v7", RTYPE_VEC | 7}, \ | |
2414 | {"$v8", RTYPE_VEC | 8}, \ | |
2415 | {"$v9", RTYPE_VEC | 9}, \ | |
2416 | {"$v10", RTYPE_VEC | 10}, \ | |
2417 | {"$v11", RTYPE_VEC | 11}, \ | |
2418 | {"$v12", RTYPE_VEC | 12}, \ | |
2419 | {"$v13", RTYPE_VEC | 13}, \ | |
2420 | {"$v14", RTYPE_VEC | 14}, \ | |
2421 | {"$v15", RTYPE_VEC | 15}, \ | |
2422 | {"$v16", RTYPE_VEC | 16}, \ | |
2423 | {"$v17", RTYPE_VEC | 17}, \ | |
2424 | {"$v18", RTYPE_VEC | 18}, \ | |
2425 | {"$v19", RTYPE_VEC | 19}, \ | |
2426 | {"$v20", RTYPE_VEC | 20}, \ | |
2427 | {"$v21", RTYPE_VEC | 21}, \ | |
2428 | {"$v22", RTYPE_VEC | 22}, \ | |
2429 | {"$v23", RTYPE_VEC | 23}, \ | |
2430 | {"$v24", RTYPE_VEC | 24}, \ | |
2431 | {"$v25", RTYPE_VEC | 25}, \ | |
2432 | {"$v26", RTYPE_VEC | 26}, \ | |
2433 | {"$v27", RTYPE_VEC | 27}, \ | |
2434 | {"$v28", RTYPE_VEC | 28}, \ | |
2435 | {"$v29", RTYPE_VEC | 29}, \ | |
2436 | {"$v30", RTYPE_VEC | 30}, \ | |
2437 | {"$v31", RTYPE_VEC | 31} | |
2438 | ||
2439 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2440 | {"$ac0", RTYPE_ACC | 0}, \ | |
2441 | {"$ac1", RTYPE_ACC | 1}, \ | |
2442 | {"$ac2", RTYPE_ACC | 2}, \ | |
2443 | {"$ac3", RTYPE_ACC | 3} | |
2444 | ||
2445 | static const struct regname reg_names[] = { | |
2446 | GENERIC_REGISTER_NUMBERS, | |
2447 | FPU_REGISTER_NAMES, | |
2448 | FPU_CONDITION_CODE_NAMES, | |
2449 | COPROC_CONDITION_CODE_NAMES, | |
2450 | ||
2451 | /* The $txx registers depends on the abi, | |
2452 | these will be added later into the symbol table from | |
2453 | one of the tables below once mips_abi is set after | |
2454 | parsing of arguments from the command line. */ | |
2455 | SYMBOLIC_REGISTER_NAMES, | |
2456 | ||
2457 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2458 | MDMX_VECTOR_REGISTER_NAMES, | |
2459 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2460 | {0, 0} | |
2461 | }; | |
2462 | ||
2463 | static const struct regname reg_names_o32[] = { | |
2464 | O32_SYMBOLIC_REGISTER_NAMES, | |
2465 | {0, 0} | |
2466 | }; | |
2467 | ||
2468 | static const struct regname reg_names_n32n64[] = { | |
2469 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2470 | {0, 0} | |
2471 | }; | |
2472 | ||
df58fc94 RS |
2473 | /* Check if S points at a valid register specifier according to TYPES. |
2474 | If so, then return 1, advance S to consume the specifier and store | |
2475 | the register's number in REGNOP, otherwise return 0. */ | |
2476 | ||
707bfff6 TS |
2477 | static int |
2478 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2479 | { | |
2480 | symbolS *symbolP; | |
2481 | char *e; | |
2482 | char save_c; | |
2483 | int reg = -1; | |
2484 | ||
2485 | /* Find end of name. */ | |
2486 | e = *s; | |
2487 | if (is_name_beginner (*e)) | |
2488 | ++e; | |
2489 | while (is_part_of_name (*e)) | |
2490 | ++e; | |
2491 | ||
2492 | /* Terminate name. */ | |
2493 | save_c = *e; | |
2494 | *e = '\0'; | |
2495 | ||
2496 | /* Look for a register symbol. */ | |
2497 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2498 | { | |
2499 | int r = S_GET_VALUE (symbolP); | |
2500 | if (r & types) | |
2501 | reg = r & RNUM_MASK; | |
2502 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2503 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2504 | reg = (r & RNUM_MASK) - 2; | |
2505 | } | |
2506 | /* Else see if this is a register defined in an itbl entry. */ | |
2507 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2508 | { | |
2509 | char *n = *s; | |
2510 | unsigned long r; | |
2511 | ||
2512 | if (*n == '$') | |
2513 | ++n; | |
2514 | if (itbl_get_reg_val (n, &r)) | |
2515 | reg = r & RNUM_MASK; | |
2516 | } | |
2517 | ||
2518 | /* Advance to next token if a register was recognised. */ | |
2519 | if (reg >= 0) | |
2520 | *s = e; | |
2521 | else if (types & RWARN) | |
20203fb9 | 2522 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2523 | |
2524 | *e = save_c; | |
2525 | if (regnop) | |
2526 | *regnop = reg; | |
2527 | return reg >= 0; | |
2528 | } | |
2529 | ||
df58fc94 RS |
2530 | /* Check if S points at a valid register list according to TYPES. |
2531 | If so, then return 1, advance S to consume the list and store | |
2532 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2533 | otherwise return 0. A valid list comprises a comma-separated | |
2534 | enumeration of valid single registers and/or dash-separated | |
2535 | contiguous register ranges as determined by their numbers. | |
2536 | ||
2537 | As a special exception if one of s0-s7 registers is specified as | |
2538 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2539 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2540 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2541 | |
2542 | static int | |
2543 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2544 | { | |
2545 | unsigned int reglist = 0; | |
2546 | unsigned int lastregno; | |
2547 | bfd_boolean ok = TRUE; | |
2548 | unsigned int regmask; | |
2309ddf2 | 2549 | char *s_endlist = *s; |
df58fc94 | 2550 | char *s_reset = *s; |
2309ddf2 | 2551 | unsigned int regno; |
df58fc94 RS |
2552 | |
2553 | while (reg_lookup (s, types, ®no)) | |
2554 | { | |
2555 | lastregno = regno; | |
2556 | if (**s == '-') | |
2557 | { | |
2558 | (*s)++; | |
2559 | ok = reg_lookup (s, types, &lastregno); | |
2560 | if (ok && lastregno < regno) | |
2561 | ok = FALSE; | |
2562 | if (!ok) | |
2563 | break; | |
2564 | } | |
2565 | ||
2566 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2567 | { | |
2568 | lastregno = S7; | |
2569 | reglist |= 1 << FP; | |
2570 | } | |
2571 | regmask = 1 << lastregno; | |
2572 | regmask = (regmask << 1) - 1; | |
2573 | regmask ^= (1 << regno) - 1; | |
2574 | reglist |= regmask; | |
2575 | ||
2309ddf2 | 2576 | s_endlist = *s; |
df58fc94 RS |
2577 | if (**s != ',') |
2578 | break; | |
2579 | (*s)++; | |
2580 | } | |
2581 | ||
2582 | if (ok) | |
2309ddf2 | 2583 | *s = s_endlist; |
df58fc94 RS |
2584 | else |
2585 | *s = s_reset; | |
2586 | if (reglistp) | |
2587 | *reglistp = reglist; | |
2588 | return ok && reglist != 0; | |
2589 | } | |
2590 | ||
e76ff5ab RS |
2591 | static unsigned int |
2592 | mips_lookup_reg_pair (unsigned int regno1, unsigned int regno2, | |
2593 | const unsigned int *map1, const unsigned int *map2, | |
2594 | unsigned int count) | |
2595 | { | |
2596 | unsigned int i; | |
2597 | ||
2598 | for (i = 0; i < count; i++) | |
2599 | if (map1[i] == regno1 && map2[i] == regno2) | |
2600 | return i; | |
2601 | return ILLEGAL_REG; | |
2602 | } | |
2603 | ||
d301a56b RS |
2604 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
2605 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
2606 | |
2607 | static bfd_boolean | |
f79e2745 | 2608 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2609 | { |
2610 | int isa = mips_opts.isa; | |
846ef2d0 | 2611 | int ase = mips_opts.ase; |
037b32b9 | 2612 | int fp_s, fp_d; |
c6278170 | 2613 | unsigned int i; |
037b32b9 | 2614 | |
c6278170 RS |
2615 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
2616 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2617 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
2618 | ase |= mips_ases[i].flags64; | |
037b32b9 | 2619 | |
d301a56b | 2620 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
2621 | return FALSE; |
2622 | ||
2623 | /* Check whether the instruction or macro requires single-precision or | |
2624 | double-precision floating-point support. Note that this information is | |
2625 | stored differently in the opcode table for insns and macros. */ | |
2626 | if (mo->pinfo == INSN_MACRO) | |
2627 | { | |
2628 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2629 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2630 | } | |
2631 | else | |
2632 | { | |
2633 | fp_s = mo->pinfo & FP_S; | |
2634 | fp_d = mo->pinfo & FP_D; | |
2635 | } | |
2636 | ||
2637 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2638 | return FALSE; | |
2639 | ||
2640 | if (fp_s && mips_opts.soft_float) | |
2641 | return FALSE; | |
2642 | ||
2643 | return TRUE; | |
2644 | } | |
2645 | ||
2646 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2647 | selected ISA and architecture. */ | |
2648 | ||
2649 | static bfd_boolean | |
2650 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2651 | { | |
d301a56b | 2652 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
2653 | } |
2654 | ||
df58fc94 RS |
2655 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2656 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2657 | ||
2658 | static bfd_boolean | |
2659 | is_size_valid (const struct mips_opcode *mo) | |
2660 | { | |
2661 | if (!mips_opts.micromips) | |
2662 | return TRUE; | |
2663 | ||
833794fc MR |
2664 | if (mips_opts.insn32) |
2665 | { | |
2666 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
2667 | return FALSE; | |
2668 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
2669 | return FALSE; | |
2670 | } | |
df58fc94 RS |
2671 | if (!forced_insn_length) |
2672 | return TRUE; | |
2673 | if (mo->pinfo == INSN_MACRO) | |
2674 | return FALSE; | |
2675 | return forced_insn_length == micromips_insn_length (mo); | |
2676 | } | |
2677 | ||
2678 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2679 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2680 | ||
2681 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2682 | a macro expansion fails because it relies on a preceding 32-bit real | |
2683 | instruction to have matched and does not handle the operands correctly. | |
2684 | The only macros that may expand to 16-bit instructions are JAL that | |
2685 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2686 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2687 | a NOP. In all these cases the macros precede any corresponding real | |
2688 | instruction definitions in the opcode table, so they will match in the | |
2689 | second pass where the size of the delay slot is ignored and therefore | |
2690 | produce correct code. */ | |
df58fc94 RS |
2691 | |
2692 | static bfd_boolean | |
2693 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2694 | { | |
2695 | if (!mips_opts.micromips) | |
2696 | return TRUE; | |
2697 | ||
2698 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2699 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2700 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2701 | && micromips_insn_length (mo) != 4) | |
2702 | return FALSE; | |
2703 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2704 | && micromips_insn_length (mo) != 2) | |
2705 | return FALSE; | |
2706 | ||
2707 | return TRUE; | |
2708 | } | |
2709 | ||
707bfff6 TS |
2710 | /* This function is called once, at assembler startup time. It should set up |
2711 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2712 | |
252b5132 | 2713 | void |
17a2f251 | 2714 | md_begin (void) |
252b5132 | 2715 | { |
3994f87e | 2716 | const char *retval = NULL; |
156c2f8b | 2717 | int i = 0; |
252b5132 | 2718 | int broken = 0; |
1f25f5d3 | 2719 | |
0a44bf69 RS |
2720 | if (mips_pic != NO_PIC) |
2721 | { | |
2722 | if (g_switch_seen && g_switch_value != 0) | |
2723 | as_bad (_("-G may not be used in position-independent code")); | |
2724 | g_switch_value = 0; | |
2725 | } | |
2726 | ||
fef14a42 | 2727 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2728 | as_warn (_("Could not set architecture and machine")); |
2729 | ||
252b5132 RH |
2730 | op_hash = hash_new (); |
2731 | ||
2732 | for (i = 0; i < NUMOPCODES;) | |
2733 | { | |
2734 | const char *name = mips_opcodes[i].name; | |
2735 | ||
17a2f251 | 2736 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2737 | if (retval != NULL) |
2738 | { | |
2739 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2740 | mips_opcodes[i].name, retval); | |
2741 | /* Probably a memory allocation problem? Give up now. */ | |
2742 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2743 | } | |
2744 | do | |
2745 | { | |
2746 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2747 | { | |
2748 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2749 | broken = 1; | |
1e915849 RS |
2750 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2751 | { | |
2752 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2753 | if (mips_fix_loongson2f_nop) |
2754 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2755 | nop_insn.fixed_p = 1; |
2756 | } | |
252b5132 RH |
2757 | } |
2758 | ++i; | |
2759 | } | |
2760 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2761 | } | |
2762 | ||
2763 | mips16_op_hash = hash_new (); | |
2764 | ||
2765 | i = 0; | |
2766 | while (i < bfd_mips16_num_opcodes) | |
2767 | { | |
2768 | const char *name = mips16_opcodes[i].name; | |
2769 | ||
17a2f251 | 2770 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2771 | if (retval != NULL) |
2772 | as_fatal (_("internal: can't hash `%s': %s"), | |
2773 | mips16_opcodes[i].name, retval); | |
2774 | do | |
2775 | { | |
2776 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2777 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2778 | != mips16_opcodes[i].match)) | |
2779 | { | |
2780 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2781 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2782 | broken = 1; | |
2783 | } | |
1e915849 RS |
2784 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2785 | { | |
2786 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2787 | mips16_nop_insn.fixed_p = 1; | |
2788 | } | |
252b5132 RH |
2789 | ++i; |
2790 | } | |
2791 | while (i < bfd_mips16_num_opcodes | |
2792 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2793 | } | |
2794 | ||
df58fc94 RS |
2795 | micromips_op_hash = hash_new (); |
2796 | ||
2797 | i = 0; | |
2798 | while (i < bfd_micromips_num_opcodes) | |
2799 | { | |
2800 | const char *name = micromips_opcodes[i].name; | |
2801 | ||
2802 | retval = hash_insert (micromips_op_hash, name, | |
2803 | (void *) µmips_opcodes[i]); | |
2804 | if (retval != NULL) | |
2805 | as_fatal (_("internal: can't hash `%s': %s"), | |
2806 | micromips_opcodes[i].name, retval); | |
2807 | do | |
2808 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2809 | { | |
2810 | struct mips_cl_insn *micromips_nop_insn; | |
2811 | ||
2812 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2813 | broken = 1; | |
2814 | ||
2815 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2816 | micromips_nop_insn = µmips_nop16_insn; | |
2817 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2818 | micromips_nop_insn = µmips_nop32_insn; | |
2819 | else | |
2820 | continue; | |
2821 | ||
2822 | if (micromips_nop_insn->insn_mo == NULL | |
2823 | && strcmp (name, "nop") == 0) | |
2824 | { | |
2825 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2826 | micromips_nop_insn->fixed_p = 1; | |
2827 | } | |
2828 | } | |
2829 | while (++i < bfd_micromips_num_opcodes | |
2830 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2831 | } | |
2832 | ||
252b5132 RH |
2833 | if (broken) |
2834 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2835 | ||
2836 | /* We add all the general register names to the symbol table. This | |
2837 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2838 | for (i = 0; reg_names[i].name; i++) |
2839 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2840 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2841 | &zero_address_frag)); |
2842 | if (HAVE_NEWABI) | |
2843 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2844 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2845 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2846 | &zero_address_frag)); |
707bfff6 TS |
2847 | else |
2848 | for (i = 0; reg_names_o32[i].name; i++) | |
2849 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2850 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2851 | &zero_address_frag)); |
6047c971 | 2852 | |
7d10b47d | 2853 | mips_no_prev_insn (); |
252b5132 RH |
2854 | |
2855 | mips_gprmask = 0; | |
2856 | mips_cprmask[0] = 0; | |
2857 | mips_cprmask[1] = 0; | |
2858 | mips_cprmask[2] = 0; | |
2859 | mips_cprmask[3] = 0; | |
2860 | ||
2861 | /* set the default alignment for the text section (2**2) */ | |
2862 | record_alignment (text_section, 2); | |
2863 | ||
4d0d148d | 2864 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2865 | |
f3ded42a RS |
2866 | /* On a native system other than VxWorks, sections must be aligned |
2867 | to 16 byte boundaries. When configured for an embedded ELF | |
2868 | target, we don't bother. */ | |
2869 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
2870 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 2871 | { |
f3ded42a RS |
2872 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
2873 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2874 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2875 | } | |
252b5132 | 2876 | |
f3ded42a RS |
2877 | /* Create a .reginfo section for register masks and a .mdebug |
2878 | section for debugging information. */ | |
2879 | { | |
2880 | segT seg; | |
2881 | subsegT subseg; | |
2882 | flagword flags; | |
2883 | segT sec; | |
2884 | ||
2885 | seg = now_seg; | |
2886 | subseg = now_subseg; | |
2887 | ||
2888 | /* The ABI says this section should be loaded so that the | |
2889 | running program can access it. However, we don't load it | |
2890 | if we are configured for an embedded target */ | |
2891 | flags = SEC_READONLY | SEC_DATA; | |
2892 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
2893 | flags |= SEC_ALLOC | SEC_LOAD; | |
2894 | ||
2895 | if (mips_abi != N64_ABI) | |
252b5132 | 2896 | { |
f3ded42a | 2897 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 2898 | |
f3ded42a RS |
2899 | bfd_set_section_flags (stdoutput, sec, flags); |
2900 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 2901 | |
f3ded42a RS |
2902 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
2903 | } | |
2904 | else | |
2905 | { | |
2906 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2907 | .reginfo section. */ | |
2908 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
2909 | bfd_set_section_flags (stdoutput, sec, flags); | |
2910 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2911 | |
f3ded42a RS |
2912 | /* Set up the option header. */ |
2913 | { | |
2914 | Elf_Internal_Options opthdr; | |
2915 | char *f; | |
2916 | ||
2917 | opthdr.kind = ODK_REGINFO; | |
2918 | opthdr.size = (sizeof (Elf_External_Options) | |
2919 | + sizeof (Elf64_External_RegInfo)); | |
2920 | opthdr.section = 0; | |
2921 | opthdr.info = 0; | |
2922 | f = frag_more (sizeof (Elf_External_Options)); | |
2923 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2924 | (Elf_External_Options *) f); | |
2925 | ||
2926 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2927 | } | |
2928 | } | |
252b5132 | 2929 | |
f3ded42a RS |
2930 | if (ECOFF_DEBUGGING) |
2931 | { | |
2932 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2933 | (void) bfd_set_section_flags (stdoutput, sec, | |
2934 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2935 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 2936 | } |
f3ded42a RS |
2937 | else if (mips_flag_pdr) |
2938 | { | |
2939 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2940 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2941 | SEC_READONLY | SEC_RELOC | |
2942 | | SEC_DEBUGGING); | |
2943 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2944 | } | |
2945 | ||
2946 | subseg_set (seg, subseg); | |
2947 | } | |
252b5132 RH |
2948 | |
2949 | if (! ECOFF_DEBUGGING) | |
2950 | md_obj_begin (); | |
71400594 RS |
2951 | |
2952 | if (mips_fix_vr4120) | |
2953 | init_vr4120_conflicts (); | |
252b5132 RH |
2954 | } |
2955 | ||
2956 | void | |
17a2f251 | 2957 | md_mips_end (void) |
252b5132 | 2958 | { |
02b1ab82 | 2959 | mips_emit_delays (); |
252b5132 RH |
2960 | if (! ECOFF_DEBUGGING) |
2961 | md_obj_end (); | |
2962 | } | |
2963 | ||
2964 | void | |
17a2f251 | 2965 | md_assemble (char *str) |
252b5132 RH |
2966 | { |
2967 | struct mips_cl_insn insn; | |
f6688943 TS |
2968 | bfd_reloc_code_real_type unused_reloc[3] |
2969 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2970 | |
2971 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2972 | imm2_expr.X_op = O_absent; |
252b5132 | 2973 | offset_expr.X_op = O_absent; |
f6688943 TS |
2974 | offset_reloc[0] = BFD_RELOC_UNUSED; |
2975 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2976 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2977 | |
e1b47bd5 RS |
2978 | mips_mark_labels (); |
2979 | mips_assembling_insn = TRUE; | |
2980 | ||
252b5132 RH |
2981 | if (mips_opts.mips16) |
2982 | mips16_ip (str, &insn); | |
2983 | else | |
2984 | { | |
2985 | mips_ip (str, &insn); | |
beae10d5 KH |
2986 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2987 | str, insn.insn_opcode)); | |
252b5132 RH |
2988 | } |
2989 | ||
2990 | if (insn_error) | |
e1b47bd5 RS |
2991 | as_bad ("%s `%s'", insn_error, str); |
2992 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2993 | { |
584892a6 | 2994 | macro_start (); |
252b5132 RH |
2995 | if (mips_opts.mips16) |
2996 | mips16_macro (&insn); | |
2997 | else | |
833794fc | 2998 | macro (&insn, str); |
584892a6 | 2999 | macro_end (); |
252b5132 RH |
3000 | } |
3001 | else | |
3002 | { | |
77bd4346 | 3003 | if (offset_expr.X_op != O_absent) |
df58fc94 | 3004 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 3005 | else |
df58fc94 | 3006 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 3007 | } |
e1b47bd5 RS |
3008 | |
3009 | mips_assembling_insn = FALSE; | |
252b5132 RH |
3010 | } |
3011 | ||
738e5348 RS |
3012 | /* Convenience functions for abstracting away the differences between |
3013 | MIPS16 and non-MIPS16 relocations. */ | |
3014 | ||
3015 | static inline bfd_boolean | |
3016 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
3017 | { | |
3018 | switch (reloc) | |
3019 | { | |
3020 | case BFD_RELOC_MIPS16_JMP: | |
3021 | case BFD_RELOC_MIPS16_GPREL: | |
3022 | case BFD_RELOC_MIPS16_GOT16: | |
3023 | case BFD_RELOC_MIPS16_CALL16: | |
3024 | case BFD_RELOC_MIPS16_HI16_S: | |
3025 | case BFD_RELOC_MIPS16_HI16: | |
3026 | case BFD_RELOC_MIPS16_LO16: | |
3027 | return TRUE; | |
3028 | ||
3029 | default: | |
3030 | return FALSE; | |
3031 | } | |
3032 | } | |
3033 | ||
df58fc94 RS |
3034 | static inline bfd_boolean |
3035 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
3036 | { | |
3037 | switch (reloc) | |
3038 | { | |
3039 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3040 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3041 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3042 | case BFD_RELOC_MICROMIPS_GPREL16: | |
3043 | case BFD_RELOC_MICROMIPS_JMP: | |
3044 | case BFD_RELOC_MICROMIPS_HI16: | |
3045 | case BFD_RELOC_MICROMIPS_HI16_S: | |
3046 | case BFD_RELOC_MICROMIPS_LO16: | |
3047 | case BFD_RELOC_MICROMIPS_LITERAL: | |
3048 | case BFD_RELOC_MICROMIPS_GOT16: | |
3049 | case BFD_RELOC_MICROMIPS_CALL16: | |
3050 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
3051 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
3052 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
3053 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
3054 | case BFD_RELOC_MICROMIPS_SUB: | |
3055 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
3056 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
3057 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
3058 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
3059 | case BFD_RELOC_MICROMIPS_HIGHER: | |
3060 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
3061 | case BFD_RELOC_MICROMIPS_JALR: | |
3062 | return TRUE; | |
3063 | ||
3064 | default: | |
3065 | return FALSE; | |
3066 | } | |
3067 | } | |
3068 | ||
2309ddf2 MR |
3069 | static inline bfd_boolean |
3070 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
3071 | { | |
3072 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
3073 | } | |
3074 | ||
738e5348 RS |
3075 | static inline bfd_boolean |
3076 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
3077 | { | |
2309ddf2 | 3078 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 3079 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
3080 | } |
3081 | ||
3082 | static inline bfd_boolean | |
3083 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
3084 | { | |
2309ddf2 | 3085 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 3086 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
3087 | } |
3088 | ||
3089 | static inline bfd_boolean | |
3090 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
3091 | { | |
2309ddf2 | 3092 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
3093 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
3094 | } | |
3095 | ||
df58fc94 RS |
3096 | static inline bfd_boolean |
3097 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
3098 | { | |
2309ddf2 | 3099 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
3100 | } |
3101 | ||
f2ae14a1 RS |
3102 | static inline bfd_boolean |
3103 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
3104 | { | |
3105 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
3106 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
3107 | } | |
3108 | ||
2de39019 CM |
3109 | /* Return true if RELOC is a PC-relative relocation that does not have |
3110 | full address range. */ | |
3111 | ||
3112 | static inline bfd_boolean | |
3113 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
3114 | { | |
3115 | switch (reloc) | |
3116 | { | |
3117 | case BFD_RELOC_16_PCREL_S2: | |
3118 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3119 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3120 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3121 | return TRUE; | |
3122 | ||
b47468a6 CM |
3123 | case BFD_RELOC_32_PCREL: |
3124 | return HAVE_64BIT_ADDRESSES; | |
3125 | ||
2de39019 CM |
3126 | default: |
3127 | return FALSE; | |
3128 | } | |
3129 | } | |
b47468a6 | 3130 | |
5919d012 | 3131 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
3132 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
3133 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
3134 | |
3135 | static inline bfd_boolean | |
17a2f251 | 3136 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 3137 | { |
3b91255e | 3138 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 3139 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
3140 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
3141 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
3142 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
3143 | } | |
3144 | ||
3145 | /* Return the type of %lo() reloc needed by RELOC, given that | |
3146 | reloc_needs_lo_p. */ | |
3147 | ||
3148 | static inline bfd_reloc_code_real_type | |
3149 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
3150 | { | |
df58fc94 RS |
3151 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
3152 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
3153 | : BFD_RELOC_LO16)); | |
5919d012 RS |
3154 | } |
3155 | ||
3156 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
3157 | relocation. */ | |
3158 | ||
3159 | static inline bfd_boolean | |
17a2f251 | 3160 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
3161 | { |
3162 | return (fixp->fx_next != NULL | |
738e5348 | 3163 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
3164 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
3165 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
3166 | } | |
3167 | ||
252b5132 RH |
3168 | /* This function returns true if modifying a register requires a |
3169 | delay. */ | |
3170 | ||
3171 | static int | |
17a2f251 | 3172 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
3173 | { |
3174 | unsigned long prev_pinfo; | |
3175 | ||
47e39b9d | 3176 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 3177 | if (! mips_opts.noreorder |
81912461 ILT |
3178 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
3179 | && ! gpr_interlocks) | |
3180 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
3181 | && ! cop_interlocks))) | |
252b5132 | 3182 | { |
81912461 ILT |
3183 | /* A load from a coprocessor or from memory. All load delays |
3184 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 3185 | /* Itbl support may require additional care here. */ |
252b5132 | 3186 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 3187 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
3188 | return 1; |
3189 | } | |
3190 | ||
3191 | return 0; | |
3192 | } | |
3193 | ||
462427c4 RS |
3194 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
3195 | says whether the labels refer to text or data. */ | |
404a8071 RS |
3196 | |
3197 | static void | |
462427c4 | 3198 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
3199 | { |
3200 | struct insn_label_list *l; | |
3201 | valueT val; | |
3202 | ||
462427c4 | 3203 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 3204 | { |
9c2799c2 | 3205 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
3206 | symbol_set_frag (l->label, frag_now); |
3207 | val = (valueT) frag_now_fix (); | |
df58fc94 | 3208 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 3209 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
3210 | ++val; |
3211 | S_SET_VALUE (l->label, val); | |
3212 | } | |
3213 | } | |
3214 | ||
462427c4 RS |
3215 | /* Move all labels in insn_labels to the current insertion point |
3216 | and treat them as text labels. */ | |
3217 | ||
3218 | static void | |
3219 | mips_move_text_labels (void) | |
3220 | { | |
3221 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
3222 | } | |
3223 | ||
5f0fe04b TS |
3224 | static bfd_boolean |
3225 | s_is_linkonce (symbolS *sym, segT from_seg) | |
3226 | { | |
3227 | bfd_boolean linkonce = FALSE; | |
3228 | segT symseg = S_GET_SEGMENT (sym); | |
3229 | ||
3230 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
3231 | { | |
3232 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
3233 | linkonce = TRUE; | |
5f0fe04b TS |
3234 | /* The GNU toolchain uses an extension for ELF: a section |
3235 | beginning with the magic string .gnu.linkonce is a | |
3236 | linkonce section. */ | |
3237 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
3238 | sizeof ".gnu.linkonce" - 1) == 0) | |
3239 | linkonce = TRUE; | |
5f0fe04b TS |
3240 | } |
3241 | return linkonce; | |
3242 | } | |
3243 | ||
e1b47bd5 | 3244 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
3245 | linker to handle them specially, such as generating jalx instructions |
3246 | when needed. We also make them odd for the duration of the assembly, | |
3247 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
3248 | in the adjust_symtab routine, while leaving them marked. This is |
3249 | convenient for the debugger and the disassembler. The linker knows | |
3250 | to make them odd again. */ | |
3251 | ||
3252 | static void | |
e1b47bd5 | 3253 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 3254 | { |
df58fc94 | 3255 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 3256 | |
f3ded42a RS |
3257 | if (mips_opts.mips16) |
3258 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
3259 | else | |
3260 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
3261 | if ((S_GET_VALUE (label) & 1) == 0 |
3262 | /* Don't adjust the address if the label is global or weak, or | |
3263 | in a link-once section, since we'll be emitting symbol reloc | |
3264 | references to it which will be patched up by the linker, and | |
3265 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
3266 | && !S_IS_WEAK (label) | |
3267 | && !S_IS_EXTERNAL (label) | |
3268 | && !s_is_linkonce (label, now_seg)) | |
3269 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
3270 | } | |
3271 | ||
3272 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
3273 | ||
3274 | static void | |
3275 | mips_compressed_mark_labels (void) | |
3276 | { | |
3277 | struct insn_label_list *l; | |
3278 | ||
3279 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
3280 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
3281 | } |
3282 | ||
4d7206a2 RS |
3283 | /* End the current frag. Make it a variant frag and record the |
3284 | relaxation info. */ | |
3285 | ||
3286 | static void | |
3287 | relax_close_frag (void) | |
3288 | { | |
584892a6 | 3289 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 3290 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 3291 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
3292 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
3293 | ||
3294 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
3295 | mips_relax.first_fixup = 0; | |
3296 | } | |
3297 | ||
3298 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
3299 | See the comment above RELAX_ENCODE for more details. */ | |
3300 | ||
3301 | static void | |
3302 | relax_start (symbolS *symbol) | |
3303 | { | |
9c2799c2 | 3304 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
3305 | mips_relax.sequence = 1; |
3306 | mips_relax.symbol = symbol; | |
3307 | } | |
3308 | ||
3309 | /* Start generating the second version of a relaxable sequence. | |
3310 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
3311 | |
3312 | static void | |
4d7206a2 RS |
3313 | relax_switch (void) |
3314 | { | |
9c2799c2 | 3315 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
3316 | mips_relax.sequence = 2; |
3317 | } | |
3318 | ||
3319 | /* End the current relaxable sequence. */ | |
3320 | ||
3321 | static void | |
3322 | relax_end (void) | |
3323 | { | |
9c2799c2 | 3324 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
3325 | relax_close_frag (); |
3326 | mips_relax.sequence = 0; | |
3327 | } | |
3328 | ||
11625dd8 RS |
3329 | /* Return true if IP is a delayed branch or jump. */ |
3330 | ||
3331 | static inline bfd_boolean | |
3332 | delayed_branch_p (const struct mips_cl_insn *ip) | |
3333 | { | |
3334 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3335 | | INSN_COND_BRANCH_DELAY | |
3336 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
3337 | } | |
3338 | ||
3339 | /* Return true if IP is a compact branch or jump. */ | |
3340 | ||
3341 | static inline bfd_boolean | |
3342 | compact_branch_p (const struct mips_cl_insn *ip) | |
3343 | { | |
3344 | if (mips_opts.mips16) | |
3345 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3346 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
3347 | else | |
3348 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
3349 | | INSN2_COND_BRANCH)) != 0; | |
3350 | } | |
3351 | ||
3352 | /* Return true if IP is an unconditional branch or jump. */ | |
3353 | ||
3354 | static inline bfd_boolean | |
3355 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3356 | { | |
3357 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
3358 | || (mips_opts.mips16 | |
3359 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3360 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3361 | } | |
3362 | ||
3363 | /* Return true if IP is a branch-likely instruction. */ | |
3364 | ||
3365 | static inline bfd_boolean | |
3366 | branch_likely_p (const struct mips_cl_insn *ip) | |
3367 | { | |
3368 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3369 | } | |
3370 | ||
14fe068b RS |
3371 | /* Return the type of nop that should be used to fill the delay slot |
3372 | of delayed branch IP. */ | |
3373 | ||
3374 | static struct mips_cl_insn * | |
3375 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3376 | { | |
3377 | if (mips_opts.micromips | |
3378 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3379 | return µmips_nop32_insn; | |
3380 | return NOP_INSN; | |
3381 | } | |
3382 | ||
2309ddf2 | 3383 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3384 | |
3385 | static unsigned int | |
3386 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3387 | { | |
2309ddf2 | 3388 | unsigned long pinfo2; |
df58fc94 RS |
3389 | unsigned int mask; |
3390 | ||
3391 | mask = 0; | |
df58fc94 RS |
3392 | pinfo2 = ip->insn_mo->pinfo2; |
3393 | if (mips_opts.micromips) | |
3394 | { | |
df58fc94 RS |
3395 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3396 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3397 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3398 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3399 | if (pinfo2 & INSN2_MOD_SP) |
3400 | mask |= 1 << SP; | |
3401 | } | |
3402 | return mask; | |
3403 | } | |
3404 | ||
4c260379 RS |
3405 | /* Return the mask of core registers that IP reads. */ |
3406 | ||
3407 | static unsigned int | |
3408 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3409 | { | |
3410 | unsigned long pinfo, pinfo2; | |
3411 | unsigned int mask; | |
3412 | ||
df58fc94 | 3413 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3414 | pinfo = ip->insn_mo->pinfo; |
3415 | pinfo2 = ip->insn_mo->pinfo2; | |
3416 | if (mips_opts.mips16) | |
3417 | { | |
3418 | if (pinfo & MIPS16_INSN_READ_X) | |
3419 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3420 | if (pinfo & MIPS16_INSN_READ_Y) | |
3421 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3422 | if (pinfo & MIPS16_INSN_READ_T) | |
3423 | mask |= 1 << TREG; | |
3424 | if (pinfo & MIPS16_INSN_READ_SP) | |
3425 | mask |= 1 << SP; | |
3426 | if (pinfo & MIPS16_INSN_READ_31) | |
3427 | mask |= 1 << RA; | |
3428 | if (pinfo & MIPS16_INSN_READ_Z) | |
3429 | mask |= 1 << (mips16_to_32_reg_map | |
3430 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3431 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3432 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3433 | } | |
3434 | else | |
3435 | { | |
3436 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3437 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3438 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3439 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3440 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3441 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3442 | if (pinfo2 & INSN2_READ_GP) | |
3443 | mask |= 1 << GP; | |
3444 | if (pinfo2 & INSN2_READ_GPR_31) | |
3445 | mask |= 1 << RA; | |
4c260379 | 3446 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3447 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3448 | } |
2b0c8b40 MR |
3449 | if (mips_opts.micromips) |
3450 | { | |
3451 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3452 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3453 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3454 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3455 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3456 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3457 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3458 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3459 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3460 | { | |
3461 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3462 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3463 | } | |
3464 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3465 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3466 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3467 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3468 | } | |
fe35f09f RS |
3469 | /* Don't include register 0. */ |
3470 | return mask & ~1; | |
4c260379 RS |
3471 | } |
3472 | ||
3473 | /* Return the mask of core registers that IP writes. */ | |
3474 | ||
3475 | static unsigned int | |
3476 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3477 | { | |
3478 | unsigned long pinfo, pinfo2; | |
3479 | unsigned int mask; | |
3480 | ||
df58fc94 | 3481 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3482 | pinfo = ip->insn_mo->pinfo; |
3483 | pinfo2 = ip->insn_mo->pinfo2; | |
3484 | if (mips_opts.mips16) | |
3485 | { | |
3486 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3487 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3488 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3489 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3490 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3491 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3492 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3493 | mask |= 1 << TREG; | |
3494 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3495 | mask |= 1 << SP; | |
3496 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3497 | mask |= 1 << RA; | |
3498 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3499 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3500 | } | |
3501 | else | |
3502 | { | |
3503 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3504 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3505 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3506 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3507 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3508 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3509 | if (pinfo & INSN_WRITE_GPR_31) |
3510 | mask |= 1 << RA; | |
3511 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3512 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3513 | } |
2b0c8b40 MR |
3514 | if (mips_opts.micromips) |
3515 | { | |
3516 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3517 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
e76ff5ab | 3518 | if (pinfo2 & INSN2_WRITE_GPR_MH) |
2b0c8b40 | 3519 | { |
e76ff5ab RS |
3520 | mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)]; |
3521 | mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)]; | |
2b0c8b40 MR |
3522 | } |
3523 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3524 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3525 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3526 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3527 | } | |
fe35f09f RS |
3528 | /* Don't include register 0. */ |
3529 | return mask & ~1; | |
4c260379 RS |
3530 | } |
3531 | ||
3532 | /* Return the mask of floating-point registers that IP reads. */ | |
3533 | ||
3534 | static unsigned int | |
3535 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3536 | { | |
3537 | unsigned long pinfo, pinfo2; | |
3538 | unsigned int mask; | |
3539 | ||
3540 | mask = 0; | |
3541 | pinfo = ip->insn_mo->pinfo; | |
3542 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3543 | if (!mips_opts.mips16) |
df58fc94 RS |
3544 | { |
3545 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3546 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3547 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3548 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3549 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3550 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3551 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3552 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3553 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3554 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3555 | } |
3556 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3557 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3558 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3559 | mask |= mask << 1; | |
3560 | return mask; | |
3561 | } | |
3562 | ||
3563 | /* Return the mask of floating-point registers that IP writes. */ | |
3564 | ||
3565 | static unsigned int | |
3566 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3567 | { | |
3568 | unsigned long pinfo, pinfo2; | |
3569 | unsigned int mask; | |
3570 | ||
3571 | mask = 0; | |
3572 | pinfo = ip->insn_mo->pinfo; | |
3573 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3574 | if (!mips_opts.mips16) |
4c260379 RS |
3575 | { |
3576 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3577 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3578 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3579 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3580 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3581 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3582 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3583 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3584 | } |
3585 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3586 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3587 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3588 | mask |= mask << 1; | |
3589 | return mask; | |
3590 | } | |
3591 | ||
71400594 RS |
3592 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3593 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3594 | by VR4120 errata. */ | |
4d7206a2 | 3595 | |
71400594 RS |
3596 | static unsigned int |
3597 | classify_vr4120_insn (const char *name) | |
252b5132 | 3598 | { |
71400594 RS |
3599 | if (strncmp (name, "macc", 4) == 0) |
3600 | return FIX_VR4120_MACC; | |
3601 | if (strncmp (name, "dmacc", 5) == 0) | |
3602 | return FIX_VR4120_DMACC; | |
3603 | if (strncmp (name, "mult", 4) == 0) | |
3604 | return FIX_VR4120_MULT; | |
3605 | if (strncmp (name, "dmult", 5) == 0) | |
3606 | return FIX_VR4120_DMULT; | |
3607 | if (strstr (name, "div")) | |
3608 | return FIX_VR4120_DIV; | |
3609 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3610 | return FIX_VR4120_MTHILO; | |
3611 | return NUM_FIX_VR4120_CLASSES; | |
3612 | } | |
252b5132 | 3613 | |
ff239038 CM |
3614 | #define INSN_ERET 0x42000018 |
3615 | #define INSN_DERET 0x4200001f | |
3616 | ||
71400594 RS |
3617 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3618 | where INSN1 is the earlier instruction. Return the worst-case value | |
3619 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3620 | |
71400594 RS |
3621 | static unsigned int |
3622 | insns_between (const struct mips_cl_insn *insn1, | |
3623 | const struct mips_cl_insn *insn2) | |
3624 | { | |
3625 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3626 | unsigned int mask; |
71400594 RS |
3627 | |
3628 | /* This function needs to know which pinfo flags are set for INSN2 | |
3629 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3630 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3631 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3632 | pinfo1 = insn1->insn_mo->pinfo; |
3633 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3634 | |
4c260379 RS |
3635 | #define INSN2_USES_GPR(REG) \ |
3636 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3637 | |
3638 | /* For most targets, write-after-read dependencies on the HI and LO | |
3639 | registers must be separated by at least two instructions. */ | |
3640 | if (!hilo_interlocks) | |
252b5132 | 3641 | { |
71400594 RS |
3642 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3643 | return 2; | |
3644 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3645 | return 2; | |
3646 | } | |
3647 | ||
3648 | /* If we're working around r7000 errata, there must be two instructions | |
3649 | between an mfhi or mflo and any instruction that uses the result. */ | |
3650 | if (mips_7000_hilo_fix | |
df58fc94 | 3651 | && !mips_opts.micromips |
71400594 | 3652 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3653 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3654 | return 2; |
3655 | ||
ff239038 CM |
3656 | /* If we're working around 24K errata, one instruction is required |
3657 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3658 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3659 | { |
3660 | if (insn1->insn_opcode == INSN_ERET | |
3661 | || insn1->insn_opcode == INSN_DERET) | |
3662 | { | |
3663 | if (insn2 == NULL | |
3664 | || insn2->insn_opcode == INSN_ERET | |
3665 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3666 | || delayed_branch_p (insn2)) |
ff239038 CM |
3667 | return 1; |
3668 | } | |
3669 | } | |
3670 | ||
71400594 RS |
3671 | /* If working around VR4120 errata, check for combinations that need |
3672 | a single intervening instruction. */ | |
df58fc94 | 3673 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3674 | { |
3675 | unsigned int class1, class2; | |
252b5132 | 3676 | |
71400594 RS |
3677 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3678 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3679 | { |
71400594 RS |
3680 | if (insn2 == NULL) |
3681 | return 1; | |
3682 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3683 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3684 | return 1; | |
252b5132 | 3685 | } |
71400594 RS |
3686 | } |
3687 | ||
df58fc94 | 3688 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3689 | { |
3690 | /* Check for GPR or coprocessor load delays. All such delays | |
3691 | are on the RT register. */ | |
3692 | /* Itbl support may require additional care here. */ | |
3693 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3694 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3695 | { |
71400594 | 3696 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3697 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3698 | return 1; |
3699 | } | |
3700 | ||
3701 | /* Check for generic coprocessor hazards. | |
3702 | ||
3703 | This case is not handled very well. There is no special | |
3704 | knowledge of CP0 handling, and the coprocessors other than | |
3705 | the floating point unit are not distinguished at all. */ | |
3706 | /* Itbl support may require additional care here. FIXME! | |
3707 | Need to modify this to include knowledge about | |
3708 | user specified delays! */ | |
3709 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3710 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3711 | { | |
3712 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3713 | register. There must be a one instruction delay before INSN2 | |
3714 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3715 | mask = fpr_write_mask (insn1); |
3716 | if (mask != 0) | |
252b5132 | 3717 | { |
4c260379 | 3718 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3719 | return 1; |
252b5132 RH |
3720 | } |
3721 | else | |
3722 | { | |
71400594 RS |
3723 | /* Read-after-write dependencies on the control registers |
3724 | require a two-instruction gap. */ | |
3725 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3726 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3727 | return 2; | |
3728 | ||
3729 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3730 | also a coprocessor instruction, assume there must be | |
3731 | a one instruction gap. */ | |
3732 | if (pinfo2 & INSN_COP) | |
3733 | return 1; | |
252b5132 RH |
3734 | } |
3735 | } | |
6b76fefe | 3736 | |
71400594 RS |
3737 | /* Check for read-after-write dependencies on the coprocessor |
3738 | control registers in cases where INSN1 does not need a general | |
3739 | coprocessor delay. This means that INSN1 is a floating point | |
3740 | comparison instruction. */ | |
3741 | /* Itbl support may require additional care here. */ | |
3742 | else if (!cop_interlocks | |
3743 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3744 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3745 | return 1; | |
3746 | } | |
6b76fefe | 3747 | |
4c260379 | 3748 | #undef INSN2_USES_GPR |
6b76fefe | 3749 | |
71400594 RS |
3750 | return 0; |
3751 | } | |
6b76fefe | 3752 | |
7d8e00cf RS |
3753 | /* Return the number of nops that would be needed to work around the |
3754 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3755 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3756 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3757 | |
3758 | static int | |
932d1a1b | 3759 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3760 | const struct mips_cl_insn *insn) |
3761 | { | |
4c260379 RS |
3762 | int i, j; |
3763 | unsigned int mask; | |
7d8e00cf RS |
3764 | |
3765 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3766 | are not affected by the errata. */ | |
3767 | if (insn != 0 | |
3768 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3769 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3770 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3771 | return 0; | |
3772 | ||
3773 | /* Search for the first MFLO or MFHI. */ | |
3774 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3775 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3776 | { |
3777 | /* Extract the destination register. */ | |
4c260379 | 3778 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3779 | |
3780 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3781 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3782 | return 0; |
3783 | ||
3784 | /* ...or if any of the intervening instructions do. */ | |
3785 | for (j = 0; j < i; j++) | |
4c260379 | 3786 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3787 | return 0; |
3788 | ||
932d1a1b RS |
3789 | if (i >= ignore) |
3790 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3791 | } |
3792 | return 0; | |
3793 | } | |
3794 | ||
15be625d CM |
3795 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3796 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3797 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3798 | ||
3799 | /* Return the minimum alignment for this store instruction. */ | |
3800 | ||
3801 | static int | |
3802 | fix_24k_align_to (const struct mips_opcode *mo) | |
3803 | { | |
3804 | if (strcmp (mo->name, "sh") == 0) | |
3805 | return 2; | |
3806 | ||
3807 | if (strcmp (mo->name, "swc1") == 0 | |
3808 | || strcmp (mo->name, "swc2") == 0 | |
3809 | || strcmp (mo->name, "sw") == 0 | |
3810 | || strcmp (mo->name, "sc") == 0 | |
3811 | || strcmp (mo->name, "s.s") == 0) | |
3812 | return 4; | |
3813 | ||
3814 | if (strcmp (mo->name, "sdc1") == 0 | |
3815 | || strcmp (mo->name, "sdc2") == 0 | |
3816 | || strcmp (mo->name, "s.d") == 0) | |
3817 | return 8; | |
3818 | ||
3819 | /* sb, swl, swr */ | |
3820 | return 1; | |
3821 | } | |
3822 | ||
3823 | struct fix_24k_store_info | |
3824 | { | |
3825 | /* Immediate offset, if any, for this store instruction. */ | |
3826 | short off; | |
3827 | /* Alignment required by this store instruction. */ | |
3828 | int align_to; | |
3829 | /* True for register offsets. */ | |
3830 | int register_offset; | |
3831 | }; | |
3832 | ||
3833 | /* Comparison function used by qsort. */ | |
3834 | ||
3835 | static int | |
3836 | fix_24k_sort (const void *a, const void *b) | |
3837 | { | |
3838 | const struct fix_24k_store_info *pos1 = a; | |
3839 | const struct fix_24k_store_info *pos2 = b; | |
3840 | ||
3841 | return (pos1->off - pos2->off); | |
3842 | } | |
3843 | ||
3844 | /* INSN is a store instruction. Try to record the store information | |
3845 | in STINFO. Return false if the information isn't known. */ | |
3846 | ||
3847 | static bfd_boolean | |
3848 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3849 | const struct mips_cl_insn *insn) |
15be625d CM |
3850 | { |
3851 | /* The instruction must have a known offset. */ | |
3852 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3853 | return FALSE; | |
3854 | ||
3855 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3856 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3857 | return TRUE; | |
3858 | } | |
3859 | ||
932d1a1b RS |
3860 | /* Return the number of nops that would be needed to work around the 24k |
3861 | "lost data on stores during refill" errata if instruction INSN | |
3862 | immediately followed the 2 instructions described by HIST. | |
3863 | Ignore hazards that are contained within the first IGNORE | |
3864 | instructions of HIST. | |
3865 | ||
3866 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3867 | for the data cache refills and store data. The following describes | |
3868 | the scenario where the store data could be lost. | |
3869 | ||
3870 | * A data cache miss, due to either a load or a store, causing fill | |
3871 | data to be supplied by the memory subsystem | |
3872 | * The first three doublewords of fill data are returned and written | |
3873 | into the cache | |
3874 | * A sequence of four stores occurs in consecutive cycles around the | |
3875 | final doubleword of the fill: | |
3876 | * Store A | |
3877 | * Store B | |
3878 | * Store C | |
3879 | * Zero, One or more instructions | |
3880 | * Store D | |
3881 | ||
3882 | The four stores A-D must be to different doublewords of the line that | |
3883 | is being filled. The fourth instruction in the sequence above permits | |
3884 | the fill of the final doubleword to be transferred from the FSB into | |
3885 | the cache. In the sequence above, the stores may be either integer | |
3886 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3887 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3888 | different doublewords on the line. If the floating point unit is | |
3889 | running in 1:2 mode, it is not possible to create the sequence above | |
3890 | using only floating point store instructions. | |
15be625d CM |
3891 | |
3892 | In this case, the cache line being filled is incorrectly marked | |
3893 | invalid, thereby losing the data from any store to the line that | |
3894 | occurs between the original miss and the completion of the five | |
3895 | cycle sequence shown above. | |
3896 | ||
932d1a1b | 3897 | The workarounds are: |
15be625d | 3898 | |
932d1a1b RS |
3899 | * Run the data cache in write-through mode. |
3900 | * Insert a non-store instruction between | |
3901 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3902 | |
3903 | static int | |
932d1a1b | 3904 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3905 | const struct mips_cl_insn *insn) |
3906 | { | |
3907 | struct fix_24k_store_info pos[3]; | |
3908 | int align, i, base_offset; | |
3909 | ||
932d1a1b RS |
3910 | if (ignore >= 2) |
3911 | return 0; | |
3912 | ||
ab9794cf RS |
3913 | /* If the previous instruction wasn't a store, there's nothing to |
3914 | worry about. */ | |
15be625d CM |
3915 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3916 | return 0; | |
3917 | ||
ab9794cf RS |
3918 | /* If the instructions after the previous one are unknown, we have |
3919 | to assume the worst. */ | |
3920 | if (!insn) | |
15be625d CM |
3921 | return 1; |
3922 | ||
ab9794cf RS |
3923 | /* Check whether we are dealing with three consecutive stores. */ |
3924 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3925 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3926 | return 0; |
3927 | ||
3928 | /* If we don't know the relationship between the store addresses, | |
3929 | assume the worst. */ | |
ab9794cf | 3930 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3931 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3932 | return 1; | |
3933 | ||
3934 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3935 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3936 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3937 | return 1; | |
3938 | ||
3939 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3940 | ||
3941 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3942 | X bytes and such that the base register + X is known to be aligned | |
3943 | to align bytes. */ | |
3944 | ||
3945 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3946 | align = 8; | |
3947 | else | |
3948 | { | |
3949 | align = pos[0].align_to; | |
3950 | base_offset = pos[0].off; | |
3951 | for (i = 1; i < 3; i++) | |
3952 | if (align < pos[i].align_to) | |
3953 | { | |
3954 | align = pos[i].align_to; | |
3955 | base_offset = pos[i].off; | |
3956 | } | |
3957 | for (i = 0; i < 3; i++) | |
3958 | pos[i].off -= base_offset; | |
3959 | } | |
3960 | ||
3961 | pos[0].off &= ~align + 1; | |
3962 | pos[1].off &= ~align + 1; | |
3963 | pos[2].off &= ~align + 1; | |
3964 | ||
3965 | /* If any two stores write to the same chunk, they also write to the | |
3966 | same doubleword. The offsets are still sorted at this point. */ | |
3967 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3968 | return 0; | |
3969 | ||
3970 | /* A range of at least 9 bytes is needed for the stores to be in | |
3971 | non-overlapping doublewords. */ | |
3972 | if (pos[2].off - pos[0].off <= 8) | |
3973 | return 0; | |
3974 | ||
3975 | if (pos[2].off - pos[1].off >= 24 | |
3976 | || pos[1].off - pos[0].off >= 24 | |
3977 | || pos[2].off - pos[0].off >= 32) | |
3978 | return 0; | |
3979 | ||
3980 | return 1; | |
3981 | } | |
3982 | ||
71400594 | 3983 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3984 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3985 | where HIST[0] is the most recent instruction. Ignore hazards |
3986 | between INSN and the first IGNORE instructions in HIST. | |
3987 | ||
3988 | If INSN is null, return the worse-case number of nops for any | |
3989 | instruction. */ | |
bdaaa2e1 | 3990 | |
71400594 | 3991 | static int |
932d1a1b | 3992 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3993 | const struct mips_cl_insn *insn) |
3994 | { | |
3995 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3996 | |
71400594 | 3997 | nops = 0; |
932d1a1b | 3998 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3999 | { |
91d6fa6a | 4000 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
4001 | if (tmp_nops > nops) |
4002 | nops = tmp_nops; | |
4003 | } | |
7d8e00cf | 4004 | |
df58fc94 | 4005 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 4006 | { |
932d1a1b | 4007 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
4008 | if (tmp_nops > nops) |
4009 | nops = tmp_nops; | |
4010 | } | |
4011 | ||
df58fc94 | 4012 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 4013 | { |
932d1a1b | 4014 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
4015 | if (tmp_nops > nops) |
4016 | nops = tmp_nops; | |
4017 | } | |
4018 | ||
71400594 RS |
4019 | return nops; |
4020 | } | |
252b5132 | 4021 | |
71400594 | 4022 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 4023 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
4024 | would be needed after the extended sequence, ignoring hazards |
4025 | in the first IGNORE instructions. */ | |
252b5132 | 4026 | |
71400594 | 4027 | static int |
932d1a1b RS |
4028 | nops_for_sequence (int num_insns, int ignore, |
4029 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
4030 | { |
4031 | va_list args; | |
4032 | struct mips_cl_insn buffer[MAX_NOPS]; | |
4033 | struct mips_cl_insn *cursor; | |
4034 | int nops; | |
4035 | ||
91d6fa6a | 4036 | va_start (args, hist); |
71400594 | 4037 | cursor = buffer + num_insns; |
91d6fa6a | 4038 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
4039 | while (cursor > buffer) |
4040 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
4041 | ||
932d1a1b | 4042 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
4043 | va_end (args); |
4044 | return nops; | |
4045 | } | |
252b5132 | 4046 | |
71400594 RS |
4047 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
4048 | worst-case delay for the branch target. */ | |
252b5132 | 4049 | |
71400594 | 4050 | static int |
932d1a1b | 4051 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
4052 | const struct mips_cl_insn *insn) |
4053 | { | |
4054 | int nops, tmp_nops; | |
60b63b72 | 4055 | |
932d1a1b | 4056 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 4057 | if (delayed_branch_p (insn)) |
71400594 | 4058 | { |
932d1a1b | 4059 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 4060 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
4061 | if (tmp_nops > nops) |
4062 | nops = tmp_nops; | |
4063 | } | |
11625dd8 | 4064 | else if (compact_branch_p (insn)) |
71400594 | 4065 | { |
932d1a1b | 4066 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
4067 | if (tmp_nops > nops) |
4068 | nops = tmp_nops; | |
4069 | } | |
4070 | return nops; | |
4071 | } | |
4072 | ||
c67a084a NC |
4073 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
4074 | ||
4075 | static void | |
4076 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
4077 | { | |
df58fc94 | 4078 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
4079 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
4080 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
4081 | } | |
4082 | ||
4083 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
4084 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
4085 | ||
4086 | static void | |
4087 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
4088 | { | |
df58fc94 | 4089 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
4090 | if (strcmp (ip->insn_mo->name, "j") == 0 |
4091 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
4092 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
4093 | { | |
4094 | int sreg; | |
4095 | expressionS ep; | |
4096 | ||
4097 | if (! mips_opts.at) | |
4098 | return; | |
4099 | ||
df58fc94 | 4100 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
4101 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
4102 | return; | |
4103 | ||
4104 | ep.X_op = O_constant; | |
4105 | ep.X_add_number = 0xcfff0000; | |
4106 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
4107 | ep.X_add_number = 0xffff; | |
4108 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
4109 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
4110 | } | |
4111 | } | |
4112 | ||
4113 | static void | |
4114 | fix_loongson2f (struct mips_cl_insn * ip) | |
4115 | { | |
4116 | if (mips_fix_loongson2f_nop) | |
4117 | fix_loongson2f_nop (ip); | |
4118 | ||
4119 | if (mips_fix_loongson2f_jump) | |
4120 | fix_loongson2f_jump (ip); | |
4121 | } | |
4122 | ||
a4e06468 RS |
4123 | /* IP is a branch that has a delay slot, and we need to fill it |
4124 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
4125 | with the previous instruction. |
4126 | ADDRESS_EXPR is an operand of the instruction to be used with | |
4127 | RELOC_TYPE. */ | |
a4e06468 RS |
4128 | |
4129 | static bfd_boolean | |
e407c74b NC |
4130 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
4131 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 4132 | { |
2b0c8b40 | 4133 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
4134 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
4135 | ||
4136 | /* -O2 and above is required for this optimization. */ | |
4137 | if (mips_optimize < 2) | |
4138 | return FALSE; | |
4139 | ||
4140 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
4141 | if (mips_opts.nomove) | |
4142 | return FALSE; | |
4143 | ||
4144 | /* We can't swap if the previous instruction's position is fixed. */ | |
4145 | if (history[0].fixed_p) | |
4146 | return FALSE; | |
4147 | ||
4148 | /* If the previous previous insn was in a .set noreorder, we can't | |
4149 | swap. Actually, the MIPS assembler will swap in this situation. | |
4150 | However, gcc configured -with-gnu-as will generate code like | |
4151 | ||
4152 | .set noreorder | |
4153 | lw $4,XXX | |
4154 | .set reorder | |
4155 | INSN | |
4156 | bne $4,$0,foo | |
4157 | ||
4158 | in which we can not swap the bne and INSN. If gcc is not configured | |
4159 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
4160 | if (history[1].noreorder_p) | |
4161 | return FALSE; | |
4162 | ||
87333bb7 MR |
4163 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
4164 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
4165 | if (mips_opts.mips16 && history[0].fixp[0]) |
4166 | return FALSE; | |
4167 | ||
4168 | /* If the branch is itself the target of a branch, we can not swap. | |
4169 | We cheat on this; all we check for is whether there is a label on | |
4170 | this instruction. If there are any branches to anything other than | |
4171 | a label, users must use .set noreorder. */ | |
4172 | if (seg_info (now_seg)->label_list) | |
4173 | return FALSE; | |
4174 | ||
4175 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 4176 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
4177 | MIPS16 code, which uses variant frags for different purposes. */ |
4178 | if (!mips_opts.mips16 | |
a4e06468 RS |
4179 | && history[0].frag |
4180 | && history[0].frag->fr_type == rs_machine_dependent) | |
4181 | return FALSE; | |
4182 | ||
bcd530a7 RS |
4183 | /* We do not swap with instructions that cannot architecturally |
4184 | be placed in a branch delay slot, such as SYNC or ERET. We | |
4185 | also refrain from swapping with a trap instruction, since it | |
4186 | complicates trap handlers to have the trap instruction be in | |
4187 | a delay slot. */ | |
a4e06468 | 4188 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 4189 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
4190 | return FALSE; |
4191 | ||
4192 | /* Check for conflicts between the branch and the instructions | |
4193 | before the candidate delay slot. */ | |
4194 | if (nops_for_insn (0, history + 1, ip) > 0) | |
4195 | return FALSE; | |
4196 | ||
4197 | /* Check for conflicts between the swapped sequence and the | |
4198 | target of the branch. */ | |
4199 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
4200 | return FALSE; | |
4201 | ||
4202 | /* If the branch reads a register that the previous | |
4203 | instruction sets, we can not swap. */ | |
4204 | gpr_read = gpr_read_mask (ip); | |
4205 | prev_gpr_write = gpr_write_mask (&history[0]); | |
4206 | if (gpr_read & prev_gpr_write) | |
4207 | return FALSE; | |
4208 | ||
4209 | /* If the branch writes a register that the previous | |
4210 | instruction sets, we can not swap. */ | |
4211 | gpr_write = gpr_write_mask (ip); | |
4212 | if (gpr_write & prev_gpr_write) | |
4213 | return FALSE; | |
4214 | ||
4215 | /* If the branch writes a register that the previous | |
4216 | instruction reads, we can not swap. */ | |
4217 | prev_gpr_read = gpr_read_mask (&history[0]); | |
4218 | if (gpr_write & prev_gpr_read) | |
4219 | return FALSE; | |
4220 | ||
4221 | /* If one instruction sets a condition code and the | |
4222 | other one uses a condition code, we can not swap. */ | |
4223 | pinfo = ip->insn_mo->pinfo; | |
4224 | if ((pinfo & INSN_READ_COND_CODE) | |
4225 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
4226 | return FALSE; | |
4227 | if ((pinfo & INSN_WRITE_COND_CODE) | |
4228 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
4229 | return FALSE; | |
4230 | ||
4231 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 4232 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
4233 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
4234 | return FALSE; | |
2b0c8b40 MR |
4235 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
4236 | return FALSE; | |
a4e06468 | 4237 | |
df58fc94 RS |
4238 | /* If the previous instruction has an incorrect size for a fixed |
4239 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
4240 | pinfo2 = ip->insn_mo->pinfo2; |
4241 | if (mips_opts.micromips | |
4242 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
4243 | && insn_length (history) != 2) | |
4244 | return FALSE; | |
4245 | if (mips_opts.micromips | |
4246 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
4247 | && insn_length (history) != 4) | |
4248 | return FALSE; | |
4249 | ||
e407c74b NC |
4250 | /* On R5900 short loops need to be fixed by inserting a nop in |
4251 | the branch delay slots. | |
4252 | A short loop can be terminated too early. */ | |
4253 | if (mips_opts.arch == CPU_R5900 | |
4254 | /* Check if instruction has a parameter, ignore "j $31". */ | |
4255 | && (address_expr != NULL) | |
4256 | /* Parameter must be 16 bit. */ | |
4257 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
4258 | /* Branch to same segment. */ | |
4259 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
4260 | /* Branch to same code fragment. */ | |
4261 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
4262 | /* Can only calculate branch offset if value is known. */ | |
4263 | && symbol_constant_p(address_expr->X_add_symbol) | |
4264 | /* Check if branch is really conditional. */ | |
4265 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
4266 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
4267 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
4268 | { | |
4269 | int distance; | |
4270 | /* Check if loop is shorter than 6 instructions including | |
4271 | branch and delay slot. */ | |
4272 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
4273 | if (distance <= 20) | |
4274 | { | |
4275 | int i; | |
4276 | int rv; | |
4277 | ||
4278 | rv = FALSE; | |
4279 | /* When the loop includes branches or jumps, | |
4280 | it is not a short loop. */ | |
4281 | for (i = 0; i < (distance / 4); i++) | |
4282 | { | |
4283 | if ((history[i].cleared_p) | |
4284 | || delayed_branch_p(&history[i])) | |
4285 | { | |
4286 | rv = TRUE; | |
4287 | break; | |
4288 | } | |
4289 | } | |
4290 | if (rv == FALSE) | |
4291 | { | |
4292 | /* Insert nop after branch to fix short loop. */ | |
4293 | return FALSE; | |
4294 | } | |
4295 | } | |
4296 | } | |
4297 | ||
a4e06468 RS |
4298 | return TRUE; |
4299 | } | |
4300 | ||
e407c74b NC |
4301 | /* Decide how we should add IP to the instruction stream. |
4302 | ADDRESS_EXPR is an operand of the instruction to be used with | |
4303 | RELOC_TYPE. */ | |
a4e06468 RS |
4304 | |
4305 | static enum append_method | |
e407c74b NC |
4306 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
4307 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
4308 | { |
4309 | unsigned long pinfo; | |
4310 | ||
4311 | /* The relaxed version of a macro sequence must be inherently | |
4312 | hazard-free. */ | |
4313 | if (mips_relax.sequence == 2) | |
4314 | return APPEND_ADD; | |
4315 | ||
4316 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
4317 | if (mips_opts.noreorder) | |
4318 | return APPEND_ADD; | |
4319 | ||
4320 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 4321 | if (delayed_branch_p (ip)) |
a4e06468 | 4322 | { |
e407c74b NC |
4323 | if (!branch_likely_p (ip) |
4324 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
4325 | return APPEND_SWAP; |
4326 | ||
11625dd8 | 4327 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
4328 | if (mips_opts.mips16 |
4329 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
4330 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
4331 | return APPEND_ADD_COMPACT; | |
4332 | ||
4333 | return APPEND_ADD_WITH_NOP; | |
4334 | } | |
4335 | ||
a4e06468 RS |
4336 | return APPEND_ADD; |
4337 | } | |
4338 | ||
ceb94aa5 RS |
4339 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
4340 | Point IP->insn_mo to the new opcode's definition. */ | |
4341 | ||
4342 | static void | |
4343 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
4344 | { | |
4345 | const struct mips_opcode *mo, *end; | |
4346 | ||
4347 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
4348 | for (mo = ip->insn_mo; mo < end; mo++) | |
4349 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
4350 | { | |
4351 | ip->insn_mo = mo; | |
4352 | return; | |
4353 | } | |
4354 | abort (); | |
4355 | } | |
4356 | ||
df58fc94 RS |
4357 | /* For microMIPS macros, we need to generate a local number label |
4358 | as the target of branches. */ | |
4359 | #define MICROMIPS_LABEL_CHAR '\037' | |
4360 | static unsigned long micromips_target_label; | |
4361 | static char micromips_target_name[32]; | |
4362 | ||
4363 | static char * | |
4364 | micromips_label_name (void) | |
4365 | { | |
4366 | char *p = micromips_target_name; | |
4367 | char symbol_name_temporary[24]; | |
4368 | unsigned long l; | |
4369 | int i; | |
4370 | ||
4371 | if (*p) | |
4372 | return p; | |
4373 | ||
4374 | i = 0; | |
4375 | l = micromips_target_label; | |
4376 | #ifdef LOCAL_LABEL_PREFIX | |
4377 | *p++ = LOCAL_LABEL_PREFIX; | |
4378 | #endif | |
4379 | *p++ = 'L'; | |
4380 | *p++ = MICROMIPS_LABEL_CHAR; | |
4381 | do | |
4382 | { | |
4383 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4384 | l /= 10; | |
4385 | } | |
4386 | while (l != 0); | |
4387 | while (i > 0) | |
4388 | *p++ = symbol_name_temporary[--i]; | |
4389 | *p = '\0'; | |
4390 | ||
4391 | return micromips_target_name; | |
4392 | } | |
4393 | ||
4394 | static void | |
4395 | micromips_label_expr (expressionS *label_expr) | |
4396 | { | |
4397 | label_expr->X_op = O_symbol; | |
4398 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4399 | label_expr->X_add_number = 0; | |
4400 | } | |
4401 | ||
4402 | static void | |
4403 | micromips_label_inc (void) | |
4404 | { | |
4405 | micromips_target_label++; | |
4406 | *micromips_target_name = '\0'; | |
4407 | } | |
4408 | ||
4409 | static void | |
4410 | micromips_add_label (void) | |
4411 | { | |
4412 | symbolS *s; | |
4413 | ||
4414 | s = colon (micromips_label_name ()); | |
4415 | micromips_label_inc (); | |
f3ded42a | 4416 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
4417 | } |
4418 | ||
4419 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4420 | corresponding to the requested one if any. Otherwise return | |
4421 | the reloc unchanged. */ | |
4422 | ||
4423 | static bfd_reloc_code_real_type | |
4424 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4425 | { | |
4426 | static const bfd_reloc_code_real_type relocs[][2] = | |
4427 | { | |
4428 | /* Keep sorted incrementally by the left-hand key. */ | |
4429 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4430 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4431 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4432 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4433 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4434 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4435 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4436 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4437 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4438 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4439 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4440 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4441 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4442 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4443 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4444 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4445 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4446 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4447 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4448 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4449 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4450 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4451 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4452 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4453 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4454 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4455 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4456 | }; | |
4457 | bfd_reloc_code_real_type r; | |
4458 | size_t i; | |
4459 | ||
4460 | if (!mips_opts.micromips) | |
4461 | return reloc; | |
4462 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4463 | { | |
4464 | r = relocs[i][0]; | |
4465 | if (r > reloc) | |
4466 | return reloc; | |
4467 | if (r == reloc) | |
4468 | return relocs[i][1]; | |
4469 | } | |
4470 | return reloc; | |
4471 | } | |
4472 | ||
b886a2ab RS |
4473 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4474 | Return true on success, storing the resolved value in RESULT. */ | |
4475 | ||
4476 | static bfd_boolean | |
4477 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4478 | offsetT *result) | |
4479 | { | |
4480 | switch (reloc) | |
4481 | { | |
4482 | case BFD_RELOC_MIPS_HIGHEST: | |
4483 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4484 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4485 | return TRUE; | |
4486 | ||
4487 | case BFD_RELOC_MIPS_HIGHER: | |
4488 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4489 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4490 | return TRUE; | |
4491 | ||
4492 | case BFD_RELOC_HI16_S: | |
4493 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4494 | case BFD_RELOC_MIPS16_HI16_S: | |
4495 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4496 | return TRUE; | |
4497 | ||
4498 | case BFD_RELOC_HI16: | |
4499 | case BFD_RELOC_MICROMIPS_HI16: | |
4500 | case BFD_RELOC_MIPS16_HI16: | |
4501 | *result = (operand >> 16) & 0xffff; | |
4502 | return TRUE; | |
4503 | ||
4504 | case BFD_RELOC_LO16: | |
4505 | case BFD_RELOC_MICROMIPS_LO16: | |
4506 | case BFD_RELOC_MIPS16_LO16: | |
4507 | *result = operand & 0xffff; | |
4508 | return TRUE; | |
4509 | ||
4510 | case BFD_RELOC_UNUSED: | |
4511 | *result = operand; | |
4512 | return TRUE; | |
4513 | ||
4514 | default: | |
4515 | return FALSE; | |
4516 | } | |
4517 | } | |
4518 | ||
71400594 RS |
4519 | /* Output an instruction. IP is the instruction information. |
4520 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4521 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4522 | a macro expansion. */ | |
71400594 RS |
4523 | |
4524 | static void | |
4525 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4526 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4527 | { |
14fe068b | 4528 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4529 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4530 | enum append_method method; |
2309ddf2 | 4531 | bfd_boolean relax32; |
2b0c8b40 | 4532 | int branch_disp; |
71400594 | 4533 | |
2309ddf2 | 4534 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4535 | fix_loongson2f (ip); |
4536 | ||
738f4d98 | 4537 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4538 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4539 | |
df58fc94 | 4540 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4541 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4542 | |
4543 | if (mips_opts.micromips | |
4544 | && !expansionp | |
4545 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4546 | && micromips_insn_length (ip->insn_mo) != 2) | |
4547 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4548 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4549 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4550 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4551 | |
15be625d CM |
4552 | if (address_expr == NULL) |
4553 | ip->complete_p = 1; | |
b886a2ab RS |
4554 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4555 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4556 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4557 | && address_expr->X_op == O_constant) |
4558 | { | |
15be625d CM |
4559 | switch (*reloc_type) |
4560 | { | |
15be625d | 4561 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4562 | { |
4563 | int shift; | |
4564 | ||
4565 | shift = mips_opts.micromips ? 1 : 2; | |
4566 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4567 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4568 | (unsigned long) address_expr->X_add_number); | |
4569 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4570 | & 0x3ffffff); | |
335574df | 4571 | ip->complete_p = 1; |
df58fc94 | 4572 | } |
15be625d CM |
4573 | break; |
4574 | ||
4575 | case BFD_RELOC_MIPS16_JMP: | |
4576 | if ((address_expr->X_add_number & 3) != 0) | |
4577 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4578 | (unsigned long) address_expr->X_add_number); | |
4579 | ip->insn_opcode |= | |
4580 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4581 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4582 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4583 | ip->complete_p = 1; |
15be625d CM |
4584 | break; |
4585 | ||
4586 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4587 | { |
4588 | int shift; | |
4589 | ||
4590 | shift = mips_opts.micromips ? 1 : 2; | |
4591 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4592 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4593 | (unsigned long) address_expr->X_add_number); | |
4594 | if (!mips_relax_branch) | |
4595 | { | |
4596 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4597 | & ~((1 << (shift + 16)) - 1)) | |
4598 | as_bad (_("branch address range overflow (0x%lx)"), | |
4599 | (unsigned long) address_expr->X_add_number); | |
4600 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4601 | & 0xffff); | |
4602 | } | |
df58fc94 | 4603 | } |
15be625d CM |
4604 | break; |
4605 | ||
4606 | default: | |
b886a2ab RS |
4607 | { |
4608 | offsetT value; | |
4609 | ||
4610 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4611 | &value)) | |
4612 | { | |
4613 | ip->insn_opcode |= value & 0xffff; | |
4614 | ip->complete_p = 1; | |
4615 | } | |
4616 | } | |
4617 | break; | |
4618 | } | |
15be625d CM |
4619 | } |
4620 | ||
71400594 RS |
4621 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4622 | { | |
4623 | /* There are a lot of optimizations we could do that we don't. | |
4624 | In particular, we do not, in general, reorder instructions. | |
4625 | If you use gcc with optimization, it will reorder | |
4626 | instructions and generally do much more optimization then we | |
4627 | do here; repeating all that work in the assembler would only | |
4628 | benefit hand written assembly code, and does not seem worth | |
4629 | it. */ | |
4630 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4631 | ? nops_for_insn (0, history, NULL) |
4632 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4633 | if (nops > 0) |
252b5132 RH |
4634 | { |
4635 | fragS *old_frag; | |
4636 | unsigned long old_frag_offset; | |
4637 | int i; | |
252b5132 RH |
4638 | |
4639 | old_frag = frag_now; | |
4640 | old_frag_offset = frag_now_fix (); | |
4641 | ||
4642 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4643 | add_fixed_insn (NOP_INSN); |
4644 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4645 | |
4646 | if (listing) | |
4647 | { | |
4648 | listing_prev_line (); | |
4649 | /* We may be at the start of a variant frag. In case we | |
4650 | are, make sure there is enough space for the frag | |
4651 | after the frags created by listing_prev_line. The | |
4652 | argument to frag_grow here must be at least as large | |
4653 | as the argument to all other calls to frag_grow in | |
4654 | this file. We don't have to worry about being in the | |
4655 | middle of a variant frag, because the variants insert | |
4656 | all needed nop instructions themselves. */ | |
4657 | frag_grow (40); | |
4658 | } | |
4659 | ||
462427c4 | 4660 | mips_move_text_labels (); |
252b5132 RH |
4661 | |
4662 | #ifndef NO_ECOFF_DEBUGGING | |
4663 | if (ECOFF_DEBUGGING) | |
4664 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4665 | #endif | |
4666 | } | |
71400594 RS |
4667 | } |
4668 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4669 | { | |
932d1a1b RS |
4670 | int nops; |
4671 | ||
4672 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4673 | ignoring hazards generated by the first prev_nop_frag_since | |
4674 | instructions. */ | |
4675 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4676 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4677 | |
71400594 RS |
4678 | /* Enforce NOPS as a minimum. */ |
4679 | if (nops > prev_nop_frag_required) | |
4680 | prev_nop_frag_required = nops; | |
252b5132 | 4681 | |
71400594 RS |
4682 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4683 | { | |
4684 | /* Settle for the current number of nops. Update the history | |
4685 | accordingly (for the benefit of any future .set reorder code). */ | |
4686 | prev_nop_frag = NULL; | |
4687 | insert_into_history (prev_nop_frag_since, | |
4688 | prev_nop_frag_holds, NOP_INSN); | |
4689 | } | |
4690 | else | |
4691 | { | |
4692 | /* Allow this instruction to replace one of the nops that was | |
4693 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4694 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4695 | prev_nop_frag_holds--; |
4696 | prev_nop_frag_since++; | |
252b5132 RH |
4697 | } |
4698 | } | |
4699 | ||
e407c74b | 4700 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4701 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4702 | |
e410add4 RS |
4703 | dwarf2_emit_insn (0); |
4704 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
4705 | so "move" the instruction address accordingly. | |
4706 | ||
4707 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
4708 | entries. If this instruction is a branch that we are going to swap | |
4709 | with the previous instruction, the two instructions should be | |
4710 | treated as a unit, and the debug information for both instructions | |
4711 | should refer to the start of the branch sequence. Using the | |
4712 | current position is certainly wrong when swapping a 32-bit branch | |
4713 | and a 16-bit delay slot, since the current position would then be | |
4714 | in the middle of a branch. */ | |
4715 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 4716 | |
df58fc94 RS |
4717 | relax32 = (mips_relax_branch |
4718 | /* Don't try branch relaxation within .set nomacro, or within | |
4719 | .set noat if we use $at for PIC computations. If it turns | |
4720 | out that the branch was out-of-range, we'll get an error. */ | |
4721 | && !mips_opts.warn_about_macros | |
4722 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
4723 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
4724 | as they have no complementing branches. */ | |
4725 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
4726 | |
4727 | if (!HAVE_CODE_COMPRESSION | |
4728 | && address_expr | |
4729 | && relax32 | |
0b25d3e6 | 4730 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4731 | && delayed_branch_p (ip)) |
4a6a3df4 | 4732 | { |
895921c9 | 4733 | relaxed_branch = TRUE; |
1e915849 RS |
4734 | add_relaxed_insn (ip, (relaxed_branch_length |
4735 | (NULL, NULL, | |
11625dd8 RS |
4736 | uncond_branch_p (ip) ? -1 |
4737 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4738 | : 0)), 4, |
4739 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4740 | (AT, |
11625dd8 RS |
4741 | uncond_branch_p (ip), |
4742 | branch_likely_p (ip), | |
1e915849 RS |
4743 | pinfo & INSN_WRITE_GPR_31, |
4744 | 0), | |
4745 | address_expr->X_add_symbol, | |
4746 | address_expr->X_add_number); | |
4a6a3df4 AO |
4747 | *reloc_type = BFD_RELOC_UNUSED; |
4748 | } | |
df58fc94 RS |
4749 | else if (mips_opts.micromips |
4750 | && address_expr | |
4751 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4752 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4753 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4754 | /* Don't try branch relaxation when users specify | |
4755 | 16-bit/32-bit instructions. */ | |
4756 | && !forced_insn_length) | |
df58fc94 RS |
4757 | { |
4758 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4759 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4760 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4761 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4762 | int al = pinfo & INSN_WRITE_GPR_31; |
4763 | int length32; | |
4764 | ||
4765 | gas_assert (address_expr != NULL); | |
4766 | gas_assert (!mips_relax.sequence); | |
4767 | ||
2b0c8b40 | 4768 | relaxed_branch = TRUE; |
df58fc94 RS |
4769 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4770 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4771 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4772 | relax32, 0, 0), | |
df58fc94 RS |
4773 | address_expr->X_add_symbol, |
4774 | address_expr->X_add_number); | |
4775 | *reloc_type = BFD_RELOC_UNUSED; | |
4776 | } | |
4777 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4778 | { |
4779 | /* We need to set up a variant frag. */ | |
df58fc94 | 4780 | gas_assert (address_expr != NULL); |
1e915849 RS |
4781 | add_relaxed_insn (ip, 4, 0, |
4782 | RELAX_MIPS16_ENCODE | |
4783 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4784 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4785 | delayed_branch_p (&history[0]), |
1e915849 RS |
4786 | history[0].mips16_absolute_jump_p), |
4787 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4788 | } |
5c04167a | 4789 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4790 | { |
11625dd8 | 4791 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4792 | /* Make sure there is enough room to swap this instruction with |
4793 | a following jump instruction. */ | |
4794 | frag_grow (6); | |
1e915849 | 4795 | add_fixed_insn (ip); |
252b5132 RH |
4796 | } |
4797 | else | |
4798 | { | |
4799 | if (mips_opts.mips16 | |
4800 | && mips_opts.noreorder | |
11625dd8 | 4801 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4802 | as_warn (_("extended instruction in delay slot")); |
4803 | ||
4d7206a2 RS |
4804 | if (mips_relax.sequence) |
4805 | { | |
4806 | /* If we've reached the end of this frag, turn it into a variant | |
4807 | frag and record the information for the instructions we've | |
4808 | written so far. */ | |
4809 | if (frag_room () < 4) | |
4810 | relax_close_frag (); | |
df58fc94 | 4811 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4812 | } |
4813 | ||
584892a6 | 4814 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4815 | { |
4816 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4817 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4818 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4819 | mips_macro_warning.insns[0]++; | |
4820 | } | |
584892a6 | 4821 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4822 | { |
4823 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4824 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4825 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4826 | mips_macro_warning.insns[1]++; | |
4827 | } | |
584892a6 | 4828 | |
1e915849 RS |
4829 | if (mips_opts.mips16) |
4830 | { | |
4831 | ip->fixed_p = 1; | |
4832 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4833 | } | |
4834 | add_fixed_insn (ip); | |
252b5132 RH |
4835 | } |
4836 | ||
9fe77896 | 4837 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4838 | { |
df58fc94 | 4839 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4840 | reloc_howto_type *howto0; |
9fe77896 RS |
4841 | reloc_howto_type *howto; |
4842 | int i; | |
34ce925e | 4843 | |
df58fc94 RS |
4844 | /* Perform any necessary conversion to microMIPS relocations |
4845 | and find out how many relocations there actually are. */ | |
4846 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4847 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4848 | ||
9fe77896 RS |
4849 | /* In a compound relocation, it is the final (outermost) |
4850 | operator that determines the relocated field. */ | |
2309ddf2 | 4851 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
4852 | if (!howto) |
4853 | abort (); | |
2309ddf2 MR |
4854 | |
4855 | if (i > 1) | |
4856 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4857 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4858 | bfd_get_reloc_size (howto), | |
4859 | address_expr, | |
2309ddf2 MR |
4860 | howto0 && howto0->pc_relative, |
4861 | final_type[0]); | |
9fe77896 RS |
4862 | |
4863 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4864 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4865 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4866 | ||
4867 | /* These relocations can have an addend that won't fit in | |
4868 | 4 octets for 64bit assembly. */ | |
4869 | if (HAVE_64BIT_GPRS | |
4870 | && ! howto->partial_inplace | |
4871 | && (reloc_type[0] == BFD_RELOC_16 | |
4872 | || reloc_type[0] == BFD_RELOC_32 | |
4873 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4874 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4875 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4876 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4877 | || reloc_type[0] == BFD_RELOC_64 | |
4878 | || reloc_type[0] == BFD_RELOC_CTOR | |
4879 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4880 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4881 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4882 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4883 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4884 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4885 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4886 | || hi16_reloc_p (reloc_type[0]) | |
4887 | || lo16_reloc_p (reloc_type[0]))) | |
4888 | ip->fixp[0]->fx_no_overflow = 1; | |
4889 | ||
ddaf2c41 MR |
4890 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4891 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4892 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4893 | ip->fixp[0]->fx_no_overflow = 1; | |
4894 | ||
9fe77896 RS |
4895 | if (mips_relax.sequence) |
4896 | { | |
4897 | if (mips_relax.first_fixup == 0) | |
4898 | mips_relax.first_fixup = ip->fixp[0]; | |
4899 | } | |
4900 | else if (reloc_needs_lo_p (*reloc_type)) | |
4901 | { | |
4902 | struct mips_hi_fixup *hi_fixup; | |
4903 | ||
4904 | /* Reuse the last entry if it already has a matching %lo. */ | |
4905 | hi_fixup = mips_hi_fixup_list; | |
4906 | if (hi_fixup == 0 | |
4907 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4908 | { |
9fe77896 RS |
4909 | hi_fixup = ((struct mips_hi_fixup *) |
4910 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4911 | hi_fixup->next = mips_hi_fixup_list; | |
4912 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4913 | } |
9fe77896 RS |
4914 | hi_fixup->fixp = ip->fixp[0]; |
4915 | hi_fixup->seg = now_seg; | |
4916 | } | |
252b5132 | 4917 | |
9fe77896 RS |
4918 | /* Add fixups for the second and third relocations, if given. |
4919 | Note that the ABI allows the second relocation to be | |
4920 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4921 | moment we only use RSS_UNDEF, but we could add support | |
4922 | for the others if it ever becomes necessary. */ | |
4923 | for (i = 1; i < 3; i++) | |
4924 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4925 | { | |
4926 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4927 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4928 | FALSE, final_type[i]); |
f6688943 | 4929 | |
9fe77896 RS |
4930 | /* Use fx_tcbit to mark compound relocs. */ |
4931 | ip->fixp[0]->fx_tcbit = 1; | |
4932 | ip->fixp[i]->fx_tcbit = 1; | |
4933 | } | |
252b5132 | 4934 | } |
1e915849 | 4935 | install_insn (ip); |
252b5132 RH |
4936 | |
4937 | /* Update the register mask information. */ | |
4c260379 RS |
4938 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4939 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4940 | |
a4e06468 | 4941 | switch (method) |
252b5132 | 4942 | { |
a4e06468 RS |
4943 | case APPEND_ADD: |
4944 | insert_into_history (0, 1, ip); | |
4945 | break; | |
4946 | ||
4947 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4948 | { |
4949 | struct mips_cl_insn *nop; | |
4950 | ||
4951 | insert_into_history (0, 1, ip); | |
4952 | nop = get_delay_slot_nop (ip); | |
4953 | add_fixed_insn (nop); | |
4954 | insert_into_history (0, 1, nop); | |
4955 | if (mips_relax.sequence) | |
4956 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4957 | } | |
a4e06468 RS |
4958 | break; |
4959 | ||
4960 | case APPEND_ADD_COMPACT: | |
4961 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4962 | gas_assert (mips_opts.mips16); | |
4963 | ip->insn_opcode |= 0x0080; | |
4964 | find_altered_mips16_opcode (ip); | |
4965 | install_insn (ip); | |
4966 | insert_into_history (0, 1, ip); | |
4967 | break; | |
4968 | ||
4969 | case APPEND_SWAP: | |
4970 | { | |
4971 | struct mips_cl_insn delay = history[0]; | |
4972 | if (mips_opts.mips16) | |
4973 | { | |
4974 | know (delay.frag == ip->frag); | |
4975 | move_insn (ip, delay.frag, delay.where); | |
4976 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4977 | } | |
464ab0e5 | 4978 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4979 | { |
4980 | /* Add the delay slot instruction to the end of the | |
4981 | current frag and shrink the fixed part of the | |
4982 | original frag. If the branch occupies the tail of | |
4983 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4984 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4985 | if (delay.frag == ip->frag) |
2b0c8b40 | 4986 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4987 | add_fixed_insn (&delay); |
4988 | } | |
4989 | else | |
4990 | { | |
2b0c8b40 MR |
4991 | move_insn (&delay, ip->frag, |
4992 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4993 | move_insn (ip, history[0].frag, history[0].where); |
4994 | } | |
4995 | history[0] = *ip; | |
4996 | delay.fixed_p = 1; | |
4997 | insert_into_history (0, 1, &delay); | |
4998 | } | |
4999 | break; | |
252b5132 RH |
5000 | } |
5001 | ||
13408f1e | 5002 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
5003 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
5004 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
5005 | { |
5006 | unsigned int i; | |
5007 | ||
79850f26 | 5008 | mips_no_prev_insn (); |
13408f1e | 5009 | |
e407c74b | 5010 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 5011 | history[i].cleared_p = 1; |
e407c74b NC |
5012 | } |
5013 | ||
df58fc94 RS |
5014 | /* We need to emit a label at the end of branch-likely macros. */ |
5015 | if (emit_branch_likely_macro) | |
5016 | { | |
5017 | emit_branch_likely_macro = FALSE; | |
5018 | micromips_add_label (); | |
5019 | } | |
5020 | ||
252b5132 RH |
5021 | /* We just output an insn, so the next one doesn't have a label. */ |
5022 | mips_clear_insn_labels (); | |
252b5132 RH |
5023 | } |
5024 | ||
e407c74b NC |
5025 | /* Forget that there was any previous instruction or label. |
5026 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
5027 | |
5028 | static void | |
7d10b47d | 5029 | mips_no_prev_insn (void) |
252b5132 | 5030 | { |
7d10b47d RS |
5031 | prev_nop_frag = NULL; |
5032 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
5033 | mips_clear_insn_labels (); |
5034 | } | |
5035 | ||
7d10b47d RS |
5036 | /* This function must be called before we emit something other than |
5037 | instructions. It is like mips_no_prev_insn except that it inserts | |
5038 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 5039 | |
7d10b47d RS |
5040 | void |
5041 | mips_emit_delays (void) | |
252b5132 RH |
5042 | { |
5043 | if (! mips_opts.noreorder) | |
5044 | { | |
932d1a1b | 5045 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
5046 | if (nops > 0) |
5047 | { | |
7d10b47d RS |
5048 | while (nops-- > 0) |
5049 | add_fixed_insn (NOP_INSN); | |
462427c4 | 5050 | mips_move_text_labels (); |
7d10b47d RS |
5051 | } |
5052 | } | |
5053 | mips_no_prev_insn (); | |
5054 | } | |
5055 | ||
5056 | /* Start a (possibly nested) noreorder block. */ | |
5057 | ||
5058 | static void | |
5059 | start_noreorder (void) | |
5060 | { | |
5061 | if (mips_opts.noreorder == 0) | |
5062 | { | |
5063 | unsigned int i; | |
5064 | int nops; | |
5065 | ||
5066 | /* None of the instructions before the .set noreorder can be moved. */ | |
5067 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
5068 | history[i].fixed_p = 1; | |
5069 | ||
5070 | /* Insert any nops that might be needed between the .set noreorder | |
5071 | block and the previous instructions. We will later remove any | |
5072 | nops that turn out not to be needed. */ | |
932d1a1b | 5073 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
5074 | if (nops > 0) |
5075 | { | |
5076 | if (mips_optimize != 0) | |
252b5132 RH |
5077 | { |
5078 | /* Record the frag which holds the nop instructions, so | |
5079 | that we can remove them if we don't need them. */ | |
df58fc94 | 5080 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
5081 | prev_nop_frag = frag_now; |
5082 | prev_nop_frag_holds = nops; | |
5083 | prev_nop_frag_required = 0; | |
5084 | prev_nop_frag_since = 0; | |
5085 | } | |
5086 | ||
5087 | for (; nops > 0; --nops) | |
1e915849 | 5088 | add_fixed_insn (NOP_INSN); |
252b5132 | 5089 | |
7d10b47d RS |
5090 | /* Move on to a new frag, so that it is safe to simply |
5091 | decrease the size of prev_nop_frag. */ | |
5092 | frag_wane (frag_now); | |
5093 | frag_new (0); | |
462427c4 | 5094 | mips_move_text_labels (); |
252b5132 | 5095 | } |
df58fc94 | 5096 | mips_mark_labels (); |
7d10b47d | 5097 | mips_clear_insn_labels (); |
252b5132 | 5098 | } |
7d10b47d RS |
5099 | mips_opts.noreorder++; |
5100 | mips_any_noreorder = 1; | |
5101 | } | |
252b5132 | 5102 | |
7d10b47d | 5103 | /* End a nested noreorder block. */ |
252b5132 | 5104 | |
7d10b47d RS |
5105 | static void |
5106 | end_noreorder (void) | |
5107 | { | |
5108 | mips_opts.noreorder--; | |
5109 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
5110 | { | |
5111 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
5112 | handling nop insertion the .set reorder way. */ | |
5113 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 5114 | * NOP_INSN_SIZE); |
7d10b47d RS |
5115 | insert_into_history (prev_nop_frag_since, |
5116 | prev_nop_frag_required, NOP_INSN); | |
5117 | prev_nop_frag = NULL; | |
5118 | } | |
252b5132 RH |
5119 | } |
5120 | ||
584892a6 RS |
5121 | /* Set up global variables for the start of a new macro. */ |
5122 | ||
5123 | static void | |
5124 | macro_start (void) | |
5125 | { | |
5126 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
5127 | memset (&mips_macro_warning.first_insn_sizes, 0, |
5128 | sizeof (mips_macro_warning.first_insn_sizes)); | |
5129 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 5130 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 5131 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
5132 | switch (history[0].insn_mo->pinfo2 |
5133 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
5134 | { | |
5135 | case INSN2_BRANCH_DELAY_32BIT: | |
5136 | mips_macro_warning.delay_slot_length = 4; | |
5137 | break; | |
5138 | case INSN2_BRANCH_DELAY_16BIT: | |
5139 | mips_macro_warning.delay_slot_length = 2; | |
5140 | break; | |
5141 | default: | |
5142 | mips_macro_warning.delay_slot_length = 0; | |
5143 | break; | |
5144 | } | |
5145 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
5146 | } |
5147 | ||
df58fc94 RS |
5148 | /* Given that a macro is longer than one instruction or of the wrong size, |
5149 | return the appropriate warning for it. Return null if no warning is | |
5150 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
5151 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
5152 | and RELAX_NOMACRO. */ | |
584892a6 RS |
5153 | |
5154 | static const char * | |
5155 | macro_warning (relax_substateT subtype) | |
5156 | { | |
5157 | if (subtype & RELAX_DELAY_SLOT) | |
5158 | return _("Macro instruction expanded into multiple instructions" | |
5159 | " in a branch delay slot"); | |
5160 | else if (subtype & RELAX_NOMACRO) | |
5161 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
5162 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
5163 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
5164 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
5165 | ? _("Macro instruction expanded into a wrong size instruction" | |
5166 | " in a 16-bit branch delay slot") | |
5167 | : _("Macro instruction expanded into a wrong size instruction" | |
5168 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
5169 | else |
5170 | return 0; | |
5171 | } | |
5172 | ||
5173 | /* Finish up a macro. Emit warnings as appropriate. */ | |
5174 | ||
5175 | static void | |
5176 | macro_end (void) | |
5177 | { | |
df58fc94 RS |
5178 | /* Relaxation warning flags. */ |
5179 | relax_substateT subtype = 0; | |
5180 | ||
5181 | /* Check delay slot size requirements. */ | |
5182 | if (mips_macro_warning.delay_slot_length == 2) | |
5183 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
5184 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 5185 | { |
df58fc94 RS |
5186 | if (mips_macro_warning.delay_slot_length |
5187 | != mips_macro_warning.first_insn_sizes[0]) | |
5188 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
5189 | if (mips_macro_warning.delay_slot_length | |
5190 | != mips_macro_warning.first_insn_sizes[1]) | |
5191 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
5192 | } | |
584892a6 | 5193 | |
df58fc94 RS |
5194 | /* Check instruction count requirements. */ |
5195 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
5196 | { | |
5197 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
5198 | subtype |= RELAX_SECOND_LONGER; |
5199 | if (mips_opts.warn_about_macros) | |
5200 | subtype |= RELAX_NOMACRO; | |
5201 | if (mips_macro_warning.delay_slot_p) | |
5202 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 5203 | } |
584892a6 | 5204 | |
df58fc94 RS |
5205 | /* If both alternatives fail to fill a delay slot correctly, |
5206 | emit the warning now. */ | |
5207 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
5208 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
5209 | { | |
5210 | relax_substateT s; | |
5211 | const char *msg; | |
5212 | ||
5213 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
5214 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
5215 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
5216 | msg = macro_warning (s); | |
5217 | if (msg != NULL) | |
5218 | as_warn ("%s", msg); | |
5219 | subtype &= ~s; | |
5220 | } | |
5221 | ||
5222 | /* If both implementations are longer than 1 instruction, then emit the | |
5223 | warning now. */ | |
5224 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
5225 | { | |
5226 | relax_substateT s; | |
5227 | const char *msg; | |
5228 | ||
5229 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
5230 | msg = macro_warning (s); | |
5231 | if (msg != NULL) | |
5232 | as_warn ("%s", msg); | |
5233 | subtype &= ~s; | |
584892a6 | 5234 | } |
df58fc94 RS |
5235 | |
5236 | /* If any flags still set, then one implementation might need a warning | |
5237 | and the other either will need one of a different kind or none at all. | |
5238 | Pass any remaining flags over to relaxation. */ | |
5239 | if (mips_macro_warning.first_frag != NULL) | |
5240 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
5241 | } |
5242 | ||
df58fc94 RS |
5243 | /* Instruction operand formats used in macros that vary between |
5244 | standard MIPS and microMIPS code. */ | |
5245 | ||
833794fc | 5246 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
5247 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
5248 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
5249 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
5250 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 5251 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
5252 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
5253 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
5254 | ||
833794fc | 5255 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
5256 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) |
5257 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
5258 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
5259 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
833794fc | 5260 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
5261 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
5262 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
5263 | ||
6e1304d8 RS |
5264 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
5265 | The first argument in *ARGS will be either the code for a single | |
5266 | relocation or -1 followed by the three codes that make up a | |
5267 | composite relocation. */ | |
5268 | ||
5269 | static void | |
5270 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
5271 | { | |
5272 | int i, next; | |
5273 | ||
5274 | next = va_arg (*args, int); | |
5275 | if (next >= 0) | |
5276 | r[0] = (bfd_reloc_code_real_type) next; | |
5277 | else | |
f2ae14a1 RS |
5278 | { |
5279 | for (i = 0; i < 3; i++) | |
5280 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
5281 | /* This function is only used for 16-bit relocation fields. | |
5282 | To make the macro code simpler, treat an unrelocated value | |
5283 | in the same way as BFD_RELOC_LO16. */ | |
5284 | if (r[0] == BFD_RELOC_UNUSED) | |
5285 | r[0] = BFD_RELOC_LO16; | |
5286 | } | |
6e1304d8 RS |
5287 | } |
5288 | ||
252b5132 RH |
5289 | /* Build an instruction created by a macro expansion. This is passed |
5290 | a pointer to the count of instructions created so far, an | |
5291 | expression, the name of the instruction to build, an operand format | |
5292 | string, and corresponding arguments. */ | |
5293 | ||
252b5132 | 5294 | static void |
67c0d1eb | 5295 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 5296 | { |
df58fc94 | 5297 | const struct mips_opcode *mo = NULL; |
f6688943 | 5298 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
5299 | const struct mips_opcode *amo; |
5300 | struct hash_control *hash; | |
5301 | struct mips_cl_insn insn; | |
252b5132 | 5302 | va_list args; |
252b5132 | 5303 | |
252b5132 | 5304 | va_start (args, fmt); |
252b5132 | 5305 | |
252b5132 RH |
5306 | if (mips_opts.mips16) |
5307 | { | |
03ea81db | 5308 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
5309 | va_end (args); |
5310 | return; | |
5311 | } | |
5312 | ||
f6688943 TS |
5313 | r[0] = BFD_RELOC_UNUSED; |
5314 | r[1] = BFD_RELOC_UNUSED; | |
5315 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
5316 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
5317 | amo = (struct mips_opcode *) hash_find (hash, name); | |
5318 | gas_assert (amo); | |
5319 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 5320 | |
df58fc94 | 5321 | do |
8b082fb1 TS |
5322 | { |
5323 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
5324 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
5325 | We try to match an instruction that fulfils the branch delay | |
5326 | slot instruction length requirement (if any) of the previous | |
5327 | instruction. While doing this we record the first instruction | |
5328 | seen that matches all the other conditions and use it anyway | |
5329 | if the requirement cannot be met; we will issue an appropriate | |
5330 | warning later on. */ | |
5331 | if (strcmp (fmt, amo->args) == 0 | |
5332 | && amo->pinfo != INSN_MACRO | |
5333 | && is_opcode_valid (amo) | |
5334 | && is_size_valid (amo)) | |
5335 | { | |
5336 | if (is_delay_slot_valid (amo)) | |
5337 | { | |
5338 | mo = amo; | |
5339 | break; | |
5340 | } | |
5341 | else if (!mo) | |
5342 | mo = amo; | |
5343 | } | |
8b082fb1 | 5344 | |
df58fc94 RS |
5345 | ++amo; |
5346 | gas_assert (amo->name); | |
252b5132 | 5347 | } |
df58fc94 | 5348 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5349 | |
df58fc94 | 5350 | gas_assert (mo); |
1e915849 | 5351 | create_insn (&insn, mo); |
252b5132 RH |
5352 | for (;;) |
5353 | { | |
5354 | switch (*fmt++) | |
5355 | { | |
5356 | case '\0': | |
5357 | break; | |
5358 | ||
5359 | case ',': | |
5360 | case '(': | |
5361 | case ')': | |
5362 | continue; | |
5363 | ||
5f74bc13 CD |
5364 | case '+': |
5365 | switch (*fmt++) | |
5366 | { | |
5367 | case 'A': | |
5368 | case 'E': | |
df58fc94 RS |
5369 | INSERT_OPERAND (mips_opts.micromips, |
5370 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5371 | continue; |
5372 | ||
5373 | case 'B': | |
5374 | case 'F': | |
5375 | /* Note that in the macro case, these arguments are already | |
5376 | in MSB form. (When handling the instruction in the | |
5377 | non-macro case, these arguments are sizes from which | |
5378 | MSB values must be calculated.) */ | |
df58fc94 RS |
5379 | INSERT_OPERAND (mips_opts.micromips, |
5380 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5381 | continue; |
5382 | ||
b015e599 AP |
5383 | case 'J': |
5384 | gas_assert (!mips_opts.micromips); | |
5385 | INSERT_OPERAND (0, CODE10, insn, va_arg (args, int)); | |
5386 | continue; | |
5387 | ||
5f74bc13 CD |
5388 | case 'C': |
5389 | case 'G': | |
5390 | case 'H': | |
5391 | /* Note that in the macro case, these arguments are already | |
5392 | in MSBD form. (When handling the instruction in the | |
5393 | non-macro case, these arguments are sizes from which | |
5394 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5395 | INSERT_OPERAND (mips_opts.micromips, |
5396 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5397 | continue; |
5398 | ||
dd3cbb7e | 5399 | case 'Q': |
df58fc94 RS |
5400 | gas_assert (!mips_opts.micromips); |
5401 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5402 | continue; |
5403 | ||
7f3c4072 CM |
5404 | case 'j': |
5405 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int)); | |
5406 | continue; | |
5407 | ||
5f74bc13 | 5408 | default: |
b37df7c4 | 5409 | abort (); |
5f74bc13 CD |
5410 | } |
5411 | continue; | |
5412 | ||
8b082fb1 | 5413 | case '2': |
03f66e8a | 5414 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5415 | continue; |
5416 | ||
df58fc94 RS |
5417 | case 'n': |
5418 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5419 | case 't': |
5420 | case 'w': | |
5421 | case 'E': | |
df58fc94 | 5422 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5423 | continue; |
5424 | ||
5425 | case 'c': | |
833794fc | 5426 | INSERT_OPERAND (mips_opts.micromips, CODE, insn, va_arg (args, int)); |
38487616 TS |
5427 | continue; |
5428 | ||
252b5132 | 5429 | case 'W': |
df58fc94 RS |
5430 | gas_assert (!mips_opts.micromips); |
5431 | case 'T': | |
5432 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5433 | continue; |
5434 | ||
252b5132 | 5435 | case 'G': |
df58fc94 RS |
5436 | if (mips_opts.micromips) |
5437 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5438 | else | |
5439 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5440 | continue; | |
5441 | ||
af7ee8bf | 5442 | case 'K': |
df58fc94 RS |
5443 | gas_assert (!mips_opts.micromips); |
5444 | case 'd': | |
5445 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5446 | continue; |
5447 | ||
4372b673 | 5448 | case 'U': |
df58fc94 | 5449 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5450 | { |
5451 | int tmp = va_arg (args, int); | |
5452 | ||
df58fc94 RS |
5453 | INSERT_OPERAND (0, RT, insn, tmp); |
5454 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5455 | } |
df58fc94 | 5456 | continue; |
4372b673 | 5457 | |
252b5132 RH |
5458 | case 'V': |
5459 | case 'S': | |
df58fc94 RS |
5460 | gas_assert (!mips_opts.micromips); |
5461 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5462 | continue; |
5463 | ||
5464 | case 'z': | |
5465 | continue; | |
5466 | ||
5467 | case '<': | |
df58fc94 RS |
5468 | INSERT_OPERAND (mips_opts.micromips, |
5469 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5470 | continue; |
5471 | ||
5472 | case 'D': | |
df58fc94 RS |
5473 | gas_assert (!mips_opts.micromips); |
5474 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5475 | continue; |
5476 | ||
5477 | case 'B': | |
df58fc94 RS |
5478 | gas_assert (!mips_opts.micromips); |
5479 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5480 | continue; |
5481 | ||
4372b673 | 5482 | case 'J': |
df58fc94 RS |
5483 | gas_assert (!mips_opts.micromips); |
5484 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5485 | continue; |
5486 | ||
252b5132 | 5487 | case 'q': |
df58fc94 RS |
5488 | gas_assert (!mips_opts.micromips); |
5489 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5490 | continue; |
5491 | ||
5492 | case 'b': | |
5493 | case 's': | |
5494 | case 'r': | |
5495 | case 'v': | |
df58fc94 | 5496 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5497 | continue; |
5498 | ||
5499 | case 'i': | |
5500 | case 'j': | |
6e1304d8 | 5501 | macro_read_relocs (&args, r); |
9c2799c2 | 5502 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5503 | || *r == BFD_RELOC_MIPS_HIGHER |
5504 | || *r == BFD_RELOC_HI16_S | |
5505 | || *r == BFD_RELOC_LO16 | |
5506 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5507 | continue; | |
5508 | ||
5509 | case 'o': | |
5510 | macro_read_relocs (&args, r); | |
252b5132 RH |
5511 | continue; |
5512 | ||
5513 | case 'u': | |
6e1304d8 | 5514 | macro_read_relocs (&args, r); |
9c2799c2 | 5515 | gas_assert (ep != NULL |
90ecf173 MR |
5516 | && (ep->X_op == O_constant |
5517 | || (ep->X_op == O_symbol | |
5518 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5519 | || *r == BFD_RELOC_HI16_S | |
5520 | || *r == BFD_RELOC_HI16 | |
5521 | || *r == BFD_RELOC_GPREL16 | |
5522 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5523 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5524 | continue; |
5525 | ||
5526 | case 'p': | |
9c2799c2 | 5527 | gas_assert (ep != NULL); |
bad36eac | 5528 | |
252b5132 RH |
5529 | /* |
5530 | * This allows macro() to pass an immediate expression for | |
5531 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5532 | * |
5533 | * We don't allow branch relaxation for these branches, as | |
5534 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5535 | */ |
5536 | if (ep->X_op == O_constant) | |
5537 | { | |
df58fc94 RS |
5538 | /* For microMIPS we always use relocations for branches. |
5539 | So we should not resolve immediate values. */ | |
5540 | gas_assert (!mips_opts.micromips); | |
5541 | ||
bad36eac DJ |
5542 | if ((ep->X_add_number & 3) != 0) |
5543 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5544 | (unsigned long) ep->X_add_number); | |
5545 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5546 | as_bad (_("branch address range overflow (0x%lx)"), | |
5547 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5548 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5549 | ep = NULL; | |
5550 | } | |
5551 | else | |
0b25d3e6 | 5552 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5553 | continue; |
5554 | ||
5555 | case 'a': | |
9c2799c2 | 5556 | gas_assert (ep != NULL); |
f6688943 | 5557 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5558 | continue; |
5559 | ||
5560 | case 'C': | |
df58fc94 | 5561 | gas_assert (!mips_opts.micromips); |
c8276761 | 5562 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, int)); |
252b5132 RH |
5563 | continue; |
5564 | ||
d43b4baf | 5565 | case 'k': |
df58fc94 | 5566 | INSERT_OPERAND (mips_opts.micromips, |
c8276761 | 5567 | CACHE, insn, va_arg (args, int)); |
df58fc94 RS |
5568 | continue; |
5569 | ||
5570 | case '|': | |
5571 | gas_assert (mips_opts.micromips); | |
5572 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5573 | continue; | |
5574 | ||
5575 | case '.': | |
5576 | gas_assert (mips_opts.micromips); | |
5577 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5578 | continue; | |
5579 | ||
dec0624d MR |
5580 | case '\\': |
5581 | INSERT_OPERAND (mips_opts.micromips, | |
c8276761 | 5582 | 3BITPOS, insn, va_arg (args, int)); |
dec0624d MR |
5583 | continue; |
5584 | ||
df58fc94 | 5585 | case '~': |
dec0624d | 5586 | INSERT_OPERAND (mips_opts.micromips, |
c8276761 | 5587 | OFFSET12, insn, va_arg (args, int)); |
df58fc94 RS |
5588 | continue; |
5589 | ||
5590 | case 'N': | |
5591 | gas_assert (mips_opts.micromips); | |
5592 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5593 | continue; | |
5594 | ||
5595 | case 'm': /* Opcode extension character. */ | |
5596 | gas_assert (mips_opts.micromips); | |
5597 | switch (*fmt++) | |
5598 | { | |
5599 | case 'j': | |
5600 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5601 | break; | |
5602 | ||
5603 | case 'p': | |
5604 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5605 | break; | |
5606 | ||
5607 | case 'F': | |
5608 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5609 | break; | |
5610 | ||
5611 | default: | |
b37df7c4 | 5612 | abort (); |
df58fc94 | 5613 | } |
d43b4baf TS |
5614 | continue; |
5615 | ||
252b5132 | 5616 | default: |
b37df7c4 | 5617 | abort (); |
252b5132 RH |
5618 | } |
5619 | break; | |
5620 | } | |
5621 | va_end (args); | |
9c2799c2 | 5622 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5623 | |
df58fc94 | 5624 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5625 | } |
5626 | ||
5627 | static void | |
67c0d1eb | 5628 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5629 | va_list *args) |
252b5132 | 5630 | { |
1e915849 | 5631 | struct mips_opcode *mo; |
252b5132 | 5632 | struct mips_cl_insn insn; |
f6688943 TS |
5633 | bfd_reloc_code_real_type r[3] |
5634 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5635 | |
1e915849 | 5636 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5637 | gas_assert (mo); |
5638 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5639 | |
1e915849 | 5640 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5641 | { |
1e915849 | 5642 | ++mo; |
9c2799c2 NC |
5643 | gas_assert (mo->name); |
5644 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5645 | } |
5646 | ||
1e915849 | 5647 | create_insn (&insn, mo); |
252b5132 RH |
5648 | for (;;) |
5649 | { | |
5650 | int c; | |
5651 | ||
5652 | c = *fmt++; | |
5653 | switch (c) | |
5654 | { | |
5655 | case '\0': | |
5656 | break; | |
5657 | ||
5658 | case ',': | |
5659 | case '(': | |
5660 | case ')': | |
5661 | continue; | |
5662 | ||
5663 | case 'y': | |
5664 | case 'w': | |
03ea81db | 5665 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5666 | continue; |
5667 | ||
5668 | case 'x': | |
5669 | case 'v': | |
03ea81db | 5670 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5671 | continue; |
5672 | ||
5673 | case 'z': | |
03ea81db | 5674 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5675 | continue; |
5676 | ||
5677 | case 'Z': | |
03ea81db | 5678 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5679 | continue; |
5680 | ||
5681 | case '0': | |
5682 | case 'S': | |
5683 | case 'P': | |
5684 | case 'R': | |
5685 | continue; | |
5686 | ||
5687 | case 'X': | |
03ea81db | 5688 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 | 5689 | continue; |
252b5132 RH |
5690 | |
5691 | case '<': | |
5692 | case '>': | |
5693 | case '4': | |
5694 | case '5': | |
5695 | case 'H': | |
5696 | case 'W': | |
5697 | case 'D': | |
5698 | case 'j': | |
5699 | case '8': | |
5700 | case 'V': | |
5701 | case 'C': | |
5702 | case 'U': | |
5703 | case 'k': | |
5704 | case 'K': | |
5705 | case 'p': | |
5706 | case 'q': | |
5707 | { | |
b886a2ab RS |
5708 | offsetT value; |
5709 | ||
9c2799c2 | 5710 | gas_assert (ep != NULL); |
252b5132 RH |
5711 | |
5712 | if (ep->X_op != O_constant) | |
874e8986 | 5713 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5714 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5715 | { |
b886a2ab | 5716 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5717 | ep = NULL; |
f6688943 | 5718 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5719 | } |
5720 | } | |
5721 | continue; | |
5722 | ||
5723 | case '6': | |
03ea81db | 5724 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5725 | continue; |
5726 | } | |
5727 | ||
5728 | break; | |
5729 | } | |
5730 | ||
9c2799c2 | 5731 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5732 | |
df58fc94 | 5733 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5734 | } |
5735 | ||
2051e8c4 MR |
5736 | /* |
5737 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5738 | * higher bits unset. | |
5739 | */ | |
9f872bbe | 5740 | static void |
2051e8c4 MR |
5741 | normalize_constant_expr (expressionS *ex) |
5742 | { | |
9ee2a2d4 | 5743 | if (ex->X_op == O_constant |
2051e8c4 MR |
5744 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5745 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5746 | - 0x80000000); | |
5747 | } | |
5748 | ||
5749 | /* | |
5750 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5751 | * all higher bits unset. | |
5752 | */ | |
5753 | static void | |
5754 | normalize_address_expr (expressionS *ex) | |
5755 | { | |
5756 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5757 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5758 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5759 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5760 | - 0x80000000); | |
5761 | } | |
5762 | ||
438c16b8 TS |
5763 | /* |
5764 | * Generate a "jalr" instruction with a relocation hint to the called | |
5765 | * function. This occurs in NewABI PIC code. | |
5766 | */ | |
5767 | static void | |
df58fc94 | 5768 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5769 | { |
df58fc94 RS |
5770 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5771 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5772 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5773 | const char *jalr; | |
685736be | 5774 | char *f = NULL; |
b34976b6 | 5775 | |
1180b5a4 | 5776 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5777 | { |
cc3d92a5 | 5778 | frag_grow (8); |
f21f8242 AO |
5779 | f = frag_more (0); |
5780 | } | |
2906b037 | 5781 | if (mips_opts.micromips) |
df58fc94 | 5782 | { |
833794fc MR |
5783 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
5784 | ? "jalr" : "jalrs"); | |
e64af278 | 5785 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 5786 | || mips_opts.insn32 |
e64af278 | 5787 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
5788 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5789 | else | |
5790 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5791 | } | |
2906b037 MR |
5792 | else |
5793 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5794 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5795 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5796 | } |
5797 | ||
252b5132 RH |
5798 | /* |
5799 | * Generate a "lui" instruction. | |
5800 | */ | |
5801 | static void | |
67c0d1eb | 5802 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5803 | { |
9c2799c2 | 5804 | gas_assert (! mips_opts.mips16); |
252b5132 | 5805 | |
df58fc94 | 5806 | if (ep->X_op != O_constant) |
252b5132 | 5807 | { |
9c2799c2 | 5808 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5809 | /* _gp_disp is a special case, used from s_cpload. |
5810 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5811 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5812 | || (! HAVE_NEWABI |
aa6975fb ILT |
5813 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5814 | || (! mips_in_shared | |
bbe506e8 TS |
5815 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5816 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5817 | } |
5818 | ||
df58fc94 | 5819 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5820 | } |
5821 | ||
885add95 CD |
5822 | /* Generate a sequence of instructions to do a load or store from a constant |
5823 | offset off of a base register (breg) into/from a target register (treg), | |
5824 | using AT if necessary. */ | |
5825 | static void | |
67c0d1eb RS |
5826 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5827 | int treg, int breg, int dbl) | |
885add95 | 5828 | { |
9c2799c2 | 5829 | gas_assert (ep->X_op == O_constant); |
885add95 | 5830 | |
256ab948 | 5831 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5832 | if (!dbl) |
5833 | normalize_constant_expr (ep); | |
256ab948 | 5834 | |
67c1ffbe | 5835 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5836 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5837 | as_warn (_("operand overflow")); |
5838 | ||
5839 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5840 | { | |
5841 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5842 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5843 | } |
5844 | else | |
5845 | { | |
5846 | /* 32-bit offset, need multiple instructions and AT, like: | |
5847 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5848 | addu $tempreg,$tempreg,$breg | |
5849 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5850 | to handle the complete offset. */ | |
67c0d1eb RS |
5851 | macro_build_lui (ep, AT); |
5852 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5853 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5854 | |
741fe287 | 5855 | if (!mips_opts.at) |
8fc2e39e | 5856 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5857 | } |
5858 | } | |
5859 | ||
252b5132 RH |
5860 | /* set_at() |
5861 | * Generates code to set the $at register to true (one) | |
5862 | * if reg is less than the immediate expression. | |
5863 | */ | |
5864 | static void | |
67c0d1eb | 5865 | set_at (int reg, int unsignedp) |
252b5132 RH |
5866 | { |
5867 | if (imm_expr.X_op == O_constant | |
5868 | && imm_expr.X_add_number >= -0x8000 | |
5869 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5870 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5871 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5872 | else |
5873 | { | |
67c0d1eb RS |
5874 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5875 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5876 | } |
5877 | } | |
5878 | ||
5879 | /* Warn if an expression is not a constant. */ | |
5880 | ||
5881 | static void | |
17a2f251 | 5882 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5883 | { |
5884 | if (ex->X_op == O_big) | |
5885 | as_bad (_("unsupported large constant")); | |
5886 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5887 | as_bad (_("Instruction %s requires absolute expression"), |
5888 | ip->insn_mo->name); | |
13757d0c | 5889 | |
9ee2a2d4 MR |
5890 | if (HAVE_32BIT_GPRS) |
5891 | normalize_constant_expr (ex); | |
252b5132 RH |
5892 | } |
5893 | ||
5894 | /* Count the leading zeroes by performing a binary chop. This is a | |
5895 | bulky bit of source, but performance is a LOT better for the | |
5896 | majority of values than a simple loop to count the bits: | |
5897 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5898 | if ((v) & (1 << (31 - lcnt))) | |
5899 | break; | |
5900 | However it is not code size friendly, and the gain will drop a bit | |
5901 | on certain cached systems. | |
5902 | */ | |
5903 | #define COUNT_TOP_ZEROES(v) \ | |
5904 | (((v) & ~0xffff) == 0 \ | |
5905 | ? ((v) & ~0xff) == 0 \ | |
5906 | ? ((v) & ~0xf) == 0 \ | |
5907 | ? ((v) & ~0x3) == 0 \ | |
5908 | ? ((v) & ~0x1) == 0 \ | |
5909 | ? !(v) \ | |
5910 | ? 32 \ | |
5911 | : 31 \ | |
5912 | : 30 \ | |
5913 | : ((v) & ~0x7) == 0 \ | |
5914 | ? 29 \ | |
5915 | : 28 \ | |
5916 | : ((v) & ~0x3f) == 0 \ | |
5917 | ? ((v) & ~0x1f) == 0 \ | |
5918 | ? 27 \ | |
5919 | : 26 \ | |
5920 | : ((v) & ~0x7f) == 0 \ | |
5921 | ? 25 \ | |
5922 | : 24 \ | |
5923 | : ((v) & ~0xfff) == 0 \ | |
5924 | ? ((v) & ~0x3ff) == 0 \ | |
5925 | ? ((v) & ~0x1ff) == 0 \ | |
5926 | ? 23 \ | |
5927 | : 22 \ | |
5928 | : ((v) & ~0x7ff) == 0 \ | |
5929 | ? 21 \ | |
5930 | : 20 \ | |
5931 | : ((v) & ~0x3fff) == 0 \ | |
5932 | ? ((v) & ~0x1fff) == 0 \ | |
5933 | ? 19 \ | |
5934 | : 18 \ | |
5935 | : ((v) & ~0x7fff) == 0 \ | |
5936 | ? 17 \ | |
5937 | : 16 \ | |
5938 | : ((v) & ~0xffffff) == 0 \ | |
5939 | ? ((v) & ~0xfffff) == 0 \ | |
5940 | ? ((v) & ~0x3ffff) == 0 \ | |
5941 | ? ((v) & ~0x1ffff) == 0 \ | |
5942 | ? 15 \ | |
5943 | : 14 \ | |
5944 | : ((v) & ~0x7ffff) == 0 \ | |
5945 | ? 13 \ | |
5946 | : 12 \ | |
5947 | : ((v) & ~0x3fffff) == 0 \ | |
5948 | ? ((v) & ~0x1fffff) == 0 \ | |
5949 | ? 11 \ | |
5950 | : 10 \ | |
5951 | : ((v) & ~0x7fffff) == 0 \ | |
5952 | ? 9 \ | |
5953 | : 8 \ | |
5954 | : ((v) & ~0xfffffff) == 0 \ | |
5955 | ? ((v) & ~0x3ffffff) == 0 \ | |
5956 | ? ((v) & ~0x1ffffff) == 0 \ | |
5957 | ? 7 \ | |
5958 | : 6 \ | |
5959 | : ((v) & ~0x7ffffff) == 0 \ | |
5960 | ? 5 \ | |
5961 | : 4 \ | |
5962 | : ((v) & ~0x3fffffff) == 0 \ | |
5963 | ? ((v) & ~0x1fffffff) == 0 \ | |
5964 | ? 3 \ | |
5965 | : 2 \ | |
5966 | : ((v) & ~0x7fffffff) == 0 \ | |
5967 | ? 1 \ | |
5968 | : 0) | |
5969 | ||
5970 | /* load_register() | |
67c1ffbe | 5971 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5972 | * an absolute expression value into a register. |
5973 | */ | |
5974 | static void | |
67c0d1eb | 5975 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5976 | { |
5977 | int freg; | |
5978 | expressionS hi32, lo32; | |
5979 | ||
5980 | if (ep->X_op != O_big) | |
5981 | { | |
9c2799c2 | 5982 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5983 | |
5984 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5985 | if (!dbl) |
5986 | normalize_constant_expr (ep); | |
256ab948 TS |
5987 | |
5988 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5989 | { |
5990 | /* We can handle 16 bit signed values with an addiu to | |
5991 | $zero. No need to ever use daddiu here, since $zero and | |
5992 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5993 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5994 | return; |
5995 | } | |
5996 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5997 | { | |
5998 | /* We can handle 16 bit unsigned values with an ori to | |
5999 | $zero. */ | |
67c0d1eb | 6000 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
6001 | return; |
6002 | } | |
256ab948 | 6003 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
6004 | { |
6005 | /* 32 bit values require an lui. */ | |
df58fc94 | 6006 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 6007 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 6008 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
6009 | return; |
6010 | } | |
6011 | } | |
6012 | ||
6013 | /* The value is larger than 32 bits. */ | |
6014 | ||
2051e8c4 | 6015 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 6016 | { |
55e08f71 NC |
6017 | char value[32]; |
6018 | ||
6019 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 6020 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 6021 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
6022 | return; |
6023 | } | |
6024 | ||
6025 | if (ep->X_op != O_big) | |
6026 | { | |
6027 | hi32 = *ep; | |
6028 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6029 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6030 | hi32.X_add_number &= 0xffffffff; | |
6031 | lo32 = *ep; | |
6032 | lo32.X_add_number &= 0xffffffff; | |
6033 | } | |
6034 | else | |
6035 | { | |
9c2799c2 | 6036 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
6037 | if (ep->X_add_number == 3) |
6038 | generic_bignum[3] = 0; | |
6039 | else if (ep->X_add_number > 4) | |
6040 | as_bad (_("Number larger than 64 bits")); | |
6041 | lo32.X_op = O_constant; | |
6042 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
6043 | hi32.X_op = O_constant; | |
6044 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
6045 | } | |
6046 | ||
6047 | if (hi32.X_add_number == 0) | |
6048 | freg = 0; | |
6049 | else | |
6050 | { | |
6051 | int shift, bit; | |
6052 | unsigned long hi, lo; | |
6053 | ||
956cd1d6 | 6054 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
6055 | { |
6056 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
6057 | { | |
67c0d1eb | 6058 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
6059 | return; |
6060 | } | |
6061 | if (lo32.X_add_number & 0x80000000) | |
6062 | { | |
df58fc94 | 6063 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 6064 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 6065 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
6066 | return; |
6067 | } | |
6068 | } | |
252b5132 RH |
6069 | |
6070 | /* Check for 16bit shifted constant. We know that hi32 is | |
6071 | non-zero, so start the mask on the first bit of the hi32 | |
6072 | value. */ | |
6073 | shift = 17; | |
6074 | do | |
beae10d5 KH |
6075 | { |
6076 | unsigned long himask, lomask; | |
6077 | ||
6078 | if (shift < 32) | |
6079 | { | |
6080 | himask = 0xffff >> (32 - shift); | |
6081 | lomask = (0xffff << shift) & 0xffffffff; | |
6082 | } | |
6083 | else | |
6084 | { | |
6085 | himask = 0xffff << (shift - 32); | |
6086 | lomask = 0; | |
6087 | } | |
6088 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
6089 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
6090 | { | |
6091 | expressionS tmp; | |
6092 | ||
6093 | tmp.X_op = O_constant; | |
6094 | if (shift < 32) | |
6095 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
6096 | | (lo32.X_add_number >> shift)); | |
6097 | else | |
6098 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 6099 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 6100 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 6101 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
6102 | return; |
6103 | } | |
f9419b05 | 6104 | ++shift; |
beae10d5 KH |
6105 | } |
6106 | while (shift <= (64 - 16)); | |
252b5132 RH |
6107 | |
6108 | /* Find the bit number of the lowest one bit, and store the | |
6109 | shifted value in hi/lo. */ | |
6110 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
6111 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
6112 | if (lo != 0) | |
6113 | { | |
6114 | bit = 0; | |
6115 | while ((lo & 1) == 0) | |
6116 | { | |
6117 | lo >>= 1; | |
6118 | ++bit; | |
6119 | } | |
6120 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
6121 | hi >>= bit; | |
6122 | } | |
6123 | else | |
6124 | { | |
6125 | bit = 32; | |
6126 | while ((hi & 1) == 0) | |
6127 | { | |
6128 | hi >>= 1; | |
6129 | ++bit; | |
6130 | } | |
6131 | lo = hi; | |
6132 | hi = 0; | |
6133 | } | |
6134 | ||
6135 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
6136 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
6137 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
6138 | { |
6139 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 6140 | if (shift != 0) |
beae10d5 | 6141 | { |
252b5132 RH |
6142 | expressionS tmp; |
6143 | ||
6144 | /* This instruction will set the register to be all | |
6145 | ones. */ | |
beae10d5 KH |
6146 | tmp.X_op = O_constant; |
6147 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 6148 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
6149 | if (bit != 0) |
6150 | { | |
6151 | bit += shift; | |
df58fc94 | 6152 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 6153 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 6154 | } |
df58fc94 | 6155 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 6156 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
6157 | return; |
6158 | } | |
6159 | } | |
252b5132 RH |
6160 | |
6161 | /* Sign extend hi32 before calling load_register, because we can | |
6162 | generally get better code when we load a sign extended value. */ | |
6163 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 6164 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 6165 | load_register (reg, &hi32, 0); |
252b5132 RH |
6166 | freg = reg; |
6167 | } | |
6168 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
6169 | { | |
6170 | if (freg != 0) | |
6171 | { | |
df58fc94 | 6172 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
6173 | freg = reg; |
6174 | } | |
6175 | } | |
6176 | else | |
6177 | { | |
6178 | expressionS mid16; | |
6179 | ||
956cd1d6 | 6180 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 6181 | { |
df58fc94 RS |
6182 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
6183 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
6184 | return; |
6185 | } | |
252b5132 RH |
6186 | |
6187 | if (freg != 0) | |
6188 | { | |
df58fc94 | 6189 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
6190 | freg = reg; |
6191 | } | |
6192 | mid16 = lo32; | |
6193 | mid16.X_add_number >>= 16; | |
67c0d1eb | 6194 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 6195 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
6196 | freg = reg; |
6197 | } | |
6198 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 6199 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
6200 | } |
6201 | ||
269137b2 TS |
6202 | static inline void |
6203 | load_delay_nop (void) | |
6204 | { | |
6205 | if (!gpr_interlocks) | |
6206 | macro_build (NULL, "nop", ""); | |
6207 | } | |
6208 | ||
252b5132 RH |
6209 | /* Load an address into a register. */ |
6210 | ||
6211 | static void | |
67c0d1eb | 6212 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 6213 | { |
252b5132 RH |
6214 | if (ep->X_op != O_constant |
6215 | && ep->X_op != O_symbol) | |
6216 | { | |
6217 | as_bad (_("expression too complex")); | |
6218 | ep->X_op = O_constant; | |
6219 | } | |
6220 | ||
6221 | if (ep->X_op == O_constant) | |
6222 | { | |
67c0d1eb | 6223 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
6224 | return; |
6225 | } | |
6226 | ||
6227 | if (mips_pic == NO_PIC) | |
6228 | { | |
6229 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 6230 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
6231 | Otherwise we want |
6232 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
6233 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 6234 | If we have an addend, we always use the latter form. |
76b3015f | 6235 | |
d6bc6245 TS |
6236 | With 64bit address space and a usable $at we want |
6237 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6238 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6239 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6240 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
6241 | dsll32 $reg,0 | |
3a482fd5 | 6242 | daddu $reg,$reg,$at |
76b3015f | 6243 | |
c03099e6 | 6244 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
6245 | on superscalar processors. |
6246 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6247 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6248 | dsll $reg,16 | |
6249 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
6250 | dsll $reg,16 | |
6251 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
6252 | |
6253 | For GP relative symbols in 64bit address space we can use | |
6254 | the same sequence as in 32bit address space. */ | |
aed1a261 | 6255 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 6256 | { |
6caf9ef4 TS |
6257 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6258 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
6259 | { | |
6260 | relax_start (ep->X_add_symbol); | |
6261 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
6262 | mips_gp_register, BFD_RELOC_GPREL16); | |
6263 | relax_switch (); | |
6264 | } | |
d6bc6245 | 6265 | |
741fe287 | 6266 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 6267 | { |
df58fc94 RS |
6268 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
6269 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
6270 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6271 | BFD_RELOC_MIPS_HIGHER); | |
6272 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 6273 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 6274 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
6275 | *used_at = 1; |
6276 | } | |
6277 | else | |
6278 | { | |
df58fc94 | 6279 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
6280 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6281 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 6282 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6283 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 6284 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6285 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 6286 | } |
6caf9ef4 TS |
6287 | |
6288 | if (mips_relax.sequence) | |
6289 | relax_end (); | |
d6bc6245 | 6290 | } |
252b5132 RH |
6291 | else |
6292 | { | |
d6bc6245 | 6293 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6294 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 6295 | { |
4d7206a2 | 6296 | relax_start (ep->X_add_symbol); |
67c0d1eb | 6297 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 6298 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 6299 | relax_switch (); |
d6bc6245 | 6300 | } |
67c0d1eb RS |
6301 | macro_build_lui (ep, reg); |
6302 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
6303 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6304 | if (mips_relax.sequence) |
6305 | relax_end (); | |
d6bc6245 | 6306 | } |
252b5132 | 6307 | } |
0a44bf69 | 6308 | else if (!mips_big_got) |
252b5132 RH |
6309 | { |
6310 | expressionS ex; | |
6311 | ||
6312 | /* If this is a reference to an external symbol, we want | |
6313 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6314 | Otherwise we want | |
6315 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6316 | nop | |
6317 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
6318 | If there is a constant, it must be added in after. |
6319 | ||
ed6fb7bd | 6320 | If we have NewABI, we want |
f5040a92 AO |
6321 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
6322 | unless we're referencing a global symbol with a non-zero | |
6323 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
6324 | if (HAVE_NEWABI) |
6325 | { | |
f5040a92 AO |
6326 | if (ep->X_add_number) |
6327 | { | |
4d7206a2 | 6328 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6329 | ep->X_add_number = 0; |
4d7206a2 | 6330 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
6331 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6332 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6333 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6334 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6335 | ex.X_op = O_constant; | |
67c0d1eb | 6336 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6337 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6338 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 6339 | relax_switch (); |
f5040a92 | 6340 | } |
67c0d1eb | 6341 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6342 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
6343 | if (mips_relax.sequence) |
6344 | relax_end (); | |
ed6fb7bd SC |
6345 | } |
6346 | else | |
6347 | { | |
f5040a92 AO |
6348 | ex.X_add_number = ep->X_add_number; |
6349 | ep->X_add_number = 0; | |
67c0d1eb RS |
6350 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6351 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6352 | load_delay_nop (); |
4d7206a2 RS |
6353 | relax_start (ep->X_add_symbol); |
6354 | relax_switch (); | |
67c0d1eb | 6355 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6356 | BFD_RELOC_LO16); |
4d7206a2 | 6357 | relax_end (); |
ed6fb7bd | 6358 | |
f5040a92 AO |
6359 | if (ex.X_add_number != 0) |
6360 | { | |
6361 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6362 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6363 | ex.X_op = O_constant; | |
67c0d1eb | 6364 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6365 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6366 | } |
252b5132 RH |
6367 | } |
6368 | } | |
0a44bf69 | 6369 | else if (mips_big_got) |
252b5132 RH |
6370 | { |
6371 | expressionS ex; | |
252b5132 RH |
6372 | |
6373 | /* This is the large GOT case. If this is a reference to an | |
6374 | external symbol, we want | |
6375 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6376 | addu $reg,$reg,$gp | |
6377 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6378 | |
6379 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6380 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6381 | nop | |
6382 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6383 | If there is a constant, it must be added in after. |
f5040a92 AO |
6384 | |
6385 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6386 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6387 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6388 | */ |
438c16b8 TS |
6389 | if (HAVE_NEWABI) |
6390 | { | |
4d7206a2 | 6391 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6392 | ep->X_add_number = 0; |
4d7206a2 | 6393 | relax_start (ep->X_add_symbol); |
df58fc94 | 6394 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6395 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6396 | reg, reg, mips_gp_register); | |
6397 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6398 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6399 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6400 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6401 | else if (ex.X_add_number) | |
6402 | { | |
6403 | ex.X_op = O_constant; | |
67c0d1eb RS |
6404 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6405 | BFD_RELOC_LO16); | |
f5040a92 AO |
6406 | } |
6407 | ||
6408 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6409 | relax_switch (); |
67c0d1eb | 6410 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6411 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6412 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6413 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6414 | relax_end (); |
438c16b8 | 6415 | } |
252b5132 | 6416 | else |
438c16b8 | 6417 | { |
f5040a92 AO |
6418 | ex.X_add_number = ep->X_add_number; |
6419 | ep->X_add_number = 0; | |
4d7206a2 | 6420 | relax_start (ep->X_add_symbol); |
df58fc94 | 6421 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6422 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6423 | reg, reg, mips_gp_register); | |
6424 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6425 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6426 | relax_switch (); |
6427 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6428 | { |
6429 | /* We need a nop before loading from $gp. This special | |
6430 | check is required because the lui which starts the main | |
6431 | instruction stream does not refer to $gp, and so will not | |
6432 | insert the nop which may be required. */ | |
67c0d1eb | 6433 | macro_build (NULL, "nop", ""); |
438c16b8 | 6434 | } |
67c0d1eb | 6435 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6436 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6437 | load_delay_nop (); |
67c0d1eb | 6438 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6439 | BFD_RELOC_LO16); |
4d7206a2 | 6440 | relax_end (); |
438c16b8 | 6441 | |
f5040a92 AO |
6442 | if (ex.X_add_number != 0) |
6443 | { | |
6444 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6445 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6446 | ex.X_op = O_constant; | |
67c0d1eb RS |
6447 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6448 | BFD_RELOC_LO16); | |
f5040a92 | 6449 | } |
252b5132 RH |
6450 | } |
6451 | } | |
252b5132 RH |
6452 | else |
6453 | abort (); | |
8fc2e39e | 6454 | |
741fe287 | 6455 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6456 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6457 | } |
6458 | ||
ea1fb5dc RS |
6459 | /* Move the contents of register SOURCE into register DEST. */ |
6460 | ||
6461 | static void | |
67c0d1eb | 6462 | move_register (int dest, int source) |
ea1fb5dc | 6463 | { |
df58fc94 RS |
6464 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6465 | instruction specifically requires a 32-bit one. */ | |
6466 | if (mips_opts.micromips | |
833794fc | 6467 | && !mips_opts.insn32 |
df58fc94 | 6468 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 6469 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6470 | else |
6471 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6472 | dest, source, 0); | |
ea1fb5dc RS |
6473 | } |
6474 | ||
4d7206a2 | 6475 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6476 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6477 | The two alternatives are: | |
4d7206a2 RS |
6478 | |
6479 | Global symbol Local sybmol | |
6480 | ------------- ------------ | |
6481 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6482 | ... ... | |
6483 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6484 | ||
6485 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6486 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6487 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6488 | |
6489 | static void | |
67c0d1eb | 6490 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6491 | { |
6492 | expressionS global; | |
6493 | ||
6494 | global = *local; | |
6495 | global.X_add_number = 0; | |
6496 | ||
6497 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6498 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6499 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6500 | relax_switch (); |
67c0d1eb RS |
6501 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6502 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6503 | relax_end (); |
6504 | } | |
6505 | ||
6506 | static void | |
67c0d1eb | 6507 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6508 | { |
6509 | expressionS global; | |
6510 | ||
6511 | global.X_op = O_constant; | |
6512 | global.X_op_symbol = NULL; | |
6513 | global.X_add_symbol = NULL; | |
6514 | global.X_add_number = local->X_add_number; | |
6515 | ||
6516 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6517 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6518 | dest, dest, BFD_RELOC_LO16); |
6519 | relax_switch (); | |
67c0d1eb | 6520 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6521 | relax_end (); |
6522 | } | |
6523 | ||
f6a22291 MR |
6524 | static void |
6525 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6526 | { | |
6527 | expressionS global; | |
6528 | int hold_mips_optimize; | |
6529 | ||
6530 | global.X_op = O_constant; | |
6531 | global.X_op_symbol = NULL; | |
6532 | global.X_add_symbol = NULL; | |
6533 | global.X_add_number = local->X_add_number; | |
6534 | ||
6535 | relax_start (local->X_add_symbol); | |
6536 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6537 | relax_switch (); | |
6538 | /* Set mips_optimize around the lui instruction to avoid | |
6539 | inserting an unnecessary nop after the lw. */ | |
6540 | hold_mips_optimize = mips_optimize; | |
6541 | mips_optimize = 2; | |
6542 | macro_build_lui (&global, tmp); | |
6543 | mips_optimize = hold_mips_optimize; | |
6544 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6545 | relax_end (); | |
6546 | ||
6547 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6548 | } | |
6549 | ||
df58fc94 RS |
6550 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6551 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6552 | is its complementing branch with the original condition negated. | |
6553 | CALL is set if the original branch specified the link operation. | |
6554 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6555 | ||
6556 | Code like this is produced in the noreorder mode: | |
6557 | ||
6558 | BRNEG <args>, 1f | |
6559 | nop | |
6560 | b <sym> | |
6561 | delay slot (executed only if branch taken) | |
6562 | 1: | |
6563 | ||
6564 | or, if CALL is set: | |
6565 | ||
6566 | BRNEG <args>, 1f | |
6567 | nop | |
6568 | bal <sym> | |
6569 | delay slot (executed only if branch taken) | |
6570 | 1: | |
6571 | ||
6572 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6573 | so code produced is simply: | |
6574 | ||
6575 | BR <args>, <sym> | |
6576 | nop | |
6577 | ||
6578 | This function is used when producing code for the microMIPS ASE that | |
6579 | does not implement branch likely instructions in hardware. */ | |
6580 | ||
6581 | static void | |
6582 | macro_build_branch_likely (const char *br, const char *brneg, | |
6583 | int call, expressionS *ep, const char *fmt, | |
6584 | unsigned int sreg, unsigned int treg) | |
6585 | { | |
6586 | int noreorder = mips_opts.noreorder; | |
6587 | expressionS expr1; | |
6588 | ||
6589 | gas_assert (mips_opts.micromips); | |
6590 | start_noreorder (); | |
6591 | if (noreorder) | |
6592 | { | |
6593 | micromips_label_expr (&expr1); | |
6594 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6595 | macro_build (NULL, "nop", ""); | |
6596 | macro_build (ep, call ? "bal" : "b", "p"); | |
6597 | ||
6598 | /* Set to true so that append_insn adds a label. */ | |
6599 | emit_branch_likely_macro = TRUE; | |
6600 | } | |
6601 | else | |
6602 | { | |
6603 | macro_build (ep, br, fmt, sreg, treg); | |
6604 | macro_build (NULL, "nop", ""); | |
6605 | } | |
6606 | end_noreorder (); | |
6607 | } | |
6608 | ||
6609 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6610 | the condition code tested. EP specifies the branch target. */ | |
6611 | ||
6612 | static void | |
6613 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6614 | { | |
6615 | const int call = 0; | |
6616 | const char *brneg; | |
6617 | const char *br; | |
6618 | ||
6619 | switch (type) | |
6620 | { | |
6621 | case M_BC1FL: | |
6622 | br = "bc1f"; | |
6623 | brneg = "bc1t"; | |
6624 | break; | |
6625 | case M_BC1TL: | |
6626 | br = "bc1t"; | |
6627 | brneg = "bc1f"; | |
6628 | break; | |
6629 | case M_BC2FL: | |
6630 | br = "bc2f"; | |
6631 | brneg = "bc2t"; | |
6632 | break; | |
6633 | case M_BC2TL: | |
6634 | br = "bc2t"; | |
6635 | brneg = "bc2f"; | |
6636 | break; | |
6637 | default: | |
6638 | abort (); | |
6639 | } | |
6640 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6641 | } | |
6642 | ||
6643 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6644 | the register tested. EP specifies the branch target. */ | |
6645 | ||
6646 | static void | |
6647 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6648 | { | |
6649 | const char *brneg = NULL; | |
6650 | const char *br; | |
6651 | int call = 0; | |
6652 | ||
6653 | switch (type) | |
6654 | { | |
6655 | case M_BGEZ: | |
6656 | br = "bgez"; | |
6657 | break; | |
6658 | case M_BGEZL: | |
6659 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6660 | brneg = "bltz"; | |
6661 | break; | |
6662 | case M_BGEZALL: | |
6663 | gas_assert (mips_opts.micromips); | |
833794fc | 6664 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
6665 | brneg = "bltz"; |
6666 | call = 1; | |
6667 | break; | |
6668 | case M_BGTZ: | |
6669 | br = "bgtz"; | |
6670 | break; | |
6671 | case M_BGTZL: | |
6672 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6673 | brneg = "blez"; | |
6674 | break; | |
6675 | case M_BLEZ: | |
6676 | br = "blez"; | |
6677 | break; | |
6678 | case M_BLEZL: | |
6679 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6680 | brneg = "bgtz"; | |
6681 | break; | |
6682 | case M_BLTZ: | |
6683 | br = "bltz"; | |
6684 | break; | |
6685 | case M_BLTZL: | |
6686 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6687 | brneg = "bgez"; | |
6688 | break; | |
6689 | case M_BLTZALL: | |
6690 | gas_assert (mips_opts.micromips); | |
833794fc | 6691 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
6692 | brneg = "bgez"; |
6693 | call = 1; | |
6694 | break; | |
6695 | default: | |
6696 | abort (); | |
6697 | } | |
6698 | if (mips_opts.micromips && brneg) | |
6699 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6700 | else | |
6701 | macro_build (ep, br, "s,p", sreg); | |
6702 | } | |
6703 | ||
6704 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6705 | TREG as the registers tested. EP specifies the branch target. */ | |
6706 | ||
6707 | static void | |
6708 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6709 | unsigned int sreg, unsigned int treg) | |
6710 | { | |
6711 | const char *brneg = NULL; | |
6712 | const int call = 0; | |
6713 | const char *br; | |
6714 | ||
6715 | switch (type) | |
6716 | { | |
6717 | case M_BEQ: | |
6718 | case M_BEQ_I: | |
6719 | br = "beq"; | |
6720 | break; | |
6721 | case M_BEQL: | |
6722 | case M_BEQL_I: | |
6723 | br = mips_opts.micromips ? "beq" : "beql"; | |
6724 | brneg = "bne"; | |
6725 | break; | |
6726 | case M_BNE: | |
6727 | case M_BNE_I: | |
6728 | br = "bne"; | |
6729 | break; | |
6730 | case M_BNEL: | |
6731 | case M_BNEL_I: | |
6732 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6733 | brneg = "beq"; | |
6734 | break; | |
6735 | default: | |
6736 | abort (); | |
6737 | } | |
6738 | if (mips_opts.micromips && brneg) | |
6739 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6740 | else | |
6741 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6742 | } | |
6743 | ||
f2ae14a1 RS |
6744 | /* Return the high part that should be loaded in order to make the low |
6745 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
6746 | ||
6747 | static offsetT | |
6748 | offset_high_part (offsetT value, unsigned int offbits) | |
6749 | { | |
6750 | offsetT bias; | |
6751 | addressT low_mask; | |
6752 | ||
6753 | if (offbits == 0) | |
6754 | return value; | |
6755 | bias = 1 << (offbits - 1); | |
6756 | low_mask = bias * 2 - 1; | |
6757 | return (value + bias) & ~low_mask; | |
6758 | } | |
6759 | ||
6760 | /* Return true if the value stored in offset_expr and offset_reloc | |
6761 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
6762 | amount that the caller wants to add without inducing overflow | |
6763 | and ALIGN is the known alignment of the value in bytes. */ | |
6764 | ||
6765 | static bfd_boolean | |
6766 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
6767 | { | |
6768 | if (offbits == 16) | |
6769 | { | |
6770 | /* Accept any relocation operator if overflow isn't a concern. */ | |
6771 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
6772 | return TRUE; | |
6773 | ||
6774 | /* These relocations are guaranteed not to overflow in correct links. */ | |
6775 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
6776 | || gprel16_reloc_p (*offset_reloc)) | |
6777 | return TRUE; | |
6778 | } | |
6779 | if (offset_expr.X_op == O_constant | |
6780 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
6781 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
6782 | return TRUE; | |
6783 | return FALSE; | |
6784 | } | |
6785 | ||
252b5132 RH |
6786 | /* |
6787 | * Build macros | |
6788 | * This routine implements the seemingly endless macro or synthesized | |
6789 | * instructions and addressing modes in the mips assembly language. Many | |
6790 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6791 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6792 | * this verbose method. Others are not simple macros but are more like |
6793 | * optimizing code generation. | |
6794 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6795 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6796 | * The ensuing load upper instructions are ommited. This implies some kind |
6797 | * of global optimization. We currently only optimize within a single macro. | |
6798 | * For many of the load and store macros if the address is specified as a | |
6799 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6800 | * first load register 'at' with zero and use it as the base register. The | |
6801 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6802 | * we're missing. | |
6803 | */ | |
6804 | static void | |
833794fc | 6805 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 6806 | { |
741fe287 MR |
6807 | unsigned int treg, sreg, dreg, breg; |
6808 | unsigned int tempreg; | |
252b5132 | 6809 | int mask; |
43841e91 | 6810 | int used_at = 0; |
df58fc94 | 6811 | expressionS label_expr; |
252b5132 | 6812 | expressionS expr1; |
df58fc94 | 6813 | expressionS *ep; |
252b5132 RH |
6814 | const char *s; |
6815 | const char *s2; | |
6816 | const char *fmt; | |
6817 | int likely = 0; | |
252b5132 | 6818 | int coproc = 0; |
7f3c4072 | 6819 | int offbits = 16; |
1abe91b1 | 6820 | int call = 0; |
df58fc94 RS |
6821 | int jals = 0; |
6822 | int dbl = 0; | |
6823 | int imm = 0; | |
6824 | int ust = 0; | |
6825 | int lp = 0; | |
f2ae14a1 | 6826 | bfd_boolean large_offset; |
252b5132 | 6827 | int off; |
252b5132 | 6828 | int hold_mips_optimize; |
f2ae14a1 | 6829 | unsigned int align; |
252b5132 | 6830 | |
9c2799c2 | 6831 | gas_assert (! mips_opts.mips16); |
252b5132 | 6832 | |
df58fc94 RS |
6833 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6834 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6835 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6836 | mask = ip->insn_mo->mask; |
6837 | ||
df58fc94 RS |
6838 | label_expr.X_op = O_constant; |
6839 | label_expr.X_op_symbol = NULL; | |
6840 | label_expr.X_add_symbol = NULL; | |
6841 | label_expr.X_add_number = 0; | |
6842 | ||
252b5132 RH |
6843 | expr1.X_op = O_constant; |
6844 | expr1.X_op_symbol = NULL; | |
6845 | expr1.X_add_symbol = NULL; | |
6846 | expr1.X_add_number = 1; | |
f2ae14a1 | 6847 | align = 1; |
252b5132 RH |
6848 | |
6849 | switch (mask) | |
6850 | { | |
6851 | case M_DABS: | |
6852 | dbl = 1; | |
6853 | case M_ABS: | |
df58fc94 RS |
6854 | /* bgez $a0,1f |
6855 | move v0,$a0 | |
6856 | sub v0,$zero,$a0 | |
6857 | 1: | |
6858 | */ | |
252b5132 | 6859 | |
7d10b47d | 6860 | start_noreorder (); |
252b5132 | 6861 | |
df58fc94 RS |
6862 | if (mips_opts.micromips) |
6863 | micromips_label_expr (&label_expr); | |
6864 | else | |
6865 | label_expr.X_add_number = 8; | |
6866 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6867 | if (dreg == sreg) |
a605d2b3 | 6868 | macro_build (NULL, "nop", ""); |
252b5132 | 6869 | else |
67c0d1eb RS |
6870 | move_register (dreg, sreg); |
6871 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6872 | if (mips_opts.micromips) |
6873 | micromips_add_label (); | |
252b5132 | 6874 | |
7d10b47d | 6875 | end_noreorder (); |
8fc2e39e | 6876 | break; |
252b5132 RH |
6877 | |
6878 | case M_ADD_I: | |
6879 | s = "addi"; | |
6880 | s2 = "add"; | |
6881 | goto do_addi; | |
6882 | case M_ADDU_I: | |
6883 | s = "addiu"; | |
6884 | s2 = "addu"; | |
6885 | goto do_addi; | |
6886 | case M_DADD_I: | |
6887 | dbl = 1; | |
6888 | s = "daddi"; | |
6889 | s2 = "dadd"; | |
df58fc94 RS |
6890 | if (!mips_opts.micromips) |
6891 | goto do_addi; | |
6892 | if (imm_expr.X_op == O_constant | |
6893 | && imm_expr.X_add_number >= -0x200 | |
6894 | && imm_expr.X_add_number < 0x200) | |
6895 | { | |
6896 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6897 | break; | |
6898 | } | |
6899 | goto do_addi_i; | |
252b5132 RH |
6900 | case M_DADDU_I: |
6901 | dbl = 1; | |
6902 | s = "daddiu"; | |
6903 | s2 = "daddu"; | |
6904 | do_addi: | |
6905 | if (imm_expr.X_op == O_constant | |
6906 | && imm_expr.X_add_number >= -0x8000 | |
6907 | && imm_expr.X_add_number < 0x8000) | |
6908 | { | |
67c0d1eb | 6909 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6910 | break; |
252b5132 | 6911 | } |
df58fc94 | 6912 | do_addi_i: |
8fc2e39e | 6913 | used_at = 1; |
67c0d1eb RS |
6914 | load_register (AT, &imm_expr, dbl); |
6915 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6916 | break; |
6917 | ||
6918 | case M_AND_I: | |
6919 | s = "andi"; | |
6920 | s2 = "and"; | |
6921 | goto do_bit; | |
6922 | case M_OR_I: | |
6923 | s = "ori"; | |
6924 | s2 = "or"; | |
6925 | goto do_bit; | |
6926 | case M_NOR_I: | |
6927 | s = ""; | |
6928 | s2 = "nor"; | |
6929 | goto do_bit; | |
6930 | case M_XOR_I: | |
6931 | s = "xori"; | |
6932 | s2 = "xor"; | |
6933 | do_bit: | |
6934 | if (imm_expr.X_op == O_constant | |
6935 | && imm_expr.X_add_number >= 0 | |
6936 | && imm_expr.X_add_number < 0x10000) | |
6937 | { | |
6938 | if (mask != M_NOR_I) | |
67c0d1eb | 6939 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6940 | else |
6941 | { | |
67c0d1eb RS |
6942 | macro_build (&imm_expr, "ori", "t,r,i", |
6943 | treg, sreg, BFD_RELOC_LO16); | |
6944 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6945 | } |
8fc2e39e | 6946 | break; |
252b5132 RH |
6947 | } |
6948 | ||
8fc2e39e | 6949 | used_at = 1; |
67c0d1eb RS |
6950 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6951 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6952 | break; |
6953 | ||
8b082fb1 TS |
6954 | case M_BALIGN: |
6955 | switch (imm_expr.X_add_number) | |
6956 | { | |
6957 | case 0: | |
6958 | macro_build (NULL, "nop", ""); | |
6959 | break; | |
6960 | case 2: | |
6961 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6962 | break; | |
03f66e8a MR |
6963 | case 1: |
6964 | case 3: | |
8b082fb1 | 6965 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6966 | (int) imm_expr.X_add_number); |
8b082fb1 | 6967 | break; |
03f66e8a MR |
6968 | default: |
6969 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6970 | (unsigned long) imm_expr.X_add_number); | |
6971 | break; | |
8b082fb1 TS |
6972 | } |
6973 | break; | |
6974 | ||
df58fc94 RS |
6975 | case M_BC1FL: |
6976 | case M_BC1TL: | |
6977 | case M_BC2FL: | |
6978 | case M_BC2TL: | |
6979 | gas_assert (mips_opts.micromips); | |
6980 | macro_build_branch_ccl (mask, &offset_expr, | |
6981 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6982 | break; | |
6983 | ||
252b5132 | 6984 | case M_BEQ_I: |
252b5132 | 6985 | case M_BEQL_I: |
252b5132 | 6986 | case M_BNE_I: |
252b5132 | 6987 | case M_BNEL_I: |
252b5132 | 6988 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6989 | treg = 0; |
6990 | else | |
252b5132 | 6991 | { |
df58fc94 RS |
6992 | treg = AT; |
6993 | used_at = 1; | |
6994 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6995 | } |
df58fc94 RS |
6996 | /* Fall through. */ |
6997 | case M_BEQL: | |
6998 | case M_BNEL: | |
6999 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
7000 | break; |
7001 | ||
7002 | case M_BGEL: | |
7003 | likely = 1; | |
7004 | case M_BGE: | |
7005 | if (treg == 0) | |
df58fc94 RS |
7006 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
7007 | else if (sreg == 0) | |
7008 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
7009 | else | |
252b5132 | 7010 | { |
df58fc94 RS |
7011 | used_at = 1; |
7012 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
7013 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7014 | &offset_expr, AT, ZERO); | |
252b5132 | 7015 | } |
df58fc94 RS |
7016 | break; |
7017 | ||
7018 | case M_BGEZL: | |
7019 | case M_BGEZALL: | |
7020 | case M_BGTZL: | |
7021 | case M_BLEZL: | |
7022 | case M_BLTZL: | |
7023 | case M_BLTZALL: | |
7024 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
7025 | break; |
7026 | ||
7027 | case M_BGTL_I: | |
7028 | likely = 1; | |
7029 | case M_BGT_I: | |
90ecf173 | 7030 | /* Check for > max integer. */ |
42429eac | 7031 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
7032 | { |
7033 | do_false: | |
90ecf173 | 7034 | /* Result is always false. */ |
252b5132 | 7035 | if (! likely) |
a605d2b3 | 7036 | macro_build (NULL, "nop", ""); |
252b5132 | 7037 | else |
df58fc94 | 7038 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 7039 | break; |
252b5132 RH |
7040 | } |
7041 | if (imm_expr.X_op != O_constant) | |
7042 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7043 | ++imm_expr.X_add_number; |
252b5132 RH |
7044 | /* FALLTHROUGH */ |
7045 | case M_BGE_I: | |
7046 | case M_BGEL_I: | |
7047 | if (mask == M_BGEL_I) | |
7048 | likely = 1; | |
7049 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7050 | { | |
df58fc94 RS |
7051 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
7052 | &offset_expr, sreg); | |
8fc2e39e | 7053 | break; |
252b5132 RH |
7054 | } |
7055 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7056 | { | |
df58fc94 RS |
7057 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
7058 | &offset_expr, sreg); | |
8fc2e39e | 7059 | break; |
252b5132 | 7060 | } |
42429eac | 7061 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
7062 | { |
7063 | do_true: | |
7064 | /* result is always true */ | |
7065 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 7066 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7067 | break; |
252b5132 | 7068 | } |
8fc2e39e | 7069 | used_at = 1; |
67c0d1eb | 7070 | set_at (sreg, 0); |
df58fc94 RS |
7071 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
7072 | &offset_expr, AT, ZERO); | |
252b5132 RH |
7073 | break; |
7074 | ||
7075 | case M_BGEUL: | |
7076 | likely = 1; | |
7077 | case M_BGEU: | |
7078 | if (treg == 0) | |
7079 | goto do_true; | |
df58fc94 RS |
7080 | else if (sreg == 0) |
7081 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7082 | &offset_expr, ZERO, treg); | |
7083 | else | |
252b5132 | 7084 | { |
df58fc94 RS |
7085 | used_at = 1; |
7086 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
7087 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7088 | &offset_expr, AT, ZERO); | |
252b5132 | 7089 | } |
252b5132 RH |
7090 | break; |
7091 | ||
7092 | case M_BGTUL_I: | |
7093 | likely = 1; | |
7094 | case M_BGTU_I: | |
7095 | if (sreg == 0 | |
ca4e0257 | 7096 | || (HAVE_32BIT_GPRS |
252b5132 | 7097 | && imm_expr.X_op == O_constant |
f01dc953 | 7098 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
7099 | goto do_false; |
7100 | if (imm_expr.X_op != O_constant) | |
7101 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7102 | ++imm_expr.X_add_number; |
252b5132 RH |
7103 | /* FALLTHROUGH */ |
7104 | case M_BGEU_I: | |
7105 | case M_BGEUL_I: | |
7106 | if (mask == M_BGEUL_I) | |
7107 | likely = 1; | |
7108 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7109 | goto do_true; | |
df58fc94 RS |
7110 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
7111 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7112 | &offset_expr, sreg, ZERO); | |
7113 | else | |
252b5132 | 7114 | { |
df58fc94 RS |
7115 | used_at = 1; |
7116 | set_at (sreg, 1); | |
7117 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7118 | &offset_expr, AT, ZERO); | |
252b5132 | 7119 | } |
252b5132 RH |
7120 | break; |
7121 | ||
7122 | case M_BGTL: | |
7123 | likely = 1; | |
7124 | case M_BGT: | |
7125 | if (treg == 0) | |
df58fc94 RS |
7126 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
7127 | else if (sreg == 0) | |
7128 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
7129 | else | |
252b5132 | 7130 | { |
df58fc94 RS |
7131 | used_at = 1; |
7132 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
7133 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7134 | &offset_expr, AT, ZERO); | |
252b5132 | 7135 | } |
252b5132 RH |
7136 | break; |
7137 | ||
7138 | case M_BGTUL: | |
7139 | likely = 1; | |
7140 | case M_BGTU: | |
7141 | if (treg == 0) | |
df58fc94 RS |
7142 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
7143 | &offset_expr, sreg, ZERO); | |
7144 | else if (sreg == 0) | |
7145 | goto do_false; | |
7146 | else | |
252b5132 | 7147 | { |
df58fc94 RS |
7148 | used_at = 1; |
7149 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
7150 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7151 | &offset_expr, AT, ZERO); | |
252b5132 | 7152 | } |
252b5132 RH |
7153 | break; |
7154 | ||
7155 | case M_BLEL: | |
7156 | likely = 1; | |
7157 | case M_BLE: | |
7158 | if (treg == 0) | |
df58fc94 RS |
7159 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
7160 | else if (sreg == 0) | |
7161 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
7162 | else | |
252b5132 | 7163 | { |
df58fc94 RS |
7164 | used_at = 1; |
7165 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
7166 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7167 | &offset_expr, AT, ZERO); | |
252b5132 | 7168 | } |
252b5132 RH |
7169 | break; |
7170 | ||
7171 | case M_BLEL_I: | |
7172 | likely = 1; | |
7173 | case M_BLE_I: | |
42429eac | 7174 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
7175 | goto do_true; |
7176 | if (imm_expr.X_op != O_constant) | |
7177 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7178 | ++imm_expr.X_add_number; |
252b5132 RH |
7179 | /* FALLTHROUGH */ |
7180 | case M_BLT_I: | |
7181 | case M_BLTL_I: | |
7182 | if (mask == M_BLTL_I) | |
7183 | likely = 1; | |
7184 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
7185 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7186 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7187 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
7188 | else | |
252b5132 | 7189 | { |
df58fc94 RS |
7190 | used_at = 1; |
7191 | set_at (sreg, 0); | |
7192 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7193 | &offset_expr, AT, ZERO); | |
252b5132 | 7194 | } |
252b5132 RH |
7195 | break; |
7196 | ||
7197 | case M_BLEUL: | |
7198 | likely = 1; | |
7199 | case M_BLEU: | |
7200 | if (treg == 0) | |
df58fc94 RS |
7201 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
7202 | &offset_expr, sreg, ZERO); | |
7203 | else if (sreg == 0) | |
7204 | goto do_true; | |
7205 | else | |
252b5132 | 7206 | { |
df58fc94 RS |
7207 | used_at = 1; |
7208 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
7209 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7210 | &offset_expr, AT, ZERO); | |
252b5132 | 7211 | } |
252b5132 RH |
7212 | break; |
7213 | ||
7214 | case M_BLEUL_I: | |
7215 | likely = 1; | |
7216 | case M_BLEU_I: | |
7217 | if (sreg == 0 | |
ca4e0257 | 7218 | || (HAVE_32BIT_GPRS |
252b5132 | 7219 | && imm_expr.X_op == O_constant |
f01dc953 | 7220 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
7221 | goto do_true; |
7222 | if (imm_expr.X_op != O_constant) | |
7223 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7224 | ++imm_expr.X_add_number; |
252b5132 RH |
7225 | /* FALLTHROUGH */ |
7226 | case M_BLTU_I: | |
7227 | case M_BLTUL_I: | |
7228 | if (mask == M_BLTUL_I) | |
7229 | likely = 1; | |
7230 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7231 | goto do_false; | |
df58fc94 RS |
7232 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
7233 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7234 | &offset_expr, sreg, ZERO); | |
7235 | else | |
252b5132 | 7236 | { |
df58fc94 RS |
7237 | used_at = 1; |
7238 | set_at (sreg, 1); | |
7239 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7240 | &offset_expr, AT, ZERO); | |
252b5132 | 7241 | } |
252b5132 RH |
7242 | break; |
7243 | ||
7244 | case M_BLTL: | |
7245 | likely = 1; | |
7246 | case M_BLT: | |
7247 | if (treg == 0) | |
df58fc94 RS |
7248 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7249 | else if (sreg == 0) | |
7250 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
7251 | else | |
252b5132 | 7252 | { |
df58fc94 RS |
7253 | used_at = 1; |
7254 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
7255 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7256 | &offset_expr, AT, ZERO); | |
252b5132 | 7257 | } |
252b5132 RH |
7258 | break; |
7259 | ||
7260 | case M_BLTUL: | |
7261 | likely = 1; | |
7262 | case M_BLTU: | |
7263 | if (treg == 0) | |
7264 | goto do_false; | |
df58fc94 RS |
7265 | else if (sreg == 0) |
7266 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7267 | &offset_expr, ZERO, treg); | |
7268 | else | |
252b5132 | 7269 | { |
df58fc94 RS |
7270 | used_at = 1; |
7271 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
7272 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7273 | &offset_expr, AT, ZERO); | |
252b5132 | 7274 | } |
252b5132 RH |
7275 | break; |
7276 | ||
5f74bc13 CD |
7277 | case M_DEXT: |
7278 | { | |
d5818fca MR |
7279 | /* Use unsigned arithmetic. */ |
7280 | addressT pos; | |
7281 | addressT size; | |
5f74bc13 | 7282 | |
90ecf173 | 7283 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7284 | { |
7285 | as_bad (_("Unsupported large constant")); | |
7286 | pos = size = 1; | |
7287 | } | |
7288 | else | |
7289 | { | |
d5818fca MR |
7290 | pos = imm_expr.X_add_number; |
7291 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7292 | } |
7293 | ||
7294 | if (pos > 63) | |
7295 | { | |
d5818fca | 7296 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7297 | pos = 1; |
7298 | } | |
90ecf173 | 7299 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7300 | { |
7301 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 7302 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7303 | size = 1; |
7304 | } | |
7305 | ||
7306 | if (size <= 32 && pos < 32) | |
7307 | { | |
7308 | s = "dext"; | |
7309 | fmt = "t,r,+A,+C"; | |
7310 | } | |
7311 | else if (size <= 32) | |
7312 | { | |
7313 | s = "dextu"; | |
7314 | fmt = "t,r,+E,+H"; | |
7315 | } | |
7316 | else | |
7317 | { | |
7318 | s = "dextm"; | |
7319 | fmt = "t,r,+A,+G"; | |
7320 | } | |
d5818fca MR |
7321 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7322 | (int) (size - 1)); | |
5f74bc13 | 7323 | } |
8fc2e39e | 7324 | break; |
5f74bc13 CD |
7325 | |
7326 | case M_DINS: | |
7327 | { | |
d5818fca MR |
7328 | /* Use unsigned arithmetic. */ |
7329 | addressT pos; | |
7330 | addressT size; | |
5f74bc13 | 7331 | |
90ecf173 | 7332 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7333 | { |
7334 | as_bad (_("Unsupported large constant")); | |
7335 | pos = size = 1; | |
7336 | } | |
7337 | else | |
7338 | { | |
d5818fca MR |
7339 | pos = imm_expr.X_add_number; |
7340 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7341 | } |
7342 | ||
7343 | if (pos > 63) | |
7344 | { | |
d5818fca | 7345 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7346 | pos = 1; |
7347 | } | |
90ecf173 | 7348 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7349 | { |
7350 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 7351 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7352 | size = 1; |
7353 | } | |
7354 | ||
7355 | if (pos < 32 && (pos + size - 1) < 32) | |
7356 | { | |
7357 | s = "dins"; | |
7358 | fmt = "t,r,+A,+B"; | |
7359 | } | |
7360 | else if (pos >= 32) | |
7361 | { | |
7362 | s = "dinsu"; | |
7363 | fmt = "t,r,+E,+F"; | |
7364 | } | |
7365 | else | |
7366 | { | |
7367 | s = "dinsm"; | |
7368 | fmt = "t,r,+A,+F"; | |
7369 | } | |
750bdd57 AS |
7370 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7371 | (int) (pos + size - 1)); | |
5f74bc13 | 7372 | } |
8fc2e39e | 7373 | break; |
5f74bc13 | 7374 | |
252b5132 RH |
7375 | case M_DDIV_3: |
7376 | dbl = 1; | |
7377 | case M_DIV_3: | |
7378 | s = "mflo"; | |
7379 | goto do_div3; | |
7380 | case M_DREM_3: | |
7381 | dbl = 1; | |
7382 | case M_REM_3: | |
7383 | s = "mfhi"; | |
7384 | do_div3: | |
7385 | if (treg == 0) | |
7386 | { | |
7387 | as_warn (_("Divide by zero.")); | |
7388 | if (mips_trap) | |
df58fc94 | 7389 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7390 | else |
df58fc94 | 7391 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7392 | break; |
252b5132 RH |
7393 | } |
7394 | ||
7d10b47d | 7395 | start_noreorder (); |
252b5132 RH |
7396 | if (mips_trap) |
7397 | { | |
df58fc94 | 7398 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7399 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7400 | } |
7401 | else | |
7402 | { | |
df58fc94 RS |
7403 | if (mips_opts.micromips) |
7404 | micromips_label_expr (&label_expr); | |
7405 | else | |
7406 | label_expr.X_add_number = 8; | |
7407 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7408 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7409 | macro_build (NULL, "break", BRK_FMT, 7); |
7410 | if (mips_opts.micromips) | |
7411 | micromips_add_label (); | |
252b5132 RH |
7412 | } |
7413 | expr1.X_add_number = -1; | |
8fc2e39e | 7414 | used_at = 1; |
f6a22291 | 7415 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7416 | if (mips_opts.micromips) |
7417 | micromips_label_expr (&label_expr); | |
7418 | else | |
7419 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7420 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7421 | if (dbl) |
7422 | { | |
7423 | expr1.X_add_number = 1; | |
f6a22291 | 7424 | load_register (AT, &expr1, dbl); |
df58fc94 | 7425 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7426 | } |
7427 | else | |
7428 | { | |
7429 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7430 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7431 | } |
7432 | if (mips_trap) | |
7433 | { | |
df58fc94 | 7434 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7435 | /* We want to close the noreorder block as soon as possible, so |
7436 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7437 | end_noreorder (); |
252b5132 RH |
7438 | } |
7439 | else | |
7440 | { | |
df58fc94 RS |
7441 | if (mips_opts.micromips) |
7442 | micromips_label_expr (&label_expr); | |
7443 | else | |
7444 | label_expr.X_add_number = 8; | |
7445 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7446 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7447 | |
7448 | /* We want to close the noreorder block as soon as possible, so | |
7449 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7450 | end_noreorder (); |
252b5132 | 7451 | |
df58fc94 | 7452 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7453 | } |
df58fc94 RS |
7454 | if (mips_opts.micromips) |
7455 | micromips_add_label (); | |
7456 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7457 | break; |
7458 | ||
7459 | case M_DIV_3I: | |
7460 | s = "div"; | |
7461 | s2 = "mflo"; | |
7462 | goto do_divi; | |
7463 | case M_DIVU_3I: | |
7464 | s = "divu"; | |
7465 | s2 = "mflo"; | |
7466 | goto do_divi; | |
7467 | case M_REM_3I: | |
7468 | s = "div"; | |
7469 | s2 = "mfhi"; | |
7470 | goto do_divi; | |
7471 | case M_REMU_3I: | |
7472 | s = "divu"; | |
7473 | s2 = "mfhi"; | |
7474 | goto do_divi; | |
7475 | case M_DDIV_3I: | |
7476 | dbl = 1; | |
7477 | s = "ddiv"; | |
7478 | s2 = "mflo"; | |
7479 | goto do_divi; | |
7480 | case M_DDIVU_3I: | |
7481 | dbl = 1; | |
7482 | s = "ddivu"; | |
7483 | s2 = "mflo"; | |
7484 | goto do_divi; | |
7485 | case M_DREM_3I: | |
7486 | dbl = 1; | |
7487 | s = "ddiv"; | |
7488 | s2 = "mfhi"; | |
7489 | goto do_divi; | |
7490 | case M_DREMU_3I: | |
7491 | dbl = 1; | |
7492 | s = "ddivu"; | |
7493 | s2 = "mfhi"; | |
7494 | do_divi: | |
7495 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7496 | { | |
7497 | as_warn (_("Divide by zero.")); | |
7498 | if (mips_trap) | |
df58fc94 | 7499 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7500 | else |
df58fc94 | 7501 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7502 | break; |
252b5132 RH |
7503 | } |
7504 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7505 | { | |
7506 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7507 | move_register (dreg, sreg); |
252b5132 | 7508 | else |
c80c840e | 7509 | move_register (dreg, ZERO); |
8fc2e39e | 7510 | break; |
252b5132 RH |
7511 | } |
7512 | if (imm_expr.X_op == O_constant | |
7513 | && imm_expr.X_add_number == -1 | |
7514 | && s[strlen (s) - 1] != 'u') | |
7515 | { | |
7516 | if (strcmp (s2, "mflo") == 0) | |
7517 | { | |
67c0d1eb | 7518 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7519 | } |
7520 | else | |
c80c840e | 7521 | move_register (dreg, ZERO); |
8fc2e39e | 7522 | break; |
252b5132 RH |
7523 | } |
7524 | ||
8fc2e39e | 7525 | used_at = 1; |
67c0d1eb RS |
7526 | load_register (AT, &imm_expr, dbl); |
7527 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7528 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7529 | break; |
7530 | ||
7531 | case M_DIVU_3: | |
7532 | s = "divu"; | |
7533 | s2 = "mflo"; | |
7534 | goto do_divu3; | |
7535 | case M_REMU_3: | |
7536 | s = "divu"; | |
7537 | s2 = "mfhi"; | |
7538 | goto do_divu3; | |
7539 | case M_DDIVU_3: | |
7540 | s = "ddivu"; | |
7541 | s2 = "mflo"; | |
7542 | goto do_divu3; | |
7543 | case M_DREMU_3: | |
7544 | s = "ddivu"; | |
7545 | s2 = "mfhi"; | |
7546 | do_divu3: | |
7d10b47d | 7547 | start_noreorder (); |
252b5132 RH |
7548 | if (mips_trap) |
7549 | { | |
df58fc94 | 7550 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7551 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7552 | /* We want to close the noreorder block as soon as possible, so |
7553 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7554 | end_noreorder (); |
252b5132 RH |
7555 | } |
7556 | else | |
7557 | { | |
df58fc94 RS |
7558 | if (mips_opts.micromips) |
7559 | micromips_label_expr (&label_expr); | |
7560 | else | |
7561 | label_expr.X_add_number = 8; | |
7562 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7563 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7564 | |
7565 | /* We want to close the noreorder block as soon as possible, so | |
7566 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7567 | end_noreorder (); |
df58fc94 RS |
7568 | macro_build (NULL, "break", BRK_FMT, 7); |
7569 | if (mips_opts.micromips) | |
7570 | micromips_add_label (); | |
252b5132 | 7571 | } |
df58fc94 | 7572 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7573 | break; |
252b5132 | 7574 | |
1abe91b1 MR |
7575 | case M_DLCA_AB: |
7576 | dbl = 1; | |
7577 | case M_LCA_AB: | |
7578 | call = 1; | |
7579 | goto do_la; | |
252b5132 RH |
7580 | case M_DLA_AB: |
7581 | dbl = 1; | |
7582 | case M_LA_AB: | |
1abe91b1 | 7583 | do_la: |
252b5132 RH |
7584 | /* Load the address of a symbol into a register. If breg is not |
7585 | zero, we then add a base register to it. */ | |
7586 | ||
3bec30a8 TS |
7587 | if (dbl && HAVE_32BIT_GPRS) |
7588 | as_warn (_("dla used to load 32-bit register")); | |
7589 | ||
90ecf173 | 7590 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7591 | as_warn (_("la used to load 64-bit address")); |
7592 | ||
f2ae14a1 | 7593 | if (small_offset_p (0, align, 16)) |
0c11417f | 7594 | { |
f2ae14a1 RS |
7595 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg, |
7596 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8fc2e39e | 7597 | break; |
0c11417f MR |
7598 | } |
7599 | ||
741fe287 | 7600 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7601 | { |
7602 | tempreg = AT; | |
7603 | used_at = 1; | |
7604 | } | |
7605 | else | |
7606 | { | |
7607 | tempreg = treg; | |
afdbd6d0 CD |
7608 | } |
7609 | ||
252b5132 RH |
7610 | if (offset_expr.X_op != O_symbol |
7611 | && offset_expr.X_op != O_constant) | |
7612 | { | |
f71d0d44 | 7613 | as_bad (_("Expression too complex")); |
252b5132 RH |
7614 | offset_expr.X_op = O_constant; |
7615 | } | |
7616 | ||
252b5132 | 7617 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7618 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7619 | else if (mips_pic == NO_PIC) |
7620 | { | |
d6bc6245 | 7621 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7622 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7623 | Otherwise we want |
7624 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7625 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7626 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7627 | so we may as well always use the latter form. |
76b3015f | 7628 | |
6caf9ef4 TS |
7629 | With 64bit address space and a usable $at we want |
7630 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7631 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7632 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7633 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7634 | dsll32 $tempreg,0 | |
7635 | daddu $tempreg,$tempreg,$at | |
7636 | ||
7637 | If $at is already in use, we use a path which is suboptimal | |
7638 | on superscalar processors. | |
7639 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7640 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7641 | dsll $tempreg,16 | |
7642 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7643 | dsll $tempreg,16 | |
7644 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7645 | ||
7646 | For GP relative symbols in 64bit address space we can use | |
7647 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7648 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7649 | { |
6caf9ef4 TS |
7650 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7651 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7652 | { | |
7653 | relax_start (offset_expr.X_add_symbol); | |
7654 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7655 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7656 | relax_switch (); | |
7657 | } | |
d6bc6245 | 7658 | |
741fe287 | 7659 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7660 | { |
df58fc94 | 7661 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7662 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7663 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7664 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7665 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7666 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7667 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7668 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7669 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7670 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7671 | used_at = 1; |
7672 | } | |
7673 | else | |
7674 | { | |
df58fc94 | 7675 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7676 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7677 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7678 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7679 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7680 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7681 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7682 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7683 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7684 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7685 | } |
6caf9ef4 TS |
7686 | |
7687 | if (mips_relax.sequence) | |
7688 | relax_end (); | |
98d3f06f KH |
7689 | } |
7690 | else | |
7691 | { | |
7692 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7693 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7694 | { |
4d7206a2 | 7695 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7696 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7697 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7698 | relax_switch (); |
98d3f06f | 7699 | } |
6943caf0 | 7700 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7701 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7702 | macro_build_lui (&offset_expr, tempreg); |
7703 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7704 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7705 | if (mips_relax.sequence) |
7706 | relax_end (); | |
98d3f06f | 7707 | } |
252b5132 | 7708 | } |
0a44bf69 | 7709 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7710 | { |
9117d219 NC |
7711 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7712 | ||
252b5132 RH |
7713 | /* If this is a reference to an external symbol, and there |
7714 | is no constant, we want | |
7715 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7716 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7717 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7718 | For a local symbol, we want |
7719 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7720 | nop | |
7721 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7722 | ||
7723 | If we have a small constant, and this is a reference to | |
7724 | an external symbol, we want | |
7725 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7726 | nop | |
7727 | addiu $tempreg,$tempreg,<constant> | |
7728 | For a local symbol, we want the same instruction | |
7729 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7730 | addiu instruction. | |
7731 | ||
7732 | If we have a large constant, and this is a reference to | |
7733 | an external symbol, we want | |
7734 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7735 | lui $at,<hiconstant> | |
7736 | addiu $at,$at,<loconstant> | |
7737 | addu $tempreg,$tempreg,$at | |
7738 | For a local symbol, we want the same instruction | |
7739 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7740 | addiu instruction. |
ed6fb7bd SC |
7741 | */ |
7742 | ||
4d7206a2 | 7743 | if (offset_expr.X_add_number == 0) |
252b5132 | 7744 | { |
0a44bf69 RS |
7745 | if (mips_pic == SVR4_PIC |
7746 | && breg == 0 | |
7747 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7748 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7749 | ||
7750 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7751 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7752 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7753 | if (breg != 0) |
252b5132 RH |
7754 | { |
7755 | /* We're going to put in an addu instruction using | |
7756 | tempreg, so we may as well insert the nop right | |
7757 | now. */ | |
269137b2 | 7758 | load_delay_nop (); |
252b5132 | 7759 | } |
4d7206a2 | 7760 | relax_switch (); |
67c0d1eb RS |
7761 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7762 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7763 | load_delay_nop (); |
67c0d1eb RS |
7764 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7765 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7766 | relax_end (); |
252b5132 RH |
7767 | /* FIXME: If breg == 0, and the next instruction uses |
7768 | $tempreg, then if this variant case is used an extra | |
7769 | nop will be generated. */ | |
7770 | } | |
4d7206a2 RS |
7771 | else if (offset_expr.X_add_number >= -0x8000 |
7772 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7773 | { |
67c0d1eb | 7774 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7775 | load_delay_nop (); |
67c0d1eb | 7776 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7777 | } |
7778 | else | |
7779 | { | |
4d7206a2 RS |
7780 | expr1.X_add_number = offset_expr.X_add_number; |
7781 | offset_expr.X_add_number = | |
43c0598f | 7782 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7783 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7784 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7785 | /* If we are going to add in a base register, and the |
7786 | target register and the base register are the same, | |
7787 | then we are using AT as a temporary register. Since | |
7788 | we want to load the constant into AT, we add our | |
7789 | current AT (from the global offset table) and the | |
7790 | register into the register now, and pretend we were | |
7791 | not using a base register. */ | |
67c0d1eb | 7792 | if (breg == treg) |
252b5132 | 7793 | { |
269137b2 | 7794 | load_delay_nop (); |
67c0d1eb | 7795 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7796 | treg, AT, breg); |
252b5132 RH |
7797 | breg = 0; |
7798 | tempreg = treg; | |
252b5132 | 7799 | } |
f6a22291 | 7800 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7801 | used_at = 1; |
7802 | } | |
7803 | } | |
0a44bf69 | 7804 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7805 | { |
67c0d1eb | 7806 | int add_breg_early = 0; |
f5040a92 AO |
7807 | |
7808 | /* If this is a reference to an external, and there is no | |
7809 | constant, or local symbol (*), with or without a | |
7810 | constant, we want | |
7811 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7812 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7813 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7814 | ||
7815 | If we have a small constant, and this is a reference to | |
7816 | an external symbol, we want | |
7817 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7818 | addiu $tempreg,$tempreg,<constant> | |
7819 | ||
7820 | If we have a large constant, and this is a reference to | |
7821 | an external symbol, we want | |
7822 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7823 | lui $at,<hiconstant> | |
7824 | addiu $at,$at,<loconstant> | |
7825 | addu $tempreg,$tempreg,$at | |
7826 | ||
7827 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7828 | local symbols, even though it introduces an additional | |
7829 | instruction. */ | |
7830 | ||
f5040a92 AO |
7831 | if (offset_expr.X_add_number) |
7832 | { | |
4d7206a2 | 7833 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7834 | offset_expr.X_add_number = 0; |
7835 | ||
4d7206a2 | 7836 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7837 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7838 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7839 | |
7840 | if (expr1.X_add_number >= -0x8000 | |
7841 | && expr1.X_add_number < 0x8000) | |
7842 | { | |
67c0d1eb RS |
7843 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7844 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7845 | } |
ecd13cd3 | 7846 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7847 | { |
f5040a92 AO |
7848 | /* If we are going to add in a base register, and the |
7849 | target register and the base register are the same, | |
7850 | then we are using AT as a temporary register. Since | |
7851 | we want to load the constant into AT, we add our | |
7852 | current AT (from the global offset table) and the | |
7853 | register into the register now, and pretend we were | |
7854 | not using a base register. */ | |
7855 | if (breg != treg) | |
7856 | dreg = tempreg; | |
7857 | else | |
7858 | { | |
9c2799c2 | 7859 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7860 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7861 | treg, AT, breg); | |
f5040a92 | 7862 | dreg = treg; |
67c0d1eb | 7863 | add_breg_early = 1; |
f5040a92 AO |
7864 | } |
7865 | ||
f6a22291 | 7866 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7867 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7868 | dreg, dreg, AT); |
f5040a92 | 7869 | |
f5040a92 AO |
7870 | used_at = 1; |
7871 | } | |
7872 | else | |
7873 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7874 | ||
4d7206a2 | 7875 | relax_switch (); |
f5040a92 AO |
7876 | offset_expr.X_add_number = expr1.X_add_number; |
7877 | ||
67c0d1eb RS |
7878 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7879 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7880 | if (add_breg_early) | |
f5040a92 | 7881 | { |
67c0d1eb | 7882 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7883 | treg, tempreg, breg); |
f5040a92 AO |
7884 | breg = 0; |
7885 | tempreg = treg; | |
7886 | } | |
4d7206a2 | 7887 | relax_end (); |
f5040a92 | 7888 | } |
4d7206a2 | 7889 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7890 | { |
4d7206a2 | 7891 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7892 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7893 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7894 | relax_switch (); |
67c0d1eb RS |
7895 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7896 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7897 | relax_end (); |
f5040a92 | 7898 | } |
4d7206a2 | 7899 | else |
f5040a92 | 7900 | { |
67c0d1eb RS |
7901 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7902 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7903 | } |
7904 | } | |
0a44bf69 | 7905 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7906 | { |
67c0d1eb | 7907 | int gpdelay; |
9117d219 NC |
7908 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7909 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7910 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7911 | |
7912 | /* This is the large GOT case. If this is a reference to an | |
7913 | external symbol, and there is no constant, we want | |
7914 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7915 | addu $tempreg,$tempreg,$gp | |
7916 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7917 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7918 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7919 | addu $tempreg,$tempreg,$gp | |
7920 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7921 | For a local symbol, we want |
7922 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7923 | nop | |
7924 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7925 | ||
7926 | If we have a small constant, and this is a reference to | |
7927 | an external symbol, we want | |
7928 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7929 | addu $tempreg,$tempreg,$gp | |
7930 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7931 | nop | |
7932 | addiu $tempreg,$tempreg,<constant> | |
7933 | For a local symbol, we want | |
7934 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7935 | nop | |
7936 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7937 | ||
7938 | If we have a large constant, and this is a reference to | |
7939 | an external symbol, we want | |
7940 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7941 | addu $tempreg,$tempreg,$gp | |
7942 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7943 | lui $at,<hiconstant> | |
7944 | addiu $at,$at,<loconstant> | |
7945 | addu $tempreg,$tempreg,$at | |
7946 | For a local symbol, we want | |
7947 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7948 | lui $at,<hiconstant> | |
7949 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7950 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7951 | */ |
438c16b8 | 7952 | |
252b5132 RH |
7953 | expr1.X_add_number = offset_expr.X_add_number; |
7954 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7955 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7956 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7957 | if (expr1.X_add_number == 0 && breg == 0 |
7958 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7959 | { |
7960 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7961 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7962 | } | |
df58fc94 | 7963 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7964 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7965 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7966 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7967 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7968 | if (expr1.X_add_number == 0) |
7969 | { | |
67c0d1eb | 7970 | if (breg != 0) |
252b5132 RH |
7971 | { |
7972 | /* We're going to put in an addu instruction using | |
7973 | tempreg, so we may as well insert the nop right | |
7974 | now. */ | |
269137b2 | 7975 | load_delay_nop (); |
252b5132 | 7976 | } |
252b5132 RH |
7977 | } |
7978 | else if (expr1.X_add_number >= -0x8000 | |
7979 | && expr1.X_add_number < 0x8000) | |
7980 | { | |
269137b2 | 7981 | load_delay_nop (); |
67c0d1eb | 7982 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7983 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7984 | } |
7985 | else | |
7986 | { | |
252b5132 RH |
7987 | /* If we are going to add in a base register, and the |
7988 | target register and the base register are the same, | |
7989 | then we are using AT as a temporary register. Since | |
7990 | we want to load the constant into AT, we add our | |
7991 | current AT (from the global offset table) and the | |
7992 | register into the register now, and pretend we were | |
7993 | not using a base register. */ | |
7994 | if (breg != treg) | |
67c0d1eb | 7995 | dreg = tempreg; |
252b5132 RH |
7996 | else |
7997 | { | |
9c2799c2 | 7998 | gas_assert (tempreg == AT); |
269137b2 | 7999 | load_delay_nop (); |
67c0d1eb | 8000 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8001 | treg, AT, breg); |
252b5132 | 8002 | dreg = treg; |
252b5132 RH |
8003 | } |
8004 | ||
f6a22291 | 8005 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 8006 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 8007 | |
252b5132 RH |
8008 | used_at = 1; |
8009 | } | |
43c0598f | 8010 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 8011 | relax_switch (); |
252b5132 | 8012 | |
67c0d1eb | 8013 | if (gpdelay) |
252b5132 RH |
8014 | { |
8015 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 8016 | the first instruction on the main stream does not. */ |
67c0d1eb | 8017 | macro_build (NULL, "nop", ""); |
252b5132 | 8018 | } |
ed6fb7bd | 8019 | |
67c0d1eb RS |
8020 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8021 | local_reloc_type, mips_gp_register); | |
f5040a92 | 8022 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
8023 | && expr1.X_add_number < 0x8000) |
8024 | { | |
269137b2 | 8025 | load_delay_nop (); |
67c0d1eb RS |
8026 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8027 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 8028 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
8029 | register, the external symbol case ended with a load, |
8030 | so if the symbol turns out to not be external, and | |
8031 | the next instruction uses tempreg, an unnecessary nop | |
8032 | will be inserted. */ | |
252b5132 RH |
8033 | } |
8034 | else | |
8035 | { | |
8036 | if (breg == treg) | |
8037 | { | |
8038 | /* We must add in the base register now, as in the | |
f5040a92 | 8039 | external symbol case. */ |
9c2799c2 | 8040 | gas_assert (tempreg == AT); |
269137b2 | 8041 | load_delay_nop (); |
67c0d1eb | 8042 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8043 | treg, AT, breg); |
252b5132 RH |
8044 | tempreg = treg; |
8045 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 8046 | it in in both cases. */ |
252b5132 RH |
8047 | breg = 0; |
8048 | } | |
8049 | ||
67c0d1eb RS |
8050 | macro_build_lui (&expr1, AT); |
8051 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 8052 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 8053 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8054 | tempreg, tempreg, AT); |
8fc2e39e | 8055 | used_at = 1; |
252b5132 | 8056 | } |
4d7206a2 | 8057 | relax_end (); |
252b5132 | 8058 | } |
0a44bf69 | 8059 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8060 | { |
f5040a92 AO |
8061 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
8062 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 8063 | int add_breg_early = 0; |
f5040a92 AO |
8064 | |
8065 | /* This is the large GOT case. If this is a reference to an | |
8066 | external symbol, and there is no constant, we want | |
8067 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8068 | add $tempreg,$tempreg,$gp | |
8069 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 8070 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
8071 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
8072 | add $tempreg,$tempreg,$gp | |
8073 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
8074 | ||
8075 | If we have a small constant, and this is a reference to | |
8076 | an external symbol, we want | |
8077 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8078 | add $tempreg,$tempreg,$gp | |
8079 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8080 | addi $tempreg,$tempreg,<constant> | |
8081 | ||
8082 | If we have a large constant, and this is a reference to | |
8083 | an external symbol, we want | |
8084 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8085 | addu $tempreg,$tempreg,$gp | |
8086 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8087 | lui $at,<hiconstant> | |
8088 | addi $at,$at,<loconstant> | |
8089 | add $tempreg,$tempreg,$at | |
8090 | ||
8091 | If we have NewABI, and we know it's a local symbol, we want | |
8092 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8093 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
8094 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
8095 | ||
4d7206a2 | 8096 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 8097 | |
4d7206a2 | 8098 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8099 | offset_expr.X_add_number = 0; |
8100 | ||
1abe91b1 MR |
8101 | if (expr1.X_add_number == 0 && breg == 0 |
8102 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
8103 | { |
8104 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
8105 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
8106 | } | |
df58fc94 | 8107 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 8108 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8109 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
8110 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8111 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
8112 | |
8113 | if (expr1.X_add_number == 0) | |
4d7206a2 | 8114 | ; |
f5040a92 AO |
8115 | else if (expr1.X_add_number >= -0x8000 |
8116 | && expr1.X_add_number < 0x8000) | |
8117 | { | |
67c0d1eb | 8118 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 8119 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 8120 | } |
ecd13cd3 | 8121 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 8122 | { |
f5040a92 AO |
8123 | /* If we are going to add in a base register, and the |
8124 | target register and the base register are the same, | |
8125 | then we are using AT as a temporary register. Since | |
8126 | we want to load the constant into AT, we add our | |
8127 | current AT (from the global offset table) and the | |
8128 | register into the register now, and pretend we were | |
8129 | not using a base register. */ | |
8130 | if (breg != treg) | |
8131 | dreg = tempreg; | |
8132 | else | |
8133 | { | |
9c2799c2 | 8134 | gas_assert (tempreg == AT); |
67c0d1eb | 8135 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8136 | treg, AT, breg); |
f5040a92 | 8137 | dreg = treg; |
67c0d1eb | 8138 | add_breg_early = 1; |
f5040a92 AO |
8139 | } |
8140 | ||
f6a22291 | 8141 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 8142 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 8143 | |
f5040a92 AO |
8144 | used_at = 1; |
8145 | } | |
8146 | else | |
8147 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
8148 | ||
4d7206a2 | 8149 | relax_switch (); |
f5040a92 | 8150 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8151 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8152 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
8153 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
8154 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
8155 | if (add_breg_early) | |
f5040a92 | 8156 | { |
67c0d1eb | 8157 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8158 | treg, tempreg, breg); |
f5040a92 AO |
8159 | breg = 0; |
8160 | tempreg = treg; | |
8161 | } | |
4d7206a2 | 8162 | relax_end (); |
f5040a92 | 8163 | } |
252b5132 RH |
8164 | else |
8165 | abort (); | |
8166 | ||
8167 | if (breg != 0) | |
aed1a261 | 8168 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
8169 | break; |
8170 | ||
52b6b6b9 | 8171 | case M_MSGSND: |
df58fc94 | 8172 | gas_assert (!mips_opts.micromips); |
c8276761 | 8173 | macro_build (NULL, "c2", "C", (treg << 16) | 0x01); |
c7af4273 | 8174 | break; |
52b6b6b9 JM |
8175 | |
8176 | case M_MSGLD: | |
df58fc94 | 8177 | gas_assert (!mips_opts.micromips); |
c8276761 | 8178 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 8179 | break; |
52b6b6b9 JM |
8180 | |
8181 | case M_MSGLD_T: | |
df58fc94 | 8182 | gas_assert (!mips_opts.micromips); |
c8276761 | 8183 | macro_build (NULL, "c2", "C", (treg << 16) | 0x02); |
c7af4273 | 8184 | break; |
52b6b6b9 JM |
8185 | |
8186 | case M_MSGWAIT: | |
df58fc94 | 8187 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 8188 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 8189 | break; |
52b6b6b9 JM |
8190 | |
8191 | case M_MSGWAIT_T: | |
df58fc94 | 8192 | gas_assert (!mips_opts.micromips); |
c8276761 | 8193 | macro_build (NULL, "c2", "C", (treg << 16) | 0x03); |
c7af4273 | 8194 | break; |
52b6b6b9 | 8195 | |
252b5132 RH |
8196 | case M_J_A: |
8197 | /* The j instruction may not be used in PIC code, since it | |
8198 | requires an absolute address. We convert it to a b | |
8199 | instruction. */ | |
8200 | if (mips_pic == NO_PIC) | |
67c0d1eb | 8201 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 8202 | else |
67c0d1eb | 8203 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 8204 | break; |
252b5132 RH |
8205 | |
8206 | /* The jal instructions must be handled as macros because when | |
8207 | generating PIC code they expand to multi-instruction | |
8208 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
8209 | case M_JALS_1: |
8210 | dreg = RA; | |
8211 | /* Fall through. */ | |
8212 | case M_JALS_2: | |
8213 | gas_assert (mips_opts.micromips); | |
833794fc MR |
8214 | if (mips_opts.insn32) |
8215 | { | |
8216 | as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str); | |
8217 | break; | |
8218 | } | |
df58fc94 RS |
8219 | jals = 1; |
8220 | goto jal; | |
252b5132 RH |
8221 | case M_JAL_1: |
8222 | dreg = RA; | |
8223 | /* Fall through. */ | |
8224 | case M_JAL_2: | |
df58fc94 | 8225 | jal: |
3e722fb5 | 8226 | if (mips_pic == NO_PIC) |
df58fc94 RS |
8227 | { |
8228 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 8229 | if (mips_opts.micromips |
833794fc | 8230 | && !mips_opts.insn32 |
e64af278 MR |
8231 | && dreg == RA |
8232 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8233 | macro_build (NULL, s, "mj", sreg); |
8234 | else | |
8235 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
8236 | } | |
0a44bf69 | 8237 | else |
252b5132 | 8238 | { |
df58fc94 RS |
8239 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
8240 | && mips_cprestore_offset >= 0); | |
8241 | ||
252b5132 RH |
8242 | if (sreg != PIC_CALL_REG) |
8243 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 8244 | |
833794fc MR |
8245 | s = ((mips_opts.micromips |
8246 | && !mips_opts.insn32 | |
8247 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 8248 | ? "jalrs" : "jalr"); |
e64af278 | 8249 | if (mips_opts.micromips |
833794fc | 8250 | && !mips_opts.insn32 |
e64af278 MR |
8251 | && dreg == RA |
8252 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8253 | macro_build (NULL, s, "mj", sreg); |
8254 | else | |
8255 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 8256 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 8257 | { |
6478892d TS |
8258 | if (mips_cprestore_offset < 0) |
8259 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8260 | else | |
8261 | { | |
90ecf173 | 8262 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8263 | { |
8264 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8265 | /* Quiet this warning. */ | |
8266 | mips_frame_reg_valid = 1; | |
8267 | } | |
90ecf173 | 8268 | if (!mips_cprestore_valid) |
7a621144 DJ |
8269 | { |
8270 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8271 | /* Quiet this warning. */ | |
8272 | mips_cprestore_valid = 1; | |
8273 | } | |
d3fca0b5 MR |
8274 | if (mips_opts.noreorder) |
8275 | macro_build (NULL, "nop", ""); | |
6478892d | 8276 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8277 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8278 | mips_gp_register, |
256ab948 TS |
8279 | mips_frame_reg, |
8280 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8281 | } |
252b5132 RH |
8282 | } |
8283 | } | |
252b5132 | 8284 | |
8fc2e39e | 8285 | break; |
252b5132 | 8286 | |
df58fc94 RS |
8287 | case M_JALS_A: |
8288 | gas_assert (mips_opts.micromips); | |
833794fc MR |
8289 | if (mips_opts.insn32) |
8290 | { | |
8291 | as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str); | |
8292 | break; | |
8293 | } | |
df58fc94 RS |
8294 | jals = 1; |
8295 | /* Fall through. */ | |
252b5132 RH |
8296 | case M_JAL_A: |
8297 | if (mips_pic == NO_PIC) | |
df58fc94 | 8298 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
8299 | else if (mips_pic == SVR4_PIC) |
8300 | { | |
8301 | /* If this is a reference to an external symbol, and we are | |
8302 | using a small GOT, we want | |
8303 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
8304 | nop | |
f9419b05 | 8305 | jalr $ra,$25 |
252b5132 RH |
8306 | nop |
8307 | lw $gp,cprestore($sp) | |
8308 | The cprestore value is set using the .cprestore | |
8309 | pseudo-op. If we are using a big GOT, we want | |
8310 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
8311 | addu $25,$25,$gp | |
8312 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
8313 | nop | |
f9419b05 | 8314 | jalr $ra,$25 |
252b5132 RH |
8315 | nop |
8316 | lw $gp,cprestore($sp) | |
8317 | If the symbol is not external, we want | |
8318 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8319 | nop | |
8320 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 8321 | jalr $ra,$25 |
252b5132 | 8322 | nop |
438c16b8 | 8323 | lw $gp,cprestore($sp) |
f5040a92 AO |
8324 | |
8325 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
8326 | sequences above, minus nops, unless the symbol is local, | |
8327 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
8328 | GOT_DISP. */ | |
438c16b8 | 8329 | if (HAVE_NEWABI) |
252b5132 | 8330 | { |
90ecf173 | 8331 | if (!mips_big_got) |
f5040a92 | 8332 | { |
4d7206a2 | 8333 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8334 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8335 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 8336 | mips_gp_register); |
4d7206a2 | 8337 | relax_switch (); |
67c0d1eb RS |
8338 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8339 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
8340 | mips_gp_register); |
8341 | relax_end (); | |
f5040a92 AO |
8342 | } |
8343 | else | |
8344 | { | |
4d7206a2 | 8345 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8346 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8347 | BFD_RELOC_MIPS_CALL_HI16); |
8348 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8349 | PIC_CALL_REG, mips_gp_register); | |
8350 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8351 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8352 | PIC_CALL_REG); | |
4d7206a2 | 8353 | relax_switch (); |
67c0d1eb RS |
8354 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8355 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
8356 | mips_gp_register); | |
8357 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8358 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8359 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8360 | relax_end (); |
f5040a92 | 8361 | } |
684022ea | 8362 | |
df58fc94 | 8363 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8364 | } |
8365 | else | |
8366 | { | |
4d7206a2 | 8367 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8368 | if (!mips_big_got) |
438c16b8 | 8369 | { |
67c0d1eb RS |
8370 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8371 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8372 | mips_gp_register); |
269137b2 | 8373 | load_delay_nop (); |
4d7206a2 | 8374 | relax_switch (); |
438c16b8 | 8375 | } |
252b5132 | 8376 | else |
252b5132 | 8377 | { |
67c0d1eb RS |
8378 | int gpdelay; |
8379 | ||
8380 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8381 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8382 | BFD_RELOC_MIPS_CALL_HI16); |
8383 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8384 | PIC_CALL_REG, mips_gp_register); | |
8385 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8386 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8387 | PIC_CALL_REG); | |
269137b2 | 8388 | load_delay_nop (); |
4d7206a2 | 8389 | relax_switch (); |
67c0d1eb RS |
8390 | if (gpdelay) |
8391 | macro_build (NULL, "nop", ""); | |
252b5132 | 8392 | } |
67c0d1eb RS |
8393 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8394 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8395 | mips_gp_register); |
269137b2 | 8396 | load_delay_nop (); |
67c0d1eb RS |
8397 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8398 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8399 | relax_end (); |
df58fc94 | 8400 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8401 | |
6478892d TS |
8402 | if (mips_cprestore_offset < 0) |
8403 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8404 | else | |
8405 | { | |
90ecf173 | 8406 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8407 | { |
8408 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8409 | /* Quiet this warning. */ | |
8410 | mips_frame_reg_valid = 1; | |
8411 | } | |
90ecf173 | 8412 | if (!mips_cprestore_valid) |
7a621144 DJ |
8413 | { |
8414 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8415 | /* Quiet this warning. */ | |
8416 | mips_cprestore_valid = 1; | |
8417 | } | |
6478892d | 8418 | if (mips_opts.noreorder) |
67c0d1eb | 8419 | macro_build (NULL, "nop", ""); |
6478892d | 8420 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8421 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8422 | mips_gp_register, |
256ab948 TS |
8423 | mips_frame_reg, |
8424 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8425 | } |
252b5132 RH |
8426 | } |
8427 | } | |
0a44bf69 RS |
8428 | else if (mips_pic == VXWORKS_PIC) |
8429 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8430 | else |
8431 | abort (); | |
8432 | ||
8fc2e39e | 8433 | break; |
252b5132 | 8434 | |
7f3c4072 | 8435 | case M_LBUE_AB: |
7f3c4072 CM |
8436 | s = "lbue"; |
8437 | fmt = "t,+j(b)"; | |
8438 | offbits = 9; | |
8439 | goto ld_st; | |
8440 | case M_LHUE_AB: | |
7f3c4072 CM |
8441 | s = "lhue"; |
8442 | fmt = "t,+j(b)"; | |
8443 | offbits = 9; | |
8444 | goto ld_st; | |
8445 | case M_LBE_AB: | |
7f3c4072 CM |
8446 | s = "lbe"; |
8447 | fmt = "t,+j(b)"; | |
8448 | offbits = 9; | |
8449 | goto ld_st; | |
8450 | case M_LHE_AB: | |
7f3c4072 CM |
8451 | s = "lhe"; |
8452 | fmt = "t,+j(b)"; | |
8453 | offbits = 9; | |
8454 | goto ld_st; | |
8455 | case M_LLE_AB: | |
7f3c4072 CM |
8456 | s = "lle"; |
8457 | fmt = "t,+j(b)"; | |
8458 | offbits = 9; | |
8459 | goto ld_st; | |
8460 | case M_LWE_AB: | |
7f3c4072 CM |
8461 | s = "lwe"; |
8462 | fmt = "t,+j(b)"; | |
8463 | offbits = 9; | |
8464 | goto ld_st; | |
8465 | case M_LWLE_AB: | |
7f3c4072 CM |
8466 | s = "lwle"; |
8467 | fmt = "t,+j(b)"; | |
8468 | offbits = 9; | |
8469 | goto ld_st; | |
8470 | case M_LWRE_AB: | |
7f3c4072 CM |
8471 | s = "lwre"; |
8472 | fmt = "t,+j(b)"; | |
8473 | offbits = 9; | |
8474 | goto ld_st; | |
8475 | case M_SBE_AB: | |
7f3c4072 CM |
8476 | s = "sbe"; |
8477 | fmt = "t,+j(b)"; | |
8478 | offbits = 9; | |
8479 | goto ld_st; | |
8480 | case M_SCE_AB: | |
7f3c4072 CM |
8481 | s = "sce"; |
8482 | fmt = "t,+j(b)"; | |
8483 | offbits = 9; | |
8484 | goto ld_st; | |
8485 | case M_SHE_AB: | |
7f3c4072 CM |
8486 | s = "she"; |
8487 | fmt = "t,+j(b)"; | |
8488 | offbits = 9; | |
8489 | goto ld_st; | |
8490 | case M_SWE_AB: | |
7f3c4072 CM |
8491 | s = "swe"; |
8492 | fmt = "t,+j(b)"; | |
8493 | offbits = 9; | |
8494 | goto ld_st; | |
8495 | case M_SWLE_AB: | |
7f3c4072 CM |
8496 | s = "swle"; |
8497 | fmt = "t,+j(b)"; | |
8498 | offbits = 9; | |
8499 | goto ld_st; | |
8500 | case M_SWRE_AB: | |
7f3c4072 CM |
8501 | s = "swre"; |
8502 | fmt = "t,+j(b)"; | |
8503 | offbits = 9; | |
8504 | goto ld_st; | |
dec0624d | 8505 | case M_ACLR_AB: |
dec0624d MR |
8506 | s = "aclr"; |
8507 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8508 | fmt = "\\,~(b)"; | |
7f3c4072 | 8509 | offbits = 12; |
dec0624d MR |
8510 | goto ld_st; |
8511 | case M_ASET_AB: | |
dec0624d MR |
8512 | s = "aset"; |
8513 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8514 | fmt = "\\,~(b)"; | |
7f3c4072 | 8515 | offbits = 12; |
dec0624d | 8516 | goto ld_st; |
252b5132 RH |
8517 | case M_LB_AB: |
8518 | s = "lb"; | |
df58fc94 | 8519 | fmt = "t,o(b)"; |
252b5132 RH |
8520 | goto ld; |
8521 | case M_LBU_AB: | |
8522 | s = "lbu"; | |
df58fc94 | 8523 | fmt = "t,o(b)"; |
252b5132 RH |
8524 | goto ld; |
8525 | case M_LH_AB: | |
8526 | s = "lh"; | |
df58fc94 | 8527 | fmt = "t,o(b)"; |
252b5132 RH |
8528 | goto ld; |
8529 | case M_LHU_AB: | |
8530 | s = "lhu"; | |
df58fc94 | 8531 | fmt = "t,o(b)"; |
252b5132 RH |
8532 | goto ld; |
8533 | case M_LW_AB: | |
8534 | s = "lw"; | |
df58fc94 | 8535 | fmt = "t,o(b)"; |
252b5132 RH |
8536 | goto ld; |
8537 | case M_LWC0_AB: | |
df58fc94 | 8538 | gas_assert (!mips_opts.micromips); |
252b5132 | 8539 | s = "lwc0"; |
df58fc94 | 8540 | fmt = "E,o(b)"; |
bdaaa2e1 | 8541 | /* Itbl support may require additional care here. */ |
252b5132 | 8542 | coproc = 1; |
df58fc94 | 8543 | goto ld_st; |
252b5132 RH |
8544 | case M_LWC1_AB: |
8545 | s = "lwc1"; | |
df58fc94 | 8546 | fmt = "T,o(b)"; |
bdaaa2e1 | 8547 | /* Itbl support may require additional care here. */ |
252b5132 | 8548 | coproc = 1; |
df58fc94 | 8549 | goto ld_st; |
252b5132 RH |
8550 | case M_LWC2_AB: |
8551 | s = "lwc2"; | |
df58fc94 | 8552 | fmt = COP12_FMT; |
7f3c4072 | 8553 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8554 | /* Itbl support may require additional care here. */ |
252b5132 | 8555 | coproc = 1; |
df58fc94 | 8556 | goto ld_st; |
252b5132 | 8557 | case M_LWC3_AB: |
df58fc94 | 8558 | gas_assert (!mips_opts.micromips); |
252b5132 | 8559 | s = "lwc3"; |
df58fc94 | 8560 | fmt = "E,o(b)"; |
bdaaa2e1 | 8561 | /* Itbl support may require additional care here. */ |
252b5132 | 8562 | coproc = 1; |
df58fc94 | 8563 | goto ld_st; |
252b5132 RH |
8564 | case M_LWL_AB: |
8565 | s = "lwl"; | |
df58fc94 | 8566 | fmt = MEM12_FMT; |
7f3c4072 | 8567 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8568 | goto ld_st; |
252b5132 RH |
8569 | case M_LWR_AB: |
8570 | s = "lwr"; | |
df58fc94 | 8571 | fmt = MEM12_FMT; |
7f3c4072 | 8572 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8573 | goto ld_st; |
252b5132 | 8574 | case M_LDC1_AB: |
252b5132 | 8575 | s = "ldc1"; |
df58fc94 | 8576 | fmt = "T,o(b)"; |
bdaaa2e1 | 8577 | /* Itbl support may require additional care here. */ |
252b5132 | 8578 | coproc = 1; |
df58fc94 | 8579 | goto ld_st; |
252b5132 RH |
8580 | case M_LDC2_AB: |
8581 | s = "ldc2"; | |
df58fc94 | 8582 | fmt = COP12_FMT; |
7f3c4072 | 8583 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8584 | /* Itbl support may require additional care here. */ |
252b5132 | 8585 | coproc = 1; |
df58fc94 | 8586 | goto ld_st; |
c77c0862 | 8587 | case M_LQC2_AB: |
c77c0862 RS |
8588 | s = "lqc2"; |
8589 | fmt = "E,o(b)"; | |
8590 | /* Itbl support may require additional care here. */ | |
8591 | coproc = 1; | |
8592 | goto ld_st; | |
252b5132 RH |
8593 | case M_LDC3_AB: |
8594 | s = "ldc3"; | |
df58fc94 | 8595 | fmt = "E,o(b)"; |
bdaaa2e1 | 8596 | /* Itbl support may require additional care here. */ |
252b5132 | 8597 | coproc = 1; |
df58fc94 | 8598 | goto ld_st; |
252b5132 RH |
8599 | case M_LDL_AB: |
8600 | s = "ldl"; | |
df58fc94 | 8601 | fmt = MEM12_FMT; |
7f3c4072 | 8602 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8603 | goto ld_st; |
252b5132 RH |
8604 | case M_LDR_AB: |
8605 | s = "ldr"; | |
df58fc94 | 8606 | fmt = MEM12_FMT; |
7f3c4072 | 8607 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8608 | goto ld_st; |
252b5132 RH |
8609 | case M_LL_AB: |
8610 | s = "ll"; | |
df58fc94 | 8611 | fmt = MEM12_FMT; |
7f3c4072 | 8612 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8613 | goto ld; |
8614 | case M_LLD_AB: | |
8615 | s = "lld"; | |
df58fc94 | 8616 | fmt = MEM12_FMT; |
7f3c4072 | 8617 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8618 | goto ld; |
8619 | case M_LWU_AB: | |
8620 | s = "lwu"; | |
df58fc94 | 8621 | fmt = MEM12_FMT; |
7f3c4072 | 8622 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8623 | goto ld; |
8624 | case M_LWP_AB: | |
df58fc94 RS |
8625 | gas_assert (mips_opts.micromips); |
8626 | s = "lwp"; | |
8627 | fmt = "t,~(b)"; | |
7f3c4072 | 8628 | offbits = 12; |
df58fc94 RS |
8629 | lp = 1; |
8630 | goto ld; | |
8631 | case M_LDP_AB: | |
df58fc94 RS |
8632 | gas_assert (mips_opts.micromips); |
8633 | s = "ldp"; | |
8634 | fmt = "t,~(b)"; | |
7f3c4072 | 8635 | offbits = 12; |
df58fc94 RS |
8636 | lp = 1; |
8637 | goto ld; | |
8638 | case M_LWM_AB: | |
df58fc94 RS |
8639 | gas_assert (mips_opts.micromips); |
8640 | s = "lwm"; | |
8641 | fmt = "n,~(b)"; | |
7f3c4072 | 8642 | offbits = 12; |
df58fc94 RS |
8643 | goto ld_st; |
8644 | case M_LDM_AB: | |
df58fc94 RS |
8645 | gas_assert (mips_opts.micromips); |
8646 | s = "ldm"; | |
8647 | fmt = "n,~(b)"; | |
7f3c4072 | 8648 | offbits = 12; |
df58fc94 RS |
8649 | goto ld_st; |
8650 | ||
252b5132 | 8651 | ld: |
f19ccbda MR |
8652 | /* We don't want to use $0 as tempreg. */ |
8653 | if (breg == treg + lp || treg + lp == ZERO) | |
df58fc94 | 8654 | goto ld_st; |
252b5132 | 8655 | else |
df58fc94 RS |
8656 | tempreg = treg + lp; |
8657 | goto ld_noat; | |
8658 | ||
252b5132 RH |
8659 | case M_SB_AB: |
8660 | s = "sb"; | |
df58fc94 RS |
8661 | fmt = "t,o(b)"; |
8662 | goto ld_st; | |
252b5132 RH |
8663 | case M_SH_AB: |
8664 | s = "sh"; | |
df58fc94 RS |
8665 | fmt = "t,o(b)"; |
8666 | goto ld_st; | |
252b5132 RH |
8667 | case M_SW_AB: |
8668 | s = "sw"; | |
df58fc94 RS |
8669 | fmt = "t,o(b)"; |
8670 | goto ld_st; | |
252b5132 | 8671 | case M_SWC0_AB: |
df58fc94 | 8672 | gas_assert (!mips_opts.micromips); |
252b5132 | 8673 | s = "swc0"; |
df58fc94 | 8674 | fmt = "E,o(b)"; |
bdaaa2e1 | 8675 | /* Itbl support may require additional care here. */ |
252b5132 | 8676 | coproc = 1; |
df58fc94 | 8677 | goto ld_st; |
252b5132 RH |
8678 | case M_SWC1_AB: |
8679 | s = "swc1"; | |
df58fc94 | 8680 | fmt = "T,o(b)"; |
bdaaa2e1 | 8681 | /* Itbl support may require additional care here. */ |
252b5132 | 8682 | coproc = 1; |
df58fc94 | 8683 | goto ld_st; |
252b5132 RH |
8684 | case M_SWC2_AB: |
8685 | s = "swc2"; | |
df58fc94 | 8686 | fmt = COP12_FMT; |
7f3c4072 | 8687 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8688 | /* Itbl support may require additional care here. */ |
252b5132 | 8689 | coproc = 1; |
df58fc94 | 8690 | goto ld_st; |
252b5132 | 8691 | case M_SWC3_AB: |
df58fc94 | 8692 | gas_assert (!mips_opts.micromips); |
252b5132 | 8693 | s = "swc3"; |
df58fc94 | 8694 | fmt = "E,o(b)"; |
bdaaa2e1 | 8695 | /* Itbl support may require additional care here. */ |
252b5132 | 8696 | coproc = 1; |
df58fc94 | 8697 | goto ld_st; |
252b5132 RH |
8698 | case M_SWL_AB: |
8699 | s = "swl"; | |
df58fc94 | 8700 | fmt = MEM12_FMT; |
7f3c4072 | 8701 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8702 | goto ld_st; |
252b5132 RH |
8703 | case M_SWR_AB: |
8704 | s = "swr"; | |
df58fc94 | 8705 | fmt = MEM12_FMT; |
7f3c4072 | 8706 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8707 | goto ld_st; |
252b5132 RH |
8708 | case M_SC_AB: |
8709 | s = "sc"; | |
df58fc94 | 8710 | fmt = MEM12_FMT; |
7f3c4072 | 8711 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8712 | goto ld_st; |
252b5132 RH |
8713 | case M_SCD_AB: |
8714 | s = "scd"; | |
df58fc94 | 8715 | fmt = MEM12_FMT; |
7f3c4072 | 8716 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8717 | goto ld_st; |
d43b4baf TS |
8718 | case M_CACHE_AB: |
8719 | s = "cache"; | |
df58fc94 | 8720 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
7f3c4072 CM |
8721 | offbits = (mips_opts.micromips ? 12 : 16); |
8722 | goto ld_st; | |
8723 | case M_CACHEE_AB: | |
7f3c4072 CM |
8724 | s = "cachee"; |
8725 | fmt = "k,+j(b)"; | |
8726 | offbits = 9; | |
df58fc94 | 8727 | goto ld_st; |
3eebd5eb MR |
8728 | case M_PREF_AB: |
8729 | s = "pref"; | |
df58fc94 | 8730 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
7f3c4072 CM |
8731 | offbits = (mips_opts.micromips ? 12 : 16); |
8732 | goto ld_st; | |
8733 | case M_PREFE_AB: | |
7f3c4072 CM |
8734 | s = "prefe"; |
8735 | fmt = "k,+j(b)"; | |
8736 | offbits = 9; | |
df58fc94 | 8737 | goto ld_st; |
252b5132 | 8738 | case M_SDC1_AB: |
252b5132 | 8739 | s = "sdc1"; |
df58fc94 | 8740 | fmt = "T,o(b)"; |
252b5132 | 8741 | coproc = 1; |
bdaaa2e1 | 8742 | /* Itbl support may require additional care here. */ |
df58fc94 | 8743 | goto ld_st; |
252b5132 RH |
8744 | case M_SDC2_AB: |
8745 | s = "sdc2"; | |
df58fc94 | 8746 | fmt = COP12_FMT; |
7f3c4072 | 8747 | offbits = (mips_opts.micromips ? 12 : 16); |
c77c0862 RS |
8748 | /* Itbl support may require additional care here. */ |
8749 | coproc = 1; | |
8750 | goto ld_st; | |
8751 | case M_SQC2_AB: | |
c77c0862 RS |
8752 | s = "sqc2"; |
8753 | fmt = "E,o(b)"; | |
bdaaa2e1 | 8754 | /* Itbl support may require additional care here. */ |
252b5132 | 8755 | coproc = 1; |
df58fc94 | 8756 | goto ld_st; |
252b5132 | 8757 | case M_SDC3_AB: |
df58fc94 | 8758 | gas_assert (!mips_opts.micromips); |
252b5132 | 8759 | s = "sdc3"; |
df58fc94 | 8760 | fmt = "E,o(b)"; |
bdaaa2e1 | 8761 | /* Itbl support may require additional care here. */ |
252b5132 | 8762 | coproc = 1; |
df58fc94 | 8763 | goto ld_st; |
252b5132 RH |
8764 | case M_SDL_AB: |
8765 | s = "sdl"; | |
df58fc94 | 8766 | fmt = MEM12_FMT; |
7f3c4072 | 8767 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8768 | goto ld_st; |
252b5132 RH |
8769 | case M_SDR_AB: |
8770 | s = "sdr"; | |
df58fc94 | 8771 | fmt = MEM12_FMT; |
7f3c4072 | 8772 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8773 | goto ld_st; |
8774 | case M_SWP_AB: | |
df58fc94 RS |
8775 | gas_assert (mips_opts.micromips); |
8776 | s = "swp"; | |
8777 | fmt = "t,~(b)"; | |
7f3c4072 | 8778 | offbits = 12; |
df58fc94 RS |
8779 | goto ld_st; |
8780 | case M_SDP_AB: | |
df58fc94 RS |
8781 | gas_assert (mips_opts.micromips); |
8782 | s = "sdp"; | |
8783 | fmt = "t,~(b)"; | |
7f3c4072 | 8784 | offbits = 12; |
df58fc94 RS |
8785 | goto ld_st; |
8786 | case M_SWM_AB: | |
df58fc94 RS |
8787 | gas_assert (mips_opts.micromips); |
8788 | s = "swm"; | |
8789 | fmt = "n,~(b)"; | |
7f3c4072 | 8790 | offbits = 12; |
df58fc94 RS |
8791 | goto ld_st; |
8792 | case M_SDM_AB: | |
df58fc94 RS |
8793 | gas_assert (mips_opts.micromips); |
8794 | s = "sdm"; | |
8795 | fmt = "n,~(b)"; | |
7f3c4072 | 8796 | offbits = 12; |
df58fc94 RS |
8797 | |
8798 | ld_st: | |
8fc2e39e | 8799 | tempreg = AT; |
df58fc94 | 8800 | ld_noat: |
f2ae14a1 RS |
8801 | if (small_offset_p (0, align, 16)) |
8802 | { | |
8803 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
8804 | macros for o32 but which should act like normal instructions | |
8805 | otherwise. */ | |
8806 | if (offbits == 16) | |
8807 | macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0], | |
8808 | offset_reloc[1], offset_reloc[2], breg); | |
8809 | else if (small_offset_p (0, align, offbits)) | |
8810 | { | |
8811 | if (offbits == 0) | |
8812 | macro_build (NULL, s, fmt, treg, breg); | |
8813 | else | |
8814 | macro_build (NULL, s, fmt, treg, | |
c8276761 | 8815 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
8816 | } |
8817 | else | |
8818 | { | |
8819 | if (tempreg == AT) | |
8820 | used_at = 1; | |
8821 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8822 | tempreg, breg, -1, offset_reloc[0], | |
8823 | offset_reloc[1], offset_reloc[2]); | |
8824 | if (offbits == 0) | |
8825 | macro_build (NULL, s, fmt, treg, tempreg); | |
8826 | else | |
c8276761 | 8827 | macro_build (NULL, s, fmt, treg, 0, tempreg); |
f2ae14a1 RS |
8828 | } |
8829 | break; | |
8830 | } | |
8831 | ||
8832 | if (tempreg == AT) | |
8833 | used_at = 1; | |
8834 | ||
252b5132 RH |
8835 | if (offset_expr.X_op != O_constant |
8836 | && offset_expr.X_op != O_symbol) | |
8837 | { | |
f71d0d44 | 8838 | as_bad (_("Expression too complex")); |
252b5132 RH |
8839 | offset_expr.X_op = O_constant; |
8840 | } | |
8841 | ||
2051e8c4 MR |
8842 | if (HAVE_32BIT_ADDRESSES |
8843 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8844 | { |
8845 | char value [32]; | |
8846 | ||
8847 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8848 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8849 | } |
2051e8c4 | 8850 | |
252b5132 RH |
8851 | /* A constant expression in PIC code can be handled just as it |
8852 | is in non PIC code. */ | |
aed1a261 RS |
8853 | if (offset_expr.X_op == O_constant) |
8854 | { | |
f2ae14a1 RS |
8855 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
8856 | offbits == 0 ? 16 : offbits); | |
8857 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 8858 | |
f2ae14a1 RS |
8859 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8860 | if (breg != 0) | |
8861 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8862 | tempreg, tempreg, breg); | |
7f3c4072 | 8863 | if (offbits == 0) |
dd6a37e7 | 8864 | { |
f2ae14a1 | 8865 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 8866 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 8867 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
dd6a37e7 AP |
8868 | macro_build (NULL, s, fmt, treg, tempreg); |
8869 | } | |
7f3c4072 | 8870 | else if (offbits == 16) |
f2ae14a1 | 8871 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
df58fc94 | 8872 | else |
f2ae14a1 | 8873 | macro_build (NULL, s, fmt, treg, |
c8276761 | 8874 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 8875 | } |
7f3c4072 | 8876 | else if (offbits != 16) |
df58fc94 | 8877 | { |
7f3c4072 CM |
8878 | /* The offset field is too narrow to be used for a low-part |
8879 | relocation, so load the whole address into the auxillary | |
f2ae14a1 RS |
8880 | register. */ |
8881 | load_address (tempreg, &offset_expr, &used_at); | |
8882 | if (breg != 0) | |
8883 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8884 | tempreg, tempreg, breg); | |
7f3c4072 | 8885 | if (offbits == 0) |
dd6a37e7 AP |
8886 | macro_build (NULL, s, fmt, treg, tempreg); |
8887 | else | |
c8276761 | 8888 | macro_build (NULL, s, fmt, treg, 0, tempreg); |
aed1a261 RS |
8889 | } |
8890 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8891 | { |
8892 | /* If this is a reference to a GP relative symbol, and there | |
8893 | is no base register, we want | |
cdf6fd85 | 8894 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8895 | Otherwise, if there is no base register, we want |
8896 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8897 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8898 | If we have a constant, we need two instructions anyhow, | |
8899 | so we always use the latter form. | |
8900 | ||
8901 | If we have a base register, and this is a reference to a | |
8902 | GP relative symbol, we want | |
8903 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8904 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8905 | Otherwise we want |
8906 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8907 | addu $tempreg,$tempreg,$breg | |
8908 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8909 | With a constant we always use the latter case. |
76b3015f | 8910 | |
d6bc6245 TS |
8911 | With 64bit address space and no base register and $at usable, |
8912 | we want | |
8913 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8914 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8915 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8916 | dsll32 $tempreg,0 | |
8917 | daddu $tempreg,$at | |
8918 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8919 | If we have a base register, we want | |
8920 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8921 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8922 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8923 | daddu $at,$breg | |
8924 | dsll32 $tempreg,0 | |
8925 | daddu $tempreg,$at | |
8926 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8927 | ||
8928 | Without $at we can't generate the optimal path for superscalar | |
8929 | processors here since this would require two temporary registers. | |
8930 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8931 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8932 | dsll $tempreg,16 | |
8933 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8934 | dsll $tempreg,16 | |
8935 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8936 | If we have a base register, we want | |
8937 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8938 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8939 | dsll $tempreg,16 | |
8940 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8941 | dsll $tempreg,16 | |
8942 | daddu $tempreg,$tempreg,$breg | |
8943 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8944 | |
6caf9ef4 | 8945 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8946 | the same sequence as in 32bit address space. */ |
8947 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8948 | { |
aed1a261 | 8949 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8950 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8951 | { | |
8952 | relax_start (offset_expr.X_add_symbol); | |
8953 | if (breg == 0) | |
8954 | { | |
8955 | macro_build (&offset_expr, s, fmt, treg, | |
8956 | BFD_RELOC_GPREL16, mips_gp_register); | |
8957 | } | |
8958 | else | |
8959 | { | |
8960 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8961 | tempreg, breg, mips_gp_register); | |
8962 | macro_build (&offset_expr, s, fmt, treg, | |
8963 | BFD_RELOC_GPREL16, tempreg); | |
8964 | } | |
8965 | relax_switch (); | |
8966 | } | |
d6bc6245 | 8967 | |
741fe287 | 8968 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8969 | { |
df58fc94 | 8970 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8971 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8972 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8973 | BFD_RELOC_HI16_S); |
8974 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8975 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8976 | if (breg != 0) |
67c0d1eb | 8977 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8978 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8979 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8980 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8981 | tempreg); | |
d6bc6245 TS |
8982 | used_at = 1; |
8983 | } | |
8984 | else | |
8985 | { | |
df58fc94 | 8986 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8987 | BFD_RELOC_MIPS_HIGHEST); |
8988 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8989 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8990 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8991 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8992 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8993 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8994 | if (breg != 0) |
67c0d1eb | 8995 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8996 | tempreg, tempreg, breg); |
67c0d1eb | 8997 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8998 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8999 | } |
6caf9ef4 TS |
9000 | |
9001 | if (mips_relax.sequence) | |
9002 | relax_end (); | |
8fc2e39e | 9003 | break; |
d6bc6245 | 9004 | } |
256ab948 | 9005 | |
252b5132 RH |
9006 | if (breg == 0) |
9007 | { | |
67c0d1eb | 9008 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9009 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9010 | { |
4d7206a2 | 9011 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9012 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
9013 | mips_gp_register); | |
4d7206a2 | 9014 | relax_switch (); |
252b5132 | 9015 | } |
67c0d1eb RS |
9016 | macro_build_lui (&offset_expr, tempreg); |
9017 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 9018 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
9019 | if (mips_relax.sequence) |
9020 | relax_end (); | |
252b5132 RH |
9021 | } |
9022 | else | |
9023 | { | |
67c0d1eb | 9024 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9025 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9026 | { |
4d7206a2 | 9027 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 9028 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9029 | tempreg, breg, mips_gp_register); |
67c0d1eb | 9030 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9031 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 9032 | relax_switch (); |
252b5132 | 9033 | } |
67c0d1eb RS |
9034 | macro_build_lui (&offset_expr, tempreg); |
9035 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9036 | tempreg, tempreg, breg); |
67c0d1eb | 9037 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9038 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
9039 | if (mips_relax.sequence) |
9040 | relax_end (); | |
252b5132 RH |
9041 | } |
9042 | } | |
0a44bf69 | 9043 | else if (!mips_big_got) |
252b5132 | 9044 | { |
ed6fb7bd | 9045 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 9046 | |
252b5132 RH |
9047 | /* If this is a reference to an external symbol, we want |
9048 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9049 | nop | |
9050 | <op> $treg,0($tempreg) | |
9051 | Otherwise we want | |
9052 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9053 | nop | |
9054 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9055 | <op> $treg,0($tempreg) | |
f5040a92 AO |
9056 | |
9057 | For NewABI, we want | |
9058 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9059 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
9060 | ||
252b5132 RH |
9061 | If there is a base register, we add it to $tempreg before |
9062 | the <op>. If there is a constant, we stick it in the | |
9063 | <op> instruction. We don't handle constants larger than | |
9064 | 16 bits, because we have no way to load the upper 16 bits | |
9065 | (actually, we could handle them for the subset of cases | |
9066 | in which we are not using $at). */ | |
9c2799c2 | 9067 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
9068 | if (HAVE_NEWABI) |
9069 | { | |
67c0d1eb RS |
9070 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9071 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9072 | if (breg != 0) |
67c0d1eb | 9073 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9074 | tempreg, tempreg, breg); |
67c0d1eb | 9075 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9076 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
9077 | break; |
9078 | } | |
252b5132 RH |
9079 | expr1.X_add_number = offset_expr.X_add_number; |
9080 | offset_expr.X_add_number = 0; | |
9081 | if (expr1.X_add_number < -0x8000 | |
9082 | || expr1.X_add_number >= 0x8000) | |
9083 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
9084 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9085 | lw_reloc_type, mips_gp_register); | |
269137b2 | 9086 | load_delay_nop (); |
4d7206a2 RS |
9087 | relax_start (offset_expr.X_add_symbol); |
9088 | relax_switch (); | |
67c0d1eb RS |
9089 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9090 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 9091 | relax_end (); |
252b5132 | 9092 | if (breg != 0) |
67c0d1eb | 9093 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9094 | tempreg, tempreg, breg); |
67c0d1eb | 9095 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9096 | } |
0a44bf69 | 9097 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 9098 | { |
67c0d1eb | 9099 | int gpdelay; |
252b5132 RH |
9100 | |
9101 | /* If this is a reference to an external symbol, we want | |
9102 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9103 | addu $tempreg,$tempreg,$gp | |
9104 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9105 | <op> $treg,0($tempreg) | |
9106 | Otherwise we want | |
9107 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9108 | nop | |
9109 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9110 | <op> $treg,0($tempreg) | |
9111 | If there is a base register, we add it to $tempreg before | |
9112 | the <op>. If there is a constant, we stick it in the | |
9113 | <op> instruction. We don't handle constants larger than | |
9114 | 16 bits, because we have no way to load the upper 16 bits | |
9115 | (actually, we could handle them for the subset of cases | |
f5040a92 | 9116 | in which we are not using $at). */ |
9c2799c2 | 9117 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
9118 | expr1.X_add_number = offset_expr.X_add_number; |
9119 | offset_expr.X_add_number = 0; | |
9120 | if (expr1.X_add_number < -0x8000 | |
9121 | || expr1.X_add_number >= 0x8000) | |
9122 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9123 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9124 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9125 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9126 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9127 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9128 | mips_gp_register); | |
9129 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9130 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 9131 | relax_switch (); |
67c0d1eb RS |
9132 | if (gpdelay) |
9133 | macro_build (NULL, "nop", ""); | |
9134 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9135 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9136 | load_delay_nop (); |
67c0d1eb RS |
9137 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9138 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9139 | relax_end (); |
9140 | ||
252b5132 | 9141 | if (breg != 0) |
67c0d1eb | 9142 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9143 | tempreg, tempreg, breg); |
67c0d1eb | 9144 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9145 | } |
0a44bf69 | 9146 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 9147 | { |
f5040a92 AO |
9148 | /* If this is a reference to an external symbol, we want |
9149 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9150 | add $tempreg,$tempreg,$gp | |
9151 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9152 | <op> $treg,<ofst>($tempreg) | |
9153 | Otherwise, for local symbols, we want: | |
9154 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9155 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 9156 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 9157 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
9158 | offset_expr.X_add_number = 0; |
9159 | if (expr1.X_add_number < -0x8000 | |
9160 | || expr1.X_add_number >= 0x8000) | |
9161 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 9162 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9163 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9164 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9165 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9166 | mips_gp_register); | |
9167 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9168 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 9169 | if (breg != 0) |
67c0d1eb | 9170 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9171 | tempreg, tempreg, breg); |
67c0d1eb | 9172 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 9173 | |
4d7206a2 | 9174 | relax_switch (); |
f5040a92 | 9175 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
9176 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9177 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9178 | if (breg != 0) |
67c0d1eb | 9179 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9180 | tempreg, tempreg, breg); |
67c0d1eb | 9181 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9182 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 9183 | relax_end (); |
f5040a92 | 9184 | } |
252b5132 RH |
9185 | else |
9186 | abort (); | |
9187 | ||
252b5132 RH |
9188 | break; |
9189 | ||
833794fc MR |
9190 | case M_JRADDIUSP: |
9191 | gas_assert (mips_opts.micromips); | |
9192 | gas_assert (mips_opts.insn32); | |
9193 | start_noreorder (); | |
9194 | macro_build (NULL, "jr", "s", RA); | |
9195 | expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2; | |
9196 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); | |
9197 | end_noreorder (); | |
9198 | break; | |
9199 | ||
9200 | case M_JRC: | |
9201 | gas_assert (mips_opts.micromips); | |
9202 | gas_assert (mips_opts.insn32); | |
9203 | macro_build (NULL, "jr", "s", sreg); | |
9204 | if (mips_opts.noreorder) | |
9205 | macro_build (NULL, "nop", ""); | |
9206 | break; | |
9207 | ||
252b5132 RH |
9208 | case M_LI: |
9209 | case M_LI_S: | |
67c0d1eb | 9210 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 9211 | break; |
252b5132 RH |
9212 | |
9213 | case M_DLI: | |
67c0d1eb | 9214 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 9215 | break; |
252b5132 RH |
9216 | |
9217 | case M_LI_SS: | |
9218 | if (imm_expr.X_op == O_constant) | |
9219 | { | |
8fc2e39e | 9220 | used_at = 1; |
67c0d1eb RS |
9221 | load_register (AT, &imm_expr, 0); |
9222 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9223 | break; |
9224 | } | |
9225 | else | |
9226 | { | |
9c2799c2 | 9227 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
9228 | && strcmp (segment_name (S_GET_SEGMENT |
9229 | (offset_expr.X_add_symbol)), | |
9230 | ".lit4") == 0 | |
9231 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 9232 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 9233 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9234 | break; |
252b5132 RH |
9235 | } |
9236 | ||
9237 | case M_LI_D: | |
ca4e0257 RS |
9238 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
9239 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
9240 | order 32 bits of the value and the low order 32 bits are either | |
9241 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
9242 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9243 | { | |
ca4e0257 | 9244 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 9245 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
9246 | else |
9247 | { | |
9248 | int hreg, lreg; | |
9249 | ||
9250 | if (target_big_endian) | |
9251 | { | |
9252 | hreg = treg; | |
9253 | lreg = treg + 1; | |
9254 | } | |
9255 | else | |
9256 | { | |
9257 | hreg = treg + 1; | |
9258 | lreg = treg; | |
9259 | } | |
9260 | ||
9261 | if (hreg <= 31) | |
67c0d1eb | 9262 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
9263 | if (lreg <= 31) |
9264 | { | |
9265 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 9266 | move_register (lreg, 0); |
252b5132 RH |
9267 | else |
9268 | { | |
9c2799c2 | 9269 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 9270 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
9271 | } |
9272 | } | |
9273 | } | |
8fc2e39e | 9274 | break; |
252b5132 RH |
9275 | } |
9276 | ||
9277 | /* We know that sym is in the .rdata section. First we get the | |
9278 | upper 16 bits of the address. */ | |
9279 | if (mips_pic == NO_PIC) | |
9280 | { | |
67c0d1eb | 9281 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 9282 | used_at = 1; |
252b5132 | 9283 | } |
0a44bf69 | 9284 | else |
252b5132 | 9285 | { |
67c0d1eb RS |
9286 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9287 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 9288 | used_at = 1; |
252b5132 | 9289 | } |
bdaaa2e1 | 9290 | |
252b5132 | 9291 | /* Now we load the register(s). */ |
ca4e0257 | 9292 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
9293 | { |
9294 | used_at = 1; | |
9295 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
9296 | } | |
252b5132 RH |
9297 | else |
9298 | { | |
8fc2e39e | 9299 | used_at = 1; |
67c0d1eb | 9300 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 9301 | if (treg != RA) |
252b5132 RH |
9302 | { |
9303 | /* FIXME: How in the world do we deal with the possible | |
9304 | overflow here? */ | |
9305 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9306 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 9307 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
9308 | } |
9309 | } | |
252b5132 RH |
9310 | break; |
9311 | ||
9312 | case M_LI_DD: | |
ca4e0257 RS |
9313 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
9314 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
9315 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
9316 | the value and the low order 32 bits are either zero or in | |
9317 | OFFSET_EXPR. */ | |
252b5132 RH |
9318 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9319 | { | |
8fc2e39e | 9320 | used_at = 1; |
67c0d1eb | 9321 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
9322 | if (HAVE_64BIT_FPRS) |
9323 | { | |
9c2799c2 | 9324 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 9325 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 9326 | } |
252b5132 RH |
9327 | else |
9328 | { | |
67c0d1eb | 9329 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 9330 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 9331 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
9332 | else |
9333 | { | |
9c2799c2 | 9334 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
9335 | load_register (AT, &offset_expr, 0); |
9336 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9337 | } |
9338 | } | |
9339 | break; | |
9340 | } | |
9341 | ||
9c2799c2 | 9342 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 9343 | && offset_expr.X_add_number == 0); |
252b5132 RH |
9344 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
9345 | if (strcmp (s, ".lit8") == 0) | |
f2ae14a1 RS |
9346 | { |
9347 | breg = mips_gp_register; | |
9348 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; | |
9349 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9350 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9351 | } |
9352 | else | |
9353 | { | |
9c2799c2 | 9354 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 9355 | used_at = 1; |
0a44bf69 | 9356 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
9357 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9358 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
9359 | else |
9360 | { | |
9361 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 9362 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9363 | } |
bdaaa2e1 | 9364 | |
252b5132 | 9365 | breg = AT; |
f2ae14a1 RS |
9366 | offset_reloc[0] = BFD_RELOC_LO16; |
9367 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9368 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
9369 | } | |
9370 | align = 8; | |
9371 | /* Fall through */ | |
c4a68bea | 9372 | |
252b5132 RH |
9373 | case M_L_DAB: |
9374 | /* | |
9375 | * The MIPS assembler seems to check for X_add_number not | |
9376 | * being double aligned and generating: | |
9377 | * lui at,%hi(foo+1) | |
9378 | * addu at,at,v1 | |
9379 | * addiu at,at,%lo(foo+1) | |
9380 | * lwc1 f2,0(at) | |
9381 | * lwc1 f3,4(at) | |
9382 | * But, the resulting address is the same after relocation so why | |
9383 | * generate the extra instruction? | |
9384 | */ | |
bdaaa2e1 | 9385 | /* Itbl support may require additional care here. */ |
252b5132 | 9386 | coproc = 1; |
df58fc94 | 9387 | fmt = "T,o(b)"; |
0aa27725 | 9388 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9389 | { |
9390 | s = "ldc1"; | |
df58fc94 | 9391 | goto ld_st; |
252b5132 | 9392 | } |
252b5132 | 9393 | s = "lwc1"; |
252b5132 RH |
9394 | goto ldd_std; |
9395 | ||
9396 | case M_S_DAB: | |
df58fc94 RS |
9397 | gas_assert (!mips_opts.micromips); |
9398 | /* Itbl support may require additional care here. */ | |
9399 | coproc = 1; | |
9400 | fmt = "T,o(b)"; | |
0aa27725 | 9401 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9402 | { |
9403 | s = "sdc1"; | |
df58fc94 | 9404 | goto ld_st; |
252b5132 | 9405 | } |
252b5132 | 9406 | s = "swc1"; |
252b5132 RH |
9407 | goto ldd_std; |
9408 | ||
e407c74b NC |
9409 | case M_LQ_AB: |
9410 | fmt = "t,o(b)"; | |
9411 | s = "lq"; | |
9412 | goto ld; | |
9413 | ||
9414 | case M_SQ_AB: | |
9415 | fmt = "t,o(b)"; | |
9416 | s = "sq"; | |
9417 | goto ld_st; | |
9418 | ||
252b5132 | 9419 | case M_LD_AB: |
df58fc94 | 9420 | fmt = "t,o(b)"; |
ca4e0257 | 9421 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9422 | { |
9423 | s = "ld"; | |
9424 | goto ld; | |
9425 | } | |
252b5132 | 9426 | s = "lw"; |
252b5132 RH |
9427 | goto ldd_std; |
9428 | ||
9429 | case M_SD_AB: | |
df58fc94 | 9430 | fmt = "t,o(b)"; |
ca4e0257 | 9431 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9432 | { |
9433 | s = "sd"; | |
df58fc94 | 9434 | goto ld_st; |
252b5132 | 9435 | } |
252b5132 | 9436 | s = "sw"; |
252b5132 RH |
9437 | |
9438 | ldd_std: | |
f2ae14a1 RS |
9439 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9440 | to adjust when loading from memory. We set coproc if we must | |
9441 | load $fn+1 first. */ | |
9442 | /* Itbl support may require additional care here. */ | |
9443 | if (!target_big_endian) | |
9444 | coproc = 0; | |
9445 | ||
9446 | if (small_offset_p (0, align, 16)) | |
9447 | { | |
9448 | ep = &offset_expr; | |
9449 | if (!small_offset_p (4, align, 16)) | |
9450 | { | |
9451 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
9452 | -1, offset_reloc[0], offset_reloc[1], | |
9453 | offset_reloc[2]); | |
9454 | expr1.X_add_number = 0; | |
9455 | ep = &expr1; | |
9456 | breg = AT; | |
9457 | used_at = 1; | |
9458 | offset_reloc[0] = BFD_RELOC_LO16; | |
9459 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9460 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
9461 | } | |
9462 | if (strcmp (s, "lw") == 0 && treg == breg) | |
9463 | { | |
9464 | ep->X_add_number += 4; | |
9465 | macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0], | |
9466 | offset_reloc[1], offset_reloc[2], breg); | |
9467 | ep->X_add_number -= 4; | |
9468 | macro_build (ep, s, fmt, treg, -1, offset_reloc[0], | |
9469 | offset_reloc[1], offset_reloc[2], breg); | |
9470 | } | |
9471 | else | |
9472 | { | |
9473 | macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1, | |
9474 | offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9475 | breg); | |
9476 | ep->X_add_number += 4; | |
9477 | macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1, | |
9478 | offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9479 | breg); | |
9480 | } | |
9481 | break; | |
9482 | } | |
9483 | ||
252b5132 RH |
9484 | if (offset_expr.X_op != O_symbol |
9485 | && offset_expr.X_op != O_constant) | |
9486 | { | |
f71d0d44 | 9487 | as_bad (_("Expression too complex")); |
252b5132 RH |
9488 | offset_expr.X_op = O_constant; |
9489 | } | |
9490 | ||
2051e8c4 MR |
9491 | if (HAVE_32BIT_ADDRESSES |
9492 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9493 | { |
9494 | char value [32]; | |
9495 | ||
9496 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9497 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9498 | } |
2051e8c4 | 9499 | |
90ecf173 | 9500 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9501 | { |
9502 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9503 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9504 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9505 | If we have a base register, we use this |
9506 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9507 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9508 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9509 | If this is not a GP relative symbol, we want |
9510 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9511 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9512 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9513 | If there is a base register, we add it to $at after the | |
9514 | lui instruction. If there is a constant, we always use | |
9515 | the last case. */ | |
39a59cf8 MR |
9516 | if (offset_expr.X_op == O_symbol |
9517 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9518 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9519 | { |
4d7206a2 | 9520 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9521 | if (breg == 0) |
9522 | { | |
c9914766 | 9523 | tempreg = mips_gp_register; |
252b5132 RH |
9524 | } |
9525 | else | |
9526 | { | |
67c0d1eb | 9527 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9528 | AT, breg, mips_gp_register); |
252b5132 | 9529 | tempreg = AT; |
252b5132 RH |
9530 | used_at = 1; |
9531 | } | |
9532 | ||
beae10d5 | 9533 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9534 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9535 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9536 | offset_expr.X_add_number += 4; |
9537 | ||
9538 | /* Set mips_optimize to 2 to avoid inserting an | |
9539 | undesired nop. */ | |
9540 | hold_mips_optimize = mips_optimize; | |
9541 | mips_optimize = 2; | |
beae10d5 | 9542 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9543 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9544 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9545 | mips_optimize = hold_mips_optimize; |
9546 | ||
4d7206a2 | 9547 | relax_switch (); |
252b5132 | 9548 | |
0970e49e | 9549 | offset_expr.X_add_number -= 4; |
252b5132 | 9550 | } |
8fc2e39e | 9551 | used_at = 1; |
f2ae14a1 RS |
9552 | if (offset_high_part (offset_expr.X_add_number, 16) |
9553 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
9554 | { | |
9555 | load_address (AT, &offset_expr, &used_at); | |
9556 | offset_expr.X_op = O_constant; | |
9557 | offset_expr.X_add_number = 0; | |
9558 | } | |
9559 | else | |
9560 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 9561 | if (breg != 0) |
67c0d1eb | 9562 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9563 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9564 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9565 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9566 | /* FIXME: How do we handle overflow here? */ |
9567 | offset_expr.X_add_number += 4; | |
beae10d5 | 9568 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9569 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9570 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9571 | if (mips_relax.sequence) |
9572 | relax_end (); | |
bdaaa2e1 | 9573 | } |
0a44bf69 | 9574 | else if (!mips_big_got) |
252b5132 | 9575 | { |
252b5132 RH |
9576 | /* If this is a reference to an external symbol, we want |
9577 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9578 | nop | |
9579 | <op> $treg,0($at) | |
9580 | <op> $treg+1,4($at) | |
9581 | Otherwise we want | |
9582 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9583 | nop | |
9584 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9585 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9586 | If there is a base register we add it to $at before the | |
9587 | lwc1 instructions. If there is a constant we include it | |
9588 | in the lwc1 instructions. */ | |
9589 | used_at = 1; | |
9590 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9591 | if (expr1.X_add_number < -0x8000 |
9592 | || expr1.X_add_number >= 0x8000 - 4) | |
9593 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9594 | load_got_offset (AT, &offset_expr); |
269137b2 | 9595 | load_delay_nop (); |
252b5132 | 9596 | if (breg != 0) |
67c0d1eb | 9597 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9598 | |
9599 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9600 | nop. */ | |
9601 | hold_mips_optimize = mips_optimize; | |
9602 | mips_optimize = 2; | |
4d7206a2 | 9603 | |
beae10d5 | 9604 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9605 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9606 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9607 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9608 | expr1.X_add_number += 4; |
67c0d1eb RS |
9609 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9610 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9611 | relax_switch (); |
67c0d1eb RS |
9612 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9613 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9614 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9615 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9616 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9617 | relax_end (); |
252b5132 | 9618 | |
4d7206a2 | 9619 | mips_optimize = hold_mips_optimize; |
252b5132 | 9620 | } |
0a44bf69 | 9621 | else if (mips_big_got) |
252b5132 | 9622 | { |
67c0d1eb | 9623 | int gpdelay; |
252b5132 RH |
9624 | |
9625 | /* If this is a reference to an external symbol, we want | |
9626 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9627 | addu $at,$at,$gp | |
9628 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9629 | nop | |
9630 | <op> $treg,0($at) | |
9631 | <op> $treg+1,4($at) | |
9632 | Otherwise we want | |
9633 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9634 | nop | |
9635 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9636 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9637 | If there is a base register we add it to $at before the | |
9638 | lwc1 instructions. If there is a constant we include it | |
9639 | in the lwc1 instructions. */ | |
9640 | used_at = 1; | |
9641 | expr1.X_add_number = offset_expr.X_add_number; | |
9642 | offset_expr.X_add_number = 0; | |
9643 | if (expr1.X_add_number < -0x8000 | |
9644 | || expr1.X_add_number >= 0x8000 - 4) | |
9645 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9646 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9647 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9648 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9649 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9650 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9651 | AT, AT, mips_gp_register); |
67c0d1eb | 9652 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9653 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9654 | load_delay_nop (); |
252b5132 | 9655 | if (breg != 0) |
67c0d1eb | 9656 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9657 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9658 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9659 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9660 | expr1.X_add_number += 4; |
9661 | ||
9662 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9663 | nop. */ | |
9664 | hold_mips_optimize = mips_optimize; | |
9665 | mips_optimize = 2; | |
beae10d5 | 9666 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9667 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9668 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9669 | mips_optimize = hold_mips_optimize; |
9670 | expr1.X_add_number -= 4; | |
9671 | ||
4d7206a2 RS |
9672 | relax_switch (); |
9673 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9674 | if (gpdelay) |
9675 | macro_build (NULL, "nop", ""); | |
9676 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9677 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9678 | load_delay_nop (); |
252b5132 | 9679 | if (breg != 0) |
67c0d1eb | 9680 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9681 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9682 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9683 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9684 | offset_expr.X_add_number += 4; |
252b5132 RH |
9685 | |
9686 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9687 | nop. */ | |
9688 | hold_mips_optimize = mips_optimize; | |
9689 | mips_optimize = 2; | |
beae10d5 | 9690 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9691 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9692 | BFD_RELOC_LO16, AT); | |
252b5132 | 9693 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9694 | relax_end (); |
252b5132 | 9695 | } |
252b5132 RH |
9696 | else |
9697 | abort (); | |
9698 | ||
252b5132 | 9699 | break; |
dd6a37e7 AP |
9700 | |
9701 | case M_SAA_AB: | |
dd6a37e7 | 9702 | s = "saa"; |
7f3c4072 | 9703 | offbits = 0; |
dd6a37e7 AP |
9704 | fmt = "t,(b)"; |
9705 | goto ld_st; | |
9706 | case M_SAAD_AB: | |
dd6a37e7 | 9707 | s = "saad"; |
7f3c4072 | 9708 | offbits = 0; |
dd6a37e7 AP |
9709 | fmt = "t,(b)"; |
9710 | goto ld_st; | |
9711 | ||
252b5132 RH |
9712 | /* New code added to support COPZ instructions. |
9713 | This code builds table entries out of the macros in mip_opcodes. | |
9714 | R4000 uses interlocks to handle coproc delays. | |
9715 | Other chips (like the R3000) require nops to be inserted for delays. | |
9716 | ||
f72c8c98 | 9717 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9718 | In order to fill delay slots for non-interlocked chips, |
9719 | we must have a way to specify delays based on the coprocessor. | |
9720 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9721 | What are the side-effects of the cop instruction? | |
9722 | What cache support might we have and what are its effects? | |
9723 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9724 | What registers are read/set/modified? |
252b5132 RH |
9725 | |
9726 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9727 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9728 | |
9729 | case M_COP0: | |
9730 | s = "c0"; | |
9731 | goto copz; | |
9732 | case M_COP1: | |
9733 | s = "c1"; | |
9734 | goto copz; | |
9735 | case M_COP2: | |
9736 | s = "c2"; | |
9737 | goto copz; | |
9738 | case M_COP3: | |
9739 | s = "c3"; | |
9740 | copz: | |
df58fc94 | 9741 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9742 | /* For now we just do C (same as Cz). The parameter will be |
9743 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 9744 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 9745 | break; |
252b5132 | 9746 | |
ea1fb5dc | 9747 | case M_MOVE: |
67c0d1eb | 9748 | move_register (dreg, sreg); |
8fc2e39e | 9749 | break; |
ea1fb5dc | 9750 | |
833794fc MR |
9751 | case M_MOVEP: |
9752 | gas_assert (mips_opts.micromips); | |
9753 | gas_assert (mips_opts.insn32); | |
e76ff5ab RS |
9754 | dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)]; |
9755 | breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)]; | |
833794fc MR |
9756 | sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; |
9757 | treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
9758 | move_register (dreg, sreg); | |
9759 | move_register (breg, treg); | |
9760 | break; | |
9761 | ||
252b5132 RH |
9762 | case M_DMUL: |
9763 | dbl = 1; | |
9764 | case M_MUL: | |
e407c74b NC |
9765 | if (mips_opts.arch == CPU_R5900) |
9766 | { | |
9767 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9768 | } | |
9769 | else | |
9770 | { | |
67c0d1eb | 9771 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9772 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9773 | } |
8fc2e39e | 9774 | break; |
252b5132 RH |
9775 | |
9776 | case M_DMUL_I: | |
9777 | dbl = 1; | |
9778 | case M_MUL_I: | |
9779 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9780 | not trying to be that fancy. GCC should do this for us | |
9781 | anyway. */ | |
8fc2e39e | 9782 | used_at = 1; |
67c0d1eb RS |
9783 | load_register (AT, &imm_expr, dbl); |
9784 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9785 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9786 | break; |
9787 | ||
9788 | case M_DMULO_I: | |
9789 | dbl = 1; | |
9790 | case M_MULO_I: | |
9791 | imm = 1; | |
9792 | goto do_mulo; | |
9793 | ||
9794 | case M_DMULO: | |
9795 | dbl = 1; | |
9796 | case M_MULO: | |
9797 | do_mulo: | |
7d10b47d | 9798 | start_noreorder (); |
8fc2e39e | 9799 | used_at = 1; |
252b5132 | 9800 | if (imm) |
67c0d1eb RS |
9801 | load_register (AT, &imm_expr, dbl); |
9802 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9803 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9804 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9805 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9806 | if (mips_trap) |
df58fc94 | 9807 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9808 | else |
9809 | { | |
df58fc94 RS |
9810 | if (mips_opts.micromips) |
9811 | micromips_label_expr (&label_expr); | |
9812 | else | |
9813 | label_expr.X_add_number = 8; | |
9814 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9815 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9816 | macro_build (NULL, "break", BRK_FMT, 6); |
9817 | if (mips_opts.micromips) | |
9818 | micromips_add_label (); | |
252b5132 | 9819 | } |
7d10b47d | 9820 | end_noreorder (); |
df58fc94 | 9821 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9822 | break; |
9823 | ||
9824 | case M_DMULOU_I: | |
9825 | dbl = 1; | |
9826 | case M_MULOU_I: | |
9827 | imm = 1; | |
9828 | goto do_mulou; | |
9829 | ||
9830 | case M_DMULOU: | |
9831 | dbl = 1; | |
9832 | case M_MULOU: | |
9833 | do_mulou: | |
7d10b47d | 9834 | start_noreorder (); |
8fc2e39e | 9835 | used_at = 1; |
252b5132 | 9836 | if (imm) |
67c0d1eb RS |
9837 | load_register (AT, &imm_expr, dbl); |
9838 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9839 | sreg, imm ? AT : treg); |
df58fc94 RS |
9840 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9841 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9842 | if (mips_trap) |
df58fc94 | 9843 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9844 | else |
9845 | { | |
df58fc94 RS |
9846 | if (mips_opts.micromips) |
9847 | micromips_label_expr (&label_expr); | |
9848 | else | |
9849 | label_expr.X_add_number = 8; | |
9850 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9851 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9852 | macro_build (NULL, "break", BRK_FMT, 6); |
9853 | if (mips_opts.micromips) | |
9854 | micromips_add_label (); | |
252b5132 | 9855 | } |
7d10b47d | 9856 | end_noreorder (); |
252b5132 RH |
9857 | break; |
9858 | ||
771c7ce4 | 9859 | case M_DROL: |
fef14a42 | 9860 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9861 | { |
9862 | if (dreg == sreg) | |
9863 | { | |
9864 | tempreg = AT; | |
9865 | used_at = 1; | |
9866 | } | |
9867 | else | |
9868 | { | |
9869 | tempreg = dreg; | |
82dd0097 | 9870 | } |
67c0d1eb RS |
9871 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9872 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9873 | break; |
82dd0097 | 9874 | } |
8fc2e39e | 9875 | used_at = 1; |
c80c840e | 9876 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9877 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9878 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9879 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9880 | break; |
9881 | ||
252b5132 | 9882 | case M_ROL: |
fef14a42 | 9883 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9884 | { |
9885 | if (dreg == sreg) | |
9886 | { | |
9887 | tempreg = AT; | |
9888 | used_at = 1; | |
9889 | } | |
9890 | else | |
9891 | { | |
9892 | tempreg = dreg; | |
82dd0097 | 9893 | } |
67c0d1eb RS |
9894 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9895 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9896 | break; |
82dd0097 | 9897 | } |
8fc2e39e | 9898 | used_at = 1; |
c80c840e | 9899 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9900 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9901 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9902 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9903 | break; |
9904 | ||
771c7ce4 TS |
9905 | case M_DROL_I: |
9906 | { | |
9907 | unsigned int rot; | |
91d6fa6a NC |
9908 | char *l; |
9909 | char *rr; | |
771c7ce4 TS |
9910 | |
9911 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9912 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9913 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9914 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9915 | { |
9916 | rot = (64 - rot) & 0x3f; | |
9917 | if (rot >= 32) | |
df58fc94 | 9918 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9919 | else |
df58fc94 | 9920 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9921 | break; |
60b63b72 | 9922 | } |
483fc7cd | 9923 | if (rot == 0) |
483fc7cd | 9924 | { |
df58fc94 | 9925 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9926 | break; |
483fc7cd | 9927 | } |
82dd0097 | 9928 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9929 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9930 | rot &= 0x1f; |
8fc2e39e | 9931 | used_at = 1; |
df58fc94 RS |
9932 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9933 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9934 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9935 | } |
9936 | break; | |
9937 | ||
252b5132 | 9938 | case M_ROL_I: |
771c7ce4 TS |
9939 | { |
9940 | unsigned int rot; | |
9941 | ||
9942 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9943 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9944 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9945 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9946 | { |
df58fc94 | 9947 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9948 | break; |
60b63b72 | 9949 | } |
483fc7cd | 9950 | if (rot == 0) |
483fc7cd | 9951 | { |
df58fc94 | 9952 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9953 | break; |
483fc7cd | 9954 | } |
8fc2e39e | 9955 | used_at = 1; |
df58fc94 RS |
9956 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9957 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9958 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9959 | } |
9960 | break; | |
9961 | ||
9962 | case M_DROR: | |
fef14a42 | 9963 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9964 | { |
67c0d1eb | 9965 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9966 | break; |
82dd0097 | 9967 | } |
8fc2e39e | 9968 | used_at = 1; |
c80c840e | 9969 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9970 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9971 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9972 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9973 | break; |
9974 | ||
9975 | case M_ROR: | |
fef14a42 | 9976 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9977 | { |
67c0d1eb | 9978 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9979 | break; |
82dd0097 | 9980 | } |
8fc2e39e | 9981 | used_at = 1; |
c80c840e | 9982 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9983 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9984 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9985 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9986 | break; |
9987 | ||
771c7ce4 TS |
9988 | case M_DROR_I: |
9989 | { | |
9990 | unsigned int rot; | |
91d6fa6a NC |
9991 | char *l; |
9992 | char *rr; | |
771c7ce4 TS |
9993 | |
9994 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9995 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9996 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9997 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9998 | { |
9999 | if (rot >= 32) | |
df58fc94 | 10000 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 10001 | else |
df58fc94 | 10002 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 10003 | break; |
82dd0097 | 10004 | } |
483fc7cd | 10005 | if (rot == 0) |
483fc7cd | 10006 | { |
df58fc94 | 10007 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 10008 | break; |
483fc7cd | 10009 | } |
91d6fa6a | 10010 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
10011 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
10012 | rot &= 0x1f; | |
8fc2e39e | 10013 | used_at = 1; |
df58fc94 RS |
10014 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
10015 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 10016 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
10017 | } |
10018 | break; | |
10019 | ||
252b5132 | 10020 | case M_ROR_I: |
771c7ce4 TS |
10021 | { |
10022 | unsigned int rot; | |
10023 | ||
10024 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 10025 | as_bad (_("Improper rotate count")); |
771c7ce4 | 10026 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 10027 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 10028 | { |
df58fc94 | 10029 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 10030 | break; |
82dd0097 | 10031 | } |
483fc7cd | 10032 | if (rot == 0) |
483fc7cd | 10033 | { |
df58fc94 | 10034 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 10035 | break; |
483fc7cd | 10036 | } |
8fc2e39e | 10037 | used_at = 1; |
df58fc94 RS |
10038 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
10039 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 10040 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 10041 | } |
252b5132 RH |
10042 | break; |
10043 | ||
252b5132 RH |
10044 | case M_SEQ: |
10045 | if (sreg == 0) | |
67c0d1eb | 10046 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 10047 | else if (treg == 0) |
67c0d1eb | 10048 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10049 | else |
10050 | { | |
67c0d1eb RS |
10051 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10052 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 10053 | } |
8fc2e39e | 10054 | break; |
252b5132 RH |
10055 | |
10056 | case M_SEQ_I: | |
10057 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10058 | { | |
67c0d1eb | 10059 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10060 | break; |
252b5132 RH |
10061 | } |
10062 | if (sreg == 0) | |
10063 | { | |
10064 | as_warn (_("Instruction %s: result is always false"), | |
10065 | ip->insn_mo->name); | |
67c0d1eb | 10066 | move_register (dreg, 0); |
8fc2e39e | 10067 | break; |
252b5132 | 10068 | } |
dd3cbb7e NC |
10069 | if (CPU_HAS_SEQ (mips_opts.arch) |
10070 | && -512 <= imm_expr.X_add_number | |
10071 | && imm_expr.X_add_number < 512) | |
10072 | { | |
10073 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10074 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10075 | break; |
10076 | } | |
252b5132 RH |
10077 | if (imm_expr.X_op == O_constant |
10078 | && imm_expr.X_add_number >= 0 | |
10079 | && imm_expr.X_add_number < 0x10000) | |
10080 | { | |
67c0d1eb | 10081 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10082 | } |
10083 | else if (imm_expr.X_op == O_constant | |
10084 | && imm_expr.X_add_number > -0x8000 | |
10085 | && imm_expr.X_add_number < 0) | |
10086 | { | |
10087 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10088 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10089 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10090 | } |
dd3cbb7e NC |
10091 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10092 | { | |
10093 | used_at = 1; | |
10094 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10095 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
10096 | break; | |
10097 | } | |
252b5132 RH |
10098 | else |
10099 | { | |
67c0d1eb RS |
10100 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10101 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10102 | used_at = 1; |
10103 | } | |
67c0d1eb | 10104 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10105 | break; |
252b5132 RH |
10106 | |
10107 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
10108 | s = "slt"; | |
10109 | goto sge; | |
10110 | case M_SGEU: | |
10111 | s = "sltu"; | |
10112 | sge: | |
67c0d1eb RS |
10113 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
10114 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10115 | break; |
252b5132 RH |
10116 | |
10117 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
10118 | case M_SGEU_I: | |
10119 | if (imm_expr.X_op == O_constant | |
10120 | && imm_expr.X_add_number >= -0x8000 | |
10121 | && imm_expr.X_add_number < 0x8000) | |
10122 | { | |
67c0d1eb RS |
10123 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
10124 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
10125 | } |
10126 | else | |
10127 | { | |
67c0d1eb RS |
10128 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10129 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
10130 | dreg, sreg, AT); | |
252b5132 RH |
10131 | used_at = 1; |
10132 | } | |
67c0d1eb | 10133 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10134 | break; |
252b5132 RH |
10135 | |
10136 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
10137 | s = "slt"; | |
10138 | goto sgt; | |
10139 | case M_SGTU: | |
10140 | s = "sltu"; | |
10141 | sgt: | |
67c0d1eb | 10142 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 10143 | break; |
252b5132 RH |
10144 | |
10145 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
10146 | s = "slt"; | |
10147 | goto sgti; | |
10148 | case M_SGTU_I: | |
10149 | s = "sltu"; | |
10150 | sgti: | |
8fc2e39e | 10151 | used_at = 1; |
67c0d1eb RS |
10152 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10153 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
10154 | break; |
10155 | ||
2396cfb9 | 10156 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
10157 | s = "slt"; |
10158 | goto sle; | |
10159 | case M_SLEU: | |
10160 | s = "sltu"; | |
10161 | sle: | |
67c0d1eb RS |
10162 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
10163 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10164 | break; |
252b5132 | 10165 | |
2396cfb9 | 10166 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
10167 | s = "slt"; |
10168 | goto slei; | |
10169 | case M_SLEU_I: | |
10170 | s = "sltu"; | |
10171 | slei: | |
8fc2e39e | 10172 | used_at = 1; |
67c0d1eb RS |
10173 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10174 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
10175 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
10176 | break; |
10177 | ||
10178 | case M_SLT_I: | |
10179 | if (imm_expr.X_op == O_constant | |
10180 | && imm_expr.X_add_number >= -0x8000 | |
10181 | && imm_expr.X_add_number < 0x8000) | |
10182 | { | |
67c0d1eb | 10183 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10184 | break; |
252b5132 | 10185 | } |
8fc2e39e | 10186 | used_at = 1; |
67c0d1eb RS |
10187 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10188 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10189 | break; |
10190 | ||
10191 | case M_SLTU_I: | |
10192 | if (imm_expr.X_op == O_constant | |
10193 | && imm_expr.X_add_number >= -0x8000 | |
10194 | && imm_expr.X_add_number < 0x8000) | |
10195 | { | |
67c0d1eb | 10196 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 10197 | BFD_RELOC_LO16); |
8fc2e39e | 10198 | break; |
252b5132 | 10199 | } |
8fc2e39e | 10200 | used_at = 1; |
67c0d1eb RS |
10201 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10202 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10203 | break; |
10204 | ||
10205 | case M_SNE: | |
10206 | if (sreg == 0) | |
67c0d1eb | 10207 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 10208 | else if (treg == 0) |
67c0d1eb | 10209 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
10210 | else |
10211 | { | |
67c0d1eb RS |
10212 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10213 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 10214 | } |
8fc2e39e | 10215 | break; |
252b5132 RH |
10216 | |
10217 | case M_SNE_I: | |
10218 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10219 | { | |
67c0d1eb | 10220 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 10221 | break; |
252b5132 RH |
10222 | } |
10223 | if (sreg == 0) | |
10224 | { | |
10225 | as_warn (_("Instruction %s: result is always true"), | |
10226 | ip->insn_mo->name); | |
67c0d1eb RS |
10227 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
10228 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 10229 | break; |
252b5132 | 10230 | } |
dd3cbb7e NC |
10231 | if (CPU_HAS_SEQ (mips_opts.arch) |
10232 | && -512 <= imm_expr.X_add_number | |
10233 | && imm_expr.X_add_number < 512) | |
10234 | { | |
10235 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10236 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10237 | break; |
10238 | } | |
252b5132 RH |
10239 | if (imm_expr.X_op == O_constant |
10240 | && imm_expr.X_add_number >= 0 | |
10241 | && imm_expr.X_add_number < 0x10000) | |
10242 | { | |
67c0d1eb | 10243 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10244 | } |
10245 | else if (imm_expr.X_op == O_constant | |
10246 | && imm_expr.X_add_number > -0x8000 | |
10247 | && imm_expr.X_add_number < 0) | |
10248 | { | |
10249 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10250 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10251 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10252 | } |
dd3cbb7e NC |
10253 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10254 | { | |
10255 | used_at = 1; | |
10256 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10257 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
10258 | break; | |
10259 | } | |
252b5132 RH |
10260 | else |
10261 | { | |
67c0d1eb RS |
10262 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10263 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10264 | used_at = 1; |
10265 | } | |
67c0d1eb | 10266 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 10267 | break; |
252b5132 | 10268 | |
df58fc94 RS |
10269 | case M_SUB_I: |
10270 | s = "addi"; | |
10271 | s2 = "sub"; | |
10272 | goto do_subi; | |
10273 | case M_SUBU_I: | |
10274 | s = "addiu"; | |
10275 | s2 = "subu"; | |
10276 | goto do_subi; | |
252b5132 RH |
10277 | case M_DSUB_I: |
10278 | dbl = 1; | |
df58fc94 RS |
10279 | s = "daddi"; |
10280 | s2 = "dsub"; | |
10281 | if (!mips_opts.micromips) | |
10282 | goto do_subi; | |
252b5132 | 10283 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
10284 | && imm_expr.X_add_number > -0x200 |
10285 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 10286 | { |
df58fc94 | 10287 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 10288 | break; |
252b5132 | 10289 | } |
df58fc94 | 10290 | goto do_subi_i; |
252b5132 RH |
10291 | case M_DSUBU_I: |
10292 | dbl = 1; | |
df58fc94 RS |
10293 | s = "daddiu"; |
10294 | s2 = "dsubu"; | |
10295 | do_subi: | |
252b5132 RH |
10296 | if (imm_expr.X_op == O_constant |
10297 | && imm_expr.X_add_number > -0x8000 | |
10298 | && imm_expr.X_add_number <= 0x8000) | |
10299 | { | |
10300 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 10301 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10302 | break; |
252b5132 | 10303 | } |
df58fc94 | 10304 | do_subi_i: |
8fc2e39e | 10305 | used_at = 1; |
67c0d1eb | 10306 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 10307 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
10308 | break; |
10309 | ||
10310 | case M_TEQ_I: | |
10311 | s = "teq"; | |
10312 | goto trap; | |
10313 | case M_TGE_I: | |
10314 | s = "tge"; | |
10315 | goto trap; | |
10316 | case M_TGEU_I: | |
10317 | s = "tgeu"; | |
10318 | goto trap; | |
10319 | case M_TLT_I: | |
10320 | s = "tlt"; | |
10321 | goto trap; | |
10322 | case M_TLTU_I: | |
10323 | s = "tltu"; | |
10324 | goto trap; | |
10325 | case M_TNE_I: | |
10326 | s = "tne"; | |
10327 | trap: | |
8fc2e39e | 10328 | used_at = 1; |
67c0d1eb RS |
10329 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10330 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
10331 | break; |
10332 | ||
252b5132 | 10333 | case M_TRUNCWS: |
43841e91 | 10334 | case M_TRUNCWD: |
df58fc94 | 10335 | gas_assert (!mips_opts.micromips); |
0aa27725 | 10336 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 10337 | used_at = 1; |
252b5132 RH |
10338 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
10339 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
10340 | ||
10341 | /* | |
10342 | * Is the double cfc1 instruction a bug in the mips assembler; | |
10343 | * or is there a reason for it? | |
10344 | */ | |
7d10b47d | 10345 | start_noreorder (); |
67c0d1eb RS |
10346 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
10347 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
10348 | macro_build (NULL, "nop", ""); | |
252b5132 | 10349 | expr1.X_add_number = 3; |
67c0d1eb | 10350 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 10351 | expr1.X_add_number = 2; |
67c0d1eb RS |
10352 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
10353 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
10354 | macro_build (NULL, "nop", ""); | |
10355 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
10356 | dreg, sreg); | |
10357 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
10358 | macro_build (NULL, "nop", ""); | |
7d10b47d | 10359 | end_noreorder (); |
252b5132 RH |
10360 | break; |
10361 | ||
f2ae14a1 | 10362 | case M_ULH_AB: |
252b5132 | 10363 | s = "lb"; |
df58fc94 RS |
10364 | s2 = "lbu"; |
10365 | off = 1; | |
10366 | goto uld_st; | |
f2ae14a1 | 10367 | case M_ULHU_AB: |
252b5132 | 10368 | s = "lbu"; |
df58fc94 RS |
10369 | s2 = "lbu"; |
10370 | off = 1; | |
10371 | goto uld_st; | |
f2ae14a1 | 10372 | case M_ULW_AB: |
df58fc94 RS |
10373 | s = "lwl"; |
10374 | s2 = "lwr"; | |
7f3c4072 | 10375 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10376 | off = 3; |
10377 | goto uld_st; | |
f2ae14a1 | 10378 | case M_ULD_AB: |
252b5132 RH |
10379 | s = "ldl"; |
10380 | s2 = "ldr"; | |
7f3c4072 | 10381 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10382 | off = 7; |
df58fc94 | 10383 | goto uld_st; |
f2ae14a1 | 10384 | case M_USH_AB: |
df58fc94 RS |
10385 | s = "sb"; |
10386 | s2 = "sb"; | |
10387 | off = 1; | |
10388 | ust = 1; | |
10389 | goto uld_st; | |
f2ae14a1 | 10390 | case M_USW_AB: |
df58fc94 RS |
10391 | s = "swl"; |
10392 | s2 = "swr"; | |
7f3c4072 | 10393 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10394 | off = 3; |
df58fc94 RS |
10395 | ust = 1; |
10396 | goto uld_st; | |
f2ae14a1 | 10397 | case M_USD_AB: |
df58fc94 RS |
10398 | s = "sdl"; |
10399 | s2 = "sdr"; | |
7f3c4072 | 10400 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10401 | off = 7; |
10402 | ust = 1; | |
10403 | ||
10404 | uld_st: | |
f2ae14a1 | 10405 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
10406 | ep = &offset_expr; |
10407 | expr1.X_add_number = 0; | |
f2ae14a1 | 10408 | if (large_offset) |
df58fc94 RS |
10409 | { |
10410 | used_at = 1; | |
10411 | tempreg = AT; | |
f2ae14a1 RS |
10412 | if (small_offset_p (0, align, 16)) |
10413 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
10414 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10415 | else | |
10416 | { | |
10417 | load_address (tempreg, ep, &used_at); | |
10418 | if (breg != 0) | |
10419 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10420 | tempreg, tempreg, breg); | |
10421 | } | |
10422 | offset_reloc[0] = BFD_RELOC_LO16; | |
10423 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10424 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
10425 | breg = tempreg; |
10426 | tempreg = treg; | |
10427 | ep = &expr1; | |
10428 | } | |
10429 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10430 | { |
10431 | used_at = 1; | |
10432 | tempreg = AT; | |
10433 | } | |
252b5132 | 10434 | else |
df58fc94 | 10435 | tempreg = treg; |
af22f5b2 | 10436 | |
df58fc94 RS |
10437 | if (off == 1) |
10438 | goto ulh_sh; | |
252b5132 | 10439 | |
90ecf173 | 10440 | if (!target_big_endian) |
df58fc94 | 10441 | ep->X_add_number += off; |
f2ae14a1 | 10442 | if (offbits == 12) |
c8276761 | 10443 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
10444 | else |
10445 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
10446 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 10447 | |
90ecf173 | 10448 | if (!target_big_endian) |
df58fc94 | 10449 | ep->X_add_number -= off; |
252b5132 | 10450 | else |
df58fc94 | 10451 | ep->X_add_number += off; |
f2ae14a1 | 10452 | if (offbits == 12) |
df58fc94 | 10453 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 10454 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
10455 | else |
10456 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
10457 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 10458 | |
df58fc94 RS |
10459 | /* If necessary, move the result in tempreg to the final destination. */ |
10460 | if (!ust && treg != tempreg) | |
10461 | { | |
10462 | /* Protect second load's delay slot. */ | |
10463 | load_delay_nop (); | |
10464 | move_register (treg, tempreg); | |
10465 | } | |
8fc2e39e | 10466 | break; |
252b5132 | 10467 | |
df58fc94 | 10468 | ulh_sh: |
d6bc6245 | 10469 | used_at = 1; |
df58fc94 RS |
10470 | if (target_big_endian == ust) |
10471 | ep->X_add_number += off; | |
f2ae14a1 RS |
10472 | tempreg = ust || large_offset ? treg : AT; |
10473 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
10474 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
10475 | |
10476 | /* For halfword transfers we need a temporary register to shuffle | |
10477 | bytes. Unfortunately for M_USH_A we have none available before | |
10478 | the next store as AT holds the base address. We deal with this | |
10479 | case by clobbering TREG and then restoring it as with ULH. */ | |
f2ae14a1 | 10480 | tempreg = ust == large_offset ? treg : AT; |
df58fc94 RS |
10481 | if (ust) |
10482 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10483 | ||
10484 | if (target_big_endian == ust) | |
10485 | ep->X_add_number -= off; | |
252b5132 | 10486 | else |
df58fc94 | 10487 | ep->X_add_number += off; |
f2ae14a1 RS |
10488 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
10489 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 10490 | |
df58fc94 | 10491 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 10492 | if (ust && large_offset) |
df58fc94 RS |
10493 | { |
10494 | if (target_big_endian) | |
10495 | ep->X_add_number += off; | |
10496 | else | |
10497 | ep->X_add_number -= off; | |
f2ae14a1 RS |
10498 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
10499 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
10500 | } |
10501 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 10502 | if (!ust || large_offset) |
df58fc94 | 10503 | { |
f2ae14a1 | 10504 | tempreg = !large_offset ? AT : treg; |
df58fc94 RS |
10505 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
10506 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10507 | } | |
252b5132 RH |
10508 | break; |
10509 | ||
10510 | default: | |
10511 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10512 | are added dynamically. */ |
252b5132 RH |
10513 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10514 | break; | |
10515 | } | |
741fe287 | 10516 | if (!mips_opts.at && used_at) |
8fc2e39e | 10517 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10518 | } |
10519 | ||
10520 | /* Implement macros in mips16 mode. */ | |
10521 | ||
10522 | static void | |
17a2f251 | 10523 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10524 | { |
10525 | int mask; | |
10526 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10527 | expressionS expr1; |
10528 | int dbl; | |
10529 | const char *s, *s2, *s3; | |
10530 | ||
10531 | mask = ip->insn_mo->mask; | |
10532 | ||
bf12938e RS |
10533 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10534 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10535 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10536 | |
252b5132 RH |
10537 | expr1.X_op = O_constant; |
10538 | expr1.X_op_symbol = NULL; | |
10539 | expr1.X_add_symbol = NULL; | |
10540 | expr1.X_add_number = 1; | |
10541 | ||
10542 | dbl = 0; | |
10543 | ||
10544 | switch (mask) | |
10545 | { | |
10546 | default: | |
b37df7c4 | 10547 | abort (); |
252b5132 RH |
10548 | |
10549 | case M_DDIV_3: | |
10550 | dbl = 1; | |
10551 | case M_DIV_3: | |
10552 | s = "mflo"; | |
10553 | goto do_div3; | |
10554 | case M_DREM_3: | |
10555 | dbl = 1; | |
10556 | case M_REM_3: | |
10557 | s = "mfhi"; | |
10558 | do_div3: | |
7d10b47d | 10559 | start_noreorder (); |
67c0d1eb | 10560 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10561 | expr1.X_add_number = 2; |
67c0d1eb RS |
10562 | macro_build (&expr1, "bnez", "x,p", yreg); |
10563 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10564 | |
252b5132 RH |
10565 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10566 | since that causes an overflow. We should do that as well, | |
10567 | but I don't see how to do the comparisons without a temporary | |
10568 | register. */ | |
7d10b47d | 10569 | end_noreorder (); |
67c0d1eb | 10570 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10571 | break; |
10572 | ||
10573 | case M_DIVU_3: | |
10574 | s = "divu"; | |
10575 | s2 = "mflo"; | |
10576 | goto do_divu3; | |
10577 | case M_REMU_3: | |
10578 | s = "divu"; | |
10579 | s2 = "mfhi"; | |
10580 | goto do_divu3; | |
10581 | case M_DDIVU_3: | |
10582 | s = "ddivu"; | |
10583 | s2 = "mflo"; | |
10584 | goto do_divu3; | |
10585 | case M_DREMU_3: | |
10586 | s = "ddivu"; | |
10587 | s2 = "mfhi"; | |
10588 | do_divu3: | |
7d10b47d | 10589 | start_noreorder (); |
67c0d1eb | 10590 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10591 | expr1.X_add_number = 2; |
67c0d1eb RS |
10592 | macro_build (&expr1, "bnez", "x,p", yreg); |
10593 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10594 | end_noreorder (); |
67c0d1eb | 10595 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10596 | break; |
10597 | ||
10598 | case M_DMUL: | |
10599 | dbl = 1; | |
10600 | case M_MUL: | |
67c0d1eb RS |
10601 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10602 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10603 | break; |
252b5132 RH |
10604 | |
10605 | case M_DSUBU_I: | |
10606 | dbl = 1; | |
10607 | goto do_subu; | |
10608 | case M_SUBU_I: | |
10609 | do_subu: | |
10610 | if (imm_expr.X_op != O_constant) | |
10611 | as_bad (_("Unsupported large constant")); | |
10612 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10613 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10614 | break; |
10615 | ||
10616 | case M_SUBU_I_2: | |
10617 | if (imm_expr.X_op != O_constant) | |
10618 | as_bad (_("Unsupported large constant")); | |
10619 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10620 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10621 | break; |
10622 | ||
10623 | case M_DSUBU_I_2: | |
10624 | if (imm_expr.X_op != O_constant) | |
10625 | as_bad (_("Unsupported large constant")); | |
10626 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10627 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10628 | break; |
10629 | ||
10630 | case M_BEQ: | |
10631 | s = "cmp"; | |
10632 | s2 = "bteqz"; | |
10633 | goto do_branch; | |
10634 | case M_BNE: | |
10635 | s = "cmp"; | |
10636 | s2 = "btnez"; | |
10637 | goto do_branch; | |
10638 | case M_BLT: | |
10639 | s = "slt"; | |
10640 | s2 = "btnez"; | |
10641 | goto do_branch; | |
10642 | case M_BLTU: | |
10643 | s = "sltu"; | |
10644 | s2 = "btnez"; | |
10645 | goto do_branch; | |
10646 | case M_BLE: | |
10647 | s = "slt"; | |
10648 | s2 = "bteqz"; | |
10649 | goto do_reverse_branch; | |
10650 | case M_BLEU: | |
10651 | s = "sltu"; | |
10652 | s2 = "bteqz"; | |
10653 | goto do_reverse_branch; | |
10654 | case M_BGE: | |
10655 | s = "slt"; | |
10656 | s2 = "bteqz"; | |
10657 | goto do_branch; | |
10658 | case M_BGEU: | |
10659 | s = "sltu"; | |
10660 | s2 = "bteqz"; | |
10661 | goto do_branch; | |
10662 | case M_BGT: | |
10663 | s = "slt"; | |
10664 | s2 = "btnez"; | |
10665 | goto do_reverse_branch; | |
10666 | case M_BGTU: | |
10667 | s = "sltu"; | |
10668 | s2 = "btnez"; | |
10669 | ||
10670 | do_reverse_branch: | |
10671 | tmp = xreg; | |
10672 | xreg = yreg; | |
10673 | yreg = tmp; | |
10674 | ||
10675 | do_branch: | |
67c0d1eb RS |
10676 | macro_build (NULL, s, "x,y", xreg, yreg); |
10677 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10678 | break; |
10679 | ||
10680 | case M_BEQ_I: | |
10681 | s = "cmpi"; | |
10682 | s2 = "bteqz"; | |
10683 | s3 = "x,U"; | |
10684 | goto do_branch_i; | |
10685 | case M_BNE_I: | |
10686 | s = "cmpi"; | |
10687 | s2 = "btnez"; | |
10688 | s3 = "x,U"; | |
10689 | goto do_branch_i; | |
10690 | case M_BLT_I: | |
10691 | s = "slti"; | |
10692 | s2 = "btnez"; | |
10693 | s3 = "x,8"; | |
10694 | goto do_branch_i; | |
10695 | case M_BLTU_I: | |
10696 | s = "sltiu"; | |
10697 | s2 = "btnez"; | |
10698 | s3 = "x,8"; | |
10699 | goto do_branch_i; | |
10700 | case M_BLE_I: | |
10701 | s = "slti"; | |
10702 | s2 = "btnez"; | |
10703 | s3 = "x,8"; | |
10704 | goto do_addone_branch_i; | |
10705 | case M_BLEU_I: | |
10706 | s = "sltiu"; | |
10707 | s2 = "btnez"; | |
10708 | s3 = "x,8"; | |
10709 | goto do_addone_branch_i; | |
10710 | case M_BGE_I: | |
10711 | s = "slti"; | |
10712 | s2 = "bteqz"; | |
10713 | s3 = "x,8"; | |
10714 | goto do_branch_i; | |
10715 | case M_BGEU_I: | |
10716 | s = "sltiu"; | |
10717 | s2 = "bteqz"; | |
10718 | s3 = "x,8"; | |
10719 | goto do_branch_i; | |
10720 | case M_BGT_I: | |
10721 | s = "slti"; | |
10722 | s2 = "bteqz"; | |
10723 | s3 = "x,8"; | |
10724 | goto do_addone_branch_i; | |
10725 | case M_BGTU_I: | |
10726 | s = "sltiu"; | |
10727 | s2 = "bteqz"; | |
10728 | s3 = "x,8"; | |
10729 | ||
10730 | do_addone_branch_i: | |
10731 | if (imm_expr.X_op != O_constant) | |
10732 | as_bad (_("Unsupported large constant")); | |
10733 | ++imm_expr.X_add_number; | |
10734 | ||
10735 | do_branch_i: | |
67c0d1eb RS |
10736 | macro_build (&imm_expr, s, s3, xreg); |
10737 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10738 | break; |
10739 | ||
10740 | case M_ABS: | |
10741 | expr1.X_add_number = 0; | |
67c0d1eb | 10742 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10743 | if (xreg != yreg) |
67c0d1eb | 10744 | move_register (xreg, yreg); |
252b5132 | 10745 | expr1.X_add_number = 2; |
67c0d1eb RS |
10746 | macro_build (&expr1, "bteqz", "p"); |
10747 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10748 | } |
10749 | } | |
10750 | ||
10751 | /* For consistency checking, verify that all bits are specified either | |
10752 | by the match/mask part of the instruction definition, or by the | |
10753 | operand list. */ | |
10754 | static int | |
17a2f251 | 10755 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10756 | { |
10757 | const char *p = opc->args; | |
10758 | char c; | |
10759 | unsigned long used_bits = opc->mask; | |
10760 | ||
10761 | if ((used_bits & opc->match) != opc->match) | |
10762 | { | |
10763 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10764 | opc->name, opc->args); | |
10765 | return 0; | |
10766 | } | |
10767 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10768 | while (*p) | |
10769 | switch (c = *p++) | |
10770 | { | |
10771 | case ',': break; | |
10772 | case '(': break; | |
10773 | case ')': break; | |
af7ee8bf CD |
10774 | case '+': |
10775 | switch (c = *p++) | |
10776 | { | |
9bcd4f99 TS |
10777 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10778 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10779 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10780 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10781 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10782 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10783 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
5f74bc13 CD |
10784 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10785 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10786 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10787 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10788 | case 'I': break; | |
b015e599 | 10789 | case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; |
ef2e4d86 | 10790 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
bb35fb24 NC |
10791 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10792 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10793 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10794 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10795 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10796 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10797 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10798 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10799 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10800 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10801 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10802 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
27c5c572 | 10803 | case 'i': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7f3c4072 | 10804 | case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break; |
bb35fb24 | 10805 | |
af7ee8bf CD |
10806 | default: |
10807 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10808 | c, opc->name, opc->args); | |
10809 | return 0; | |
10810 | } | |
10811 | break; | |
252b5132 RH |
10812 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10813 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10814 | case 'A': break; | |
4372b673 | 10815 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10816 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10817 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10818 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10819 | case 'F': break; | |
10820 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10821 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10822 | case 'I': break; |
e972090a | 10823 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10824 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10825 | case 'L': break; |
10826 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10827 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10828 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10829 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10830 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10831 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10832 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10833 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10834 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10835 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10836 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10837 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10838 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10839 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10840 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10841 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10842 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10843 | case 'f': break; | |
10844 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10845 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10846 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10847 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10848 | case 'l': break; | |
10849 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10850 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10851 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10852 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10853 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10854 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10855 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10856 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10857 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10858 | case 'x': break; | |
10859 | case 'z': break; | |
10860 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10861 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10862 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10863 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10864 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
18870af7 | 10865 | case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break; |
8b082fb1 | 10866 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10867 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10868 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10869 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10870 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10871 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10872 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10873 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10874 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10875 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10876 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10877 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10878 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10879 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10880 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10881 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10882 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10883 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10884 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10885 | default: |
10886 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10887 | c, opc->name, opc->args); | |
10888 | return 0; | |
10889 | } | |
10890 | #undef USE_BITS | |
10891 | if (used_bits != 0xffffffff) | |
10892 | { | |
10893 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10894 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10895 | return 0; | |
10896 | } | |
10897 | return 1; | |
10898 | } | |
10899 | ||
df58fc94 RS |
10900 | /* For consistency checking, verify that the length implied matches the |
10901 | major opcode and that all bits are specified either by the match/mask | |
10902 | part of the instruction definition, or by the operand list. */ | |
10903 | ||
10904 | static int | |
10905 | validate_micromips_insn (const struct mips_opcode *opc) | |
10906 | { | |
10907 | unsigned long match = opc->match; | |
10908 | unsigned long mask = opc->mask; | |
10909 | const char *p = opc->args; | |
10910 | unsigned long insn_bits; | |
10911 | unsigned long used_bits; | |
10912 | unsigned long major; | |
10913 | unsigned int length; | |
10914 | char e; | |
10915 | char c; | |
10916 | ||
10917 | if ((mask & match) != match) | |
10918 | { | |
10919 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10920 | opc->name, opc->args); | |
10921 | return 0; | |
10922 | } | |
10923 | length = micromips_insn_length (opc); | |
10924 | if (length != 2 && length != 4) | |
10925 | { | |
10926 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10927 | "%s %s"), length, opc->name, opc->args); | |
10928 | return 0; | |
10929 | } | |
10930 | major = match >> (10 + 8 * (length - 2)); | |
10931 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10932 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10933 | { | |
10934 | as_bad (_("Internal error: bad microMIPS opcode " | |
10935 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10936 | return 0; | |
10937 | } | |
10938 | ||
10939 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10940 | insn_bits = 1 << 4 * length; | |
10941 | insn_bits <<= 4 * length; | |
10942 | insn_bits -= 1; | |
10943 | used_bits = mask; | |
10944 | #define USE_BITS(field) \ | |
10945 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10946 | while (*p) | |
10947 | switch (c = *p++) | |
10948 | { | |
10949 | case ',': break; | |
10950 | case '(': break; | |
10951 | case ')': break; | |
10952 | case '+': | |
10953 | e = c; | |
10954 | switch (c = *p++) | |
10955 | { | |
10956 | case 'A': USE_BITS (EXTLSB); break; | |
10957 | case 'B': USE_BITS (INSMSB); break; | |
10958 | case 'C': USE_BITS (EXTMSBD); break; | |
df58fc94 RS |
10959 | case 'E': USE_BITS (EXTLSB); break; |
10960 | case 'F': USE_BITS (INSMSB); break; | |
10961 | case 'G': USE_BITS (EXTMSBD); break; | |
10962 | case 'H': USE_BITS (EXTMSBD); break; | |
27c5c572 | 10963 | case 'i': USE_BITS (TARGET); break; |
7f3c4072 | 10964 | case 'j': USE_BITS (EVAOFFSET); break; |
df58fc94 RS |
10965 | default: |
10966 | as_bad (_("Internal error: bad mips opcode " | |
10967 | "(unknown extension operand type `%c%c'): %s %s"), | |
10968 | e, c, opc->name, opc->args); | |
10969 | return 0; | |
10970 | } | |
10971 | break; | |
10972 | case 'm': | |
10973 | e = c; | |
10974 | switch (c = *p++) | |
10975 | { | |
10976 | case 'A': USE_BITS (IMMA); break; | |
10977 | case 'B': USE_BITS (IMMB); break; | |
10978 | case 'C': USE_BITS (IMMC); break; | |
10979 | case 'D': USE_BITS (IMMD); break; | |
10980 | case 'E': USE_BITS (IMME); break; | |
10981 | case 'F': USE_BITS (IMMF); break; | |
10982 | case 'G': USE_BITS (IMMG); break; | |
10983 | case 'H': USE_BITS (IMMH); break; | |
10984 | case 'I': USE_BITS (IMMI); break; | |
10985 | case 'J': USE_BITS (IMMJ); break; | |
10986 | case 'L': USE_BITS (IMML); break; | |
10987 | case 'M': USE_BITS (IMMM); break; | |
10988 | case 'N': USE_BITS (IMMN); break; | |
10989 | case 'O': USE_BITS (IMMO); break; | |
10990 | case 'P': USE_BITS (IMMP); break; | |
10991 | case 'Q': USE_BITS (IMMQ); break; | |
10992 | case 'U': USE_BITS (IMMU); break; | |
10993 | case 'W': USE_BITS (IMMW); break; | |
10994 | case 'X': USE_BITS (IMMX); break; | |
10995 | case 'Y': USE_BITS (IMMY); break; | |
10996 | case 'Z': break; | |
10997 | case 'a': break; | |
10998 | case 'b': USE_BITS (MB); break; | |
10999 | case 'c': USE_BITS (MC); break; | |
11000 | case 'd': USE_BITS (MD); break; | |
11001 | case 'e': USE_BITS (ME); break; | |
11002 | case 'f': USE_BITS (MF); break; | |
11003 | case 'g': USE_BITS (MG); break; | |
11004 | case 'h': USE_BITS (MH); break; | |
df58fc94 RS |
11005 | case 'j': USE_BITS (MJ); break; |
11006 | case 'l': USE_BITS (ML); break; | |
11007 | case 'm': USE_BITS (MM); break; | |
11008 | case 'n': USE_BITS (MN); break; | |
11009 | case 'p': USE_BITS (MP); break; | |
11010 | case 'q': USE_BITS (MQ); break; | |
11011 | case 'r': break; | |
11012 | case 's': break; | |
11013 | case 't': break; | |
11014 | case 'x': break; | |
11015 | case 'y': break; | |
11016 | case 'z': break; | |
11017 | default: | |
11018 | as_bad (_("Internal error: bad mips opcode " | |
11019 | "(unknown extension operand type `%c%c'): %s %s"), | |
11020 | e, c, opc->name, opc->args); | |
11021 | return 0; | |
11022 | } | |
11023 | break; | |
11024 | case '.': USE_BITS (OFFSET10); break; | |
11025 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
11026 | case '2': USE_BITS (BP); break; |
11027 | case '3': USE_BITS (SA3); break; | |
11028 | case '4': USE_BITS (SA4); break; | |
11029 | case '5': USE_BITS (IMM8); break; | |
11030 | case '6': USE_BITS (RS); break; | |
11031 | case '7': USE_BITS (DSPACC); break; | |
11032 | case '8': USE_BITS (WRDSP); break; | |
11033 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
11034 | case '<': USE_BITS (SHAMT); break; |
11035 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 11036 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
11037 | case 'B': USE_BITS (CODE10); break; |
11038 | case 'C': USE_BITS (COPZ); break; | |
11039 | case 'D': USE_BITS (FD); break; | |
11040 | case 'E': USE_BITS (RT); break; | |
11041 | case 'G': USE_BITS (RS); break; | |
444d75be | 11042 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
11043 | case 'K': USE_BITS (RS); break; |
11044 | case 'M': USE_BITS (CCC); break; | |
11045 | case 'N': USE_BITS (BCC); break; | |
11046 | case 'R': USE_BITS (FR); break; | |
11047 | case 'S': USE_BITS (FS); break; | |
11048 | case 'T': USE_BITS (FT); break; | |
11049 | case 'V': USE_BITS (FS); break; | |
dec0624d | 11050 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 11051 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
11052 | case 'a': USE_BITS (TARGET); break; |
11053 | case 'b': USE_BITS (RS); break; | |
11054 | case 'c': USE_BITS (CODE); break; | |
11055 | case 'd': USE_BITS (RD); break; | |
11056 | case 'h': USE_BITS (PREFX); break; | |
11057 | case 'i': USE_BITS (IMMEDIATE); break; | |
11058 | case 'j': USE_BITS (DELTA); break; | |
11059 | case 'k': USE_BITS (CACHE); break; | |
11060 | case 'n': USE_BITS (RT); break; | |
11061 | case 'o': USE_BITS (DELTA); break; | |
11062 | case 'p': USE_BITS (DELTA); break; | |
11063 | case 'q': USE_BITS (CODE2); break; | |
11064 | case 'r': USE_BITS (RS); break; | |
11065 | case 's': USE_BITS (RS); break; | |
11066 | case 't': USE_BITS (RT); break; | |
11067 | case 'u': USE_BITS (IMMEDIATE); break; | |
11068 | case 'v': USE_BITS (RS); break; | |
11069 | case 'w': USE_BITS (RT); break; | |
11070 | case 'y': USE_BITS (RS3); break; | |
11071 | case 'z': break; | |
11072 | case '|': USE_BITS (TRAP); break; | |
11073 | case '~': USE_BITS (OFFSET12); break; | |
11074 | default: | |
11075 | as_bad (_("Internal error: bad microMIPS opcode " | |
11076 | "(unknown operand type `%c'): %s %s"), | |
11077 | c, opc->name, opc->args); | |
11078 | return 0; | |
11079 | } | |
11080 | #undef USE_BITS | |
11081 | if (used_bits != insn_bits) | |
11082 | { | |
11083 | if (~used_bits & insn_bits) | |
11084 | as_bad (_("Internal error: bad microMIPS opcode " | |
11085 | "(bits 0x%lx undefined): %s %s"), | |
11086 | ~used_bits & insn_bits, opc->name, opc->args); | |
11087 | if (used_bits & ~insn_bits) | |
11088 | as_bad (_("Internal error: bad microMIPS opcode " | |
11089 | "(bits 0x%lx defined): %s %s"), | |
11090 | used_bits & ~insn_bits, opc->name, opc->args); | |
11091 | return 0; | |
11092 | } | |
11093 | return 1; | |
11094 | } | |
11095 | ||
9bcd4f99 TS |
11096 | /* UDI immediates. */ |
11097 | struct mips_immed { | |
11098 | char type; | |
11099 | unsigned int shift; | |
11100 | unsigned long mask; | |
11101 | const char * desc; | |
11102 | }; | |
11103 | ||
11104 | static const struct mips_immed mips_immed[] = { | |
11105 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
11106 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
11107 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
11108 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
11109 | { 0,0,0,0 } | |
11110 | }; | |
11111 | ||
7455baf8 TS |
11112 | /* Check whether an odd floating-point register is allowed. */ |
11113 | static int | |
11114 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
11115 | { | |
11116 | const char *s = insn->name; | |
11117 | ||
11118 | if (insn->pinfo == INSN_MACRO) | |
11119 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
11120 | return 1; | |
11121 | ||
e407c74b | 11122 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
11123 | { |
11124 | /* Allow odd registers for single-precision ops. */ | |
11125 | switch (insn->pinfo & (FP_S | FP_D)) | |
11126 | { | |
11127 | case FP_S: | |
11128 | case 0: | |
11129 | return 1; /* both single precision - ok */ | |
11130 | case FP_D: | |
11131 | return 0; /* both double precision - fail */ | |
11132 | default: | |
11133 | break; | |
11134 | } | |
11135 | ||
11136 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
11137 | s = strchr (insn->name, '.'); | |
11138 | if (argnum == 2) | |
11139 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
11140 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
11141 | } | |
11142 | ||
11143 | /* Single-precision coprocessor loads and moves are OK too. */ | |
11144 | if ((insn->pinfo & FP_S) | |
11145 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
11146 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
11147 | return 1; | |
11148 | ||
11149 | return 0; | |
11150 | } | |
11151 | ||
df58fc94 RS |
11152 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
11153 | taking bits from BIT up. */ | |
11154 | static int | |
11155 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
11156 | { | |
11157 | return (ep->X_op == O_constant | |
11158 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
11159 | && ep->X_add_number >= min << bit | |
11160 | && ep->X_add_number < max << bit); | |
11161 | } | |
11162 | ||
77bd4346 RS |
11163 | /* Assemble an instruction into its binary format. If the instruction |
11164 | is a macro, set imm_expr, imm2_expr and offset_expr to the values | |
11165 | associated with "I", "+I" and "A" operands respectively. Otherwise | |
11166 | store the value of the relocatable field (if any) in offset_expr. | |
11167 | In both cases set offset_reloc to the relocation operators applied | |
11168 | to offset_expr. */ | |
252b5132 RH |
11169 | |
11170 | static void | |
17a2f251 | 11171 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 11172 | { |
df58fc94 RS |
11173 | bfd_boolean wrong_delay_slot_insns = FALSE; |
11174 | bfd_boolean need_delay_slot_ok = TRUE; | |
11175 | struct mips_opcode *firstinsn = NULL; | |
11176 | const struct mips_opcode *past; | |
11177 | struct hash_control *hash; | |
252b5132 RH |
11178 | char *s; |
11179 | const char *args; | |
43841e91 | 11180 | char c = 0; |
252b5132 RH |
11181 | struct mips_opcode *insn; |
11182 | char *argsStart; | |
e76ff5ab | 11183 | unsigned int regno, regno2; |
34224acf | 11184 | unsigned int lastregno; |
df58fc94 | 11185 | unsigned int destregno = 0; |
af7ee8bf | 11186 | unsigned int lastpos = 0; |
071742cf | 11187 | unsigned int limlo, limhi; |
f02d8318 | 11188 | int sizelo; |
252b5132 | 11189 | char *s_reset; |
74cd071d | 11190 | offsetT min_range, max_range; |
df58fc94 | 11191 | long opend; |
a40bc9dd | 11192 | char *name; |
707bfff6 TS |
11193 | int argnum; |
11194 | unsigned int rtype; | |
df58fc94 | 11195 | char *dot; |
a40bc9dd | 11196 | long end; |
252b5132 RH |
11197 | |
11198 | insn_error = NULL; | |
11199 | ||
df58fc94 RS |
11200 | if (mips_opts.micromips) |
11201 | { | |
11202 | hash = micromips_op_hash; | |
11203 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
11204 | } | |
11205 | else | |
11206 | { | |
11207 | hash = op_hash; | |
11208 | past = &mips_opcodes[NUMOPCODES]; | |
11209 | } | |
11210 | forced_insn_length = 0; | |
252b5132 | 11211 | insn = NULL; |
252b5132 | 11212 | |
df58fc94 | 11213 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
11214 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
11215 | continue; | |
bdaaa2e1 | 11216 | |
a40bc9dd RS |
11217 | /* Make a copy of the instruction so that we can fiddle with it. */ |
11218 | name = alloca (end + 1); | |
11219 | memcpy (name, str, end); | |
11220 | name[end] = '\0'; | |
252b5132 | 11221 | |
df58fc94 RS |
11222 | for (;;) |
11223 | { | |
11224 | insn = (struct mips_opcode *) hash_find (hash, name); | |
11225 | ||
11226 | if (insn != NULL || !mips_opts.micromips) | |
11227 | break; | |
11228 | if (forced_insn_length) | |
11229 | break; | |
11230 | ||
11231 | /* See if there's an instruction size override suffix, | |
11232 | either `16' or `32', at the end of the mnemonic proper, | |
11233 | that defines the operation, i.e. before the first `.' | |
11234 | character if any. Strip it and retry. */ | |
11235 | dot = strchr (name, '.'); | |
11236 | opend = dot != NULL ? dot - name : end; | |
11237 | if (opend < 3) | |
11238 | break; | |
11239 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
11240 | forced_insn_length = 2; | |
11241 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
11242 | forced_insn_length = 4; | |
11243 | else | |
11244 | break; | |
11245 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
11246 | } | |
252b5132 RH |
11247 | if (insn == NULL) |
11248 | { | |
a40bc9dd RS |
11249 | insn_error = _("Unrecognized opcode"); |
11250 | return; | |
252b5132 RH |
11251 | } |
11252 | ||
df58fc94 RS |
11253 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
11254 | we make up to two passes over the relevant fragment of the opcode | |
11255 | table. First we try instructions that meet the delay slot's length | |
11256 | requirement. If none matched, then we retry with the remaining ones | |
11257 | and if one matches, then we use it and then issue an appropriate | |
11258 | warning later on. */ | |
a40bc9dd | 11259 | argsStart = s = str + end; |
252b5132 RH |
11260 | for (;;) |
11261 | { | |
df58fc94 RS |
11262 | bfd_boolean delay_slot_ok; |
11263 | bfd_boolean size_ok; | |
b34976b6 | 11264 | bfd_boolean ok; |
252b5132 | 11265 | |
a40bc9dd | 11266 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 11267 | |
f79e2745 | 11268 | ok = is_opcode_valid (insn); |
df58fc94 RS |
11269 | size_ok = is_size_valid (insn); |
11270 | delay_slot_ok = is_delay_slot_valid (insn); | |
11271 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 11272 | { |
df58fc94 RS |
11273 | firstinsn = insn; |
11274 | wrong_delay_slot_insns = TRUE; | |
11275 | } | |
11276 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
11277 | { | |
11278 | static char buf[256]; | |
11279 | ||
11280 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
11281 | { |
11282 | ++insn; | |
11283 | continue; | |
11284 | } | |
df58fc94 | 11285 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 11286 | { |
df58fc94 RS |
11287 | gas_assert (firstinsn); |
11288 | need_delay_slot_ok = FALSE; | |
11289 | past = insn + 1; | |
11290 | insn = firstinsn; | |
11291 | continue; | |
252b5132 | 11292 | } |
df58fc94 RS |
11293 | |
11294 | if (insn_error) | |
11295 | return; | |
11296 | ||
11297 | if (!ok) | |
7bd942df | 11298 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
11299 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
11300 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
833794fc MR |
11301 | else if (mips_opts.insn32) |
11302 | sprintf (buf, _("Opcode not supported in the `insn32' mode")); | |
df58fc94 RS |
11303 | else |
11304 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
11305 | 8 * forced_insn_length); | |
11306 | insn_error = buf; | |
11307 | ||
11308 | return; | |
252b5132 RH |
11309 | } |
11310 | ||
f2ae14a1 RS |
11311 | imm_expr.X_op = O_absent; |
11312 | imm2_expr.X_op = O_absent; | |
11313 | offset_expr.X_op = O_absent; | |
f2ae14a1 RS |
11314 | offset_reloc[0] = BFD_RELOC_UNUSED; |
11315 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
11316 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
11317 | ||
1e915849 | 11318 | create_insn (ip, insn); |
268f6bed | 11319 | insn_error = NULL; |
707bfff6 | 11320 | argnum = 1; |
24864476 | 11321 | lastregno = 0xffffffff; |
252b5132 RH |
11322 | for (args = insn->args;; ++args) |
11323 | { | |
deec1734 CD |
11324 | int is_mdmx; |
11325 | ||
ad8d3bb3 | 11326 | s += strspn (s, " \t"); |
deec1734 | 11327 | is_mdmx = 0; |
252b5132 RH |
11328 | switch (*args) |
11329 | { | |
11330 | case '\0': /* end of args */ | |
11331 | if (*s == '\0') | |
11332 | return; | |
11333 | break; | |
11334 | ||
03f66e8a MR |
11335 | case '2': |
11336 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
11337 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
11338 | my_getExpression (&imm_expr, s); |
11339 | check_absolute_expr (ip, &imm_expr); | |
11340 | if ((unsigned long) imm_expr.X_add_number != 1 | |
11341 | && (unsigned long) imm_expr.X_add_number != 3) | |
11342 | { | |
11343 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
11344 | (unsigned long) imm_expr.X_add_number); | |
11345 | } | |
03f66e8a MR |
11346 | INSERT_OPERAND (mips_opts.micromips, |
11347 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
11348 | imm_expr.X_op = O_absent; |
11349 | s = expr_end; | |
11350 | continue; | |
11351 | ||
03f66e8a | 11352 | case '3': |
c3678916 RS |
11353 | /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS |
11354 | code) or 13 (for microMIPS code). */ | |
03f66e8a MR |
11355 | { |
11356 | unsigned long mask = (mips_opts.micromips | |
11357 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
11358 | ||
11359 | my_getExpression (&imm_expr, s); | |
11360 | check_absolute_expr (ip, &imm_expr); | |
11361 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11362 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11363 | mask, (unsigned long) imm_expr.X_add_number); | |
11364 | INSERT_OPERAND (mips_opts.micromips, | |
11365 | SA3, *ip, imm_expr.X_add_number); | |
11366 | imm_expr.X_op = O_absent; | |
11367 | s = expr_end; | |
11368 | } | |
74cd071d CF |
11369 | continue; |
11370 | ||
03f66e8a | 11371 | case '4': |
c3678916 RS |
11372 | /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS |
11373 | code) or 12 (for microMIPS code). */ | |
03f66e8a MR |
11374 | { |
11375 | unsigned long mask = (mips_opts.micromips | |
11376 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
11377 | ||
11378 | my_getExpression (&imm_expr, s); | |
11379 | check_absolute_expr (ip, &imm_expr); | |
11380 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11381 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11382 | mask, (unsigned long) imm_expr.X_add_number); | |
11383 | INSERT_OPERAND (mips_opts.micromips, | |
11384 | SA4, *ip, imm_expr.X_add_number); | |
11385 | imm_expr.X_op = O_absent; | |
11386 | s = expr_end; | |
11387 | } | |
74cd071d CF |
11388 | continue; |
11389 | ||
03f66e8a | 11390 | case '5': |
c3678916 RS |
11391 | /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS |
11392 | code) or 13 (for microMIPS code). */ | |
03f66e8a MR |
11393 | { |
11394 | unsigned long mask = (mips_opts.micromips | |
11395 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11396 | ||
11397 | my_getExpression (&imm_expr, s); | |
11398 | check_absolute_expr (ip, &imm_expr); | |
11399 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11400 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11401 | mask, (unsigned long) imm_expr.X_add_number); | |
11402 | INSERT_OPERAND (mips_opts.micromips, | |
11403 | IMM8, *ip, imm_expr.X_add_number); | |
11404 | imm_expr.X_op = O_absent; | |
11405 | s = expr_end; | |
11406 | } | |
74cd071d CF |
11407 | continue; |
11408 | ||
03f66e8a | 11409 | case '6': |
c3678916 RS |
11410 | /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS |
11411 | code) or 16 (for microMIPS code). */ | |
03f66e8a MR |
11412 | { |
11413 | unsigned long mask = (mips_opts.micromips | |
11414 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11415 | ||
11416 | my_getExpression (&imm_expr, s); | |
11417 | check_absolute_expr (ip, &imm_expr); | |
11418 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11419 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11420 | mask, (unsigned long) imm_expr.X_add_number); | |
11421 | INSERT_OPERAND (mips_opts.micromips, | |
11422 | RS, *ip, imm_expr.X_add_number); | |
11423 | imm_expr.X_op = O_absent; | |
11424 | s = expr_end; | |
11425 | } | |
74cd071d CF |
11426 | continue; |
11427 | ||
c3678916 RS |
11428 | case '7': |
11429 | /* Four DSP accumulators in bit 11 (for standard MIPS code) | |
11430 | or 14 (for microMIPS code). */ | |
03f66e8a MR |
11431 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11432 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11433 | { |
11434 | regno = s[3] - '0'; | |
11435 | s += 4; | |
03f66e8a | 11436 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11437 | continue; |
11438 | } | |
11439 | else | |
11440 | as_bad (_("Invalid dsp acc register")); | |
11441 | break; | |
11442 | ||
03f66e8a MR |
11443 | case '8': |
11444 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11445 | code) or 14 (for microMIPS code). */ | |
11446 | { | |
11447 | unsigned long mask = (mips_opts.micromips | |
11448 | ? MICROMIPSOP_MASK_WRDSP | |
11449 | : OP_MASK_WRDSP); | |
11450 | ||
11451 | my_getExpression (&imm_expr, s); | |
11452 | check_absolute_expr (ip, &imm_expr); | |
11453 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11454 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11455 | mask, (unsigned long) imm_expr.X_add_number); | |
11456 | INSERT_OPERAND (mips_opts.micromips, | |
11457 | WRDSP, *ip, imm_expr.X_add_number); | |
11458 | imm_expr.X_op = O_absent; | |
11459 | s = expr_end; | |
11460 | } | |
74cd071d CF |
11461 | continue; |
11462 | ||
90ecf173 | 11463 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11464 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11465 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11466 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11467 | { |
11468 | regno = s[3] - '0'; | |
11469 | s += 4; | |
df58fc94 | 11470 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11471 | continue; |
11472 | } | |
11473 | else | |
11474 | as_bad (_("Invalid dsp acc register")); | |
11475 | break; | |
11476 | ||
03f66e8a | 11477 | case '0': |
c3678916 RS |
11478 | /* DSP 6-bit signed immediate in bit 20 (for standard MIPS |
11479 | code) or 16 (for microMIPS code). */ | |
03f66e8a MR |
11480 | { |
11481 | long mask = (mips_opts.micromips | |
11482 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11483 | ||
11484 | my_getExpression (&imm_expr, s); | |
11485 | check_absolute_expr (ip, &imm_expr); | |
11486 | min_range = -((mask + 1) >> 1); | |
11487 | max_range = ((mask + 1) >> 1) - 1; | |
11488 | if (imm_expr.X_add_number < min_range | |
11489 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11490 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11491 | (long) min_range, (long) max_range, | |
11492 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11493 | INSERT_OPERAND (mips_opts.micromips, |
11494 | DSPSFT, *ip, imm_expr.X_add_number); | |
11495 | imm_expr.X_op = O_absent; | |
11496 | s = expr_end; | |
11497 | } | |
74cd071d CF |
11498 | continue; |
11499 | ||
90ecf173 | 11500 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11501 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11502 | my_getExpression (&imm_expr, s); |
11503 | check_absolute_expr (ip, &imm_expr); | |
11504 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11505 | { | |
a9e24354 TS |
11506 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11507 | OP_MASK_RDDSP, | |
11508 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11509 | } |
df58fc94 | 11510 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11511 | imm_expr.X_op = O_absent; |
11512 | s = expr_end; | |
11513 | continue; | |
11514 | ||
90ecf173 | 11515 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11516 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11517 | my_getExpression (&imm_expr, s); |
11518 | check_absolute_expr (ip, &imm_expr); | |
11519 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11520 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11521 | if (imm_expr.X_add_number < min_range || | |
11522 | imm_expr.X_add_number > max_range) | |
11523 | { | |
a9e24354 TS |
11524 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11525 | (long) min_range, (long) max_range, | |
11526 | (long) imm_expr.X_add_number); | |
74cd071d | 11527 | } |
df58fc94 | 11528 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11529 | imm_expr.X_op = O_absent; |
11530 | s = expr_end; | |
11531 | continue; | |
11532 | ||
90ecf173 | 11533 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11534 | { |
11535 | long mask = (mips_opts.micromips | |
11536 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11537 | ||
11538 | my_getExpression (&imm_expr, s); | |
11539 | check_absolute_expr (ip, &imm_expr); | |
11540 | min_range = -((mask + 1) >> 1); | |
11541 | max_range = ((mask + 1) >> 1) - 1; | |
11542 | if (imm_expr.X_add_number < min_range | |
11543 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11544 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11545 | (long) min_range, (long) max_range, | |
11546 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11547 | INSERT_OPERAND (mips_opts.micromips, |
11548 | IMM10, *ip, imm_expr.X_add_number); | |
11549 | imm_expr.X_op = O_absent; | |
11550 | s = expr_end; | |
11551 | } | |
11552 | continue; | |
11553 | ||
11554 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11555 | gas_assert (mips_opts.micromips); | |
11556 | my_getExpression (&imm_expr, s); | |
11557 | check_absolute_expr (ip, &imm_expr); | |
11558 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11559 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11560 | MICROMIPSOP_MASK_RD, | |
11561 | (unsigned long) imm_expr.X_add_number); | |
11562 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11563 | imm_expr.X_op = O_absent; |
11564 | s = expr_end; | |
11565 | continue; | |
11566 | ||
a9e24354 | 11567 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11568 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11569 | my_getExpression (&imm_expr, s); |
11570 | check_absolute_expr (ip, &imm_expr); | |
11571 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11572 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11573 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11574 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11575 | imm_expr.X_op = O_absent; |
11576 | s = expr_end; | |
11577 | continue; | |
11578 | ||
a9e24354 | 11579 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11580 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11581 | my_getExpression (&imm_expr, s); |
11582 | check_absolute_expr (ip, &imm_expr); | |
11583 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11584 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11585 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11586 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11587 | imm_expr.X_op = O_absent; |
11588 | s = expr_end; | |
11589 | continue; | |
11590 | ||
90ecf173 | 11591 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11592 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11593 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11594 | s[3] >= '0' && s[3] <= '3') | |
11595 | { | |
11596 | regno = s[3] - '0'; | |
11597 | s += 4; | |
df58fc94 | 11598 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11599 | continue; |
11600 | } | |
11601 | else | |
11602 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11603 | break; | |
11604 | ||
90ecf173 | 11605 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11606 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11607 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11608 | s[3] >= '0' && s[3] <= '3') | |
11609 | { | |
11610 | regno = s[3] - '0'; | |
11611 | s += 4; | |
df58fc94 | 11612 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11613 | continue; |
11614 | } | |
11615 | else | |
11616 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11617 | break; | |
11618 | ||
dec0624d MR |
11619 | case '\\': /* 3-bit bit position. */ |
11620 | { | |
2906b037 MR |
11621 | unsigned long mask = (mips_opts.micromips |
11622 | ? MICROMIPSOP_MASK_3BITPOS | |
11623 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11624 | |
11625 | my_getExpression (&imm_expr, s); | |
11626 | check_absolute_expr (ip, &imm_expr); | |
11627 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11628 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11629 | ip->insn_mo->name, | |
11630 | mask, (unsigned long) imm_expr.X_add_number); | |
11631 | INSERT_OPERAND (mips_opts.micromips, | |
11632 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11633 | imm_expr.X_op = O_absent; | |
11634 | s = expr_end; | |
11635 | } | |
11636 | continue; | |
11637 | ||
252b5132 | 11638 | case ',': |
a339155f | 11639 | ++argnum; |
252b5132 RH |
11640 | if (*s++ == *args) |
11641 | continue; | |
11642 | s--; | |
11643 | switch (*++args) | |
11644 | { | |
11645 | case 'r': | |
11646 | case 'v': | |
df58fc94 | 11647 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11648 | continue; |
11649 | ||
11650 | case 'w': | |
df58fc94 | 11651 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11652 | continue; |
11653 | ||
252b5132 | 11654 | case 'W': |
df58fc94 RS |
11655 | gas_assert (!mips_opts.micromips); |
11656 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11657 | continue; |
11658 | ||
11659 | case 'V': | |
df58fc94 | 11660 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11661 | continue; |
11662 | } | |
11663 | break; | |
11664 | ||
11665 | case '(': | |
11666 | /* Handle optional base register. | |
11667 | Either the base register is omitted or | |
bdaaa2e1 | 11668 | we must have a left paren. */ |
252b5132 RH |
11669 | /* This is dependent on the next operand specifier |
11670 | is a base register specification. */ | |
df58fc94 RS |
11671 | gas_assert (args[1] == 'b' |
11672 | || (mips_opts.micromips | |
11673 | && args[1] == 'm' | |
11674 | && (args[2] == 'l' || args[2] == 'n' | |
11675 | || args[2] == 's' || args[2] == 'a'))); | |
11676 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11677 | return; |
df58fc94 | 11678 | /* Fall through. */ |
252b5132 | 11679 | |
90ecf173 | 11680 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11681 | if (*s++ == *args) |
11682 | continue; | |
11683 | break; | |
11684 | ||
af7ee8bf CD |
11685 | case '+': /* Opcode extension character. */ |
11686 | switch (*++args) | |
11687 | { | |
9bcd4f99 TS |
11688 | case '1': /* UDI immediates. */ |
11689 | case '2': | |
11690 | case '3': | |
11691 | case '4': | |
df58fc94 | 11692 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11693 | { |
11694 | const struct mips_immed *imm = mips_immed; | |
11695 | ||
11696 | while (imm->type && imm->type != *args) | |
11697 | ++imm; | |
11698 | if (! imm->type) | |
b37df7c4 | 11699 | abort (); |
9bcd4f99 TS |
11700 | my_getExpression (&imm_expr, s); |
11701 | check_absolute_expr (ip, &imm_expr); | |
11702 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11703 | { | |
11704 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11705 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11706 | (unsigned long) imm_expr.X_add_number, | |
11707 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11708 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11709 | } |
11710 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11711 | << imm->shift); | |
11712 | imm_expr.X_op = O_absent; | |
11713 | s = expr_end; | |
11714 | } | |
11715 | continue; | |
90ecf173 | 11716 | |
b015e599 AP |
11717 | case 'J': /* 10-bit hypcall code. */ |
11718 | gas_assert (!mips_opts.micromips); | |
11719 | { | |
11720 | unsigned long mask = OP_MASK_CODE10; | |
11721 | ||
11722 | my_getExpression (&imm_expr, s); | |
11723 | check_absolute_expr (ip, &imm_expr); | |
11724 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11725 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11726 | ip->insn_mo->name, | |
11727 | mask, (unsigned long) imm_expr.X_add_number); | |
11728 | INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number); | |
11729 | imm_expr.X_op = O_absent; | |
11730 | s = expr_end; | |
11731 | } | |
11732 | continue; | |
11733 | ||
071742cf CD |
11734 | case 'A': /* ins/ext position, becomes LSB. */ |
11735 | limlo = 0; | |
11736 | limhi = 31; | |
5f74bc13 CD |
11737 | goto do_lsb; |
11738 | case 'E': | |
11739 | limlo = 32; | |
11740 | limhi = 63; | |
11741 | goto do_lsb; | |
90ecf173 | 11742 | do_lsb: |
071742cf CD |
11743 | my_getExpression (&imm_expr, s); |
11744 | check_absolute_expr (ip, &imm_expr); | |
11745 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11746 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11747 | { | |
11748 | as_bad (_("Improper position (%lu)"), | |
11749 | (unsigned long) imm_expr.X_add_number); | |
11750 | imm_expr.X_add_number = limlo; | |
11751 | } | |
11752 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11753 | INSERT_OPERAND (mips_opts.micromips, |
11754 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11755 | imm_expr.X_op = O_absent; |
11756 | s = expr_end; | |
11757 | continue; | |
11758 | ||
11759 | case 'B': /* ins size, becomes MSB. */ | |
11760 | limlo = 1; | |
11761 | limhi = 32; | |
5f74bc13 CD |
11762 | goto do_msb; |
11763 | case 'F': | |
11764 | limlo = 33; | |
11765 | limhi = 64; | |
11766 | goto do_msb; | |
90ecf173 | 11767 | do_msb: |
071742cf CD |
11768 | my_getExpression (&imm_expr, s); |
11769 | check_absolute_expr (ip, &imm_expr); | |
11770 | /* Check for negative input so that small negative numbers | |
11771 | will not succeed incorrectly. The checks against | |
11772 | (pos+size) transitively check "size" itself, | |
11773 | assuming that "pos" is reasonable. */ | |
11774 | if ((long) imm_expr.X_add_number < 0 | |
11775 | || ((unsigned long) imm_expr.X_add_number | |
11776 | + lastpos) < limlo | |
11777 | || ((unsigned long) imm_expr.X_add_number | |
11778 | + lastpos) > limhi) | |
11779 | { | |
11780 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11781 | (unsigned long) imm_expr.X_add_number, | |
11782 | (unsigned long) lastpos); | |
11783 | imm_expr.X_add_number = limlo - lastpos; | |
11784 | } | |
df58fc94 RS |
11785 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11786 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11787 | imm_expr.X_op = O_absent; |
11788 | s = expr_end; | |
11789 | continue; | |
11790 | ||
11791 | case 'C': /* ext size, becomes MSBD. */ | |
11792 | limlo = 1; | |
11793 | limhi = 32; | |
f02d8318 | 11794 | sizelo = 1; |
5f74bc13 CD |
11795 | goto do_msbd; |
11796 | case 'G': | |
11797 | limlo = 33; | |
11798 | limhi = 64; | |
f02d8318 | 11799 | sizelo = 33; |
5f74bc13 CD |
11800 | goto do_msbd; |
11801 | case 'H': | |
11802 | limlo = 33; | |
11803 | limhi = 64; | |
f02d8318 | 11804 | sizelo = 1; |
5f74bc13 | 11805 | goto do_msbd; |
90ecf173 | 11806 | do_msbd: |
071742cf CD |
11807 | my_getExpression (&imm_expr, s); |
11808 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11809 | /* The checks against (pos+size) don't transitively check |
11810 | "size" itself, assuming that "pos" is reasonable. | |
11811 | We also need to check the lower bound of "size". */ | |
11812 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11813 | || ((unsigned long) imm_expr.X_add_number |
11814 | + lastpos) < limlo | |
11815 | || ((unsigned long) imm_expr.X_add_number | |
11816 | + lastpos) > limhi) | |
11817 | { | |
11818 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11819 | (unsigned long) imm_expr.X_add_number, | |
11820 | (unsigned long) lastpos); | |
11821 | imm_expr.X_add_number = limlo - lastpos; | |
11822 | } | |
df58fc94 RS |
11823 | INSERT_OPERAND (mips_opts.micromips, |
11824 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11825 | imm_expr.X_op = O_absent; |
11826 | s = expr_end; | |
11827 | continue; | |
af7ee8bf | 11828 | |
5f74bc13 CD |
11829 | case 'I': |
11830 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11831 | my_getExpression (&imm2_expr, s); | |
11832 | if (imm2_expr.X_op != O_big | |
11833 | && imm2_expr.X_op != O_constant) | |
11834 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11835 | if (HAVE_32BIT_GPRS) |
11836 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11837 | s = expr_end; |
11838 | continue; | |
11839 | ||
707bfff6 | 11840 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11841 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11842 | if (s[0] == '$' && ISDIGIT (s[1])) |
11843 | { | |
11844 | ++s; | |
11845 | regno = 0; | |
11846 | do | |
11847 | { | |
11848 | regno *= 10; | |
11849 | regno += *s - '0'; | |
11850 | ++s; | |
11851 | } | |
11852 | while (ISDIGIT (*s)); | |
11853 | if (regno > 31) | |
11854 | as_bad (_("Invalid register number (%d)"), regno); | |
11855 | else | |
11856 | { | |
df58fc94 | 11857 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11858 | continue; |
11859 | } | |
11860 | } | |
11861 | else | |
11862 | as_bad (_("Invalid coprocessor 0 register number")); | |
11863 | break; | |
11864 | ||
bb35fb24 NC |
11865 | case 'x': |
11866 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11867 | is not in the valid range. */ | |
df58fc94 | 11868 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11869 | my_getExpression (&imm_expr, s); |
11870 | check_absolute_expr (ip, &imm_expr); | |
11871 | if ((unsigned) imm_expr.X_add_number > 31) | |
11872 | { | |
11873 | as_bad (_("Improper bit index (%lu)"), | |
11874 | (unsigned long) imm_expr.X_add_number); | |
11875 | imm_expr.X_add_number = 0; | |
11876 | } | |
df58fc94 | 11877 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11878 | imm_expr.X_op = O_absent; |
11879 | s = expr_end; | |
11880 | continue; | |
11881 | ||
11882 | case 'X': | |
11883 | /* bbit[01] bit index when bbit is used but we generate | |
11884 | bbit[01]32 because the index is over 32. Move to the | |
11885 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11886 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11887 | my_getExpression (&imm_expr, s); |
11888 | check_absolute_expr (ip, &imm_expr); | |
11889 | if ((unsigned) imm_expr.X_add_number < 32 | |
11890 | || (unsigned) imm_expr.X_add_number > 63) | |
11891 | break; | |
df58fc94 | 11892 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11893 | imm_expr.X_op = O_absent; |
11894 | s = expr_end; | |
11895 | continue; | |
11896 | ||
11897 | case 'p': | |
11898 | /* cins, cins32, exts and exts32 position field. Give error | |
11899 | if it's not in the valid range. */ | |
df58fc94 | 11900 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11901 | my_getExpression (&imm_expr, s); |
11902 | check_absolute_expr (ip, &imm_expr); | |
11903 | if ((unsigned) imm_expr.X_add_number > 31) | |
11904 | { | |
11905 | as_bad (_("Improper position (%lu)"), | |
11906 | (unsigned long) imm_expr.X_add_number); | |
11907 | imm_expr.X_add_number = 0; | |
11908 | } | |
23e69e47 | 11909 | lastpos = imm_expr.X_add_number; |
df58fc94 | 11910 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11911 | imm_expr.X_op = O_absent; |
11912 | s = expr_end; | |
11913 | continue; | |
11914 | ||
11915 | case 'P': | |
11916 | /* cins, cins32, exts and exts32 position field. Move to | |
11917 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11918 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11919 | my_getExpression (&imm_expr, s); |
11920 | check_absolute_expr (ip, &imm_expr); | |
11921 | if ((unsigned) imm_expr.X_add_number < 32 | |
11922 | || (unsigned) imm_expr.X_add_number > 63) | |
11923 | break; | |
11924 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11925 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11926 | imm_expr.X_op = O_absent; |
11927 | s = expr_end; | |
11928 | continue; | |
11929 | ||
11930 | case 's': | |
23e69e47 | 11931 | /* cins32 and exts32 length-minus-one field. */ |
df58fc94 | 11932 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11933 | my_getExpression (&imm_expr, s); |
11934 | check_absolute_expr (ip, &imm_expr); | |
23e69e47 RS |
11935 | if ((unsigned long) imm_expr.X_add_number > 31 |
11936 | || (unsigned long) imm_expr.X_add_number + lastpos > 31) | |
bb35fb24 NC |
11937 | { |
11938 | as_bad (_("Improper size (%lu)"), | |
11939 | (unsigned long) imm_expr.X_add_number); | |
11940 | imm_expr.X_add_number = 0; | |
11941 | } | |
df58fc94 | 11942 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11943 | imm_expr.X_op = O_absent; |
11944 | s = expr_end; | |
11945 | continue; | |
11946 | ||
11947 | case 'S': | |
23e69e47 | 11948 | /* cins/exts length-minus-one field. */ |
df58fc94 | 11949 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11950 | my_getExpression (&imm_expr, s); |
11951 | check_absolute_expr (ip, &imm_expr); | |
23e69e47 | 11952 | if ((unsigned long) imm_expr.X_add_number > 31 |
bb35fb24 NC |
11953 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) |
11954 | { | |
11955 | as_bad (_("Improper size (%lu)"), | |
11956 | (unsigned long) imm_expr.X_add_number); | |
11957 | imm_expr.X_add_number = 0; | |
11958 | } | |
df58fc94 | 11959 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11960 | imm_expr.X_op = O_absent; |
11961 | s = expr_end; | |
11962 | continue; | |
11963 | ||
dd3cbb7e NC |
11964 | case 'Q': |
11965 | /* seqi/snei immediate field. */ | |
df58fc94 | 11966 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11967 | my_getExpression (&imm_expr, s); |
11968 | check_absolute_expr (ip, &imm_expr); | |
11969 | if ((long) imm_expr.X_add_number < -512 | |
11970 | || (long) imm_expr.X_add_number >= 512) | |
11971 | { | |
11972 | as_bad (_("Improper immediate (%ld)"), | |
11973 | (long) imm_expr.X_add_number); | |
11974 | imm_expr.X_add_number = 0; | |
11975 | } | |
df58fc94 | 11976 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11977 | imm_expr.X_op = O_absent; |
11978 | s = expr_end; | |
11979 | continue; | |
11980 | ||
98675402 | 11981 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11982 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11983 | my_getExpression (&imm_expr, s); |
11984 | check_absolute_expr (ip, &imm_expr); | |
11985 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11986 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11987 | if (imm_expr.X_add_number < min_range | |
11988 | || imm_expr.X_add_number > max_range) | |
11989 | { | |
c95354ed | 11990 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11991 | (long) min_range, (long) max_range, |
11992 | (long) imm_expr.X_add_number); | |
11993 | } | |
df58fc94 | 11994 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11995 | imm_expr.X_op = O_absent; |
11996 | s = expr_end; | |
11997 | continue; | |
11998 | ||
11999 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 12000 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12001 | my_getExpression (&imm_expr, s); |
12002 | check_absolute_expr (ip, &imm_expr); | |
12003 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
12004 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
12005 | if (imm_expr.X_add_number < min_range | |
12006 | || imm_expr.X_add_number > max_range) | |
12007 | { | |
c95354ed | 12008 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12009 | (long) min_range, (long) max_range, |
12010 | (long) imm_expr.X_add_number); | |
12011 | } | |
df58fc94 | 12012 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
12013 | imm_expr.X_op = O_absent; |
12014 | s = expr_end; | |
12015 | continue; | |
12016 | ||
12017 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 12018 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12019 | my_getExpression (&imm_expr, s); |
12020 | check_absolute_expr (ip, &imm_expr); | |
12021 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
12022 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
12023 | /* We check the offset range before adjusted. */ |
12024 | min_range <<= 4; | |
12025 | max_range <<= 4; | |
98675402 RS |
12026 | if (imm_expr.X_add_number < min_range |
12027 | || imm_expr.X_add_number > max_range) | |
12028 | { | |
c95354ed | 12029 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12030 | (long) min_range, (long) max_range, |
12031 | (long) imm_expr.X_add_number); | |
12032 | } | |
c95354ed MX |
12033 | if (imm_expr.X_add_number & 0xf) |
12034 | { | |
12035 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
12036 | (long) imm_expr.X_add_number); | |
12037 | } | |
12038 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
12039 | INSERT_OPERAND (0, OFFSET_C, *ip, |
12040 | imm_expr.X_add_number >> 4); | |
98675402 RS |
12041 | imm_expr.X_op = O_absent; |
12042 | s = expr_end; | |
12043 | continue; | |
12044 | ||
12045 | case 'z': | |
df58fc94 | 12046 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12047 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
12048 | break; | |
12049 | if (regno == AT && mips_opts.at) | |
12050 | { | |
12051 | if (mips_opts.at == ATREG) | |
12052 | as_warn (_("used $at without \".set noat\"")); | |
12053 | else | |
12054 | as_warn (_("used $%u with \".set at=$%u\""), | |
12055 | regno, mips_opts.at); | |
12056 | } | |
df58fc94 | 12057 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
12058 | continue; |
12059 | ||
12060 | case 'Z': | |
df58fc94 | 12061 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12062 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
12063 | break; | |
df58fc94 | 12064 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
12065 | continue; |
12066 | ||
27c5c572 RS |
12067 | case 'i': |
12068 | goto jump; | |
12069 | ||
7f3c4072 CM |
12070 | case 'j': |
12071 | { | |
12072 | int shift = 8; | |
12073 | size_t i; | |
77bd4346 RS |
12074 | bfd_reloc_code_real_type r[3]; |
12075 | ||
7f3c4072 CM |
12076 | /* Check whether there is only a single bracketed expression |
12077 | left. If so, it must be the base register and the | |
12078 | constant must be zero. */ | |
12079 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12080 | continue; | |
12081 | ||
12082 | /* If this value won't fit into the offset, then go find | |
12083 | a macro that will generate a 16- or 32-bit offset code | |
12084 | pattern. */ | |
77bd4346 | 12085 | i = my_getSmallExpression (&imm_expr, r, s); |
7f3c4072 CM |
12086 | if ((i == 0 && (imm_expr.X_op != O_constant |
12087 | || imm_expr.X_add_number >= 1 << shift | |
12088 | || imm_expr.X_add_number < -1 << shift)) | |
12089 | || i > 0) | |
12090 | { | |
12091 | imm_expr.X_op = O_absent; | |
12092 | break; | |
12093 | } | |
12094 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip, | |
12095 | imm_expr.X_add_number); | |
12096 | imm_expr.X_op = O_absent; | |
12097 | s = expr_end; | |
12098 | } | |
12099 | continue; | |
12100 | ||
af7ee8bf | 12101 | default: |
df58fc94 | 12102 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 12103 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 12104 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 12105 | *args, insn->name, insn->args); |
af7ee8bf CD |
12106 | /* Further processing is fruitless. */ |
12107 | return; | |
12108 | } | |
12109 | break; | |
12110 | ||
df58fc94 | 12111 | case '.': /* 10-bit offset. */ |
df58fc94 | 12112 | gas_assert (mips_opts.micromips); |
dec0624d | 12113 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
12114 | { |
12115 | int shift = *args == '.' ? 9 : 11; | |
12116 | size_t i; | |
77bd4346 | 12117 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
12118 | |
12119 | /* Check whether there is only a single bracketed expression | |
12120 | left. If so, it must be the base register and the | |
12121 | constant must be zero. */ | |
12122 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12123 | continue; | |
12124 | ||
12125 | /* If this value won't fit into the offset, then go find | |
12126 | a macro that will generate a 16- or 32-bit offset code | |
12127 | pattern. */ | |
77bd4346 | 12128 | i = my_getSmallExpression (&imm_expr, r, s); |
df58fc94 RS |
12129 | if ((i == 0 && (imm_expr.X_op != O_constant |
12130 | || imm_expr.X_add_number >= 1 << shift | |
12131 | || imm_expr.X_add_number < -1 << shift)) | |
12132 | || i > 0) | |
12133 | { | |
12134 | imm_expr.X_op = O_absent; | |
12135 | break; | |
12136 | } | |
12137 | if (shift == 9) | |
12138 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
12139 | else | |
dec0624d MR |
12140 | INSERT_OPERAND (mips_opts.micromips, |
12141 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
12142 | imm_expr.X_op = O_absent; |
12143 | s = expr_end; | |
12144 | } | |
12145 | continue; | |
12146 | ||
252b5132 RH |
12147 | case '<': /* must be at least one digit */ |
12148 | /* | |
12149 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
12150 | * than 31 or less than 0, then the shift amount should be |
12151 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
12152 | * We issue a warning and mask out all but the low 5 bits. |
12153 | */ | |
12154 | my_getExpression (&imm_expr, s); | |
12155 | check_absolute_expr (ip, &imm_expr); | |
12156 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12157 | as_warn (_("Improper shift amount (%lu)"), |
12158 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
12159 | INSERT_OPERAND (mips_opts.micromips, |
12160 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
12161 | imm_expr.X_op = O_absent; |
12162 | s = expr_end; | |
12163 | continue; | |
12164 | ||
12165 | case '>': /* shift amount minus 32 */ | |
12166 | my_getExpression (&imm_expr, s); | |
12167 | check_absolute_expr (ip, &imm_expr); | |
12168 | if ((unsigned long) imm_expr.X_add_number < 32 | |
12169 | || (unsigned long) imm_expr.X_add_number > 63) | |
12170 | break; | |
df58fc94 RS |
12171 | INSERT_OPERAND (mips_opts.micromips, |
12172 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
12173 | imm_expr.X_op = O_absent; |
12174 | s = expr_end; | |
12175 | continue; | |
12176 | ||
90ecf173 MR |
12177 | case 'k': /* CACHE code. */ |
12178 | case 'h': /* PREFX code. */ | |
12179 | case '1': /* SYNC type. */ | |
252b5132 RH |
12180 | my_getExpression (&imm_expr, s); |
12181 | check_absolute_expr (ip, &imm_expr); | |
12182 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12183 | as_warn (_("Invalid value for `%s' (%lu)"), |
12184 | ip->insn_mo->name, | |
12185 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12186 | switch (*args) |
d954098f | 12187 | { |
df58fc94 RS |
12188 | case 'k': |
12189 | if (mips_fix_cn63xxp1 | |
12190 | && !mips_opts.micromips | |
12191 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
12192 | switch (imm_expr.X_add_number) |
12193 | { | |
12194 | case 5: | |
12195 | case 25: | |
12196 | case 26: | |
12197 | case 27: | |
12198 | case 28: | |
12199 | case 29: | |
12200 | case 30: | |
12201 | case 31: /* These are ok. */ | |
12202 | break; | |
12203 | ||
12204 | default: /* The rest must be changed to 28. */ | |
12205 | imm_expr.X_add_number = 28; | |
12206 | break; | |
12207 | } | |
df58fc94 RS |
12208 | INSERT_OPERAND (mips_opts.micromips, |
12209 | CACHE, *ip, imm_expr.X_add_number); | |
12210 | break; | |
12211 | case 'h': | |
12212 | INSERT_OPERAND (mips_opts.micromips, | |
12213 | PREFX, *ip, imm_expr.X_add_number); | |
12214 | break; | |
12215 | case '1': | |
12216 | INSERT_OPERAND (mips_opts.micromips, | |
12217 | STYPE, *ip, imm_expr.X_add_number); | |
12218 | break; | |
d954098f | 12219 | } |
252b5132 RH |
12220 | imm_expr.X_op = O_absent; |
12221 | s = expr_end; | |
12222 | continue; | |
12223 | ||
90ecf173 | 12224 | case 'c': /* BREAK code. */ |
df58fc94 RS |
12225 | { |
12226 | unsigned long mask = (mips_opts.micromips | |
12227 | ? MICROMIPSOP_MASK_CODE | |
12228 | : OP_MASK_CODE); | |
12229 | ||
12230 | my_getExpression (&imm_expr, s); | |
12231 | check_absolute_expr (ip, &imm_expr); | |
12232 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12233 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12234 | ip->insn_mo->name, | |
12235 | mask, (unsigned long) imm_expr.X_add_number); | |
12236 | INSERT_OPERAND (mips_opts.micromips, | |
12237 | CODE, *ip, imm_expr.X_add_number); | |
12238 | imm_expr.X_op = O_absent; | |
12239 | s = expr_end; | |
12240 | } | |
252b5132 RH |
12241 | continue; |
12242 | ||
90ecf173 | 12243 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
12244 | { |
12245 | unsigned long mask = (mips_opts.micromips | |
12246 | ? MICROMIPSOP_MASK_CODE2 | |
12247 | : OP_MASK_CODE2); | |
12248 | ||
12249 | my_getExpression (&imm_expr, s); | |
12250 | check_absolute_expr (ip, &imm_expr); | |
12251 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12252 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
12253 | ip->insn_mo->name, | |
12254 | mask, (unsigned long) imm_expr.X_add_number); | |
12255 | INSERT_OPERAND (mips_opts.micromips, | |
12256 | CODE2, *ip, imm_expr.X_add_number); | |
12257 | imm_expr.X_op = O_absent; | |
12258 | s = expr_end; | |
12259 | } | |
252b5132 RH |
12260 | continue; |
12261 | ||
df58fc94 RS |
12262 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
12263 | { | |
12264 | unsigned long mask = (mips_opts.micromips | |
12265 | ? MICROMIPSOP_MASK_CODE10 | |
12266 | : OP_MASK_CODE20); | |
12267 | ||
12268 | my_getExpression (&imm_expr, s); | |
12269 | check_absolute_expr (ip, &imm_expr); | |
12270 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12271 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12272 | ip->insn_mo->name, | |
12273 | mask, (unsigned long) imm_expr.X_add_number); | |
12274 | if (mips_opts.micromips) | |
12275 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
12276 | else | |
12277 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
12278 | imm_expr.X_op = O_absent; | |
12279 | s = expr_end; | |
12280 | } | |
252b5132 RH |
12281 | continue; |
12282 | ||
df58fc94 RS |
12283 | case 'C': /* 25- or 23-bit coprocessor code. */ |
12284 | { | |
12285 | unsigned long mask = (mips_opts.micromips | |
12286 | ? MICROMIPSOP_MASK_COPZ | |
12287 | : OP_MASK_COPZ); | |
12288 | ||
12289 | my_getExpression (&imm_expr, s); | |
12290 | check_absolute_expr (ip, &imm_expr); | |
12291 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12292 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
12293 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 12294 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12295 | INSERT_OPERAND (mips_opts.micromips, |
12296 | COPZ, *ip, imm_expr.X_add_number); | |
12297 | imm_expr.X_op = O_absent; | |
12298 | s = expr_end; | |
12299 | } | |
beae10d5 | 12300 | continue; |
252b5132 | 12301 | |
df58fc94 RS |
12302 | case 'J': /* 19-bit WAIT code. */ |
12303 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
12304 | my_getExpression (&imm_expr, s); |
12305 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 12306 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
12307 | { |
12308 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 12309 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12310 | imm_expr.X_add_number &= OP_MASK_CODE19; |
12311 | } | |
12312 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
12313 | imm_expr.X_op = O_absent; |
12314 | s = expr_end; | |
12315 | continue; | |
12316 | ||
707bfff6 | 12317 | case 'P': /* Performance register. */ |
df58fc94 | 12318 | gas_assert (!mips_opts.micromips); |
beae10d5 | 12319 | my_getExpression (&imm_expr, s); |
252b5132 | 12320 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 12321 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
12322 | as_warn (_("Invalid performance register (%lu)"), |
12323 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
12324 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
12325 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
12326 | as_warn (_("Invalid performance register (%lu)"), | |
12327 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12328 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
12329 | imm_expr.X_op = O_absent; |
12330 | s = expr_end; | |
12331 | continue; | |
252b5132 | 12332 | |
707bfff6 | 12333 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
12334 | { |
12335 | unsigned long opcode = ip->insn_opcode; | |
12336 | unsigned long mask; | |
12337 | unsigned int types; | |
12338 | int cop0; | |
12339 | ||
12340 | if (mips_opts.micromips) | |
12341 | { | |
12342 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
12343 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
12344 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
12345 | opcode &= mask; | |
12346 | switch (opcode) | |
12347 | { | |
12348 | case 0x000000fc: /* mfc0 */ | |
12349 | case 0x000002fc: /* mtc0 */ | |
12350 | case 0x580000fc: /* dmfc0 */ | |
12351 | case 0x580002fc: /* dmtc0 */ | |
12352 | cop0 = 1; | |
12353 | break; | |
12354 | default: | |
12355 | cop0 = 0; | |
12356 | break; | |
12357 | } | |
12358 | } | |
12359 | else | |
12360 | { | |
12361 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
12362 | cop0 = opcode == OP_OP_COP0; | |
12363 | } | |
12364 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
12365 | ok = reg_lookup (&s, types, ®no); | |
12366 | if (mips_opts.micromips) | |
12367 | INSERT_OPERAND (1, RS, *ip, regno); | |
12368 | else | |
12369 | INSERT_OPERAND (0, RD, *ip, regno); | |
12370 | if (ok) | |
12371 | { | |
12372 | lastregno = regno; | |
12373 | continue; | |
12374 | } | |
12375 | } | |
12376 | break; | |
707bfff6 | 12377 | |
df58fc94 RS |
12378 | case 'y': /* ALNV.PS source register. */ |
12379 | gas_assert (mips_opts.micromips); | |
12380 | goto do_reg; | |
12381 | case 'x': /* Ignore register name. */ | |
12382 | case 'U': /* Destination register (CLO/CLZ). */ | |
12383 | case 'g': /* Coprocessor destination register. */ | |
12384 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12385 | case 'b': /* Base register. */ |
12386 | case 'd': /* Destination register. */ | |
12387 | case 's': /* Source register. */ | |
12388 | case 't': /* Target register. */ | |
12389 | case 'r': /* Both target and source. */ | |
12390 | case 'v': /* Both dest and source. */ | |
12391 | case 'w': /* Both dest and target. */ | |
12392 | case 'E': /* Coprocessor target register. */ | |
12393 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 12394 | case 'z': /* Must be zero register. */ |
df58fc94 | 12395 | do_reg: |
90ecf173 | 12396 | s_reset = s; |
707bfff6 TS |
12397 | if (*args == 'E' || *args == 'K') |
12398 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
12399 | else | |
12400 | { | |
12401 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
12402 | if (regno == AT && mips_opts.at) |
12403 | { | |
12404 | if (mips_opts.at == ATREG) | |
f71d0d44 | 12405 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 12406 | else |
f71d0d44 | 12407 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
12408 | regno, mips_opts.at); |
12409 | } | |
707bfff6 TS |
12410 | } |
12411 | if (ok) | |
252b5132 | 12412 | { |
252b5132 RH |
12413 | c = *args; |
12414 | if (*s == ' ') | |
f9419b05 | 12415 | ++s; |
252b5132 RH |
12416 | if (args[1] != *s) |
12417 | { | |
12418 | if (c == 'r' || c == 'v' || c == 'w') | |
12419 | { | |
12420 | regno = lastregno; | |
12421 | s = s_reset; | |
f9419b05 | 12422 | ++args; |
252b5132 RH |
12423 | } |
12424 | } | |
12425 | /* 'z' only matches $0. */ | |
12426 | if (c == 'z' && regno != 0) | |
12427 | break; | |
12428 | ||
24864476 | 12429 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12430 | { |
12431 | if (regno == lastregno) | |
90ecf173 MR |
12432 | { |
12433 | insn_error | |
f71d0d44 | 12434 | = _("Source and destination must be different"); |
e7c604dd | 12435 | continue; |
90ecf173 | 12436 | } |
24864476 | 12437 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12438 | { |
12439 | insn_error | |
f71d0d44 | 12440 | = _("A destination register must be supplied"); |
e7c604dd | 12441 | continue; |
90ecf173 | 12442 | } |
e7c604dd | 12443 | } |
90ecf173 MR |
12444 | /* Now that we have assembled one operand, we use the args |
12445 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12446 | switch (c) |
12447 | { | |
12448 | case 'r': | |
12449 | case 's': | |
12450 | case 'v': | |
12451 | case 'b': | |
df58fc94 | 12452 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12453 | break; |
df58fc94 | 12454 | |
af7ee8bf | 12455 | case 'K': |
df58fc94 RS |
12456 | if (mips_opts.micromips) |
12457 | INSERT_OPERAND (1, RS, *ip, regno); | |
12458 | else | |
12459 | INSERT_OPERAND (0, RD, *ip, regno); | |
12460 | break; | |
12461 | ||
12462 | case 'd': | |
ef2e4d86 | 12463 | case 'g': |
df58fc94 | 12464 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12465 | break; |
df58fc94 | 12466 | |
4372b673 | 12467 | case 'U': |
df58fc94 RS |
12468 | gas_assert (!mips_opts.micromips); |
12469 | INSERT_OPERAND (0, RD, *ip, regno); | |
12470 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12471 | break; |
df58fc94 | 12472 | |
252b5132 RH |
12473 | case 'w': |
12474 | case 't': | |
12475 | case 'E': | |
df58fc94 RS |
12476 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12477 | break; | |
12478 | ||
12479 | case 'y': | |
12480 | gas_assert (mips_opts.micromips); | |
12481 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12482 | break; |
df58fc94 | 12483 | |
252b5132 RH |
12484 | case 'x': |
12485 | /* This case exists because on the r3000 trunc | |
12486 | expands into a macro which requires a gp | |
12487 | register. On the r6000 or r4000 it is | |
12488 | assembled into a single instruction which | |
12489 | ignores the register. Thus the insn version | |
12490 | is MIPS_ISA2 and uses 'x', and the macro | |
12491 | version is MIPS_ISA1 and uses 't'. */ | |
12492 | break; | |
df58fc94 | 12493 | |
252b5132 RH |
12494 | case 'z': |
12495 | /* This case is for the div instruction, which | |
12496 | acts differently if the destination argument | |
12497 | is $0. This only matches $0, and is checked | |
12498 | outside the switch. */ | |
12499 | break; | |
252b5132 RH |
12500 | } |
12501 | lastregno = regno; | |
12502 | continue; | |
12503 | } | |
252b5132 RH |
12504 | switch (*args++) |
12505 | { | |
12506 | case 'r': | |
12507 | case 'v': | |
df58fc94 | 12508 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12509 | continue; |
df58fc94 | 12510 | |
252b5132 | 12511 | case 'w': |
df58fc94 | 12512 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12513 | continue; |
12514 | } | |
12515 | break; | |
12516 | ||
deec1734 | 12517 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12518 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12519 | my_getExpression (&imm_expr, s); |
12520 | check_absolute_expr (ip, &imm_expr); | |
12521 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12522 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12523 | (long) imm_expr.X_add_number); |
df58fc94 | 12524 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12525 | imm_expr.X_op = O_absent; |
12526 | s = expr_end; | |
12527 | continue; | |
12528 | ||
12529 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12530 | if (s[0] != '$') | |
12531 | { | |
12532 | /* MDMX Immediate. */ | |
df58fc94 | 12533 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12534 | my_getExpression (&imm_expr, s); |
12535 | check_absolute_expr (ip, &imm_expr); | |
12536 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12537 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12538 | (long) imm_expr.X_add_number); | |
df58fc94 | 12539 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12540 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12541 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12542 | else | |
12543 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12544 | imm_expr.X_op = O_absent; |
12545 | s = expr_end; | |
12546 | continue; | |
12547 | } | |
12548 | /* Not MDMX Immediate. Fall through. */ | |
12549 | case 'X': /* MDMX destination register. */ | |
12550 | case 'Y': /* MDMX source register. */ | |
12551 | case 'Z': /* MDMX target register. */ | |
5c324c16 | 12552 | is_mdmx = !(insn->membership & INSN_5400); |
df58fc94 RS |
12553 | case 'W': |
12554 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12555 | case 'D': /* Floating point destination register. */ |
12556 | case 'S': /* Floating point source register. */ | |
12557 | case 'T': /* Floating point target register. */ | |
12558 | case 'R': /* Floating point source register. */ | |
252b5132 | 12559 | case 'V': |
707bfff6 TS |
12560 | rtype = RTYPE_FPU; |
12561 | if (is_mdmx | |
846ef2d0 | 12562 | || ((mips_opts.ase & ASE_MDMX) |
707bfff6 TS |
12563 | && (ip->insn_mo->pinfo & FP_D) |
12564 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12565 | | INSN_COPROC_MEMORY_DELAY | |
12566 | | INSN_LOAD_COPROC_DELAY | |
12567 | | INSN_LOAD_MEMORY_DELAY | |
12568 | | INSN_STORE_MEMORY)))) | |
12569 | rtype |= RTYPE_VEC; | |
252b5132 | 12570 | s_reset = s; |
707bfff6 | 12571 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12572 | { |
252b5132 | 12573 | if ((regno & 1) != 0 |
ca4e0257 | 12574 | && HAVE_32BIT_FPRS |
90ecf173 | 12575 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12576 | as_warn (_("Float register should be even, was %d"), |
12577 | regno); | |
12578 | ||
12579 | c = *args; | |
12580 | if (*s == ' ') | |
f9419b05 | 12581 | ++s; |
252b5132 RH |
12582 | if (args[1] != *s) |
12583 | { | |
12584 | if (c == 'V' || c == 'W') | |
12585 | { | |
12586 | regno = lastregno; | |
12587 | s = s_reset; | |
f9419b05 | 12588 | ++args; |
252b5132 RH |
12589 | } |
12590 | } | |
12591 | switch (c) | |
12592 | { | |
12593 | case 'D': | |
deec1734 | 12594 | case 'X': |
df58fc94 | 12595 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12596 | break; |
df58fc94 | 12597 | |
252b5132 RH |
12598 | case 'V': |
12599 | case 'S': | |
deec1734 | 12600 | case 'Y': |
df58fc94 | 12601 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12602 | break; |
df58fc94 | 12603 | |
deec1734 CD |
12604 | case 'Q': |
12605 | /* This is like 'Z', but also needs to fix the MDMX | |
12606 | vector/scalar select bits. Note that the | |
12607 | scalar immediate case is handled above. */ | |
5c324c16 RS |
12608 | if ((ip->insn_mo->membership & INSN_5400) |
12609 | && strcmp (insn->name, "rzu.ob") == 0) | |
12610 | as_bad (_("Operand %d of `%s' must be an immediate"), | |
12611 | argnum, ip->insn_mo->name); | |
12612 | ||
deec1734 CD |
12613 | if (*s == '[') |
12614 | { | |
12615 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12616 | int max_el = (is_qh ? 3 : 7); | |
12617 | s++; | |
12618 | my_getExpression(&imm_expr, s); | |
12619 | check_absolute_expr (ip, &imm_expr); | |
12620 | s = expr_end; | |
12621 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12622 | as_bad (_("Bad element selector %ld"), |
12623 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12624 | imm_expr.X_add_number &= max_el; |
12625 | ip->insn_opcode |= (imm_expr.X_add_number | |
12626 | << (OP_SH_VSEL + | |
12627 | (is_qh ? 2 : 1))); | |
01a3f561 | 12628 | imm_expr.X_op = O_absent; |
deec1734 | 12629 | if (*s != ']') |
20203fb9 | 12630 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12631 | else |
12632 | s++; | |
12633 | } | |
12634 | else | |
5c324c16 RS |
12635 | { |
12636 | if ((ip->insn_mo->membership & INSN_5400) | |
12637 | && (strcmp (insn->name, "sll.ob") == 0 | |
12638 | || strcmp (insn->name, "srl.ob") == 0)) | |
12639 | as_bad (_("Operand %d of `%s' must be scalar"), | |
12640 | argnum, ip->insn_mo->name); | |
12641 | ||
deec1734 CD |
12642 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12643 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12644 | << OP_SH_VSEL); | |
12645 | else | |
12646 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12647 | OP_SH_VSEL); | |
12648 | } | |
90ecf173 | 12649 | /* Fall through. */ |
252b5132 RH |
12650 | case 'W': |
12651 | case 'T': | |
deec1734 | 12652 | case 'Z': |
df58fc94 | 12653 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12654 | break; |
df58fc94 | 12655 | |
252b5132 | 12656 | case 'R': |
df58fc94 | 12657 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12658 | break; |
12659 | } | |
12660 | lastregno = regno; | |
12661 | continue; | |
12662 | } | |
12663 | ||
252b5132 RH |
12664 | switch (*args++) |
12665 | { | |
12666 | case 'V': | |
df58fc94 | 12667 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12668 | continue; |
df58fc94 | 12669 | |
252b5132 | 12670 | case 'W': |
df58fc94 | 12671 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12672 | continue; |
12673 | } | |
12674 | break; | |
12675 | ||
12676 | case 'I': | |
12677 | my_getExpression (&imm_expr, s); | |
12678 | if (imm_expr.X_op != O_big | |
12679 | && imm_expr.X_op != O_constant) | |
12680 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12681 | if (HAVE_32BIT_GPRS) |
12682 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12683 | s = expr_end; |
12684 | continue; | |
12685 | ||
12686 | case 'A': | |
0cbbe1b8 RS |
12687 | my_getSmallExpression (&offset_expr, offset_reloc, s); |
12688 | if (offset_expr.X_op == O_register) | |
f2ae14a1 | 12689 | { |
0cbbe1b8 RS |
12690 | /* Assume that the offset has been elided and that what |
12691 | we saw was a base register. The match will fail later | |
12692 | if that assumption turns out to be wrong. */ | |
f2ae14a1 RS |
12693 | offset_expr.X_op = O_constant; |
12694 | offset_expr.X_add_number = 0; | |
12695 | } | |
12696 | else | |
12697 | { | |
f2ae14a1 RS |
12698 | normalize_address_expr (&offset_expr); |
12699 | s = expr_end; | |
12700 | } | |
252b5132 RH |
12701 | continue; |
12702 | ||
12703 | case 'F': | |
12704 | case 'L': | |
12705 | case 'f': | |
12706 | case 'l': | |
12707 | { | |
12708 | int f64; | |
ca4e0257 | 12709 | int using_gprs; |
252b5132 RH |
12710 | char *save_in; |
12711 | char *err; | |
12712 | unsigned char temp[8]; | |
12713 | int len; | |
12714 | unsigned int length; | |
12715 | segT seg; | |
12716 | subsegT subseg; | |
12717 | char *p; | |
12718 | ||
12719 | /* These only appear as the last operand in an | |
12720 | instruction, and every instruction that accepts | |
12721 | them in any variant accepts them in all variants. | |
12722 | This means we don't have to worry about backing out | |
12723 | any changes if the instruction does not match. | |
12724 | ||
12725 | The difference between them is the size of the | |
12726 | floating point constant and where it goes. For 'F' | |
12727 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12728 | is 32 bits. Where the constant is placed is based | |
12729 | on how the MIPS assembler does things: | |
12730 | F -- .rdata | |
12731 | L -- .lit8 | |
12732 | f -- immediate value | |
12733 | l -- .lit4 | |
12734 | ||
12735 | The .lit4 and .lit8 sections are only used if | |
12736 | permitted by the -G argument. | |
12737 | ||
ca4e0257 RS |
12738 | The code below needs to know whether the target register |
12739 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12740 | 'F' are used with GPR-based instructions and 'l' and | |
12741 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12742 | |
12743 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12744 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12745 | |
12746 | save_in = input_line_pointer; | |
12747 | input_line_pointer = s; | |
12748 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12749 | length = len; | |
12750 | s = input_line_pointer; | |
12751 | input_line_pointer = save_in; | |
12752 | if (err != NULL && *err != '\0') | |
12753 | { | |
12754 | as_bad (_("Bad floating point constant: %s"), err); | |
12755 | memset (temp, '\0', sizeof temp); | |
12756 | length = f64 ? 8 : 4; | |
12757 | } | |
12758 | ||
9c2799c2 | 12759 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12760 | |
12761 | if (*args == 'f' | |
12762 | || (*args == 'l' | |
3e722fb5 | 12763 | && (g_switch_value < 4 |
252b5132 RH |
12764 | || (temp[0] == 0 && temp[1] == 0) |
12765 | || (temp[2] == 0 && temp[3] == 0)))) | |
12766 | { | |
12767 | imm_expr.X_op = O_constant; | |
90ecf173 | 12768 | if (!target_big_endian) |
252b5132 RH |
12769 | imm_expr.X_add_number = bfd_getl32 (temp); |
12770 | else | |
12771 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12772 | } | |
12773 | else if (length > 4 | |
90ecf173 | 12774 | && !mips_disable_float_construction |
ca4e0257 RS |
12775 | /* Constants can only be constructed in GPRs and |
12776 | copied to FPRs if the GPRs are at least as wide | |
12777 | as the FPRs. Force the constant into memory if | |
12778 | we are using 64-bit FPRs but the GPRs are only | |
12779 | 32 bits wide. */ | |
12780 | && (using_gprs | |
90ecf173 | 12781 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12782 | && ((temp[0] == 0 && temp[1] == 0) |
12783 | || (temp[2] == 0 && temp[3] == 0)) | |
12784 | && ((temp[4] == 0 && temp[5] == 0) | |
12785 | || (temp[6] == 0 && temp[7] == 0))) | |
12786 | { | |
ca4e0257 | 12787 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12788 | instructions. If using 32-bit registers, set |
12789 | imm_expr to the high order 32 bits and offset_expr to | |
12790 | the low order 32 bits. Otherwise, set imm_expr to | |
12791 | the entire 64 bit constant. */ | |
ca4e0257 | 12792 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12793 | { |
12794 | imm_expr.X_op = O_constant; | |
12795 | offset_expr.X_op = O_constant; | |
90ecf173 | 12796 | if (!target_big_endian) |
252b5132 RH |
12797 | { |
12798 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12799 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12800 | } | |
12801 | else | |
12802 | { | |
12803 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12804 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12805 | } | |
12806 | if (offset_expr.X_add_number == 0) | |
12807 | offset_expr.X_op = O_absent; | |
12808 | } | |
42429eac | 12809 | else |
252b5132 RH |
12810 | { |
12811 | imm_expr.X_op = O_constant; | |
90ecf173 | 12812 | if (!target_big_endian) |
252b5132 RH |
12813 | imm_expr.X_add_number = bfd_getl64 (temp); |
12814 | else | |
12815 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12816 | } | |
252b5132 RH |
12817 | } |
12818 | else | |
12819 | { | |
12820 | const char *newname; | |
12821 | segT new_seg; | |
12822 | ||
12823 | /* Switch to the right section. */ | |
12824 | seg = now_seg; | |
12825 | subseg = now_subseg; | |
12826 | switch (*args) | |
12827 | { | |
12828 | default: /* unused default case avoids warnings. */ | |
12829 | case 'L': | |
12830 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12831 | if (g_switch_value >= 8) |
252b5132 RH |
12832 | newname = ".lit8"; |
12833 | break; | |
12834 | case 'F': | |
3e722fb5 | 12835 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12836 | break; |
12837 | case 'l': | |
9c2799c2 | 12838 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12839 | newname = ".lit4"; |
12840 | break; | |
12841 | } | |
12842 | new_seg = subseg_new (newname, (subsegT) 0); | |
f3ded42a RS |
12843 | bfd_set_section_flags (stdoutput, new_seg, |
12844 | (SEC_ALLOC | |
12845 | | SEC_LOAD | |
12846 | | SEC_READONLY | |
12847 | | SEC_DATA)); | |
252b5132 | 12848 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
f3ded42a | 12849 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12850 | record_alignment (new_seg, 4); |
12851 | else | |
12852 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12853 | if (seg == now_seg) | |
12854 | as_bad (_("Can't use floating point insn in this section")); | |
12855 | ||
df58fc94 RS |
12856 | /* Set the argument to the current address in the |
12857 | section. */ | |
12858 | offset_expr.X_op = O_symbol; | |
12859 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12860 | offset_expr.X_add_number = 0; | |
12861 | ||
12862 | /* Put the floating point number into the section. */ | |
12863 | p = frag_more ((int) length); | |
12864 | memcpy (p, temp, length); | |
12865 | ||
12866 | /* Switch back to the original section. */ | |
12867 | subseg_set (seg, subseg); | |
12868 | } | |
12869 | } | |
12870 | continue; | |
12871 | ||
12872 | case 'i': /* 16-bit unsigned immediate. */ | |
12873 | case 'j': /* 16-bit signed immediate. */ | |
77bd4346 RS |
12874 | *offset_reloc = BFD_RELOC_LO16; |
12875 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0) | |
df58fc94 RS |
12876 | { |
12877 | int more; | |
12878 | offsetT minval, maxval; | |
12879 | ||
12880 | more = (insn + 1 < past | |
12881 | && strcmp (insn->name, insn[1].name) == 0); | |
12882 | ||
df58fc94 RS |
12883 | /* For compatibility with older assemblers, we accept |
12884 | 0x8000-0xffff as signed 16-bit numbers when only | |
12885 | signed numbers are allowed. */ | |
12886 | if (*args == 'i') | |
12887 | minval = 0, maxval = 0xffff; | |
12888 | else if (more) | |
12889 | minval = -0x8000, maxval = 0x7fff; | |
12890 | else | |
12891 | minval = -0x8000, maxval = 0xffff; | |
12892 | ||
77bd4346 RS |
12893 | if (offset_expr.X_op != O_constant |
12894 | || offset_expr.X_add_number < minval | |
12895 | || offset_expr.X_add_number > maxval) | |
df58fc94 RS |
12896 | { |
12897 | if (more) | |
12898 | break; | |
77bd4346 RS |
12899 | if (offset_expr.X_op == O_constant |
12900 | || offset_expr.X_op == O_big) | |
df58fc94 RS |
12901 | as_bad (_("Expression out of range")); |
12902 | } | |
12903 | } | |
12904 | s = expr_end; | |
12905 | continue; | |
12906 | ||
12907 | case 'o': /* 16-bit offset. */ | |
12908 | offset_reloc[0] = BFD_RELOC_LO16; | |
12909 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12910 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12911 | ||
12912 | /* Check whether there is only a single bracketed expression | |
12913 | left. If so, it must be the base register and the | |
12914 | constant must be zero. */ | |
12915 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12916 | { | |
12917 | offset_expr.X_op = O_constant; | |
12918 | offset_expr.X_add_number = 0; | |
12919 | continue; | |
12920 | } | |
12921 | ||
12922 | /* If this value won't fit into a 16 bit offset, then go | |
12923 | find a macro that will generate the 32 bit offset | |
12924 | code pattern. */ | |
12925 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12926 | && (offset_expr.X_op != O_constant | |
12927 | || offset_expr.X_add_number >= 0x8000 | |
12928 | || offset_expr.X_add_number < -0x8000)) | |
12929 | break; | |
12930 | ||
12931 | s = expr_end; | |
12932 | continue; | |
12933 | ||
12934 | case 'p': /* PC-relative offset. */ | |
12935 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12936 | my_getExpression (&offset_expr, s); | |
12937 | s = expr_end; | |
12938 | continue; | |
12939 | ||
12940 | case 'u': /* Upper 16 bits. */ | |
77bd4346 RS |
12941 | *offset_reloc = BFD_RELOC_LO16; |
12942 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12943 | && offset_expr.X_op == O_constant | |
12944 | && (offset_expr.X_add_number < 0 | |
12945 | || offset_expr.X_add_number >= 0x10000)) | |
df58fc94 | 12946 | as_bad (_("lui expression (%lu) not in range 0..65535"), |
77bd4346 | 12947 | (unsigned long) offset_expr.X_add_number); |
df58fc94 RS |
12948 | s = expr_end; |
12949 | continue; | |
12950 | ||
12951 | case 'a': /* 26-bit address. */ | |
27c5c572 | 12952 | jump: |
df58fc94 RS |
12953 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
12954 | my_getExpression (&offset_expr, s); | |
12955 | s = expr_end; | |
12956 | continue; | |
12957 | ||
12958 | case 'N': /* 3-bit branch condition code. */ | |
12959 | case 'M': /* 3-bit compare condition code. */ | |
12960 | rtype = RTYPE_CCC; | |
12961 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12962 | rtype |= RTYPE_FCC; | |
12963 | if (!reg_lookup (&s, rtype, ®no)) | |
12964 | break; | |
12965 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12966 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12967 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12968 | && (regno & 1) != 0) | |
12969 | as_warn (_("Condition code register should be even for %s, " | |
12970 | "was %d"), | |
12971 | str, regno); | |
12972 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12973 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12974 | && (regno & 3) != 0) | |
12975 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12976 | "was %d"), | |
12977 | str, regno); | |
12978 | if (*args == 'N') | |
12979 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12980 | else | |
12981 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12982 | continue; | |
12983 | ||
12984 | case 'H': | |
12985 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12986 | s += 2; | |
12987 | if (ISDIGIT (*s)) | |
12988 | { | |
12989 | c = 0; | |
12990 | do | |
12991 | { | |
12992 | c *= 10; | |
12993 | c += *s - '0'; | |
12994 | ++s; | |
12995 | } | |
12996 | while (ISDIGIT (*s)); | |
12997 | } | |
12998 | else | |
12999 | c = 8; /* Invalid sel value. */ | |
13000 | ||
13001 | if (c > 7) | |
13002 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
13003 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
13004 | continue; | |
13005 | ||
13006 | case 'e': | |
13007 | gas_assert (!mips_opts.micromips); | |
13008 | /* Must be at least one digit. */ | |
13009 | my_getExpression (&imm_expr, s); | |
13010 | check_absolute_expr (ip, &imm_expr); | |
13011 | ||
13012 | if ((unsigned long) imm_expr.X_add_number | |
13013 | > (unsigned long) OP_MASK_VECBYTE) | |
13014 | { | |
13015 | as_bad (_("bad byte vector index (%ld)"), | |
13016 | (long) imm_expr.X_add_number); | |
13017 | imm_expr.X_add_number = 0; | |
13018 | } | |
13019 | ||
13020 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
13021 | imm_expr.X_op = O_absent; | |
13022 | s = expr_end; | |
13023 | continue; | |
13024 | ||
13025 | case '%': | |
13026 | gas_assert (!mips_opts.micromips); | |
13027 | my_getExpression (&imm_expr, s); | |
13028 | check_absolute_expr (ip, &imm_expr); | |
13029 | ||
13030 | if ((unsigned long) imm_expr.X_add_number | |
13031 | > (unsigned long) OP_MASK_VECALIGN) | |
13032 | { | |
13033 | as_bad (_("bad byte vector index (%ld)"), | |
13034 | (long) imm_expr.X_add_number); | |
13035 | imm_expr.X_add_number = 0; | |
13036 | } | |
13037 | ||
13038 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
13039 | imm_expr.X_op = O_absent; | |
13040 | s = expr_end; | |
13041 | continue; | |
13042 | ||
13043 | case 'm': /* Opcode extension character. */ | |
13044 | gas_assert (mips_opts.micromips); | |
13045 | c = *++args; | |
13046 | switch (c) | |
13047 | { | |
13048 | case 'r': | |
13049 | if (strncmp (s, "$pc", 3) == 0) | |
13050 | { | |
13051 | s += 3; | |
13052 | continue; | |
13053 | } | |
13054 | break; | |
13055 | ||
13056 | case 'a': | |
13057 | case 'b': | |
13058 | case 'c': | |
13059 | case 'd': | |
13060 | case 'e': | |
13061 | case 'f': | |
13062 | case 'g': | |
13063 | case 'h': | |
df58fc94 RS |
13064 | case 'j': |
13065 | case 'l': | |
13066 | case 'm': | |
13067 | case 'n': | |
13068 | case 'p': | |
13069 | case 'q': | |
13070 | case 's': | |
13071 | case 't': | |
13072 | case 'x': | |
13073 | case 'y': | |
13074 | case 'z': | |
13075 | s_reset = s; | |
13076 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
13077 | if (regno == AT && mips_opts.at) | |
13078 | { | |
13079 | if (mips_opts.at == ATREG) | |
13080 | as_warn (_("Used $at without \".set noat\"")); | |
13081 | else | |
13082 | as_warn (_("Used $%u with \".set at=$%u\""), | |
13083 | regno, mips_opts.at); | |
13084 | } | |
13085 | if (!ok) | |
13086 | { | |
13087 | if (c == 'c') | |
13088 | { | |
13089 | gas_assert (args[1] == ','); | |
13090 | regno = lastregno; | |
13091 | ++args; | |
13092 | } | |
13093 | else if (c == 't') | |
13094 | { | |
13095 | gas_assert (args[1] == ','); | |
13096 | ++args; | |
13097 | continue; /* Nothing to do. */ | |
13098 | } | |
13099 | else | |
13100 | break; | |
13101 | } | |
13102 | ||
13103 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
13104 | { | |
13105 | if (regno == lastregno) | |
13106 | { | |
13107 | insn_error | |
13108 | = _("Source and destination must be different"); | |
13109 | continue; | |
13110 | } | |
13111 | if (regno == 31 && lastregno == 0xffffffff) | |
13112 | { | |
13113 | insn_error | |
13114 | = _("A destination register must be supplied"); | |
13115 | continue; | |
13116 | } | |
13117 | } | |
13118 | ||
13119 | if (*s == ' ') | |
13120 | ++s; | |
13121 | if (args[1] != *s) | |
13122 | { | |
13123 | if (c == 'e') | |
13124 | { | |
13125 | gas_assert (args[1] == ','); | |
13126 | regno = lastregno; | |
13127 | s = s_reset; | |
13128 | ++args; | |
13129 | } | |
13130 | else if (c == 't') | |
13131 | { | |
13132 | gas_assert (args[1] == ','); | |
13133 | s = s_reset; | |
13134 | ++args; | |
13135 | continue; /* Nothing to do. */ | |
13136 | } | |
13137 | } | |
13138 | ||
13139 | /* Make sure regno is the same as lastregno. */ | |
13140 | if (c == 't' && regno != lastregno) | |
13141 | break; | |
13142 | ||
13143 | /* Make sure regno is the same as destregno. */ | |
13144 | if (c == 'x' && regno != destregno) | |
13145 | break; | |
13146 | ||
13147 | /* We need to save regno, before regno maps to the | |
13148 | microMIPS register encoding. */ | |
13149 | lastregno = regno; | |
13150 | ||
13151 | if (c == 'f') | |
13152 | destregno = regno; | |
13153 | ||
13154 | switch (c) | |
13155 | { | |
13156 | case 'a': | |
13157 | if (regno != GP) | |
13158 | regno = ILLEGAL_REG; | |
13159 | break; | |
13160 | ||
13161 | case 'b': | |
13162 | regno = mips32_to_micromips_reg_b_map[regno]; | |
13163 | break; | |
13164 | ||
13165 | case 'c': | |
13166 | regno = mips32_to_micromips_reg_c_map[regno]; | |
13167 | break; | |
13168 | ||
13169 | case 'd': | |
13170 | regno = mips32_to_micromips_reg_d_map[regno]; | |
13171 | break; | |
13172 | ||
13173 | case 'e': | |
13174 | regno = mips32_to_micromips_reg_e_map[regno]; | |
13175 | break; | |
13176 | ||
13177 | case 'f': | |
13178 | regno = mips32_to_micromips_reg_f_map[regno]; | |
13179 | break; | |
13180 | ||
13181 | case 'g': | |
13182 | regno = mips32_to_micromips_reg_g_map[regno]; | |
13183 | break; | |
13184 | ||
13185 | case 'h': | |
e76ff5ab RS |
13186 | s += strspn (s, " \t"); |
13187 | if (*s != ',') | |
df58fc94 | 13188 | { |
e76ff5ab RS |
13189 | regno = ILLEGAL_REG; |
13190 | break; | |
df58fc94 | 13191 | } |
e76ff5ab RS |
13192 | ++s; |
13193 | s += strspn (s, " \t"); | |
13194 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no2); | |
13195 | if (!ok) | |
13196 | { | |
13197 | regno = ILLEGAL_REG; | |
13198 | break; | |
13199 | } | |
13200 | if (regno2 == AT && mips_opts.at) | |
13201 | { | |
13202 | if (mips_opts.at == ATREG) | |
13203 | as_warn (_("Used $at without \".set noat\"")); | |
13204 | else | |
13205 | as_warn (_("Used $%u with \".set at=$%u\""), | |
13206 | regno2, mips_opts.at); | |
13207 | } | |
13208 | regno = (mips_lookup_reg_pair | |
13209 | (regno, regno2, | |
13210 | micromips_to_32_reg_h_map1, | |
13211 | micromips_to_32_reg_h_map2, 8)); | |
df58fc94 RS |
13212 | break; |
13213 | ||
13214 | case 'l': | |
13215 | regno = mips32_to_micromips_reg_l_map[regno]; | |
13216 | break; | |
13217 | ||
13218 | case 'm': | |
13219 | regno = mips32_to_micromips_reg_m_map[regno]; | |
13220 | break; | |
13221 | ||
13222 | case 'n': | |
13223 | regno = mips32_to_micromips_reg_n_map[regno]; | |
13224 | break; | |
13225 | ||
13226 | case 'q': | |
13227 | regno = mips32_to_micromips_reg_q_map[regno]; | |
13228 | break; | |
13229 | ||
13230 | case 's': | |
13231 | if (regno != SP) | |
13232 | regno = ILLEGAL_REG; | |
13233 | break; | |
13234 | ||
13235 | case 'y': | |
13236 | if (regno != 31) | |
13237 | regno = ILLEGAL_REG; | |
13238 | break; | |
13239 | ||
13240 | case 'z': | |
13241 | if (regno != ZERO) | |
13242 | regno = ILLEGAL_REG; | |
13243 | break; | |
13244 | ||
13245 | case 'j': /* Do nothing. */ | |
13246 | case 'p': | |
13247 | case 't': | |
13248 | case 'x': | |
13249 | break; | |
13250 | ||
13251 | default: | |
b37df7c4 | 13252 | abort (); |
df58fc94 RS |
13253 | } |
13254 | ||
13255 | if (regno == ILLEGAL_REG) | |
13256 | break; | |
13257 | ||
13258 | switch (c) | |
13259 | { | |
13260 | case 'b': | |
13261 | INSERT_OPERAND (1, MB, *ip, regno); | |
13262 | break; | |
13263 | ||
13264 | case 'c': | |
13265 | INSERT_OPERAND (1, MC, *ip, regno); | |
13266 | break; | |
13267 | ||
13268 | case 'd': | |
13269 | INSERT_OPERAND (1, MD, *ip, regno); | |
13270 | break; | |
13271 | ||
13272 | case 'e': | |
13273 | INSERT_OPERAND (1, ME, *ip, regno); | |
13274 | break; | |
13275 | ||
13276 | case 'f': | |
13277 | INSERT_OPERAND (1, MF, *ip, regno); | |
13278 | break; | |
13279 | ||
13280 | case 'g': | |
13281 | INSERT_OPERAND (1, MG, *ip, regno); | |
13282 | break; | |
13283 | ||
13284 | case 'h': | |
13285 | INSERT_OPERAND (1, MH, *ip, regno); | |
13286 | break; | |
13287 | ||
df58fc94 RS |
13288 | case 'j': |
13289 | INSERT_OPERAND (1, MJ, *ip, regno); | |
13290 | break; | |
13291 | ||
13292 | case 'l': | |
13293 | INSERT_OPERAND (1, ML, *ip, regno); | |
13294 | break; | |
13295 | ||
13296 | case 'm': | |
13297 | INSERT_OPERAND (1, MM, *ip, regno); | |
13298 | break; | |
13299 | ||
13300 | case 'n': | |
13301 | INSERT_OPERAND (1, MN, *ip, regno); | |
13302 | break; | |
13303 | ||
13304 | case 'p': | |
13305 | INSERT_OPERAND (1, MP, *ip, regno); | |
13306 | break; | |
13307 | ||
13308 | case 'q': | |
13309 | INSERT_OPERAND (1, MQ, *ip, regno); | |
13310 | break; | |
13311 | ||
13312 | case 'a': /* Do nothing. */ | |
13313 | case 's': /* Do nothing. */ | |
13314 | case 't': /* Do nothing. */ | |
13315 | case 'x': /* Do nothing. */ | |
13316 | case 'y': /* Do nothing. */ | |
13317 | case 'z': /* Do nothing. */ | |
13318 | break; | |
13319 | ||
13320 | default: | |
b37df7c4 | 13321 | abort (); |
df58fc94 RS |
13322 | } |
13323 | continue; | |
13324 | ||
13325 | case 'A': | |
13326 | { | |
13327 | bfd_reloc_code_real_type r[3]; | |
13328 | expressionS ep; | |
13329 | int imm; | |
13330 | ||
13331 | /* Check whether there is only a single bracketed | |
13332 | expression left. If so, it must be the base register | |
13333 | and the constant must be zero. */ | |
13334 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13335 | { | |
13336 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
13337 | continue; | |
13338 | } | |
13339 | ||
13340 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13341 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
13342 | break; | |
13343 | ||
13344 | imm = ep.X_add_number >> 2; | |
13345 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
13346 | } | |
13347 | s = expr_end; | |
13348 | continue; | |
13349 | ||
13350 | case 'B': | |
13351 | { | |
13352 | bfd_reloc_code_real_type r[3]; | |
13353 | expressionS ep; | |
13354 | int imm; | |
13355 | ||
13356 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13357 | || ep.X_op != O_constant) | |
13358 | break; | |
13359 | ||
13360 | for (imm = 0; imm < 8; imm++) | |
13361 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
13362 | break; | |
13363 | if (imm >= 8) | |
13364 | break; | |
13365 | ||
13366 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
13367 | } | |
13368 | s = expr_end; | |
13369 | continue; | |
13370 | ||
13371 | case 'C': | |
13372 | { | |
13373 | bfd_reloc_code_real_type r[3]; | |
13374 | expressionS ep; | |
13375 | int imm; | |
13376 | ||
13377 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13378 | || ep.X_op != O_constant) | |
13379 | break; | |
13380 | ||
13381 | for (imm = 0; imm < 16; imm++) | |
13382 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
13383 | break; | |
13384 | if (imm >= 16) | |
13385 | break; | |
13386 | ||
13387 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
13388 | } | |
13389 | s = expr_end; | |
13390 | continue; | |
13391 | ||
13392 | case 'D': /* pc relative offset */ | |
13393 | case 'E': /* pc relative offset */ | |
13394 | my_getExpression (&offset_expr, s); | |
13395 | if (offset_expr.X_op == O_register) | |
13396 | break; | |
13397 | ||
40209cad MR |
13398 | if (!forced_insn_length) |
13399 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13400 | else if (c == 'D') | |
13401 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13402 | else | |
13403 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13404 | s = expr_end; |
13405 | continue; | |
13406 | ||
13407 | case 'F': | |
13408 | { | |
13409 | bfd_reloc_code_real_type r[3]; | |
13410 | expressionS ep; | |
13411 | int imm; | |
13412 | ||
13413 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13414 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13415 | break; | |
13416 | ||
13417 | imm = ep.X_add_number; | |
13418 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13419 | } | |
13420 | s = expr_end; | |
13421 | continue; | |
13422 | ||
13423 | case 'G': | |
13424 | { | |
13425 | bfd_reloc_code_real_type r[3]; | |
13426 | expressionS ep; | |
13427 | int imm; | |
13428 | ||
13429 | /* Check whether there is only a single bracketed | |
13430 | expression left. If so, it must be the base register | |
13431 | and the constant must be zero. */ | |
13432 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13433 | { | |
13434 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13435 | continue; | |
13436 | } | |
13437 | ||
13438 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13439 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13440 | break; | |
13441 | ||
13442 | imm = ep.X_add_number & 15; | |
13443 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13444 | } | |
13445 | s = expr_end; | |
13446 | continue; | |
13447 | ||
13448 | case 'H': | |
13449 | { | |
13450 | bfd_reloc_code_real_type r[3]; | |
13451 | expressionS ep; | |
13452 | int imm; | |
13453 | ||
13454 | /* Check whether there is only a single bracketed | |
13455 | expression left. If so, it must be the base register | |
13456 | and the constant must be zero. */ | |
13457 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13458 | { | |
13459 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13460 | continue; | |
13461 | } | |
13462 | ||
13463 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13464 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13465 | break; | |
13466 | ||
13467 | imm = ep.X_add_number >> 1; | |
13468 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13469 | } | |
13470 | s = expr_end; | |
13471 | continue; | |
13472 | ||
13473 | case 'I': | |
13474 | { | |
13475 | bfd_reloc_code_real_type r[3]; | |
13476 | expressionS ep; | |
13477 | int imm; | |
13478 | ||
13479 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13480 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13481 | break; | |
13482 | ||
13483 | imm = ep.X_add_number & 127; | |
13484 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13485 | } | |
13486 | s = expr_end; | |
13487 | continue; | |
13488 | ||
13489 | case 'J': | |
13490 | { | |
13491 | bfd_reloc_code_real_type r[3]; | |
13492 | expressionS ep; | |
13493 | int imm; | |
13494 | ||
13495 | /* Check whether there is only a single bracketed | |
13496 | expression left. If so, it must be the base register | |
13497 | and the constant must be zero. */ | |
13498 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13499 | { | |
13500 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13501 | continue; | |
13502 | } | |
13503 | ||
13504 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13505 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13506 | break; | |
13507 | ||
13508 | imm = ep.X_add_number >> 2; | |
13509 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13510 | } | |
13511 | s = expr_end; | |
13512 | continue; | |
13513 | ||
13514 | case 'L': | |
13515 | { | |
13516 | bfd_reloc_code_real_type r[3]; | |
13517 | expressionS ep; | |
13518 | int imm; | |
13519 | ||
13520 | /* Check whether there is only a single bracketed | |
13521 | expression left. If so, it must be the base register | |
13522 | and the constant must be zero. */ | |
13523 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13524 | { | |
13525 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13526 | continue; | |
13527 | } | |
13528 | ||
13529 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13530 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13531 | break; | |
13532 | ||
13533 | imm = ep.X_add_number; | |
13534 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13535 | } | |
13536 | s = expr_end; | |
13537 | continue; | |
13538 | ||
13539 | case 'M': | |
13540 | { | |
13541 | bfd_reloc_code_real_type r[3]; | |
13542 | expressionS ep; | |
13543 | int imm; | |
13544 | ||
13545 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13546 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13547 | break; | |
13548 | ||
13549 | imm = ep.X_add_number & 7; | |
13550 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13551 | } | |
13552 | s = expr_end; | |
13553 | continue; | |
13554 | ||
13555 | case 'N': /* Register list for lwm and swm. */ | |
13556 | { | |
13557 | /* A comma-separated list of registers and/or | |
13558 | dash-separated contiguous ranges including | |
13559 | both ra and a set of one or more registers | |
13560 | starting at s0 up to s3 which have to be | |
13561 | consecutive, e.g.: | |
13562 | ||
13563 | s0, ra | |
13564 | s0, s1, ra, s2, s3 | |
13565 | s0-s2, ra | |
13566 | ||
13567 | and any permutations of these. */ | |
13568 | unsigned int reglist; | |
13569 | int imm; | |
13570 | ||
13571 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13572 | break; | |
13573 | ||
13574 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13575 | break; | |
13576 | ||
13577 | reglist = (reglist >> 17) & 7; | |
13578 | reglist += 1; | |
13579 | if ((reglist & -reglist) != reglist) | |
13580 | break; | |
252b5132 | 13581 | |
df58fc94 RS |
13582 | imm = ffs (reglist) - 1; |
13583 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13584 | } | |
13585 | continue; | |
252b5132 | 13586 | |
df58fc94 RS |
13587 | case 'O': /* sdbbp 4-bit code. */ |
13588 | { | |
13589 | bfd_reloc_code_real_type r[3]; | |
13590 | expressionS ep; | |
13591 | int imm; | |
13592 | ||
13593 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13594 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13595 | break; | |
13596 | ||
13597 | imm = ep.X_add_number; | |
13598 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13599 | } |
df58fc94 RS |
13600 | s = expr_end; |
13601 | continue; | |
252b5132 | 13602 | |
df58fc94 RS |
13603 | case 'P': |
13604 | { | |
13605 | bfd_reloc_code_real_type r[3]; | |
13606 | expressionS ep; | |
13607 | int imm; | |
5e0116d5 | 13608 | |
df58fc94 RS |
13609 | if (my_getSmallExpression (&ep, r, s) > 0 |
13610 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13611 | break; | |
5e0116d5 | 13612 | |
df58fc94 RS |
13613 | imm = ep.X_add_number >> 2; |
13614 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13615 | } | |
13616 | s = expr_end; | |
13617 | continue; | |
5e0116d5 | 13618 | |
df58fc94 RS |
13619 | case 'Q': |
13620 | { | |
13621 | bfd_reloc_code_real_type r[3]; | |
13622 | expressionS ep; | |
13623 | int imm; | |
5e0116d5 | 13624 | |
df58fc94 RS |
13625 | if (my_getSmallExpression (&ep, r, s) > 0 |
13626 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13627 | break; | |
252b5132 | 13628 | |
df58fc94 RS |
13629 | imm = ep.X_add_number >> 2; |
13630 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13631 | } | |
13632 | s = expr_end; | |
13633 | continue; | |
4614d845 | 13634 | |
df58fc94 RS |
13635 | case 'U': |
13636 | { | |
13637 | bfd_reloc_code_real_type r[3]; | |
13638 | expressionS ep; | |
13639 | int imm; | |
13640 | ||
13641 | /* Check whether there is only a single bracketed | |
13642 | expression left. If so, it must be the base register | |
13643 | and the constant must be zero. */ | |
13644 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13645 | { | |
13646 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13647 | continue; | |
13648 | } | |
13649 | ||
13650 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13651 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13652 | break; | |
13653 | ||
13654 | imm = ep.X_add_number >> 2; | |
13655 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13656 | } | |
13657 | s = expr_end; | |
5e0116d5 | 13658 | continue; |
252b5132 | 13659 | |
df58fc94 RS |
13660 | case 'W': |
13661 | { | |
13662 | bfd_reloc_code_real_type r[3]; | |
13663 | expressionS ep; | |
13664 | int imm; | |
252b5132 | 13665 | |
df58fc94 RS |
13666 | if (my_getSmallExpression (&ep, r, s) > 0 |
13667 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13668 | break; | |
252b5132 | 13669 | |
df58fc94 RS |
13670 | imm = ep.X_add_number >> 2; |
13671 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13672 | } | |
13673 | s = expr_end; | |
13674 | continue; | |
252b5132 | 13675 | |
df58fc94 RS |
13676 | case 'X': |
13677 | { | |
13678 | bfd_reloc_code_real_type r[3]; | |
13679 | expressionS ep; | |
13680 | int imm; | |
252b5132 | 13681 | |
df58fc94 RS |
13682 | if (my_getSmallExpression (&ep, r, s) > 0 |
13683 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13684 | break; | |
252b5132 | 13685 | |
df58fc94 RS |
13686 | imm = ep.X_add_number; |
13687 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13688 | } | |
13689 | s = expr_end; | |
13690 | continue; | |
252b5132 | 13691 | |
df58fc94 RS |
13692 | case 'Y': |
13693 | { | |
13694 | bfd_reloc_code_real_type r[3]; | |
13695 | expressionS ep; | |
13696 | int imm; | |
156c2f8b | 13697 | |
df58fc94 RS |
13698 | if (my_getSmallExpression (&ep, r, s) > 0 |
13699 | || expr_const_in_range (&ep, -2, 2, 2) | |
13700 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13701 | break; | |
156c2f8b | 13702 | |
df58fc94 RS |
13703 | imm = ep.X_add_number >> 2; |
13704 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13705 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13706 | } | |
13707 | s = expr_end; | |
13708 | continue; | |
60b63b72 | 13709 | |
df58fc94 RS |
13710 | case 'Z': |
13711 | { | |
13712 | bfd_reloc_code_real_type r[3]; | |
13713 | expressionS ep; | |
13714 | ||
13715 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13716 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13717 | break; | |
13718 | } | |
13719 | s = expr_end; | |
13720 | continue; | |
13721 | ||
13722 | default: | |
13723 | as_bad (_("Internal error: bad microMIPS opcode " | |
13724 | "(unknown extension operand type `m%c'): %s %s"), | |
13725 | *args, insn->name, insn->args); | |
13726 | /* Further processing is fruitless. */ | |
13727 | return; | |
60b63b72 | 13728 | } |
df58fc94 | 13729 | break; |
60b63b72 | 13730 | |
df58fc94 RS |
13731 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13732 | gas_assert (mips_opts.micromips); | |
13733 | { | |
13734 | /* A comma-separated list of registers and/or | |
13735 | dash-separated contiguous ranges including | |
13736 | at least one of ra and a set of one or more | |
13737 | registers starting at s0 up to s7 and then | |
13738 | s8 which have to be consecutive, e.g.: | |
13739 | ||
13740 | ra | |
13741 | s0 | |
13742 | ra, s0, s1, s2 | |
13743 | s0-s8 | |
13744 | s0-s5, ra | |
13745 | ||
13746 | and any permutations of these. */ | |
13747 | unsigned int reglist; | |
13748 | int imm; | |
13749 | int ra; | |
13750 | ||
13751 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13752 | break; | |
13753 | ||
13754 | if ((reglist & 0x3f00ffff) != 0) | |
13755 | break; | |
13756 | ||
13757 | ra = (reglist >> 27) & 0x10; | |
13758 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13759 | reglist += 1; | |
13760 | if ((reglist & -reglist) != reglist) | |
13761 | break; | |
13762 | ||
13763 | imm = (ffs (reglist) - 1) | ra; | |
13764 | INSERT_OPERAND (1, RT, *ip, imm); | |
13765 | imm_expr.X_op = O_absent; | |
13766 | } | |
60b63b72 RS |
13767 | continue; |
13768 | ||
df58fc94 RS |
13769 | case '|': /* 4-bit trap code. */ |
13770 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13771 | my_getExpression (&imm_expr, s); |
13772 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13773 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13774 | > MICROMIPSOP_MASK_TRAP) |
13775 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13776 | (unsigned long) imm_expr.X_add_number, | |
13777 | ip->insn_mo->name); | |
13778 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13779 | imm_expr.X_op = O_absent; |
13780 | s = expr_end; | |
13781 | continue; | |
13782 | ||
252b5132 | 13783 | default: |
f71d0d44 | 13784 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13785 | abort (); |
252b5132 RH |
13786 | } |
13787 | break; | |
13788 | } | |
13789 | /* Args don't match. */ | |
df58fc94 RS |
13790 | s = argsStart; |
13791 | insn_error = _("Illegal operands"); | |
13792 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13793 | { |
13794 | ++insn; | |
252b5132 RH |
13795 | continue; |
13796 | } | |
df58fc94 RS |
13797 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13798 | { | |
13799 | gas_assert (firstinsn); | |
13800 | need_delay_slot_ok = FALSE; | |
13801 | past = insn + 1; | |
13802 | insn = firstinsn; | |
13803 | continue; | |
13804 | } | |
252b5132 RH |
13805 | return; |
13806 | } | |
13807 | } | |
13808 | ||
0499d65b TS |
13809 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13810 | ||
77bd4346 RS |
13811 | /* As for mips_ip, but used when assembling MIPS16 code. |
13812 | Also set forced_insn_length to the resulting instruction size in | |
13813 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13814 | |
13815 | static void | |
17a2f251 | 13816 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13817 | { |
13818 | char *s; | |
13819 | const char *args; | |
13820 | struct mips_opcode *insn; | |
13821 | char *argsstart; | |
13822 | unsigned int regno; | |
13823 | unsigned int lastregno = 0; | |
13824 | char *s_reset; | |
d6f16593 | 13825 | size_t i; |
252b5132 RH |
13826 | |
13827 | insn_error = NULL; | |
13828 | ||
df58fc94 | 13829 | forced_insn_length = 0; |
252b5132 | 13830 | |
3882b010 | 13831 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13832 | ; |
13833 | switch (*s) | |
13834 | { | |
13835 | case '\0': | |
13836 | break; | |
13837 | ||
13838 | case ' ': | |
13839 | *s++ = '\0'; | |
13840 | break; | |
13841 | ||
13842 | case '.': | |
13843 | if (s[1] == 't' && s[2] == ' ') | |
13844 | { | |
13845 | *s = '\0'; | |
df58fc94 | 13846 | forced_insn_length = 2; |
252b5132 RH |
13847 | s += 3; |
13848 | break; | |
13849 | } | |
13850 | else if (s[1] == 'e' && s[2] == ' ') | |
13851 | { | |
13852 | *s = '\0'; | |
df58fc94 | 13853 | forced_insn_length = 4; |
252b5132 RH |
13854 | s += 3; |
13855 | break; | |
13856 | } | |
13857 | /* Fall through. */ | |
13858 | default: | |
13859 | insn_error = _("unknown opcode"); | |
13860 | return; | |
13861 | } | |
13862 | ||
df58fc94 RS |
13863 | if (mips_opts.noautoextend && !forced_insn_length) |
13864 | forced_insn_length = 2; | |
252b5132 RH |
13865 | |
13866 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13867 | { | |
13868 | insn_error = _("unrecognized opcode"); | |
13869 | return; | |
13870 | } | |
13871 | ||
13872 | argsstart = s; | |
13873 | for (;;) | |
13874 | { | |
9b3f89ee | 13875 | bfd_boolean ok; |
77bd4346 | 13876 | char relax_char; |
9b3f89ee | 13877 | |
9c2799c2 | 13878 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13879 | |
037b32b9 | 13880 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13881 | if (! ok) |
13882 | { | |
13883 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13884 | && strcmp (insn->name, insn[1].name) == 0) | |
13885 | { | |
13886 | ++insn; | |
13887 | continue; | |
13888 | } | |
13889 | else | |
13890 | { | |
13891 | if (!insn_error) | |
13892 | { | |
13893 | static char buf[100]; | |
13894 | sprintf (buf, | |
7bd942df | 13895 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13896 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13897 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13898 | insn_error = buf; | |
13899 | } | |
13900 | return; | |
13901 | } | |
13902 | } | |
13903 | ||
1e915849 | 13904 | create_insn (ip, insn); |
252b5132 | 13905 | imm_expr.X_op = O_absent; |
5f74bc13 | 13906 | imm2_expr.X_op = O_absent; |
252b5132 | 13907 | offset_expr.X_op = O_absent; |
f6688943 TS |
13908 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13909 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13910 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
77bd4346 | 13911 | relax_char = 0; |
252b5132 RH |
13912 | for (args = insn->args; 1; ++args) |
13913 | { | |
13914 | int c; | |
13915 | ||
13916 | if (*s == ' ') | |
13917 | ++s; | |
13918 | ||
13919 | /* In this switch statement we call break if we did not find | |
13920 | a match, continue if we did find a match, or return if we | |
13921 | are done. */ | |
13922 | ||
13923 | c = *args; | |
13924 | switch (c) | |
13925 | { | |
13926 | case '\0': | |
13927 | if (*s == '\0') | |
13928 | { | |
b886a2ab RS |
13929 | offsetT value; |
13930 | ||
252b5132 | 13931 | /* Stuff the immediate value in now, if we can. */ |
77bd4346 RS |
13932 | if (insn->pinfo == INSN_MACRO) |
13933 | { | |
13934 | gas_assert (relax_char == 0); | |
13935 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
13936 | } | |
13937 | else if (relax_char | |
13938 | && offset_expr.X_op == O_constant | |
13939 | && calculate_reloc (*offset_reloc, | |
13940 | offset_expr.X_add_number, | |
13941 | &value)) | |
252b5132 | 13942 | { |
77bd4346 RS |
13943 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, |
13944 | forced_insn_length, &ip->insn_opcode); | |
13945 | offset_expr.X_op = O_absent; | |
43c0598f | 13946 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 | 13947 | } |
77bd4346 RS |
13948 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) |
13949 | { | |
13950 | if (forced_insn_length == 2) | |
13951 | as_bad (_("invalid unextended operand value")); | |
13952 | forced_insn_length = 4; | |
13953 | ip->insn_opcode |= MIPS16_EXTEND; | |
13954 | } | |
13955 | else if (relax_char) | |
13956 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
252b5132 RH |
13957 | |
13958 | return; | |
13959 | } | |
13960 | break; | |
13961 | ||
13962 | case ',': | |
13963 | if (*s++ == c) | |
13964 | continue; | |
13965 | s--; | |
13966 | switch (*++args) | |
13967 | { | |
13968 | case 'v': | |
bf12938e | 13969 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13970 | continue; |
13971 | case 'w': | |
bf12938e | 13972 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13973 | continue; |
13974 | } | |
13975 | break; | |
13976 | ||
13977 | case '(': | |
13978 | case ')': | |
13979 | if (*s++ == c) | |
13980 | continue; | |
13981 | break; | |
13982 | ||
13983 | case 'v': | |
13984 | case 'w': | |
13985 | if (s[0] != '$') | |
13986 | { | |
13987 | if (c == 'v') | |
bf12938e | 13988 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13989 | else |
bf12938e | 13990 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13991 | ++args; |
13992 | continue; | |
13993 | } | |
13994 | /* Fall through. */ | |
13995 | case 'x': | |
13996 | case 'y': | |
13997 | case 'z': | |
13998 | case 'Z': | |
13999 | case '0': | |
14000 | case 'S': | |
14001 | case 'R': | |
14002 | case 'X': | |
14003 | case 'Y': | |
707bfff6 TS |
14004 | s_reset = s; |
14005 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 14006 | { |
707bfff6 | 14007 | if (c == 'v' || c == 'w') |
85b51719 | 14008 | { |
707bfff6 | 14009 | if (c == 'v') |
a9e24354 | 14010 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 14011 | else |
a9e24354 | 14012 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
14013 | ++args; |
14014 | continue; | |
85b51719 | 14015 | } |
707bfff6 | 14016 | break; |
252b5132 RH |
14017 | } |
14018 | ||
14019 | if (*s == ' ') | |
14020 | ++s; | |
14021 | if (args[1] != *s) | |
14022 | { | |
14023 | if (c == 'v' || c == 'w') | |
14024 | { | |
14025 | regno = mips16_to_32_reg_map[lastregno]; | |
14026 | s = s_reset; | |
f9419b05 | 14027 | ++args; |
252b5132 RH |
14028 | } |
14029 | } | |
14030 | ||
14031 | switch (c) | |
14032 | { | |
14033 | case 'x': | |
14034 | case 'y': | |
14035 | case 'z': | |
14036 | case 'v': | |
14037 | case 'w': | |
14038 | case 'Z': | |
14039 | regno = mips32_to_16_reg_map[regno]; | |
14040 | break; | |
14041 | ||
14042 | case '0': | |
14043 | if (regno != 0) | |
14044 | regno = ILLEGAL_REG; | |
14045 | break; | |
14046 | ||
14047 | case 'S': | |
14048 | if (regno != SP) | |
14049 | regno = ILLEGAL_REG; | |
14050 | break; | |
14051 | ||
14052 | case 'R': | |
14053 | if (regno != RA) | |
14054 | regno = ILLEGAL_REG; | |
14055 | break; | |
14056 | ||
14057 | case 'X': | |
14058 | case 'Y': | |
741fe287 MR |
14059 | if (regno == AT && mips_opts.at) |
14060 | { | |
14061 | if (mips_opts.at == ATREG) | |
14062 | as_warn (_("used $at without \".set noat\"")); | |
14063 | else | |
14064 | as_warn (_("used $%u with \".set at=$%u\""), | |
14065 | regno, mips_opts.at); | |
14066 | } | |
252b5132 RH |
14067 | break; |
14068 | ||
14069 | default: | |
b37df7c4 | 14070 | abort (); |
252b5132 RH |
14071 | } |
14072 | ||
14073 | if (regno == ILLEGAL_REG) | |
14074 | break; | |
14075 | ||
14076 | switch (c) | |
14077 | { | |
14078 | case 'x': | |
14079 | case 'v': | |
bf12938e | 14080 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
14081 | break; |
14082 | case 'y': | |
14083 | case 'w': | |
bf12938e | 14084 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
14085 | break; |
14086 | case 'z': | |
bf12938e | 14087 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
14088 | break; |
14089 | case 'Z': | |
bf12938e | 14090 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
14091 | case '0': |
14092 | case 'S': | |
14093 | case 'R': | |
14094 | break; | |
14095 | case 'X': | |
bf12938e | 14096 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
14097 | break; |
14098 | case 'Y': | |
14099 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 14100 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
14101 | break; |
14102 | default: | |
b37df7c4 | 14103 | abort (); |
252b5132 RH |
14104 | } |
14105 | ||
14106 | lastregno = regno; | |
14107 | continue; | |
14108 | ||
14109 | case 'P': | |
14110 | if (strncmp (s, "$pc", 3) == 0) | |
14111 | { | |
14112 | s += 3; | |
14113 | continue; | |
14114 | } | |
14115 | break; | |
14116 | ||
252b5132 RH |
14117 | case '5': |
14118 | case 'H': | |
14119 | case 'W': | |
14120 | case 'D': | |
14121 | case 'j': | |
252b5132 RH |
14122 | case 'V': |
14123 | case 'C': | |
14124 | case 'U': | |
14125 | case 'k': | |
14126 | case 'K': | |
77bd4346 | 14127 | i = my_getSmallExpression (&offset_expr, offset_reloc, s); |
d6f16593 | 14128 | if (i > 0) |
252b5132 | 14129 | { |
77bd4346 | 14130 | relax_char = c; |
d6f16593 MR |
14131 | s = expr_end; |
14132 | continue; | |
252b5132 | 14133 | } |
77bd4346 | 14134 | *offset_reloc = BFD_RELOC_UNUSED; |
d6f16593 MR |
14135 | /* Fall through. */ |
14136 | case '<': | |
14137 | case '>': | |
14138 | case '[': | |
14139 | case ']': | |
14140 | case '4': | |
14141 | case '8': | |
77bd4346 RS |
14142 | my_getExpression (&offset_expr, s); |
14143 | if (offset_expr.X_op == O_register) | |
252b5132 RH |
14144 | { |
14145 | /* What we thought was an expression turned out to | |
14146 | be a register. */ | |
14147 | ||
14148 | if (s[0] == '(' && args[1] == '(') | |
14149 | { | |
14150 | /* It looks like the expression was omitted | |
14151 | before a register indirection, which means | |
14152 | that the expression is implicitly zero. We | |
77bd4346 | 14153 | still set up offset_expr, so that we handle |
252b5132 | 14154 | explicit extensions correctly. */ |
77bd4346 RS |
14155 | offset_expr.X_op = O_constant; |
14156 | offset_expr.X_add_number = 0; | |
14157 | relax_char = c; | |
252b5132 RH |
14158 | continue; |
14159 | } | |
14160 | ||
14161 | break; | |
14162 | } | |
14163 | ||
14164 | /* We need to relax this instruction. */ | |
77bd4346 | 14165 | relax_char = c; |
252b5132 RH |
14166 | s = expr_end; |
14167 | continue; | |
14168 | ||
14169 | case 'p': | |
14170 | case 'q': | |
14171 | case 'A': | |
14172 | case 'B': | |
14173 | case 'E': | |
14174 | /* We use offset_reloc rather than imm_reloc for the PC | |
14175 | relative operands. This lets macros with both | |
14176 | immediate and address operands work correctly. */ | |
14177 | my_getExpression (&offset_expr, s); | |
14178 | ||
14179 | if (offset_expr.X_op == O_register) | |
14180 | break; | |
14181 | ||
14182 | /* We need to relax this instruction. */ | |
77bd4346 | 14183 | relax_char = c; |
252b5132 RH |
14184 | s = expr_end; |
14185 | continue; | |
14186 | ||
14187 | case '6': /* break code */ | |
14188 | my_getExpression (&imm_expr, s); | |
14189 | check_absolute_expr (ip, &imm_expr); | |
14190 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
14191 | as_warn (_("Invalid value for `%s' (%lu)"), |
14192 | ip->insn_mo->name, | |
14193 | (unsigned long) imm_expr.X_add_number); | |
14194 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
14195 | imm_expr.X_op = O_absent; |
14196 | s = expr_end; | |
14197 | continue; | |
14198 | ||
cc537e56 RS |
14199 | case 'I': |
14200 | my_getExpression (&imm_expr, s); | |
14201 | if (imm_expr.X_op != O_big | |
14202 | && imm_expr.X_op != O_constant) | |
14203 | insn_error = _("absolute expression required"); | |
14204 | if (HAVE_32BIT_GPRS) | |
14205 | normalize_constant_expr (&imm_expr); | |
14206 | s = expr_end; | |
14207 | continue; | |
14208 | ||
252b5132 | 14209 | case 'a': /* 26 bit address */ |
27c5c572 | 14210 | case 'i': |
252b5132 RH |
14211 | my_getExpression (&offset_expr, s); |
14212 | s = expr_end; | |
f6688943 | 14213 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
14214 | ip->insn_opcode <<= 16; |
14215 | continue; | |
14216 | ||
14217 | case 'l': /* register list for entry macro */ | |
14218 | case 'L': /* register list for exit macro */ | |
14219 | { | |
14220 | int mask; | |
14221 | ||
14222 | if (c == 'l') | |
14223 | mask = 0; | |
14224 | else | |
14225 | mask = 7 << 3; | |
14226 | while (*s != '\0') | |
14227 | { | |
707bfff6 | 14228 | unsigned int freg, reg1, reg2; |
252b5132 RH |
14229 | |
14230 | while (*s == ' ' || *s == ',') | |
14231 | ++s; | |
707bfff6 | 14232 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 14233 | freg = 0; |
707bfff6 TS |
14234 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
14235 | freg = 1; | |
252b5132 RH |
14236 | else |
14237 | { | |
707bfff6 TS |
14238 | as_bad (_("can't parse register list")); |
14239 | break; | |
252b5132 RH |
14240 | } |
14241 | if (*s == ' ') | |
14242 | ++s; | |
14243 | if (*s != '-') | |
14244 | reg2 = reg1; | |
14245 | else | |
14246 | { | |
14247 | ++s; | |
707bfff6 TS |
14248 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
14249 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 14250 | { |
707bfff6 TS |
14251 | as_bad (_("invalid register list")); |
14252 | break; | |
252b5132 RH |
14253 | } |
14254 | } | |
14255 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
14256 | { | |
14257 | mask &= ~ (7 << 3); | |
14258 | mask |= 5 << 3; | |
14259 | } | |
14260 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
14261 | { | |
14262 | mask &= ~ (7 << 3); | |
14263 | mask |= 6 << 3; | |
14264 | } | |
14265 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
14266 | mask |= (reg2 - 3) << 3; | |
14267 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
14268 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 14269 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
14270 | mask |= 1; |
14271 | else | |
14272 | { | |
14273 | as_bad (_("invalid register list")); | |
14274 | break; | |
14275 | } | |
14276 | } | |
14277 | /* The mask is filled in in the opcode table for the | |
14278 | benefit of the disassembler. We remove it before | |
14279 | applying the actual mask. */ | |
14280 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
14281 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
14282 | } | |
14283 | continue; | |
14284 | ||
0499d65b TS |
14285 | case 'm': /* Register list for save insn. */ |
14286 | case 'M': /* Register list for restore insn. */ | |
14287 | { | |
5c04167a | 14288 | int opcode = ip->insn_opcode; |
0499d65b | 14289 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 14290 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
14291 | |
14292 | while (*s != '\0') | |
14293 | { | |
14294 | unsigned int reg1, reg2; | |
14295 | ||
14296 | SKIP_SPACE_TABS (s); | |
14297 | while (*s == ',') | |
14298 | ++s; | |
14299 | SKIP_SPACE_TABS (s); | |
14300 | ||
14301 | my_getExpression (&imm_expr, s); | |
14302 | if (imm_expr.X_op == O_constant) | |
14303 | { | |
14304 | /* Handle the frame size. */ | |
14305 | if (seen_framesz) | |
14306 | { | |
14307 | as_bad (_("more than one frame size in list")); | |
14308 | break; | |
14309 | } | |
14310 | seen_framesz = 1; | |
14311 | framesz = imm_expr.X_add_number; | |
14312 | imm_expr.X_op = O_absent; | |
14313 | s = expr_end; | |
14314 | continue; | |
14315 | } | |
14316 | ||
707bfff6 | 14317 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
14318 | { |
14319 | as_bad (_("can't parse register list")); | |
14320 | break; | |
14321 | } | |
0499d65b | 14322 | |
707bfff6 TS |
14323 | while (*s == ' ') |
14324 | ++s; | |
14325 | ||
0499d65b TS |
14326 | if (*s != '-') |
14327 | reg2 = reg1; | |
14328 | else | |
14329 | { | |
14330 | ++s; | |
707bfff6 TS |
14331 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
14332 | || reg2 < reg1) | |
0499d65b TS |
14333 | { |
14334 | as_bad (_("can't parse register list")); | |
14335 | break; | |
14336 | } | |
0499d65b TS |
14337 | } |
14338 | ||
14339 | while (reg1 <= reg2) | |
14340 | { | |
14341 | if (reg1 >= 4 && reg1 <= 7) | |
14342 | { | |
3a93f742 | 14343 | if (!seen_framesz) |
0499d65b | 14344 | /* args $a0-$a3 */ |
91d6fa6a | 14345 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
14346 | else |
14347 | /* statics $a0-$a3 */ | |
14348 | statics |= 1 << (reg1 - 4); | |
14349 | } | |
14350 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
14351 | { | |
14352 | /* $s0-$s8 */ | |
14353 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
14354 | } | |
14355 | else if (reg1 == 31) | |
14356 | { | |
14357 | /* Add $ra to insn. */ | |
14358 | opcode |= 0x40; | |
14359 | } | |
14360 | else | |
14361 | { | |
14362 | as_bad (_("unexpected register in list")); | |
14363 | break; | |
14364 | } | |
14365 | if (++reg1 == 24) | |
14366 | reg1 = 30; | |
14367 | } | |
14368 | } | |
14369 | ||
14370 | /* Encode args/statics combination. */ | |
91d6fa6a | 14371 | if (nargs & statics) |
0499d65b | 14372 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 14373 | else if (nargs == 0xf) |
0499d65b TS |
14374 | /* All $a0-$a3 are args. */ |
14375 | opcode |= MIPS16_ALL_ARGS << 16; | |
14376 | else if (statics == 0xf) | |
14377 | /* All $a0-$a3 are statics. */ | |
14378 | opcode |= MIPS16_ALL_STATICS << 16; | |
14379 | else | |
14380 | { | |
14381 | int narg = 0, nstat = 0; | |
14382 | ||
14383 | /* Count arg registers. */ | |
91d6fa6a | 14384 | while (nargs & 0x1) |
0499d65b | 14385 | { |
91d6fa6a | 14386 | nargs >>= 1; |
0499d65b TS |
14387 | narg++; |
14388 | } | |
91d6fa6a | 14389 | if (nargs != 0) |
0499d65b TS |
14390 | as_bad (_("invalid arg register list")); |
14391 | ||
14392 | /* Count static registers. */ | |
14393 | while (statics & 0x8) | |
14394 | { | |
14395 | statics = (statics << 1) & 0xf; | |
14396 | nstat++; | |
14397 | } | |
14398 | if (statics != 0) | |
14399 | as_bad (_("invalid static register list")); | |
14400 | ||
14401 | /* Encode args/statics. */ | |
14402 | opcode |= ((narg << 2) | nstat) << 16; | |
14403 | } | |
14404 | ||
14405 | /* Encode $s0/$s1. */ | |
14406 | if (sregs & (1 << 0)) /* $s0 */ | |
14407 | opcode |= 0x20; | |
14408 | if (sregs & (1 << 1)) /* $s1 */ | |
14409 | opcode |= 0x10; | |
14410 | sregs >>= 2; | |
14411 | ||
14412 | if (sregs != 0) | |
14413 | { | |
14414 | /* Count regs $s2-$s8. */ | |
14415 | int nsreg = 0; | |
14416 | while (sregs & 1) | |
14417 | { | |
14418 | sregs >>= 1; | |
14419 | nsreg++; | |
14420 | } | |
14421 | if (sregs != 0) | |
14422 | as_bad (_("invalid static register list")); | |
14423 | /* Encode $s2-$s8. */ | |
14424 | opcode |= nsreg << 24; | |
14425 | } | |
14426 | ||
14427 | /* Encode frame size. */ | |
14428 | if (!seen_framesz) | |
14429 | as_bad (_("missing frame size")); | |
14430 | else if ((framesz & 7) != 0 || framesz < 0 | |
14431 | || framesz > 0xff * 8) | |
14432 | as_bad (_("invalid frame size")); | |
14433 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14434 | { | |
14435 | framesz /= 8; | |
14436 | opcode |= (((framesz & 0xf0) << 16) | |
14437 | | (framesz & 0x0f)); | |
14438 | } | |
14439 | ||
14440 | /* Finally build the instruction. */ | |
14441 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14442 | opcode |= MIPS16_EXTEND; |
14443 | ip->insn_opcode = opcode; | |
0499d65b TS |
14444 | } |
14445 | continue; | |
14446 | ||
252b5132 RH |
14447 | case 'e': /* extend code */ |
14448 | my_getExpression (&imm_expr, s); | |
14449 | check_absolute_expr (ip, &imm_expr); | |
14450 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14451 | { | |
14452 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14453 | ip->insn_mo->name, | |
14454 | (unsigned long) imm_expr.X_add_number); | |
14455 | imm_expr.X_add_number &= 0x7ff; | |
14456 | } | |
14457 | ip->insn_opcode |= imm_expr.X_add_number; | |
14458 | imm_expr.X_op = O_absent; | |
14459 | s = expr_end; | |
14460 | continue; | |
14461 | ||
14462 | default: | |
b37df7c4 | 14463 | abort (); |
252b5132 RH |
14464 | } |
14465 | break; | |
14466 | } | |
14467 | ||
14468 | /* Args don't match. */ | |
14469 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14470 | strcmp (insn->name, insn[1].name) == 0) | |
14471 | { | |
14472 | ++insn; | |
14473 | s = argsstart; | |
14474 | continue; | |
14475 | } | |
14476 | ||
14477 | insn_error = _("illegal operands"); | |
14478 | ||
14479 | return; | |
14480 | } | |
14481 | } | |
14482 | ||
14483 | /* This structure holds information we know about a mips16 immediate | |
14484 | argument type. */ | |
14485 | ||
e972090a NC |
14486 | struct mips16_immed_operand |
14487 | { | |
252b5132 RH |
14488 | /* The type code used in the argument string in the opcode table. */ |
14489 | int type; | |
14490 | /* The number of bits in the short form of the opcode. */ | |
14491 | int nbits; | |
14492 | /* The number of bits in the extended form of the opcode. */ | |
14493 | int extbits; | |
14494 | /* The amount by which the short form is shifted when it is used; | |
14495 | for example, the sw instruction has a shift count of 2. */ | |
14496 | int shift; | |
14497 | /* The amount by which the short form is shifted when it is stored | |
14498 | into the instruction code. */ | |
14499 | int op_shift; | |
14500 | /* Non-zero if the short form is unsigned. */ | |
14501 | int unsp; | |
14502 | /* Non-zero if the extended form is unsigned. */ | |
14503 | int extu; | |
14504 | /* Non-zero if the value is PC relative. */ | |
14505 | int pcrel; | |
14506 | }; | |
14507 | ||
14508 | /* The mips16 immediate operand types. */ | |
14509 | ||
14510 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14511 | { | |
14512 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14513 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14514 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14515 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14516 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14517 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14518 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14519 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14520 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14521 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14522 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14523 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14524 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14525 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14526 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14527 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14528 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14529 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14530 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14531 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14532 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14533 | }; | |
14534 | ||
14535 | #define MIPS16_NUM_IMMED \ | |
14536 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14537 | ||
b886a2ab RS |
14538 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14539 | NBITS is the number of significant bits in VAL. */ | |
14540 | ||
14541 | static unsigned long | |
14542 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14543 | { | |
14544 | int extval; | |
14545 | if (nbits == 16) | |
14546 | { | |
14547 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14548 | val &= 0x1f; | |
14549 | } | |
14550 | else if (nbits == 15) | |
14551 | { | |
14552 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14553 | val &= 0xf; | |
14554 | } | |
14555 | else | |
14556 | { | |
14557 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14558 | val = 0; | |
14559 | } | |
14560 | return (extval << 16) | val; | |
14561 | } | |
14562 | ||
5c04167a RS |
14563 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14564 | extending it if necessary. The instruction in *INSN may | |
14565 | already be extended. | |
14566 | ||
43c0598f RS |
14567 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14568 | if none. In the former case, VAL is a 16-bit number with no | |
14569 | defined signedness. | |
14570 | ||
14571 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14572 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14573 | |
14574 | static void | |
43c0598f RS |
14575 | mips16_immed (char *file, unsigned int line, int type, |
14576 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14577 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14578 | { |
3994f87e | 14579 | const struct mips16_immed_operand *op; |
252b5132 | 14580 | int mintiny, maxtiny; |
252b5132 RH |
14581 | |
14582 | op = mips16_immed_operands; | |
14583 | while (op->type != type) | |
14584 | { | |
14585 | ++op; | |
9c2799c2 | 14586 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14587 | } |
14588 | ||
14589 | if (op->unsp) | |
14590 | { | |
14591 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14592 | { | |
14593 | mintiny = 1; | |
14594 | maxtiny = 1 << op->nbits; | |
14595 | } | |
14596 | else | |
14597 | { | |
14598 | mintiny = 0; | |
14599 | maxtiny = (1 << op->nbits) - 1; | |
14600 | } | |
43c0598f RS |
14601 | if (reloc != BFD_RELOC_UNUSED) |
14602 | val &= 0xffff; | |
252b5132 RH |
14603 | } |
14604 | else | |
14605 | { | |
14606 | mintiny = - (1 << (op->nbits - 1)); | |
14607 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14608 | if (reloc != BFD_RELOC_UNUSED) |
14609 | val = SEXT_16BIT (val); | |
252b5132 RH |
14610 | } |
14611 | ||
14612 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14613 | if (type == 'p' || type == 'q') | |
14614 | val /= 2; | |
14615 | ||
14616 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14617 | || val < (mintiny << op->shift) | |
14618 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14619 | { |
14620 | /* We need an extended instruction. */ | |
14621 | if (user_insn_length == 2) | |
14622 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14623 | else | |
14624 | *insn |= MIPS16_EXTEND; | |
14625 | } | |
14626 | else if (user_insn_length == 4) | |
14627 | { | |
14628 | /* The operand doesn't force an unextended instruction to be extended. | |
14629 | Warn if the user wanted an extended instruction anyway. */ | |
14630 | *insn |= MIPS16_EXTEND; | |
14631 | as_warn_where (file, line, | |
14632 | _("extended operand requested but not required")); | |
14633 | } | |
252b5132 | 14634 | |
5c04167a | 14635 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14636 | { |
14637 | int insnval; | |
14638 | ||
252b5132 RH |
14639 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14640 | insnval <<= op->op_shift; | |
14641 | *insn |= insnval; | |
14642 | } | |
14643 | else | |
14644 | { | |
14645 | long minext, maxext; | |
252b5132 | 14646 | |
43c0598f | 14647 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14648 | { |
43c0598f RS |
14649 | if (op->extu) |
14650 | { | |
14651 | minext = 0; | |
14652 | maxext = (1 << op->extbits) - 1; | |
14653 | } | |
14654 | else | |
14655 | { | |
14656 | minext = - (1 << (op->extbits - 1)); | |
14657 | maxext = (1 << (op->extbits - 1)) - 1; | |
14658 | } | |
14659 | if (val < minext || val > maxext) | |
14660 | as_bad_where (file, line, | |
14661 | _("operand value out of range for instruction")); | |
252b5132 | 14662 | } |
252b5132 | 14663 | |
b886a2ab | 14664 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14665 | } |
14666 | } | |
14667 | \f | |
d6f16593 | 14668 | struct percent_op_match |
ad8d3bb3 | 14669 | { |
5e0116d5 RS |
14670 | const char *str; |
14671 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14672 | }; |
14673 | ||
14674 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14675 | { |
5e0116d5 | 14676 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14677 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14678 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14679 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14680 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14681 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14682 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14683 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14684 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14685 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14686 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14687 | {"%half", BFD_RELOC_16}, | |
14688 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14689 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14690 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14691 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14692 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14693 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14694 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14695 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14696 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14697 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
5e0116d5 | 14698 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14699 | }; |
14700 | ||
d6f16593 MR |
14701 | static const struct percent_op_match mips16_percent_op[] = |
14702 | { | |
14703 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14704 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14705 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14706 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14707 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14708 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14709 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14710 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14711 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14712 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14713 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14714 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14715 | }; |
14716 | ||
252b5132 | 14717 | |
5e0116d5 RS |
14718 | /* Return true if *STR points to a relocation operator. When returning true, |
14719 | move *STR over the operator and store its relocation code in *RELOC. | |
14720 | Leave both *STR and *RELOC alone when returning false. */ | |
14721 | ||
14722 | static bfd_boolean | |
17a2f251 | 14723 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14724 | { |
d6f16593 MR |
14725 | const struct percent_op_match *percent_op; |
14726 | size_t limit, i; | |
14727 | ||
14728 | if (mips_opts.mips16) | |
14729 | { | |
14730 | percent_op = mips16_percent_op; | |
14731 | limit = ARRAY_SIZE (mips16_percent_op); | |
14732 | } | |
14733 | else | |
14734 | { | |
14735 | percent_op = mips_percent_op; | |
14736 | limit = ARRAY_SIZE (mips_percent_op); | |
14737 | } | |
76b3015f | 14738 | |
d6f16593 | 14739 | for (i = 0; i < limit; i++) |
5e0116d5 | 14740 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14741 | { |
3f98094e DJ |
14742 | int len = strlen (percent_op[i].str); |
14743 | ||
14744 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14745 | continue; | |
14746 | ||
5e0116d5 RS |
14747 | *str += strlen (percent_op[i].str); |
14748 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14749 | |
5e0116d5 RS |
14750 | /* Check whether the output BFD supports this relocation. |
14751 | If not, issue an error and fall back on something safe. */ | |
14752 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14753 | { |
20203fb9 | 14754 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14755 | percent_op[i].str); |
01a3f561 | 14756 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14757 | } |
5e0116d5 | 14758 | return TRUE; |
394f9b3a | 14759 | } |
5e0116d5 | 14760 | return FALSE; |
394f9b3a | 14761 | } |
ad8d3bb3 | 14762 | |
ad8d3bb3 | 14763 | |
5e0116d5 RS |
14764 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14765 | expression in *EP and the relocations in the array starting | |
14766 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14767 | |
01a3f561 | 14768 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14769 | |
5e0116d5 | 14770 | static size_t |
17a2f251 TS |
14771 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14772 | char *str) | |
ad8d3bb3 | 14773 | { |
5e0116d5 RS |
14774 | bfd_reloc_code_real_type reversed_reloc[3]; |
14775 | size_t reloc_index, i; | |
09b8f35a RS |
14776 | int crux_depth, str_depth; |
14777 | char *crux; | |
5e0116d5 RS |
14778 | |
14779 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14780 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14781 | of the main expression and with CRUX_DEPTH containing the number | |
14782 | of open brackets at that point. */ | |
14783 | reloc_index = -1; | |
14784 | str_depth = 0; | |
14785 | do | |
fb1b3232 | 14786 | { |
09b8f35a RS |
14787 | reloc_index++; |
14788 | crux = str; | |
14789 | crux_depth = str_depth; | |
14790 | ||
14791 | /* Skip over whitespace and brackets, keeping count of the number | |
14792 | of brackets. */ | |
14793 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14794 | if (*str++ == '(') | |
14795 | str_depth++; | |
5e0116d5 | 14796 | } |
09b8f35a RS |
14797 | while (*str == '%' |
14798 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14799 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14800 | |
09b8f35a | 14801 | my_getExpression (ep, crux); |
5e0116d5 | 14802 | str = expr_end; |
394f9b3a | 14803 | |
5e0116d5 | 14804 | /* Match every open bracket. */ |
09b8f35a | 14805 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14806 | if (*str++ == ')') |
09b8f35a | 14807 | crux_depth--; |
394f9b3a | 14808 | |
09b8f35a | 14809 | if (crux_depth > 0) |
20203fb9 | 14810 | as_bad (_("unclosed '('")); |
394f9b3a | 14811 | |
5e0116d5 | 14812 | expr_end = str; |
252b5132 | 14813 | |
01a3f561 | 14814 | if (reloc_index != 0) |
64bdfcaf RS |
14815 | { |
14816 | prev_reloc_op_frag = frag_now; | |
14817 | for (i = 0; i < reloc_index; i++) | |
14818 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14819 | } | |
fb1b3232 | 14820 | |
5e0116d5 | 14821 | return reloc_index; |
252b5132 RH |
14822 | } |
14823 | ||
14824 | static void | |
17a2f251 | 14825 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14826 | { |
14827 | char *save_in; | |
14828 | ||
14829 | save_in = input_line_pointer; | |
14830 | input_line_pointer = str; | |
14831 | expression (ep); | |
14832 | expr_end = input_line_pointer; | |
14833 | input_line_pointer = save_in; | |
252b5132 RH |
14834 | } |
14835 | ||
252b5132 | 14836 | char * |
17a2f251 | 14837 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14838 | { |
499ac353 | 14839 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14840 | } |
14841 | ||
14842 | void | |
17a2f251 | 14843 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14844 | { |
14845 | if (target_big_endian) | |
14846 | number_to_chars_bigendian (buf, val, n); | |
14847 | else | |
14848 | number_to_chars_littleendian (buf, val, n); | |
14849 | } | |
14850 | \f | |
e013f690 TS |
14851 | static int support_64bit_objects(void) |
14852 | { | |
14853 | const char **list, **l; | |
aa3d8fdf | 14854 | int yes; |
e013f690 TS |
14855 | |
14856 | list = bfd_target_list (); | |
14857 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14858 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14859 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14860 | break; |
aa3d8fdf | 14861 | yes = (*l != NULL); |
e013f690 | 14862 | free (list); |
aa3d8fdf | 14863 | return yes; |
e013f690 TS |
14864 | } |
14865 | ||
316f5878 RS |
14866 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14867 | NEW_VALUE. Warn if another value was already specified. Note: | |
14868 | we have to defer parsing the -march and -mtune arguments in order | |
14869 | to handle 'from-abi' correctly, since the ABI might be specified | |
14870 | in a later argument. */ | |
14871 | ||
14872 | static void | |
17a2f251 | 14873 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14874 | { |
14875 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14876 | as_warn (_("A different %s was already specified, is now %s"), | |
14877 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14878 | new_value); | |
14879 | ||
14880 | *string_ptr = new_value; | |
14881 | } | |
14882 | ||
252b5132 | 14883 | int |
17a2f251 | 14884 | md_parse_option (int c, char *arg) |
252b5132 | 14885 | { |
c6278170 RS |
14886 | unsigned int i; |
14887 | ||
14888 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14889 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14890 | { | |
14891 | file_ase_explicit |= mips_set_ase (&mips_ases[i], | |
14892 | c == mips_ases[i].option_on); | |
14893 | return 1; | |
14894 | } | |
14895 | ||
252b5132 RH |
14896 | switch (c) |
14897 | { | |
119d663a NC |
14898 | case OPTION_CONSTRUCT_FLOATS: |
14899 | mips_disable_float_construction = 0; | |
14900 | break; | |
bdaaa2e1 | 14901 | |
119d663a NC |
14902 | case OPTION_NO_CONSTRUCT_FLOATS: |
14903 | mips_disable_float_construction = 1; | |
14904 | break; | |
bdaaa2e1 | 14905 | |
252b5132 RH |
14906 | case OPTION_TRAP: |
14907 | mips_trap = 1; | |
14908 | break; | |
14909 | ||
14910 | case OPTION_BREAK: | |
14911 | mips_trap = 0; | |
14912 | break; | |
14913 | ||
14914 | case OPTION_EB: | |
14915 | target_big_endian = 1; | |
14916 | break; | |
14917 | ||
14918 | case OPTION_EL: | |
14919 | target_big_endian = 0; | |
14920 | break; | |
14921 | ||
14922 | case 'O': | |
4ffff32f TS |
14923 | if (arg == NULL) |
14924 | mips_optimize = 1; | |
14925 | else if (arg[0] == '0') | |
14926 | mips_optimize = 0; | |
14927 | else if (arg[0] == '1') | |
252b5132 RH |
14928 | mips_optimize = 1; |
14929 | else | |
14930 | mips_optimize = 2; | |
14931 | break; | |
14932 | ||
14933 | case 'g': | |
14934 | if (arg == NULL) | |
14935 | mips_debug = 2; | |
14936 | else | |
14937 | mips_debug = atoi (arg); | |
252b5132 RH |
14938 | break; |
14939 | ||
14940 | case OPTION_MIPS1: | |
316f5878 | 14941 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14942 | break; |
14943 | ||
14944 | case OPTION_MIPS2: | |
316f5878 | 14945 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14946 | break; |
14947 | ||
14948 | case OPTION_MIPS3: | |
316f5878 | 14949 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14950 | break; |
14951 | ||
14952 | case OPTION_MIPS4: | |
316f5878 | 14953 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14954 | break; |
14955 | ||
84ea6cf2 | 14956 | case OPTION_MIPS5: |
316f5878 | 14957 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14958 | break; |
14959 | ||
e7af610e | 14960 | case OPTION_MIPS32: |
316f5878 | 14961 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14962 | break; |
14963 | ||
af7ee8bf CD |
14964 | case OPTION_MIPS32R2: |
14965 | file_mips_isa = ISA_MIPS32R2; | |
14966 | break; | |
14967 | ||
5f74bc13 CD |
14968 | case OPTION_MIPS64R2: |
14969 | file_mips_isa = ISA_MIPS64R2; | |
14970 | break; | |
14971 | ||
84ea6cf2 | 14972 | case OPTION_MIPS64: |
316f5878 | 14973 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14974 | break; |
14975 | ||
ec68c924 | 14976 | case OPTION_MTUNE: |
316f5878 RS |
14977 | mips_set_option_string (&mips_tune_string, arg); |
14978 | break; | |
ec68c924 | 14979 | |
316f5878 RS |
14980 | case OPTION_MARCH: |
14981 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14982 | break; |
14983 | ||
14984 | case OPTION_M4650: | |
316f5878 RS |
14985 | mips_set_option_string (&mips_arch_string, "4650"); |
14986 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14987 | break; |
14988 | ||
14989 | case OPTION_NO_M4650: | |
14990 | break; | |
14991 | ||
14992 | case OPTION_M4010: | |
316f5878 RS |
14993 | mips_set_option_string (&mips_arch_string, "4010"); |
14994 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14995 | break; |
14996 | ||
14997 | case OPTION_NO_M4010: | |
14998 | break; | |
14999 | ||
15000 | case OPTION_M4100: | |
316f5878 RS |
15001 | mips_set_option_string (&mips_arch_string, "4100"); |
15002 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
15003 | break; |
15004 | ||
15005 | case OPTION_NO_M4100: | |
15006 | break; | |
15007 | ||
252b5132 | 15008 | case OPTION_M3900: |
316f5878 RS |
15009 | mips_set_option_string (&mips_arch_string, "3900"); |
15010 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 15011 | break; |
bdaaa2e1 | 15012 | |
252b5132 RH |
15013 | case OPTION_NO_M3900: |
15014 | break; | |
15015 | ||
df58fc94 RS |
15016 | case OPTION_MICROMIPS: |
15017 | if (mips_opts.mips16 == 1) | |
15018 | { | |
15019 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
15020 | return 0; | |
15021 | } | |
15022 | mips_opts.micromips = 1; | |
15023 | mips_no_prev_insn (); | |
15024 | break; | |
15025 | ||
15026 | case OPTION_NO_MICROMIPS: | |
15027 | mips_opts.micromips = 0; | |
15028 | mips_no_prev_insn (); | |
15029 | break; | |
15030 | ||
252b5132 | 15031 | case OPTION_MIPS16: |
df58fc94 RS |
15032 | if (mips_opts.micromips == 1) |
15033 | { | |
15034 | as_bad (_("-mips16 cannot be used with -micromips")); | |
15035 | return 0; | |
15036 | } | |
252b5132 | 15037 | mips_opts.mips16 = 1; |
7d10b47d | 15038 | mips_no_prev_insn (); |
252b5132 RH |
15039 | break; |
15040 | ||
15041 | case OPTION_NO_MIPS16: | |
15042 | mips_opts.mips16 = 0; | |
7d10b47d | 15043 | mips_no_prev_insn (); |
252b5132 RH |
15044 | break; |
15045 | ||
6a32d874 CM |
15046 | case OPTION_FIX_24K: |
15047 | mips_fix_24k = 1; | |
15048 | break; | |
15049 | ||
15050 | case OPTION_NO_FIX_24K: | |
15051 | mips_fix_24k = 0; | |
15052 | break; | |
15053 | ||
c67a084a NC |
15054 | case OPTION_FIX_LOONGSON2F_JUMP: |
15055 | mips_fix_loongson2f_jump = TRUE; | |
15056 | break; | |
15057 | ||
15058 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
15059 | mips_fix_loongson2f_jump = FALSE; | |
15060 | break; | |
15061 | ||
15062 | case OPTION_FIX_LOONGSON2F_NOP: | |
15063 | mips_fix_loongson2f_nop = TRUE; | |
15064 | break; | |
15065 | ||
15066 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
15067 | mips_fix_loongson2f_nop = FALSE; | |
15068 | break; | |
15069 | ||
d766e8ec RS |
15070 | case OPTION_FIX_VR4120: |
15071 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15072 | break; |
15073 | ||
d766e8ec RS |
15074 | case OPTION_NO_FIX_VR4120: |
15075 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15076 | break; |
15077 | ||
7d8e00cf RS |
15078 | case OPTION_FIX_VR4130: |
15079 | mips_fix_vr4130 = 1; | |
15080 | break; | |
15081 | ||
15082 | case OPTION_NO_FIX_VR4130: | |
15083 | mips_fix_vr4130 = 0; | |
15084 | break; | |
15085 | ||
d954098f DD |
15086 | case OPTION_FIX_CN63XXP1: |
15087 | mips_fix_cn63xxp1 = TRUE; | |
15088 | break; | |
15089 | ||
15090 | case OPTION_NO_FIX_CN63XXP1: | |
15091 | mips_fix_cn63xxp1 = FALSE; | |
15092 | break; | |
15093 | ||
4a6a3df4 AO |
15094 | case OPTION_RELAX_BRANCH: |
15095 | mips_relax_branch = 1; | |
15096 | break; | |
15097 | ||
15098 | case OPTION_NO_RELAX_BRANCH: | |
15099 | mips_relax_branch = 0; | |
15100 | break; | |
15101 | ||
833794fc MR |
15102 | case OPTION_INSN32: |
15103 | mips_opts.insn32 = TRUE; | |
15104 | break; | |
15105 | ||
15106 | case OPTION_NO_INSN32: | |
15107 | mips_opts.insn32 = FALSE; | |
15108 | break; | |
15109 | ||
aa6975fb ILT |
15110 | case OPTION_MSHARED: |
15111 | mips_in_shared = TRUE; | |
15112 | break; | |
15113 | ||
15114 | case OPTION_MNO_SHARED: | |
15115 | mips_in_shared = FALSE; | |
15116 | break; | |
15117 | ||
aed1a261 RS |
15118 | case OPTION_MSYM32: |
15119 | mips_opts.sym32 = TRUE; | |
15120 | break; | |
15121 | ||
15122 | case OPTION_MNO_SYM32: | |
15123 | mips_opts.sym32 = FALSE; | |
15124 | break; | |
15125 | ||
252b5132 RH |
15126 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15127 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15128 | intended to be compatible with Irix 5. */ | |
15129 | case OPTION_CALL_SHARED: | |
252b5132 | 15130 | mips_pic = SVR4_PIC; |
143d77c5 | 15131 | mips_abicalls = TRUE; |
252b5132 RH |
15132 | break; |
15133 | ||
861fb55a | 15134 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
15135 | mips_pic = NO_PIC; |
15136 | mips_abicalls = TRUE; | |
15137 | break; | |
15138 | ||
252b5132 | 15139 | case OPTION_NON_SHARED: |
252b5132 | 15140 | mips_pic = NO_PIC; |
143d77c5 | 15141 | mips_abicalls = FALSE; |
252b5132 RH |
15142 | break; |
15143 | ||
44075ae2 TS |
15144 | /* The -xgot option tells the assembler to use 32 bit offsets |
15145 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15146 | compatibility. */ |
15147 | case OPTION_XGOT: | |
15148 | mips_big_got = 1; | |
15149 | break; | |
15150 | ||
15151 | case 'G': | |
6caf9ef4 TS |
15152 | g_switch_value = atoi (arg); |
15153 | g_switch_seen = 1; | |
252b5132 RH |
15154 | break; |
15155 | ||
34ba82a8 TS |
15156 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15157 | and -mabi=64. */ | |
252b5132 | 15158 | case OPTION_32: |
f3ded42a | 15159 | mips_abi = O32_ABI; |
252b5132 RH |
15160 | break; |
15161 | ||
e013f690 | 15162 | case OPTION_N32: |
316f5878 | 15163 | mips_abi = N32_ABI; |
e013f690 | 15164 | break; |
252b5132 | 15165 | |
e013f690 | 15166 | case OPTION_64: |
316f5878 | 15167 | mips_abi = N64_ABI; |
f43abd2b | 15168 | if (!support_64bit_objects()) |
e013f690 | 15169 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 RH |
15170 | break; |
15171 | ||
c97ef257 | 15172 | case OPTION_GP32: |
a325df1d | 15173 | file_mips_gp32 = 1; |
c97ef257 AH |
15174 | break; |
15175 | ||
15176 | case OPTION_GP64: | |
a325df1d | 15177 | file_mips_gp32 = 0; |
c97ef257 | 15178 | break; |
252b5132 | 15179 | |
ca4e0257 | 15180 | case OPTION_FP32: |
a325df1d | 15181 | file_mips_fp32 = 1; |
316f5878 RS |
15182 | break; |
15183 | ||
15184 | case OPTION_FP64: | |
15185 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15186 | break; |
15187 | ||
037b32b9 AN |
15188 | case OPTION_SINGLE_FLOAT: |
15189 | file_mips_single_float = 1; | |
15190 | break; | |
15191 | ||
15192 | case OPTION_DOUBLE_FLOAT: | |
15193 | file_mips_single_float = 0; | |
15194 | break; | |
15195 | ||
15196 | case OPTION_SOFT_FLOAT: | |
15197 | file_mips_soft_float = 1; | |
15198 | break; | |
15199 | ||
15200 | case OPTION_HARD_FLOAT: | |
15201 | file_mips_soft_float = 0; | |
15202 | break; | |
15203 | ||
252b5132 | 15204 | case OPTION_MABI: |
e013f690 | 15205 | if (strcmp (arg, "32") == 0) |
316f5878 | 15206 | mips_abi = O32_ABI; |
e013f690 | 15207 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15208 | mips_abi = O64_ABI; |
e013f690 | 15209 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15210 | mips_abi = N32_ABI; |
e013f690 TS |
15211 | else if (strcmp (arg, "64") == 0) |
15212 | { | |
316f5878 | 15213 | mips_abi = N64_ABI; |
e013f690 TS |
15214 | if (! support_64bit_objects()) |
15215 | as_fatal (_("No compiled in support for 64 bit object file " | |
15216 | "format")); | |
15217 | } | |
15218 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15219 | mips_abi = EABI_ABI; |
e013f690 | 15220 | else |
da0e507f TS |
15221 | { |
15222 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15223 | return 0; | |
15224 | } | |
252b5132 RH |
15225 | break; |
15226 | ||
6b76fefe | 15227 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15228 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15229 | break; |
15230 | ||
9ee72ff1 | 15231 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15232 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15233 | break; |
15234 | ||
ecb4347a | 15235 | case OPTION_MDEBUG: |
b34976b6 | 15236 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15237 | break; |
15238 | ||
15239 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15240 | mips_flag_mdebug = FALSE; |
ecb4347a | 15241 | break; |
dcd410fe RO |
15242 | |
15243 | case OPTION_PDR: | |
15244 | mips_flag_pdr = TRUE; | |
15245 | break; | |
15246 | ||
15247 | case OPTION_NO_PDR: | |
15248 | mips_flag_pdr = FALSE; | |
15249 | break; | |
0a44bf69 RS |
15250 | |
15251 | case OPTION_MVXWORKS_PIC: | |
15252 | mips_pic = VXWORKS_PIC; | |
15253 | break; | |
ecb4347a | 15254 | |
ba92f887 MR |
15255 | case OPTION_NAN: |
15256 | if (strcmp (arg, "2008") == 0) | |
15257 | mips_flag_nan2008 = TRUE; | |
15258 | else if (strcmp (arg, "legacy") == 0) | |
15259 | mips_flag_nan2008 = FALSE; | |
15260 | else | |
15261 | { | |
15262 | as_fatal (_("Invalid NaN setting -mnan=%s"), arg); | |
15263 | return 0; | |
15264 | } | |
15265 | break; | |
15266 | ||
252b5132 RH |
15267 | default: |
15268 | return 0; | |
15269 | } | |
15270 | ||
c67a084a NC |
15271 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15272 | ||
252b5132 RH |
15273 | return 1; |
15274 | } | |
316f5878 RS |
15275 | \f |
15276 | /* Set up globals to generate code for the ISA or processor | |
15277 | described by INFO. */ | |
252b5132 | 15278 | |
252b5132 | 15279 | static void |
17a2f251 | 15280 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15281 | { |
316f5878 | 15282 | if (info != 0) |
252b5132 | 15283 | { |
fef14a42 TS |
15284 | file_mips_arch = info->cpu; |
15285 | mips_opts.arch = info->cpu; | |
316f5878 | 15286 | mips_opts.isa = info->isa; |
252b5132 | 15287 | } |
252b5132 RH |
15288 | } |
15289 | ||
252b5132 | 15290 | |
316f5878 | 15291 | /* Likewise for tuning. */ |
252b5132 | 15292 | |
316f5878 | 15293 | static void |
17a2f251 | 15294 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15295 | { |
15296 | if (info != 0) | |
fef14a42 | 15297 | mips_tune = info->cpu; |
316f5878 | 15298 | } |
80cc45a5 | 15299 | |
34ba82a8 | 15300 | |
252b5132 | 15301 | void |
17a2f251 | 15302 | mips_after_parse_args (void) |
e9670677 | 15303 | { |
fef14a42 TS |
15304 | const struct mips_cpu_info *arch_info = 0; |
15305 | const struct mips_cpu_info *tune_info = 0; | |
15306 | ||
e9670677 | 15307 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15308 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15309 | { |
6caf9ef4 | 15310 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15311 | as_bad (_("-G not supported in this configuration.")); |
15312 | g_switch_value = 0; | |
15313 | } | |
15314 | ||
cac012d6 AO |
15315 | if (mips_abi == NO_ABI) |
15316 | mips_abi = MIPS_DEFAULT_ABI; | |
15317 | ||
22923709 RS |
15318 | /* The following code determines the architecture and register size. |
15319 | Similar code was added to GCC 3.3 (see override_options() in | |
15320 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15321 | as much as possible. */ | |
e9670677 | 15322 | |
316f5878 | 15323 | if (mips_arch_string != 0) |
fef14a42 | 15324 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15325 | |
316f5878 | 15326 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15327 | { |
316f5878 | 15328 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15329 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15330 | the -march selection (if any). */ |
fef14a42 | 15331 | if (arch_info != 0) |
e9670677 | 15332 | { |
316f5878 RS |
15333 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15334 | There's no harm in specifying both as long as the ISA levels | |
15335 | are the same. */ | |
fef14a42 | 15336 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15337 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15338 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15339 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15340 | } |
316f5878 | 15341 | else |
fef14a42 | 15342 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15343 | } |
15344 | ||
fef14a42 | 15345 | if (arch_info == 0) |
95bfe26e MF |
15346 | { |
15347 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15348 | gas_assert (arch_info); | |
15349 | } | |
e9670677 | 15350 | |
fef14a42 | 15351 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15352 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15353 | arch_info->name); |
15354 | ||
15355 | mips_set_architecture (arch_info); | |
15356 | ||
15357 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15358 | if (mips_tune_string != 0) | |
15359 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15360 | |
fef14a42 TS |
15361 | if (tune_info == 0) |
15362 | mips_set_tune (arch_info); | |
15363 | else | |
15364 | mips_set_tune (tune_info); | |
e9670677 | 15365 | |
316f5878 | 15366 | if (file_mips_gp32 >= 0) |
e9670677 | 15367 | { |
316f5878 RS |
15368 | /* The user specified the size of the integer registers. Make sure |
15369 | it agrees with the ABI and ISA. */ | |
15370 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15371 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15372 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15373 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15374 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15375 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15376 | } |
15377 | else | |
15378 | { | |
316f5878 RS |
15379 | /* Infer the integer register size from the ABI and processor. |
15380 | Restrict ourselves to 32-bit registers if that's all the | |
15381 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15382 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15383 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15384 | } |
15385 | ||
ad3fea08 TS |
15386 | switch (file_mips_fp32) |
15387 | { | |
15388 | default: | |
15389 | case -1: | |
15390 | /* No user specified float register size. | |
15391 | ??? GAS treats single-float processors as though they had 64-bit | |
15392 | float registers (although it complains when double-precision | |
15393 | instructions are used). As things stand, saying they have 32-bit | |
15394 | registers would lead to spurious "register must be even" messages. | |
15395 | So here we assume float registers are never smaller than the | |
15396 | integer ones. */ | |
15397 | if (file_mips_gp32 == 0) | |
15398 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15399 | file_mips_fp32 = 0; | |
c6278170 | 15400 | else if ((mips_opts.ase & FP64_ASES) |
ad3fea08 TS |
15401 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
15402 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15403 | file_mips_fp32 = 0; | |
15404 | else | |
15405 | /* 32-bit float registers. */ | |
15406 | file_mips_fp32 = 1; | |
15407 | break; | |
15408 | ||
15409 | /* The user specified the size of the float registers. Check if it | |
15410 | agrees with the ABI and ISA. */ | |
15411 | case 0: | |
15412 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15413 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15414 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15415 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15416 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15417 | break; | |
15418 | case 1: | |
15419 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15420 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15421 | break; | |
15422 | } | |
e9670677 | 15423 | |
316f5878 | 15424 | /* End of GCC-shared inference code. */ |
e9670677 | 15425 | |
17a2f251 TS |
15426 | /* This flag is set when we have a 64-bit capable CPU but use only |
15427 | 32-bit wide registers. Note that EABI does not use it. */ | |
15428 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15429 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15430 | || mips_abi == O32_ABI)) | |
316f5878 | 15431 | mips_32bitmode = 1; |
e9670677 MR |
15432 | |
15433 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15434 | as_bad (_("trap exception not supported at ISA 1")); | |
15435 | ||
e9670677 MR |
15436 | /* If the selected architecture includes support for ASEs, enable |
15437 | generation of code for them. */ | |
a4672219 | 15438 | if (mips_opts.mips16 == -1) |
fef14a42 | 15439 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15440 | if (mips_opts.micromips == -1) |
15441 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
846ef2d0 RS |
15442 | |
15443 | /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those | |
15444 | ASEs from being selected implicitly. */ | |
15445 | if (file_mips_fp32 == 1) | |
15446 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX; | |
15447 | ||
15448 | /* If the user didn't explicitly select or deselect a particular ASE, | |
15449 | use the default setting for the CPU. */ | |
15450 | mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
15451 | ||
e9670677 | 15452 | file_mips_isa = mips_opts.isa; |
846ef2d0 | 15453 | file_ase = mips_opts.ase; |
e9670677 MR |
15454 | mips_opts.gp32 = file_mips_gp32; |
15455 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15456 | mips_opts.soft_float = file_mips_soft_float; |
15457 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15458 | |
c6278170 RS |
15459 | mips_check_isa_supports_ases (); |
15460 | ||
ecb4347a | 15461 | if (mips_flag_mdebug < 0) |
e8044f35 | 15462 | mips_flag_mdebug = 0; |
e9670677 MR |
15463 | } |
15464 | \f | |
15465 | void | |
17a2f251 | 15466 | mips_init_after_args (void) |
252b5132 RH |
15467 | { |
15468 | /* initialize opcodes */ | |
15469 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15470 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15471 | } |
15472 | ||
15473 | long | |
17a2f251 | 15474 | md_pcrel_from (fixS *fixP) |
252b5132 | 15475 | { |
a7ebbfdf TS |
15476 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15477 | switch (fixP->fx_r_type) | |
15478 | { | |
df58fc94 RS |
15479 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15480 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15481 | /* Return the address of the delay slot. */ | |
15482 | return addr + 2; | |
15483 | ||
15484 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15485 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15486 | case BFD_RELOC_16_PCREL_S2: |
15487 | case BFD_RELOC_MIPS_JMP: | |
15488 | /* Return the address of the delay slot. */ | |
15489 | return addr + 4; | |
df58fc94 | 15490 | |
b47468a6 CM |
15491 | case BFD_RELOC_32_PCREL: |
15492 | return addr; | |
15493 | ||
a7ebbfdf | 15494 | default: |
58ea3d6a | 15495 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15496 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15497 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15498 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15499 | return addr; |
15500 | } | |
252b5132 RH |
15501 | } |
15502 | ||
252b5132 RH |
15503 | /* This is called before the symbol table is processed. In order to |
15504 | work with gcc when using mips-tfile, we must keep all local labels. | |
15505 | However, in other cases, we want to discard them. If we were | |
15506 | called with -g, but we didn't see any debugging information, it may | |
15507 | mean that gcc is smuggling debugging information through to | |
15508 | mips-tfile, in which case we must generate all local labels. */ | |
15509 | ||
15510 | void | |
17a2f251 | 15511 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15512 | { |
15513 | #ifndef NO_ECOFF_DEBUGGING | |
15514 | if (ECOFF_DEBUGGING | |
15515 | && mips_debug != 0 | |
15516 | && ! ecoff_debugging_seen) | |
15517 | flag_keep_locals = 1; | |
15518 | #endif | |
15519 | } | |
15520 | ||
3b91255e | 15521 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15522 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15523 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15524 | relocation operators. | |
15525 | ||
15526 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15527 | expression if: | |
15528 | ||
15529 | (a) it refers to the same symbol; and | |
15530 | (b) the offset applied in the %lo() expression is no lower than | |
15531 | the offset applied in the %got() or %hi(). | |
15532 | ||
15533 | (b) allows us to cope with code like: | |
15534 | ||
15535 | lui $4,%hi(foo) | |
15536 | lh $4,%lo(foo+2)($4) | |
15537 | ||
15538 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15539 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15540 | the high 16 bits. | |
15541 | ||
15542 | When several %lo()s match a particular %got() or %hi(), we use the | |
15543 | following rules to distinguish them: | |
15544 | ||
15545 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15546 | higher offsets. | |
15547 | ||
15548 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15549 | that already have a matching %got() or %hi(). | |
15550 | ||
15551 | (3) later %lo()s are better than earlier %lo()s. | |
15552 | ||
15553 | These rules are applied in order. | |
15554 | ||
15555 | (1) means, among other things, that %lo()s with identical offsets are | |
15556 | chosen if they exist. | |
15557 | ||
15558 | (2) means that we won't associate several high-part relocations with | |
15559 | the same low-part relocation unless there's no alternative. Having | |
15560 | several high parts for the same low part is a GNU extension; this rule | |
15561 | allows careful users to avoid it. | |
15562 | ||
15563 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15564 | with the last high-part relocation being at the front of the list. | |
15565 | It therefore makes sense to choose the last matching low-part | |
15566 | relocation, all other things being equal. It's also easier | |
15567 | to code that way. */ | |
252b5132 RH |
15568 | |
15569 | void | |
17a2f251 | 15570 | mips_frob_file (void) |
252b5132 RH |
15571 | { |
15572 | struct mips_hi_fixup *l; | |
35903be0 | 15573 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15574 | |
15575 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15576 | { | |
15577 | segment_info_type *seginfo; | |
3b91255e RS |
15578 | bfd_boolean matched_lo_p; |
15579 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15580 | |
9c2799c2 | 15581 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15582 | |
5919d012 | 15583 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15584 | there isn't supposed to be a matching LO. Ignore %gots against |
15585 | constants; we'll report an error for those later. */ | |
738e5348 | 15586 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15587 | && !(l->fixp->fx_addsy |
15588 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15589 | continue; |
15590 | ||
15591 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15592 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15593 | continue; |
15594 | ||
252b5132 | 15595 | seginfo = seg_info (l->seg); |
252b5132 | 15596 | |
3b91255e RS |
15597 | /* Set HI_POS to the position of this relocation in the chain. |
15598 | Set LO_POS to the position of the chosen low-part relocation. | |
15599 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15600 | relocation that matches an immediately-preceding high-part | |
15601 | relocation. */ | |
15602 | hi_pos = NULL; | |
15603 | lo_pos = NULL; | |
15604 | matched_lo_p = FALSE; | |
738e5348 | 15605 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15606 | |
3b91255e RS |
15607 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15608 | { | |
15609 | if (*pos == l->fixp) | |
15610 | hi_pos = pos; | |
15611 | ||
35903be0 | 15612 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15613 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15614 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15615 | && (lo_pos == NULL | |
15616 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15617 | || (!matched_lo_p | |
15618 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15619 | lo_pos = pos; | |
15620 | ||
15621 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15622 | && fixup_has_matching_lo_p (*pos)); | |
15623 | } | |
15624 | ||
15625 | /* If we found a match, remove the high-part relocation from its | |
15626 | current position and insert it before the low-part relocation. | |
15627 | Make the offsets match so that fixup_has_matching_lo_p() | |
15628 | will return true. | |
15629 | ||
15630 | We don't warn about unmatched high-part relocations since some | |
15631 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15632 | instructions. */ | |
15633 | if (lo_pos != NULL) | |
15634 | { | |
15635 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15636 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15637 | { |
3b91255e RS |
15638 | *hi_pos = l->fixp->fx_next; |
15639 | l->fixp->fx_next = *lo_pos; | |
15640 | *lo_pos = l->fixp; | |
252b5132 | 15641 | } |
252b5132 RH |
15642 | } |
15643 | } | |
15644 | } | |
15645 | ||
252b5132 | 15646 | int |
17a2f251 | 15647 | mips_force_relocation (fixS *fixp) |
252b5132 | 15648 | { |
ae6063d4 | 15649 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15650 | return 1; |
15651 | ||
df58fc94 RS |
15652 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15653 | so that the linker relaxation can update targets. */ | |
15654 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15655 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15656 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15657 | return 1; | |
15658 | ||
3e722fb5 | 15659 | return 0; |
252b5132 RH |
15660 | } |
15661 | ||
b886a2ab RS |
15662 | /* Read the instruction associated with RELOC from BUF. */ |
15663 | ||
15664 | static unsigned int | |
15665 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15666 | { | |
15667 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15668 | return read_compressed_insn (buf, 4); | |
15669 | else | |
15670 | return read_insn (buf); | |
15671 | } | |
15672 | ||
15673 | /* Write instruction INSN to BUF, given that it has been relocated | |
15674 | by RELOC. */ | |
15675 | ||
15676 | static void | |
15677 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15678 | unsigned long insn) | |
15679 | { | |
15680 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15681 | write_compressed_insn (buf, insn, 4); | |
15682 | else | |
15683 | write_insn (buf, insn); | |
15684 | } | |
15685 | ||
252b5132 RH |
15686 | /* Apply a fixup to the object file. */ |
15687 | ||
94f592af | 15688 | void |
55cf6793 | 15689 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15690 | { |
4d68580a | 15691 | char *buf; |
b886a2ab | 15692 | unsigned long insn; |
a7ebbfdf | 15693 | reloc_howto_type *howto; |
252b5132 | 15694 | |
a7ebbfdf TS |
15695 | /* We ignore generic BFD relocations we don't know about. */ |
15696 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15697 | if (! howto) | |
15698 | return; | |
65551fa4 | 15699 | |
df58fc94 RS |
15700 | gas_assert (fixP->fx_size == 2 |
15701 | || fixP->fx_size == 4 | |
90ecf173 MR |
15702 | || fixP->fx_r_type == BFD_RELOC_16 |
15703 | || fixP->fx_r_type == BFD_RELOC_64 | |
15704 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15705 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15706 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15707 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15708 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15709 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15710 | |
4d68580a | 15711 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15712 | |
df58fc94 RS |
15713 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15714 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15715 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
15716 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
15717 | || fixP->fx_r_type == BFD_RELOC_32_PCREL); | |
b1dca8ee RS |
15718 | |
15719 | /* Don't treat parts of a composite relocation as done. There are two | |
15720 | reasons for this: | |
15721 | ||
15722 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15723 | should nevertheless be emitted if the first part is. | |
15724 | ||
15725 | (2) In normal usage, composite relocations are never assembly-time | |
15726 | constants. The easiest way of dealing with the pathological | |
15727 | exceptions is to generate a relocation against STN_UNDEF and | |
15728 | leave everything up to the linker. */ | |
3994f87e | 15729 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15730 | fixP->fx_done = 1; |
15731 | ||
15732 | switch (fixP->fx_r_type) | |
15733 | { | |
3f98094e DJ |
15734 | case BFD_RELOC_MIPS_TLS_GD: |
15735 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15736 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15737 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15738 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15739 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15740 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15741 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15742 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15743 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15744 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15745 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15746 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15747 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15748 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15749 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15750 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15751 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15752 | case BFD_RELOC_MIPS16_TLS_GD: |
15753 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15754 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15755 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15756 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15757 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15758 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15759 | if (!fixP->fx_addsy) |
15760 | { | |
15761 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15762 | _("TLS relocation against a constant")); | |
15763 | break; | |
15764 | } | |
3f98094e DJ |
15765 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15766 | /* fall through */ | |
15767 | ||
252b5132 | 15768 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15769 | case BFD_RELOC_MIPS_SHIFT5: |
15770 | case BFD_RELOC_MIPS_SHIFT6: | |
15771 | case BFD_RELOC_MIPS_GOT_DISP: | |
15772 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15773 | case BFD_RELOC_MIPS_GOT_OFST: | |
15774 | case BFD_RELOC_MIPS_SUB: | |
15775 | case BFD_RELOC_MIPS_INSERT_A: | |
15776 | case BFD_RELOC_MIPS_INSERT_B: | |
15777 | case BFD_RELOC_MIPS_DELETE: | |
15778 | case BFD_RELOC_MIPS_HIGHEST: | |
15779 | case BFD_RELOC_MIPS_HIGHER: | |
15780 | case BFD_RELOC_MIPS_SCN_DISP: | |
15781 | case BFD_RELOC_MIPS_REL16: | |
15782 | case BFD_RELOC_MIPS_RELGOT: | |
15783 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15784 | case BFD_RELOC_HI16: |
15785 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15786 | case BFD_RELOC_LO16: |
cdf6fd85 | 15787 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15788 | case BFD_RELOC_MIPS_LITERAL: |
15789 | case BFD_RELOC_MIPS_CALL16: | |
15790 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15791 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15792 | case BFD_RELOC_MIPS_GOT_HI16: |
15793 | case BFD_RELOC_MIPS_GOT_LO16: | |
15794 | case BFD_RELOC_MIPS_CALL_HI16: | |
15795 | case BFD_RELOC_MIPS_CALL_LO16: | |
15796 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15797 | case BFD_RELOC_MIPS16_GOT16: |
15798 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15799 | case BFD_RELOC_MIPS16_HI16: |
15800 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15801 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15802 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15803 | case BFD_RELOC_MICROMIPS_JMP: |
15804 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15805 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15806 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15807 | case BFD_RELOC_MICROMIPS_SUB: | |
15808 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15809 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15810 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15811 | case BFD_RELOC_MICROMIPS_JALR: | |
15812 | case BFD_RELOC_MICROMIPS_HI16: | |
15813 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15814 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15815 | case BFD_RELOC_MICROMIPS_GPREL16: |
15816 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15817 | case BFD_RELOC_MICROMIPS_CALL16: | |
15818 | case BFD_RELOC_MICROMIPS_GOT16: | |
15819 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15820 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15821 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15822 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15823 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15824 | if (fixP->fx_done) |
15825 | { | |
15826 | offsetT value; | |
15827 | ||
15828 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15829 | { | |
15830 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15831 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15832 | insn |= mips16_immed_extend (value, 16); | |
15833 | else | |
15834 | insn |= (value & 0xffff); | |
15835 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15836 | } | |
15837 | else | |
15838 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15839 | _("Unsupported constant in relocation")); | |
15840 | } | |
252b5132 RH |
15841 | break; |
15842 | ||
252b5132 RH |
15843 | case BFD_RELOC_64: |
15844 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15845 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15846 | if (fixP->fx_done) |
252b5132 RH |
15847 | { |
15848 | if (8 <= sizeof (valueT)) | |
4d68580a | 15849 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15850 | else |
15851 | { | |
a7ebbfdf | 15852 | valueT hiv; |
252b5132 | 15853 | |
a7ebbfdf | 15854 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15855 | hiv = 0xffffffff; |
15856 | else | |
15857 | hiv = 0; | |
4d68580a RS |
15858 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15859 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15860 | } |
15861 | } | |
15862 | break; | |
15863 | ||
056350c6 | 15864 | case BFD_RELOC_RVA: |
252b5132 | 15865 | case BFD_RELOC_32: |
b47468a6 | 15866 | case BFD_RELOC_32_PCREL: |
252b5132 RH |
15867 | case BFD_RELOC_16: |
15868 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15869 | value now. This can happen if we have a .word which is not |
15870 | resolved when it appears but is later defined. */ | |
252b5132 | 15871 | if (fixP->fx_done) |
4d68580a | 15872 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15873 | break; |
15874 | ||
252b5132 | 15875 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15876 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15877 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15878 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15879 | |
54f4ddb3 TS |
15880 | /* We need to save the bits in the instruction since fixup_segment() |
15881 | might be deleting the relocation entry (i.e., a branch within | |
15882 | the current segment). */ | |
a7ebbfdf | 15883 | if (! fixP->fx_done) |
bb2d6cd7 | 15884 | break; |
252b5132 | 15885 | |
54f4ddb3 | 15886 | /* Update old instruction data. */ |
4d68580a | 15887 | insn = read_insn (buf); |
252b5132 | 15888 | |
a7ebbfdf TS |
15889 | if (*valP + 0x20000 <= 0x3ffff) |
15890 | { | |
15891 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15892 | write_insn (buf, insn); |
a7ebbfdf TS |
15893 | } |
15894 | else if (mips_pic == NO_PIC | |
15895 | && fixP->fx_done | |
15896 | && fixP->fx_frag->fr_address >= text_section->vma | |
15897 | && (fixP->fx_frag->fr_address | |
587aac4e | 15898 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15899 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15900 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15901 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15902 | { |
15903 | /* The branch offset is too large. If this is an | |
15904 | unconditional branch, and we are not generating PIC code, | |
15905 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15906 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15907 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15908 | else |
a7ebbfdf TS |
15909 | insn = 0x08000000; /* j */ |
15910 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15911 | fixP->fx_done = 0; | |
15912 | fixP->fx_addsy = section_symbol (text_section); | |
15913 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15914 | write_insn (buf, insn); |
a7ebbfdf TS |
15915 | } |
15916 | else | |
15917 | { | |
15918 | /* If we got here, we have branch-relaxation disabled, | |
15919 | and there's nothing we can do to fix this instruction | |
15920 | without turning it into a longer sequence. */ | |
15921 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15922 | _("Branch out of range")); | |
252b5132 | 15923 | } |
252b5132 RH |
15924 | break; |
15925 | ||
df58fc94 RS |
15926 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15927 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15928 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15929 | /* We adjust the offset back to even. */ | |
15930 | if ((*valP & 0x1) != 0) | |
15931 | --(*valP); | |
15932 | ||
15933 | if (! fixP->fx_done) | |
15934 | break; | |
15935 | ||
15936 | /* Should never visit here, because we keep the relocation. */ | |
15937 | abort (); | |
15938 | break; | |
15939 | ||
252b5132 RH |
15940 | case BFD_RELOC_VTABLE_INHERIT: |
15941 | fixP->fx_done = 0; | |
15942 | if (fixP->fx_addsy | |
15943 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15944 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15945 | S_SET_WEAK (fixP->fx_addsy); | |
15946 | break; | |
15947 | ||
15948 | case BFD_RELOC_VTABLE_ENTRY: | |
15949 | fixP->fx_done = 0; | |
15950 | break; | |
15951 | ||
15952 | default: | |
b37df7c4 | 15953 | abort (); |
252b5132 | 15954 | } |
a7ebbfdf TS |
15955 | |
15956 | /* Remember value for tc_gen_reloc. */ | |
15957 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15958 | } |
15959 | ||
252b5132 | 15960 | static symbolS * |
17a2f251 | 15961 | get_symbol (void) |
252b5132 RH |
15962 | { |
15963 | int c; | |
15964 | char *name; | |
15965 | symbolS *p; | |
15966 | ||
15967 | name = input_line_pointer; | |
15968 | c = get_symbol_end (); | |
15969 | p = (symbolS *) symbol_find_or_make (name); | |
15970 | *input_line_pointer = c; | |
15971 | return p; | |
15972 | } | |
15973 | ||
742a56fe RS |
15974 | /* Align the current frag to a given power of two. If a particular |
15975 | fill byte should be used, FILL points to an integer that contains | |
15976 | that byte, otherwise FILL is null. | |
15977 | ||
462427c4 RS |
15978 | This function used to have the comment: |
15979 | ||
15980 | The MIPS assembler also automatically adjusts any preceding label. | |
15981 | ||
15982 | The implementation therefore applied the adjustment to a maximum of | |
15983 | one label. However, other label adjustments are applied to batches | |
15984 | of labels, and adjusting just one caused problems when new labels | |
15985 | were added for the sake of debugging or unwind information. | |
15986 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15987 | |
15988 | static void | |
462427c4 | 15989 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15990 | { |
7d10b47d | 15991 | mips_emit_delays (); |
df58fc94 | 15992 | mips_record_compressed_mode (); |
742a56fe RS |
15993 | if (fill == NULL && subseg_text_p (now_seg)) |
15994 | frag_align_code (to, 0); | |
15995 | else | |
15996 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15997 | record_alignment (now_seg, to); |
462427c4 | 15998 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15999 | } |
16000 | ||
16001 | /* Align to a given power of two. .align 0 turns off the automatic | |
16002 | alignment used by the data creating pseudo-ops. */ | |
16003 | ||
16004 | static void | |
17a2f251 | 16005 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16006 | { |
742a56fe | 16007 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16008 | long max_alignment = 28; |
252b5132 | 16009 | |
54f4ddb3 | 16010 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16011 | to the aligned address. |
54f4ddb3 | 16012 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16013 | a .align pseudo instruction. |
54f4ddb3 | 16014 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16015 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16016 | We don't. */ |
252b5132 RH |
16017 | |
16018 | temp = get_absolute_expression (); | |
16019 | if (temp > max_alignment) | |
16020 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
16021 | else if (temp < 0) | |
16022 | { | |
16023 | as_warn (_("Alignment negative: 0 assumed.")); | |
16024 | temp = 0; | |
16025 | } | |
16026 | if (*input_line_pointer == ',') | |
16027 | { | |
f9419b05 | 16028 | ++input_line_pointer; |
742a56fe RS |
16029 | fill_value = get_absolute_expression (); |
16030 | fill_ptr = &fill_value; | |
252b5132 RH |
16031 | } |
16032 | else | |
742a56fe | 16033 | fill_ptr = 0; |
252b5132 RH |
16034 | if (temp) |
16035 | { | |
a8dbcb85 TS |
16036 | segment_info_type *si = seg_info (now_seg); |
16037 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16038 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16039 | auto_align = 1; |
462427c4 | 16040 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16041 | } |
16042 | else | |
16043 | { | |
16044 | auto_align = 0; | |
16045 | } | |
16046 | ||
16047 | demand_empty_rest_of_line (); | |
16048 | } | |
16049 | ||
252b5132 | 16050 | static void |
17a2f251 | 16051 | s_change_sec (int sec) |
252b5132 RH |
16052 | { |
16053 | segT seg; | |
16054 | ||
252b5132 RH |
16055 | /* The ELF backend needs to know that we are changing sections, so |
16056 | that .previous works correctly. We could do something like check | |
b6ff326e | 16057 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16058 | as it would not be appropriate to use it in the section changing |
16059 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16060 | This should be cleaner, somehow. */ | |
f3ded42a | 16061 | obj_elf_section_change_hook (); |
252b5132 | 16062 | |
7d10b47d | 16063 | mips_emit_delays (); |
6a32d874 | 16064 | |
252b5132 RH |
16065 | switch (sec) |
16066 | { | |
16067 | case 't': | |
16068 | s_text (0); | |
16069 | break; | |
16070 | case 'd': | |
16071 | s_data (0); | |
16072 | break; | |
16073 | case 'b': | |
16074 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16075 | demand_empty_rest_of_line (); | |
16076 | break; | |
16077 | ||
16078 | case 'r': | |
4d0d148d TS |
16079 | seg = subseg_new (RDATA_SECTION_NAME, |
16080 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16081 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16082 | | SEC_READONLY | SEC_RELOC | |
16083 | | SEC_DATA)); | |
16084 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16085 | record_alignment (seg, 4); | |
4d0d148d | 16086 | demand_empty_rest_of_line (); |
252b5132 RH |
16087 | break; |
16088 | ||
16089 | case 's': | |
4d0d148d | 16090 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
16091 | bfd_set_section_flags (stdoutput, seg, |
16092 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
16093 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16094 | record_alignment (seg, 4); | |
4d0d148d TS |
16095 | demand_empty_rest_of_line (); |
16096 | break; | |
998b3c36 MR |
16097 | |
16098 | case 'B': | |
16099 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16100 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
16101 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16102 | record_alignment (seg, 4); | |
998b3c36 MR |
16103 | demand_empty_rest_of_line (); |
16104 | break; | |
252b5132 RH |
16105 | } |
16106 | ||
16107 | auto_align = 1; | |
16108 | } | |
b34976b6 | 16109 | |
cca86cc8 | 16110 | void |
17a2f251 | 16111 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16112 | { |
cca86cc8 SC |
16113 | char *section_name; |
16114 | char c; | |
684022ea | 16115 | char next_c = 0; |
cca86cc8 SC |
16116 | int section_type; |
16117 | int section_flag; | |
16118 | int section_entry_size; | |
16119 | int section_alignment; | |
b34976b6 | 16120 | |
cca86cc8 SC |
16121 | section_name = input_line_pointer; |
16122 | c = get_symbol_end (); | |
a816d1ed AO |
16123 | if (c) |
16124 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16125 | |
4cf0dd0d TS |
16126 | /* Do we have .section Name<,"flags">? */ |
16127 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16128 | { |
4cf0dd0d TS |
16129 | /* just after name is now '\0'. */ |
16130 | *input_line_pointer = c; | |
cca86cc8 SC |
16131 | input_line_pointer = section_name; |
16132 | obj_elf_section (ignore); | |
16133 | return; | |
16134 | } | |
16135 | input_line_pointer++; | |
16136 | ||
16137 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16138 | if (c == ',') | |
16139 | section_type = get_absolute_expression (); | |
16140 | else | |
16141 | section_type = 0; | |
16142 | if (*input_line_pointer++ == ',') | |
16143 | section_flag = get_absolute_expression (); | |
16144 | else | |
16145 | section_flag = 0; | |
16146 | if (*input_line_pointer++ == ',') | |
16147 | section_entry_size = get_absolute_expression (); | |
16148 | else | |
16149 | section_entry_size = 0; | |
16150 | if (*input_line_pointer++ == ',') | |
16151 | section_alignment = get_absolute_expression (); | |
16152 | else | |
16153 | section_alignment = 0; | |
87975d2a AM |
16154 | /* FIXME: really ignore? */ |
16155 | (void) section_alignment; | |
cca86cc8 | 16156 | |
a816d1ed AO |
16157 | section_name = xstrdup (section_name); |
16158 | ||
8ab8a5c8 RS |
16159 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16160 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16161 | traditionally had to fall back on the more common @progbits instead. | |
16162 | ||
16163 | There's nothing really harmful in this, since bfd will correct | |
16164 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16165 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16166 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16167 | ||
16168 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16169 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16170 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16171 | generic type-checking code. */ | |
16172 | if (section_type == SHT_MIPS_DWARF) | |
16173 | section_type = SHT_PROGBITS; | |
16174 | ||
cca86cc8 SC |
16175 | obj_elf_change_section (section_name, section_type, section_flag, |
16176 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16177 | |
16178 | if (now_seg->name != section_name) | |
16179 | free (section_name); | |
cca86cc8 | 16180 | } |
252b5132 RH |
16181 | |
16182 | void | |
17a2f251 | 16183 | mips_enable_auto_align (void) |
252b5132 RH |
16184 | { |
16185 | auto_align = 1; | |
16186 | } | |
16187 | ||
16188 | static void | |
17a2f251 | 16189 | s_cons (int log_size) |
252b5132 | 16190 | { |
a8dbcb85 TS |
16191 | segment_info_type *si = seg_info (now_seg); |
16192 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16193 | |
7d10b47d | 16194 | mips_emit_delays (); |
252b5132 | 16195 | if (log_size > 0 && auto_align) |
462427c4 | 16196 | mips_align (log_size, 0, l); |
252b5132 | 16197 | cons (1 << log_size); |
a1facbec | 16198 | mips_clear_insn_labels (); |
252b5132 RH |
16199 | } |
16200 | ||
16201 | static void | |
17a2f251 | 16202 | s_float_cons (int type) |
252b5132 | 16203 | { |
a8dbcb85 TS |
16204 | segment_info_type *si = seg_info (now_seg); |
16205 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16206 | |
7d10b47d | 16207 | mips_emit_delays (); |
252b5132 RH |
16208 | |
16209 | if (auto_align) | |
49309057 ILT |
16210 | { |
16211 | if (type == 'd') | |
462427c4 | 16212 | mips_align (3, 0, l); |
49309057 | 16213 | else |
462427c4 | 16214 | mips_align (2, 0, l); |
49309057 | 16215 | } |
252b5132 | 16216 | |
252b5132 | 16217 | float_cons (type); |
a1facbec | 16218 | mips_clear_insn_labels (); |
252b5132 RH |
16219 | } |
16220 | ||
16221 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16222 | permitted to say | |
16223 | .globl foo .text | |
16224 | where foo is an undefined symbol, to mean that foo should be | |
16225 | considered to be the address of a function. */ | |
16226 | ||
16227 | static void | |
17a2f251 | 16228 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16229 | { |
16230 | char *name; | |
16231 | int c; | |
16232 | symbolS *symbolP; | |
16233 | flagword flag; | |
16234 | ||
8a06b769 | 16235 | do |
252b5132 | 16236 | { |
8a06b769 | 16237 | name = input_line_pointer; |
252b5132 | 16238 | c = get_symbol_end (); |
8a06b769 TS |
16239 | symbolP = symbol_find_or_make (name); |
16240 | S_SET_EXTERNAL (symbolP); | |
16241 | ||
252b5132 | 16242 | *input_line_pointer = c; |
8a06b769 | 16243 | SKIP_WHITESPACE (); |
252b5132 | 16244 | |
8a06b769 TS |
16245 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16246 | being a function is apparently labelled as being an object. */ | |
16247 | flag = BSF_OBJECT; | |
252b5132 | 16248 | |
8a06b769 TS |
16249 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16250 | && (*input_line_pointer != ',')) | |
16251 | { | |
16252 | char *secname; | |
16253 | asection *sec; | |
16254 | ||
16255 | secname = input_line_pointer; | |
16256 | c = get_symbol_end (); | |
16257 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16258 | if (sec == NULL) | |
16259 | as_bad (_("%s: no such section"), secname); | |
16260 | *input_line_pointer = c; | |
16261 | ||
16262 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16263 | flag = BSF_FUNCTION; | |
16264 | } | |
16265 | ||
16266 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16267 | ||
16268 | c = *input_line_pointer; | |
16269 | if (c == ',') | |
16270 | { | |
16271 | input_line_pointer++; | |
16272 | SKIP_WHITESPACE (); | |
16273 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16274 | c = '\n'; | |
16275 | } | |
16276 | } | |
16277 | while (c == ','); | |
252b5132 | 16278 | |
252b5132 RH |
16279 | demand_empty_rest_of_line (); |
16280 | } | |
16281 | ||
16282 | static void | |
17a2f251 | 16283 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16284 | { |
16285 | char *opt; | |
16286 | char c; | |
16287 | ||
16288 | opt = input_line_pointer; | |
16289 | c = get_symbol_end (); | |
16290 | ||
16291 | if (*opt == 'O') | |
16292 | { | |
16293 | /* FIXME: What does this mean? */ | |
16294 | } | |
16295 | else if (strncmp (opt, "pic", 3) == 0) | |
16296 | { | |
16297 | int i; | |
16298 | ||
16299 | i = atoi (opt + 3); | |
16300 | if (i == 0) | |
16301 | mips_pic = NO_PIC; | |
16302 | else if (i == 2) | |
143d77c5 | 16303 | { |
8b828383 | 16304 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16305 | mips_abicalls = TRUE; |
16306 | } | |
252b5132 RH |
16307 | else |
16308 | as_bad (_(".option pic%d not supported"), i); | |
16309 | ||
4d0d148d | 16310 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16311 | { |
16312 | if (g_switch_seen && g_switch_value != 0) | |
16313 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16314 | g_switch_value = 0; | |
16315 | bfd_set_gp_size (stdoutput, 0); | |
16316 | } | |
16317 | } | |
16318 | else | |
16319 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16320 | ||
16321 | *input_line_pointer = c; | |
16322 | demand_empty_rest_of_line (); | |
16323 | } | |
16324 | ||
16325 | /* This structure is used to hold a stack of .set values. */ | |
16326 | ||
e972090a NC |
16327 | struct mips_option_stack |
16328 | { | |
252b5132 RH |
16329 | struct mips_option_stack *next; |
16330 | struct mips_set_options options; | |
16331 | }; | |
16332 | ||
16333 | static struct mips_option_stack *mips_opts_stack; | |
16334 | ||
16335 | /* Handle the .set pseudo-op. */ | |
16336 | ||
16337 | static void | |
17a2f251 | 16338 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16339 | { |
16340 | char *name = input_line_pointer, ch; | |
c6278170 | 16341 | const struct mips_ase *ase; |
252b5132 RH |
16342 | |
16343 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16344 | ++input_line_pointer; |
252b5132 RH |
16345 | ch = *input_line_pointer; |
16346 | *input_line_pointer = '\0'; | |
16347 | ||
16348 | if (strcmp (name, "reorder") == 0) | |
16349 | { | |
7d10b47d RS |
16350 | if (mips_opts.noreorder) |
16351 | end_noreorder (); | |
252b5132 RH |
16352 | } |
16353 | else if (strcmp (name, "noreorder") == 0) | |
16354 | { | |
7d10b47d RS |
16355 | if (!mips_opts.noreorder) |
16356 | start_noreorder (); | |
252b5132 | 16357 | } |
741fe287 MR |
16358 | else if (strncmp (name, "at=", 3) == 0) |
16359 | { | |
16360 | char *s = name + 3; | |
16361 | ||
16362 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16363 | as_bad (_("Unrecognized register name `%s'"), s); | |
16364 | } | |
252b5132 RH |
16365 | else if (strcmp (name, "at") == 0) |
16366 | { | |
741fe287 | 16367 | mips_opts.at = ATREG; |
252b5132 RH |
16368 | } |
16369 | else if (strcmp (name, "noat") == 0) | |
16370 | { | |
741fe287 | 16371 | mips_opts.at = ZERO; |
252b5132 RH |
16372 | } |
16373 | else if (strcmp (name, "macro") == 0) | |
16374 | { | |
16375 | mips_opts.warn_about_macros = 0; | |
16376 | } | |
16377 | else if (strcmp (name, "nomacro") == 0) | |
16378 | { | |
16379 | if (mips_opts.noreorder == 0) | |
16380 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16381 | mips_opts.warn_about_macros = 1; | |
16382 | } | |
16383 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16384 | { | |
16385 | mips_opts.nomove = 0; | |
16386 | } | |
16387 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16388 | { | |
16389 | mips_opts.nomove = 1; | |
16390 | } | |
16391 | else if (strcmp (name, "bopt") == 0) | |
16392 | { | |
16393 | mips_opts.nobopt = 0; | |
16394 | } | |
16395 | else if (strcmp (name, "nobopt") == 0) | |
16396 | { | |
16397 | mips_opts.nobopt = 1; | |
16398 | } | |
ad3fea08 TS |
16399 | else if (strcmp (name, "gp=default") == 0) |
16400 | mips_opts.gp32 = file_mips_gp32; | |
16401 | else if (strcmp (name, "gp=32") == 0) | |
16402 | mips_opts.gp32 = 1; | |
16403 | else if (strcmp (name, "gp=64") == 0) | |
16404 | { | |
16405 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16406 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16407 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16408 | mips_opts.gp32 = 0; | |
16409 | } | |
16410 | else if (strcmp (name, "fp=default") == 0) | |
16411 | mips_opts.fp32 = file_mips_fp32; | |
16412 | else if (strcmp (name, "fp=32") == 0) | |
16413 | mips_opts.fp32 = 1; | |
16414 | else if (strcmp (name, "fp=64") == 0) | |
16415 | { | |
16416 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16417 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16418 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16419 | mips_opts.fp32 = 0; | |
16420 | } | |
037b32b9 AN |
16421 | else if (strcmp (name, "softfloat") == 0) |
16422 | mips_opts.soft_float = 1; | |
16423 | else if (strcmp (name, "hardfloat") == 0) | |
16424 | mips_opts.soft_float = 0; | |
16425 | else if (strcmp (name, "singlefloat") == 0) | |
16426 | mips_opts.single_float = 1; | |
16427 | else if (strcmp (name, "doublefloat") == 0) | |
16428 | mips_opts.single_float = 0; | |
252b5132 RH |
16429 | else if (strcmp (name, "mips16") == 0 |
16430 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16431 | { |
16432 | if (mips_opts.micromips == 1) | |
16433 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16434 | mips_opts.mips16 = 1; | |
16435 | } | |
252b5132 RH |
16436 | else if (strcmp (name, "nomips16") == 0 |
16437 | || strcmp (name, "noMIPS-16") == 0) | |
16438 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16439 | else if (strcmp (name, "micromips") == 0) |
16440 | { | |
16441 | if (mips_opts.mips16 == 1) | |
16442 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16443 | mips_opts.micromips = 1; | |
16444 | } | |
16445 | else if (strcmp (name, "nomicromips") == 0) | |
16446 | mips_opts.micromips = 0; | |
c6278170 RS |
16447 | else if (name[0] == 'n' |
16448 | && name[1] == 'o' | |
16449 | && (ase = mips_lookup_ase (name + 2))) | |
16450 | mips_set_ase (ase, FALSE); | |
16451 | else if ((ase = mips_lookup_ase (name))) | |
16452 | mips_set_ase (ase, TRUE); | |
1a2c1fad | 16453 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16454 | { |
af7ee8bf | 16455 | int reset = 0; |
252b5132 | 16456 | |
1a2c1fad CD |
16457 | /* Permit the user to change the ISA and architecture on the fly. |
16458 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16459 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16460 | { |
16461 | reset = 1; | |
16462 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16463 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16464 | } |
16465 | else if (strncmp (name, "arch=", 5) == 0) | |
16466 | { | |
16467 | const struct mips_cpu_info *p; | |
16468 | ||
16469 | p = mips_parse_cpu("internal use", name + 5); | |
16470 | if (!p) | |
16471 | as_bad (_("unknown architecture %s"), name + 5); | |
16472 | else | |
16473 | { | |
16474 | mips_opts.arch = p->cpu; | |
16475 | mips_opts.isa = p->isa; | |
16476 | } | |
16477 | } | |
81a21e38 TS |
16478 | else if (strncmp (name, "mips", 4) == 0) |
16479 | { | |
16480 | const struct mips_cpu_info *p; | |
16481 | ||
16482 | p = mips_parse_cpu("internal use", name); | |
16483 | if (!p) | |
16484 | as_bad (_("unknown ISA level %s"), name + 4); | |
16485 | else | |
16486 | { | |
16487 | mips_opts.arch = p->cpu; | |
16488 | mips_opts.isa = p->isa; | |
16489 | } | |
16490 | } | |
af7ee8bf | 16491 | else |
81a21e38 | 16492 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16493 | |
16494 | switch (mips_opts.isa) | |
98d3f06f KH |
16495 | { |
16496 | case 0: | |
98d3f06f | 16497 | break; |
af7ee8bf CD |
16498 | case ISA_MIPS1: |
16499 | case ISA_MIPS2: | |
16500 | case ISA_MIPS32: | |
16501 | case ISA_MIPS32R2: | |
98d3f06f KH |
16502 | mips_opts.gp32 = 1; |
16503 | mips_opts.fp32 = 1; | |
16504 | break; | |
af7ee8bf CD |
16505 | case ISA_MIPS3: |
16506 | case ISA_MIPS4: | |
16507 | case ISA_MIPS5: | |
16508 | case ISA_MIPS64: | |
5f74bc13 | 16509 | case ISA_MIPS64R2: |
98d3f06f | 16510 | mips_opts.gp32 = 0; |
e407c74b NC |
16511 | if (mips_opts.arch == CPU_R5900) |
16512 | { | |
16513 | mips_opts.fp32 = 1; | |
16514 | } | |
16515 | else | |
16516 | { | |
98d3f06f | 16517 | mips_opts.fp32 = 0; |
e407c74b | 16518 | } |
98d3f06f KH |
16519 | break; |
16520 | default: | |
16521 | as_bad (_("unknown ISA level %s"), name + 4); | |
16522 | break; | |
16523 | } | |
af7ee8bf | 16524 | if (reset) |
98d3f06f | 16525 | { |
af7ee8bf CD |
16526 | mips_opts.gp32 = file_mips_gp32; |
16527 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16528 | } |
252b5132 RH |
16529 | } |
16530 | else if (strcmp (name, "autoextend") == 0) | |
16531 | mips_opts.noautoextend = 0; | |
16532 | else if (strcmp (name, "noautoextend") == 0) | |
16533 | mips_opts.noautoextend = 1; | |
833794fc MR |
16534 | else if (strcmp (name, "insn32") == 0) |
16535 | mips_opts.insn32 = TRUE; | |
16536 | else if (strcmp (name, "noinsn32") == 0) | |
16537 | mips_opts.insn32 = FALSE; | |
252b5132 RH |
16538 | else if (strcmp (name, "push") == 0) |
16539 | { | |
16540 | struct mips_option_stack *s; | |
16541 | ||
16542 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16543 | s->next = mips_opts_stack; | |
16544 | s->options = mips_opts; | |
16545 | mips_opts_stack = s; | |
16546 | } | |
16547 | else if (strcmp (name, "pop") == 0) | |
16548 | { | |
16549 | struct mips_option_stack *s; | |
16550 | ||
16551 | s = mips_opts_stack; | |
16552 | if (s == NULL) | |
16553 | as_bad (_(".set pop with no .set push")); | |
16554 | else | |
16555 | { | |
16556 | /* If we're changing the reorder mode we need to handle | |
16557 | delay slots correctly. */ | |
16558 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16559 | start_noreorder (); |
252b5132 | 16560 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16561 | end_noreorder (); |
252b5132 RH |
16562 | |
16563 | mips_opts = s->options; | |
16564 | mips_opts_stack = s->next; | |
16565 | free (s); | |
16566 | } | |
16567 | } | |
aed1a261 RS |
16568 | else if (strcmp (name, "sym32") == 0) |
16569 | mips_opts.sym32 = TRUE; | |
16570 | else if (strcmp (name, "nosym32") == 0) | |
16571 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16572 | else if (strchr (name, ',')) |
16573 | { | |
16574 | /* Generic ".set" directive; use the generic handler. */ | |
16575 | *input_line_pointer = ch; | |
16576 | input_line_pointer = name; | |
16577 | s_set (0); | |
16578 | return; | |
16579 | } | |
252b5132 RH |
16580 | else |
16581 | { | |
16582 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16583 | } | |
c6278170 | 16584 | mips_check_isa_supports_ases (); |
252b5132 RH |
16585 | *input_line_pointer = ch; |
16586 | demand_empty_rest_of_line (); | |
16587 | } | |
16588 | ||
16589 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16590 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16591 | ||
16592 | static void | |
17a2f251 | 16593 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16594 | { |
16595 | mips_pic = SVR4_PIC; | |
143d77c5 | 16596 | mips_abicalls = TRUE; |
4d0d148d TS |
16597 | |
16598 | if (g_switch_seen && g_switch_value != 0) | |
16599 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16600 | g_switch_value = 0; | |
16601 | ||
252b5132 RH |
16602 | bfd_set_gp_size (stdoutput, 0); |
16603 | demand_empty_rest_of_line (); | |
16604 | } | |
16605 | ||
16606 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16607 | PIC code. It sets the $gp register for the function based on the | |
16608 | function address, which is in the register named in the argument. | |
16609 | This uses a relocation against _gp_disp, which is handled specially | |
16610 | by the linker. The result is: | |
16611 | lui $gp,%hi(_gp_disp) | |
16612 | addiu $gp,$gp,%lo(_gp_disp) | |
16613 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16614 | The .cpload argument is normally $25 == $t9. |
16615 | ||
16616 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16617 | lui $gp,%hi(__gnu_local_gp) |
16618 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16619 | and the argument is ignored. This saves an instruction, but the |
16620 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16621 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16622 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16623 | |
16624 | static void | |
17a2f251 | 16625 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16626 | { |
16627 | expressionS ex; | |
aa6975fb ILT |
16628 | int reg; |
16629 | int in_shared; | |
252b5132 | 16630 | |
6478892d TS |
16631 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16632 | .cpload is ignored. */ | |
16633 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16634 | { |
16635 | s_ignore (0); | |
16636 | return; | |
16637 | } | |
16638 | ||
a276b80c MR |
16639 | if (mips_opts.mips16) |
16640 | { | |
16641 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16642 | ignore_rest_of_line (); | |
16643 | return; | |
16644 | } | |
16645 | ||
d3ecfc59 | 16646 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16647 | if (mips_opts.noreorder == 0) |
16648 | as_warn (_(".cpload not in noreorder section")); | |
16649 | ||
aa6975fb ILT |
16650 | reg = tc_get_register (0); |
16651 | ||
16652 | /* If we need to produce a 64-bit address, we are better off using | |
16653 | the default instruction sequence. */ | |
aed1a261 | 16654 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16655 | |
252b5132 | 16656 | ex.X_op = O_symbol; |
bbe506e8 TS |
16657 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16658 | "__gnu_local_gp"); | |
252b5132 RH |
16659 | ex.X_op_symbol = NULL; |
16660 | ex.X_add_number = 0; | |
16661 | ||
16662 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16663 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16664 | |
8a75745d MR |
16665 | mips_mark_labels (); |
16666 | mips_assembling_insn = TRUE; | |
16667 | ||
584892a6 | 16668 | macro_start (); |
67c0d1eb RS |
16669 | macro_build_lui (&ex, mips_gp_register); |
16670 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16671 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16672 | if (in_shared) |
16673 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16674 | mips_gp_register, reg); | |
584892a6 | 16675 | macro_end (); |
252b5132 | 16676 | |
8a75745d | 16677 | mips_assembling_insn = FALSE; |
252b5132 RH |
16678 | demand_empty_rest_of_line (); |
16679 | } | |
16680 | ||
6478892d TS |
16681 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16682 | .cpsetup $reg1, offset|$reg2, label | |
16683 | ||
16684 | If offset is given, this results in: | |
16685 | sd $gp, offset($sp) | |
956cd1d6 | 16686 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16687 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16688 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16689 | |
16690 | If $reg2 is given, this results in: | |
16691 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16692 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16693 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16694 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16695 | $reg1 is normally $25 == $t9. |
16696 | ||
16697 | The -mno-shared option replaces the last three instructions with | |
16698 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16699 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16700 | |
6478892d | 16701 | static void |
17a2f251 | 16702 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16703 | { |
16704 | expressionS ex_off; | |
16705 | expressionS ex_sym; | |
16706 | int reg1; | |
6478892d | 16707 | |
8586fc66 | 16708 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16709 | We also need NewABI support. */ |
16710 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16711 | { | |
16712 | s_ignore (0); | |
16713 | return; | |
16714 | } | |
16715 | ||
a276b80c MR |
16716 | if (mips_opts.mips16) |
16717 | { | |
16718 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16719 | ignore_rest_of_line (); | |
16720 | return; | |
16721 | } | |
16722 | ||
6478892d TS |
16723 | reg1 = tc_get_register (0); |
16724 | SKIP_WHITESPACE (); | |
16725 | if (*input_line_pointer != ',') | |
16726 | { | |
16727 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16728 | return; | |
16729 | } | |
16730 | else | |
80245285 | 16731 | ++input_line_pointer; |
6478892d TS |
16732 | SKIP_WHITESPACE (); |
16733 | if (*input_line_pointer == '$') | |
80245285 TS |
16734 | { |
16735 | mips_cpreturn_register = tc_get_register (0); | |
16736 | mips_cpreturn_offset = -1; | |
16737 | } | |
6478892d | 16738 | else |
80245285 TS |
16739 | { |
16740 | mips_cpreturn_offset = get_absolute_expression (); | |
16741 | mips_cpreturn_register = -1; | |
16742 | } | |
6478892d TS |
16743 | SKIP_WHITESPACE (); |
16744 | if (*input_line_pointer != ',') | |
16745 | { | |
16746 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16747 | return; | |
16748 | } | |
16749 | else | |
f9419b05 | 16750 | ++input_line_pointer; |
6478892d | 16751 | SKIP_WHITESPACE (); |
f21f8242 | 16752 | expression (&ex_sym); |
6478892d | 16753 | |
8a75745d MR |
16754 | mips_mark_labels (); |
16755 | mips_assembling_insn = TRUE; | |
16756 | ||
584892a6 | 16757 | macro_start (); |
6478892d TS |
16758 | if (mips_cpreturn_register == -1) |
16759 | { | |
16760 | ex_off.X_op = O_constant; | |
16761 | ex_off.X_add_symbol = NULL; | |
16762 | ex_off.X_op_symbol = NULL; | |
16763 | ex_off.X_add_number = mips_cpreturn_offset; | |
16764 | ||
67c0d1eb | 16765 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16766 | BFD_RELOC_LO16, SP); |
6478892d TS |
16767 | } |
16768 | else | |
67c0d1eb | 16769 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16770 | mips_gp_register, 0); |
6478892d | 16771 | |
aed1a261 | 16772 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16773 | { |
df58fc94 | 16774 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16775 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16776 | BFD_RELOC_HI16_S); | |
16777 | ||
16778 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16779 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16780 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16781 | ||
16782 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16783 | mips_gp_register, reg1); | |
16784 | } | |
16785 | else | |
16786 | { | |
16787 | expressionS ex; | |
16788 | ||
16789 | ex.X_op = O_symbol; | |
4184909a | 16790 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16791 | ex.X_op_symbol = NULL; |
16792 | ex.X_add_number = 0; | |
6e1304d8 | 16793 | |
aa6975fb ILT |
16794 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16795 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16796 | ||
16797 | macro_build_lui (&ex, mips_gp_register); | |
16798 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16799 | mips_gp_register, BFD_RELOC_LO16); | |
16800 | } | |
f21f8242 | 16801 | |
584892a6 | 16802 | macro_end (); |
6478892d | 16803 | |
8a75745d | 16804 | mips_assembling_insn = FALSE; |
6478892d TS |
16805 | demand_empty_rest_of_line (); |
16806 | } | |
16807 | ||
16808 | static void | |
17a2f251 | 16809 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16810 | { |
16811 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16812 | .cplocal is ignored. */ |
6478892d TS |
16813 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16814 | { | |
16815 | s_ignore (0); | |
16816 | return; | |
16817 | } | |
16818 | ||
a276b80c MR |
16819 | if (mips_opts.mips16) |
16820 | { | |
16821 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16822 | ignore_rest_of_line (); | |
16823 | return; | |
16824 | } | |
16825 | ||
6478892d | 16826 | mips_gp_register = tc_get_register (0); |
85b51719 | 16827 | demand_empty_rest_of_line (); |
6478892d TS |
16828 | } |
16829 | ||
252b5132 RH |
16830 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16831 | offset from $sp. The offset is remembered, and after making a PIC | |
16832 | call $gp is restored from that location. */ | |
16833 | ||
16834 | static void | |
17a2f251 | 16835 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16836 | { |
16837 | expressionS ex; | |
252b5132 | 16838 | |
6478892d | 16839 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16840 | .cprestore is ignored. */ |
6478892d | 16841 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16842 | { |
16843 | s_ignore (0); | |
16844 | return; | |
16845 | } | |
16846 | ||
a276b80c MR |
16847 | if (mips_opts.mips16) |
16848 | { | |
16849 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16850 | ignore_rest_of_line (); | |
16851 | return; | |
16852 | } | |
16853 | ||
252b5132 | 16854 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16855 | mips_cprestore_valid = 1; |
252b5132 RH |
16856 | |
16857 | ex.X_op = O_constant; | |
16858 | ex.X_add_symbol = NULL; | |
16859 | ex.X_op_symbol = NULL; | |
16860 | ex.X_add_number = mips_cprestore_offset; | |
16861 | ||
8a75745d MR |
16862 | mips_mark_labels (); |
16863 | mips_assembling_insn = TRUE; | |
16864 | ||
584892a6 | 16865 | macro_start (); |
67c0d1eb RS |
16866 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16867 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16868 | macro_end (); |
252b5132 | 16869 | |
8a75745d | 16870 | mips_assembling_insn = FALSE; |
252b5132 RH |
16871 | demand_empty_rest_of_line (); |
16872 | } | |
16873 | ||
6478892d | 16874 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16875 | was given in the preceding .cpsetup, it results in: |
6478892d | 16876 | ld $gp, offset($sp) |
76b3015f | 16877 | |
6478892d | 16878 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16879 | daddu $gp, $reg2, $0 */ |
16880 | ||
6478892d | 16881 | static void |
17a2f251 | 16882 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16883 | { |
16884 | expressionS ex; | |
6478892d TS |
16885 | |
16886 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16887 | We also need NewABI support. */ | |
16888 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16889 | { | |
16890 | s_ignore (0); | |
16891 | return; | |
16892 | } | |
16893 | ||
a276b80c MR |
16894 | if (mips_opts.mips16) |
16895 | { | |
16896 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16897 | ignore_rest_of_line (); | |
16898 | return; | |
16899 | } | |
16900 | ||
8a75745d MR |
16901 | mips_mark_labels (); |
16902 | mips_assembling_insn = TRUE; | |
16903 | ||
584892a6 | 16904 | macro_start (); |
6478892d TS |
16905 | if (mips_cpreturn_register == -1) |
16906 | { | |
16907 | ex.X_op = O_constant; | |
16908 | ex.X_add_symbol = NULL; | |
16909 | ex.X_op_symbol = NULL; | |
16910 | ex.X_add_number = mips_cpreturn_offset; | |
16911 | ||
67c0d1eb | 16912 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16913 | } |
16914 | else | |
67c0d1eb | 16915 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16916 | mips_cpreturn_register, 0); |
584892a6 | 16917 | macro_end (); |
6478892d | 16918 | |
8a75745d | 16919 | mips_assembling_insn = FALSE; |
6478892d TS |
16920 | demand_empty_rest_of_line (); |
16921 | } | |
16922 | ||
d0f13682 CLT |
16923 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16924 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16925 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16926 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16927 | |
16928 | static void | |
d0f13682 CLT |
16929 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16930 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16931 | { |
16932 | expressionS ex; | |
16933 | char *p; | |
16934 | ||
16935 | expression (&ex); | |
16936 | ||
16937 | if (ex.X_op != O_symbol) | |
16938 | { | |
d0f13682 | 16939 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
16940 | ignore_rest_of_line (); |
16941 | } | |
16942 | ||
16943 | p = frag_more (bytes); | |
16944 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16945 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16946 | demand_empty_rest_of_line (); |
de64cffd | 16947 | mips_clear_insn_labels (); |
741d6ea8 JM |
16948 | } |
16949 | ||
16950 | /* Handle .dtprelword. */ | |
16951 | ||
16952 | static void | |
16953 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16954 | { | |
d0f13682 | 16955 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16956 | } |
16957 | ||
16958 | /* Handle .dtpreldword. */ | |
16959 | ||
16960 | static void | |
16961 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16962 | { | |
d0f13682 CLT |
16963 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16964 | } | |
16965 | ||
16966 | /* Handle .tprelword. */ | |
16967 | ||
16968 | static void | |
16969 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16970 | { | |
16971 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16972 | } | |
16973 | ||
16974 | /* Handle .tpreldword. */ | |
16975 | ||
16976 | static void | |
16977 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16978 | { | |
16979 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16980 | } |
16981 | ||
6478892d TS |
16982 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16983 | code. It sets the offset to use in gp_rel relocations. */ | |
16984 | ||
16985 | static void | |
17a2f251 | 16986 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16987 | { |
16988 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16989 | We also need NewABI support. */ | |
16990 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16991 | { | |
16992 | s_ignore (0); | |
16993 | return; | |
16994 | } | |
16995 | ||
def2e0dd | 16996 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16997 | |
16998 | demand_empty_rest_of_line (); | |
16999 | } | |
17000 | ||
252b5132 RH |
17001 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17002 | code. It generates a 32 bit GP relative reloc. */ | |
17003 | ||
17004 | static void | |
17a2f251 | 17005 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17006 | { |
a8dbcb85 TS |
17007 | segment_info_type *si; |
17008 | struct insn_label_list *l; | |
252b5132 RH |
17009 | expressionS ex; |
17010 | char *p; | |
17011 | ||
17012 | /* When not generating PIC code, this is treated as .word. */ | |
17013 | if (mips_pic != SVR4_PIC) | |
17014 | { | |
17015 | s_cons (2); | |
17016 | return; | |
17017 | } | |
17018 | ||
a8dbcb85 TS |
17019 | si = seg_info (now_seg); |
17020 | l = si->label_list; | |
7d10b47d | 17021 | mips_emit_delays (); |
252b5132 | 17022 | if (auto_align) |
462427c4 | 17023 | mips_align (2, 0, l); |
252b5132 RH |
17024 | |
17025 | expression (&ex); | |
a1facbec | 17026 | mips_clear_insn_labels (); |
252b5132 RH |
17027 | |
17028 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17029 | { | |
17030 | as_bad (_("Unsupported use of .gpword")); | |
17031 | ignore_rest_of_line (); | |
17032 | } | |
17033 | ||
17034 | p = frag_more (4); | |
17a2f251 | 17035 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17036 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17037 | BFD_RELOC_GPREL32); |
252b5132 RH |
17038 | |
17039 | demand_empty_rest_of_line (); | |
17040 | } | |
17041 | ||
10181a0d | 17042 | static void |
17a2f251 | 17043 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17044 | { |
a8dbcb85 TS |
17045 | segment_info_type *si; |
17046 | struct insn_label_list *l; | |
10181a0d AO |
17047 | expressionS ex; |
17048 | char *p; | |
17049 | ||
17050 | /* When not generating PIC code, this is treated as .dword. */ | |
17051 | if (mips_pic != SVR4_PIC) | |
17052 | { | |
17053 | s_cons (3); | |
17054 | return; | |
17055 | } | |
17056 | ||
a8dbcb85 TS |
17057 | si = seg_info (now_seg); |
17058 | l = si->label_list; | |
7d10b47d | 17059 | mips_emit_delays (); |
10181a0d | 17060 | if (auto_align) |
462427c4 | 17061 | mips_align (3, 0, l); |
10181a0d AO |
17062 | |
17063 | expression (&ex); | |
a1facbec | 17064 | mips_clear_insn_labels (); |
10181a0d AO |
17065 | |
17066 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17067 | { | |
17068 | as_bad (_("Unsupported use of .gpdword")); | |
17069 | ignore_rest_of_line (); | |
17070 | } | |
17071 | ||
17072 | p = frag_more (8); | |
17a2f251 | 17073 | md_number_to_chars (p, 0, 8); |
a105a300 | 17074 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17075 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17076 | |
17077 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17078 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17079 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17080 | |
17081 | demand_empty_rest_of_line (); | |
17082 | } | |
17083 | ||
a3f278e2 CM |
17084 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17085 | tables. It generates a R_MIPS_EH reloc. */ | |
17086 | ||
17087 | static void | |
17088 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17089 | { | |
17090 | expressionS ex; | |
17091 | char *p; | |
17092 | ||
17093 | mips_emit_delays (); | |
17094 | ||
17095 | expression (&ex); | |
17096 | mips_clear_insn_labels (); | |
17097 | ||
17098 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17099 | { | |
17100 | as_bad (_("Unsupported use of .ehword")); | |
17101 | ignore_rest_of_line (); | |
17102 | } | |
17103 | ||
17104 | p = frag_more (4); | |
17105 | md_number_to_chars (p, 0, 4); | |
17106 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
17107 | BFD_RELOC_MIPS_EH); | |
17108 | ||
17109 | demand_empty_rest_of_line (); | |
17110 | } | |
17111 | ||
252b5132 RH |
17112 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17113 | tables in SVR4 PIC code. */ | |
17114 | ||
17115 | static void | |
17a2f251 | 17116 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17117 | { |
252b5132 RH |
17118 | int reg; |
17119 | ||
10181a0d AO |
17120 | /* This is ignored when not generating SVR4 PIC code. */ |
17121 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17122 | { |
17123 | s_ignore (0); | |
17124 | return; | |
17125 | } | |
17126 | ||
8a75745d MR |
17127 | mips_mark_labels (); |
17128 | mips_assembling_insn = TRUE; | |
17129 | ||
252b5132 | 17130 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17131 | macro_start (); |
252b5132 | 17132 | reg = tc_get_register (0); |
67c0d1eb | 17133 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17134 | macro_end (); |
252b5132 | 17135 | |
8a75745d | 17136 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17137 | demand_empty_rest_of_line (); |
252b5132 RH |
17138 | } |
17139 | ||
17140 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17141 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17142 | such as generating jalx instructions when needed. We also make |
17143 | them odd for the duration of the assembly, in order to generate the | |
17144 | right sort of code. We will make them even in the adjust_symtab | |
17145 | routine, while leaving them marked. This is convenient for the | |
17146 | debugger and the disassembler. The linker knows to make them odd | |
17147 | again. */ | |
17148 | ||
17149 | static void | |
17a2f251 | 17150 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17151 | { |
df58fc94 | 17152 | mips_mark_labels (); |
252b5132 RH |
17153 | |
17154 | demand_empty_rest_of_line (); | |
17155 | } | |
17156 | ||
ba92f887 MR |
17157 | /* Handle the .nan pseudo-op. */ |
17158 | ||
17159 | static void | |
17160 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17161 | { | |
17162 | static const char str_legacy[] = "legacy"; | |
17163 | static const char str_2008[] = "2008"; | |
17164 | size_t i; | |
17165 | ||
17166 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17167 | ||
17168 | if (i == sizeof (str_2008) - 1 | |
17169 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
17170 | mips_flag_nan2008 = TRUE; | |
17171 | else if (i == sizeof (str_legacy) - 1 | |
17172 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
17173 | mips_flag_nan2008 = FALSE; | |
17174 | else | |
17175 | as_bad (_("Bad .nan directive")); | |
17176 | ||
17177 | input_line_pointer += i; | |
17178 | demand_empty_rest_of_line (); | |
17179 | } | |
17180 | ||
754e2bb9 RS |
17181 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17182 | implemented in a transparent way, so that removing them would not | |
17183 | have any effect on the generated instructions. However, s_stab | |
17184 | internally changes the section, so in practice we need to decide | |
17185 | now whether the preceding label marks compressed code. We do not | |
17186 | support changing the compression mode of a label after a .stab* | |
17187 | directive, such as in: | |
17188 | ||
17189 | foo: | |
17190 | .stabs ... | |
17191 | .set mips16 | |
17192 | ||
17193 | so the current mode wins. */ | |
252b5132 RH |
17194 | |
17195 | static void | |
17a2f251 | 17196 | s_mips_stab (int type) |
252b5132 | 17197 | { |
754e2bb9 | 17198 | mips_mark_labels (); |
252b5132 RH |
17199 | s_stab (type); |
17200 | } | |
17201 | ||
54f4ddb3 | 17202 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17203 | |
17204 | static void | |
17a2f251 | 17205 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17206 | { |
17207 | char *name; | |
17208 | int c; | |
17209 | symbolS *symbolP; | |
17210 | expressionS exp; | |
17211 | ||
17212 | name = input_line_pointer; | |
17213 | c = get_symbol_end (); | |
17214 | symbolP = symbol_find_or_make (name); | |
17215 | S_SET_WEAK (symbolP); | |
17216 | *input_line_pointer = c; | |
17217 | ||
17218 | SKIP_WHITESPACE (); | |
17219 | ||
17220 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17221 | { | |
17222 | if (S_IS_DEFINED (symbolP)) | |
17223 | { | |
20203fb9 | 17224 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17225 | S_GET_NAME (symbolP)); |
17226 | ignore_rest_of_line (); | |
17227 | return; | |
17228 | } | |
bdaaa2e1 | 17229 | |
252b5132 RH |
17230 | if (*input_line_pointer == ',') |
17231 | { | |
17232 | ++input_line_pointer; | |
17233 | SKIP_WHITESPACE (); | |
17234 | } | |
bdaaa2e1 | 17235 | |
252b5132 RH |
17236 | expression (&exp); |
17237 | if (exp.X_op != O_symbol) | |
17238 | { | |
20203fb9 | 17239 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17240 | ignore_rest_of_line (); |
252b5132 RH |
17241 | return; |
17242 | } | |
49309057 | 17243 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17244 | } |
17245 | ||
17246 | demand_empty_rest_of_line (); | |
17247 | } | |
17248 | ||
17249 | /* Parse a register string into a number. Called from the ECOFF code | |
17250 | to parse .frame. The argument is non-zero if this is the frame | |
17251 | register, so that we can record it in mips_frame_reg. */ | |
17252 | ||
17253 | int | |
17a2f251 | 17254 | tc_get_register (int frame) |
252b5132 | 17255 | { |
707bfff6 | 17256 | unsigned int reg; |
252b5132 RH |
17257 | |
17258 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17259 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17260 | reg = 0; | |
252b5132 | 17261 | if (frame) |
7a621144 DJ |
17262 | { |
17263 | mips_frame_reg = reg != 0 ? reg : SP; | |
17264 | mips_frame_reg_valid = 1; | |
17265 | mips_cprestore_valid = 0; | |
17266 | } | |
252b5132 RH |
17267 | return reg; |
17268 | } | |
17269 | ||
17270 | valueT | |
17a2f251 | 17271 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17272 | { |
17273 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17274 | ||
f3ded42a RS |
17275 | /* We don't need to align ELF sections to the full alignment. |
17276 | However, Irix 5 may prefer that we align them at least to a 16 | |
17277 | byte boundary. We don't bother to align the sections if we | |
17278 | are targeted for an embedded system. */ | |
17279 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17280 | return addr; | |
17281 | if (align > 4) | |
17282 | align = 4; | |
252b5132 RH |
17283 | |
17284 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17285 | } | |
17286 | ||
17287 | /* Utility routine, called from above as well. If called while the | |
17288 | input file is still being read, it's only an approximation. (For | |
17289 | example, a symbol may later become defined which appeared to be | |
17290 | undefined earlier.) */ | |
17291 | ||
17292 | static int | |
17a2f251 | 17293 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17294 | { |
17295 | if (sym == 0) | |
17296 | return 0; | |
17297 | ||
4d0d148d | 17298 | if (g_switch_value > 0) |
252b5132 RH |
17299 | { |
17300 | const char *symname; | |
17301 | int change; | |
17302 | ||
c9914766 | 17303 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17304 | register. It can be if it is smaller than the -G size or if |
17305 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17306 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17307 | they can. */ |
17308 | symname = S_GET_NAME (sym); | |
17309 | if (symname != (const char *) NULL | |
17310 | && (strcmp (symname, "eprol") == 0 | |
17311 | || strcmp (symname, "etext") == 0 | |
17312 | || strcmp (symname, "_gp") == 0 | |
17313 | || strcmp (symname, "edata") == 0 | |
17314 | || strcmp (symname, "_fbss") == 0 | |
17315 | || strcmp (symname, "_fdata") == 0 | |
17316 | || strcmp (symname, "_ftext") == 0 | |
17317 | || strcmp (symname, "end") == 0 | |
17318 | || strcmp (symname, "_gp_disp") == 0)) | |
17319 | change = 1; | |
17320 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17321 | && (0 | |
17322 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17323 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17324 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17325 | <= g_switch_value)) | |
252b5132 RH |
17326 | #endif |
17327 | /* We must defer this decision until after the whole | |
17328 | file has been read, since there might be a .extern | |
17329 | after the first use of this symbol. */ | |
17330 | || (before_relaxing | |
17331 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17332 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17333 | #endif |
17334 | && S_GET_VALUE (sym) == 0) | |
17335 | || (S_GET_VALUE (sym) != 0 | |
17336 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17337 | change = 0; | |
17338 | else | |
17339 | { | |
17340 | const char *segname; | |
17341 | ||
17342 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17343 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17344 | && strcmp (segname, ".lit4") != 0); |
17345 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17346 | && strcmp (segname, ".sbss") != 0 |
17347 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17348 | && strncmp (segname, ".sbss.", 6) != 0 |
17349 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17350 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17351 | } |
17352 | return change; | |
17353 | } | |
17354 | else | |
c9914766 | 17355 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17356 | return 1; |
17357 | } | |
17358 | ||
5919d012 RS |
17359 | |
17360 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17361 | ||
17362 | static bfd_boolean | |
17a2f251 | 17363 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17364 | { |
17365 | asection *symsec; | |
5919d012 RS |
17366 | |
17367 | /* Handle the case of a symbol equated to another symbol. */ | |
17368 | while (symbol_equated_reloc_p (sym)) | |
17369 | { | |
17370 | symbolS *n; | |
17371 | ||
5f0fe04b | 17372 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17373 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17374 | if (n == sym) | |
17375 | break; | |
17376 | sym = n; | |
17377 | } | |
17378 | ||
df1f3cda DD |
17379 | if (symbol_section_p (sym)) |
17380 | return TRUE; | |
17381 | ||
5919d012 RS |
17382 | symsec = S_GET_SEGMENT (sym); |
17383 | ||
5919d012 | 17384 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17385 | return (!bfd_is_und_section (symsec) |
17386 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17387 | && !bfd_is_com_section (symsec) |
17388 | && !s_is_linkonce (sym, segtype) | |
5919d012 | 17389 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17390 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 RS |
17391 | } |
17392 | ||
17393 | ||
252b5132 RH |
17394 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17395 | extended opcode. SEC is the section the frag is in. */ | |
17396 | ||
17397 | static int | |
17a2f251 | 17398 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17399 | { |
17400 | int type; | |
3994f87e | 17401 | const struct mips16_immed_operand *op; |
252b5132 RH |
17402 | offsetT val; |
17403 | int mintiny, maxtiny; | |
17404 | segT symsec; | |
98aa84af | 17405 | fragS *sym_frag; |
252b5132 RH |
17406 | |
17407 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17408 | return 0; | |
17409 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17410 | return 1; | |
17411 | ||
17412 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17413 | op = mips16_immed_operands; | |
17414 | while (op->type != type) | |
17415 | { | |
17416 | ++op; | |
9c2799c2 | 17417 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17418 | } |
17419 | ||
17420 | if (op->unsp) | |
17421 | { | |
17422 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17423 | { | |
17424 | mintiny = 1; | |
17425 | maxtiny = 1 << op->nbits; | |
17426 | } | |
17427 | else | |
17428 | { | |
17429 | mintiny = 0; | |
17430 | maxtiny = (1 << op->nbits) - 1; | |
17431 | } | |
17432 | } | |
17433 | else | |
17434 | { | |
17435 | mintiny = - (1 << (op->nbits - 1)); | |
17436 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17437 | } | |
17438 | ||
98aa84af | 17439 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17440 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17441 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17442 | |
17443 | if (op->pcrel) | |
17444 | { | |
17445 | addressT addr; | |
17446 | ||
17447 | /* We won't have the section when we are called from | |
17448 | mips_relax_frag. However, we will always have been called | |
17449 | from md_estimate_size_before_relax first. If this is a | |
17450 | branch to a different section, we mark it as such. If SEC is | |
17451 | NULL, and the frag is not marked, then it must be a branch to | |
17452 | the same section. */ | |
17453 | if (sec == NULL) | |
17454 | { | |
17455 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17456 | return 1; | |
17457 | } | |
17458 | else | |
17459 | { | |
98aa84af | 17460 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17461 | if (symsec != sec) |
17462 | { | |
17463 | fragp->fr_subtype = | |
17464 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17465 | ||
17466 | /* FIXME: We should support this, and let the linker | |
17467 | catch branches and loads that are out of range. */ | |
17468 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17469 | _("unsupported PC relative reference to different section")); | |
17470 | ||
17471 | return 1; | |
17472 | } | |
98aa84af AM |
17473 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17474 | /* Assume non-extended on the first relaxation pass. | |
17475 | The address we have calculated will be bogus if this is | |
17476 | a forward branch to another frag, as the forward frag | |
17477 | will have fr_address == 0. */ | |
17478 | return 0; | |
252b5132 RH |
17479 | } |
17480 | ||
17481 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17482 | the same section. If the relax_marker of the symbol fragment |
17483 | differs from the relax_marker of this fragment, we have not | |
17484 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17485 | in STRETCH in order to get a better estimate of the address. |
17486 | This particularly matters because of the shift bits. */ | |
17487 | if (stretch != 0 | |
98aa84af | 17488 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17489 | { |
17490 | fragS *f; | |
17491 | ||
17492 | /* Adjust stretch for any alignment frag. Note that if have | |
17493 | been expanding the earlier code, the symbol may be | |
17494 | defined in what appears to be an earlier frag. FIXME: | |
17495 | This doesn't handle the fr_subtype field, which specifies | |
17496 | a maximum number of bytes to skip when doing an | |
17497 | alignment. */ | |
98aa84af | 17498 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17499 | { |
17500 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17501 | { | |
17502 | if (stretch < 0) | |
17503 | stretch = - ((- stretch) | |
17504 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17505 | else | |
17506 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17507 | if (stretch == 0) | |
17508 | break; | |
17509 | } | |
17510 | } | |
17511 | if (f != NULL) | |
17512 | val += stretch; | |
17513 | } | |
17514 | ||
17515 | addr = fragp->fr_address + fragp->fr_fix; | |
17516 | ||
17517 | /* The base address rules are complicated. The base address of | |
17518 | a branch is the following instruction. The base address of a | |
17519 | PC relative load or add is the instruction itself, but if it | |
17520 | is in a delay slot (in which case it can not be extended) use | |
17521 | the address of the instruction whose delay slot it is in. */ | |
17522 | if (type == 'p' || type == 'q') | |
17523 | { | |
17524 | addr += 2; | |
17525 | ||
17526 | /* If we are currently assuming that this frag should be | |
17527 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17528 | higher. */ |
252b5132 RH |
17529 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17530 | addr += 2; | |
17531 | ||
17532 | /* Ignore the low bit in the target, since it will be set | |
17533 | for a text label. */ | |
17534 | if ((val & 1) != 0) | |
17535 | --val; | |
17536 | } | |
17537 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17538 | addr -= 4; | |
17539 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17540 | addr -= 2; | |
17541 | ||
17542 | val -= addr & ~ ((1 << op->shift) - 1); | |
17543 | ||
17544 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17545 | if (type == 'p' || type == 'q') | |
17546 | val /= 2; | |
17547 | ||
17548 | /* If any of the shifted bits are set, we must use an extended | |
17549 | opcode. If the address depends on the size of this | |
17550 | instruction, this can lead to a loop, so we arrange to always | |
17551 | use an extended opcode. We only check this when we are in | |
17552 | the main relaxation loop, when SEC is NULL. */ | |
17553 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17554 | { | |
17555 | fragp->fr_subtype = | |
17556 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17557 | return 1; | |
17558 | } | |
17559 | ||
17560 | /* If we are about to mark a frag as extended because the value | |
17561 | is precisely maxtiny + 1, then there is a chance of an | |
17562 | infinite loop as in the following code: | |
17563 | la $4,foo | |
17564 | .skip 1020 | |
17565 | .align 2 | |
17566 | foo: | |
17567 | In this case when the la is extended, foo is 0x3fc bytes | |
17568 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17569 | the la must be extended. To avoid this loop, we mark the | |
17570 | frag as extended if it was small, and is about to become | |
17571 | extended with a value of maxtiny + 1. */ | |
17572 | if (val == ((maxtiny + 1) << op->shift) | |
17573 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17574 | && sec == NULL) | |
17575 | { | |
17576 | fragp->fr_subtype = | |
17577 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17578 | return 1; | |
17579 | } | |
17580 | } | |
17581 | else if (symsec != absolute_section && sec != NULL) | |
17582 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17583 | ||
17584 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17585 | || val < (mintiny << op->shift) | |
17586 | || val > (maxtiny << op->shift)) | |
17587 | return 1; | |
17588 | else | |
17589 | return 0; | |
17590 | } | |
17591 | ||
4a6a3df4 AO |
17592 | /* Compute the length of a branch sequence, and adjust the |
17593 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17594 | worst-case length is computed, with UPDATE being used to indicate | |
17595 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17596 | branch is to be computed. */ | |
17597 | static int | |
17a2f251 | 17598 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17599 | { |
b34976b6 | 17600 | bfd_boolean toofar; |
4a6a3df4 AO |
17601 | int length; |
17602 | ||
17603 | if (fragp | |
17604 | && S_IS_DEFINED (fragp->fr_symbol) | |
17605 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17606 | { | |
17607 | addressT addr; | |
17608 | offsetT val; | |
17609 | ||
17610 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17611 | ||
17612 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17613 | ||
17614 | val -= addr; | |
17615 | ||
17616 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17617 | } | |
17618 | else if (fragp) | |
17619 | /* If the symbol is not defined or it's in a different segment, | |
17620 | assume the user knows what's going on and emit a short | |
17621 | branch. */ | |
b34976b6 | 17622 | toofar = FALSE; |
4a6a3df4 | 17623 | else |
b34976b6 | 17624 | toofar = TRUE; |
4a6a3df4 AO |
17625 | |
17626 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17627 | fragp->fr_subtype | |
66b3e8da MR |
17628 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17629 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17630 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17631 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17632 | toofar); | |
17633 | ||
17634 | length = 4; | |
17635 | if (toofar) | |
17636 | { | |
17637 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17638 | length += 8; | |
17639 | ||
17640 | if (mips_pic != NO_PIC) | |
17641 | { | |
17642 | /* Additional space for PIC loading of target address. */ | |
17643 | length += 8; | |
17644 | if (mips_opts.isa == ISA_MIPS1) | |
17645 | /* Additional space for $at-stabilizing nop. */ | |
17646 | length += 4; | |
17647 | } | |
17648 | ||
17649 | /* If branch is conditional. */ | |
17650 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17651 | length += 8; | |
17652 | } | |
b34976b6 | 17653 | |
4a6a3df4 AO |
17654 | return length; |
17655 | } | |
17656 | ||
df58fc94 RS |
17657 | /* Compute the length of a branch sequence, and adjust the |
17658 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17659 | worst-case length is computed, with UPDATE being used to indicate | |
17660 | whether an unconditional (-1), or regular (0) branch is to be | |
17661 | computed. */ | |
17662 | ||
17663 | static int | |
17664 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17665 | { | |
17666 | bfd_boolean toofar; | |
17667 | int length; | |
17668 | ||
17669 | if (fragp | |
17670 | && S_IS_DEFINED (fragp->fr_symbol) | |
17671 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17672 | { | |
17673 | addressT addr; | |
17674 | offsetT val; | |
17675 | ||
17676 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17677 | /* Ignore the low bit in the target, since it will be set | |
17678 | for a text label. */ | |
17679 | if ((val & 1) != 0) | |
17680 | --val; | |
17681 | ||
17682 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17683 | ||
17684 | val -= addr; | |
17685 | ||
17686 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17687 | } | |
17688 | else if (fragp) | |
17689 | /* If the symbol is not defined or it's in a different segment, | |
17690 | assume the user knows what's going on and emit a short | |
17691 | branch. */ | |
17692 | toofar = FALSE; | |
17693 | else | |
17694 | toofar = TRUE; | |
17695 | ||
17696 | if (fragp && update | |
17697 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17698 | fragp->fr_subtype = (toofar | |
17699 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17700 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17701 | ||
17702 | length = 4; | |
17703 | if (toofar) | |
17704 | { | |
17705 | bfd_boolean compact_known = fragp != NULL; | |
17706 | bfd_boolean compact = FALSE; | |
17707 | bfd_boolean uncond; | |
17708 | ||
17709 | if (compact_known) | |
17710 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17711 | if (fragp) | |
17712 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17713 | else | |
17714 | uncond = update < 0; | |
17715 | ||
17716 | /* If label is out of range, we turn branch <br>: | |
17717 | ||
17718 | <br> label # 4 bytes | |
17719 | 0: | |
17720 | ||
17721 | into: | |
17722 | ||
17723 | j label # 4 bytes | |
17724 | nop # 2 bytes if compact && !PIC | |
17725 | 0: | |
17726 | */ | |
17727 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17728 | length += 2; | |
17729 | ||
17730 | /* If assembling PIC code, we further turn: | |
17731 | ||
17732 | j label # 4 bytes | |
17733 | ||
17734 | into: | |
17735 | ||
17736 | lw/ld at, %got(label)(gp) # 4 bytes | |
17737 | d/addiu at, %lo(label) # 4 bytes | |
17738 | jr/c at # 2 bytes | |
17739 | */ | |
17740 | if (mips_pic != NO_PIC) | |
17741 | length += 6; | |
17742 | ||
17743 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17744 | ||
17745 | <brneg> 0f # 4 bytes | |
17746 | nop # 2 bytes if !compact | |
17747 | */ | |
17748 | if (!uncond) | |
17749 | length += (compact_known && compact) ? 4 : 6; | |
17750 | } | |
17751 | ||
17752 | return length; | |
17753 | } | |
17754 | ||
17755 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17756 | bit accordingly. */ | |
17757 | ||
17758 | static int | |
17759 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17760 | { | |
17761 | bfd_boolean toofar; | |
17762 | ||
df58fc94 RS |
17763 | if (fragp |
17764 | && S_IS_DEFINED (fragp->fr_symbol) | |
17765 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17766 | { | |
17767 | addressT addr; | |
17768 | offsetT val; | |
17769 | int type; | |
17770 | ||
17771 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17772 | /* Ignore the low bit in the target, since it will be set | |
17773 | for a text label. */ | |
17774 | if ((val & 1) != 0) | |
17775 | --val; | |
17776 | ||
17777 | /* Assume this is a 2-byte branch. */ | |
17778 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17779 | ||
17780 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17781 | long branches. */ | |
17782 | ||
17783 | val -= addr; | |
17784 | ||
17785 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17786 | if (type == 'D') | |
17787 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17788 | else if (type == 'E') | |
17789 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17790 | else | |
17791 | abort (); | |
17792 | } | |
17793 | else | |
17794 | /* If the symbol is not defined or it's in a different segment, | |
17795 | we emit a normal 32-bit branch. */ | |
17796 | toofar = TRUE; | |
17797 | ||
17798 | if (fragp && update | |
17799 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17800 | fragp->fr_subtype | |
17801 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17802 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17803 | ||
17804 | if (toofar) | |
17805 | return 4; | |
17806 | ||
17807 | return 2; | |
17808 | } | |
17809 | ||
252b5132 RH |
17810 | /* Estimate the size of a frag before relaxing. Unless this is the |
17811 | mips16, we are not really relaxing here, and the final size is | |
17812 | encoded in the subtype information. For the mips16, we have to | |
17813 | decide whether we are using an extended opcode or not. */ | |
17814 | ||
252b5132 | 17815 | int |
17a2f251 | 17816 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17817 | { |
5919d012 | 17818 | int change; |
252b5132 | 17819 | |
4a6a3df4 AO |
17820 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17821 | { | |
17822 | ||
b34976b6 AM |
17823 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17824 | ||
4a6a3df4 AO |
17825 | return fragp->fr_var; |
17826 | } | |
17827 | ||
252b5132 | 17828 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17829 | /* We don't want to modify the EXTENDED bit here; it might get us |
17830 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17831 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17832 | |
df58fc94 RS |
17833 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17834 | { | |
17835 | int length = 4; | |
17836 | ||
17837 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17838 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17839 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17840 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17841 | fragp->fr_var = length; | |
17842 | ||
17843 | return length; | |
17844 | } | |
17845 | ||
252b5132 | 17846 | if (mips_pic == NO_PIC) |
5919d012 | 17847 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17848 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17849 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17850 | else if (mips_pic == VXWORKS_PIC) |
17851 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17852 | change = 0; | |
252b5132 RH |
17853 | else |
17854 | abort (); | |
17855 | ||
17856 | if (change) | |
17857 | { | |
4d7206a2 | 17858 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17859 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17860 | } |
4d7206a2 RS |
17861 | else |
17862 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17863 | } |
17864 | ||
17865 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17866 | should be converted into a reloc against a section. */ |
252b5132 RH |
17867 | |
17868 | int | |
17a2f251 | 17869 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17870 | { |
252b5132 RH |
17871 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17872 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17873 | return 0; | |
a161fe53 | 17874 | |
252b5132 RH |
17875 | if (fixp->fx_addsy == NULL) |
17876 | return 1; | |
a161fe53 | 17877 | |
de7e6852 RS |
17878 | /* If symbol SYM is in a mergeable section, relocations of the form |
17879 | SYM + 0 can usually be made section-relative. The mergeable data | |
17880 | is then identified by the section offset rather than by the symbol. | |
17881 | ||
17882 | However, if we're generating REL LO16 relocations, the offset is split | |
17883 | between the LO16 and parterning high part relocation. The linker will | |
17884 | need to recalculate the complete offset in order to correctly identify | |
17885 | the merge data. | |
17886 | ||
17887 | The linker has traditionally not looked for the parterning high part | |
17888 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17889 | placed anywhere. Rather than break backwards compatibility by changing | |
17890 | this, it seems better not to force the issue, and instead keep the | |
17891 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17892 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17893 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17894 | && HAVE_IN_PLACE_ADDENDS |
17895 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17896 | return 0; | |
17897 | ||
ce70d90a | 17898 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
17899 | Likewise an in-range offset of limited PC-relative relocations may |
17900 | overflow the in-place relocatable field if recalculated against the | |
17901 | start address of the symbol's containing section. */ | |
ce70d90a | 17902 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
17903 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
17904 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
17905 | return 0; |
17906 | ||
b314ec0e RS |
17907 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17908 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17909 | relocations against MIPS16 functions; in this case, the stub becomes | |
17910 | the function's canonical address. | |
17911 | ||
17912 | Floating-point stubs are stored in unique .mips16.call.* or | |
17913 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17914 | the first relocation in section S must be against F; this is how the | |
17915 | linker determines the target function. All relocations that might | |
17916 | resolve to T must also be against F. We therefore have the following | |
17917 | restrictions, which are given in an intentionally-redundant way: | |
17918 | ||
17919 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17920 | symbols. | |
17921 | ||
17922 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17923 | if that stub might be used. | |
17924 | ||
17925 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17926 | symbols. | |
17927 | ||
17928 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17929 | that stub might be used. | |
17930 | ||
17931 | There is a further restriction: | |
17932 | ||
df58fc94 RS |
17933 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17934 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17935 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17936 | encode the low bit. |
17937 | ||
df58fc94 RS |
17938 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17939 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17940 | such relocations on REL targets. | |
b314ec0e RS |
17941 | |
17942 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17943 | relocation against some symbol R, no relocation against R may be | |
17944 | reduced. (Note that this deals with (2) as well as (1) because | |
17945 | relocations against global symbols will never be reduced on ELF | |
17946 | targets.) This approach is a little simpler than trying to detect | |
17947 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17948 | that we have for MIPS16 symbols. */ | |
f3ded42a | 17949 | if (fixp->fx_subsy == NULL |
30c09090 | 17950 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17951 | || *symbol_get_tc (fixp->fx_addsy) |
17952 | || (HAVE_IN_PLACE_ADDENDS | |
17953 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17954 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 | 17955 | return 0; |
a161fe53 | 17956 | |
252b5132 RH |
17957 | return 1; |
17958 | } | |
17959 | ||
17960 | /* Translate internal representation of relocation info to BFD target | |
17961 | format. */ | |
17962 | ||
17963 | arelent ** | |
17a2f251 | 17964 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17965 | { |
17966 | static arelent *retval[4]; | |
17967 | arelent *reloc; | |
17968 | bfd_reloc_code_real_type code; | |
17969 | ||
4b0cff4e TS |
17970 | memset (retval, 0, sizeof(retval)); |
17971 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17972 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17973 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17974 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17975 | ||
bad36eac DJ |
17976 | if (fixp->fx_pcrel) |
17977 | { | |
df58fc94 RS |
17978 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17979 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17980 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
17981 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
17982 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
17983 | |
17984 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17985 | Relocations want only the symbol offset. */ | |
17986 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
bad36eac DJ |
17987 | } |
17988 | else | |
17989 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17990 | |
438c16b8 TS |
17991 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17992 | entry to be used in the relocation's section offset. */ | |
17993 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17994 | { |
17995 | reloc->address = reloc->addend; | |
17996 | reloc->addend = 0; | |
17997 | } | |
17998 | ||
252b5132 | 17999 | code = fixp->fx_r_type; |
252b5132 | 18000 | |
bad36eac | 18001 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18002 | if (reloc->howto == NULL) |
18003 | { | |
18004 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18005 | _("Can not represent %s relocation in this object file format"), | |
18006 | bfd_get_reloc_code_name (code)); | |
18007 | retval[0] = NULL; | |
18008 | } | |
18009 | ||
18010 | return retval; | |
18011 | } | |
18012 | ||
18013 | /* Relax a machine dependent frag. This returns the amount by which | |
18014 | the current size of the frag should change. */ | |
18015 | ||
18016 | int | |
17a2f251 | 18017 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18018 | { |
4a6a3df4 AO |
18019 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18020 | { | |
18021 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18022 | |
18023 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18024 | |
18025 | return fragp->fr_var - old_var; | |
18026 | } | |
18027 | ||
df58fc94 RS |
18028 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18029 | { | |
18030 | offsetT old_var = fragp->fr_var; | |
18031 | offsetT new_var = 4; | |
18032 | ||
18033 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18034 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18035 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18036 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18037 | fragp->fr_var = new_var; | |
18038 | ||
18039 | return new_var - old_var; | |
18040 | } | |
18041 | ||
252b5132 RH |
18042 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18043 | return 0; | |
18044 | ||
c4e7957c | 18045 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
18046 | { |
18047 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18048 | return 0; | |
18049 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18050 | return 2; | |
18051 | } | |
18052 | else | |
18053 | { | |
18054 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18055 | return 0; | |
18056 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18057 | return -2; | |
18058 | } | |
18059 | ||
18060 | return 0; | |
18061 | } | |
18062 | ||
18063 | /* Convert a machine dependent frag. */ | |
18064 | ||
18065 | void | |
17a2f251 | 18066 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18067 | { |
4a6a3df4 AO |
18068 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18069 | { | |
4d68580a | 18070 | char *buf; |
4a6a3df4 AO |
18071 | unsigned long insn; |
18072 | expressionS exp; | |
18073 | fixS *fixp; | |
b34976b6 | 18074 | |
4d68580a RS |
18075 | buf = fragp->fr_literal + fragp->fr_fix; |
18076 | insn = read_insn (buf); | |
b34976b6 | 18077 | |
4a6a3df4 AO |
18078 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18079 | { | |
18080 | /* We generate a fixup instead of applying it right now | |
18081 | because, if there are linker relaxations, we're going to | |
18082 | need the relocations. */ | |
18083 | exp.X_op = O_symbol; | |
18084 | exp.X_add_symbol = fragp->fr_symbol; | |
18085 | exp.X_add_number = fragp->fr_offset; | |
18086 | ||
4d68580a RS |
18087 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18088 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18089 | fixp->fx_file = fragp->fr_file; |
18090 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18091 | |
4d68580a | 18092 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18093 | } |
18094 | else | |
18095 | { | |
18096 | int i; | |
18097 | ||
18098 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18099 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18100 | |
18101 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18102 | goto uncond; | |
18103 | ||
18104 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18105 | { | |
18106 | /* Reverse the branch. */ | |
18107 | switch ((insn >> 28) & 0xf) | |
18108 | { | |
18109 | case 4: | |
3bf0dbfb MR |
18110 | /* bc[0-3][tf]l? instructions can have the condition |
18111 | reversed by tweaking a single TF bit, and their | |
18112 | opcodes all have 0x4???????. */ | |
18113 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
4a6a3df4 AO |
18114 | insn ^= 0x00010000; |
18115 | break; | |
18116 | ||
18117 | case 0: | |
18118 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18119 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18120 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18121 | insn ^= 0x00010000; |
18122 | break; | |
b34976b6 | 18123 | |
4a6a3df4 AO |
18124 | case 1: |
18125 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18126 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18127 | insn ^= 0x04000000; |
18128 | break; | |
18129 | ||
18130 | default: | |
18131 | abort (); | |
18132 | } | |
18133 | } | |
18134 | ||
18135 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18136 | { | |
18137 | /* Clear the and-link bit. */ | |
9c2799c2 | 18138 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18139 | |
54f4ddb3 TS |
18140 | /* bltzal 0x04100000 bgezal 0x04110000 |
18141 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18142 | insn &= ~0x00100000; |
18143 | } | |
18144 | ||
18145 | /* Branch over the branch (if the branch was likely) or the | |
18146 | full jump (not likely case). Compute the offset from the | |
18147 | current instruction to branch to. */ | |
18148 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18149 | i = 16; | |
18150 | else | |
18151 | { | |
18152 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18153 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18154 | /* How many bytes in instructions from here to the end? */ |
18155 | i = fragp->fr_var - i; | |
18156 | } | |
18157 | /* Convert to instruction count. */ | |
18158 | i >>= 2; | |
18159 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18160 | i--; |
4a6a3df4 AO |
18161 | insn |= i; |
18162 | /* Branch over the jump. */ | |
4d68580a | 18163 | buf = write_insn (buf, insn); |
4a6a3df4 | 18164 | |
54f4ddb3 | 18165 | /* nop */ |
4d68580a | 18166 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18167 | |
18168 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18169 | { | |
18170 | /* beql $0, $0, 2f */ | |
18171 | insn = 0x50000000; | |
18172 | /* Compute the PC offset from the current instruction to | |
18173 | the end of the variable frag. */ | |
18174 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18175 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18176 | /* How many bytes in instructions from here to the end? */ |
18177 | i = fragp->fr_var - i; | |
18178 | /* Convert to instruction count. */ | |
18179 | i >>= 2; | |
18180 | /* Don't decrement i, because we want to branch over the | |
18181 | delay slot. */ | |
4a6a3df4 | 18182 | insn |= i; |
4a6a3df4 | 18183 | |
4d68580a RS |
18184 | buf = write_insn (buf, insn); |
18185 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18186 | } |
18187 | ||
18188 | uncond: | |
18189 | if (mips_pic == NO_PIC) | |
18190 | { | |
18191 | /* j or jal. */ | |
18192 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18193 | ? 0x0c000000 : 0x08000000); | |
18194 | exp.X_op = O_symbol; | |
18195 | exp.X_add_symbol = fragp->fr_symbol; | |
18196 | exp.X_add_number = fragp->fr_offset; | |
18197 | ||
4d68580a RS |
18198 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18199 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18200 | fixp->fx_file = fragp->fr_file; |
18201 | fixp->fx_line = fragp->fr_line; | |
18202 | ||
4d68580a | 18203 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18204 | } |
18205 | else | |
18206 | { | |
66b3e8da MR |
18207 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18208 | ||
4a6a3df4 | 18209 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18210 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18211 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18212 | exp.X_op = O_symbol; |
18213 | exp.X_add_symbol = fragp->fr_symbol; | |
18214 | exp.X_add_number = fragp->fr_offset; | |
18215 | ||
18216 | if (fragp->fr_offset) | |
18217 | { | |
18218 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18219 | exp.X_add_number = 0; | |
18220 | } | |
18221 | ||
4d68580a RS |
18222 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18223 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18224 | fixp->fx_file = fragp->fr_file; |
18225 | fixp->fx_line = fragp->fr_line; | |
18226 | ||
4d68580a | 18227 | buf = write_insn (buf, insn); |
b34976b6 | 18228 | |
4a6a3df4 | 18229 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18230 | /* nop */ |
18231 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18232 | |
18233 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18234 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18235 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18236 | |
4d68580a RS |
18237 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18238 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18239 | fixp->fx_file = fragp->fr_file; |
18240 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18241 | |
4d68580a | 18242 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18243 | |
18244 | /* j(al)r $at. */ | |
18245 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18246 | insn = 0x0000f809; |
4a6a3df4 | 18247 | else |
66b3e8da MR |
18248 | insn = 0x00000008; |
18249 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18250 | |
4d68580a | 18251 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18252 | } |
18253 | } | |
18254 | ||
4a6a3df4 | 18255 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18256 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18257 | return; |
18258 | } | |
18259 | ||
df58fc94 RS |
18260 | /* Relax microMIPS branches. */ |
18261 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18262 | { | |
4d68580a | 18263 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18264 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18265 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18266 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18267 | bfd_boolean short_ds; |
df58fc94 RS |
18268 | unsigned long insn; |
18269 | expressionS exp; | |
18270 | fixS *fixp; | |
18271 | ||
18272 | exp.X_op = O_symbol; | |
18273 | exp.X_add_symbol = fragp->fr_symbol; | |
18274 | exp.X_add_number = fragp->fr_offset; | |
18275 | ||
18276 | fragp->fr_fix += fragp->fr_var; | |
18277 | ||
18278 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18279 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18280 | { | |
18281 | /* We generate a fixup instead of applying it right now, | |
18282 | because if there is linker relaxation, we're going to | |
18283 | need the relocations. */ | |
18284 | if (type == 'D') | |
4d68580a | 18285 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18286 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18287 | else if (type == 'E') | |
4d68580a | 18288 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18289 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18290 | else | |
18291 | abort (); | |
18292 | ||
18293 | fixp->fx_file = fragp->fr_file; | |
18294 | fixp->fx_line = fragp->fr_line; | |
18295 | ||
18296 | /* These relocations can have an addend that won't fit in | |
18297 | 2 octets. */ | |
18298 | fixp->fx_no_overflow = 1; | |
18299 | ||
18300 | return; | |
18301 | } | |
18302 | ||
2309ddf2 | 18303 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18304 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18305 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18306 | { | |
18307 | /* We generate a fixup instead of applying it right now, | |
18308 | because if there is linker relaxation, we're going to | |
18309 | need the relocations. */ | |
4d68580a RS |
18310 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18311 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18312 | fixp->fx_file = fragp->fr_file; |
18313 | fixp->fx_line = fragp->fr_line; | |
18314 | ||
18315 | if (type == 0) | |
18316 | return; | |
18317 | } | |
18318 | ||
18319 | /* Relax 16-bit branches to 32-bit branches. */ | |
18320 | if (type != 0) | |
18321 | { | |
4d68580a | 18322 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18323 | |
18324 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18325 | insn = 0x94000000; /* beq */ | |
18326 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18327 | { | |
18328 | unsigned long regno; | |
18329 | ||
18330 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18331 | regno = micromips_to_32_reg_d_map [regno]; | |
18332 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18333 | insn |= regno << MICROMIPSOP_SH_RS; | |
18334 | } | |
18335 | else | |
18336 | abort (); | |
18337 | ||
18338 | /* Nothing else to do, just write it out. */ | |
18339 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18340 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18341 | { | |
4d68580a RS |
18342 | buf = write_compressed_insn (buf, insn, 4); |
18343 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18344 | return; |
18345 | } | |
18346 | } | |
18347 | else | |
4d68580a | 18348 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18349 | |
18350 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18351 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18352 | _("Relaxed out-of-range branch into a jump")); | |
18353 | ||
2309ddf2 MR |
18354 | /* Set the short-delay-slot bit. */ |
18355 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18356 | |
18357 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18358 | { | |
18359 | symbolS *l; | |
18360 | ||
18361 | /* Reverse the branch. */ | |
18362 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18363 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18364 | insn ^= 0x20000000; | |
18365 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18366 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18367 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18368 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18369 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18370 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18371 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18372 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18373 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18374 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18375 | insn ^= 0x00400000; | |
18376 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18377 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18378 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18379 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18380 | insn ^= 0x00200000; | |
18381 | else | |
18382 | abort (); | |
18383 | ||
18384 | if (al) | |
18385 | { | |
18386 | /* Clear the and-link and short-delay-slot bits. */ | |
18387 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18388 | ||
18389 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18390 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18391 | insn &= ~0x02200000; | |
18392 | } | |
18393 | ||
18394 | /* Make a label at the end for use with the branch. */ | |
18395 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18396 | micromips_label_inc (); | |
f3ded42a | 18397 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18398 | |
18399 | /* Refer to it. */ | |
4d68580a RS |
18400 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18401 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18402 | fixp->fx_file = fragp->fr_file; |
18403 | fixp->fx_line = fragp->fr_line; | |
18404 | ||
18405 | /* Branch over the jump. */ | |
4d68580a | 18406 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18407 | if (!compact) |
4d68580a RS |
18408 | /* nop */ |
18409 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18410 | } |
18411 | ||
18412 | if (mips_pic == NO_PIC) | |
18413 | { | |
2309ddf2 MR |
18414 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18415 | ||
df58fc94 RS |
18416 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18417 | insn = al ? jal : 0xd4000000; | |
18418 | ||
4d68580a RS |
18419 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18420 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18421 | fixp->fx_file = fragp->fr_file; |
18422 | fixp->fx_line = fragp->fr_line; | |
18423 | ||
4d68580a | 18424 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18425 | if (compact) |
4d68580a RS |
18426 | /* nop */ |
18427 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18428 | } |
18429 | else | |
18430 | { | |
18431 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18432 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18433 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18434 | |
18435 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18436 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18437 | insn |= at << MICROMIPSOP_SH_RT; | |
18438 | ||
18439 | if (exp.X_add_number) | |
18440 | { | |
18441 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18442 | exp.X_add_number = 0; | |
18443 | } | |
18444 | ||
4d68580a RS |
18445 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18446 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18447 | fixp->fx_file = fragp->fr_file; |
18448 | fixp->fx_line = fragp->fr_line; | |
18449 | ||
4d68580a | 18450 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18451 | |
18452 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18453 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18454 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18455 | ||
4d68580a RS |
18456 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18457 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18458 | fixp->fx_file = fragp->fr_file; |
18459 | fixp->fx_line = fragp->fr_line; | |
18460 | ||
4d68580a | 18461 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18462 | |
18463 | /* jr/jrc/jalr/jalrs $at */ | |
18464 | insn = al ? jalr : jr; | |
18465 | insn |= at << MICROMIPSOP_SH_MJ; | |
18466 | ||
4d68580a | 18467 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18468 | } |
18469 | ||
4d68580a | 18470 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18471 | return; |
18472 | } | |
18473 | ||
252b5132 RH |
18474 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18475 | { | |
18476 | int type; | |
3994f87e | 18477 | const struct mips16_immed_operand *op; |
252b5132 | 18478 | offsetT val; |
5c04167a RS |
18479 | char *buf; |
18480 | unsigned int user_length, length; | |
252b5132 | 18481 | unsigned long insn; |
5c04167a | 18482 | bfd_boolean ext; |
252b5132 RH |
18483 | |
18484 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18485 | op = mips16_immed_operands; | |
18486 | while (op->type != type) | |
18487 | ++op; | |
18488 | ||
5c04167a | 18489 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18490 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18491 | if (op->pcrel) |
18492 | { | |
18493 | addressT addr; | |
18494 | ||
18495 | addr = fragp->fr_address + fragp->fr_fix; | |
18496 | ||
18497 | /* The rules for the base address of a PC relative reloc are | |
18498 | complicated; see mips16_extended_frag. */ | |
18499 | if (type == 'p' || type == 'q') | |
18500 | { | |
18501 | addr += 2; | |
18502 | if (ext) | |
18503 | addr += 2; | |
18504 | /* Ignore the low bit in the target, since it will be | |
18505 | set for a text label. */ | |
18506 | if ((val & 1) != 0) | |
18507 | --val; | |
18508 | } | |
18509 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18510 | addr -= 4; | |
18511 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18512 | addr -= 2; | |
18513 | ||
18514 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18515 | val -= addr; | |
18516 | ||
18517 | /* Make sure the section winds up with the alignment we have | |
18518 | assumed. */ | |
18519 | if (op->shift > 0) | |
18520 | record_alignment (asec, op->shift); | |
18521 | } | |
18522 | ||
18523 | if (ext | |
18524 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18525 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18526 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18527 | _("extended instruction in delay slot")); | |
18528 | ||
5c04167a | 18529 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18530 | |
4d68580a | 18531 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18532 | if (ext) |
18533 | insn |= MIPS16_EXTEND; | |
252b5132 | 18534 | |
5c04167a RS |
18535 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18536 | user_length = 4; | |
18537 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18538 | user_length = 2; | |
18539 | else | |
18540 | user_length = 0; | |
18541 | ||
43c0598f | 18542 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18543 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18544 | |
5c04167a RS |
18545 | length = (ext ? 4 : 2); |
18546 | gas_assert (mips16_opcode_length (insn) == length); | |
18547 | write_compressed_insn (buf, insn, length); | |
18548 | fragp->fr_fix += length; | |
252b5132 RH |
18549 | } |
18550 | else | |
18551 | { | |
df58fc94 RS |
18552 | relax_substateT subtype = fragp->fr_subtype; |
18553 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18554 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18555 | int first, second; |
18556 | fixS *fixp; | |
252b5132 | 18557 | |
df58fc94 RS |
18558 | first = RELAX_FIRST (subtype); |
18559 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18560 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18561 | |
df58fc94 RS |
18562 | /* If the delay slot chosen does not match the size of the instruction, |
18563 | then emit a warning. */ | |
18564 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18565 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18566 | { | |
18567 | relax_substateT s; | |
18568 | const char *msg; | |
18569 | ||
18570 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18571 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18572 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18573 | msg = macro_warning (s); | |
18574 | if (msg != NULL) | |
db9b2be4 | 18575 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18576 | subtype &= ~s; |
18577 | } | |
18578 | ||
584892a6 | 18579 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18580 | if (use_second == second_longer) |
584892a6 | 18581 | { |
df58fc94 RS |
18582 | relax_substateT s; |
18583 | const char *msg; | |
18584 | ||
18585 | s = (subtype | |
18586 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18587 | msg = macro_warning (s); | |
18588 | if (msg != NULL) | |
db9b2be4 | 18589 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18590 | subtype &= ~s; |
584892a6 RS |
18591 | } |
18592 | ||
4d7206a2 RS |
18593 | /* Go through all the fixups for the first sequence. Disable them |
18594 | (by marking them as done) if we're going to use the second | |
18595 | sequence instead. */ | |
18596 | while (fixp | |
18597 | && fixp->fx_frag == fragp | |
18598 | && fixp->fx_where < fragp->fr_fix - second) | |
18599 | { | |
df58fc94 | 18600 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18601 | fixp->fx_done = 1; |
18602 | fixp = fixp->fx_next; | |
18603 | } | |
252b5132 | 18604 | |
4d7206a2 RS |
18605 | /* Go through the fixups for the second sequence. Disable them if |
18606 | we're going to use the first sequence, otherwise adjust their | |
18607 | addresses to account for the relaxation. */ | |
18608 | while (fixp && fixp->fx_frag == fragp) | |
18609 | { | |
df58fc94 | 18610 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18611 | fixp->fx_where -= first; |
18612 | else | |
18613 | fixp->fx_done = 1; | |
18614 | fixp = fixp->fx_next; | |
18615 | } | |
18616 | ||
18617 | /* Now modify the frag contents. */ | |
df58fc94 | 18618 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18619 | { |
18620 | char *start; | |
18621 | ||
18622 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18623 | memmove (start, start + first, second); | |
18624 | fragp->fr_fix -= first; | |
18625 | } | |
18626 | else | |
18627 | fragp->fr_fix -= second; | |
252b5132 RH |
18628 | } |
18629 | } | |
18630 | ||
252b5132 RH |
18631 | /* This function is called after the relocs have been generated. |
18632 | We've been storing mips16 text labels as odd. Here we convert them | |
18633 | back to even for the convenience of the debugger. */ | |
18634 | ||
18635 | void | |
17a2f251 | 18636 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18637 | { |
18638 | asymbol **syms; | |
18639 | unsigned int count, i; | |
18640 | ||
252b5132 RH |
18641 | syms = bfd_get_outsymbols (stdoutput); |
18642 | count = bfd_get_symcount (stdoutput); | |
18643 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18644 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18645 | && ((*syms)->value & 1) != 0) | |
18646 | { | |
18647 | (*syms)->value &= ~1; | |
18648 | /* If the symbol has an odd size, it was probably computed | |
18649 | incorrectly, so adjust that as well. */ | |
18650 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18651 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18652 | } | |
252b5132 RH |
18653 | } |
18654 | ||
a1facbec MR |
18655 | /* This function is called whenever a label is defined, including fake |
18656 | labels instantiated off the dot special symbol. It is used when | |
18657 | handling branch delays; if a branch has a label, we assume we cannot | |
18658 | move it. This also bumps the value of the symbol by 1 in compressed | |
18659 | code. */ | |
252b5132 | 18660 | |
e1b47bd5 | 18661 | static void |
a1facbec | 18662 | mips_record_label (symbolS *sym) |
252b5132 | 18663 | { |
a8dbcb85 | 18664 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18665 | struct insn_label_list *l; |
18666 | ||
18667 | if (free_insn_labels == NULL) | |
18668 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18669 | else | |
18670 | { | |
18671 | l = free_insn_labels; | |
18672 | free_insn_labels = l->next; | |
18673 | } | |
18674 | ||
18675 | l->label = sym; | |
a8dbcb85 TS |
18676 | l->next = si->label_list; |
18677 | si->label_list = l; | |
a1facbec | 18678 | } |
07a53e5c | 18679 | |
a1facbec MR |
18680 | /* This function is called as tc_frob_label() whenever a label is defined |
18681 | and adds a DWARF-2 record we only want for true labels. */ | |
18682 | ||
18683 | void | |
18684 | mips_define_label (symbolS *sym) | |
18685 | { | |
18686 | mips_record_label (sym); | |
07a53e5c | 18687 | dwarf2_emit_label (sym); |
252b5132 | 18688 | } |
e1b47bd5 RS |
18689 | |
18690 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18691 | is defined. */ | |
18692 | ||
18693 | void | |
18694 | mips_add_dot_label (symbolS *sym) | |
18695 | { | |
18696 | mips_record_label (sym); | |
18697 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18698 | mips_compressed_mark_label (sym); | |
18699 | } | |
252b5132 | 18700 | \f |
252b5132 RH |
18701 | /* Some special processing for a MIPS ELF file. */ |
18702 | ||
18703 | void | |
17a2f251 | 18704 | mips_elf_final_processing (void) |
252b5132 RH |
18705 | { |
18706 | /* Write out the register information. */ | |
316f5878 | 18707 | if (mips_abi != N64_ABI) |
252b5132 RH |
18708 | { |
18709 | Elf32_RegInfo s; | |
18710 | ||
18711 | s.ri_gprmask = mips_gprmask; | |
18712 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18713 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18714 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18715 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18716 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18717 | ||
18718 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18719 | ((Elf32_External_RegInfo *) | |
18720 | mips_regmask_frag)); | |
18721 | } | |
18722 | else | |
18723 | { | |
18724 | Elf64_Internal_RegInfo s; | |
18725 | ||
18726 | s.ri_gprmask = mips_gprmask; | |
18727 | s.ri_pad = 0; | |
18728 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18729 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18730 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18731 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18732 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18733 | ||
18734 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18735 | ((Elf64_External_RegInfo *) | |
18736 | mips_regmask_frag)); | |
18737 | } | |
18738 | ||
18739 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18740 | sort of BFD interface for this. */ | |
18741 | if (mips_any_noreorder) | |
18742 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18743 | if (mips_pic != NO_PIC) | |
143d77c5 | 18744 | { |
8b828383 | 18745 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18746 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18747 | } | |
18748 | if (mips_abicalls) | |
18749 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18750 | |
b015e599 AP |
18751 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18752 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18753 | if (file_ase_mips16) |
18754 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18755 | if (file_ase_micromips) |
18756 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
846ef2d0 | 18757 | if (file_ase & ASE_MDMX) |
deec1734 | 18758 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 18759 | |
bdaaa2e1 | 18760 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18761 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18762 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18763 | else if (mips_abi == O64_ABI) |
252b5132 | 18764 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18765 | else if (mips_abi == EABI_ABI) |
252b5132 | 18766 | { |
316f5878 | 18767 | if (!file_mips_gp32) |
252b5132 RH |
18768 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18769 | else | |
18770 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18771 | } | |
316f5878 | 18772 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18773 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18774 | ||
c9914766 | 18775 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18776 | |
18777 | if (mips_32bitmode) | |
18778 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 18779 | |
ba92f887 MR |
18780 | if (mips_flag_nan2008) |
18781 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; | |
18782 | ||
ad3fea08 TS |
18783 | #if 0 /* XXX FIXME */ |
18784 | /* 32 bit code with 64 bit FP registers. */ | |
18785 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18786 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18787 | #endif | |
252b5132 | 18788 | } |
252b5132 | 18789 | \f |
beae10d5 | 18790 | typedef struct proc { |
9b2f1d35 EC |
18791 | symbolS *func_sym; |
18792 | symbolS *func_end_sym; | |
beae10d5 KH |
18793 | unsigned long reg_mask; |
18794 | unsigned long reg_offset; | |
18795 | unsigned long fpreg_mask; | |
18796 | unsigned long fpreg_offset; | |
18797 | unsigned long frame_offset; | |
18798 | unsigned long frame_reg; | |
18799 | unsigned long pc_reg; | |
18800 | } procS; | |
252b5132 RH |
18801 | |
18802 | static procS cur_proc; | |
18803 | static procS *cur_proc_ptr; | |
18804 | static int numprocs; | |
18805 | ||
df58fc94 RS |
18806 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18807 | as "2", and a normal nop as "0". */ | |
18808 | ||
18809 | #define NOP_OPCODE_MIPS 0 | |
18810 | #define NOP_OPCODE_MIPS16 1 | |
18811 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18812 | |
18813 | char | |
18814 | mips_nop_opcode (void) | |
18815 | { | |
df58fc94 RS |
18816 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18817 | return NOP_OPCODE_MICROMIPS; | |
18818 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18819 | return NOP_OPCODE_MIPS16; | |
18820 | else | |
18821 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18822 | } |
18823 | ||
df58fc94 RS |
18824 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18825 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18826 | |
0a9ef439 | 18827 | void |
17a2f251 | 18828 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18829 | { |
df58fc94 | 18830 | char nop_opcode; |
742a56fe | 18831 | char *p; |
c67a084a NC |
18832 | int bytes, size, excess; |
18833 | valueT opcode; | |
742a56fe | 18834 | |
0a9ef439 RH |
18835 | if (fragp->fr_type != rs_align_code) |
18836 | return; | |
18837 | ||
742a56fe | 18838 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18839 | nop_opcode = *p; |
18840 | switch (nop_opcode) | |
a19d8eb0 | 18841 | { |
df58fc94 RS |
18842 | case NOP_OPCODE_MICROMIPS: |
18843 | opcode = micromips_nop32_insn.insn_opcode; | |
18844 | size = 4; | |
18845 | break; | |
18846 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18847 | opcode = mips16_nop_insn.insn_opcode; |
18848 | size = 2; | |
df58fc94 RS |
18849 | break; |
18850 | case NOP_OPCODE_MIPS: | |
18851 | default: | |
c67a084a NC |
18852 | opcode = nop_insn.insn_opcode; |
18853 | size = 4; | |
df58fc94 | 18854 | break; |
c67a084a | 18855 | } |
a19d8eb0 | 18856 | |
c67a084a NC |
18857 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18858 | excess = bytes % size; | |
df58fc94 RS |
18859 | |
18860 | /* Handle the leading part if we're not inserting a whole number of | |
18861 | instructions, and make it the end of the fixed part of the frag. | |
18862 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18863 | and use zeroes otherwise. */ | |
18864 | gas_assert (excess < 4); | |
18865 | fragp->fr_fix += excess; | |
18866 | switch (excess) | |
c67a084a | 18867 | { |
df58fc94 RS |
18868 | case 3: |
18869 | *p++ = '\0'; | |
18870 | /* Fall through. */ | |
18871 | case 2: | |
833794fc | 18872 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 18873 | { |
4d68580a | 18874 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18875 | break; |
18876 | } | |
18877 | *p++ = '\0'; | |
18878 | /* Fall through. */ | |
18879 | case 1: | |
18880 | *p++ = '\0'; | |
18881 | /* Fall through. */ | |
18882 | case 0: | |
18883 | break; | |
a19d8eb0 | 18884 | } |
c67a084a NC |
18885 | |
18886 | md_number_to_chars (p, opcode, size); | |
18887 | fragp->fr_var = size; | |
a19d8eb0 CP |
18888 | } |
18889 | ||
252b5132 | 18890 | static void |
17a2f251 | 18891 | md_obj_begin (void) |
252b5132 RH |
18892 | { |
18893 | } | |
18894 | ||
18895 | static void | |
17a2f251 | 18896 | md_obj_end (void) |
252b5132 | 18897 | { |
54f4ddb3 | 18898 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18899 | if (cur_proc_ptr) |
9a41af64 | 18900 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18901 | } |
18902 | ||
18903 | static long | |
17a2f251 | 18904 | get_number (void) |
252b5132 RH |
18905 | { |
18906 | int negative = 0; | |
18907 | long val = 0; | |
18908 | ||
18909 | if (*input_line_pointer == '-') | |
18910 | { | |
18911 | ++input_line_pointer; | |
18912 | negative = 1; | |
18913 | } | |
3882b010 | 18914 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18915 | as_bad (_("expected simple number")); |
252b5132 RH |
18916 | if (input_line_pointer[0] == '0') |
18917 | { | |
18918 | if (input_line_pointer[1] == 'x') | |
18919 | { | |
18920 | input_line_pointer += 2; | |
3882b010 | 18921 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18922 | { |
18923 | val <<= 4; | |
18924 | val |= hex_value (*input_line_pointer++); | |
18925 | } | |
18926 | return negative ? -val : val; | |
18927 | } | |
18928 | else | |
18929 | { | |
18930 | ++input_line_pointer; | |
3882b010 | 18931 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18932 | { |
18933 | val <<= 3; | |
18934 | val |= *input_line_pointer++ - '0'; | |
18935 | } | |
18936 | return negative ? -val : val; | |
18937 | } | |
18938 | } | |
3882b010 | 18939 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18940 | { |
18941 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18942 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18943 | as_warn (_("invalid number")); |
252b5132 RH |
18944 | return -1; |
18945 | } | |
3882b010 | 18946 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18947 | { |
18948 | val *= 10; | |
18949 | val += *input_line_pointer++ - '0'; | |
18950 | } | |
18951 | return negative ? -val : val; | |
18952 | } | |
18953 | ||
18954 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18955 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18956 | case .file implies DWARF-2. */ | |
18957 | ||
18958 | static void | |
17a2f251 | 18959 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18960 | { |
ecb4347a DJ |
18961 | static int first_file_directive = 0; |
18962 | ||
c5dd6aab DJ |
18963 | if (ECOFF_DEBUGGING) |
18964 | { | |
18965 | get_number (); | |
18966 | s_app_file (0); | |
18967 | } | |
18968 | else | |
ecb4347a DJ |
18969 | { |
18970 | char *filename; | |
18971 | ||
18972 | filename = dwarf2_directive_file (0); | |
18973 | ||
18974 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18975 | directive even for stabs output. Make sure that this | |
18976 | ".file" is handled. Note that you need a version of GCC | |
18977 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18978 | if (filename != NULL && ! first_file_directive) | |
18979 | { | |
18980 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18981 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18982 | } |
18983 | first_file_directive = 1; | |
18984 | } | |
c5dd6aab DJ |
18985 | } |
18986 | ||
18987 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18988 | |
18989 | static void | |
17a2f251 | 18990 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18991 | { |
c5dd6aab DJ |
18992 | if (!ECOFF_DEBUGGING) |
18993 | dwarf2_directive_loc (0); | |
252b5132 RH |
18994 | } |
18995 | ||
252b5132 RH |
18996 | /* The .end directive. */ |
18997 | ||
18998 | static void | |
17a2f251 | 18999 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19000 | { |
19001 | symbolS *p; | |
252b5132 | 19002 | |
7a621144 DJ |
19003 | /* Following functions need their own .frame and .cprestore directives. */ |
19004 | mips_frame_reg_valid = 0; | |
19005 | mips_cprestore_valid = 0; | |
19006 | ||
252b5132 RH |
19007 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19008 | { | |
19009 | p = get_symbol (); | |
19010 | demand_empty_rest_of_line (); | |
19011 | } | |
19012 | else | |
19013 | p = NULL; | |
19014 | ||
14949570 | 19015 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19016 | as_warn (_(".end not in text section")); |
19017 | ||
19018 | if (!cur_proc_ptr) | |
19019 | { | |
19020 | as_warn (_(".end directive without a preceding .ent directive.")); | |
19021 | demand_empty_rest_of_line (); | |
19022 | return; | |
19023 | } | |
19024 | ||
19025 | if (p != NULL) | |
19026 | { | |
9c2799c2 | 19027 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19028 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 19029 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
19030 | |
19031 | if (debug_type == DEBUG_STABS) | |
19032 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19033 | S_GET_NAME (p)); | |
252b5132 RH |
19034 | } |
19035 | else | |
19036 | as_warn (_(".end directive missing or unknown symbol")); | |
19037 | ||
9b2f1d35 EC |
19038 | /* Create an expression to calculate the size of the function. */ |
19039 | if (p && cur_proc_ptr) | |
19040 | { | |
19041 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19042 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19043 | ||
19044 | obj->size = exp; | |
19045 | exp->X_op = O_subtract; | |
19046 | exp->X_add_symbol = symbol_temp_new_now (); | |
19047 | exp->X_op_symbol = p; | |
19048 | exp->X_add_number = 0; | |
19049 | ||
19050 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19051 | } | |
19052 | ||
ecb4347a | 19053 | /* Generate a .pdr section. */ |
f3ded42a | 19054 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19055 | { |
19056 | segT saved_seg = now_seg; | |
19057 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19058 | expressionS exp; |
19059 | char *fragp; | |
252b5132 | 19060 | |
252b5132 | 19061 | #ifdef md_flush_pending_output |
ecb4347a | 19062 | md_flush_pending_output (); |
252b5132 RH |
19063 | #endif |
19064 | ||
9c2799c2 | 19065 | gas_assert (pdr_seg); |
ecb4347a | 19066 | subseg_set (pdr_seg, 0); |
252b5132 | 19067 | |
ecb4347a DJ |
19068 | /* Write the symbol. */ |
19069 | exp.X_op = O_symbol; | |
19070 | exp.X_add_symbol = p; | |
19071 | exp.X_add_number = 0; | |
19072 | emit_expr (&exp, 4); | |
252b5132 | 19073 | |
ecb4347a | 19074 | fragp = frag_more (7 * 4); |
252b5132 | 19075 | |
17a2f251 TS |
19076 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19077 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19078 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19079 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19080 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19081 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19082 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19083 | |
ecb4347a DJ |
19084 | subseg_set (saved_seg, saved_subseg); |
19085 | } | |
252b5132 RH |
19086 | |
19087 | cur_proc_ptr = NULL; | |
19088 | } | |
19089 | ||
19090 | /* The .aent and .ent directives. */ | |
19091 | ||
19092 | static void | |
17a2f251 | 19093 | s_mips_ent (int aent) |
252b5132 | 19094 | { |
252b5132 | 19095 | symbolS *symbolP; |
252b5132 RH |
19096 | |
19097 | symbolP = get_symbol (); | |
19098 | if (*input_line_pointer == ',') | |
f9419b05 | 19099 | ++input_line_pointer; |
252b5132 | 19100 | SKIP_WHITESPACE (); |
3882b010 | 19101 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19102 | || *input_line_pointer == '-') |
874e8986 | 19103 | get_number (); |
252b5132 | 19104 | |
14949570 | 19105 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19106 | as_warn (_(".ent or .aent not in text section.")); |
19107 | ||
19108 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19109 | as_warn (_("missing .end")); |
252b5132 RH |
19110 | |
19111 | if (!aent) | |
19112 | { | |
7a621144 DJ |
19113 | /* This function needs its own .frame and .cprestore directives. */ |
19114 | mips_frame_reg_valid = 0; | |
19115 | mips_cprestore_valid = 0; | |
19116 | ||
252b5132 RH |
19117 | cur_proc_ptr = &cur_proc; |
19118 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19119 | ||
9b2f1d35 | 19120 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19121 | |
f9419b05 | 19122 | ++numprocs; |
ecb4347a DJ |
19123 | |
19124 | if (debug_type == DEBUG_STABS) | |
19125 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19126 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19127 | } |
19128 | ||
7c0fc524 MR |
19129 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19130 | ||
252b5132 RH |
19131 | demand_empty_rest_of_line (); |
19132 | } | |
19133 | ||
19134 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19135 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19136 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19137 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19138 | symbol table (in the mdebug section). */ |
19139 | ||
19140 | static void | |
17a2f251 | 19141 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19142 | { |
f3ded42a RS |
19143 | if (ECOFF_DEBUGGING) |
19144 | s_ignore (ignore); | |
19145 | else | |
ecb4347a DJ |
19146 | { |
19147 | long val; | |
252b5132 | 19148 | |
ecb4347a DJ |
19149 | if (cur_proc_ptr == (procS *) NULL) |
19150 | { | |
19151 | as_warn (_(".frame outside of .ent")); | |
19152 | demand_empty_rest_of_line (); | |
19153 | return; | |
19154 | } | |
252b5132 | 19155 | |
ecb4347a DJ |
19156 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19157 | ||
19158 | SKIP_WHITESPACE (); | |
19159 | if (*input_line_pointer++ != ',' | |
19160 | || get_absolute_expression_and_terminator (&val) != ',') | |
19161 | { | |
19162 | as_warn (_("Bad .frame directive")); | |
19163 | --input_line_pointer; | |
19164 | demand_empty_rest_of_line (); | |
19165 | return; | |
19166 | } | |
252b5132 | 19167 | |
ecb4347a DJ |
19168 | cur_proc_ptr->frame_offset = val; |
19169 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19170 | |
252b5132 | 19171 | demand_empty_rest_of_line (); |
252b5132 | 19172 | } |
252b5132 RH |
19173 | } |
19174 | ||
bdaaa2e1 KH |
19175 | /* The .fmask and .mask directives. If the mdebug section is present |
19176 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19177 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19178 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19179 | make reference to the ecoff symbol table (in the mdebug section). */ |
19180 | ||
19181 | static void | |
17a2f251 | 19182 | s_mips_mask (int reg_type) |
252b5132 | 19183 | { |
f3ded42a RS |
19184 | if (ECOFF_DEBUGGING) |
19185 | s_ignore (reg_type); | |
19186 | else | |
252b5132 | 19187 | { |
ecb4347a | 19188 | long mask, off; |
252b5132 | 19189 | |
ecb4347a DJ |
19190 | if (cur_proc_ptr == (procS *) NULL) |
19191 | { | |
19192 | as_warn (_(".mask/.fmask outside of .ent")); | |
19193 | demand_empty_rest_of_line (); | |
19194 | return; | |
19195 | } | |
252b5132 | 19196 | |
ecb4347a DJ |
19197 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19198 | { | |
19199 | as_warn (_("Bad .mask/.fmask directive")); | |
19200 | --input_line_pointer; | |
19201 | demand_empty_rest_of_line (); | |
19202 | return; | |
19203 | } | |
252b5132 | 19204 | |
ecb4347a DJ |
19205 | off = get_absolute_expression (); |
19206 | ||
19207 | if (reg_type == 'F') | |
19208 | { | |
19209 | cur_proc_ptr->fpreg_mask = mask; | |
19210 | cur_proc_ptr->fpreg_offset = off; | |
19211 | } | |
19212 | else | |
19213 | { | |
19214 | cur_proc_ptr->reg_mask = mask; | |
19215 | cur_proc_ptr->reg_offset = off; | |
19216 | } | |
19217 | ||
19218 | demand_empty_rest_of_line (); | |
252b5132 | 19219 | } |
252b5132 RH |
19220 | } |
19221 | ||
316f5878 RS |
19222 | /* A table describing all the processors gas knows about. Names are |
19223 | matched in the order listed. | |
e7af610e | 19224 | |
316f5878 RS |
19225 | To ease comparison, please keep this table in the same order as |
19226 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19227 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19228 | { | |
316f5878 | 19229 | /* Entries for generic ISAs */ |
d16afab6 RS |
19230 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19231 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19232 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19233 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19234 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19235 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19236 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19237 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19238 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19239 | |
19240 | /* MIPS I */ | |
d16afab6 RS |
19241 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19242 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19243 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19244 | |
19245 | /* MIPS II */ | |
d16afab6 | 19246 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19247 | |
19248 | /* MIPS III */ | |
d16afab6 RS |
19249 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19250 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19251 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19252 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19253 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19254 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19255 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19256 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19257 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19258 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19259 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19260 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19261 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19262 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
19263 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
19264 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19265 | |
19266 | /* MIPS IV */ | |
d16afab6 RS |
19267 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19268 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19269 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19270 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19271 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19272 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19273 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19274 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19275 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19276 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19277 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19278 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19279 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19280 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19281 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19282 | |
19283 | /* MIPS 32 */ | |
d16afab6 RS |
19284 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19285 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19286 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19287 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19288 | |
19289 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19290 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19291 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19292 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19293 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19294 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19295 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19296 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19297 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19298 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19299 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19300 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19301 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19302 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19303 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19304 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19305 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19306 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19307 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19308 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19309 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19310 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19311 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19312 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19313 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19314 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19315 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19316 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19317 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19318 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19319 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19320 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19321 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19322 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19323 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19324 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19325 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19326 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19327 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19328 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19329 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19330 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19331 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19332 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19333 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19334 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19335 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19336 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19337 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19338 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19339 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19340 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19341 | |
316f5878 | 19342 | /* MIPS 64 */ |
d16afab6 RS |
19343 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19344 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19345 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19346 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19347 | |
c7a23324 | 19348 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19349 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19350 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19351 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
d051516a | 19352 | |
d16afab6 | 19353 | { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A }, |
e7af610e | 19354 | |
ed163775 MR |
19355 | /* MIPS 64 Release 2 */ |
19356 | ||
967344c6 | 19357 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19358 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19359 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19360 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
967344c6 | 19361 | |
52b6b6b9 | 19362 | /* RMI Xlr */ |
d16afab6 | 19363 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19364 | |
55a36193 MK |
19365 | /* Broadcom XLP. |
19366 | XLP is mostly like XLR, with the prominent exception that it is | |
19367 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19368 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19369 | |
316f5878 | 19370 | /* End marker */ |
d16afab6 | 19371 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19372 | }; |
e7af610e | 19373 | |
84ea6cf2 | 19374 | |
316f5878 RS |
19375 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19376 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19377 | |
316f5878 | 19378 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19379 | |
b34976b6 | 19380 | static bfd_boolean |
17a2f251 | 19381 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19382 | { |
19383 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19384 | given++, canonical++; | |
19385 | ||
19386 | return ((*given == 0 && *canonical == 0) | |
19387 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19388 | } | |
19389 | ||
19390 | ||
19391 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19392 | CPU name. We've traditionally allowed a lot of variation here. | |
19393 | ||
19394 | Note: this function is shared between GCC and GAS. */ | |
19395 | ||
b34976b6 | 19396 | static bfd_boolean |
17a2f251 | 19397 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19398 | { |
19399 | /* First see if the name matches exactly, or with a final "000" | |
19400 | turned into "k". */ | |
19401 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19402 | return TRUE; |
316f5878 RS |
19403 | |
19404 | /* If not, try comparing based on numerical designation alone. | |
19405 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19406 | if (TOLOWER (*given) == 'r') | |
19407 | given++; | |
19408 | if (!ISDIGIT (*given)) | |
b34976b6 | 19409 | return FALSE; |
316f5878 RS |
19410 | |
19411 | /* Skip over some well-known prefixes in the canonical name, | |
19412 | hoping to find a number there too. */ | |
19413 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19414 | canonical += 2; | |
19415 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19416 | canonical += 2; | |
19417 | else if (TOLOWER (canonical[0]) == 'r') | |
19418 | canonical += 1; | |
19419 | ||
19420 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19421 | } | |
19422 | ||
19423 | ||
19424 | /* Parse an option that takes the name of a processor as its argument. | |
19425 | OPTION is the name of the option and CPU_STRING is the argument. | |
19426 | Return the corresponding processor enumeration if the CPU_STRING is | |
19427 | recognized, otherwise report an error and return null. | |
19428 | ||
19429 | A similar function exists in GCC. */ | |
e7af610e NC |
19430 | |
19431 | static const struct mips_cpu_info * | |
17a2f251 | 19432 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19433 | { |
316f5878 | 19434 | const struct mips_cpu_info *p; |
e7af610e | 19435 | |
316f5878 RS |
19436 | /* 'from-abi' selects the most compatible architecture for the given |
19437 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19438 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19439 | version. Look first at the -mgp options, if given, otherwise base | |
19440 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19441 | |
316f5878 RS |
19442 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19443 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19444 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19445 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19446 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19447 | { | |
19448 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19449 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19450 | ||
19451 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19452 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19453 | ||
19454 | if (file_mips_gp32 >= 0) | |
19455 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19456 | ||
19457 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19458 | ? ISA_MIPS3 | |
19459 | : ISA_MIPS1); | |
19460 | } | |
19461 | ||
19462 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19463 | if (strcasecmp (cpu_string, "default") == 0) | |
19464 | return 0; | |
19465 | ||
19466 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19467 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19468 | return p; | |
19469 | ||
20203fb9 | 19470 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19471 | return 0; |
e7af610e NC |
19472 | } |
19473 | ||
316f5878 RS |
19474 | /* Return the canonical processor information for ISA (a member of the |
19475 | ISA_MIPS* enumeration). */ | |
19476 | ||
e7af610e | 19477 | static const struct mips_cpu_info * |
17a2f251 | 19478 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19479 | { |
19480 | int i; | |
19481 | ||
19482 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19483 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19484 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19485 | return (&mips_cpu_info_table[i]); |
19486 | ||
e972090a | 19487 | return NULL; |
e7af610e | 19488 | } |
fef14a42 TS |
19489 | |
19490 | static const struct mips_cpu_info * | |
17a2f251 | 19491 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19492 | { |
19493 | int i; | |
19494 | ||
19495 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19496 | if (arch == mips_cpu_info_table[i].cpu) | |
19497 | return (&mips_cpu_info_table[i]); | |
19498 | ||
19499 | return NULL; | |
19500 | } | |
316f5878 RS |
19501 | \f |
19502 | static void | |
17a2f251 | 19503 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19504 | { |
19505 | if (*first_p) | |
19506 | { | |
19507 | fprintf (stream, "%24s", ""); | |
19508 | *col_p = 24; | |
19509 | } | |
19510 | else | |
19511 | { | |
19512 | fprintf (stream, ", "); | |
19513 | *col_p += 2; | |
19514 | } | |
e7af610e | 19515 | |
316f5878 RS |
19516 | if (*col_p + strlen (string) > 72) |
19517 | { | |
19518 | fprintf (stream, "\n%24s", ""); | |
19519 | *col_p = 24; | |
19520 | } | |
19521 | ||
19522 | fprintf (stream, "%s", string); | |
19523 | *col_p += strlen (string); | |
19524 | ||
19525 | *first_p = 0; | |
19526 | } | |
19527 | ||
19528 | void | |
17a2f251 | 19529 | md_show_usage (FILE *stream) |
e7af610e | 19530 | { |
316f5878 RS |
19531 | int column, first; |
19532 | size_t i; | |
19533 | ||
19534 | fprintf (stream, _("\ | |
19535 | MIPS options:\n\ | |
316f5878 RS |
19536 | -EB generate big endian output\n\ |
19537 | -EL generate little endian output\n\ | |
19538 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19539 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19540 | implicitly with the gp register [default 8]\n")); | |
19541 | fprintf (stream, _("\ | |
19542 | -mips1 generate MIPS ISA I instructions\n\ | |
19543 | -mips2 generate MIPS ISA II instructions\n\ | |
19544 | -mips3 generate MIPS ISA III instructions\n\ | |
19545 | -mips4 generate MIPS ISA IV instructions\n\ | |
19546 | -mips5 generate MIPS ISA V instructions\n\ | |
19547 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19548 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19549 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19550 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19551 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19552 | ||
19553 | first = 1; | |
e7af610e NC |
19554 | |
19555 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19556 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19557 | show (stream, "from-abi", &column, &first); | |
19558 | fputc ('\n', stream); | |
e7af610e | 19559 | |
316f5878 RS |
19560 | fprintf (stream, _("\ |
19561 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19562 | -no-mCPU don't generate code specific to CPU.\n\ | |
19563 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19564 | ||
19565 | first = 1; | |
19566 | ||
19567 | show (stream, "3900", &column, &first); | |
19568 | show (stream, "4010", &column, &first); | |
19569 | show (stream, "4100", &column, &first); | |
19570 | show (stream, "4650", &column, &first); | |
19571 | fputc ('\n', stream); | |
19572 | ||
19573 | fprintf (stream, _("\ | |
19574 | -mips16 generate mips16 instructions\n\ | |
19575 | -no-mips16 do not generate mips16 instructions\n")); | |
19576 | fprintf (stream, _("\ | |
df58fc94 RS |
19577 | -mmicromips generate microMIPS instructions\n\ |
19578 | -mno-micromips do not generate microMIPS instructions\n")); | |
19579 | fprintf (stream, _("\ | |
e16bfa71 TS |
19580 | -msmartmips generate smartmips instructions\n\ |
19581 | -mno-smartmips do not generate smartmips instructions\n")); | |
19582 | fprintf (stream, _("\ | |
74cd071d CF |
19583 | -mdsp generate DSP instructions\n\ |
19584 | -mno-dsp do not generate DSP instructions\n")); | |
19585 | fprintf (stream, _("\ | |
8b082fb1 TS |
19586 | -mdspr2 generate DSP R2 instructions\n\ |
19587 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19588 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19589 | -mmt generate MT instructions\n\ |
19590 | -mno-mt do not generate MT instructions\n")); | |
19591 | fprintf (stream, _("\ | |
dec0624d MR |
19592 | -mmcu generate MCU instructions\n\ |
19593 | -mno-mcu do not generate MCU instructions\n")); | |
19594 | fprintf (stream, _("\ | |
b015e599 AP |
19595 | -mvirt generate Virtualization instructions\n\ |
19596 | -mno-virt do not generate Virtualization instructions\n")); | |
19597 | fprintf (stream, _("\ | |
833794fc MR |
19598 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
19599 | -mno-insn32 generate all microMIPS instructions\n")); | |
19600 | fprintf (stream, _("\ | |
c67a084a NC |
19601 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19602 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19603 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19604 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19605 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19606 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19607 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19608 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19609 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19610 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19611 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19612 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19613 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19614 | fprintf (stream, _("\ |
19615 | -mhard-float allow floating-point instructions\n\ | |
19616 | -msoft-float do not allow floating-point instructions\n\ | |
19617 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19618 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 19619 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 MR |
19620 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
19621 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); | |
19622 | ||
19623 | first = 1; | |
19624 | ||
19625 | show (stream, "legacy", &column, &first); | |
19626 | show (stream, "2008", &column, &first); | |
19627 | ||
19628 | fputc ('\n', stream); | |
19629 | ||
316f5878 RS |
19630 | fprintf (stream, _("\ |
19631 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19632 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19633 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19634 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19635 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19636 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19637 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19638 | position dependent (non shared) code\n\ |
316f5878 RS |
19639 | -mabi=ABI create ABI conformant object file for:\n")); |
19640 | ||
19641 | first = 1; | |
19642 | ||
19643 | show (stream, "32", &column, &first); | |
19644 | show (stream, "o64", &column, &first); | |
19645 | show (stream, "n32", &column, &first); | |
19646 | show (stream, "64", &column, &first); | |
19647 | show (stream, "eabi", &column, &first); | |
19648 | ||
19649 | fputc ('\n', stream); | |
19650 | ||
19651 | fprintf (stream, _("\ | |
19652 | -32 create o32 ABI object file (default)\n\ | |
19653 | -n32 create n32 ABI object file\n\ | |
19654 | -64 create 64 ABI object file\n")); | |
e7af610e | 19655 | } |
14e777e0 | 19656 | |
1575952e | 19657 | #ifdef TE_IRIX |
14e777e0 | 19658 | enum dwarf2_format |
413a266c | 19659 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19660 | { |
369943fe | 19661 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19662 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19663 | else |
19664 | return dwarf2_format_32bit; | |
19665 | } | |
1575952e | 19666 | #endif |
73369e65 EC |
19667 | |
19668 | int | |
19669 | mips_dwarf2_addr_size (void) | |
19670 | { | |
6b6b3450 | 19671 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19672 | return 8; |
73369e65 EC |
19673 | else |
19674 | return 4; | |
19675 | } | |
5862107c EC |
19676 | |
19677 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19678 | void | |
19679 | mips_cfi_frame_initial_instructions (void) | |
19680 | { | |
19681 | cfi_add_CFA_def_cfa_register (SP); | |
19682 | } | |
19683 | ||
707bfff6 TS |
19684 | int |
19685 | tc_mips_regname_to_dw2regnum (char *regname) | |
19686 | { | |
19687 | unsigned int regnum = -1; | |
19688 | unsigned int reg; | |
19689 | ||
19690 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19691 | regnum = reg; | |
19692 | ||
19693 | return regnum; | |
19694 | } |